arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * Hyper-V requires all of these, so mark them as supported even though
 137  * they are just treated the same as all-context.
 138  */
 139 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 140         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 141         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 143         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 144
 145 /*
 146  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 147  * ple_gap:    upper bound on the amount of time between two successive
 148  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 149  *             According to test, this time is usually smaller than 128 cycles.
 150  * ple_window: upper bound on the amount of time a guest is allowed to execute
 151  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 152  *             less than 2^12 cycles
 153  * Time is measured based on a counter that runs at the same rate as the TSC,
 154  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 155  */
 156 #define KVM_VMX_DEFAULT_PLE_GAP           128
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 161                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 162
 163 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, int, S_IRUGO);
 165
 166 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, int, S_IRUGO);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, int, S_IRUGO);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, int, S_IRUGO);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 180 module_param(ple_window_max, int, S_IRUGO);
 181
 182 extern const ulong vmx_return;
 183
 184 #define NR_AUTOLOAD_MSRS 8
 185 #define VMCS02_POOL_SIZE 1
 186
 187 struct vmcs {
 188         u32 revision_id;
 189         u32 abort;
 190         char data[0];
 191 };
 192
 193 /*
 194  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 195  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 196  * loaded on this CPU (so we can clear them if the CPU goes down).
 197  */
 198 struct loaded_vmcs {
 199         struct vmcs *vmcs;
 200         struct vmcs *shadow_vmcs;
 201         int cpu;
 202         int launched;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 ept_pointer;
 247         u64 eoi_exit_bitmap0;
 248         u64 eoi_exit_bitmap1;
 249         u64 eoi_exit_bitmap2;
 250         u64 eoi_exit_bitmap3;
 251         u64 xss_exit_bitmap;
 252         u64 guest_physical_address;
 253         u64 vmcs_link_pointer;
 254         u64 guest_ia32_debugctl;
 255         u64 guest_ia32_pat;
 256         u64 guest_ia32_efer;
 257         u64 guest_ia32_perf_global_ctrl;
 258         u64 guest_pdptr0;
 259         u64 guest_pdptr1;
 260         u64 guest_pdptr2;
 261         u64 guest_pdptr3;
 262         u64 guest_bndcfgs;
 263         u64 host_ia32_pat;
 264         u64 host_ia32_efer;
 265         u64 host_ia32_perf_global_ctrl;
 266         u64 padding64[8]; /* room for future expansion */
 267         /*
 268          * To allow migration of L1 (complete with its L2 guests) between
 269          * machines of different natural widths (32 or 64 bit), we cannot have
 270          * unsigned long fields with no explict size. We use u64 (aliased
 271          * natural_width) instead. Luckily, x86 is little-endian.
 272          */
 273         natural_width cr0_guest_host_mask;
 274         natural_width cr4_guest_host_mask;
 275         natural_width cr0_read_shadow;
 276         natural_width cr4_read_shadow;
 277         natural_width cr3_target_value0;
 278         natural_width cr3_target_value1;
 279         natural_width cr3_target_value2;
 280         natural_width cr3_target_value3;
 281         natural_width exit_qualification;
 282         natural_width guest_linear_address;
 283         natural_width guest_cr0;
 284         natural_width guest_cr3;
 285         natural_width guest_cr4;
 286         natural_width guest_es_base;
 287         natural_width guest_cs_base;
 288         natural_width guest_ss_base;
 289         natural_width guest_ds_base;
 290         natural_width guest_fs_base;
 291         natural_width guest_gs_base;
 292         natural_width guest_ldtr_base;
 293         natural_width guest_tr_base;
 294         natural_width guest_gdtr_base;
 295         natural_width guest_idtr_base;
 296         natural_width guest_dr7;
 297         natural_width guest_rsp;
 298         natural_width guest_rip;
 299         natural_width guest_rflags;
 300         natural_width guest_pending_dbg_exceptions;
 301         natural_width guest_sysenter_esp;
 302         natural_width guest_sysenter_eip;
 303         natural_width host_cr0;
 304         natural_width host_cr3;
 305         natural_width host_cr4;
 306         natural_width host_fs_base;
 307         natural_width host_gs_base;
 308         natural_width host_tr_base;
 309         natural_width host_gdtr_base;
 310         natural_width host_idtr_base;
 311         natural_width host_ia32_sysenter_esp;
 312         natural_width host_ia32_sysenter_eip;
 313         natural_width host_rsp;
 314         natural_width host_rip;
 315         natural_width paddingl[8]; /* room for future expansion */
 316         u32 pin_based_vm_exec_control;
 317         u32 cpu_based_vm_exec_control;
 318         u32 exception_bitmap;
 319         u32 page_fault_error_code_mask;
 320         u32 page_fault_error_code_match;
 321         u32 cr3_target_count;
 322         u32 vm_exit_controls;
 323         u32 vm_exit_msr_store_count;
 324         u32 vm_exit_msr_load_count;
 325         u32 vm_entry_controls;
 326         u32 vm_entry_msr_load_count;
 327         u32 vm_entry_intr_info_field;
 328         u32 vm_entry_exception_error_code;
 329         u32 vm_entry_instruction_len;
 330         u32 tpr_threshold;
 331         u32 secondary_vm_exec_control;
 332         u32 vm_instruction_error;
 333         u32 vm_exit_reason;
 334         u32 vm_exit_intr_info;
 335         u32 vm_exit_intr_error_code;
 336         u32 idt_vectoring_info_field;
 337         u32 idt_vectoring_error_code;
 338         u32 vm_exit_instruction_len;
 339         u32 vmx_instruction_info;
 340         u32 guest_es_limit;
 341         u32 guest_cs_limit;
 342         u32 guest_ss_limit;
 343         u32 guest_ds_limit;
 344         u32 guest_fs_limit;
 345         u32 guest_gs_limit;
 346         u32 guest_ldtr_limit;
 347         u32 guest_tr_limit;
 348         u32 guest_gdtr_limit;
 349         u32 guest_idtr_limit;
 350         u32 guest_es_ar_bytes;
 351         u32 guest_cs_ar_bytes;
 352         u32 guest_ss_ar_bytes;
 353         u32 guest_ds_ar_bytes;
 354         u32 guest_fs_ar_bytes;
 355         u32 guest_gs_ar_bytes;
 356         u32 guest_ldtr_ar_bytes;
 357         u32 guest_tr_ar_bytes;
 358         u32 guest_interruptibility_info;
 359         u32 guest_activity_state;
 360         u32 guest_sysenter_cs;
 361         u32 host_ia32_sysenter_cs;
 362         u32 vmx_preemption_timer_value;
 363         u32 padding32[7]; /* room for future expansion */
 364         u16 virtual_processor_id;
 365         u16 posted_intr_nv;
 366         u16 guest_es_selector;
 367         u16 guest_cs_selector;
 368         u16 guest_ss_selector;
 369         u16 guest_ds_selector;
 370         u16 guest_fs_selector;
 371         u16 guest_gs_selector;
 372         u16 guest_ldtr_selector;
 373         u16 guest_tr_selector;
 374         u16 guest_intr_status;
 375         u16 host_es_selector;
 376         u16 host_cs_selector;
 377         u16 host_ss_selector;
 378         u16 host_ds_selector;
 379         u16 host_fs_selector;
 380         u16 host_gs_selector;
 381         u16 host_tr_selector;
 382 };
 383
 384 /*
 385  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 386  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 387  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 388  */
 389 #define VMCS12_REVISION 0x11e57ed0
 390
 391 /*
 392  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 393  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 394  * current implementation, 4K are reserved to avoid future complications.
 395  */
 396 #define VMCS12_SIZE 0x1000
 397
 398 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 399 struct vmcs02_list {
 400         struct list_head list;
 401         gpa_t vmptr;
 402         struct loaded_vmcs vmcs02;
 403 };
 404
 405 /*
 406  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 407  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 408  */
 409 struct nested_vmx {
 410         /* Has the level1 guest done vmxon? */
 411         bool vmxon;
 412         gpa_t vmxon_ptr;
 413
 414         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 415         gpa_t current_vmptr;
 416         /* The host-usable pointer to the above */
 417         struct page *current_vmcs12_page;
 418         struct vmcs12 *current_vmcs12;
 419         /*
 420          * Cache of the guest's VMCS, existing outside of guest memory.
 421          * Loaded from guest memory during VMPTRLD. Flushed to guest
 422          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 423          */
 424         struct vmcs12 *cached_vmcs12;
 425         /*
 426          * Indicates if the shadow vmcs must be updated with the
 427          * data hold by vmcs12
 428          */
 429         bool sync_shadow_vmcs;
 430
 431         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 432         struct list_head vmcs02_pool;
 433         int vmcs02_num;
 434         bool change_vmcs01_virtual_x2apic_mode;
 435         /* L2 must run next, and mustn't decide to exit to L1. */
 436         bool nested_run_pending;
 437         /*
 438          * Guest pages referred to in vmcs02 with host-physical pointers, so
 439          * we must keep them pinned while L2 runs.
 440          */
 441         struct page *apic_access_page;
 442         struct page *virtual_apic_page;
 443         struct page *pi_desc_page;
 444         struct pi_desc *pi_desc;
 445         bool pi_pending;
 446         u16 posted_intr_nv;
 447
 448         unsigned long *msr_bitmap;
 449
 450         struct hrtimer preemption_timer;
 451         bool preemption_timer_expired;
 452
 453         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 454         u64 vmcs01_debugctl;
 455
 456         u16 vpid02;
 457         u16 last_vpid;
 458
 459         /*
 460          * We only store the "true" versions of the VMX capability MSRs. We
 461          * generate the "non-true" versions by setting the must-be-1 bits
 462          * according to the SDM.
 463          */
 464         u32 nested_vmx_procbased_ctls_low;
 465         u32 nested_vmx_procbased_ctls_high;
 466         u32 nested_vmx_secondary_ctls_low;
 467         u32 nested_vmx_secondary_ctls_high;
 468         u32 nested_vmx_pinbased_ctls_low;
 469         u32 nested_vmx_pinbased_ctls_high;
 470         u32 nested_vmx_exit_ctls_low;
 471         u32 nested_vmx_exit_ctls_high;
 472         u32 nested_vmx_entry_ctls_low;
 473         u32 nested_vmx_entry_ctls_high;
 474         u32 nested_vmx_misc_low;
 475         u32 nested_vmx_misc_high;
 476         u32 nested_vmx_ept_caps;
 477         u32 nested_vmx_vpid_caps;
 478         u64 nested_vmx_basic;
 479         u64 nested_vmx_cr0_fixed0;
 480         u64 nested_vmx_cr0_fixed1;
 481         u64 nested_vmx_cr4_fixed0;
 482         u64 nested_vmx_cr4_fixed1;
 483         u64 nested_vmx_vmcs_enum;
 484 };
 485
 486 #define POSTED_INTR_ON  0
 487 #define POSTED_INTR_SN  1
 488
 489 /* Posted-Interrupt Descriptor */
 490 struct pi_desc {
 491         u32 pir[8];     /* Posted interrupt requested */
 492         union {
 493                 struct {
 494                                 /* bit 256 - Outstanding Notification */
 495                         u16     on      : 1,
 496                                 /* bit 257 - Suppress Notification */
 497                                 sn      : 1,
 498                                 /* bit 271:258 - Reserved */
 499                                 rsvd_1  : 14;
 500                                 /* bit 279:272 - Notification Vector */
 501                         u8      nv;
 502                                 /* bit 287:280 - Reserved */
 503                         u8      rsvd_2;
 504                                 /* bit 319:288 - Notification Destination */
 505                         u32     ndst;
 506                 };
 507                 u64 control;
 508         };
 509         u32 rsvd[6];
 510 } __aligned(64);
 511
 512 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 513 {
 514         return test_and_set_bit(POSTED_INTR_ON,
 515                         (unsigned long *)&pi_desc->control);
 516 }
 517
 518 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 519 {
 520         return test_and_clear_bit(POSTED_INTR_ON,
 521                         (unsigned long *)&pi_desc->control);
 522 }
 523
 524 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 525 {
 526         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 527 }
 528
 529 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 530 {
 531         return clear_bit(POSTED_INTR_SN,
 532                         (unsigned long *)&pi_desc->control);
 533 }
 534
 535 static inline void pi_set_sn(struct pi_desc *pi_desc)
 536 {
 537         return set_bit(POSTED_INTR_SN,
 538                         (unsigned long *)&pi_desc->control);
 539 }
 540
 541 static inline void pi_clear_on(struct pi_desc *pi_desc)
 542 {
 543         clear_bit(POSTED_INTR_ON,
 544                   (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static inline int pi_test_on(struct pi_desc *pi_desc)
 548 {
 549         return test_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static inline int pi_test_sn(struct pi_desc *pi_desc)
 554 {
 555         return test_bit(POSTED_INTR_SN,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 struct vcpu_vmx {
 560         struct kvm_vcpu       vcpu;
 561         unsigned long         host_rsp;
 562         u8                    fail;
 563         bool                  nmi_known_unmasked;
 564         u32                   exit_intr_info;
 565         u32                   idt_vectoring_info;
 566         ulong                 rflags;
 567         struct shared_msr_entry *guest_msrs;
 568         int                   nmsrs;
 569         int                   save_nmsrs;
 570         unsigned long         host_idt_base;
 571 #ifdef CONFIG_X86_64
 572         u64                   msr_host_kernel_gs_base;
 573         u64                   msr_guest_kernel_gs_base;
 574 #endif
 575         u32 vm_entry_controls_shadow;
 576         u32 vm_exit_controls_shadow;
 577         /*
 578          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 579          * non-nested (L1) guest, it always points to vmcs01. For a nested
 580          * guest (L2), it points to a different VMCS.
 581          */
 582         struct loaded_vmcs    vmcs01;
 583         struct loaded_vmcs   *loaded_vmcs;
 584         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 585         struct msr_autoload {
 586                 unsigned nr;
 587                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 588                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 589         } msr_autoload;
 590         struct {
 591                 int           loaded;
 592                 u16           fs_sel, gs_sel, ldt_sel;
 593 #ifdef CONFIG_X86_64
 594                 u16           ds_sel, es_sel;
 595 #endif
 596                 int           gs_ldt_reload_needed;
 597                 int           fs_reload_needed;
 598                 u64           msr_host_bndcfgs;
 599                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 600         } host_state;
 601         struct {
 602                 int vm86_active;
 603                 ulong save_rflags;
 604                 struct kvm_segment segs[8];
 605         } rmode;
 606         struct {
 607                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 608                 struct kvm_save_segment {
 609                         u16 selector;
 610                         unsigned long base;
 611                         u32 limit;
 612                         u32 ar;
 613                 } seg[8];
 614         } segment_cache;
 615         int vpid;
 616         bool emulation_required;
 617
 618         /* Support for vnmi-less CPUs */
 619         int soft_vnmi_blocked;
 620         ktime_t entry_time;
 621         s64 vnmi_blocked_time;
 622         u32 exit_reason;
 623
 624         /* Posted interrupt descriptor */
 625         struct pi_desc pi_desc;
 626
 627         /* Support for a guest hypervisor (nested VMX) */
 628         struct nested_vmx nested;
 629
 630         /* Dynamic PLE window. */
 631         int ple_window;
 632         bool ple_window_dirty;
 633
 634         /* Support for PML */
 635 #define PML_ENTITY_NUM          512
 636         struct page *pml_pg;
 637
 638         /* apic deadline value in host tsc */
 639         u64 hv_deadline_tsc;
 640
 641         u64 current_tsc_ratio;
 642
 643         bool guest_pkru_valid;
 644         u32 guest_pkru;
 645         u32 host_pkru;
 646
 647         /*
 648          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 649          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 650          * in msr_ia32_feature_control_valid_bits.
 651          */
 652         u64 msr_ia32_feature_control;
 653         u64 msr_ia32_feature_control_valid_bits;
 654 };
 655
 656 enum segment_cache_field {
 657         SEG_FIELD_SEL = 0,
 658         SEG_FIELD_BASE = 1,
 659         SEG_FIELD_LIMIT = 2,
 660         SEG_FIELD_AR = 3,
 661
 662         SEG_FIELD_NR = 4
 663 };
 664
 665 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 666 {
 667         return container_of(vcpu, struct vcpu_vmx, vcpu);
 668 }
 669
 670 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 671 {
 672         return &(to_vmx(vcpu)->pi_desc);
 673 }
 674
 675 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 676 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 677 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 678                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 679
 680
 681 static unsigned long shadow_read_only_fields[] = {
 682         /*
 683          * We do NOT shadow fields that are modified when L0
 684          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 685          * VMXON...) executed by L1.
 686          * For example, VM_INSTRUCTION_ERROR is read
 687          * by L1 if a vmx instruction fails (part of the error path).
 688          * Note the code assumes this logic. If for some reason
 689          * we start shadowing these fields then we need to
 690          * force a shadow sync when L0 emulates vmx instructions
 691          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 692          * by nested_vmx_failValid)
 693          */
 694         VM_EXIT_REASON,
 695         VM_EXIT_INTR_INFO,
 696         VM_EXIT_INSTRUCTION_LEN,
 697         IDT_VECTORING_INFO_FIELD,
 698         IDT_VECTORING_ERROR_CODE,
 699         VM_EXIT_INTR_ERROR_CODE,
 700         EXIT_QUALIFICATION,
 701         GUEST_LINEAR_ADDRESS,
 702         GUEST_PHYSICAL_ADDRESS
 703 };
 704 static int max_shadow_read_only_fields =
 705         ARRAY_SIZE(shadow_read_only_fields);
 706
 707 static unsigned long shadow_read_write_fields[] = {
 708         TPR_THRESHOLD,
 709         GUEST_RIP,
 710         GUEST_RSP,
 711         GUEST_CR0,
 712         GUEST_CR3,
 713         GUEST_CR4,
 714         GUEST_INTERRUPTIBILITY_INFO,
 715         GUEST_RFLAGS,
 716         GUEST_CS_SELECTOR,
 717         GUEST_CS_AR_BYTES,
 718         GUEST_CS_LIMIT,
 719         GUEST_CS_BASE,
 720         GUEST_ES_BASE,
 721         GUEST_BNDCFGS,
 722         CR0_GUEST_HOST_MASK,
 723         CR0_READ_SHADOW,
 724         CR4_READ_SHADOW,
 725         TSC_OFFSET,
 726         EXCEPTION_BITMAP,
 727         CPU_BASED_VM_EXEC_CONTROL,
 728         VM_ENTRY_EXCEPTION_ERROR_CODE,
 729         VM_ENTRY_INTR_INFO_FIELD,
 730         VM_ENTRY_INSTRUCTION_LEN,
 731         VM_ENTRY_EXCEPTION_ERROR_CODE,
 732         HOST_FS_BASE,
 733         HOST_GS_BASE,
 734         HOST_FS_SELECTOR,
 735         HOST_GS_SELECTOR
 736 };
 737 static int max_shadow_read_write_fields =
 738         ARRAY_SIZE(shadow_read_write_fields);
 739
 740 static const unsigned short vmcs_field_to_offset_table[] = {
 741         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 742         FIELD(POSTED_INTR_NV, posted_intr_nv),
 743         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 744         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 745         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 746         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 747         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 748         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 749         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 750         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 751         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(EPT_POINTER, ept_pointer),
 770         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 771         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 772         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 773         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 774         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 775         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 776         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 777         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 778         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 779         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 780         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 781         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 782         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 783         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 784         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 785         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 786         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 787         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 788         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 789         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 790         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 791         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 792         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 793         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 794         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 795         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 796         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 797         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 798         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 799         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 800         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 801         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 802         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 803         FIELD(TPR_THRESHOLD, tpr_threshold),
 804         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 805         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 806         FIELD(VM_EXIT_REASON, vm_exit_reason),
 807         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 808         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 809         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 810         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 811         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 812         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 813         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 814         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 815         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 816         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 817         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 818         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 819         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 820         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 821         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 822         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 823         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 824         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 825         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 826         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 827         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 828         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 829         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 830         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 831         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 832         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 833         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 834         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 835         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 836         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 837         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 838         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 839         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 840         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 841         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 842         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 843         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 844         FIELD(EXIT_QUALIFICATION, exit_qualification),
 845         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 846         FIELD(GUEST_CR0, guest_cr0),
 847         FIELD(GUEST_CR3, guest_cr3),
 848         FIELD(GUEST_CR4, guest_cr4),
 849         FIELD(GUEST_ES_BASE, guest_es_base),
 850         FIELD(GUEST_CS_BASE, guest_cs_base),
 851         FIELD(GUEST_SS_BASE, guest_ss_base),
 852         FIELD(GUEST_DS_BASE, guest_ds_base),
 853         FIELD(GUEST_FS_BASE, guest_fs_base),
 854         FIELD(GUEST_GS_BASE, guest_gs_base),
 855         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 856         FIELD(GUEST_TR_BASE, guest_tr_base),
 857         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 858         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 859         FIELD(GUEST_DR7, guest_dr7),
 860         FIELD(GUEST_RSP, guest_rsp),
 861         FIELD(GUEST_RIP, guest_rip),
 862         FIELD(GUEST_RFLAGS, guest_rflags),
 863         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 864         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 865         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 866         FIELD(HOST_CR0, host_cr0),
 867         FIELD(HOST_CR3, host_cr3),
 868         FIELD(HOST_CR4, host_cr4),
 869         FIELD(HOST_FS_BASE, host_fs_base),
 870         FIELD(HOST_GS_BASE, host_gs_base),
 871         FIELD(HOST_TR_BASE, host_tr_base),
 872         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 873         FIELD(HOST_IDTR_BASE, host_idtr_base),
 874         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 875         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 876         FIELD(HOST_RSP, host_rsp),
 877         FIELD(HOST_RIP, host_rip),
 878 };
 879
 880 static inline short vmcs_field_to_offset(unsigned long field)
 881 {
 882         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 883
 884         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 885             vmcs_field_to_offset_table[field] == 0)
 886                 return -ENOENT;
 887
 888         return vmcs_field_to_offset_table[field];
 889 }
 890
 891 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 892 {
 893         return to_vmx(vcpu)->nested.cached_vmcs12;
 894 }
 895
 896 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 897 {
 898         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 899         if (is_error_page(page))
 900                 return NULL;
 901
 902         return page;
 903 }
 904
 905 static void nested_release_page(struct page *page)
 906 {
 907         kvm_release_page_dirty(page);
 908 }
 909
 910 static void nested_release_page_clean(struct page *page)
 911 {
 912         kvm_release_page_clean(page);
 913 }
 914
 915 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 916 static u64 construct_eptp(unsigned long root_hpa);
 917 static void kvm_cpu_vmxon(u64 addr);
 918 static void kvm_cpu_vmxoff(void);
 919 static bool vmx_xsaves_supported(void);
 920 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 921 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 922                             struct kvm_segment *var, int seg);
 923 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 924                             struct kvm_segment *var, int seg);
 925 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 926 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 927 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 928 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 929 static int alloc_identity_pagetable(struct kvm *kvm);
 930
 931 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 932 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 933 /*
 934  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 935  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 936  */
 937 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 938 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 939
 940 /*
 941  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 942  * can find which vCPU should be waken up.
 943  */
 944 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 945 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 946
 947 enum {
 948         VMX_IO_BITMAP_A,
 949         VMX_IO_BITMAP_B,
 950         VMX_MSR_BITMAP_LEGACY,
 951         VMX_MSR_BITMAP_LONGMODE,
 952         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 953         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 954         VMX_MSR_BITMAP_LEGACY_X2APIC,
 955         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 956         VMX_VMREAD_BITMAP,
 957         VMX_VMWRITE_BITMAP,
 958         VMX_BITMAP_NR
 959 };
 960
 961 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 962
 963 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 964 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 965 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 966 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 967 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 968 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 969 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 970 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 971 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 972 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 973
 974 static bool cpu_has_load_ia32_efer;
 975 static bool cpu_has_load_perf_global_ctrl;
 976
 977 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 978 static DEFINE_SPINLOCK(vmx_vpid_lock);
 979
 980 static struct vmcs_config {
 981         int size;
 982         int order;
 983         u32 basic_cap;
 984         u32 revision_id;
 985         u32 pin_based_exec_ctrl;
 986         u32 cpu_based_exec_ctrl;
 987         u32 cpu_based_2nd_exec_ctrl;
 988         u32 vmexit_ctrl;
 989         u32 vmentry_ctrl;
 990 } vmcs_config;
 991
 992 static struct vmx_capability {
 993         u32 ept;
 994         u32 vpid;
 995 } vmx_capability;
 996
 997 #define VMX_SEGMENT_FIELD(seg)                                  \
 998         [VCPU_SREG_##seg] = {                                   \
 999                 .selector = GUEST_##seg##_SELECTOR,             \
1000                 .base = GUEST_##seg##_BASE,                     \
1001                 .limit = GUEST_##seg##_LIMIT,                   \
1002                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1003         }
1004
1005 static const struct kvm_vmx_segment_field {
1006         unsigned selector;
1007         unsigned base;
1008         unsigned limit;
1009         unsigned ar_bytes;
1010 } kvm_vmx_segment_fields[] = {
1011         VMX_SEGMENT_FIELD(CS),
1012         VMX_SEGMENT_FIELD(DS),
1013         VMX_SEGMENT_FIELD(ES),
1014         VMX_SEGMENT_FIELD(FS),
1015         VMX_SEGMENT_FIELD(GS),
1016         VMX_SEGMENT_FIELD(SS),
1017         VMX_SEGMENT_FIELD(TR),
1018         VMX_SEGMENT_FIELD(LDTR),
1019 };
1020
1021 static u64 host_efer;
1022
1023 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1024
1025 /*
1026  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1027  * away by decrementing the array size.
1028  */
1029 static const u32 vmx_msr_index[] = {
1030 #ifdef CONFIG_X86_64
1031         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1032 #endif
1033         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1034 };
1035
1036 static inline bool is_exception_n(u32 intr_info, u8 vector)
1037 {
1038         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1039                              INTR_INFO_VALID_MASK)) ==
1040                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1041 }
1042
1043 static inline bool is_debug(u32 intr_info)
1044 {
1045         return is_exception_n(intr_info, DB_VECTOR);
1046 }
1047
1048 static inline bool is_breakpoint(u32 intr_info)
1049 {
1050         return is_exception_n(intr_info, BP_VECTOR);
1051 }
1052
1053 static inline bool is_page_fault(u32 intr_info)
1054 {
1055         return is_exception_n(intr_info, PF_VECTOR);
1056 }
1057
1058 static inline bool is_no_device(u32 intr_info)
1059 {
1060         return is_exception_n(intr_info, NM_VECTOR);
1061 }
1062
1063 static inline bool is_invalid_opcode(u32 intr_info)
1064 {
1065         return is_exception_n(intr_info, UD_VECTOR);
1066 }
1067
1068 static inline bool is_external_interrupt(u32 intr_info)
1069 {
1070         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1071                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1072 }
1073
1074 static inline bool is_machine_check(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1077                              INTR_INFO_VALID_MASK)) ==
1078                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1079 }
1080
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1082 {
1083         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1084 }
1085
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1087 {
1088         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1089 }
1090
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1092 {
1093         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1094 }
1095
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1097 {
1098         return vmcs_config.cpu_based_exec_ctrl &
1099                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1100 }
1101
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1103 {
1104         return vmcs_config.cpu_based_2nd_exec_ctrl &
1105                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1106 }
1107
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1109 {
1110         return vmcs_config.cpu_based_2nd_exec_ctrl &
1111                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1112 }
1113
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1115 {
1116         return vmcs_config.cpu_based_2nd_exec_ctrl &
1117                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1118 }
1119
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1121 {
1122         return vmcs_config.cpu_based_2nd_exec_ctrl &
1123                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1124 }
1125
1126 /*
1127  * Comment's format: document - errata name - stepping - processor name.
1128  * Refer from
1129  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1130  */
1131 static u32 vmx_preemption_cpu_tfms[] = {
1132 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1133 0x000206E6,
1134 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 0x00020652,
1138 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1139 0x00020655,
1140 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1142 /*
1143  * 320767.pdf - AAP86  - B1 -
1144  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1145  */
1146 0x000106E5,
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1148 0x000106A0,
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1150 0x000106A1,
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1152 0x000106A4,
1153  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1156 0x000106A5,
1157 };
1158
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1160 {
1161         u32 eax = cpuid_eax(0x00000001), i;
1162
1163         /* Clear the reserved bits */
1164         eax &= ~(0x3U << 14 | 0xfU << 28);
1165         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1166                 if (eax == vmx_preemption_cpu_tfms[i])
1167                         return true;
1168
1169         return false;
1170 }
1171
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1173 {
1174         return vmcs_config.pin_based_exec_ctrl &
1175                 PIN_BASED_VMX_PREEMPTION_TIMER;
1176 }
1177
1178 static inline bool cpu_has_vmx_posted_intr(void)
1179 {
1180         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1181                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1182 }
1183
1184 static inline bool cpu_has_vmx_apicv(void)
1185 {
1186         return cpu_has_vmx_apic_register_virt() &&
1187                 cpu_has_vmx_virtual_intr_delivery() &&
1188                 cpu_has_vmx_posted_intr();
1189 }
1190
1191 static inline bool cpu_has_vmx_flexpriority(void)
1192 {
1193         return cpu_has_vmx_tpr_shadow() &&
1194                 cpu_has_vmx_virtualize_apic_accesses();
1195 }
1196
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1198 {
1199         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1200 }
1201
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1203 {
1204         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1205 }
1206
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1208 {
1209         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1210 }
1211
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1213 {
1214         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1215 }
1216
1217 static inline bool cpu_has_vmx_ept_ad_bits(void)
1218 {
1219         return vmx_capability.ept & VMX_EPT_AD_BIT;
1220 }
1221
1222 static inline bool cpu_has_vmx_invept_context(void)
1223 {
1224         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1225 }
1226
1227 static inline bool cpu_has_vmx_invept_global(void)
1228 {
1229         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1230 }
1231
1232 static inline bool cpu_has_vmx_invvpid_single(void)
1233 {
1234         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1235 }
1236
1237 static inline bool cpu_has_vmx_invvpid_global(void)
1238 {
1239         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1240 }
1241
1242 static inline bool cpu_has_vmx_ept(void)
1243 {
1244         return vmcs_config.cpu_based_2nd_exec_ctrl &
1245                 SECONDARY_EXEC_ENABLE_EPT;
1246 }
1247
1248 static inline bool cpu_has_vmx_unrestricted_guest(void)
1249 {
1250         return vmcs_config.cpu_based_2nd_exec_ctrl &
1251                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1252 }
1253
1254 static inline bool cpu_has_vmx_ple(void)
1255 {
1256         return vmcs_config.cpu_based_2nd_exec_ctrl &
1257                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1258 }
1259
1260 static inline bool cpu_has_vmx_basic_inout(void)
1261 {
1262         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1263 }
1264
1265 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1266 {
1267         return flexpriority_enabled && lapic_in_kernel(vcpu);
1268 }
1269
1270 static inline bool cpu_has_vmx_vpid(void)
1271 {
1272         return vmcs_config.cpu_based_2nd_exec_ctrl &
1273                 SECONDARY_EXEC_ENABLE_VPID;
1274 }
1275
1276 static inline bool cpu_has_vmx_rdtscp(void)
1277 {
1278         return vmcs_config.cpu_based_2nd_exec_ctrl &
1279                 SECONDARY_EXEC_RDTSCP;
1280 }
1281
1282 static inline bool cpu_has_vmx_invpcid(void)
1283 {
1284         return vmcs_config.cpu_based_2nd_exec_ctrl &
1285                 SECONDARY_EXEC_ENABLE_INVPCID;
1286 }
1287
1288 static inline bool cpu_has_virtual_nmis(void)
1289 {
1290         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1291 }
1292
1293 static inline bool cpu_has_vmx_wbinvd_exit(void)
1294 {
1295         return vmcs_config.cpu_based_2nd_exec_ctrl &
1296                 SECONDARY_EXEC_WBINVD_EXITING;
1297 }
1298
1299 static inline bool cpu_has_vmx_shadow_vmcs(void)
1300 {
1301         u64 vmx_msr;
1302         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1303         /* check if the cpu supports writing r/o exit information fields */
1304         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1305                 return false;
1306
1307         return vmcs_config.cpu_based_2nd_exec_ctrl &
1308                 SECONDARY_EXEC_SHADOW_VMCS;
1309 }
1310
1311 static inline bool cpu_has_vmx_pml(void)
1312 {
1313         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1314 }
1315
1316 static inline bool cpu_has_vmx_tsc_scaling(void)
1317 {
1318         return vmcs_config.cpu_based_2nd_exec_ctrl &
1319                 SECONDARY_EXEC_TSC_SCALING;
1320 }
1321
1322 static inline bool report_flexpriority(void)
1323 {
1324         return flexpriority_enabled;
1325 }
1326
1327 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1328 {
1329         return vmcs12->cpu_based_vm_exec_control & bit;
1330 }
1331
1332 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1333 {
1334         return (vmcs12->cpu_based_vm_exec_control &
1335                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1336                 (vmcs12->secondary_vm_exec_control & bit);
1337 }
1338
1339 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1340 {
1341         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1342 }
1343
1344 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1345 {
1346         return vmcs12->pin_based_vm_exec_control &
1347                 PIN_BASED_VMX_PREEMPTION_TIMER;
1348 }
1349
1350 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1351 {
1352         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1353 }
1354
1355 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1356 {
1357         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1358                 vmx_xsaves_supported();
1359 }
1360
1361 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1362 {
1363         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1364 }
1365
1366 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1367 {
1368         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1369 }
1370
1371 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1372 {
1373         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1374 }
1375
1376 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1377 {
1378         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1379 }
1380
1381 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1382 {
1383         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1384 }
1385
1386 static inline bool is_nmi(u32 intr_info)
1387 {
1388         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1389                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1390 }
1391
1392 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1393                               u32 exit_intr_info,
1394                               unsigned long exit_qualification);
1395 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1396                         struct vmcs12 *vmcs12,
1397                         u32 reason, unsigned long qualification);
1398
1399 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1400 {
1401         int i;
1402
1403         for (i = 0; i < vmx->nmsrs; ++i)
1404                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1405                         return i;
1406         return -1;
1407 }
1408
1409 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1410 {
1411     struct {
1412         u64 vpid : 16;
1413         u64 rsvd : 48;
1414         u64 gva;
1415     } operand = { vpid, 0, gva };
1416
1417     asm volatile (__ex(ASM_VMX_INVVPID)
1418                   /* CF==1 or ZF==1 --> rc = -1 */
1419                   "; ja 1f ; ud2 ; 1:"
1420                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1421 }
1422
1423 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1424 {
1425         struct {
1426                 u64 eptp, gpa;
1427         } operand = {eptp, gpa};
1428
1429         asm volatile (__ex(ASM_VMX_INVEPT)
1430                         /* CF==1 or ZF==1 --> rc = -1 */
1431                         "; ja 1f ; ud2 ; 1:\n"
1432                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1433 }
1434
1435 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1436 {
1437         int i;
1438
1439         i = __find_msr_index(vmx, msr);
1440         if (i >= 0)
1441                 return &vmx->guest_msrs[i];
1442         return NULL;
1443 }
1444
1445 static void vmcs_clear(struct vmcs *vmcs)
1446 {
1447         u64 phys_addr = __pa(vmcs);
1448         u8 error;
1449
1450         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1451                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1452                       : "cc", "memory");
1453         if (error)
1454                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1455                        vmcs, phys_addr);
1456 }
1457
1458 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1459 {
1460         vmcs_clear(loaded_vmcs->vmcs);
1461         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1462                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1463         loaded_vmcs->cpu = -1;
1464         loaded_vmcs->launched = 0;
1465 }
1466
1467 static void vmcs_load(struct vmcs *vmcs)
1468 {
1469         u64 phys_addr = __pa(vmcs);
1470         u8 error;
1471
1472         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1473                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1474                         : "cc", "memory");
1475         if (error)
1476                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1477                        vmcs, phys_addr);
1478 }
1479
1480 #ifdef CONFIG_KEXEC_CORE
1481 /*
1482  * This bitmap is used to indicate whether the vmclear
1483  * operation is enabled on all cpus. All disabled by
1484  * default.
1485  */
1486 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1487
1488 static inline void crash_enable_local_vmclear(int cpu)
1489 {
1490         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1491 }
1492
1493 static inline void crash_disable_local_vmclear(int cpu)
1494 {
1495         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1496 }
1497
1498 static inline int crash_local_vmclear_enabled(int cpu)
1499 {
1500         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1501 }
1502
1503 static void crash_vmclear_local_loaded_vmcss(void)
1504 {
1505         int cpu = raw_smp_processor_id();
1506         struct loaded_vmcs *v;
1507
1508         if (!crash_local_vmclear_enabled(cpu))
1509                 return;
1510
1511         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1512                             loaded_vmcss_on_cpu_link)
1513                 vmcs_clear(v->vmcs);
1514 }
1515 #else
1516 static inline void crash_enable_local_vmclear(int cpu) { }
1517 static inline void crash_disable_local_vmclear(int cpu) { }
1518 #endif /* CONFIG_KEXEC_CORE */
1519
1520 static void __loaded_vmcs_clear(void *arg)
1521 {
1522         struct loaded_vmcs *loaded_vmcs = arg;
1523         int cpu = raw_smp_processor_id();
1524
1525         if (loaded_vmcs->cpu != cpu)
1526                 return; /* vcpu migration can race with cpu offline */
1527         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1528                 per_cpu(current_vmcs, cpu) = NULL;
1529         crash_disable_local_vmclear(cpu);
1530         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1531
1532         /*
1533          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1534          * is before setting loaded_vmcs->vcpu to -1 which is done in
1535          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1536          * then adds the vmcs into percpu list before it is deleted.
1537          */
1538         smp_wmb();
1539
1540         loaded_vmcs_init(loaded_vmcs);
1541         crash_enable_local_vmclear(cpu);
1542 }
1543
1544 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1545 {
1546         int cpu = loaded_vmcs->cpu;
1547
1548         if (cpu != -1)
1549                 smp_call_function_single(cpu,
1550                          __loaded_vmcs_clear, loaded_vmcs, 1);
1551 }
1552
1553 static inline void vpid_sync_vcpu_single(int vpid)
1554 {
1555         if (vpid == 0)
1556                 return;
1557
1558         if (cpu_has_vmx_invvpid_single())
1559                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1560 }
1561
1562 static inline void vpid_sync_vcpu_global(void)
1563 {
1564         if (cpu_has_vmx_invvpid_global())
1565                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1566 }
1567
1568 static inline void vpid_sync_context(int vpid)
1569 {
1570         if (cpu_has_vmx_invvpid_single())
1571                 vpid_sync_vcpu_single(vpid);
1572         else
1573                 vpid_sync_vcpu_global();
1574 }
1575
1576 static inline void ept_sync_global(void)
1577 {
1578         if (cpu_has_vmx_invept_global())
1579                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1580 }
1581
1582 static inline void ept_sync_context(u64 eptp)
1583 {
1584         if (enable_ept) {
1585                 if (cpu_has_vmx_invept_context())
1586                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1587                 else
1588                         ept_sync_global();
1589         }
1590 }
1591
1592 static __always_inline void vmcs_check16(unsigned long field)
1593 {
1594         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1595                          "16-bit accessor invalid for 64-bit field");
1596         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1597                          "16-bit accessor invalid for 64-bit high field");
1598         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1599                          "16-bit accessor invalid for 32-bit high field");
1600         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1601                          "16-bit accessor invalid for natural width field");
1602 }
1603
1604 static __always_inline void vmcs_check32(unsigned long field)
1605 {
1606         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1607                          "32-bit accessor invalid for 16-bit field");
1608         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1609                          "32-bit accessor invalid for natural width field");
1610 }
1611
1612 static __always_inline void vmcs_check64(unsigned long field)
1613 {
1614         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1615                          "64-bit accessor invalid for 16-bit field");
1616         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1617                          "64-bit accessor invalid for 64-bit high field");
1618         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1619                          "64-bit accessor invalid for 32-bit field");
1620         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1621                          "64-bit accessor invalid for natural width field");
1622 }
1623
1624 static __always_inline void vmcs_checkl(unsigned long field)
1625 {
1626         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1627                          "Natural width accessor invalid for 16-bit field");
1628         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1629                          "Natural width accessor invalid for 64-bit field");
1630         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1631                          "Natural width accessor invalid for 64-bit high field");
1632         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1633                          "Natural width accessor invalid for 32-bit field");
1634 }
1635
1636 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1637 {
1638         unsigned long value;
1639
1640         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1641                       : "=a"(value) : "d"(field) : "cc");
1642         return value;
1643 }
1644
1645 static __always_inline u16 vmcs_read16(unsigned long field)
1646 {
1647         vmcs_check16(field);
1648         return __vmcs_readl(field);
1649 }
1650
1651 static __always_inline u32 vmcs_read32(unsigned long field)
1652 {
1653         vmcs_check32(field);
1654         return __vmcs_readl(field);
1655 }
1656
1657 static __always_inline u64 vmcs_read64(unsigned long field)
1658 {
1659         vmcs_check64(field);
1660 #ifdef CONFIG_X86_64
1661         return __vmcs_readl(field);
1662 #else
1663         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1664 #endif
1665 }
1666
1667 static __always_inline unsigned long vmcs_readl(unsigned long field)
1668 {
1669         vmcs_checkl(field);
1670         return __vmcs_readl(field);
1671 }
1672
1673 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1674 {
1675         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1676                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1677         dump_stack();
1678 }
1679
1680 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1681 {
1682         u8 error;
1683
1684         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1685                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1686         if (unlikely(error))
1687                 vmwrite_error(field, value);
1688 }
1689
1690 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1691 {
1692         vmcs_check16(field);
1693         __vmcs_writel(field, value);
1694 }
1695
1696 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1697 {
1698         vmcs_check32(field);
1699         __vmcs_writel(field, value);
1700 }
1701
1702 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1703 {
1704         vmcs_check64(field);
1705         __vmcs_writel(field, value);
1706 #ifndef CONFIG_X86_64
1707         asm volatile ("");
1708         __vmcs_writel(field+1, value >> 32);
1709 #endif
1710 }
1711
1712 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1713 {
1714         vmcs_checkl(field);
1715         __vmcs_writel(field, value);
1716 }
1717
1718 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1719 {
1720         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1721                          "vmcs_clear_bits does not support 64-bit fields");
1722         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1723 }
1724
1725 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1726 {
1727         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1728                          "vmcs_set_bits does not support 64-bit fields");
1729         __vmcs_writel(field, __vmcs_readl(field) | mask);
1730 }
1731
1732 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1733 {
1734         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1735 }
1736
1737 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1738 {
1739         vmcs_write32(VM_ENTRY_CONTROLS, val);
1740         vmx->vm_entry_controls_shadow = val;
1741 }
1742
1743 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1744 {
1745         if (vmx->vm_entry_controls_shadow != val)
1746                 vm_entry_controls_init(vmx, val);
1747 }
1748
1749 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1750 {
1751         return vmx->vm_entry_controls_shadow;
1752 }
1753
1754
1755 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1756 {
1757         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1758 }
1759
1760 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1761 {
1762         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1763 }
1764
1765 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1766 {
1767         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1768 }
1769
1770 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1771 {
1772         vmcs_write32(VM_EXIT_CONTROLS, val);
1773         vmx->vm_exit_controls_shadow = val;
1774 }
1775
1776 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1777 {
1778         if (vmx->vm_exit_controls_shadow != val)
1779                 vm_exit_controls_init(vmx, val);
1780 }
1781
1782 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1783 {
1784         return vmx->vm_exit_controls_shadow;
1785 }
1786
1787
1788 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1789 {
1790         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1791 }
1792
1793 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1794 {
1795         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1796 }
1797
1798 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1799 {
1800         vmx->segment_cache.bitmask = 0;
1801 }
1802
1803 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1804                                        unsigned field)
1805 {
1806         bool ret;
1807         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1808
1809         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1810                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1811                 vmx->segment_cache.bitmask = 0;
1812         }
1813         ret = vmx->segment_cache.bitmask & mask;
1814         vmx->segment_cache.bitmask |= mask;
1815         return ret;
1816 }
1817
1818 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1819 {
1820         u16 *p = &vmx->segment_cache.seg[seg].selector;
1821
1822         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1823                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1824         return *p;
1825 }
1826
1827 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1828 {
1829         ulong *p = &vmx->segment_cache.seg[seg].base;
1830
1831         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1832                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1833         return *p;
1834 }
1835
1836 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1837 {
1838         u32 *p = &vmx->segment_cache.seg[seg].limit;
1839
1840         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1841                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1842         return *p;
1843 }
1844
1845 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1846 {
1847         u32 *p = &vmx->segment_cache.seg[seg].ar;
1848
1849         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1850                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1851         return *p;
1852 }
1853
1854 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1855 {
1856         u32 eb;
1857
1858         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1859              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1860         if ((vcpu->guest_debug &
1861              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1862             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1863                 eb |= 1u << BP_VECTOR;
1864         if (to_vmx(vcpu)->rmode.vm86_active)
1865                 eb = ~0;
1866         if (enable_ept)
1867                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1868         if (vcpu->fpu_active)
1869                 eb &= ~(1u << NM_VECTOR);
1870
1871         /* When we are running a nested L2 guest and L1 specified for it a
1872          * certain exception bitmap, we must trap the same exceptions and pass
1873          * them to L1. When running L2, we will only handle the exceptions
1874          * specified above if L1 did not want them.
1875          */
1876         if (is_guest_mode(vcpu))
1877                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1878
1879         vmcs_write32(EXCEPTION_BITMAP, eb);
1880 }
1881
1882 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1883                 unsigned long entry, unsigned long exit)
1884 {
1885         vm_entry_controls_clearbit(vmx, entry);
1886         vm_exit_controls_clearbit(vmx, exit);
1887 }
1888
1889 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1890 {
1891         unsigned i;
1892         struct msr_autoload *m = &vmx->msr_autoload;
1893
1894         switch (msr) {
1895         case MSR_EFER:
1896                 if (cpu_has_load_ia32_efer) {
1897                         clear_atomic_switch_msr_special(vmx,
1898                                         VM_ENTRY_LOAD_IA32_EFER,
1899                                         VM_EXIT_LOAD_IA32_EFER);
1900                         return;
1901                 }
1902                 break;
1903         case MSR_CORE_PERF_GLOBAL_CTRL:
1904                 if (cpu_has_load_perf_global_ctrl) {
1905                         clear_atomic_switch_msr_special(vmx,
1906                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1907                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1908                         return;
1909                 }
1910                 break;
1911         }
1912
1913         for (i = 0; i < m->nr; ++i)
1914                 if (m->guest[i].index == msr)
1915                         break;
1916
1917         if (i == m->nr)
1918                 return;
1919         --m->nr;
1920         m->guest[i] = m->guest[m->nr];
1921         m->host[i] = m->host[m->nr];
1922         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1923         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1924 }
1925
1926 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1927                 unsigned long entry, unsigned long exit,
1928                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1929                 u64 guest_val, u64 host_val)
1930 {
1931         vmcs_write64(guest_val_vmcs, guest_val);
1932         vmcs_write64(host_val_vmcs, host_val);
1933         vm_entry_controls_setbit(vmx, entry);
1934         vm_exit_controls_setbit(vmx, exit);
1935 }
1936
1937 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1938                                   u64 guest_val, u64 host_val)
1939 {
1940         unsigned i;
1941         struct msr_autoload *m = &vmx->msr_autoload;
1942
1943         switch (msr) {
1944         case MSR_EFER:
1945                 if (cpu_has_load_ia32_efer) {
1946                         add_atomic_switch_msr_special(vmx,
1947                                         VM_ENTRY_LOAD_IA32_EFER,
1948                                         VM_EXIT_LOAD_IA32_EFER,
1949                                         GUEST_IA32_EFER,
1950                                         HOST_IA32_EFER,
1951                                         guest_val, host_val);
1952                         return;
1953                 }
1954                 break;
1955         case MSR_CORE_PERF_GLOBAL_CTRL:
1956                 if (cpu_has_load_perf_global_ctrl) {
1957                         add_atomic_switch_msr_special(vmx,
1958                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1959                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1960                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1961                                         HOST_IA32_PERF_GLOBAL_CTRL,
1962                                         guest_val, host_val);
1963                         return;
1964                 }
1965                 break;
1966         case MSR_IA32_PEBS_ENABLE:
1967                 /* PEBS needs a quiescent period after being disabled (to write
1968                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1969                  * provide that period, so a CPU could write host's record into
1970                  * guest's memory.
1971                  */
1972                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1973         }
1974
1975         for (i = 0; i < m->nr; ++i)
1976                 if (m->guest[i].index == msr)
1977                         break;
1978
1979         if (i == NR_AUTOLOAD_MSRS) {
1980                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1981                                 "Can't add msr %x\n", msr);
1982                 return;
1983         } else if (i == m->nr) {
1984                 ++m->nr;
1985                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1986                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1987         }
1988
1989         m->guest[i].index = msr;
1990         m->guest[i].value = guest_val;
1991         m->host[i].index = msr;
1992         m->host[i].value = host_val;
1993 }
1994
1995 static void reload_tss(void)
1996 {
1997         /*
1998          * VT restores TR but not its size.  Useless.
1999          */
2000         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2001         struct desc_struct *descs;
2002
2003         descs = (void *)gdt->address;
2004         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
2005         load_TR_desc();
2006 }
2007
2008 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2009 {
2010         u64 guest_efer = vmx->vcpu.arch.efer;
2011         u64 ignore_bits = 0;
2012
2013         if (!enable_ept) {
2014                 /*
2015                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2016                  * host CPUID is more efficient than testing guest CPUID
2017                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2018                  */
2019                 if (boot_cpu_has(X86_FEATURE_SMEP))
2020                         guest_efer |= EFER_NX;
2021                 else if (!(guest_efer & EFER_NX))
2022                         ignore_bits |= EFER_NX;
2023         }
2024
2025         /*
2026          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2027          */
2028         ignore_bits |= EFER_SCE;
2029 #ifdef CONFIG_X86_64
2030         ignore_bits |= EFER_LMA | EFER_LME;
2031         /* SCE is meaningful only in long mode on Intel */
2032         if (guest_efer & EFER_LMA)
2033                 ignore_bits &= ~(u64)EFER_SCE;
2034 #endif
2035
2036         clear_atomic_switch_msr(vmx, MSR_EFER);
2037
2038         /*
2039          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2040          * On CPUs that support "load IA32_EFER", always switch EFER
2041          * atomically, since it's faster than switching it manually.
2042          */
2043         if (cpu_has_load_ia32_efer ||
2044             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2045                 if (!(guest_efer & EFER_LMA))
2046                         guest_efer &= ~EFER_LME;
2047                 if (guest_efer != host_efer)
2048                         add_atomic_switch_msr(vmx, MSR_EFER,
2049                                               guest_efer, host_efer);
2050                 return false;
2051         } else {
2052                 guest_efer &= ~ignore_bits;
2053                 guest_efer |= host_efer & ignore_bits;
2054
2055                 vmx->guest_msrs[efer_offset].data = guest_efer;
2056                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2057
2058                 return true;
2059         }
2060 }
2061
2062 static unsigned long segment_base(u16 selector)
2063 {
2064         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2065         struct desc_struct *d;
2066         unsigned long table_base;
2067         unsigned long v;
2068
2069         if (!(selector & ~3))
2070                 return 0;
2071
2072         table_base = gdt->address;
2073
2074         if (selector & 4) {           /* from ldt */
2075                 u16 ldt_selector = kvm_read_ldt();
2076
2077                 if (!(ldt_selector & ~3))
2078                         return 0;
2079
2080                 table_base = segment_base(ldt_selector);
2081         }
2082         d = (struct desc_struct *)(table_base + (selector & ~7));
2083         v = get_desc_base(d);
2084 #ifdef CONFIG_X86_64
2085        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2086                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2087 #endif
2088         return v;
2089 }
2090
2091 static inline unsigned long kvm_read_tr_base(void)
2092 {
2093         u16 tr;
2094         asm("str %0" : "=g"(tr));
2095         return segment_base(tr);
2096 }
2097
2098 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2099 {
2100         struct vcpu_vmx *vmx = to_vmx(vcpu);
2101         int i;
2102
2103         if (vmx->host_state.loaded)
2104                 return;
2105
2106         vmx->host_state.loaded = 1;
2107         /*
2108          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2109          * allow segment selectors with cpl > 0 or ti == 1.
2110          */
2111         vmx->host_state.ldt_sel = kvm_read_ldt();
2112         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2113         savesegment(fs, vmx->host_state.fs_sel);
2114         if (!(vmx->host_state.fs_sel & 7)) {
2115                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2116                 vmx->host_state.fs_reload_needed = 0;
2117         } else {
2118                 vmcs_write16(HOST_FS_SELECTOR, 0);
2119                 vmx->host_state.fs_reload_needed = 1;
2120         }
2121         savesegment(gs, vmx->host_state.gs_sel);
2122         if (!(vmx->host_state.gs_sel & 7))
2123                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2124         else {
2125                 vmcs_write16(HOST_GS_SELECTOR, 0);
2126                 vmx->host_state.gs_ldt_reload_needed = 1;
2127         }
2128
2129 #ifdef CONFIG_X86_64
2130         savesegment(ds, vmx->host_state.ds_sel);
2131         savesegment(es, vmx->host_state.es_sel);
2132 #endif
2133
2134 #ifdef CONFIG_X86_64
2135         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2136         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2137 #else
2138         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2139         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2140 #endif
2141
2142 #ifdef CONFIG_X86_64
2143         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2144         if (is_long_mode(&vmx->vcpu))
2145                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2146 #endif
2147         if (boot_cpu_has(X86_FEATURE_MPX))
2148                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2149         for (i = 0; i < vmx->save_nmsrs; ++i)
2150                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2151                                    vmx->guest_msrs[i].data,
2152                                    vmx->guest_msrs[i].mask);
2153 }
2154
2155 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2156 {
2157         if (!vmx->host_state.loaded)
2158                 return;
2159
2160         ++vmx->vcpu.stat.host_state_reload;
2161         vmx->host_state.loaded = 0;
2162 #ifdef CONFIG_X86_64
2163         if (is_long_mode(&vmx->vcpu))
2164                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2165 #endif
2166         if (vmx->host_state.gs_ldt_reload_needed) {
2167                 kvm_load_ldt(vmx->host_state.ldt_sel);
2168 #ifdef CONFIG_X86_64
2169                 load_gs_index(vmx->host_state.gs_sel);
2170 #else
2171                 loadsegment(gs, vmx->host_state.gs_sel);
2172 #endif
2173         }
2174         if (vmx->host_state.fs_reload_needed)
2175                 loadsegment(fs, vmx->host_state.fs_sel);
2176 #ifdef CONFIG_X86_64
2177         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2178                 loadsegment(ds, vmx->host_state.ds_sel);
2179                 loadsegment(es, vmx->host_state.es_sel);
2180         }
2181 #endif
2182         reload_tss();
2183 #ifdef CONFIG_X86_64
2184         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2185 #endif
2186         if (vmx->host_state.msr_host_bndcfgs)
2187                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2188         load_gdt(this_cpu_ptr(&host_gdt));
2189 }
2190
2191 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2192 {
2193         preempt_disable();
2194         __vmx_load_host_state(vmx);
2195         preempt_enable();
2196 }
2197
2198 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2199 {
2200         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2201         struct pi_desc old, new;
2202         unsigned int dest;
2203
2204         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2205                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2206                 !kvm_vcpu_apicv_active(vcpu))
2207                 return;
2208
2209         do {
2210                 old.control = new.control = pi_desc->control;
2211
2212                 /*
2213                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2214                  * are two possible cases:
2215                  * 1. After running 'pre_block', context switch
2216                  *    happened. For this case, 'sn' was set in
2217                  *    vmx_vcpu_put(), so we need to clear it here.
2218                  * 2. After running 'pre_block', we were blocked,
2219                  *    and woken up by some other guy. For this case,
2220                  *    we don't need to do anything, 'pi_post_block'
2221                  *    will do everything for us. However, we cannot
2222                  *    check whether it is case #1 or case #2 here
2223                  *    (maybe, not needed), so we also clear sn here,
2224                  *    I think it is not a big deal.
2225                  */
2226                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2227                         if (vcpu->cpu != cpu) {
2228                                 dest = cpu_physical_id(cpu);
2229
2230                                 if (x2apic_enabled())
2231                                         new.ndst = dest;
2232                                 else
2233                                         new.ndst = (dest << 8) & 0xFF00;
2234                         }
2235
2236                         /* set 'NV' to 'notification vector' */
2237                         new.nv = POSTED_INTR_VECTOR;
2238                 }
2239
2240                 /* Allow posting non-urgent interrupts */
2241                 new.sn = 0;
2242         } while (cmpxchg(&pi_desc->control, old.control,
2243                         new.control) != old.control);
2244 }
2245
2246 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2247 {
2248         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2249         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2250 }
2251
2252 /*
2253  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2254  * vcpu mutex is already taken.
2255  */
2256 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2257 {
2258         struct vcpu_vmx *vmx = to_vmx(vcpu);
2259         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2260         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2261
2262         if (!vmm_exclusive)
2263                 kvm_cpu_vmxon(phys_addr);
2264         else if (!already_loaded)
2265                 loaded_vmcs_clear(vmx->loaded_vmcs);
2266
2267         if (!already_loaded) {
2268                 local_irq_disable();
2269                 crash_disable_local_vmclear(cpu);
2270
2271                 /*
2272                  * Read loaded_vmcs->cpu should be before fetching
2273                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2274                  * See the comments in __loaded_vmcs_clear().
2275                  */
2276                 smp_rmb();
2277
2278                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2279                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2280                 crash_enable_local_vmclear(cpu);
2281                 local_irq_enable();
2282         }
2283
2284         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2285                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2286                 vmcs_load(vmx->loaded_vmcs->vmcs);
2287         }
2288
2289         if (!already_loaded) {
2290                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2291                 unsigned long sysenter_esp;
2292
2293                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2294
2295                 /*
2296                  * Linux uses per-cpu TSS and GDT, so set these when switching
2297                  * processors.
2298                  */
2299                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2300                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2301
2302                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2303                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2304
2305                 vmx->loaded_vmcs->cpu = cpu;
2306         }
2307
2308         /* Setup TSC multiplier */
2309         if (kvm_has_tsc_control &&
2310             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2311                 decache_tsc_multiplier(vmx);
2312
2313         vmx_vcpu_pi_load(vcpu, cpu);
2314         vmx->host_pkru = read_pkru();
2315 }
2316
2317 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2318 {
2319         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2320
2321         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2322                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2323                 !kvm_vcpu_apicv_active(vcpu))
2324                 return;
2325
2326         /* Set SN when the vCPU is preempted */
2327         if (vcpu->preempted)
2328                 pi_set_sn(pi_desc);
2329 }
2330
2331 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2332 {
2333         vmx_vcpu_pi_put(vcpu);
2334
2335         __vmx_load_host_state(to_vmx(vcpu));
2336         if (!vmm_exclusive) {
2337                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2338                 vcpu->cpu = -1;
2339                 kvm_cpu_vmxoff();
2340         }
2341 }
2342
2343 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2344 {
2345         ulong cr0;
2346
2347         if (vcpu->fpu_active)
2348                 return;
2349         vcpu->fpu_active = 1;
2350         cr0 = vmcs_readl(GUEST_CR0);
2351         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2352         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2353         vmcs_writel(GUEST_CR0, cr0);
2354         update_exception_bitmap(vcpu);
2355         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2356         if (is_guest_mode(vcpu))
2357                 vcpu->arch.cr0_guest_owned_bits &=
2358                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2359         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2360 }
2361
2362 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2363
2364 /*
2365  * Return the cr0 value that a nested guest would read. This is a combination
2366  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2367  * its hypervisor (cr0_read_shadow).
2368  */
2369 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2370 {
2371         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2372                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2373 }
2374 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2375 {
2376         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2377                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2378 }
2379
2380 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2381 {
2382         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2383          * set this *before* calling this function.
2384          */
2385         vmx_decache_cr0_guest_bits(vcpu);
2386         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2387         update_exception_bitmap(vcpu);
2388         vcpu->arch.cr0_guest_owned_bits = 0;
2389         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2390         if (is_guest_mode(vcpu)) {
2391                 /*
2392                  * L1's specified read shadow might not contain the TS bit,
2393                  * so now that we turned on shadowing of this bit, we need to
2394                  * set this bit of the shadow. Like in nested_vmx_run we need
2395                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2396                  * up-to-date here because we just decached cr0.TS (and we'll
2397                  * only update vmcs12->guest_cr0 on nested exit).
2398                  */
2399                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2400                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2401                         (vcpu->arch.cr0 & X86_CR0_TS);
2402                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2403         } else
2404                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2405 }
2406
2407 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2408 {
2409         unsigned long rflags, save_rflags;
2410
2411         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2412                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2413                 rflags = vmcs_readl(GUEST_RFLAGS);
2414                 if (to_vmx(vcpu)->rmode.vm86_active) {
2415                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2416                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2417                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2418                 }
2419                 to_vmx(vcpu)->rflags = rflags;
2420         }
2421         return to_vmx(vcpu)->rflags;
2422 }
2423
2424 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2425 {
2426         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2427         to_vmx(vcpu)->rflags = rflags;
2428         if (to_vmx(vcpu)->rmode.vm86_active) {
2429                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2430                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2431         }
2432         vmcs_writel(GUEST_RFLAGS, rflags);
2433 }
2434
2435 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2436 {
2437         return to_vmx(vcpu)->guest_pkru;
2438 }
2439
2440 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2441 {
2442         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2443         int ret = 0;
2444
2445         if (interruptibility & GUEST_INTR_STATE_STI)
2446                 ret |= KVM_X86_SHADOW_INT_STI;
2447         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2448                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2449
2450         return ret;
2451 }
2452
2453 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2454 {
2455         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2456         u32 interruptibility = interruptibility_old;
2457
2458         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2459
2460         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2461                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2462         else if (mask & KVM_X86_SHADOW_INT_STI)
2463                 interruptibility |= GUEST_INTR_STATE_STI;
2464
2465         if ((interruptibility != interruptibility_old))
2466                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2467 }
2468
2469 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2470 {
2471         unsigned long rip;
2472
2473         rip = kvm_rip_read(vcpu);
2474         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2475         kvm_rip_write(vcpu, rip);
2476
2477         /* skipping an emulated instruction also counts */
2478         vmx_set_interrupt_shadow(vcpu, 0);
2479 }
2480
2481 /*
2482  * KVM wants to inject page-faults which it got to the guest. This function
2483  * checks whether in a nested guest, we need to inject them to L1 or L2.
2484  */
2485 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2486 {
2487         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2488
2489         if (!(vmcs12->exception_bitmap & (1u << nr)))
2490                 return 0;
2491
2492         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2493                           vmcs_read32(VM_EXIT_INTR_INFO),
2494                           vmcs_readl(EXIT_QUALIFICATION));
2495         return 1;
2496 }
2497
2498 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2499                                 bool has_error_code, u32 error_code,
2500                                 bool reinject)
2501 {
2502         struct vcpu_vmx *vmx = to_vmx(vcpu);
2503         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2504
2505         if (!reinject && is_guest_mode(vcpu) &&
2506             nested_vmx_check_exception(vcpu, nr))
2507                 return;
2508
2509         if (has_error_code) {
2510                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2511                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2512         }
2513
2514         if (vmx->rmode.vm86_active) {
2515                 int inc_eip = 0;
2516                 if (kvm_exception_is_soft(nr))
2517                         inc_eip = vcpu->arch.event_exit_inst_len;
2518                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2519                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2520                 return;
2521         }
2522
2523         if (kvm_exception_is_soft(nr)) {
2524                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2525                              vmx->vcpu.arch.event_exit_inst_len);
2526                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2527         } else
2528                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2529
2530         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2531 }
2532
2533 static bool vmx_rdtscp_supported(void)
2534 {
2535         return cpu_has_vmx_rdtscp();
2536 }
2537
2538 static bool vmx_invpcid_supported(void)
2539 {
2540         return cpu_has_vmx_invpcid() && enable_ept;
2541 }
2542
2543 /*
2544  * Swap MSR entry in host/guest MSR entry array.
2545  */
2546 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2547 {
2548         struct shared_msr_entry tmp;
2549
2550         tmp = vmx->guest_msrs[to];
2551         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2552         vmx->guest_msrs[from] = tmp;
2553 }
2554
2555 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2556 {
2557         unsigned long *msr_bitmap;
2558
2559         if (is_guest_mode(vcpu))
2560                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2561         else if (cpu_has_secondary_exec_ctrls() &&
2562                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2563                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2564                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2565                         if (is_long_mode(vcpu))
2566                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2567                         else
2568                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2569                 } else {
2570                         if (is_long_mode(vcpu))
2571                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2572                         else
2573                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2574                 }
2575         } else {
2576                 if (is_long_mode(vcpu))
2577                         msr_bitmap = vmx_msr_bitmap_longmode;
2578                 else
2579                         msr_bitmap = vmx_msr_bitmap_legacy;
2580         }
2581
2582         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2583 }
2584
2585 /*
2586  * Set up the vmcs to automatically save and restore system
2587  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2588  * mode, as fiddling with msrs is very expensive.
2589  */
2590 static void setup_msrs(struct vcpu_vmx *vmx)
2591 {
2592         int save_nmsrs, index;
2593
2594         save_nmsrs = 0;
2595 #ifdef CONFIG_X86_64
2596         if (is_long_mode(&vmx->vcpu)) {
2597                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2598                 if (index >= 0)
2599                         move_msr_up(vmx, index, save_nmsrs++);
2600                 index = __find_msr_index(vmx, MSR_LSTAR);
2601                 if (index >= 0)
2602                         move_msr_up(vmx, index, save_nmsrs++);
2603                 index = __find_msr_index(vmx, MSR_CSTAR);
2604                 if (index >= 0)
2605                         move_msr_up(vmx, index, save_nmsrs++);
2606                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2607                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2608                         move_msr_up(vmx, index, save_nmsrs++);
2609                 /*
2610                  * MSR_STAR is only needed on long mode guests, and only
2611                  * if efer.sce is enabled.
2612                  */
2613                 index = __find_msr_index(vmx, MSR_STAR);
2614                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2615                         move_msr_up(vmx, index, save_nmsrs++);
2616         }
2617 #endif
2618         index = __find_msr_index(vmx, MSR_EFER);
2619         if (index >= 0 && update_transition_efer(vmx, index))
2620                 move_msr_up(vmx, index, save_nmsrs++);
2621
2622         vmx->save_nmsrs = save_nmsrs;
2623
2624         if (cpu_has_vmx_msr_bitmap())
2625                 vmx_set_msr_bitmap(&vmx->vcpu);
2626 }
2627
2628 /*
2629  * reads and returns guest's timestamp counter "register"
2630  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2631  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2632  */
2633 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2634 {
2635         u64 host_tsc, tsc_offset;
2636
2637         host_tsc = rdtsc();
2638         tsc_offset = vmcs_read64(TSC_OFFSET);
2639         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2640 }
2641
2642 /*
2643  * writes 'offset' into guest's timestamp counter offset register
2644  */
2645 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2646 {
2647         if (is_guest_mode(vcpu)) {
2648                 /*
2649                  * We're here if L1 chose not to trap WRMSR to TSC. According
2650                  * to the spec, this should set L1's TSC; The offset that L1
2651                  * set for L2 remains unchanged, and still needs to be added
2652                  * to the newly set TSC to get L2's TSC.
2653                  */
2654                 struct vmcs12 *vmcs12;
2655                 /* recalculate vmcs02.TSC_OFFSET: */
2656                 vmcs12 = get_vmcs12(vcpu);
2657                 vmcs_write64(TSC_OFFSET, offset +
2658                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2659                          vmcs12->tsc_offset : 0));
2660         } else {
2661                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2662                                            vmcs_read64(TSC_OFFSET), offset);
2663                 vmcs_write64(TSC_OFFSET, offset);
2664         }
2665 }
2666
2667 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2668 {
2669         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2670         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2671 }
2672
2673 /*
2674  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2675  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2676  * all guests if the "nested" module option is off, and can also be disabled
2677  * for a single guest by disabling its VMX cpuid bit.
2678  */
2679 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2680 {
2681         return nested && guest_cpuid_has_vmx(vcpu);
2682 }
2683
2684 /*
2685  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2686  * returned for the various VMX controls MSRs when nested VMX is enabled.
2687  * The same values should also be used to verify that vmcs12 control fields are
2688  * valid during nested entry from L1 to L2.
2689  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2690  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2691  * bit in the high half is on if the corresponding bit in the control field
2692  * may be on. See also vmx_control_verify().
2693  */
2694 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2695 {
2696         /*
2697          * Note that as a general rule, the high half of the MSRs (bits in
2698          * the control fields which may be 1) should be initialized by the
2699          * intersection of the underlying hardware's MSR (i.e., features which
2700          * can be supported) and the list of features we want to expose -
2701          * because they are known to be properly supported in our code.
2702          * Also, usually, the low half of the MSRs (bits which must be 1) can
2703          * be set to 0, meaning that L1 may turn off any of these bits. The
2704          * reason is that if one of these bits is necessary, it will appear
2705          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2706          * fields of vmcs01 and vmcs02, will turn these bits off - and
2707          * nested_vmx_exit_handled() will not pass related exits to L1.
2708          * These rules have exceptions below.
2709          */
2710
2711         /* pin-based controls */
2712         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2713                 vmx->nested.nested_vmx_pinbased_ctls_low,
2714                 vmx->nested.nested_vmx_pinbased_ctls_high);
2715         vmx->nested.nested_vmx_pinbased_ctls_low |=
2716                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2717         vmx->nested.nested_vmx_pinbased_ctls_high &=
2718                 PIN_BASED_EXT_INTR_MASK |
2719                 PIN_BASED_NMI_EXITING |
2720                 PIN_BASED_VIRTUAL_NMIS;
2721         vmx->nested.nested_vmx_pinbased_ctls_high |=
2722                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2723                 PIN_BASED_VMX_PREEMPTION_TIMER;
2724         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2725                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2726                         PIN_BASED_POSTED_INTR;
2727
2728         /* exit controls */
2729         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2730                 vmx->nested.nested_vmx_exit_ctls_low,
2731                 vmx->nested.nested_vmx_exit_ctls_high);
2732         vmx->nested.nested_vmx_exit_ctls_low =
2733                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2734
2735         vmx->nested.nested_vmx_exit_ctls_high &=
2736 #ifdef CONFIG_X86_64
2737                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2738 #endif
2739                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2740         vmx->nested.nested_vmx_exit_ctls_high |=
2741                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2742                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2743                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2744
2745         if (kvm_mpx_supported())
2746                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2747
2748         /* We support free control of debug control saving. */
2749         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2750
2751         /* entry controls */
2752         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2753                 vmx->nested.nested_vmx_entry_ctls_low,
2754                 vmx->nested.nested_vmx_entry_ctls_high);
2755         vmx->nested.nested_vmx_entry_ctls_low =
2756                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2757         vmx->nested.nested_vmx_entry_ctls_high &=
2758 #ifdef CONFIG_X86_64
2759                 VM_ENTRY_IA32E_MODE |
2760 #endif
2761                 VM_ENTRY_LOAD_IA32_PAT;
2762         vmx->nested.nested_vmx_entry_ctls_high |=
2763                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2764         if (kvm_mpx_supported())
2765                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2766
2767         /* We support free control of debug control loading. */
2768         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2769
2770         /* cpu-based controls */
2771         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2772                 vmx->nested.nested_vmx_procbased_ctls_low,
2773                 vmx->nested.nested_vmx_procbased_ctls_high);
2774         vmx->nested.nested_vmx_procbased_ctls_low =
2775                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2776         vmx->nested.nested_vmx_procbased_ctls_high &=
2777                 CPU_BASED_VIRTUAL_INTR_PENDING |
2778                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2779                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2780                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2781                 CPU_BASED_CR3_STORE_EXITING |
2782 #ifdef CONFIG_X86_64
2783                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2784 #endif
2785                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2786                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2787                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2788                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2789                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2790         /*
2791          * We can allow some features even when not supported by the
2792          * hardware. For example, L1 can specify an MSR bitmap - and we
2793          * can use it to avoid exits to L1 - even when L0 runs L2
2794          * without MSR bitmaps.
2795          */
2796         vmx->nested.nested_vmx_procbased_ctls_high |=
2797                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2798                 CPU_BASED_USE_MSR_BITMAPS;
2799
2800         /* We support free control of CR3 access interception. */
2801         vmx->nested.nested_vmx_procbased_ctls_low &=
2802                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2803
2804         /* secondary cpu-based controls */
2805         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2806                 vmx->nested.nested_vmx_secondary_ctls_low,
2807                 vmx->nested.nested_vmx_secondary_ctls_high);
2808         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2809         vmx->nested.nested_vmx_secondary_ctls_high &=
2810                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2811                 SECONDARY_EXEC_RDTSCP |
2812                 SECONDARY_EXEC_DESC |
2813                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2814                 SECONDARY_EXEC_ENABLE_VPID |
2815                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2816                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2817                 SECONDARY_EXEC_WBINVD_EXITING |
2818                 SECONDARY_EXEC_XSAVES;
2819
2820         if (enable_ept) {
2821                 /* nested EPT: emulate EPT also to L1 */
2822                 vmx->nested.nested_vmx_secondary_ctls_high |=
2823                         SECONDARY_EXEC_ENABLE_EPT;
2824                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2825                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2826                          VMX_EPT_INVEPT_BIT;
2827                 if (cpu_has_vmx_ept_execute_only())
2828                         vmx->nested.nested_vmx_ept_caps |=
2829                                 VMX_EPT_EXECUTE_ONLY_BIT;
2830                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2831                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2832                         VMX_EPT_EXTENT_CONTEXT_BIT;
2833         } else
2834                 vmx->nested.nested_vmx_ept_caps = 0;
2835
2836         /*
2837          * Old versions of KVM use the single-context version without
2838          * checking for support, so declare that it is supported even
2839          * though it is treated as global context.  The alternative is
2840          * not failing the single-context invvpid, and it is worse.
2841          */
2842         if (enable_vpid)
2843                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2844                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2845         else
2846                 vmx->nested.nested_vmx_vpid_caps = 0;
2847
2848         if (enable_unrestricted_guest)
2849                 vmx->nested.nested_vmx_secondary_ctls_high |=
2850                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2851
2852         /* miscellaneous data */
2853         rdmsr(MSR_IA32_VMX_MISC,
2854                 vmx->nested.nested_vmx_misc_low,
2855                 vmx->nested.nested_vmx_misc_high);
2856         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2857         vmx->nested.nested_vmx_misc_low |=
2858                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2859                 VMX_MISC_ACTIVITY_HLT;
2860         vmx->nested.nested_vmx_misc_high = 0;
2861
2862         /*
2863          * This MSR reports some information about VMX support. We
2864          * should return information about the VMX we emulate for the
2865          * guest, and the VMCS structure we give it - not about the
2866          * VMX support of the underlying hardware.
2867          */
2868         vmx->nested.nested_vmx_basic =
2869                 VMCS12_REVISION |
2870                 VMX_BASIC_TRUE_CTLS |
2871                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2872                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2873
2874         if (cpu_has_vmx_basic_inout())
2875                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2876
2877         /*
2878          * These MSRs specify bits which the guest must keep fixed on
2879          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2880          * We picked the standard core2 setting.
2881          */
2882 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2883 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2884         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2885         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2886
2887         /* These MSRs specify bits which the guest must keep fixed off. */
2888         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2889         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2890
2891         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2892         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2893 }
2894
2895 /*
2896  * if fixed0[i] == 1: val[i] must be 1
2897  * if fixed1[i] == 0: val[i] must be 0
2898  */
2899 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2900 {
2901         return ((val & fixed1) | fixed0) == val;
2902 }
2903
2904 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2905 {
2906         return fixed_bits_valid(control, low, high);
2907 }
2908
2909 static inline u64 vmx_control_msr(u32 low, u32 high)
2910 {
2911         return low | ((u64)high << 32);
2912 }
2913
2914 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2915 {
2916         superset &= mask;
2917         subset &= mask;
2918
2919         return (superset | subset) == superset;
2920 }
2921
2922 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2923 {
2924         const u64 feature_and_reserved =
2925                 /* feature (except bit 48; see below) */
2926                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2927                 /* reserved */
2928                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2929         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2930
2931         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2932                 return -EINVAL;
2933
2934         /*
2935          * KVM does not emulate a version of VMX that constrains physical
2936          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2937          */
2938         if (data & BIT_ULL(48))
2939                 return -EINVAL;
2940
2941         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2942             vmx_basic_vmcs_revision_id(data))
2943                 return -EINVAL;
2944
2945         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2946                 return -EINVAL;
2947
2948         vmx->nested.nested_vmx_basic = data;
2949         return 0;
2950 }
2951
2952 static int
2953 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2954 {
2955         u64 supported;
2956         u32 *lowp, *highp;
2957
2958         switch (msr_index) {
2959         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2960                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2961                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2962                 break;
2963         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2964                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2965                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2966                 break;
2967         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2968                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2969                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2970                 break;
2971         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2972                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2973                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2974                 break;
2975         case MSR_IA32_VMX_PROCBASED_CTLS2:
2976                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2977                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2978                 break;
2979         default:
2980                 BUG();
2981         }
2982
2983         supported = vmx_control_msr(*lowp, *highp);
2984
2985         /* Check must-be-1 bits are still 1. */
2986         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2987                 return -EINVAL;
2988
2989         /* Check must-be-0 bits are still 0. */
2990         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2991                 return -EINVAL;
2992
2993         *lowp = data;
2994         *highp = data >> 32;
2995         return 0;
2996 }
2997
2998 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2999 {
3000         const u64 feature_and_reserved_bits =
3001                 /* feature */
3002                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3003                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3004                 /* reserved */
3005                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3006         u64 vmx_misc;
3007
3008         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3009                                    vmx->nested.nested_vmx_misc_high);
3010
3011         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3012                 return -EINVAL;
3013
3014         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3015              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3016             vmx_misc_preemption_timer_rate(data) !=
3017             vmx_misc_preemption_timer_rate(vmx_misc))
3018                 return -EINVAL;
3019
3020         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3021                 return -EINVAL;
3022
3023         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3024                 return -EINVAL;
3025
3026         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3027                 return -EINVAL;
3028
3029         vmx->nested.nested_vmx_misc_low = data;
3030         vmx->nested.nested_vmx_misc_high = data >> 32;
3031         return 0;
3032 }
3033
3034 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3035 {
3036         u64 vmx_ept_vpid_cap;
3037
3038         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3039                                            vmx->nested.nested_vmx_vpid_caps);
3040
3041         /* Every bit is either reserved or a feature bit. */
3042         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3043                 return -EINVAL;
3044
3045         vmx->nested.nested_vmx_ept_caps = data;
3046         vmx->nested.nested_vmx_vpid_caps = data >> 32;
3047         return 0;
3048 }
3049
3050 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3051 {
3052         u64 *msr;
3053
3054         switch (msr_index) {
3055         case MSR_IA32_VMX_CR0_FIXED0:
3056                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3057                 break;
3058         case MSR_IA32_VMX_CR4_FIXED0:
3059                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3060                 break;
3061         default:
3062                 BUG();
3063         }
3064
3065         /*
3066          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3067          * must be 1 in the restored value.
3068          */
3069         if (!is_bitwise_subset(data, *msr, -1ULL))
3070                 return -EINVAL;
3071
3072         *msr = data;
3073         return 0;
3074 }
3075
3076 /*
3077  * Called when userspace is restoring VMX MSRs.
3078  *
3079  * Returns 0 on success, non-0 otherwise.
3080  */
3081 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3082 {
3083         struct vcpu_vmx *vmx = to_vmx(vcpu);
3084
3085         switch (msr_index) {
3086         case MSR_IA32_VMX_BASIC:
3087                 return vmx_restore_vmx_basic(vmx, data);
3088         case MSR_IA32_VMX_PINBASED_CTLS:
3089         case MSR_IA32_VMX_PROCBASED_CTLS:
3090         case MSR_IA32_VMX_EXIT_CTLS:
3091         case MSR_IA32_VMX_ENTRY_CTLS:
3092                 /*
3093                  * The "non-true" VMX capability MSRs are generated from the
3094                  * "true" MSRs, so we do not support restoring them directly.
3095                  *
3096                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3097                  * should restore the "true" MSRs with the must-be-1 bits
3098                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3099                  * DEFAULT SETTINGS".
3100                  */
3101                 return -EINVAL;
3102         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3103         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3104         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3105         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3106         case MSR_IA32_VMX_PROCBASED_CTLS2:
3107                 return vmx_restore_control_msr(vmx, msr_index, data);
3108         case MSR_IA32_VMX_MISC:
3109                 return vmx_restore_vmx_misc(vmx, data);
3110         case MSR_IA32_VMX_CR0_FIXED0:
3111         case MSR_IA32_VMX_CR4_FIXED0:
3112                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3113         case MSR_IA32_VMX_CR0_FIXED1:
3114         case MSR_IA32_VMX_CR4_FIXED1:
3115                 /*
3116                  * These MSRs are generated based on the vCPU's CPUID, so we
3117                  * do not support restoring them directly.
3118                  */
3119                 return -EINVAL;
3120         case MSR_IA32_VMX_EPT_VPID_CAP:
3121                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3122         case MSR_IA32_VMX_VMCS_ENUM:
3123                 vmx->nested.nested_vmx_vmcs_enum = data;
3124                 return 0;
3125         default:
3126                 /*
3127                  * The rest of the VMX capability MSRs do not support restore.
3128                  */
3129                 return -EINVAL;
3130         }
3131 }
3132
3133 /* Returns 0 on success, non-0 otherwise. */
3134 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3135 {
3136         struct vcpu_vmx *vmx = to_vmx(vcpu);
3137
3138         switch (msr_index) {
3139         case MSR_IA32_VMX_BASIC:
3140                 *pdata = vmx->nested.nested_vmx_basic;
3141                 break;
3142         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3143         case MSR_IA32_VMX_PINBASED_CTLS:
3144                 *pdata = vmx_control_msr(
3145                         vmx->nested.nested_vmx_pinbased_ctls_low,
3146                         vmx->nested.nested_vmx_pinbased_ctls_high);
3147                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3148                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3149                 break;
3150         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3151         case MSR_IA32_VMX_PROCBASED_CTLS:
3152                 *pdata = vmx_control_msr(
3153                         vmx->nested.nested_vmx_procbased_ctls_low,
3154                         vmx->nested.nested_vmx_procbased_ctls_high);
3155                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3156                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3157                 break;
3158         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3159         case MSR_IA32_VMX_EXIT_CTLS:
3160                 *pdata = vmx_control_msr(
3161                         vmx->nested.nested_vmx_exit_ctls_low,
3162                         vmx->nested.nested_vmx_exit_ctls_high);
3163                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3164                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3165                 break;
3166         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3167         case MSR_IA32_VMX_ENTRY_CTLS:
3168                 *pdata = vmx_control_msr(
3169                         vmx->nested.nested_vmx_entry_ctls_low,
3170                         vmx->nested.nested_vmx_entry_ctls_high);
3171                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3172                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3173                 break;
3174         case MSR_IA32_VMX_MISC:
3175                 *pdata = vmx_control_msr(
3176                         vmx->nested.nested_vmx_misc_low,
3177                         vmx->nested.nested_vmx_misc_high);
3178                 break;
3179         case MSR_IA32_VMX_CR0_FIXED0:
3180                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3181                 break;
3182         case MSR_IA32_VMX_CR0_FIXED1:
3183                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3184                 break;
3185         case MSR_IA32_VMX_CR4_FIXED0:
3186                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3187                 break;
3188         case MSR_IA32_VMX_CR4_FIXED1:
3189                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3190                 break;
3191         case MSR_IA32_VMX_VMCS_ENUM:
3192                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3193                 break;
3194         case MSR_IA32_VMX_PROCBASED_CTLS2:
3195                 *pdata = vmx_control_msr(
3196                         vmx->nested.nested_vmx_secondary_ctls_low,
3197                         vmx->nested.nested_vmx_secondary_ctls_high);
3198                 break;
3199         case MSR_IA32_VMX_EPT_VPID_CAP:
3200                 *pdata = vmx->nested.nested_vmx_ept_caps |
3201                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3202                 break;
3203         default:
3204                 return 1;
3205         }
3206
3207         return 0;
3208 }
3209
3210 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3211                                                  uint64_t val)
3212 {
3213         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3214
3215         return !(val & ~valid_bits);
3216 }
3217
3218 /*
3219  * Reads an msr value (of 'msr_index') into 'pdata'.
3220  * Returns 0 on success, non-0 otherwise.
3221  * Assumes vcpu_load() was already called.
3222  */
3223 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3224 {
3225         struct shared_msr_entry *msr;
3226
3227         switch (msr_info->index) {
3228 #ifdef CONFIG_X86_64
3229         case MSR_FS_BASE:
3230                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3231                 break;
3232         case MSR_GS_BASE:
3233                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3234                 break;
3235         case MSR_KERNEL_GS_BASE:
3236                 vmx_load_host_state(to_vmx(vcpu));
3237                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3238                 break;
3239 #endif
3240         case MSR_EFER:
3241                 return kvm_get_msr_common(vcpu, msr_info);
3242         case MSR_IA32_TSC:
3243                 msr_info->data = guest_read_tsc(vcpu);
3244                 break;
3245         case MSR_IA32_SYSENTER_CS:
3246                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3247                 break;
3248         case MSR_IA32_SYSENTER_EIP:
3249                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3250                 break;
3251         case MSR_IA32_SYSENTER_ESP:
3252                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3253                 break;
3254         case MSR_IA32_BNDCFGS:
3255                 if (!kvm_mpx_supported())
3256                         return 1;
3257                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3258                 break;
3259         case MSR_IA32_MCG_EXT_CTL:
3260                 if (!msr_info->host_initiated &&
3261                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3262                       FEATURE_CONTROL_LMCE))
3263                         return 1;
3264                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3265                 break;
3266         case MSR_IA32_FEATURE_CONTROL:
3267                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3268                 break;
3269         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3270                 if (!nested_vmx_allowed(vcpu))
3271                         return 1;
3272                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3273         case MSR_IA32_XSS:
3274                 if (!vmx_xsaves_supported())
3275                         return 1;
3276                 msr_info->data = vcpu->arch.ia32_xss;
3277                 break;
3278         case MSR_TSC_AUX:
3279                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3280                         return 1;
3281                 /* Otherwise falls through */
3282         default:
3283                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3284                 if (msr) {
3285                         msr_info->data = msr->data;
3286                         break;
3287                 }
3288                 return kvm_get_msr_common(vcpu, msr_info);
3289         }
3290
3291         return 0;
3292 }
3293
3294 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3295
3296 /*
3297  * Writes msr value into into the appropriate "register".
3298  * Returns 0 on success, non-0 otherwise.
3299  * Assumes vcpu_load() was already called.
3300  */
3301 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3302 {
3303         struct vcpu_vmx *vmx = to_vmx(vcpu);
3304         struct shared_msr_entry *msr;
3305         int ret = 0;
3306         u32 msr_index = msr_info->index;
3307         u64 data = msr_info->data;
3308
3309         switch (msr_index) {
3310         case MSR_EFER:
3311                 ret = kvm_set_msr_common(vcpu, msr_info);
3312                 break;
3313 #ifdef CONFIG_X86_64
3314         case MSR_FS_BASE:
3315                 vmx_segment_cache_clear(vmx);
3316                 vmcs_writel(GUEST_FS_BASE, data);
3317                 break;
3318         case MSR_GS_BASE:
3319                 vmx_segment_cache_clear(vmx);
3320                 vmcs_writel(GUEST_GS_BASE, data);
3321                 break;
3322         case MSR_KERNEL_GS_BASE:
3323                 vmx_load_host_state(vmx);
3324                 vmx->msr_guest_kernel_gs_base = data;
3325                 break;
3326 #endif
3327         case MSR_IA32_SYSENTER_CS:
3328                 vmcs_write32(GUEST_SYSENTER_CS, data);
3329                 break;
3330         case MSR_IA32_SYSENTER_EIP:
3331                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3332                 break;
3333         case MSR_IA32_SYSENTER_ESP:
3334                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3335                 break;
3336         case MSR_IA32_BNDCFGS:
3337                 if (!kvm_mpx_supported())
3338                         return 1;
3339                 vmcs_write64(GUEST_BNDCFGS, data);
3340                 break;
3341         case MSR_IA32_TSC:
3342                 kvm_write_tsc(vcpu, msr_info);
3343                 break;
3344         case MSR_IA32_CR_PAT:
3345                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3346                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3347                                 return 1;
3348                         vmcs_write64(GUEST_IA32_PAT, data);
3349                         vcpu->arch.pat = data;
3350                         break;
3351                 }
3352                 ret = kvm_set_msr_common(vcpu, msr_info);
3353                 break;
3354         case MSR_IA32_TSC_ADJUST:
3355                 ret = kvm_set_msr_common(vcpu, msr_info);
3356                 break;
3357         case MSR_IA32_MCG_EXT_CTL:
3358                 if ((!msr_info->host_initiated &&
3359                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3360                        FEATURE_CONTROL_LMCE)) ||
3361                     (data & ~MCG_EXT_CTL_LMCE_EN))
3362                         return 1;
3363                 vcpu->arch.mcg_ext_ctl = data;
3364                 break;
3365         case MSR_IA32_FEATURE_CONTROL:
3366                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3367                     (to_vmx(vcpu)->msr_ia32_feature_control &
3368                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3369                         return 1;
3370                 vmx->msr_ia32_feature_control = data;
3371                 if (msr_info->host_initiated && data == 0)
3372                         vmx_leave_nested(vcpu);
3373                 break;
3374         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3375                 if (!msr_info->host_initiated)
3376                         return 1; /* they are read-only */
3377                 if (!nested_vmx_allowed(vcpu))
3378                         return 1;
3379                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3380         case MSR_IA32_XSS:
3381                 if (!vmx_xsaves_supported())
3382                         return 1;
3383                 /*
3384                  * The only supported bit as of Skylake is bit 8, but
3385                  * it is not supported on KVM.
3386                  */
3387                 if (data != 0)
3388                         return 1;
3389                 vcpu->arch.ia32_xss = data;
3390                 if (vcpu->arch.ia32_xss != host_xss)
3391                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3392                                 vcpu->arch.ia32_xss, host_xss);
3393                 else
3394                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3395                 break;
3396         case MSR_TSC_AUX:
3397                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3398                         return 1;
3399                 /* Check reserved bit, higher 32 bits should be zero */
3400                 if ((data >> 32) != 0)
3401                         return 1;
3402                 /* Otherwise falls through */
3403         default:
3404                 msr = find_msr_entry(vmx, msr_index);
3405                 if (msr) {
3406                         u64 old_msr_data = msr->data;
3407                         msr->data = data;
3408                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3409                                 preempt_disable();
3410                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3411                                                          msr->mask);
3412                                 preempt_enable();
3413                                 if (ret)
3414                                         msr->data = old_msr_data;
3415                         }
3416                         break;
3417                 }
3418                 ret = kvm_set_msr_common(vcpu, msr_info);
3419         }
3420
3421         return ret;
3422 }
3423
3424 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3425 {
3426         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3427         switch (reg) {
3428         case VCPU_REGS_RSP:
3429                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3430                 break;
3431         case VCPU_REGS_RIP:
3432                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3433                 break;
3434         case VCPU_EXREG_PDPTR:
3435                 if (enable_ept)
3436                         ept_save_pdptrs(vcpu);
3437                 break;
3438         default:
3439                 break;
3440         }
3441 }
3442
3443 static __init int cpu_has_kvm_support(void)
3444 {
3445         return cpu_has_vmx();
3446 }
3447
3448 static __init int vmx_disabled_by_bios(void)
3449 {
3450         u64 msr;
3451
3452         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3453         if (msr & FEATURE_CONTROL_LOCKED) {
3454                 /* launched w/ TXT and VMX disabled */
3455                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3456                         && tboot_enabled())
3457                         return 1;
3458                 /* launched w/o TXT and VMX only enabled w/ TXT */
3459                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3460                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3461                         && !tboot_enabled()) {
3462                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3463                                 "activate TXT before enabling KVM\n");
3464                         return 1;
3465                 }
3466                 /* launched w/o TXT and VMX disabled */
3467                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3468                         && !tboot_enabled())
3469                         return 1;
3470         }
3471
3472         return 0;
3473 }
3474
3475 static void kvm_cpu_vmxon(u64 addr)
3476 {
3477         intel_pt_handle_vmx(1);
3478
3479         asm volatile (ASM_VMX_VMXON_RAX
3480                         : : "a"(&addr), "m"(addr)
3481                         : "memory", "cc");
3482 }
3483
3484 static int hardware_enable(void)
3485 {
3486         int cpu = raw_smp_processor_id();
3487         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3488         u64 old, test_bits;
3489
3490         if (cr4_read_shadow() & X86_CR4_VMXE)
3491                 return -EBUSY;
3492
3493         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3494         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3495         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3496
3497         /*
3498          * Now we can enable the vmclear operation in kdump
3499          * since the loaded_vmcss_on_cpu list on this cpu
3500          * has been initialized.
3501          *
3502          * Though the cpu is not in VMX operation now, there
3503          * is no problem to enable the vmclear operation
3504          * for the loaded_vmcss_on_cpu list is empty!
3505          */
3506         crash_enable_local_vmclear(cpu);
3507
3508         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3509
3510         test_bits = FEATURE_CONTROL_LOCKED;
3511         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3512         if (tboot_enabled())
3513                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3514
3515         if ((old & test_bits) != test_bits) {
3516                 /* enable and lock */
3517                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3518         }
3519         cr4_set_bits(X86_CR4_VMXE);
3520
3521         if (vmm_exclusive) {
3522                 kvm_cpu_vmxon(phys_addr);
3523                 ept_sync_global();
3524         }
3525
3526         native_store_gdt(this_cpu_ptr(&host_gdt));
3527
3528         return 0;
3529 }
3530
3531 static void vmclear_local_loaded_vmcss(void)
3532 {
3533         int cpu = raw_smp_processor_id();
3534         struct loaded_vmcs *v, *n;
3535
3536         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3537                                  loaded_vmcss_on_cpu_link)
3538                 __loaded_vmcs_clear(v);
3539 }
3540
3541
3542 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3543  * tricks.
3544  */
3545 static void kvm_cpu_vmxoff(void)
3546 {
3547         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3548
3549         intel_pt_handle_vmx(0);
3550 }
3551
3552 static void hardware_disable(void)
3553 {
3554         if (vmm_exclusive) {
3555                 vmclear_local_loaded_vmcss();
3556                 kvm_cpu_vmxoff();
3557         }
3558         cr4_clear_bits(X86_CR4_VMXE);
3559 }
3560
3561 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3562                                       u32 msr, u32 *result)
3563 {
3564         u32 vmx_msr_low, vmx_msr_high;
3565         u32 ctl = ctl_min | ctl_opt;
3566
3567         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3568
3569         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3570         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3571
3572         /* Ensure minimum (required) set of control bits are supported. */
3573         if (ctl_min & ~ctl)
3574                 return -EIO;
3575
3576         *result = ctl;
3577         return 0;
3578 }
3579
3580 static __init bool allow_1_setting(u32 msr, u32 ctl)
3581 {
3582         u32 vmx_msr_low, vmx_msr_high;
3583
3584         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3585         return vmx_msr_high & ctl;
3586 }
3587
3588 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3589 {
3590         u32 vmx_msr_low, vmx_msr_high;
3591         u32 min, opt, min2, opt2;
3592         u32 _pin_based_exec_control = 0;
3593         u32 _cpu_based_exec_control = 0;
3594         u32 _cpu_based_2nd_exec_control = 0;
3595         u32 _vmexit_control = 0;
3596         u32 _vmentry_control = 0;
3597
3598         min = CPU_BASED_HLT_EXITING |
3599 #ifdef CONFIG_X86_64
3600               CPU_BASED_CR8_LOAD_EXITING |
3601               CPU_BASED_CR8_STORE_EXITING |
3602 #endif
3603               CPU_BASED_CR3_LOAD_EXITING |
3604               CPU_BASED_CR3_STORE_EXITING |
3605               CPU_BASED_USE_IO_BITMAPS |
3606               CPU_BASED_MOV_DR_EXITING |
3607               CPU_BASED_USE_TSC_OFFSETING |
3608               CPU_BASED_MWAIT_EXITING |
3609               CPU_BASED_MONITOR_EXITING |
3610               CPU_BASED_INVLPG_EXITING |
3611               CPU_BASED_RDPMC_EXITING;
3612
3613         opt = CPU_BASED_TPR_SHADOW |
3614               CPU_BASED_USE_MSR_BITMAPS |
3615               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3616         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3617                                 &_cpu_based_exec_control) < 0)
3618                 return -EIO;
3619 #ifdef CONFIG_X86_64
3620         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3621                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3622                                            ~CPU_BASED_CR8_STORE_EXITING;
3623 #endif
3624         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3625                 min2 = 0;
3626                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3627                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3628                         SECONDARY_EXEC_WBINVD_EXITING |
3629                         SECONDARY_EXEC_ENABLE_VPID |
3630                         SECONDARY_EXEC_ENABLE_EPT |
3631                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3632                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3633                         SECONDARY_EXEC_RDTSCP |
3634                         SECONDARY_EXEC_ENABLE_INVPCID |
3635                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3636                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3637                         SECONDARY_EXEC_SHADOW_VMCS |
3638                         SECONDARY_EXEC_XSAVES |
3639                         SECONDARY_EXEC_ENABLE_PML |
3640                         SECONDARY_EXEC_TSC_SCALING;
3641                 if (adjust_vmx_controls(min2, opt2,
3642                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3643                                         &_cpu_based_2nd_exec_control) < 0)
3644                         return -EIO;
3645         }
3646 #ifndef CONFIG_X86_64
3647         if (!(_cpu_based_2nd_exec_control &
3648                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3649                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3650 #endif
3651
3652         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3653                 _cpu_based_2nd_exec_control &= ~(
3654                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3655                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3656                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3657
3658         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3659                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3660                    enabled */
3661                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3662                                              CPU_BASED_CR3_STORE_EXITING |
3663                                              CPU_BASED_INVLPG_EXITING);
3664                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3665                       vmx_capability.ept, vmx_capability.vpid);
3666         }
3667
3668         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3669 #ifdef CONFIG_X86_64
3670         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3671 #endif
3672         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3673                 VM_EXIT_CLEAR_BNDCFGS;
3674         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3675                                 &_vmexit_control) < 0)
3676                 return -EIO;
3677
3678         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3679         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3680                  PIN_BASED_VMX_PREEMPTION_TIMER;
3681         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3682                                 &_pin_based_exec_control) < 0)
3683                 return -EIO;
3684
3685         if (cpu_has_broken_vmx_preemption_timer())
3686                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3687         if (!(_cpu_based_2nd_exec_control &
3688                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3689                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3690
3691         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3692         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3693         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3694                                 &_vmentry_control) < 0)
3695                 return -EIO;
3696
3697         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3698
3699         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3700         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3701                 return -EIO;
3702
3703 #ifdef CONFIG_X86_64
3704         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3705         if (vmx_msr_high & (1u<<16))
3706                 return -EIO;
3707 #endif
3708
3709         /* Require Write-Back (WB) memory type for VMCS accesses. */
3710         if (((vmx_msr_high >> 18) & 15) != 6)
3711                 return -EIO;
3712
3713         vmcs_conf->size = vmx_msr_high & 0x1fff;
3714         vmcs_conf->order = get_order(vmcs_conf->size);
3715         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3716         vmcs_conf->revision_id = vmx_msr_low;
3717
3718         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3719         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3720         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3721         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3722         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3723
3724         cpu_has_load_ia32_efer =
3725                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3726                                 VM_ENTRY_LOAD_IA32_EFER)
3727                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3728                                    VM_EXIT_LOAD_IA32_EFER);
3729
3730         cpu_has_load_perf_global_ctrl =
3731                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3732                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3733                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3734                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3735
3736         /*
3737          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3738          * but due to errata below it can't be used. Workaround is to use
3739          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3740          *
3741          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3742          *
3743          * AAK155             (model 26)
3744          * AAP115             (model 30)
3745          * AAT100             (model 37)
3746          * BC86,AAY89,BD102   (model 44)
3747          * BA97               (model 46)
3748          *
3749          */
3750         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3751                 switch (boot_cpu_data.x86_model) {
3752                 case 26:
3753                 case 30:
3754                 case 37:
3755                 case 44:
3756                 case 46:
3757                         cpu_has_load_perf_global_ctrl = false;
3758                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3759                                         "does not work properly. Using workaround\n");
3760                         break;
3761                 default:
3762                         break;
3763                 }
3764         }
3765
3766         if (boot_cpu_has(X86_FEATURE_XSAVES))
3767                 rdmsrl(MSR_IA32_XSS, host_xss);
3768
3769         return 0;
3770 }
3771
3772 static struct vmcs *alloc_vmcs_cpu(int cpu)
3773 {
3774         int node = cpu_to_node(cpu);
3775         struct page *pages;
3776         struct vmcs *vmcs;
3777
3778         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3779         if (!pages)
3780                 return NULL;
3781         vmcs = page_address(pages);
3782         memset(vmcs, 0, vmcs_config.size);
3783         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3784         return vmcs;
3785 }
3786
3787 static struct vmcs *alloc_vmcs(void)
3788 {
3789         return alloc_vmcs_cpu(raw_smp_processor_id());
3790 }
3791
3792 static void free_vmcs(struct vmcs *vmcs)
3793 {
3794         free_pages((unsigned long)vmcs, vmcs_config.order);
3795 }
3796
3797 /*
3798  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3799  */
3800 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3801 {
3802         if (!loaded_vmcs->vmcs)
3803                 return;
3804         loaded_vmcs_clear(loaded_vmcs);
3805         free_vmcs(loaded_vmcs->vmcs);
3806         loaded_vmcs->vmcs = NULL;
3807         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3808 }
3809
3810 static void free_kvm_area(void)
3811 {
3812         int cpu;
3813
3814         for_each_possible_cpu(cpu) {
3815                 free_vmcs(per_cpu(vmxarea, cpu));
3816                 per_cpu(vmxarea, cpu) = NULL;
3817         }
3818 }
3819
3820 static void init_vmcs_shadow_fields(void)
3821 {
3822         int i, j;
3823
3824         /* No checks for read only fields yet */
3825
3826         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3827                 switch (shadow_read_write_fields[i]) {
3828                 case GUEST_BNDCFGS:
3829                         if (!kvm_mpx_supported())
3830                                 continue;
3831                         break;
3832                 default:
3833                         break;
3834                 }
3835
3836                 if (j < i)
3837                         shadow_read_write_fields[j] =
3838                                 shadow_read_write_fields[i];
3839                 j++;
3840         }
3841         max_shadow_read_write_fields = j;
3842
3843         /* shadowed fields guest access without vmexit */
3844         for (i = 0; i < max_shadow_read_write_fields; i++) {
3845                 clear_bit(shadow_read_write_fields[i],
3846                           vmx_vmwrite_bitmap);
3847                 clear_bit(shadow_read_write_fields[i],
3848                           vmx_vmread_bitmap);
3849         }
3850         for (i = 0; i < max_shadow_read_only_fields; i++)
3851                 clear_bit(shadow_read_only_fields[i],
3852                           vmx_vmread_bitmap);
3853 }
3854
3855 static __init int alloc_kvm_area(void)
3856 {
3857         int cpu;
3858
3859         for_each_possible_cpu(cpu) {
3860                 struct vmcs *vmcs;
3861
3862                 vmcs = alloc_vmcs_cpu(cpu);
3863                 if (!vmcs) {
3864                         free_kvm_area();
3865                         return -ENOMEM;
3866                 }
3867
3868                 per_cpu(vmxarea, cpu) = vmcs;
3869         }
3870         return 0;
3871 }
3872
3873 static bool emulation_required(struct kvm_vcpu *vcpu)
3874 {
3875         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3876 }
3877
3878 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3879                 struct kvm_segment *save)
3880 {
3881         if (!emulate_invalid_guest_state) {
3882                 /*
3883                  * CS and SS RPL should be equal during guest entry according
3884                  * to VMX spec, but in reality it is not always so. Since vcpu
3885                  * is in the middle of the transition from real mode to
3886                  * protected mode it is safe to assume that RPL 0 is a good
3887                  * default value.
3888                  */
3889                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3890                         save->selector &= ~SEGMENT_RPL_MASK;
3891                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3892                 save->s = 1;
3893         }
3894         vmx_set_segment(vcpu, save, seg);
3895 }
3896
3897 static void enter_pmode(struct kvm_vcpu *vcpu)
3898 {
3899         unsigned long flags;
3900         struct vcpu_vmx *vmx = to_vmx(vcpu);
3901
3902         /*
3903          * Update real mode segment cache. It may be not up-to-date if sement
3904          * register was written while vcpu was in a guest mode.
3905          */
3906         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3907         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3908         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3909         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3910         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3911         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3912
3913         vmx->rmode.vm86_active = 0;
3914
3915         vmx_segment_cache_clear(vmx);
3916
3917         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3918
3919         flags = vmcs_readl(GUEST_RFLAGS);
3920         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3921         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3922         vmcs_writel(GUEST_RFLAGS, flags);
3923
3924         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3925                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3926
3927         update_exception_bitmap(vcpu);
3928
3929         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3930         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3931         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3932         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3933         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3934         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3935 }
3936
3937 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3938 {
3939         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3940         struct kvm_segment var = *save;
3941
3942         var.dpl = 0x3;
3943         if (seg == VCPU_SREG_CS)
3944                 var.type = 0x3;
3945
3946         if (!emulate_invalid_guest_state) {
3947                 var.selector = var.base >> 4;
3948                 var.base = var.base & 0xffff0;
3949                 var.limit = 0xffff;
3950                 var.g = 0;
3951                 var.db = 0;
3952                 var.present = 1;
3953                 var.s = 1;
3954                 var.l = 0;
3955                 var.unusable = 0;
3956                 var.type = 0x3;
3957                 var.avl = 0;
3958                 if (save->base & 0xf)
3959                         printk_once(KERN_WARNING "kvm: segment base is not "
3960                                         "paragraph aligned when entering "
3961                                         "protected mode (seg=%d)", seg);
3962         }
3963
3964         vmcs_write16(sf->selector, var.selector);
3965         vmcs_write32(sf->base, var.base);
3966         vmcs_write32(sf->limit, var.limit);
3967         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3968 }
3969
3970 static void enter_rmode(struct kvm_vcpu *vcpu)
3971 {
3972         unsigned long flags;
3973         struct vcpu_vmx *vmx = to_vmx(vcpu);
3974
3975         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3976         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3977         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3978         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3979         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3980         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3981         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3982
3983         vmx->rmode.vm86_active = 1;
3984
3985         /*
3986          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3987          * vcpu. Warn the user that an update is overdue.
3988          */
3989         if (!vcpu->kvm->arch.tss_addr)
3990                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3991                              "called before entering vcpu\n");
3992
3993         vmx_segment_cache_clear(vmx);
3994
3995         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3996         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3997         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3998
3999         flags = vmcs_readl(GUEST_RFLAGS);
4000         vmx->rmode.save_rflags = flags;
4001
4002         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4003
4004         vmcs_writel(GUEST_RFLAGS, flags);
4005         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4006         update_exception_bitmap(vcpu);
4007
4008         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4009         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4010         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4011         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4012         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4013         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4014
4015         kvm_mmu_reset_context(vcpu);
4016 }
4017
4018 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4019 {
4020         struct vcpu_vmx *vmx = to_vmx(vcpu);
4021         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4022
4023         if (!msr)
4024                 return;
4025
4026         /*
4027          * Force kernel_gs_base reloading before EFER changes, as control
4028          * of this msr depends on is_long_mode().
4029          */
4030         vmx_load_host_state(to_vmx(vcpu));
4031         vcpu->arch.efer = efer;
4032         if (efer & EFER_LMA) {
4033                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4034                 msr->data = efer;
4035         } else {
4036                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4037
4038                 msr->data = efer & ~EFER_LME;
4039         }
4040         setup_msrs(vmx);
4041 }
4042
4043 #ifdef CONFIG_X86_64
4044
4045 static void enter_lmode(struct kvm_vcpu *vcpu)
4046 {
4047         u32 guest_tr_ar;
4048
4049         vmx_segment_cache_clear(to_vmx(vcpu));
4050
4051         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4052         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4053                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4054                                      __func__);
4055                 vmcs_write32(GUEST_TR_AR_BYTES,
4056                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4057                              | VMX_AR_TYPE_BUSY_64_TSS);
4058         }
4059         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4060 }
4061
4062 static void exit_lmode(struct kvm_vcpu *vcpu)
4063 {
4064         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4065         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4066 }
4067
4068 #endif
4069
4070 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4071 {
4072         vpid_sync_context(vpid);
4073         if (enable_ept) {
4074                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4075                         return;
4076                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
4077         }
4078 }
4079
4080 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4081 {
4082         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4083 }
4084
4085 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4086 {
4087         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4088
4089         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4090         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4091 }
4092
4093 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4094 {
4095         if (enable_ept && is_paging(vcpu))
4096                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4097         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4098 }
4099
4100 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4101 {
4102         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4103
4104         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4105         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4106 }
4107
4108 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4109 {
4110         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4111
4112         if (!test_bit(VCPU_EXREG_PDPTR,
4113                       (unsigned long *)&vcpu->arch.regs_dirty))
4114                 return;
4115
4116         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4117                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4118                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4119                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4120                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4121         }
4122 }
4123
4124 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4125 {
4126         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4127
4128         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4129                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4130                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4131                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4132                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4133         }
4134
4135         __set_bit(VCPU_EXREG_PDPTR,
4136                   (unsigned long *)&vcpu->arch.regs_avail);
4137         __set_bit(VCPU_EXREG_PDPTR,
4138                   (unsigned long *)&vcpu->arch.regs_dirty);
4139 }
4140
4141 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4142 {
4143         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4144         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4145         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4146
4147         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4148                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4149             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4150                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4151
4152         return fixed_bits_valid(val, fixed0, fixed1);
4153 }
4154
4155 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4156 {
4157         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4158         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4159
4160         return fixed_bits_valid(val, fixed0, fixed1);
4161 }
4162
4163 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4164 {
4165         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4166         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4167
4168         return fixed_bits_valid(val, fixed0, fixed1);
4169 }
4170
4171 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4172 #define nested_guest_cr4_valid  nested_cr4_valid
4173 #define nested_host_cr4_valid   nested_cr4_valid
4174
4175 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4176
4177 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4178                                         unsigned long cr0,
4179                                         struct kvm_vcpu *vcpu)
4180 {
4181         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4182                 vmx_decache_cr3(vcpu);
4183         if (!(cr0 & X86_CR0_PG)) {
4184                 /* From paging/starting to nonpaging */
4185                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4186                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4187                              (CPU_BASED_CR3_LOAD_EXITING |
4188                               CPU_BASED_CR3_STORE_EXITING));
4189                 vcpu->arch.cr0 = cr0;
4190                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4191         } else if (!is_paging(vcpu)) {
4192                 /* From nonpaging to paging */
4193                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4194                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4195                              ~(CPU_BASED_CR3_LOAD_EXITING |
4196                                CPU_BASED_CR3_STORE_EXITING));
4197                 vcpu->arch.cr0 = cr0;
4198                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4199         }
4200
4201         if (!(cr0 & X86_CR0_WP))
4202                 *hw_cr0 &= ~X86_CR0_WP;
4203 }
4204
4205 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4206 {
4207         struct vcpu_vmx *vmx = to_vmx(vcpu);
4208         unsigned long hw_cr0;
4209
4210         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4211         if (enable_unrestricted_guest)
4212                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4213         else {
4214                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4215
4216                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4217                         enter_pmode(vcpu);
4218
4219                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4220                         enter_rmode(vcpu);
4221         }
4222
4223 #ifdef CONFIG_X86_64
4224         if (vcpu->arch.efer & EFER_LME) {
4225                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4226                         enter_lmode(vcpu);
4227                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4228                         exit_lmode(vcpu);
4229         }
4230 #endif
4231
4232         if (enable_ept)
4233                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4234
4235         if (!vcpu->fpu_active)
4236                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
4237
4238         vmcs_writel(CR0_READ_SHADOW, cr0);
4239         vmcs_writel(GUEST_CR0, hw_cr0);
4240         vcpu->arch.cr0 = cr0;
4241
4242         /* depends on vcpu->arch.cr0 to be set to a new value */
4243         vmx->emulation_required = emulation_required(vcpu);
4244 }
4245
4246 static u64 construct_eptp(unsigned long root_hpa)
4247 {
4248         u64 eptp;
4249
4250         /* TODO write the value reading from MSR */
4251         eptp = VMX_EPT_DEFAULT_MT |
4252                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4253         if (enable_ept_ad_bits)
4254                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4255         eptp |= (root_hpa & PAGE_MASK);
4256
4257         return eptp;
4258 }
4259
4260 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4261 {
4262         unsigned long guest_cr3;
4263         u64 eptp;
4264
4265         guest_cr3 = cr3;
4266         if (enable_ept) {
4267                 eptp = construct_eptp(cr3);
4268                 vmcs_write64(EPT_POINTER, eptp);
4269                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4270                         guest_cr3 = kvm_read_cr3(vcpu);
4271                 else
4272                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4273                 ept_load_pdptrs(vcpu);
4274         }
4275
4276         vmx_flush_tlb(vcpu);
4277         vmcs_writel(GUEST_CR3, guest_cr3);
4278 }
4279
4280 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4281 {
4282         /*
4283          * Pass through host's Machine Check Enable value to hw_cr4, which
4284          * is in force while we are in guest mode.  Do not let guests control
4285          * this bit, even if host CR4.MCE == 0.
4286          */
4287         unsigned long hw_cr4 =
4288                 (cr4_read_shadow() & X86_CR4_MCE) |
4289                 (cr4 & ~X86_CR4_MCE) |
4290                 (to_vmx(vcpu)->rmode.vm86_active ?
4291                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4292
4293         if (cr4 & X86_CR4_VMXE) {
4294                 /*
4295                  * To use VMXON (and later other VMX instructions), a guest
4296                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4297                  * So basically the check on whether to allow nested VMX
4298                  * is here.
4299                  */
4300                 if (!nested_vmx_allowed(vcpu))
4301                         return 1;
4302         }
4303
4304         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4305                 return 1;
4306
4307         vcpu->arch.cr4 = cr4;
4308         if (enable_ept) {
4309                 if (!is_paging(vcpu)) {
4310                         hw_cr4 &= ~X86_CR4_PAE;
4311                         hw_cr4 |= X86_CR4_PSE;
4312                 } else if (!(cr4 & X86_CR4_PAE)) {
4313                         hw_cr4 &= ~X86_CR4_PAE;
4314                 }
4315         }
4316
4317         if (!enable_unrestricted_guest && !is_paging(vcpu))
4318                 /*
4319                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4320                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4321                  * to be manually disabled when guest switches to non-paging
4322                  * mode.
4323                  *
4324                  * If !enable_unrestricted_guest, the CPU is always running
4325                  * with CR0.PG=1 and CR4 needs to be modified.
4326                  * If enable_unrestricted_guest, the CPU automatically
4327                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4328                  */
4329                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4330
4331         vmcs_writel(CR4_READ_SHADOW, cr4);
4332         vmcs_writel(GUEST_CR4, hw_cr4);
4333         return 0;
4334 }
4335
4336 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4337                             struct kvm_segment *var, int seg)
4338 {
4339         struct vcpu_vmx *vmx = to_vmx(vcpu);
4340         u32 ar;
4341
4342         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4343                 *var = vmx->rmode.segs[seg];
4344                 if (seg == VCPU_SREG_TR
4345                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4346                         return;
4347                 var->base = vmx_read_guest_seg_base(vmx, seg);
4348                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4349                 return;
4350         }
4351         var->base = vmx_read_guest_seg_base(vmx, seg);
4352         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4353         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4354         ar = vmx_read_guest_seg_ar(vmx, seg);
4355         var->unusable = (ar >> 16) & 1;
4356         var->type = ar & 15;
4357         var->s = (ar >> 4) & 1;
4358         var->dpl = (ar >> 5) & 3;
4359         /*
4360          * Some userspaces do not preserve unusable property. Since usable
4361          * segment has to be present according to VMX spec we can use present
4362          * property to amend userspace bug by making unusable segment always
4363          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4364          * segment as unusable.
4365          */
4366         var->present = !var->unusable;
4367         var->avl = (ar >> 12) & 1;
4368         var->l = (ar >> 13) & 1;
4369         var->db = (ar >> 14) & 1;
4370         var->g = (ar >> 15) & 1;
4371 }
4372
4373 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4374 {
4375         struct kvm_segment s;
4376
4377         if (to_vmx(vcpu)->rmode.vm86_active) {
4378                 vmx_get_segment(vcpu, &s, seg);
4379                 return s.base;
4380         }
4381         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4382 }
4383
4384 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4385 {
4386         struct vcpu_vmx *vmx = to_vmx(vcpu);
4387
4388         if (unlikely(vmx->rmode.vm86_active))
4389                 return 0;
4390         else {
4391                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4392                 return VMX_AR_DPL(ar);
4393         }
4394 }
4395
4396 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4397 {
4398         u32 ar;
4399
4400         if (var->unusable || !var->present)
4401                 ar = 1 << 16;
4402         else {
4403                 ar = var->type & 15;
4404                 ar |= (var->s & 1) << 4;
4405                 ar |= (var->dpl & 3) << 5;
4406                 ar |= (var->present & 1) << 7;
4407                 ar |= (var->avl & 1) << 12;
4408                 ar |= (var->l & 1) << 13;
4409                 ar |= (var->db & 1) << 14;
4410                 ar |= (var->g & 1) << 15;
4411         }
4412
4413         return ar;
4414 }
4415
4416 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4417                             struct kvm_segment *var, int seg)
4418 {
4419         struct vcpu_vmx *vmx = to_vmx(vcpu);
4420         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4421
4422         vmx_segment_cache_clear(vmx);
4423
4424         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4425                 vmx->rmode.segs[seg] = *var;
4426                 if (seg == VCPU_SREG_TR)
4427                         vmcs_write16(sf->selector, var->selector);
4428                 else if (var->s)
4429                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4430                 goto out;
4431         }
4432
4433         vmcs_writel(sf->base, var->base);
4434         vmcs_write32(sf->limit, var->limit);
4435         vmcs_write16(sf->selector, var->selector);
4436
4437         /*
4438          *   Fix the "Accessed" bit in AR field of segment registers for older
4439          * qemu binaries.
4440          *   IA32 arch specifies that at the time of processor reset the
4441          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4442          * is setting it to 0 in the userland code. This causes invalid guest
4443          * state vmexit when "unrestricted guest" mode is turned on.
4444          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4445          * tree. Newer qemu binaries with that qemu fix would not need this
4446          * kvm hack.
4447          */
4448         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4449                 var->type |= 0x1; /* Accessed */
4450
4451         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4452
4453 out:
4454         vmx->emulation_required = emulation_required(vcpu);
4455 }
4456
4457 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4458 {
4459         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4460
4461         *db = (ar >> 14) & 1;
4462         *l = (ar >> 13) & 1;
4463 }
4464
4465 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4466 {
4467         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4468         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4469 }
4470
4471 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4472 {
4473         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4474         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4475 }
4476
4477 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4478 {
4479         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4480         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4481 }
4482
4483 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4484 {
4485         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4486         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4487 }
4488
4489 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4490 {
4491         struct kvm_segment var;
4492         u32 ar;
4493
4494         vmx_get_segment(vcpu, &var, seg);
4495         var.dpl = 0x3;
4496         if (seg == VCPU_SREG_CS)
4497                 var.type = 0x3;
4498         ar = vmx_segment_access_rights(&var);
4499
4500         if (var.base != (var.selector << 4))
4501                 return false;
4502         if (var.limit != 0xffff)
4503                 return false;
4504         if (ar != 0xf3)
4505                 return false;
4506
4507         return true;
4508 }
4509
4510 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4511 {
4512         struct kvm_segment cs;
4513         unsigned int cs_rpl;
4514
4515         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4516         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4517
4518         if (cs.unusable)
4519                 return false;
4520         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4521                 return false;
4522         if (!cs.s)
4523                 return false;
4524         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4525                 if (cs.dpl > cs_rpl)
4526                         return false;
4527         } else {
4528                 if (cs.dpl != cs_rpl)
4529                         return false;
4530         }
4531         if (!cs.present)
4532                 return false;
4533
4534         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4535         return true;
4536 }
4537
4538 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4539 {
4540         struct kvm_segment ss;
4541         unsigned int ss_rpl;
4542
4543         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4544         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4545
4546         if (ss.unusable)
4547                 return true;
4548         if (ss.type != 3 && ss.type != 7)
4549                 return false;
4550         if (!ss.s)
4551                 return false;
4552         if (ss.dpl != ss_rpl) /* DPL != RPL */
4553                 return false;
4554         if (!ss.present)
4555                 return false;
4556
4557         return true;
4558 }
4559
4560 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4561 {
4562         struct kvm_segment var;
4563         unsigned int rpl;
4564
4565         vmx_get_segment(vcpu, &var, seg);
4566         rpl = var.selector & SEGMENT_RPL_MASK;
4567
4568         if (var.unusable)
4569                 return true;
4570         if (!var.s)
4571                 return false;
4572         if (!var.present)
4573                 return false;
4574         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4575                 if (var.dpl < rpl) /* DPL < RPL */
4576                         return false;
4577         }
4578
4579         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4580          * rights flags
4581          */
4582         return true;
4583 }
4584
4585 static bool tr_valid(struct kvm_vcpu *vcpu)
4586 {
4587         struct kvm_segment tr;
4588
4589         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4590
4591         if (tr.unusable)
4592                 return false;
4593         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4594                 return false;
4595         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4596                 return false;
4597         if (!tr.present)
4598                 return false;
4599
4600         return true;
4601 }
4602
4603 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4604 {
4605         struct kvm_segment ldtr;
4606
4607         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4608
4609         if (ldtr.unusable)
4610                 return true;
4611         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4612                 return false;
4613         if (ldtr.type != 2)
4614                 return false;
4615         if (!ldtr.present)
4616                 return false;
4617
4618         return true;
4619 }
4620
4621 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4622 {
4623         struct kvm_segment cs, ss;
4624
4625         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4626         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4627
4628         return ((cs.selector & SEGMENT_RPL_MASK) ==
4629                  (ss.selector & SEGMENT_RPL_MASK));
4630 }
4631
4632 /*
4633  * Check if guest state is valid. Returns true if valid, false if
4634  * not.
4635  * We assume that registers are always usable
4636  */
4637 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4638 {
4639         if (enable_unrestricted_guest)
4640                 return true;
4641
4642         /* real mode guest state checks */
4643         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4644                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4645                         return false;
4646                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4647                         return false;
4648                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4649                         return false;
4650                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4651                         return false;
4652                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4653                         return false;
4654                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4655                         return false;
4656         } else {
4657         /* protected mode guest state checks */
4658                 if (!cs_ss_rpl_check(vcpu))
4659                         return false;
4660                 if (!code_segment_valid(vcpu))
4661                         return false;
4662                 if (!stack_segment_valid(vcpu))
4663                         return false;
4664                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4665                         return false;
4666                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4667                         return false;
4668                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4669                         return false;
4670                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4671                         return false;
4672                 if (!tr_valid(vcpu))
4673                         return false;
4674                 if (!ldtr_valid(vcpu))
4675                         return false;
4676         }
4677         /* TODO:
4678          * - Add checks on RIP
4679          * - Add checks on RFLAGS
4680          */
4681
4682         return true;
4683 }
4684
4685 static int init_rmode_tss(struct kvm *kvm)
4686 {
4687         gfn_t fn;
4688         u16 data = 0;
4689         int idx, r;
4690
4691         idx = srcu_read_lock(&kvm->srcu);
4692         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4693         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4694         if (r < 0)
4695                 goto out;
4696         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4697         r = kvm_write_guest_page(kvm, fn++, &data,
4698                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4699         if (r < 0)
4700                 goto out;
4701         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4702         if (r < 0)
4703                 goto out;
4704         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4705         if (r < 0)
4706                 goto out;
4707         data = ~0;
4708         r = kvm_write_guest_page(kvm, fn, &data,
4709                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4710                                  sizeof(u8));
4711 out:
4712         srcu_read_unlock(&kvm->srcu, idx);
4713         return r;
4714 }
4715
4716 static int init_rmode_identity_map(struct kvm *kvm)
4717 {
4718         int i, idx, r = 0;
4719         kvm_pfn_t identity_map_pfn;
4720         u32 tmp;
4721
4722         if (!enable_ept)
4723                 return 0;
4724
4725         /* Protect kvm->arch.ept_identity_pagetable_done. */
4726         mutex_lock(&kvm->slots_lock);
4727
4728         if (likely(kvm->arch.ept_identity_pagetable_done))
4729                 goto out2;
4730
4731         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4732
4733         r = alloc_identity_pagetable(kvm);
4734         if (r < 0)
4735                 goto out2;
4736
4737         idx = srcu_read_lock(&kvm->srcu);
4738         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4739         if (r < 0)
4740                 goto out;
4741         /* Set up identity-mapping pagetable for EPT in real mode */
4742         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4743                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4744                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4745                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4746                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4747                 if (r < 0)
4748                         goto out;
4749         }
4750         kvm->arch.ept_identity_pagetable_done = true;
4751
4752 out:
4753         srcu_read_unlock(&kvm->srcu, idx);
4754
4755 out2:
4756         mutex_unlock(&kvm->slots_lock);
4757         return r;
4758 }
4759
4760 static void seg_setup(int seg)
4761 {
4762         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4763         unsigned int ar;
4764
4765         vmcs_write16(sf->selector, 0);
4766         vmcs_writel(sf->base, 0);
4767         vmcs_write32(sf->limit, 0xffff);
4768         ar = 0x93;
4769         if (seg == VCPU_SREG_CS)
4770                 ar |= 0x08; /* code segment */
4771
4772         vmcs_write32(sf->ar_bytes, ar);
4773 }
4774
4775 static int alloc_apic_access_page(struct kvm *kvm)
4776 {
4777         struct page *page;
4778         int r = 0;
4779
4780         mutex_lock(&kvm->slots_lock);
4781         if (kvm->arch.apic_access_page_done)
4782                 goto out;
4783         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4784                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4785         if (r)
4786                 goto out;
4787
4788         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4789         if (is_error_page(page)) {
4790                 r = -EFAULT;
4791                 goto out;
4792         }
4793
4794         /*
4795          * Do not pin the page in memory, so that memory hot-unplug
4796          * is able to migrate it.
4797          */
4798         put_page(page);
4799         kvm->arch.apic_access_page_done = true;
4800 out:
4801         mutex_unlock(&kvm->slots_lock);
4802         return r;
4803 }
4804
4805 static int alloc_identity_pagetable(struct kvm *kvm)
4806 {
4807         /* Called with kvm->slots_lock held. */
4808
4809         int r = 0;
4810
4811         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4812
4813         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4814                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4815
4816         return r;
4817 }
4818
4819 static int allocate_vpid(void)
4820 {
4821         int vpid;
4822
4823         if (!enable_vpid)
4824                 return 0;
4825         spin_lock(&vmx_vpid_lock);
4826         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4827         if (vpid < VMX_NR_VPIDS)
4828                 __set_bit(vpid, vmx_vpid_bitmap);
4829         else
4830                 vpid = 0;
4831         spin_unlock(&vmx_vpid_lock);
4832         return vpid;
4833 }
4834
4835 static void free_vpid(int vpid)
4836 {
4837         if (!enable_vpid || vpid == 0)
4838                 return;
4839         spin_lock(&vmx_vpid_lock);
4840         __clear_bit(vpid, vmx_vpid_bitmap);
4841         spin_unlock(&vmx_vpid_lock);
4842 }
4843
4844 #define MSR_TYPE_R      1
4845 #define MSR_TYPE_W      2
4846 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4847                                                 u32 msr, int type)
4848 {
4849         int f = sizeof(unsigned long);
4850
4851         if (!cpu_has_vmx_msr_bitmap())
4852                 return;
4853
4854         /*
4855          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4856          * have the write-low and read-high bitmap offsets the wrong way round.
4857          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4858          */
4859         if (msr <= 0x1fff) {
4860                 if (type & MSR_TYPE_R)
4861                         /* read-low */
4862                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4863
4864                 if (type & MSR_TYPE_W)
4865                         /* write-low */
4866                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4867
4868         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4869                 msr &= 0x1fff;
4870                 if (type & MSR_TYPE_R)
4871                         /* read-high */
4872                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4873
4874                 if (type & MSR_TYPE_W)
4875                         /* write-high */
4876                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4877
4878         }
4879 }
4880
4881 /*
4882  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4883  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4884  */
4885 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4886                                                unsigned long *msr_bitmap_nested,
4887                                                u32 msr, int type)
4888 {
4889         int f = sizeof(unsigned long);
4890
4891         if (!cpu_has_vmx_msr_bitmap()) {
4892                 WARN_ON(1);
4893                 return;
4894         }
4895
4896         /*
4897          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4898          * have the write-low and read-high bitmap offsets the wrong way round.
4899          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4900          */
4901         if (msr <= 0x1fff) {
4902                 if (type & MSR_TYPE_R &&
4903                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4904                         /* read-low */
4905                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4906
4907                 if (type & MSR_TYPE_W &&
4908                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4909                         /* write-low */
4910                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4911
4912         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4913                 msr &= 0x1fff;
4914                 if (type & MSR_TYPE_R &&
4915                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4916                         /* read-high */
4917                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4918
4919                 if (type & MSR_TYPE_W &&
4920                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4921                         /* write-high */
4922                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4923
4924         }
4925 }
4926
4927 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4928 {
4929         if (!longmode_only)
4930                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4931                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4932         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4933                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4934 }
4935
4936 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4937 {
4938         if (apicv_active) {
4939                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4940                                 msr, type);
4941                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4942                                 msr, type);
4943         } else {
4944                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4945                                 msr, type);
4946                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4947                                 msr, type);
4948         }
4949 }
4950
4951 static bool vmx_get_enable_apicv(void)
4952 {
4953         return enable_apicv;
4954 }
4955
4956 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4957 {
4958         struct vcpu_vmx *vmx = to_vmx(vcpu);
4959         int max_irr;
4960         void *vapic_page;
4961         u16 status;
4962
4963         if (vmx->nested.pi_desc &&
4964             vmx->nested.pi_pending) {
4965                 vmx->nested.pi_pending = false;
4966                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4967                         return;
4968
4969                 max_irr = find_last_bit(
4970                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4971
4972                 if (max_irr == 256)
4973                         return;
4974
4975                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4976                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4977                 kunmap(vmx->nested.virtual_apic_page);
4978
4979                 status = vmcs_read16(GUEST_INTR_STATUS);
4980                 if ((u8)max_irr > ((u8)status & 0xff)) {
4981                         status &= ~0xff;
4982                         status |= (u8)max_irr;
4983                         vmcs_write16(GUEST_INTR_STATUS, status);
4984                 }
4985         }
4986 }
4987
4988 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4989 {
4990 #ifdef CONFIG_SMP
4991         if (vcpu->mode == IN_GUEST_MODE) {
4992                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4993
4994                 /*
4995                  * Currently, we don't support urgent interrupt,
4996                  * all interrupts are recognized as non-urgent
4997                  * interrupt, so we cannot post interrupts when
4998                  * 'SN' is set.
4999                  *
5000                  * If the vcpu is in guest mode, it means it is
5001                  * running instead of being scheduled out and
5002                  * waiting in the run queue, and that's the only
5003                  * case when 'SN' is set currently, warning if
5004                  * 'SN' is set.
5005                  */
5006                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
5007
5008                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
5009                                 POSTED_INTR_VECTOR);
5010                 return true;
5011         }
5012 #endif
5013         return false;
5014 }
5015
5016 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5017                                                 int vector)
5018 {
5019         struct vcpu_vmx *vmx = to_vmx(vcpu);
5020
5021         if (is_guest_mode(vcpu) &&
5022             vector == vmx->nested.posted_intr_nv) {
5023                 /* the PIR and ON have been set by L1. */
5024                 kvm_vcpu_trigger_posted_interrupt(vcpu);
5025                 /*
5026                  * If a posted intr is not recognized by hardware,
5027                  * we will accomplish it in the next vmentry.
5028                  */
5029                 vmx->nested.pi_pending = true;
5030                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5031                 return 0;
5032         }
5033         return -1;
5034 }
5035 /*
5036  * Send interrupt to vcpu via posted interrupt way.
5037  * 1. If target vcpu is running(non-root mode), send posted interrupt
5038  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5039  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5040  * interrupt from PIR in next vmentry.
5041  */
5042 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5043 {
5044         struct vcpu_vmx *vmx = to_vmx(vcpu);
5045         int r;
5046
5047         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5048         if (!r)
5049                 return;
5050
5051         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5052                 return;
5053
5054         /* If a previous notification has sent the IPI, nothing to do.  */
5055         if (pi_test_and_set_on(&vmx->pi_desc))
5056                 return;
5057
5058         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5059                 kvm_vcpu_kick(vcpu);
5060 }
5061
5062 /*
5063  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5064  * will not change in the lifetime of the guest.
5065  * Note that host-state that does change is set elsewhere. E.g., host-state
5066  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5067  */
5068 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5069 {
5070         u32 low32, high32;
5071         unsigned long tmpl;
5072         struct desc_ptr dt;
5073         unsigned long cr0, cr4;
5074
5075         cr0 = read_cr0();
5076         WARN_ON(cr0 & X86_CR0_TS);
5077         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5078         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
5079
5080         /* Save the most likely value for this task's CR4 in the VMCS. */
5081         cr4 = cr4_read_shadow();
5082         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5083         vmx->host_state.vmcs_host_cr4 = cr4;
5084
5085         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5086 #ifdef CONFIG_X86_64
5087         /*
5088          * Load null selectors, so we can avoid reloading them in
5089          * __vmx_load_host_state(), in case userspace uses the null selectors
5090          * too (the expected case).
5091          */
5092         vmcs_write16(HOST_DS_SELECTOR, 0);
5093         vmcs_write16(HOST_ES_SELECTOR, 0);
5094 #else
5095         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5096         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5097 #endif
5098         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5099         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5100
5101         native_store_idt(&dt);
5102         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5103         vmx->host_idt_base = dt.address;
5104
5105         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5106
5107         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5108         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5109         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5110         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5111
5112         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5113                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5114                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5115         }
5116 }
5117
5118 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5119 {
5120         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5121         if (enable_ept)
5122                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5123         if (is_guest_mode(&vmx->vcpu))
5124                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5125                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5126         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5127 }
5128
5129 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5130 {
5131         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5132
5133         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5134                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5135         /* Enable the preemption timer dynamically */
5136         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5137         return pin_based_exec_ctrl;
5138 }
5139
5140 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5141 {
5142         struct vcpu_vmx *vmx = to_vmx(vcpu);
5143
5144         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5145         if (cpu_has_secondary_exec_ctrls()) {
5146                 if (kvm_vcpu_apicv_active(vcpu))
5147                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5148                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5149                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5150                 else
5151                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5152                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5153                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5154         }
5155
5156         if (cpu_has_vmx_msr_bitmap())
5157                 vmx_set_msr_bitmap(vcpu);
5158 }
5159
5160 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5161 {
5162         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5163
5164         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5165                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5166
5167         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5168                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5169 #ifdef CONFIG_X86_64
5170                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5171                                 CPU_BASED_CR8_LOAD_EXITING;
5172 #endif
5173         }
5174         if (!enable_ept)
5175                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5176                                 CPU_BASED_CR3_LOAD_EXITING  |
5177                                 CPU_BASED_INVLPG_EXITING;
5178         return exec_control;
5179 }
5180
5181 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5182 {
5183         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5184         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5185                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5186         if (vmx->vpid == 0)
5187                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5188         if (!enable_ept) {
5189                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5190                 enable_unrestricted_guest = 0;
5191                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5192                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5193         }
5194         if (!enable_unrestricted_guest)
5195                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5196         if (!ple_gap)
5197                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5198         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5199                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5200                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5201         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5202         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5203            (handle_vmptrld).
5204            We can NOT enable shadow_vmcs here because we don't have yet
5205            a current VMCS12
5206         */
5207         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5208
5209         if (!enable_pml)
5210                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5211
5212         return exec_control;
5213 }
5214
5215 static void ept_set_mmio_spte_mask(void)
5216 {
5217         /*
5218          * EPT Misconfigurations can be generated if the value of bits 2:0
5219          * of an EPT paging-structure entry is 110b (write/execute).
5220          */
5221         kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5222 }
5223
5224 #define VMX_XSS_EXIT_BITMAP 0
5225 /*
5226  * Sets up the vmcs for emulated real mode.
5227  */
5228 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5229 {
5230 #ifdef CONFIG_X86_64
5231         unsigned long a;
5232 #endif
5233         int i;
5234
5235         /* I/O */
5236         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5237         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5238
5239         if (enable_shadow_vmcs) {
5240                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5241                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5242         }
5243         if (cpu_has_vmx_msr_bitmap())
5244                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5245
5246         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5247
5248         /* Control */
5249         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5250         vmx->hv_deadline_tsc = -1;
5251
5252         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5253
5254         if (cpu_has_secondary_exec_ctrls()) {
5255                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5256                                 vmx_secondary_exec_control(vmx));
5257         }
5258
5259         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5260                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5261                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5262                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5263                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5264
5265                 vmcs_write16(GUEST_INTR_STATUS, 0);
5266
5267                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5268                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5269         }
5270
5271         if (ple_gap) {
5272                 vmcs_write32(PLE_GAP, ple_gap);
5273                 vmx->ple_window = ple_window;
5274                 vmx->ple_window_dirty = true;
5275         }
5276
5277         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5278         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5279         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5280
5281         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5282         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5283         vmx_set_constant_host_state(vmx);
5284 #ifdef CONFIG_X86_64
5285         rdmsrl(MSR_FS_BASE, a);
5286         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5287         rdmsrl(MSR_GS_BASE, a);
5288         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5289 #else
5290         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5291         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5292 #endif
5293
5294         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5295         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5296         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5297         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5298         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5299
5300         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5301                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5302
5303         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5304                 u32 index = vmx_msr_index[i];
5305                 u32 data_low, data_high;
5306                 int j = vmx->nmsrs;
5307
5308                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5309                         continue;
5310                 if (wrmsr_safe(index, data_low, data_high) < 0)
5311                         continue;
5312                 vmx->guest_msrs[j].index = i;
5313                 vmx->guest_msrs[j].data = 0;
5314                 vmx->guest_msrs[j].mask = -1ull;
5315                 ++vmx->nmsrs;
5316         }
5317
5318
5319         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5320
5321         /* 22.2.1, 20.8.1 */
5322         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5323
5324         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
5325         set_cr4_guest_host_mask(vmx);
5326
5327         if (vmx_xsaves_supported())
5328                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5329
5330         if (enable_pml) {
5331                 ASSERT(vmx->pml_pg);
5332                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5333                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5334         }
5335
5336         return 0;
5337 }
5338
5339 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5340 {
5341         struct vcpu_vmx *vmx = to_vmx(vcpu);
5342         struct msr_data apic_base_msr;
5343         u64 cr0;
5344
5345         vmx->rmode.vm86_active = 0;
5346
5347         vmx->soft_vnmi_blocked = 0;
5348
5349         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5350         kvm_set_cr8(vcpu, 0);
5351
5352         if (!init_event) {
5353                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5354                                      MSR_IA32_APICBASE_ENABLE;
5355                 if (kvm_vcpu_is_reset_bsp(vcpu))
5356                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5357                 apic_base_msr.host_initiated = true;
5358                 kvm_set_apic_base(vcpu, &apic_base_msr);
5359         }
5360
5361         vmx_segment_cache_clear(vmx);
5362
5363         seg_setup(VCPU_SREG_CS);
5364         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5365         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5366
5367         seg_setup(VCPU_SREG_DS);
5368         seg_setup(VCPU_SREG_ES);
5369         seg_setup(VCPU_SREG_FS);
5370         seg_setup(VCPU_SREG_GS);
5371         seg_setup(VCPU_SREG_SS);
5372
5373         vmcs_write16(GUEST_TR_SELECTOR, 0);
5374         vmcs_writel(GUEST_TR_BASE, 0);
5375         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5376         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5377
5378         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5379         vmcs_writel(GUEST_LDTR_BASE, 0);
5380         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5381         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5382
5383         if (!init_event) {
5384                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5385                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5386                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5387                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5388         }
5389
5390         vmcs_writel(GUEST_RFLAGS, 0x02);
5391         kvm_rip_write(vcpu, 0xfff0);
5392
5393         vmcs_writel(GUEST_GDTR_BASE, 0);
5394         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5395
5396         vmcs_writel(GUEST_IDTR_BASE, 0);
5397         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5398
5399         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5400         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5401         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5402
5403         setup_msrs(vmx);
5404
5405         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5406
5407         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5408                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5409                 if (cpu_need_tpr_shadow(vcpu))
5410                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5411                                      __pa(vcpu->arch.apic->regs));
5412                 vmcs_write32(TPR_THRESHOLD, 0);
5413         }
5414
5415         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5416
5417         if (kvm_vcpu_apicv_active(vcpu))
5418                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5419
5420         if (vmx->vpid != 0)
5421                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5422
5423         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5424         vmx->vcpu.arch.cr0 = cr0;
5425         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5426         vmx_set_cr4(vcpu, 0);
5427         vmx_set_efer(vcpu, 0);
5428         vmx_fpu_activate(vcpu);
5429         update_exception_bitmap(vcpu);
5430
5431         vpid_sync_context(vmx->vpid);
5432 }
5433
5434 /*
5435  * In nested virtualization, check if L1 asked to exit on external interrupts.
5436  * For most existing hypervisors, this will always return true.
5437  */
5438 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5439 {
5440         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5441                 PIN_BASED_EXT_INTR_MASK;
5442 }
5443
5444 /*
5445  * In nested virtualization, check if L1 has set
5446  * VM_EXIT_ACK_INTR_ON_EXIT
5447  */
5448 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5449 {
5450         return get_vmcs12(vcpu)->vm_exit_controls &
5451                 VM_EXIT_ACK_INTR_ON_EXIT;
5452 }
5453
5454 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5455 {
5456         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5457                 PIN_BASED_NMI_EXITING;
5458 }
5459
5460 static void enable_irq_window(struct kvm_vcpu *vcpu)
5461 {
5462         u32 cpu_based_vm_exec_control;
5463
5464         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5465         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5466         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5467 }
5468
5469 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5470 {
5471         u32 cpu_based_vm_exec_control;
5472
5473         if (!cpu_has_virtual_nmis() ||
5474             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5475                 enable_irq_window(vcpu);
5476                 return;
5477         }
5478
5479         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5480         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5481         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5482 }
5483
5484 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5485 {
5486         struct vcpu_vmx *vmx = to_vmx(vcpu);
5487         uint32_t intr;
5488         int irq = vcpu->arch.interrupt.nr;
5489
5490         trace_kvm_inj_virq(irq);
5491
5492         ++vcpu->stat.irq_injections;
5493         if (vmx->rmode.vm86_active) {
5494                 int inc_eip = 0;
5495                 if (vcpu->arch.interrupt.soft)
5496                         inc_eip = vcpu->arch.event_exit_inst_len;
5497                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5498                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5499                 return;
5500         }
5501         intr = irq | INTR_INFO_VALID_MASK;
5502         if (vcpu->arch.interrupt.soft) {
5503                 intr |= INTR_TYPE_SOFT_INTR;
5504                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5505                              vmx->vcpu.arch.event_exit_inst_len);
5506         } else
5507                 intr |= INTR_TYPE_EXT_INTR;
5508         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5509 }
5510
5511 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5512 {
5513         struct vcpu_vmx *vmx = to_vmx(vcpu);
5514
5515         if (!is_guest_mode(vcpu)) {
5516                 if (!cpu_has_virtual_nmis()) {
5517                         /*
5518                          * Tracking the NMI-blocked state in software is built upon
5519                          * finding the next open IRQ window. This, in turn, depends on
5520                          * well-behaving guests: They have to keep IRQs disabled at
5521                          * least as long as the NMI handler runs. Otherwise we may
5522                          * cause NMI nesting, maybe breaking the guest. But as this is
5523                          * highly unlikely, we can live with the residual risk.
5524                          */
5525                         vmx->soft_vnmi_blocked = 1;
5526                         vmx->vnmi_blocked_time = 0;
5527                 }
5528
5529                 ++vcpu->stat.nmi_injections;
5530                 vmx->nmi_known_unmasked = false;
5531         }
5532
5533         if (vmx->rmode.vm86_active) {
5534                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5535                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5536                 return;
5537         }
5538
5539         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5540                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5541 }
5542
5543 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5544 {
5545         if (!cpu_has_virtual_nmis())
5546                 return to_vmx(vcpu)->soft_vnmi_blocked;
5547         if (to_vmx(vcpu)->nmi_known_unmasked)
5548                 return false;
5549         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5550 }
5551
5552 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5553 {
5554         struct vcpu_vmx *vmx = to_vmx(vcpu);
5555
5556         if (!cpu_has_virtual_nmis()) {
5557                 if (vmx->soft_vnmi_blocked != masked) {
5558                         vmx->soft_vnmi_blocked = masked;
5559                         vmx->vnmi_blocked_time = 0;
5560                 }
5561         } else {
5562                 vmx->nmi_known_unmasked = !masked;
5563                 if (masked)
5564                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5565                                       GUEST_INTR_STATE_NMI);
5566                 else
5567                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5568                                         GUEST_INTR_STATE_NMI);
5569         }
5570 }
5571
5572 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5573 {
5574         if (to_vmx(vcpu)->nested.nested_run_pending)
5575                 return 0;
5576
5577         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5578                 return 0;
5579
5580         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5581                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5582                    | GUEST_INTR_STATE_NMI));
5583 }
5584
5585 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5586 {
5587         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5588                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5589                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5590                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5591 }
5592
5593 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5594 {
5595         int ret;
5596
5597         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5598                                     PAGE_SIZE * 3);
5599         if (ret)
5600                 return ret;
5601         kvm->arch.tss_addr = addr;
5602         return init_rmode_tss(kvm);
5603 }
5604
5605 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5606 {
5607         switch (vec) {
5608         case BP_VECTOR:
5609                 /*
5610                  * Update instruction length as we may reinject the exception
5611                  * from user space while in guest debugging mode.
5612                  */
5613                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5614                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5615                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5616                         return false;
5617                 /* fall through */
5618         case DB_VECTOR:
5619                 if (vcpu->guest_debug &
5620                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5621                         return false;
5622                 /* fall through */
5623         case DE_VECTOR:
5624         case OF_VECTOR:
5625         case BR_VECTOR:
5626         case UD_VECTOR:
5627         case DF_VECTOR:
5628         case SS_VECTOR:
5629         case GP_VECTOR:
5630         case MF_VECTOR:
5631                 return true;
5632         break;
5633         }
5634         return false;
5635 }
5636
5637 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5638                                   int vec, u32 err_code)
5639 {
5640         /*
5641          * Instruction with address size override prefix opcode 0x67
5642          * Cause the #SS fault with 0 error code in VM86 mode.
5643          */
5644         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5645                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5646                         if (vcpu->arch.halt_request) {
5647                                 vcpu->arch.halt_request = 0;
5648                                 return kvm_vcpu_halt(vcpu);
5649                         }
5650                         return 1;
5651                 }
5652                 return 0;
5653         }
5654
5655         /*
5656          * Forward all other exceptions that are valid in real mode.
5657          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5658          *        the required debugging infrastructure rework.
5659          */
5660         kvm_queue_exception(vcpu, vec);
5661         return 1;
5662 }
5663
5664 /*
5665  * Trigger machine check on the host. We assume all the MSRs are already set up
5666  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5667  * We pass a fake environment to the machine check handler because we want
5668  * the guest to be always treated like user space, no matter what context
5669  * it used internally.
5670  */
5671 static void kvm_machine_check(void)
5672 {
5673 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5674         struct pt_regs regs = {
5675                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5676                 .flags = X86_EFLAGS_IF,
5677         };
5678
5679         do_machine_check(&regs, 0);
5680 #endif
5681 }
5682
5683 static int handle_machine_check(struct kvm_vcpu *vcpu)
5684 {
5685         /* already handled by vcpu_run */
5686         return 1;
5687 }
5688
5689 static int handle_exception(struct kvm_vcpu *vcpu)
5690 {
5691         struct vcpu_vmx *vmx = to_vmx(vcpu);
5692         struct kvm_run *kvm_run = vcpu->run;
5693         u32 intr_info, ex_no, error_code;
5694         unsigned long cr2, rip, dr6;
5695         u32 vect_info;
5696         enum emulation_result er;
5697
5698         vect_info = vmx->idt_vectoring_info;
5699         intr_info = vmx->exit_intr_info;
5700
5701         if (is_machine_check(intr_info))
5702                 return handle_machine_check(vcpu);
5703
5704         if (is_nmi(intr_info))
5705                 return 1;  /* already handled by vmx_vcpu_run() */
5706
5707         if (is_no_device(intr_info)) {
5708                 vmx_fpu_activate(vcpu);
5709                 return 1;
5710         }
5711
5712         if (is_invalid_opcode(intr_info)) {
5713                 if (is_guest_mode(vcpu)) {
5714                         kvm_queue_exception(vcpu, UD_VECTOR);
5715                         return 1;
5716                 }
5717                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5718                 if (er != EMULATE_DONE)
5719                         kvm_queue_exception(vcpu, UD_VECTOR);
5720                 return 1;
5721         }
5722
5723         error_code = 0;
5724         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5725                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5726
5727         /*
5728          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5729          * MMIO, it is better to report an internal error.
5730          * See the comments in vmx_handle_exit.
5731          */
5732         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5733             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5734                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5735                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5736                 vcpu->run->internal.ndata = 3;
5737                 vcpu->run->internal.data[0] = vect_info;
5738                 vcpu->run->internal.data[1] = intr_info;
5739                 vcpu->run->internal.data[2] = error_code;
5740                 return 0;
5741         }
5742
5743         if (is_page_fault(intr_info)) {
5744                 /* EPT won't cause page fault directly */
5745                 BUG_ON(enable_ept);
5746                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5747                 trace_kvm_page_fault(cr2, error_code);
5748
5749                 if (kvm_event_needs_reinjection(vcpu))
5750                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5751                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5752         }
5753
5754         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5755
5756         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5757                 return handle_rmode_exception(vcpu, ex_no, error_code);
5758
5759         switch (ex_no) {
5760         case AC_VECTOR:
5761                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5762                 return 1;
5763         case DB_VECTOR:
5764                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5765                 if (!(vcpu->guest_debug &
5766                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5767                         vcpu->arch.dr6 &= ~15;
5768                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5769                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5770                                 skip_emulated_instruction(vcpu);
5771
5772                         kvm_queue_exception(vcpu, DB_VECTOR);
5773                         return 1;
5774                 }
5775                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5776                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5777                 /* fall through */
5778         case BP_VECTOR:
5779                 /*
5780                  * Update instruction length as we may reinject #BP from
5781                  * user space while in guest debugging mode. Reading it for
5782                  * #DB as well causes no harm, it is not used in that case.
5783                  */
5784                 vmx->vcpu.arch.event_exit_inst_len =
5785                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5786                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5787                 rip = kvm_rip_read(vcpu);
5788                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5789                 kvm_run->debug.arch.exception = ex_no;
5790                 break;
5791         default:
5792                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5793                 kvm_run->ex.exception = ex_no;
5794                 kvm_run->ex.error_code = error_code;
5795                 break;
5796         }
5797         return 0;
5798 }
5799
5800 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5801 {
5802         ++vcpu->stat.irq_exits;
5803         return 1;
5804 }
5805
5806 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5807 {
5808         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5809         return 0;
5810 }
5811
5812 static int handle_io(struct kvm_vcpu *vcpu)
5813 {
5814         unsigned long exit_qualification;
5815         int size, in, string, ret;
5816         unsigned port;
5817
5818         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5819         string = (exit_qualification & 16) != 0;
5820         in = (exit_qualification & 8) != 0;
5821
5822         ++vcpu->stat.io_exits;
5823
5824         if (string || in)
5825                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5826
5827         port = exit_qualification >> 16;
5828         size = (exit_qualification & 7) + 1;
5829
5830         ret = kvm_skip_emulated_instruction(vcpu);
5831
5832         /*
5833          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5834          * KVM_EXIT_DEBUG here.
5835          */
5836         return kvm_fast_pio_out(vcpu, size, port) && ret;
5837 }
5838
5839 static void
5840 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5841 {
5842         /*
5843          * Patch in the VMCALL instruction:
5844          */
5845         hypercall[0] = 0x0f;
5846         hypercall[1] = 0x01;
5847         hypercall[2] = 0xc1;
5848 }
5849
5850 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5851 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5852 {
5853         if (is_guest_mode(vcpu)) {
5854                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5855                 unsigned long orig_val = val;
5856
5857                 /*
5858                  * We get here when L2 changed cr0 in a way that did not change
5859                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5860                  * but did change L0 shadowed bits. So we first calculate the
5861                  * effective cr0 value that L1 would like to write into the
5862                  * hardware. It consists of the L2-owned bits from the new
5863                  * value combined with the L1-owned bits from L1's guest_cr0.
5864                  */
5865                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5866                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5867
5868                 if (!nested_guest_cr0_valid(vcpu, val))
5869                         return 1;
5870
5871                 if (kvm_set_cr0(vcpu, val))
5872                         return 1;
5873                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5874                 return 0;
5875         } else {
5876                 if (to_vmx(vcpu)->nested.vmxon &&
5877                     !nested_host_cr0_valid(vcpu, val))
5878                         return 1;
5879
5880                 return kvm_set_cr0(vcpu, val);
5881         }
5882 }
5883
5884 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5885 {
5886         if (is_guest_mode(vcpu)) {
5887                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5888                 unsigned long orig_val = val;
5889
5890                 /* analogously to handle_set_cr0 */
5891                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5892                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5893                 if (kvm_set_cr4(vcpu, val))
5894                         return 1;
5895                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5896                 return 0;
5897         } else
5898                 return kvm_set_cr4(vcpu, val);
5899 }
5900
5901 /* called to set cr0 as appropriate for clts instruction exit. */
5902 static void handle_clts(struct kvm_vcpu *vcpu)
5903 {
5904         if (is_guest_mode(vcpu)) {
5905                 /*
5906                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5907                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5908                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5909                  */
5910                 vmcs_writel(CR0_READ_SHADOW,
5911                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5912                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5913         } else
5914                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5915 }
5916
5917 static int handle_cr(struct kvm_vcpu *vcpu)
5918 {
5919         unsigned long exit_qualification, val;
5920         int cr;
5921         int reg;
5922         int err;
5923         int ret;
5924
5925         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5926         cr = exit_qualification & 15;
5927         reg = (exit_qualification >> 8) & 15;
5928         switch ((exit_qualification >> 4) & 3) {
5929         case 0: /* mov to cr */
5930                 val = kvm_register_readl(vcpu, reg);
5931                 trace_kvm_cr_write(cr, val);
5932                 switch (cr) {
5933                 case 0:
5934                         err = handle_set_cr0(vcpu, val);
5935                         return kvm_complete_insn_gp(vcpu, err);
5936                 case 3:
5937                         err = kvm_set_cr3(vcpu, val);
5938                         return kvm_complete_insn_gp(vcpu, err);
5939                 case 4:
5940                         err = handle_set_cr4(vcpu, val);
5941                         return kvm_complete_insn_gp(vcpu, err);
5942                 case 8: {
5943                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5944                                 u8 cr8 = (u8)val;
5945                                 err = kvm_set_cr8(vcpu, cr8);
5946                                 ret = kvm_complete_insn_gp(vcpu, err);
5947                                 if (lapic_in_kernel(vcpu))
5948                                         return ret;
5949                                 if (cr8_prev <= cr8)
5950                                         return ret;
5951                                 /*
5952                                  * TODO: we might be squashing a
5953                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5954                                  * KVM_EXIT_DEBUG here.
5955                                  */
5956                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5957                                 return 0;
5958                         }
5959                 }
5960                 break;
5961         case 2: /* clts */
5962                 handle_clts(vcpu);
5963                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5964                 vmx_fpu_activate(vcpu);
5965                 return kvm_skip_emulated_instruction(vcpu);
5966         case 1: /*mov from cr*/
5967                 switch (cr) {
5968                 case 3:
5969                         val = kvm_read_cr3(vcpu);
5970                         kvm_register_write(vcpu, reg, val);
5971                         trace_kvm_cr_read(cr, val);
5972                         return kvm_skip_emulated_instruction(vcpu);
5973                 case 8:
5974                         val = kvm_get_cr8(vcpu);
5975                         kvm_register_write(vcpu, reg, val);
5976                         trace_kvm_cr_read(cr, val);
5977                         return kvm_skip_emulated_instruction(vcpu);
5978                 }
5979                 break;
5980         case 3: /* lmsw */
5981                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5982                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5983                 kvm_lmsw(vcpu, val);
5984
5985                 return kvm_skip_emulated_instruction(vcpu);
5986         default:
5987                 break;
5988         }
5989         vcpu->run->exit_reason = 0;
5990         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5991                (int)(exit_qualification >> 4) & 3, cr);
5992         return 0;
5993 }
5994
5995 static int handle_dr(struct kvm_vcpu *vcpu)
5996 {
5997         unsigned long exit_qualification;
5998         int dr, dr7, reg;
5999
6000         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6001         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6002
6003         /* First, if DR does not exist, trigger UD */
6004         if (!kvm_require_dr(vcpu, dr))
6005                 return 1;
6006
6007         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6008         if (!kvm_require_cpl(vcpu, 0))
6009                 return 1;
6010         dr7 = vmcs_readl(GUEST_DR7);
6011         if (dr7 & DR7_GD) {
6012                 /*
6013                  * As the vm-exit takes precedence over the debug trap, we
6014                  * need to emulate the latter, either for the host or the
6015                  * guest debugging itself.
6016                  */
6017                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6018                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6019                         vcpu->run->debug.arch.dr7 = dr7;
6020                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6021                         vcpu->run->debug.arch.exception = DB_VECTOR;
6022                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6023                         return 0;
6024                 } else {
6025                         vcpu->arch.dr6 &= ~15;
6026                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6027                         kvm_queue_exception(vcpu, DB_VECTOR);
6028                         return 1;
6029                 }
6030         }
6031
6032         if (vcpu->guest_debug == 0) {
6033                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6034                                 CPU_BASED_MOV_DR_EXITING);
6035
6036                 /*
6037                  * No more DR vmexits; force a reload of the debug registers
6038                  * and reenter on this instruction.  The next vmexit will
6039                  * retrieve the full state of the debug registers.
6040                  */
6041                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6042                 return 1;
6043         }
6044
6045         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6046         if (exit_qualification & TYPE_MOV_FROM_DR) {
6047                 unsigned long val;
6048
6049                 if (kvm_get_dr(vcpu, dr, &val))
6050                         return 1;
6051                 kvm_register_write(vcpu, reg, val);
6052         } else
6053                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6054                         return 1;
6055
6056         return kvm_skip_emulated_instruction(vcpu);
6057 }
6058
6059 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6060 {
6061         return vcpu->arch.dr6;
6062 }
6063
6064 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6065 {
6066 }
6067
6068 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6069 {
6070         get_debugreg(vcpu->arch.db[0], 0);
6071         get_debugreg(vcpu->arch.db[1], 1);
6072         get_debugreg(vcpu->arch.db[2], 2);
6073         get_debugreg(vcpu->arch.db[3], 3);
6074         get_debugreg(vcpu->arch.dr6, 6);
6075         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6076
6077         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6078         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6079 }
6080
6081 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6082 {
6083         vmcs_writel(GUEST_DR7, val);
6084 }
6085
6086 static int handle_cpuid(struct kvm_vcpu *vcpu)
6087 {
6088         return kvm_emulate_cpuid(vcpu);
6089 }
6090
6091 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6092 {
6093         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6094         struct msr_data msr_info;
6095
6096         msr_info.index = ecx;
6097         msr_info.host_initiated = false;
6098         if (vmx_get_msr(vcpu, &msr_info)) {
6099                 trace_kvm_msr_read_ex(ecx);
6100                 kvm_inject_gp(vcpu, 0);
6101                 return 1;
6102         }
6103
6104         trace_kvm_msr_read(ecx, msr_info.data);
6105
6106         /* FIXME: handling of bits 32:63 of rax, rdx */
6107         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6108         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6109         return kvm_skip_emulated_instruction(vcpu);
6110 }
6111
6112 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6113 {
6114         struct msr_data msr;
6115         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6116         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6117                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6118
6119         msr.data = data;
6120         msr.index = ecx;
6121         msr.host_initiated = false;
6122         if (kvm_set_msr(vcpu, &msr) != 0) {
6123                 trace_kvm_msr_write_ex(ecx, data);
6124                 kvm_inject_gp(vcpu, 0);
6125                 return 1;
6126         }
6127
6128         trace_kvm_msr_write(ecx, data);
6129         return kvm_skip_emulated_instruction(vcpu);
6130 }
6131
6132 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6133 {
6134         kvm_apic_update_ppr(vcpu);
6135         return 1;
6136 }
6137
6138 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6139 {
6140         u32 cpu_based_vm_exec_control;
6141
6142         /* clear pending irq */
6143         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6144         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6145         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6146
6147         kvm_make_request(KVM_REQ_EVENT, vcpu);
6148
6149         ++vcpu->stat.irq_window_exits;
6150         return 1;
6151 }
6152
6153 static int handle_halt(struct kvm_vcpu *vcpu)
6154 {
6155         return kvm_emulate_halt(vcpu);
6156 }
6157
6158 static int handle_vmcall(struct kvm_vcpu *vcpu)
6159 {
6160         return kvm_emulate_hypercall(vcpu);
6161 }
6162
6163 static int handle_invd(struct kvm_vcpu *vcpu)
6164 {
6165         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6166 }
6167
6168 static int handle_invlpg(struct kvm_vcpu *vcpu)
6169 {
6170         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6171
6172         kvm_mmu_invlpg(vcpu, exit_qualification);
6173         return kvm_skip_emulated_instruction(vcpu);
6174 }
6175
6176 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6177 {
6178         int err;
6179
6180         err = kvm_rdpmc(vcpu);
6181         return kvm_complete_insn_gp(vcpu, err);
6182 }
6183
6184 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6185 {
6186         return kvm_emulate_wbinvd(vcpu);
6187 }
6188
6189 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6190 {
6191         u64 new_bv = kvm_read_edx_eax(vcpu);
6192         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6193
6194         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6195                 return kvm_skip_emulated_instruction(vcpu);
6196         return 1;
6197 }
6198
6199 static int handle_xsaves(struct kvm_vcpu *vcpu)
6200 {
6201         kvm_skip_emulated_instruction(vcpu);
6202         WARN(1, "this should never happen\n");
6203         return 1;
6204 }
6205
6206 static int handle_xrstors(struct kvm_vcpu *vcpu)
6207 {
6208         kvm_skip_emulated_instruction(vcpu);
6209         WARN(1, "this should never happen\n");
6210         return 1;
6211 }
6212
6213 static int handle_apic_access(struct kvm_vcpu *vcpu)
6214 {
6215         if (likely(fasteoi)) {
6216                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6217                 int access_type, offset;
6218
6219                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6220                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6221                 /*
6222                  * Sane guest uses MOV to write EOI, with written value
6223                  * not cared. So make a short-circuit here by avoiding
6224                  * heavy instruction emulation.
6225                  */
6226                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6227                     (offset == APIC_EOI)) {
6228                         kvm_lapic_set_eoi(vcpu);
6229                         return kvm_skip_emulated_instruction(vcpu);
6230                 }
6231         }
6232         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6233 }
6234
6235 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6236 {
6237         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6238         int vector = exit_qualification & 0xff;
6239
6240         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6241         kvm_apic_set_eoi_accelerated(vcpu, vector);
6242         return 1;
6243 }
6244
6245 static int handle_apic_write(struct kvm_vcpu *vcpu)
6246 {
6247         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6248         u32 offset = exit_qualification & 0xfff;
6249
6250         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6251         kvm_apic_write_nodecode(vcpu, offset);
6252         return 1;
6253 }
6254
6255 static int handle_task_switch(struct kvm_vcpu *vcpu)
6256 {
6257         struct vcpu_vmx *vmx = to_vmx(vcpu);
6258         unsigned long exit_qualification;
6259         bool has_error_code = false;
6260         u32 error_code = 0;
6261         u16 tss_selector;
6262         int reason, type, idt_v, idt_index;
6263
6264         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6265         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6266         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6267
6268         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6269
6270         reason = (u32)exit_qualification >> 30;
6271         if (reason == TASK_SWITCH_GATE && idt_v) {
6272                 switch (type) {
6273                 case INTR_TYPE_NMI_INTR:
6274                         vcpu->arch.nmi_injected = false;
6275                         vmx_set_nmi_mask(vcpu, true);
6276                         break;
6277                 case INTR_TYPE_EXT_INTR:
6278                 case INTR_TYPE_SOFT_INTR:
6279                         kvm_clear_interrupt_queue(vcpu);
6280                         break;
6281                 case INTR_TYPE_HARD_EXCEPTION:
6282                         if (vmx->idt_vectoring_info &
6283                             VECTORING_INFO_DELIVER_CODE_MASK) {
6284                                 has_error_code = true;
6285                                 error_code =
6286                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6287                         }
6288                         /* fall through */
6289                 case INTR_TYPE_SOFT_EXCEPTION:
6290                         kvm_clear_exception_queue(vcpu);
6291                         break;
6292                 default:
6293                         break;
6294                 }
6295         }
6296         tss_selector = exit_qualification;
6297
6298         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6299                        type != INTR_TYPE_EXT_INTR &&
6300                        type != INTR_TYPE_NMI_INTR))
6301                 skip_emulated_instruction(vcpu);
6302
6303         if (kvm_task_switch(vcpu, tss_selector,
6304                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6305                             has_error_code, error_code) == EMULATE_FAIL) {
6306                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6307                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6308                 vcpu->run->internal.ndata = 0;
6309                 return 0;
6310         }
6311
6312         /*
6313          * TODO: What about debug traps on tss switch?
6314          *       Are we supposed to inject them and update dr6?
6315          */
6316
6317         return 1;
6318 }
6319
6320 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6321 {
6322         unsigned long exit_qualification;
6323         gpa_t gpa;
6324         u32 error_code;
6325         int gla_validity;
6326
6327         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6328
6329         gla_validity = (exit_qualification >> 7) & 0x3;
6330         if (gla_validity == 0x2) {
6331                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6332                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6333                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6334                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6335                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6336                         (long unsigned int)exit_qualification);
6337                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6338                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6339                 return 0;
6340         }
6341
6342         /*
6343          * EPT violation happened while executing iret from NMI,
6344          * "blocked by NMI" bit has to be set before next VM entry.
6345          * There are errata that may cause this bit to not be set:
6346          * AAK134, BY25.
6347          */
6348         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6349                         cpu_has_virtual_nmis() &&
6350                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6351                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6352
6353         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6354         trace_kvm_page_fault(gpa, exit_qualification);
6355
6356         /* Is it a read fault? */
6357         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6358                      ? PFERR_USER_MASK : 0;
6359         /* Is it a write fault? */
6360         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6361                       ? PFERR_WRITE_MASK : 0;
6362         /* Is it a fetch fault? */
6363         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6364                       ? PFERR_FETCH_MASK : 0;
6365         /* ept page table entry is present? */
6366         error_code |= (exit_qualification &
6367                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6368                         EPT_VIOLATION_EXECUTABLE))
6369                       ? PFERR_PRESENT_MASK : 0;
6370
6371         vcpu->arch.gpa_available = true;
6372         vcpu->arch.exit_qualification = exit_qualification;
6373
6374         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6375 }
6376
6377 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6378 {
6379         int ret;
6380         gpa_t gpa;
6381
6382         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6383         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6384                 trace_kvm_fast_mmio(gpa);
6385                 return kvm_skip_emulated_instruction(vcpu);
6386         }
6387
6388         ret = handle_mmio_page_fault(vcpu, gpa, true);
6389         vcpu->arch.gpa_available = true;
6390         if (likely(ret == RET_MMIO_PF_EMULATE))
6391                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6392                                               EMULATE_DONE;
6393
6394         if (unlikely(ret == RET_MMIO_PF_INVALID))
6395                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6396
6397         if (unlikely(ret == RET_MMIO_PF_RETRY))
6398                 return 1;
6399
6400         /* It is the real ept misconfig */
6401         WARN_ON(1);
6402
6403         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6404         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6405
6406         return 0;
6407 }
6408
6409 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6410 {
6411         u32 cpu_based_vm_exec_control;
6412
6413         /* clear pending NMI */
6414         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6415         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6416         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6417         ++vcpu->stat.nmi_window_exits;
6418         kvm_make_request(KVM_REQ_EVENT, vcpu);
6419
6420         return 1;
6421 }
6422
6423 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6424 {
6425         struct vcpu_vmx *vmx = to_vmx(vcpu);
6426         enum emulation_result err = EMULATE_DONE;
6427         int ret = 1;
6428         u32 cpu_exec_ctrl;
6429         bool intr_window_requested;
6430         unsigned count = 130;
6431
6432         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6433         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6434
6435         while (vmx->emulation_required && count-- != 0) {
6436                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6437                         return handle_interrupt_window(&vmx->vcpu);
6438
6439                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6440                         return 1;
6441
6442                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6443
6444                 if (err == EMULATE_USER_EXIT) {
6445                         ++vcpu->stat.mmio_exits;
6446                         ret = 0;
6447                         goto out;
6448                 }
6449
6450                 if (err != EMULATE_DONE) {
6451                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6452                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6453                         vcpu->run->internal.ndata = 0;
6454                         return 0;
6455                 }
6456
6457                 if (vcpu->arch.halt_request) {
6458                         vcpu->arch.halt_request = 0;
6459                         ret = kvm_vcpu_halt(vcpu);
6460                         goto out;
6461                 }
6462
6463                 if (signal_pending(current))
6464                         goto out;
6465                 if (need_resched())
6466                         schedule();
6467         }
6468
6469 out:
6470         return ret;
6471 }
6472
6473 static int __grow_ple_window(int val)
6474 {
6475         if (ple_window_grow < 1)
6476                 return ple_window;
6477
6478         val = min(val, ple_window_actual_max);
6479
6480         if (ple_window_grow < ple_window)
6481                 val *= ple_window_grow;
6482         else
6483                 val += ple_window_grow;
6484
6485         return val;
6486 }
6487
6488 static int __shrink_ple_window(int val, int modifier, int minimum)
6489 {
6490         if (modifier < 1)
6491                 return ple_window;
6492
6493         if (modifier < ple_window)
6494                 val /= modifier;
6495         else
6496                 val -= modifier;
6497
6498         return max(val, minimum);
6499 }
6500
6501 static void grow_ple_window(struct kvm_vcpu *vcpu)
6502 {
6503         struct vcpu_vmx *vmx = to_vmx(vcpu);
6504         int old = vmx->ple_window;
6505
6506         vmx->ple_window = __grow_ple_window(old);
6507
6508         if (vmx->ple_window != old)
6509                 vmx->ple_window_dirty = true;
6510
6511         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6512 }
6513
6514 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6515 {
6516         struct vcpu_vmx *vmx = to_vmx(vcpu);
6517         int old = vmx->ple_window;
6518
6519         vmx->ple_window = __shrink_ple_window(old,
6520                                               ple_window_shrink, ple_window);
6521
6522         if (vmx->ple_window != old)
6523                 vmx->ple_window_dirty = true;
6524
6525         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6526 }
6527
6528 /*
6529  * ple_window_actual_max is computed to be one grow_ple_window() below
6530  * ple_window_max. (See __grow_ple_window for the reason.)
6531  * This prevents overflows, because ple_window_max is int.
6532  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6533  * this process.
6534  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6535  */
6536 static void update_ple_window_actual_max(void)
6537 {
6538         ple_window_actual_max =
6539                         __shrink_ple_window(max(ple_window_max, ple_window),
6540                                             ple_window_grow, INT_MIN);
6541 }
6542
6543 /*
6544  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6545  */
6546 static void wakeup_handler(void)
6547 {
6548         struct kvm_vcpu *vcpu;
6549         int cpu = smp_processor_id();
6550
6551         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6552         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6553                         blocked_vcpu_list) {
6554                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6555
6556                 if (pi_test_on(pi_desc) == 1)
6557                         kvm_vcpu_kick(vcpu);
6558         }
6559         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6560 }
6561
6562 void vmx_enable_tdp(void)
6563 {
6564         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6565                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6566                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6567                 0ull, VMX_EPT_EXECUTABLE_MASK,
6568                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6569                 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6570
6571         ept_set_mmio_spte_mask();
6572         kvm_enable_tdp();
6573 }
6574
6575 static __init int hardware_setup(void)
6576 {
6577         int r = -ENOMEM, i, msr;
6578
6579         rdmsrl_safe(MSR_EFER, &host_efer);
6580
6581         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6582                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6583
6584         for (i = 0; i < VMX_BITMAP_NR; i++) {
6585                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6586                 if (!vmx_bitmap[i])
6587                         goto out;
6588         }
6589
6590         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6591         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6592         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6593
6594         /*
6595          * Allow direct access to the PC debug port (it is often used for I/O
6596          * delays, but the vmexits simply slow things down).
6597          */
6598         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6599         clear_bit(0x80, vmx_io_bitmap_a);
6600
6601         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6602
6603         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6604         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6605
6606         if (setup_vmcs_config(&vmcs_config) < 0) {
6607                 r = -EIO;
6608                 goto out;
6609         }
6610
6611         if (boot_cpu_has(X86_FEATURE_NX))
6612                 kvm_enable_efer_bits(EFER_NX);
6613
6614         if (!cpu_has_vmx_vpid())
6615                 enable_vpid = 0;
6616         if (!cpu_has_vmx_shadow_vmcs())
6617                 enable_shadow_vmcs = 0;
6618         if (enable_shadow_vmcs)
6619                 init_vmcs_shadow_fields();
6620
6621         if (!cpu_has_vmx_ept() ||
6622             !cpu_has_vmx_ept_4levels()) {
6623                 enable_ept = 0;
6624                 enable_unrestricted_guest = 0;
6625                 enable_ept_ad_bits = 0;
6626         }
6627
6628         if (!cpu_has_vmx_ept_ad_bits())
6629                 enable_ept_ad_bits = 0;
6630
6631         if (!cpu_has_vmx_unrestricted_guest())
6632                 enable_unrestricted_guest = 0;
6633
6634         if (!cpu_has_vmx_flexpriority())
6635                 flexpriority_enabled = 0;
6636
6637         /*
6638          * set_apic_access_page_addr() is used to reload apic access
6639          * page upon invalidation.  No need to do anything if not
6640          * using the APIC_ACCESS_ADDR VMCS field.
6641          */
6642         if (!flexpriority_enabled)
6643                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6644
6645         if (!cpu_has_vmx_tpr_shadow())
6646                 kvm_x86_ops->update_cr8_intercept = NULL;
6647
6648         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6649                 kvm_disable_largepages();
6650
6651         if (!cpu_has_vmx_ple())
6652                 ple_gap = 0;
6653
6654         if (!cpu_has_vmx_apicv()) {
6655                 enable_apicv = 0;
6656                 kvm_x86_ops->sync_pir_to_irr = NULL;
6657         }
6658
6659         if (cpu_has_vmx_tsc_scaling()) {
6660                 kvm_has_tsc_control = true;
6661                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6662                 kvm_tsc_scaling_ratio_frac_bits = 48;
6663         }
6664
6665         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6666         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6667         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6668         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6669         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6670         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6671         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6672
6673         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6674                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6675         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6676                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6677         memcpy(vmx_msr_bitmap_legacy_x2apic,
6678                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6679         memcpy(vmx_msr_bitmap_longmode_x2apic,
6680                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6681
6682         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6683
6684         for (msr = 0x800; msr <= 0x8ff; msr++) {
6685                 if (msr == 0x839 /* TMCCT */)
6686                         continue;
6687                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6688         }
6689
6690         /*
6691          * TPR reads and writes can be virtualized even if virtual interrupt
6692          * delivery is not in use.
6693          */
6694         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6695         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6696
6697         /* EOI */
6698         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6699         /* SELF-IPI */
6700         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6701
6702         if (enable_ept)
6703                 vmx_enable_tdp();
6704         else
6705                 kvm_disable_tdp();
6706
6707         update_ple_window_actual_max();
6708
6709         /*
6710          * Only enable PML when hardware supports PML feature, and both EPT
6711          * and EPT A/D bit features are enabled -- PML depends on them to work.
6712          */
6713         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6714                 enable_pml = 0;
6715
6716         if (!enable_pml) {
6717                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6718                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6719                 kvm_x86_ops->flush_log_dirty = NULL;
6720                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6721         }
6722
6723         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6724                 u64 vmx_msr;
6725
6726                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6727                 cpu_preemption_timer_multi =
6728                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6729         } else {
6730                 kvm_x86_ops->set_hv_timer = NULL;
6731                 kvm_x86_ops->cancel_hv_timer = NULL;
6732         }
6733
6734         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6735
6736         kvm_mce_cap_supported |= MCG_LMCE_P;
6737
6738         return alloc_kvm_area();
6739
6740 out:
6741         for (i = 0; i < VMX_BITMAP_NR; i++)
6742                 free_page((unsigned long)vmx_bitmap[i]);
6743
6744     return r;
6745 }
6746
6747 static __exit void hardware_unsetup(void)
6748 {
6749         int i;
6750
6751         for (i = 0; i < VMX_BITMAP_NR; i++)
6752                 free_page((unsigned long)vmx_bitmap[i]);
6753
6754         free_kvm_area();
6755 }
6756
6757 /*
6758  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6759  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6760  */
6761 static int handle_pause(struct kvm_vcpu *vcpu)
6762 {
6763         if (ple_gap)
6764                 grow_ple_window(vcpu);
6765
6766         kvm_vcpu_on_spin(vcpu);
6767         return kvm_skip_emulated_instruction(vcpu);
6768 }
6769
6770 static int handle_nop(struct kvm_vcpu *vcpu)
6771 {
6772         return kvm_skip_emulated_instruction(vcpu);
6773 }
6774
6775 static int handle_mwait(struct kvm_vcpu *vcpu)
6776 {
6777         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6778         return handle_nop(vcpu);
6779 }
6780
6781 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6782 {
6783         return 1;
6784 }
6785
6786 static int handle_monitor(struct kvm_vcpu *vcpu)
6787 {
6788         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6789         return handle_nop(vcpu);
6790 }
6791
6792 /*
6793  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6794  * We could reuse a single VMCS for all the L2 guests, but we also want the
6795  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6796  * allows keeping them loaded on the processor, and in the future will allow
6797  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6798  * every entry if they never change.
6799  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6800  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6801  *
6802  * The following functions allocate and free a vmcs02 in this pool.
6803  */
6804
6805 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6806 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6807 {
6808         struct vmcs02_list *item;
6809         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6810                 if (item->vmptr == vmx->nested.current_vmptr) {
6811                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6812                         return &item->vmcs02;
6813                 }
6814
6815         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6816                 /* Recycle the least recently used VMCS. */
6817                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6818                                        struct vmcs02_list, list);
6819                 item->vmptr = vmx->nested.current_vmptr;
6820                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6821                 return &item->vmcs02;
6822         }
6823
6824         /* Create a new VMCS */
6825         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6826         if (!item)
6827                 return NULL;
6828         item->vmcs02.vmcs = alloc_vmcs();
6829         item->vmcs02.shadow_vmcs = NULL;
6830         if (!item->vmcs02.vmcs) {
6831                 kfree(item);
6832                 return NULL;
6833         }
6834         loaded_vmcs_init(&item->vmcs02);
6835         item->vmptr = vmx->nested.current_vmptr;
6836         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6837         vmx->nested.vmcs02_num++;
6838         return &item->vmcs02;
6839 }
6840
6841 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6842 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6843 {
6844         struct vmcs02_list *item;
6845         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6846                 if (item->vmptr == vmptr) {
6847                         free_loaded_vmcs(&item->vmcs02);
6848                         list_del(&item->list);
6849                         kfree(item);
6850                         vmx->nested.vmcs02_num--;
6851                         return;
6852                 }
6853 }
6854
6855 /*
6856  * Free all VMCSs saved for this vcpu, except the one pointed by
6857  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6858  * must be &vmx->vmcs01.
6859  */
6860 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6861 {
6862         struct vmcs02_list *item, *n;
6863
6864         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6865         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6866                 /*
6867                  * Something will leak if the above WARN triggers.  Better than
6868                  * a use-after-free.
6869                  */
6870                 if (vmx->loaded_vmcs == &item->vmcs02)
6871                         continue;
6872
6873                 free_loaded_vmcs(&item->vmcs02);
6874                 list_del(&item->list);
6875                 kfree(item);
6876                 vmx->nested.vmcs02_num--;
6877         }
6878 }
6879
6880 /*
6881  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6882  * set the success or error code of an emulated VMX instruction, as specified
6883  * by Vol 2B, VMX Instruction Reference, "Conventions".
6884  */
6885 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6886 {
6887         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6888                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6889                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6890 }
6891
6892 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6893 {
6894         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6895                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6896                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6897                         | X86_EFLAGS_CF);
6898 }
6899
6900 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6901                                         u32 vm_instruction_error)
6902 {
6903         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6904                 /*
6905                  * failValid writes the error number to the current VMCS, which
6906                  * can't be done there isn't a current VMCS.
6907                  */
6908                 nested_vmx_failInvalid(vcpu);
6909                 return;
6910         }
6911         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6912                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6913                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6914                         | X86_EFLAGS_ZF);
6915         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6916         /*
6917          * We don't need to force a shadow sync because
6918          * VM_INSTRUCTION_ERROR is not shadowed
6919          */
6920 }
6921
6922 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6923 {
6924         /* TODO: not to reset guest simply here. */
6925         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6926         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6927 }
6928
6929 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6930 {
6931         struct vcpu_vmx *vmx =
6932                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6933
6934         vmx->nested.preemption_timer_expired = true;
6935         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6936         kvm_vcpu_kick(&vmx->vcpu);
6937
6938         return HRTIMER_NORESTART;
6939 }
6940
6941 /*
6942  * Decode the memory-address operand of a vmx instruction, as recorded on an
6943  * exit caused by such an instruction (run by a guest hypervisor).
6944  * On success, returns 0. When the operand is invalid, returns 1 and throws
6945  * #UD or #GP.
6946  */
6947 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6948                                  unsigned long exit_qualification,
6949                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6950 {
6951         gva_t off;
6952         bool exn;
6953         struct kvm_segment s;
6954
6955         /*
6956          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6957          * Execution", on an exit, vmx_instruction_info holds most of the
6958          * addressing components of the operand. Only the displacement part
6959          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6960          * For how an actual address is calculated from all these components,
6961          * refer to Vol. 1, "Operand Addressing".
6962          */
6963         int  scaling = vmx_instruction_info & 3;
6964         int  addr_size = (vmx_instruction_info >> 7) & 7;
6965         bool is_reg = vmx_instruction_info & (1u << 10);
6966         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6967         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6968         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6969         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6970         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6971
6972         if (is_reg) {
6973                 kvm_queue_exception(vcpu, UD_VECTOR);
6974                 return 1;
6975         }
6976
6977         /* Addr = segment_base + offset */
6978         /* offset = base + [index * scale] + displacement */
6979         off = exit_qualification; /* holds the displacement */
6980         if (base_is_valid)
6981                 off += kvm_register_read(vcpu, base_reg);
6982         if (index_is_valid)
6983                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6984         vmx_get_segment(vcpu, &s, seg_reg);
6985         *ret = s.base + off;
6986
6987         if (addr_size == 1) /* 32 bit */
6988                 *ret &= 0xffffffff;
6989
6990         /* Checks for #GP/#SS exceptions. */
6991         exn = false;
6992         if (is_long_mode(vcpu)) {
6993                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6994                  * non-canonical form. This is the only check on the memory
6995                  * destination for long mode!
6996                  */
6997                 exn = is_noncanonical_address(*ret);
6998         } else if (is_protmode(vcpu)) {
6999                 /* Protected mode: apply checks for segment validity in the
7000                  * following order:
7001                  * - segment type check (#GP(0) may be thrown)
7002                  * - usability check (#GP(0)/#SS(0))
7003                  * - limit check (#GP(0)/#SS(0))
7004                  */
7005                 if (wr)
7006                         /* #GP(0) if the destination operand is located in a
7007                          * read-only data segment or any code segment.
7008                          */
7009                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
7010                 else
7011                         /* #GP(0) if the source operand is located in an
7012                          * execute-only code segment
7013                          */
7014                         exn = ((s.type & 0xa) == 8);
7015                 if (exn) {
7016                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7017                         return 1;
7018                 }
7019                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7020                  */
7021                 exn = (s.unusable != 0);
7022                 /* Protected mode: #GP(0)/#SS(0) if the memory
7023                  * operand is outside the segment limit.
7024                  */
7025                 exn = exn || (off + sizeof(u64) > s.limit);
7026         }
7027         if (exn) {
7028                 kvm_queue_exception_e(vcpu,
7029                                       seg_reg == VCPU_SREG_SS ?
7030                                                 SS_VECTOR : GP_VECTOR,
7031                                       0);
7032                 return 1;
7033         }
7034
7035         return 0;
7036 }
7037
7038 /*
7039  * This function performs the various checks including
7040  * - if it's 4KB aligned
7041  * - No bits beyond the physical address width are set
7042  * - Returns 0 on success or else 1
7043  * (Intel SDM Section 30.3)
7044  */
7045 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
7046                                   gpa_t *vmpointer)
7047 {
7048         gva_t gva;
7049         gpa_t vmptr;
7050         struct x86_exception e;
7051         struct page *page;
7052         struct vcpu_vmx *vmx = to_vmx(vcpu);
7053         int maxphyaddr = cpuid_maxphyaddr(vcpu);
7054
7055         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7056                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7057                 return 1;
7058
7059         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
7060                                 sizeof(vmptr), &e)) {
7061                 kvm_inject_page_fault(vcpu, &e);
7062                 return 1;
7063         }
7064
7065         switch (exit_reason) {
7066         case EXIT_REASON_VMON:
7067                 /*
7068                  * SDM 3: 24.11.5
7069                  * The first 4 bytes of VMXON region contain the supported
7070                  * VMCS revision identifier
7071                  *
7072                  * Note - IA32_VMX_BASIC[48] will never be 1
7073                  * for the nested case;
7074                  * which replaces physical address width with 32
7075                  *
7076                  */
7077                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7078                         nested_vmx_failInvalid(vcpu);
7079                         return kvm_skip_emulated_instruction(vcpu);
7080                 }
7081
7082                 page = nested_get_page(vcpu, vmptr);
7083                 if (page == NULL ||
7084                     *(u32 *)kmap(page) != VMCS12_REVISION) {
7085                         nested_vmx_failInvalid(vcpu);
7086                         kunmap(page);
7087                         return kvm_skip_emulated_instruction(vcpu);
7088                 }
7089                 kunmap(page);
7090                 vmx->nested.vmxon_ptr = vmptr;
7091                 break;
7092         case EXIT_REASON_VMCLEAR:
7093                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7094                         nested_vmx_failValid(vcpu,
7095                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
7096                         return kvm_skip_emulated_instruction(vcpu);
7097                 }
7098
7099                 if (vmptr == vmx->nested.vmxon_ptr) {
7100                         nested_vmx_failValid(vcpu,
7101                                              VMXERR_VMCLEAR_VMXON_POINTER);
7102                         return kvm_skip_emulated_instruction(vcpu);
7103                 }
7104                 break;
7105         case EXIT_REASON_VMPTRLD:
7106                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7107                         nested_vmx_failValid(vcpu,
7108                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
7109                         return kvm_skip_emulated_instruction(vcpu);
7110                 }
7111
7112                 if (vmptr == vmx->nested.vmxon_ptr) {
7113                         nested_vmx_failValid(vcpu,
7114                                              VMXERR_VMPTRLD_VMXON_POINTER);
7115                         return kvm_skip_emulated_instruction(vcpu);
7116                 }
7117                 break;
7118         default:
7119                 return 1; /* shouldn't happen */
7120         }
7121
7122         if (vmpointer)
7123                 *vmpointer = vmptr;
7124         return 0;
7125 }
7126
7127 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7128 {
7129         struct vcpu_vmx *vmx = to_vmx(vcpu);
7130         struct vmcs *shadow_vmcs;
7131
7132         if (cpu_has_vmx_msr_bitmap()) {
7133                 vmx->nested.msr_bitmap =
7134                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7135                 if (!vmx->nested.msr_bitmap)
7136                         goto out_msr_bitmap;
7137         }
7138
7139         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7140         if (!vmx->nested.cached_vmcs12)
7141                 goto out_cached_vmcs12;
7142
7143         if (enable_shadow_vmcs) {
7144                 shadow_vmcs = alloc_vmcs();
7145                 if (!shadow_vmcs)
7146                         goto out_shadow_vmcs;
7147                 /* mark vmcs as shadow */
7148                 shadow_vmcs->revision_id |= (1u << 31);
7149                 /* init shadow vmcs */
7150                 vmcs_clear(shadow_vmcs);
7151                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7152         }
7153
7154         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7155         vmx->nested.vmcs02_num = 0;
7156
7157         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7158                      HRTIMER_MODE_REL_PINNED);
7159         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7160
7161         vmx->nested.vmxon = true;
7162         return 0;
7163
7164 out_shadow_vmcs:
7165         kfree(vmx->nested.cached_vmcs12);
7166
7167 out_cached_vmcs12:
7168         free_page((unsigned long)vmx->nested.msr_bitmap);
7169
7170 out_msr_bitmap:
7171         return -ENOMEM;
7172 }
7173
7174 /*
7175  * Emulate the VMXON instruction.
7176  * Currently, we just remember that VMX is active, and do not save or even
7177  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7178  * do not currently need to store anything in that guest-allocated memory
7179  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7180  * argument is different from the VMXON pointer (which the spec says they do).
7181  */
7182 static int handle_vmon(struct kvm_vcpu *vcpu)
7183 {
7184         int ret;
7185         struct kvm_segment cs;
7186         struct vcpu_vmx *vmx = to_vmx(vcpu);
7187         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7188                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7189
7190         /* The Intel VMX Instruction Reference lists a bunch of bits that
7191          * are prerequisite to running VMXON, most notably cr4.VMXE must be
7192          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7193          * Otherwise, we should fail with #UD. We test these now:
7194          */
7195         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7196             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7197             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7198                 kvm_queue_exception(vcpu, UD_VECTOR);
7199                 return 1;
7200         }
7201
7202         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7203         if (is_long_mode(vcpu) && !cs.l) {
7204                 kvm_queue_exception(vcpu, UD_VECTOR);
7205                 return 1;
7206         }
7207
7208         if (vmx_get_cpl(vcpu)) {
7209                 kvm_inject_gp(vcpu, 0);
7210                 return 1;
7211         }
7212
7213         if (vmx->nested.vmxon) {
7214                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7215                 return kvm_skip_emulated_instruction(vcpu);
7216         }
7217
7218         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7219                         != VMXON_NEEDED_FEATURES) {
7220                 kvm_inject_gp(vcpu, 0);
7221                 return 1;
7222         }
7223
7224         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7225                 return 1;
7226
7227         ret = enter_vmx_operation(vcpu);
7228         if (ret)
7229                 return ret;
7230
7231         nested_vmx_succeed(vcpu);
7232         return kvm_skip_emulated_instruction(vcpu);
7233 }
7234
7235 /*
7236  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7237  * for running VMX instructions (except VMXON, whose prerequisites are
7238  * slightly different). It also specifies what exception to inject otherwise.
7239  */
7240 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7241 {
7242         struct kvm_segment cs;
7243         struct vcpu_vmx *vmx = to_vmx(vcpu);
7244
7245         if (!vmx->nested.vmxon) {
7246                 kvm_queue_exception(vcpu, UD_VECTOR);
7247                 return 0;
7248         }
7249
7250         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7251         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7252             (is_long_mode(vcpu) && !cs.l)) {
7253                 kvm_queue_exception(vcpu, UD_VECTOR);
7254                 return 0;
7255         }
7256
7257         if (vmx_get_cpl(vcpu)) {
7258                 kvm_inject_gp(vcpu, 0);
7259                 return 0;
7260         }
7261
7262         return 1;
7263 }
7264
7265 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7266 {
7267         if (vmx->nested.current_vmptr == -1ull)
7268                 return;
7269
7270         /* current_vmptr and current_vmcs12 are always set/reset together */
7271         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7272                 return;
7273
7274         if (enable_shadow_vmcs) {
7275                 /* copy to memory all shadowed fields in case
7276                    they were modified */
7277                 copy_shadow_to_vmcs12(vmx);
7278                 vmx->nested.sync_shadow_vmcs = false;
7279                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7280                                 SECONDARY_EXEC_SHADOW_VMCS);
7281                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7282         }
7283         vmx->nested.posted_intr_nv = -1;
7284
7285         /* Flush VMCS12 to guest memory */
7286         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7287                VMCS12_SIZE);
7288
7289         kunmap(vmx->nested.current_vmcs12_page);
7290         nested_release_page(vmx->nested.current_vmcs12_page);
7291         vmx->nested.current_vmptr = -1ull;
7292         vmx->nested.current_vmcs12 = NULL;
7293 }
7294
7295 /*
7296  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7297  * just stops using VMX.
7298  */
7299 static void free_nested(struct vcpu_vmx *vmx)
7300 {
7301         if (!vmx->nested.vmxon)
7302                 return;
7303
7304         vmx->nested.vmxon = false;
7305         free_vpid(vmx->nested.vpid02);
7306         nested_release_vmcs12(vmx);
7307         if (vmx->nested.msr_bitmap) {
7308                 free_page((unsigned long)vmx->nested.msr_bitmap);
7309                 vmx->nested.msr_bitmap = NULL;
7310         }
7311         if (enable_shadow_vmcs) {
7312                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7313                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7314                 vmx->vmcs01.shadow_vmcs = NULL;
7315         }
7316         kfree(vmx->nested.cached_vmcs12);
7317         /* Unpin physical memory we referred to in current vmcs02 */
7318         if (vmx->nested.apic_access_page) {
7319                 nested_release_page(vmx->nested.apic_access_page);
7320                 vmx->nested.apic_access_page = NULL;
7321         }
7322         if (vmx->nested.virtual_apic_page) {
7323                 nested_release_page(vmx->nested.virtual_apic_page);
7324                 vmx->nested.virtual_apic_page = NULL;
7325         }
7326         if (vmx->nested.pi_desc_page) {
7327                 kunmap(vmx->nested.pi_desc_page);
7328                 nested_release_page(vmx->nested.pi_desc_page);
7329                 vmx->nested.pi_desc_page = NULL;
7330                 vmx->nested.pi_desc = NULL;
7331         }
7332
7333         nested_free_all_saved_vmcss(vmx);
7334 }
7335
7336 /* Emulate the VMXOFF instruction */
7337 static int handle_vmoff(struct kvm_vcpu *vcpu)
7338 {
7339         if (!nested_vmx_check_permission(vcpu))
7340                 return 1;
7341         free_nested(to_vmx(vcpu));
7342         nested_vmx_succeed(vcpu);
7343         return kvm_skip_emulated_instruction(vcpu);
7344 }
7345
7346 /* Emulate the VMCLEAR instruction */
7347 static int handle_vmclear(struct kvm_vcpu *vcpu)
7348 {
7349         struct vcpu_vmx *vmx = to_vmx(vcpu);
7350         gpa_t vmptr;
7351         struct vmcs12 *vmcs12;
7352         struct page *page;
7353
7354         if (!nested_vmx_check_permission(vcpu))
7355                 return 1;
7356
7357         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7358                 return 1;
7359
7360         if (vmptr == vmx->nested.current_vmptr)
7361                 nested_release_vmcs12(vmx);
7362
7363         page = nested_get_page(vcpu, vmptr);
7364         if (page == NULL) {
7365                 /*
7366                  * For accurate processor emulation, VMCLEAR beyond available
7367                  * physical memory should do nothing at all. However, it is
7368                  * possible that a nested vmx bug, not a guest hypervisor bug,
7369                  * resulted in this case, so let's shut down before doing any
7370                  * more damage:
7371                  */
7372                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7373                 return 1;
7374         }
7375         vmcs12 = kmap(page);
7376         vmcs12->launch_state = 0;
7377         kunmap(page);
7378         nested_release_page(page);
7379
7380         nested_free_vmcs02(vmx, vmptr);
7381
7382         nested_vmx_succeed(vcpu);
7383         return kvm_skip_emulated_instruction(vcpu);
7384 }
7385
7386 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7387
7388 /* Emulate the VMLAUNCH instruction */
7389 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7390 {
7391         return nested_vmx_run(vcpu, true);
7392 }
7393
7394 /* Emulate the VMRESUME instruction */
7395 static int handle_vmresume(struct kvm_vcpu *vcpu)
7396 {
7397
7398         return nested_vmx_run(vcpu, false);
7399 }
7400
7401 enum vmcs_field_type {
7402         VMCS_FIELD_TYPE_U16 = 0,
7403         VMCS_FIELD_TYPE_U64 = 1,
7404         VMCS_FIELD_TYPE_U32 = 2,
7405         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7406 };
7407
7408 static inline int vmcs_field_type(unsigned long field)
7409 {
7410         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7411                 return VMCS_FIELD_TYPE_U32;
7412         return (field >> 13) & 0x3 ;
7413 }
7414
7415 static inline int vmcs_field_readonly(unsigned long field)
7416 {
7417         return (((field >> 10) & 0x3) == 1);
7418 }
7419
7420 /*
7421  * Read a vmcs12 field. Since these can have varying lengths and we return
7422  * one type, we chose the biggest type (u64) and zero-extend the return value
7423  * to that size. Note that the caller, handle_vmread, might need to use only
7424  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7425  * 64-bit fields are to be returned).
7426  */
7427 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7428                                   unsigned long field, u64 *ret)
7429 {
7430         short offset = vmcs_field_to_offset(field);
7431         char *p;
7432
7433         if (offset < 0)
7434                 return offset;
7435
7436         p = ((char *)(get_vmcs12(vcpu))) + offset;
7437
7438         switch (vmcs_field_type(field)) {
7439         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7440                 *ret = *((natural_width *)p);
7441                 return 0;
7442         case VMCS_FIELD_TYPE_U16:
7443                 *ret = *((u16 *)p);
7444                 return 0;
7445         case VMCS_FIELD_TYPE_U32:
7446                 *ret = *((u32 *)p);
7447                 return 0;
7448         case VMCS_FIELD_TYPE_U64:
7449                 *ret = *((u64 *)p);
7450                 return 0;
7451         default:
7452                 WARN_ON(1);
7453                 return -ENOENT;
7454         }
7455 }
7456
7457
7458 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7459                                    unsigned long field, u64 field_value){
7460         short offset = vmcs_field_to_offset(field);
7461         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7462         if (offset < 0)
7463                 return offset;
7464
7465         switch (vmcs_field_type(field)) {
7466         case VMCS_FIELD_TYPE_U16:
7467                 *(u16 *)p = field_value;
7468                 return 0;
7469         case VMCS_FIELD_TYPE_U32:
7470                 *(u32 *)p = field_value;
7471                 return 0;
7472         case VMCS_FIELD_TYPE_U64:
7473                 *(u64 *)p = field_value;
7474                 return 0;
7475         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7476                 *(natural_width *)p = field_value;
7477                 return 0;
7478         default:
7479                 WARN_ON(1);
7480                 return -ENOENT;
7481         }
7482
7483 }
7484
7485 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7486 {
7487         int i;
7488         unsigned long field;
7489         u64 field_value;
7490         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7491         const unsigned long *fields = shadow_read_write_fields;
7492         const int num_fields = max_shadow_read_write_fields;
7493
7494         preempt_disable();
7495
7496         vmcs_load(shadow_vmcs);
7497
7498         for (i = 0; i < num_fields; i++) {
7499                 field = fields[i];
7500                 switch (vmcs_field_type(field)) {
7501                 case VMCS_FIELD_TYPE_U16:
7502                         field_value = vmcs_read16(field);
7503                         break;
7504                 case VMCS_FIELD_TYPE_U32:
7505                         field_value = vmcs_read32(field);
7506                         break;
7507                 case VMCS_FIELD_TYPE_U64:
7508                         field_value = vmcs_read64(field);
7509                         break;
7510                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7511                         field_value = vmcs_readl(field);
7512                         break;
7513                 default:
7514                         WARN_ON(1);
7515                         continue;
7516                 }
7517                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7518         }
7519
7520         vmcs_clear(shadow_vmcs);
7521         vmcs_load(vmx->loaded_vmcs->vmcs);
7522
7523         preempt_enable();
7524 }
7525
7526 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7527 {
7528         const unsigned long *fields[] = {
7529                 shadow_read_write_fields,
7530                 shadow_read_only_fields
7531         };
7532         const int max_fields[] = {
7533                 max_shadow_read_write_fields,
7534                 max_shadow_read_only_fields
7535         };
7536         int i, q;
7537         unsigned long field;
7538         u64 field_value = 0;
7539         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7540
7541         vmcs_load(shadow_vmcs);
7542
7543         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7544                 for (i = 0; i < max_fields[q]; i++) {
7545                         field = fields[q][i];
7546                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7547
7548                         switch (vmcs_field_type(field)) {
7549                         case VMCS_FIELD_TYPE_U16:
7550                                 vmcs_write16(field, (u16)field_value);
7551                                 break;
7552                         case VMCS_FIELD_TYPE_U32:
7553                                 vmcs_write32(field, (u32)field_value);
7554                                 break;
7555                         case VMCS_FIELD_TYPE_U64:
7556                                 vmcs_write64(field, (u64)field_value);
7557                                 break;
7558                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7559                                 vmcs_writel(field, (long)field_value);
7560                                 break;
7561                         default:
7562                                 WARN_ON(1);
7563                                 break;
7564                         }
7565                 }
7566         }
7567
7568         vmcs_clear(shadow_vmcs);
7569         vmcs_load(vmx->loaded_vmcs->vmcs);
7570 }
7571
7572 /*
7573  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7574  * used before) all generate the same failure when it is missing.
7575  */
7576 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7577 {
7578         struct vcpu_vmx *vmx = to_vmx(vcpu);
7579         if (vmx->nested.current_vmptr == -1ull) {
7580                 nested_vmx_failInvalid(vcpu);
7581                 return 0;
7582         }
7583         return 1;
7584 }
7585
7586 static int handle_vmread(struct kvm_vcpu *vcpu)
7587 {
7588         unsigned long field;
7589         u64 field_value;
7590         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7591         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7592         gva_t gva = 0;
7593
7594         if (!nested_vmx_check_permission(vcpu))
7595                 return 1;
7596
7597         if (!nested_vmx_check_vmcs12(vcpu))
7598                 return kvm_skip_emulated_instruction(vcpu);
7599
7600         /* Decode instruction info and find the field to read */
7601         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7602         /* Read the field, zero-extended to a u64 field_value */
7603         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7604                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7605                 return kvm_skip_emulated_instruction(vcpu);
7606         }
7607         /*
7608          * Now copy part of this value to register or memory, as requested.
7609          * Note that the number of bits actually copied is 32 or 64 depending
7610          * on the guest's mode (32 or 64 bit), not on the given field's length.
7611          */
7612         if (vmx_instruction_info & (1u << 10)) {
7613                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7614                         field_value);
7615         } else {
7616                 if (get_vmx_mem_address(vcpu, exit_qualification,
7617                                 vmx_instruction_info, true, &gva))
7618                         return 1;
7619                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7620                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7621                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7622         }
7623
7624         nested_vmx_succeed(vcpu);
7625         return kvm_skip_emulated_instruction(vcpu);
7626 }
7627
7628
7629 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7630 {
7631         unsigned long field;
7632         gva_t gva;
7633         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7634         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7635         /* The value to write might be 32 or 64 bits, depending on L1's long
7636          * mode, and eventually we need to write that into a field of several
7637          * possible lengths. The code below first zero-extends the value to 64
7638          * bit (field_value), and then copies only the appropriate number of
7639          * bits into the vmcs12 field.
7640          */
7641         u64 field_value = 0;
7642         struct x86_exception e;
7643
7644         if (!nested_vmx_check_permission(vcpu))
7645                 return 1;
7646
7647         if (!nested_vmx_check_vmcs12(vcpu))
7648                 return kvm_skip_emulated_instruction(vcpu);
7649
7650         if (vmx_instruction_info & (1u << 10))
7651                 field_value = kvm_register_readl(vcpu,
7652                         (((vmx_instruction_info) >> 3) & 0xf));
7653         else {
7654                 if (get_vmx_mem_address(vcpu, exit_qualification,
7655                                 vmx_instruction_info, false, &gva))
7656                         return 1;
7657                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7658                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7659                         kvm_inject_page_fault(vcpu, &e);
7660                         return 1;
7661                 }
7662         }
7663
7664
7665         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7666         if (vmcs_field_readonly(field)) {
7667                 nested_vmx_failValid(vcpu,
7668                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7669                 return kvm_skip_emulated_instruction(vcpu);
7670         }
7671
7672         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7673                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7674                 return kvm_skip_emulated_instruction(vcpu);
7675         }
7676
7677         nested_vmx_succeed(vcpu);
7678         return kvm_skip_emulated_instruction(vcpu);
7679 }
7680
7681 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7682 {
7683         vmx->nested.current_vmptr = vmptr;
7684         if (enable_shadow_vmcs) {
7685                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7686                               SECONDARY_EXEC_SHADOW_VMCS);
7687                 vmcs_write64(VMCS_LINK_POINTER,
7688                              __pa(vmx->vmcs01.shadow_vmcs));
7689                 vmx->nested.sync_shadow_vmcs = true;
7690         }
7691 }
7692
7693 /* Emulate the VMPTRLD instruction */
7694 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7695 {
7696         struct vcpu_vmx *vmx = to_vmx(vcpu);
7697         gpa_t vmptr;
7698
7699         if (!nested_vmx_check_permission(vcpu))
7700                 return 1;
7701
7702         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7703                 return 1;
7704
7705         if (vmx->nested.current_vmptr != vmptr) {
7706                 struct vmcs12 *new_vmcs12;
7707                 struct page *page;
7708                 page = nested_get_page(vcpu, vmptr);
7709                 if (page == NULL) {
7710                         nested_vmx_failInvalid(vcpu);
7711                         return kvm_skip_emulated_instruction(vcpu);
7712                 }
7713                 new_vmcs12 = kmap(page);
7714                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7715                         kunmap(page);
7716                         nested_release_page_clean(page);
7717                         nested_vmx_failValid(vcpu,
7718                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7719                         return kvm_skip_emulated_instruction(vcpu);
7720                 }
7721
7722                 nested_release_vmcs12(vmx);
7723                 vmx->nested.current_vmcs12 = new_vmcs12;
7724                 vmx->nested.current_vmcs12_page = page;
7725                 /*
7726                  * Load VMCS12 from guest memory since it is not already
7727                  * cached.
7728                  */
7729                 memcpy(vmx->nested.cached_vmcs12,
7730                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7731                 set_current_vmptr(vmx, vmptr);
7732         }
7733
7734         nested_vmx_succeed(vcpu);
7735         return kvm_skip_emulated_instruction(vcpu);
7736 }
7737
7738 /* Emulate the VMPTRST instruction */
7739 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7740 {
7741         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7742         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7743         gva_t vmcs_gva;
7744         struct x86_exception e;
7745
7746         if (!nested_vmx_check_permission(vcpu))
7747                 return 1;
7748
7749         if (get_vmx_mem_address(vcpu, exit_qualification,
7750                         vmx_instruction_info, true, &vmcs_gva))
7751                 return 1;
7752         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7753         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7754                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7755                                  sizeof(u64), &e)) {
7756                 kvm_inject_page_fault(vcpu, &e);
7757                 return 1;
7758         }
7759         nested_vmx_succeed(vcpu);
7760         return kvm_skip_emulated_instruction(vcpu);
7761 }
7762
7763 /* Emulate the INVEPT instruction */
7764 static int handle_invept(struct kvm_vcpu *vcpu)
7765 {
7766         struct vcpu_vmx *vmx = to_vmx(vcpu);
7767         u32 vmx_instruction_info, types;
7768         unsigned long type;
7769         gva_t gva;
7770         struct x86_exception e;
7771         struct {
7772                 u64 eptp, gpa;
7773         } operand;
7774
7775         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7776               SECONDARY_EXEC_ENABLE_EPT) ||
7777             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7778                 kvm_queue_exception(vcpu, UD_VECTOR);
7779                 return 1;
7780         }
7781
7782         if (!nested_vmx_check_permission(vcpu))
7783                 return 1;
7784
7785         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7786                 kvm_queue_exception(vcpu, UD_VECTOR);
7787                 return 1;
7788         }
7789
7790         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7791         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7792
7793         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7794
7795         if (type >= 32 || !(types & (1 << type))) {
7796                 nested_vmx_failValid(vcpu,
7797                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7798                 return kvm_skip_emulated_instruction(vcpu);
7799         }
7800
7801         /* According to the Intel VMX instruction reference, the memory
7802          * operand is read even if it isn't needed (e.g., for type==global)
7803          */
7804         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7805                         vmx_instruction_info, false, &gva))
7806                 return 1;
7807         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7808                                 sizeof(operand), &e)) {
7809                 kvm_inject_page_fault(vcpu, &e);
7810                 return 1;
7811         }
7812
7813         switch (type) {
7814         case VMX_EPT_EXTENT_GLOBAL:
7815         /*
7816          * TODO: track mappings and invalidate
7817          * single context requests appropriately
7818          */
7819         case VMX_EPT_EXTENT_CONTEXT:
7820                 kvm_mmu_sync_roots(vcpu);
7821                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7822                 nested_vmx_succeed(vcpu);
7823                 break;
7824         default:
7825                 BUG_ON(1);
7826                 break;
7827         }
7828
7829         return kvm_skip_emulated_instruction(vcpu);
7830 }
7831
7832 static int handle_invvpid(struct kvm_vcpu *vcpu)
7833 {
7834         struct vcpu_vmx *vmx = to_vmx(vcpu);
7835         u32 vmx_instruction_info;
7836         unsigned long type, types;
7837         gva_t gva;
7838         struct x86_exception e;
7839         int vpid;
7840
7841         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7842               SECONDARY_EXEC_ENABLE_VPID) ||
7843                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7844                 kvm_queue_exception(vcpu, UD_VECTOR);
7845                 return 1;
7846         }
7847
7848         if (!nested_vmx_check_permission(vcpu))
7849                 return 1;
7850
7851         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7852         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7853
7854         types = (vmx->nested.nested_vmx_vpid_caps &
7855                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7856
7857         if (type >= 32 || !(types & (1 << type))) {
7858                 nested_vmx_failValid(vcpu,
7859                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7860                 return kvm_skip_emulated_instruction(vcpu);
7861         }
7862
7863         /* according to the intel vmx instruction reference, the memory
7864          * operand is read even if it isn't needed (e.g., for type==global)
7865          */
7866         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7867                         vmx_instruction_info, false, &gva))
7868                 return 1;
7869         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7870                                 sizeof(u32), &e)) {
7871                 kvm_inject_page_fault(vcpu, &e);
7872                 return 1;
7873         }
7874
7875         switch (type) {
7876         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7877         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7878         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7879                 if (!vpid) {
7880                         nested_vmx_failValid(vcpu,
7881                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7882                         return kvm_skip_emulated_instruction(vcpu);
7883                 }
7884                 break;
7885         case VMX_VPID_EXTENT_ALL_CONTEXT:
7886                 break;
7887         default:
7888                 WARN_ON_ONCE(1);
7889                 return kvm_skip_emulated_instruction(vcpu);
7890         }
7891
7892         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7893         nested_vmx_succeed(vcpu);
7894
7895         return kvm_skip_emulated_instruction(vcpu);
7896 }
7897
7898 static int handle_pml_full(struct kvm_vcpu *vcpu)
7899 {
7900         unsigned long exit_qualification;
7901
7902         trace_kvm_pml_full(vcpu->vcpu_id);
7903
7904         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7905
7906         /*
7907          * PML buffer FULL happened while executing iret from NMI,
7908          * "blocked by NMI" bit has to be set before next VM entry.
7909          */
7910         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7911                         cpu_has_virtual_nmis() &&
7912                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7913                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7914                                 GUEST_INTR_STATE_NMI);
7915
7916         /*
7917          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7918          * here.., and there's no userspace involvement needed for PML.
7919          */
7920         return 1;
7921 }
7922
7923 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7924 {
7925         kvm_lapic_expired_hv_timer(vcpu);
7926         return 1;
7927 }
7928
7929 /*
7930  * The exit handlers return 1 if the exit was handled fully and guest execution
7931  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7932  * to be done to userspace and return 0.
7933  */
7934 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7935         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7936         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7937         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7938         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7939         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7940         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7941         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7942         [EXIT_REASON_CPUID]                   = handle_cpuid,
7943         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7944         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7945         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7946         [EXIT_REASON_HLT]                     = handle_halt,
7947         [EXIT_REASON_INVD]                    = handle_invd,
7948         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7949         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7950         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7951         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7952         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7953         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7954         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7955         [EXIT_REASON_VMREAD]                  = handle_vmread,
7956         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7957         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7958         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7959         [EXIT_REASON_VMON]                    = handle_vmon,
7960         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7961         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7962         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7963         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7964         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7965         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7966         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7967         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7968         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7969         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7970         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7971         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7972         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7973         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7974         [EXIT_REASON_INVEPT]                  = handle_invept,
7975         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7976         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7977         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7978         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7979         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7980 };
7981
7982 static const int kvm_vmx_max_exit_handlers =
7983         ARRAY_SIZE(kvm_vmx_exit_handlers);
7984
7985 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7986                                        struct vmcs12 *vmcs12)
7987 {
7988         unsigned long exit_qualification;
7989         gpa_t bitmap, last_bitmap;
7990         unsigned int port;
7991         int size;
7992         u8 b;
7993
7994         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7995                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7996
7997         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7998
7999         port = exit_qualification >> 16;
8000         size = (exit_qualification & 7) + 1;
8001
8002         last_bitmap = (gpa_t)-1;
8003         b = -1;
8004
8005         while (size > 0) {
8006                 if (port < 0x8000)
8007                         bitmap = vmcs12->io_bitmap_a;
8008                 else if (port < 0x10000)
8009                         bitmap = vmcs12->io_bitmap_b;
8010                 else
8011                         return true;
8012                 bitmap += (port & 0x7fff) / 8;
8013
8014                 if (last_bitmap != bitmap)
8015                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8016                                 return true;
8017                 if (b & (1 << (port & 7)))
8018                         return true;
8019
8020                 port++;
8021                 size--;
8022                 last_bitmap = bitmap;
8023         }
8024
8025         return false;
8026 }
8027
8028 /*
8029  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8030  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8031  * disinterest in the current event (read or write a specific MSR) by using an
8032  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8033  */
8034 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8035         struct vmcs12 *vmcs12, u32 exit_reason)
8036 {
8037         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8038         gpa_t bitmap;
8039
8040         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8041                 return true;
8042
8043         /*
8044          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8045          * for the four combinations of read/write and low/high MSR numbers.
8046          * First we need to figure out which of the four to use:
8047          */
8048         bitmap = vmcs12->msr_bitmap;
8049         if (exit_reason == EXIT_REASON_MSR_WRITE)
8050                 bitmap += 2048;
8051         if (msr_index >= 0xc0000000) {
8052                 msr_index -= 0xc0000000;
8053                 bitmap += 1024;
8054         }
8055
8056         /* Then read the msr_index'th bit from this bitmap: */
8057         if (msr_index < 1024*8) {
8058                 unsigned char b;
8059                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8060                         return true;
8061                 return 1 & (b >> (msr_index & 7));
8062         } else
8063                 return true; /* let L1 handle the wrong parameter */
8064 }
8065
8066 /*
8067  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8068  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8069  * intercept (via guest_host_mask etc.) the current event.
8070  */
8071 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8072         struct vmcs12 *vmcs12)
8073 {
8074         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8075         int cr = exit_qualification & 15;
8076         int reg = (exit_qualification >> 8) & 15;
8077         unsigned long val = kvm_register_readl(vcpu, reg);
8078
8079         switch ((exit_qualification >> 4) & 3) {
8080         case 0: /* mov to cr */
8081                 switch (cr) {
8082                 case 0:
8083                         if (vmcs12->cr0_guest_host_mask &
8084                             (val ^ vmcs12->cr0_read_shadow))
8085                                 return true;
8086                         break;
8087                 case 3:
8088                         if ((vmcs12->cr3_target_count >= 1 &&
8089                                         vmcs12->cr3_target_value0 == val) ||
8090                                 (vmcs12->cr3_target_count >= 2 &&
8091                                         vmcs12->cr3_target_value1 == val) ||
8092                                 (vmcs12->cr3_target_count >= 3 &&
8093                                         vmcs12->cr3_target_value2 == val) ||
8094                                 (vmcs12->cr3_target_count >= 4 &&
8095                                         vmcs12->cr3_target_value3 == val))
8096                                 return false;
8097                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8098                                 return true;
8099                         break;
8100                 case 4:
8101                         if (vmcs12->cr4_guest_host_mask &
8102                             (vmcs12->cr4_read_shadow ^ val))
8103                                 return true;
8104                         break;
8105                 case 8:
8106                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8107                                 return true;
8108                         break;
8109                 }
8110                 break;
8111         case 2: /* clts */
8112                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8113                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8114                         return true;
8115                 break;
8116         case 1: /* mov from cr */
8117                 switch (cr) {
8118                 case 3:
8119                         if (vmcs12->cpu_based_vm_exec_control &
8120                             CPU_BASED_CR3_STORE_EXITING)
8121                                 return true;
8122                         break;
8123                 case 8:
8124                         if (vmcs12->cpu_based_vm_exec_control &
8125                             CPU_BASED_CR8_STORE_EXITING)
8126                                 return true;
8127                         break;
8128                 }
8129                 break;
8130         case 3: /* lmsw */
8131                 /*
8132                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8133                  * cr0. Other attempted changes are ignored, with no exit.
8134                  */
8135                 if (vmcs12->cr0_guest_host_mask & 0xe &
8136                     (val ^ vmcs12->cr0_read_shadow))
8137                         return true;
8138                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8139                     !(vmcs12->cr0_read_shadow & 0x1) &&
8140                     (val & 0x1))
8141                         return true;
8142                 break;
8143         }
8144         return false;
8145 }
8146
8147 /*
8148  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8149  * should handle it ourselves in L0 (and then continue L2). Only call this
8150  * when in is_guest_mode (L2).
8151  */
8152 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8153 {
8154         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8155         struct vcpu_vmx *vmx = to_vmx(vcpu);
8156         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8157         u32 exit_reason = vmx->exit_reason;
8158
8159         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8160                                 vmcs_readl(EXIT_QUALIFICATION),
8161                                 vmx->idt_vectoring_info,
8162                                 intr_info,
8163                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8164                                 KVM_ISA_VMX);
8165
8166         if (vmx->nested.nested_run_pending)
8167                 return false;
8168
8169         if (unlikely(vmx->fail)) {
8170                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8171                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8172                 return true;
8173         }
8174
8175         switch (exit_reason) {
8176         case EXIT_REASON_EXCEPTION_NMI:
8177                 if (is_nmi(intr_info))
8178                         return false;
8179                 else if (is_page_fault(intr_info))
8180                         return enable_ept;
8181                 else if (is_no_device(intr_info) &&
8182                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8183                         return false;
8184                 else if (is_debug(intr_info) &&
8185                          vcpu->guest_debug &
8186                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8187                         return false;
8188                 else if (is_breakpoint(intr_info) &&
8189                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8190                         return false;
8191                 return vmcs12->exception_bitmap &
8192                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8193         case EXIT_REASON_EXTERNAL_INTERRUPT:
8194                 return false;
8195         case EXIT_REASON_TRIPLE_FAULT:
8196                 return true;
8197         case EXIT_REASON_PENDING_INTERRUPT:
8198                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8199         case EXIT_REASON_NMI_WINDOW:
8200                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8201         case EXIT_REASON_TASK_SWITCH:
8202                 return true;
8203         case EXIT_REASON_CPUID:
8204                 return true;
8205         case EXIT_REASON_HLT:
8206                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8207         case EXIT_REASON_INVD:
8208                 return true;
8209         case EXIT_REASON_INVLPG:
8210                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8211         case EXIT_REASON_RDPMC:
8212                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8213         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8214                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8215         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8216         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8217         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8218         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8219         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8220         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8221                 /*
8222                  * VMX instructions trap unconditionally. This allows L1 to
8223                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8224                  */
8225                 return true;
8226         case EXIT_REASON_CR_ACCESS:
8227                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8228         case EXIT_REASON_DR_ACCESS:
8229                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8230         case EXIT_REASON_IO_INSTRUCTION:
8231                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8232         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8233                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8234         case EXIT_REASON_MSR_READ:
8235         case EXIT_REASON_MSR_WRITE:
8236                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8237         case EXIT_REASON_INVALID_STATE:
8238                 return true;
8239         case EXIT_REASON_MWAIT_INSTRUCTION:
8240                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8241         case EXIT_REASON_MONITOR_TRAP_FLAG:
8242                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8243         case EXIT_REASON_MONITOR_INSTRUCTION:
8244                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8245         case EXIT_REASON_PAUSE_INSTRUCTION:
8246                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8247                         nested_cpu_has2(vmcs12,
8248                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8249         case EXIT_REASON_MCE_DURING_VMENTRY:
8250                 return false;
8251         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8252                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8253         case EXIT_REASON_APIC_ACCESS:
8254                 return nested_cpu_has2(vmcs12,
8255                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8256         case EXIT_REASON_APIC_WRITE:
8257         case EXIT_REASON_EOI_INDUCED:
8258                 /* apic_write and eoi_induced should exit unconditionally. */
8259                 return true;
8260         case EXIT_REASON_EPT_VIOLATION:
8261                 /*
8262                  * L0 always deals with the EPT violation. If nested EPT is
8263                  * used, and the nested mmu code discovers that the address is
8264                  * missing in the guest EPT table (EPT12), the EPT violation
8265                  * will be injected with nested_ept_inject_page_fault()
8266                  */
8267                 return false;
8268         case EXIT_REASON_EPT_MISCONFIG:
8269                 /*
8270                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8271                  * table (shadow on EPT) or a merged EPT table that L0 built
8272                  * (EPT on EPT). So any problems with the structure of the
8273                  * table is L0's fault.
8274                  */
8275                 return false;
8276         case EXIT_REASON_WBINVD:
8277                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8278         case EXIT_REASON_XSETBV:
8279                 return true;
8280         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8281                 /*
8282                  * This should never happen, since it is not possible to
8283                  * set XSS to a non-zero value---neither in L1 nor in L2.
8284                  * If if it were, XSS would have to be checked against
8285                  * the XSS exit bitmap in vmcs12.
8286                  */
8287                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8288         case EXIT_REASON_PREEMPTION_TIMER:
8289                 return false;
8290         default:
8291                 return true;
8292         }
8293 }
8294
8295 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8296 {
8297         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8298         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8299 }
8300
8301 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8302 {
8303         if (vmx->pml_pg) {
8304                 __free_page(vmx->pml_pg);
8305                 vmx->pml_pg = NULL;
8306         }
8307 }
8308
8309 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8310 {
8311         struct vcpu_vmx *vmx = to_vmx(vcpu);
8312         u64 *pml_buf;
8313         u16 pml_idx;
8314
8315         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8316
8317         /* Do nothing if PML buffer is empty */
8318         if (pml_idx == (PML_ENTITY_NUM - 1))
8319                 return;
8320
8321         /* PML index always points to next available PML buffer entity */
8322         if (pml_idx >= PML_ENTITY_NUM)
8323                 pml_idx = 0;
8324         else
8325                 pml_idx++;
8326
8327         pml_buf = page_address(vmx->pml_pg);
8328         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8329                 u64 gpa;
8330
8331                 gpa = pml_buf[pml_idx];
8332                 WARN_ON(gpa & (PAGE_SIZE - 1));
8333                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8334         }
8335
8336         /* reset PML index */
8337         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8338 }
8339
8340 /*
8341  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8342  * Called before reporting dirty_bitmap to userspace.
8343  */
8344 static void kvm_flush_pml_buffers(struct kvm *kvm)
8345 {
8346         int i;
8347         struct kvm_vcpu *vcpu;
8348         /*
8349          * We only need to kick vcpu out of guest mode here, as PML buffer
8350          * is flushed at beginning of all VMEXITs, and it's obvious that only
8351          * vcpus running in guest are possible to have unflushed GPAs in PML
8352          * buffer.
8353          */
8354         kvm_for_each_vcpu(i, vcpu, kvm)
8355                 kvm_vcpu_kick(vcpu);
8356 }
8357
8358 static void vmx_dump_sel(char *name, uint32_t sel)
8359 {
8360         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8361                name, vmcs_read32(sel),
8362                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8363                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8364                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8365 }
8366
8367 static void vmx_dump_dtsel(char *name, uint32_t limit)
8368 {
8369         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8370                name, vmcs_read32(limit),
8371                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8372 }
8373
8374 static void dump_vmcs(void)
8375 {
8376         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8377         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8378         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8379         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8380         u32 secondary_exec_control = 0;
8381         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8382         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8383         int i, n;
8384
8385         if (cpu_has_secondary_exec_ctrls())
8386                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8387
8388         pr_err("*** Guest State ***\n");
8389         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8390                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8391                vmcs_readl(CR0_GUEST_HOST_MASK));
8392         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8393                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8394         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8395         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8396             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8397         {
8398                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8399                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8400                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8401                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8402         }
8403         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8404                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8405         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8406                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8407         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8408                vmcs_readl(GUEST_SYSENTER_ESP),
8409                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8410         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8411         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8412         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8413         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8414         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8415         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8416         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8417         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8418         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8419         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8420         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8421             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8422                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8423                        efer, vmcs_read64(GUEST_IA32_PAT));
8424         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8425                vmcs_read64(GUEST_IA32_DEBUGCTL),
8426                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8427         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8428                 pr_err("PerfGlobCtl = 0x%016llx\n",
8429                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8430         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8431                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8432         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8433                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8434                vmcs_read32(GUEST_ACTIVITY_STATE));
8435         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8436                 pr_err("InterruptStatus = %04x\n",
8437                        vmcs_read16(GUEST_INTR_STATUS));
8438
8439         pr_err("*** Host State ***\n");
8440         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8441                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8442         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8443                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8444                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8445                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8446                vmcs_read16(HOST_TR_SELECTOR));
8447         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8448                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8449                vmcs_readl(HOST_TR_BASE));
8450         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8451                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8452         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8453                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8454                vmcs_readl(HOST_CR4));
8455         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8456                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8457                vmcs_read32(HOST_IA32_SYSENTER_CS),
8458                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8459         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8460                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8461                        vmcs_read64(HOST_IA32_EFER),
8462                        vmcs_read64(HOST_IA32_PAT));
8463         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8464                 pr_err("PerfGlobCtl = 0x%016llx\n",
8465                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8466
8467         pr_err("*** Control State ***\n");
8468         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8469                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8470         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8471         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8472                vmcs_read32(EXCEPTION_BITMAP),
8473                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8474                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8475         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8476                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8477                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8478                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8479         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8480                vmcs_read32(VM_EXIT_INTR_INFO),
8481                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8482                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8483         pr_err("        reason=%08x qualification=%016lx\n",
8484                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8485         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8486                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8487                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8488         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8489         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8490                 pr_err("TSC Multiplier = 0x%016llx\n",
8491                        vmcs_read64(TSC_MULTIPLIER));
8492         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8493                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8494         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8495                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8496         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8497                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8498         n = vmcs_read32(CR3_TARGET_COUNT);
8499         for (i = 0; i + 1 < n; i += 4)
8500                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8501                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8502                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8503         if (i < n)
8504                 pr_err("CR3 target%u=%016lx\n",
8505                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8506         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8507                 pr_err("PLE Gap=%08x Window=%08x\n",
8508                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8509         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8510                 pr_err("Virtual processor ID = 0x%04x\n",
8511                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8512 }
8513
8514 /*
8515  * The guest has exited.  See if we can fix it or if we need userspace
8516  * assistance.
8517  */
8518 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8519 {
8520         struct vcpu_vmx *vmx = to_vmx(vcpu);
8521         u32 exit_reason = vmx->exit_reason;
8522         u32 vectoring_info = vmx->idt_vectoring_info;
8523
8524         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8525         vcpu->arch.gpa_available = false;
8526
8527         /*
8528          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8529          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8530          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8531          * mode as if vcpus is in root mode, the PML buffer must has been
8532          * flushed already.
8533          */
8534         if (enable_pml)
8535                 vmx_flush_pml_buffer(vcpu);
8536
8537         /* If guest state is invalid, start emulating */
8538         if (vmx->emulation_required)
8539                 return handle_invalid_guest_state(vcpu);
8540
8541         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8542                 nested_vmx_vmexit(vcpu, exit_reason,
8543                                   vmcs_read32(VM_EXIT_INTR_INFO),
8544                                   vmcs_readl(EXIT_QUALIFICATION));
8545                 return 1;
8546         }
8547
8548         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8549                 dump_vmcs();
8550                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8551                 vcpu->run->fail_entry.hardware_entry_failure_reason
8552                         = exit_reason;
8553                 return 0;
8554         }
8555
8556         if (unlikely(vmx->fail)) {
8557                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8558                 vcpu->run->fail_entry.hardware_entry_failure_reason
8559                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8560                 return 0;
8561         }
8562
8563         /*
8564          * Note:
8565          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8566          * delivery event since it indicates guest is accessing MMIO.
8567          * The vm-exit can be triggered again after return to guest that
8568          * will cause infinite loop.
8569          */
8570         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8571                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8572                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8573                         exit_reason != EXIT_REASON_PML_FULL &&
8574                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8575                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8576                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8577                 vcpu->run->internal.ndata = 2;
8578                 vcpu->run->internal.data[0] = vectoring_info;
8579                 vcpu->run->internal.data[1] = exit_reason;
8580                 return 0;
8581         }
8582
8583         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8584             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8585                                         get_vmcs12(vcpu))))) {
8586                 if (vmx_interrupt_allowed(vcpu)) {
8587                         vmx->soft_vnmi_blocked = 0;
8588                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8589                            vcpu->arch.nmi_pending) {
8590                         /*
8591                          * This CPU don't support us in finding the end of an
8592                          * NMI-blocked window if the guest runs with IRQs
8593                          * disabled. So we pull the trigger after 1 s of
8594                          * futile waiting, but inform the user about this.
8595                          */
8596                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8597                                "state on VCPU %d after 1 s timeout\n",
8598                                __func__, vcpu->vcpu_id);
8599                         vmx->soft_vnmi_blocked = 0;
8600                 }
8601         }
8602
8603         if (exit_reason < kvm_vmx_max_exit_handlers
8604             && kvm_vmx_exit_handlers[exit_reason])
8605                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8606         else {
8607                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8608                 kvm_queue_exception(vcpu, UD_VECTOR);
8609                 return 1;
8610         }
8611 }
8612
8613 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8614 {
8615         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8616
8617         if (is_guest_mode(vcpu) &&
8618                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8619                 return;
8620
8621         if (irr == -1 || tpr < irr) {
8622                 vmcs_write32(TPR_THRESHOLD, 0);
8623                 return;
8624         }
8625
8626         vmcs_write32(TPR_THRESHOLD, irr);
8627 }
8628
8629 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8630 {
8631         u32 sec_exec_control;
8632
8633         /* Postpone execution until vmcs01 is the current VMCS. */
8634         if (is_guest_mode(vcpu)) {
8635                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8636                 return;
8637         }
8638
8639         if (!cpu_has_vmx_virtualize_x2apic_mode())
8640                 return;
8641
8642         if (!cpu_need_tpr_shadow(vcpu))
8643                 return;
8644
8645         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8646
8647         if (set) {
8648                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8649                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8650         } else {
8651                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8652                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8653         }
8654         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8655
8656         vmx_set_msr_bitmap(vcpu);
8657 }
8658
8659 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8660 {
8661         struct vcpu_vmx *vmx = to_vmx(vcpu);
8662
8663         /*
8664          * Currently we do not handle the nested case where L2 has an
8665          * APIC access page of its own; that page is still pinned.
8666          * Hence, we skip the case where the VCPU is in guest mode _and_
8667          * L1 prepared an APIC access page for L2.
8668          *
8669          * For the case where L1 and L2 share the same APIC access page
8670          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8671          * in the vmcs12), this function will only update either the vmcs01
8672          * or the vmcs02.  If the former, the vmcs02 will be updated by
8673          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8674          * the next L2->L1 exit.
8675          */
8676         if (!is_guest_mode(vcpu) ||
8677             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8678                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8679                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8680 }
8681
8682 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8683 {
8684         u16 status;
8685         u8 old;
8686
8687         if (max_isr == -1)
8688                 max_isr = 0;
8689
8690         status = vmcs_read16(GUEST_INTR_STATUS);
8691         old = status >> 8;
8692         if (max_isr != old) {
8693                 status &= 0xff;
8694                 status |= max_isr << 8;
8695                 vmcs_write16(GUEST_INTR_STATUS, status);
8696         }
8697 }
8698
8699 static void vmx_set_rvi(int vector)
8700 {
8701         u16 status;
8702         u8 old;
8703
8704         if (vector == -1)
8705                 vector = 0;
8706
8707         status = vmcs_read16(GUEST_INTR_STATUS);
8708         old = (u8)status & 0xff;
8709         if ((u8)vector != old) {
8710                 status &= ~0xff;
8711                 status |= (u8)vector;
8712                 vmcs_write16(GUEST_INTR_STATUS, status);
8713         }
8714 }
8715
8716 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8717 {
8718         if (!is_guest_mode(vcpu)) {
8719                 vmx_set_rvi(max_irr);
8720                 return;
8721         }
8722
8723         if (max_irr == -1)
8724                 return;
8725
8726         /*
8727          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8728          * handles it.
8729          */
8730         if (nested_exit_on_intr(vcpu))
8731                 return;
8732
8733         /*
8734          * Else, fall back to pre-APICv interrupt injection since L2
8735          * is run without virtual interrupt delivery.
8736          */
8737         if (!kvm_event_needs_reinjection(vcpu) &&
8738             vmx_interrupt_allowed(vcpu)) {
8739                 kvm_queue_interrupt(vcpu, max_irr, false);
8740                 vmx_inject_irq(vcpu);
8741         }
8742 }
8743
8744 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8745 {
8746         struct vcpu_vmx *vmx = to_vmx(vcpu);
8747         int max_irr;
8748
8749         WARN_ON(!vcpu->arch.apicv_active);
8750         if (pi_test_on(&vmx->pi_desc)) {
8751                 pi_clear_on(&vmx->pi_desc);
8752                 /*
8753                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8754                  * But on x86 this is just a compiler barrier anyway.
8755                  */
8756                 smp_mb__after_atomic();
8757                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8758         } else {
8759                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8760         }
8761         vmx_hwapic_irr_update(vcpu, max_irr);
8762         return max_irr;
8763 }
8764
8765 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8766 {
8767         if (!kvm_vcpu_apicv_active(vcpu))
8768                 return;
8769
8770         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8771         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8772         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8773         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8774 }
8775
8776 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8777 {
8778         struct vcpu_vmx *vmx = to_vmx(vcpu);
8779
8780         pi_clear_on(&vmx->pi_desc);
8781         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8782 }
8783
8784 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8785 {
8786         u32 exit_intr_info;
8787
8788         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8789               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8790                 return;
8791
8792         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8793         exit_intr_info = vmx->exit_intr_info;
8794
8795         /* Handle machine checks before interrupts are enabled */
8796         if (is_machine_check(exit_intr_info))
8797                 kvm_machine_check();
8798
8799         /* We need to handle NMIs before interrupts are enabled */
8800         if (is_nmi(exit_intr_info)) {
8801                 kvm_before_handle_nmi(&vmx->vcpu);
8802                 asm("int $2");
8803                 kvm_after_handle_nmi(&vmx->vcpu);
8804         }
8805 }
8806
8807 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8808 {
8809         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8810         register void *__sp asm(_ASM_SP);
8811
8812         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8813                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8814                 unsigned int vector;
8815                 unsigned long entry;
8816                 gate_desc *desc;
8817                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8818 #ifdef CONFIG_X86_64
8819                 unsigned long tmp;
8820 #endif
8821
8822                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8823                 desc = (gate_desc *)vmx->host_idt_base + vector;
8824                 entry = gate_offset(*desc);
8825                 asm volatile(
8826 #ifdef CONFIG_X86_64
8827                         "mov %%" _ASM_SP ", %[sp]\n\t"
8828                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8829                         "push $%c[ss]\n\t"
8830                         "push %[sp]\n\t"
8831 #endif
8832                         "pushf\n\t"
8833                         __ASM_SIZE(push) " $%c[cs]\n\t"
8834                         "call *%[entry]\n\t"
8835                         :
8836 #ifdef CONFIG_X86_64
8837                         [sp]"=&r"(tmp),
8838 #endif
8839                         "+r"(__sp)
8840                         :
8841                         [entry]"r"(entry),
8842                         [ss]"i"(__KERNEL_DS),
8843                         [cs]"i"(__KERNEL_CS)
8844                         );
8845         }
8846 }
8847
8848 static bool vmx_has_high_real_mode_segbase(void)
8849 {
8850         return enable_unrestricted_guest || emulate_invalid_guest_state;
8851 }
8852
8853 static bool vmx_mpx_supported(void)
8854 {
8855         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8856                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8857 }
8858
8859 static bool vmx_xsaves_supported(void)
8860 {
8861         return vmcs_config.cpu_based_2nd_exec_ctrl &
8862                 SECONDARY_EXEC_XSAVES;
8863 }
8864
8865 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8866 {
8867         u32 exit_intr_info;
8868         bool unblock_nmi;
8869         u8 vector;
8870         bool idtv_info_valid;
8871
8872         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8873
8874         if (cpu_has_virtual_nmis()) {
8875                 if (vmx->nmi_known_unmasked)
8876                         return;
8877                 /*
8878                  * Can't use vmx->exit_intr_info since we're not sure what
8879                  * the exit reason is.
8880                  */
8881                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8882                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8883                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8884                 /*
8885                  * SDM 3: 27.7.1.2 (September 2008)
8886                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8887                  * a guest IRET fault.
8888                  * SDM 3: 23.2.2 (September 2008)
8889                  * Bit 12 is undefined in any of the following cases:
8890                  *  If the VM exit sets the valid bit in the IDT-vectoring
8891                  *   information field.
8892                  *  If the VM exit is due to a double fault.
8893                  */
8894                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8895                     vector != DF_VECTOR && !idtv_info_valid)
8896                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8897                                       GUEST_INTR_STATE_NMI);
8898                 else
8899                         vmx->nmi_known_unmasked =
8900                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8901                                   & GUEST_INTR_STATE_NMI);
8902         } else if (unlikely(vmx->soft_vnmi_blocked))
8903                 vmx->vnmi_blocked_time +=
8904                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8905 }
8906
8907 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8908                                       u32 idt_vectoring_info,
8909                                       int instr_len_field,
8910                                       int error_code_field)
8911 {
8912         u8 vector;
8913         int type;
8914         bool idtv_info_valid;
8915
8916         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8917
8918         vcpu->arch.nmi_injected = false;
8919         kvm_clear_exception_queue(vcpu);
8920         kvm_clear_interrupt_queue(vcpu);
8921
8922         if (!idtv_info_valid)
8923                 return;
8924
8925         kvm_make_request(KVM_REQ_EVENT, vcpu);
8926
8927         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8928         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8929
8930         switch (type) {
8931         case INTR_TYPE_NMI_INTR:
8932                 vcpu->arch.nmi_injected = true;
8933                 /*
8934                  * SDM 3: 27.7.1.2 (September 2008)
8935                  * Clear bit "block by NMI" before VM entry if a NMI
8936                  * delivery faulted.
8937                  */
8938                 vmx_set_nmi_mask(vcpu, false);
8939                 break;
8940         case INTR_TYPE_SOFT_EXCEPTION:
8941                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8942                 /* fall through */
8943         case INTR_TYPE_HARD_EXCEPTION:
8944                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8945                         u32 err = vmcs_read32(error_code_field);
8946                         kvm_requeue_exception_e(vcpu, vector, err);
8947                 } else
8948                         kvm_requeue_exception(vcpu, vector);
8949                 break;
8950         case INTR_TYPE_SOFT_INTR:
8951                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8952                 /* fall through */
8953         case INTR_TYPE_EXT_INTR:
8954                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8955                 break;
8956         default:
8957                 break;
8958         }
8959 }
8960
8961 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8962 {
8963         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8964                                   VM_EXIT_INSTRUCTION_LEN,
8965                                   IDT_VECTORING_ERROR_CODE);
8966 }
8967
8968 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8969 {
8970         __vmx_complete_interrupts(vcpu,
8971                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8972                                   VM_ENTRY_INSTRUCTION_LEN,
8973                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8974
8975         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8976 }
8977
8978 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8979 {
8980         int i, nr_msrs;
8981         struct perf_guest_switch_msr *msrs;
8982
8983         msrs = perf_guest_get_msrs(&nr_msrs);
8984
8985         if (!msrs)
8986                 return;
8987
8988         for (i = 0; i < nr_msrs; i++)
8989                 if (msrs[i].host == msrs[i].guest)
8990                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8991                 else
8992                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8993                                         msrs[i].host);
8994 }
8995
8996 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8997 {
8998         struct vcpu_vmx *vmx = to_vmx(vcpu);
8999         u64 tscl;
9000         u32 delta_tsc;
9001
9002         if (vmx->hv_deadline_tsc == -1)
9003                 return;
9004
9005         tscl = rdtsc();
9006         if (vmx->hv_deadline_tsc > tscl)
9007                 /* sure to be 32 bit only because checked on set_hv_timer */
9008                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9009                         cpu_preemption_timer_multi);
9010         else
9011                 delta_tsc = 0;
9012
9013         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9014 }
9015
9016 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9017 {
9018         struct vcpu_vmx *vmx = to_vmx(vcpu);
9019         unsigned long debugctlmsr, cr4;
9020
9021         /* Record the guest's net vcpu time for enforced NMI injections. */
9022         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
9023                 vmx->entry_time = ktime_get();
9024
9025         /* Don't enter VMX if guest state is invalid, let the exit handler
9026            start emulation until we arrive back to a valid state */
9027         if (vmx->emulation_required)
9028                 return;
9029
9030         if (vmx->ple_window_dirty) {
9031                 vmx->ple_window_dirty = false;
9032                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9033         }
9034
9035         if (vmx->nested.sync_shadow_vmcs) {
9036                 copy_vmcs12_to_shadow(vmx);
9037                 vmx->nested.sync_shadow_vmcs = false;
9038         }
9039
9040         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9041                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9042         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9043                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9044
9045         cr4 = cr4_read_shadow();
9046         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
9047                 vmcs_writel(HOST_CR4, cr4);
9048                 vmx->host_state.vmcs_host_cr4 = cr4;
9049         }
9050
9051         /* When single-stepping over STI and MOV SS, we must clear the
9052          * corresponding interruptibility bits in the guest state. Otherwise
9053          * vmentry fails as it then expects bit 14 (BS) in pending debug
9054          * exceptions being set, but that's not correct for the guest debugging
9055          * case. */
9056         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9057                 vmx_set_interrupt_shadow(vcpu, 0);
9058
9059         if (vmx->guest_pkru_valid)
9060                 __write_pkru(vmx->guest_pkru);
9061
9062         atomic_switch_perf_msrs(vmx);
9063         debugctlmsr = get_debugctlmsr();
9064
9065         vmx_arm_hv_timer(vcpu);
9066
9067         vmx->__launched = vmx->loaded_vmcs->launched;
9068         asm(
9069                 /* Store host registers */
9070                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9071                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9072                 "push %%" _ASM_CX " \n\t"
9073                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9074                 "je 1f \n\t"
9075                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9076                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9077                 "1: \n\t"
9078                 /* Reload cr2 if changed */
9079                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9080                 "mov %%cr2, %%" _ASM_DX " \n\t"
9081                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9082                 "je 2f \n\t"
9083                 "mov %%" _ASM_AX", %%cr2 \n\t"
9084                 "2: \n\t"
9085                 /* Check if vmlaunch of vmresume is needed */
9086                 "cmpl $0, %c[launched](%0) \n\t"
9087                 /* Load guest registers.  Don't clobber flags. */
9088                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9089                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9090                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9091                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9092                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9093                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9094 #ifdef CONFIG_X86_64
9095                 "mov %c[r8](%0),  %%r8  \n\t"
9096                 "mov %c[r9](%0),  %%r9  \n\t"
9097                 "mov %c[r10](%0), %%r10 \n\t"
9098                 "mov %c[r11](%0), %%r11 \n\t"
9099                 "mov %c[r12](%0), %%r12 \n\t"
9100                 "mov %c[r13](%0), %%r13 \n\t"
9101                 "mov %c[r14](%0), %%r14 \n\t"
9102                 "mov %c[r15](%0), %%r15 \n\t"
9103 #endif
9104                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9105
9106                 /* Enter guest mode */
9107                 "jne 1f \n\t"
9108                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9109                 "jmp 2f \n\t"
9110                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9111                 "2: "
9112                 /* Save guest registers, load host registers, keep flags */
9113                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9114                 "pop %0 \n\t"
9115                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9116                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9117                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9118                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9119                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9120                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9121                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9122 #ifdef CONFIG_X86_64
9123                 "mov %%r8,  %c[r8](%0) \n\t"
9124                 "mov %%r9,  %c[r9](%0) \n\t"
9125                 "mov %%r10, %c[r10](%0) \n\t"
9126                 "mov %%r11, %c[r11](%0) \n\t"
9127                 "mov %%r12, %c[r12](%0) \n\t"
9128                 "mov %%r13, %c[r13](%0) \n\t"
9129                 "mov %%r14, %c[r14](%0) \n\t"
9130                 "mov %%r15, %c[r15](%0) \n\t"
9131 #endif
9132                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9133                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9134
9135                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9136                 "setbe %c[fail](%0) \n\t"
9137                 ".pushsection .rodata \n\t"
9138                 ".global vmx_return \n\t"
9139                 "vmx_return: " _ASM_PTR " 2b \n\t"
9140                 ".popsection"
9141               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9142                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9143                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9144                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9145                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9146                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9147                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9148                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9149                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9150                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9151                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9152 #ifdef CONFIG_X86_64
9153                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9154                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9155                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9156                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9157                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9158                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9159                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9160                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9161 #endif
9162                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9163                 [wordsize]"i"(sizeof(ulong))
9164               : "cc", "memory"
9165 #ifdef CONFIG_X86_64
9166                 , "rax", "rbx", "rdi", "rsi"
9167                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9168 #else
9169                 , "eax", "ebx", "edi", "esi"
9170 #endif
9171               );
9172
9173         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9174         if (debugctlmsr)
9175                 update_debugctlmsr(debugctlmsr);
9176
9177 #ifndef CONFIG_X86_64
9178         /*
9179          * The sysexit path does not restore ds/es, so we must set them to
9180          * a reasonable value ourselves.
9181          *
9182          * We can't defer this to vmx_load_host_state() since that function
9183          * may be executed in interrupt context, which saves and restore segments
9184          * around it, nullifying its effect.
9185          */
9186         loadsegment(ds, __USER_DS);
9187         loadsegment(es, __USER_DS);
9188 #endif
9189
9190         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9191                                   | (1 << VCPU_EXREG_RFLAGS)
9192                                   | (1 << VCPU_EXREG_PDPTR)
9193                                   | (1 << VCPU_EXREG_SEGMENTS)
9194                                   | (1 << VCPU_EXREG_CR3));
9195         vcpu->arch.regs_dirty = 0;
9196
9197         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9198
9199         vmx->loaded_vmcs->launched = 1;
9200
9201         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9202
9203         /*
9204          * eager fpu is enabled if PKEY is supported and CR4 is switched
9205          * back on host, so it is safe to read guest PKRU from current
9206          * XSAVE.
9207          */
9208         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9209                 vmx->guest_pkru = __read_pkru();
9210                 if (vmx->guest_pkru != vmx->host_pkru) {
9211                         vmx->guest_pkru_valid = true;
9212                         __write_pkru(vmx->host_pkru);
9213                 } else
9214                         vmx->guest_pkru_valid = false;
9215         }
9216
9217         /*
9218          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9219          * we did not inject a still-pending event to L1 now because of
9220          * nested_run_pending, we need to re-enable this bit.
9221          */
9222         if (vmx->nested.nested_run_pending)
9223                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9224
9225         vmx->nested.nested_run_pending = 0;
9226
9227         vmx_complete_atomic_exit(vmx);
9228         vmx_recover_nmi_blocking(vmx);
9229         vmx_complete_interrupts(vmx);
9230 }
9231
9232 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9233 {
9234         struct vcpu_vmx *vmx = to_vmx(vcpu);
9235         int cpu;
9236
9237         if (vmx->loaded_vmcs == &vmx->vmcs01)
9238                 return;
9239
9240         cpu = get_cpu();
9241         vmx->loaded_vmcs = &vmx->vmcs01;
9242         vmx_vcpu_put(vcpu);
9243         vmx_vcpu_load(vcpu, cpu);
9244         vcpu->cpu = cpu;
9245         put_cpu();
9246 }
9247
9248 /*
9249  * Ensure that the current vmcs of the logical processor is the
9250  * vmcs01 of the vcpu before calling free_nested().
9251  */
9252 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9253 {
9254        struct vcpu_vmx *vmx = to_vmx(vcpu);
9255        int r;
9256
9257        r = vcpu_load(vcpu);
9258        BUG_ON(r);
9259        vmx_load_vmcs01(vcpu);
9260        free_nested(vmx);
9261        vcpu_put(vcpu);
9262 }
9263
9264 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9265 {
9266         struct vcpu_vmx *vmx = to_vmx(vcpu);
9267
9268         if (enable_pml)
9269                 vmx_destroy_pml_buffer(vmx);
9270         free_vpid(vmx->vpid);
9271         leave_guest_mode(vcpu);
9272         vmx_free_vcpu_nested(vcpu);
9273         free_loaded_vmcs(vmx->loaded_vmcs);
9274         kfree(vmx->guest_msrs);
9275         kvm_vcpu_uninit(vcpu);
9276         kmem_cache_free(kvm_vcpu_cache, vmx);
9277 }
9278
9279 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9280 {
9281         int err;
9282         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9283         int cpu;
9284
9285         if (!vmx)
9286                 return ERR_PTR(-ENOMEM);
9287
9288         vmx->vpid = allocate_vpid();
9289
9290         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9291         if (err)
9292                 goto free_vcpu;
9293
9294         err = -ENOMEM;
9295
9296         /*
9297          * If PML is turned on, failure on enabling PML just results in failure
9298          * of creating the vcpu, therefore we can simplify PML logic (by
9299          * avoiding dealing with cases, such as enabling PML partially on vcpus
9300          * for the guest, etc.
9301          */
9302         if (enable_pml) {
9303                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9304                 if (!vmx->pml_pg)
9305                         goto uninit_vcpu;
9306         }
9307
9308         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9309         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9310                      > PAGE_SIZE);
9311
9312         if (!vmx->guest_msrs)
9313                 goto free_pml;
9314
9315         vmx->loaded_vmcs = &vmx->vmcs01;
9316         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9317         vmx->loaded_vmcs->shadow_vmcs = NULL;
9318         if (!vmx->loaded_vmcs->vmcs)
9319                 goto free_msrs;
9320         if (!vmm_exclusive)
9321                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9322         loaded_vmcs_init(vmx->loaded_vmcs);
9323         if (!vmm_exclusive)
9324                 kvm_cpu_vmxoff();
9325
9326         cpu = get_cpu();
9327         vmx_vcpu_load(&vmx->vcpu, cpu);
9328         vmx->vcpu.cpu = cpu;
9329         err = vmx_vcpu_setup(vmx);
9330         vmx_vcpu_put(&vmx->vcpu);
9331         put_cpu();
9332         if (err)
9333                 goto free_vmcs;
9334         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9335                 err = alloc_apic_access_page(kvm);
9336                 if (err)
9337                         goto free_vmcs;
9338         }
9339
9340         if (enable_ept) {
9341                 if (!kvm->arch.ept_identity_map_addr)
9342                         kvm->arch.ept_identity_map_addr =
9343                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9344                 err = init_rmode_identity_map(kvm);
9345                 if (err)
9346                         goto free_vmcs;
9347         }
9348
9349         if (nested) {
9350                 nested_vmx_setup_ctls_msrs(vmx);
9351                 vmx->nested.vpid02 = allocate_vpid();
9352         }
9353
9354         vmx->nested.posted_intr_nv = -1;
9355         vmx->nested.current_vmptr = -1ull;
9356         vmx->nested.current_vmcs12 = NULL;
9357
9358         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9359
9360         return &vmx->vcpu;
9361
9362 free_vmcs:
9363         free_vpid(vmx->nested.vpid02);
9364         free_loaded_vmcs(vmx->loaded_vmcs);
9365 free_msrs:
9366         kfree(vmx->guest_msrs);
9367 free_pml:
9368         vmx_destroy_pml_buffer(vmx);
9369 uninit_vcpu:
9370         kvm_vcpu_uninit(&vmx->vcpu);
9371 free_vcpu:
9372         free_vpid(vmx->vpid);
9373         kmem_cache_free(kvm_vcpu_cache, vmx);
9374         return ERR_PTR(err);
9375 }
9376
9377 static void __init vmx_check_processor_compat(void *rtn)
9378 {
9379         struct vmcs_config vmcs_conf;
9380
9381         *(int *)rtn = 0;
9382         if (setup_vmcs_config(&vmcs_conf) < 0)
9383                 *(int *)rtn = -EIO;
9384         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9385                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9386                                 smp_processor_id());
9387                 *(int *)rtn = -EIO;
9388         }
9389 }
9390
9391 static int get_ept_level(void)
9392 {
9393         return VMX_EPT_DEFAULT_GAW + 1;
9394 }
9395
9396 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9397 {
9398         u8 cache;
9399         u64 ipat = 0;
9400
9401         /* For VT-d and EPT combination
9402          * 1. MMIO: always map as UC
9403          * 2. EPT with VT-d:
9404          *   a. VT-d without snooping control feature: can't guarantee the
9405          *      result, try to trust guest.
9406          *   b. VT-d with snooping control feature: snooping control feature of
9407          *      VT-d engine can guarantee the cache correctness. Just set it
9408          *      to WB to keep consistent with host. So the same as item 3.
9409          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9410          *    consistent with host MTRR
9411          */
9412         if (is_mmio) {
9413                 cache = MTRR_TYPE_UNCACHABLE;
9414                 goto exit;
9415         }
9416
9417         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9418                 ipat = VMX_EPT_IPAT_BIT;
9419                 cache = MTRR_TYPE_WRBACK;
9420                 goto exit;
9421         }
9422
9423         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9424                 ipat = VMX_EPT_IPAT_BIT;
9425                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9426                         cache = MTRR_TYPE_WRBACK;
9427                 else
9428                         cache = MTRR_TYPE_UNCACHABLE;
9429                 goto exit;
9430         }
9431
9432         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9433
9434 exit:
9435         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9436 }
9437
9438 static int vmx_get_lpage_level(void)
9439 {
9440         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9441                 return PT_DIRECTORY_LEVEL;
9442         else
9443                 /* For shadow and EPT supported 1GB page */
9444                 return PT_PDPE_LEVEL;
9445 }
9446
9447 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9448 {
9449         /*
9450          * These bits in the secondary execution controls field
9451          * are dynamic, the others are mostly based on the hypervisor
9452          * architecture and the guest's CPUID.  Do not touch the
9453          * dynamic bits.
9454          */
9455         u32 mask =
9456                 SECONDARY_EXEC_SHADOW_VMCS |
9457                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9458                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9459
9460         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9461
9462         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9463                      (new_ctl & ~mask) | (cur_ctl & mask));
9464 }
9465
9466 /*
9467  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9468  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9469  */
9470 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9471 {
9472         struct vcpu_vmx *vmx = to_vmx(vcpu);
9473         struct kvm_cpuid_entry2 *entry;
9474
9475         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9476         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9477
9478 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9479         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9480                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9481 } while (0)
9482
9483         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9484         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9485         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9486         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9487         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9488         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9489         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9490         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9491         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9492         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9493         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9494         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9495         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9496         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9497         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9498
9499         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9500         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9501         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9502         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9503         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9504         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9505         cr4_fixed1_update(bit(11),            ecx, bit(2));
9506
9507 #undef cr4_fixed1_update
9508 }
9509
9510 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9511 {
9512         struct kvm_cpuid_entry2 *best;
9513         struct vcpu_vmx *vmx = to_vmx(vcpu);
9514         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9515
9516         if (vmx_rdtscp_supported()) {
9517                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9518                 if (!rdtscp_enabled)
9519                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9520
9521                 if (nested) {
9522                         if (rdtscp_enabled)
9523                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9524                                         SECONDARY_EXEC_RDTSCP;
9525                         else
9526                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9527                                         ~SECONDARY_EXEC_RDTSCP;
9528                 }
9529         }
9530
9531         /* Exposing INVPCID only when PCID is exposed */
9532         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9533         if (vmx_invpcid_supported() &&
9534             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9535             !guest_cpuid_has_pcid(vcpu))) {
9536                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9537
9538                 if (best)
9539                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9540         }
9541
9542         if (cpu_has_secondary_exec_ctrls())
9543                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9544
9545         if (nested_vmx_allowed(vcpu))
9546                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9547                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9548         else
9549                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9550                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9551
9552         if (nested_vmx_allowed(vcpu))
9553                 nested_vmx_cr_fixed1_bits_update(vcpu);
9554 }
9555
9556 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9557 {
9558         if (func == 1 && nested)
9559                 entry->ecx |= bit(X86_FEATURE_VMX);
9560 }
9561
9562 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9563                 struct x86_exception *fault)
9564 {
9565         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9566         u32 exit_reason;
9567
9568         if (fault->error_code & PFERR_RSVD_MASK)
9569                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9570         else
9571                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9572         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9573         vmcs12->guest_physical_address = fault->address;
9574 }
9575
9576 /* Callbacks for nested_ept_init_mmu_context: */
9577
9578 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9579 {
9580         /* return the page table to be shadowed - in our case, EPT12 */
9581         return get_vmcs12(vcpu)->ept_pointer;
9582 }
9583
9584 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9585 {
9586         WARN_ON(mmu_is_nested(vcpu));
9587         kvm_init_shadow_ept_mmu(vcpu,
9588                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9589                         VMX_EPT_EXECUTE_ONLY_BIT);
9590         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9591         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9592         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9593
9594         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9595 }
9596
9597 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9598 {
9599         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9600 }
9601
9602 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9603                                             u16 error_code)
9604 {
9605         bool inequality, bit;
9606
9607         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9608         inequality =
9609                 (error_code & vmcs12->page_fault_error_code_mask) !=
9610                  vmcs12->page_fault_error_code_match;
9611         return inequality ^ bit;
9612 }
9613
9614 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9615                 struct x86_exception *fault)
9616 {
9617         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9618
9619         WARN_ON(!is_guest_mode(vcpu));
9620
9621         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9622                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9623                                   vmcs_read32(VM_EXIT_INTR_INFO),
9624                                   vmcs_readl(EXIT_QUALIFICATION));
9625         else
9626                 kvm_inject_page_fault(vcpu, fault);
9627 }
9628
9629 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9630                                                struct vmcs12 *vmcs12);
9631
9632 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9633                                         struct vmcs12 *vmcs12)
9634 {
9635         struct vcpu_vmx *vmx = to_vmx(vcpu);
9636         u64 hpa;
9637
9638         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9639                 /*
9640                  * Translate L1 physical address to host physical
9641                  * address for vmcs02. Keep the page pinned, so this
9642                  * physical address remains valid. We keep a reference
9643                  * to it so we can release it later.
9644                  */
9645                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9646                         nested_release_page(vmx->nested.apic_access_page);
9647                 vmx->nested.apic_access_page =
9648                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9649                 /*
9650                  * If translation failed, no matter: This feature asks
9651                  * to exit when accessing the given address, and if it
9652                  * can never be accessed, this feature won't do
9653                  * anything anyway.
9654                  */
9655                 if (vmx->nested.apic_access_page) {
9656                         hpa = page_to_phys(vmx->nested.apic_access_page);
9657                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9658                 } else {
9659                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9660                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9661                 }
9662         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9663                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9664                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9665                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9666                 kvm_vcpu_reload_apic_access_page(vcpu);
9667         }
9668
9669         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9670                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9671                         nested_release_page(vmx->nested.virtual_apic_page);
9672                 vmx->nested.virtual_apic_page =
9673                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9674
9675                 /*
9676                  * If translation failed, VM entry will fail because
9677                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9678                  * Failing the vm entry is _not_ what the processor
9679                  * does but it's basically the only possibility we
9680                  * have.  We could still enter the guest if CR8 load
9681                  * exits are enabled, CR8 store exits are enabled, and
9682                  * virtualize APIC access is disabled; in this case
9683                  * the processor would never use the TPR shadow and we
9684                  * could simply clear the bit from the execution
9685                  * control.  But such a configuration is useless, so
9686                  * let's keep the code simple.
9687                  */
9688                 if (vmx->nested.virtual_apic_page) {
9689                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9690                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9691                 }
9692         }
9693
9694         if (nested_cpu_has_posted_intr(vmcs12)) {
9695                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9696                         kunmap(vmx->nested.pi_desc_page);
9697                         nested_release_page(vmx->nested.pi_desc_page);
9698                 }
9699                 vmx->nested.pi_desc_page =
9700                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9701                 vmx->nested.pi_desc =
9702                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9703                 if (!vmx->nested.pi_desc) {
9704                         nested_release_page_clean(vmx->nested.pi_desc_page);
9705                         return;
9706                 }
9707                 vmx->nested.pi_desc =
9708                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9709                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9710                         (PAGE_SIZE - 1)));
9711                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9712                         page_to_phys(vmx->nested.pi_desc_page) +
9713                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9714                         (PAGE_SIZE - 1)));
9715         }
9716         if (cpu_has_vmx_msr_bitmap() &&
9717             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9718             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9719                 ;
9720         else
9721                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9722                                 CPU_BASED_USE_MSR_BITMAPS);
9723 }
9724
9725 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9726 {
9727         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9728         struct vcpu_vmx *vmx = to_vmx(vcpu);
9729
9730         if (vcpu->arch.virtual_tsc_khz == 0)
9731                 return;
9732
9733         /* Make sure short timeouts reliably trigger an immediate vmexit.
9734          * hrtimer_start does not guarantee this. */
9735         if (preemption_timeout <= 1) {
9736                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9737                 return;
9738         }
9739
9740         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9741         preemption_timeout *= 1000000;
9742         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9743         hrtimer_start(&vmx->nested.preemption_timer,
9744                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9745 }
9746
9747 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9748                                                 struct vmcs12 *vmcs12)
9749 {
9750         int maxphyaddr;
9751         u64 addr;
9752
9753         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9754                 return 0;
9755
9756         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9757                 WARN_ON(1);
9758                 return -EINVAL;
9759         }
9760         maxphyaddr = cpuid_maxphyaddr(vcpu);
9761
9762         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9763            ((addr + PAGE_SIZE) >> maxphyaddr))
9764                 return -EINVAL;
9765
9766         return 0;
9767 }
9768
9769 /*
9770  * Merge L0's and L1's MSR bitmap, return false to indicate that
9771  * we do not use the hardware.
9772  */
9773 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9774                                                struct vmcs12 *vmcs12)
9775 {
9776         int msr;
9777         struct page *page;
9778         unsigned long *msr_bitmap_l1;
9779         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9780
9781         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9782         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9783                 return false;
9784
9785         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9786         if (!page) {
9787                 WARN_ON(1);
9788                 return false;
9789         }
9790         msr_bitmap_l1 = (unsigned long *)kmap(page);
9791
9792         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9793
9794         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9795                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9796                         for (msr = 0x800; msr <= 0x8ff; msr++)
9797                                 nested_vmx_disable_intercept_for_msr(
9798                                         msr_bitmap_l1, msr_bitmap_l0,
9799                                         msr, MSR_TYPE_R);
9800
9801                 nested_vmx_disable_intercept_for_msr(
9802                                 msr_bitmap_l1, msr_bitmap_l0,
9803                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9804                                 MSR_TYPE_R | MSR_TYPE_W);
9805
9806                 if (nested_cpu_has_vid(vmcs12)) {
9807                         nested_vmx_disable_intercept_for_msr(
9808                                 msr_bitmap_l1, msr_bitmap_l0,
9809                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9810                                 MSR_TYPE_W);
9811                         nested_vmx_disable_intercept_for_msr(
9812                                 msr_bitmap_l1, msr_bitmap_l0,
9813                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9814                                 MSR_TYPE_W);
9815                 }
9816         }
9817         kunmap(page);
9818         nested_release_page_clean(page);
9819
9820         return true;
9821 }
9822
9823 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9824                                            struct vmcs12 *vmcs12)
9825 {
9826         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9827             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9828             !nested_cpu_has_vid(vmcs12) &&
9829             !nested_cpu_has_posted_intr(vmcs12))
9830                 return 0;
9831
9832         /*
9833          * If virtualize x2apic mode is enabled,
9834          * virtualize apic access must be disabled.
9835          */
9836         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9837             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9838                 return -EINVAL;
9839
9840         /*
9841          * If virtual interrupt delivery is enabled,
9842          * we must exit on external interrupts.
9843          */
9844         if (nested_cpu_has_vid(vmcs12) &&
9845            !nested_exit_on_intr(vcpu))
9846                 return -EINVAL;
9847
9848         /*
9849          * bits 15:8 should be zero in posted_intr_nv,
9850          * the descriptor address has been already checked
9851          * in nested_get_vmcs12_pages.
9852          */
9853         if (nested_cpu_has_posted_intr(vmcs12) &&
9854            (!nested_cpu_has_vid(vmcs12) ||
9855             !nested_exit_intr_ack_set(vcpu) ||
9856             vmcs12->posted_intr_nv & 0xff00))
9857                 return -EINVAL;
9858
9859         /* tpr shadow is needed by all apicv features. */
9860         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9861                 return -EINVAL;
9862
9863         return 0;
9864 }
9865
9866 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9867                                        unsigned long count_field,
9868                                        unsigned long addr_field)
9869 {
9870         int maxphyaddr;
9871         u64 count, addr;
9872
9873         if (vmcs12_read_any(vcpu, count_field, &count) ||
9874             vmcs12_read_any(vcpu, addr_field, &addr)) {
9875                 WARN_ON(1);
9876                 return -EINVAL;
9877         }
9878         if (count == 0)
9879                 return 0;
9880         maxphyaddr = cpuid_maxphyaddr(vcpu);
9881         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9882             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9883                 pr_debug_ratelimited(
9884                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9885                         addr_field, maxphyaddr, count, addr);
9886                 return -EINVAL;
9887         }
9888         return 0;
9889 }
9890
9891 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9892                                                 struct vmcs12 *vmcs12)
9893 {
9894         if (vmcs12->vm_exit_msr_load_count == 0 &&
9895             vmcs12->vm_exit_msr_store_count == 0 &&
9896             vmcs12->vm_entry_msr_load_count == 0)
9897                 return 0; /* Fast path */
9898         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9899                                         VM_EXIT_MSR_LOAD_ADDR) ||
9900             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9901                                         VM_EXIT_MSR_STORE_ADDR) ||
9902             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9903                                         VM_ENTRY_MSR_LOAD_ADDR))
9904                 return -EINVAL;
9905         return 0;
9906 }
9907
9908 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9909                                        struct vmx_msr_entry *e)
9910 {
9911         /* x2APIC MSR accesses are not allowed */
9912         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9913                 return -EINVAL;
9914         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9915             e->index == MSR_IA32_UCODE_REV)
9916                 return -EINVAL;
9917         if (e->reserved != 0)
9918                 return -EINVAL;
9919         return 0;
9920 }
9921
9922 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9923                                      struct vmx_msr_entry *e)
9924 {
9925         if (e->index == MSR_FS_BASE ||
9926             e->index == MSR_GS_BASE ||
9927             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9928             nested_vmx_msr_check_common(vcpu, e))
9929                 return -EINVAL;
9930         return 0;
9931 }
9932
9933 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9934                                       struct vmx_msr_entry *e)
9935 {
9936         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9937             nested_vmx_msr_check_common(vcpu, e))
9938                 return -EINVAL;
9939         return 0;
9940 }
9941
9942 /*
9943  * Load guest's/host's msr at nested entry/exit.
9944  * return 0 for success, entry index for failure.
9945  */
9946 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9947 {
9948         u32 i;
9949         struct vmx_msr_entry e;
9950         struct msr_data msr;
9951
9952         msr.host_initiated = false;
9953         for (i = 0; i < count; i++) {
9954                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9955                                         &e, sizeof(e))) {
9956                         pr_debug_ratelimited(
9957                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9958                                 __func__, i, gpa + i * sizeof(e));
9959                         goto fail;
9960                 }
9961                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9962                         pr_debug_ratelimited(
9963                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9964                                 __func__, i, e.index, e.reserved);
9965                         goto fail;
9966                 }
9967                 msr.index = e.index;
9968                 msr.data = e.value;
9969                 if (kvm_set_msr(vcpu, &msr)) {
9970                         pr_debug_ratelimited(
9971                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9972                                 __func__, i, e.index, e.value);
9973                         goto fail;
9974                 }
9975         }
9976         return 0;
9977 fail:
9978         return i + 1;
9979 }
9980
9981 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9982 {
9983         u32 i;
9984         struct vmx_msr_entry e;
9985
9986         for (i = 0; i < count; i++) {
9987                 struct msr_data msr_info;
9988                 if (kvm_vcpu_read_guest(vcpu,
9989                                         gpa + i * sizeof(e),
9990                                         &e, 2 * sizeof(u32))) {
9991                         pr_debug_ratelimited(
9992                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9993                                 __func__, i, gpa + i * sizeof(e));
9994                         return -EINVAL;
9995                 }
9996                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9997                         pr_debug_ratelimited(
9998                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9999                                 __func__, i, e.index, e.reserved);
10000                         return -EINVAL;
10001                 }
10002                 msr_info.host_initiated = false;
10003                 msr_info.index = e.index;
10004                 if (kvm_get_msr(vcpu, &msr_info)) {
10005                         pr_debug_ratelimited(
10006                                 "%s cannot read MSR (%u, 0x%x)\n",
10007                                 __func__, i, e.index);
10008                         return -EINVAL;
10009                 }
10010                 if (kvm_vcpu_write_guest(vcpu,
10011                                          gpa + i * sizeof(e) +
10012                                              offsetof(struct vmx_msr_entry, value),
10013                                          &msr_info.data, sizeof(msr_info.data))) {
10014                         pr_debug_ratelimited(
10015                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10016                                 __func__, i, e.index, msr_info.data);
10017                         return -EINVAL;
10018                 }
10019         }
10020         return 0;
10021 }
10022
10023 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10024 {
10025         unsigned long invalid_mask;
10026
10027         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10028         return (val & invalid_mask) == 0;
10029 }
10030
10031 /*
10032  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10033  * emulating VM entry into a guest with EPT enabled.
10034  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10035  * is assigned to entry_failure_code on failure.
10036  */
10037 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10038                                unsigned long *entry_failure_code)
10039 {
10040         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10041                 if (!nested_cr3_valid(vcpu, cr3)) {
10042                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10043                         return 1;
10044                 }
10045
10046                 /*
10047                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10048                  * must not be dereferenced.
10049                  */
10050                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10051                     !nested_ept) {
10052                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10053                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
10054                                 return 1;
10055                         }
10056                 }
10057
10058                 vcpu->arch.cr3 = cr3;
10059                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10060         }
10061
10062         kvm_mmu_reset_context(vcpu);
10063         return 0;
10064 }
10065
10066 /*
10067  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10068  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10069  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10070  * guest in a way that will both be appropriate to L1's requests, and our
10071  * needs. In addition to modifying the active vmcs (which is vmcs02), this
10072  * function also has additional necessary side-effects, like setting various
10073  * vcpu->arch fields.
10074  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10075  * is assigned to entry_failure_code on failure.
10076  */
10077 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10078                           bool from_vmentry, unsigned long *entry_failure_code)
10079 {
10080         struct vcpu_vmx *vmx = to_vmx(vcpu);
10081         u32 exec_control;
10082         bool nested_ept_enabled = false;
10083
10084         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10085         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10086         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10087         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10088         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10089         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10090         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10091         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10092         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10093         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10094         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10095         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10096         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10097         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10098         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10099         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10100         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10101         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10102         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10103         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10104         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10105         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10106         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10107         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10108         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10109         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10110         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10111         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10112         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10113         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10114         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10115         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10116         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10117         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10118         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10119         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10120
10121         if (from_vmentry &&
10122             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10123                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10124                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10125         } else {
10126                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10127                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10128         }
10129         if (from_vmentry) {
10130                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10131                              vmcs12->vm_entry_intr_info_field);
10132                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10133                              vmcs12->vm_entry_exception_error_code);
10134                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10135                              vmcs12->vm_entry_instruction_len);
10136                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10137                              vmcs12->guest_interruptibility_info);
10138         } else {
10139                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10140         }
10141         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10142         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10143         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10144                 vmcs12->guest_pending_dbg_exceptions);
10145         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10146         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10147
10148         if (nested_cpu_has_xsaves(vmcs12))
10149                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10150         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10151
10152         exec_control = vmcs12->pin_based_vm_exec_control;
10153
10154         /* Preemption timer setting is only taken from vmcs01.  */
10155         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10156         exec_control |= vmcs_config.pin_based_exec_ctrl;
10157         if (vmx->hv_deadline_tsc == -1)
10158                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10159
10160         /* Posted interrupts setting is only taken from vmcs12.  */
10161         if (nested_cpu_has_posted_intr(vmcs12)) {
10162                 /*
10163                  * Note that we use L0's vector here and in
10164                  * vmx_deliver_nested_posted_interrupt.
10165                  */
10166                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10167                 vmx->nested.pi_pending = false;
10168                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10169         } else {
10170                 exec_control &= ~PIN_BASED_POSTED_INTR;
10171         }
10172
10173         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10174
10175         vmx->nested.preemption_timer_expired = false;
10176         if (nested_cpu_has_preemption_timer(vmcs12))
10177                 vmx_start_preemption_timer(vcpu);
10178
10179         /*
10180          * Whether page-faults are trapped is determined by a combination of
10181          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10182          * If enable_ept, L0 doesn't care about page faults and we should
10183          * set all of these to L1's desires. However, if !enable_ept, L0 does
10184          * care about (at least some) page faults, and because it is not easy
10185          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10186          * to exit on each and every L2 page fault. This is done by setting
10187          * MASK=MATCH=0 and (see below) EB.PF=1.
10188          * Note that below we don't need special code to set EB.PF beyond the
10189          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10190          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10191          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10192          *
10193          * A problem with this approach (when !enable_ept) is that L1 may be
10194          * injected with more page faults than it asked for. This could have
10195          * caused problems, but in practice existing hypervisors don't care.
10196          * To fix this, we will need to emulate the PFEC checking (on the L1
10197          * page tables), using walk_addr(), when injecting PFs to L1.
10198          */
10199         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10200                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10201         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10202                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10203
10204         if (cpu_has_secondary_exec_ctrls()) {
10205                 exec_control = vmx_secondary_exec_control(vmx);
10206
10207                 /* Take the following fields only from vmcs12 */
10208                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10209                                   SECONDARY_EXEC_RDTSCP |
10210                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10211                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10212                 if (nested_cpu_has(vmcs12,
10213                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10214                         exec_control |= vmcs12->secondary_vm_exec_control;
10215
10216                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10217                         vmcs_write64(EOI_EXIT_BITMAP0,
10218                                 vmcs12->eoi_exit_bitmap0);
10219                         vmcs_write64(EOI_EXIT_BITMAP1,
10220                                 vmcs12->eoi_exit_bitmap1);
10221                         vmcs_write64(EOI_EXIT_BITMAP2,
10222                                 vmcs12->eoi_exit_bitmap2);
10223                         vmcs_write64(EOI_EXIT_BITMAP3,
10224                                 vmcs12->eoi_exit_bitmap3);
10225                         vmcs_write16(GUEST_INTR_STATUS,
10226                                 vmcs12->guest_intr_status);
10227                 }
10228
10229                 nested_ept_enabled = (exec_control & SECONDARY_EXEC_ENABLE_EPT) != 0;
10230
10231                 /*
10232                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10233                  * nested_get_vmcs12_pages will either fix it up or
10234                  * remove the VM execution control.
10235                  */
10236                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10237                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10238
10239                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10240         }
10241
10242
10243         /*
10244          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10245          * Some constant fields are set here by vmx_set_constant_host_state().
10246          * Other fields are different per CPU, and will be set later when
10247          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10248          */
10249         vmx_set_constant_host_state(vmx);
10250
10251         /*
10252          * Set the MSR load/store lists to match L0's settings.
10253          */
10254         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10255         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10256         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10257         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10258         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10259
10260         /*
10261          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10262          * entry, but only if the current (host) sp changed from the value
10263          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10264          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10265          * here we just force the write to happen on entry.
10266          */
10267         vmx->host_rsp = 0;
10268
10269         exec_control = vmx_exec_control(vmx); /* L0's desires */
10270         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10271         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10272         exec_control &= ~CPU_BASED_TPR_SHADOW;
10273         exec_control |= vmcs12->cpu_based_vm_exec_control;
10274
10275         /*
10276          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10277          * nested_get_vmcs12_pages can't fix it up, the illegal value
10278          * will result in a VM entry failure.
10279          */
10280         if (exec_control & CPU_BASED_TPR_SHADOW) {
10281                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10282                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10283         }
10284
10285         /*
10286          * Merging of IO bitmap not currently supported.
10287          * Rather, exit every time.
10288          */
10289         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10290         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10291
10292         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10293
10294         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10295          * bitwise-or of what L1 wants to trap for L2, and what we want to
10296          * trap. Note that CR0.TS also needs updating - we do this later.
10297          */
10298         update_exception_bitmap(vcpu);
10299         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10300         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10301
10302         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10303          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10304          * bits are further modified by vmx_set_efer() below.
10305          */
10306         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10307
10308         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10309          * emulated by vmx_set_efer(), below.
10310          */
10311         vm_entry_controls_init(vmx,
10312                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10313                         ~VM_ENTRY_IA32E_MODE) |
10314                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10315
10316         if (from_vmentry &&
10317             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10318                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10319                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10320         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10321                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10322         }
10323
10324         set_cr4_guest_host_mask(vmx);
10325
10326         if (from_vmentry &&
10327             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10328                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10329
10330         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10331                 vmcs_write64(TSC_OFFSET,
10332                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10333         else
10334                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10335         if (kvm_has_tsc_control)
10336                 decache_tsc_multiplier(vmx);
10337
10338         if (enable_vpid) {
10339                 /*
10340                  * There is no direct mapping between vpid02 and vpid12, the
10341                  * vpid02 is per-vCPU for L0 and reused while the value of
10342                  * vpid12 is changed w/ one invvpid during nested vmentry.
10343                  * The vpid12 is allocated by L1 for L2, so it will not
10344                  * influence global bitmap(for vpid01 and vpid02 allocation)
10345                  * even if spawn a lot of nested vCPUs.
10346                  */
10347                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10348                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10349                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10350                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10351                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10352                         }
10353                 } else {
10354                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10355                         vmx_flush_tlb(vcpu);
10356                 }
10357
10358         }
10359
10360         if (nested_cpu_has_ept(vmcs12)) {
10361                 kvm_mmu_unload(vcpu);
10362                 nested_ept_init_mmu_context(vcpu);
10363         }
10364
10365         /*
10366          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10367          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10368          * The CR0_READ_SHADOW is what L2 should have expected to read given
10369          * the specifications by L1; It's not enough to take
10370          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10371          * have more bits than L1 expected.
10372          */
10373         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10374         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10375
10376         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10377         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10378
10379         if (from_vmentry &&
10380             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10381                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10382         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10383                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10384         else
10385                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10386         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10387         vmx_set_efer(vcpu, vcpu->arch.efer);
10388
10389         /* Shadow page tables on either EPT or shadow page tables. */
10390         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_ept_enabled,
10391                                 entry_failure_code))
10392                 return 1;
10393
10394         kvm_mmu_reset_context(vcpu);
10395
10396         if (!enable_ept)
10397                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10398
10399         /*
10400          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10401          */
10402         if (enable_ept) {
10403                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10404                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10405                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10406                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10407         }
10408
10409         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10410         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10411         return 0;
10412 }
10413
10414 /*
10415  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10416  * for running an L2 nested guest.
10417  */
10418 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10419 {
10420         struct vmcs12 *vmcs12;
10421         struct vcpu_vmx *vmx = to_vmx(vcpu);
10422         int cpu;
10423         struct loaded_vmcs *vmcs02;
10424         bool ia32e;
10425         u32 msr_entry_idx;
10426         unsigned long exit_qualification;
10427
10428         if (!nested_vmx_check_permission(vcpu))
10429                 return 1;
10430
10431         if (!nested_vmx_check_vmcs12(vcpu))
10432                 goto out;
10433
10434         vmcs12 = get_vmcs12(vcpu);
10435
10436         if (enable_shadow_vmcs)
10437                 copy_shadow_to_vmcs12(vmx);
10438
10439         /*
10440          * The nested entry process starts with enforcing various prerequisites
10441          * on vmcs12 as required by the Intel SDM, and act appropriately when
10442          * they fail: As the SDM explains, some conditions should cause the
10443          * instruction to fail, while others will cause the instruction to seem
10444          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10445          * To speed up the normal (success) code path, we should avoid checking
10446          * for misconfigurations which will anyway be caught by the processor
10447          * when using the merged vmcs02.
10448          */
10449         if (vmcs12->launch_state == launch) {
10450                 nested_vmx_failValid(vcpu,
10451                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10452                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10453                 goto out;
10454         }
10455
10456         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10457             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
10458                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10459                 goto out;
10460         }
10461
10462         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
10463                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10464                 goto out;
10465         }
10466
10467         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
10468                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10469                 goto out;
10470         }
10471
10472         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
10473                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10474                 goto out;
10475         }
10476
10477         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10478                                 vmx->nested.nested_vmx_procbased_ctls_low,
10479                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10480             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10481                                 vmx->nested.nested_vmx_secondary_ctls_low,
10482                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10483             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10484                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10485                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10486             !vmx_control_verify(vmcs12->vm_exit_controls,
10487                                 vmx->nested.nested_vmx_exit_ctls_low,
10488                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10489             !vmx_control_verify(vmcs12->vm_entry_controls,
10490                                 vmx->nested.nested_vmx_entry_ctls_low,
10491                                 vmx->nested.nested_vmx_entry_ctls_high))
10492         {
10493                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10494                 goto out;
10495         }
10496
10497         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10498             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10499             !nested_cr3_valid(vcpu, vmcs12->host_cr3)) {
10500                 nested_vmx_failValid(vcpu,
10501                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
10502                 goto out;
10503         }
10504
10505         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10506             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)) {
10507                 nested_vmx_entry_failure(vcpu, vmcs12,
10508                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10509                 return 1;
10510         }
10511         if (vmcs12->vmcs_link_pointer != -1ull) {
10512                 nested_vmx_entry_failure(vcpu, vmcs12,
10513                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
10514                 return 1;
10515         }
10516
10517         /*
10518          * If the load IA32_EFER VM-entry control is 1, the following checks
10519          * are performed on the field for the IA32_EFER MSR:
10520          * - Bits reserved in the IA32_EFER MSR must be 0.
10521          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10522          *   the IA-32e mode guest VM-exit control. It must also be identical
10523          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10524          *   CR0.PG) is 1.
10525          */
10526         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10527                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10528                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10529                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10530                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10531                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10532                         nested_vmx_entry_failure(vcpu, vmcs12,
10533                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10534                         return 1;
10535                 }
10536         }
10537
10538         /*
10539          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10540          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10541          * the values of the LMA and LME bits in the field must each be that of
10542          * the host address-space size VM-exit control.
10543          */
10544         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10545                 ia32e = (vmcs12->vm_exit_controls &
10546                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10547                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10548                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10549                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10550                         nested_vmx_entry_failure(vcpu, vmcs12,
10551                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10552                         return 1;
10553                 }
10554         }
10555
10556         /*
10557          * We're finally done with prerequisite checking, and can start with
10558          * the nested entry.
10559          */
10560
10561         vmcs02 = nested_get_current_vmcs02(vmx);
10562         if (!vmcs02)
10563                 return -ENOMEM;
10564
10565         /*
10566          * After this point, the trap flag no longer triggers a singlestep trap
10567          * on the vm entry instructions. Don't call
10568          * kvm_skip_emulated_instruction.
10569          */
10570         skip_emulated_instruction(vcpu);
10571         enter_guest_mode(vcpu);
10572
10573         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10574                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10575
10576         cpu = get_cpu();
10577         vmx->loaded_vmcs = vmcs02;
10578         vmx_vcpu_put(vcpu);
10579         vmx_vcpu_load(vcpu, cpu);
10580         vcpu->cpu = cpu;
10581         put_cpu();
10582
10583         vmx_segment_cache_clear(vmx);
10584
10585         if (prepare_vmcs02(vcpu, vmcs12, true, &exit_qualification)) {
10586                 leave_guest_mode(vcpu);
10587                 vmx_load_vmcs01(vcpu);
10588                 nested_vmx_entry_failure(vcpu, vmcs12,
10589                                 EXIT_REASON_INVALID_STATE, exit_qualification);
10590                 return 1;
10591         }
10592
10593         nested_get_vmcs12_pages(vcpu, vmcs12);
10594
10595         msr_entry_idx = nested_vmx_load_msr(vcpu,
10596                                             vmcs12->vm_entry_msr_load_addr,
10597                                             vmcs12->vm_entry_msr_load_count);
10598         if (msr_entry_idx) {
10599                 leave_guest_mode(vcpu);
10600                 vmx_load_vmcs01(vcpu);
10601                 nested_vmx_entry_failure(vcpu, vmcs12,
10602                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10603                 return 1;
10604         }
10605
10606         vmcs12->launch_state = 1;
10607
10608         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10609                 return kvm_vcpu_halt(vcpu);
10610
10611         vmx->nested.nested_run_pending = 1;
10612
10613         /*
10614          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10615          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10616          * returned as far as L1 is concerned. It will only return (and set
10617          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10618          */
10619         return 1;
10620
10621 out:
10622         return kvm_skip_emulated_instruction(vcpu);
10623 }
10624
10625 /*
10626  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10627  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10628  * This function returns the new value we should put in vmcs12.guest_cr0.
10629  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10630  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10631  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10632  *     didn't trap the bit, because if L1 did, so would L0).
10633  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10634  *     been modified by L2, and L1 knows it. So just leave the old value of
10635  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10636  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10637  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10638  *     changed these bits, and therefore they need to be updated, but L0
10639  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10640  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10641  */
10642 static inline unsigned long
10643 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10644 {
10645         return
10646         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10647         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10648         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10649                         vcpu->arch.cr0_guest_owned_bits));
10650 }
10651
10652 static inline unsigned long
10653 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10654 {
10655         return
10656         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10657         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10658         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10659                         vcpu->arch.cr4_guest_owned_bits));
10660 }
10661
10662 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10663                                        struct vmcs12 *vmcs12)
10664 {
10665         u32 idt_vectoring;
10666         unsigned int nr;
10667
10668         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10669                 nr = vcpu->arch.exception.nr;
10670                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10671
10672                 if (kvm_exception_is_soft(nr)) {
10673                         vmcs12->vm_exit_instruction_len =
10674                                 vcpu->arch.event_exit_inst_len;
10675                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10676                 } else
10677                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10678
10679                 if (vcpu->arch.exception.has_error_code) {
10680                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10681                         vmcs12->idt_vectoring_error_code =
10682                                 vcpu->arch.exception.error_code;
10683                 }
10684
10685                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10686         } else if (vcpu->arch.nmi_injected) {
10687                 vmcs12->idt_vectoring_info_field =
10688                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10689         } else if (vcpu->arch.interrupt.pending) {
10690                 nr = vcpu->arch.interrupt.nr;
10691                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10692
10693                 if (vcpu->arch.interrupt.soft) {
10694                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10695                         vmcs12->vm_entry_instruction_len =
10696                                 vcpu->arch.event_exit_inst_len;
10697                 } else
10698                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10699
10700                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10701         }
10702 }
10703
10704 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10705 {
10706         struct vcpu_vmx *vmx = to_vmx(vcpu);
10707
10708         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10709             vmx->nested.preemption_timer_expired) {
10710                 if (vmx->nested.nested_run_pending)
10711                         return -EBUSY;
10712                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10713                 return 0;
10714         }
10715
10716         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10717                 if (vmx->nested.nested_run_pending ||
10718                     vcpu->arch.interrupt.pending)
10719                         return -EBUSY;
10720                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10721                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10722                                   INTR_INFO_VALID_MASK, 0);
10723                 /*
10724                  * The NMI-triggered VM exit counts as injection:
10725                  * clear this one and block further NMIs.
10726                  */
10727                 vcpu->arch.nmi_pending = 0;
10728                 vmx_set_nmi_mask(vcpu, true);
10729                 return 0;
10730         }
10731
10732         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10733             nested_exit_on_intr(vcpu)) {
10734                 if (vmx->nested.nested_run_pending)
10735                         return -EBUSY;
10736                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10737                 return 0;
10738         }
10739
10740         vmx_complete_nested_posted_interrupt(vcpu);
10741         return 0;
10742 }
10743
10744 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10745 {
10746         ktime_t remaining =
10747                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10748         u64 value;
10749
10750         if (ktime_to_ns(remaining) <= 0)
10751                 return 0;
10752
10753         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10754         do_div(value, 1000000);
10755         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10756 }
10757
10758 /*
10759  * Update the guest state fields of vmcs12 to reflect changes that
10760  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10761  * VM-entry controls is also updated, since this is really a guest
10762  * state bit.)
10763  */
10764 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10765 {
10766         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10767         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10768
10769         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10770         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10771         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10772
10773         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10774         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10775         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10776         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10777         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10778         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10779         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10780         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10781         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10782         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10783         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10784         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10785         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10786         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10787         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10788         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10789         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10790         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10791         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10792         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10793         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10794         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10795         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10796         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10797         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10798         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10799         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10800         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10801         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10802         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10803         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10804         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10805         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10806         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10807         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10808         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10809
10810         vmcs12->guest_interruptibility_info =
10811                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10812         vmcs12->guest_pending_dbg_exceptions =
10813                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10814         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10815                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10816         else
10817                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10818
10819         if (nested_cpu_has_preemption_timer(vmcs12)) {
10820                 if (vmcs12->vm_exit_controls &
10821                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10822                         vmcs12->vmx_preemption_timer_value =
10823                                 vmx_get_preemption_timer_value(vcpu);
10824                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10825         }
10826
10827         /*
10828          * In some cases (usually, nested EPT), L2 is allowed to change its
10829          * own CR3 without exiting. If it has changed it, we must keep it.
10830          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10831          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10832          *
10833          * Additionally, restore L2's PDPTR to vmcs12.
10834          */
10835         if (enable_ept) {
10836                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10837                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10838                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10839                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10840                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10841         }
10842
10843         if (nested_cpu_has_ept(vmcs12))
10844                 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10845
10846         if (nested_cpu_has_vid(vmcs12))
10847                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10848
10849         vmcs12->vm_entry_controls =
10850                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10851                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10852
10853         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10854                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10855                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10856         }
10857
10858         /* TODO: These cannot have changed unless we have MSR bitmaps and
10859          * the relevant bit asks not to trap the change */
10860         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10861                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10862         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10863                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10864         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10865         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10866         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10867         if (kvm_mpx_supported())
10868                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10869         if (nested_cpu_has_xsaves(vmcs12))
10870                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10871 }
10872
10873 /*
10874  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10875  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10876  * and this function updates it to reflect the changes to the guest state while
10877  * L2 was running (and perhaps made some exits which were handled directly by L0
10878  * without going back to L1), and to reflect the exit reason.
10879  * Note that we do not have to copy here all VMCS fields, just those that
10880  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10881  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10882  * which already writes to vmcs12 directly.
10883  */
10884 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10885                            u32 exit_reason, u32 exit_intr_info,
10886                            unsigned long exit_qualification)
10887 {
10888         /* update guest state fields: */
10889         sync_vmcs12(vcpu, vmcs12);
10890
10891         /* update exit information fields: */
10892
10893         vmcs12->vm_exit_reason = exit_reason;
10894         vmcs12->exit_qualification = exit_qualification;
10895
10896         vmcs12->vm_exit_intr_info = exit_intr_info;
10897         if ((vmcs12->vm_exit_intr_info &
10898              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10899             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10900                 vmcs12->vm_exit_intr_error_code =
10901                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10902         vmcs12->idt_vectoring_info_field = 0;
10903         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10904         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10905
10906         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10907                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10908                  * instead of reading the real value. */
10909                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10910
10911                 /*
10912                  * Transfer the event that L0 or L1 may wanted to inject into
10913                  * L2 to IDT_VECTORING_INFO_FIELD.
10914                  */
10915                 vmcs12_save_pending_event(vcpu, vmcs12);
10916         }
10917
10918         /*
10919          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10920          * preserved above and would only end up incorrectly in L1.
10921          */
10922         vcpu->arch.nmi_injected = false;
10923         kvm_clear_exception_queue(vcpu);
10924         kvm_clear_interrupt_queue(vcpu);
10925 }
10926
10927 /*
10928  * A part of what we need to when the nested L2 guest exits and we want to
10929  * run its L1 parent, is to reset L1's guest state to the host state specified
10930  * in vmcs12.
10931  * This function is to be called not only on normal nested exit, but also on
10932  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10933  * Failures During or After Loading Guest State").
10934  * This function should be called when the active VMCS is L1's (vmcs01).
10935  */
10936 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10937                                    struct vmcs12 *vmcs12)
10938 {
10939         struct kvm_segment seg;
10940         unsigned long entry_failure_code;
10941
10942         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10943                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10944         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10945                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10946         else
10947                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10948         vmx_set_efer(vcpu, vcpu->arch.efer);
10949
10950         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10951         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10952         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10953         /*
10954          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10955          * actually changed, because it depends on the current state of
10956          * fpu_active (which may have changed).
10957          * Note that vmx_set_cr0 refers to efer set above.
10958          */
10959         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10960         /*
10961          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10962          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10963          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10964          */
10965         update_exception_bitmap(vcpu);
10966         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10967         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10968
10969         /*
10970          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10971          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10972          */
10973         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10974         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10975
10976         nested_ept_uninit_mmu_context(vcpu);
10977
10978         /*
10979          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10980          * couldn't have changed.
10981          */
10982         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10983                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10984
10985         if (!enable_ept)
10986                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10987
10988         if (enable_vpid) {
10989                 /*
10990                  * Trivially support vpid by letting L2s share their parent
10991                  * L1's vpid. TODO: move to a more elaborate solution, giving
10992                  * each L2 its own vpid and exposing the vpid feature to L1.
10993                  */
10994                 vmx_flush_tlb(vcpu);
10995         }
10996
10997
10998         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10999         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11000         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11001         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11002         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11003
11004         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
11005         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11006                 vmcs_write64(GUEST_BNDCFGS, 0);
11007
11008         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11009                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11010                 vcpu->arch.pat = vmcs12->host_ia32_pat;
11011         }
11012         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11013                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11014                         vmcs12->host_ia32_perf_global_ctrl);
11015
11016         /* Set L1 segment info according to Intel SDM
11017             27.5.2 Loading Host Segment and Descriptor-Table Registers */
11018         seg = (struct kvm_segment) {
11019                 .base = 0,
11020                 .limit = 0xFFFFFFFF,
11021                 .selector = vmcs12->host_cs_selector,
11022                 .type = 11,
11023                 .present = 1,
11024                 .s = 1,
11025                 .g = 1
11026         };
11027         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11028                 seg.l = 1;
11029         else
11030                 seg.db = 1;
11031         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11032         seg = (struct kvm_segment) {
11033                 .base = 0,
11034                 .limit = 0xFFFFFFFF,
11035                 .type = 3,
11036                 .present = 1,
11037                 .s = 1,
11038                 .db = 1,
11039                 .g = 1
11040         };
11041         seg.selector = vmcs12->host_ds_selector;
11042         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11043         seg.selector = vmcs12->host_es_selector;
11044         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11045         seg.selector = vmcs12->host_ss_selector;
11046         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11047         seg.selector = vmcs12->host_fs_selector;
11048         seg.base = vmcs12->host_fs_base;
11049         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11050         seg.selector = vmcs12->host_gs_selector;
11051         seg.base = vmcs12->host_gs_base;
11052         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11053         seg = (struct kvm_segment) {
11054                 .base = vmcs12->host_tr_base,
11055                 .limit = 0x67,
11056                 .selector = vmcs12->host_tr_selector,
11057                 .type = 11,
11058                 .present = 1
11059         };
11060         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11061
11062         kvm_set_dr(vcpu, 7, 0x400);
11063         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11064
11065         if (cpu_has_vmx_msr_bitmap())
11066                 vmx_set_msr_bitmap(vcpu);
11067
11068         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11069                                 vmcs12->vm_exit_msr_load_count))
11070                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11071 }
11072
11073 /*
11074  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11075  * and modify vmcs12 to make it see what it would expect to see there if
11076  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11077  */
11078 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11079                               u32 exit_intr_info,
11080                               unsigned long exit_qualification)
11081 {
11082         struct vcpu_vmx *vmx = to_vmx(vcpu);
11083         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11084         u32 vm_inst_error = 0;
11085
11086         /* trying to cancel vmlaunch/vmresume is a bug */
11087         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11088
11089         leave_guest_mode(vcpu);
11090         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11091                        exit_qualification);
11092
11093         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11094                                  vmcs12->vm_exit_msr_store_count))
11095                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11096
11097         if (unlikely(vmx->fail))
11098                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11099
11100         vmx_load_vmcs01(vcpu);
11101
11102         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11103             && nested_exit_intr_ack_set(vcpu)) {
11104                 int irq = kvm_cpu_get_interrupt(vcpu);
11105                 WARN_ON(irq < 0);
11106                 vmcs12->vm_exit_intr_info = irq |
11107                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11108         }
11109
11110         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11111                                        vmcs12->exit_qualification,
11112                                        vmcs12->idt_vectoring_info_field,
11113                                        vmcs12->vm_exit_intr_info,
11114                                        vmcs12->vm_exit_intr_error_code,
11115                                        KVM_ISA_VMX);
11116
11117         vm_entry_controls_reset_shadow(vmx);
11118         vm_exit_controls_reset_shadow(vmx);
11119         vmx_segment_cache_clear(vmx);
11120
11121         /* if no vmcs02 cache requested, remove the one we used */
11122         if (VMCS02_POOL_SIZE == 0)
11123                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11124
11125         load_vmcs12_host_state(vcpu, vmcs12);
11126
11127         /* Update any VMCS fields that might have changed while L2 ran */
11128         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11129         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11130         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11131         if (vmx->hv_deadline_tsc == -1)
11132                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11133                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11134         else
11135                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11136                               PIN_BASED_VMX_PREEMPTION_TIMER);
11137         if (kvm_has_tsc_control)
11138                 decache_tsc_multiplier(vmx);
11139
11140         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11141                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11142                 vmx_set_virtual_x2apic_mode(vcpu,
11143                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11144         }
11145
11146         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11147         vmx->host_rsp = 0;
11148
11149         /* Unpin physical memory we referred to in vmcs02 */
11150         if (vmx->nested.apic_access_page) {
11151                 nested_release_page(vmx->nested.apic_access_page);
11152                 vmx->nested.apic_access_page = NULL;
11153         }
11154         if (vmx->nested.virtual_apic_page) {
11155                 nested_release_page(vmx->nested.virtual_apic_page);
11156                 vmx->nested.virtual_apic_page = NULL;
11157         }
11158         if (vmx->nested.pi_desc_page) {
11159                 kunmap(vmx->nested.pi_desc_page);
11160                 nested_release_page(vmx->nested.pi_desc_page);
11161                 vmx->nested.pi_desc_page = NULL;
11162                 vmx->nested.pi_desc = NULL;
11163         }
11164
11165         /*
11166          * We are now running in L2, mmu_notifier will force to reload the
11167          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11168          */
11169         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11170
11171         /*
11172          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11173          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11174          * success or failure flag accordingly.
11175          */
11176         if (unlikely(vmx->fail)) {
11177                 vmx->fail = 0;
11178                 nested_vmx_failValid(vcpu, vm_inst_error);
11179         } else
11180                 nested_vmx_succeed(vcpu);
11181         if (enable_shadow_vmcs)
11182                 vmx->nested.sync_shadow_vmcs = true;
11183
11184         /* in case we halted in L2 */
11185         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11186 }
11187
11188 /*
11189  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11190  */
11191 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11192 {
11193         if (is_guest_mode(vcpu))
11194                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11195         free_nested(to_vmx(vcpu));
11196 }
11197
11198 /*
11199  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11200  * 23.7 "VM-entry failures during or after loading guest state" (this also
11201  * lists the acceptable exit-reason and exit-qualification parameters).
11202  * It should only be called before L2 actually succeeded to run, and when
11203  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11204  */
11205 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11206                         struct vmcs12 *vmcs12,
11207                         u32 reason, unsigned long qualification)
11208 {
11209         load_vmcs12_host_state(vcpu, vmcs12);
11210         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11211         vmcs12->exit_qualification = qualification;
11212         nested_vmx_succeed(vcpu);
11213         if (enable_shadow_vmcs)
11214                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11215 }
11216
11217 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11218                                struct x86_instruction_info *info,
11219                                enum x86_intercept_stage stage)
11220 {
11221         return X86EMUL_CONTINUE;
11222 }
11223
11224 #ifdef CONFIG_X86_64
11225 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11226 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11227                                   u64 divisor, u64 *result)
11228 {
11229         u64 low = a << shift, high = a >> (64 - shift);
11230
11231         /* To avoid the overflow on divq */
11232         if (high >= divisor)
11233                 return 1;
11234
11235         /* Low hold the result, high hold rem which is discarded */
11236         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11237             "rm" (divisor), "0" (low), "1" (high));
11238         *result = low;
11239
11240         return 0;
11241 }
11242
11243 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11244 {
11245         struct vcpu_vmx *vmx = to_vmx(vcpu);
11246         u64 tscl = rdtsc();
11247         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11248         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11249
11250         /* Convert to host delta tsc if tsc scaling is enabled */
11251         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11252                         u64_shl_div_u64(delta_tsc,
11253                                 kvm_tsc_scaling_ratio_frac_bits,
11254                                 vcpu->arch.tsc_scaling_ratio,
11255                                 &delta_tsc))
11256                 return -ERANGE;
11257
11258         /*
11259          * If the delta tsc can't fit in the 32 bit after the multi shift,
11260          * we can't use the preemption timer.
11261          * It's possible that it fits on later vmentries, but checking
11262          * on every vmentry is costly so we just use an hrtimer.
11263          */
11264         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11265                 return -ERANGE;
11266
11267         vmx->hv_deadline_tsc = tscl + delta_tsc;
11268         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11269                         PIN_BASED_VMX_PREEMPTION_TIMER);
11270         return 0;
11271 }
11272
11273 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11274 {
11275         struct vcpu_vmx *vmx = to_vmx(vcpu);
11276         vmx->hv_deadline_tsc = -1;
11277         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11278                         PIN_BASED_VMX_PREEMPTION_TIMER);
11279 }
11280 #endif
11281
11282 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11283 {
11284         if (ple_gap)
11285                 shrink_ple_window(vcpu);
11286 }
11287
11288 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11289                                      struct kvm_memory_slot *slot)
11290 {
11291         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11292         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11293 }
11294
11295 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11296                                        struct kvm_memory_slot *slot)
11297 {
11298         kvm_mmu_slot_set_dirty(kvm, slot);
11299 }
11300
11301 static void vmx_flush_log_dirty(struct kvm *kvm)
11302 {
11303         kvm_flush_pml_buffers(kvm);
11304 }
11305
11306 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11307                                            struct kvm_memory_slot *memslot,
11308                                            gfn_t offset, unsigned long mask)
11309 {
11310         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11311 }
11312
11313 /*
11314  * This routine does the following things for vCPU which is going
11315  * to be blocked if VT-d PI is enabled.
11316  * - Store the vCPU to the wakeup list, so when interrupts happen
11317  *   we can find the right vCPU to wake up.
11318  * - Change the Posted-interrupt descriptor as below:
11319  *      'NDST' <-- vcpu->pre_pcpu
11320  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11321  * - If 'ON' is set during this process, which means at least one
11322  *   interrupt is posted for this vCPU, we cannot block it, in
11323  *   this case, return 1, otherwise, return 0.
11324  *
11325  */
11326 static int pi_pre_block(struct kvm_vcpu *vcpu)
11327 {
11328         unsigned long flags;
11329         unsigned int dest;
11330         struct pi_desc old, new;
11331         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11332
11333         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11334                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11335                 !kvm_vcpu_apicv_active(vcpu))
11336                 return 0;
11337
11338         vcpu->pre_pcpu = vcpu->cpu;
11339         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11340                           vcpu->pre_pcpu), flags);
11341         list_add_tail(&vcpu->blocked_vcpu_list,
11342                       &per_cpu(blocked_vcpu_on_cpu,
11343                       vcpu->pre_pcpu));
11344         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11345                                vcpu->pre_pcpu), flags);
11346
11347         do {
11348                 old.control = new.control = pi_desc->control;
11349
11350                 /*
11351                  * We should not block the vCPU if
11352                  * an interrupt is posted for it.
11353                  */
11354                 if (pi_test_on(pi_desc) == 1) {
11355                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11356                                           vcpu->pre_pcpu), flags);
11357                         list_del(&vcpu->blocked_vcpu_list);
11358                         spin_unlock_irqrestore(
11359                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11360                                         vcpu->pre_pcpu), flags);
11361                         vcpu->pre_pcpu = -1;
11362
11363                         return 1;
11364                 }
11365
11366                 WARN((pi_desc->sn == 1),
11367                      "Warning: SN field of posted-interrupts "
11368                      "is set before blocking\n");
11369
11370                 /*
11371                  * Since vCPU can be preempted during this process,
11372                  * vcpu->cpu could be different with pre_pcpu, we
11373                  * need to set pre_pcpu as the destination of wakeup
11374                  * notification event, then we can find the right vCPU
11375                  * to wakeup in wakeup handler if interrupts happen
11376                  * when the vCPU is in blocked state.
11377                  */
11378                 dest = cpu_physical_id(vcpu->pre_pcpu);
11379
11380                 if (x2apic_enabled())
11381                         new.ndst = dest;
11382                 else
11383                         new.ndst = (dest << 8) & 0xFF00;
11384
11385                 /* set 'NV' to 'wakeup vector' */
11386                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11387         } while (cmpxchg(&pi_desc->control, old.control,
11388                         new.control) != old.control);
11389
11390         return 0;
11391 }
11392
11393 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11394 {
11395         if (pi_pre_block(vcpu))
11396                 return 1;
11397
11398         if (kvm_lapic_hv_timer_in_use(vcpu))
11399                 kvm_lapic_switch_to_sw_timer(vcpu);
11400
11401         return 0;
11402 }
11403
11404 static void pi_post_block(struct kvm_vcpu *vcpu)
11405 {
11406         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11407         struct pi_desc old, new;
11408         unsigned int dest;
11409         unsigned long flags;
11410
11411         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11412                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11413                 !kvm_vcpu_apicv_active(vcpu))
11414                 return;
11415
11416         do {
11417                 old.control = new.control = pi_desc->control;
11418
11419                 dest = cpu_physical_id(vcpu->cpu);
11420
11421                 if (x2apic_enabled())
11422                         new.ndst = dest;
11423                 else
11424                         new.ndst = (dest << 8) & 0xFF00;
11425
11426                 /* Allow posting non-urgent interrupts */
11427                 new.sn = 0;
11428
11429                 /* set 'NV' to 'notification vector' */
11430                 new.nv = POSTED_INTR_VECTOR;
11431         } while (cmpxchg(&pi_desc->control, old.control,
11432                         new.control) != old.control);
11433
11434         if(vcpu->pre_pcpu != -1) {
11435                 spin_lock_irqsave(
11436                         &per_cpu(blocked_vcpu_on_cpu_lock,
11437                         vcpu->pre_pcpu), flags);
11438                 list_del(&vcpu->blocked_vcpu_list);
11439                 spin_unlock_irqrestore(
11440                         &per_cpu(blocked_vcpu_on_cpu_lock,
11441                         vcpu->pre_pcpu), flags);
11442                 vcpu->pre_pcpu = -1;
11443         }
11444 }
11445
11446 static void vmx_post_block(struct kvm_vcpu *vcpu)
11447 {
11448         if (kvm_x86_ops->set_hv_timer)
11449                 kvm_lapic_switch_to_hv_timer(vcpu);
11450
11451         pi_post_block(vcpu);
11452 }
11453
11454 /*
11455  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11456  *
11457  * @kvm: kvm
11458  * @host_irq: host irq of the interrupt
11459  * @guest_irq: gsi of the interrupt
11460  * @set: set or unset PI
11461  * returns 0 on success, < 0 on failure
11462  */
11463 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11464                               uint32_t guest_irq, bool set)
11465 {
11466         struct kvm_kernel_irq_routing_entry *e;
11467         struct kvm_irq_routing_table *irq_rt;
11468         struct kvm_lapic_irq irq;
11469         struct kvm_vcpu *vcpu;
11470         struct vcpu_data vcpu_info;
11471         int idx, ret = -EINVAL;
11472
11473         if (!kvm_arch_has_assigned_device(kvm) ||
11474                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11475                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11476                 return 0;
11477
11478         idx = srcu_read_lock(&kvm->irq_srcu);
11479         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11480         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11481
11482         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11483                 if (e->type != KVM_IRQ_ROUTING_MSI)
11484                         continue;
11485                 /*
11486                  * VT-d PI cannot support posting multicast/broadcast
11487                  * interrupts to a vCPU, we still use interrupt remapping
11488                  * for these kind of interrupts.
11489                  *
11490                  * For lowest-priority interrupts, we only support
11491                  * those with single CPU as the destination, e.g. user
11492                  * configures the interrupts via /proc/irq or uses
11493                  * irqbalance to make the interrupts single-CPU.
11494                  *
11495                  * We will support full lowest-priority interrupt later.
11496                  */
11497
11498                 kvm_set_msi_irq(kvm, e, &irq);
11499                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11500                         /*
11501                          * Make sure the IRTE is in remapped mode if
11502                          * we don't handle it in posted mode.
11503                          */
11504                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11505                         if (ret < 0) {
11506                                 printk(KERN_INFO
11507                                    "failed to back to remapped mode, irq: %u\n",
11508                                    host_irq);
11509                                 goto out;
11510                         }
11511
11512                         continue;
11513                 }
11514
11515                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11516                 vcpu_info.vector = irq.vector;
11517
11518                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11519                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11520
11521                 if (set)
11522                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11523                 else {
11524                         /* suppress notification event before unposting */
11525                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11526                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11527                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11528                 }
11529
11530                 if (ret < 0) {
11531                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11532                                         __func__);
11533                         goto out;
11534                 }
11535         }
11536
11537         ret = 0;
11538 out:
11539         srcu_read_unlock(&kvm->irq_srcu, idx);
11540         return ret;
11541 }
11542
11543 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11544 {
11545         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11546                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11547                         FEATURE_CONTROL_LMCE;
11548         else
11549                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11550                         ~FEATURE_CONTROL_LMCE;
11551 }
11552
11553 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11554         .cpu_has_kvm_support = cpu_has_kvm_support,
11555         .disabled_by_bios = vmx_disabled_by_bios,
11556         .hardware_setup = hardware_setup,
11557         .hardware_unsetup = hardware_unsetup,
11558         .check_processor_compatibility = vmx_check_processor_compat,
11559         .hardware_enable = hardware_enable,
11560         .hardware_disable = hardware_disable,
11561         .cpu_has_accelerated_tpr = report_flexpriority,
11562         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11563
11564         .vcpu_create = vmx_create_vcpu,
11565         .vcpu_free = vmx_free_vcpu,
11566         .vcpu_reset = vmx_vcpu_reset,
11567
11568         .prepare_guest_switch = vmx_save_host_state,
11569         .vcpu_load = vmx_vcpu_load,
11570         .vcpu_put = vmx_vcpu_put,
11571
11572         .update_bp_intercept = update_exception_bitmap,
11573         .get_msr = vmx_get_msr,
11574         .set_msr = vmx_set_msr,
11575         .get_segment_base = vmx_get_segment_base,
11576         .get_segment = vmx_get_segment,
11577         .set_segment = vmx_set_segment,
11578         .get_cpl = vmx_get_cpl,
11579         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11580         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11581         .decache_cr3 = vmx_decache_cr3,
11582         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11583         .set_cr0 = vmx_set_cr0,
11584         .set_cr3 = vmx_set_cr3,
11585         .set_cr4 = vmx_set_cr4,
11586         .set_efer = vmx_set_efer,
11587         .get_idt = vmx_get_idt,
11588         .set_idt = vmx_set_idt,
11589         .get_gdt = vmx_get_gdt,
11590         .set_gdt = vmx_set_gdt,
11591         .get_dr6 = vmx_get_dr6,
11592         .set_dr6 = vmx_set_dr6,
11593         .set_dr7 = vmx_set_dr7,
11594         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11595         .cache_reg = vmx_cache_reg,
11596         .get_rflags = vmx_get_rflags,
11597         .set_rflags = vmx_set_rflags,
11598
11599         .get_pkru = vmx_get_pkru,
11600
11601         .fpu_activate = vmx_fpu_activate,
11602         .fpu_deactivate = vmx_fpu_deactivate,
11603
11604         .tlb_flush = vmx_flush_tlb,
11605
11606         .run = vmx_vcpu_run,
11607         .handle_exit = vmx_handle_exit,
11608         .skip_emulated_instruction = skip_emulated_instruction,
11609         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11610         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11611         .patch_hypercall = vmx_patch_hypercall,
11612         .set_irq = vmx_inject_irq,
11613         .set_nmi = vmx_inject_nmi,
11614         .queue_exception = vmx_queue_exception,
11615         .cancel_injection = vmx_cancel_injection,
11616         .interrupt_allowed = vmx_interrupt_allowed,
11617         .nmi_allowed = vmx_nmi_allowed,
11618         .get_nmi_mask = vmx_get_nmi_mask,
11619         .set_nmi_mask = vmx_set_nmi_mask,
11620         .enable_nmi_window = enable_nmi_window,
11621         .enable_irq_window = enable_irq_window,
11622         .update_cr8_intercept = update_cr8_intercept,
11623         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11624         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11625         .get_enable_apicv = vmx_get_enable_apicv,
11626         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11627         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11628         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11629         .hwapic_irr_update = vmx_hwapic_irr_update,
11630         .hwapic_isr_update = vmx_hwapic_isr_update,
11631         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11632         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11633
11634         .set_tss_addr = vmx_set_tss_addr,
11635         .get_tdp_level = get_ept_level,
11636         .get_mt_mask = vmx_get_mt_mask,
11637
11638         .get_exit_info = vmx_get_exit_info,
11639
11640         .get_lpage_level = vmx_get_lpage_level,
11641
11642         .cpuid_update = vmx_cpuid_update,
11643
11644         .rdtscp_supported = vmx_rdtscp_supported,
11645         .invpcid_supported = vmx_invpcid_supported,
11646
11647         .set_supported_cpuid = vmx_set_supported_cpuid,
11648
11649         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11650
11651         .write_tsc_offset = vmx_write_tsc_offset,
11652
11653         .set_tdp_cr3 = vmx_set_cr3,
11654
11655         .check_intercept = vmx_check_intercept,
11656         .handle_external_intr = vmx_handle_external_intr,
11657         .mpx_supported = vmx_mpx_supported,
11658         .xsaves_supported = vmx_xsaves_supported,
11659
11660         .check_nested_events = vmx_check_nested_events,
11661
11662         .sched_in = vmx_sched_in,
11663
11664         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11665         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11666         .flush_log_dirty = vmx_flush_log_dirty,
11667         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11668
11669         .pre_block = vmx_pre_block,
11670         .post_block = vmx_post_block,
11671
11672         .pmu_ops = &intel_pmu_ops,
11673
11674         .update_pi_irte = vmx_update_pi_irte,
11675
11676 #ifdef CONFIG_X86_64
11677         .set_hv_timer = vmx_set_hv_timer,
11678         .cancel_hv_timer = vmx_cancel_hv_timer,
11679 #endif
11680
11681         .setup_mce = vmx_setup_mce,
11682 };
11683
11684 static int __init vmx_init(void)
11685 {
11686         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11687                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11688         if (r)
11689                 return r;
11690
11691 #ifdef CONFIG_KEXEC_CORE
11692         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11693                            crash_vmclear_local_loaded_vmcss);
11694 #endif
11695
11696         return 0;
11697 }
11698
11699 static void __exit vmx_exit(void)
11700 {
11701 #ifdef CONFIG_KEXEC_CORE
11702         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11703         synchronize_rcu();
11704 #endif
11705
11706         kvm_exit();
11707 }
11708
11709 module_init(vmx_init)
11710 module_exit(vmx_exit)