arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include <linux/nospec.h>
  38 #include "kvm_cache_regs.h"
  39 #include "x86.h"
  40
  41 #include <asm/asm.h>
  42 #include <asm/cpu.h>
  43 #include <asm/io.h>
  44 #include <asm/desc.h>
  45 #include <asm/vmx.h>
  46 #include <asm/virtext.h>
  47 #include <asm/mce.h>
  48 #include <asm/fpu/internal.h>
  49 #include <asm/perf_event.h>
  50 #include <asm/debugreg.h>
  51 #include <asm/kexec.h>
  52 #include <asm/apic.h>
  53 #include <asm/irq_remapping.h>
  54 #include <asm/mmu_context.h>
  55 #include <asm/spec-ctrl.h>
  56 #include <asm/mshyperv.h>
  57
  58 #include "trace.h"
  59 #include "pmu.h"
  60 #include "vmx_evmcs.h"
  61
  62 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  63 #define __ex_clear(x, reg) \
  64         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  65
  66 MODULE_AUTHOR("Qumranet");
  67 MODULE_LICENSE("GPL");
  68
  69 static const struct x86_cpu_id vmx_cpu_id[] = {
  70         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  71         {}
  72 };
  73 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  74
  75 static bool __read_mostly enable_vpid = 1;
  76 module_param_named(vpid, enable_vpid, bool, 0444);
  77
  78 static bool __read_mostly enable_vnmi = 1;
  79 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  80
  81 static bool __read_mostly flexpriority_enabled = 1;
  82 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  83
  84 static bool __read_mostly enable_ept = 1;
  85 module_param_named(ept, enable_ept, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_unrestricted_guest = 1;
  88 module_param_named(unrestricted_guest,
  89                         enable_unrestricted_guest, bool, S_IRUGO);
  90
  91 static bool __read_mostly enable_ept_ad_bits = 1;
  92 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  93
  94 static bool __read_mostly emulate_invalid_guest_state = true;
  95 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  96
  97 static bool __read_mostly fasteoi = 1;
  98 module_param(fasteoi, bool, S_IRUGO);
  99
 100 static bool __read_mostly enable_apicv = 1;
 101 module_param(enable_apicv, bool, S_IRUGO);
 102
 103 static bool __read_mostly enable_shadow_vmcs = 1;
 104 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
 105 /*
 106  * If nested=1, nested virtualization is supported, i.e., guests may use
 107  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 108  * use VMX instructions.
 109  */
 110 static bool __read_mostly nested = 0;
 111 module_param(nested, bool, S_IRUGO);
 112
 113 static u64 __read_mostly host_xss;
 114
 115 static bool __read_mostly enable_pml = 1;
 116 module_param_named(pml, enable_pml, bool, S_IRUGO);
 117
 118 #define MSR_TYPE_R      1
 119 #define MSR_TYPE_W      2
 120 #define MSR_TYPE_RW     3
 121
 122 #define MSR_BITMAP_MODE_X2APIC          1
 123 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 124
 125 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 126
 127 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 128 static int __read_mostly cpu_preemption_timer_multi;
 129 static bool __read_mostly enable_preemption_timer = 1;
 130 #ifdef CONFIG_X86_64
 131 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 132 #endif
 133
 134 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 135 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 136 #define KVM_VM_CR0_ALWAYS_ON                            \
 137         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 138          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 139 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 140         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 141          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 142
 143 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 144 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 145 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 146
 147 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 148
 149 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 150
 151 /*
 152  * Hyper-V requires all of these, so mark them as supported even though
 153  * they are just treated the same as all-context.
 154  */
 155 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 156         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 157         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 158         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 159         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 160
 161 /*
 162  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 163  * ple_gap:    upper bound on the amount of time between two successive
 164  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 165  *             According to test, this time is usually smaller than 128 cycles.
 166  * ple_window: upper bound on the amount of time a guest is allowed to execute
 167  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 168  *             less than 2^12 cycles
 169  * Time is measured based on a counter that runs at the same rate as the TSC,
 170  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 171  */
 172 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 173
 174 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 175 module_param(ple_window, uint, 0444);
 176
 177 /* Default doubles per-vcpu window every exit. */
 178 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 179 module_param(ple_window_grow, uint, 0444);
 180
 181 /* Default resets per-vcpu window every exit to ple_window. */
 182 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 183 module_param(ple_window_shrink, uint, 0444);
 184
 185 /* Default is to compute the maximum so we can never overflow. */
 186 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 187 module_param(ple_window_max, uint, 0444);
 188
 189 extern const ulong vmx_return;
 190
 191 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 192 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 193 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 194
 195 /* Storage for pre module init parameter parsing */
 196 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 197
 198 static const struct {
 199         const char *option;
 200         bool for_parse;
 201 } vmentry_l1d_param[] = {
 202         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 203         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 204         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 205         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 206         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 207         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 208 };
 209
 210 #define L1D_CACHE_ORDER 4
 211 static void *vmx_l1d_flush_pages;
 212
 213 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 214 {
 215         struct page *page;
 216         unsigned int i;
 217
 218         if (!enable_ept) {
 219                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 220                 return 0;
 221         }
 222
 223         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 224                 u64 msr;
 225
 226                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 227                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 228                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 229                         return 0;
 230                 }
 231         }
 232
 233         /* If set to auto use the default l1tf mitigation method */
 234         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 235                 switch (l1tf_mitigation) {
 236                 case L1TF_MITIGATION_OFF:
 237                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 238                         break;
 239                 case L1TF_MITIGATION_FLUSH_NOWARN:
 240                 case L1TF_MITIGATION_FLUSH:
 241                 case L1TF_MITIGATION_FLUSH_NOSMT:
 242                         l1tf = VMENTER_L1D_FLUSH_COND;
 243                         break;
 244                 case L1TF_MITIGATION_FULL:
 245                 case L1TF_MITIGATION_FULL_FORCE:
 246                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 247                         break;
 248                 }
 249         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 250                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 251         }
 252
 253         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 254             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 255                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 256                 if (!page)
 257                         return -ENOMEM;
 258                 vmx_l1d_flush_pages = page_address(page);
 259
 260                 /*
 261                  * Initialize each page with a different pattern in
 262                  * order to protect against KSM in the nested
 263                  * virtualization case.
 264                  */
 265                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 266                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 267                                PAGE_SIZE);
 268                 }
 269         }
 270
 271         l1tf_vmx_mitigation = l1tf;
 272
 273         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 274                 static_branch_enable(&vmx_l1d_should_flush);
 275         else
 276                 static_branch_disable(&vmx_l1d_should_flush);
 277
 278         if (l1tf == VMENTER_L1D_FLUSH_COND)
 279                 static_branch_enable(&vmx_l1d_flush_cond);
 280         else
 281                 static_branch_disable(&vmx_l1d_flush_cond);
 282         return 0;
 283 }
 284
 285 static int vmentry_l1d_flush_parse(const char *s)
 286 {
 287         unsigned int i;
 288
 289         if (s) {
 290                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 291                         if (vmentry_l1d_param[i].for_parse &&
 292                             sysfs_streq(s, vmentry_l1d_param[i].option))
 293                                 return i;
 294                 }
 295         }
 296         return -EINVAL;
 297 }
 298
 299 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 300 {
 301         int l1tf, ret;
 302
 303         l1tf = vmentry_l1d_flush_parse(s);
 304         if (l1tf < 0)
 305                 return l1tf;
 306
 307         if (!boot_cpu_has(X86_BUG_L1TF))
 308                 return 0;
 309
 310         /*
 311          * Has vmx_init() run already? If not then this is the pre init
 312          * parameter parsing. In that case just store the value and let
 313          * vmx_init() do the proper setup after enable_ept has been
 314          * established.
 315          */
 316         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 317                 vmentry_l1d_flush_param = l1tf;
 318                 return 0;
 319         }
 320
 321         mutex_lock(&vmx_l1d_flush_mutex);
 322         ret = vmx_setup_l1d_flush(l1tf);
 323         mutex_unlock(&vmx_l1d_flush_mutex);
 324         return ret;
 325 }
 326
 327 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 328 {
 329         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 330                 return sprintf(s, "???\n");
 331
 332         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 333 }
 334
 335 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 336         .set = vmentry_l1d_flush_set,
 337         .get = vmentry_l1d_flush_get,
 338 };
 339 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 340
 341 enum ept_pointers_status {
 342         EPT_POINTERS_CHECK = 0,
 343         EPT_POINTERS_MATCH = 1,
 344         EPT_POINTERS_MISMATCH = 2
 345 };
 346
 347 struct kvm_vmx {
 348         struct kvm kvm;
 349
 350         unsigned int tss_addr;
 351         bool ept_identity_pagetable_done;
 352         gpa_t ept_identity_map_addr;
 353
 354         enum ept_pointers_status ept_pointers_match;
 355         spinlock_t ept_pointer_lock;
 356 };
 357
 358 #define NR_AUTOLOAD_MSRS 8
 359
 360 struct vmcs_hdr {
 361         u32 revision_id:31;
 362         u32 shadow_vmcs:1;
 363 };
 364
 365 struct vmcs {
 366         struct vmcs_hdr hdr;
 367         u32 abort;
 368         char data[0];
 369 };
 370
 371 /*
 372  * vmcs_host_state tracks registers that are loaded from the VMCS on VMEXIT
 373  * and whose values change infrequently, but are not constant.  I.e. this is
 374  * used as a write-through cache of the corresponding VMCS fields.
 375  */
 376 struct vmcs_host_state {
 377         unsigned long cr3;      /* May not match real cr3 */
 378         unsigned long cr4;      /* May not match real cr4 */
 379         unsigned long gs_base;
 380         unsigned long fs_base;
 381
 382         u16           fs_sel, gs_sel, ldt_sel;
 383 #ifdef CONFIG_X86_64
 384         u16           ds_sel, es_sel;
 385 #endif
 386 };
 387
 388 /*
 389  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 390  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 391  * loaded on this CPU (so we can clear them if the CPU goes down).
 392  */
 393 struct loaded_vmcs {
 394         struct vmcs *vmcs;
 395         struct vmcs *shadow_vmcs;
 396         int cpu;
 397         bool launched;
 398         bool nmi_known_unmasked;
 399         bool hv_timer_armed;
 400         /* Support for vnmi-less CPUs */
 401         int soft_vnmi_blocked;
 402         ktime_t entry_time;
 403         s64 vnmi_blocked_time;
 404         unsigned long *msr_bitmap;
 405         struct list_head loaded_vmcss_on_cpu_link;
 406         struct vmcs_host_state host_state;
 407 };
 408
 409 struct shared_msr_entry {
 410         unsigned index;
 411         u64 data;
 412         u64 mask;
 413 };
 414
 415 /*
 416  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 417  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 418  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 419  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 420  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 421  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 422  * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
 423  * underlying hardware which will be used to run L2.
 424  * This structure is packed to ensure that its layout is identical across
 425  * machines (necessary for live migration).
 426  *
 427  * IMPORTANT: Changing the layout of existing fields in this structure
 428  * will break save/restore compatibility with older kvm releases. When
 429  * adding new fields, either use space in the reserved padding* arrays
 430  * or add the new fields to the end of the structure.
 431  */
 432 typedef u64 natural_width;
 433 struct __packed vmcs12 {
 434         /* According to the Intel spec, a VMCS region must start with the
 435          * following two fields. Then follow implementation-specific data.
 436          */
 437         struct vmcs_hdr hdr;
 438         u32 abort;
 439
 440         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 441         u32 padding[7]; /* room for future expansion */
 442
 443         u64 io_bitmap_a;
 444         u64 io_bitmap_b;
 445         u64 msr_bitmap;
 446         u64 vm_exit_msr_store_addr;
 447         u64 vm_exit_msr_load_addr;
 448         u64 vm_entry_msr_load_addr;
 449         u64 tsc_offset;
 450         u64 virtual_apic_page_addr;
 451         u64 apic_access_addr;
 452         u64 posted_intr_desc_addr;
 453         u64 ept_pointer;
 454         u64 eoi_exit_bitmap0;
 455         u64 eoi_exit_bitmap1;
 456         u64 eoi_exit_bitmap2;
 457         u64 eoi_exit_bitmap3;
 458         u64 xss_exit_bitmap;
 459         u64 guest_physical_address;
 460         u64 vmcs_link_pointer;
 461         u64 guest_ia32_debugctl;
 462         u64 guest_ia32_pat;
 463         u64 guest_ia32_efer;
 464         u64 guest_ia32_perf_global_ctrl;
 465         u64 guest_pdptr0;
 466         u64 guest_pdptr1;
 467         u64 guest_pdptr2;
 468         u64 guest_pdptr3;
 469         u64 guest_bndcfgs;
 470         u64 host_ia32_pat;
 471         u64 host_ia32_efer;
 472         u64 host_ia32_perf_global_ctrl;
 473         u64 vmread_bitmap;
 474         u64 vmwrite_bitmap;
 475         u64 vm_function_control;
 476         u64 eptp_list_address;
 477         u64 pml_address;
 478         u64 padding64[3]; /* room for future expansion */
 479         /*
 480          * To allow migration of L1 (complete with its L2 guests) between
 481          * machines of different natural widths (32 or 64 bit), we cannot have
 482          * unsigned long fields with no explict size. We use u64 (aliased
 483          * natural_width) instead. Luckily, x86 is little-endian.
 484          */
 485         natural_width cr0_guest_host_mask;
 486         natural_width cr4_guest_host_mask;
 487         natural_width cr0_read_shadow;
 488         natural_width cr4_read_shadow;
 489         natural_width cr3_target_value0;
 490         natural_width cr3_target_value1;
 491         natural_width cr3_target_value2;
 492         natural_width cr3_target_value3;
 493         natural_width exit_qualification;
 494         natural_width guest_linear_address;
 495         natural_width guest_cr0;
 496         natural_width guest_cr3;
 497         natural_width guest_cr4;
 498         natural_width guest_es_base;
 499         natural_width guest_cs_base;
 500         natural_width guest_ss_base;
 501         natural_width guest_ds_base;
 502         natural_width guest_fs_base;
 503         natural_width guest_gs_base;
 504         natural_width guest_ldtr_base;
 505         natural_width guest_tr_base;
 506         natural_width guest_gdtr_base;
 507         natural_width guest_idtr_base;
 508         natural_width guest_dr7;
 509         natural_width guest_rsp;
 510         natural_width guest_rip;
 511         natural_width guest_rflags;
 512         natural_width guest_pending_dbg_exceptions;
 513         natural_width guest_sysenter_esp;
 514         natural_width guest_sysenter_eip;
 515         natural_width host_cr0;
 516         natural_width host_cr3;
 517         natural_width host_cr4;
 518         natural_width host_fs_base;
 519         natural_width host_gs_base;
 520         natural_width host_tr_base;
 521         natural_width host_gdtr_base;
 522         natural_width host_idtr_base;
 523         natural_width host_ia32_sysenter_esp;
 524         natural_width host_ia32_sysenter_eip;
 525         natural_width host_rsp;
 526         natural_width host_rip;
 527         natural_width paddingl[8]; /* room for future expansion */
 528         u32 pin_based_vm_exec_control;
 529         u32 cpu_based_vm_exec_control;
 530         u32 exception_bitmap;
 531         u32 page_fault_error_code_mask;
 532         u32 page_fault_error_code_match;
 533         u32 cr3_target_count;
 534         u32 vm_exit_controls;
 535         u32 vm_exit_msr_store_count;
 536         u32 vm_exit_msr_load_count;
 537         u32 vm_entry_controls;
 538         u32 vm_entry_msr_load_count;
 539         u32 vm_entry_intr_info_field;
 540         u32 vm_entry_exception_error_code;
 541         u32 vm_entry_instruction_len;
 542         u32 tpr_threshold;
 543         u32 secondary_vm_exec_control;
 544         u32 vm_instruction_error;
 545         u32 vm_exit_reason;
 546         u32 vm_exit_intr_info;
 547         u32 vm_exit_intr_error_code;
 548         u32 idt_vectoring_info_field;
 549         u32 idt_vectoring_error_code;
 550         u32 vm_exit_instruction_len;
 551         u32 vmx_instruction_info;
 552         u32 guest_es_limit;
 553         u32 guest_cs_limit;
 554         u32 guest_ss_limit;
 555         u32 guest_ds_limit;
 556         u32 guest_fs_limit;
 557         u32 guest_gs_limit;
 558         u32 guest_ldtr_limit;
 559         u32 guest_tr_limit;
 560         u32 guest_gdtr_limit;
 561         u32 guest_idtr_limit;
 562         u32 guest_es_ar_bytes;
 563         u32 guest_cs_ar_bytes;
 564         u32 guest_ss_ar_bytes;
 565         u32 guest_ds_ar_bytes;
 566         u32 guest_fs_ar_bytes;
 567         u32 guest_gs_ar_bytes;
 568         u32 guest_ldtr_ar_bytes;
 569         u32 guest_tr_ar_bytes;
 570         u32 guest_interruptibility_info;
 571         u32 guest_activity_state;
 572         u32 guest_sysenter_cs;
 573         u32 host_ia32_sysenter_cs;
 574         u32 vmx_preemption_timer_value;
 575         u32 padding32[7]; /* room for future expansion */
 576         u16 virtual_processor_id;
 577         u16 posted_intr_nv;
 578         u16 guest_es_selector;
 579         u16 guest_cs_selector;
 580         u16 guest_ss_selector;
 581         u16 guest_ds_selector;
 582         u16 guest_fs_selector;
 583         u16 guest_gs_selector;
 584         u16 guest_ldtr_selector;
 585         u16 guest_tr_selector;
 586         u16 guest_intr_status;
 587         u16 host_es_selector;
 588         u16 host_cs_selector;
 589         u16 host_ss_selector;
 590         u16 host_ds_selector;
 591         u16 host_fs_selector;
 592         u16 host_gs_selector;
 593         u16 host_tr_selector;
 594         u16 guest_pml_index;
 595 };
 596
 597 /*
 598  * For save/restore compatibility, the vmcs12 field offsets must not change.
 599  */
 600 #define CHECK_OFFSET(field, loc)                                \
 601         BUILD_BUG_ON_MSG(offsetof(struct vmcs12, field) != (loc),       \
 602                 "Offset of " #field " in struct vmcs12 has changed.")
 603
 604 static inline void vmx_check_vmcs12_offsets(void) {
 605         CHECK_OFFSET(hdr, 0);
 606         CHECK_OFFSET(abort, 4);
 607         CHECK_OFFSET(launch_state, 8);
 608         CHECK_OFFSET(io_bitmap_a, 40);
 609         CHECK_OFFSET(io_bitmap_b, 48);
 610         CHECK_OFFSET(msr_bitmap, 56);
 611         CHECK_OFFSET(vm_exit_msr_store_addr, 64);
 612         CHECK_OFFSET(vm_exit_msr_load_addr, 72);
 613         CHECK_OFFSET(vm_entry_msr_load_addr, 80);
 614         CHECK_OFFSET(tsc_offset, 88);
 615         CHECK_OFFSET(virtual_apic_page_addr, 96);
 616         CHECK_OFFSET(apic_access_addr, 104);
 617         CHECK_OFFSET(posted_intr_desc_addr, 112);
 618         CHECK_OFFSET(ept_pointer, 120);
 619         CHECK_OFFSET(eoi_exit_bitmap0, 128);
 620         CHECK_OFFSET(eoi_exit_bitmap1, 136);
 621         CHECK_OFFSET(eoi_exit_bitmap2, 144);
 622         CHECK_OFFSET(eoi_exit_bitmap3, 152);
 623         CHECK_OFFSET(xss_exit_bitmap, 160);
 624         CHECK_OFFSET(guest_physical_address, 168);
 625         CHECK_OFFSET(vmcs_link_pointer, 176);
 626         CHECK_OFFSET(guest_ia32_debugctl, 184);
 627         CHECK_OFFSET(guest_ia32_pat, 192);
 628         CHECK_OFFSET(guest_ia32_efer, 200);
 629         CHECK_OFFSET(guest_ia32_perf_global_ctrl, 208);
 630         CHECK_OFFSET(guest_pdptr0, 216);
 631         CHECK_OFFSET(guest_pdptr1, 224);
 632         CHECK_OFFSET(guest_pdptr2, 232);
 633         CHECK_OFFSET(guest_pdptr3, 240);
 634         CHECK_OFFSET(guest_bndcfgs, 248);
 635         CHECK_OFFSET(host_ia32_pat, 256);
 636         CHECK_OFFSET(host_ia32_efer, 264);
 637         CHECK_OFFSET(host_ia32_perf_global_ctrl, 272);
 638         CHECK_OFFSET(vmread_bitmap, 280);
 639         CHECK_OFFSET(vmwrite_bitmap, 288);
 640         CHECK_OFFSET(vm_function_control, 296);
 641         CHECK_OFFSET(eptp_list_address, 304);
 642         CHECK_OFFSET(pml_address, 312);
 643         CHECK_OFFSET(cr0_guest_host_mask, 344);
 644         CHECK_OFFSET(cr4_guest_host_mask, 352);
 645         CHECK_OFFSET(cr0_read_shadow, 360);
 646         CHECK_OFFSET(cr4_read_shadow, 368);
 647         CHECK_OFFSET(cr3_target_value0, 376);
 648         CHECK_OFFSET(cr3_target_value1, 384);
 649         CHECK_OFFSET(cr3_target_value2, 392);
 650         CHECK_OFFSET(cr3_target_value3, 400);
 651         CHECK_OFFSET(exit_qualification, 408);
 652         CHECK_OFFSET(guest_linear_address, 416);
 653         CHECK_OFFSET(guest_cr0, 424);
 654         CHECK_OFFSET(guest_cr3, 432);
 655         CHECK_OFFSET(guest_cr4, 440);
 656         CHECK_OFFSET(guest_es_base, 448);
 657         CHECK_OFFSET(guest_cs_base, 456);
 658         CHECK_OFFSET(guest_ss_base, 464);
 659         CHECK_OFFSET(guest_ds_base, 472);
 660         CHECK_OFFSET(guest_fs_base, 480);
 661         CHECK_OFFSET(guest_gs_base, 488);
 662         CHECK_OFFSET(guest_ldtr_base, 496);
 663         CHECK_OFFSET(guest_tr_base, 504);
 664         CHECK_OFFSET(guest_gdtr_base, 512);
 665         CHECK_OFFSET(guest_idtr_base, 520);
 666         CHECK_OFFSET(guest_dr7, 528);
 667         CHECK_OFFSET(guest_rsp, 536);
 668         CHECK_OFFSET(guest_rip, 544);
 669         CHECK_OFFSET(guest_rflags, 552);
 670         CHECK_OFFSET(guest_pending_dbg_exceptions, 560);
 671         CHECK_OFFSET(guest_sysenter_esp, 568);
 672         CHECK_OFFSET(guest_sysenter_eip, 576);
 673         CHECK_OFFSET(host_cr0, 584);
 674         CHECK_OFFSET(host_cr3, 592);
 675         CHECK_OFFSET(host_cr4, 600);
 676         CHECK_OFFSET(host_fs_base, 608);
 677         CHECK_OFFSET(host_gs_base, 616);
 678         CHECK_OFFSET(host_tr_base, 624);
 679         CHECK_OFFSET(host_gdtr_base, 632);
 680         CHECK_OFFSET(host_idtr_base, 640);
 681         CHECK_OFFSET(host_ia32_sysenter_esp, 648);
 682         CHECK_OFFSET(host_ia32_sysenter_eip, 656);
 683         CHECK_OFFSET(host_rsp, 664);
 684         CHECK_OFFSET(host_rip, 672);
 685         CHECK_OFFSET(pin_based_vm_exec_control, 744);
 686         CHECK_OFFSET(cpu_based_vm_exec_control, 748);
 687         CHECK_OFFSET(exception_bitmap, 752);
 688         CHECK_OFFSET(page_fault_error_code_mask, 756);
 689         CHECK_OFFSET(page_fault_error_code_match, 760);
 690         CHECK_OFFSET(cr3_target_count, 764);
 691         CHECK_OFFSET(vm_exit_controls, 768);
 692         CHECK_OFFSET(vm_exit_msr_store_count, 772);
 693         CHECK_OFFSET(vm_exit_msr_load_count, 776);
 694         CHECK_OFFSET(vm_entry_controls, 780);
 695         CHECK_OFFSET(vm_entry_msr_load_count, 784);
 696         CHECK_OFFSET(vm_entry_intr_info_field, 788);
 697         CHECK_OFFSET(vm_entry_exception_error_code, 792);
 698         CHECK_OFFSET(vm_entry_instruction_len, 796);
 699         CHECK_OFFSET(tpr_threshold, 800);
 700         CHECK_OFFSET(secondary_vm_exec_control, 804);
 701         CHECK_OFFSET(vm_instruction_error, 808);
 702         CHECK_OFFSET(vm_exit_reason, 812);
 703         CHECK_OFFSET(vm_exit_intr_info, 816);
 704         CHECK_OFFSET(vm_exit_intr_error_code, 820);
 705         CHECK_OFFSET(idt_vectoring_info_field, 824);
 706         CHECK_OFFSET(idt_vectoring_error_code, 828);
 707         CHECK_OFFSET(vm_exit_instruction_len, 832);
 708         CHECK_OFFSET(vmx_instruction_info, 836);
 709         CHECK_OFFSET(guest_es_limit, 840);
 710         CHECK_OFFSET(guest_cs_limit, 844);
 711         CHECK_OFFSET(guest_ss_limit, 848);
 712         CHECK_OFFSET(guest_ds_limit, 852);
 713         CHECK_OFFSET(guest_fs_limit, 856);
 714         CHECK_OFFSET(guest_gs_limit, 860);
 715         CHECK_OFFSET(guest_ldtr_limit, 864);
 716         CHECK_OFFSET(guest_tr_limit, 868);
 717         CHECK_OFFSET(guest_gdtr_limit, 872);
 718         CHECK_OFFSET(guest_idtr_limit, 876);
 719         CHECK_OFFSET(guest_es_ar_bytes, 880);
 720         CHECK_OFFSET(guest_cs_ar_bytes, 884);
 721         CHECK_OFFSET(guest_ss_ar_bytes, 888);
 722         CHECK_OFFSET(guest_ds_ar_bytes, 892);
 723         CHECK_OFFSET(guest_fs_ar_bytes, 896);
 724         CHECK_OFFSET(guest_gs_ar_bytes, 900);
 725         CHECK_OFFSET(guest_ldtr_ar_bytes, 904);
 726         CHECK_OFFSET(guest_tr_ar_bytes, 908);
 727         CHECK_OFFSET(guest_interruptibility_info, 912);
 728         CHECK_OFFSET(guest_activity_state, 916);
 729         CHECK_OFFSET(guest_sysenter_cs, 920);
 730         CHECK_OFFSET(host_ia32_sysenter_cs, 924);
 731         CHECK_OFFSET(vmx_preemption_timer_value, 928);
 732         CHECK_OFFSET(virtual_processor_id, 960);
 733         CHECK_OFFSET(posted_intr_nv, 962);
 734         CHECK_OFFSET(guest_es_selector, 964);
 735         CHECK_OFFSET(guest_cs_selector, 966);
 736         CHECK_OFFSET(guest_ss_selector, 968);
 737         CHECK_OFFSET(guest_ds_selector, 970);
 738         CHECK_OFFSET(guest_fs_selector, 972);
 739         CHECK_OFFSET(guest_gs_selector, 974);
 740         CHECK_OFFSET(guest_ldtr_selector, 976);
 741         CHECK_OFFSET(guest_tr_selector, 978);
 742         CHECK_OFFSET(guest_intr_status, 980);
 743         CHECK_OFFSET(host_es_selector, 982);
 744         CHECK_OFFSET(host_cs_selector, 984);
 745         CHECK_OFFSET(host_ss_selector, 986);
 746         CHECK_OFFSET(host_ds_selector, 988);
 747         CHECK_OFFSET(host_fs_selector, 990);
 748         CHECK_OFFSET(host_gs_selector, 992);
 749         CHECK_OFFSET(host_tr_selector, 994);
 750         CHECK_OFFSET(guest_pml_index, 996);
 751 }
 752
 753 /*
 754  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 755  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 756  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 757  *
 758  * IMPORTANT: Changing this value will break save/restore compatibility with
 759  * older kvm releases.
 760  */
 761 #define VMCS12_REVISION 0x11e57ed0
 762
 763 /*
 764  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 765  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 766  * current implementation, 4K are reserved to avoid future complications.
 767  */
 768 #define VMCS12_SIZE 0x1000
 769
 770 /*
 771  * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
 772  * supported VMCS12 field encoding.
 773  */
 774 #define VMCS12_MAX_FIELD_INDEX 0x17
 775
 776 struct nested_vmx_msrs {
 777         /*
 778          * We only store the "true" versions of the VMX capability MSRs. We
 779          * generate the "non-true" versions by setting the must-be-1 bits
 780          * according to the SDM.
 781          */
 782         u32 procbased_ctls_low;
 783         u32 procbased_ctls_high;
 784         u32 secondary_ctls_low;
 785         u32 secondary_ctls_high;
 786         u32 pinbased_ctls_low;
 787         u32 pinbased_ctls_high;
 788         u32 exit_ctls_low;
 789         u32 exit_ctls_high;
 790         u32 entry_ctls_low;
 791         u32 entry_ctls_high;
 792         u32 misc_low;
 793         u32 misc_high;
 794         u32 ept_caps;
 795         u32 vpid_caps;
 796         u64 basic;
 797         u64 cr0_fixed0;
 798         u64 cr0_fixed1;
 799         u64 cr4_fixed0;
 800         u64 cr4_fixed1;
 801         u64 vmcs_enum;
 802         u64 vmfunc_controls;
 803 };
 804
 805 /*
 806  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 807  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 808  */
 809 struct nested_vmx {
 810         /* Has the level1 guest done vmxon? */
 811         bool vmxon;
 812         gpa_t vmxon_ptr;
 813         bool pml_full;
 814
 815         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 816         gpa_t current_vmptr;
 817         /*
 818          * Cache of the guest's VMCS, existing outside of guest memory.
 819          * Loaded from guest memory during VMPTRLD. Flushed to guest
 820          * memory during VMCLEAR and VMPTRLD.
 821          */
 822         struct vmcs12 *cached_vmcs12;
 823         /*
 824          * Cache of the guest's shadow VMCS, existing outside of guest
 825          * memory. Loaded from guest memory during VM entry. Flushed
 826          * to guest memory during VM exit.
 827          */
 828         struct vmcs12 *cached_shadow_vmcs12;
 829         /*
 830          * Indicates if the shadow vmcs must be updated with the
 831          * data hold by vmcs12
 832          */
 833         bool sync_shadow_vmcs;
 834         bool dirty_vmcs12;
 835
 836         bool change_vmcs01_virtual_apic_mode;
 837
 838         /* L2 must run next, and mustn't decide to exit to L1. */
 839         bool nested_run_pending;
 840
 841         struct loaded_vmcs vmcs02;
 842
 843         /*
 844          * Guest pages referred to in the vmcs02 with host-physical
 845          * pointers, so we must keep them pinned while L2 runs.
 846          */
 847         struct page *apic_access_page;
 848         struct page *virtual_apic_page;
 849         struct page *pi_desc_page;
 850         struct pi_desc *pi_desc;
 851         bool pi_pending;
 852         u16 posted_intr_nv;
 853
 854         struct hrtimer preemption_timer;
 855         bool preemption_timer_expired;
 856
 857         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 858         u64 vmcs01_debugctl;
 859         u64 vmcs01_guest_bndcfgs;
 860
 861         u16 vpid02;
 862         u16 last_vpid;
 863
 864         struct nested_vmx_msrs msrs;
 865
 866         /* SMM related state */
 867         struct {
 868                 /* in VMX operation on SMM entry? */
 869                 bool vmxon;
 870                 /* in guest mode on SMM entry? */
 871                 bool guest_mode;
 872         } smm;
 873 };
 874
 875 #define POSTED_INTR_ON  0
 876 #define POSTED_INTR_SN  1
 877
 878 /* Posted-Interrupt Descriptor */
 879 struct pi_desc {
 880         u32 pir[8];     /* Posted interrupt requested */
 881         union {
 882                 struct {
 883                                 /* bit 256 - Outstanding Notification */
 884                         u16     on      : 1,
 885                                 /* bit 257 - Suppress Notification */
 886                                 sn      : 1,
 887                                 /* bit 271:258 - Reserved */
 888                                 rsvd_1  : 14;
 889                                 /* bit 279:272 - Notification Vector */
 890                         u8      nv;
 891                                 /* bit 287:280 - Reserved */
 892                         u8      rsvd_2;
 893                                 /* bit 319:288 - Notification Destination */
 894                         u32     ndst;
 895                 };
 896                 u64 control;
 897         };
 898         u32 rsvd[6];
 899 } __aligned(64);
 900
 901 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 902 {
 903         return test_and_set_bit(POSTED_INTR_ON,
 904                         (unsigned long *)&pi_desc->control);
 905 }
 906
 907 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 908 {
 909         return test_and_clear_bit(POSTED_INTR_ON,
 910                         (unsigned long *)&pi_desc->control);
 911 }
 912
 913 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 914 {
 915         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 916 }
 917
 918 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 919 {
 920         return clear_bit(POSTED_INTR_SN,
 921                         (unsigned long *)&pi_desc->control);
 922 }
 923
 924 static inline void pi_set_sn(struct pi_desc *pi_desc)
 925 {
 926         return set_bit(POSTED_INTR_SN,
 927                         (unsigned long *)&pi_desc->control);
 928 }
 929
 930 static inline void pi_clear_on(struct pi_desc *pi_desc)
 931 {
 932         clear_bit(POSTED_INTR_ON,
 933                   (unsigned long *)&pi_desc->control);
 934 }
 935
 936 static inline int pi_test_on(struct pi_desc *pi_desc)
 937 {
 938         return test_bit(POSTED_INTR_ON,
 939                         (unsigned long *)&pi_desc->control);
 940 }
 941
 942 static inline int pi_test_sn(struct pi_desc *pi_desc)
 943 {
 944         return test_bit(POSTED_INTR_SN,
 945                         (unsigned long *)&pi_desc->control);
 946 }
 947
 948 struct vmx_msrs {
 949         unsigned int            nr;
 950         struct vmx_msr_entry    val[NR_AUTOLOAD_MSRS];
 951 };
 952
 953 struct vcpu_vmx {
 954         struct kvm_vcpu       vcpu;
 955         unsigned long         host_rsp;
 956         u8                    fail;
 957         u8                    msr_bitmap_mode;
 958         u32                   exit_intr_info;
 959         u32                   idt_vectoring_info;
 960         ulong                 rflags;
 961         struct shared_msr_entry *guest_msrs;
 962         int                   nmsrs;
 963         int                   save_nmsrs;
 964         unsigned long         host_idt_base;
 965 #ifdef CONFIG_X86_64
 966         u64                   msr_host_kernel_gs_base;
 967         u64                   msr_guest_kernel_gs_base;
 968 #endif
 969
 970         u64                   arch_capabilities;
 971         u64                   spec_ctrl;
 972
 973         u32 vm_entry_controls_shadow;
 974         u32 vm_exit_controls_shadow;
 975         u32 secondary_exec_control;
 976
 977         /*
 978          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 979          * non-nested (L1) guest, it always points to vmcs01. For a nested
 980          * guest (L2), it points to a different VMCS.  loaded_cpu_state points
 981          * to the VMCS whose state is loaded into the CPU registers that only
 982          * need to be switched when transitioning to/from the kernel; a NULL
 983          * value indicates that host state is loaded.
 984          */
 985         struct loaded_vmcs    vmcs01;
 986         struct loaded_vmcs   *loaded_vmcs;
 987         struct loaded_vmcs   *loaded_cpu_state;
 988         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 989         struct msr_autoload {
 990                 struct vmx_msrs guest;
 991                 struct vmx_msrs host;
 992         } msr_autoload;
 993
 994         struct {
 995                 int vm86_active;
 996                 ulong save_rflags;
 997                 struct kvm_segment segs[8];
 998         } rmode;
 999         struct {
1000                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
1001                 struct kvm_save_segment {
1002                         u16 selector;
1003                         unsigned long base;
1004                         u32 limit;
1005                         u32 ar;
1006                 } seg[8];
1007         } segment_cache;
1008         int vpid;
1009         bool emulation_required;
1010
1011         u32 exit_reason;
1012
1013         /* Posted interrupt descriptor */
1014         struct pi_desc pi_desc;
1015
1016         /* Support for a guest hypervisor (nested VMX) */
1017         struct nested_vmx nested;
1018
1019         /* Dynamic PLE window. */
1020         int ple_window;
1021         bool ple_window_dirty;
1022
1023         bool req_immediate_exit;
1024
1025         /* Support for PML */
1026 #define PML_ENTITY_NUM          512
1027         struct page *pml_pg;
1028
1029         /* apic deadline value in host tsc */
1030         u64 hv_deadline_tsc;
1031
1032         u64 current_tsc_ratio;
1033
1034         u32 host_pkru;
1035
1036         unsigned long host_debugctlmsr;
1037
1038         /*
1039          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
1040          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
1041          * in msr_ia32_feature_control_valid_bits.
1042          */
1043         u64 msr_ia32_feature_control;
1044         u64 msr_ia32_feature_control_valid_bits;
1045         u64 ept_pointer;
1046 };
1047
1048 enum segment_cache_field {
1049         SEG_FIELD_SEL = 0,
1050         SEG_FIELD_BASE = 1,
1051         SEG_FIELD_LIMIT = 2,
1052         SEG_FIELD_AR = 3,
1053
1054         SEG_FIELD_NR = 4
1055 };
1056
1057 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
1058 {
1059         return container_of(kvm, struct kvm_vmx, kvm);
1060 }
1061
1062 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
1063 {
1064         return container_of(vcpu, struct vcpu_vmx, vcpu);
1065 }
1066
1067 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
1068 {
1069         return &(to_vmx(vcpu)->pi_desc);
1070 }
1071
1072 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
1073 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
1074 #define FIELD(number, name)     [ROL16(number, 6)] = VMCS12_OFFSET(name)
1075 #define FIELD64(number, name)                                           \
1076         FIELD(number, name),                                            \
1077         [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
1078
1079
1080 static u16 shadow_read_only_fields[] = {
1081 #define SHADOW_FIELD_RO(x) x,
1082 #include "vmx_shadow_fields.h"
1083 };
1084 static int max_shadow_read_only_fields =
1085         ARRAY_SIZE(shadow_read_only_fields);
1086
1087 static u16 shadow_read_write_fields[] = {
1088 #define SHADOW_FIELD_RW(x) x,
1089 #include "vmx_shadow_fields.h"
1090 };
1091 static int max_shadow_read_write_fields =
1092         ARRAY_SIZE(shadow_read_write_fields);
1093
1094 static const unsigned short vmcs_field_to_offset_table[] = {
1095         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
1096         FIELD(POSTED_INTR_NV, posted_intr_nv),
1097         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
1098         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
1099         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
1100         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
1101         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
1102         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
1103         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
1104         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
1105         FIELD(GUEST_INTR_STATUS, guest_intr_status),
1106         FIELD(GUEST_PML_INDEX, guest_pml_index),
1107         FIELD(HOST_ES_SELECTOR, host_es_selector),
1108         FIELD(HOST_CS_SELECTOR, host_cs_selector),
1109         FIELD(HOST_SS_SELECTOR, host_ss_selector),
1110         FIELD(HOST_DS_SELECTOR, host_ds_selector),
1111         FIELD(HOST_FS_SELECTOR, host_fs_selector),
1112         FIELD(HOST_GS_SELECTOR, host_gs_selector),
1113         FIELD(HOST_TR_SELECTOR, host_tr_selector),
1114         FIELD64(IO_BITMAP_A, io_bitmap_a),
1115         FIELD64(IO_BITMAP_B, io_bitmap_b),
1116         FIELD64(MSR_BITMAP, msr_bitmap),
1117         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
1118         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
1119         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
1120         FIELD64(PML_ADDRESS, pml_address),
1121         FIELD64(TSC_OFFSET, tsc_offset),
1122         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
1123         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
1124         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
1125         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
1126         FIELD64(EPT_POINTER, ept_pointer),
1127         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
1128         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
1129         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
1130         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
1131         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
1132         FIELD64(VMREAD_BITMAP, vmread_bitmap),
1133         FIELD64(VMWRITE_BITMAP, vmwrite_bitmap),
1134         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
1135         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
1136         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
1137         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
1138         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
1139         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
1140         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
1141         FIELD64(GUEST_PDPTR0, guest_pdptr0),
1142         FIELD64(GUEST_PDPTR1, guest_pdptr1),
1143         FIELD64(GUEST_PDPTR2, guest_pdptr2),
1144         FIELD64(GUEST_PDPTR3, guest_pdptr3),
1145         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
1146         FIELD64(HOST_IA32_PAT, host_ia32_pat),
1147         FIELD64(HOST_IA32_EFER, host_ia32_efer),
1148         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
1149         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
1150         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
1151         FIELD(EXCEPTION_BITMAP, exception_bitmap),
1152         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
1153         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
1154         FIELD(CR3_TARGET_COUNT, cr3_target_count),
1155         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
1156         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
1157         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
1158         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
1159         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
1160         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
1161         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
1162         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
1163         FIELD(TPR_THRESHOLD, tpr_threshold),
1164         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
1165         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
1166         FIELD(VM_EXIT_REASON, vm_exit_reason),
1167         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
1168         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
1169         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
1170         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
1171         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
1172         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
1173         FIELD(GUEST_ES_LIMIT, guest_es_limit),
1174         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
1175         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
1176         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
1177         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
1178         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
1179         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
1180         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
1181         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
1182         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
1183         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
1184         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
1185         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
1186         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
1187         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
1188         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
1189         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
1190         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
1191         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
1192         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
1193         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
1194         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
1195         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
1196         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
1197         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
1198         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
1199         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
1200         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
1201         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
1202         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
1203         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
1204         FIELD(EXIT_QUALIFICATION, exit_qualification),
1205         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
1206         FIELD(GUEST_CR0, guest_cr0),
1207         FIELD(GUEST_CR3, guest_cr3),
1208         FIELD(GUEST_CR4, guest_cr4),
1209         FIELD(GUEST_ES_BASE, guest_es_base),
1210         FIELD(GUEST_CS_BASE, guest_cs_base),
1211         FIELD(GUEST_SS_BASE, guest_ss_base),
1212         FIELD(GUEST_DS_BASE, guest_ds_base),
1213         FIELD(GUEST_FS_BASE, guest_fs_base),
1214         FIELD(GUEST_GS_BASE, guest_gs_base),
1215         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
1216         FIELD(GUEST_TR_BASE, guest_tr_base),
1217         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
1218         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
1219         FIELD(GUEST_DR7, guest_dr7),
1220         FIELD(GUEST_RSP, guest_rsp),
1221         FIELD(GUEST_RIP, guest_rip),
1222         FIELD(GUEST_RFLAGS, guest_rflags),
1223         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
1224         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
1225         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
1226         FIELD(HOST_CR0, host_cr0),
1227         FIELD(HOST_CR3, host_cr3),
1228         FIELD(HOST_CR4, host_cr4),
1229         FIELD(HOST_FS_BASE, host_fs_base),
1230         FIELD(HOST_GS_BASE, host_gs_base),
1231         FIELD(HOST_TR_BASE, host_tr_base),
1232         FIELD(HOST_GDTR_BASE, host_gdtr_base),
1233         FIELD(HOST_IDTR_BASE, host_idtr_base),
1234         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
1235         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
1236         FIELD(HOST_RSP, host_rsp),
1237         FIELD(HOST_RIP, host_rip),
1238 };
1239
1240 static inline short vmcs_field_to_offset(unsigned long field)
1241 {
1242         const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
1243         unsigned short offset;
1244         unsigned index;
1245
1246         if (field >> 15)
1247                 return -ENOENT;
1248
1249         index = ROL16(field, 6);
1250         if (index >= size)
1251                 return -ENOENT;
1252
1253         index = array_index_nospec(index, size);
1254         offset = vmcs_field_to_offset_table[index];
1255         if (offset == 0)
1256                 return -ENOENT;
1257         return offset;
1258 }
1259
1260 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
1261 {
1262         return to_vmx(vcpu)->nested.cached_vmcs12;
1263 }
1264
1265 static inline struct vmcs12 *get_shadow_vmcs12(struct kvm_vcpu *vcpu)
1266 {
1267         return to_vmx(vcpu)->nested.cached_shadow_vmcs12;
1268 }
1269
1270 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
1271 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
1272 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
1273 static bool vmx_xsaves_supported(void);
1274 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1275                             struct kvm_segment *var, int seg);
1276 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1277                             struct kvm_segment *var, int seg);
1278 static bool guest_state_valid(struct kvm_vcpu *vcpu);
1279 static u32 vmx_segment_access_rights(struct kvm_segment *var);
1280 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
1281 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
1282 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
1283 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
1284                                             u16 error_code);
1285 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
1286 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
1287                                                           u32 msr, int type);
1288
1289 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
1290 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
1291 /*
1292  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1293  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1294  */
1295 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
1296
1297 /*
1298  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1299  * can find which vCPU should be waken up.
1300  */
1301 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
1302 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
1303
1304 enum {
1305         VMX_VMREAD_BITMAP,
1306         VMX_VMWRITE_BITMAP,
1307         VMX_BITMAP_NR
1308 };
1309
1310 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
1311
1312 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
1313 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
1314
1315 static bool cpu_has_load_ia32_efer;
1316 static bool cpu_has_load_perf_global_ctrl;
1317
1318 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
1319 static DEFINE_SPINLOCK(vmx_vpid_lock);
1320
1321 static struct vmcs_config {
1322         int size;
1323         int order;
1324         u32 basic_cap;
1325         u32 revision_id;
1326         u32 pin_based_exec_ctrl;
1327         u32 cpu_based_exec_ctrl;
1328         u32 cpu_based_2nd_exec_ctrl;
1329         u32 vmexit_ctrl;
1330         u32 vmentry_ctrl;
1331         struct nested_vmx_msrs nested;
1332 } vmcs_config;
1333
1334 static struct vmx_capability {
1335         u32 ept;
1336         u32 vpid;
1337 } vmx_capability;
1338
1339 #define VMX_SEGMENT_FIELD(seg)                                  \
1340         [VCPU_SREG_##seg] = {                                   \
1341                 .selector = GUEST_##seg##_SELECTOR,             \
1342                 .base = GUEST_##seg##_BASE,                     \
1343                 .limit = GUEST_##seg##_LIMIT,                   \
1344                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1345         }
1346
1347 static const struct kvm_vmx_segment_field {
1348         unsigned selector;
1349         unsigned base;
1350         unsigned limit;
1351         unsigned ar_bytes;
1352 } kvm_vmx_segment_fields[] = {
1353         VMX_SEGMENT_FIELD(CS),
1354         VMX_SEGMENT_FIELD(DS),
1355         VMX_SEGMENT_FIELD(ES),
1356         VMX_SEGMENT_FIELD(FS),
1357         VMX_SEGMENT_FIELD(GS),
1358         VMX_SEGMENT_FIELD(SS),
1359         VMX_SEGMENT_FIELD(TR),
1360         VMX_SEGMENT_FIELD(LDTR),
1361 };
1362
1363 static u64 host_efer;
1364
1365 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1366
1367 /*
1368  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1369  * away by decrementing the array size.
1370  */
1371 static const u32 vmx_msr_index[] = {
1372 #ifdef CONFIG_X86_64
1373         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1374 #endif
1375         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1376 };
1377
1378 DEFINE_STATIC_KEY_FALSE(enable_evmcs);
1379
1380 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1381
1382 #define KVM_EVMCS_VERSION 1
1383
1384 #if IS_ENABLED(CONFIG_HYPERV)
1385 static bool __read_mostly enlightened_vmcs = true;
1386 module_param(enlightened_vmcs, bool, 0444);
1387
1388 static inline void evmcs_write64(unsigned long field, u64 value)
1389 {
1390         u16 clean_field;
1391         int offset = get_evmcs_offset(field, &clean_field);
1392
1393         if (offset < 0)
1394                 return;
1395
1396         *(u64 *)((char *)current_evmcs + offset) = value;
1397
1398         current_evmcs->hv_clean_fields &= ~clean_field;
1399 }
1400
1401 static inline void evmcs_write32(unsigned long field, u32 value)
1402 {
1403         u16 clean_field;
1404         int offset = get_evmcs_offset(field, &clean_field);
1405
1406         if (offset < 0)
1407                 return;
1408
1409         *(u32 *)((char *)current_evmcs + offset) = value;
1410         current_evmcs->hv_clean_fields &= ~clean_field;
1411 }
1412
1413 static inline void evmcs_write16(unsigned long field, u16 value)
1414 {
1415         u16 clean_field;
1416         int offset = get_evmcs_offset(field, &clean_field);
1417
1418         if (offset < 0)
1419                 return;
1420
1421         *(u16 *)((char *)current_evmcs + offset) = value;
1422         current_evmcs->hv_clean_fields &= ~clean_field;
1423 }
1424
1425 static inline u64 evmcs_read64(unsigned long field)
1426 {
1427         int offset = get_evmcs_offset(field, NULL);
1428
1429         if (offset < 0)
1430                 return 0;
1431
1432         return *(u64 *)((char *)current_evmcs + offset);
1433 }
1434
1435 static inline u32 evmcs_read32(unsigned long field)
1436 {
1437         int offset = get_evmcs_offset(field, NULL);
1438
1439         if (offset < 0)
1440                 return 0;
1441
1442         return *(u32 *)((char *)current_evmcs + offset);
1443 }
1444
1445 static inline u16 evmcs_read16(unsigned long field)
1446 {
1447         int offset = get_evmcs_offset(field, NULL);
1448
1449         if (offset < 0)
1450                 return 0;
1451
1452         return *(u16 *)((char *)current_evmcs + offset);
1453 }
1454
1455 static inline void evmcs_touch_msr_bitmap(void)
1456 {
1457         if (unlikely(!current_evmcs))
1458                 return;
1459
1460         if (current_evmcs->hv_enlightenments_control.msr_bitmap)
1461                 current_evmcs->hv_clean_fields &=
1462                         ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP;
1463 }
1464
1465 static void evmcs_load(u64 phys_addr)
1466 {
1467         struct hv_vp_assist_page *vp_ap =
1468                 hv_get_vp_assist_page(smp_processor_id());
1469
1470         vp_ap->current_nested_vmcs = phys_addr;
1471         vp_ap->enlighten_vmentry = 1;
1472 }
1473
1474 static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
1475 {
1476         /*
1477          * Enlightened VMCSv1 doesn't support these:
1478          *
1479          *      POSTED_INTR_NV                  = 0x00000002,
1480          *      GUEST_INTR_STATUS               = 0x00000810,
1481          *      APIC_ACCESS_ADDR                = 0x00002014,
1482          *      POSTED_INTR_DESC_ADDR           = 0x00002016,
1483          *      EOI_EXIT_BITMAP0                = 0x0000201c,
1484          *      EOI_EXIT_BITMAP1                = 0x0000201e,
1485          *      EOI_EXIT_BITMAP2                = 0x00002020,
1486          *      EOI_EXIT_BITMAP3                = 0x00002022,
1487          */
1488         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
1489         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1490                 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1491         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1492                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1493         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1494                 ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
1495
1496         /*
1497          *      GUEST_PML_INDEX                 = 0x00000812,
1498          *      PML_ADDRESS                     = 0x0000200e,
1499          */
1500         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML;
1501
1502         /*      VM_FUNCTION_CONTROL             = 0x00002018, */
1503         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC;
1504
1505         /*
1506          *      EPTP_LIST_ADDRESS               = 0x00002024,
1507          *      VMREAD_BITMAP                   = 0x00002026,
1508          *      VMWRITE_BITMAP                  = 0x00002028,
1509          */
1510         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS;
1511
1512         /*
1513          *      TSC_MULTIPLIER                  = 0x00002032,
1514          */
1515         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING;
1516
1517         /*
1518          *      PLE_GAP                         = 0x00004020,
1519          *      PLE_WINDOW                      = 0x00004022,
1520          */
1521         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1522
1523         /*
1524          *      VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
1525          */
1526         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
1527
1528         /*
1529          *      GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
1530          *      HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
1531          */
1532         vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
1533         vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
1534
1535         /*
1536          * Currently unsupported in KVM:
1537          *      GUEST_IA32_RTIT_CTL             = 0x00002814,
1538          */
1539 }
1540
1541 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
1542 static void check_ept_pointer_match(struct kvm *kvm)
1543 {
1544         struct kvm_vcpu *vcpu;
1545         u64 tmp_eptp = INVALID_PAGE;
1546         int i;
1547
1548         kvm_for_each_vcpu(i, vcpu, kvm) {
1549                 if (!VALID_PAGE(tmp_eptp)) {
1550                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
1551                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
1552                         to_kvm_vmx(kvm)->ept_pointers_match
1553                                 = EPT_POINTERS_MISMATCH;
1554                         return;
1555                 }
1556         }
1557
1558         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
1559 }
1560
1561 static int vmx_hv_remote_flush_tlb(struct kvm *kvm)
1562 {
1563         int ret;
1564
1565         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
1566
1567         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
1568                 check_ept_pointer_match(kvm);
1569
1570         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
1571                 ret = -ENOTSUPP;
1572                 goto out;
1573         }
1574
1575         ret = hyperv_flush_guest_mapping(
1576                         to_vmx(kvm_get_vcpu(kvm, 0))->ept_pointer);
1577
1578 out:
1579         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
1580         return ret;
1581 }
1582 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1583 static inline void evmcs_write64(unsigned long field, u64 value) {}
1584 static inline void evmcs_write32(unsigned long field, u32 value) {}
1585 static inline void evmcs_write16(unsigned long field, u16 value) {}
1586 static inline u64 evmcs_read64(unsigned long field) { return 0; }
1587 static inline u32 evmcs_read32(unsigned long field) { return 0; }
1588 static inline u16 evmcs_read16(unsigned long field) { return 0; }
1589 static inline void evmcs_load(u64 phys_addr) {}
1590 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
1591 static inline void evmcs_touch_msr_bitmap(void) {}
1592 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1593
1594 static inline bool is_exception_n(u32 intr_info, u8 vector)
1595 {
1596         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1597                              INTR_INFO_VALID_MASK)) ==
1598                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1599 }
1600
1601 static inline bool is_debug(u32 intr_info)
1602 {
1603         return is_exception_n(intr_info, DB_VECTOR);
1604 }
1605
1606 static inline bool is_breakpoint(u32 intr_info)
1607 {
1608         return is_exception_n(intr_info, BP_VECTOR);
1609 }
1610
1611 static inline bool is_page_fault(u32 intr_info)
1612 {
1613         return is_exception_n(intr_info, PF_VECTOR);
1614 }
1615
1616 static inline bool is_no_device(u32 intr_info)
1617 {
1618         return is_exception_n(intr_info, NM_VECTOR);
1619 }
1620
1621 static inline bool is_invalid_opcode(u32 intr_info)
1622 {
1623         return is_exception_n(intr_info, UD_VECTOR);
1624 }
1625
1626 static inline bool is_gp_fault(u32 intr_info)
1627 {
1628         return is_exception_n(intr_info, GP_VECTOR);
1629 }
1630
1631 static inline bool is_external_interrupt(u32 intr_info)
1632 {
1633         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1634                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1635 }
1636
1637 static inline bool is_machine_check(u32 intr_info)
1638 {
1639         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1640                              INTR_INFO_VALID_MASK)) ==
1641                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1642 }
1643
1644 /* Undocumented: icebp/int1 */
1645 static inline bool is_icebp(u32 intr_info)
1646 {
1647         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1648                 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1649 }
1650
1651 static inline bool cpu_has_vmx_msr_bitmap(void)
1652 {
1653         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1654 }
1655
1656 static inline bool cpu_has_vmx_tpr_shadow(void)
1657 {
1658         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1659 }
1660
1661 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1662 {
1663         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1664 }
1665
1666 static inline bool cpu_has_secondary_exec_ctrls(void)
1667 {
1668         return vmcs_config.cpu_based_exec_ctrl &
1669                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1670 }
1671
1672 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1673 {
1674         return vmcs_config.cpu_based_2nd_exec_ctrl &
1675                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1676 }
1677
1678 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1679 {
1680         return vmcs_config.cpu_based_2nd_exec_ctrl &
1681                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1682 }
1683
1684 static inline bool cpu_has_vmx_apic_register_virt(void)
1685 {
1686         return vmcs_config.cpu_based_2nd_exec_ctrl &
1687                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1688 }
1689
1690 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1691 {
1692         return vmcs_config.cpu_based_2nd_exec_ctrl &
1693                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1694 }
1695
1696 static inline bool cpu_has_vmx_encls_vmexit(void)
1697 {
1698         return vmcs_config.cpu_based_2nd_exec_ctrl &
1699                 SECONDARY_EXEC_ENCLS_EXITING;
1700 }
1701
1702 /*
1703  * Comment's format: document - errata name - stepping - processor name.
1704  * Refer from
1705  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1706  */
1707 static u32 vmx_preemption_cpu_tfms[] = {
1708 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1709 0x000206E6,
1710 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1711 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1712 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1713 0x00020652,
1714 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1715 0x00020655,
1716 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1717 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1718 /*
1719  * 320767.pdf - AAP86  - B1 -
1720  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1721  */
1722 0x000106E5,
1723 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1724 0x000106A0,
1725 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1726 0x000106A1,
1727 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1728 0x000106A4,
1729  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1730  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1731  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1732 0x000106A5,
1733 };
1734
1735 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1736 {
1737         u32 eax = cpuid_eax(0x00000001), i;
1738
1739         /* Clear the reserved bits */
1740         eax &= ~(0x3U << 14 | 0xfU << 28);
1741         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1742                 if (eax == vmx_preemption_cpu_tfms[i])
1743                         return true;
1744
1745         return false;
1746 }
1747
1748 static inline bool cpu_has_vmx_preemption_timer(void)
1749 {
1750         return vmcs_config.pin_based_exec_ctrl &
1751                 PIN_BASED_VMX_PREEMPTION_TIMER;
1752 }
1753
1754 static inline bool cpu_has_vmx_posted_intr(void)
1755 {
1756         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1757                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1758 }
1759
1760 static inline bool cpu_has_vmx_apicv(void)
1761 {
1762         return cpu_has_vmx_apic_register_virt() &&
1763                 cpu_has_vmx_virtual_intr_delivery() &&
1764                 cpu_has_vmx_posted_intr();
1765 }
1766
1767 static inline bool cpu_has_vmx_flexpriority(void)
1768 {
1769         return cpu_has_vmx_tpr_shadow() &&
1770                 cpu_has_vmx_virtualize_apic_accesses();
1771 }
1772
1773 static inline bool cpu_has_vmx_ept_execute_only(void)
1774 {
1775         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1776 }
1777
1778 static inline bool cpu_has_vmx_ept_2m_page(void)
1779 {
1780         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1781 }
1782
1783 static inline bool cpu_has_vmx_ept_1g_page(void)
1784 {
1785         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1786 }
1787
1788 static inline bool cpu_has_vmx_ept_4levels(void)
1789 {
1790         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1791 }
1792
1793 static inline bool cpu_has_vmx_ept_mt_wb(void)
1794 {
1795         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1796 }
1797
1798 static inline bool cpu_has_vmx_ept_5levels(void)
1799 {
1800         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1801 }
1802
1803 static inline bool cpu_has_vmx_ept_ad_bits(void)
1804 {
1805         return vmx_capability.ept & VMX_EPT_AD_BIT;
1806 }
1807
1808 static inline bool cpu_has_vmx_invept_context(void)
1809 {
1810         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1811 }
1812
1813 static inline bool cpu_has_vmx_invept_global(void)
1814 {
1815         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1816 }
1817
1818 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
1819 {
1820         return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT;
1821 }
1822
1823 static inline bool cpu_has_vmx_invvpid_single(void)
1824 {
1825         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1826 }
1827
1828 static inline bool cpu_has_vmx_invvpid_global(void)
1829 {
1830         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1831 }
1832
1833 static inline bool cpu_has_vmx_invvpid(void)
1834 {
1835         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1836 }
1837
1838 static inline bool cpu_has_vmx_ept(void)
1839 {
1840         return vmcs_config.cpu_based_2nd_exec_ctrl &
1841                 SECONDARY_EXEC_ENABLE_EPT;
1842 }
1843
1844 static inline bool cpu_has_vmx_unrestricted_guest(void)
1845 {
1846         return vmcs_config.cpu_based_2nd_exec_ctrl &
1847                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1848 }
1849
1850 static inline bool cpu_has_vmx_ple(void)
1851 {
1852         return vmcs_config.cpu_based_2nd_exec_ctrl &
1853                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1854 }
1855
1856 static inline bool cpu_has_vmx_basic_inout(void)
1857 {
1858         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1859 }
1860
1861 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1862 {
1863         return flexpriority_enabled && lapic_in_kernel(vcpu);
1864 }
1865
1866 static inline bool cpu_has_vmx_vpid(void)
1867 {
1868         return vmcs_config.cpu_based_2nd_exec_ctrl &
1869                 SECONDARY_EXEC_ENABLE_VPID;
1870 }
1871
1872 static inline bool cpu_has_vmx_rdtscp(void)
1873 {
1874         return vmcs_config.cpu_based_2nd_exec_ctrl &
1875                 SECONDARY_EXEC_RDTSCP;
1876 }
1877
1878 static inline bool cpu_has_vmx_invpcid(void)
1879 {
1880         return vmcs_config.cpu_based_2nd_exec_ctrl &
1881                 SECONDARY_EXEC_ENABLE_INVPCID;
1882 }
1883
1884 static inline bool cpu_has_virtual_nmis(void)
1885 {
1886         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1887 }
1888
1889 static inline bool cpu_has_vmx_wbinvd_exit(void)
1890 {
1891         return vmcs_config.cpu_based_2nd_exec_ctrl &
1892                 SECONDARY_EXEC_WBINVD_EXITING;
1893 }
1894
1895 static inline bool cpu_has_vmx_shadow_vmcs(void)
1896 {
1897         u64 vmx_msr;
1898         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1899         /* check if the cpu supports writing r/o exit information fields */
1900         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1901                 return false;
1902
1903         return vmcs_config.cpu_based_2nd_exec_ctrl &
1904                 SECONDARY_EXEC_SHADOW_VMCS;
1905 }
1906
1907 static inline bool cpu_has_vmx_pml(void)
1908 {
1909         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1910 }
1911
1912 static inline bool cpu_has_vmx_tsc_scaling(void)
1913 {
1914         return vmcs_config.cpu_based_2nd_exec_ctrl &
1915                 SECONDARY_EXEC_TSC_SCALING;
1916 }
1917
1918 static inline bool cpu_has_vmx_vmfunc(void)
1919 {
1920         return vmcs_config.cpu_based_2nd_exec_ctrl &
1921                 SECONDARY_EXEC_ENABLE_VMFUNC;
1922 }
1923
1924 static bool vmx_umip_emulated(void)
1925 {
1926         return vmcs_config.cpu_based_2nd_exec_ctrl &
1927                 SECONDARY_EXEC_DESC;
1928 }
1929
1930 static inline bool report_flexpriority(void)
1931 {
1932         return flexpriority_enabled;
1933 }
1934
1935 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1936 {
1937         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
1938 }
1939
1940 /*
1941  * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
1942  * to modify any valid field of the VMCS, or are the VM-exit
1943  * information fields read-only?
1944  */
1945 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
1946 {
1947         return to_vmx(vcpu)->nested.msrs.misc_low &
1948                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
1949 }
1950
1951 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)
1952 {
1953         return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS;
1954 }
1955
1956 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu)
1957 {
1958         return to_vmx(vcpu)->nested.msrs.procbased_ctls_high &
1959                         CPU_BASED_MONITOR_TRAP_FLAG;
1960 }
1961
1962 static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu *vcpu)
1963 {
1964         return to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
1965                 SECONDARY_EXEC_SHADOW_VMCS;
1966 }
1967
1968 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1969 {
1970         return vmcs12->cpu_based_vm_exec_control & bit;
1971 }
1972
1973 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1974 {
1975         return (vmcs12->cpu_based_vm_exec_control &
1976                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1977                 (vmcs12->secondary_vm_exec_control & bit);
1978 }
1979
1980 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1981 {
1982         return vmcs12->pin_based_vm_exec_control &
1983                 PIN_BASED_VMX_PREEMPTION_TIMER;
1984 }
1985
1986 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
1987 {
1988         return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
1989 }
1990
1991 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1992 {
1993         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1994 }
1995
1996 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1997 {
1998         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1999 }
2000
2001 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
2002 {
2003         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
2004 }
2005
2006 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
2007 {
2008         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
2009 }
2010
2011 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
2012 {
2013         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
2014 }
2015
2016 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
2017 {
2018         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
2019 }
2020
2021 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
2022 {
2023         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
2024 }
2025
2026 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
2027 {
2028         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2029 }
2030
2031 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
2032 {
2033         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
2034 }
2035
2036 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
2037 {
2038         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
2039 }
2040
2041 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
2042 {
2043         return nested_cpu_has_vmfunc(vmcs12) &&
2044                 (vmcs12->vm_function_control &
2045                  VMX_VMFUNC_EPTP_SWITCHING);
2046 }
2047
2048 static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12 *vmcs12)
2049 {
2050         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS);
2051 }
2052
2053 static inline bool is_nmi(u32 intr_info)
2054 {
2055         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
2056                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
2057 }
2058
2059 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
2060                               u32 exit_intr_info,
2061                               unsigned long exit_qualification);
2062 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
2063                         struct vmcs12 *vmcs12,
2064                         u32 reason, unsigned long qualification);
2065
2066 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
2067 {
2068         int i;
2069
2070         for (i = 0; i < vmx->nmsrs; ++i)
2071                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
2072                         return i;
2073         return -1;
2074 }
2075
2076 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
2077 {
2078     struct {
2079         u64 vpid : 16;
2080         u64 rsvd : 48;
2081         u64 gva;
2082     } operand = { vpid, 0, gva };
2083     bool error;
2084
2085     asm volatile (__ex(ASM_VMX_INVVPID) CC_SET(na)
2086                   : CC_OUT(na) (error) : "a"(&operand), "c"(ext)
2087                   : "memory");
2088     BUG_ON(error);
2089 }
2090
2091 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
2092 {
2093         struct {
2094                 u64 eptp, gpa;
2095         } operand = {eptp, gpa};
2096         bool error;
2097
2098         asm volatile (__ex(ASM_VMX_INVEPT) CC_SET(na)
2099                       : CC_OUT(na) (error) : "a" (&operand), "c" (ext)
2100                       : "memory");
2101         BUG_ON(error);
2102 }
2103
2104 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
2105 {
2106         int i;
2107
2108         i = __find_msr_index(vmx, msr);
2109         if (i >= 0)
2110                 return &vmx->guest_msrs[i];
2111         return NULL;
2112 }
2113
2114 static void vmcs_clear(struct vmcs *vmcs)
2115 {
2116         u64 phys_addr = __pa(vmcs);
2117         bool error;
2118
2119         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) CC_SET(na)
2120                       : CC_OUT(na) (error) : "a"(&phys_addr), "m"(phys_addr)
2121                       : "memory");
2122         if (unlikely(error))
2123                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
2124                        vmcs, phys_addr);
2125 }
2126
2127 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
2128 {
2129         vmcs_clear(loaded_vmcs->vmcs);
2130         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
2131                 vmcs_clear(loaded_vmcs->shadow_vmcs);
2132         loaded_vmcs->cpu = -1;
2133         loaded_vmcs->launched = 0;
2134 }
2135
2136 static void vmcs_load(struct vmcs *vmcs)
2137 {
2138         u64 phys_addr = __pa(vmcs);
2139         bool error;
2140
2141         if (static_branch_unlikely(&enable_evmcs))
2142                 return evmcs_load(phys_addr);
2143
2144         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) CC_SET(na)
2145                       : CC_OUT(na) (error) : "a"(&phys_addr), "m"(phys_addr)
2146                       : "memory");
2147         if (unlikely(error))
2148                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
2149                        vmcs, phys_addr);
2150 }
2151
2152 #ifdef CONFIG_KEXEC_CORE
2153 /*
2154  * This bitmap is used to indicate whether the vmclear
2155  * operation is enabled on all cpus. All disabled by
2156  * default.
2157  */
2158 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
2159
2160 static inline void crash_enable_local_vmclear(int cpu)
2161 {
2162         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
2163 }
2164
2165 static inline void crash_disable_local_vmclear(int cpu)
2166 {
2167         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
2168 }
2169
2170 static inline int crash_local_vmclear_enabled(int cpu)
2171 {
2172         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
2173 }
2174
2175 static void crash_vmclear_local_loaded_vmcss(void)
2176 {
2177         int cpu = raw_smp_processor_id();
2178         struct loaded_vmcs *v;
2179
2180         if (!crash_local_vmclear_enabled(cpu))
2181                 return;
2182
2183         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
2184                             loaded_vmcss_on_cpu_link)
2185                 vmcs_clear(v->vmcs);
2186 }
2187 #else
2188 static inline void crash_enable_local_vmclear(int cpu) { }
2189 static inline void crash_disable_local_vmclear(int cpu) { }
2190 #endif /* CONFIG_KEXEC_CORE */
2191
2192 static void __loaded_vmcs_clear(void *arg)
2193 {
2194         struct loaded_vmcs *loaded_vmcs = arg;
2195         int cpu = raw_smp_processor_id();
2196
2197         if (loaded_vmcs->cpu != cpu)
2198                 return; /* vcpu migration can race with cpu offline */
2199         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
2200                 per_cpu(current_vmcs, cpu) = NULL;
2201         crash_disable_local_vmclear(cpu);
2202         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
2203
2204         /*
2205          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
2206          * is before setting loaded_vmcs->vcpu to -1 which is done in
2207          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
2208          * then adds the vmcs into percpu list before it is deleted.
2209          */
2210         smp_wmb();
2211
2212         loaded_vmcs_init(loaded_vmcs);
2213         crash_enable_local_vmclear(cpu);
2214 }
2215
2216 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
2217 {
2218         int cpu = loaded_vmcs->cpu;
2219
2220         if (cpu != -1)
2221                 smp_call_function_single(cpu,
2222                          __loaded_vmcs_clear, loaded_vmcs, 1);
2223 }
2224
2225 static inline bool vpid_sync_vcpu_addr(int vpid, gva_t addr)
2226 {
2227         if (vpid == 0)
2228                 return true;
2229
2230         if (cpu_has_vmx_invvpid_individual_addr()) {
2231                 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR, vpid, addr);
2232                 return true;
2233         }
2234
2235         return false;
2236 }
2237
2238 static inline void vpid_sync_vcpu_single(int vpid)
2239 {
2240         if (vpid == 0)
2241                 return;
2242
2243         if (cpu_has_vmx_invvpid_single())
2244                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2245 }
2246
2247 static inline void vpid_sync_vcpu_global(void)
2248 {
2249         if (cpu_has_vmx_invvpid_global())
2250                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
2251 }
2252
2253 static inline void vpid_sync_context(int vpid)
2254 {
2255         if (cpu_has_vmx_invvpid_single())
2256                 vpid_sync_vcpu_single(vpid);
2257         else
2258                 vpid_sync_vcpu_global();
2259 }
2260
2261 static inline void ept_sync_global(void)
2262 {
2263         __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
2264 }
2265
2266 static inline void ept_sync_context(u64 eptp)
2267 {
2268         if (cpu_has_vmx_invept_context())
2269                 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
2270         else
2271                 ept_sync_global();
2272 }
2273
2274 static __always_inline void vmcs_check16(unsigned long field)
2275 {
2276         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2277                          "16-bit accessor invalid for 64-bit field");
2278         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2279                          "16-bit accessor invalid for 64-bit high field");
2280         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2281                          "16-bit accessor invalid for 32-bit high field");
2282         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2283                          "16-bit accessor invalid for natural width field");
2284 }
2285
2286 static __always_inline void vmcs_check32(unsigned long field)
2287 {
2288         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2289                          "32-bit accessor invalid for 16-bit field");
2290         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2291                          "32-bit accessor invalid for natural width field");
2292 }
2293
2294 static __always_inline void vmcs_check64(unsigned long field)
2295 {
2296         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2297                          "64-bit accessor invalid for 16-bit field");
2298         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2299                          "64-bit accessor invalid for 64-bit high field");
2300         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2301                          "64-bit accessor invalid for 32-bit field");
2302         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2303                          "64-bit accessor invalid for natural width field");
2304 }
2305
2306 static __always_inline void vmcs_checkl(unsigned long field)
2307 {
2308         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2309                          "Natural width accessor invalid for 16-bit field");
2310         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2311                          "Natural width accessor invalid for 64-bit field");
2312         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2313                          "Natural width accessor invalid for 64-bit high field");
2314         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2315                          "Natural width accessor invalid for 32-bit field");
2316 }
2317
2318 static __always_inline unsigned long __vmcs_readl(unsigned long field)
2319 {
2320         unsigned long value;
2321
2322         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
2323                       : "=a"(value) : "d"(field) : "cc");
2324         return value;
2325 }
2326
2327 static __always_inline u16 vmcs_read16(unsigned long field)
2328 {
2329         vmcs_check16(field);
2330         if (static_branch_unlikely(&enable_evmcs))
2331                 return evmcs_read16(field);
2332         return __vmcs_readl(field);
2333 }
2334
2335 static __always_inline u32 vmcs_read32(unsigned long field)
2336 {
2337         vmcs_check32(field);
2338         if (static_branch_unlikely(&enable_evmcs))
2339                 return evmcs_read32(field);
2340         return __vmcs_readl(field);
2341 }
2342
2343 static __always_inline u64 vmcs_read64(unsigned long field)
2344 {
2345         vmcs_check64(field);
2346         if (static_branch_unlikely(&enable_evmcs))
2347                 return evmcs_read64(field);
2348 #ifdef CONFIG_X86_64
2349         return __vmcs_readl(field);
2350 #else
2351         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
2352 #endif
2353 }
2354
2355 static __always_inline unsigned long vmcs_readl(unsigned long field)
2356 {
2357         vmcs_checkl(field);
2358         if (static_branch_unlikely(&enable_evmcs))
2359                 return evmcs_read64(field);
2360         return __vmcs_readl(field);
2361 }
2362
2363 static noinline void vmwrite_error(unsigned long field, unsigned long value)
2364 {
2365         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
2366                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
2367         dump_stack();
2368 }
2369
2370 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
2371 {
2372         bool error;
2373
2374         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) CC_SET(na)
2375                       : CC_OUT(na) (error) : "a"(value), "d"(field));
2376         if (unlikely(error))
2377                 vmwrite_error(field, value);
2378 }
2379
2380 static __always_inline void vmcs_write16(unsigned long field, u16 value)
2381 {
2382         vmcs_check16(field);
2383         if (static_branch_unlikely(&enable_evmcs))
2384                 return evmcs_write16(field, value);
2385
2386         __vmcs_writel(field, value);
2387 }
2388
2389 static __always_inline void vmcs_write32(unsigned long field, u32 value)
2390 {
2391         vmcs_check32(field);
2392         if (static_branch_unlikely(&enable_evmcs))
2393                 return evmcs_write32(field, value);
2394
2395         __vmcs_writel(field, value);
2396 }
2397
2398 static __always_inline void vmcs_write64(unsigned long field, u64 value)
2399 {
2400         vmcs_check64(field);
2401         if (static_branch_unlikely(&enable_evmcs))
2402                 return evmcs_write64(field, value);
2403
2404         __vmcs_writel(field, value);
2405 #ifndef CONFIG_X86_64
2406         asm volatile ("");
2407         __vmcs_writel(field+1, value >> 32);
2408 #endif
2409 }
2410
2411 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2412 {
2413         vmcs_checkl(field);
2414         if (static_branch_unlikely(&enable_evmcs))
2415                 return evmcs_write64(field, value);
2416
2417         __vmcs_writel(field, value);
2418 }
2419
2420 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2421 {
2422         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2423                          "vmcs_clear_bits does not support 64-bit fields");
2424         if (static_branch_unlikely(&enable_evmcs))
2425                 return evmcs_write32(field, evmcs_read32(field) & ~mask);
2426
2427         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2428 }
2429
2430 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2431 {
2432         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2433                          "vmcs_set_bits does not support 64-bit fields");
2434         if (static_branch_unlikely(&enable_evmcs))
2435                 return evmcs_write32(field, evmcs_read32(field) | mask);
2436
2437         __vmcs_writel(field, __vmcs_readl(field) | mask);
2438 }
2439
2440 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
2441 {
2442         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
2443 }
2444
2445 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
2446 {
2447         vmcs_write32(VM_ENTRY_CONTROLS, val);
2448         vmx->vm_entry_controls_shadow = val;
2449 }
2450
2451 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
2452 {
2453         if (vmx->vm_entry_controls_shadow != val)
2454                 vm_entry_controls_init(vmx, val);
2455 }
2456
2457 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
2458 {
2459         return vmx->vm_entry_controls_shadow;
2460 }
2461
2462
2463 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2464 {
2465         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
2466 }
2467
2468 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2469 {
2470         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
2471 }
2472
2473 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
2474 {
2475         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
2476 }
2477
2478 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
2479 {
2480         vmcs_write32(VM_EXIT_CONTROLS, val);
2481         vmx->vm_exit_controls_shadow = val;
2482 }
2483
2484 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2485 {
2486         if (vmx->vm_exit_controls_shadow != val)
2487                 vm_exit_controls_init(vmx, val);
2488 }
2489
2490 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2491 {
2492         return vmx->vm_exit_controls_shadow;
2493 }
2494
2495
2496 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2497 {
2498         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2499 }
2500
2501 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2502 {
2503         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2504 }
2505
2506 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2507 {
2508         vmx->segment_cache.bitmask = 0;
2509 }
2510
2511 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2512                                        unsigned field)
2513 {
2514         bool ret;
2515         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2516
2517         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2518                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2519                 vmx->segment_cache.bitmask = 0;
2520         }
2521         ret = vmx->segment_cache.bitmask & mask;
2522         vmx->segment_cache.bitmask |= mask;
2523         return ret;
2524 }
2525
2526 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2527 {
2528         u16 *p = &vmx->segment_cache.seg[seg].selector;
2529
2530         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2531                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2532         return *p;
2533 }
2534
2535 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2536 {
2537         ulong *p = &vmx->segment_cache.seg[seg].base;
2538
2539         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2540                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2541         return *p;
2542 }
2543
2544 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2545 {
2546         u32 *p = &vmx->segment_cache.seg[seg].limit;
2547
2548         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2549                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2550         return *p;
2551 }
2552
2553 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2554 {
2555         u32 *p = &vmx->segment_cache.seg[seg].ar;
2556
2557         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2558                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2559         return *p;
2560 }
2561
2562 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2563 {
2564         u32 eb;
2565
2566         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2567              (1u << DB_VECTOR) | (1u << AC_VECTOR);
2568         /*
2569          * Guest access to VMware backdoor ports could legitimately
2570          * trigger #GP because of TSS I/O permission bitmap.
2571          * We intercept those #GP and allow access to them anyway
2572          * as VMware does.
2573          */
2574         if (enable_vmware_backdoor)
2575                 eb |= (1u << GP_VECTOR);
2576         if ((vcpu->guest_debug &
2577              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2578             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2579                 eb |= 1u << BP_VECTOR;
2580         if (to_vmx(vcpu)->rmode.vm86_active)
2581                 eb = ~0;
2582         if (enable_ept)
2583                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2584
2585         /* When we are running a nested L2 guest and L1 specified for it a
2586          * certain exception bitmap, we must trap the same exceptions and pass
2587          * them to L1. When running L2, we will only handle the exceptions
2588          * specified above if L1 did not want them.
2589          */
2590         if (is_guest_mode(vcpu))
2591                 eb |= get_vmcs12(vcpu)->exception_bitmap;
2592
2593         vmcs_write32(EXCEPTION_BITMAP, eb);
2594 }
2595
2596 /*
2597  * Check if MSR is intercepted for currently loaded MSR bitmap.
2598  */
2599 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2600 {
2601         unsigned long *msr_bitmap;
2602         int f = sizeof(unsigned long);
2603
2604         if (!cpu_has_vmx_msr_bitmap())
2605                 return true;
2606
2607         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2608
2609         if (msr <= 0x1fff) {
2610                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2611         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2612                 msr &= 0x1fff;
2613                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2614         }
2615
2616         return true;
2617 }
2618
2619 /*
2620  * Check if MSR is intercepted for L01 MSR bitmap.
2621  */
2622 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2623 {
2624         unsigned long *msr_bitmap;
2625         int f = sizeof(unsigned long);
2626
2627         if (!cpu_has_vmx_msr_bitmap())
2628                 return true;
2629
2630         msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2631
2632         if (msr <= 0x1fff) {
2633                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2634         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2635                 msr &= 0x1fff;
2636                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2637         }
2638
2639         return true;
2640 }
2641
2642 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2643                 unsigned long entry, unsigned long exit)
2644 {
2645         vm_entry_controls_clearbit(vmx, entry);
2646         vm_exit_controls_clearbit(vmx, exit);
2647 }
2648
2649 static int find_msr(struct vmx_msrs *m, unsigned int msr)
2650 {
2651         unsigned int i;
2652
2653         for (i = 0; i < m->nr; ++i) {
2654                 if (m->val[i].index == msr)
2655                         return i;
2656         }
2657         return -ENOENT;
2658 }
2659
2660 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2661 {
2662         int i;
2663         struct msr_autoload *m = &vmx->msr_autoload;
2664
2665         switch (msr) {
2666         case MSR_EFER:
2667                 if (cpu_has_load_ia32_efer) {
2668                         clear_atomic_switch_msr_special(vmx,
2669                                         VM_ENTRY_LOAD_IA32_EFER,
2670                                         VM_EXIT_LOAD_IA32_EFER);
2671                         return;
2672                 }
2673                 break;
2674         case MSR_CORE_PERF_GLOBAL_CTRL:
2675                 if (cpu_has_load_perf_global_ctrl) {
2676                         clear_atomic_switch_msr_special(vmx,
2677                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2678                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2679                         return;
2680                 }
2681                 break;
2682         }
2683         i = find_msr(&m->guest, msr);
2684         if (i < 0)
2685                 goto skip_guest;
2686         --m->guest.nr;
2687         m->guest.val[i] = m->guest.val[m->guest.nr];
2688         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2689
2690 skip_guest:
2691         i = find_msr(&m->host, msr);
2692         if (i < 0)
2693                 return;
2694
2695         --m->host.nr;
2696         m->host.val[i] = m->host.val[m->host.nr];
2697         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2698 }
2699
2700 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2701                 unsigned long entry, unsigned long exit,
2702                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2703                 u64 guest_val, u64 host_val)
2704 {
2705         vmcs_write64(guest_val_vmcs, guest_val);
2706         vmcs_write64(host_val_vmcs, host_val);
2707         vm_entry_controls_setbit(vmx, entry);
2708         vm_exit_controls_setbit(vmx, exit);
2709 }
2710
2711 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2712                                   u64 guest_val, u64 host_val, bool entry_only)
2713 {
2714         int i, j = 0;
2715         struct msr_autoload *m = &vmx->msr_autoload;
2716
2717         switch (msr) {
2718         case MSR_EFER:
2719                 if (cpu_has_load_ia32_efer) {
2720                         add_atomic_switch_msr_special(vmx,
2721                                         VM_ENTRY_LOAD_IA32_EFER,
2722                                         VM_EXIT_LOAD_IA32_EFER,
2723                                         GUEST_IA32_EFER,
2724                                         HOST_IA32_EFER,
2725                                         guest_val, host_val);
2726                         return;
2727                 }
2728                 break;
2729         case MSR_CORE_PERF_GLOBAL_CTRL:
2730                 if (cpu_has_load_perf_global_ctrl) {
2731                         add_atomic_switch_msr_special(vmx,
2732                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2733                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2734                                         GUEST_IA32_PERF_GLOBAL_CTRL,
2735                                         HOST_IA32_PERF_GLOBAL_CTRL,
2736                                         guest_val, host_val);
2737                         return;
2738                 }
2739                 break;
2740         case MSR_IA32_PEBS_ENABLE:
2741                 /* PEBS needs a quiescent period after being disabled (to write
2742                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
2743                  * provide that period, so a CPU could write host's record into
2744                  * guest's memory.
2745                  */
2746                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2747         }
2748
2749         i = find_msr(&m->guest, msr);
2750         if (!entry_only)
2751                 j = find_msr(&m->host, msr);
2752
2753         if (i == NR_AUTOLOAD_MSRS || j == NR_AUTOLOAD_MSRS) {
2754                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2755                                 "Can't add msr %x\n", msr);
2756                 return;
2757         }
2758         if (i < 0) {
2759                 i = m->guest.nr++;
2760                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2761         }
2762         m->guest.val[i].index = msr;
2763         m->guest.val[i].value = guest_val;
2764
2765         if (entry_only)
2766                 return;
2767
2768         if (j < 0) {
2769                 j = m->host.nr++;
2770                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2771         }
2772         m->host.val[j].index = msr;
2773         m->host.val[j].value = host_val;
2774 }
2775
2776 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2777 {
2778         u64 guest_efer = vmx->vcpu.arch.efer;
2779         u64 ignore_bits = 0;
2780
2781         if (!enable_ept) {
2782                 /*
2783                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2784                  * host CPUID is more efficient than testing guest CPUID
2785                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2786                  */
2787                 if (boot_cpu_has(X86_FEATURE_SMEP))
2788                         guest_efer |= EFER_NX;
2789                 else if (!(guest_efer & EFER_NX))
2790                         ignore_bits |= EFER_NX;
2791         }
2792
2793         /*
2794          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2795          */
2796         ignore_bits |= EFER_SCE;
2797 #ifdef CONFIG_X86_64
2798         ignore_bits |= EFER_LMA | EFER_LME;
2799         /* SCE is meaningful only in long mode on Intel */
2800         if (guest_efer & EFER_LMA)
2801                 ignore_bits &= ~(u64)EFER_SCE;
2802 #endif
2803
2804         clear_atomic_switch_msr(vmx, MSR_EFER);
2805
2806         /*
2807          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2808          * On CPUs that support "load IA32_EFER", always switch EFER
2809          * atomically, since it's faster than switching it manually.
2810          */
2811         if (cpu_has_load_ia32_efer ||
2812             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2813                 if (!(guest_efer & EFER_LMA))
2814                         guest_efer &= ~EFER_LME;
2815                 if (guest_efer != host_efer)
2816                         add_atomic_switch_msr(vmx, MSR_EFER,
2817                                               guest_efer, host_efer, false);
2818                 return false;
2819         } else {
2820                 guest_efer &= ~ignore_bits;
2821                 guest_efer |= host_efer & ignore_bits;
2822
2823                 vmx->guest_msrs[efer_offset].data = guest_efer;
2824                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2825
2826                 return true;
2827         }
2828 }
2829
2830 #ifdef CONFIG_X86_32
2831 /*
2832  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2833  * VMCS rather than the segment table.  KVM uses this helper to figure
2834  * out the current bases to poke them into the VMCS before entry.
2835  */
2836 static unsigned long segment_base(u16 selector)
2837 {
2838         struct desc_struct *table;
2839         unsigned long v;
2840
2841         if (!(selector & ~SEGMENT_RPL_MASK))
2842                 return 0;
2843
2844         table = get_current_gdt_ro();
2845
2846         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2847                 u16 ldt_selector = kvm_read_ldt();
2848
2849                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2850                         return 0;
2851
2852                 table = (struct desc_struct *)segment_base(ldt_selector);
2853         }
2854         v = get_desc_base(&table[selector >> 3]);
2855         return v;
2856 }
2857 #endif
2858
2859 static void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
2860 {
2861         struct vcpu_vmx *vmx = to_vmx(vcpu);
2862         struct vmcs_host_state *host_state;
2863 #ifdef CONFIG_X86_64
2864         int cpu = raw_smp_processor_id();
2865 #endif
2866         unsigned long fs_base, gs_base;
2867         u16 fs_sel, gs_sel;
2868         int i;
2869
2870         vmx->req_immediate_exit = false;
2871
2872         if (vmx->loaded_cpu_state)
2873                 return;
2874
2875         vmx->loaded_cpu_state = vmx->loaded_vmcs;
2876         host_state = &vmx->loaded_cpu_state->host_state;
2877
2878         /*
2879          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2880          * allow segment selectors with cpl > 0 or ti == 1.
2881          */
2882         host_state->ldt_sel = kvm_read_ldt();
2883
2884 #ifdef CONFIG_X86_64
2885         savesegment(ds, host_state->ds_sel);
2886         savesegment(es, host_state->es_sel);
2887
2888         gs_base = cpu_kernelmode_gs_base(cpu);
2889         if (likely(is_64bit_mm(current->mm))) {
2890                 save_fsgs_for_kvm();
2891                 fs_sel = current->thread.fsindex;
2892                 gs_sel = current->thread.gsindex;
2893                 fs_base = current->thread.fsbase;
2894                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
2895         } else {
2896                 savesegment(fs, fs_sel);
2897                 savesegment(gs, gs_sel);
2898                 fs_base = read_msr(MSR_FS_BASE);
2899                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
2900         }
2901
2902         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2903 #else
2904         savesegment(fs, fs_sel);
2905         savesegment(gs, gs_sel);
2906         fs_base = segment_base(fs_sel);
2907         gs_base = segment_base(gs_sel);
2908 #endif
2909
2910         if (unlikely(fs_sel != host_state->fs_sel)) {
2911                 if (!(fs_sel & 7))
2912                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
2913                 else
2914                         vmcs_write16(HOST_FS_SELECTOR, 0);
2915                 host_state->fs_sel = fs_sel;
2916         }
2917         if (unlikely(gs_sel != host_state->gs_sel)) {
2918                 if (!(gs_sel & 7))
2919                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
2920                 else
2921                         vmcs_write16(HOST_GS_SELECTOR, 0);
2922                 host_state->gs_sel = gs_sel;
2923         }
2924         if (unlikely(fs_base != host_state->fs_base)) {
2925                 vmcs_writel(HOST_FS_BASE, fs_base);
2926                 host_state->fs_base = fs_base;
2927         }
2928         if (unlikely(gs_base != host_state->gs_base)) {
2929                 vmcs_writel(HOST_GS_BASE, gs_base);
2930                 host_state->gs_base = gs_base;
2931         }
2932
2933         for (i = 0; i < vmx->save_nmsrs; ++i)
2934                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2935                                    vmx->guest_msrs[i].data,
2936                                    vmx->guest_msrs[i].mask);
2937 }
2938
2939 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
2940 {
2941         struct vmcs_host_state *host_state;
2942
2943         if (!vmx->loaded_cpu_state)
2944                 return;
2945
2946         WARN_ON_ONCE(vmx->loaded_cpu_state != vmx->loaded_vmcs);
2947         host_state = &vmx->loaded_cpu_state->host_state;
2948
2949         ++vmx->vcpu.stat.host_state_reload;
2950         vmx->loaded_cpu_state = NULL;
2951
2952 #ifdef CONFIG_X86_64
2953         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2954 #endif
2955         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
2956                 kvm_load_ldt(host_state->ldt_sel);
2957 #ifdef CONFIG_X86_64
2958                 load_gs_index(host_state->gs_sel);
2959 #else
2960                 loadsegment(gs, host_state->gs_sel);
2961 #endif
2962         }
2963         if (host_state->fs_sel & 7)
2964                 loadsegment(fs, host_state->fs_sel);
2965 #ifdef CONFIG_X86_64
2966         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
2967                 loadsegment(ds, host_state->ds_sel);
2968                 loadsegment(es, host_state->es_sel);
2969         }
2970 #endif
2971         invalidate_tss_limit();
2972 #ifdef CONFIG_X86_64
2973         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2974 #endif
2975         load_fixmap_gdt(raw_smp_processor_id());
2976 }
2977
2978 #ifdef CONFIG_X86_64
2979 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
2980 {
2981         preempt_disable();
2982         if (vmx->loaded_cpu_state)
2983                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2984         preempt_enable();
2985         return vmx->msr_guest_kernel_gs_base;
2986 }
2987
2988 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
2989 {
2990         preempt_disable();
2991         if (vmx->loaded_cpu_state)
2992                 wrmsrl(MSR_KERNEL_GS_BASE, data);
2993         preempt_enable();
2994         vmx->msr_guest_kernel_gs_base = data;
2995 }
2996 #endif
2997
2998 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2999 {
3000         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
3001         struct pi_desc old, new;
3002         unsigned int dest;
3003
3004         /*
3005          * In case of hot-plug or hot-unplug, we may have to undo
3006          * vmx_vcpu_pi_put even if there is no assigned device.  And we
3007          * always keep PI.NDST up to date for simplicity: it makes the
3008          * code easier, and CPU migration is not a fast path.
3009          */
3010         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
3011                 return;
3012
3013         /*
3014          * First handle the simple case where no cmpxchg is necessary; just
3015          * allow posting non-urgent interrupts.
3016          *
3017          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
3018          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
3019          * expects the VCPU to be on the blocked_vcpu_list that matches
3020          * PI.NDST.
3021          */
3022         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
3023             vcpu->cpu == cpu) {
3024                 pi_clear_sn(pi_desc);
3025                 return;
3026         }
3027
3028         /* The full case.  */
3029         do {
3030                 old.control = new.control = pi_desc->control;
3031
3032                 dest = cpu_physical_id(cpu);
3033
3034                 if (x2apic_enabled())
3035                         new.ndst = dest;
3036                 else
3037                         new.ndst = (dest << 8) & 0xFF00;
3038
3039                 new.sn = 0;
3040         } while (cmpxchg64(&pi_desc->control, old.control,
3041                            new.control) != old.control);
3042 }
3043
3044 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
3045 {
3046         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
3047         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
3048 }
3049
3050 /*
3051  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
3052  * vcpu mutex is already taken.
3053  */
3054 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3055 {
3056         struct vcpu_vmx *vmx = to_vmx(vcpu);
3057         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
3058
3059         if (!already_loaded) {
3060                 loaded_vmcs_clear(vmx->loaded_vmcs);
3061                 local_irq_disable();
3062                 crash_disable_local_vmclear(cpu);
3063
3064                 /*
3065                  * Read loaded_vmcs->cpu should be before fetching
3066                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
3067                  * See the comments in __loaded_vmcs_clear().
3068                  */
3069                 smp_rmb();
3070
3071                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
3072                          &per_cpu(loaded_vmcss_on_cpu, cpu));
3073                 crash_enable_local_vmclear(cpu);
3074                 local_irq_enable();
3075         }
3076
3077         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
3078                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
3079                 vmcs_load(vmx->loaded_vmcs->vmcs);
3080                 indirect_branch_prediction_barrier();
3081         }
3082
3083         if (!already_loaded) {
3084                 void *gdt = get_current_gdt_ro();
3085                 unsigned long sysenter_esp;
3086
3087                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3088
3089                 /*
3090                  * Linux uses per-cpu TSS and GDT, so set these when switching
3091                  * processors.  See 22.2.4.
3092                  */
3093                 vmcs_writel(HOST_TR_BASE,
3094                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
3095                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
3096
3097                 /*
3098                  * VM exits change the host TR limit to 0x67 after a VM
3099                  * exit.  This is okay, since 0x67 covers everything except
3100                  * the IO bitmap and have have code to handle the IO bitmap
3101                  * being lost after a VM exit.
3102                  */
3103                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
3104
3105                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
3106                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
3107
3108                 vmx->loaded_vmcs->cpu = cpu;
3109         }
3110
3111         /* Setup TSC multiplier */
3112         if (kvm_has_tsc_control &&
3113             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
3114                 decache_tsc_multiplier(vmx);
3115
3116         vmx_vcpu_pi_load(vcpu, cpu);
3117         vmx->host_pkru = read_pkru();
3118         vmx->host_debugctlmsr = get_debugctlmsr();
3119 }
3120
3121 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
3122 {
3123         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
3124
3125         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
3126                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
3127                 !kvm_vcpu_apicv_active(vcpu))
3128                 return;
3129
3130         /* Set SN when the vCPU is preempted */
3131         if (vcpu->preempted)
3132                 pi_set_sn(pi_desc);
3133 }
3134
3135 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
3136 {
3137         vmx_vcpu_pi_put(vcpu);
3138
3139         vmx_prepare_switch_to_host(to_vmx(vcpu));
3140 }
3141
3142 static bool emulation_required(struct kvm_vcpu *vcpu)
3143 {
3144         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3145 }
3146
3147 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
3148
3149 /*
3150  * Return the cr0 value that a nested guest would read. This is a combination
3151  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
3152  * its hypervisor (cr0_read_shadow).
3153  */
3154 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
3155 {
3156         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
3157                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
3158 }
3159 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
3160 {
3161         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
3162                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
3163 }
3164
3165 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
3166 {
3167         unsigned long rflags, save_rflags;
3168
3169         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
3170                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
3171                 rflags = vmcs_readl(GUEST_RFLAGS);
3172                 if (to_vmx(vcpu)->rmode.vm86_active) {
3173                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3174                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
3175                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3176                 }
3177                 to_vmx(vcpu)->rflags = rflags;
3178         }
3179         return to_vmx(vcpu)->rflags;
3180 }
3181
3182 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
3183 {
3184         unsigned long old_rflags = vmx_get_rflags(vcpu);
3185
3186         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
3187         to_vmx(vcpu)->rflags = rflags;
3188         if (to_vmx(vcpu)->rmode.vm86_active) {
3189                 to_vmx(vcpu)->rmode.save_rflags = rflags;
3190                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3191         }
3192         vmcs_writel(GUEST_RFLAGS, rflags);
3193
3194         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
3195                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
3196 }
3197
3198 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
3199 {
3200         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3201         int ret = 0;
3202
3203         if (interruptibility & GUEST_INTR_STATE_STI)
3204                 ret |= KVM_X86_SHADOW_INT_STI;
3205         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
3206                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
3207
3208         return ret;
3209 }
3210
3211 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
3212 {
3213         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3214         u32 interruptibility = interruptibility_old;
3215
3216         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
3217
3218         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
3219                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
3220         else if (mask & KVM_X86_SHADOW_INT_STI)
3221                 interruptibility |= GUEST_INTR_STATE_STI;
3222
3223         if ((interruptibility != interruptibility_old))
3224                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
3225 }
3226
3227 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
3228 {
3229         unsigned long rip;
3230
3231         rip = kvm_rip_read(vcpu);
3232         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3233         kvm_rip_write(vcpu, rip);
3234
3235         /* skipping an emulated instruction also counts */
3236         vmx_set_interrupt_shadow(vcpu, 0);
3237 }
3238
3239 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
3240                                                unsigned long exit_qual)
3241 {
3242         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3243         unsigned int nr = vcpu->arch.exception.nr;
3244         u32 intr_info = nr | INTR_INFO_VALID_MASK;
3245
3246         if (vcpu->arch.exception.has_error_code) {
3247                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
3248                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3249         }
3250
3251         if (kvm_exception_is_soft(nr))
3252                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3253         else
3254                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3255
3256         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
3257             vmx_get_nmi_mask(vcpu))
3258                 intr_info |= INTR_INFO_UNBLOCK_NMI;
3259
3260         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
3261 }
3262
3263 /*
3264  * KVM wants to inject page-faults which it got to the guest. This function
3265  * checks whether in a nested guest, we need to inject them to L1 or L2.
3266  */
3267 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
3268 {
3269         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3270         unsigned int nr = vcpu->arch.exception.nr;
3271
3272         if (nr == PF_VECTOR) {
3273                 if (vcpu->arch.exception.nested_apf) {
3274                         *exit_qual = vcpu->arch.apf.nested_apf_token;
3275                         return 1;
3276                 }
3277                 /*
3278                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
3279                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
3280                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
3281                  * can be written only when inject_pending_event runs.  This should be
3282                  * conditional on a new capability---if the capability is disabled,
3283                  * kvm_multiple_exception would write the ancillary information to
3284                  * CR2 or DR6, for backwards ABI-compatibility.
3285                  */
3286                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
3287                                                     vcpu->arch.exception.error_code)) {
3288                         *exit_qual = vcpu->arch.cr2;
3289                         return 1;
3290                 }
3291         } else {
3292                 if (vmcs12->exception_bitmap & (1u << nr)) {
3293                         if (nr == DB_VECTOR)
3294                                 *exit_qual = vcpu->arch.dr6;
3295                         else
3296                                 *exit_qual = 0;
3297                         return 1;
3298                 }
3299         }
3300
3301         return 0;
3302 }
3303
3304 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
3305 {
3306         /*
3307          * Ensure that we clear the HLT state in the VMCS.  We don't need to
3308          * explicitly skip the instruction because if the HLT state is set,
3309          * then the instruction is already executing and RIP has already been
3310          * advanced.
3311          */
3312         if (kvm_hlt_in_guest(vcpu->kvm) &&
3313                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
3314                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3315 }
3316
3317 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
3318 {
3319         struct vcpu_vmx *vmx = to_vmx(vcpu);
3320         unsigned nr = vcpu->arch.exception.nr;
3321         bool has_error_code = vcpu->arch.exception.has_error_code;
3322         u32 error_code = vcpu->arch.exception.error_code;
3323         u32 intr_info = nr | INTR_INFO_VALID_MASK;
3324
3325         if (has_error_code) {
3326                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
3327                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3328         }
3329
3330         if (vmx->rmode.vm86_active) {
3331                 int inc_eip = 0;
3332                 if (kvm_exception_is_soft(nr))
3333                         inc_eip = vcpu->arch.event_exit_inst_len;
3334                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
3335                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3336                 return;
3337         }
3338
3339         WARN_ON_ONCE(vmx->emulation_required);
3340
3341         if (kvm_exception_is_soft(nr)) {
3342                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3343                              vmx->vcpu.arch.event_exit_inst_len);
3344                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3345         } else
3346                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3347
3348         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
3349
3350         vmx_clear_hlt(vcpu);
3351 }
3352
3353 static bool vmx_rdtscp_supported(void)
3354 {
3355         return cpu_has_vmx_rdtscp();
3356 }
3357
3358 static bool vmx_invpcid_supported(void)
3359 {
3360         return cpu_has_vmx_invpcid();
3361 }
3362
3363 /*
3364  * Swap MSR entry in host/guest MSR entry array.
3365  */
3366 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
3367 {
3368         struct shared_msr_entry tmp;
3369
3370         tmp = vmx->guest_msrs[to];
3371         vmx->guest_msrs[to] = vmx->guest_msrs[from];
3372         vmx->guest_msrs[from] = tmp;
3373 }
3374
3375 /*
3376  * Set up the vmcs to automatically save and restore system
3377  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
3378  * mode, as fiddling with msrs is very expensive.
3379  */
3380 static void setup_msrs(struct vcpu_vmx *vmx)
3381 {
3382         int save_nmsrs, index;
3383
3384         save_nmsrs = 0;
3385 #ifdef CONFIG_X86_64
3386         if (is_long_mode(&vmx->vcpu)) {
3387                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
3388                 if (index >= 0)
3389                         move_msr_up(vmx, index, save_nmsrs++);
3390                 index = __find_msr_index(vmx, MSR_LSTAR);
3391                 if (index >= 0)
3392                         move_msr_up(vmx, index, save_nmsrs++);
3393                 index = __find_msr_index(vmx, MSR_CSTAR);
3394                 if (index >= 0)
3395                         move_msr_up(vmx, index, save_nmsrs++);
3396                 index = __find_msr_index(vmx, MSR_TSC_AUX);
3397                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
3398                         move_msr_up(vmx, index, save_nmsrs++);
3399                 /*
3400                  * MSR_STAR is only needed on long mode guests, and only
3401                  * if efer.sce is enabled.
3402                  */
3403                 index = __find_msr_index(vmx, MSR_STAR);
3404                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
3405                         move_msr_up(vmx, index, save_nmsrs++);
3406         }
3407 #endif
3408         index = __find_msr_index(vmx, MSR_EFER);
3409         if (index >= 0 && update_transition_efer(vmx, index))
3410                 move_msr_up(vmx, index, save_nmsrs++);
3411
3412         vmx->save_nmsrs = save_nmsrs;
3413
3414         if (cpu_has_vmx_msr_bitmap())
3415                 vmx_update_msr_bitmap(&vmx->vcpu);
3416 }
3417
3418 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
3419 {
3420         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3421
3422         if (is_guest_mode(vcpu) &&
3423             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
3424                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
3425
3426         return vcpu->arch.tsc_offset;
3427 }
3428
3429 /*
3430  * writes 'offset' into guest's timestamp counter offset register
3431  */
3432 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
3433 {
3434         if (is_guest_mode(vcpu)) {
3435                 /*
3436                  * We're here if L1 chose not to trap WRMSR to TSC. According
3437                  * to the spec, this should set L1's TSC; The offset that L1
3438                  * set for L2 remains unchanged, and still needs to be added
3439                  * to the newly set TSC to get L2's TSC.
3440                  */
3441                 struct vmcs12 *vmcs12;
3442                 /* recalculate vmcs02.TSC_OFFSET: */
3443                 vmcs12 = get_vmcs12(vcpu);
3444                 vmcs_write64(TSC_OFFSET, offset +
3445                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
3446                          vmcs12->tsc_offset : 0));
3447         } else {
3448                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
3449                                            vmcs_read64(TSC_OFFSET), offset);
3450                 vmcs_write64(TSC_OFFSET, offset);
3451         }
3452 }
3453
3454 /*
3455  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
3456  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
3457  * all guests if the "nested" module option is off, and can also be disabled
3458  * for a single guest by disabling its VMX cpuid bit.
3459  */
3460 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
3461 {
3462         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
3463 }
3464
3465 /*
3466  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
3467  * returned for the various VMX controls MSRs when nested VMX is enabled.
3468  * The same values should also be used to verify that vmcs12 control fields are
3469  * valid during nested entry from L1 to L2.
3470  * Each of these control msrs has a low and high 32-bit half: A low bit is on
3471  * if the corresponding bit in the (32-bit) control field *must* be on, and a
3472  * bit in the high half is on if the corresponding bit in the control field
3473  * may be on. See also vmx_control_verify().
3474  */
3475 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
3476 {
3477         if (!nested) {
3478                 memset(msrs, 0, sizeof(*msrs));
3479                 return;
3480         }
3481
3482         /*
3483          * Note that as a general rule, the high half of the MSRs (bits in
3484          * the control fields which may be 1) should be initialized by the
3485          * intersection of the underlying hardware's MSR (i.e., features which
3486          * can be supported) and the list of features we want to expose -
3487          * because they are known to be properly supported in our code.
3488          * Also, usually, the low half of the MSRs (bits which must be 1) can
3489          * be set to 0, meaning that L1 may turn off any of these bits. The
3490          * reason is that if one of these bits is necessary, it will appear
3491          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
3492          * fields of vmcs01 and vmcs02, will turn these bits off - and
3493          * nested_vmx_exit_reflected() will not pass related exits to L1.
3494          * These rules have exceptions below.
3495          */
3496
3497         /* pin-based controls */
3498         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
3499                 msrs->pinbased_ctls_low,
3500                 msrs->pinbased_ctls_high);
3501         msrs->pinbased_ctls_low |=
3502                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3503         msrs->pinbased_ctls_high &=
3504                 PIN_BASED_EXT_INTR_MASK |
3505                 PIN_BASED_NMI_EXITING |
3506                 PIN_BASED_VIRTUAL_NMIS |
3507                 (apicv ? PIN_BASED_POSTED_INTR : 0);
3508         msrs->pinbased_ctls_high |=
3509                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3510                 PIN_BASED_VMX_PREEMPTION_TIMER;
3511
3512         /* exit controls */
3513         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
3514                 msrs->exit_ctls_low,
3515                 msrs->exit_ctls_high);
3516         msrs->exit_ctls_low =
3517                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3518
3519         msrs->exit_ctls_high &=
3520 #ifdef CONFIG_X86_64
3521                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
3522 #endif
3523                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
3524         msrs->exit_ctls_high |=
3525                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
3526                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
3527                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
3528
3529         /* We support free control of debug control saving. */
3530         msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
3531
3532         /* entry controls */
3533         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
3534                 msrs->entry_ctls_low,
3535                 msrs->entry_ctls_high);
3536         msrs->entry_ctls_low =
3537                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3538         msrs->entry_ctls_high &=
3539 #ifdef CONFIG_X86_64
3540                 VM_ENTRY_IA32E_MODE |
3541 #endif
3542                 VM_ENTRY_LOAD_IA32_PAT;
3543         msrs->entry_ctls_high |=
3544                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3545
3546         /* We support free control of debug control loading. */
3547         msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3548
3549         /* cpu-based controls */
3550         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3551                 msrs->procbased_ctls_low,
3552                 msrs->procbased_ctls_high);
3553         msrs->procbased_ctls_low =
3554                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3555         msrs->procbased_ctls_high &=
3556                 CPU_BASED_VIRTUAL_INTR_PENDING |
3557                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3558                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3559                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3560                 CPU_BASED_CR3_STORE_EXITING |
3561 #ifdef CONFIG_X86_64
3562                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3563 #endif
3564                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3565                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3566                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3567                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3568                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3569         /*
3570          * We can allow some features even when not supported by the
3571          * hardware. For example, L1 can specify an MSR bitmap - and we
3572          * can use it to avoid exits to L1 - even when L0 runs L2
3573          * without MSR bitmaps.
3574          */
3575         msrs->procbased_ctls_high |=
3576                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3577                 CPU_BASED_USE_MSR_BITMAPS;
3578
3579         /* We support free control of CR3 access interception. */
3580         msrs->procbased_ctls_low &=
3581                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3582
3583         /*
3584          * secondary cpu-based controls.  Do not include those that
3585          * depend on CPUID bits, they are added later by vmx_cpuid_update.
3586          */
3587         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3588                 msrs->secondary_ctls_low,
3589                 msrs->secondary_ctls_high);
3590         msrs->secondary_ctls_low = 0;
3591         msrs->secondary_ctls_high &=
3592                 SECONDARY_EXEC_DESC |
3593                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3594                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3595                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3596                 SECONDARY_EXEC_WBINVD_EXITING;
3597
3598         /*
3599          * We can emulate "VMCS shadowing," even if the hardware
3600          * doesn't support it.
3601          */
3602         msrs->secondary_ctls_high |=
3603                 SECONDARY_EXEC_SHADOW_VMCS;
3604
3605         if (enable_ept) {
3606                 /* nested EPT: emulate EPT also to L1 */
3607                 msrs->secondary_ctls_high |=
3608                         SECONDARY_EXEC_ENABLE_EPT;
3609                 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3610                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3611                 if (cpu_has_vmx_ept_execute_only())
3612                         msrs->ept_caps |=
3613                                 VMX_EPT_EXECUTE_ONLY_BIT;
3614                 msrs->ept_caps &= vmx_capability.ept;
3615                 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3616                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3617                         VMX_EPT_1GB_PAGE_BIT;
3618                 if (enable_ept_ad_bits) {
3619                         msrs->secondary_ctls_high |=
3620                                 SECONDARY_EXEC_ENABLE_PML;
3621                         msrs->ept_caps |= VMX_EPT_AD_BIT;
3622                 }
3623         }
3624
3625         if (cpu_has_vmx_vmfunc()) {
3626                 msrs->secondary_ctls_high |=
3627                         SECONDARY_EXEC_ENABLE_VMFUNC;
3628                 /*
3629                  * Advertise EPTP switching unconditionally
3630                  * since we emulate it
3631                  */
3632                 if (enable_ept)
3633                         msrs->vmfunc_controls =
3634                                 VMX_VMFUNC_EPTP_SWITCHING;
3635         }
3636
3637         /*
3638          * Old versions of KVM use the single-context version without
3639          * checking for support, so declare that it is supported even
3640          * though it is treated as global context.  The alternative is
3641          * not failing the single-context invvpid, and it is worse.
3642          */
3643         if (enable_vpid) {
3644                 msrs->secondary_ctls_high |=
3645                         SECONDARY_EXEC_ENABLE_VPID;
3646                 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
3647                         VMX_VPID_EXTENT_SUPPORTED_MASK;
3648         }
3649
3650         if (enable_unrestricted_guest)
3651                 msrs->secondary_ctls_high |=
3652                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
3653
3654         if (flexpriority_enabled)
3655                 msrs->secondary_ctls_high |=
3656                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3657
3658         /* miscellaneous data */
3659         rdmsr(MSR_IA32_VMX_MISC,
3660                 msrs->misc_low,
3661                 msrs->misc_high);
3662         msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
3663         msrs->misc_low |=
3664                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
3665                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3666                 VMX_MISC_ACTIVITY_HLT;
3667         msrs->misc_high = 0;
3668
3669         /*
3670          * This MSR reports some information about VMX support. We
3671          * should return information about the VMX we emulate for the
3672          * guest, and the VMCS structure we give it - not about the
3673          * VMX support of the underlying hardware.
3674          */
3675         msrs->basic =
3676                 VMCS12_REVISION |
3677                 VMX_BASIC_TRUE_CTLS |
3678                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3679                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3680
3681         if (cpu_has_vmx_basic_inout())
3682                 msrs->basic |= VMX_BASIC_INOUT;
3683
3684         /*
3685          * These MSRs specify bits which the guest must keep fixed on
3686          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3687          * We picked the standard core2 setting.
3688          */
3689 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3690 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
3691         msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
3692         msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
3693
3694         /* These MSRs specify bits which the guest must keep fixed off. */
3695         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
3696         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
3697
3698         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3699         msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
3700 }
3701
3702 /*
3703  * if fixed0[i] == 1: val[i] must be 1
3704  * if fixed1[i] == 0: val[i] must be 0
3705  */
3706 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3707 {
3708         return ((val & fixed1) | fixed0) == val;
3709 }
3710
3711 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3712 {
3713         return fixed_bits_valid(control, low, high);
3714 }
3715
3716 static inline u64 vmx_control_msr(u32 low, u32 high)
3717 {
3718         return low | ((u64)high << 32);
3719 }
3720
3721 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3722 {
3723         superset &= mask;
3724         subset &= mask;
3725
3726         return (superset | subset) == superset;
3727 }
3728
3729 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3730 {
3731         const u64 feature_and_reserved =
3732                 /* feature (except bit 48; see below) */
3733                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3734                 /* reserved */
3735                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3736         u64 vmx_basic = vmx->nested.msrs.basic;
3737
3738         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3739                 return -EINVAL;
3740
3741         /*
3742          * KVM does not emulate a version of VMX that constrains physical
3743          * addresses of VMX structures (e.g. VMCS) to 32-bits.
3744          */
3745         if (data & BIT_ULL(48))
3746                 return -EINVAL;
3747
3748         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3749             vmx_basic_vmcs_revision_id(data))
3750                 return -EINVAL;
3751
3752         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3753                 return -EINVAL;
3754
3755         vmx->nested.msrs.basic = data;
3756         return 0;
3757 }
3758
3759 static int
3760 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3761 {
3762         u64 supported;
3763         u32 *lowp, *highp;
3764
3765         switch (msr_index) {
3766         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3767                 lowp = &vmx->nested.msrs.pinbased_ctls_low;
3768                 highp = &vmx->nested.msrs.pinbased_ctls_high;
3769                 break;
3770         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3771                 lowp = &vmx->nested.msrs.procbased_ctls_low;
3772                 highp = &vmx->nested.msrs.procbased_ctls_high;
3773                 break;
3774         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3775                 lowp = &vmx->nested.msrs.exit_ctls_low;
3776                 highp = &vmx->nested.msrs.exit_ctls_high;
3777                 break;
3778         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3779                 lowp = &vmx->nested.msrs.entry_ctls_low;
3780                 highp = &vmx->nested.msrs.entry_ctls_high;
3781                 break;
3782         case MSR_IA32_VMX_PROCBASED_CTLS2:
3783                 lowp = &vmx->nested.msrs.secondary_ctls_low;
3784                 highp = &vmx->nested.msrs.secondary_ctls_high;
3785                 break;
3786         default:
3787                 BUG();
3788         }
3789
3790         supported = vmx_control_msr(*lowp, *highp);
3791
3792         /* Check must-be-1 bits are still 1. */
3793         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3794                 return -EINVAL;
3795
3796         /* Check must-be-0 bits are still 0. */
3797         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3798                 return -EINVAL;
3799
3800         *lowp = data;
3801         *highp = data >> 32;
3802         return 0;
3803 }
3804
3805 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3806 {
3807         const u64 feature_and_reserved_bits =
3808                 /* feature */
3809                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3810                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3811                 /* reserved */
3812                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3813         u64 vmx_misc;
3814
3815         vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
3816                                    vmx->nested.msrs.misc_high);
3817
3818         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3819                 return -EINVAL;
3820
3821         if ((vmx->nested.msrs.pinbased_ctls_high &
3822              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3823             vmx_misc_preemption_timer_rate(data) !=
3824             vmx_misc_preemption_timer_rate(vmx_misc))
3825                 return -EINVAL;
3826
3827         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3828                 return -EINVAL;
3829
3830         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3831                 return -EINVAL;
3832
3833         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3834                 return -EINVAL;
3835
3836         vmx->nested.msrs.misc_low = data;
3837         vmx->nested.msrs.misc_high = data >> 32;
3838
3839         /*
3840          * If L1 has read-only VM-exit information fields, use the
3841          * less permissive vmx_vmwrite_bitmap to specify write
3842          * permissions for the shadow VMCS.
3843          */
3844         if (enable_shadow_vmcs && !nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
3845                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
3846
3847         return 0;
3848 }
3849
3850 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3851 {
3852         u64 vmx_ept_vpid_cap;
3853
3854         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
3855                                            vmx->nested.msrs.vpid_caps);
3856
3857         /* Every bit is either reserved or a feature bit. */
3858         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3859                 return -EINVAL;
3860
3861         vmx->nested.msrs.ept_caps = data;
3862         vmx->nested.msrs.vpid_caps = data >> 32;
3863         return 0;
3864 }
3865
3866 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3867 {
3868         u64 *msr;
3869
3870         switch (msr_index) {
3871         case MSR_IA32_VMX_CR0_FIXED0:
3872                 msr = &vmx->nested.msrs.cr0_fixed0;
3873                 break;
3874         case MSR_IA32_VMX_CR4_FIXED0:
3875                 msr = &vmx->nested.msrs.cr4_fixed0;
3876                 break;
3877         default:
3878                 BUG();
3879         }
3880
3881         /*
3882          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3883          * must be 1 in the restored value.
3884          */
3885         if (!is_bitwise_subset(data, *msr, -1ULL))
3886                 return -EINVAL;
3887
3888         *msr = data;
3889         return 0;
3890 }
3891
3892 /*
3893  * Called when userspace is restoring VMX MSRs.
3894  *
3895  * Returns 0 on success, non-0 otherwise.
3896  */
3897 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3898 {
3899         struct vcpu_vmx *vmx = to_vmx(vcpu);
3900
3901         /*
3902          * Don't allow changes to the VMX capability MSRs while the vCPU
3903          * is in VMX operation.
3904          */
3905         if (vmx->nested.vmxon)
3906                 return -EBUSY;
3907
3908         switch (msr_index) {
3909         case MSR_IA32_VMX_BASIC:
3910                 return vmx_restore_vmx_basic(vmx, data);
3911         case MSR_IA32_VMX_PINBASED_CTLS:
3912         case MSR_IA32_VMX_PROCBASED_CTLS:
3913         case MSR_IA32_VMX_EXIT_CTLS:
3914         case MSR_IA32_VMX_ENTRY_CTLS:
3915                 /*
3916                  * The "non-true" VMX capability MSRs are generated from the
3917                  * "true" MSRs, so we do not support restoring them directly.
3918                  *
3919                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3920                  * should restore the "true" MSRs with the must-be-1 bits
3921                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3922                  * DEFAULT SETTINGS".
3923                  */
3924                 return -EINVAL;
3925         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3926         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3927         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3928         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3929         case MSR_IA32_VMX_PROCBASED_CTLS2:
3930                 return vmx_restore_control_msr(vmx, msr_index, data);
3931         case MSR_IA32_VMX_MISC:
3932                 return vmx_restore_vmx_misc(vmx, data);
3933         case MSR_IA32_VMX_CR0_FIXED0:
3934         case MSR_IA32_VMX_CR4_FIXED0:
3935                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3936         case MSR_IA32_VMX_CR0_FIXED1:
3937         case MSR_IA32_VMX_CR4_FIXED1:
3938                 /*
3939                  * These MSRs are generated based on the vCPU's CPUID, so we
3940                  * do not support restoring them directly.
3941                  */
3942                 return -EINVAL;
3943         case MSR_IA32_VMX_EPT_VPID_CAP:
3944                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3945         case MSR_IA32_VMX_VMCS_ENUM:
3946                 vmx->nested.msrs.vmcs_enum = data;
3947                 return 0;
3948         default:
3949                 /*
3950                  * The rest of the VMX capability MSRs do not support restore.
3951                  */
3952                 return -EINVAL;
3953         }
3954 }
3955
3956 /* Returns 0 on success, non-0 otherwise. */
3957 static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
3958 {
3959         switch (msr_index) {
3960         case MSR_IA32_VMX_BASIC:
3961                 *pdata = msrs->basic;
3962                 break;
3963         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3964         case MSR_IA32_VMX_PINBASED_CTLS:
3965                 *pdata = vmx_control_msr(
3966                         msrs->pinbased_ctls_low,
3967                         msrs->pinbased_ctls_high);
3968                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3969                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3970                 break;
3971         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3972         case MSR_IA32_VMX_PROCBASED_CTLS:
3973                 *pdata = vmx_control_msr(
3974                         msrs->procbased_ctls_low,
3975                         msrs->procbased_ctls_high);
3976                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3977                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3978                 break;
3979         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3980         case MSR_IA32_VMX_EXIT_CTLS:
3981                 *pdata = vmx_control_msr(
3982                         msrs->exit_ctls_low,
3983                         msrs->exit_ctls_high);
3984                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3985                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3986                 break;
3987         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3988         case MSR_IA32_VMX_ENTRY_CTLS:
3989                 *pdata = vmx_control_msr(
3990                         msrs->entry_ctls_low,
3991                         msrs->entry_ctls_high);
3992                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3993                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3994                 break;
3995         case MSR_IA32_VMX_MISC:
3996                 *pdata = vmx_control_msr(
3997                         msrs->misc_low,
3998                         msrs->misc_high);
3999                 break;
4000         case MSR_IA32_VMX_CR0_FIXED0:
4001                 *pdata = msrs->cr0_fixed0;
4002                 break;
4003         case MSR_IA32_VMX_CR0_FIXED1:
4004                 *pdata = msrs->cr0_fixed1;
4005                 break;
4006         case MSR_IA32_VMX_CR4_FIXED0:
4007                 *pdata = msrs->cr4_fixed0;
4008                 break;
4009         case MSR_IA32_VMX_CR4_FIXED1:
4010                 *pdata = msrs->cr4_fixed1;
4011                 break;
4012         case MSR_IA32_VMX_VMCS_ENUM:
4013                 *pdata = msrs->vmcs_enum;
4014                 break;
4015         case MSR_IA32_VMX_PROCBASED_CTLS2:
4016                 *pdata = vmx_control_msr(
4017                         msrs->secondary_ctls_low,
4018                         msrs->secondary_ctls_high);
4019                 break;
4020         case MSR_IA32_VMX_EPT_VPID_CAP:
4021                 *pdata = msrs->ept_caps |
4022                         ((u64)msrs->vpid_caps << 32);
4023                 break;
4024         case MSR_IA32_VMX_VMFUNC:
4025                 *pdata = msrs->vmfunc_controls;
4026                 break;
4027         default:
4028                 return 1;
4029         }
4030
4031         return 0;
4032 }
4033
4034 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
4035                                                  uint64_t val)
4036 {
4037         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
4038
4039         return !(val & ~valid_bits);
4040 }
4041
4042 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
4043 {
4044         switch (msr->index) {
4045         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4046                 if (!nested)
4047                         return 1;
4048                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
4049         default:
4050                 return 1;
4051         }
4052
4053         return 0;
4054 }
4055
4056 /*
4057  * Reads an msr value (of 'msr_index') into 'pdata'.
4058  * Returns 0 on success, non-0 otherwise.
4059  * Assumes vcpu_load() was already called.
4060  */
4061 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4062 {
4063         struct vcpu_vmx *vmx = to_vmx(vcpu);
4064         struct shared_msr_entry *msr;
4065
4066         switch (msr_info->index) {
4067 #ifdef CONFIG_X86_64
4068         case MSR_FS_BASE:
4069                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
4070                 break;
4071         case MSR_GS_BASE:
4072                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
4073                 break;
4074         case MSR_KERNEL_GS_BASE:
4075                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
4076                 break;
4077 #endif
4078         case MSR_EFER:
4079                 return kvm_get_msr_common(vcpu, msr_info);
4080         case MSR_IA32_SPEC_CTRL:
4081                 if (!msr_info->host_initiated &&
4082                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4083                         return 1;
4084
4085                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
4086                 break;
4087         case MSR_IA32_ARCH_CAPABILITIES:
4088                 if (!msr_info->host_initiated &&
4089                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4090                         return 1;
4091                 msr_info->data = to_vmx(vcpu)->arch_capabilities;
4092                 break;
4093         case MSR_IA32_SYSENTER_CS:
4094                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
4095                 break;
4096         case MSR_IA32_SYSENTER_EIP:
4097                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
4098                 break;
4099         case MSR_IA32_SYSENTER_ESP:
4100                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
4101                 break;
4102         case MSR_IA32_BNDCFGS:
4103                 if (!kvm_mpx_supported() ||
4104                     (!msr_info->host_initiated &&
4105                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
4106                         return 1;
4107                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
4108                 break;
4109         case MSR_IA32_MCG_EXT_CTL:
4110                 if (!msr_info->host_initiated &&
4111                     !(vmx->msr_ia32_feature_control &
4112                       FEATURE_CONTROL_LMCE))
4113                         return 1;
4114                 msr_info->data = vcpu->arch.mcg_ext_ctl;
4115                 break;
4116         case MSR_IA32_FEATURE_CONTROL:
4117                 msr_info->data = vmx->msr_ia32_feature_control;
4118                 break;
4119         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4120                 if (!nested_vmx_allowed(vcpu))
4121                         return 1;
4122                 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
4123                                        &msr_info->data);
4124         case MSR_IA32_XSS:
4125                 if (!vmx_xsaves_supported())
4126                         return 1;
4127                 msr_info->data = vcpu->arch.ia32_xss;
4128                 break;
4129         case MSR_TSC_AUX:
4130                 if (!msr_info->host_initiated &&
4131                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4132                         return 1;
4133                 /* Otherwise falls through */
4134         default:
4135                 msr = find_msr_entry(vmx, msr_info->index);
4136                 if (msr) {
4137                         msr_info->data = msr->data;
4138                         break;
4139                 }
4140                 return kvm_get_msr_common(vcpu, msr_info);
4141         }
4142
4143         return 0;
4144 }
4145
4146 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
4147
4148 /*
4149  * Writes msr value into into the appropriate "register".
4150  * Returns 0 on success, non-0 otherwise.
4151  * Assumes vcpu_load() was already called.
4152  */
4153 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4154 {
4155         struct vcpu_vmx *vmx = to_vmx(vcpu);
4156         struct shared_msr_entry *msr;
4157         int ret = 0;
4158         u32 msr_index = msr_info->index;
4159         u64 data = msr_info->data;
4160
4161         switch (msr_index) {
4162         case MSR_EFER:
4163                 ret = kvm_set_msr_common(vcpu, msr_info);
4164                 break;
4165 #ifdef CONFIG_X86_64
4166         case MSR_FS_BASE:
4167                 vmx_segment_cache_clear(vmx);
4168                 vmcs_writel(GUEST_FS_BASE, data);
4169                 break;
4170         case MSR_GS_BASE:
4171                 vmx_segment_cache_clear(vmx);
4172                 vmcs_writel(GUEST_GS_BASE, data);
4173                 break;
4174         case MSR_KERNEL_GS_BASE:
4175                 vmx_write_guest_kernel_gs_base(vmx, data);
4176                 break;
4177 #endif
4178         case MSR_IA32_SYSENTER_CS:
4179                 vmcs_write32(GUEST_SYSENTER_CS, data);
4180                 break;
4181         case MSR_IA32_SYSENTER_EIP:
4182                 vmcs_writel(GUEST_SYSENTER_EIP, data);
4183                 break;
4184         case MSR_IA32_SYSENTER_ESP:
4185                 vmcs_writel(GUEST_SYSENTER_ESP, data);
4186                 break;
4187         case MSR_IA32_BNDCFGS:
4188                 if (!kvm_mpx_supported() ||
4189                     (!msr_info->host_initiated &&
4190                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
4191                         return 1;
4192                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4193                     (data & MSR_IA32_BNDCFGS_RSVD))
4194                         return 1;
4195                 vmcs_write64(GUEST_BNDCFGS, data);
4196                 break;
4197         case MSR_IA32_SPEC_CTRL:
4198                 if (!msr_info->host_initiated &&
4199                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4200                         return 1;
4201
4202                 /* The STIBP bit doesn't fault even if it's not advertised */
4203                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4204                         return 1;
4205
4206                 vmx->spec_ctrl = data;
4207
4208                 if (!data)
4209                         break;
4210
4211                 /*
4212                  * For non-nested:
4213                  * When it's written (to non-zero) for the first time, pass
4214                  * it through.
4215                  *
4216                  * For nested:
4217                  * The handling of the MSR bitmap for L2 guests is done in
4218                  * nested_vmx_merge_msr_bitmap. We should not touch the
4219                  * vmcs02.msr_bitmap here since it gets completely overwritten
4220                  * in the merging. We update the vmcs01 here for L1 as well
4221                  * since it will end up touching the MSR anyway now.
4222                  */
4223                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
4224                                               MSR_IA32_SPEC_CTRL,
4225                                               MSR_TYPE_RW);
4226                 break;
4227         case MSR_IA32_PRED_CMD:
4228                 if (!msr_info->host_initiated &&
4229                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4230                         return 1;
4231
4232                 if (data & ~PRED_CMD_IBPB)
4233                         return 1;
4234
4235                 if (!data)
4236                         break;
4237
4238                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4239
4240                 /*
4241                  * For non-nested:
4242                  * When it's written (to non-zero) for the first time, pass
4243                  * it through.
4244                  *
4245                  * For nested:
4246                  * The handling of the MSR bitmap for L2 guests is done in
4247                  * nested_vmx_merge_msr_bitmap. We should not touch the
4248                  * vmcs02.msr_bitmap here since it gets completely overwritten
4249                  * in the merging.
4250                  */
4251                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
4252                                               MSR_TYPE_W);
4253                 break;
4254         case MSR_IA32_ARCH_CAPABILITIES:
4255                 if (!msr_info->host_initiated)
4256                         return 1;
4257                 vmx->arch_capabilities = data;
4258                 break;
4259         case MSR_IA32_CR_PAT:
4260                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4261                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4262                                 return 1;
4263                         vmcs_write64(GUEST_IA32_PAT, data);
4264                         vcpu->arch.pat = data;
4265                         break;
4266                 }
4267                 ret = kvm_set_msr_common(vcpu, msr_info);
4268                 break;
4269         case MSR_IA32_TSC_ADJUST:
4270                 ret = kvm_set_msr_common(vcpu, msr_info);
4271                 break;
4272         case MSR_IA32_MCG_EXT_CTL:
4273                 if ((!msr_info->host_initiated &&
4274                      !(to_vmx(vcpu)->msr_ia32_feature_control &
4275                        FEATURE_CONTROL_LMCE)) ||
4276                     (data & ~MCG_EXT_CTL_LMCE_EN))
4277                         return 1;
4278                 vcpu->arch.mcg_ext_ctl = data;
4279                 break;
4280         case MSR_IA32_FEATURE_CONTROL:
4281                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
4282                     (to_vmx(vcpu)->msr_ia32_feature_control &
4283                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
4284                         return 1;
4285                 vmx->msr_ia32_feature_control = data;
4286                 if (msr_info->host_initiated && data == 0)
4287                         vmx_leave_nested(vcpu);
4288                 break;
4289         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4290                 if (!msr_info->host_initiated)
4291                         return 1; /* they are read-only */
4292                 if (!nested_vmx_allowed(vcpu))
4293                         return 1;
4294                 return vmx_set_vmx_msr(vcpu, msr_index, data);
4295         case MSR_IA32_XSS:
4296                 if (!vmx_xsaves_supported())
4297                         return 1;
4298                 /*
4299                  * The only supported bit as of Skylake is bit 8, but
4300                  * it is not supported on KVM.
4301                  */
4302                 if (data != 0)
4303                         return 1;
4304                 vcpu->arch.ia32_xss = data;
4305                 if (vcpu->arch.ia32_xss != host_xss)
4306                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
4307                                 vcpu->arch.ia32_xss, host_xss, false);
4308                 else
4309                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
4310                 break;
4311         case MSR_TSC_AUX:
4312                 if (!msr_info->host_initiated &&
4313                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4314                         return 1;
4315                 /* Check reserved bit, higher 32 bits should be zero */
4316                 if ((data >> 32) != 0)
4317                         return 1;
4318                 /* Otherwise falls through */
4319         default:
4320                 msr = find_msr_entry(vmx, msr_index);
4321                 if (msr) {
4322                         u64 old_msr_data = msr->data;
4323                         msr->data = data;
4324                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
4325                                 preempt_disable();
4326                                 ret = kvm_set_shared_msr(msr->index, msr->data,
4327                                                          msr->mask);
4328                                 preempt_enable();
4329                                 if (ret)
4330                                         msr->data = old_msr_data;
4331                         }
4332                         break;
4333                 }
4334                 ret = kvm_set_msr_common(vcpu, msr_info);
4335         }
4336
4337         return ret;
4338 }
4339
4340 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
4341 {
4342         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
4343         switch (reg) {
4344         case VCPU_REGS_RSP:
4345                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
4346                 break;
4347         case VCPU_REGS_RIP:
4348                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
4349                 break;
4350         case VCPU_EXREG_PDPTR:
4351                 if (enable_ept)
4352                         ept_save_pdptrs(vcpu);
4353                 break;
4354         default:
4355                 break;
4356         }
4357 }
4358
4359 static __init int cpu_has_kvm_support(void)
4360 {
4361         return cpu_has_vmx();
4362 }
4363
4364 static __init int vmx_disabled_by_bios(void)
4365 {
4366         u64 msr;
4367
4368         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
4369         if (msr & FEATURE_CONTROL_LOCKED) {
4370                 /* launched w/ TXT and VMX disabled */
4371                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4372                         && tboot_enabled())
4373                         return 1;
4374                 /* launched w/o TXT and VMX only enabled w/ TXT */
4375                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4376                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4377                         && !tboot_enabled()) {
4378                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
4379                                 "activate TXT before enabling KVM\n");
4380                         return 1;
4381                 }
4382                 /* launched w/o TXT and VMX disabled */
4383                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4384                         && !tboot_enabled())
4385                         return 1;
4386         }
4387
4388         return 0;
4389 }
4390
4391 static void kvm_cpu_vmxon(u64 addr)
4392 {
4393         cr4_set_bits(X86_CR4_VMXE);
4394         intel_pt_handle_vmx(1);
4395
4396         asm volatile (ASM_VMX_VMXON_RAX
4397                         : : "a"(&addr), "m"(addr)
4398                         : "memory", "cc");
4399 }
4400
4401 static int hardware_enable(void)
4402 {
4403         int cpu = raw_smp_processor_id();
4404         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
4405         u64 old, test_bits;
4406
4407         if (cr4_read_shadow() & X86_CR4_VMXE)
4408                 return -EBUSY;
4409
4410         /*
4411          * This can happen if we hot-added a CPU but failed to allocate
4412          * VP assist page for it.
4413          */
4414         if (static_branch_unlikely(&enable_evmcs) &&
4415             !hv_get_vp_assist_page(cpu))
4416                 return -EFAULT;
4417
4418         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
4419         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
4420         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
4421
4422         /*
4423          * Now we can enable the vmclear operation in kdump
4424          * since the loaded_vmcss_on_cpu list on this cpu
4425          * has been initialized.
4426          *
4427          * Though the cpu is not in VMX operation now, there
4428          * is no problem to enable the vmclear operation
4429          * for the loaded_vmcss_on_cpu list is empty!
4430          */
4431         crash_enable_local_vmclear(cpu);
4432
4433         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
4434
4435         test_bits = FEATURE_CONTROL_LOCKED;
4436         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4437         if (tboot_enabled())
4438                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
4439
4440         if ((old & test_bits) != test_bits) {
4441                 /* enable and lock */
4442                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
4443         }
4444         kvm_cpu_vmxon(phys_addr);
4445         if (enable_ept)
4446                 ept_sync_global();
4447
4448         return 0;
4449 }
4450
4451 static void vmclear_local_loaded_vmcss(void)
4452 {
4453         int cpu = raw_smp_processor_id();
4454         struct loaded_vmcs *v, *n;
4455
4456         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
4457                                  loaded_vmcss_on_cpu_link)
4458                 __loaded_vmcs_clear(v);
4459 }
4460
4461
4462 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
4463  * tricks.
4464  */
4465 static void kvm_cpu_vmxoff(void)
4466 {
4467         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
4468
4469         intel_pt_handle_vmx(0);
4470         cr4_clear_bits(X86_CR4_VMXE);
4471 }
4472
4473 static void hardware_disable(void)
4474 {
4475         vmclear_local_loaded_vmcss();
4476         kvm_cpu_vmxoff();
4477 }
4478
4479 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
4480                                       u32 msr, u32 *result)
4481 {
4482         u32 vmx_msr_low, vmx_msr_high;
4483         u32 ctl = ctl_min | ctl_opt;
4484
4485         rdmsr(msr, vmx_msr_low, vmx_msr_high);
4486
4487         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
4488         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
4489
4490         /* Ensure minimum (required) set of control bits are supported. */
4491         if (ctl_min & ~ctl)
4492                 return -EIO;
4493
4494         *result = ctl;
4495         return 0;
4496 }
4497
4498 static __init bool allow_1_setting(u32 msr, u32 ctl)
4499 {
4500         u32 vmx_msr_low, vmx_msr_high;
4501
4502         rdmsr(msr, vmx_msr_low, vmx_msr_high);
4503         return vmx_msr_high & ctl;
4504 }
4505
4506 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
4507 {
4508         u32 vmx_msr_low, vmx_msr_high;
4509         u32 min, opt, min2, opt2;
4510         u32 _pin_based_exec_control = 0;
4511         u32 _cpu_based_exec_control = 0;
4512         u32 _cpu_based_2nd_exec_control = 0;
4513         u32 _vmexit_control = 0;
4514         u32 _vmentry_control = 0;
4515
4516         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
4517         min = CPU_BASED_HLT_EXITING |
4518 #ifdef CONFIG_X86_64
4519               CPU_BASED_CR8_LOAD_EXITING |
4520               CPU_BASED_CR8_STORE_EXITING |
4521 #endif
4522               CPU_BASED_CR3_LOAD_EXITING |
4523               CPU_BASED_CR3_STORE_EXITING |
4524               CPU_BASED_UNCOND_IO_EXITING |
4525               CPU_BASED_MOV_DR_EXITING |
4526               CPU_BASED_USE_TSC_OFFSETING |
4527               CPU_BASED_MWAIT_EXITING |
4528               CPU_BASED_MONITOR_EXITING |
4529               CPU_BASED_INVLPG_EXITING |
4530               CPU_BASED_RDPMC_EXITING;
4531
4532         opt = CPU_BASED_TPR_SHADOW |
4533               CPU_BASED_USE_MSR_BITMAPS |
4534               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
4535         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
4536                                 &_cpu_based_exec_control) < 0)
4537                 return -EIO;
4538 #ifdef CONFIG_X86_64
4539         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4540                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
4541                                            ~CPU_BASED_CR8_STORE_EXITING;
4542 #endif
4543         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
4544                 min2 = 0;
4545                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4546                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4547                         SECONDARY_EXEC_WBINVD_EXITING |
4548                         SECONDARY_EXEC_ENABLE_VPID |
4549                         SECONDARY_EXEC_ENABLE_EPT |
4550                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
4551                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
4552                         SECONDARY_EXEC_DESC |
4553                         SECONDARY_EXEC_RDTSCP |
4554                         SECONDARY_EXEC_ENABLE_INVPCID |
4555                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4556                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4557                         SECONDARY_EXEC_SHADOW_VMCS |
4558                         SECONDARY_EXEC_XSAVES |
4559                         SECONDARY_EXEC_RDSEED_EXITING |
4560                         SECONDARY_EXEC_RDRAND_EXITING |
4561                         SECONDARY_EXEC_ENABLE_PML |
4562                         SECONDARY_EXEC_TSC_SCALING |
4563                         SECONDARY_EXEC_ENABLE_VMFUNC |
4564                         SECONDARY_EXEC_ENCLS_EXITING;
4565                 if (adjust_vmx_controls(min2, opt2,
4566                                         MSR_IA32_VMX_PROCBASED_CTLS2,
4567                                         &_cpu_based_2nd_exec_control) < 0)
4568                         return -EIO;
4569         }
4570 #ifndef CONFIG_X86_64
4571         if (!(_cpu_based_2nd_exec_control &
4572                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
4573                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
4574 #endif
4575
4576         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4577                 _cpu_based_2nd_exec_control &= ~(
4578                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4579                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4580                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4581
4582         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
4583                 &vmx_capability.ept, &vmx_capability.vpid);
4584
4585         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
4586                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4587                    enabled */
4588                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
4589                                              CPU_BASED_CR3_STORE_EXITING |
4590                                              CPU_BASED_INVLPG_EXITING);
4591         } else if (vmx_capability.ept) {
4592                 vmx_capability.ept = 0;
4593                 pr_warn_once("EPT CAP should not exist if not support "
4594                                 "1-setting enable EPT VM-execution control\n");
4595         }
4596         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
4597                 vmx_capability.vpid) {
4598                 vmx_capability.vpid = 0;
4599                 pr_warn_once("VPID CAP should not exist if not support "
4600                                 "1-setting enable VPID VM-execution control\n");
4601         }
4602
4603         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4604 #ifdef CONFIG_X86_64
4605         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4606 #endif
4607         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4608                 VM_EXIT_CLEAR_BNDCFGS;
4609         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4610                                 &_vmexit_control) < 0)
4611                 return -EIO;
4612
4613         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4614         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4615                  PIN_BASED_VMX_PREEMPTION_TIMER;
4616         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4617                                 &_pin_based_exec_control) < 0)
4618                 return -EIO;
4619
4620         if (cpu_has_broken_vmx_preemption_timer())
4621                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4622         if (!(_cpu_based_2nd_exec_control &
4623                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4624                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4625
4626         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4627         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4628         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4629                                 &_vmentry_control) < 0)
4630                 return -EIO;
4631
4632         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4633
4634         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4635         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4636                 return -EIO;
4637
4638 #ifdef CONFIG_X86_64
4639         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4640         if (vmx_msr_high & (1u<<16))
4641                 return -EIO;
4642 #endif
4643
4644         /* Require Write-Back (WB) memory type for VMCS accesses. */
4645         if (((vmx_msr_high >> 18) & 15) != 6)
4646                 return -EIO;
4647
4648         vmcs_conf->size = vmx_msr_high & 0x1fff;
4649         vmcs_conf->order = get_order(vmcs_conf->size);
4650         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4651
4652         vmcs_conf->revision_id = vmx_msr_low;
4653
4654         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4655         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4656         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4657         vmcs_conf->vmexit_ctrl         = _vmexit_control;
4658         vmcs_conf->vmentry_ctrl        = _vmentry_control;
4659
4660         if (static_branch_unlikely(&enable_evmcs))
4661                 evmcs_sanitize_exec_ctrls(vmcs_conf);
4662
4663         cpu_has_load_ia32_efer =
4664                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4665                                 VM_ENTRY_LOAD_IA32_EFER)
4666                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4667                                    VM_EXIT_LOAD_IA32_EFER);
4668
4669         cpu_has_load_perf_global_ctrl =
4670                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4671                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4672                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4673                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4674
4675         /*
4676          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4677          * but due to errata below it can't be used. Workaround is to use
4678          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4679          *
4680          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4681          *
4682          * AAK155             (model 26)
4683          * AAP115             (model 30)
4684          * AAT100             (model 37)
4685          * BC86,AAY89,BD102   (model 44)
4686          * BA97               (model 46)
4687          *
4688          */
4689         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4690                 switch (boot_cpu_data.x86_model) {
4691                 case 26:
4692                 case 30:
4693                 case 37:
4694                 case 44:
4695                 case 46:
4696                         cpu_has_load_perf_global_ctrl = false;
4697                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4698                                         "does not work properly. Using workaround\n");
4699                         break;
4700                 default:
4701                         break;
4702                 }
4703         }
4704
4705         if (boot_cpu_has(X86_FEATURE_XSAVES))
4706                 rdmsrl(MSR_IA32_XSS, host_xss);
4707
4708         return 0;
4709 }
4710
4711 static struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu)
4712 {
4713         int node = cpu_to_node(cpu);
4714         struct page *pages;
4715         struct vmcs *vmcs;
4716
4717         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4718         if (!pages)
4719                 return NULL;
4720         vmcs = page_address(pages);
4721         memset(vmcs, 0, vmcs_config.size);
4722
4723         /* KVM supports Enlightened VMCS v1 only */
4724         if (static_branch_unlikely(&enable_evmcs))
4725                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
4726         else
4727                 vmcs->hdr.revision_id = vmcs_config.revision_id;
4728
4729         if (shadow)
4730                 vmcs->hdr.shadow_vmcs = 1;
4731         return vmcs;
4732 }
4733
4734 static void free_vmcs(struct vmcs *vmcs)
4735 {
4736         free_pages((unsigned long)vmcs, vmcs_config.order);
4737 }
4738
4739 /*
4740  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4741  */
4742 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4743 {
4744         if (!loaded_vmcs->vmcs)
4745                 return;
4746         loaded_vmcs_clear(loaded_vmcs);
4747         free_vmcs(loaded_vmcs->vmcs);
4748         loaded_vmcs->vmcs = NULL;
4749         if (loaded_vmcs->msr_bitmap)
4750                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4751         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4752 }
4753
4754 static struct vmcs *alloc_vmcs(bool shadow)
4755 {
4756         return alloc_vmcs_cpu(shadow, raw_smp_processor_id());
4757 }
4758
4759 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4760 {
4761         loaded_vmcs->vmcs = alloc_vmcs(false);
4762         if (!loaded_vmcs->vmcs)
4763                 return -ENOMEM;
4764
4765         loaded_vmcs->shadow_vmcs = NULL;
4766         loaded_vmcs_init(loaded_vmcs);
4767
4768         if (cpu_has_vmx_msr_bitmap()) {
4769                 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4770                 if (!loaded_vmcs->msr_bitmap)
4771                         goto out_vmcs;
4772                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4773
4774                 if (IS_ENABLED(CONFIG_HYPERV) &&
4775                     static_branch_unlikely(&enable_evmcs) &&
4776                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
4777                         struct hv_enlightened_vmcs *evmcs =
4778                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
4779
4780                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
4781                 }
4782         }
4783
4784         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
4785
4786         return 0;
4787
4788 out_vmcs:
4789         free_loaded_vmcs(loaded_vmcs);
4790         return -ENOMEM;
4791 }
4792
4793 static void free_kvm_area(void)
4794 {
4795         int cpu;
4796
4797         for_each_possible_cpu(cpu) {
4798                 free_vmcs(per_cpu(vmxarea, cpu));
4799                 per_cpu(vmxarea, cpu) = NULL;
4800         }
4801 }
4802
4803 enum vmcs_field_width {
4804         VMCS_FIELD_WIDTH_U16 = 0,
4805         VMCS_FIELD_WIDTH_U64 = 1,
4806         VMCS_FIELD_WIDTH_U32 = 2,
4807         VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
4808 };
4809
4810 static inline int vmcs_field_width(unsigned long field)
4811 {
4812         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
4813                 return VMCS_FIELD_WIDTH_U32;
4814         return (field >> 13) & 0x3 ;
4815 }
4816
4817 static inline int vmcs_field_readonly(unsigned long field)
4818 {
4819         return (((field >> 10) & 0x3) == 1);
4820 }
4821
4822 static void init_vmcs_shadow_fields(void)
4823 {
4824         int i, j;
4825
4826         for (i = j = 0; i < max_shadow_read_only_fields; i++) {
4827                 u16 field = shadow_read_only_fields[i];
4828                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4829                     (i + 1 == max_shadow_read_only_fields ||
4830                      shadow_read_only_fields[i + 1] != field + 1))
4831                         pr_err("Missing field from shadow_read_only_field %x\n",
4832                                field + 1);
4833
4834                 clear_bit(field, vmx_vmread_bitmap);
4835 #ifdef CONFIG_X86_64
4836                 if (field & 1)
4837                         continue;
4838 #endif
4839                 if (j < i)
4840                         shadow_read_only_fields[j] = field;
4841                 j++;
4842         }
4843         max_shadow_read_only_fields = j;
4844
4845         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4846                 u16 field = shadow_read_write_fields[i];
4847                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4848                     (i + 1 == max_shadow_read_write_fields ||
4849                      shadow_read_write_fields[i + 1] != field + 1))
4850                         pr_err("Missing field from shadow_read_write_field %x\n",
4851                                field + 1);
4852
4853                 /*
4854                  * PML and the preemption timer can be emulated, but the
4855                  * processor cannot vmwrite to fields that don't exist
4856                  * on bare metal.
4857                  */
4858                 switch (field) {
4859                 case GUEST_PML_INDEX:
4860                         if (!cpu_has_vmx_pml())
4861                                 continue;
4862                         break;
4863                 case VMX_PREEMPTION_TIMER_VALUE:
4864                         if (!cpu_has_vmx_preemption_timer())
4865                                 continue;
4866                         break;
4867                 case GUEST_INTR_STATUS:
4868                         if (!cpu_has_vmx_apicv())
4869                                 continue;
4870                         break;
4871                 default:
4872                         break;
4873                 }
4874
4875                 clear_bit(field, vmx_vmwrite_bitmap);
4876                 clear_bit(field, vmx_vmread_bitmap);
4877 #ifdef CONFIG_X86_64
4878                 if (field & 1)
4879                         continue;
4880 #endif
4881                 if (j < i)
4882                         shadow_read_write_fields[j] = field;
4883                 j++;
4884         }
4885         max_shadow_read_write_fields = j;
4886 }
4887
4888 static __init int alloc_kvm_area(void)
4889 {
4890         int cpu;
4891
4892         for_each_possible_cpu(cpu) {
4893                 struct vmcs *vmcs;
4894
4895                 vmcs = alloc_vmcs_cpu(false, cpu);
4896                 if (!vmcs) {
4897                         free_kvm_area();
4898                         return -ENOMEM;
4899                 }
4900
4901                 /*
4902                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
4903                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
4904                  * revision_id reported by MSR_IA32_VMX_BASIC.
4905                  *
4906                  * However, even though not explictly documented by
4907                  * TLFS, VMXArea passed as VMXON argument should
4908                  * still be marked with revision_id reported by
4909                  * physical CPU.
4910                  */
4911                 if (static_branch_unlikely(&enable_evmcs))
4912                         vmcs->hdr.revision_id = vmcs_config.revision_id;
4913
4914                 per_cpu(vmxarea, cpu) = vmcs;
4915         }
4916         return 0;
4917 }
4918
4919 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4920                 struct kvm_segment *save)
4921 {
4922         if (!emulate_invalid_guest_state) {
4923                 /*
4924                  * CS and SS RPL should be equal during guest entry according
4925                  * to VMX spec, but in reality it is not always so. Since vcpu
4926                  * is in the middle of the transition from real mode to
4927                  * protected mode it is safe to assume that RPL 0 is a good
4928                  * default value.
4929                  */
4930                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4931                         save->selector &= ~SEGMENT_RPL_MASK;
4932                 save->dpl = save->selector & SEGMENT_RPL_MASK;
4933                 save->s = 1;
4934         }
4935         vmx_set_segment(vcpu, save, seg);
4936 }
4937
4938 static void enter_pmode(struct kvm_vcpu *vcpu)
4939 {
4940         unsigned long flags;
4941         struct vcpu_vmx *vmx = to_vmx(vcpu);
4942
4943         /*
4944          * Update real mode segment cache. It may be not up-to-date if sement
4945          * register was written while vcpu was in a guest mode.
4946          */
4947         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4948         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4949         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4950         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4951         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4952         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4953
4954         vmx->rmode.vm86_active = 0;
4955
4956         vmx_segment_cache_clear(vmx);
4957
4958         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4959
4960         flags = vmcs_readl(GUEST_RFLAGS);
4961         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4962         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4963         vmcs_writel(GUEST_RFLAGS, flags);
4964
4965         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4966                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4967
4968         update_exception_bitmap(vcpu);
4969
4970         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4971         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4972         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4973         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4974         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4975         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4976 }
4977
4978 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4979 {
4980         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4981         struct kvm_segment var = *save;
4982
4983         var.dpl = 0x3;
4984         if (seg == VCPU_SREG_CS)
4985                 var.type = 0x3;
4986
4987         if (!emulate_invalid_guest_state) {
4988                 var.selector = var.base >> 4;
4989                 var.base = var.base & 0xffff0;
4990                 var.limit = 0xffff;
4991                 var.g = 0;
4992                 var.db = 0;
4993                 var.present = 1;
4994                 var.s = 1;
4995                 var.l = 0;
4996                 var.unusable = 0;
4997                 var.type = 0x3;
4998                 var.avl = 0;
4999                 if (save->base & 0xf)
5000                         printk_once(KERN_WARNING "kvm: segment base is not "
5001                                         "paragraph aligned when entering "
5002                                         "protected mode (seg=%d)", seg);
5003         }
5004
5005         vmcs_write16(sf->selector, var.selector);
5006         vmcs_writel(sf->base, var.base);
5007         vmcs_write32(sf->limit, var.limit);
5008         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
5009 }
5010
5011 static void enter_rmode(struct kvm_vcpu *vcpu)
5012 {
5013         unsigned long flags;
5014         struct vcpu_vmx *vmx = to_vmx(vcpu);
5015         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
5016
5017         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
5018         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
5019         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
5020         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
5021         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
5022         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
5023         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
5024
5025         vmx->rmode.vm86_active = 1;
5026
5027         /*
5028          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
5029          * vcpu. Warn the user that an update is overdue.
5030          */
5031         if (!kvm_vmx->tss_addr)
5032                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
5033                              "called before entering vcpu\n");
5034
5035         vmx_segment_cache_clear(vmx);
5036
5037         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
5038         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
5039         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5040
5041         flags = vmcs_readl(GUEST_RFLAGS);
5042         vmx->rmode.save_rflags = flags;
5043
5044         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
5045
5046         vmcs_writel(GUEST_RFLAGS, flags);
5047         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
5048         update_exception_bitmap(vcpu);
5049
5050         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
5051         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
5052         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
5053         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
5054         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
5055         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
5056
5057         kvm_mmu_reset_context(vcpu);
5058 }
5059
5060 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
5061 {
5062         struct vcpu_vmx *vmx = to_vmx(vcpu);
5063         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
5064
5065         if (!msr)
5066                 return;
5067
5068         vcpu->arch.efer = efer;
5069         if (efer & EFER_LMA) {
5070                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5071                 msr->data = efer;
5072         } else {
5073                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5074
5075                 msr->data = efer & ~EFER_LME;
5076         }
5077         setup_msrs(vmx);
5078 }
5079
5080 #ifdef CONFIG_X86_64
5081
5082 static void enter_lmode(struct kvm_vcpu *vcpu)
5083 {
5084         u32 guest_tr_ar;
5085
5086         vmx_segment_cache_clear(to_vmx(vcpu));
5087
5088         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
5089         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
5090                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
5091                                      __func__);
5092                 vmcs_write32(GUEST_TR_AR_BYTES,
5093                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
5094                              | VMX_AR_TYPE_BUSY_64_TSS);
5095         }
5096         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
5097 }
5098
5099 static void exit_lmode(struct kvm_vcpu *vcpu)
5100 {
5101         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5102         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
5103 }
5104
5105 #endif
5106
5107 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
5108                                 bool invalidate_gpa)
5109 {
5110         if (enable_ept && (invalidate_gpa || !enable_vpid)) {
5111                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
5112                         return;
5113                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
5114         } else {
5115                 vpid_sync_context(vpid);
5116         }
5117 }
5118
5119 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5120 {
5121         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
5122 }
5123
5124 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
5125 {
5126         int vpid = to_vmx(vcpu)->vpid;
5127
5128         if (!vpid_sync_vcpu_addr(vpid, addr))
5129                 vpid_sync_context(vpid);
5130
5131         /*
5132          * If VPIDs are not supported or enabled, then the above is a no-op.
5133          * But we don't really need a TLB flush in that case anyway, because
5134          * each VM entry/exit includes an implicit flush when VPID is 0.
5135          */
5136 }
5137
5138 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
5139 {
5140         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
5141
5142         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
5143         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
5144 }
5145
5146 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
5147 {
5148         if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
5149                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
5150         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5151 }
5152
5153 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
5154 {
5155         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
5156
5157         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
5158         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
5159 }
5160
5161 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
5162 {
5163         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
5164
5165         if (!test_bit(VCPU_EXREG_PDPTR,
5166                       (unsigned long *)&vcpu->arch.regs_dirty))
5167                 return;
5168
5169         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
5170                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
5171                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
5172                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
5173                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
5174         }
5175 }
5176
5177 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
5178 {
5179         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
5180
5181         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
5182                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
5183                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
5184                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
5185                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
5186         }
5187
5188         __set_bit(VCPU_EXREG_PDPTR,
5189                   (unsigned long *)&vcpu->arch.regs_avail);
5190         __set_bit(VCPU_EXREG_PDPTR,
5191                   (unsigned long *)&vcpu->arch.regs_dirty);
5192 }
5193
5194 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5195 {
5196         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
5197         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
5198         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5199
5200         if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
5201                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5202             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5203                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5204
5205         return fixed_bits_valid(val, fixed0, fixed1);
5206 }
5207
5208 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5209 {
5210         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
5211         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
5212
5213         return fixed_bits_valid(val, fixed0, fixed1);
5214 }
5215
5216 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
5217 {
5218         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
5219         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
5220
5221         return fixed_bits_valid(val, fixed0, fixed1);
5222 }
5223
5224 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
5225 #define nested_guest_cr4_valid  nested_cr4_valid
5226 #define nested_host_cr4_valid   nested_cr4_valid
5227
5228 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
5229
5230 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
5231                                         unsigned long cr0,
5232                                         struct kvm_vcpu *vcpu)
5233 {
5234         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
5235                 vmx_decache_cr3(vcpu);
5236         if (!(cr0 & X86_CR0_PG)) {
5237                 /* From paging/starting to nonpaging */
5238                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
5239                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
5240                              (CPU_BASED_CR3_LOAD_EXITING |
5241                               CPU_BASED_CR3_STORE_EXITING));
5242                 vcpu->arch.cr0 = cr0;
5243                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
5244         } else if (!is_paging(vcpu)) {
5245                 /* From nonpaging to paging */
5246                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
5247                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
5248                              ~(CPU_BASED_CR3_LOAD_EXITING |
5249                                CPU_BASED_CR3_STORE_EXITING));
5250                 vcpu->arch.cr0 = cr0;
5251                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
5252         }
5253
5254         if (!(cr0 & X86_CR0_WP))
5255                 *hw_cr0 &= ~X86_CR0_WP;
5256 }
5257
5258 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
5259 {
5260         struct vcpu_vmx *vmx = to_vmx(vcpu);
5261         unsigned long hw_cr0;
5262
5263         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
5264         if (enable_unrestricted_guest)
5265                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
5266         else {
5267                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
5268
5269                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
5270                         enter_pmode(vcpu);
5271
5272                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
5273                         enter_rmode(vcpu);
5274         }
5275
5276 #ifdef CONFIG_X86_64
5277         if (vcpu->arch.efer & EFER_LME) {
5278                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
5279                         enter_lmode(vcpu);
5280                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
5281                         exit_lmode(vcpu);
5282         }
5283 #endif
5284
5285         if (enable_ept && !enable_unrestricted_guest)
5286                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
5287
5288         vmcs_writel(CR0_READ_SHADOW, cr0);
5289         vmcs_writel(GUEST_CR0, hw_cr0);
5290         vcpu->arch.cr0 = cr0;
5291
5292         /* depends on vcpu->arch.cr0 to be set to a new value */
5293         vmx->emulation_required = emulation_required(vcpu);
5294 }
5295
5296 static int get_ept_level(struct kvm_vcpu *vcpu)
5297 {
5298         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
5299                 return 5;
5300         return 4;
5301 }
5302
5303 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
5304 {
5305         u64 eptp = VMX_EPTP_MT_WB;
5306
5307         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
5308
5309         if (enable_ept_ad_bits &&
5310             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
5311                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
5312         eptp |= (root_hpa & PAGE_MASK);
5313
5314         return eptp;
5315 }
5316
5317 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
5318 {
5319         struct kvm *kvm = vcpu->kvm;
5320         unsigned long guest_cr3;
5321         u64 eptp;
5322
5323         guest_cr3 = cr3;
5324         if (enable_ept) {
5325                 eptp = construct_eptp(vcpu, cr3);
5326                 vmcs_write64(EPT_POINTER, eptp);
5327
5328                 if (kvm_x86_ops->tlb_remote_flush) {
5329                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
5330                         to_vmx(vcpu)->ept_pointer = eptp;
5331                         to_kvm_vmx(kvm)->ept_pointers_match
5332                                 = EPT_POINTERS_CHECK;
5333                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
5334                 }
5335
5336                 if (enable_unrestricted_guest || is_paging(vcpu) ||
5337                     is_guest_mode(vcpu))
5338                         guest_cr3 = kvm_read_cr3(vcpu);
5339                 else
5340                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
5341                 ept_load_pdptrs(vcpu);
5342         }
5343
5344         vmcs_writel(GUEST_CR3, guest_cr3);
5345 }
5346
5347 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
5348 {
5349         /*
5350          * Pass through host's Machine Check Enable value to hw_cr4, which
5351          * is in force while we are in guest mode.  Do not let guests control
5352          * this bit, even if host CR4.MCE == 0.
5353          */
5354         unsigned long hw_cr4;
5355
5356         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
5357         if (enable_unrestricted_guest)
5358                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
5359         else if (to_vmx(vcpu)->rmode.vm86_active)
5360                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
5361         else
5362                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
5363
5364         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
5365                 if (cr4 & X86_CR4_UMIP) {
5366                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5367                                 SECONDARY_EXEC_DESC);
5368                         hw_cr4 &= ~X86_CR4_UMIP;
5369                 } else if (!is_guest_mode(vcpu) ||
5370                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
5371                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5372                                         SECONDARY_EXEC_DESC);
5373         }
5374
5375         if (cr4 & X86_CR4_VMXE) {
5376                 /*
5377                  * To use VMXON (and later other VMX instructions), a guest
5378                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
5379                  * So basically the check on whether to allow nested VMX
5380                  * is here.  We operate under the default treatment of SMM,
5381                  * so VMX cannot be enabled under SMM.
5382                  */
5383                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5384                         return 1;
5385         }
5386
5387         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5388                 return 1;
5389
5390         vcpu->arch.cr4 = cr4;
5391
5392         if (!enable_unrestricted_guest) {
5393                 if (enable_ept) {
5394                         if (!is_paging(vcpu)) {
5395                                 hw_cr4 &= ~X86_CR4_PAE;
5396                                 hw_cr4 |= X86_CR4_PSE;
5397                         } else if (!(cr4 & X86_CR4_PAE)) {
5398                                 hw_cr4 &= ~X86_CR4_PAE;
5399                         }
5400                 }
5401
5402                 /*
5403                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
5404                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
5405                  * to be manually disabled when guest switches to non-paging
5406                  * mode.
5407                  *
5408                  * If !enable_unrestricted_guest, the CPU is always running
5409                  * with CR0.PG=1 and CR4 needs to be modified.
5410                  * If enable_unrestricted_guest, the CPU automatically
5411                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
5412                  */
5413                 if (!is_paging(vcpu))
5414                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
5415         }
5416
5417         vmcs_writel(CR4_READ_SHADOW, cr4);
5418         vmcs_writel(GUEST_CR4, hw_cr4);
5419         return 0;
5420 }
5421
5422 static void vmx_get_segment(struct kvm_vcpu *vcpu,
5423                             struct kvm_segment *var, int seg)
5424 {
5425         struct vcpu_vmx *vmx = to_vmx(vcpu);
5426         u32 ar;
5427
5428         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5429                 *var = vmx->rmode.segs[seg];
5430                 if (seg == VCPU_SREG_TR
5431                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
5432                         return;
5433                 var->base = vmx_read_guest_seg_base(vmx, seg);
5434                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5435                 return;
5436         }
5437         var->base = vmx_read_guest_seg_base(vmx, seg);
5438         var->limit = vmx_read_guest_seg_limit(vmx, seg);
5439         var->selector = vmx_read_guest_seg_selector(vmx, seg);
5440         ar = vmx_read_guest_seg_ar(vmx, seg);
5441         var->unusable = (ar >> 16) & 1;
5442         var->type = ar & 15;
5443         var->s = (ar >> 4) & 1;
5444         var->dpl = (ar >> 5) & 3;
5445         /*
5446          * Some userspaces do not preserve unusable property. Since usable
5447          * segment has to be present according to VMX spec we can use present
5448          * property to amend userspace bug by making unusable segment always
5449          * nonpresent. vmx_segment_access_rights() already marks nonpresent
5450          * segment as unusable.
5451          */
5452         var->present = !var->unusable;
5453         var->avl = (ar >> 12) & 1;
5454         var->l = (ar >> 13) & 1;
5455         var->db = (ar >> 14) & 1;
5456         var->g = (ar >> 15) & 1;
5457 }
5458
5459 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
5460 {
5461         struct kvm_segment s;
5462
5463         if (to_vmx(vcpu)->rmode.vm86_active) {
5464                 vmx_get_segment(vcpu, &s, seg);
5465                 return s.base;
5466         }
5467         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
5468 }
5469
5470 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
5471 {
5472         struct vcpu_vmx *vmx = to_vmx(vcpu);
5473
5474         if (unlikely(vmx->rmode.vm86_active))
5475                 return 0;
5476         else {
5477                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
5478                 return VMX_AR_DPL(ar);
5479         }
5480 }
5481
5482 static u32 vmx_segment_access_rights(struct kvm_segment *var)
5483 {
5484         u32 ar;
5485
5486         if (var->unusable || !var->present)
5487                 ar = 1 << 16;
5488         else {
5489                 ar = var->type & 15;
5490                 ar |= (var->s & 1) << 4;
5491                 ar |= (var->dpl & 3) << 5;
5492                 ar |= (var->present & 1) << 7;
5493                 ar |= (var->avl & 1) << 12;
5494                 ar |= (var->l & 1) << 13;
5495                 ar |= (var->db & 1) << 14;
5496                 ar |= (var->g & 1) << 15;
5497         }
5498
5499         return ar;
5500 }
5501
5502 static void vmx_set_segment(struct kvm_vcpu *vcpu,
5503                             struct kvm_segment *var, int seg)
5504 {
5505         struct vcpu_vmx *vmx = to_vmx(vcpu);
5506         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5507
5508         vmx_segment_cache_clear(vmx);
5509
5510         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5511                 vmx->rmode.segs[seg] = *var;
5512                 if (seg == VCPU_SREG_TR)
5513                         vmcs_write16(sf->selector, var->selector);
5514                 else if (var->s)
5515                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
5516                 goto out;
5517         }
5518
5519         vmcs_writel(sf->base, var->base);
5520         vmcs_write32(sf->limit, var->limit);
5521         vmcs_write16(sf->selector, var->selector);
5522
5523         /*
5524          *   Fix the "Accessed" bit in AR field of segment registers for older
5525          * qemu binaries.
5526          *   IA32 arch specifies that at the time of processor reset the
5527          * "Accessed" bit in the AR field of segment registers is 1. And qemu
5528          * is setting it to 0 in the userland code. This causes invalid guest
5529          * state vmexit when "unrestricted guest" mode is turned on.
5530          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
5531          * tree. Newer qemu binaries with that qemu fix would not need this
5532          * kvm hack.
5533          */
5534         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
5535                 var->type |= 0x1; /* Accessed */
5536
5537         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
5538
5539 out:
5540         vmx->emulation_required = emulation_required(vcpu);
5541 }
5542
5543 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5544 {
5545         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
5546
5547         *db = (ar >> 14) & 1;
5548         *l = (ar >> 13) & 1;
5549 }
5550
5551 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5552 {
5553         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
5554         dt->address = vmcs_readl(GUEST_IDTR_BASE);
5555 }
5556
5557 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5558 {
5559         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
5560         vmcs_writel(GUEST_IDTR_BASE, dt->address);
5561 }
5562
5563 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5564 {
5565         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
5566         dt->address = vmcs_readl(GUEST_GDTR_BASE);
5567 }
5568
5569 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5570 {
5571         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
5572         vmcs_writel(GUEST_GDTR_BASE, dt->address);
5573 }
5574
5575 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
5576 {
5577         struct kvm_segment var;
5578         u32 ar;
5579
5580         vmx_get_segment(vcpu, &var, seg);
5581         var.dpl = 0x3;
5582         if (seg == VCPU_SREG_CS)
5583                 var.type = 0x3;
5584         ar = vmx_segment_access_rights(&var);
5585
5586         if (var.base != (var.selector << 4))
5587                 return false;
5588         if (var.limit != 0xffff)
5589                 return false;
5590         if (ar != 0xf3)
5591                 return false;
5592
5593         return true;
5594 }
5595
5596 static bool code_segment_valid(struct kvm_vcpu *vcpu)
5597 {
5598         struct kvm_segment cs;
5599         unsigned int cs_rpl;
5600
5601         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5602         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
5603
5604         if (cs.unusable)
5605                 return false;
5606         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
5607                 return false;
5608         if (!cs.s)
5609                 return false;
5610         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
5611                 if (cs.dpl > cs_rpl)
5612                         return false;
5613         } else {
5614                 if (cs.dpl != cs_rpl)
5615                         return false;
5616         }
5617         if (!cs.present)
5618                 return false;
5619
5620         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5621         return true;
5622 }
5623
5624 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
5625 {
5626         struct kvm_segment ss;
5627         unsigned int ss_rpl;
5628
5629         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5630         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
5631
5632         if (ss.unusable)
5633                 return true;
5634         if (ss.type != 3 && ss.type != 7)
5635                 return false;
5636         if (!ss.s)
5637                 return false;
5638         if (ss.dpl != ss_rpl) /* DPL != RPL */
5639                 return false;
5640         if (!ss.present)
5641                 return false;
5642
5643         return true;
5644 }
5645
5646 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
5647 {
5648         struct kvm_segment var;
5649         unsigned int rpl;
5650
5651         vmx_get_segment(vcpu, &var, seg);
5652         rpl = var.selector & SEGMENT_RPL_MASK;
5653
5654         if (var.unusable)
5655                 return true;
5656         if (!var.s)
5657                 return false;
5658         if (!var.present)
5659                 return false;
5660         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
5661                 if (var.dpl < rpl) /* DPL < RPL */
5662                         return false;
5663         }
5664
5665         /* TODO: Add other members to kvm_segment_field to allow checking for other access
5666          * rights flags
5667          */
5668         return true;
5669 }
5670
5671 static bool tr_valid(struct kvm_vcpu *vcpu)
5672 {
5673         struct kvm_segment tr;
5674
5675         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
5676
5677         if (tr.unusable)
5678                 return false;
5679         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
5680                 return false;
5681         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
5682                 return false;
5683         if (!tr.present)
5684                 return false;
5685
5686         return true;
5687 }
5688
5689 static bool ldtr_valid(struct kvm_vcpu *vcpu)
5690 {
5691         struct kvm_segment ldtr;
5692
5693         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
5694
5695         if (ldtr.unusable)
5696                 return true;
5697         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
5698                 return false;
5699         if (ldtr.type != 2)
5700                 return false;
5701         if (!ldtr.present)
5702                 return false;
5703
5704         return true;
5705 }
5706
5707 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5708 {
5709         struct kvm_segment cs, ss;
5710
5711         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5712         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5713
5714         return ((cs.selector & SEGMENT_RPL_MASK) ==
5715                  (ss.selector & SEGMENT_RPL_MASK));
5716 }
5717
5718 /*
5719  * Check if guest state is valid. Returns true if valid, false if
5720  * not.
5721  * We assume that registers are always usable
5722  */
5723 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5724 {
5725         if (enable_unrestricted_guest)
5726                 return true;
5727
5728         /* real mode guest state checks */
5729         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5730                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5731                         return false;
5732                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5733                         return false;
5734                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5735                         return false;
5736                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5737                         return false;
5738                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5739                         return false;
5740                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5741                         return false;
5742         } else {
5743         /* protected mode guest state checks */
5744                 if (!cs_ss_rpl_check(vcpu))
5745                         return false;
5746                 if (!code_segment_valid(vcpu))
5747                         return false;
5748                 if (!stack_segment_valid(vcpu))
5749                         return false;
5750                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5751                         return false;
5752                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5753                         return false;
5754                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5755                         return false;
5756                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5757                         return false;
5758                 if (!tr_valid(vcpu))
5759                         return false;
5760                 if (!ldtr_valid(vcpu))
5761                         return false;
5762         }
5763         /* TODO:
5764          * - Add checks on RIP
5765          * - Add checks on RFLAGS
5766          */
5767
5768         return true;
5769 }
5770
5771 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5772 {
5773         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5774 }
5775
5776 static int init_rmode_tss(struct kvm *kvm)
5777 {
5778         gfn_t fn;
5779         u16 data = 0;
5780         int idx, r;
5781
5782         idx = srcu_read_lock(&kvm->srcu);
5783         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
5784         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5785         if (r < 0)
5786                 goto out;
5787         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5788         r = kvm_write_guest_page(kvm, fn++, &data,
5789                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
5790         if (r < 0)
5791                 goto out;
5792         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5793         if (r < 0)
5794                 goto out;
5795         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5796         if (r < 0)
5797                 goto out;
5798         data = ~0;
5799         r = kvm_write_guest_page(kvm, fn, &data,
5800                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5801                                  sizeof(u8));
5802 out:
5803         srcu_read_unlock(&kvm->srcu, idx);
5804         return r;
5805 }
5806
5807 static int init_rmode_identity_map(struct kvm *kvm)
5808 {
5809         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
5810         int i, idx, r = 0;
5811         kvm_pfn_t identity_map_pfn;
5812         u32 tmp;
5813
5814         /* Protect kvm_vmx->ept_identity_pagetable_done. */
5815         mutex_lock(&kvm->slots_lock);
5816
5817         if (likely(kvm_vmx->ept_identity_pagetable_done))
5818                 goto out2;
5819
5820         if (!kvm_vmx->ept_identity_map_addr)
5821                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5822         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
5823
5824         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5825                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
5826         if (r < 0)
5827                 goto out2;
5828
5829         idx = srcu_read_lock(&kvm->srcu);
5830         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5831         if (r < 0)
5832                 goto out;
5833         /* Set up identity-mapping pagetable for EPT in real mode */
5834         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5835                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5836                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5837                 r = kvm_write_guest_page(kvm, identity_map_pfn,
5838                                 &tmp, i * sizeof(tmp), sizeof(tmp));
5839                 if (r < 0)
5840                         goto out;
5841         }
5842         kvm_vmx->ept_identity_pagetable_done = true;
5843
5844 out:
5845         srcu_read_unlock(&kvm->srcu, idx);
5846
5847 out2:
5848         mutex_unlock(&kvm->slots_lock);
5849         return r;
5850 }
5851
5852 static void seg_setup(int seg)
5853 {
5854         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5855         unsigned int ar;
5856
5857         vmcs_write16(sf->selector, 0);
5858         vmcs_writel(sf->base, 0);
5859         vmcs_write32(sf->limit, 0xffff);
5860         ar = 0x93;
5861         if (seg == VCPU_SREG_CS)
5862                 ar |= 0x08; /* code segment */
5863
5864         vmcs_write32(sf->ar_bytes, ar);
5865 }
5866
5867 static int alloc_apic_access_page(struct kvm *kvm)
5868 {
5869         struct page *page;
5870         int r = 0;
5871
5872         mutex_lock(&kvm->slots_lock);
5873         if (kvm->arch.apic_access_page_done)
5874                 goto out;
5875         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5876                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5877         if (r)
5878                 goto out;
5879
5880         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5881         if (is_error_page(page)) {
5882                 r = -EFAULT;
5883                 goto out;
5884         }
5885
5886         /*
5887          * Do not pin the page in memory, so that memory hot-unplug
5888          * is able to migrate it.
5889          */
5890         put_page(page);
5891         kvm->arch.apic_access_page_done = true;
5892 out:
5893         mutex_unlock(&kvm->slots_lock);
5894         return r;
5895 }
5896
5897 static int allocate_vpid(void)
5898 {
5899         int vpid;
5900
5901         if (!enable_vpid)
5902                 return 0;
5903         spin_lock(&vmx_vpid_lock);
5904         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5905         if (vpid < VMX_NR_VPIDS)
5906                 __set_bit(vpid, vmx_vpid_bitmap);
5907         else
5908                 vpid = 0;
5909         spin_unlock(&vmx_vpid_lock);
5910         return vpid;
5911 }
5912
5913 static void free_vpid(int vpid)
5914 {
5915         if (!enable_vpid || vpid == 0)
5916                 return;
5917         spin_lock(&vmx_vpid_lock);
5918         __clear_bit(vpid, vmx_vpid_bitmap);
5919         spin_unlock(&vmx_vpid_lock);
5920 }
5921
5922 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5923                                                           u32 msr, int type)
5924 {
5925         int f = sizeof(unsigned long);
5926
5927         if (!cpu_has_vmx_msr_bitmap())
5928                 return;
5929
5930         if (static_branch_unlikely(&enable_evmcs))
5931                 evmcs_touch_msr_bitmap();
5932
5933         /*
5934          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5935          * have the write-low and read-high bitmap offsets the wrong way round.
5936          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5937          */
5938         if (msr <= 0x1fff) {
5939                 if (type & MSR_TYPE_R)
5940                         /* read-low */
5941                         __clear_bit(msr, msr_bitmap + 0x000 / f);
5942
5943                 if (type & MSR_TYPE_W)
5944                         /* write-low */
5945                         __clear_bit(msr, msr_bitmap + 0x800 / f);
5946
5947         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5948                 msr &= 0x1fff;
5949                 if (type & MSR_TYPE_R)
5950                         /* read-high */
5951                         __clear_bit(msr, msr_bitmap + 0x400 / f);
5952
5953                 if (type & MSR_TYPE_W)
5954                         /* write-high */
5955                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
5956
5957         }
5958 }
5959
5960 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5961                                                          u32 msr, int type)
5962 {
5963         int f = sizeof(unsigned long);
5964
5965         if (!cpu_has_vmx_msr_bitmap())
5966                 return;
5967
5968         if (static_branch_unlikely(&enable_evmcs))
5969                 evmcs_touch_msr_bitmap();
5970
5971         /*
5972          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5973          * have the write-low and read-high bitmap offsets the wrong way round.
5974          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5975          */
5976         if (msr <= 0x1fff) {
5977                 if (type & MSR_TYPE_R)
5978                         /* read-low */
5979                         __set_bit(msr, msr_bitmap + 0x000 / f);
5980
5981                 if (type & MSR_TYPE_W)
5982                         /* write-low */
5983                         __set_bit(msr, msr_bitmap + 0x800 / f);
5984
5985         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5986                 msr &= 0x1fff;
5987                 if (type & MSR_TYPE_R)
5988                         /* read-high */
5989                         __set_bit(msr, msr_bitmap + 0x400 / f);
5990
5991                 if (type & MSR_TYPE_W)
5992                         /* write-high */
5993                         __set_bit(msr, msr_bitmap + 0xc00 / f);
5994
5995         }
5996 }
5997
5998 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5999                                                       u32 msr, int type, bool value)
6000 {
6001         if (value)
6002                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
6003         else
6004                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
6005 }
6006
6007 /*
6008  * If a msr is allowed by L0, we should check whether it is allowed by L1.
6009  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
6010  */
6011 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
6012                                                unsigned long *msr_bitmap_nested,
6013                                                u32 msr, int type)
6014 {
6015         int f = sizeof(unsigned long);
6016
6017         /*
6018          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
6019          * have the write-low and read-high bitmap offsets the wrong way round.
6020          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
6021          */
6022         if (msr <= 0x1fff) {
6023                 if (type & MSR_TYPE_R &&
6024                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
6025                         /* read-low */
6026                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
6027
6028                 if (type & MSR_TYPE_W &&
6029                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
6030                         /* write-low */
6031                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
6032
6033         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
6034                 msr &= 0x1fff;
6035                 if (type & MSR_TYPE_R &&
6036                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
6037                         /* read-high */
6038                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
6039
6040                 if (type & MSR_TYPE_W &&
6041                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
6042                         /* write-high */
6043                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
6044
6045         }
6046 }
6047
6048 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
6049 {
6050         u8 mode = 0;
6051
6052         if (cpu_has_secondary_exec_ctrls() &&
6053             (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
6054              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
6055                 mode |= MSR_BITMAP_MODE_X2APIC;
6056                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
6057                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
6058         }
6059
6060         return mode;
6061 }
6062
6063 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
6064
6065 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
6066                                          u8 mode)
6067 {
6068         int msr;
6069
6070         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
6071                 unsigned word = msr / BITS_PER_LONG;
6072                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
6073                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
6074         }
6075
6076         if (mode & MSR_BITMAP_MODE_X2APIC) {
6077                 /*
6078                  * TPR reads and writes can be virtualized even if virtual interrupt
6079                  * delivery is not in use.
6080                  */
6081                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
6082                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
6083                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
6084                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
6085                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
6086                 }
6087         }
6088 }
6089
6090 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
6091 {
6092         struct vcpu_vmx *vmx = to_vmx(vcpu);
6093         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
6094         u8 mode = vmx_msr_bitmap_mode(vcpu);
6095         u8 changed = mode ^ vmx->msr_bitmap_mode;
6096
6097         if (!changed)
6098                 return;
6099
6100         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
6101                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
6102
6103         vmx->msr_bitmap_mode = mode;
6104 }
6105
6106 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
6107 {
6108         return enable_apicv;
6109 }
6110
6111 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
6112 {
6113         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6114         gfn_t gfn;
6115
6116         /*
6117          * Don't need to mark the APIC access page dirty; it is never
6118          * written to by the CPU during APIC virtualization.
6119          */
6120
6121         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
6122                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
6123                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
6124         }
6125
6126         if (nested_cpu_has_posted_intr(vmcs12)) {
6127                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
6128                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
6129         }
6130 }
6131
6132
6133 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
6134 {
6135         struct vcpu_vmx *vmx = to_vmx(vcpu);
6136         int max_irr;
6137         void *vapic_page;
6138         u16 status;
6139
6140         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
6141                 return;
6142
6143         vmx->nested.pi_pending = false;
6144         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
6145                 return;
6146
6147         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
6148         if (max_irr != 256) {
6149                 vapic_page = kmap(vmx->nested.virtual_apic_page);
6150                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
6151                         vapic_page, &max_irr);
6152                 kunmap(vmx->nested.virtual_apic_page);
6153
6154                 status = vmcs_read16(GUEST_INTR_STATUS);
6155                 if ((u8)max_irr > ((u8)status & 0xff)) {
6156                         status &= ~0xff;
6157                         status |= (u8)max_irr;
6158                         vmcs_write16(GUEST_INTR_STATUS, status);
6159                 }
6160         }
6161
6162         nested_mark_vmcs12_pages_dirty(vcpu);
6163 }
6164
6165 static u8 vmx_get_rvi(void)
6166 {
6167         return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
6168 }
6169
6170 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
6171 {
6172         struct vcpu_vmx *vmx = to_vmx(vcpu);
6173         void *vapic_page;
6174         u32 vppr;
6175         int rvi;
6176
6177         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
6178                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
6179                 WARN_ON_ONCE(!vmx->nested.virtual_apic_page))
6180                 return false;
6181
6182         rvi = vmx_get_rvi();
6183
6184         vapic_page = kmap(vmx->nested.virtual_apic_page);
6185         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
6186         kunmap(vmx->nested.virtual_apic_page);
6187
6188         return ((rvi & 0xf0) > (vppr & 0xf0));
6189 }
6190
6191 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
6192                                                      bool nested)
6193 {
6194 #ifdef CONFIG_SMP
6195         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
6196
6197         if (vcpu->mode == IN_GUEST_MODE) {
6198                 /*
6199                  * The vector of interrupt to be delivered to vcpu had
6200                  * been set in PIR before this function.
6201                  *
6202                  * Following cases will be reached in this block, and
6203                  * we always send a notification event in all cases as
6204                  * explained below.
6205                  *
6206                  * Case 1: vcpu keeps in non-root mode. Sending a
6207                  * notification event posts the interrupt to vcpu.
6208                  *
6209                  * Case 2: vcpu exits to root mode and is still
6210                  * runnable. PIR will be synced to vIRR before the
6211                  * next vcpu entry. Sending a notification event in
6212                  * this case has no effect, as vcpu is not in root
6213                  * mode.
6214                  *
6215                  * Case 3: vcpu exits to root mode and is blocked.
6216                  * vcpu_block() has already synced PIR to vIRR and
6217                  * never blocks vcpu if vIRR is not cleared. Therefore,
6218                  * a blocked vcpu here does not wait for any requested
6219                  * interrupts in PIR, and sending a notification event
6220                  * which has no effect is safe here.
6221                  */
6222
6223                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
6224                 return true;
6225         }
6226 #endif
6227         return false;
6228 }
6229
6230 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
6231                                                 int vector)
6232 {
6233         struct vcpu_vmx *vmx = to_vmx(vcpu);
6234
6235         if (is_guest_mode(vcpu) &&
6236             vector == vmx->nested.posted_intr_nv) {
6237                 /*
6238                  * If a posted intr is not recognized by hardware,
6239                  * we will accomplish it in the next vmentry.
6240                  */
6241                 vmx->nested.pi_pending = true;
6242                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6243                 /* the PIR and ON have been set by L1. */
6244                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
6245                         kvm_vcpu_kick(vcpu);
6246                 return 0;
6247         }
6248         return -1;
6249 }
6250 /*
6251  * Send interrupt to vcpu via posted interrupt way.
6252  * 1. If target vcpu is running(non-root mode), send posted interrupt
6253  * notification to vcpu and hardware will sync PIR to vIRR atomically.
6254  * 2. If target vcpu isn't running(root mode), kick it to pick up the
6255  * interrupt from PIR in next vmentry.
6256  */
6257 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
6258 {
6259         struct vcpu_vmx *vmx = to_vmx(vcpu);
6260         int r;
6261
6262         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
6263         if (!r)
6264                 return;
6265
6266         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
6267                 return;
6268
6269         /* If a previous notification has sent the IPI, nothing to do.  */
6270         if (pi_test_and_set_on(&vmx->pi_desc))
6271                 return;
6272
6273         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
6274                 kvm_vcpu_kick(vcpu);
6275 }
6276
6277 /*
6278  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
6279  * will not change in the lifetime of the guest.
6280  * Note that host-state that does change is set elsewhere. E.g., host-state
6281  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
6282  */
6283 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
6284 {
6285         u32 low32, high32;
6286         unsigned long tmpl;
6287         struct desc_ptr dt;
6288         unsigned long cr0, cr3, cr4;
6289
6290         cr0 = read_cr0();
6291         WARN_ON(cr0 & X86_CR0_TS);
6292         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
6293
6294         /*
6295          * Save the most likely value for this task's CR3 in the VMCS.
6296          * We can't use __get_current_cr3_fast() because we're not atomic.
6297          */
6298         cr3 = __read_cr3();
6299         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
6300         vmx->loaded_vmcs->host_state.cr3 = cr3;
6301
6302         /* Save the most likely value for this task's CR4 in the VMCS. */
6303         cr4 = cr4_read_shadow();
6304         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
6305         vmx->loaded_vmcs->host_state.cr4 = cr4;
6306
6307         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
6308 #ifdef CONFIG_X86_64
6309         /*
6310          * Load null selectors, so we can avoid reloading them in
6311          * vmx_prepare_switch_to_host(), in case userspace uses
6312          * the null selectors too (the expected case).
6313          */
6314         vmcs_write16(HOST_DS_SELECTOR, 0);
6315         vmcs_write16(HOST_ES_SELECTOR, 0);
6316 #else
6317         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
6318         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
6319 #endif
6320         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
6321         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
6322
6323         store_idt(&dt);
6324         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
6325         vmx->host_idt_base = dt.address;
6326
6327         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
6328
6329         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
6330         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
6331         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
6332         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
6333
6334         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
6335                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
6336                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
6337         }
6338 }
6339
6340 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
6341 {
6342         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
6343         if (enable_ept)
6344                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
6345         if (is_guest_mode(&vmx->vcpu))
6346                 vmx->vcpu.arch.cr4_guest_owned_bits &=
6347                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
6348         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
6349 }
6350
6351 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
6352 {
6353         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
6354
6355         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
6356                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
6357
6358         if (!enable_vnmi)
6359                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
6360
6361         /* Enable the preemption timer dynamically */
6362         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
6363         return pin_based_exec_ctrl;
6364 }
6365
6366 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
6367 {
6368         struct vcpu_vmx *vmx = to_vmx(vcpu);
6369
6370         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6371         if (cpu_has_secondary_exec_ctrls()) {
6372                 if (kvm_vcpu_apicv_active(vcpu))
6373                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
6374                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
6375                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6376                 else
6377                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6378                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
6379                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6380         }
6381
6382         if (cpu_has_vmx_msr_bitmap())
6383                 vmx_update_msr_bitmap(vcpu);
6384 }
6385
6386 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
6387 {
6388         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
6389
6390         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
6391                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
6392
6393         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
6394                 exec_control &= ~CPU_BASED_TPR_SHADOW;
6395 #ifdef CONFIG_X86_64
6396                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
6397                                 CPU_BASED_CR8_LOAD_EXITING;
6398 #endif
6399         }
6400         if (!enable_ept)
6401                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
6402                                 CPU_BASED_CR3_LOAD_EXITING  |
6403                                 CPU_BASED_INVLPG_EXITING;
6404         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
6405                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
6406                                 CPU_BASED_MONITOR_EXITING);
6407         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
6408                 exec_control &= ~CPU_BASED_HLT_EXITING;
6409         return exec_control;
6410 }
6411
6412 static bool vmx_rdrand_supported(void)
6413 {
6414         return vmcs_config.cpu_based_2nd_exec_ctrl &
6415                 SECONDARY_EXEC_RDRAND_EXITING;
6416 }
6417
6418 static bool vmx_rdseed_supported(void)
6419 {
6420         return vmcs_config.cpu_based_2nd_exec_ctrl &
6421                 SECONDARY_EXEC_RDSEED_EXITING;
6422 }
6423
6424 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
6425 {
6426         struct kvm_vcpu *vcpu = &vmx->vcpu;
6427
6428         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
6429
6430         if (!cpu_need_virtualize_apic_accesses(vcpu))
6431                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6432         if (vmx->vpid == 0)
6433                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
6434         if (!enable_ept) {
6435                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
6436                 enable_unrestricted_guest = 0;
6437         }
6438         if (!enable_unrestricted_guest)
6439                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
6440         if (kvm_pause_in_guest(vmx->vcpu.kvm))
6441                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
6442         if (!kvm_vcpu_apicv_active(vcpu))
6443                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
6444                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6445         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6446
6447         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
6448          * in vmx_set_cr4.  */
6449         exec_control &= ~SECONDARY_EXEC_DESC;
6450
6451         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
6452            (handle_vmptrld).
6453            We can NOT enable shadow_vmcs here because we don't have yet
6454            a current VMCS12
6455         */
6456         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6457
6458         if (!enable_pml)
6459                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
6460
6461         if (vmx_xsaves_supported()) {
6462                 /* Exposing XSAVES only when XSAVE is exposed */
6463                 bool xsaves_enabled =
6464                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
6465                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
6466
6467                 if (!xsaves_enabled)
6468                         exec_control &= ~SECONDARY_EXEC_XSAVES;
6469
6470                 if (nested) {
6471                         if (xsaves_enabled)
6472                                 vmx->nested.msrs.secondary_ctls_high |=
6473                                         SECONDARY_EXEC_XSAVES;
6474                         else
6475                                 vmx->nested.msrs.secondary_ctls_high &=
6476                                         ~SECONDARY_EXEC_XSAVES;
6477                 }
6478         }
6479
6480         if (vmx_rdtscp_supported()) {
6481                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
6482                 if (!rdtscp_enabled)
6483                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6484
6485                 if (nested) {
6486                         if (rdtscp_enabled)
6487                                 vmx->nested.msrs.secondary_ctls_high |=
6488                                         SECONDARY_EXEC_RDTSCP;
6489                         else
6490                                 vmx->nested.msrs.secondary_ctls_high &=
6491                                         ~SECONDARY_EXEC_RDTSCP;
6492                 }
6493         }
6494
6495         if (vmx_invpcid_supported()) {
6496                 /* Exposing INVPCID only when PCID is exposed */
6497                 bool invpcid_enabled =
6498                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
6499                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
6500
6501                 if (!invpcid_enabled) {
6502                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6503                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
6504                 }
6505
6506                 if (nested) {
6507                         if (invpcid_enabled)
6508                                 vmx->nested.msrs.secondary_ctls_high |=
6509                                         SECONDARY_EXEC_ENABLE_INVPCID;
6510                         else
6511                                 vmx->nested.msrs.secondary_ctls_high &=
6512                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
6513                 }
6514         }
6515
6516         if (vmx_rdrand_supported()) {
6517                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
6518                 if (rdrand_enabled)
6519                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
6520
6521                 if (nested) {
6522                         if (rdrand_enabled)
6523                                 vmx->nested.msrs.secondary_ctls_high |=
6524                                         SECONDARY_EXEC_RDRAND_EXITING;
6525                         else
6526                                 vmx->nested.msrs.secondary_ctls_high &=
6527                                         ~SECONDARY_EXEC_RDRAND_EXITING;
6528                 }
6529         }
6530
6531         if (vmx_rdseed_supported()) {
6532                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
6533                 if (rdseed_enabled)
6534                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
6535
6536                 if (nested) {
6537                         if (rdseed_enabled)
6538                                 vmx->nested.msrs.secondary_ctls_high |=
6539                                         SECONDARY_EXEC_RDSEED_EXITING;
6540                         else
6541                                 vmx->nested.msrs.secondary_ctls_high &=
6542                                         ~SECONDARY_EXEC_RDSEED_EXITING;
6543                 }
6544         }
6545
6546         vmx->secondary_exec_control = exec_control;
6547 }
6548
6549 static void ept_set_mmio_spte_mask(void)
6550 {
6551         /*
6552          * EPT Misconfigurations can be generated if the value of bits 2:0
6553          * of an EPT paging-structure entry is 110b (write/execute).
6554          */
6555         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
6556                                    VMX_EPT_MISCONFIG_WX_VALUE);
6557 }
6558
6559 #define VMX_XSS_EXIT_BITMAP 0
6560 /*
6561  * Sets up the vmcs for emulated real mode.
6562  */
6563 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
6564 {
6565         int i;
6566
6567         if (enable_shadow_vmcs) {
6568                 /*
6569                  * At vCPU creation, "VMWRITE to any supported field
6570                  * in the VMCS" is supported, so use the more
6571                  * permissive vmx_vmread_bitmap to specify both read
6572                  * and write permissions for the shadow VMCS.
6573                  */
6574                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6575                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmread_bitmap));
6576         }
6577         if (cpu_has_vmx_msr_bitmap())
6578                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
6579
6580         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
6581
6582         /* Control */
6583         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6584         vmx->hv_deadline_tsc = -1;
6585
6586         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6587
6588         if (cpu_has_secondary_exec_ctrls()) {
6589                 vmx_compute_secondary_exec_control(vmx);
6590                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6591                              vmx->secondary_exec_control);
6592         }
6593
6594         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
6595                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
6596                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
6597                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
6598                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
6599
6600                 vmcs_write16(GUEST_INTR_STATUS, 0);
6601
6602                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6603                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
6604         }
6605
6606         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
6607                 vmcs_write32(PLE_GAP, ple_gap);
6608                 vmx->ple_window = ple_window;
6609                 vmx->ple_window_dirty = true;
6610         }
6611
6612         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
6613         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6614         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
6615
6616         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
6617         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
6618         vmx_set_constant_host_state(vmx);
6619         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
6620         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6621
6622         if (cpu_has_vmx_vmfunc())
6623                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
6624
6625         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
6626         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
6627         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
6628         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6629         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6630
6631         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6632                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6633
6634         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6635                 u32 index = vmx_msr_index[i];
6636                 u32 data_low, data_high;
6637                 int j = vmx->nmsrs;
6638
6639                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6640                         continue;
6641                 if (wrmsr_safe(index, data_low, data_high) < 0)
6642                         continue;
6643                 vmx->guest_msrs[j].index = i;
6644                 vmx->guest_msrs[j].data = 0;
6645                 vmx->guest_msrs[j].mask = -1ull;
6646                 ++vmx->nmsrs;
6647         }
6648
6649         vmx->arch_capabilities = kvm_get_arch_capabilities();
6650
6651         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6652
6653         /* 22.2.1, 20.8.1 */
6654         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
6655
6656         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
6657         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
6658
6659         set_cr4_guest_host_mask(vmx);
6660
6661         if (vmx_xsaves_supported())
6662                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
6663
6664         if (enable_pml) {
6665                 ASSERT(vmx->pml_pg);
6666                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
6667                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6668         }
6669
6670         if (cpu_has_vmx_encls_vmexit())
6671                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
6672 }
6673
6674 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
6675 {
6676         struct vcpu_vmx *vmx = to_vmx(vcpu);
6677         struct msr_data apic_base_msr;
6678         u64 cr0;
6679
6680         vmx->rmode.vm86_active = 0;
6681         vmx->spec_ctrl = 0;
6682
6683         vcpu->arch.microcode_version = 0x100000000ULL;
6684         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
6685         kvm_set_cr8(vcpu, 0);
6686
6687         if (!init_event) {
6688                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6689                                      MSR_IA32_APICBASE_ENABLE;
6690                 if (kvm_vcpu_is_reset_bsp(vcpu))
6691                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6692                 apic_base_msr.host_initiated = true;
6693                 kvm_set_apic_base(vcpu, &apic_base_msr);
6694         }
6695
6696         vmx_segment_cache_clear(vmx);
6697
6698         seg_setup(VCPU_SREG_CS);
6699         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6700         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6701
6702         seg_setup(VCPU_SREG_DS);
6703         seg_setup(VCPU_SREG_ES);
6704         seg_setup(VCPU_SREG_FS);
6705         seg_setup(VCPU_SREG_GS);
6706         seg_setup(VCPU_SREG_SS);
6707
6708         vmcs_write16(GUEST_TR_SELECTOR, 0);
6709         vmcs_writel(GUEST_TR_BASE, 0);
6710         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6711         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6712
6713         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6714         vmcs_writel(GUEST_LDTR_BASE, 0);
6715         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6716         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6717
6718         if (!init_event) {
6719                 vmcs_write32(GUEST_SYSENTER_CS, 0);
6720                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6721                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6722                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6723         }
6724
6725         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6726         kvm_rip_write(vcpu, 0xfff0);
6727
6728         vmcs_writel(GUEST_GDTR_BASE, 0);
6729         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6730
6731         vmcs_writel(GUEST_IDTR_BASE, 0);
6732         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6733
6734         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6735         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6736         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6737         if (kvm_mpx_supported())
6738                 vmcs_write64(GUEST_BNDCFGS, 0);
6739
6740         setup_msrs(vmx);
6741
6742         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
6743
6744         if (cpu_has_vmx_tpr_shadow() && !init_event) {
6745                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6746                 if (cpu_need_tpr_shadow(vcpu))
6747                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6748                                      __pa(vcpu->arch.apic->regs));
6749                 vmcs_write32(TPR_THRESHOLD, 0);
6750         }
6751
6752         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6753
6754         if (vmx->vpid != 0)
6755                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6756
6757         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6758         vmx->vcpu.arch.cr0 = cr0;
6759         vmx_set_cr0(vcpu, cr0); /* enter rmode */
6760         vmx_set_cr4(vcpu, 0);
6761         vmx_set_efer(vcpu, 0);
6762
6763         update_exception_bitmap(vcpu);
6764
6765         vpid_sync_context(vmx->vpid);
6766         if (init_event)
6767                 vmx_clear_hlt(vcpu);
6768 }
6769
6770 /*
6771  * In nested virtualization, check if L1 asked to exit on external interrupts.
6772  * For most existing hypervisors, this will always return true.
6773  */
6774 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6775 {
6776         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6777                 PIN_BASED_EXT_INTR_MASK;
6778 }
6779
6780 /*
6781  * In nested virtualization, check if L1 has set
6782  * VM_EXIT_ACK_INTR_ON_EXIT
6783  */
6784 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6785 {
6786         return get_vmcs12(vcpu)->vm_exit_controls &
6787                 VM_EXIT_ACK_INTR_ON_EXIT;
6788 }
6789
6790 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6791 {
6792         return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
6793 }
6794
6795 static void enable_irq_window(struct kvm_vcpu *vcpu)
6796 {
6797         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6798                       CPU_BASED_VIRTUAL_INTR_PENDING);
6799 }
6800
6801 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6802 {
6803         if (!enable_vnmi ||
6804             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6805                 enable_irq_window(vcpu);
6806                 return;
6807         }
6808
6809         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6810                       CPU_BASED_VIRTUAL_NMI_PENDING);
6811 }
6812
6813 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6814 {
6815         struct vcpu_vmx *vmx = to_vmx(vcpu);
6816         uint32_t intr;
6817         int irq = vcpu->arch.interrupt.nr;
6818
6819         trace_kvm_inj_virq(irq);
6820
6821         ++vcpu->stat.irq_injections;
6822         if (vmx->rmode.vm86_active) {
6823                 int inc_eip = 0;
6824                 if (vcpu->arch.interrupt.soft)
6825                         inc_eip = vcpu->arch.event_exit_inst_len;
6826                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6827                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6828                 return;
6829         }
6830         intr = irq | INTR_INFO_VALID_MASK;
6831         if (vcpu->arch.interrupt.soft) {
6832                 intr |= INTR_TYPE_SOFT_INTR;
6833                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6834                              vmx->vcpu.arch.event_exit_inst_len);
6835         } else
6836                 intr |= INTR_TYPE_EXT_INTR;
6837         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6838
6839         vmx_clear_hlt(vcpu);
6840 }
6841
6842 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6843 {
6844         struct vcpu_vmx *vmx = to_vmx(vcpu);
6845
6846         if (!enable_vnmi) {
6847                 /*
6848                  * Tracking the NMI-blocked state in software is built upon
6849                  * finding the next open IRQ window. This, in turn, depends on
6850                  * well-behaving guests: They have to keep IRQs disabled at
6851                  * least as long as the NMI handler runs. Otherwise we may
6852                  * cause NMI nesting, maybe breaking the guest. But as this is
6853                  * highly unlikely, we can live with the residual risk.
6854                  */
6855                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6856                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6857         }
6858
6859         ++vcpu->stat.nmi_injections;
6860         vmx->loaded_vmcs->nmi_known_unmasked = false;
6861
6862         if (vmx->rmode.vm86_active) {
6863                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6864                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6865                 return;
6866         }
6867
6868         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6869                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6870
6871         vmx_clear_hlt(vcpu);
6872 }
6873
6874 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6875 {
6876         struct vcpu_vmx *vmx = to_vmx(vcpu);
6877         bool masked;
6878
6879         if (!enable_vnmi)
6880                 return vmx->loaded_vmcs->soft_vnmi_blocked;
6881         if (vmx->loaded_vmcs->nmi_known_unmasked)
6882                 return false;
6883         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6884         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6885         return masked;
6886 }
6887
6888 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6889 {
6890         struct vcpu_vmx *vmx = to_vmx(vcpu);
6891
6892         if (!enable_vnmi) {
6893                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6894                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6895                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
6896                 }
6897         } else {
6898                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6899                 if (masked)
6900                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6901                                       GUEST_INTR_STATE_NMI);
6902                 else
6903                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6904                                         GUEST_INTR_STATE_NMI);
6905         }
6906 }
6907
6908 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6909 {
6910         if (to_vmx(vcpu)->nested.nested_run_pending)
6911                 return 0;
6912
6913         if (!enable_vnmi &&
6914             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6915                 return 0;
6916
6917         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6918                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6919                    | GUEST_INTR_STATE_NMI));
6920 }
6921
6922 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6923 {
6924         return (!to_vmx(vcpu)->nested.nested_run_pending &&
6925                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6926                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6927                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6928 }
6929
6930 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6931 {
6932         int ret;
6933
6934         if (enable_unrestricted_guest)
6935                 return 0;
6936
6937         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6938                                     PAGE_SIZE * 3);
6939         if (ret)
6940                 return ret;
6941         to_kvm_vmx(kvm)->tss_addr = addr;
6942         return init_rmode_tss(kvm);
6943 }
6944
6945 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
6946 {
6947         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
6948         return 0;
6949 }
6950
6951 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6952 {
6953         switch (vec) {
6954         case BP_VECTOR:
6955                 /*
6956                  * Update instruction length as we may reinject the exception
6957                  * from user space while in guest debugging mode.
6958                  */
6959                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6960                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6961                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6962                         return false;
6963                 /* fall through */
6964         case DB_VECTOR:
6965                 if (vcpu->guest_debug &
6966                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6967                         return false;
6968                 /* fall through */
6969         case DE_VECTOR:
6970         case OF_VECTOR:
6971         case BR_VECTOR:
6972         case UD_VECTOR:
6973         case DF_VECTOR:
6974         case SS_VECTOR:
6975         case GP_VECTOR:
6976         case MF_VECTOR:
6977                 return true;
6978         break;
6979         }
6980         return false;
6981 }
6982
6983 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6984                                   int vec, u32 err_code)
6985 {
6986         /*
6987          * Instruction with address size override prefix opcode 0x67
6988          * Cause the #SS fault with 0 error code in VM86 mode.
6989          */
6990         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6991                 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6992                         if (vcpu->arch.halt_request) {
6993                                 vcpu->arch.halt_request = 0;
6994                                 return kvm_vcpu_halt(vcpu);
6995                         }
6996                         return 1;
6997                 }
6998                 return 0;
6999         }
7000
7001         /*
7002          * Forward all other exceptions that are valid in real mode.
7003          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
7004          *        the required debugging infrastructure rework.
7005          */
7006         kvm_queue_exception(vcpu, vec);
7007         return 1;
7008 }
7009
7010 /*
7011  * Trigger machine check on the host. We assume all the MSRs are already set up
7012  * by the CPU and that we still run on the same CPU as the MCE occurred on.
7013  * We pass a fake environment to the machine check handler because we want
7014  * the guest to be always treated like user space, no matter what context
7015  * it used internally.
7016  */
7017 static void kvm_machine_check(void)
7018 {
7019 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
7020         struct pt_regs regs = {
7021                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
7022                 .flags = X86_EFLAGS_IF,
7023         };
7024
7025         do_machine_check(&regs, 0);
7026 #endif
7027 }
7028
7029 static int handle_machine_check(struct kvm_vcpu *vcpu)
7030 {
7031         /* already handled by vcpu_run */
7032         return 1;
7033 }
7034
7035 static int handle_exception(struct kvm_vcpu *vcpu)
7036 {
7037         struct vcpu_vmx *vmx = to_vmx(vcpu);
7038         struct kvm_run *kvm_run = vcpu->run;
7039         u32 intr_info, ex_no, error_code;
7040         unsigned long cr2, rip, dr6;
7041         u32 vect_info;
7042         enum emulation_result er;
7043
7044         vect_info = vmx->idt_vectoring_info;
7045         intr_info = vmx->exit_intr_info;
7046
7047         if (is_machine_check(intr_info))
7048                 return handle_machine_check(vcpu);
7049
7050         if (is_nmi(intr_info))
7051                 return 1;  /* already handled by vmx_vcpu_run() */
7052
7053         if (is_invalid_opcode(intr_info))
7054                 return handle_ud(vcpu);
7055
7056         error_code = 0;
7057         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
7058                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7059
7060         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
7061                 WARN_ON_ONCE(!enable_vmware_backdoor);
7062                 er = kvm_emulate_instruction(vcpu,
7063                         EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
7064                 if (er == EMULATE_USER_EXIT)
7065                         return 0;
7066                 else if (er != EMULATE_DONE)
7067                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
7068                 return 1;
7069         }
7070
7071         /*
7072          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
7073          * MMIO, it is better to report an internal error.
7074          * See the comments in vmx_handle_exit.
7075          */
7076         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
7077             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
7078                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7079                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
7080                 vcpu->run->internal.ndata = 3;
7081                 vcpu->run->internal.data[0] = vect_info;
7082                 vcpu->run->internal.data[1] = intr_info;
7083                 vcpu->run->internal.data[2] = error_code;
7084                 return 0;
7085         }
7086
7087         if (is_page_fault(intr_info)) {
7088                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
7089                 /* EPT won't cause page fault directly */
7090                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
7091                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
7092         }
7093
7094         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
7095
7096         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
7097                 return handle_rmode_exception(vcpu, ex_no, error_code);
7098
7099         switch (ex_no) {
7100         case AC_VECTOR:
7101                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
7102                 return 1;
7103         case DB_VECTOR:
7104                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
7105                 if (!(vcpu->guest_debug &
7106                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
7107                         vcpu->arch.dr6 &= ~15;
7108                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
7109                         if (is_icebp(intr_info))
7110                                 skip_emulated_instruction(vcpu);
7111
7112                         kvm_queue_exception(vcpu, DB_VECTOR);
7113                         return 1;
7114                 }
7115                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
7116                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
7117                 /* fall through */
7118         case BP_VECTOR:
7119                 /*
7120                  * Update instruction length as we may reinject #BP from
7121                  * user space while in guest debugging mode. Reading it for
7122                  * #DB as well causes no harm, it is not used in that case.
7123                  */
7124                 vmx->vcpu.arch.event_exit_inst_len =
7125                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7126                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7127                 rip = kvm_rip_read(vcpu);
7128                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
7129                 kvm_run->debug.arch.exception = ex_no;
7130                 break;
7131         default:
7132                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
7133                 kvm_run->ex.exception = ex_no;
7134                 kvm_run->ex.error_code = error_code;
7135                 break;
7136         }
7137         return 0;
7138 }
7139
7140 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
7141 {
7142         ++vcpu->stat.irq_exits;
7143         return 1;
7144 }
7145
7146 static int handle_triple_fault(struct kvm_vcpu *vcpu)
7147 {
7148         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7149         vcpu->mmio_needed = 0;
7150         return 0;
7151 }
7152
7153 static int handle_io(struct kvm_vcpu *vcpu)
7154 {
7155         unsigned long exit_qualification;
7156         int size, in, string;
7157         unsigned port;
7158
7159         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7160         string = (exit_qualification & 16) != 0;
7161
7162         ++vcpu->stat.io_exits;
7163
7164         if (string)
7165                 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7166
7167         port = exit_qualification >> 16;
7168         size = (exit_qualification & 7) + 1;
7169         in = (exit_qualification & 8) != 0;
7170
7171         return kvm_fast_pio(vcpu, size, port, in);
7172 }
7173
7174 static void
7175 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
7176 {
7177         /*
7178          * Patch in the VMCALL instruction:
7179          */
7180         hypercall[0] = 0x0f;
7181         hypercall[1] = 0x01;
7182         hypercall[2] = 0xc1;
7183 }
7184
7185 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
7186 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
7187 {
7188         if (is_guest_mode(vcpu)) {
7189                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7190                 unsigned long orig_val = val;
7191
7192                 /*
7193                  * We get here when L2 changed cr0 in a way that did not change
7194                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
7195                  * but did change L0 shadowed bits. So we first calculate the
7196                  * effective cr0 value that L1 would like to write into the
7197                  * hardware. It consists of the L2-owned bits from the new
7198                  * value combined with the L1-owned bits from L1's guest_cr0.
7199                  */
7200                 val = (val & ~vmcs12->cr0_guest_host_mask) |
7201                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
7202
7203                 if (!nested_guest_cr0_valid(vcpu, val))
7204                         return 1;
7205
7206                 if (kvm_set_cr0(vcpu, val))
7207                         return 1;
7208                 vmcs_writel(CR0_READ_SHADOW, orig_val);
7209                 return 0;
7210         } else {
7211                 if (to_vmx(vcpu)->nested.vmxon &&
7212                     !nested_host_cr0_valid(vcpu, val))
7213                         return 1;
7214
7215                 return kvm_set_cr0(vcpu, val);
7216         }
7217 }
7218
7219 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
7220 {
7221         if (is_guest_mode(vcpu)) {
7222                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7223                 unsigned long orig_val = val;
7224
7225                 /* analogously to handle_set_cr0 */
7226                 val = (val & ~vmcs12->cr4_guest_host_mask) |
7227                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
7228                 if (kvm_set_cr4(vcpu, val))
7229                         return 1;
7230                 vmcs_writel(CR4_READ_SHADOW, orig_val);
7231                 return 0;
7232         } else
7233                 return kvm_set_cr4(vcpu, val);
7234 }
7235
7236 static int handle_desc(struct kvm_vcpu *vcpu)
7237 {
7238         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
7239         return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7240 }
7241
7242 static int handle_cr(struct kvm_vcpu *vcpu)
7243 {
7244         unsigned long exit_qualification, val;
7245         int cr;
7246         int reg;
7247         int err;
7248         int ret;
7249
7250         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7251         cr = exit_qualification & 15;
7252         reg = (exit_qualification >> 8) & 15;
7253         switch ((exit_qualification >> 4) & 3) {
7254         case 0: /* mov to cr */
7255                 val = kvm_register_readl(vcpu, reg);
7256                 trace_kvm_cr_write(cr, val);
7257                 switch (cr) {
7258                 case 0:
7259                         err = handle_set_cr0(vcpu, val);
7260                         return kvm_complete_insn_gp(vcpu, err);
7261                 case 3:
7262                         WARN_ON_ONCE(enable_unrestricted_guest);
7263                         err = kvm_set_cr3(vcpu, val);
7264                         return kvm_complete_insn_gp(vcpu, err);
7265                 case 4:
7266                         err = handle_set_cr4(vcpu, val);
7267                         return kvm_complete_insn_gp(vcpu, err);
7268                 case 8: {
7269                                 u8 cr8_prev = kvm_get_cr8(vcpu);
7270                                 u8 cr8 = (u8)val;
7271                                 err = kvm_set_cr8(vcpu, cr8);
7272                                 ret = kvm_complete_insn_gp(vcpu, err);
7273                                 if (lapic_in_kernel(vcpu))
7274                                         return ret;
7275                                 if (cr8_prev <= cr8)
7276                                         return ret;
7277                                 /*
7278                                  * TODO: we might be squashing a
7279                                  * KVM_GUESTDBG_SINGLESTEP-triggered
7280                                  * KVM_EXIT_DEBUG here.
7281                                  */
7282                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
7283                                 return 0;
7284                         }
7285                 }
7286                 break;
7287         case 2: /* clts */
7288                 WARN_ONCE(1, "Guest should always own CR0.TS");
7289                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
7290                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
7291                 return kvm_skip_emulated_instruction(vcpu);
7292         case 1: /*mov from cr*/
7293                 switch (cr) {
7294                 case 3:
7295                         WARN_ON_ONCE(enable_unrestricted_guest);
7296                         val = kvm_read_cr3(vcpu);
7297                         kvm_register_write(vcpu, reg, val);
7298                         trace_kvm_cr_read(cr, val);
7299                         return kvm_skip_emulated_instruction(vcpu);
7300                 case 8:
7301                         val = kvm_get_cr8(vcpu);
7302                         kvm_register_write(vcpu, reg, val);
7303                         trace_kvm_cr_read(cr, val);
7304                         return kvm_skip_emulated_instruction(vcpu);
7305                 }
7306                 break;
7307         case 3: /* lmsw */
7308                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
7309                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
7310                 kvm_lmsw(vcpu, val);
7311
7312                 return kvm_skip_emulated_instruction(vcpu);
7313         default:
7314                 break;
7315         }
7316         vcpu->run->exit_reason = 0;
7317         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
7318                (int)(exit_qualification >> 4) & 3, cr);
7319         return 0;
7320 }
7321
7322 static int handle_dr(struct kvm_vcpu *vcpu)
7323 {
7324         unsigned long exit_qualification;
7325         int dr, dr7, reg;
7326
7327         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7328         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
7329
7330         /* First, if DR does not exist, trigger UD */
7331         if (!kvm_require_dr(vcpu, dr))
7332                 return 1;
7333
7334         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
7335         if (!kvm_require_cpl(vcpu, 0))
7336                 return 1;
7337         dr7 = vmcs_readl(GUEST_DR7);
7338         if (dr7 & DR7_GD) {
7339                 /*
7340                  * As the vm-exit takes precedence over the debug trap, we
7341                  * need to emulate the latter, either for the host or the
7342                  * guest debugging itself.
7343                  */
7344                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7345                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
7346                         vcpu->run->debug.arch.dr7 = dr7;
7347                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7348                         vcpu->run->debug.arch.exception = DB_VECTOR;
7349                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
7350                         return 0;
7351                 } else {
7352                         vcpu->arch.dr6 &= ~15;
7353                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
7354                         kvm_queue_exception(vcpu, DB_VECTOR);
7355                         return 1;
7356                 }
7357         }
7358
7359         if (vcpu->guest_debug == 0) {
7360                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7361                                 CPU_BASED_MOV_DR_EXITING);
7362
7363                 /*
7364                  * No more DR vmexits; force a reload of the debug registers
7365                  * and reenter on this instruction.  The next vmexit will
7366                  * retrieve the full state of the debug registers.
7367                  */
7368                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
7369                 return 1;
7370         }
7371
7372         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
7373         if (exit_qualification & TYPE_MOV_FROM_DR) {
7374                 unsigned long val;
7375
7376                 if (kvm_get_dr(vcpu, dr, &val))
7377                         return 1;
7378                 kvm_register_write(vcpu, reg, val);
7379         } else
7380                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
7381                         return 1;
7382
7383         return kvm_skip_emulated_instruction(vcpu);
7384 }
7385
7386 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
7387 {
7388         return vcpu->arch.dr6;
7389 }
7390
7391 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
7392 {
7393 }
7394
7395 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
7396 {
7397         get_debugreg(vcpu->arch.db[0], 0);
7398         get_debugreg(vcpu->arch.db[1], 1);
7399         get_debugreg(vcpu->arch.db[2], 2);
7400         get_debugreg(vcpu->arch.db[3], 3);
7401         get_debugreg(vcpu->arch.dr6, 6);
7402         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
7403
7404         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
7405         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
7406 }
7407
7408 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
7409 {
7410         vmcs_writel(GUEST_DR7, val);
7411 }
7412
7413 static int handle_cpuid(struct kvm_vcpu *vcpu)
7414 {
7415         return kvm_emulate_cpuid(vcpu);
7416 }
7417
7418 static int handle_rdmsr(struct kvm_vcpu *vcpu)
7419 {
7420         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7421         struct msr_data msr_info;
7422
7423         msr_info.index = ecx;
7424         msr_info.host_initiated = false;
7425         if (vmx_get_msr(vcpu, &msr_info)) {
7426                 trace_kvm_msr_read_ex(ecx);
7427                 kvm_inject_gp(vcpu, 0);
7428                 return 1;
7429         }
7430
7431         trace_kvm_msr_read(ecx, msr_info.data);
7432
7433         /* FIXME: handling of bits 32:63 of rax, rdx */
7434         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
7435         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
7436         return kvm_skip_emulated_instruction(vcpu);
7437 }
7438
7439 static int handle_wrmsr(struct kvm_vcpu *vcpu)
7440 {
7441         struct msr_data msr;
7442         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7443         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
7444                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
7445
7446         msr.data = data;
7447         msr.index = ecx;
7448         msr.host_initiated = false;
7449         if (kvm_set_msr(vcpu, &msr) != 0) {
7450                 trace_kvm_msr_write_ex(ecx, data);
7451                 kvm_inject_gp(vcpu, 0);
7452                 return 1;
7453         }
7454
7455         trace_kvm_msr_write(ecx, data);
7456         return kvm_skip_emulated_instruction(vcpu);
7457 }
7458
7459 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
7460 {
7461         kvm_apic_update_ppr(vcpu);
7462         return 1;
7463 }
7464
7465 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
7466 {
7467         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7468                         CPU_BASED_VIRTUAL_INTR_PENDING);
7469
7470         kvm_make_request(KVM_REQ_EVENT, vcpu);
7471
7472         ++vcpu->stat.irq_window_exits;
7473         return 1;
7474 }
7475
7476 static int handle_halt(struct kvm_vcpu *vcpu)
7477 {
7478         return kvm_emulate_halt(vcpu);
7479 }
7480
7481 static int handle_vmcall(struct kvm_vcpu *vcpu)
7482 {
7483         return kvm_emulate_hypercall(vcpu);
7484 }
7485
7486 static int handle_invd(struct kvm_vcpu *vcpu)
7487 {
7488         return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7489 }
7490
7491 static int handle_invlpg(struct kvm_vcpu *vcpu)
7492 {
7493         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7494
7495         kvm_mmu_invlpg(vcpu, exit_qualification);
7496         return kvm_skip_emulated_instruction(vcpu);
7497 }
7498
7499 static int handle_rdpmc(struct kvm_vcpu *vcpu)
7500 {
7501         int err;
7502
7503         err = kvm_rdpmc(vcpu);
7504         return kvm_complete_insn_gp(vcpu, err);
7505 }
7506
7507 static int handle_wbinvd(struct kvm_vcpu *vcpu)
7508 {
7509         return kvm_emulate_wbinvd(vcpu);
7510 }
7511
7512 static int handle_xsetbv(struct kvm_vcpu *vcpu)
7513 {
7514         u64 new_bv = kvm_read_edx_eax(vcpu);
7515         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
7516
7517         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
7518                 return kvm_skip_emulated_instruction(vcpu);
7519         return 1;
7520 }
7521
7522 static int handle_xsaves(struct kvm_vcpu *vcpu)
7523 {
7524         kvm_skip_emulated_instruction(vcpu);
7525         WARN(1, "this should never happen\n");
7526         return 1;
7527 }
7528
7529 static int handle_xrstors(struct kvm_vcpu *vcpu)
7530 {
7531         kvm_skip_emulated_instruction(vcpu);
7532         WARN(1, "this should never happen\n");
7533         return 1;
7534 }
7535
7536 static int handle_apic_access(struct kvm_vcpu *vcpu)
7537 {
7538         if (likely(fasteoi)) {
7539                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7540                 int access_type, offset;
7541
7542                 access_type = exit_qualification & APIC_ACCESS_TYPE;
7543                 offset = exit_qualification & APIC_ACCESS_OFFSET;
7544                 /*
7545                  * Sane guest uses MOV to write EOI, with written value
7546                  * not cared. So make a short-circuit here by avoiding
7547                  * heavy instruction emulation.
7548                  */
7549                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
7550                     (offset == APIC_EOI)) {
7551                         kvm_lapic_set_eoi(vcpu);
7552                         return kvm_skip_emulated_instruction(vcpu);
7553                 }
7554         }
7555         return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7556 }
7557
7558 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
7559 {
7560         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7561         int vector = exit_qualification & 0xff;
7562
7563         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
7564         kvm_apic_set_eoi_accelerated(vcpu, vector);
7565         return 1;
7566 }
7567
7568 static int handle_apic_write(struct kvm_vcpu *vcpu)
7569 {
7570         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7571         u32 offset = exit_qualification & 0xfff;
7572
7573         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
7574         kvm_apic_write_nodecode(vcpu, offset);
7575         return 1;
7576 }
7577
7578 static int handle_task_switch(struct kvm_vcpu *vcpu)
7579 {
7580         struct vcpu_vmx *vmx = to_vmx(vcpu);
7581         unsigned long exit_qualification;
7582         bool has_error_code = false;
7583         u32 error_code = 0;
7584         u16 tss_selector;
7585         int reason, type, idt_v, idt_index;
7586
7587         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7588         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
7589         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
7590
7591         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7592
7593         reason = (u32)exit_qualification >> 30;
7594         if (reason == TASK_SWITCH_GATE && idt_v) {
7595                 switch (type) {
7596                 case INTR_TYPE_NMI_INTR:
7597                         vcpu->arch.nmi_injected = false;
7598                         vmx_set_nmi_mask(vcpu, true);
7599                         break;
7600                 case INTR_TYPE_EXT_INTR:
7601                 case INTR_TYPE_SOFT_INTR:
7602                         kvm_clear_interrupt_queue(vcpu);
7603                         break;
7604                 case INTR_TYPE_HARD_EXCEPTION:
7605                         if (vmx->idt_vectoring_info &
7606                             VECTORING_INFO_DELIVER_CODE_MASK) {
7607                                 has_error_code = true;
7608                                 error_code =
7609                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
7610                         }
7611                         /* fall through */
7612                 case INTR_TYPE_SOFT_EXCEPTION:
7613                         kvm_clear_exception_queue(vcpu);
7614                         break;
7615                 default:
7616                         break;
7617                 }
7618         }
7619         tss_selector = exit_qualification;
7620
7621         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
7622                        type != INTR_TYPE_EXT_INTR &&
7623                        type != INTR_TYPE_NMI_INTR))
7624                 skip_emulated_instruction(vcpu);
7625
7626         if (kvm_task_switch(vcpu, tss_selector,
7627                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
7628                             has_error_code, error_code) == EMULATE_FAIL) {
7629                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7630                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7631                 vcpu->run->internal.ndata = 0;
7632                 return 0;
7633         }
7634
7635         /*
7636          * TODO: What about debug traps on tss switch?
7637          *       Are we supposed to inject them and update dr6?
7638          */
7639
7640         return 1;
7641 }
7642
7643 static int handle_ept_violation(struct kvm_vcpu *vcpu)
7644 {
7645         unsigned long exit_qualification;
7646         gpa_t gpa;
7647         u64 error_code;
7648
7649         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7650
7651         /*
7652          * EPT violation happened while executing iret from NMI,
7653          * "blocked by NMI" bit has to be set before next VM entry.
7654          * There are errata that may cause this bit to not be set:
7655          * AAK134, BY25.
7656          */
7657         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7658                         enable_vnmi &&
7659                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7660                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
7661
7662         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7663         trace_kvm_page_fault(gpa, exit_qualification);
7664
7665         /* Is it a read fault? */
7666         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
7667                      ? PFERR_USER_MASK : 0;
7668         /* Is it a write fault? */
7669         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
7670                       ? PFERR_WRITE_MASK : 0;
7671         /* Is it a fetch fault? */
7672         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
7673                       ? PFERR_FETCH_MASK : 0;
7674         /* ept page table entry is present? */
7675         error_code |= (exit_qualification &
7676                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
7677                         EPT_VIOLATION_EXECUTABLE))
7678                       ? PFERR_PRESENT_MASK : 0;
7679
7680         error_code |= (exit_qualification & 0x100) != 0 ?
7681                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
7682
7683         vcpu->arch.exit_qualification = exit_qualification;
7684         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
7685 }
7686
7687 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
7688 {
7689         gpa_t gpa;
7690
7691         /*
7692          * A nested guest cannot optimize MMIO vmexits, because we have an
7693          * nGPA here instead of the required GPA.
7694          */
7695         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7696         if (!is_guest_mode(vcpu) &&
7697             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
7698                 trace_kvm_fast_mmio(gpa);
7699                 /*
7700                  * Doing kvm_skip_emulated_instruction() depends on undefined
7701                  * behavior: Intel's manual doesn't mandate
7702                  * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7703                  * occurs and while on real hardware it was observed to be set,
7704                  * other hypervisors (namely Hyper-V) don't set it, we end up
7705                  * advancing IP with some random value. Disable fast mmio when
7706                  * running nested and keep it for real hardware in hope that
7707                  * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7708                  */
7709                 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7710                         return kvm_skip_emulated_instruction(vcpu);
7711                 else
7712                         return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) ==
7713                                                                 EMULATE_DONE;
7714         }
7715
7716         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7717 }
7718
7719 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7720 {
7721         WARN_ON_ONCE(!enable_vnmi);
7722         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7723                         CPU_BASED_VIRTUAL_NMI_PENDING);
7724         ++vcpu->stat.nmi_window_exits;
7725         kvm_make_request(KVM_REQ_EVENT, vcpu);
7726
7727         return 1;
7728 }
7729
7730 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7731 {
7732         struct vcpu_vmx *vmx = to_vmx(vcpu);
7733         enum emulation_result err = EMULATE_DONE;
7734         int ret = 1;
7735         u32 cpu_exec_ctrl;
7736         bool intr_window_requested;
7737         unsigned count = 130;
7738
7739         /*
7740          * We should never reach the point where we are emulating L2
7741          * due to invalid guest state as that means we incorrectly
7742          * allowed a nested VMEntry with an invalid vmcs12.
7743          */
7744         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
7745
7746         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7747         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7748
7749         while (vmx->emulation_required && count-- != 0) {
7750                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7751                         return handle_interrupt_window(&vmx->vcpu);
7752
7753                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7754                         return 1;
7755
7756                 err = kvm_emulate_instruction(vcpu, 0);
7757
7758                 if (err == EMULATE_USER_EXIT) {
7759                         ++vcpu->stat.mmio_exits;
7760                         ret = 0;
7761                         goto out;
7762                 }
7763
7764                 if (err != EMULATE_DONE)
7765                         goto emulation_error;
7766
7767                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7768                     vcpu->arch.exception.pending)
7769                         goto emulation_error;
7770
7771                 if (vcpu->arch.halt_request) {
7772                         vcpu->arch.halt_request = 0;
7773                         ret = kvm_vcpu_halt(vcpu);
7774                         goto out;
7775                 }
7776
7777                 if (signal_pending(current))
7778                         goto out;
7779                 if (need_resched())
7780                         schedule();
7781         }
7782
7783 out:
7784         return ret;
7785
7786 emulation_error:
7787         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7788         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7789         vcpu->run->internal.ndata = 0;
7790         return 0;
7791 }
7792
7793 static void grow_ple_window(struct kvm_vcpu *vcpu)
7794 {
7795         struct vcpu_vmx *vmx = to_vmx(vcpu);
7796         int old = vmx->ple_window;
7797
7798         vmx->ple_window = __grow_ple_window(old, ple_window,
7799                                             ple_window_grow,
7800                                             ple_window_max);
7801
7802         if (vmx->ple_window != old)
7803                 vmx->ple_window_dirty = true;
7804
7805         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7806 }
7807
7808 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7809 {
7810         struct vcpu_vmx *vmx = to_vmx(vcpu);
7811         int old = vmx->ple_window;
7812
7813         vmx->ple_window = __shrink_ple_window(old, ple_window,
7814                                               ple_window_shrink,
7815                                               ple_window);
7816
7817         if (vmx->ple_window != old)
7818                 vmx->ple_window_dirty = true;
7819
7820         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7821 }
7822
7823 /*
7824  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7825  */
7826 static void wakeup_handler(void)
7827 {
7828         struct kvm_vcpu *vcpu;
7829         int cpu = smp_processor_id();
7830
7831         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7832         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7833                         blocked_vcpu_list) {
7834                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7835
7836                 if (pi_test_on(pi_desc) == 1)
7837                         kvm_vcpu_kick(vcpu);
7838         }
7839         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7840 }
7841
7842 static void vmx_enable_tdp(void)
7843 {
7844         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7845                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7846                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7847                 0ull, VMX_EPT_EXECUTABLE_MASK,
7848                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7849                 VMX_EPT_RWX_MASK, 0ull);
7850
7851         ept_set_mmio_spte_mask();
7852         kvm_enable_tdp();
7853 }
7854
7855 static __init int hardware_setup(void)
7856 {
7857         unsigned long host_bndcfgs;
7858         int r = -ENOMEM, i;
7859
7860         rdmsrl_safe(MSR_EFER, &host_efer);
7861
7862         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7863                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7864
7865         for (i = 0; i < VMX_BITMAP_NR; i++) {
7866                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7867                 if (!vmx_bitmap[i])
7868                         goto out;
7869         }
7870
7871         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7872         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7873
7874         if (setup_vmcs_config(&vmcs_config) < 0) {
7875                 r = -EIO;
7876                 goto out;
7877         }
7878
7879         if (boot_cpu_has(X86_FEATURE_NX))
7880                 kvm_enable_efer_bits(EFER_NX);
7881
7882         if (boot_cpu_has(X86_FEATURE_MPX)) {
7883                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7884                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7885         }
7886
7887         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7888                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7889                 enable_vpid = 0;
7890
7891         if (!cpu_has_vmx_ept() ||
7892             !cpu_has_vmx_ept_4levels() ||
7893             !cpu_has_vmx_ept_mt_wb() ||
7894             !cpu_has_vmx_invept_global())
7895                 enable_ept = 0;
7896
7897         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7898                 enable_ept_ad_bits = 0;
7899
7900         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7901                 enable_unrestricted_guest = 0;
7902
7903         if (!cpu_has_vmx_flexpriority())
7904                 flexpriority_enabled = 0;
7905
7906         if (!cpu_has_virtual_nmis())
7907                 enable_vnmi = 0;
7908
7909         /*
7910          * set_apic_access_page_addr() is used to reload apic access
7911          * page upon invalidation.  No need to do anything if not
7912          * using the APIC_ACCESS_ADDR VMCS field.
7913          */
7914         if (!flexpriority_enabled)
7915                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7916
7917         if (!cpu_has_vmx_tpr_shadow())
7918                 kvm_x86_ops->update_cr8_intercept = NULL;
7919
7920         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7921                 kvm_disable_largepages();
7922
7923 #if IS_ENABLED(CONFIG_HYPERV)
7924         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7925             && enable_ept)
7926                 kvm_x86_ops->tlb_remote_flush = vmx_hv_remote_flush_tlb;
7927 #endif
7928
7929         if (!cpu_has_vmx_ple()) {
7930                 ple_gap = 0;
7931                 ple_window = 0;
7932                 ple_window_grow = 0;
7933                 ple_window_max = 0;
7934                 ple_window_shrink = 0;
7935         }
7936
7937         if (!cpu_has_vmx_apicv()) {
7938                 enable_apicv = 0;
7939                 kvm_x86_ops->sync_pir_to_irr = NULL;
7940         }
7941
7942         if (cpu_has_vmx_tsc_scaling()) {
7943                 kvm_has_tsc_control = true;
7944                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7945                 kvm_tsc_scaling_ratio_frac_bits = 48;
7946         }
7947
7948         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7949
7950         if (enable_ept)
7951                 vmx_enable_tdp();
7952         else
7953                 kvm_disable_tdp();
7954
7955         if (!nested) {
7956                 kvm_x86_ops->get_nested_state = NULL;
7957                 kvm_x86_ops->set_nested_state = NULL;
7958         }
7959
7960         /*
7961          * Only enable PML when hardware supports PML feature, and both EPT
7962          * and EPT A/D bit features are enabled -- PML depends on them to work.
7963          */
7964         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7965                 enable_pml = 0;
7966
7967         if (!enable_pml) {
7968                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7969                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7970                 kvm_x86_ops->flush_log_dirty = NULL;
7971                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7972         }
7973
7974         if (!cpu_has_vmx_preemption_timer())
7975                 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7976
7977         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7978                 u64 vmx_msr;
7979
7980                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7981                 cpu_preemption_timer_multi =
7982                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7983         } else {
7984                 kvm_x86_ops->set_hv_timer = NULL;
7985                 kvm_x86_ops->cancel_hv_timer = NULL;
7986         }
7987
7988         if (!cpu_has_vmx_shadow_vmcs())
7989                 enable_shadow_vmcs = 0;
7990         if (enable_shadow_vmcs)
7991                 init_vmcs_shadow_fields();
7992
7993         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7994         nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv);
7995
7996         kvm_mce_cap_supported |= MCG_LMCE_P;
7997
7998         return alloc_kvm_area();
7999
8000 out:
8001         for (i = 0; i < VMX_BITMAP_NR; i++)
8002                 free_page((unsigned long)vmx_bitmap[i]);
8003
8004     return r;
8005 }
8006
8007 static __exit void hardware_unsetup(void)
8008 {
8009         int i;
8010
8011         for (i = 0; i < VMX_BITMAP_NR; i++)
8012                 free_page((unsigned long)vmx_bitmap[i]);
8013
8014         free_kvm_area();
8015 }
8016
8017 /*
8018  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
8019  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
8020  */
8021 static int handle_pause(struct kvm_vcpu *vcpu)
8022 {
8023         if (!kvm_pause_in_guest(vcpu->kvm))
8024                 grow_ple_window(vcpu);
8025
8026         /*
8027          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
8028          * VM-execution control is ignored if CPL > 0. OTOH, KVM
8029          * never set PAUSE_EXITING and just set PLE if supported,
8030          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
8031          */
8032         kvm_vcpu_on_spin(vcpu, true);
8033         return kvm_skip_emulated_instruction(vcpu);
8034 }
8035
8036 static int handle_nop(struct kvm_vcpu *vcpu)
8037 {
8038         return kvm_skip_emulated_instruction(vcpu);
8039 }
8040
8041 static int handle_mwait(struct kvm_vcpu *vcpu)
8042 {
8043         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
8044         return handle_nop(vcpu);
8045 }
8046
8047 static int handle_invalid_op(struct kvm_vcpu *vcpu)
8048 {
8049         kvm_queue_exception(vcpu, UD_VECTOR);
8050         return 1;
8051 }
8052
8053 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
8054 {
8055         return 1;
8056 }
8057
8058 static int handle_monitor(struct kvm_vcpu *vcpu)
8059 {
8060         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
8061         return handle_nop(vcpu);
8062 }
8063
8064 /*
8065  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
8066  * set the success or error code of an emulated VMX instruction, as specified
8067  * by Vol 2B, VMX Instruction Reference, "Conventions".
8068  */
8069 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
8070 {
8071         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
8072                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
8073                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
8074 }
8075
8076 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
8077 {
8078         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
8079                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
8080                             X86_EFLAGS_SF | X86_EFLAGS_OF))
8081                         | X86_EFLAGS_CF);
8082 }
8083
8084 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
8085                                         u32 vm_instruction_error)
8086 {
8087         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
8088                 /*
8089                  * failValid writes the error number to the current VMCS, which
8090                  * can't be done there isn't a current VMCS.
8091                  */
8092                 nested_vmx_failInvalid(vcpu);
8093                 return;
8094         }
8095         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
8096                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
8097                             X86_EFLAGS_SF | X86_EFLAGS_OF))
8098                         | X86_EFLAGS_ZF);
8099         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
8100         /*
8101          * We don't need to force a shadow sync because
8102          * VM_INSTRUCTION_ERROR is not shadowed
8103          */
8104 }
8105
8106 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
8107 {
8108         /* TODO: not to reset guest simply here. */
8109         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8110         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
8111 }
8112
8113 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
8114 {
8115         struct vcpu_vmx *vmx =
8116                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
8117
8118         vmx->nested.preemption_timer_expired = true;
8119         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
8120         kvm_vcpu_kick(&vmx->vcpu);
8121
8122         return HRTIMER_NORESTART;
8123 }
8124
8125 /*
8126  * Decode the memory-address operand of a vmx instruction, as recorded on an
8127  * exit caused by such an instruction (run by a guest hypervisor).
8128  * On success, returns 0. When the operand is invalid, returns 1 and throws
8129  * #UD or #GP.
8130  */
8131 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
8132                                  unsigned long exit_qualification,
8133                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
8134 {
8135         gva_t off;
8136         bool exn;
8137         struct kvm_segment s;
8138
8139         /*
8140          * According to Vol. 3B, "Information for VM Exits Due to Instruction
8141          * Execution", on an exit, vmx_instruction_info holds most of the
8142          * addressing components of the operand. Only the displacement part
8143          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
8144          * For how an actual address is calculated from all these components,
8145          * refer to Vol. 1, "Operand Addressing".
8146          */
8147         int  scaling = vmx_instruction_info & 3;
8148         int  addr_size = (vmx_instruction_info >> 7) & 7;
8149         bool is_reg = vmx_instruction_info & (1u << 10);
8150         int  seg_reg = (vmx_instruction_info >> 15) & 7;
8151         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
8152         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
8153         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
8154         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
8155
8156         if (is_reg) {
8157                 kvm_queue_exception(vcpu, UD_VECTOR);
8158                 return 1;
8159         }
8160
8161         /* Addr = segment_base + offset */
8162         /* offset = base + [index * scale] + displacement */
8163         off = exit_qualification; /* holds the displacement */
8164         if (base_is_valid)
8165                 off += kvm_register_read(vcpu, base_reg);
8166         if (index_is_valid)
8167                 off += kvm_register_read(vcpu, index_reg)<<scaling;
8168         vmx_get_segment(vcpu, &s, seg_reg);
8169         *ret = s.base + off;
8170
8171         if (addr_size == 1) /* 32 bit */
8172                 *ret &= 0xffffffff;
8173
8174         /* Checks for #GP/#SS exceptions. */
8175         exn = false;
8176         if (is_long_mode(vcpu)) {
8177                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
8178                  * non-canonical form. This is the only check on the memory
8179                  * destination for long mode!
8180                  */
8181                 exn = is_noncanonical_address(*ret, vcpu);
8182         } else if (is_protmode(vcpu)) {
8183                 /* Protected mode: apply checks for segment validity in the
8184                  * following order:
8185                  * - segment type check (#GP(0) may be thrown)
8186                  * - usability check (#GP(0)/#SS(0))
8187                  * - limit check (#GP(0)/#SS(0))
8188                  */
8189                 if (wr)
8190                         /* #GP(0) if the destination operand is located in a
8191                          * read-only data segment or any code segment.
8192                          */
8193                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
8194                 else
8195                         /* #GP(0) if the source operand is located in an
8196                          * execute-only code segment
8197                          */
8198                         exn = ((s.type & 0xa) == 8);
8199                 if (exn) {
8200                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8201                         return 1;
8202                 }
8203                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
8204                  */
8205                 exn = (s.unusable != 0);
8206                 /* Protected mode: #GP(0)/#SS(0) if the memory
8207                  * operand is outside the segment limit.
8208                  */
8209                 exn = exn || (off + sizeof(u64) > s.limit);
8210         }
8211         if (exn) {
8212                 kvm_queue_exception_e(vcpu,
8213                                       seg_reg == VCPU_SREG_SS ?
8214                                                 SS_VECTOR : GP_VECTOR,
8215                                       0);
8216                 return 1;
8217         }
8218
8219         return 0;
8220 }
8221
8222 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
8223 {
8224         gva_t gva;
8225         struct x86_exception e;
8226
8227         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8228                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
8229                 return 1;
8230
8231         if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) {
8232                 kvm_inject_page_fault(vcpu, &e);
8233                 return 1;
8234         }
8235
8236         return 0;
8237 }
8238
8239 /*
8240  * Allocate a shadow VMCS and associate it with the currently loaded
8241  * VMCS, unless such a shadow VMCS already exists. The newly allocated
8242  * VMCS is also VMCLEARed, so that it is ready for use.
8243  */
8244 static struct vmcs *alloc_shadow_vmcs(struct kvm_vcpu *vcpu)
8245 {
8246         struct vcpu_vmx *vmx = to_vmx(vcpu);
8247         struct loaded_vmcs *loaded_vmcs = vmx->loaded_vmcs;
8248
8249         /*
8250          * We should allocate a shadow vmcs for vmcs01 only when L1
8251          * executes VMXON and free it when L1 executes VMXOFF.
8252          * As it is invalid to execute VMXON twice, we shouldn't reach
8253          * here when vmcs01 already have an allocated shadow vmcs.
8254          */
8255         WARN_ON(loaded_vmcs == &vmx->vmcs01 && loaded_vmcs->shadow_vmcs);
8256
8257         if (!loaded_vmcs->shadow_vmcs) {
8258                 loaded_vmcs->shadow_vmcs = alloc_vmcs(true);
8259                 if (loaded_vmcs->shadow_vmcs)
8260                         vmcs_clear(loaded_vmcs->shadow_vmcs);
8261         }
8262         return loaded_vmcs->shadow_vmcs;
8263 }
8264
8265 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
8266 {
8267         struct vcpu_vmx *vmx = to_vmx(vcpu);
8268         int r;
8269
8270         r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
8271         if (r < 0)
8272                 goto out_vmcs02;
8273
8274         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
8275         if (!vmx->nested.cached_vmcs12)
8276                 goto out_cached_vmcs12;
8277
8278         vmx->nested.cached_shadow_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
8279         if (!vmx->nested.cached_shadow_vmcs12)
8280                 goto out_cached_shadow_vmcs12;
8281
8282         if (enable_shadow_vmcs && !alloc_shadow_vmcs(vcpu))
8283                 goto out_shadow_vmcs;
8284
8285         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
8286                      HRTIMER_MODE_REL_PINNED);
8287         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
8288
8289         vmx->nested.vpid02 = allocate_vpid();
8290
8291         vmx->nested.vmxon = true;
8292         return 0;
8293
8294 out_shadow_vmcs:
8295         kfree(vmx->nested.cached_shadow_vmcs12);
8296
8297 out_cached_shadow_vmcs12:
8298         kfree(vmx->nested.cached_vmcs12);
8299
8300 out_cached_vmcs12:
8301         free_loaded_vmcs(&vmx->nested.vmcs02);
8302
8303 out_vmcs02:
8304         return -ENOMEM;
8305 }
8306
8307 /*
8308  * Emulate the VMXON instruction.
8309  * Currently, we just remember that VMX is active, and do not save or even
8310  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
8311  * do not currently need to store anything in that guest-allocated memory
8312  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
8313  * argument is different from the VMXON pointer (which the spec says they do).
8314  */
8315 static int handle_vmon(struct kvm_vcpu *vcpu)
8316 {
8317         int ret;
8318         gpa_t vmptr;
8319         struct page *page;
8320         struct vcpu_vmx *vmx = to_vmx(vcpu);
8321         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
8322                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
8323
8324         /*
8325          * The Intel VMX Instruction Reference lists a bunch of bits that are
8326          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
8327          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
8328          * Otherwise, we should fail with #UD.  But most faulting conditions
8329          * have already been checked by hardware, prior to the VM-exit for
8330          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
8331          * that bit set to 1 in non-root mode.
8332          */
8333         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
8334                 kvm_queue_exception(vcpu, UD_VECTOR);
8335                 return 1;
8336         }
8337
8338         /* CPL=0 must be checked manually. */
8339         if (vmx_get_cpl(vcpu)) {
8340                 kvm_inject_gp(vcpu, 0);
8341                 return 1;
8342         }
8343
8344         if (vmx->nested.vmxon) {
8345                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
8346                 return kvm_skip_emulated_instruction(vcpu);
8347         }
8348
8349         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
8350                         != VMXON_NEEDED_FEATURES) {
8351                 kvm_inject_gp(vcpu, 0);
8352                 return 1;
8353         }
8354
8355         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8356                 return 1;
8357
8358         /*
8359          * SDM 3: 24.11.5
8360          * The first 4 bytes of VMXON region contain the supported
8361          * VMCS revision identifier
8362          *
8363          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
8364          * which replaces physical address width with 32
8365          */
8366         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8367                 nested_vmx_failInvalid(vcpu);
8368                 return kvm_skip_emulated_instruction(vcpu);
8369         }
8370
8371         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8372         if (is_error_page(page)) {
8373                 nested_vmx_failInvalid(vcpu);
8374                 return kvm_skip_emulated_instruction(vcpu);
8375         }
8376         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
8377                 kunmap(page);
8378                 kvm_release_page_clean(page);
8379                 nested_vmx_failInvalid(vcpu);
8380                 return kvm_skip_emulated_instruction(vcpu);
8381         }
8382         kunmap(page);
8383         kvm_release_page_clean(page);
8384
8385         vmx->nested.vmxon_ptr = vmptr;
8386         ret = enter_vmx_operation(vcpu);
8387         if (ret)
8388                 return ret;
8389
8390         nested_vmx_succeed(vcpu);
8391         return kvm_skip_emulated_instruction(vcpu);
8392 }
8393
8394 /*
8395  * Intel's VMX Instruction Reference specifies a common set of prerequisites
8396  * for running VMX instructions (except VMXON, whose prerequisites are
8397  * slightly different). It also specifies what exception to inject otherwise.
8398  * Note that many of these exceptions have priority over VM exits, so they
8399  * don't have to be checked again here.
8400  */
8401 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
8402 {
8403         if (!to_vmx(vcpu)->nested.vmxon) {
8404                 kvm_queue_exception(vcpu, UD_VECTOR);
8405                 return 0;
8406         }
8407
8408         if (vmx_get_cpl(vcpu)) {
8409                 kvm_inject_gp(vcpu, 0);
8410                 return 0;
8411         }
8412
8413         return 1;
8414 }
8415
8416 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
8417 {
8418         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
8419         vmcs_write64(VMCS_LINK_POINTER, -1ull);
8420 }
8421
8422 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
8423 {
8424         if (vmx->nested.current_vmptr == -1ull)
8425                 return;
8426
8427         if (enable_shadow_vmcs) {
8428                 /* copy to memory all shadowed fields in case
8429                    they were modified */
8430                 copy_shadow_to_vmcs12(vmx);
8431                 vmx->nested.sync_shadow_vmcs = false;
8432                 vmx_disable_shadow_vmcs(vmx);
8433         }
8434         vmx->nested.posted_intr_nv = -1;
8435
8436         /* Flush VMCS12 to guest memory */
8437         kvm_vcpu_write_guest_page(&vmx->vcpu,
8438                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
8439                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
8440
8441         vmx->nested.current_vmptr = -1ull;
8442 }
8443
8444 /*
8445  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
8446  * just stops using VMX.
8447  */
8448 static void free_nested(struct vcpu_vmx *vmx)
8449 {
8450         if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
8451                 return;
8452
8453         vmx->nested.vmxon = false;
8454         vmx->nested.smm.vmxon = false;
8455         free_vpid(vmx->nested.vpid02);
8456         vmx->nested.posted_intr_nv = -1;
8457         vmx->nested.current_vmptr = -1ull;
8458         if (enable_shadow_vmcs) {
8459                 vmx_disable_shadow_vmcs(vmx);
8460                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
8461                 free_vmcs(vmx->vmcs01.shadow_vmcs);
8462                 vmx->vmcs01.shadow_vmcs = NULL;
8463         }
8464         kfree(vmx->nested.cached_vmcs12);
8465         kfree(vmx->nested.cached_shadow_vmcs12);
8466         /* Unpin physical memory we referred to in the vmcs02 */
8467         if (vmx->nested.apic_access_page) {
8468                 kvm_release_page_dirty(vmx->nested.apic_access_page);
8469                 vmx->nested.apic_access_page = NULL;
8470         }
8471         if (vmx->nested.virtual_apic_page) {
8472                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
8473                 vmx->nested.virtual_apic_page = NULL;
8474         }
8475         if (vmx->nested.pi_desc_page) {
8476                 kunmap(vmx->nested.pi_desc_page);
8477                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
8478                 vmx->nested.pi_desc_page = NULL;
8479                 vmx->nested.pi_desc = NULL;
8480         }
8481
8482         free_loaded_vmcs(&vmx->nested.vmcs02);
8483 }
8484
8485 /* Emulate the VMXOFF instruction */
8486 static int handle_vmoff(struct kvm_vcpu *vcpu)
8487 {
8488         if (!nested_vmx_check_permission(vcpu))
8489                 return 1;
8490         free_nested(to_vmx(vcpu));
8491         nested_vmx_succeed(vcpu);
8492         return kvm_skip_emulated_instruction(vcpu);
8493 }
8494
8495 /* Emulate the VMCLEAR instruction */
8496 static int handle_vmclear(struct kvm_vcpu *vcpu)
8497 {
8498         struct vcpu_vmx *vmx = to_vmx(vcpu);
8499         u32 zero = 0;
8500         gpa_t vmptr;
8501
8502         if (!nested_vmx_check_permission(vcpu))
8503                 return 1;
8504
8505         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8506                 return 1;
8507
8508         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8509                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
8510                 return kvm_skip_emulated_instruction(vcpu);
8511         }
8512
8513         if (vmptr == vmx->nested.vmxon_ptr) {
8514                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
8515                 return kvm_skip_emulated_instruction(vcpu);
8516         }
8517
8518         if (vmptr == vmx->nested.current_vmptr)
8519                 nested_release_vmcs12(vmx);
8520
8521         kvm_vcpu_write_guest(vcpu,
8522                         vmptr + offsetof(struct vmcs12, launch_state),
8523                         &zero, sizeof(zero));
8524
8525         nested_vmx_succeed(vcpu);
8526         return kvm_skip_emulated_instruction(vcpu);
8527 }
8528
8529 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
8530
8531 /* Emulate the VMLAUNCH instruction */
8532 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
8533 {
8534         return nested_vmx_run(vcpu, true);
8535 }
8536
8537 /* Emulate the VMRESUME instruction */
8538 static int handle_vmresume(struct kvm_vcpu *vcpu)
8539 {
8540
8541         return nested_vmx_run(vcpu, false);
8542 }
8543
8544 /*
8545  * Read a vmcs12 field. Since these can have varying lengths and we return
8546  * one type, we chose the biggest type (u64) and zero-extend the return value
8547  * to that size. Note that the caller, handle_vmread, might need to use only
8548  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
8549  * 64-bit fields are to be returned).
8550  */
8551 static inline int vmcs12_read_any(struct vmcs12 *vmcs12,
8552                                   unsigned long field, u64 *ret)
8553 {
8554         short offset = vmcs_field_to_offset(field);
8555         char *p;
8556
8557         if (offset < 0)
8558                 return offset;
8559
8560         p = (char *)vmcs12 + offset;
8561
8562         switch (vmcs_field_width(field)) {
8563         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8564                 *ret = *((natural_width *)p);
8565                 return 0;
8566         case VMCS_FIELD_WIDTH_U16:
8567                 *ret = *((u16 *)p);
8568                 return 0;
8569         case VMCS_FIELD_WIDTH_U32:
8570                 *ret = *((u32 *)p);
8571                 return 0;
8572         case VMCS_FIELD_WIDTH_U64:
8573                 *ret = *((u64 *)p);
8574                 return 0;
8575         default:
8576                 WARN_ON(1);
8577                 return -ENOENT;
8578         }
8579 }
8580
8581
8582 static inline int vmcs12_write_any(struct vmcs12 *vmcs12,
8583                                    unsigned long field, u64 field_value){
8584         short offset = vmcs_field_to_offset(field);
8585         char *p = (char *)vmcs12 + offset;
8586         if (offset < 0)
8587                 return offset;
8588
8589         switch (vmcs_field_width(field)) {
8590         case VMCS_FIELD_WIDTH_U16:
8591                 *(u16 *)p = field_value;
8592                 return 0;
8593         case VMCS_FIELD_WIDTH_U32:
8594                 *(u32 *)p = field_value;
8595                 return 0;
8596         case VMCS_FIELD_WIDTH_U64:
8597                 *(u64 *)p = field_value;
8598                 return 0;
8599         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8600                 *(natural_width *)p = field_value;
8601                 return 0;
8602         default:
8603                 WARN_ON(1);
8604                 return -ENOENT;
8605         }
8606
8607 }
8608
8609 /*
8610  * Copy the writable VMCS shadow fields back to the VMCS12, in case
8611  * they have been modified by the L1 guest. Note that the "read-only"
8612  * VM-exit information fields are actually writable if the vCPU is
8613  * configured to support "VMWRITE to any supported field in the VMCS."
8614  */
8615 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
8616 {
8617         const u16 *fields[] = {
8618                 shadow_read_write_fields,
8619                 shadow_read_only_fields
8620         };
8621         const int max_fields[] = {
8622                 max_shadow_read_write_fields,
8623                 max_shadow_read_only_fields
8624         };
8625         int i, q;
8626         unsigned long field;
8627         u64 field_value;
8628         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8629
8630         preempt_disable();
8631
8632         vmcs_load(shadow_vmcs);
8633
8634         for (q = 0; q < ARRAY_SIZE(fields); q++) {
8635                 for (i = 0; i < max_fields[q]; i++) {
8636                         field = fields[q][i];
8637                         field_value = __vmcs_readl(field);
8638                         vmcs12_write_any(get_vmcs12(&vmx->vcpu), field, field_value);
8639                 }
8640                 /*
8641                  * Skip the VM-exit information fields if they are read-only.
8642                  */
8643                 if (!nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
8644                         break;
8645         }
8646
8647         vmcs_clear(shadow_vmcs);
8648         vmcs_load(vmx->loaded_vmcs->vmcs);
8649
8650         preempt_enable();
8651 }
8652
8653 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
8654 {
8655         const u16 *fields[] = {
8656                 shadow_read_write_fields,
8657                 shadow_read_only_fields
8658         };
8659         const int max_fields[] = {
8660                 max_shadow_read_write_fields,
8661                 max_shadow_read_only_fields
8662         };
8663         int i, q;
8664         unsigned long field;
8665         u64 field_value = 0;
8666         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8667
8668         vmcs_load(shadow_vmcs);
8669
8670         for (q = 0; q < ARRAY_SIZE(fields); q++) {
8671                 for (i = 0; i < max_fields[q]; i++) {
8672                         field = fields[q][i];
8673                         vmcs12_read_any(get_vmcs12(&vmx->vcpu), field, &field_value);
8674                         __vmcs_writel(field, field_value);
8675                 }
8676         }
8677
8678         vmcs_clear(shadow_vmcs);
8679         vmcs_load(vmx->loaded_vmcs->vmcs);
8680 }
8681
8682 /*
8683  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
8684  * used before) all generate the same failure when it is missing.
8685  */
8686 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
8687 {
8688         struct vcpu_vmx *vmx = to_vmx(vcpu);
8689         if (vmx->nested.current_vmptr == -1ull) {
8690                 nested_vmx_failInvalid(vcpu);
8691                 return 0;
8692         }
8693         return 1;
8694 }
8695
8696 static int handle_vmread(struct kvm_vcpu *vcpu)
8697 {
8698         unsigned long field;
8699         u64 field_value;
8700         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8701         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8702         gva_t gva = 0;
8703         struct vmcs12 *vmcs12;
8704
8705         if (!nested_vmx_check_permission(vcpu))
8706                 return 1;
8707
8708         if (!nested_vmx_check_vmcs12(vcpu))
8709                 return kvm_skip_emulated_instruction(vcpu);
8710
8711         if (!is_guest_mode(vcpu))
8712                 vmcs12 = get_vmcs12(vcpu);
8713         else {
8714                 /*
8715                  * When vmcs->vmcs_link_pointer is -1ull, any VMREAD
8716                  * to shadowed-field sets the ALU flags for VMfailInvalid.
8717                  */
8718                 if (get_vmcs12(vcpu)->vmcs_link_pointer == -1ull) {
8719                         nested_vmx_failInvalid(vcpu);
8720                         return kvm_skip_emulated_instruction(vcpu);
8721                 }
8722                 vmcs12 = get_shadow_vmcs12(vcpu);
8723         }
8724
8725         /* Decode instruction info and find the field to read */
8726         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8727         /* Read the field, zero-extended to a u64 field_value */
8728         if (vmcs12_read_any(vmcs12, field, &field_value) < 0) {
8729                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8730                 return kvm_skip_emulated_instruction(vcpu);
8731         }
8732         /*
8733          * Now copy part of this value to register or memory, as requested.
8734          * Note that the number of bits actually copied is 32 or 64 depending
8735          * on the guest's mode (32 or 64 bit), not on the given field's length.
8736          */
8737         if (vmx_instruction_info & (1u << 10)) {
8738                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
8739                         field_value);
8740         } else {
8741                 if (get_vmx_mem_address(vcpu, exit_qualification,
8742                                 vmx_instruction_info, true, &gva))
8743                         return 1;
8744                 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
8745                 kvm_write_guest_virt_system(vcpu, gva, &field_value,
8746                                             (is_long_mode(vcpu) ? 8 : 4), NULL);
8747         }
8748
8749         nested_vmx_succeed(vcpu);
8750         return kvm_skip_emulated_instruction(vcpu);
8751 }
8752
8753
8754 static int handle_vmwrite(struct kvm_vcpu *vcpu)
8755 {
8756         unsigned long field;
8757         gva_t gva;
8758         struct vcpu_vmx *vmx = to_vmx(vcpu);
8759         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8760         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8761
8762         /* The value to write might be 32 or 64 bits, depending on L1's long
8763          * mode, and eventually we need to write that into a field of several
8764          * possible lengths. The code below first zero-extends the value to 64
8765          * bit (field_value), and then copies only the appropriate number of
8766          * bits into the vmcs12 field.
8767          */
8768         u64 field_value = 0;
8769         struct x86_exception e;
8770         struct vmcs12 *vmcs12;
8771
8772         if (!nested_vmx_check_permission(vcpu))
8773                 return 1;
8774
8775         if (!nested_vmx_check_vmcs12(vcpu))
8776                 return kvm_skip_emulated_instruction(vcpu);
8777
8778         if (vmx_instruction_info & (1u << 10))
8779                 field_value = kvm_register_readl(vcpu,
8780                         (((vmx_instruction_info) >> 3) & 0xf));
8781         else {
8782                 if (get_vmx_mem_address(vcpu, exit_qualification,
8783                                 vmx_instruction_info, false, &gva))
8784                         return 1;
8785                 if (kvm_read_guest_virt(vcpu, gva, &field_value,
8786                                         (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
8787                         kvm_inject_page_fault(vcpu, &e);
8788                         return 1;
8789                 }
8790         }
8791
8792
8793         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8794         /*
8795          * If the vCPU supports "VMWRITE to any supported field in the
8796          * VMCS," then the "read-only" fields are actually read/write.
8797          */
8798         if (vmcs_field_readonly(field) &&
8799             !nested_cpu_has_vmwrite_any_field(vcpu)) {
8800                 nested_vmx_failValid(vcpu,
8801                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
8802                 return kvm_skip_emulated_instruction(vcpu);
8803         }
8804
8805         if (!is_guest_mode(vcpu))
8806                 vmcs12 = get_vmcs12(vcpu);
8807         else {
8808                 /*
8809                  * When vmcs->vmcs_link_pointer is -1ull, any VMWRITE
8810                  * to shadowed-field sets the ALU flags for VMfailInvalid.
8811                  */
8812                 if (get_vmcs12(vcpu)->vmcs_link_pointer == -1ull) {
8813                         nested_vmx_failInvalid(vcpu);
8814                         return kvm_skip_emulated_instruction(vcpu);
8815                 }
8816                 vmcs12 = get_shadow_vmcs12(vcpu);
8817
8818         }
8819
8820         if (vmcs12_write_any(vmcs12, field, field_value) < 0) {
8821                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8822                 return kvm_skip_emulated_instruction(vcpu);
8823         }
8824
8825         /*
8826          * Do not track vmcs12 dirty-state if in guest-mode
8827          * as we actually dirty shadow vmcs12 instead of vmcs12.
8828          */
8829         if (!is_guest_mode(vcpu)) {
8830                 switch (field) {
8831 #define SHADOW_FIELD_RW(x) case x:
8832 #include "vmx_shadow_fields.h"
8833                         /*
8834                          * The fields that can be updated by L1 without a vmexit are
8835                          * always updated in the vmcs02, the others go down the slow
8836                          * path of prepare_vmcs02.
8837                          */
8838                         break;
8839                 default:
8840                         vmx->nested.dirty_vmcs12 = true;
8841                         break;
8842                 }
8843         }
8844
8845         nested_vmx_succeed(vcpu);
8846         return kvm_skip_emulated_instruction(vcpu);
8847 }
8848
8849 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
8850 {
8851         vmx->nested.current_vmptr = vmptr;
8852         if (enable_shadow_vmcs) {
8853                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
8854                               SECONDARY_EXEC_SHADOW_VMCS);
8855                 vmcs_write64(VMCS_LINK_POINTER,
8856                              __pa(vmx->vmcs01.shadow_vmcs));
8857                 vmx->nested.sync_shadow_vmcs = true;
8858         }
8859         vmx->nested.dirty_vmcs12 = true;
8860 }
8861
8862 /* Emulate the VMPTRLD instruction */
8863 static int handle_vmptrld(struct kvm_vcpu *vcpu)
8864 {
8865         struct vcpu_vmx *vmx = to_vmx(vcpu);
8866         gpa_t vmptr;
8867
8868         if (!nested_vmx_check_permission(vcpu))
8869                 return 1;
8870
8871         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8872                 return 1;
8873
8874         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8875                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
8876                 return kvm_skip_emulated_instruction(vcpu);
8877         }
8878
8879         if (vmptr == vmx->nested.vmxon_ptr) {
8880                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
8881                 return kvm_skip_emulated_instruction(vcpu);
8882         }
8883
8884         if (vmx->nested.current_vmptr != vmptr) {
8885                 struct vmcs12 *new_vmcs12;
8886                 struct page *page;
8887                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8888                 if (is_error_page(page)) {
8889                         nested_vmx_failInvalid(vcpu);
8890                         return kvm_skip_emulated_instruction(vcpu);
8891                 }
8892                 new_vmcs12 = kmap(page);
8893                 if (new_vmcs12->hdr.revision_id != VMCS12_REVISION ||
8894                     (new_vmcs12->hdr.shadow_vmcs &&
8895                      !nested_cpu_has_vmx_shadow_vmcs(vcpu))) {
8896                         kunmap(page);
8897                         kvm_release_page_clean(page);
8898                         nested_vmx_failValid(vcpu,
8899                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
8900                         return kvm_skip_emulated_instruction(vcpu);
8901                 }
8902
8903                 nested_release_vmcs12(vmx);
8904                 /*
8905                  * Load VMCS12 from guest memory since it is not already
8906                  * cached.
8907                  */
8908                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
8909                 kunmap(page);
8910                 kvm_release_page_clean(page);
8911
8912                 set_current_vmptr(vmx, vmptr);
8913         }
8914
8915         nested_vmx_succeed(vcpu);
8916         return kvm_skip_emulated_instruction(vcpu);
8917 }
8918
8919 /* Emulate the VMPTRST instruction */
8920 static int handle_vmptrst(struct kvm_vcpu *vcpu)
8921 {
8922         unsigned long exit_qual = vmcs_readl(EXIT_QUALIFICATION);
8923         u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8924         gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr;
8925         struct x86_exception e;
8926         gva_t gva;
8927
8928         if (!nested_vmx_check_permission(vcpu))
8929                 return 1;
8930
8931         if (get_vmx_mem_address(vcpu, exit_qual, instr_info, true, &gva))
8932                 return 1;
8933         /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
8934         if (kvm_write_guest_virt_system(vcpu, gva, (void *)&current_vmptr,
8935                                         sizeof(gpa_t), &e)) {
8936                 kvm_inject_page_fault(vcpu, &e);
8937                 return 1;
8938         }
8939         nested_vmx_succeed(vcpu);
8940         return kvm_skip_emulated_instruction(vcpu);
8941 }
8942
8943 /* Emulate the INVEPT instruction */
8944 static int handle_invept(struct kvm_vcpu *vcpu)
8945 {
8946         struct vcpu_vmx *vmx = to_vmx(vcpu);
8947         u32 vmx_instruction_info, types;
8948         unsigned long type;
8949         gva_t gva;
8950         struct x86_exception e;
8951         struct {
8952                 u64 eptp, gpa;
8953         } operand;
8954
8955         if (!(vmx->nested.msrs.secondary_ctls_high &
8956               SECONDARY_EXEC_ENABLE_EPT) ||
8957             !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
8958                 kvm_queue_exception(vcpu, UD_VECTOR);
8959                 return 1;
8960         }
8961
8962         if (!nested_vmx_check_permission(vcpu))
8963                 return 1;
8964
8965         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8966         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8967
8968         types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
8969
8970         if (type >= 32 || !(types & (1 << type))) {
8971                 nested_vmx_failValid(vcpu,
8972                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8973                 return kvm_skip_emulated_instruction(vcpu);
8974         }
8975
8976         /* According to the Intel VMX instruction reference, the memory
8977          * operand is read even if it isn't needed (e.g., for type==global)
8978          */
8979         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8980                         vmx_instruction_info, false, &gva))
8981                 return 1;
8982         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8983                 kvm_inject_page_fault(vcpu, &e);
8984                 return 1;
8985         }
8986
8987         switch (type) {
8988         case VMX_EPT_EXTENT_GLOBAL:
8989         /*
8990          * TODO: track mappings and invalidate
8991          * single context requests appropriately
8992          */
8993         case VMX_EPT_EXTENT_CONTEXT:
8994                 kvm_mmu_sync_roots(vcpu);
8995                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
8996                 nested_vmx_succeed(vcpu);
8997                 break;
8998         default:
8999                 BUG_ON(1);
9000                 break;
9001         }
9002
9003         return kvm_skip_emulated_instruction(vcpu);
9004 }
9005
9006 static int handle_invvpid(struct kvm_vcpu *vcpu)
9007 {
9008         struct vcpu_vmx *vmx = to_vmx(vcpu);
9009         u32 vmx_instruction_info;
9010         unsigned long type, types;
9011         gva_t gva;
9012         struct x86_exception e;
9013         struct {
9014                 u64 vpid;
9015                 u64 gla;
9016         } operand;
9017
9018         if (!(vmx->nested.msrs.secondary_ctls_high &
9019               SECONDARY_EXEC_ENABLE_VPID) ||
9020                         !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
9021                 kvm_queue_exception(vcpu, UD_VECTOR);
9022                 return 1;
9023         }
9024
9025         if (!nested_vmx_check_permission(vcpu))
9026                 return 1;
9027
9028         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9029         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
9030
9031         types = (vmx->nested.msrs.vpid_caps &
9032                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
9033
9034         if (type >= 32 || !(types & (1 << type))) {
9035                 nested_vmx_failValid(vcpu,
9036                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9037                 return kvm_skip_emulated_instruction(vcpu);
9038         }
9039
9040         /* according to the intel vmx instruction reference, the memory
9041          * operand is read even if it isn't needed (e.g., for type==global)
9042          */
9043         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
9044                         vmx_instruction_info, false, &gva))
9045                 return 1;
9046         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
9047                 kvm_inject_page_fault(vcpu, &e);
9048                 return 1;
9049         }
9050         if (operand.vpid >> 16) {
9051                 nested_vmx_failValid(vcpu,
9052                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9053                 return kvm_skip_emulated_instruction(vcpu);
9054         }
9055
9056         switch (type) {
9057         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
9058                 if (!operand.vpid ||
9059                     is_noncanonical_address(operand.gla, vcpu)) {
9060                         nested_vmx_failValid(vcpu,
9061                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9062                         return kvm_skip_emulated_instruction(vcpu);
9063                 }
9064                 if (cpu_has_vmx_invvpid_individual_addr() &&
9065                     vmx->nested.vpid02) {
9066                         __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR,
9067                                 vmx->nested.vpid02, operand.gla);
9068                 } else
9069                         __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
9070                 break;
9071         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
9072         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
9073                 if (!operand.vpid) {
9074                         nested_vmx_failValid(vcpu,
9075                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9076                         return kvm_skip_emulated_instruction(vcpu);
9077                 }
9078                 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
9079                 break;
9080         case VMX_VPID_EXTENT_ALL_CONTEXT:
9081                 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
9082                 break;
9083         default:
9084                 WARN_ON_ONCE(1);
9085                 return kvm_skip_emulated_instruction(vcpu);
9086         }
9087
9088         nested_vmx_succeed(vcpu);
9089
9090         return kvm_skip_emulated_instruction(vcpu);
9091 }
9092
9093 static int handle_invpcid(struct kvm_vcpu *vcpu)
9094 {
9095         u32 vmx_instruction_info;
9096         unsigned long type;
9097         bool pcid_enabled;
9098         gva_t gva;
9099         struct x86_exception e;
9100         unsigned i;
9101         unsigned long roots_to_free = 0;
9102         struct {
9103                 u64 pcid;
9104                 u64 gla;
9105         } operand;
9106
9107         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
9108                 kvm_queue_exception(vcpu, UD_VECTOR);
9109                 return 1;
9110         }
9111
9112         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9113         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
9114
9115         if (type > 3) {
9116                 kvm_inject_gp(vcpu, 0);
9117                 return 1;
9118         }
9119
9120         /* According to the Intel instruction reference, the memory operand
9121          * is read even if it isn't needed (e.g., for type==all)
9122          */
9123         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
9124                                 vmx_instruction_info, false, &gva))
9125                 return 1;
9126
9127         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
9128                 kvm_inject_page_fault(vcpu, &e);
9129                 return 1;
9130         }
9131
9132         if (operand.pcid >> 12 != 0) {
9133                 kvm_inject_gp(vcpu, 0);
9134                 return 1;
9135         }
9136
9137         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
9138
9139         switch (type) {
9140         case INVPCID_TYPE_INDIV_ADDR:
9141                 if ((!pcid_enabled && (operand.pcid != 0)) ||
9142                     is_noncanonical_address(operand.gla, vcpu)) {
9143                         kvm_inject_gp(vcpu, 0);
9144                         return 1;
9145                 }
9146                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
9147                 return kvm_skip_emulated_instruction(vcpu);
9148
9149         case INVPCID_TYPE_SINGLE_CTXT:
9150                 if (!pcid_enabled && (operand.pcid != 0)) {
9151                         kvm_inject_gp(vcpu, 0);
9152                         return 1;
9153                 }
9154
9155                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
9156                         kvm_mmu_sync_roots(vcpu);
9157                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
9158                 }
9159
9160                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
9161                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu.prev_roots[i].cr3)
9162                             == operand.pcid)
9163                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
9164
9165                 kvm_mmu_free_roots(vcpu, roots_to_free);
9166                 /*
9167                  * If neither the current cr3 nor any of the prev_roots use the
9168                  * given PCID, then nothing needs to be done here because a
9169                  * resync will happen anyway before switching to any other CR3.
9170                  */
9171
9172                 return kvm_skip_emulated_instruction(vcpu);
9173
9174         case INVPCID_TYPE_ALL_NON_GLOBAL:
9175                 /*
9176                  * Currently, KVM doesn't mark global entries in the shadow
9177                  * page tables, so a non-global flush just degenerates to a
9178                  * global flush. If needed, we could optimize this later by
9179                  * keeping track of global entries in shadow page tables.
9180                  */
9181
9182                 /* fall-through */
9183         case INVPCID_TYPE_ALL_INCL_GLOBAL:
9184                 kvm_mmu_unload(vcpu);
9185                 return kvm_skip_emulated_instruction(vcpu);
9186
9187         default:
9188                 BUG(); /* We have already checked above that type <= 3 */
9189         }
9190 }
9191
9192 static int handle_pml_full(struct kvm_vcpu *vcpu)
9193 {
9194         unsigned long exit_qualification;
9195
9196         trace_kvm_pml_full(vcpu->vcpu_id);
9197
9198         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9199
9200         /*
9201          * PML buffer FULL happened while executing iret from NMI,
9202          * "blocked by NMI" bit has to be set before next VM entry.
9203          */
9204         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
9205                         enable_vnmi &&
9206                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
9207                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9208                                 GUEST_INTR_STATE_NMI);
9209
9210         /*
9211          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
9212          * here.., and there's no userspace involvement needed for PML.
9213          */
9214         return 1;
9215 }
9216
9217 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
9218 {
9219         if (!to_vmx(vcpu)->req_immediate_exit)
9220                 kvm_lapic_expired_hv_timer(vcpu);
9221         return 1;
9222 }
9223
9224 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
9225 {
9226         struct vcpu_vmx *vmx = to_vmx(vcpu);
9227         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9228
9229         /* Check for memory type validity */
9230         switch (address & VMX_EPTP_MT_MASK) {
9231         case VMX_EPTP_MT_UC:
9232                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))
9233                         return false;
9234                 break;
9235         case VMX_EPTP_MT_WB:
9236                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))
9237                         return false;
9238                 break;
9239         default:
9240                 return false;
9241         }
9242
9243         /* only 4 levels page-walk length are valid */
9244         if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
9245                 return false;
9246
9247         /* Reserved bits should not be set */
9248         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
9249                 return false;
9250
9251         /* AD, if set, should be supported */
9252         if (address & VMX_EPTP_AD_ENABLE_BIT) {
9253                 if (!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))
9254                         return false;
9255         }
9256
9257         return true;
9258 }
9259
9260 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
9261                                      struct vmcs12 *vmcs12)
9262 {
9263         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
9264         u64 address;
9265         bool accessed_dirty;
9266         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
9267
9268         if (!nested_cpu_has_eptp_switching(vmcs12) ||
9269             !nested_cpu_has_ept(vmcs12))
9270                 return 1;
9271
9272         if (index >= VMFUNC_EPTP_ENTRIES)
9273                 return 1;
9274
9275
9276         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
9277                                      &address, index * 8, 8))
9278                 return 1;
9279
9280         accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
9281
9282         /*
9283          * If the (L2) guest does a vmfunc to the currently
9284          * active ept pointer, we don't have to do anything else
9285          */
9286         if (vmcs12->ept_pointer != address) {
9287                 if (!valid_ept_address(vcpu, address))
9288                         return 1;
9289
9290                 kvm_mmu_unload(vcpu);
9291                 mmu->ept_ad = accessed_dirty;
9292                 mmu->base_role.ad_disabled = !accessed_dirty;
9293                 vmcs12->ept_pointer = address;
9294                 /*
9295                  * TODO: Check what's the correct approach in case
9296                  * mmu reload fails. Currently, we just let the next
9297                  * reload potentially fail
9298                  */
9299                 kvm_mmu_reload(vcpu);
9300         }
9301
9302         return 0;
9303 }
9304
9305 static int handle_vmfunc(struct kvm_vcpu *vcpu)
9306 {
9307         struct vcpu_vmx *vmx = to_vmx(vcpu);
9308         struct vmcs12 *vmcs12;
9309         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
9310
9311         /*
9312          * VMFUNC is only supported for nested guests, but we always enable the
9313          * secondary control for simplicity; for non-nested mode, fake that we
9314          * didn't by injecting #UD.
9315          */
9316         if (!is_guest_mode(vcpu)) {
9317                 kvm_queue_exception(vcpu, UD_VECTOR);
9318                 return 1;
9319         }
9320
9321         vmcs12 = get_vmcs12(vcpu);
9322         if ((vmcs12->vm_function_control & (1 << function)) == 0)
9323                 goto fail;
9324
9325         switch (function) {
9326         case 0:
9327                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
9328                         goto fail;
9329                 break;
9330         default:
9331                 goto fail;
9332         }
9333         return kvm_skip_emulated_instruction(vcpu);
9334
9335 fail:
9336         nested_vmx_vmexit(vcpu, vmx->exit_reason,
9337                           vmcs_read32(VM_EXIT_INTR_INFO),
9338                           vmcs_readl(EXIT_QUALIFICATION));
9339         return 1;
9340 }
9341
9342 static int handle_encls(struct kvm_vcpu *vcpu)
9343 {
9344         /*
9345          * SGX virtualization is not yet supported.  There is no software
9346          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
9347          * to prevent the guest from executing ENCLS.
9348          */
9349         kvm_queue_exception(vcpu, UD_VECTOR);
9350         return 1;
9351 }
9352
9353 /*
9354  * The exit handlers return 1 if the exit was handled fully and guest execution
9355  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
9356  * to be done to userspace and return 0.
9357  */
9358 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
9359         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
9360         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
9361         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
9362         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
9363         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
9364         [EXIT_REASON_CR_ACCESS]               = handle_cr,
9365         [EXIT_REASON_DR_ACCESS]               = handle_dr,
9366         [EXIT_REASON_CPUID]                   = handle_cpuid,
9367         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
9368         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
9369         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
9370         [EXIT_REASON_HLT]                     = handle_halt,
9371         [EXIT_REASON_INVD]                    = handle_invd,
9372         [EXIT_REASON_INVLPG]                  = handle_invlpg,
9373         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
9374         [EXIT_REASON_VMCALL]                  = handle_vmcall,
9375         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
9376         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
9377         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
9378         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
9379         [EXIT_REASON_VMREAD]                  = handle_vmread,
9380         [EXIT_REASON_VMRESUME]                = handle_vmresume,
9381         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
9382         [EXIT_REASON_VMOFF]                   = handle_vmoff,
9383         [EXIT_REASON_VMON]                    = handle_vmon,
9384         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
9385         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
9386         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
9387         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
9388         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
9389         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
9390         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
9391         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
9392         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
9393         [EXIT_REASON_LDTR_TR]                 = handle_desc,
9394         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
9395         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
9396         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
9397         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
9398         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
9399         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
9400         [EXIT_REASON_INVEPT]                  = handle_invept,
9401         [EXIT_REASON_INVVPID]                 = handle_invvpid,
9402         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
9403         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
9404         [EXIT_REASON_XSAVES]                  = handle_xsaves,
9405         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
9406         [EXIT_REASON_PML_FULL]                = handle_pml_full,
9407         [EXIT_REASON_INVPCID]                 = handle_invpcid,
9408         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
9409         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
9410         [EXIT_REASON_ENCLS]                   = handle_encls,
9411 };
9412
9413 static const int kvm_vmx_max_exit_handlers =
9414         ARRAY_SIZE(kvm_vmx_exit_handlers);
9415
9416 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
9417                                        struct vmcs12 *vmcs12)
9418 {
9419         unsigned long exit_qualification;
9420         gpa_t bitmap, last_bitmap;
9421         unsigned int port;
9422         int size;
9423         u8 b;
9424
9425         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9426                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
9427
9428         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9429
9430         port = exit_qualification >> 16;
9431         size = (exit_qualification & 7) + 1;
9432
9433         last_bitmap = (gpa_t)-1;
9434         b = -1;
9435
9436         while (size > 0) {
9437                 if (port < 0x8000)
9438                         bitmap = vmcs12->io_bitmap_a;
9439                 else if (port < 0x10000)
9440                         bitmap = vmcs12->io_bitmap_b;
9441                 else
9442                         return true;
9443                 bitmap += (port & 0x7fff) / 8;
9444
9445                 if (last_bitmap != bitmap)
9446                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
9447                                 return true;
9448                 if (b & (1 << (port & 7)))
9449                         return true;
9450
9451                 port++;
9452                 size--;
9453                 last_bitmap = bitmap;
9454         }
9455
9456         return false;
9457 }
9458
9459 /*
9460  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
9461  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
9462  * disinterest in the current event (read or write a specific MSR) by using an
9463  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
9464  */
9465 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
9466         struct vmcs12 *vmcs12, u32 exit_reason)
9467 {
9468         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
9469         gpa_t bitmap;
9470
9471         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9472                 return true;
9473
9474         /*
9475          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
9476          * for the four combinations of read/write and low/high MSR numbers.
9477          * First we need to figure out which of the four to use:
9478          */
9479         bitmap = vmcs12->msr_bitmap;
9480         if (exit_reason == EXIT_REASON_MSR_WRITE)
9481                 bitmap += 2048;
9482         if (msr_index >= 0xc0000000) {
9483                 msr_index -= 0xc0000000;
9484                 bitmap += 1024;
9485         }
9486
9487         /* Then read the msr_index'th bit from this bitmap: */
9488         if (msr_index < 1024*8) {
9489                 unsigned char b;
9490                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
9491                         return true;
9492                 return 1 & (b >> (msr_index & 7));
9493         } else
9494                 return true; /* let L1 handle the wrong parameter */
9495 }
9496
9497 /*
9498  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
9499  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
9500  * intercept (via guest_host_mask etc.) the current event.
9501  */
9502 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
9503         struct vmcs12 *vmcs12)
9504 {
9505         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9506         int cr = exit_qualification & 15;
9507         int reg;
9508         unsigned long val;
9509
9510         switch ((exit_qualification >> 4) & 3) {
9511         case 0: /* mov to cr */
9512                 reg = (exit_qualification >> 8) & 15;
9513                 val = kvm_register_readl(vcpu, reg);
9514                 switch (cr) {
9515                 case 0:
9516                         if (vmcs12->cr0_guest_host_mask &
9517                             (val ^ vmcs12->cr0_read_shadow))
9518                                 return true;
9519                         break;
9520                 case 3:
9521                         if ((vmcs12->cr3_target_count >= 1 &&
9522                                         vmcs12->cr3_target_value0 == val) ||
9523                                 (vmcs12->cr3_target_count >= 2 &&
9524                                         vmcs12->cr3_target_value1 == val) ||
9525                                 (vmcs12->cr3_target_count >= 3 &&
9526                                         vmcs12->cr3_target_value2 == val) ||
9527                                 (vmcs12->cr3_target_count >= 4 &&
9528                                         vmcs12->cr3_target_value3 == val))
9529                                 return false;
9530                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
9531                                 return true;
9532                         break;
9533                 case 4:
9534                         if (vmcs12->cr4_guest_host_mask &
9535                             (vmcs12->cr4_read_shadow ^ val))
9536                                 return true;
9537                         break;
9538                 case 8:
9539                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
9540                                 return true;
9541                         break;
9542                 }
9543                 break;
9544         case 2: /* clts */
9545                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
9546                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
9547                         return true;
9548                 break;
9549         case 1: /* mov from cr */
9550                 switch (cr) {
9551                 case 3:
9552                         if (vmcs12->cpu_based_vm_exec_control &
9553                             CPU_BASED_CR3_STORE_EXITING)
9554                                 return true;
9555                         break;
9556                 case 8:
9557                         if (vmcs12->cpu_based_vm_exec_control &
9558                             CPU_BASED_CR8_STORE_EXITING)
9559                                 return true;
9560                         break;
9561                 }
9562                 break;
9563         case 3: /* lmsw */
9564                 /*
9565                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
9566                  * cr0. Other attempted changes are ignored, with no exit.
9567                  */
9568                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
9569                 if (vmcs12->cr0_guest_host_mask & 0xe &
9570                     (val ^ vmcs12->cr0_read_shadow))
9571                         return true;
9572                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
9573                     !(vmcs12->cr0_read_shadow & 0x1) &&
9574                     (val & 0x1))
9575                         return true;
9576                 break;
9577         }
9578         return false;
9579 }
9580
9581 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu,
9582         struct vmcs12 *vmcs12, gpa_t bitmap)
9583 {
9584         u32 vmx_instruction_info;
9585         unsigned long field;
9586         u8 b;
9587
9588         if (!nested_cpu_has_shadow_vmcs(vmcs12))
9589                 return true;
9590
9591         /* Decode instruction info and find the field to access */
9592         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9593         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
9594
9595         /* Out-of-range fields always cause a VM exit from L2 to L1 */
9596         if (field >> 15)
9597                 return true;
9598
9599         if (kvm_vcpu_read_guest(vcpu, bitmap + field/8, &b, 1))
9600                 return true;
9601
9602         return 1 & (b >> (field & 7));
9603 }
9604
9605 /*
9606  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
9607  * should handle it ourselves in L0 (and then continue L2). Only call this
9608  * when in is_guest_mode (L2).
9609  */
9610 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
9611 {
9612         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9613         struct vcpu_vmx *vmx = to_vmx(vcpu);
9614         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9615
9616         if (vmx->nested.nested_run_pending)
9617                 return false;
9618
9619         if (unlikely(vmx->fail)) {
9620                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
9621                                     vmcs_read32(VM_INSTRUCTION_ERROR));
9622                 return true;
9623         }
9624
9625         /*
9626          * The host physical addresses of some pages of guest memory
9627          * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
9628          * Page). The CPU may write to these pages via their host
9629          * physical address while L2 is running, bypassing any
9630          * address-translation-based dirty tracking (e.g. EPT write
9631          * protection).
9632          *
9633          * Mark them dirty on every exit from L2 to prevent them from
9634          * getting out of sync with dirty tracking.
9635          */
9636         nested_mark_vmcs12_pages_dirty(vcpu);
9637
9638         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
9639                                 vmcs_readl(EXIT_QUALIFICATION),
9640                                 vmx->idt_vectoring_info,
9641                                 intr_info,
9642                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9643                                 KVM_ISA_VMX);
9644
9645         switch (exit_reason) {
9646         case EXIT_REASON_EXCEPTION_NMI:
9647                 if (is_nmi(intr_info))
9648                         return false;
9649                 else if (is_page_fault(intr_info))
9650                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
9651                 else if (is_no_device(intr_info) &&
9652                          !(vmcs12->guest_cr0 & X86_CR0_TS))
9653                         return false;
9654                 else if (is_debug(intr_info) &&
9655                          vcpu->guest_debug &
9656                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
9657                         return false;
9658                 else if (is_breakpoint(intr_info) &&
9659                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
9660                         return false;
9661                 return vmcs12->exception_bitmap &
9662                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
9663         case EXIT_REASON_EXTERNAL_INTERRUPT:
9664                 return false;
9665         case EXIT_REASON_TRIPLE_FAULT:
9666                 return true;
9667         case EXIT_REASON_PENDING_INTERRUPT:
9668                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
9669         case EXIT_REASON_NMI_WINDOW:
9670                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
9671         case EXIT_REASON_TASK_SWITCH:
9672                 return true;
9673         case EXIT_REASON_CPUID:
9674                 return true;
9675         case EXIT_REASON_HLT:
9676                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
9677         case EXIT_REASON_INVD:
9678                 return true;
9679         case EXIT_REASON_INVLPG:
9680                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9681         case EXIT_REASON_RDPMC:
9682                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
9683         case EXIT_REASON_RDRAND:
9684                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
9685         case EXIT_REASON_RDSEED:
9686                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
9687         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
9688                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
9689         case EXIT_REASON_VMREAD:
9690                 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
9691                         vmcs12->vmread_bitmap);
9692         case EXIT_REASON_VMWRITE:
9693                 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
9694                         vmcs12->vmwrite_bitmap);
9695         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
9696         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
9697         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMRESUME:
9698         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
9699         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
9700                 /*
9701                  * VMX instructions trap unconditionally. This allows L1 to
9702                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
9703                  */
9704                 return true;
9705         case EXIT_REASON_CR_ACCESS:
9706                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
9707         case EXIT_REASON_DR_ACCESS:
9708                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
9709         case EXIT_REASON_IO_INSTRUCTION:
9710                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
9711         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
9712                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
9713         case EXIT_REASON_MSR_READ:
9714         case EXIT_REASON_MSR_WRITE:
9715                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
9716         case EXIT_REASON_INVALID_STATE:
9717                 return true;
9718         case EXIT_REASON_MWAIT_INSTRUCTION:
9719                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
9720         case EXIT_REASON_MONITOR_TRAP_FLAG:
9721                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
9722         case EXIT_REASON_MONITOR_INSTRUCTION:
9723                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
9724         case EXIT_REASON_PAUSE_INSTRUCTION:
9725                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
9726                         nested_cpu_has2(vmcs12,
9727                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
9728         case EXIT_REASON_MCE_DURING_VMENTRY:
9729                 return false;
9730         case EXIT_REASON_TPR_BELOW_THRESHOLD:
9731                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
9732         case EXIT_REASON_APIC_ACCESS:
9733         case EXIT_REASON_APIC_WRITE:
9734         case EXIT_REASON_EOI_INDUCED:
9735                 /*
9736                  * The controls for "virtualize APIC accesses," "APIC-
9737                  * register virtualization," and "virtual-interrupt
9738                  * delivery" only come from vmcs12.
9739                  */
9740                 return true;
9741         case EXIT_REASON_EPT_VIOLATION:
9742                 /*
9743                  * L0 always deals with the EPT violation. If nested EPT is
9744                  * used, and the nested mmu code discovers that the address is
9745                  * missing in the guest EPT table (EPT12), the EPT violation
9746                  * will be injected with nested_ept_inject_page_fault()
9747                  */
9748                 return false;
9749         case EXIT_REASON_EPT_MISCONFIG:
9750                 /*
9751                  * L2 never uses directly L1's EPT, but rather L0's own EPT
9752                  * table (shadow on EPT) or a merged EPT table that L0 built
9753                  * (EPT on EPT). So any problems with the structure of the
9754                  * table is L0's fault.
9755                  */
9756                 return false;
9757         case EXIT_REASON_INVPCID:
9758                 return
9759                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
9760                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9761         case EXIT_REASON_WBINVD:
9762                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
9763         case EXIT_REASON_XSETBV:
9764                 return true;
9765         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
9766                 /*
9767                  * This should never happen, since it is not possible to
9768                  * set XSS to a non-zero value---neither in L1 nor in L2.
9769                  * If if it were, XSS would have to be checked against
9770                  * the XSS exit bitmap in vmcs12.
9771                  */
9772                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
9773         case EXIT_REASON_PREEMPTION_TIMER:
9774                 return false;
9775         case EXIT_REASON_PML_FULL:
9776                 /* We emulate PML support to L1. */
9777                 return false;
9778         case EXIT_REASON_VMFUNC:
9779                 /* VM functions are emulated through L2->L0 vmexits. */
9780                 return false;
9781         case EXIT_REASON_ENCLS:
9782                 /* SGX is never exposed to L1 */
9783                 return false;
9784         default:
9785                 return true;
9786         }
9787 }
9788
9789 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
9790 {
9791         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9792
9793         /*
9794          * At this point, the exit interruption info in exit_intr_info
9795          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
9796          * we need to query the in-kernel LAPIC.
9797          */
9798         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
9799         if ((exit_intr_info &
9800              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9801             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
9802                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9803                 vmcs12->vm_exit_intr_error_code =
9804                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9805         }
9806
9807         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
9808                           vmcs_readl(EXIT_QUALIFICATION));
9809         return 1;
9810 }
9811
9812 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
9813 {
9814         *info1 = vmcs_readl(EXIT_QUALIFICATION);
9815         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
9816 }
9817
9818 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
9819 {
9820         if (vmx->pml_pg) {
9821                 __free_page(vmx->pml_pg);
9822                 vmx->pml_pg = NULL;
9823         }
9824 }
9825
9826 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
9827 {
9828         struct vcpu_vmx *vmx = to_vmx(vcpu);
9829         u64 *pml_buf;
9830         u16 pml_idx;
9831
9832         pml_idx = vmcs_read16(GUEST_PML_INDEX);
9833
9834         /* Do nothing if PML buffer is empty */
9835         if (pml_idx == (PML_ENTITY_NUM - 1))
9836                 return;
9837
9838         /* PML index always points to next available PML buffer entity */
9839         if (pml_idx >= PML_ENTITY_NUM)
9840                 pml_idx = 0;
9841         else
9842                 pml_idx++;
9843
9844         pml_buf = page_address(vmx->pml_pg);
9845         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
9846                 u64 gpa;
9847
9848                 gpa = pml_buf[pml_idx];
9849                 WARN_ON(gpa & (PAGE_SIZE - 1));
9850                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
9851         }
9852
9853         /* reset PML index */
9854         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
9855 }
9856
9857 /*
9858  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
9859  * Called before reporting dirty_bitmap to userspace.
9860  */
9861 static void kvm_flush_pml_buffers(struct kvm *kvm)
9862 {
9863         int i;
9864         struct kvm_vcpu *vcpu;
9865         /*
9866          * We only need to kick vcpu out of guest mode here, as PML buffer
9867          * is flushed at beginning of all VMEXITs, and it's obvious that only
9868          * vcpus running in guest are possible to have unflushed GPAs in PML
9869          * buffer.
9870          */
9871         kvm_for_each_vcpu(i, vcpu, kvm)
9872                 kvm_vcpu_kick(vcpu);
9873 }
9874
9875 static void vmx_dump_sel(char *name, uint32_t sel)
9876 {
9877         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
9878                name, vmcs_read16(sel),
9879                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
9880                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
9881                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
9882 }
9883
9884 static void vmx_dump_dtsel(char *name, uint32_t limit)
9885 {
9886         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
9887                name, vmcs_read32(limit),
9888                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
9889 }
9890
9891 static void dump_vmcs(void)
9892 {
9893         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
9894         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
9895         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
9896         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
9897         u32 secondary_exec_control = 0;
9898         unsigned long cr4 = vmcs_readl(GUEST_CR4);
9899         u64 efer = vmcs_read64(GUEST_IA32_EFER);
9900         int i, n;
9901
9902         if (cpu_has_secondary_exec_ctrls())
9903                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9904
9905         pr_err("*** Guest State ***\n");
9906         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9907                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
9908                vmcs_readl(CR0_GUEST_HOST_MASK));
9909         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9910                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
9911         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
9912         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
9913             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
9914         {
9915                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
9916                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
9917                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
9918                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
9919         }
9920         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
9921                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
9922         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
9923                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
9924         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9925                vmcs_readl(GUEST_SYSENTER_ESP),
9926                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
9927         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
9928         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
9929         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
9930         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
9931         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
9932         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
9933         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
9934         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
9935         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
9936         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
9937         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
9938             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
9939                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
9940                        efer, vmcs_read64(GUEST_IA32_PAT));
9941         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
9942                vmcs_read64(GUEST_IA32_DEBUGCTL),
9943                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
9944         if (cpu_has_load_perf_global_ctrl &&
9945             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
9946                 pr_err("PerfGlobCtl = 0x%016llx\n",
9947                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
9948         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
9949                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
9950         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
9951                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
9952                vmcs_read32(GUEST_ACTIVITY_STATE));
9953         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
9954                 pr_err("InterruptStatus = %04x\n",
9955                        vmcs_read16(GUEST_INTR_STATUS));
9956
9957         pr_err("*** Host State ***\n");
9958         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
9959                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
9960         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9961                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
9962                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
9963                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
9964                vmcs_read16(HOST_TR_SELECTOR));
9965         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9966                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
9967                vmcs_readl(HOST_TR_BASE));
9968         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9969                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
9970         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9971                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
9972                vmcs_readl(HOST_CR4));
9973         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9974                vmcs_readl(HOST_IA32_SYSENTER_ESP),
9975                vmcs_read32(HOST_IA32_SYSENTER_CS),
9976                vmcs_readl(HOST_IA32_SYSENTER_EIP));
9977         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
9978                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
9979                        vmcs_read64(HOST_IA32_EFER),
9980                        vmcs_read64(HOST_IA32_PAT));
9981         if (cpu_has_load_perf_global_ctrl &&
9982             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9983                 pr_err("PerfGlobCtl = 0x%016llx\n",
9984                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
9985
9986         pr_err("*** Control State ***\n");
9987         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
9988                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
9989         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
9990         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
9991                vmcs_read32(EXCEPTION_BITMAP),
9992                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
9993                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
9994         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
9995                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9996                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
9997                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
9998         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
9999                vmcs_read32(VM_EXIT_INTR_INFO),
10000                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
10001                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
10002         pr_err("        reason=%08x qualification=%016lx\n",
10003                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
10004         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
10005                vmcs_read32(IDT_VECTORING_INFO_FIELD),
10006                vmcs_read32(IDT_VECTORING_ERROR_CODE));
10007         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
10008         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
10009                 pr_err("TSC Multiplier = 0x%016llx\n",
10010                        vmcs_read64(TSC_MULTIPLIER));
10011         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
10012                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
10013         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
10014                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
10015         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
10016                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
10017         n = vmcs_read32(CR3_TARGET_COUNT);
10018         for (i = 0; i + 1 < n; i += 4)
10019                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
10020                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
10021                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
10022         if (i < n)
10023                 pr_err("CR3 target%u=%016lx\n",
10024                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
10025         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
10026                 pr_err("PLE Gap=%08x Window=%08x\n",
10027                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
10028         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
10029                 pr_err("Virtual processor ID = 0x%04x\n",
10030                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
10031 }
10032
10033 /*
10034  * The guest has exited.  See if we can fix it or if we need userspace
10035  * assistance.
10036  */
10037 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
10038 {
10039         struct vcpu_vmx *vmx = to_vmx(vcpu);
10040         u32 exit_reason = vmx->exit_reason;
10041         u32 vectoring_info = vmx->idt_vectoring_info;
10042
10043         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
10044
10045         /*
10046          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
10047          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
10048          * querying dirty_bitmap, we only need to kick all vcpus out of guest
10049          * mode as if vcpus is in root mode, the PML buffer must has been
10050          * flushed already.
10051          */
10052         if (enable_pml)
10053                 vmx_flush_pml_buffer(vcpu);
10054
10055         /* If guest state is invalid, start emulating */
10056         if (vmx->emulation_required)
10057                 return handle_invalid_guest_state(vcpu);
10058
10059         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
10060                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
10061
10062         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
10063                 dump_vmcs();
10064                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
10065                 vcpu->run->fail_entry.hardware_entry_failure_reason
10066                         = exit_reason;
10067                 return 0;
10068         }
10069
10070         if (unlikely(vmx->fail)) {
10071                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
10072                 vcpu->run->fail_entry.hardware_entry_failure_reason
10073                         = vmcs_read32(VM_INSTRUCTION_ERROR);
10074                 return 0;
10075         }
10076
10077         /*
10078          * Note:
10079          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
10080          * delivery event since it indicates guest is accessing MMIO.
10081          * The vm-exit can be triggered again after return to guest that
10082          * will cause infinite loop.
10083          */
10084         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
10085                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
10086                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
10087                         exit_reason != EXIT_REASON_PML_FULL &&
10088                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
10089                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
10090                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
10091                 vcpu->run->internal.ndata = 3;
10092                 vcpu->run->internal.data[0] = vectoring_info;
10093                 vcpu->run->internal.data[1] = exit_reason;
10094                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
10095                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
10096                         vcpu->run->internal.ndata++;
10097                         vcpu->run->internal.data[3] =
10098                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
10099                 }
10100                 return 0;
10101         }
10102
10103         if (unlikely(!enable_vnmi &&
10104                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
10105                 if (vmx_interrupt_allowed(vcpu)) {
10106                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
10107                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
10108                            vcpu->arch.nmi_pending) {
10109                         /*
10110                          * This CPU don't support us in finding the end of an
10111                          * NMI-blocked window if the guest runs with IRQs
10112                          * disabled. So we pull the trigger after 1 s of
10113                          * futile waiting, but inform the user about this.
10114                          */
10115                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
10116                                "state on VCPU %d after 1 s timeout\n",
10117                                __func__, vcpu->vcpu_id);
10118                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
10119                 }
10120         }
10121
10122         if (exit_reason < kvm_vmx_max_exit_handlers
10123             && kvm_vmx_exit_handlers[exit_reason])
10124                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
10125         else {
10126                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
10127                                 exit_reason);
10128                 kvm_queue_exception(vcpu, UD_VECTOR);
10129                 return 1;
10130         }
10131 }
10132
10133 /*
10134  * Software based L1D cache flush which is used when microcode providing
10135  * the cache control MSR is not loaded.
10136  *
10137  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
10138  * flush it is required to read in 64 KiB because the replacement algorithm
10139  * is not exactly LRU. This could be sized at runtime via topology
10140  * information but as all relevant affected CPUs have 32KiB L1D cache size
10141  * there is no point in doing so.
10142  */
10143 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
10144 {
10145         int size = PAGE_SIZE << L1D_CACHE_ORDER;
10146
10147         /*
10148          * This code is only executed when the the flush mode is 'cond' or
10149          * 'always'
10150          */
10151         if (static_branch_likely(&vmx_l1d_flush_cond)) {
10152                 bool flush_l1d;
10153
10154                 /*
10155                  * Clear the per-vcpu flush bit, it gets set again
10156                  * either from vcpu_run() or from one of the unsafe
10157                  * VMEXIT handlers.
10158                  */
10159                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
10160                 vcpu->arch.l1tf_flush_l1d = false;
10161
10162                 /*
10163                  * Clear the per-cpu flush bit, it gets set again from
10164                  * the interrupt handlers.
10165                  */
10166                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
10167                 kvm_clear_cpu_l1tf_flush_l1d();
10168
10169                 if (!flush_l1d)
10170                         return;
10171         }
10172
10173         vcpu->stat.l1d_flush++;
10174
10175         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
10176                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
10177                 return;
10178         }
10179
10180         asm volatile(
10181                 /* First ensure the pages are in the TLB */
10182                 "xorl   %%eax, %%eax\n"
10183                 ".Lpopulate_tlb:\n\t"
10184                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
10185                 "addl   $4096, %%eax\n\t"
10186                 "cmpl   %%eax, %[size]\n\t"
10187                 "jne    .Lpopulate_tlb\n\t"
10188                 "xorl   %%eax, %%eax\n\t"
10189                 "cpuid\n\t"
10190                 /* Now fill the cache */
10191                 "xorl   %%eax, %%eax\n"
10192                 ".Lfill_cache:\n"
10193                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
10194                 "addl   $64, %%eax\n\t"
10195                 "cmpl   %%eax, %[size]\n\t"
10196                 "jne    .Lfill_cache\n\t"
10197                 "lfence\n"
10198                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
10199                     [size] "r" (size)
10200                 : "eax", "ebx", "ecx", "edx");
10201 }
10202
10203 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
10204 {
10205         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10206
10207         if (is_guest_mode(vcpu) &&
10208                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10209                 return;
10210
10211         if (irr == -1 || tpr < irr) {
10212                 vmcs_write32(TPR_THRESHOLD, 0);
10213                 return;
10214         }
10215
10216         vmcs_write32(TPR_THRESHOLD, irr);
10217 }
10218
10219 static void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
10220 {
10221         u32 sec_exec_control;
10222
10223         if (!lapic_in_kernel(vcpu))
10224                 return;
10225
10226         if (!flexpriority_enabled &&
10227             !cpu_has_vmx_virtualize_x2apic_mode())
10228                 return;
10229
10230         /* Postpone execution until vmcs01 is the current VMCS. */
10231         if (is_guest_mode(vcpu)) {
10232                 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
10233                 return;
10234         }
10235
10236         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
10237         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10238                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
10239
10240         switch (kvm_get_apic_mode(vcpu)) {
10241         case LAPIC_MODE_INVALID:
10242                 WARN_ONCE(true, "Invalid local APIC state");
10243         case LAPIC_MODE_DISABLED:
10244                 break;
10245         case LAPIC_MODE_XAPIC:
10246                 if (flexpriority_enabled) {
10247                         sec_exec_control |=
10248                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
10249                         vmx_flush_tlb(vcpu, true);
10250                 }
10251                 break;
10252         case LAPIC_MODE_X2APIC:
10253                 if (cpu_has_vmx_virtualize_x2apic_mode())
10254                         sec_exec_control |=
10255                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
10256                 break;
10257         }
10258         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
10259
10260         vmx_update_msr_bitmap(vcpu);
10261 }
10262
10263 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
10264 {
10265         if (!is_guest_mode(vcpu)) {
10266                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
10267                 vmx_flush_tlb(vcpu, true);
10268         }
10269 }
10270
10271 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
10272 {
10273         u16 status;
10274         u8 old;
10275
10276         if (max_isr == -1)
10277                 max_isr = 0;
10278
10279         status = vmcs_read16(GUEST_INTR_STATUS);
10280         old = status >> 8;
10281         if (max_isr != old) {
10282                 status &= 0xff;
10283                 status |= max_isr << 8;
10284                 vmcs_write16(GUEST_INTR_STATUS, status);
10285         }
10286 }
10287
10288 static void vmx_set_rvi(int vector)
10289 {
10290         u16 status;
10291         u8 old;
10292
10293         if (vector == -1)
10294                 vector = 0;
10295
10296         status = vmcs_read16(GUEST_INTR_STATUS);
10297         old = (u8)status & 0xff;
10298         if ((u8)vector != old) {
10299                 status &= ~0xff;
10300                 status |= (u8)vector;
10301                 vmcs_write16(GUEST_INTR_STATUS, status);
10302         }
10303 }
10304
10305 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
10306 {
10307         /*
10308          * When running L2, updating RVI is only relevant when
10309          * vmcs12 virtual-interrupt-delivery enabled.
10310          * However, it can be enabled only when L1 also
10311          * intercepts external-interrupts and in that case
10312          * we should not update vmcs02 RVI but instead intercept
10313          * interrupt. Therefore, do nothing when running L2.
10314          */
10315         if (!is_guest_mode(vcpu))
10316                 vmx_set_rvi(max_irr);
10317 }
10318
10319 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
10320 {
10321         struct vcpu_vmx *vmx = to_vmx(vcpu);
10322         int max_irr;
10323         bool max_irr_updated;
10324
10325         WARN_ON(!vcpu->arch.apicv_active);
10326         if (pi_test_on(&vmx->pi_desc)) {
10327                 pi_clear_on(&vmx->pi_desc);
10328                 /*
10329                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
10330                  * But on x86 this is just a compiler barrier anyway.
10331                  */
10332                 smp_mb__after_atomic();
10333                 max_irr_updated =
10334                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
10335
10336                 /*
10337                  * If we are running L2 and L1 has a new pending interrupt
10338                  * which can be injected, we should re-evaluate
10339                  * what should be done with this new L1 interrupt.
10340                  * If L1 intercepts external-interrupts, we should
10341                  * exit from L2 to L1. Otherwise, interrupt should be
10342                  * delivered directly to L2.
10343                  */
10344                 if (is_guest_mode(vcpu) && max_irr_updated) {
10345                         if (nested_exit_on_intr(vcpu))
10346                                 kvm_vcpu_exiting_guest_mode(vcpu);
10347                         else
10348                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
10349                 }
10350         } else {
10351                 max_irr = kvm_lapic_find_highest_irr(vcpu);
10352         }
10353         vmx_hwapic_irr_update(vcpu, max_irr);
10354         return max_irr;
10355 }
10356
10357 static u8 vmx_has_apicv_interrupt(struct kvm_vcpu *vcpu)
10358 {
10359         u8 rvi = vmx_get_rvi();
10360         u8 vppr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_PROCPRI);
10361
10362         return ((rvi & 0xf0) > (vppr & 0xf0));
10363 }
10364
10365 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
10366 {
10367         if (!kvm_vcpu_apicv_active(vcpu))
10368                 return;
10369
10370         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
10371         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
10372         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
10373         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
10374 }
10375
10376 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
10377 {
10378         struct vcpu_vmx *vmx = to_vmx(vcpu);
10379
10380         pi_clear_on(&vmx->pi_desc);
10381         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
10382 }
10383
10384 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
10385 {
10386         u32 exit_intr_info = 0;
10387         u16 basic_exit_reason = (u16)vmx->exit_reason;
10388
10389         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
10390               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
10391                 return;
10392
10393         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10394                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10395         vmx->exit_intr_info = exit_intr_info;
10396
10397         /* if exit due to PF check for async PF */
10398         if (is_page_fault(exit_intr_info))
10399                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
10400
10401         /* Handle machine checks before interrupts are enabled */
10402         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
10403             is_machine_check(exit_intr_info))
10404                 kvm_machine_check();
10405
10406         /* We need to handle NMIs before interrupts are enabled */
10407         if (is_nmi(exit_intr_info)) {
10408                 kvm_before_interrupt(&vmx->vcpu);
10409                 asm("int $2");
10410                 kvm_after_interrupt(&vmx->vcpu);
10411         }
10412 }
10413
10414 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
10415 {
10416         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10417
10418         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
10419                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
10420                 unsigned int vector;
10421                 unsigned long entry;
10422                 gate_desc *desc;
10423                 struct vcpu_vmx *vmx = to_vmx(vcpu);
10424 #ifdef CONFIG_X86_64
10425                 unsigned long tmp;
10426 #endif
10427
10428                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
10429                 desc = (gate_desc *)vmx->host_idt_base + vector;
10430                 entry = gate_offset(desc);
10431                 asm volatile(
10432 #ifdef CONFIG_X86_64
10433                         "mov %%" _ASM_SP ", %[sp]\n\t"
10434                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
10435                         "push $%c[ss]\n\t"
10436                         "push %[sp]\n\t"
10437 #endif
10438                         "pushf\n\t"
10439                         __ASM_SIZE(push) " $%c[cs]\n\t"
10440                         CALL_NOSPEC
10441                         :
10442 #ifdef CONFIG_X86_64
10443                         [sp]"=&r"(tmp),
10444 #endif
10445                         ASM_CALL_CONSTRAINT
10446                         :
10447                         THUNK_TARGET(entry),
10448                         [ss]"i"(__KERNEL_DS),
10449                         [cs]"i"(__KERNEL_CS)
10450                         );
10451         }
10452 }
10453 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
10454
10455 static bool vmx_has_emulated_msr(int index)
10456 {
10457         switch (index) {
10458         case MSR_IA32_SMBASE:
10459                 /*
10460                  * We cannot do SMM unless we can run the guest in big
10461                  * real mode.
10462                  */
10463                 return enable_unrestricted_guest || emulate_invalid_guest_state;
10464         case MSR_AMD64_VIRT_SPEC_CTRL:
10465                 /* This is AMD only.  */
10466                 return false;
10467         default:
10468                 return true;
10469         }
10470 }
10471
10472 static bool vmx_mpx_supported(void)
10473 {
10474         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
10475                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
10476 }
10477
10478 static bool vmx_xsaves_supported(void)
10479 {
10480         return vmcs_config.cpu_based_2nd_exec_ctrl &
10481                 SECONDARY_EXEC_XSAVES;
10482 }
10483
10484 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
10485 {
10486         u32 exit_intr_info;
10487         bool unblock_nmi;
10488         u8 vector;
10489         bool idtv_info_valid;
10490
10491         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
10492
10493         if (enable_vnmi) {
10494                 if (vmx->loaded_vmcs->nmi_known_unmasked)
10495                         return;
10496                 /*
10497                  * Can't use vmx->exit_intr_info since we're not sure what
10498                  * the exit reason is.
10499                  */
10500                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10501                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
10502                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
10503                 /*
10504                  * SDM 3: 27.7.1.2 (September 2008)
10505                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
10506                  * a guest IRET fault.
10507                  * SDM 3: 23.2.2 (September 2008)
10508                  * Bit 12 is undefined in any of the following cases:
10509                  *  If the VM exit sets the valid bit in the IDT-vectoring
10510                  *   information field.
10511                  *  If the VM exit is due to a double fault.
10512                  */
10513                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
10514                     vector != DF_VECTOR && !idtv_info_valid)
10515                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
10516                                       GUEST_INTR_STATE_NMI);
10517                 else
10518                         vmx->loaded_vmcs->nmi_known_unmasked =
10519                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
10520                                   & GUEST_INTR_STATE_NMI);
10521         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
10522                 vmx->loaded_vmcs->vnmi_blocked_time +=
10523                         ktime_to_ns(ktime_sub(ktime_get(),
10524                                               vmx->loaded_vmcs->entry_time));
10525 }
10526
10527 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
10528                                       u32 idt_vectoring_info,
10529                                       int instr_len_field,
10530                                       int error_code_field)
10531 {
10532         u8 vector;
10533         int type;
10534         bool idtv_info_valid;
10535
10536         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
10537
10538         vcpu->arch.nmi_injected = false;
10539         kvm_clear_exception_queue(vcpu);
10540         kvm_clear_interrupt_queue(vcpu);
10541
10542         if (!idtv_info_valid)
10543                 return;
10544
10545         kvm_make_request(KVM_REQ_EVENT, vcpu);
10546
10547         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
10548         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
10549
10550         switch (type) {
10551         case INTR_TYPE_NMI_INTR:
10552                 vcpu->arch.nmi_injected = true;
10553                 /*
10554                  * SDM 3: 27.7.1.2 (September 2008)
10555                  * Clear bit "block by NMI" before VM entry if a NMI
10556                  * delivery faulted.
10557                  */
10558                 vmx_set_nmi_mask(vcpu, false);
10559                 break;
10560         case INTR_TYPE_SOFT_EXCEPTION:
10561                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
10562                 /* fall through */
10563         case INTR_TYPE_HARD_EXCEPTION:
10564                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
10565                         u32 err = vmcs_read32(error_code_field);
10566                         kvm_requeue_exception_e(vcpu, vector, err);
10567                 } else
10568                         kvm_requeue_exception(vcpu, vector);
10569                 break;
10570         case INTR_TYPE_SOFT_INTR:
10571                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
10572                 /* fall through */
10573         case INTR_TYPE_EXT_INTR:
10574                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
10575                 break;
10576         default:
10577                 break;
10578         }
10579 }
10580
10581 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
10582 {
10583         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
10584                                   VM_EXIT_INSTRUCTION_LEN,
10585                                   IDT_VECTORING_ERROR_CODE);
10586 }
10587
10588 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
10589 {
10590         __vmx_complete_interrupts(vcpu,
10591                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
10592                                   VM_ENTRY_INSTRUCTION_LEN,
10593                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
10594
10595         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10596 }
10597
10598 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
10599 {
10600         int i, nr_msrs;
10601         struct perf_guest_switch_msr *msrs;
10602
10603         msrs = perf_guest_get_msrs(&nr_msrs);
10604
10605         if (!msrs)
10606                 return;
10607
10608         for (i = 0; i < nr_msrs; i++)
10609                 if (msrs[i].host == msrs[i].guest)
10610                         clear_atomic_switch_msr(vmx, msrs[i].msr);
10611                 else
10612                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
10613                                         msrs[i].host, false);
10614 }
10615
10616 static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
10617 {
10618         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
10619         if (!vmx->loaded_vmcs->hv_timer_armed)
10620                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10621                               PIN_BASED_VMX_PREEMPTION_TIMER);
10622         vmx->loaded_vmcs->hv_timer_armed = true;
10623 }
10624
10625 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
10626 {
10627         struct vcpu_vmx *vmx = to_vmx(vcpu);
10628         u64 tscl;
10629         u32 delta_tsc;
10630
10631         if (vmx->req_immediate_exit) {
10632                 vmx_arm_hv_timer(vmx, 0);
10633                 return;
10634         }
10635
10636         if (vmx->hv_deadline_tsc != -1) {
10637                 tscl = rdtsc();
10638                 if (vmx->hv_deadline_tsc > tscl)
10639                         /* set_hv_timer ensures the delta fits in 32-bits */
10640                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
10641                                 cpu_preemption_timer_multi);
10642                 else
10643                         delta_tsc = 0;
10644
10645                 vmx_arm_hv_timer(vmx, delta_tsc);
10646                 return;
10647         }
10648
10649         if (vmx->loaded_vmcs->hv_timer_armed)
10650                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10651                                 PIN_BASED_VMX_PREEMPTION_TIMER);
10652         vmx->loaded_vmcs->hv_timer_armed = false;
10653 }
10654
10655 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
10656 {
10657         struct vcpu_vmx *vmx = to_vmx(vcpu);
10658         unsigned long cr3, cr4, evmcs_rsp;
10659
10660         /* Record the guest's net vcpu time for enforced NMI injections. */
10661         if (unlikely(!enable_vnmi &&
10662                      vmx->loaded_vmcs->soft_vnmi_blocked))
10663                 vmx->loaded_vmcs->entry_time = ktime_get();
10664
10665         /* Don't enter VMX if guest state is invalid, let the exit handler
10666            start emulation until we arrive back to a valid state */
10667         if (vmx->emulation_required)
10668                 return;
10669
10670         if (vmx->ple_window_dirty) {
10671                 vmx->ple_window_dirty = false;
10672                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
10673         }
10674
10675         if (vmx->nested.sync_shadow_vmcs) {
10676                 copy_vmcs12_to_shadow(vmx);
10677                 vmx->nested.sync_shadow_vmcs = false;
10678         }
10679
10680         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
10681                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
10682         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
10683                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
10684
10685         cr3 = __get_current_cr3_fast();
10686         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
10687                 vmcs_writel(HOST_CR3, cr3);
10688                 vmx->loaded_vmcs->host_state.cr3 = cr3;
10689         }
10690
10691         cr4 = cr4_read_shadow();
10692         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
10693                 vmcs_writel(HOST_CR4, cr4);
10694                 vmx->loaded_vmcs->host_state.cr4 = cr4;
10695         }
10696
10697         /* When single-stepping over STI and MOV SS, we must clear the
10698          * corresponding interruptibility bits in the guest state. Otherwise
10699          * vmentry fails as it then expects bit 14 (BS) in pending debug
10700          * exceptions being set, but that's not correct for the guest debugging
10701          * case. */
10702         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10703                 vmx_set_interrupt_shadow(vcpu, 0);
10704
10705         if (static_cpu_has(X86_FEATURE_PKU) &&
10706             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
10707             vcpu->arch.pkru != vmx->host_pkru)
10708                 __write_pkru(vcpu->arch.pkru);
10709
10710         atomic_switch_perf_msrs(vmx);
10711
10712         vmx_update_hv_timer(vcpu);
10713
10714         /*
10715          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
10716          * it's non-zero. Since vmentry is serialising on affected CPUs, there
10717          * is no need to worry about the conditional branch over the wrmsr
10718          * being speculatively taken.
10719          */
10720         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
10721
10722         vmx->__launched = vmx->loaded_vmcs->launched;
10723
10724         evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
10725                 (unsigned long)&current_evmcs->host_rsp : 0;
10726
10727         if (static_branch_unlikely(&vmx_l1d_should_flush))
10728                 vmx_l1d_flush(vcpu);
10729
10730         asm(
10731                 /* Store host registers */
10732                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
10733                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
10734                 "push %%" _ASM_CX " \n\t"
10735                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10736                 "je 1f \n\t"
10737                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10738                 /* Avoid VMWRITE when Enlightened VMCS is in use */
10739                 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
10740                 "jz 2f \n\t"
10741                 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
10742                 "jmp 1f \n\t"
10743                 "2: \n\t"
10744                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
10745                 "1: \n\t"
10746                 /* Reload cr2 if changed */
10747                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
10748                 "mov %%cr2, %%" _ASM_DX " \n\t"
10749                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
10750                 "je 3f \n\t"
10751                 "mov %%" _ASM_AX", %%cr2 \n\t"
10752                 "3: \n\t"
10753                 /* Check if vmlaunch of vmresume is needed */
10754                 "cmpl $0, %c[launched](%0) \n\t"
10755                 /* Load guest registers.  Don't clobber flags. */
10756                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
10757                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
10758                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
10759                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
10760                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
10761                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
10762 #ifdef CONFIG_X86_64
10763                 "mov %c[r8](%0),  %%r8  \n\t"
10764                 "mov %c[r9](%0),  %%r9  \n\t"
10765                 "mov %c[r10](%0), %%r10 \n\t"
10766                 "mov %c[r11](%0), %%r11 \n\t"
10767                 "mov %c[r12](%0), %%r12 \n\t"
10768                 "mov %c[r13](%0), %%r13 \n\t"
10769                 "mov %c[r14](%0), %%r14 \n\t"
10770                 "mov %c[r15](%0), %%r15 \n\t"
10771 #endif
10772                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
10773
10774                 /* Enter guest mode */
10775                 "jne 1f \n\t"
10776                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
10777                 "jmp 2f \n\t"
10778                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
10779                 "2: "
10780                 /* Save guest registers, load host registers, keep flags */
10781                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
10782                 "pop %0 \n\t"
10783                 "setbe %c[fail](%0)\n\t"
10784                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
10785                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
10786                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
10787                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
10788                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
10789                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
10790                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
10791 #ifdef CONFIG_X86_64
10792                 "mov %%r8,  %c[r8](%0) \n\t"
10793                 "mov %%r9,  %c[r9](%0) \n\t"
10794                 "mov %%r10, %c[r10](%0) \n\t"
10795                 "mov %%r11, %c[r11](%0) \n\t"
10796                 "mov %%r12, %c[r12](%0) \n\t"
10797                 "mov %%r13, %c[r13](%0) \n\t"
10798                 "mov %%r14, %c[r14](%0) \n\t"
10799                 "mov %%r15, %c[r15](%0) \n\t"
10800                 "xor %%r8d,  %%r8d \n\t"
10801                 "xor %%r9d,  %%r9d \n\t"
10802                 "xor %%r10d, %%r10d \n\t"
10803                 "xor %%r11d, %%r11d \n\t"
10804                 "xor %%r12d, %%r12d \n\t"
10805                 "xor %%r13d, %%r13d \n\t"
10806                 "xor %%r14d, %%r14d \n\t"
10807                 "xor %%r15d, %%r15d \n\t"
10808 #endif
10809                 "mov %%cr2, %%" _ASM_AX "   \n\t"
10810                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
10811
10812                 "xor %%eax, %%eax \n\t"
10813                 "xor %%ebx, %%ebx \n\t"
10814                 "xor %%esi, %%esi \n\t"
10815                 "xor %%edi, %%edi \n\t"
10816                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
10817                 ".pushsection .rodata \n\t"
10818                 ".global vmx_return \n\t"
10819                 "vmx_return: " _ASM_PTR " 2b \n\t"
10820                 ".popsection"
10821               : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
10822                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
10823                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
10824                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
10825                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
10826                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
10827                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
10828                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
10829                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
10830                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
10831                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
10832 #ifdef CONFIG_X86_64
10833                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
10834                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
10835                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
10836                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
10837                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
10838                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
10839                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
10840                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
10841 #endif
10842                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
10843                 [wordsize]"i"(sizeof(ulong))
10844               : "cc", "memory"
10845 #ifdef CONFIG_X86_64
10846                 , "rax", "rbx", "rdi"
10847                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
10848 #else
10849                 , "eax", "ebx", "edi"
10850 #endif
10851               );
10852
10853         /*
10854          * We do not use IBRS in the kernel. If this vCPU has used the
10855          * SPEC_CTRL MSR it may have left it on; save the value and
10856          * turn it off. This is much more efficient than blindly adding
10857          * it to the atomic save/restore list. Especially as the former
10858          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
10859          *
10860          * For non-nested case:
10861          * If the L01 MSR bitmap does not intercept the MSR, then we need to
10862          * save it.
10863          *
10864          * For nested case:
10865          * If the L02 MSR bitmap does not intercept the MSR, then we need to
10866          * save it.
10867          */
10868         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
10869                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
10870
10871         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
10872
10873         /* Eliminate branch target predictions from guest mode */
10874         vmexit_fill_RSB();
10875
10876         /* All fields are clean at this point */
10877         if (static_branch_unlikely(&enable_evmcs))
10878                 current_evmcs->hv_clean_fields |=
10879                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
10880
10881         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
10882         if (vmx->host_debugctlmsr)
10883                 update_debugctlmsr(vmx->host_debugctlmsr);
10884
10885 #ifndef CONFIG_X86_64
10886         /*
10887          * The sysexit path does not restore ds/es, so we must set them to
10888          * a reasonable value ourselves.
10889          *
10890          * We can't defer this to vmx_prepare_switch_to_host() since that
10891          * function may be executed in interrupt context, which saves and
10892          * restore segments around it, nullifying its effect.
10893          */
10894         loadsegment(ds, __USER_DS);
10895         loadsegment(es, __USER_DS);
10896 #endif
10897
10898         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
10899                                   | (1 << VCPU_EXREG_RFLAGS)
10900                                   | (1 << VCPU_EXREG_PDPTR)
10901                                   | (1 << VCPU_EXREG_SEGMENTS)
10902                                   | (1 << VCPU_EXREG_CR3));
10903         vcpu->arch.regs_dirty = 0;
10904
10905         /*
10906          * eager fpu is enabled if PKEY is supported and CR4 is switched
10907          * back on host, so it is safe to read guest PKRU from current
10908          * XSAVE.
10909          */
10910         if (static_cpu_has(X86_FEATURE_PKU) &&
10911             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
10912                 vcpu->arch.pkru = __read_pkru();
10913                 if (vcpu->arch.pkru != vmx->host_pkru)
10914                         __write_pkru(vmx->host_pkru);
10915         }
10916
10917         vmx->nested.nested_run_pending = 0;
10918         vmx->idt_vectoring_info = 0;
10919
10920         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
10921         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10922                 return;
10923
10924         vmx->loaded_vmcs->launched = 1;
10925         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
10926
10927         vmx_complete_atomic_exit(vmx);
10928         vmx_recover_nmi_blocking(vmx);
10929         vmx_complete_interrupts(vmx);
10930 }
10931 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
10932
10933 static struct kvm *vmx_vm_alloc(void)
10934 {
10935         struct kvm_vmx *kvm_vmx = vzalloc(sizeof(struct kvm_vmx));
10936         return &kvm_vmx->kvm;
10937 }
10938
10939 static void vmx_vm_free(struct kvm *kvm)
10940 {
10941         vfree(to_kvm_vmx(kvm));
10942 }
10943
10944 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
10945 {
10946         struct vcpu_vmx *vmx = to_vmx(vcpu);
10947         int cpu;
10948
10949         if (vmx->loaded_vmcs == vmcs)
10950                 return;
10951
10952         cpu = get_cpu();
10953         vmx_vcpu_put(vcpu);
10954         vmx->loaded_vmcs = vmcs;
10955         vmx_vcpu_load(vcpu, cpu);
10956         put_cpu();
10957 }
10958
10959 /*
10960  * Ensure that the current vmcs of the logical processor is the
10961  * vmcs01 of the vcpu before calling free_nested().
10962  */
10963 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
10964 {
10965        struct vcpu_vmx *vmx = to_vmx(vcpu);
10966
10967        vcpu_load(vcpu);
10968        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10969        free_nested(vmx);
10970        vcpu_put(vcpu);
10971 }
10972
10973 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
10974 {
10975         struct vcpu_vmx *vmx = to_vmx(vcpu);
10976
10977         if (enable_pml)
10978                 vmx_destroy_pml_buffer(vmx);
10979         free_vpid(vmx->vpid);
10980         leave_guest_mode(vcpu);
10981         vmx_free_vcpu_nested(vcpu);
10982         free_loaded_vmcs(vmx->loaded_vmcs);
10983         kfree(vmx->guest_msrs);
10984         kvm_vcpu_uninit(vcpu);
10985         kmem_cache_free(kvm_vcpu_cache, vmx);
10986 }
10987
10988 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
10989 {
10990         int err;
10991         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
10992         unsigned long *msr_bitmap;
10993         int cpu;
10994
10995         if (!vmx)
10996                 return ERR_PTR(-ENOMEM);
10997
10998         vmx->vpid = allocate_vpid();
10999
11000         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
11001         if (err)
11002                 goto free_vcpu;
11003
11004         err = -ENOMEM;
11005
11006         /*
11007          * If PML is turned on, failure on enabling PML just results in failure
11008          * of creating the vcpu, therefore we can simplify PML logic (by
11009          * avoiding dealing with cases, such as enabling PML partially on vcpus
11010          * for the guest, etc.
11011          */
11012         if (enable_pml) {
11013                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
11014                 if (!vmx->pml_pg)
11015                         goto uninit_vcpu;
11016         }
11017
11018         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
11019         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
11020                      > PAGE_SIZE);
11021
11022         if (!vmx->guest_msrs)
11023                 goto free_pml;
11024
11025         err = alloc_loaded_vmcs(&vmx->vmcs01);
11026         if (err < 0)
11027                 goto free_msrs;
11028
11029         msr_bitmap = vmx->vmcs01.msr_bitmap;
11030         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
11031         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
11032         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
11033         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
11034         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
11035         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
11036         vmx->msr_bitmap_mode = 0;
11037
11038         vmx->loaded_vmcs = &vmx->vmcs01;
11039         cpu = get_cpu();
11040         vmx_vcpu_load(&vmx->vcpu, cpu);
11041         vmx->vcpu.cpu = cpu;
11042         vmx_vcpu_setup(vmx);
11043         vmx_vcpu_put(&vmx->vcpu);
11044         put_cpu();
11045         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
11046                 err = alloc_apic_access_page(kvm);
11047                 if (err)
11048                         goto free_vmcs;
11049         }
11050
11051         if (enable_ept && !enable_unrestricted_guest) {
11052                 err = init_rmode_identity_map(kvm);
11053                 if (err)
11054                         goto free_vmcs;
11055         }
11056
11057         if (nested)
11058                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
11059                                            kvm_vcpu_apicv_active(&vmx->vcpu));
11060
11061         vmx->nested.posted_intr_nv = -1;
11062         vmx->nested.current_vmptr = -1ull;
11063
11064         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
11065
11066         /*
11067          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
11068          * or POSTED_INTR_WAKEUP_VECTOR.
11069          */
11070         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
11071         vmx->pi_desc.sn = 1;
11072
11073         return &vmx->vcpu;
11074
11075 free_vmcs:
11076         free_loaded_vmcs(vmx->loaded_vmcs);
11077 free_msrs:
11078         kfree(vmx->guest_msrs);
11079 free_pml:
11080         vmx_destroy_pml_buffer(vmx);
11081 uninit_vcpu:
11082         kvm_vcpu_uninit(&vmx->vcpu);
11083 free_vcpu:
11084         free_vpid(vmx->vpid);
11085         kmem_cache_free(kvm_vcpu_cache, vmx);
11086         return ERR_PTR(err);
11087 }
11088
11089 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
11090 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
11091
11092 static int vmx_vm_init(struct kvm *kvm)
11093 {
11094         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
11095
11096         if (!ple_gap)
11097                 kvm->arch.pause_in_guest = true;
11098
11099         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
11100                 switch (l1tf_mitigation) {
11101                 case L1TF_MITIGATION_OFF:
11102                 case L1TF_MITIGATION_FLUSH_NOWARN:
11103                         /* 'I explicitly don't care' is set */
11104                         break;
11105                 case L1TF_MITIGATION_FLUSH:
11106                 case L1TF_MITIGATION_FLUSH_NOSMT:
11107                 case L1TF_MITIGATION_FULL:
11108                         /*
11109                          * Warn upon starting the first VM in a potentially
11110                          * insecure environment.
11111                          */
11112                         if (cpu_smt_control == CPU_SMT_ENABLED)
11113                                 pr_warn_once(L1TF_MSG_SMT);
11114                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
11115                                 pr_warn_once(L1TF_MSG_L1D);
11116                         break;
11117                 case L1TF_MITIGATION_FULL_FORCE:
11118                         /* Flush is enforced */
11119                         break;
11120                 }
11121         }
11122         return 0;
11123 }
11124
11125 static void __init vmx_check_processor_compat(void *rtn)
11126 {
11127         struct vmcs_config vmcs_conf;
11128
11129         *(int *)rtn = 0;
11130         if (setup_vmcs_config(&vmcs_conf) < 0)
11131                 *(int *)rtn = -EIO;
11132         nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, enable_apicv);
11133         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
11134                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
11135                                 smp_processor_id());
11136                 *(int *)rtn = -EIO;
11137         }
11138 }
11139
11140 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
11141 {
11142         u8 cache;
11143         u64 ipat = 0;
11144
11145         /* For VT-d and EPT combination
11146          * 1. MMIO: always map as UC
11147          * 2. EPT with VT-d:
11148          *   a. VT-d without snooping control feature: can't guarantee the
11149          *      result, try to trust guest.
11150          *   b. VT-d with snooping control feature: snooping control feature of
11151          *      VT-d engine can guarantee the cache correctness. Just set it
11152          *      to WB to keep consistent with host. So the same as item 3.
11153          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
11154          *    consistent with host MTRR
11155          */
11156         if (is_mmio) {
11157                 cache = MTRR_TYPE_UNCACHABLE;
11158                 goto exit;
11159         }
11160
11161         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
11162                 ipat = VMX_EPT_IPAT_BIT;
11163                 cache = MTRR_TYPE_WRBACK;
11164                 goto exit;
11165         }
11166
11167         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
11168                 ipat = VMX_EPT_IPAT_BIT;
11169                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
11170                         cache = MTRR_TYPE_WRBACK;
11171                 else
11172                         cache = MTRR_TYPE_UNCACHABLE;
11173                 goto exit;
11174         }
11175
11176         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
11177
11178 exit:
11179         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
11180 }
11181
11182 static int vmx_get_lpage_level(void)
11183 {
11184         if (enable_ept && !cpu_has_vmx_ept_1g_page())
11185                 return PT_DIRECTORY_LEVEL;
11186         else
11187                 /* For shadow and EPT supported 1GB page */
11188                 return PT_PDPE_LEVEL;
11189 }
11190
11191 static void vmcs_set_secondary_exec_control(u32 new_ctl)
11192 {
11193         /*
11194          * These bits in the secondary execution controls field
11195          * are dynamic, the others are mostly based on the hypervisor
11196          * architecture and the guest's CPUID.  Do not touch the
11197          * dynamic bits.
11198          */
11199         u32 mask =
11200                 SECONDARY_EXEC_SHADOW_VMCS |
11201                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
11202                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
11203                 SECONDARY_EXEC_DESC;
11204
11205         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
11206
11207         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
11208                      (new_ctl & ~mask) | (cur_ctl & mask));
11209 }
11210
11211 /*
11212  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
11213  * (indicating "allowed-1") if they are supported in the guest's CPUID.
11214  */
11215 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
11216 {
11217         struct vcpu_vmx *vmx = to_vmx(vcpu);
11218         struct kvm_cpuid_entry2 *entry;
11219
11220         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
11221         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
11222
11223 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
11224         if (entry && (entry->_reg & (_cpuid_mask)))                     \
11225                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
11226 } while (0)
11227
11228         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
11229         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
11230         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
11231         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
11232         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
11233         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
11234         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
11235         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
11236         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
11237         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
11238         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
11239         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
11240         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
11241         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
11242         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
11243
11244         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
11245         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
11246         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
11247         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
11248         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
11249         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
11250
11251 #undef cr4_fixed1_update
11252 }
11253
11254 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
11255 {
11256         struct vcpu_vmx *vmx = to_vmx(vcpu);
11257
11258         if (kvm_mpx_supported()) {
11259                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
11260
11261                 if (mpx_enabled) {
11262                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
11263                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
11264                 } else {
11265                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
11266                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
11267                 }
11268         }
11269 }
11270
11271 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
11272 {
11273         struct vcpu_vmx *vmx = to_vmx(vcpu);
11274
11275         if (cpu_has_secondary_exec_ctrls()) {
11276                 vmx_compute_secondary_exec_control(vmx);
11277                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
11278         }
11279
11280         if (nested_vmx_allowed(vcpu))
11281                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11282                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
11283         else
11284                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11285                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
11286
11287         if (nested_vmx_allowed(vcpu)) {
11288                 nested_vmx_cr_fixed1_bits_update(vcpu);
11289                 nested_vmx_entry_exit_ctls_update(vcpu);
11290         }
11291 }
11292
11293 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
11294 {
11295         if (func == 1 && nested)
11296                 entry->ecx |= bit(X86_FEATURE_VMX);
11297 }
11298
11299 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
11300                 struct x86_exception *fault)
11301 {
11302         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11303         struct vcpu_vmx *vmx = to_vmx(vcpu);
11304         u32 exit_reason;
11305         unsigned long exit_qualification = vcpu->arch.exit_qualification;
11306
11307         if (vmx->nested.pml_full) {
11308                 exit_reason = EXIT_REASON_PML_FULL;
11309                 vmx->nested.pml_full = false;
11310                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
11311         } else if (fault->error_code & PFERR_RSVD_MASK)
11312                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
11313         else
11314                 exit_reason = EXIT_REASON_EPT_VIOLATION;
11315
11316         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
11317         vmcs12->guest_physical_address = fault->address;
11318 }
11319
11320 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
11321 {
11322         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
11323 }
11324
11325 /* Callbacks for nested_ept_init_mmu_context: */
11326
11327 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
11328 {
11329         /* return the page table to be shadowed - in our case, EPT12 */
11330         return get_vmcs12(vcpu)->ept_pointer;
11331 }
11332
11333 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
11334 {
11335         WARN_ON(mmu_is_nested(vcpu));
11336         if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
11337                 return 1;
11338
11339         kvm_init_shadow_ept_mmu(vcpu,
11340                         to_vmx(vcpu)->nested.msrs.ept_caps &
11341                         VMX_EPT_EXECUTE_ONLY_BIT,
11342                         nested_ept_ad_enabled(vcpu),
11343                         nested_ept_get_cr3(vcpu));
11344         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
11345         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
11346         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
11347
11348         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
11349         return 0;
11350 }
11351
11352 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
11353 {
11354         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
11355 }
11356
11357 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
11358                                             u16 error_code)
11359 {
11360         bool inequality, bit;
11361
11362         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
11363         inequality =
11364                 (error_code & vmcs12->page_fault_error_code_mask) !=
11365                  vmcs12->page_fault_error_code_match;
11366         return inequality ^ bit;
11367 }
11368
11369 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
11370                 struct x86_exception *fault)
11371 {
11372         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11373
11374         WARN_ON(!is_guest_mode(vcpu));
11375
11376         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
11377                 !to_vmx(vcpu)->nested.nested_run_pending) {
11378                 vmcs12->vm_exit_intr_error_code = fault->error_code;
11379                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11380                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
11381                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
11382                                   fault->address);
11383         } else {
11384                 kvm_inject_page_fault(vcpu, fault);
11385         }
11386 }
11387
11388 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
11389                                                  struct vmcs12 *vmcs12);
11390
11391 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
11392 {
11393         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11394         struct vcpu_vmx *vmx = to_vmx(vcpu);
11395         struct page *page;
11396         u64 hpa;
11397
11398         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11399                 /*
11400                  * Translate L1 physical address to host physical
11401                  * address for vmcs02. Keep the page pinned, so this
11402                  * physical address remains valid. We keep a reference
11403                  * to it so we can release it later.
11404                  */
11405                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
11406                         kvm_release_page_dirty(vmx->nested.apic_access_page);
11407                         vmx->nested.apic_access_page = NULL;
11408                 }
11409                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
11410                 /*
11411                  * If translation failed, no matter: This feature asks
11412                  * to exit when accessing the given address, and if it
11413                  * can never be accessed, this feature won't do
11414                  * anything anyway.
11415                  */
11416                 if (!is_error_page(page)) {
11417                         vmx->nested.apic_access_page = page;
11418                         hpa = page_to_phys(vmx->nested.apic_access_page);
11419                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
11420                 } else {
11421                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
11422                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
11423                 }
11424         }
11425
11426         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
11427                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
11428                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11429                         vmx->nested.virtual_apic_page = NULL;
11430                 }
11431                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
11432
11433                 /*
11434                  * If translation failed, VM entry will fail because
11435                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
11436                  * Failing the vm entry is _not_ what the processor
11437                  * does but it's basically the only possibility we
11438                  * have.  We could still enter the guest if CR8 load
11439                  * exits are enabled, CR8 store exits are enabled, and
11440                  * virtualize APIC access is disabled; in this case
11441                  * the processor would never use the TPR shadow and we
11442                  * could simply clear the bit from the execution
11443                  * control.  But such a configuration is useless, so
11444                  * let's keep the code simple.
11445                  */
11446                 if (!is_error_page(page)) {
11447                         vmx->nested.virtual_apic_page = page;
11448                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
11449                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
11450                 }
11451         }
11452
11453         if (nested_cpu_has_posted_intr(vmcs12)) {
11454                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
11455                         kunmap(vmx->nested.pi_desc_page);
11456                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
11457                         vmx->nested.pi_desc_page = NULL;
11458                 }
11459                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
11460                 if (is_error_page(page))
11461                         return;
11462                 vmx->nested.pi_desc_page = page;
11463                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
11464                 vmx->nested.pi_desc =
11465                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
11466                         (unsigned long)(vmcs12->posted_intr_desc_addr &
11467                         (PAGE_SIZE - 1)));
11468                 vmcs_write64(POSTED_INTR_DESC_ADDR,
11469                         page_to_phys(vmx->nested.pi_desc_page) +
11470                         (unsigned long)(vmcs12->posted_intr_desc_addr &
11471                         (PAGE_SIZE - 1)));
11472         }
11473         if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
11474                 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
11475                               CPU_BASED_USE_MSR_BITMAPS);
11476         else
11477                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
11478                                 CPU_BASED_USE_MSR_BITMAPS);
11479 }
11480
11481 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
11482 {
11483         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
11484         struct vcpu_vmx *vmx = to_vmx(vcpu);
11485
11486         /*
11487          * A timer value of zero is architecturally guaranteed to cause
11488          * a VMExit prior to executing any instructions in the guest.
11489          */
11490         if (preemption_timeout == 0) {
11491                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
11492                 return;
11493         }
11494
11495         if (vcpu->arch.virtual_tsc_khz == 0)
11496                 return;
11497
11498         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11499         preemption_timeout *= 1000000;
11500         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
11501         hrtimer_start(&vmx->nested.preemption_timer,
11502                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
11503 }
11504
11505 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
11506                                                struct vmcs12 *vmcs12)
11507 {
11508         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
11509                 return 0;
11510
11511         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
11512             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
11513                 return -EINVAL;
11514
11515         return 0;
11516 }
11517
11518 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
11519                                                 struct vmcs12 *vmcs12)
11520 {
11521         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
11522                 return 0;
11523
11524         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
11525                 return -EINVAL;
11526
11527         return 0;
11528 }
11529
11530 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
11531                                                 struct vmcs12 *vmcs12)
11532 {
11533         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
11534                 return 0;
11535
11536         if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
11537                 return -EINVAL;
11538
11539         return 0;
11540 }
11541
11542 /*
11543  * Merge L0's and L1's MSR bitmap, return false to indicate that
11544  * we do not use the hardware.
11545  */
11546 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
11547                                                  struct vmcs12 *vmcs12)
11548 {
11549         int msr;
11550         struct page *page;
11551         unsigned long *msr_bitmap_l1;
11552         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
11553         /*
11554          * pred_cmd & spec_ctrl are trying to verify two things:
11555          *
11556          * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
11557          *    ensures that we do not accidentally generate an L02 MSR bitmap
11558          *    from the L12 MSR bitmap that is too permissive.
11559          * 2. That L1 or L2s have actually used the MSR. This avoids
11560          *    unnecessarily merging of the bitmap if the MSR is unused. This
11561          *    works properly because we only update the L01 MSR bitmap lazily.
11562          *    So even if L0 should pass L1 these MSRs, the L01 bitmap is only
11563          *    updated to reflect this when L1 (or its L2s) actually write to
11564          *    the MSR.
11565          */
11566         bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
11567         bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
11568
11569         /* Nothing to do if the MSR bitmap is not in use.  */
11570         if (!cpu_has_vmx_msr_bitmap() ||
11571             !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
11572                 return false;
11573
11574         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11575             !pred_cmd && !spec_ctrl)
11576                 return false;
11577
11578         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
11579         if (is_error_page(page))
11580                 return false;
11581
11582         msr_bitmap_l1 = (unsigned long *)kmap(page);
11583         if (nested_cpu_has_apic_reg_virt(vmcs12)) {
11584                 /*
11585                  * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
11586                  * just lets the processor take the value from the virtual-APIC page;
11587                  * take those 256 bits directly from the L1 bitmap.
11588                  */
11589                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
11590                         unsigned word = msr / BITS_PER_LONG;
11591                         msr_bitmap_l0[word] = msr_bitmap_l1[word];
11592                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
11593                 }
11594         } else {
11595                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
11596                         unsigned word = msr / BITS_PER_LONG;
11597                         msr_bitmap_l0[word] = ~0;
11598                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
11599                 }
11600         }
11601
11602         nested_vmx_disable_intercept_for_msr(
11603                 msr_bitmap_l1, msr_bitmap_l0,
11604                 X2APIC_MSR(APIC_TASKPRI),
11605                 MSR_TYPE_W);
11606
11607         if (nested_cpu_has_vid(vmcs12)) {
11608                 nested_vmx_disable_intercept_for_msr(
11609                         msr_bitmap_l1, msr_bitmap_l0,
11610                         X2APIC_MSR(APIC_EOI),
11611                         MSR_TYPE_W);
11612                 nested_vmx_disable_intercept_for_msr(
11613                         msr_bitmap_l1, msr_bitmap_l0,
11614                         X2APIC_MSR(APIC_SELF_IPI),
11615                         MSR_TYPE_W);
11616         }
11617
11618         if (spec_ctrl)
11619                 nested_vmx_disable_intercept_for_msr(
11620                                         msr_bitmap_l1, msr_bitmap_l0,
11621                                         MSR_IA32_SPEC_CTRL,
11622                                         MSR_TYPE_R | MSR_TYPE_W);
11623
11624         if (pred_cmd)
11625                 nested_vmx_disable_intercept_for_msr(
11626                                         msr_bitmap_l1, msr_bitmap_l0,
11627                                         MSR_IA32_PRED_CMD,
11628                                         MSR_TYPE_W);
11629
11630         kunmap(page);
11631         kvm_release_page_clean(page);
11632
11633         return true;
11634 }
11635
11636 static void nested_cache_shadow_vmcs12(struct kvm_vcpu *vcpu,
11637                                        struct vmcs12 *vmcs12)
11638 {
11639         struct vmcs12 *shadow;
11640         struct page *page;
11641
11642         if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
11643             vmcs12->vmcs_link_pointer == -1ull)
11644                 return;
11645
11646         shadow = get_shadow_vmcs12(vcpu);
11647         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->vmcs_link_pointer);
11648
11649         memcpy(shadow, kmap(page), VMCS12_SIZE);
11650
11651         kunmap(page);
11652         kvm_release_page_clean(page);
11653 }
11654
11655 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu *vcpu,
11656                                               struct vmcs12 *vmcs12)
11657 {
11658         struct vcpu_vmx *vmx = to_vmx(vcpu);
11659
11660         if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
11661             vmcs12->vmcs_link_pointer == -1ull)
11662                 return;
11663
11664         kvm_write_guest(vmx->vcpu.kvm, vmcs12->vmcs_link_pointer,
11665                         get_shadow_vmcs12(vcpu), VMCS12_SIZE);
11666 }
11667
11668 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
11669                                           struct vmcs12 *vmcs12)
11670 {
11671         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
11672             !page_address_valid(vcpu, vmcs12->apic_access_addr))
11673                 return -EINVAL;
11674         else
11675                 return 0;
11676 }
11677
11678 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
11679                                            struct vmcs12 *vmcs12)
11680 {
11681         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11682             !nested_cpu_has_apic_reg_virt(vmcs12) &&
11683             !nested_cpu_has_vid(vmcs12) &&
11684             !nested_cpu_has_posted_intr(vmcs12))
11685                 return 0;
11686
11687         /*
11688          * If virtualize x2apic mode is enabled,
11689          * virtualize apic access must be disabled.
11690          */
11691         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11692             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
11693                 return -EINVAL;
11694
11695         /*
11696          * If virtual interrupt delivery is enabled,
11697          * we must exit on external interrupts.
11698          */
11699         if (nested_cpu_has_vid(vmcs12) &&
11700            !nested_exit_on_intr(vcpu))
11701                 return -EINVAL;
11702
11703         /*
11704          * bits 15:8 should be zero in posted_intr_nv,
11705          * the descriptor address has been already checked
11706          * in nested_get_vmcs12_pages.
11707          *
11708          * bits 5:0 of posted_intr_desc_addr should be zero.
11709          */
11710         if (nested_cpu_has_posted_intr(vmcs12) &&
11711            (!nested_cpu_has_vid(vmcs12) ||
11712             !nested_exit_intr_ack_set(vcpu) ||
11713             (vmcs12->posted_intr_nv & 0xff00) ||
11714             (vmcs12->posted_intr_desc_addr & 0x3f) ||
11715             (!page_address_valid(vcpu, vmcs12->posted_intr_desc_addr))))
11716                 return -EINVAL;
11717
11718         /* tpr shadow is needed by all apicv features. */
11719         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
11720                 return -EINVAL;
11721
11722         return 0;
11723 }
11724
11725 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
11726                                        unsigned long count_field,
11727                                        unsigned long addr_field)
11728 {
11729         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11730         int maxphyaddr;
11731         u64 count, addr;
11732
11733         if (vmcs12_read_any(vmcs12, count_field, &count) ||
11734             vmcs12_read_any(vmcs12, addr_field, &addr)) {
11735                 WARN_ON(1);
11736                 return -EINVAL;
11737         }
11738         if (count == 0)
11739                 return 0;
11740         maxphyaddr = cpuid_maxphyaddr(vcpu);
11741         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
11742             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
11743                 pr_debug_ratelimited(
11744                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
11745                         addr_field, maxphyaddr, count, addr);
11746                 return -EINVAL;
11747         }
11748         return 0;
11749 }
11750
11751 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
11752                                                 struct vmcs12 *vmcs12)
11753 {
11754         if (vmcs12->vm_exit_msr_load_count == 0 &&
11755             vmcs12->vm_exit_msr_store_count == 0 &&
11756             vmcs12->vm_entry_msr_load_count == 0)
11757                 return 0; /* Fast path */
11758         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
11759                                         VM_EXIT_MSR_LOAD_ADDR) ||
11760             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
11761                                         VM_EXIT_MSR_STORE_ADDR) ||
11762             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
11763                                         VM_ENTRY_MSR_LOAD_ADDR))
11764                 return -EINVAL;
11765         return 0;
11766 }
11767
11768 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
11769                                          struct vmcs12 *vmcs12)
11770 {
11771         u64 address = vmcs12->pml_address;
11772         int maxphyaddr = cpuid_maxphyaddr(vcpu);
11773
11774         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
11775                 if (!nested_cpu_has_ept(vmcs12) ||
11776                     !IS_ALIGNED(address, 4096)  ||
11777                     address >> maxphyaddr)
11778                         return -EINVAL;
11779         }
11780
11781         return 0;
11782 }
11783
11784 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu *vcpu,
11785                                                  struct vmcs12 *vmcs12)
11786 {
11787         if (!nested_cpu_has_shadow_vmcs(vmcs12))
11788                 return 0;
11789
11790         if (!page_address_valid(vcpu, vmcs12->vmread_bitmap) ||
11791             !page_address_valid(vcpu, vmcs12->vmwrite_bitmap))
11792                 return -EINVAL;
11793
11794         return 0;
11795 }
11796
11797 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
11798                                        struct vmx_msr_entry *e)
11799 {
11800         /* x2APIC MSR accesses are not allowed */
11801         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
11802                 return -EINVAL;
11803         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
11804             e->index == MSR_IA32_UCODE_REV)
11805                 return -EINVAL;
11806         if (e->reserved != 0)
11807                 return -EINVAL;
11808         return 0;
11809 }
11810
11811 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
11812                                      struct vmx_msr_entry *e)
11813 {
11814         if (e->index == MSR_FS_BASE ||
11815             e->index == MSR_GS_BASE ||
11816             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
11817             nested_vmx_msr_check_common(vcpu, e))
11818                 return -EINVAL;
11819         return 0;
11820 }
11821
11822 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
11823                                       struct vmx_msr_entry *e)
11824 {
11825         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
11826             nested_vmx_msr_check_common(vcpu, e))
11827                 return -EINVAL;
11828         return 0;
11829 }
11830
11831 /*
11832  * Load guest's/host's msr at nested entry/exit.
11833  * return 0 for success, entry index for failure.
11834  */
11835 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11836 {
11837         u32 i;
11838         struct vmx_msr_entry e;
11839         struct msr_data msr;
11840
11841         msr.host_initiated = false;
11842         for (i = 0; i < count; i++) {
11843                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
11844                                         &e, sizeof(e))) {
11845                         pr_debug_ratelimited(
11846                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11847                                 __func__, i, gpa + i * sizeof(e));
11848                         goto fail;
11849                 }
11850                 if (nested_vmx_load_msr_check(vcpu, &e)) {
11851                         pr_debug_ratelimited(
11852                                 "%s check failed (%u, 0x%x, 0x%x)\n",
11853                                 __func__, i, e.index, e.reserved);
11854                         goto fail;
11855                 }
11856                 msr.index = e.index;
11857                 msr.data = e.value;
11858                 if (kvm_set_msr(vcpu, &msr)) {
11859                         pr_debug_ratelimited(
11860                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11861                                 __func__, i, e.index, e.value);
11862                         goto fail;
11863                 }
11864         }
11865         return 0;
11866 fail:
11867         return i + 1;
11868 }
11869
11870 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11871 {
11872         u32 i;
11873         struct vmx_msr_entry e;
11874
11875         for (i = 0; i < count; i++) {
11876                 struct msr_data msr_info;
11877                 if (kvm_vcpu_read_guest(vcpu,
11878                                         gpa + i * sizeof(e),
11879                                         &e, 2 * sizeof(u32))) {
11880                         pr_debug_ratelimited(
11881                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11882                                 __func__, i, gpa + i * sizeof(e));
11883                         return -EINVAL;
11884                 }
11885                 if (nested_vmx_store_msr_check(vcpu, &e)) {
11886                         pr_debug_ratelimited(
11887                                 "%s check failed (%u, 0x%x, 0x%x)\n",
11888                                 __func__, i, e.index, e.reserved);
11889                         return -EINVAL;
11890                 }
11891                 msr_info.host_initiated = false;
11892                 msr_info.index = e.index;
11893                 if (kvm_get_msr(vcpu, &msr_info)) {
11894                         pr_debug_ratelimited(
11895                                 "%s cannot read MSR (%u, 0x%x)\n",
11896                                 __func__, i, e.index);
11897                         return -EINVAL;
11898                 }
11899                 if (kvm_vcpu_write_guest(vcpu,
11900                                          gpa + i * sizeof(e) +
11901                                              offsetof(struct vmx_msr_entry, value),
11902                                          &msr_info.data, sizeof(msr_info.data))) {
11903                         pr_debug_ratelimited(
11904                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11905                                 __func__, i, e.index, msr_info.data);
11906                         return -EINVAL;
11907                 }
11908         }
11909         return 0;
11910 }
11911
11912 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
11913 {
11914         unsigned long invalid_mask;
11915
11916         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
11917         return (val & invalid_mask) == 0;
11918 }
11919
11920 /*
11921  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
11922  * emulating VM entry into a guest with EPT enabled.
11923  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11924  * is assigned to entry_failure_code on failure.
11925  */
11926 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
11927                                u32 *entry_failure_code)
11928 {
11929         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
11930                 if (!nested_cr3_valid(vcpu, cr3)) {
11931                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
11932                         return 1;
11933                 }
11934
11935                 /*
11936                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
11937                  * must not be dereferenced.
11938                  */
11939                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
11940                     !nested_ept) {
11941                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
11942                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
11943                                 return 1;
11944                         }
11945                 }
11946         }
11947
11948         if (!nested_ept)
11949                 kvm_mmu_new_cr3(vcpu, cr3, false);
11950
11951         vcpu->arch.cr3 = cr3;
11952         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
11953
11954         kvm_init_mmu(vcpu, false);
11955
11956         return 0;
11957 }
11958
11959 static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11960 {
11961         struct vcpu_vmx *vmx = to_vmx(vcpu);
11962
11963         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
11964         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
11965         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
11966         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
11967         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
11968         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
11969         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
11970         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
11971         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
11972         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
11973         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
11974         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
11975         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
11976         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
11977         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
11978         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
11979         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
11980         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
11981         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
11982         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
11983         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
11984         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
11985         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
11986         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
11987         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
11988         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
11989         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
11990         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
11991         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
11992         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
11993         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
11994
11995         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
11996         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
11997                 vmcs12->guest_pending_dbg_exceptions);
11998         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
11999         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
12000
12001         if (nested_cpu_has_xsaves(vmcs12))
12002                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
12003         vmcs_write64(VMCS_LINK_POINTER, -1ull);
12004
12005         if (cpu_has_vmx_posted_intr())
12006                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
12007
12008         /*
12009          * Whether page-faults are trapped is determined by a combination of
12010          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
12011          * If enable_ept, L0 doesn't care about page faults and we should
12012          * set all of these to L1's desires. However, if !enable_ept, L0 does
12013          * care about (at least some) page faults, and because it is not easy
12014          * (if at all possible?) to merge L0 and L1's desires, we simply ask
12015          * to exit on each and every L2 page fault. This is done by setting
12016          * MASK=MATCH=0 and (see below) EB.PF=1.
12017          * Note that below we don't need special code to set EB.PF beyond the
12018          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
12019          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
12020          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
12021          */
12022         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
12023                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
12024         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
12025                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
12026
12027         /* All VMFUNCs are currently emulated through L0 vmexits.  */
12028         if (cpu_has_vmx_vmfunc())
12029                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
12030
12031         if (cpu_has_vmx_apicv()) {
12032                 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
12033                 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
12034                 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
12035                 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
12036         }
12037
12038         /*
12039          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
12040          * Some constant fields are set here by vmx_set_constant_host_state().
12041          * Other fields are different per CPU, and will be set later when
12042          * vmx_vcpu_load() is called, and when vmx_prepare_switch_to_guest()
12043          * is called.
12044          */
12045         vmx_set_constant_host_state(vmx);
12046
12047         /*
12048          * Set the MSR load/store lists to match L0's settings.
12049          */
12050         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
12051         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
12052         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
12053         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
12054         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
12055
12056         set_cr4_guest_host_mask(vmx);
12057
12058         if (kvm_mpx_supported()) {
12059                 if (vmx->nested.nested_run_pending &&
12060                         (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
12061                         vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
12062                 else
12063                         vmcs_write64(GUEST_BNDCFGS, vmx->nested.vmcs01_guest_bndcfgs);
12064         }
12065
12066         if (enable_vpid) {
12067                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
12068                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
12069                 else
12070                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
12071         }
12072
12073         /*
12074          * L1 may access the L2's PDPTR, so save them to construct vmcs12
12075          */
12076         if (enable_ept) {
12077                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
12078                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
12079                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
12080                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
12081         }
12082
12083         if (cpu_has_vmx_msr_bitmap())
12084                 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
12085 }
12086
12087 /*
12088  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
12089  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
12090  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
12091  * guest in a way that will both be appropriate to L1's requests, and our
12092  * needs. In addition to modifying the active vmcs (which is vmcs02), this
12093  * function also has additional necessary side-effects, like setting various
12094  * vcpu->arch fields.
12095  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
12096  * is assigned to entry_failure_code on failure.
12097  */
12098 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12099                           u32 *entry_failure_code)
12100 {
12101         struct vcpu_vmx *vmx = to_vmx(vcpu);
12102         u32 exec_control, vmcs12_exec_ctrl;
12103
12104         if (vmx->nested.dirty_vmcs12) {
12105                 prepare_vmcs02_full(vcpu, vmcs12);
12106                 vmx->nested.dirty_vmcs12 = false;
12107         }
12108
12109         /*
12110          * First, the fields that are shadowed.  This must be kept in sync
12111          * with vmx_shadow_fields.h.
12112          */
12113
12114         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
12115         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
12116         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
12117         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
12118         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
12119
12120         if (vmx->nested.nested_run_pending &&
12121             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
12122                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
12123                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
12124         } else {
12125                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
12126                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
12127         }
12128         if (vmx->nested.nested_run_pending) {
12129                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
12130                              vmcs12->vm_entry_intr_info_field);
12131                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
12132                              vmcs12->vm_entry_exception_error_code);
12133                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
12134                              vmcs12->vm_entry_instruction_len);
12135                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
12136                              vmcs12->guest_interruptibility_info);
12137                 vmx->loaded_vmcs->nmi_known_unmasked =
12138                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
12139         } else {
12140                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
12141         }
12142         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
12143
12144         exec_control = vmcs12->pin_based_vm_exec_control;
12145
12146         /* Preemption timer setting is computed directly in vmx_vcpu_run.  */
12147         exec_control |= vmcs_config.pin_based_exec_ctrl;
12148         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
12149         vmx->loaded_vmcs->hv_timer_armed = false;
12150
12151         /* Posted interrupts setting is only taken from vmcs12.  */
12152         if (nested_cpu_has_posted_intr(vmcs12)) {
12153                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
12154                 vmx->nested.pi_pending = false;
12155         } else {
12156                 exec_control &= ~PIN_BASED_POSTED_INTR;
12157         }
12158
12159         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
12160
12161         vmx->nested.preemption_timer_expired = false;
12162         if (nested_cpu_has_preemption_timer(vmcs12))
12163                 vmx_start_preemption_timer(vcpu);
12164
12165         if (cpu_has_secondary_exec_ctrls()) {
12166                 exec_control = vmx->secondary_exec_control;
12167
12168                 /* Take the following fields only from vmcs12 */
12169                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
12170                                   SECONDARY_EXEC_ENABLE_INVPCID |
12171                                   SECONDARY_EXEC_RDTSCP |
12172                                   SECONDARY_EXEC_XSAVES |
12173                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
12174                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
12175                                   SECONDARY_EXEC_ENABLE_VMFUNC);
12176                 if (nested_cpu_has(vmcs12,
12177                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
12178                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
12179                                 ~SECONDARY_EXEC_ENABLE_PML;
12180                         exec_control |= vmcs12_exec_ctrl;
12181                 }
12182
12183                 /* VMCS shadowing for L2 is emulated for now */
12184                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
12185
12186                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
12187                         vmcs_write16(GUEST_INTR_STATUS,
12188                                 vmcs12->guest_intr_status);
12189
12190                 /*
12191                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
12192                  * nested_get_vmcs12_pages will either fix it up or
12193                  * remove the VM execution control.
12194                  */
12195                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
12196                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
12197
12198                 if (exec_control & SECONDARY_EXEC_ENCLS_EXITING)
12199                         vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
12200
12201                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
12202         }
12203
12204         /*
12205          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
12206          * entry, but only if the current (host) sp changed from the value
12207          * we wrote last (vmx->host_rsp). This cache is no longer relevant
12208          * if we switch vmcs, and rather than hold a separate cache per vmcs,
12209          * here we just force the write to happen on entry.
12210          */
12211         vmx->host_rsp = 0;
12212
12213         exec_control = vmx_exec_control(vmx); /* L0's desires */
12214         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
12215         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
12216         exec_control &= ~CPU_BASED_TPR_SHADOW;
12217         exec_control |= vmcs12->cpu_based_vm_exec_control;
12218
12219         /*
12220          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
12221          * nested_get_vmcs12_pages can't fix it up, the illegal value
12222          * will result in a VM entry failure.
12223          */
12224         if (exec_control & CPU_BASED_TPR_SHADOW) {
12225                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
12226                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
12227         } else {
12228 #ifdef CONFIG_X86_64
12229                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
12230                                 CPU_BASED_CR8_STORE_EXITING;
12231 #endif
12232         }
12233
12234         /*
12235          * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
12236          * for I/O port accesses.
12237          */
12238         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
12239         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
12240
12241         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
12242
12243         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
12244          * bitwise-or of what L1 wants to trap for L2, and what we want to
12245          * trap. Note that CR0.TS also needs updating - we do this later.
12246          */
12247         update_exception_bitmap(vcpu);
12248         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
12249         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
12250
12251         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
12252          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
12253          * bits are further modified by vmx_set_efer() below.
12254          */
12255         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
12256
12257         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
12258          * emulated by vmx_set_efer(), below.
12259          */
12260         vm_entry_controls_init(vmx,
12261                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
12262                         ~VM_ENTRY_IA32E_MODE) |
12263                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
12264
12265         if (vmx->nested.nested_run_pending &&
12266             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
12267                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
12268                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
12269         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
12270                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
12271         }
12272
12273         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
12274
12275         if (kvm_has_tsc_control)
12276                 decache_tsc_multiplier(vmx);
12277
12278         if (enable_vpid) {
12279                 /*
12280                  * There is no direct mapping between vpid02 and vpid12, the
12281                  * vpid02 is per-vCPU for L0 and reused while the value of
12282                  * vpid12 is changed w/ one invvpid during nested vmentry.
12283                  * The vpid12 is allocated by L1 for L2, so it will not
12284                  * influence global bitmap(for vpid01 and vpid02 allocation)
12285                  * even if spawn a lot of nested vCPUs.
12286                  */
12287                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
12288                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
12289                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
12290                                 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
12291                         }
12292                 } else {
12293                         vmx_flush_tlb(vcpu, true);
12294                 }
12295         }
12296
12297         if (enable_pml) {
12298                 /*
12299                  * Conceptually we want to copy the PML address and index from
12300                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
12301                  * since we always flush the log on each vmexit, this happens
12302                  * to be equivalent to simply resetting the fields in vmcs02.
12303                  */
12304                 ASSERT(vmx->pml_pg);
12305                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
12306                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
12307         }
12308
12309         if (nested_cpu_has_ept(vmcs12)) {
12310                 if (nested_ept_init_mmu_context(vcpu)) {
12311                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
12312                         return 1;
12313                 }
12314         } else if (nested_cpu_has2(vmcs12,
12315                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
12316                 vmx_flush_tlb(vcpu, true);
12317         }
12318
12319         /*
12320          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
12321          * bits which we consider mandatory enabled.
12322          * The CR0_READ_SHADOW is what L2 should have expected to read given
12323          * the specifications by L1; It's not enough to take
12324          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
12325          * have more bits than L1 expected.
12326          */
12327         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
12328         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
12329
12330         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
12331         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
12332
12333         if (vmx->nested.nested_run_pending &&
12334             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
12335                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
12336         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
12337                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
12338         else
12339                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
12340         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
12341         vmx_set_efer(vcpu, vcpu->arch.efer);
12342
12343         /*
12344          * Guest state is invalid and unrestricted guest is disabled,
12345          * which means L1 attempted VMEntry to L2 with invalid state.
12346          * Fail the VMEntry.
12347          */
12348         if (vmx->emulation_required) {
12349                 *entry_failure_code = ENTRY_FAIL_DEFAULT;
12350                 return 1;
12351         }
12352
12353         /* Shadow page tables on either EPT or shadow page tables. */
12354         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
12355                                 entry_failure_code))
12356                 return 1;
12357
12358         if (!enable_ept)
12359                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
12360
12361         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
12362         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
12363         return 0;
12364 }
12365
12366 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
12367 {
12368         if (!nested_cpu_has_nmi_exiting(vmcs12) &&
12369             nested_cpu_has_virtual_nmis(vmcs12))
12370                 return -EINVAL;
12371
12372         if (!nested_cpu_has_virtual_nmis(vmcs12) &&
12373             nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING))
12374                 return -EINVAL;
12375
12376         return 0;
12377 }
12378
12379 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12380 {
12381         struct vcpu_vmx *vmx = to_vmx(vcpu);
12382
12383         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
12384             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
12385                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12386
12387         if (nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id)
12388                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12389
12390         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
12391                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12392
12393         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
12394                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12395
12396         if (nested_vmx_check_apic_access_controls(vcpu, vmcs12))
12397                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12398
12399         if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
12400                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12401
12402         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
12403                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12404
12405         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
12406                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12407
12408         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
12409                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12410
12411         if (nested_vmx_check_shadow_vmcs_controls(vcpu, vmcs12))
12412                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12413
12414         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
12415                                 vmx->nested.msrs.procbased_ctls_low,
12416                                 vmx->nested.msrs.procbased_ctls_high) ||
12417             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
12418              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
12419                                  vmx->nested.msrs.secondary_ctls_low,
12420                                  vmx->nested.msrs.secondary_ctls_high)) ||
12421             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
12422                                 vmx->nested.msrs.pinbased_ctls_low,
12423                                 vmx->nested.msrs.pinbased_ctls_high) ||
12424             !vmx_control_verify(vmcs12->vm_exit_controls,
12425                                 vmx->nested.msrs.exit_ctls_low,
12426                                 vmx->nested.msrs.exit_ctls_high) ||
12427             !vmx_control_verify(vmcs12->vm_entry_controls,
12428                                 vmx->nested.msrs.entry_ctls_low,
12429                                 vmx->nested.msrs.entry_ctls_high))
12430                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12431
12432         if (nested_vmx_check_nmi_controls(vmcs12))
12433                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12434
12435         if (nested_cpu_has_vmfunc(vmcs12)) {
12436                 if (vmcs12->vm_function_control &
12437                     ~vmx->nested.msrs.vmfunc_controls)
12438                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12439
12440                 if (nested_cpu_has_eptp_switching(vmcs12)) {
12441                         if (!nested_cpu_has_ept(vmcs12) ||
12442                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
12443                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12444                 }
12445         }
12446
12447         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
12448                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12449
12450         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
12451             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
12452             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
12453                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
12454
12455         /*
12456          * From the Intel SDM, volume 3:
12457          * Fields relevant to VM-entry event injection must be set properly.
12458          * These fields are the VM-entry interruption-information field, the
12459          * VM-entry exception error code, and the VM-entry instruction length.
12460          */
12461         if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) {
12462                 u32 intr_info = vmcs12->vm_entry_intr_info_field;
12463                 u8 vector = intr_info & INTR_INFO_VECTOR_MASK;
12464                 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK;
12465                 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK;
12466                 bool should_have_error_code;
12467                 bool urg = nested_cpu_has2(vmcs12,
12468                                            SECONDARY_EXEC_UNRESTRICTED_GUEST);
12469                 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE;
12470
12471                 /* VM-entry interruption-info field: interruption type */
12472                 if (intr_type == INTR_TYPE_RESERVED ||
12473                     (intr_type == INTR_TYPE_OTHER_EVENT &&
12474                      !nested_cpu_supports_monitor_trap_flag(vcpu)))
12475                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12476
12477                 /* VM-entry interruption-info field: vector */
12478                 if ((intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) ||
12479                     (intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) ||
12480                     (intr_type == INTR_TYPE_OTHER_EVENT && vector != 0))
12481                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12482
12483                 /* VM-entry interruption-info field: deliver error code */
12484                 should_have_error_code =
12485                         intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode &&
12486                         x86_exception_has_error_code(vector);
12487                 if (has_error_code != should_have_error_code)
12488                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12489
12490                 /* VM-entry exception error code */
12491                 if (has_error_code &&
12492                     vmcs12->vm_entry_exception_error_code & GENMASK(31, 15))
12493                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12494
12495                 /* VM-entry interruption-info field: reserved bits */
12496                 if (intr_info & INTR_INFO_RESVD_BITS_MASK)
12497                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12498
12499                 /* VM-entry instruction length */
12500                 switch (intr_type) {
12501                 case INTR_TYPE_SOFT_EXCEPTION:
12502                 case INTR_TYPE_SOFT_INTR:
12503                 case INTR_TYPE_PRIV_SW_EXCEPTION:
12504                         if ((vmcs12->vm_entry_instruction_len > 15) ||
12505                             (vmcs12->vm_entry_instruction_len == 0 &&
12506                              !nested_cpu_has_zero_length_injection(vcpu)))
12507                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12508                 }
12509         }
12510
12511         return 0;
12512 }
12513
12514 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu,
12515                                           struct vmcs12 *vmcs12)
12516 {
12517         int r;
12518         struct page *page;
12519         struct vmcs12 *shadow;
12520
12521         if (vmcs12->vmcs_link_pointer == -1ull)
12522                 return 0;
12523
12524         if (!page_address_valid(vcpu, vmcs12->vmcs_link_pointer))
12525                 return -EINVAL;
12526
12527         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->vmcs_link_pointer);
12528         if (is_error_page(page))
12529                 return -EINVAL;
12530
12531         r = 0;
12532         shadow = kmap(page);
12533         if (shadow->hdr.revision_id != VMCS12_REVISION ||
12534             shadow->hdr.shadow_vmcs != nested_cpu_has_shadow_vmcs(vmcs12))
12535                 r = -EINVAL;
12536         kunmap(page);
12537         kvm_release_page_clean(page);
12538         return r;
12539 }
12540
12541 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12542                                   u32 *exit_qual)
12543 {
12544         bool ia32e;
12545
12546         *exit_qual = ENTRY_FAIL_DEFAULT;
12547
12548         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
12549             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
12550                 return 1;
12551
12552         if (nested_vmx_check_vmcs_link_ptr(vcpu, vmcs12)) {
12553                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
12554                 return 1;
12555         }
12556
12557         /*
12558          * If the load IA32_EFER VM-entry control is 1, the following checks
12559          * are performed on the field for the IA32_EFER MSR:
12560          * - Bits reserved in the IA32_EFER MSR must be 0.
12561          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
12562          *   the IA-32e mode guest VM-exit control. It must also be identical
12563          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
12564          *   CR0.PG) is 1.
12565          */
12566         if (to_vmx(vcpu)->nested.nested_run_pending &&
12567             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
12568                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
12569                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
12570                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
12571                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
12572                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
12573                         return 1;
12574         }
12575
12576         /*
12577          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
12578          * IA32_EFER MSR must be 0 in the field for that register. In addition,
12579          * the values of the LMA and LME bits in the field must each be that of
12580          * the host address-space size VM-exit control.
12581          */
12582         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
12583                 ia32e = (vmcs12->vm_exit_controls &
12584                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
12585                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
12586                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
12587                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
12588                         return 1;
12589         }
12590
12591         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
12592                 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
12593                 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
12594                         return 1;
12595
12596         return 0;
12597 }
12598
12599 /*
12600  * If exit_qual is NULL, this is being called from state restore (either RSM
12601  * or KVM_SET_NESTED_STATE).  Otherwise it's called from vmlaunch/vmresume.
12602  */
12603 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, u32 *exit_qual)
12604 {
12605         struct vcpu_vmx *vmx = to_vmx(vcpu);
12606         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12607         bool from_vmentry = !!exit_qual;
12608         u32 dummy_exit_qual;
12609         bool evaluate_pending_interrupts;
12610         int r = 0;
12611
12612         evaluate_pending_interrupts = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
12613                 (CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_VIRTUAL_NMI_PENDING);
12614         if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu))
12615                 evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu);
12616
12617         enter_guest_mode(vcpu);
12618
12619         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
12620                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
12621         if (kvm_mpx_supported() &&
12622                 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
12623                 vmx->nested.vmcs01_guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
12624
12625         vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
12626         vmx_segment_cache_clear(vmx);
12627
12628         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12629                 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
12630
12631         r = EXIT_REASON_INVALID_STATE;
12632         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry ? exit_qual : &dummy_exit_qual))
12633                 goto fail;
12634
12635         if (from_vmentry) {
12636                 nested_get_vmcs12_pages(vcpu);
12637
12638                 r = EXIT_REASON_MSR_LOAD_FAIL;
12639                 *exit_qual = nested_vmx_load_msr(vcpu,
12640                                                  vmcs12->vm_entry_msr_load_addr,
12641                                                  vmcs12->vm_entry_msr_load_count);
12642                 if (*exit_qual)
12643                         goto fail;
12644         } else {
12645                 /*
12646                  * The MMU is not initialized to point at the right entities yet and
12647                  * "get pages" would need to read data from the guest (i.e. we will
12648                  * need to perform gpa to hpa translation). Request a call
12649                  * to nested_get_vmcs12_pages before the next VM-entry.  The MSRs
12650                  * have already been set at vmentry time and should not be reset.
12651                  */
12652                 kvm_make_request(KVM_REQ_GET_VMCS12_PAGES, vcpu);
12653         }
12654
12655         /*
12656          * If L1 had a pending IRQ/NMI until it executed
12657          * VMLAUNCH/VMRESUME which wasn't delivered because it was
12658          * disallowed (e.g. interrupts disabled), L0 needs to
12659          * evaluate if this pending event should cause an exit from L2
12660          * to L1 or delivered directly to L2 (e.g. In case L1 don't
12661          * intercept EXTERNAL_INTERRUPT).
12662          *
12663          * Usually this would be handled by the processor noticing an
12664          * IRQ/NMI window request, or checking RVI during evaluation of
12665          * pending virtual interrupts.  However, this setting was done
12666          * on VMCS01 and now VMCS02 is active instead. Thus, we force L0
12667          * to perform pending event evaluation by requesting a KVM_REQ_EVENT.
12668          */
12669         if (unlikely(evaluate_pending_interrupts))
12670                 kvm_make_request(KVM_REQ_EVENT, vcpu);
12671
12672         /*
12673          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
12674          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
12675          * returned as far as L1 is concerned. It will only return (and set
12676          * the success flag) when L2 exits (see nested_vmx_vmexit()).
12677          */
12678         return 0;
12679
12680 fail:
12681         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12682                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
12683         leave_guest_mode(vcpu);
12684         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12685         return r;
12686 }
12687
12688 /*
12689  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
12690  * for running an L2 nested guest.
12691  */
12692 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
12693 {
12694         struct vmcs12 *vmcs12;
12695         struct vcpu_vmx *vmx = to_vmx(vcpu);
12696         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
12697         u32 exit_qual;
12698         int ret;
12699
12700         if (!nested_vmx_check_permission(vcpu))
12701                 return 1;
12702
12703         if (!nested_vmx_check_vmcs12(vcpu))
12704                 goto out;
12705
12706         vmcs12 = get_vmcs12(vcpu);
12707
12708         /*
12709          * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact
12710          * that there *is* a valid VMCS pointer, RFLAGS.CF is set
12711          * rather than RFLAGS.ZF, and no error number is stored to the
12712          * VM-instruction error field.
12713          */
12714         if (vmcs12->hdr.shadow_vmcs) {
12715                 nested_vmx_failInvalid(vcpu);
12716                 goto out;
12717         }
12718
12719         if (enable_shadow_vmcs)
12720                 copy_shadow_to_vmcs12(vmx);
12721
12722         /*
12723          * The nested entry process starts with enforcing various prerequisites
12724          * on vmcs12 as required by the Intel SDM, and act appropriately when
12725          * they fail: As the SDM explains, some conditions should cause the
12726          * instruction to fail, while others will cause the instruction to seem
12727          * to succeed, but return an EXIT_REASON_INVALID_STATE.
12728          * To speed up the normal (success) code path, we should avoid checking
12729          * for misconfigurations which will anyway be caught by the processor
12730          * when using the merged vmcs02.
12731          */
12732         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
12733                 nested_vmx_failValid(vcpu,
12734                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
12735                 goto out;
12736         }
12737
12738         if (vmcs12->launch_state == launch) {
12739                 nested_vmx_failValid(vcpu,
12740                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
12741                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
12742                 goto out;
12743         }
12744
12745         ret = check_vmentry_prereqs(vcpu, vmcs12);
12746         if (ret) {
12747                 nested_vmx_failValid(vcpu, ret);
12748                 goto out;
12749         }
12750
12751         /*
12752          * After this point, the trap flag no longer triggers a singlestep trap
12753          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
12754          * This is not 100% correct; for performance reasons, we delegate most
12755          * of the checks on host state to the processor.  If those fail,
12756          * the singlestep trap is missed.
12757          */
12758         skip_emulated_instruction(vcpu);
12759
12760         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
12761         if (ret) {
12762                 nested_vmx_entry_failure(vcpu, vmcs12,
12763                                          EXIT_REASON_INVALID_STATE, exit_qual);
12764                 return 1;
12765         }
12766
12767         /*
12768          * We're finally done with prerequisite checking, and can start with
12769          * the nested entry.
12770          */
12771
12772         vmx->nested.nested_run_pending = 1;
12773         ret = enter_vmx_non_root_mode(vcpu, &exit_qual);
12774         if (ret) {
12775                 nested_vmx_entry_failure(vcpu, vmcs12, ret, exit_qual);
12776                 vmx->nested.nested_run_pending = 0;
12777                 return 1;
12778         }
12779
12780         /* Hide L1D cache contents from the nested guest.  */
12781         vmx->vcpu.arch.l1tf_flush_l1d = true;
12782
12783         /*
12784          * Must happen outside of enter_vmx_non_root_mode() as it will
12785          * also be used as part of restoring nVMX state for
12786          * snapshot restore (migration).
12787          *
12788          * In this flow, it is assumed that vmcs12 cache was
12789          * trasferred as part of captured nVMX state and should
12790          * therefore not be read from guest memory (which may not
12791          * exist on destination host yet).
12792          */
12793         nested_cache_shadow_vmcs12(vcpu, vmcs12);
12794
12795         /*
12796          * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
12797          * by event injection, halt vcpu.
12798          */
12799         if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
12800             !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK)) {
12801                 vmx->nested.nested_run_pending = 0;
12802                 return kvm_vcpu_halt(vcpu);
12803         }
12804         return 1;
12805
12806 out:
12807         return kvm_skip_emulated_instruction(vcpu);
12808 }
12809
12810 /*
12811  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
12812  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
12813  * This function returns the new value we should put in vmcs12.guest_cr0.
12814  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
12815  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
12816  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
12817  *     didn't trap the bit, because if L1 did, so would L0).
12818  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
12819  *     been modified by L2, and L1 knows it. So just leave the old value of
12820  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
12821  *     isn't relevant, because if L0 traps this bit it can set it to anything.
12822  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
12823  *     changed these bits, and therefore they need to be updated, but L0
12824  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
12825  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
12826  */
12827 static inline unsigned long
12828 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12829 {
12830         return
12831         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
12832         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
12833         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
12834                         vcpu->arch.cr0_guest_owned_bits));
12835 }
12836
12837 static inline unsigned long
12838 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12839 {
12840         return
12841         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
12842         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
12843         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
12844                         vcpu->arch.cr4_guest_owned_bits));
12845 }
12846
12847 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
12848                                        struct vmcs12 *vmcs12)
12849 {
12850         u32 idt_vectoring;
12851         unsigned int nr;
12852
12853         if (vcpu->arch.exception.injected) {
12854                 nr = vcpu->arch.exception.nr;
12855                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
12856
12857                 if (kvm_exception_is_soft(nr)) {
12858                         vmcs12->vm_exit_instruction_len =
12859                                 vcpu->arch.event_exit_inst_len;
12860                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
12861                 } else
12862                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
12863
12864                 if (vcpu->arch.exception.has_error_code) {
12865                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
12866                         vmcs12->idt_vectoring_error_code =
12867                                 vcpu->arch.exception.error_code;
12868                 }
12869
12870                 vmcs12->idt_vectoring_info_field = idt_vectoring;
12871         } else if (vcpu->arch.nmi_injected) {
12872                 vmcs12->idt_vectoring_info_field =
12873                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
12874         } else if (vcpu->arch.interrupt.injected) {
12875                 nr = vcpu->arch.interrupt.nr;
12876                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
12877
12878                 if (vcpu->arch.interrupt.soft) {
12879                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
12880                         vmcs12->vm_entry_instruction_len =
12881                                 vcpu->arch.event_exit_inst_len;
12882                 } else
12883                         idt_vectoring |= INTR_TYPE_EXT_INTR;
12884
12885                 vmcs12->idt_vectoring_info_field = idt_vectoring;
12886         }
12887 }
12888
12889 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
12890 {
12891         struct vcpu_vmx *vmx = to_vmx(vcpu);
12892         unsigned long exit_qual;
12893         bool block_nested_events =
12894             vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
12895
12896         if (vcpu->arch.exception.pending &&
12897                 nested_vmx_check_exception(vcpu, &exit_qual)) {
12898                 if (block_nested_events)
12899                         return -EBUSY;
12900                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
12901                 return 0;
12902         }
12903
12904         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
12905             vmx->nested.preemption_timer_expired) {
12906                 if (block_nested_events)
12907                         return -EBUSY;
12908                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
12909                 return 0;
12910         }
12911
12912         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
12913                 if (block_nested_events)
12914                         return -EBUSY;
12915                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
12916                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
12917                                   INTR_INFO_VALID_MASK, 0);
12918                 /*
12919                  * The NMI-triggered VM exit counts as injection:
12920                  * clear this one and block further NMIs.
12921                  */
12922                 vcpu->arch.nmi_pending = 0;
12923                 vmx_set_nmi_mask(vcpu, true);
12924                 return 0;
12925         }
12926
12927         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
12928             nested_exit_on_intr(vcpu)) {
12929                 if (block_nested_events)
12930                         return -EBUSY;
12931                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
12932                 return 0;
12933         }
12934
12935         vmx_complete_nested_posted_interrupt(vcpu);
12936         return 0;
12937 }
12938
12939 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
12940 {
12941         to_vmx(vcpu)->req_immediate_exit = true;
12942 }
12943
12944 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
12945 {
12946         ktime_t remaining =
12947                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
12948         u64 value;
12949
12950         if (ktime_to_ns(remaining) <= 0)
12951                 return 0;
12952
12953         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
12954         do_div(value, 1000000);
12955         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
12956 }
12957
12958 /*
12959  * Update the guest state fields of vmcs12 to reflect changes that
12960  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
12961  * VM-entry controls is also updated, since this is really a guest
12962  * state bit.)
12963  */
12964 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12965 {
12966         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
12967         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
12968
12969         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
12970         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
12971         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
12972
12973         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
12974         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
12975         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
12976         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
12977         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
12978         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
12979         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
12980         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
12981         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
12982         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
12983         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
12984         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
12985         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
12986         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
12987         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
12988         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
12989         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
12990         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
12991         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
12992         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
12993         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
12994         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
12995         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
12996         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
12997         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
12998         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
12999         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
13000         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
13001         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
13002         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
13003         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
13004         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
13005         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
13006         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
13007         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
13008         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
13009
13010         vmcs12->guest_interruptibility_info =
13011                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
13012         vmcs12->guest_pending_dbg_exceptions =
13013                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
13014         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
13015                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
13016         else
13017                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
13018
13019         if (nested_cpu_has_preemption_timer(vmcs12)) {
13020                 if (vmcs12->vm_exit_controls &
13021                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
13022                         vmcs12->vmx_preemption_timer_value =
13023                                 vmx_get_preemption_timer_value(vcpu);
13024                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
13025         }
13026
13027         /*
13028          * In some cases (usually, nested EPT), L2 is allowed to change its
13029          * own CR3 without exiting. If it has changed it, we must keep it.
13030          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
13031          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
13032          *
13033          * Additionally, restore L2's PDPTR to vmcs12.
13034          */
13035         if (enable_ept) {
13036                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
13037                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
13038                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
13039                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
13040                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
13041         }
13042
13043         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
13044
13045         if (nested_cpu_has_vid(vmcs12))
13046                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
13047
13048         vmcs12->vm_entry_controls =
13049                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
13050                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
13051
13052         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
13053                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
13054                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
13055         }
13056
13057         /* TODO: These cannot have changed unless we have MSR bitmaps and
13058          * the relevant bit asks not to trap the change */
13059         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
13060                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
13061         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
13062                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
13063         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
13064         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
13065         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
13066         if (kvm_mpx_supported())
13067                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
13068 }
13069
13070 /*
13071  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
13072  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
13073  * and this function updates it to reflect the changes to the guest state while
13074  * L2 was running (and perhaps made some exits which were handled directly by L0
13075  * without going back to L1), and to reflect the exit reason.
13076  * Note that we do not have to copy here all VMCS fields, just those that
13077  * could have changed by the L2 guest or the exit - i.e., the guest-state and
13078  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
13079  * which already writes to vmcs12 directly.
13080  */
13081 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
13082                            u32 exit_reason, u32 exit_intr_info,
13083                            unsigned long exit_qualification)
13084 {
13085         /* update guest state fields: */
13086         sync_vmcs12(vcpu, vmcs12);
13087
13088         /* update exit information fields: */
13089
13090         vmcs12->vm_exit_reason = exit_reason;
13091         vmcs12->exit_qualification = exit_qualification;
13092         vmcs12->vm_exit_intr_info = exit_intr_info;
13093
13094         vmcs12->idt_vectoring_info_field = 0;
13095         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
13096         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
13097
13098         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
13099                 vmcs12->launch_state = 1;
13100
13101                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
13102                  * instead of reading the real value. */
13103                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
13104
13105                 /*
13106                  * Transfer the event that L0 or L1 may wanted to inject into
13107                  * L2 to IDT_VECTORING_INFO_FIELD.
13108                  */
13109                 vmcs12_save_pending_event(vcpu, vmcs12);
13110         }
13111
13112         /*
13113          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
13114          * preserved above and would only end up incorrectly in L1.
13115          */
13116         vcpu->arch.nmi_injected = false;
13117         kvm_clear_exception_queue(vcpu);
13118         kvm_clear_interrupt_queue(vcpu);
13119 }
13120
13121 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
13122                         struct vmcs12 *vmcs12)
13123 {
13124         u32 entry_failure_code;
13125
13126         nested_ept_uninit_mmu_context(vcpu);
13127
13128         /*
13129          * Only PDPTE load can fail as the value of cr3 was checked on entry and
13130          * couldn't have changed.
13131          */
13132         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
13133                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
13134
13135         if (!enable_ept)
13136                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
13137 }
13138
13139 /*
13140  * A part of what we need to when the nested L2 guest exits and we want to
13141  * run its L1 parent, is to reset L1's guest state to the host state specified
13142  * in vmcs12.
13143  * This function is to be called not only on normal nested exit, but also on
13144  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
13145  * Failures During or After Loading Guest State").
13146  * This function should be called when the active VMCS is L1's (vmcs01).
13147  */
13148 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
13149                                    struct vmcs12 *vmcs12)
13150 {
13151         struct kvm_segment seg;
13152
13153         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
13154                 vcpu->arch.efer = vmcs12->host_ia32_efer;
13155         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
13156                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
13157         else
13158                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
13159         vmx_set_efer(vcpu, vcpu->arch.efer);
13160
13161         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
13162         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
13163         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
13164         /*
13165          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
13166          * actually changed, because vmx_set_cr0 refers to efer set above.
13167          *
13168          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
13169          * (KVM doesn't change it);
13170          */
13171         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
13172         vmx_set_cr0(vcpu, vmcs12->host_cr0);
13173
13174         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
13175         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
13176         vmx_set_cr4(vcpu, vmcs12->host_cr4);
13177
13178         load_vmcs12_mmu_host_state(vcpu, vmcs12);
13179
13180         /*
13181          * If vmcs01 don't use VPID, CPU flushes TLB on every
13182          * VMEntry/VMExit. Thus, no need to flush TLB.
13183          *
13184          * If vmcs12 uses VPID, TLB entries populated by L2 are
13185          * tagged with vmx->nested.vpid02 while L1 entries are tagged
13186          * with vmx->vpid. Thus, no need to flush TLB.
13187          *
13188          * Therefore, flush TLB only in case vmcs01 uses VPID and
13189          * vmcs12 don't use VPID as in this case L1 & L2 TLB entries
13190          * are both tagged with vmx->vpid.
13191          */
13192         if (enable_vpid &&
13193             !(nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02)) {
13194                 vmx_flush_tlb(vcpu, true);
13195         }
13196
13197         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
13198         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
13199         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
13200         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
13201         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
13202         vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
13203         vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
13204
13205         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
13206         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
13207                 vmcs_write64(GUEST_BNDCFGS, 0);
13208
13209         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
13210                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
13211                 vcpu->arch.pat = vmcs12->host_ia32_pat;
13212         }
13213         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
13214                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
13215                         vmcs12->host_ia32_perf_global_ctrl);
13216
13217         /* Set L1 segment info according to Intel SDM
13218             27.5.2 Loading Host Segment and Descriptor-Table Registers */
13219         seg = (struct kvm_segment) {
13220                 .base = 0,
13221                 .limit = 0xFFFFFFFF,
13222                 .selector = vmcs12->host_cs_selector,
13223                 .type = 11,
13224                 .present = 1,
13225                 .s = 1,
13226                 .g = 1
13227         };
13228         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
13229                 seg.l = 1;
13230         else
13231                 seg.db = 1;
13232         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
13233         seg = (struct kvm_segment) {
13234                 .base = 0,
13235                 .limit = 0xFFFFFFFF,
13236                 .type = 3,
13237                 .present = 1,
13238                 .s = 1,
13239                 .db = 1,
13240                 .g = 1
13241         };
13242         seg.selector = vmcs12->host_ds_selector;
13243         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
13244         seg.selector = vmcs12->host_es_selector;
13245         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
13246         seg.selector = vmcs12->host_ss_selector;
13247         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
13248         seg.selector = vmcs12->host_fs_selector;
13249         seg.base = vmcs12->host_fs_base;
13250         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
13251         seg.selector = vmcs12->host_gs_selector;
13252         seg.base = vmcs12->host_gs_base;
13253         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
13254         seg = (struct kvm_segment) {
13255                 .base = vmcs12->host_tr_base,
13256                 .limit = 0x67,
13257                 .selector = vmcs12->host_tr_selector,
13258                 .type = 11,
13259                 .present = 1
13260         };
13261         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
13262
13263         kvm_set_dr(vcpu, 7, 0x400);
13264         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
13265
13266         if (cpu_has_vmx_msr_bitmap())
13267                 vmx_update_msr_bitmap(vcpu);
13268
13269         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
13270                                 vmcs12->vm_exit_msr_load_count))
13271                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
13272 }
13273
13274 /*
13275  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
13276  * and modify vmcs12 to make it see what it would expect to see there if
13277  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
13278  */
13279 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
13280                               u32 exit_intr_info,
13281                               unsigned long exit_qualification)
13282 {
13283         struct vcpu_vmx *vmx = to_vmx(vcpu);
13284         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
13285
13286         /* trying to cancel vmlaunch/vmresume is a bug */
13287         WARN_ON_ONCE(vmx->nested.nested_run_pending);
13288
13289         /*
13290          * The only expected VM-instruction error is "VM entry with
13291          * invalid control field(s)." Anything else indicates a
13292          * problem with L0.
13293          */
13294         WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
13295                                    VMXERR_ENTRY_INVALID_CONTROL_FIELD));
13296
13297         leave_guest_mode(vcpu);
13298
13299         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
13300                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
13301
13302         if (likely(!vmx->fail)) {
13303                 if (exit_reason == -1)
13304                         sync_vmcs12(vcpu, vmcs12);
13305                 else
13306                         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
13307                                        exit_qualification);
13308
13309                 /*
13310                  * Must happen outside of sync_vmcs12() as it will
13311                  * also be used to capture vmcs12 cache as part of
13312                  * capturing nVMX state for snapshot (migration).
13313                  *
13314                  * Otherwise, this flush will dirty guest memory at a
13315                  * point it is already assumed by user-space to be
13316                  * immutable.
13317                  */
13318                 nested_flush_cached_shadow_vmcs12(vcpu, vmcs12);
13319
13320                 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
13321                                          vmcs12->vm_exit_msr_store_count))
13322                         nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
13323         }
13324
13325         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
13326         vm_entry_controls_reset_shadow(vmx);
13327         vm_exit_controls_reset_shadow(vmx);
13328         vmx_segment_cache_clear(vmx);
13329
13330         /* Update any VMCS fields that might have changed while L2 ran */
13331         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
13332         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
13333         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
13334
13335         if (kvm_has_tsc_control)
13336                 decache_tsc_multiplier(vmx);
13337
13338         if (vmx->nested.change_vmcs01_virtual_apic_mode) {
13339                 vmx->nested.change_vmcs01_virtual_apic_mode = false;
13340                 vmx_set_virtual_apic_mode(vcpu);
13341         } else if (!nested_cpu_has_ept(vmcs12) &&
13342                    nested_cpu_has2(vmcs12,
13343                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
13344                 vmx_flush_tlb(vcpu, true);
13345         }
13346
13347         /* This is needed for same reason as it was needed in prepare_vmcs02 */
13348         vmx->host_rsp = 0;
13349
13350         /* Unpin physical memory we referred to in vmcs02 */
13351         if (vmx->nested.apic_access_page) {
13352                 kvm_release_page_dirty(vmx->nested.apic_access_page);
13353                 vmx->nested.apic_access_page = NULL;
13354         }
13355         if (vmx->nested.virtual_apic_page) {
13356                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
13357                 vmx->nested.virtual_apic_page = NULL;
13358         }
13359         if (vmx->nested.pi_desc_page) {
13360                 kunmap(vmx->nested.pi_desc_page);
13361                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
13362                 vmx->nested.pi_desc_page = NULL;
13363                 vmx->nested.pi_desc = NULL;
13364         }
13365
13366         /*
13367          * We are now running in L2, mmu_notifier will force to reload the
13368          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
13369          */
13370         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
13371
13372         if (enable_shadow_vmcs && exit_reason != -1)
13373                 vmx->nested.sync_shadow_vmcs = true;
13374
13375         /* in case we halted in L2 */
13376         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13377
13378         if (likely(!vmx->fail)) {
13379                 /*
13380                  * TODO: SDM says that with acknowledge interrupt on
13381                  * exit, bit 31 of the VM-exit interrupt information
13382                  * (valid interrupt) is always set to 1 on
13383                  * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
13384                  * need kvm_cpu_has_interrupt().  See the commit
13385                  * message for details.
13386                  */
13387                 if (nested_exit_intr_ack_set(vcpu) &&
13388                     exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
13389                     kvm_cpu_has_interrupt(vcpu)) {
13390                         int irq = kvm_cpu_get_interrupt(vcpu);
13391                         WARN_ON(irq < 0);
13392                         vmcs12->vm_exit_intr_info = irq |
13393                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
13394                 }
13395
13396                 if (exit_reason != -1)
13397                         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
13398                                                        vmcs12->exit_qualification,
13399                                                        vmcs12->idt_vectoring_info_field,
13400                                                        vmcs12->vm_exit_intr_info,
13401                                                        vmcs12->vm_exit_intr_error_code,
13402                                                        KVM_ISA_VMX);
13403
13404                 load_vmcs12_host_state(vcpu, vmcs12);
13405
13406                 return;
13407         }
13408
13409         /*
13410          * After an early L2 VM-entry failure, we're now back
13411          * in L1 which thinks it just finished a VMLAUNCH or
13412          * VMRESUME instruction, so we need to set the failure
13413          * flag and the VM-instruction error field of the VMCS
13414          * accordingly.
13415          */
13416         nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
13417
13418         load_vmcs12_mmu_host_state(vcpu, vmcs12);
13419
13420         /*
13421          * The emulated instruction was already skipped in
13422          * nested_vmx_run, but the updated RIP was never
13423          * written back to the vmcs01.
13424          */
13425         skip_emulated_instruction(vcpu);
13426         vmx->fail = 0;
13427 }
13428
13429 /*
13430  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
13431  */
13432 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
13433 {
13434         if (is_guest_mode(vcpu)) {
13435                 to_vmx(vcpu)->nested.nested_run_pending = 0;
13436                 nested_vmx_vmexit(vcpu, -1, 0, 0);
13437         }
13438         free_nested(to_vmx(vcpu));
13439 }
13440
13441 /*
13442  * L1's failure to enter L2 is a subset of a normal exit, as explained in
13443  * 23.7 "VM-entry failures during or after loading guest state" (this also
13444  * lists the acceptable exit-reason and exit-qualification parameters).
13445  * It should only be called before L2 actually succeeded to run, and when
13446  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
13447  */
13448 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
13449                         struct vmcs12 *vmcs12,
13450                         u32 reason, unsigned long qualification)
13451 {
13452         load_vmcs12_host_state(vcpu, vmcs12);
13453         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
13454         vmcs12->exit_qualification = qualification;
13455         nested_vmx_succeed(vcpu);
13456         if (enable_shadow_vmcs)
13457                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
13458 }
13459
13460 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
13461                                struct x86_instruction_info *info,
13462                                enum x86_intercept_stage stage)
13463 {
13464         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
13465         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
13466
13467         /*
13468          * RDPID causes #UD if disabled through secondary execution controls.
13469          * Because it is marked as EmulateOnUD, we need to intercept it here.
13470          */
13471         if (info->intercept == x86_intercept_rdtscp &&
13472             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
13473                 ctxt->exception.vector = UD_VECTOR;
13474                 ctxt->exception.error_code_valid = false;
13475                 return X86EMUL_PROPAGATE_FAULT;
13476         }
13477
13478         /* TODO: check more intercepts... */
13479         return X86EMUL_CONTINUE;
13480 }
13481
13482 #ifdef CONFIG_X86_64
13483 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
13484 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
13485                                   u64 divisor, u64 *result)
13486 {
13487         u64 low = a << shift, high = a >> (64 - shift);
13488
13489         /* To avoid the overflow on divq */
13490         if (high >= divisor)
13491                 return 1;
13492
13493         /* Low hold the result, high hold rem which is discarded */
13494         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
13495             "rm" (divisor), "0" (low), "1" (high));
13496         *result = low;
13497
13498         return 0;
13499 }
13500
13501 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
13502 {
13503         struct vcpu_vmx *vmx;
13504         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
13505
13506         if (kvm_mwait_in_guest(vcpu->kvm))
13507                 return -EOPNOTSUPP;
13508
13509         vmx = to_vmx(vcpu);
13510         tscl = rdtsc();
13511         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
13512         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
13513         lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns);
13514
13515         if (delta_tsc > lapic_timer_advance_cycles)
13516                 delta_tsc -= lapic_timer_advance_cycles;
13517         else
13518                 delta_tsc = 0;
13519
13520         /* Convert to host delta tsc if tsc scaling is enabled */
13521         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
13522                         u64_shl_div_u64(delta_tsc,
13523                                 kvm_tsc_scaling_ratio_frac_bits,
13524                                 vcpu->arch.tsc_scaling_ratio,
13525                                 &delta_tsc))
13526                 return -ERANGE;
13527
13528         /*
13529          * If the delta tsc can't fit in the 32 bit after the multi shift,
13530          * we can't use the preemption timer.
13531          * It's possible that it fits on later vmentries, but checking
13532          * on every vmentry is costly so we just use an hrtimer.
13533          */
13534         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
13535                 return -ERANGE;
13536
13537         vmx->hv_deadline_tsc = tscl + delta_tsc;
13538         return delta_tsc == 0;
13539 }
13540
13541 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
13542 {
13543         to_vmx(vcpu)->hv_deadline_tsc = -1;
13544 }
13545 #endif
13546
13547 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
13548 {
13549         if (!kvm_pause_in_guest(vcpu->kvm))
13550                 shrink_ple_window(vcpu);
13551 }
13552
13553 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
13554                                      struct kvm_memory_slot *slot)
13555 {
13556         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
13557         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
13558 }
13559
13560 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
13561                                        struct kvm_memory_slot *slot)
13562 {
13563         kvm_mmu_slot_set_dirty(kvm, slot);
13564 }
13565
13566 static void vmx_flush_log_dirty(struct kvm *kvm)
13567 {
13568         kvm_flush_pml_buffers(kvm);
13569 }
13570
13571 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
13572 {
13573         struct vmcs12 *vmcs12;
13574         struct vcpu_vmx *vmx = to_vmx(vcpu);
13575         gpa_t gpa;
13576         struct page *page = NULL;
13577         u64 *pml_address;
13578
13579         if (is_guest_mode(vcpu)) {
13580                 WARN_ON_ONCE(vmx->nested.pml_full);
13581
13582                 /*
13583                  * Check if PML is enabled for the nested guest.
13584                  * Whether eptp bit 6 is set is already checked
13585                  * as part of A/D emulation.
13586                  */
13587                 vmcs12 = get_vmcs12(vcpu);
13588                 if (!nested_cpu_has_pml(vmcs12))
13589                         return 0;
13590
13591                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
13592                         vmx->nested.pml_full = true;
13593                         return 1;
13594                 }
13595
13596                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
13597
13598                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
13599                 if (is_error_page(page))
13600                         return 0;
13601
13602                 pml_address = kmap(page);
13603                 pml_address[vmcs12->guest_pml_index--] = gpa;
13604                 kunmap(page);
13605                 kvm_release_page_clean(page);
13606         }
13607
13608         return 0;
13609 }
13610
13611 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
13612                                            struct kvm_memory_slot *memslot,
13613                                            gfn_t offset, unsigned long mask)
13614 {
13615         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
13616 }
13617
13618 static void __pi_post_block(struct kvm_vcpu *vcpu)
13619 {
13620         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
13621         struct pi_desc old, new;
13622         unsigned int dest;
13623
13624         do {
13625                 old.control = new.control = pi_desc->control;
13626                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
13627                      "Wakeup handler not enabled while the VCPU is blocked\n");
13628
13629                 dest = cpu_physical_id(vcpu->cpu);
13630
13631                 if (x2apic_enabled())
13632                         new.ndst = dest;
13633                 else
13634                         new.ndst = (dest << 8) & 0xFF00;
13635
13636                 /* set 'NV' to 'notification vector' */
13637                 new.nv = POSTED_INTR_VECTOR;
13638         } while (cmpxchg64(&pi_desc->control, old.control,
13639                            new.control) != old.control);
13640
13641         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
13642                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13643                 list_del(&vcpu->blocked_vcpu_list);
13644                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13645                 vcpu->pre_pcpu = -1;
13646         }
13647 }
13648
13649 /*
13650  * This routine does the following things for vCPU which is going
13651  * to be blocked if VT-d PI is enabled.
13652  * - Store the vCPU to the wakeup list, so when interrupts happen
13653  *   we can find the right vCPU to wake up.
13654  * - Change the Posted-interrupt descriptor as below:
13655  *      'NDST' <-- vcpu->pre_pcpu
13656  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
13657  * - If 'ON' is set during this process, which means at least one
13658  *   interrupt is posted for this vCPU, we cannot block it, in
13659  *   this case, return 1, otherwise, return 0.
13660  *
13661  */
13662 static int pi_pre_block(struct kvm_vcpu *vcpu)
13663 {
13664         unsigned int dest;
13665         struct pi_desc old, new;
13666         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
13667
13668         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
13669                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
13670                 !kvm_vcpu_apicv_active(vcpu))
13671                 return 0;
13672
13673         WARN_ON(irqs_disabled());
13674         local_irq_disable();
13675         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
13676                 vcpu->pre_pcpu = vcpu->cpu;
13677                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13678                 list_add_tail(&vcpu->blocked_vcpu_list,
13679                               &per_cpu(blocked_vcpu_on_cpu,
13680                                        vcpu->pre_pcpu));
13681                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13682         }
13683
13684         do {
13685                 old.control = new.control = pi_desc->control;
13686
13687                 WARN((pi_desc->sn == 1),
13688                      "Warning: SN field of posted-interrupts "
13689                      "is set before blocking\n");
13690
13691                 /*
13692                  * Since vCPU can be preempted during this process,
13693                  * vcpu->cpu could be different with pre_pcpu, we
13694                  * need to set pre_pcpu as the destination of wakeup
13695                  * notification event, then we can find the right vCPU
13696                  * to wakeup in wakeup handler if interrupts happen
13697                  * when the vCPU is in blocked state.
13698                  */
13699                 dest = cpu_physical_id(vcpu->pre_pcpu);
13700
13701                 if (x2apic_enabled())
13702                         new.ndst = dest;
13703                 else
13704                         new.ndst = (dest << 8) & 0xFF00;
13705
13706                 /* set 'NV' to 'wakeup vector' */
13707                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
13708         } while (cmpxchg64(&pi_desc->control, old.control,
13709                            new.control) != old.control);
13710
13711         /* We should not block the vCPU if an interrupt is posted for it.  */
13712         if (pi_test_on(pi_desc) == 1)
13713                 __pi_post_block(vcpu);
13714
13715         local_irq_enable();
13716         return (vcpu->pre_pcpu == -1);
13717 }
13718
13719 static int vmx_pre_block(struct kvm_vcpu *vcpu)
13720 {
13721         if (pi_pre_block(vcpu))
13722                 return 1;
13723
13724         if (kvm_lapic_hv_timer_in_use(vcpu))
13725                 kvm_lapic_switch_to_sw_timer(vcpu);
13726
13727         return 0;
13728 }
13729
13730 static void pi_post_block(struct kvm_vcpu *vcpu)
13731 {
13732         if (vcpu->pre_pcpu == -1)
13733                 return;
13734
13735         WARN_ON(irqs_disabled());
13736         local_irq_disable();
13737         __pi_post_block(vcpu);
13738         local_irq_enable();
13739 }
13740
13741 static void vmx_post_block(struct kvm_vcpu *vcpu)
13742 {
13743         if (kvm_x86_ops->set_hv_timer)
13744                 kvm_lapic_switch_to_hv_timer(vcpu);
13745
13746         pi_post_block(vcpu);
13747 }
13748
13749 /*
13750  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
13751  *
13752  * @kvm: kvm
13753  * @host_irq: host irq of the interrupt
13754  * @guest_irq: gsi of the interrupt
13755  * @set: set or unset PI
13756  * returns 0 on success, < 0 on failure
13757  */
13758 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
13759                               uint32_t guest_irq, bool set)
13760 {
13761         struct kvm_kernel_irq_routing_entry *e;
13762         struct kvm_irq_routing_table *irq_rt;
13763         struct kvm_lapic_irq irq;
13764         struct kvm_vcpu *vcpu;
13765         struct vcpu_data vcpu_info;
13766         int idx, ret = 0;
13767
13768         if (!kvm_arch_has_assigned_device(kvm) ||
13769                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
13770                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
13771                 return 0;
13772
13773         idx = srcu_read_lock(&kvm->irq_srcu);
13774         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
13775         if (guest_irq >= irq_rt->nr_rt_entries ||
13776             hlist_empty(&irq_rt->map[guest_irq])) {
13777                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
13778                              guest_irq, irq_rt->nr_rt_entries);
13779                 goto out;
13780         }
13781
13782         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
13783                 if (e->type != KVM_IRQ_ROUTING_MSI)
13784                         continue;
13785                 /*
13786                  * VT-d PI cannot support posting multicast/broadcast
13787                  * interrupts to a vCPU, we still use interrupt remapping
13788                  * for these kind of interrupts.
13789                  *
13790                  * For lowest-priority interrupts, we only support
13791                  * those with single CPU as the destination, e.g. user
13792                  * configures the interrupts via /proc/irq or uses
13793                  * irqbalance to make the interrupts single-CPU.
13794                  *
13795                  * We will support full lowest-priority interrupt later.
13796                  */
13797
13798                 kvm_set_msi_irq(kvm, e, &irq);
13799                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
13800                         /*
13801                          * Make sure the IRTE is in remapped mode if
13802                          * we don't handle it in posted mode.
13803                          */
13804                         ret = irq_set_vcpu_affinity(host_irq, NULL);
13805                         if (ret < 0) {
13806                                 printk(KERN_INFO
13807                                    "failed to back to remapped mode, irq: %u\n",
13808                                    host_irq);
13809                                 goto out;
13810                         }
13811
13812                         continue;
13813                 }
13814
13815                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
13816                 vcpu_info.vector = irq.vector;
13817
13818                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
13819                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
13820
13821                 if (set)
13822                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
13823                 else
13824                         ret = irq_set_vcpu_affinity(host_irq, NULL);
13825
13826                 if (ret < 0) {
13827                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
13828                                         __func__);
13829                         goto out;
13830                 }
13831         }
13832
13833         ret = 0;
13834 out:
13835         srcu_read_unlock(&kvm->irq_srcu, idx);
13836         return ret;
13837 }
13838
13839 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
13840 {
13841         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
13842                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
13843                         FEATURE_CONTROL_LMCE;
13844         else
13845                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
13846                         ~FEATURE_CONTROL_LMCE;
13847 }
13848
13849 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
13850 {
13851         /* we need a nested vmexit to enter SMM, postpone if run is pending */
13852         if (to_vmx(vcpu)->nested.nested_run_pending)
13853                 return 0;
13854         return 1;
13855 }
13856
13857 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
13858 {
13859         struct vcpu_vmx *vmx = to_vmx(vcpu);
13860
13861         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
13862         if (vmx->nested.smm.guest_mode)
13863                 nested_vmx_vmexit(vcpu, -1, 0, 0);
13864
13865         vmx->nested.smm.vmxon = vmx->nested.vmxon;
13866         vmx->nested.vmxon = false;
13867         vmx_clear_hlt(vcpu);
13868         return 0;
13869 }
13870
13871 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
13872 {
13873         struct vcpu_vmx *vmx = to_vmx(vcpu);
13874         int ret;
13875
13876         if (vmx->nested.smm.vmxon) {
13877                 vmx->nested.vmxon = true;
13878                 vmx->nested.smm.vmxon = false;
13879         }
13880
13881         if (vmx->nested.smm.guest_mode) {
13882                 vcpu->arch.hflags &= ~HF_SMM_MASK;
13883                 ret = enter_vmx_non_root_mode(vcpu, NULL);
13884                 vcpu->arch.hflags |= HF_SMM_MASK;
13885                 if (ret)
13886                         return ret;
13887
13888                 vmx->nested.smm.guest_mode = false;
13889         }
13890         return 0;
13891 }
13892
13893 static int enable_smi_window(struct kvm_vcpu *vcpu)
13894 {
13895         return 0;
13896 }
13897
13898 static int vmx_get_nested_state(struct kvm_vcpu *vcpu,
13899                                 struct kvm_nested_state __user *user_kvm_nested_state,
13900                                 u32 user_data_size)
13901 {
13902         struct vcpu_vmx *vmx;
13903         struct vmcs12 *vmcs12;
13904         struct kvm_nested_state kvm_state = {
13905                 .flags = 0,
13906                 .format = 0,
13907                 .size = sizeof(kvm_state),
13908                 .vmx.vmxon_pa = -1ull,
13909                 .vmx.vmcs_pa = -1ull,
13910         };
13911
13912         if (!vcpu)
13913                 return kvm_state.size + 2 * VMCS12_SIZE;
13914
13915         vmx = to_vmx(vcpu);
13916         vmcs12 = get_vmcs12(vcpu);
13917         if (nested_vmx_allowed(vcpu) &&
13918             (vmx->nested.vmxon || vmx->nested.smm.vmxon)) {
13919                 kvm_state.vmx.vmxon_pa = vmx->nested.vmxon_ptr;
13920                 kvm_state.vmx.vmcs_pa = vmx->nested.current_vmptr;
13921
13922                 if (vmx->nested.current_vmptr != -1ull) {
13923                         kvm_state.size += VMCS12_SIZE;
13924
13925                         if (is_guest_mode(vcpu) &&
13926                             nested_cpu_has_shadow_vmcs(vmcs12) &&
13927                             vmcs12->vmcs_link_pointer != -1ull)
13928                                 kvm_state.size += VMCS12_SIZE;
13929                 }
13930
13931                 if (vmx->nested.smm.vmxon)
13932                         kvm_state.vmx.smm.flags |= KVM_STATE_NESTED_SMM_VMXON;
13933
13934                 if (vmx->nested.smm.guest_mode)
13935                         kvm_state.vmx.smm.flags |= KVM_STATE_NESTED_SMM_GUEST_MODE;
13936
13937                 if (is_guest_mode(vcpu)) {
13938                         kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE;
13939
13940                         if (vmx->nested.nested_run_pending)
13941                                 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING;
13942                 }
13943         }
13944
13945         if (user_data_size < kvm_state.size)
13946                 goto out;
13947
13948         if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state)))
13949                 return -EFAULT;
13950
13951         if (vmx->nested.current_vmptr == -1ull)
13952                 goto out;
13953
13954         /*
13955          * When running L2, the authoritative vmcs12 state is in the
13956          * vmcs02. When running L1, the authoritative vmcs12 state is
13957          * in the shadow vmcs linked to vmcs01, unless
13958          * sync_shadow_vmcs is set, in which case, the authoritative
13959          * vmcs12 state is in the vmcs12 already.
13960          */
13961         if (is_guest_mode(vcpu))
13962                 sync_vmcs12(vcpu, vmcs12);
13963         else if (enable_shadow_vmcs && !vmx->nested.sync_shadow_vmcs)
13964                 copy_shadow_to_vmcs12(vmx);
13965
13966         if (copy_to_user(user_kvm_nested_state->data, vmcs12, sizeof(*vmcs12)))
13967                 return -EFAULT;
13968
13969         if (nested_cpu_has_shadow_vmcs(vmcs12) &&
13970             vmcs12->vmcs_link_pointer != -1ull) {
13971                 if (copy_to_user(user_kvm_nested_state->data + VMCS12_SIZE,
13972                                  get_shadow_vmcs12(vcpu), sizeof(*vmcs12)))
13973                         return -EFAULT;
13974         }
13975
13976 out:
13977         return kvm_state.size;
13978 }
13979
13980 static int vmx_set_nested_state(struct kvm_vcpu *vcpu,
13981                                 struct kvm_nested_state __user *user_kvm_nested_state,
13982                                 struct kvm_nested_state *kvm_state)
13983 {
13984         struct vcpu_vmx *vmx = to_vmx(vcpu);
13985         struct vmcs12 *vmcs12;
13986         u32 exit_qual;
13987         int ret;
13988
13989         if (kvm_state->format != 0)
13990                 return -EINVAL;
13991
13992         if (!nested_vmx_allowed(vcpu))
13993                 return kvm_state->vmx.vmxon_pa == -1ull ? 0 : -EINVAL;
13994
13995         if (kvm_state->vmx.vmxon_pa == -1ull) {
13996                 if (kvm_state->vmx.smm.flags)
13997                         return -EINVAL;
13998
13999                 if (kvm_state->vmx.vmcs_pa != -1ull)
14000                         return -EINVAL;
14001
14002                 vmx_leave_nested(vcpu);
14003                 return 0;
14004         }
14005
14006         if (!page_address_valid(vcpu, kvm_state->vmx.vmxon_pa))
14007                 return -EINVAL;
14008
14009         if (kvm_state->size < sizeof(kvm_state) + sizeof(*vmcs12))
14010                 return -EINVAL;
14011
14012         if (kvm_state->vmx.vmcs_pa == kvm_state->vmx.vmxon_pa ||
14013             !page_address_valid(vcpu, kvm_state->vmx.vmcs_pa))
14014                 return -EINVAL;
14015
14016         if ((kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
14017             (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
14018                 return -EINVAL;
14019
14020         if (kvm_state->vmx.smm.flags &
14021             ~(KVM_STATE_NESTED_SMM_GUEST_MODE | KVM_STATE_NESTED_SMM_VMXON))
14022                 return -EINVAL;
14023
14024         /*
14025          * SMM temporarily disables VMX, so we cannot be in guest mode,
14026          * nor can VMLAUNCH/VMRESUME be pending.  Outside SMM, SMM flags
14027          * must be zero.
14028          */
14029         if (is_smm(vcpu) ? kvm_state->flags : kvm_state->vmx.smm.flags)
14030                 return -EINVAL;
14031
14032         if ((kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
14033             !(kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON))
14034                 return -EINVAL;
14035
14036         vmx_leave_nested(vcpu);
14037         if (kvm_state->vmx.vmxon_pa == -1ull)
14038                 return 0;
14039
14040         vmx->nested.vmxon_ptr = kvm_state->vmx.vmxon_pa;
14041         ret = enter_vmx_operation(vcpu);
14042         if (ret)
14043                 return ret;
14044
14045         set_current_vmptr(vmx, kvm_state->vmx.vmcs_pa);
14046
14047         if (kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON) {
14048                 vmx->nested.smm.vmxon = true;
14049                 vmx->nested.vmxon = false;
14050
14051                 if (kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE)
14052                         vmx->nested.smm.guest_mode = true;
14053         }
14054
14055         vmcs12 = get_vmcs12(vcpu);
14056         if (copy_from_user(vmcs12, user_kvm_nested_state->data, sizeof(*vmcs12)))
14057                 return -EFAULT;
14058
14059         if (vmcs12->hdr.revision_id != VMCS12_REVISION)
14060                 return -EINVAL;
14061
14062         if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
14063                 return 0;
14064
14065         vmx->nested.nested_run_pending =
14066                 !!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);
14067
14068         if (nested_cpu_has_shadow_vmcs(vmcs12) &&
14069             vmcs12->vmcs_link_pointer != -1ull) {
14070                 struct vmcs12 *shadow_vmcs12 = get_shadow_vmcs12(vcpu);
14071                 if (kvm_state->size < sizeof(kvm_state) + 2 * sizeof(*vmcs12))
14072                         return -EINVAL;
14073
14074                 if (copy_from_user(shadow_vmcs12,
14075                                    user_kvm_nested_state->data + VMCS12_SIZE,
14076                                    sizeof(*vmcs12)))
14077                         return -EFAULT;
14078
14079                 if (shadow_vmcs12->hdr.revision_id != VMCS12_REVISION ||
14080                     !shadow_vmcs12->hdr.shadow_vmcs)
14081                         return -EINVAL;
14082         }
14083
14084         if (check_vmentry_prereqs(vcpu, vmcs12) ||
14085             check_vmentry_postreqs(vcpu, vmcs12, &exit_qual))
14086                 return -EINVAL;
14087
14088         vmx->nested.dirty_vmcs12 = true;
14089         ret = enter_vmx_non_root_mode(vcpu, NULL);
14090         if (ret)
14091                 return -EINVAL;
14092
14093         return 0;
14094 }
14095
14096 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
14097         .cpu_has_kvm_support = cpu_has_kvm_support,
14098         .disabled_by_bios = vmx_disabled_by_bios,
14099         .hardware_setup = hardware_setup,
14100         .hardware_unsetup = hardware_unsetup,
14101         .check_processor_compatibility = vmx_check_processor_compat,
14102         .hardware_enable = hardware_enable,
14103         .hardware_disable = hardware_disable,
14104         .cpu_has_accelerated_tpr = report_flexpriority,
14105         .has_emulated_msr = vmx_has_emulated_msr,
14106
14107         .vm_init = vmx_vm_init,
14108         .vm_alloc = vmx_vm_alloc,
14109         .vm_free = vmx_vm_free,
14110
14111         .vcpu_create = vmx_create_vcpu,
14112         .vcpu_free = vmx_free_vcpu,
14113         .vcpu_reset = vmx_vcpu_reset,
14114
14115         .prepare_guest_switch = vmx_prepare_switch_to_guest,
14116         .vcpu_load = vmx_vcpu_load,
14117         .vcpu_put = vmx_vcpu_put,
14118
14119         .update_bp_intercept = update_exception_bitmap,
14120         .get_msr_feature = vmx_get_msr_feature,
14121         .get_msr = vmx_get_msr,
14122         .set_msr = vmx_set_msr,
14123         .get_segment_base = vmx_get_segment_base,
14124         .get_segment = vmx_get_segment,
14125         .set_segment = vmx_set_segment,
14126         .get_cpl = vmx_get_cpl,
14127         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
14128         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
14129         .decache_cr3 = vmx_decache_cr3,
14130         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
14131         .set_cr0 = vmx_set_cr0,
14132         .set_cr3 = vmx_set_cr3,
14133         .set_cr4 = vmx_set_cr4,
14134         .set_efer = vmx_set_efer,
14135         .get_idt = vmx_get_idt,
14136         .set_idt = vmx_set_idt,
14137         .get_gdt = vmx_get_gdt,
14138         .set_gdt = vmx_set_gdt,
14139         .get_dr6 = vmx_get_dr6,
14140         .set_dr6 = vmx_set_dr6,
14141         .set_dr7 = vmx_set_dr7,
14142         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
14143         .cache_reg = vmx_cache_reg,
14144         .get_rflags = vmx_get_rflags,
14145         .set_rflags = vmx_set_rflags,
14146
14147         .tlb_flush = vmx_flush_tlb,
14148         .tlb_flush_gva = vmx_flush_tlb_gva,
14149
14150         .run = vmx_vcpu_run,
14151         .handle_exit = vmx_handle_exit,
14152         .skip_emulated_instruction = skip_emulated_instruction,
14153         .set_interrupt_shadow = vmx_set_interrupt_shadow,
14154         .get_interrupt_shadow = vmx_get_interrupt_shadow,
14155         .patch_hypercall = vmx_patch_hypercall,
14156         .set_irq = vmx_inject_irq,
14157         .set_nmi = vmx_inject_nmi,
14158         .queue_exception = vmx_queue_exception,
14159         .cancel_injection = vmx_cancel_injection,
14160         .interrupt_allowed = vmx_interrupt_allowed,
14161         .nmi_allowed = vmx_nmi_allowed,
14162         .get_nmi_mask = vmx_get_nmi_mask,
14163         .set_nmi_mask = vmx_set_nmi_mask,
14164         .enable_nmi_window = enable_nmi_window,
14165         .enable_irq_window = enable_irq_window,
14166         .update_cr8_intercept = update_cr8_intercept,
14167         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
14168         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
14169         .get_enable_apicv = vmx_get_enable_apicv,
14170         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
14171         .load_eoi_exitmap = vmx_load_eoi_exitmap,
14172         .apicv_post_state_restore = vmx_apicv_post_state_restore,
14173         .hwapic_irr_update = vmx_hwapic_irr_update,
14174         .hwapic_isr_update = vmx_hwapic_isr_update,
14175         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
14176         .sync_pir_to_irr = vmx_sync_pir_to_irr,
14177         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
14178
14179         .set_tss_addr = vmx_set_tss_addr,
14180         .set_identity_map_addr = vmx_set_identity_map_addr,
14181         .get_tdp_level = get_ept_level,
14182         .get_mt_mask = vmx_get_mt_mask,
14183
14184         .get_exit_info = vmx_get_exit_info,
14185
14186         .get_lpage_level = vmx_get_lpage_level,
14187
14188         .cpuid_update = vmx_cpuid_update,
14189
14190         .rdtscp_supported = vmx_rdtscp_supported,
14191         .invpcid_supported = vmx_invpcid_supported,
14192
14193         .set_supported_cpuid = vmx_set_supported_cpuid,
14194
14195         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
14196
14197         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
14198         .write_tsc_offset = vmx_write_tsc_offset,
14199
14200         .set_tdp_cr3 = vmx_set_cr3,
14201
14202         .check_intercept = vmx_check_intercept,
14203         .handle_external_intr = vmx_handle_external_intr,
14204         .mpx_supported = vmx_mpx_supported,
14205         .xsaves_supported = vmx_xsaves_supported,
14206         .umip_emulated = vmx_umip_emulated,
14207
14208         .check_nested_events = vmx_check_nested_events,
14209         .request_immediate_exit = vmx_request_immediate_exit,
14210
14211         .sched_in = vmx_sched_in,
14212
14213         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
14214         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
14215         .flush_log_dirty = vmx_flush_log_dirty,
14216         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
14217         .write_log_dirty = vmx_write_pml_buffer,
14218
14219         .pre_block = vmx_pre_block,
14220         .post_block = vmx_post_block,
14221
14222         .pmu_ops = &intel_pmu_ops,
14223
14224         .update_pi_irte = vmx_update_pi_irte,
14225
14226 #ifdef CONFIG_X86_64
14227         .set_hv_timer = vmx_set_hv_timer,
14228         .cancel_hv_timer = vmx_cancel_hv_timer,
14229 #endif
14230
14231         .setup_mce = vmx_setup_mce,
14232
14233         .get_nested_state = vmx_get_nested_state,
14234         .set_nested_state = vmx_set_nested_state,
14235         .get_vmcs12_pages = nested_get_vmcs12_pages,
14236
14237         .smi_allowed = vmx_smi_allowed,
14238         .pre_enter_smm = vmx_pre_enter_smm,
14239         .pre_leave_smm = vmx_pre_leave_smm,
14240         .enable_smi_window = enable_smi_window,
14241 };
14242
14243 static void vmx_cleanup_l1d_flush(void)
14244 {
14245         if (vmx_l1d_flush_pages) {
14246                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
14247                 vmx_l1d_flush_pages = NULL;
14248         }
14249         /* Restore state so sysfs ignores VMX */
14250         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
14251 }
14252
14253 static void vmx_exit(void)
14254 {
14255 #ifdef CONFIG_KEXEC_CORE
14256         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
14257         synchronize_rcu();
14258 #endif
14259
14260         kvm_exit();
14261
14262 #if IS_ENABLED(CONFIG_HYPERV)
14263         if (static_branch_unlikely(&enable_evmcs)) {
14264                 int cpu;
14265                 struct hv_vp_assist_page *vp_ap;
14266                 /*
14267                  * Reset everything to support using non-enlightened VMCS
14268                  * access later (e.g. when we reload the module with
14269                  * enlightened_vmcs=0)
14270                  */
14271                 for_each_online_cpu(cpu) {
14272                         vp_ap = hv_get_vp_assist_page(cpu);
14273
14274                         if (!vp_ap)
14275                                 continue;
14276
14277                         vp_ap->current_nested_vmcs = 0;
14278                         vp_ap->enlighten_vmentry = 0;
14279                 }
14280
14281                 static_branch_disable(&enable_evmcs);
14282         }
14283 #endif
14284         vmx_cleanup_l1d_flush();
14285 }
14286 module_exit(vmx_exit);
14287
14288 static int __init vmx_init(void)
14289 {
14290         int r;
14291
14292 #if IS_ENABLED(CONFIG_HYPERV)
14293         /*
14294          * Enlightened VMCS usage should be recommended and the host needs
14295          * to support eVMCS v1 or above. We can also disable eVMCS support
14296          * with module parameter.
14297          */
14298         if (enlightened_vmcs &&
14299             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
14300             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
14301             KVM_EVMCS_VERSION) {
14302                 int cpu;
14303
14304                 /* Check that we have assist pages on all online CPUs */
14305                 for_each_online_cpu(cpu) {
14306                         if (!hv_get_vp_assist_page(cpu)) {
14307                                 enlightened_vmcs = false;
14308                                 break;
14309                         }
14310                 }
14311
14312                 if (enlightened_vmcs) {
14313                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
14314                         static_branch_enable(&enable_evmcs);
14315                 }
14316         } else {
14317                 enlightened_vmcs = false;
14318         }
14319 #endif
14320
14321         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
14322                      __alignof__(struct vcpu_vmx), THIS_MODULE);
14323         if (r)
14324                 return r;
14325
14326         /*
14327          * Must be called after kvm_init() so enable_ept is properly set
14328          * up. Hand the parameter mitigation value in which was stored in
14329          * the pre module init parser. If no parameter was given, it will
14330          * contain 'auto' which will be turned into the default 'cond'
14331          * mitigation mode.
14332          */
14333         if (boot_cpu_has(X86_BUG_L1TF)) {
14334                 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
14335                 if (r) {
14336                         vmx_exit();
14337                         return r;
14338                 }
14339         }
14340
14341 #ifdef CONFIG_KEXEC_CORE
14342         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
14343                            crash_vmclear_local_loaded_vmcss);
14344 #endif
14345         vmx_check_vmcs12_offsets();
14346
14347         return 0;
14348 }
14349 module_init(vmx_init);