2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include <linux/nospec.h>
38 #include "kvm_cache_regs.h"
46 #include <asm/virtext.h>
48 #include <asm/fpu/internal.h>
49 #include <asm/perf_event.h>
50 #include <asm/debugreg.h>
51 #include <asm/kexec.h>
53 #include <asm/irq_remapping.h>
54 #include <asm/mmu_context.h>
55 #include <asm/spec-ctrl.h>
56 #include <asm/mshyperv.h>
60 #include "vmx_evmcs.h"
62 #define __ex(x) __kvm_handle_fault_on_reboot(x)
63 #define __ex_clear(x, reg) \
64 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
66 MODULE_AUTHOR("Qumranet");
67 MODULE_LICENSE("GPL");
69 static const struct x86_cpu_id vmx_cpu_id[] = {
70 X86_FEATURE_MATCH(X86_FEATURE_VMX),
73 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
75 static bool __read_mostly enable_vpid = 1;
76 module_param_named(vpid, enable_vpid, bool, 0444);
78 static bool __read_mostly enable_vnmi = 1;
79 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
81 static bool __read_mostly flexpriority_enabled = 1;
82 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
84 static bool __read_mostly enable_ept = 1;
85 module_param_named(ept, enable_ept, bool, S_IRUGO);
87 static bool __read_mostly enable_unrestricted_guest = 1;
88 module_param_named(unrestricted_guest,
89 enable_unrestricted_guest, bool, S_IRUGO);
91 static bool __read_mostly enable_ept_ad_bits = 1;
92 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
94 static bool __read_mostly emulate_invalid_guest_state = true;
95 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
97 static bool __read_mostly fasteoi = 1;
98 module_param(fasteoi, bool, S_IRUGO);
100 static bool __read_mostly enable_apicv = 1;
101 module_param(enable_apicv, bool, S_IRUGO);
103 static bool __read_mostly enable_shadow_vmcs = 1;
104 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
106 * If nested=1, nested virtualization is supported, i.e., guests may use
107 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
108 * use VMX instructions.
110 static bool __read_mostly nested = 0;
111 module_param(nested, bool, S_IRUGO);
113 static u64 __read_mostly host_xss;
115 static bool __read_mostly enable_pml = 1;
116 module_param_named(pml, enable_pml, bool, S_IRUGO);
120 #define MSR_TYPE_RW 3
122 #define MSR_BITMAP_MODE_X2APIC 1
123 #define MSR_BITMAP_MODE_X2APIC_APICV 2
125 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
127 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
128 static int __read_mostly cpu_preemption_timer_multi;
129 static bool __read_mostly enable_preemption_timer = 1;
131 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
134 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
135 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
136 #define KVM_VM_CR0_ALWAYS_ON \
137 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
138 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
139 #define KVM_CR4_GUEST_OWNED_BITS \
140 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
141 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
143 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
144 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
145 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
147 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
149 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
152 * Hyper-V requires all of these, so mark them as supported even though
153 * they are just treated the same as all-context.
155 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
156 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
157 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
158 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
159 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
162 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
163 * ple_gap: upper bound on the amount of time between two successive
164 * executions of PAUSE in a loop. Also indicate if ple enabled.
165 * According to test, this time is usually smaller than 128 cycles.
166 * ple_window: upper bound on the amount of time a guest is allowed to execute
167 * in a PAUSE loop. Tests indicate that most spinlocks are held for
168 * less than 2^12 cycles
169 * Time is measured based on a counter that runs at the same rate as the TSC,
170 * refer SDM volume 3b section 21.6.13 & 22.1.3.
172 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
174 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
175 module_param(ple_window, uint, 0444);
177 /* Default doubles per-vcpu window every exit. */
178 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
179 module_param(ple_window_grow, uint, 0444);
181 /* Default resets per-vcpu window every exit to ple_window. */
182 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
183 module_param(ple_window_shrink, uint, 0444);
185 /* Default is to compute the maximum so we can never overflow. */
186 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
187 module_param(ple_window_max, uint, 0444);
189 extern const ulong vmx_return;
191 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
192 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
193 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
195 /* Storage for pre module init parameter parsing */
196 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
198 static const struct {
201 } vmentry_l1d_param[] = {
202 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
203 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
204 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
205 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
206 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
207 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
210 #define L1D_CACHE_ORDER 4
211 static void *vmx_l1d_flush_pages;
213 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
219 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
223 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
226 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
227 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
228 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
233 /* If set to auto use the default l1tf mitigation method */
234 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
235 switch (l1tf_mitigation) {
236 case L1TF_MITIGATION_OFF:
237 l1tf = VMENTER_L1D_FLUSH_NEVER;
239 case L1TF_MITIGATION_FLUSH_NOWARN:
240 case L1TF_MITIGATION_FLUSH:
241 case L1TF_MITIGATION_FLUSH_NOSMT:
242 l1tf = VMENTER_L1D_FLUSH_COND;
244 case L1TF_MITIGATION_FULL:
245 case L1TF_MITIGATION_FULL_FORCE:
246 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
249 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
250 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
253 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
254 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
255 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
258 vmx_l1d_flush_pages = page_address(page);
261 * Initialize each page with a different pattern in
262 * order to protect against KSM in the nested
263 * virtualization case.
265 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
266 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
271 l1tf_vmx_mitigation = l1tf;
273 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
274 static_branch_enable(&vmx_l1d_should_flush);
276 static_branch_disable(&vmx_l1d_should_flush);
278 if (l1tf == VMENTER_L1D_FLUSH_COND)
279 static_branch_enable(&vmx_l1d_flush_cond);
281 static_branch_disable(&vmx_l1d_flush_cond);
285 static int vmentry_l1d_flush_parse(const char *s)
290 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
291 if (vmentry_l1d_param[i].for_parse &&
292 sysfs_streq(s, vmentry_l1d_param[i].option))
299 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
303 l1tf = vmentry_l1d_flush_parse(s);
307 if (!boot_cpu_has(X86_BUG_L1TF))
311 * Has vmx_init() run already? If not then this is the pre init
312 * parameter parsing. In that case just store the value and let
313 * vmx_init() do the proper setup after enable_ept has been
316 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
317 vmentry_l1d_flush_param = l1tf;
321 mutex_lock(&vmx_l1d_flush_mutex);
322 ret = vmx_setup_l1d_flush(l1tf);
323 mutex_unlock(&vmx_l1d_flush_mutex);
327 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
329 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
330 return sprintf(s, "???\n");
332 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
335 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
336 .set = vmentry_l1d_flush_set,
337 .get = vmentry_l1d_flush_get,
339 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
341 enum ept_pointers_status {
342 EPT_POINTERS_CHECK = 0,
343 EPT_POINTERS_MATCH = 1,
344 EPT_POINTERS_MISMATCH = 2
350 unsigned int tss_addr;
351 bool ept_identity_pagetable_done;
352 gpa_t ept_identity_map_addr;
354 enum ept_pointers_status ept_pointers_match;
355 spinlock_t ept_pointer_lock;
358 #define NR_AUTOLOAD_MSRS 8
372 * vmcs_host_state tracks registers that are loaded from the VMCS on VMEXIT
373 * and whose values change infrequently, but are not constant. I.e. this is
374 * used as a write-through cache of the corresponding VMCS fields.
376 struct vmcs_host_state {
377 unsigned long cr3; /* May not match real cr3 */
378 unsigned long cr4; /* May not match real cr4 */
379 unsigned long gs_base;
380 unsigned long fs_base;
382 u16 fs_sel, gs_sel, ldt_sel;
389 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
390 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
391 * loaded on this CPU (so we can clear them if the CPU goes down).
395 struct vmcs *shadow_vmcs;
398 bool nmi_known_unmasked;
400 /* Support for vnmi-less CPUs */
401 int soft_vnmi_blocked;
403 s64 vnmi_blocked_time;
404 unsigned long *msr_bitmap;
405 struct list_head loaded_vmcss_on_cpu_link;
406 struct vmcs_host_state host_state;
409 struct shared_msr_entry {
416 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
417 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
418 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
419 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
420 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
421 * More than one of these structures may exist, if L1 runs multiple L2 guests.
422 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
423 * underlying hardware which will be used to run L2.
424 * This structure is packed to ensure that its layout is identical across
425 * machines (necessary for live migration).
427 * IMPORTANT: Changing the layout of existing fields in this structure
428 * will break save/restore compatibility with older kvm releases. When
429 * adding new fields, either use space in the reserved padding* arrays
430 * or add the new fields to the end of the structure.
432 typedef u64 natural_width;
433 struct __packed vmcs12 {
434 /* According to the Intel spec, a VMCS region must start with the
435 * following two fields. Then follow implementation-specific data.
440 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
441 u32 padding[7]; /* room for future expansion */
446 u64 vm_exit_msr_store_addr;
447 u64 vm_exit_msr_load_addr;
448 u64 vm_entry_msr_load_addr;
450 u64 virtual_apic_page_addr;
451 u64 apic_access_addr;
452 u64 posted_intr_desc_addr;
454 u64 eoi_exit_bitmap0;
455 u64 eoi_exit_bitmap1;
456 u64 eoi_exit_bitmap2;
457 u64 eoi_exit_bitmap3;
459 u64 guest_physical_address;
460 u64 vmcs_link_pointer;
461 u64 guest_ia32_debugctl;
464 u64 guest_ia32_perf_global_ctrl;
472 u64 host_ia32_perf_global_ctrl;
475 u64 vm_function_control;
476 u64 eptp_list_address;
478 u64 padding64[3]; /* room for future expansion */
480 * To allow migration of L1 (complete with its L2 guests) between
481 * machines of different natural widths (32 or 64 bit), we cannot have
482 * unsigned long fields with no explict size. We use u64 (aliased
483 * natural_width) instead. Luckily, x86 is little-endian.
485 natural_width cr0_guest_host_mask;
486 natural_width cr4_guest_host_mask;
487 natural_width cr0_read_shadow;
488 natural_width cr4_read_shadow;
489 natural_width cr3_target_value0;
490 natural_width cr3_target_value1;
491 natural_width cr3_target_value2;
492 natural_width cr3_target_value3;
493 natural_width exit_qualification;
494 natural_width guest_linear_address;
495 natural_width guest_cr0;
496 natural_width guest_cr3;
497 natural_width guest_cr4;
498 natural_width guest_es_base;
499 natural_width guest_cs_base;
500 natural_width guest_ss_base;
501 natural_width guest_ds_base;
502 natural_width guest_fs_base;
503 natural_width guest_gs_base;
504 natural_width guest_ldtr_base;
505 natural_width guest_tr_base;
506 natural_width guest_gdtr_base;
507 natural_width guest_idtr_base;
508 natural_width guest_dr7;
509 natural_width guest_rsp;
510 natural_width guest_rip;
511 natural_width guest_rflags;
512 natural_width guest_pending_dbg_exceptions;
513 natural_width guest_sysenter_esp;
514 natural_width guest_sysenter_eip;
515 natural_width host_cr0;
516 natural_width host_cr3;
517 natural_width host_cr4;
518 natural_width host_fs_base;
519 natural_width host_gs_base;
520 natural_width host_tr_base;
521 natural_width host_gdtr_base;
522 natural_width host_idtr_base;
523 natural_width host_ia32_sysenter_esp;
524 natural_width host_ia32_sysenter_eip;
525 natural_width host_rsp;
526 natural_width host_rip;
527 natural_width paddingl[8]; /* room for future expansion */
528 u32 pin_based_vm_exec_control;
529 u32 cpu_based_vm_exec_control;
530 u32 exception_bitmap;
531 u32 page_fault_error_code_mask;
532 u32 page_fault_error_code_match;
533 u32 cr3_target_count;
534 u32 vm_exit_controls;
535 u32 vm_exit_msr_store_count;
536 u32 vm_exit_msr_load_count;
537 u32 vm_entry_controls;
538 u32 vm_entry_msr_load_count;
539 u32 vm_entry_intr_info_field;
540 u32 vm_entry_exception_error_code;
541 u32 vm_entry_instruction_len;
543 u32 secondary_vm_exec_control;
544 u32 vm_instruction_error;
546 u32 vm_exit_intr_info;
547 u32 vm_exit_intr_error_code;
548 u32 idt_vectoring_info_field;
549 u32 idt_vectoring_error_code;
550 u32 vm_exit_instruction_len;
551 u32 vmx_instruction_info;
558 u32 guest_ldtr_limit;
560 u32 guest_gdtr_limit;
561 u32 guest_idtr_limit;
562 u32 guest_es_ar_bytes;
563 u32 guest_cs_ar_bytes;
564 u32 guest_ss_ar_bytes;
565 u32 guest_ds_ar_bytes;
566 u32 guest_fs_ar_bytes;
567 u32 guest_gs_ar_bytes;
568 u32 guest_ldtr_ar_bytes;
569 u32 guest_tr_ar_bytes;
570 u32 guest_interruptibility_info;
571 u32 guest_activity_state;
572 u32 guest_sysenter_cs;
573 u32 host_ia32_sysenter_cs;
574 u32 vmx_preemption_timer_value;
575 u32 padding32[7]; /* room for future expansion */
576 u16 virtual_processor_id;
578 u16 guest_es_selector;
579 u16 guest_cs_selector;
580 u16 guest_ss_selector;
581 u16 guest_ds_selector;
582 u16 guest_fs_selector;
583 u16 guest_gs_selector;
584 u16 guest_ldtr_selector;
585 u16 guest_tr_selector;
586 u16 guest_intr_status;
587 u16 host_es_selector;
588 u16 host_cs_selector;
589 u16 host_ss_selector;
590 u16 host_ds_selector;
591 u16 host_fs_selector;
592 u16 host_gs_selector;
593 u16 host_tr_selector;
598 * For save/restore compatibility, the vmcs12 field offsets must not change.
600 #define CHECK_OFFSET(field, loc) \
601 BUILD_BUG_ON_MSG(offsetof(struct vmcs12, field) != (loc), \
602 "Offset of " #field " in struct vmcs12 has changed.")
604 static inline void vmx_check_vmcs12_offsets(void) {
605 CHECK_OFFSET(hdr, 0);
606 CHECK_OFFSET(abort, 4);
607 CHECK_OFFSET(launch_state, 8);
608 CHECK_OFFSET(io_bitmap_a, 40);
609 CHECK_OFFSET(io_bitmap_b, 48);
610 CHECK_OFFSET(msr_bitmap, 56);
611 CHECK_OFFSET(vm_exit_msr_store_addr, 64);
612 CHECK_OFFSET(vm_exit_msr_load_addr, 72);
613 CHECK_OFFSET(vm_entry_msr_load_addr, 80);
614 CHECK_OFFSET(tsc_offset, 88);
615 CHECK_OFFSET(virtual_apic_page_addr, 96);
616 CHECK_OFFSET(apic_access_addr, 104);
617 CHECK_OFFSET(posted_intr_desc_addr, 112);
618 CHECK_OFFSET(ept_pointer, 120);
619 CHECK_OFFSET(eoi_exit_bitmap0, 128);
620 CHECK_OFFSET(eoi_exit_bitmap1, 136);
621 CHECK_OFFSET(eoi_exit_bitmap2, 144);
622 CHECK_OFFSET(eoi_exit_bitmap3, 152);
623 CHECK_OFFSET(xss_exit_bitmap, 160);
624 CHECK_OFFSET(guest_physical_address, 168);
625 CHECK_OFFSET(vmcs_link_pointer, 176);
626 CHECK_OFFSET(guest_ia32_debugctl, 184);
627 CHECK_OFFSET(guest_ia32_pat, 192);
628 CHECK_OFFSET(guest_ia32_efer, 200);
629 CHECK_OFFSET(guest_ia32_perf_global_ctrl, 208);
630 CHECK_OFFSET(guest_pdptr0, 216);
631 CHECK_OFFSET(guest_pdptr1, 224);
632 CHECK_OFFSET(guest_pdptr2, 232);
633 CHECK_OFFSET(guest_pdptr3, 240);
634 CHECK_OFFSET(guest_bndcfgs, 248);
635 CHECK_OFFSET(host_ia32_pat, 256);
636 CHECK_OFFSET(host_ia32_efer, 264);
637 CHECK_OFFSET(host_ia32_perf_global_ctrl, 272);
638 CHECK_OFFSET(vmread_bitmap, 280);
639 CHECK_OFFSET(vmwrite_bitmap, 288);
640 CHECK_OFFSET(vm_function_control, 296);
641 CHECK_OFFSET(eptp_list_address, 304);
642 CHECK_OFFSET(pml_address, 312);
643 CHECK_OFFSET(cr0_guest_host_mask, 344);
644 CHECK_OFFSET(cr4_guest_host_mask, 352);
645 CHECK_OFFSET(cr0_read_shadow, 360);
646 CHECK_OFFSET(cr4_read_shadow, 368);
647 CHECK_OFFSET(cr3_target_value0, 376);
648 CHECK_OFFSET(cr3_target_value1, 384);
649 CHECK_OFFSET(cr3_target_value2, 392);
650 CHECK_OFFSET(cr3_target_value3, 400);
651 CHECK_OFFSET(exit_qualification, 408);
652 CHECK_OFFSET(guest_linear_address, 416);
653 CHECK_OFFSET(guest_cr0, 424);
654 CHECK_OFFSET(guest_cr3, 432);
655 CHECK_OFFSET(guest_cr4, 440);
656 CHECK_OFFSET(guest_es_base, 448);
657 CHECK_OFFSET(guest_cs_base, 456);
658 CHECK_OFFSET(guest_ss_base, 464);
659 CHECK_OFFSET(guest_ds_base, 472);
660 CHECK_OFFSET(guest_fs_base, 480);
661 CHECK_OFFSET(guest_gs_base, 488);
662 CHECK_OFFSET(guest_ldtr_base, 496);
663 CHECK_OFFSET(guest_tr_base, 504);
664 CHECK_OFFSET(guest_gdtr_base, 512);
665 CHECK_OFFSET(guest_idtr_base, 520);
666 CHECK_OFFSET(guest_dr7, 528);
667 CHECK_OFFSET(guest_rsp, 536);
668 CHECK_OFFSET(guest_rip, 544);
669 CHECK_OFFSET(guest_rflags, 552);
670 CHECK_OFFSET(guest_pending_dbg_exceptions, 560);
671 CHECK_OFFSET(guest_sysenter_esp, 568);
672 CHECK_OFFSET(guest_sysenter_eip, 576);
673 CHECK_OFFSET(host_cr0, 584);
674 CHECK_OFFSET(host_cr3, 592);
675 CHECK_OFFSET(host_cr4, 600);
676 CHECK_OFFSET(host_fs_base, 608);
677 CHECK_OFFSET(host_gs_base, 616);
678 CHECK_OFFSET(host_tr_base, 624);
679 CHECK_OFFSET(host_gdtr_base, 632);
680 CHECK_OFFSET(host_idtr_base, 640);
681 CHECK_OFFSET(host_ia32_sysenter_esp, 648);
682 CHECK_OFFSET(host_ia32_sysenter_eip, 656);
683 CHECK_OFFSET(host_rsp, 664);
684 CHECK_OFFSET(host_rip, 672);
685 CHECK_OFFSET(pin_based_vm_exec_control, 744);
686 CHECK_OFFSET(cpu_based_vm_exec_control, 748);
687 CHECK_OFFSET(exception_bitmap, 752);
688 CHECK_OFFSET(page_fault_error_code_mask, 756);
689 CHECK_OFFSET(page_fault_error_code_match, 760);
690 CHECK_OFFSET(cr3_target_count, 764);
691 CHECK_OFFSET(vm_exit_controls, 768);
692 CHECK_OFFSET(vm_exit_msr_store_count, 772);
693 CHECK_OFFSET(vm_exit_msr_load_count, 776);
694 CHECK_OFFSET(vm_entry_controls, 780);
695 CHECK_OFFSET(vm_entry_msr_load_count, 784);
696 CHECK_OFFSET(vm_entry_intr_info_field, 788);
697 CHECK_OFFSET(vm_entry_exception_error_code, 792);
698 CHECK_OFFSET(vm_entry_instruction_len, 796);
699 CHECK_OFFSET(tpr_threshold, 800);
700 CHECK_OFFSET(secondary_vm_exec_control, 804);
701 CHECK_OFFSET(vm_instruction_error, 808);
702 CHECK_OFFSET(vm_exit_reason, 812);
703 CHECK_OFFSET(vm_exit_intr_info, 816);
704 CHECK_OFFSET(vm_exit_intr_error_code, 820);
705 CHECK_OFFSET(idt_vectoring_info_field, 824);
706 CHECK_OFFSET(idt_vectoring_error_code, 828);
707 CHECK_OFFSET(vm_exit_instruction_len, 832);
708 CHECK_OFFSET(vmx_instruction_info, 836);
709 CHECK_OFFSET(guest_es_limit, 840);
710 CHECK_OFFSET(guest_cs_limit, 844);
711 CHECK_OFFSET(guest_ss_limit, 848);
712 CHECK_OFFSET(guest_ds_limit, 852);
713 CHECK_OFFSET(guest_fs_limit, 856);
714 CHECK_OFFSET(guest_gs_limit, 860);
715 CHECK_OFFSET(guest_ldtr_limit, 864);
716 CHECK_OFFSET(guest_tr_limit, 868);
717 CHECK_OFFSET(guest_gdtr_limit, 872);
718 CHECK_OFFSET(guest_idtr_limit, 876);
719 CHECK_OFFSET(guest_es_ar_bytes, 880);
720 CHECK_OFFSET(guest_cs_ar_bytes, 884);
721 CHECK_OFFSET(guest_ss_ar_bytes, 888);
722 CHECK_OFFSET(guest_ds_ar_bytes, 892);
723 CHECK_OFFSET(guest_fs_ar_bytes, 896);
724 CHECK_OFFSET(guest_gs_ar_bytes, 900);
725 CHECK_OFFSET(guest_ldtr_ar_bytes, 904);
726 CHECK_OFFSET(guest_tr_ar_bytes, 908);
727 CHECK_OFFSET(guest_interruptibility_info, 912);
728 CHECK_OFFSET(guest_activity_state, 916);
729 CHECK_OFFSET(guest_sysenter_cs, 920);
730 CHECK_OFFSET(host_ia32_sysenter_cs, 924);
731 CHECK_OFFSET(vmx_preemption_timer_value, 928);
732 CHECK_OFFSET(virtual_processor_id, 960);
733 CHECK_OFFSET(posted_intr_nv, 962);
734 CHECK_OFFSET(guest_es_selector, 964);
735 CHECK_OFFSET(guest_cs_selector, 966);
736 CHECK_OFFSET(guest_ss_selector, 968);
737 CHECK_OFFSET(guest_ds_selector, 970);
738 CHECK_OFFSET(guest_fs_selector, 972);
739 CHECK_OFFSET(guest_gs_selector, 974);
740 CHECK_OFFSET(guest_ldtr_selector, 976);
741 CHECK_OFFSET(guest_tr_selector, 978);
742 CHECK_OFFSET(guest_intr_status, 980);
743 CHECK_OFFSET(host_es_selector, 982);
744 CHECK_OFFSET(host_cs_selector, 984);
745 CHECK_OFFSET(host_ss_selector, 986);
746 CHECK_OFFSET(host_ds_selector, 988);
747 CHECK_OFFSET(host_fs_selector, 990);
748 CHECK_OFFSET(host_gs_selector, 992);
749 CHECK_OFFSET(host_tr_selector, 994);
750 CHECK_OFFSET(guest_pml_index, 996);
754 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
755 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
756 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
758 * IMPORTANT: Changing this value will break save/restore compatibility with
759 * older kvm releases.
761 #define VMCS12_REVISION 0x11e57ed0
764 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
765 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
766 * current implementation, 4K are reserved to avoid future complications.
768 #define VMCS12_SIZE 0x1000
771 * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
772 * supported VMCS12 field encoding.
774 #define VMCS12_MAX_FIELD_INDEX 0x17
776 struct nested_vmx_msrs {
778 * We only store the "true" versions of the VMX capability MSRs. We
779 * generate the "non-true" versions by setting the must-be-1 bits
780 * according to the SDM.
782 u32 procbased_ctls_low;
783 u32 procbased_ctls_high;
784 u32 secondary_ctls_low;
785 u32 secondary_ctls_high;
786 u32 pinbased_ctls_low;
787 u32 pinbased_ctls_high;
806 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
807 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
810 /* Has the level1 guest done vmxon? */
815 /* The guest-physical address of the current VMCS L1 keeps for L2 */
818 * Cache of the guest's VMCS, existing outside of guest memory.
819 * Loaded from guest memory during VMPTRLD. Flushed to guest
820 * memory during VMCLEAR and VMPTRLD.
822 struct vmcs12 *cached_vmcs12;
824 * Cache of the guest's shadow VMCS, existing outside of guest
825 * memory. Loaded from guest memory during VM entry. Flushed
826 * to guest memory during VM exit.
828 struct vmcs12 *cached_shadow_vmcs12;
830 * Indicates if the shadow vmcs must be updated with the
831 * data hold by vmcs12
833 bool sync_shadow_vmcs;
837 * vmcs02 has been initialized, i.e. state that is constant for
838 * vmcs02 has been written to the backing VMCS. Initialization
839 * is delayed until L1 actually attempts to run a nested VM.
841 bool vmcs02_initialized;
843 bool change_vmcs01_virtual_apic_mode;
845 /* L2 must run next, and mustn't decide to exit to L1. */
846 bool nested_run_pending;
848 struct loaded_vmcs vmcs02;
851 * Guest pages referred to in the vmcs02 with host-physical
852 * pointers, so we must keep them pinned while L2 runs.
854 struct page *apic_access_page;
855 struct page *virtual_apic_page;
856 struct page *pi_desc_page;
857 struct pi_desc *pi_desc;
861 struct hrtimer preemption_timer;
862 bool preemption_timer_expired;
864 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
866 u64 vmcs01_guest_bndcfgs;
871 struct nested_vmx_msrs msrs;
873 /* SMM related state */
875 /* in VMX operation on SMM entry? */
877 /* in guest mode on SMM entry? */
882 #define POSTED_INTR_ON 0
883 #define POSTED_INTR_SN 1
885 /* Posted-Interrupt Descriptor */
887 u32 pir[8]; /* Posted interrupt requested */
890 /* bit 256 - Outstanding Notification */
892 /* bit 257 - Suppress Notification */
894 /* bit 271:258 - Reserved */
896 /* bit 279:272 - Notification Vector */
898 /* bit 287:280 - Reserved */
900 /* bit 319:288 - Notification Destination */
908 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
910 return test_and_set_bit(POSTED_INTR_ON,
911 (unsigned long *)&pi_desc->control);
914 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
916 return test_and_clear_bit(POSTED_INTR_ON,
917 (unsigned long *)&pi_desc->control);
920 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
922 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
925 static inline void pi_clear_sn(struct pi_desc *pi_desc)
927 return clear_bit(POSTED_INTR_SN,
928 (unsigned long *)&pi_desc->control);
931 static inline void pi_set_sn(struct pi_desc *pi_desc)
933 return set_bit(POSTED_INTR_SN,
934 (unsigned long *)&pi_desc->control);
937 static inline void pi_clear_on(struct pi_desc *pi_desc)
939 clear_bit(POSTED_INTR_ON,
940 (unsigned long *)&pi_desc->control);
943 static inline int pi_test_on(struct pi_desc *pi_desc)
945 return test_bit(POSTED_INTR_ON,
946 (unsigned long *)&pi_desc->control);
949 static inline int pi_test_sn(struct pi_desc *pi_desc)
951 return test_bit(POSTED_INTR_SN,
952 (unsigned long *)&pi_desc->control);
957 struct vmx_msr_entry val[NR_AUTOLOAD_MSRS];
961 struct kvm_vcpu vcpu;
962 unsigned long host_rsp;
966 u32 idt_vectoring_info;
968 struct shared_msr_entry *guest_msrs;
971 unsigned long host_idt_base;
973 u64 msr_host_kernel_gs_base;
974 u64 msr_guest_kernel_gs_base;
977 u64 arch_capabilities;
980 u32 vm_entry_controls_shadow;
981 u32 vm_exit_controls_shadow;
982 u32 secondary_exec_control;
985 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
986 * non-nested (L1) guest, it always points to vmcs01. For a nested
987 * guest (L2), it points to a different VMCS. loaded_cpu_state points
988 * to the VMCS whose state is loaded into the CPU registers that only
989 * need to be switched when transitioning to/from the kernel; a NULL
990 * value indicates that host state is loaded.
992 struct loaded_vmcs vmcs01;
993 struct loaded_vmcs *loaded_vmcs;
994 struct loaded_vmcs *loaded_cpu_state;
995 bool __launched; /* temporary, used in vmx_vcpu_run */
996 struct msr_autoload {
997 struct vmx_msrs guest;
998 struct vmx_msrs host;
1004 struct kvm_segment segs[8];
1007 u32 bitmask; /* 4 bits per segment (1 bit per field) */
1008 struct kvm_save_segment {
1016 bool emulation_required;
1020 /* Posted interrupt descriptor */
1021 struct pi_desc pi_desc;
1023 /* Support for a guest hypervisor (nested VMX) */
1024 struct nested_vmx nested;
1026 /* Dynamic PLE window. */
1028 bool ple_window_dirty;
1030 bool req_immediate_exit;
1032 /* Support for PML */
1033 #define PML_ENTITY_NUM 512
1034 struct page *pml_pg;
1036 /* apic deadline value in host tsc */
1037 u64 hv_deadline_tsc;
1039 u64 current_tsc_ratio;
1043 unsigned long host_debugctlmsr;
1046 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
1047 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
1048 * in msr_ia32_feature_control_valid_bits.
1050 u64 msr_ia32_feature_control;
1051 u64 msr_ia32_feature_control_valid_bits;
1055 enum segment_cache_field {
1058 SEG_FIELD_LIMIT = 2,
1064 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
1066 return container_of(kvm, struct kvm_vmx, kvm);
1069 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
1071 return container_of(vcpu, struct vcpu_vmx, vcpu);
1074 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
1076 return &(to_vmx(vcpu)->pi_desc);
1079 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
1080 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
1081 #define FIELD(number, name) [ROL16(number, 6)] = VMCS12_OFFSET(name)
1082 #define FIELD64(number, name) \
1083 FIELD(number, name), \
1084 [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
1087 static u16 shadow_read_only_fields[] = {
1088 #define SHADOW_FIELD_RO(x) x,
1089 #include "vmx_shadow_fields.h"
1091 static int max_shadow_read_only_fields =
1092 ARRAY_SIZE(shadow_read_only_fields);
1094 static u16 shadow_read_write_fields[] = {
1095 #define SHADOW_FIELD_RW(x) x,
1096 #include "vmx_shadow_fields.h"
1098 static int max_shadow_read_write_fields =
1099 ARRAY_SIZE(shadow_read_write_fields);
1101 static const unsigned short vmcs_field_to_offset_table[] = {
1102 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
1103 FIELD(POSTED_INTR_NV, posted_intr_nv),
1104 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
1105 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
1106 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
1107 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
1108 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
1109 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
1110 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
1111 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
1112 FIELD(GUEST_INTR_STATUS, guest_intr_status),
1113 FIELD(GUEST_PML_INDEX, guest_pml_index),
1114 FIELD(HOST_ES_SELECTOR, host_es_selector),
1115 FIELD(HOST_CS_SELECTOR, host_cs_selector),
1116 FIELD(HOST_SS_SELECTOR, host_ss_selector),
1117 FIELD(HOST_DS_SELECTOR, host_ds_selector),
1118 FIELD(HOST_FS_SELECTOR, host_fs_selector),
1119 FIELD(HOST_GS_SELECTOR, host_gs_selector),
1120 FIELD(HOST_TR_SELECTOR, host_tr_selector),
1121 FIELD64(IO_BITMAP_A, io_bitmap_a),
1122 FIELD64(IO_BITMAP_B, io_bitmap_b),
1123 FIELD64(MSR_BITMAP, msr_bitmap),
1124 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
1125 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
1126 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
1127 FIELD64(PML_ADDRESS, pml_address),
1128 FIELD64(TSC_OFFSET, tsc_offset),
1129 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
1130 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
1131 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
1132 FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
1133 FIELD64(EPT_POINTER, ept_pointer),
1134 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
1135 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
1136 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
1137 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
1138 FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
1139 FIELD64(VMREAD_BITMAP, vmread_bitmap),
1140 FIELD64(VMWRITE_BITMAP, vmwrite_bitmap),
1141 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
1142 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
1143 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
1144 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
1145 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
1146 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
1147 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
1148 FIELD64(GUEST_PDPTR0, guest_pdptr0),
1149 FIELD64(GUEST_PDPTR1, guest_pdptr1),
1150 FIELD64(GUEST_PDPTR2, guest_pdptr2),
1151 FIELD64(GUEST_PDPTR3, guest_pdptr3),
1152 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
1153 FIELD64(HOST_IA32_PAT, host_ia32_pat),
1154 FIELD64(HOST_IA32_EFER, host_ia32_efer),
1155 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
1156 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
1157 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
1158 FIELD(EXCEPTION_BITMAP, exception_bitmap),
1159 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
1160 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
1161 FIELD(CR3_TARGET_COUNT, cr3_target_count),
1162 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
1163 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
1164 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
1165 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
1166 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
1167 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
1168 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
1169 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
1170 FIELD(TPR_THRESHOLD, tpr_threshold),
1171 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
1172 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
1173 FIELD(VM_EXIT_REASON, vm_exit_reason),
1174 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
1175 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
1176 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
1177 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
1178 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
1179 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
1180 FIELD(GUEST_ES_LIMIT, guest_es_limit),
1181 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
1182 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
1183 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
1184 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
1185 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
1186 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
1187 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
1188 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
1189 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
1190 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
1191 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
1192 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
1193 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
1194 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
1195 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
1196 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
1197 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
1198 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
1199 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
1200 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
1201 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
1202 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
1203 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
1204 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
1205 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
1206 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
1207 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
1208 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
1209 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
1210 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
1211 FIELD(EXIT_QUALIFICATION, exit_qualification),
1212 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
1213 FIELD(GUEST_CR0, guest_cr0),
1214 FIELD(GUEST_CR3, guest_cr3),
1215 FIELD(GUEST_CR4, guest_cr4),
1216 FIELD(GUEST_ES_BASE, guest_es_base),
1217 FIELD(GUEST_CS_BASE, guest_cs_base),
1218 FIELD(GUEST_SS_BASE, guest_ss_base),
1219 FIELD(GUEST_DS_BASE, guest_ds_base),
1220 FIELD(GUEST_FS_BASE, guest_fs_base),
1221 FIELD(GUEST_GS_BASE, guest_gs_base),
1222 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
1223 FIELD(GUEST_TR_BASE, guest_tr_base),
1224 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
1225 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
1226 FIELD(GUEST_DR7, guest_dr7),
1227 FIELD(GUEST_RSP, guest_rsp),
1228 FIELD(GUEST_RIP, guest_rip),
1229 FIELD(GUEST_RFLAGS, guest_rflags),
1230 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
1231 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
1232 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
1233 FIELD(HOST_CR0, host_cr0),
1234 FIELD(HOST_CR3, host_cr3),
1235 FIELD(HOST_CR4, host_cr4),
1236 FIELD(HOST_FS_BASE, host_fs_base),
1237 FIELD(HOST_GS_BASE, host_gs_base),
1238 FIELD(HOST_TR_BASE, host_tr_base),
1239 FIELD(HOST_GDTR_BASE, host_gdtr_base),
1240 FIELD(HOST_IDTR_BASE, host_idtr_base),
1241 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
1242 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
1243 FIELD(HOST_RSP, host_rsp),
1244 FIELD(HOST_RIP, host_rip),
1247 static inline short vmcs_field_to_offset(unsigned long field)
1249 const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
1250 unsigned short offset;
1256 index = ROL16(field, 6);
1260 index = array_index_nospec(index, size);
1261 offset = vmcs_field_to_offset_table[index];
1267 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
1269 return to_vmx(vcpu)->nested.cached_vmcs12;
1272 static inline struct vmcs12 *get_shadow_vmcs12(struct kvm_vcpu *vcpu)
1274 return to_vmx(vcpu)->nested.cached_shadow_vmcs12;
1277 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
1278 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
1279 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
1280 static bool vmx_xsaves_supported(void);
1281 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1282 struct kvm_segment *var, int seg);
1283 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1284 struct kvm_segment *var, int seg);
1285 static bool guest_state_valid(struct kvm_vcpu *vcpu);
1286 static u32 vmx_segment_access_rights(struct kvm_segment *var);
1287 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
1288 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
1289 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
1290 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
1292 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
1293 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
1296 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
1297 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
1299 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1300 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1302 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
1305 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1306 * can find which vCPU should be waken up.
1308 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
1309 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
1317 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
1319 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
1320 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
1322 static bool cpu_has_load_ia32_efer;
1323 static bool cpu_has_load_perf_global_ctrl;
1325 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
1326 static DEFINE_SPINLOCK(vmx_vpid_lock);
1328 static struct vmcs_config {
1333 u32 pin_based_exec_ctrl;
1334 u32 cpu_based_exec_ctrl;
1335 u32 cpu_based_2nd_exec_ctrl;
1338 struct nested_vmx_msrs nested;
1341 static struct vmx_capability {
1346 #define VMX_SEGMENT_FIELD(seg) \
1347 [VCPU_SREG_##seg] = { \
1348 .selector = GUEST_##seg##_SELECTOR, \
1349 .base = GUEST_##seg##_BASE, \
1350 .limit = GUEST_##seg##_LIMIT, \
1351 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1354 static const struct kvm_vmx_segment_field {
1359 } kvm_vmx_segment_fields[] = {
1360 VMX_SEGMENT_FIELD(CS),
1361 VMX_SEGMENT_FIELD(DS),
1362 VMX_SEGMENT_FIELD(ES),
1363 VMX_SEGMENT_FIELD(FS),
1364 VMX_SEGMENT_FIELD(GS),
1365 VMX_SEGMENT_FIELD(SS),
1366 VMX_SEGMENT_FIELD(TR),
1367 VMX_SEGMENT_FIELD(LDTR),
1370 static u64 host_efer;
1372 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1375 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1376 * away by decrementing the array size.
1378 static const u32 vmx_msr_index[] = {
1379 #ifdef CONFIG_X86_64
1380 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1382 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1385 DEFINE_STATIC_KEY_FALSE(enable_evmcs);
1387 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1389 #define KVM_EVMCS_VERSION 1
1391 #if IS_ENABLED(CONFIG_HYPERV)
1392 static bool __read_mostly enlightened_vmcs = true;
1393 module_param(enlightened_vmcs, bool, 0444);
1395 static inline void evmcs_write64(unsigned long field, u64 value)
1398 int offset = get_evmcs_offset(field, &clean_field);
1403 *(u64 *)((char *)current_evmcs + offset) = value;
1405 current_evmcs->hv_clean_fields &= ~clean_field;
1408 static inline void evmcs_write32(unsigned long field, u32 value)
1411 int offset = get_evmcs_offset(field, &clean_field);
1416 *(u32 *)((char *)current_evmcs + offset) = value;
1417 current_evmcs->hv_clean_fields &= ~clean_field;
1420 static inline void evmcs_write16(unsigned long field, u16 value)
1423 int offset = get_evmcs_offset(field, &clean_field);
1428 *(u16 *)((char *)current_evmcs + offset) = value;
1429 current_evmcs->hv_clean_fields &= ~clean_field;
1432 static inline u64 evmcs_read64(unsigned long field)
1434 int offset = get_evmcs_offset(field, NULL);
1439 return *(u64 *)((char *)current_evmcs + offset);
1442 static inline u32 evmcs_read32(unsigned long field)
1444 int offset = get_evmcs_offset(field, NULL);
1449 return *(u32 *)((char *)current_evmcs + offset);
1452 static inline u16 evmcs_read16(unsigned long field)
1454 int offset = get_evmcs_offset(field, NULL);
1459 return *(u16 *)((char *)current_evmcs + offset);
1462 static inline void evmcs_touch_msr_bitmap(void)
1464 if (unlikely(!current_evmcs))
1467 if (current_evmcs->hv_enlightenments_control.msr_bitmap)
1468 current_evmcs->hv_clean_fields &=
1469 ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP;
1472 static void evmcs_load(u64 phys_addr)
1474 struct hv_vp_assist_page *vp_ap =
1475 hv_get_vp_assist_page(smp_processor_id());
1477 vp_ap->current_nested_vmcs = phys_addr;
1478 vp_ap->enlighten_vmentry = 1;
1481 static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
1484 * Enlightened VMCSv1 doesn't support these:
1486 * POSTED_INTR_NV = 0x00000002,
1487 * GUEST_INTR_STATUS = 0x00000810,
1488 * APIC_ACCESS_ADDR = 0x00002014,
1489 * POSTED_INTR_DESC_ADDR = 0x00002016,
1490 * EOI_EXIT_BITMAP0 = 0x0000201c,
1491 * EOI_EXIT_BITMAP1 = 0x0000201e,
1492 * EOI_EXIT_BITMAP2 = 0x00002020,
1493 * EOI_EXIT_BITMAP3 = 0x00002022,
1495 vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
1496 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1497 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1498 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1499 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1500 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1501 ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
1504 * GUEST_PML_INDEX = 0x00000812,
1505 * PML_ADDRESS = 0x0000200e,
1507 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML;
1509 /* VM_FUNCTION_CONTROL = 0x00002018, */
1510 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC;
1513 * EPTP_LIST_ADDRESS = 0x00002024,
1514 * VMREAD_BITMAP = 0x00002026,
1515 * VMWRITE_BITMAP = 0x00002028,
1517 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS;
1520 * TSC_MULTIPLIER = 0x00002032,
1522 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING;
1525 * PLE_GAP = 0x00004020,
1526 * PLE_WINDOW = 0x00004022,
1528 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1531 * VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
1533 vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
1536 * GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
1537 * HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
1539 vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
1540 vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
1543 * Currently unsupported in KVM:
1544 * GUEST_IA32_RTIT_CTL = 0x00002814,
1548 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
1549 static void check_ept_pointer_match(struct kvm *kvm)
1551 struct kvm_vcpu *vcpu;
1552 u64 tmp_eptp = INVALID_PAGE;
1555 kvm_for_each_vcpu(i, vcpu, kvm) {
1556 if (!VALID_PAGE(tmp_eptp)) {
1557 tmp_eptp = to_vmx(vcpu)->ept_pointer;
1558 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
1559 to_kvm_vmx(kvm)->ept_pointers_match
1560 = EPT_POINTERS_MISMATCH;
1565 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
1568 static int vmx_hv_remote_flush_tlb(struct kvm *kvm)
1572 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
1574 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
1575 check_ept_pointer_match(kvm);
1577 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
1582 ret = hyperv_flush_guest_mapping(
1583 to_vmx(kvm_get_vcpu(kvm, 0))->ept_pointer);
1586 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
1589 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1590 static inline void evmcs_write64(unsigned long field, u64 value) {}
1591 static inline void evmcs_write32(unsigned long field, u32 value) {}
1592 static inline void evmcs_write16(unsigned long field, u16 value) {}
1593 static inline u64 evmcs_read64(unsigned long field) { return 0; }
1594 static inline u32 evmcs_read32(unsigned long field) { return 0; }
1595 static inline u16 evmcs_read16(unsigned long field) { return 0; }
1596 static inline void evmcs_load(u64 phys_addr) {}
1597 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
1598 static inline void evmcs_touch_msr_bitmap(void) {}
1599 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1601 static inline bool is_exception_n(u32 intr_info, u8 vector)
1603 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1604 INTR_INFO_VALID_MASK)) ==
1605 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1608 static inline bool is_debug(u32 intr_info)
1610 return is_exception_n(intr_info, DB_VECTOR);
1613 static inline bool is_breakpoint(u32 intr_info)
1615 return is_exception_n(intr_info, BP_VECTOR);
1618 static inline bool is_page_fault(u32 intr_info)
1620 return is_exception_n(intr_info, PF_VECTOR);
1623 static inline bool is_invalid_opcode(u32 intr_info)
1625 return is_exception_n(intr_info, UD_VECTOR);
1628 static inline bool is_gp_fault(u32 intr_info)
1630 return is_exception_n(intr_info, GP_VECTOR);
1633 static inline bool is_machine_check(u32 intr_info)
1635 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1636 INTR_INFO_VALID_MASK)) ==
1637 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1640 /* Undocumented: icebp/int1 */
1641 static inline bool is_icebp(u32 intr_info)
1643 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1644 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1647 static inline bool cpu_has_vmx_msr_bitmap(void)
1649 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1652 static inline bool cpu_has_vmx_tpr_shadow(void)
1654 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1657 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1659 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1662 static inline bool cpu_has_secondary_exec_ctrls(void)
1664 return vmcs_config.cpu_based_exec_ctrl &
1665 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1668 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1670 return vmcs_config.cpu_based_2nd_exec_ctrl &
1671 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1674 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1676 return vmcs_config.cpu_based_2nd_exec_ctrl &
1677 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1680 static inline bool cpu_has_vmx_apic_register_virt(void)
1682 return vmcs_config.cpu_based_2nd_exec_ctrl &
1683 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1686 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1688 return vmcs_config.cpu_based_2nd_exec_ctrl &
1689 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1692 static inline bool cpu_has_vmx_encls_vmexit(void)
1694 return vmcs_config.cpu_based_2nd_exec_ctrl &
1695 SECONDARY_EXEC_ENCLS_EXITING;
1699 * Comment's format: document - errata name - stepping - processor name.
1701 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1703 static u32 vmx_preemption_cpu_tfms[] = {
1704 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1706 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1707 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1708 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1710 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1712 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1713 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1715 * 320767.pdf - AAP86 - B1 -
1716 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1719 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1721 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1723 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1725 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1726 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1727 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1731 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1733 u32 eax = cpuid_eax(0x00000001), i;
1735 /* Clear the reserved bits */
1736 eax &= ~(0x3U << 14 | 0xfU << 28);
1737 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1738 if (eax == vmx_preemption_cpu_tfms[i])
1744 static inline bool cpu_has_vmx_preemption_timer(void)
1746 return vmcs_config.pin_based_exec_ctrl &
1747 PIN_BASED_VMX_PREEMPTION_TIMER;
1750 static inline bool cpu_has_vmx_posted_intr(void)
1752 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1753 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1756 static inline bool cpu_has_vmx_apicv(void)
1758 return cpu_has_vmx_apic_register_virt() &&
1759 cpu_has_vmx_virtual_intr_delivery() &&
1760 cpu_has_vmx_posted_intr();
1763 static inline bool cpu_has_vmx_flexpriority(void)
1765 return cpu_has_vmx_tpr_shadow() &&
1766 cpu_has_vmx_virtualize_apic_accesses();
1769 static inline bool cpu_has_vmx_ept_execute_only(void)
1771 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1774 static inline bool cpu_has_vmx_ept_2m_page(void)
1776 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1779 static inline bool cpu_has_vmx_ept_1g_page(void)
1781 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1784 static inline bool cpu_has_vmx_ept_4levels(void)
1786 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1789 static inline bool cpu_has_vmx_ept_mt_wb(void)
1791 return vmx_capability.ept & VMX_EPTP_WB_BIT;
1794 static inline bool cpu_has_vmx_ept_5levels(void)
1796 return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1799 static inline bool cpu_has_vmx_ept_ad_bits(void)
1801 return vmx_capability.ept & VMX_EPT_AD_BIT;
1804 static inline bool cpu_has_vmx_invept_context(void)
1806 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1809 static inline bool cpu_has_vmx_invept_global(void)
1811 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1814 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
1816 return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT;
1819 static inline bool cpu_has_vmx_invvpid_single(void)
1821 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1824 static inline bool cpu_has_vmx_invvpid_global(void)
1826 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1829 static inline bool cpu_has_vmx_invvpid(void)
1831 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1834 static inline bool cpu_has_vmx_ept(void)
1836 return vmcs_config.cpu_based_2nd_exec_ctrl &
1837 SECONDARY_EXEC_ENABLE_EPT;
1840 static inline bool cpu_has_vmx_unrestricted_guest(void)
1842 return vmcs_config.cpu_based_2nd_exec_ctrl &
1843 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1846 static inline bool cpu_has_vmx_ple(void)
1848 return vmcs_config.cpu_based_2nd_exec_ctrl &
1849 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1852 static inline bool cpu_has_vmx_basic_inout(void)
1854 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1857 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1859 return flexpriority_enabled && lapic_in_kernel(vcpu);
1862 static inline bool cpu_has_vmx_vpid(void)
1864 return vmcs_config.cpu_based_2nd_exec_ctrl &
1865 SECONDARY_EXEC_ENABLE_VPID;
1868 static inline bool cpu_has_vmx_rdtscp(void)
1870 return vmcs_config.cpu_based_2nd_exec_ctrl &
1871 SECONDARY_EXEC_RDTSCP;
1874 static inline bool cpu_has_vmx_invpcid(void)
1876 return vmcs_config.cpu_based_2nd_exec_ctrl &
1877 SECONDARY_EXEC_ENABLE_INVPCID;
1880 static inline bool cpu_has_virtual_nmis(void)
1882 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1885 static inline bool cpu_has_vmx_wbinvd_exit(void)
1887 return vmcs_config.cpu_based_2nd_exec_ctrl &
1888 SECONDARY_EXEC_WBINVD_EXITING;
1891 static inline bool cpu_has_vmx_shadow_vmcs(void)
1894 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1895 /* check if the cpu supports writing r/o exit information fields */
1896 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1899 return vmcs_config.cpu_based_2nd_exec_ctrl &
1900 SECONDARY_EXEC_SHADOW_VMCS;
1903 static inline bool cpu_has_vmx_pml(void)
1905 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1908 static inline bool cpu_has_vmx_tsc_scaling(void)
1910 return vmcs_config.cpu_based_2nd_exec_ctrl &
1911 SECONDARY_EXEC_TSC_SCALING;
1914 static inline bool cpu_has_vmx_vmfunc(void)
1916 return vmcs_config.cpu_based_2nd_exec_ctrl &
1917 SECONDARY_EXEC_ENABLE_VMFUNC;
1920 static bool vmx_umip_emulated(void)
1922 return vmcs_config.cpu_based_2nd_exec_ctrl &
1923 SECONDARY_EXEC_DESC;
1926 static inline bool report_flexpriority(void)
1928 return flexpriority_enabled;
1931 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1933 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
1937 * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
1938 * to modify any valid field of the VMCS, or are the VM-exit
1939 * information fields read-only?
1941 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
1943 return to_vmx(vcpu)->nested.msrs.misc_low &
1944 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
1947 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)
1949 return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS;
1952 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu)
1954 return to_vmx(vcpu)->nested.msrs.procbased_ctls_high &
1955 CPU_BASED_MONITOR_TRAP_FLAG;
1958 static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu *vcpu)
1960 return to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
1961 SECONDARY_EXEC_SHADOW_VMCS;
1964 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1966 return vmcs12->cpu_based_vm_exec_control & bit;
1969 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1971 return (vmcs12->cpu_based_vm_exec_control &
1972 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1973 (vmcs12->secondary_vm_exec_control & bit);
1976 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1978 return vmcs12->pin_based_vm_exec_control &
1979 PIN_BASED_VMX_PREEMPTION_TIMER;
1982 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
1984 return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
1987 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1989 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1992 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1994 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1997 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1999 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
2002 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
2004 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
2007 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
2009 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
2012 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
2014 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
2017 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
2019 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
2022 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
2024 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2027 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
2029 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
2032 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
2034 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
2037 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
2039 return nested_cpu_has_vmfunc(vmcs12) &&
2040 (vmcs12->vm_function_control &
2041 VMX_VMFUNC_EPTP_SWITCHING);
2044 static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12 *vmcs12)
2046 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS);
2049 static inline bool is_nmi(u32 intr_info)
2051 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
2052 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
2055 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
2057 unsigned long exit_qualification);
2059 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
2063 for (i = 0; i < vmx->nmsrs; ++i)
2064 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
2069 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
2075 } operand = { vpid, 0, gva };
2078 asm volatile (__ex(ASM_VMX_INVVPID) CC_SET(na)
2079 : CC_OUT(na) (error) : "a"(&operand), "c"(ext)
2084 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
2088 } operand = {eptp, gpa};
2091 asm volatile (__ex(ASM_VMX_INVEPT) CC_SET(na)
2092 : CC_OUT(na) (error) : "a" (&operand), "c" (ext)
2097 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
2101 i = __find_msr_index(vmx, msr);
2103 return &vmx->guest_msrs[i];
2107 static void vmcs_clear(struct vmcs *vmcs)
2109 u64 phys_addr = __pa(vmcs);
2112 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) CC_SET(na)
2113 : CC_OUT(na) (error) : "a"(&phys_addr), "m"(phys_addr)
2115 if (unlikely(error))
2116 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
2120 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
2122 vmcs_clear(loaded_vmcs->vmcs);
2123 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
2124 vmcs_clear(loaded_vmcs->shadow_vmcs);
2125 loaded_vmcs->cpu = -1;
2126 loaded_vmcs->launched = 0;
2129 static void vmcs_load(struct vmcs *vmcs)
2131 u64 phys_addr = __pa(vmcs);
2134 if (static_branch_unlikely(&enable_evmcs))
2135 return evmcs_load(phys_addr);
2137 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) CC_SET(na)
2138 : CC_OUT(na) (error) : "a"(&phys_addr), "m"(phys_addr)
2140 if (unlikely(error))
2141 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
2145 #ifdef CONFIG_KEXEC_CORE
2147 * This bitmap is used to indicate whether the vmclear
2148 * operation is enabled on all cpus. All disabled by
2151 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
2153 static inline void crash_enable_local_vmclear(int cpu)
2155 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
2158 static inline void crash_disable_local_vmclear(int cpu)
2160 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
2163 static inline int crash_local_vmclear_enabled(int cpu)
2165 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
2168 static void crash_vmclear_local_loaded_vmcss(void)
2170 int cpu = raw_smp_processor_id();
2171 struct loaded_vmcs *v;
2173 if (!crash_local_vmclear_enabled(cpu))
2176 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
2177 loaded_vmcss_on_cpu_link)
2178 vmcs_clear(v->vmcs);
2181 static inline void crash_enable_local_vmclear(int cpu) { }
2182 static inline void crash_disable_local_vmclear(int cpu) { }
2183 #endif /* CONFIG_KEXEC_CORE */
2185 static void __loaded_vmcs_clear(void *arg)
2187 struct loaded_vmcs *loaded_vmcs = arg;
2188 int cpu = raw_smp_processor_id();
2190 if (loaded_vmcs->cpu != cpu)
2191 return; /* vcpu migration can race with cpu offline */
2192 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
2193 per_cpu(current_vmcs, cpu) = NULL;
2194 crash_disable_local_vmclear(cpu);
2195 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
2198 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
2199 * is before setting loaded_vmcs->vcpu to -1 which is done in
2200 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
2201 * then adds the vmcs into percpu list before it is deleted.
2205 loaded_vmcs_init(loaded_vmcs);
2206 crash_enable_local_vmclear(cpu);
2209 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
2211 int cpu = loaded_vmcs->cpu;
2214 smp_call_function_single(cpu,
2215 __loaded_vmcs_clear, loaded_vmcs, 1);
2218 static inline bool vpid_sync_vcpu_addr(int vpid, gva_t addr)
2223 if (cpu_has_vmx_invvpid_individual_addr()) {
2224 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR, vpid, addr);
2231 static inline void vpid_sync_vcpu_single(int vpid)
2236 if (cpu_has_vmx_invvpid_single())
2237 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2240 static inline void vpid_sync_vcpu_global(void)
2242 if (cpu_has_vmx_invvpid_global())
2243 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
2246 static inline void vpid_sync_context(int vpid)
2248 if (cpu_has_vmx_invvpid_single())
2249 vpid_sync_vcpu_single(vpid);
2251 vpid_sync_vcpu_global();
2254 static inline void ept_sync_global(void)
2256 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
2259 static inline void ept_sync_context(u64 eptp)
2261 if (cpu_has_vmx_invept_context())
2262 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
2267 static __always_inline void vmcs_check16(unsigned long field)
2269 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2270 "16-bit accessor invalid for 64-bit field");
2271 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2272 "16-bit accessor invalid for 64-bit high field");
2273 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2274 "16-bit accessor invalid for 32-bit high field");
2275 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2276 "16-bit accessor invalid for natural width field");
2279 static __always_inline void vmcs_check32(unsigned long field)
2281 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2282 "32-bit accessor invalid for 16-bit field");
2283 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2284 "32-bit accessor invalid for natural width field");
2287 static __always_inline void vmcs_check64(unsigned long field)
2289 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2290 "64-bit accessor invalid for 16-bit field");
2291 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2292 "64-bit accessor invalid for 64-bit high field");
2293 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2294 "64-bit accessor invalid for 32-bit field");
2295 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2296 "64-bit accessor invalid for natural width field");
2299 static __always_inline void vmcs_checkl(unsigned long field)
2301 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2302 "Natural width accessor invalid for 16-bit field");
2303 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2304 "Natural width accessor invalid for 64-bit field");
2305 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2306 "Natural width accessor invalid for 64-bit high field");
2307 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2308 "Natural width accessor invalid for 32-bit field");
2311 static __always_inline unsigned long __vmcs_readl(unsigned long field)
2313 unsigned long value;
2315 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
2316 : "=a"(value) : "d"(field) : "cc");
2320 static __always_inline u16 vmcs_read16(unsigned long field)
2322 vmcs_check16(field);
2323 if (static_branch_unlikely(&enable_evmcs))
2324 return evmcs_read16(field);
2325 return __vmcs_readl(field);
2328 static __always_inline u32 vmcs_read32(unsigned long field)
2330 vmcs_check32(field);
2331 if (static_branch_unlikely(&enable_evmcs))
2332 return evmcs_read32(field);
2333 return __vmcs_readl(field);
2336 static __always_inline u64 vmcs_read64(unsigned long field)
2338 vmcs_check64(field);
2339 if (static_branch_unlikely(&enable_evmcs))
2340 return evmcs_read64(field);
2341 #ifdef CONFIG_X86_64
2342 return __vmcs_readl(field);
2344 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
2348 static __always_inline unsigned long vmcs_readl(unsigned long field)
2351 if (static_branch_unlikely(&enable_evmcs))
2352 return evmcs_read64(field);
2353 return __vmcs_readl(field);
2356 static noinline void vmwrite_error(unsigned long field, unsigned long value)
2358 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
2359 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
2363 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
2367 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) CC_SET(na)
2368 : CC_OUT(na) (error) : "a"(value), "d"(field));
2369 if (unlikely(error))
2370 vmwrite_error(field, value);
2373 static __always_inline void vmcs_write16(unsigned long field, u16 value)
2375 vmcs_check16(field);
2376 if (static_branch_unlikely(&enable_evmcs))
2377 return evmcs_write16(field, value);
2379 __vmcs_writel(field, value);
2382 static __always_inline void vmcs_write32(unsigned long field, u32 value)
2384 vmcs_check32(field);
2385 if (static_branch_unlikely(&enable_evmcs))
2386 return evmcs_write32(field, value);
2388 __vmcs_writel(field, value);
2391 static __always_inline void vmcs_write64(unsigned long field, u64 value)
2393 vmcs_check64(field);
2394 if (static_branch_unlikely(&enable_evmcs))
2395 return evmcs_write64(field, value);
2397 __vmcs_writel(field, value);
2398 #ifndef CONFIG_X86_64
2400 __vmcs_writel(field+1, value >> 32);
2404 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2407 if (static_branch_unlikely(&enable_evmcs))
2408 return evmcs_write64(field, value);
2410 __vmcs_writel(field, value);
2413 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2415 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2416 "vmcs_clear_bits does not support 64-bit fields");
2417 if (static_branch_unlikely(&enable_evmcs))
2418 return evmcs_write32(field, evmcs_read32(field) & ~mask);
2420 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2423 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2425 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2426 "vmcs_set_bits does not support 64-bit fields");
2427 if (static_branch_unlikely(&enable_evmcs))
2428 return evmcs_write32(field, evmcs_read32(field) | mask);
2430 __vmcs_writel(field, __vmcs_readl(field) | mask);
2433 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
2435 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
2438 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
2440 vmcs_write32(VM_ENTRY_CONTROLS, val);
2441 vmx->vm_entry_controls_shadow = val;
2444 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
2446 if (vmx->vm_entry_controls_shadow != val)
2447 vm_entry_controls_init(vmx, val);
2450 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
2452 return vmx->vm_entry_controls_shadow;
2456 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2458 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
2461 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2463 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
2466 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
2468 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
2471 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
2473 vmcs_write32(VM_EXIT_CONTROLS, val);
2474 vmx->vm_exit_controls_shadow = val;
2477 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2479 if (vmx->vm_exit_controls_shadow != val)
2480 vm_exit_controls_init(vmx, val);
2483 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2485 return vmx->vm_exit_controls_shadow;
2489 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2491 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2494 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2496 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2499 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2501 vmx->segment_cache.bitmask = 0;
2504 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2508 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2510 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2511 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2512 vmx->segment_cache.bitmask = 0;
2514 ret = vmx->segment_cache.bitmask & mask;
2515 vmx->segment_cache.bitmask |= mask;
2519 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2521 u16 *p = &vmx->segment_cache.seg[seg].selector;
2523 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2524 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2528 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2530 ulong *p = &vmx->segment_cache.seg[seg].base;
2532 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2533 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2537 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2539 u32 *p = &vmx->segment_cache.seg[seg].limit;
2541 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2542 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2546 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2548 u32 *p = &vmx->segment_cache.seg[seg].ar;
2550 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2551 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2555 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2559 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2560 (1u << DB_VECTOR) | (1u << AC_VECTOR);
2562 * Guest access to VMware backdoor ports could legitimately
2563 * trigger #GP because of TSS I/O permission bitmap.
2564 * We intercept those #GP and allow access to them anyway
2567 if (enable_vmware_backdoor)
2568 eb |= (1u << GP_VECTOR);
2569 if ((vcpu->guest_debug &
2570 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2571 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2572 eb |= 1u << BP_VECTOR;
2573 if (to_vmx(vcpu)->rmode.vm86_active)
2576 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2578 /* When we are running a nested L2 guest and L1 specified for it a
2579 * certain exception bitmap, we must trap the same exceptions and pass
2580 * them to L1. When running L2, we will only handle the exceptions
2581 * specified above if L1 did not want them.
2583 if (is_guest_mode(vcpu))
2584 eb |= get_vmcs12(vcpu)->exception_bitmap;
2586 vmcs_write32(EXCEPTION_BITMAP, eb);
2590 * Check if MSR is intercepted for currently loaded MSR bitmap.
2592 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2594 unsigned long *msr_bitmap;
2595 int f = sizeof(unsigned long);
2597 if (!cpu_has_vmx_msr_bitmap())
2600 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2602 if (msr <= 0x1fff) {
2603 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2604 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2606 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2613 * Check if MSR is intercepted for L01 MSR bitmap.
2615 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2617 unsigned long *msr_bitmap;
2618 int f = sizeof(unsigned long);
2620 if (!cpu_has_vmx_msr_bitmap())
2623 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2625 if (msr <= 0x1fff) {
2626 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2627 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2629 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2635 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2636 unsigned long entry, unsigned long exit)
2638 vm_entry_controls_clearbit(vmx, entry);
2639 vm_exit_controls_clearbit(vmx, exit);
2642 static int find_msr(struct vmx_msrs *m, unsigned int msr)
2646 for (i = 0; i < m->nr; ++i) {
2647 if (m->val[i].index == msr)
2653 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2656 struct msr_autoload *m = &vmx->msr_autoload;
2660 if (cpu_has_load_ia32_efer) {
2661 clear_atomic_switch_msr_special(vmx,
2662 VM_ENTRY_LOAD_IA32_EFER,
2663 VM_EXIT_LOAD_IA32_EFER);
2667 case MSR_CORE_PERF_GLOBAL_CTRL:
2668 if (cpu_has_load_perf_global_ctrl) {
2669 clear_atomic_switch_msr_special(vmx,
2670 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2671 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2676 i = find_msr(&m->guest, msr);
2680 m->guest.val[i] = m->guest.val[m->guest.nr];
2681 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2684 i = find_msr(&m->host, msr);
2689 m->host.val[i] = m->host.val[m->host.nr];
2690 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2693 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2694 unsigned long entry, unsigned long exit,
2695 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2696 u64 guest_val, u64 host_val)
2698 vmcs_write64(guest_val_vmcs, guest_val);
2699 if (host_val_vmcs != HOST_IA32_EFER)
2700 vmcs_write64(host_val_vmcs, host_val);
2701 vm_entry_controls_setbit(vmx, entry);
2702 vm_exit_controls_setbit(vmx, exit);
2705 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2706 u64 guest_val, u64 host_val, bool entry_only)
2709 struct msr_autoload *m = &vmx->msr_autoload;
2713 if (cpu_has_load_ia32_efer) {
2714 add_atomic_switch_msr_special(vmx,
2715 VM_ENTRY_LOAD_IA32_EFER,
2716 VM_EXIT_LOAD_IA32_EFER,
2719 guest_val, host_val);
2723 case MSR_CORE_PERF_GLOBAL_CTRL:
2724 if (cpu_has_load_perf_global_ctrl) {
2725 add_atomic_switch_msr_special(vmx,
2726 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2727 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2728 GUEST_IA32_PERF_GLOBAL_CTRL,
2729 HOST_IA32_PERF_GLOBAL_CTRL,
2730 guest_val, host_val);
2734 case MSR_IA32_PEBS_ENABLE:
2735 /* PEBS needs a quiescent period after being disabled (to write
2736 * a record). Disabling PEBS through VMX MSR swapping doesn't
2737 * provide that period, so a CPU could write host's record into
2740 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2743 i = find_msr(&m->guest, msr);
2745 j = find_msr(&m->host, msr);
2747 if (i == NR_AUTOLOAD_MSRS || j == NR_AUTOLOAD_MSRS) {
2748 printk_once(KERN_WARNING "Not enough msr switch entries. "
2749 "Can't add msr %x\n", msr);
2754 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2756 m->guest.val[i].index = msr;
2757 m->guest.val[i].value = guest_val;
2764 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2766 m->host.val[j].index = msr;
2767 m->host.val[j].value = host_val;
2770 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2772 u64 guest_efer = vmx->vcpu.arch.efer;
2773 u64 ignore_bits = 0;
2777 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2778 * host CPUID is more efficient than testing guest CPUID
2779 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2781 if (boot_cpu_has(X86_FEATURE_SMEP))
2782 guest_efer |= EFER_NX;
2783 else if (!(guest_efer & EFER_NX))
2784 ignore_bits |= EFER_NX;
2788 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2790 ignore_bits |= EFER_SCE;
2791 #ifdef CONFIG_X86_64
2792 ignore_bits |= EFER_LMA | EFER_LME;
2793 /* SCE is meaningful only in long mode on Intel */
2794 if (guest_efer & EFER_LMA)
2795 ignore_bits &= ~(u64)EFER_SCE;
2799 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2800 * On CPUs that support "load IA32_EFER", always switch EFER
2801 * atomically, since it's faster than switching it manually.
2803 if (cpu_has_load_ia32_efer ||
2804 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2805 if (!(guest_efer & EFER_LMA))
2806 guest_efer &= ~EFER_LME;
2807 if (guest_efer != host_efer)
2808 add_atomic_switch_msr(vmx, MSR_EFER,
2809 guest_efer, host_efer, false);
2811 clear_atomic_switch_msr(vmx, MSR_EFER);
2814 clear_atomic_switch_msr(vmx, MSR_EFER);
2816 guest_efer &= ~ignore_bits;
2817 guest_efer |= host_efer & ignore_bits;
2819 vmx->guest_msrs[efer_offset].data = guest_efer;
2820 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2826 #ifdef CONFIG_X86_32
2828 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2829 * VMCS rather than the segment table. KVM uses this helper to figure
2830 * out the current bases to poke them into the VMCS before entry.
2832 static unsigned long segment_base(u16 selector)
2834 struct desc_struct *table;
2837 if (!(selector & ~SEGMENT_RPL_MASK))
2840 table = get_current_gdt_ro();
2842 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2843 u16 ldt_selector = kvm_read_ldt();
2845 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2848 table = (struct desc_struct *)segment_base(ldt_selector);
2850 v = get_desc_base(&table[selector >> 3]);
2855 static void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
2857 struct vcpu_vmx *vmx = to_vmx(vcpu);
2858 struct vmcs_host_state *host_state;
2859 #ifdef CONFIG_X86_64
2860 int cpu = raw_smp_processor_id();
2862 unsigned long fs_base, gs_base;
2866 vmx->req_immediate_exit = false;
2868 if (vmx->loaded_cpu_state)
2871 vmx->loaded_cpu_state = vmx->loaded_vmcs;
2872 host_state = &vmx->loaded_cpu_state->host_state;
2875 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2876 * allow segment selectors with cpl > 0 or ti == 1.
2878 host_state->ldt_sel = kvm_read_ldt();
2880 #ifdef CONFIG_X86_64
2881 savesegment(ds, host_state->ds_sel);
2882 savesegment(es, host_state->es_sel);
2884 gs_base = cpu_kernelmode_gs_base(cpu);
2885 if (likely(is_64bit_mm(current->mm))) {
2886 save_fsgs_for_kvm();
2887 fs_sel = current->thread.fsindex;
2888 gs_sel = current->thread.gsindex;
2889 fs_base = current->thread.fsbase;
2890 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
2892 savesegment(fs, fs_sel);
2893 savesegment(gs, gs_sel);
2894 fs_base = read_msr(MSR_FS_BASE);
2895 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
2898 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2900 savesegment(fs, fs_sel);
2901 savesegment(gs, gs_sel);
2902 fs_base = segment_base(fs_sel);
2903 gs_base = segment_base(gs_sel);
2906 if (unlikely(fs_sel != host_state->fs_sel)) {
2908 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
2910 vmcs_write16(HOST_FS_SELECTOR, 0);
2911 host_state->fs_sel = fs_sel;
2913 if (unlikely(gs_sel != host_state->gs_sel)) {
2915 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
2917 vmcs_write16(HOST_GS_SELECTOR, 0);
2918 host_state->gs_sel = gs_sel;
2920 if (unlikely(fs_base != host_state->fs_base)) {
2921 vmcs_writel(HOST_FS_BASE, fs_base);
2922 host_state->fs_base = fs_base;
2924 if (unlikely(gs_base != host_state->gs_base)) {
2925 vmcs_writel(HOST_GS_BASE, gs_base);
2926 host_state->gs_base = gs_base;
2929 for (i = 0; i < vmx->save_nmsrs; ++i)
2930 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2931 vmx->guest_msrs[i].data,
2932 vmx->guest_msrs[i].mask);
2935 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
2937 struct vmcs_host_state *host_state;
2939 if (!vmx->loaded_cpu_state)
2942 WARN_ON_ONCE(vmx->loaded_cpu_state != vmx->loaded_vmcs);
2943 host_state = &vmx->loaded_cpu_state->host_state;
2945 ++vmx->vcpu.stat.host_state_reload;
2946 vmx->loaded_cpu_state = NULL;
2948 #ifdef CONFIG_X86_64
2949 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2951 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
2952 kvm_load_ldt(host_state->ldt_sel);
2953 #ifdef CONFIG_X86_64
2954 load_gs_index(host_state->gs_sel);
2956 loadsegment(gs, host_state->gs_sel);
2959 if (host_state->fs_sel & 7)
2960 loadsegment(fs, host_state->fs_sel);
2961 #ifdef CONFIG_X86_64
2962 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
2963 loadsegment(ds, host_state->ds_sel);
2964 loadsegment(es, host_state->es_sel);
2967 invalidate_tss_limit();
2968 #ifdef CONFIG_X86_64
2969 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2971 load_fixmap_gdt(raw_smp_processor_id());
2974 #ifdef CONFIG_X86_64
2975 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
2978 if (vmx->loaded_cpu_state)
2979 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2981 return vmx->msr_guest_kernel_gs_base;
2984 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
2987 if (vmx->loaded_cpu_state)
2988 wrmsrl(MSR_KERNEL_GS_BASE, data);
2990 vmx->msr_guest_kernel_gs_base = data;
2994 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2996 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2997 struct pi_desc old, new;
3001 * In case of hot-plug or hot-unplug, we may have to undo
3002 * vmx_vcpu_pi_put even if there is no assigned device. And we
3003 * always keep PI.NDST up to date for simplicity: it makes the
3004 * code easier, and CPU migration is not a fast path.
3006 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
3010 * First handle the simple case where no cmpxchg is necessary; just
3011 * allow posting non-urgent interrupts.
3013 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
3014 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
3015 * expects the VCPU to be on the blocked_vcpu_list that matches
3018 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
3020 pi_clear_sn(pi_desc);
3024 /* The full case. */
3026 old.control = new.control = pi_desc->control;
3028 dest = cpu_physical_id(cpu);
3030 if (x2apic_enabled())
3033 new.ndst = (dest << 8) & 0xFF00;
3036 } while (cmpxchg64(&pi_desc->control, old.control,
3037 new.control) != old.control);
3040 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
3042 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
3043 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
3047 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
3048 * vcpu mutex is already taken.
3050 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3052 struct vcpu_vmx *vmx = to_vmx(vcpu);
3053 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
3055 if (!already_loaded) {
3056 loaded_vmcs_clear(vmx->loaded_vmcs);
3057 local_irq_disable();
3058 crash_disable_local_vmclear(cpu);
3061 * Read loaded_vmcs->cpu should be before fetching
3062 * loaded_vmcs->loaded_vmcss_on_cpu_link.
3063 * See the comments in __loaded_vmcs_clear().
3067 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
3068 &per_cpu(loaded_vmcss_on_cpu, cpu));
3069 crash_enable_local_vmclear(cpu);
3073 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
3074 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
3075 vmcs_load(vmx->loaded_vmcs->vmcs);
3076 indirect_branch_prediction_barrier();
3079 if (!already_loaded) {
3080 void *gdt = get_current_gdt_ro();
3081 unsigned long sysenter_esp;
3083 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3086 * Linux uses per-cpu TSS and GDT, so set these when switching
3087 * processors. See 22.2.4.
3089 vmcs_writel(HOST_TR_BASE,
3090 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
3091 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
3094 * VM exits change the host TR limit to 0x67 after a VM
3095 * exit. This is okay, since 0x67 covers everything except
3096 * the IO bitmap and have have code to handle the IO bitmap
3097 * being lost after a VM exit.
3099 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
3101 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
3102 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
3104 vmx->loaded_vmcs->cpu = cpu;
3107 /* Setup TSC multiplier */
3108 if (kvm_has_tsc_control &&
3109 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
3110 decache_tsc_multiplier(vmx);
3112 vmx_vcpu_pi_load(vcpu, cpu);
3113 vmx->host_pkru = read_pkru();
3114 vmx->host_debugctlmsr = get_debugctlmsr();
3117 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
3119 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
3121 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
3122 !irq_remapping_cap(IRQ_POSTING_CAP) ||
3123 !kvm_vcpu_apicv_active(vcpu))
3126 /* Set SN when the vCPU is preempted */
3127 if (vcpu->preempted)
3131 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
3133 vmx_vcpu_pi_put(vcpu);
3135 vmx_prepare_switch_to_host(to_vmx(vcpu));
3138 static bool emulation_required(struct kvm_vcpu *vcpu)
3140 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3143 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
3146 * Return the cr0 value that a nested guest would read. This is a combination
3147 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
3148 * its hypervisor (cr0_read_shadow).
3150 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
3152 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
3153 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
3155 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
3157 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
3158 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
3161 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
3163 unsigned long rflags, save_rflags;
3165 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
3166 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
3167 rflags = vmcs_readl(GUEST_RFLAGS);
3168 if (to_vmx(vcpu)->rmode.vm86_active) {
3169 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3170 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
3171 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3173 to_vmx(vcpu)->rflags = rflags;
3175 return to_vmx(vcpu)->rflags;
3178 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
3180 unsigned long old_rflags = vmx_get_rflags(vcpu);
3182 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
3183 to_vmx(vcpu)->rflags = rflags;
3184 if (to_vmx(vcpu)->rmode.vm86_active) {
3185 to_vmx(vcpu)->rmode.save_rflags = rflags;
3186 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3188 vmcs_writel(GUEST_RFLAGS, rflags);
3190 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
3191 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
3194 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
3196 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3199 if (interruptibility & GUEST_INTR_STATE_STI)
3200 ret |= KVM_X86_SHADOW_INT_STI;
3201 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
3202 ret |= KVM_X86_SHADOW_INT_MOV_SS;
3207 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
3209 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3210 u32 interruptibility = interruptibility_old;
3212 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
3214 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
3215 interruptibility |= GUEST_INTR_STATE_MOV_SS;
3216 else if (mask & KVM_X86_SHADOW_INT_STI)
3217 interruptibility |= GUEST_INTR_STATE_STI;
3219 if ((interruptibility != interruptibility_old))
3220 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
3223 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
3227 rip = kvm_rip_read(vcpu);
3228 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3229 kvm_rip_write(vcpu, rip);
3231 /* skipping an emulated instruction also counts */
3232 vmx_set_interrupt_shadow(vcpu, 0);
3235 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
3236 unsigned long exit_qual)
3238 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3239 unsigned int nr = vcpu->arch.exception.nr;
3240 u32 intr_info = nr | INTR_INFO_VALID_MASK;
3242 if (vcpu->arch.exception.has_error_code) {
3243 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
3244 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3247 if (kvm_exception_is_soft(nr))
3248 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3250 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3252 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
3253 vmx_get_nmi_mask(vcpu))
3254 intr_info |= INTR_INFO_UNBLOCK_NMI;
3256 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
3260 * KVM wants to inject page-faults which it got to the guest. This function
3261 * checks whether in a nested guest, we need to inject them to L1 or L2.
3263 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
3265 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3266 unsigned int nr = vcpu->arch.exception.nr;
3268 if (nr == PF_VECTOR) {
3269 if (vcpu->arch.exception.nested_apf) {
3270 *exit_qual = vcpu->arch.apf.nested_apf_token;
3274 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
3275 * The fix is to add the ancillary datum (CR2 or DR6) to structs
3276 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
3277 * can be written only when inject_pending_event runs. This should be
3278 * conditional on a new capability---if the capability is disabled,
3279 * kvm_multiple_exception would write the ancillary information to
3280 * CR2 or DR6, for backwards ABI-compatibility.
3282 if (nested_vmx_is_page_fault_vmexit(vmcs12,
3283 vcpu->arch.exception.error_code)) {
3284 *exit_qual = vcpu->arch.cr2;
3288 if (vmcs12->exception_bitmap & (1u << nr)) {
3289 if (nr == DB_VECTOR) {
3290 *exit_qual = vcpu->arch.dr6;
3291 *exit_qual &= ~(DR6_FIXED_1 | DR6_BT);
3292 *exit_qual ^= DR6_RTM;
3303 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
3306 * Ensure that we clear the HLT state in the VMCS. We don't need to
3307 * explicitly skip the instruction because if the HLT state is set,
3308 * then the instruction is already executing and RIP has already been
3311 if (kvm_hlt_in_guest(vcpu->kvm) &&
3312 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
3313 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3316 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
3318 struct vcpu_vmx *vmx = to_vmx(vcpu);
3319 unsigned nr = vcpu->arch.exception.nr;
3320 bool has_error_code = vcpu->arch.exception.has_error_code;
3321 u32 error_code = vcpu->arch.exception.error_code;
3322 u32 intr_info = nr | INTR_INFO_VALID_MASK;
3324 if (has_error_code) {
3325 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
3326 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3329 if (vmx->rmode.vm86_active) {
3331 if (kvm_exception_is_soft(nr))
3332 inc_eip = vcpu->arch.event_exit_inst_len;
3333 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
3334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3338 WARN_ON_ONCE(vmx->emulation_required);
3340 if (kvm_exception_is_soft(nr)) {
3341 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3342 vmx->vcpu.arch.event_exit_inst_len);
3343 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3345 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3347 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
3349 vmx_clear_hlt(vcpu);
3352 static bool vmx_rdtscp_supported(void)
3354 return cpu_has_vmx_rdtscp();
3357 static bool vmx_invpcid_supported(void)
3359 return cpu_has_vmx_invpcid();
3363 * Swap MSR entry in host/guest MSR entry array.
3365 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
3367 struct shared_msr_entry tmp;
3369 tmp = vmx->guest_msrs[to];
3370 vmx->guest_msrs[to] = vmx->guest_msrs[from];
3371 vmx->guest_msrs[from] = tmp;
3375 * Set up the vmcs to automatically save and restore system
3376 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
3377 * mode, as fiddling with msrs is very expensive.
3379 static void setup_msrs(struct vcpu_vmx *vmx)
3381 int save_nmsrs, index;
3384 #ifdef CONFIG_X86_64
3385 if (is_long_mode(&vmx->vcpu)) {
3386 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
3388 move_msr_up(vmx, index, save_nmsrs++);
3389 index = __find_msr_index(vmx, MSR_LSTAR);
3391 move_msr_up(vmx, index, save_nmsrs++);
3392 index = __find_msr_index(vmx, MSR_CSTAR);
3394 move_msr_up(vmx, index, save_nmsrs++);
3395 index = __find_msr_index(vmx, MSR_TSC_AUX);
3396 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
3397 move_msr_up(vmx, index, save_nmsrs++);
3399 * MSR_STAR is only needed on long mode guests, and only
3400 * if efer.sce is enabled.
3402 index = __find_msr_index(vmx, MSR_STAR);
3403 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
3404 move_msr_up(vmx, index, save_nmsrs++);
3407 index = __find_msr_index(vmx, MSR_EFER);
3408 if (index >= 0 && update_transition_efer(vmx, index))
3409 move_msr_up(vmx, index, save_nmsrs++);
3411 vmx->save_nmsrs = save_nmsrs;
3413 if (cpu_has_vmx_msr_bitmap())
3414 vmx_update_msr_bitmap(&vmx->vcpu);
3417 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
3419 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3421 if (is_guest_mode(vcpu) &&
3422 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
3423 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
3425 return vcpu->arch.tsc_offset;
3429 * writes 'offset' into guest's timestamp counter offset register
3431 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
3433 if (is_guest_mode(vcpu)) {
3435 * We're here if L1 chose not to trap WRMSR to TSC. According
3436 * to the spec, this should set L1's TSC; The offset that L1
3437 * set for L2 remains unchanged, and still needs to be added
3438 * to the newly set TSC to get L2's TSC.
3440 struct vmcs12 *vmcs12;
3441 /* recalculate vmcs02.TSC_OFFSET: */
3442 vmcs12 = get_vmcs12(vcpu);
3443 vmcs_write64(TSC_OFFSET, offset +
3444 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
3445 vmcs12->tsc_offset : 0));
3447 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
3448 vmcs_read64(TSC_OFFSET), offset);
3449 vmcs_write64(TSC_OFFSET, offset);
3454 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
3455 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
3456 * all guests if the "nested" module option is off, and can also be disabled
3457 * for a single guest by disabling its VMX cpuid bit.
3459 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
3461 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
3465 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
3466 * returned for the various VMX controls MSRs when nested VMX is enabled.
3467 * The same values should also be used to verify that vmcs12 control fields are
3468 * valid during nested entry from L1 to L2.
3469 * Each of these control msrs has a low and high 32-bit half: A low bit is on
3470 * if the corresponding bit in the (32-bit) control field *must* be on, and a
3471 * bit in the high half is on if the corresponding bit in the control field
3472 * may be on. See also vmx_control_verify().
3474 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
3477 memset(msrs, 0, sizeof(*msrs));
3482 * Note that as a general rule, the high half of the MSRs (bits in
3483 * the control fields which may be 1) should be initialized by the
3484 * intersection of the underlying hardware's MSR (i.e., features which
3485 * can be supported) and the list of features we want to expose -
3486 * because they are known to be properly supported in our code.
3487 * Also, usually, the low half of the MSRs (bits which must be 1) can
3488 * be set to 0, meaning that L1 may turn off any of these bits. The
3489 * reason is that if one of these bits is necessary, it will appear
3490 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
3491 * fields of vmcs01 and vmcs02, will turn these bits off - and
3492 * nested_vmx_exit_reflected() will not pass related exits to L1.
3493 * These rules have exceptions below.
3496 /* pin-based controls */
3497 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
3498 msrs->pinbased_ctls_low,
3499 msrs->pinbased_ctls_high);
3500 msrs->pinbased_ctls_low |=
3501 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3502 msrs->pinbased_ctls_high &=
3503 PIN_BASED_EXT_INTR_MASK |
3504 PIN_BASED_NMI_EXITING |
3505 PIN_BASED_VIRTUAL_NMIS |
3506 (apicv ? PIN_BASED_POSTED_INTR : 0);
3507 msrs->pinbased_ctls_high |=
3508 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3509 PIN_BASED_VMX_PREEMPTION_TIMER;
3512 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
3513 msrs->exit_ctls_low,
3514 msrs->exit_ctls_high);
3515 msrs->exit_ctls_low =
3516 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3518 msrs->exit_ctls_high &=
3519 #ifdef CONFIG_X86_64
3520 VM_EXIT_HOST_ADDR_SPACE_SIZE |
3522 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
3523 msrs->exit_ctls_high |=
3524 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
3525 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
3526 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
3528 /* We support free control of debug control saving. */
3529 msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
3531 /* entry controls */
3532 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
3533 msrs->entry_ctls_low,
3534 msrs->entry_ctls_high);
3535 msrs->entry_ctls_low =
3536 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3537 msrs->entry_ctls_high &=
3538 #ifdef CONFIG_X86_64
3539 VM_ENTRY_IA32E_MODE |
3541 VM_ENTRY_LOAD_IA32_PAT;
3542 msrs->entry_ctls_high |=
3543 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3545 /* We support free control of debug control loading. */
3546 msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3548 /* cpu-based controls */
3549 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3550 msrs->procbased_ctls_low,
3551 msrs->procbased_ctls_high);
3552 msrs->procbased_ctls_low =
3553 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3554 msrs->procbased_ctls_high &=
3555 CPU_BASED_VIRTUAL_INTR_PENDING |
3556 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3557 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3558 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3559 CPU_BASED_CR3_STORE_EXITING |
3560 #ifdef CONFIG_X86_64
3561 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3563 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3564 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3565 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3566 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3567 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3569 * We can allow some features even when not supported by the
3570 * hardware. For example, L1 can specify an MSR bitmap - and we
3571 * can use it to avoid exits to L1 - even when L0 runs L2
3572 * without MSR bitmaps.
3574 msrs->procbased_ctls_high |=
3575 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3576 CPU_BASED_USE_MSR_BITMAPS;
3578 /* We support free control of CR3 access interception. */
3579 msrs->procbased_ctls_low &=
3580 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3583 * secondary cpu-based controls. Do not include those that
3584 * depend on CPUID bits, they are added later by vmx_cpuid_update.
3586 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3587 msrs->secondary_ctls_low,
3588 msrs->secondary_ctls_high);
3589 msrs->secondary_ctls_low = 0;
3590 msrs->secondary_ctls_high &=
3591 SECONDARY_EXEC_DESC |
3592 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3593 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3594 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3595 SECONDARY_EXEC_WBINVD_EXITING;
3598 * We can emulate "VMCS shadowing," even if the hardware
3599 * doesn't support it.
3601 msrs->secondary_ctls_high |=
3602 SECONDARY_EXEC_SHADOW_VMCS;
3605 /* nested EPT: emulate EPT also to L1 */
3606 msrs->secondary_ctls_high |=
3607 SECONDARY_EXEC_ENABLE_EPT;
3608 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3609 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3610 if (cpu_has_vmx_ept_execute_only())
3612 VMX_EPT_EXECUTE_ONLY_BIT;
3613 msrs->ept_caps &= vmx_capability.ept;
3614 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3615 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3616 VMX_EPT_1GB_PAGE_BIT;
3617 if (enable_ept_ad_bits) {
3618 msrs->secondary_ctls_high |=
3619 SECONDARY_EXEC_ENABLE_PML;
3620 msrs->ept_caps |= VMX_EPT_AD_BIT;
3624 if (cpu_has_vmx_vmfunc()) {
3625 msrs->secondary_ctls_high |=
3626 SECONDARY_EXEC_ENABLE_VMFUNC;
3628 * Advertise EPTP switching unconditionally
3629 * since we emulate it
3632 msrs->vmfunc_controls =
3633 VMX_VMFUNC_EPTP_SWITCHING;
3637 * Old versions of KVM use the single-context version without
3638 * checking for support, so declare that it is supported even
3639 * though it is treated as global context. The alternative is
3640 * not failing the single-context invvpid, and it is worse.
3643 msrs->secondary_ctls_high |=
3644 SECONDARY_EXEC_ENABLE_VPID;
3645 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
3646 VMX_VPID_EXTENT_SUPPORTED_MASK;
3649 if (enable_unrestricted_guest)
3650 msrs->secondary_ctls_high |=
3651 SECONDARY_EXEC_UNRESTRICTED_GUEST;
3653 if (flexpriority_enabled)
3654 msrs->secondary_ctls_high |=
3655 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3657 /* miscellaneous data */
3658 rdmsr(MSR_IA32_VMX_MISC,
3661 msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
3663 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
3664 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3665 VMX_MISC_ACTIVITY_HLT;
3666 msrs->misc_high = 0;
3669 * This MSR reports some information about VMX support. We
3670 * should return information about the VMX we emulate for the
3671 * guest, and the VMCS structure we give it - not about the
3672 * VMX support of the underlying hardware.
3676 VMX_BASIC_TRUE_CTLS |
3677 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3678 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3680 if (cpu_has_vmx_basic_inout())
3681 msrs->basic |= VMX_BASIC_INOUT;
3684 * These MSRs specify bits which the guest must keep fixed on
3685 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3686 * We picked the standard core2 setting.
3688 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3689 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
3690 msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
3691 msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
3693 /* These MSRs specify bits which the guest must keep fixed off. */
3694 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
3695 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
3697 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3698 msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
3702 * if fixed0[i] == 1: val[i] must be 1
3703 * if fixed1[i] == 0: val[i] must be 0
3705 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3707 return ((val & fixed1) | fixed0) == val;
3710 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3712 return fixed_bits_valid(control, low, high);
3715 static inline u64 vmx_control_msr(u32 low, u32 high)
3717 return low | ((u64)high << 32);
3720 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3725 return (superset | subset) == superset;
3728 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3730 const u64 feature_and_reserved =
3731 /* feature (except bit 48; see below) */
3732 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3734 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3735 u64 vmx_basic = vmx->nested.msrs.basic;
3737 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3741 * KVM does not emulate a version of VMX that constrains physical
3742 * addresses of VMX structures (e.g. VMCS) to 32-bits.
3744 if (data & BIT_ULL(48))
3747 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3748 vmx_basic_vmcs_revision_id(data))
3751 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3754 vmx->nested.msrs.basic = data;
3759 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3764 switch (msr_index) {
3765 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3766 lowp = &vmx->nested.msrs.pinbased_ctls_low;
3767 highp = &vmx->nested.msrs.pinbased_ctls_high;
3769 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3770 lowp = &vmx->nested.msrs.procbased_ctls_low;
3771 highp = &vmx->nested.msrs.procbased_ctls_high;
3773 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3774 lowp = &vmx->nested.msrs.exit_ctls_low;
3775 highp = &vmx->nested.msrs.exit_ctls_high;
3777 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3778 lowp = &vmx->nested.msrs.entry_ctls_low;
3779 highp = &vmx->nested.msrs.entry_ctls_high;
3781 case MSR_IA32_VMX_PROCBASED_CTLS2:
3782 lowp = &vmx->nested.msrs.secondary_ctls_low;
3783 highp = &vmx->nested.msrs.secondary_ctls_high;
3789 supported = vmx_control_msr(*lowp, *highp);
3791 /* Check must-be-1 bits are still 1. */
3792 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3795 /* Check must-be-0 bits are still 0. */
3796 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3800 *highp = data >> 32;
3804 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3806 const u64 feature_and_reserved_bits =
3808 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3809 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3811 GENMASK_ULL(13, 9) | BIT_ULL(31);
3814 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
3815 vmx->nested.msrs.misc_high);
3817 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3820 if ((vmx->nested.msrs.pinbased_ctls_high &
3821 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3822 vmx_misc_preemption_timer_rate(data) !=
3823 vmx_misc_preemption_timer_rate(vmx_misc))
3826 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3829 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3832 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3835 vmx->nested.msrs.misc_low = data;
3836 vmx->nested.msrs.misc_high = data >> 32;
3839 * If L1 has read-only VM-exit information fields, use the
3840 * less permissive vmx_vmwrite_bitmap to specify write
3841 * permissions for the shadow VMCS.
3843 if (enable_shadow_vmcs && !nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
3844 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
3849 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3851 u64 vmx_ept_vpid_cap;
3853 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
3854 vmx->nested.msrs.vpid_caps);
3856 /* Every bit is either reserved or a feature bit. */
3857 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3860 vmx->nested.msrs.ept_caps = data;
3861 vmx->nested.msrs.vpid_caps = data >> 32;
3865 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3869 switch (msr_index) {
3870 case MSR_IA32_VMX_CR0_FIXED0:
3871 msr = &vmx->nested.msrs.cr0_fixed0;
3873 case MSR_IA32_VMX_CR4_FIXED0:
3874 msr = &vmx->nested.msrs.cr4_fixed0;
3881 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3882 * must be 1 in the restored value.
3884 if (!is_bitwise_subset(data, *msr, -1ULL))
3892 * Called when userspace is restoring VMX MSRs.
3894 * Returns 0 on success, non-0 otherwise.
3896 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3898 struct vcpu_vmx *vmx = to_vmx(vcpu);
3901 * Don't allow changes to the VMX capability MSRs while the vCPU
3902 * is in VMX operation.
3904 if (vmx->nested.vmxon)
3907 switch (msr_index) {
3908 case MSR_IA32_VMX_BASIC:
3909 return vmx_restore_vmx_basic(vmx, data);
3910 case MSR_IA32_VMX_PINBASED_CTLS:
3911 case MSR_IA32_VMX_PROCBASED_CTLS:
3912 case MSR_IA32_VMX_EXIT_CTLS:
3913 case MSR_IA32_VMX_ENTRY_CTLS:
3915 * The "non-true" VMX capability MSRs are generated from the
3916 * "true" MSRs, so we do not support restoring them directly.
3918 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3919 * should restore the "true" MSRs with the must-be-1 bits
3920 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3921 * DEFAULT SETTINGS".
3924 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3925 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3926 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3927 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3928 case MSR_IA32_VMX_PROCBASED_CTLS2:
3929 return vmx_restore_control_msr(vmx, msr_index, data);
3930 case MSR_IA32_VMX_MISC:
3931 return vmx_restore_vmx_misc(vmx, data);
3932 case MSR_IA32_VMX_CR0_FIXED0:
3933 case MSR_IA32_VMX_CR4_FIXED0:
3934 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3935 case MSR_IA32_VMX_CR0_FIXED1:
3936 case MSR_IA32_VMX_CR4_FIXED1:
3938 * These MSRs are generated based on the vCPU's CPUID, so we
3939 * do not support restoring them directly.
3942 case MSR_IA32_VMX_EPT_VPID_CAP:
3943 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3944 case MSR_IA32_VMX_VMCS_ENUM:
3945 vmx->nested.msrs.vmcs_enum = data;
3949 * The rest of the VMX capability MSRs do not support restore.
3955 /* Returns 0 on success, non-0 otherwise. */
3956 static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
3958 switch (msr_index) {
3959 case MSR_IA32_VMX_BASIC:
3960 *pdata = msrs->basic;
3962 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3963 case MSR_IA32_VMX_PINBASED_CTLS:
3964 *pdata = vmx_control_msr(
3965 msrs->pinbased_ctls_low,
3966 msrs->pinbased_ctls_high);
3967 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3968 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3970 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3971 case MSR_IA32_VMX_PROCBASED_CTLS:
3972 *pdata = vmx_control_msr(
3973 msrs->procbased_ctls_low,
3974 msrs->procbased_ctls_high);
3975 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3976 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3978 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3979 case MSR_IA32_VMX_EXIT_CTLS:
3980 *pdata = vmx_control_msr(
3981 msrs->exit_ctls_low,
3982 msrs->exit_ctls_high);
3983 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3984 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3986 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3987 case MSR_IA32_VMX_ENTRY_CTLS:
3988 *pdata = vmx_control_msr(
3989 msrs->entry_ctls_low,
3990 msrs->entry_ctls_high);
3991 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3992 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3994 case MSR_IA32_VMX_MISC:
3995 *pdata = vmx_control_msr(
3999 case MSR_IA32_VMX_CR0_FIXED0:
4000 *pdata = msrs->cr0_fixed0;
4002 case MSR_IA32_VMX_CR0_FIXED1:
4003 *pdata = msrs->cr0_fixed1;
4005 case MSR_IA32_VMX_CR4_FIXED0:
4006 *pdata = msrs->cr4_fixed0;
4008 case MSR_IA32_VMX_CR4_FIXED1:
4009 *pdata = msrs->cr4_fixed1;
4011 case MSR_IA32_VMX_VMCS_ENUM:
4012 *pdata = msrs->vmcs_enum;
4014 case MSR_IA32_VMX_PROCBASED_CTLS2:
4015 *pdata = vmx_control_msr(
4016 msrs->secondary_ctls_low,
4017 msrs->secondary_ctls_high);
4019 case MSR_IA32_VMX_EPT_VPID_CAP:
4020 *pdata = msrs->ept_caps |
4021 ((u64)msrs->vpid_caps << 32);
4023 case MSR_IA32_VMX_VMFUNC:
4024 *pdata = msrs->vmfunc_controls;
4033 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
4036 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
4038 return !(val & ~valid_bits);
4041 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
4043 switch (msr->index) {
4044 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4047 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
4056 * Reads an msr value (of 'msr_index') into 'pdata'.
4057 * Returns 0 on success, non-0 otherwise.
4058 * Assumes vcpu_load() was already called.
4060 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4062 struct vcpu_vmx *vmx = to_vmx(vcpu);
4063 struct shared_msr_entry *msr;
4065 switch (msr_info->index) {
4066 #ifdef CONFIG_X86_64
4068 msr_info->data = vmcs_readl(GUEST_FS_BASE);
4071 msr_info->data = vmcs_readl(GUEST_GS_BASE);
4073 case MSR_KERNEL_GS_BASE:
4074 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
4078 return kvm_get_msr_common(vcpu, msr_info);
4079 case MSR_IA32_SPEC_CTRL:
4080 if (!msr_info->host_initiated &&
4081 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4084 msr_info->data = to_vmx(vcpu)->spec_ctrl;
4086 case MSR_IA32_ARCH_CAPABILITIES:
4087 if (!msr_info->host_initiated &&
4088 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4090 msr_info->data = to_vmx(vcpu)->arch_capabilities;
4092 case MSR_IA32_SYSENTER_CS:
4093 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
4095 case MSR_IA32_SYSENTER_EIP:
4096 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
4098 case MSR_IA32_SYSENTER_ESP:
4099 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
4101 case MSR_IA32_BNDCFGS:
4102 if (!kvm_mpx_supported() ||
4103 (!msr_info->host_initiated &&
4104 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
4106 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
4108 case MSR_IA32_MCG_EXT_CTL:
4109 if (!msr_info->host_initiated &&
4110 !(vmx->msr_ia32_feature_control &
4111 FEATURE_CONTROL_LMCE))
4113 msr_info->data = vcpu->arch.mcg_ext_ctl;
4115 case MSR_IA32_FEATURE_CONTROL:
4116 msr_info->data = vmx->msr_ia32_feature_control;
4118 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4119 if (!nested_vmx_allowed(vcpu))
4121 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
4124 if (!vmx_xsaves_supported())
4126 msr_info->data = vcpu->arch.ia32_xss;
4129 if (!msr_info->host_initiated &&
4130 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4132 /* Otherwise falls through */
4134 msr = find_msr_entry(vmx, msr_info->index);
4136 msr_info->data = msr->data;
4139 return kvm_get_msr_common(vcpu, msr_info);
4145 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
4148 * Writes msr value into into the appropriate "register".
4149 * Returns 0 on success, non-0 otherwise.
4150 * Assumes vcpu_load() was already called.
4152 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4154 struct vcpu_vmx *vmx = to_vmx(vcpu);
4155 struct shared_msr_entry *msr;
4157 u32 msr_index = msr_info->index;
4158 u64 data = msr_info->data;
4160 switch (msr_index) {
4162 ret = kvm_set_msr_common(vcpu, msr_info);
4164 #ifdef CONFIG_X86_64
4166 vmx_segment_cache_clear(vmx);
4167 vmcs_writel(GUEST_FS_BASE, data);
4170 vmx_segment_cache_clear(vmx);
4171 vmcs_writel(GUEST_GS_BASE, data);
4173 case MSR_KERNEL_GS_BASE:
4174 vmx_write_guest_kernel_gs_base(vmx, data);
4177 case MSR_IA32_SYSENTER_CS:
4178 vmcs_write32(GUEST_SYSENTER_CS, data);
4180 case MSR_IA32_SYSENTER_EIP:
4181 vmcs_writel(GUEST_SYSENTER_EIP, data);
4183 case MSR_IA32_SYSENTER_ESP:
4184 vmcs_writel(GUEST_SYSENTER_ESP, data);
4186 case MSR_IA32_BNDCFGS:
4187 if (!kvm_mpx_supported() ||
4188 (!msr_info->host_initiated &&
4189 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
4191 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4192 (data & MSR_IA32_BNDCFGS_RSVD))
4194 vmcs_write64(GUEST_BNDCFGS, data);
4196 case MSR_IA32_SPEC_CTRL:
4197 if (!msr_info->host_initiated &&
4198 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4201 /* The STIBP bit doesn't fault even if it's not advertised */
4202 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4205 vmx->spec_ctrl = data;
4212 * When it's written (to non-zero) for the first time, pass
4216 * The handling of the MSR bitmap for L2 guests is done in
4217 * nested_vmx_merge_msr_bitmap. We should not touch the
4218 * vmcs02.msr_bitmap here since it gets completely overwritten
4219 * in the merging. We update the vmcs01 here for L1 as well
4220 * since it will end up touching the MSR anyway now.
4222 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
4226 case MSR_IA32_PRED_CMD:
4227 if (!msr_info->host_initiated &&
4228 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4231 if (data & ~PRED_CMD_IBPB)
4237 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4241 * When it's written (to non-zero) for the first time, pass
4245 * The handling of the MSR bitmap for L2 guests is done in
4246 * nested_vmx_merge_msr_bitmap. We should not touch the
4247 * vmcs02.msr_bitmap here since it gets completely overwritten
4250 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
4253 case MSR_IA32_ARCH_CAPABILITIES:
4254 if (!msr_info->host_initiated)
4256 vmx->arch_capabilities = data;
4258 case MSR_IA32_CR_PAT:
4259 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4260 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4262 vmcs_write64(GUEST_IA32_PAT, data);
4263 vcpu->arch.pat = data;
4266 ret = kvm_set_msr_common(vcpu, msr_info);
4268 case MSR_IA32_TSC_ADJUST:
4269 ret = kvm_set_msr_common(vcpu, msr_info);
4271 case MSR_IA32_MCG_EXT_CTL:
4272 if ((!msr_info->host_initiated &&
4273 !(to_vmx(vcpu)->msr_ia32_feature_control &
4274 FEATURE_CONTROL_LMCE)) ||
4275 (data & ~MCG_EXT_CTL_LMCE_EN))
4277 vcpu->arch.mcg_ext_ctl = data;
4279 case MSR_IA32_FEATURE_CONTROL:
4280 if (!vmx_feature_control_msr_valid(vcpu, data) ||
4281 (to_vmx(vcpu)->msr_ia32_feature_control &
4282 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
4284 vmx->msr_ia32_feature_control = data;
4285 if (msr_info->host_initiated && data == 0)
4286 vmx_leave_nested(vcpu);
4288 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4289 if (!msr_info->host_initiated)
4290 return 1; /* they are read-only */
4291 if (!nested_vmx_allowed(vcpu))
4293 return vmx_set_vmx_msr(vcpu, msr_index, data);
4295 if (!vmx_xsaves_supported())
4298 * The only supported bit as of Skylake is bit 8, but
4299 * it is not supported on KVM.
4303 vcpu->arch.ia32_xss = data;
4304 if (vcpu->arch.ia32_xss != host_xss)
4305 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
4306 vcpu->arch.ia32_xss, host_xss, false);
4308 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
4311 if (!msr_info->host_initiated &&
4312 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4314 /* Check reserved bit, higher 32 bits should be zero */
4315 if ((data >> 32) != 0)
4317 /* Otherwise falls through */
4319 msr = find_msr_entry(vmx, msr_index);
4321 u64 old_msr_data = msr->data;
4323 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
4325 ret = kvm_set_shared_msr(msr->index, msr->data,
4329 msr->data = old_msr_data;
4333 ret = kvm_set_msr_common(vcpu, msr_info);
4339 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
4341 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
4344 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
4347 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
4349 case VCPU_EXREG_PDPTR:
4351 ept_save_pdptrs(vcpu);
4358 static __init int cpu_has_kvm_support(void)
4360 return cpu_has_vmx();
4363 static __init int vmx_disabled_by_bios(void)
4367 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
4368 if (msr & FEATURE_CONTROL_LOCKED) {
4369 /* launched w/ TXT and VMX disabled */
4370 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4373 /* launched w/o TXT and VMX only enabled w/ TXT */
4374 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4375 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4376 && !tboot_enabled()) {
4377 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
4378 "activate TXT before enabling KVM\n");
4381 /* launched w/o TXT and VMX disabled */
4382 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4383 && !tboot_enabled())
4390 static void kvm_cpu_vmxon(u64 addr)
4392 cr4_set_bits(X86_CR4_VMXE);
4393 intel_pt_handle_vmx(1);
4395 asm volatile (ASM_VMX_VMXON_RAX
4396 : : "a"(&addr), "m"(addr)
4400 static int hardware_enable(void)
4402 int cpu = raw_smp_processor_id();
4403 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
4406 if (cr4_read_shadow() & X86_CR4_VMXE)
4410 * This can happen if we hot-added a CPU but failed to allocate
4411 * VP assist page for it.
4413 if (static_branch_unlikely(&enable_evmcs) &&
4414 !hv_get_vp_assist_page(cpu))
4417 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
4418 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
4419 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
4422 * Now we can enable the vmclear operation in kdump
4423 * since the loaded_vmcss_on_cpu list on this cpu
4424 * has been initialized.
4426 * Though the cpu is not in VMX operation now, there
4427 * is no problem to enable the vmclear operation
4428 * for the loaded_vmcss_on_cpu list is empty!
4430 crash_enable_local_vmclear(cpu);
4432 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
4434 test_bits = FEATURE_CONTROL_LOCKED;
4435 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4436 if (tboot_enabled())
4437 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
4439 if ((old & test_bits) != test_bits) {
4440 /* enable and lock */
4441 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
4443 kvm_cpu_vmxon(phys_addr);
4450 static void vmclear_local_loaded_vmcss(void)
4452 int cpu = raw_smp_processor_id();
4453 struct loaded_vmcs *v, *n;
4455 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
4456 loaded_vmcss_on_cpu_link)
4457 __loaded_vmcs_clear(v);
4461 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
4464 static void kvm_cpu_vmxoff(void)
4466 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
4468 intel_pt_handle_vmx(0);
4469 cr4_clear_bits(X86_CR4_VMXE);
4472 static void hardware_disable(void)
4474 vmclear_local_loaded_vmcss();
4478 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
4479 u32 msr, u32 *result)
4481 u32 vmx_msr_low, vmx_msr_high;
4482 u32 ctl = ctl_min | ctl_opt;
4484 rdmsr(msr, vmx_msr_low, vmx_msr_high);
4486 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
4487 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
4489 /* Ensure minimum (required) set of control bits are supported. */
4497 static __init bool allow_1_setting(u32 msr, u32 ctl)
4499 u32 vmx_msr_low, vmx_msr_high;
4501 rdmsr(msr, vmx_msr_low, vmx_msr_high);
4502 return vmx_msr_high & ctl;
4505 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
4507 u32 vmx_msr_low, vmx_msr_high;
4508 u32 min, opt, min2, opt2;
4509 u32 _pin_based_exec_control = 0;
4510 u32 _cpu_based_exec_control = 0;
4511 u32 _cpu_based_2nd_exec_control = 0;
4512 u32 _vmexit_control = 0;
4513 u32 _vmentry_control = 0;
4515 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
4516 min = CPU_BASED_HLT_EXITING |
4517 #ifdef CONFIG_X86_64
4518 CPU_BASED_CR8_LOAD_EXITING |
4519 CPU_BASED_CR8_STORE_EXITING |
4521 CPU_BASED_CR3_LOAD_EXITING |
4522 CPU_BASED_CR3_STORE_EXITING |
4523 CPU_BASED_UNCOND_IO_EXITING |
4524 CPU_BASED_MOV_DR_EXITING |
4525 CPU_BASED_USE_TSC_OFFSETING |
4526 CPU_BASED_MWAIT_EXITING |
4527 CPU_BASED_MONITOR_EXITING |
4528 CPU_BASED_INVLPG_EXITING |
4529 CPU_BASED_RDPMC_EXITING;
4531 opt = CPU_BASED_TPR_SHADOW |
4532 CPU_BASED_USE_MSR_BITMAPS |
4533 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
4534 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
4535 &_cpu_based_exec_control) < 0)
4537 #ifdef CONFIG_X86_64
4538 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4539 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
4540 ~CPU_BASED_CR8_STORE_EXITING;
4542 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
4544 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4545 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4546 SECONDARY_EXEC_WBINVD_EXITING |
4547 SECONDARY_EXEC_ENABLE_VPID |
4548 SECONDARY_EXEC_ENABLE_EPT |
4549 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4550 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
4551 SECONDARY_EXEC_DESC |
4552 SECONDARY_EXEC_RDTSCP |
4553 SECONDARY_EXEC_ENABLE_INVPCID |
4554 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4555 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4556 SECONDARY_EXEC_SHADOW_VMCS |
4557 SECONDARY_EXEC_XSAVES |
4558 SECONDARY_EXEC_RDSEED_EXITING |
4559 SECONDARY_EXEC_RDRAND_EXITING |
4560 SECONDARY_EXEC_ENABLE_PML |
4561 SECONDARY_EXEC_TSC_SCALING |
4562 SECONDARY_EXEC_ENABLE_VMFUNC |
4563 SECONDARY_EXEC_ENCLS_EXITING;
4564 if (adjust_vmx_controls(min2, opt2,
4565 MSR_IA32_VMX_PROCBASED_CTLS2,
4566 &_cpu_based_2nd_exec_control) < 0)
4569 #ifndef CONFIG_X86_64
4570 if (!(_cpu_based_2nd_exec_control &
4571 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
4572 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
4575 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4576 _cpu_based_2nd_exec_control &= ~(
4577 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4578 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4579 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4581 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
4582 &vmx_capability.ept, &vmx_capability.vpid);
4584 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
4585 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4587 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
4588 CPU_BASED_CR3_STORE_EXITING |
4589 CPU_BASED_INVLPG_EXITING);
4590 } else if (vmx_capability.ept) {
4591 vmx_capability.ept = 0;
4592 pr_warn_once("EPT CAP should not exist if not support "
4593 "1-setting enable EPT VM-execution control\n");
4595 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
4596 vmx_capability.vpid) {
4597 vmx_capability.vpid = 0;
4598 pr_warn_once("VPID CAP should not exist if not support "
4599 "1-setting enable VPID VM-execution control\n");
4602 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4603 #ifdef CONFIG_X86_64
4604 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4606 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4607 VM_EXIT_CLEAR_BNDCFGS;
4608 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4609 &_vmexit_control) < 0)
4612 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4613 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4614 PIN_BASED_VMX_PREEMPTION_TIMER;
4615 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4616 &_pin_based_exec_control) < 0)
4619 if (cpu_has_broken_vmx_preemption_timer())
4620 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4621 if (!(_cpu_based_2nd_exec_control &
4622 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4623 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4625 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4626 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4627 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4628 &_vmentry_control) < 0)
4631 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4633 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4634 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4637 #ifdef CONFIG_X86_64
4638 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4639 if (vmx_msr_high & (1u<<16))
4643 /* Require Write-Back (WB) memory type for VMCS accesses. */
4644 if (((vmx_msr_high >> 18) & 15) != 6)
4647 vmcs_conf->size = vmx_msr_high & 0x1fff;
4648 vmcs_conf->order = get_order(vmcs_conf->size);
4649 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4651 vmcs_conf->revision_id = vmx_msr_low;
4653 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4654 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4655 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4656 vmcs_conf->vmexit_ctrl = _vmexit_control;
4657 vmcs_conf->vmentry_ctrl = _vmentry_control;
4659 if (static_branch_unlikely(&enable_evmcs))
4660 evmcs_sanitize_exec_ctrls(vmcs_conf);
4662 cpu_has_load_ia32_efer =
4663 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4664 VM_ENTRY_LOAD_IA32_EFER)
4665 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4666 VM_EXIT_LOAD_IA32_EFER);
4668 cpu_has_load_perf_global_ctrl =
4669 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4670 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4671 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4672 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4675 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4676 * but due to errata below it can't be used. Workaround is to use
4677 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4679 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4684 * BC86,AAY89,BD102 (model 44)
4688 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4689 switch (boot_cpu_data.x86_model) {
4695 cpu_has_load_perf_global_ctrl = false;
4696 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4697 "does not work properly. Using workaround\n");
4704 if (boot_cpu_has(X86_FEATURE_XSAVES))
4705 rdmsrl(MSR_IA32_XSS, host_xss);
4710 static struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu)
4712 int node = cpu_to_node(cpu);
4716 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4719 vmcs = page_address(pages);
4720 memset(vmcs, 0, vmcs_config.size);
4722 /* KVM supports Enlightened VMCS v1 only */
4723 if (static_branch_unlikely(&enable_evmcs))
4724 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
4726 vmcs->hdr.revision_id = vmcs_config.revision_id;
4729 vmcs->hdr.shadow_vmcs = 1;
4733 static void free_vmcs(struct vmcs *vmcs)
4735 free_pages((unsigned long)vmcs, vmcs_config.order);
4739 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4741 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4743 if (!loaded_vmcs->vmcs)
4745 loaded_vmcs_clear(loaded_vmcs);
4746 free_vmcs(loaded_vmcs->vmcs);
4747 loaded_vmcs->vmcs = NULL;
4748 if (loaded_vmcs->msr_bitmap)
4749 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4750 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4753 static struct vmcs *alloc_vmcs(bool shadow)
4755 return alloc_vmcs_cpu(shadow, raw_smp_processor_id());
4758 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4760 loaded_vmcs->vmcs = alloc_vmcs(false);
4761 if (!loaded_vmcs->vmcs)
4764 loaded_vmcs->shadow_vmcs = NULL;
4765 loaded_vmcs_init(loaded_vmcs);
4767 if (cpu_has_vmx_msr_bitmap()) {
4768 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4769 if (!loaded_vmcs->msr_bitmap)
4771 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4773 if (IS_ENABLED(CONFIG_HYPERV) &&
4774 static_branch_unlikely(&enable_evmcs) &&
4775 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
4776 struct hv_enlightened_vmcs *evmcs =
4777 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
4779 evmcs->hv_enlightenments_control.msr_bitmap = 1;
4783 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
4788 free_loaded_vmcs(loaded_vmcs);
4792 static void free_kvm_area(void)
4796 for_each_possible_cpu(cpu) {
4797 free_vmcs(per_cpu(vmxarea, cpu));
4798 per_cpu(vmxarea, cpu) = NULL;
4802 enum vmcs_field_width {
4803 VMCS_FIELD_WIDTH_U16 = 0,
4804 VMCS_FIELD_WIDTH_U64 = 1,
4805 VMCS_FIELD_WIDTH_U32 = 2,
4806 VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
4809 static inline int vmcs_field_width(unsigned long field)
4811 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
4812 return VMCS_FIELD_WIDTH_U32;
4813 return (field >> 13) & 0x3 ;
4816 static inline int vmcs_field_readonly(unsigned long field)
4818 return (((field >> 10) & 0x3) == 1);
4821 static void init_vmcs_shadow_fields(void)
4825 for (i = j = 0; i < max_shadow_read_only_fields; i++) {
4826 u16 field = shadow_read_only_fields[i];
4827 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4828 (i + 1 == max_shadow_read_only_fields ||
4829 shadow_read_only_fields[i + 1] != field + 1))
4830 pr_err("Missing field from shadow_read_only_field %x\n",
4833 clear_bit(field, vmx_vmread_bitmap);
4834 #ifdef CONFIG_X86_64
4839 shadow_read_only_fields[j] = field;
4842 max_shadow_read_only_fields = j;
4844 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4845 u16 field = shadow_read_write_fields[i];
4846 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4847 (i + 1 == max_shadow_read_write_fields ||
4848 shadow_read_write_fields[i + 1] != field + 1))
4849 pr_err("Missing field from shadow_read_write_field %x\n",
4853 * PML and the preemption timer can be emulated, but the
4854 * processor cannot vmwrite to fields that don't exist
4858 case GUEST_PML_INDEX:
4859 if (!cpu_has_vmx_pml())
4862 case VMX_PREEMPTION_TIMER_VALUE:
4863 if (!cpu_has_vmx_preemption_timer())
4866 case GUEST_INTR_STATUS:
4867 if (!cpu_has_vmx_apicv())
4874 clear_bit(field, vmx_vmwrite_bitmap);
4875 clear_bit(field, vmx_vmread_bitmap);
4876 #ifdef CONFIG_X86_64
4881 shadow_read_write_fields[j] = field;
4884 max_shadow_read_write_fields = j;
4887 static __init int alloc_kvm_area(void)
4891 for_each_possible_cpu(cpu) {
4894 vmcs = alloc_vmcs_cpu(false, cpu);
4901 * When eVMCS is enabled, alloc_vmcs_cpu() sets
4902 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
4903 * revision_id reported by MSR_IA32_VMX_BASIC.
4905 * However, even though not explictly documented by
4906 * TLFS, VMXArea passed as VMXON argument should
4907 * still be marked with revision_id reported by
4910 if (static_branch_unlikely(&enable_evmcs))
4911 vmcs->hdr.revision_id = vmcs_config.revision_id;
4913 per_cpu(vmxarea, cpu) = vmcs;
4918 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4919 struct kvm_segment *save)
4921 if (!emulate_invalid_guest_state) {
4923 * CS and SS RPL should be equal during guest entry according
4924 * to VMX spec, but in reality it is not always so. Since vcpu
4925 * is in the middle of the transition from real mode to
4926 * protected mode it is safe to assume that RPL 0 is a good
4929 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4930 save->selector &= ~SEGMENT_RPL_MASK;
4931 save->dpl = save->selector & SEGMENT_RPL_MASK;
4934 vmx_set_segment(vcpu, save, seg);
4937 static void enter_pmode(struct kvm_vcpu *vcpu)
4939 unsigned long flags;
4940 struct vcpu_vmx *vmx = to_vmx(vcpu);
4943 * Update real mode segment cache. It may be not up-to-date if sement
4944 * register was written while vcpu was in a guest mode.
4946 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4947 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4948 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4949 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4950 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4951 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4953 vmx->rmode.vm86_active = 0;
4955 vmx_segment_cache_clear(vmx);
4957 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4959 flags = vmcs_readl(GUEST_RFLAGS);
4960 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4961 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4962 vmcs_writel(GUEST_RFLAGS, flags);
4964 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4965 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4967 update_exception_bitmap(vcpu);
4969 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4970 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4971 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4972 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4973 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4974 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4977 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4979 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4980 struct kvm_segment var = *save;
4983 if (seg == VCPU_SREG_CS)
4986 if (!emulate_invalid_guest_state) {
4987 var.selector = var.base >> 4;
4988 var.base = var.base & 0xffff0;
4998 if (save->base & 0xf)
4999 printk_once(KERN_WARNING "kvm: segment base is not "
5000 "paragraph aligned when entering "
5001 "protected mode (seg=%d)", seg);
5004 vmcs_write16(sf->selector, var.selector);
5005 vmcs_writel(sf->base, var.base);
5006 vmcs_write32(sf->limit, var.limit);
5007 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
5010 static void enter_rmode(struct kvm_vcpu *vcpu)
5012 unsigned long flags;
5013 struct vcpu_vmx *vmx = to_vmx(vcpu);
5014 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
5016 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
5017 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
5018 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
5019 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
5020 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
5021 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
5022 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
5024 vmx->rmode.vm86_active = 1;
5027 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
5028 * vcpu. Warn the user that an update is overdue.
5030 if (!kvm_vmx->tss_addr)
5031 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
5032 "called before entering vcpu\n");
5034 vmx_segment_cache_clear(vmx);
5036 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
5037 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
5038 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5040 flags = vmcs_readl(GUEST_RFLAGS);
5041 vmx->rmode.save_rflags = flags;
5043 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
5045 vmcs_writel(GUEST_RFLAGS, flags);
5046 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
5047 update_exception_bitmap(vcpu);
5049 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
5050 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
5051 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
5052 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
5053 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
5054 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
5056 kvm_mmu_reset_context(vcpu);
5059 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
5061 struct vcpu_vmx *vmx = to_vmx(vcpu);
5062 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
5067 vcpu->arch.efer = efer;
5068 if (efer & EFER_LMA) {
5069 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5072 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5074 msr->data = efer & ~EFER_LME;
5079 #ifdef CONFIG_X86_64
5081 static void enter_lmode(struct kvm_vcpu *vcpu)
5085 vmx_segment_cache_clear(to_vmx(vcpu));
5087 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
5088 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
5089 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
5091 vmcs_write32(GUEST_TR_AR_BYTES,
5092 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
5093 | VMX_AR_TYPE_BUSY_64_TSS);
5095 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
5098 static void exit_lmode(struct kvm_vcpu *vcpu)
5100 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5101 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
5106 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
5107 bool invalidate_gpa)
5109 if (enable_ept && (invalidate_gpa || !enable_vpid)) {
5110 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
5112 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
5114 vpid_sync_context(vpid);
5118 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5120 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
5123 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
5125 int vpid = to_vmx(vcpu)->vpid;
5127 if (!vpid_sync_vcpu_addr(vpid, addr))
5128 vpid_sync_context(vpid);
5131 * If VPIDs are not supported or enabled, then the above is a no-op.
5132 * But we don't really need a TLB flush in that case anyway, because
5133 * each VM entry/exit includes an implicit flush when VPID is 0.
5137 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
5139 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
5141 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
5142 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
5145 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
5147 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
5148 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
5149 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5152 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
5154 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
5156 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
5157 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
5160 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
5162 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
5164 if (!test_bit(VCPU_EXREG_PDPTR,
5165 (unsigned long *)&vcpu->arch.regs_dirty))
5168 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
5169 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
5170 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
5171 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
5172 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
5176 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
5178 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
5180 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
5181 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
5182 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
5183 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
5184 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
5187 __set_bit(VCPU_EXREG_PDPTR,
5188 (unsigned long *)&vcpu->arch.regs_avail);
5189 __set_bit(VCPU_EXREG_PDPTR,
5190 (unsigned long *)&vcpu->arch.regs_dirty);
5193 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5195 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
5196 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
5197 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5199 if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
5200 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5201 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5202 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5204 return fixed_bits_valid(val, fixed0, fixed1);
5207 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5209 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
5210 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
5212 return fixed_bits_valid(val, fixed0, fixed1);
5215 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
5217 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
5218 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
5220 return fixed_bits_valid(val, fixed0, fixed1);
5223 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
5224 #define nested_guest_cr4_valid nested_cr4_valid
5225 #define nested_host_cr4_valid nested_cr4_valid
5227 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
5229 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
5231 struct kvm_vcpu *vcpu)
5233 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
5234 vmx_decache_cr3(vcpu);
5235 if (!(cr0 & X86_CR0_PG)) {
5236 /* From paging/starting to nonpaging */
5237 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
5238 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
5239 (CPU_BASED_CR3_LOAD_EXITING |
5240 CPU_BASED_CR3_STORE_EXITING));
5241 vcpu->arch.cr0 = cr0;
5242 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
5243 } else if (!is_paging(vcpu)) {
5244 /* From nonpaging to paging */
5245 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
5246 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
5247 ~(CPU_BASED_CR3_LOAD_EXITING |
5248 CPU_BASED_CR3_STORE_EXITING));
5249 vcpu->arch.cr0 = cr0;
5250 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
5253 if (!(cr0 & X86_CR0_WP))
5254 *hw_cr0 &= ~X86_CR0_WP;
5257 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
5259 struct vcpu_vmx *vmx = to_vmx(vcpu);
5260 unsigned long hw_cr0;
5262 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
5263 if (enable_unrestricted_guest)
5264 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
5266 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
5268 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
5271 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
5275 #ifdef CONFIG_X86_64
5276 if (vcpu->arch.efer & EFER_LME) {
5277 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
5279 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
5284 if (enable_ept && !enable_unrestricted_guest)
5285 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
5287 vmcs_writel(CR0_READ_SHADOW, cr0);
5288 vmcs_writel(GUEST_CR0, hw_cr0);
5289 vcpu->arch.cr0 = cr0;
5291 /* depends on vcpu->arch.cr0 to be set to a new value */
5292 vmx->emulation_required = emulation_required(vcpu);
5295 static int get_ept_level(struct kvm_vcpu *vcpu)
5297 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
5302 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
5304 u64 eptp = VMX_EPTP_MT_WB;
5306 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
5308 if (enable_ept_ad_bits &&
5309 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
5310 eptp |= VMX_EPTP_AD_ENABLE_BIT;
5311 eptp |= (root_hpa & PAGE_MASK);
5316 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
5318 struct kvm *kvm = vcpu->kvm;
5319 unsigned long guest_cr3;
5324 eptp = construct_eptp(vcpu, cr3);
5325 vmcs_write64(EPT_POINTER, eptp);
5327 if (kvm_x86_ops->tlb_remote_flush) {
5328 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
5329 to_vmx(vcpu)->ept_pointer = eptp;
5330 to_kvm_vmx(kvm)->ept_pointers_match
5331 = EPT_POINTERS_CHECK;
5332 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
5335 if (enable_unrestricted_guest || is_paging(vcpu) ||
5336 is_guest_mode(vcpu))
5337 guest_cr3 = kvm_read_cr3(vcpu);
5339 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
5340 ept_load_pdptrs(vcpu);
5343 vmcs_writel(GUEST_CR3, guest_cr3);
5346 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
5349 * Pass through host's Machine Check Enable value to hw_cr4, which
5350 * is in force while we are in guest mode. Do not let guests control
5351 * this bit, even if host CR4.MCE == 0.
5353 unsigned long hw_cr4;
5355 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
5356 if (enable_unrestricted_guest)
5357 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
5358 else if (to_vmx(vcpu)->rmode.vm86_active)
5359 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
5361 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
5363 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
5364 if (cr4 & X86_CR4_UMIP) {
5365 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5366 SECONDARY_EXEC_DESC);
5367 hw_cr4 &= ~X86_CR4_UMIP;
5368 } else if (!is_guest_mode(vcpu) ||
5369 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
5370 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5371 SECONDARY_EXEC_DESC);
5374 if (cr4 & X86_CR4_VMXE) {
5376 * To use VMXON (and later other VMX instructions), a guest
5377 * must first be able to turn on cr4.VMXE (see handle_vmon()).
5378 * So basically the check on whether to allow nested VMX
5379 * is here. We operate under the default treatment of SMM,
5380 * so VMX cannot be enabled under SMM.
5382 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5386 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5389 vcpu->arch.cr4 = cr4;
5391 if (!enable_unrestricted_guest) {
5393 if (!is_paging(vcpu)) {
5394 hw_cr4 &= ~X86_CR4_PAE;
5395 hw_cr4 |= X86_CR4_PSE;
5396 } else if (!(cr4 & X86_CR4_PAE)) {
5397 hw_cr4 &= ~X86_CR4_PAE;
5402 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
5403 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
5404 * to be manually disabled when guest switches to non-paging
5407 * If !enable_unrestricted_guest, the CPU is always running
5408 * with CR0.PG=1 and CR4 needs to be modified.
5409 * If enable_unrestricted_guest, the CPU automatically
5410 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
5412 if (!is_paging(vcpu))
5413 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
5416 vmcs_writel(CR4_READ_SHADOW, cr4);
5417 vmcs_writel(GUEST_CR4, hw_cr4);
5421 static void vmx_get_segment(struct kvm_vcpu *vcpu,
5422 struct kvm_segment *var, int seg)
5424 struct vcpu_vmx *vmx = to_vmx(vcpu);
5427 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5428 *var = vmx->rmode.segs[seg];
5429 if (seg == VCPU_SREG_TR
5430 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
5432 var->base = vmx_read_guest_seg_base(vmx, seg);
5433 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5436 var->base = vmx_read_guest_seg_base(vmx, seg);
5437 var->limit = vmx_read_guest_seg_limit(vmx, seg);
5438 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5439 ar = vmx_read_guest_seg_ar(vmx, seg);
5440 var->unusable = (ar >> 16) & 1;
5441 var->type = ar & 15;
5442 var->s = (ar >> 4) & 1;
5443 var->dpl = (ar >> 5) & 3;
5445 * Some userspaces do not preserve unusable property. Since usable
5446 * segment has to be present according to VMX spec we can use present
5447 * property to amend userspace bug by making unusable segment always
5448 * nonpresent. vmx_segment_access_rights() already marks nonpresent
5449 * segment as unusable.
5451 var->present = !var->unusable;
5452 var->avl = (ar >> 12) & 1;
5453 var->l = (ar >> 13) & 1;
5454 var->db = (ar >> 14) & 1;
5455 var->g = (ar >> 15) & 1;
5458 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
5460 struct kvm_segment s;
5462 if (to_vmx(vcpu)->rmode.vm86_active) {
5463 vmx_get_segment(vcpu, &s, seg);
5466 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
5469 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
5471 struct vcpu_vmx *vmx = to_vmx(vcpu);
5473 if (unlikely(vmx->rmode.vm86_active))
5476 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
5477 return VMX_AR_DPL(ar);
5481 static u32 vmx_segment_access_rights(struct kvm_segment *var)
5485 if (var->unusable || !var->present)
5488 ar = var->type & 15;
5489 ar |= (var->s & 1) << 4;
5490 ar |= (var->dpl & 3) << 5;
5491 ar |= (var->present & 1) << 7;
5492 ar |= (var->avl & 1) << 12;
5493 ar |= (var->l & 1) << 13;
5494 ar |= (var->db & 1) << 14;
5495 ar |= (var->g & 1) << 15;
5501 static void vmx_set_segment(struct kvm_vcpu *vcpu,
5502 struct kvm_segment *var, int seg)
5504 struct vcpu_vmx *vmx = to_vmx(vcpu);
5505 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5507 vmx_segment_cache_clear(vmx);
5509 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5510 vmx->rmode.segs[seg] = *var;
5511 if (seg == VCPU_SREG_TR)
5512 vmcs_write16(sf->selector, var->selector);
5514 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
5518 vmcs_writel(sf->base, var->base);
5519 vmcs_write32(sf->limit, var->limit);
5520 vmcs_write16(sf->selector, var->selector);
5523 * Fix the "Accessed" bit in AR field of segment registers for older
5525 * IA32 arch specifies that at the time of processor reset the
5526 * "Accessed" bit in the AR field of segment registers is 1. And qemu
5527 * is setting it to 0 in the userland code. This causes invalid guest
5528 * state vmexit when "unrestricted guest" mode is turned on.
5529 * Fix for this setup issue in cpu_reset is being pushed in the qemu
5530 * tree. Newer qemu binaries with that qemu fix would not need this
5533 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
5534 var->type |= 0x1; /* Accessed */
5536 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
5539 vmx->emulation_required = emulation_required(vcpu);
5542 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5544 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
5546 *db = (ar >> 14) & 1;
5547 *l = (ar >> 13) & 1;
5550 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5552 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
5553 dt->address = vmcs_readl(GUEST_IDTR_BASE);
5556 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5558 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
5559 vmcs_writel(GUEST_IDTR_BASE, dt->address);
5562 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5564 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
5565 dt->address = vmcs_readl(GUEST_GDTR_BASE);
5568 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5570 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
5571 vmcs_writel(GUEST_GDTR_BASE, dt->address);
5574 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
5576 struct kvm_segment var;
5579 vmx_get_segment(vcpu, &var, seg);
5581 if (seg == VCPU_SREG_CS)
5583 ar = vmx_segment_access_rights(&var);
5585 if (var.base != (var.selector << 4))
5587 if (var.limit != 0xffff)
5595 static bool code_segment_valid(struct kvm_vcpu *vcpu)
5597 struct kvm_segment cs;
5598 unsigned int cs_rpl;
5600 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5601 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
5605 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
5609 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
5610 if (cs.dpl > cs_rpl)
5613 if (cs.dpl != cs_rpl)
5619 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5623 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
5625 struct kvm_segment ss;
5626 unsigned int ss_rpl;
5628 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5629 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
5633 if (ss.type != 3 && ss.type != 7)
5637 if (ss.dpl != ss_rpl) /* DPL != RPL */
5645 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
5647 struct kvm_segment var;
5650 vmx_get_segment(vcpu, &var, seg);
5651 rpl = var.selector & SEGMENT_RPL_MASK;
5659 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
5660 if (var.dpl < rpl) /* DPL < RPL */
5664 /* TODO: Add other members to kvm_segment_field to allow checking for other access
5670 static bool tr_valid(struct kvm_vcpu *vcpu)
5672 struct kvm_segment tr;
5674 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
5678 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
5680 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
5688 static bool ldtr_valid(struct kvm_vcpu *vcpu)
5690 struct kvm_segment ldtr;
5692 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
5696 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
5706 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5708 struct kvm_segment cs, ss;
5710 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5711 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5713 return ((cs.selector & SEGMENT_RPL_MASK) ==
5714 (ss.selector & SEGMENT_RPL_MASK));
5718 * Check if guest state is valid. Returns true if valid, false if
5720 * We assume that registers are always usable
5722 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5724 if (enable_unrestricted_guest)
5727 /* real mode guest state checks */
5728 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5729 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5731 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5733 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5735 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5737 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5739 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5742 /* protected mode guest state checks */
5743 if (!cs_ss_rpl_check(vcpu))
5745 if (!code_segment_valid(vcpu))
5747 if (!stack_segment_valid(vcpu))
5749 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5751 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5753 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5755 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5757 if (!tr_valid(vcpu))
5759 if (!ldtr_valid(vcpu))
5763 * - Add checks on RIP
5764 * - Add checks on RFLAGS
5770 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5772 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5775 static int init_rmode_tss(struct kvm *kvm)
5781 idx = srcu_read_lock(&kvm->srcu);
5782 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
5783 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5786 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5787 r = kvm_write_guest_page(kvm, fn++, &data,
5788 TSS_IOPB_BASE_OFFSET, sizeof(u16));
5791 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5794 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5798 r = kvm_write_guest_page(kvm, fn, &data,
5799 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5802 srcu_read_unlock(&kvm->srcu, idx);
5806 static int init_rmode_identity_map(struct kvm *kvm)
5808 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
5810 kvm_pfn_t identity_map_pfn;
5813 /* Protect kvm_vmx->ept_identity_pagetable_done. */
5814 mutex_lock(&kvm->slots_lock);
5816 if (likely(kvm_vmx->ept_identity_pagetable_done))
5819 if (!kvm_vmx->ept_identity_map_addr)
5820 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5821 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
5823 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5824 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
5828 idx = srcu_read_lock(&kvm->srcu);
5829 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5832 /* Set up identity-mapping pagetable for EPT in real mode */
5833 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5834 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5835 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5836 r = kvm_write_guest_page(kvm, identity_map_pfn,
5837 &tmp, i * sizeof(tmp), sizeof(tmp));
5841 kvm_vmx->ept_identity_pagetable_done = true;
5844 srcu_read_unlock(&kvm->srcu, idx);
5847 mutex_unlock(&kvm->slots_lock);
5851 static void seg_setup(int seg)
5853 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5856 vmcs_write16(sf->selector, 0);
5857 vmcs_writel(sf->base, 0);
5858 vmcs_write32(sf->limit, 0xffff);
5860 if (seg == VCPU_SREG_CS)
5861 ar |= 0x08; /* code segment */
5863 vmcs_write32(sf->ar_bytes, ar);
5866 static int alloc_apic_access_page(struct kvm *kvm)
5871 mutex_lock(&kvm->slots_lock);
5872 if (kvm->arch.apic_access_page_done)
5874 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5875 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5879 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5880 if (is_error_page(page)) {
5886 * Do not pin the page in memory, so that memory hot-unplug
5887 * is able to migrate it.
5890 kvm->arch.apic_access_page_done = true;
5892 mutex_unlock(&kvm->slots_lock);
5896 static int allocate_vpid(void)
5902 spin_lock(&vmx_vpid_lock);
5903 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5904 if (vpid < VMX_NR_VPIDS)
5905 __set_bit(vpid, vmx_vpid_bitmap);
5908 spin_unlock(&vmx_vpid_lock);
5912 static void free_vpid(int vpid)
5914 if (!enable_vpid || vpid == 0)
5916 spin_lock(&vmx_vpid_lock);
5917 __clear_bit(vpid, vmx_vpid_bitmap);
5918 spin_unlock(&vmx_vpid_lock);
5921 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5924 int f = sizeof(unsigned long);
5926 if (!cpu_has_vmx_msr_bitmap())
5929 if (static_branch_unlikely(&enable_evmcs))
5930 evmcs_touch_msr_bitmap();
5933 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5934 * have the write-low and read-high bitmap offsets the wrong way round.
5935 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5937 if (msr <= 0x1fff) {
5938 if (type & MSR_TYPE_R)
5940 __clear_bit(msr, msr_bitmap + 0x000 / f);
5942 if (type & MSR_TYPE_W)
5944 __clear_bit(msr, msr_bitmap + 0x800 / f);
5946 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5948 if (type & MSR_TYPE_R)
5950 __clear_bit(msr, msr_bitmap + 0x400 / f);
5952 if (type & MSR_TYPE_W)
5954 __clear_bit(msr, msr_bitmap + 0xc00 / f);
5959 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5962 int f = sizeof(unsigned long);
5964 if (!cpu_has_vmx_msr_bitmap())
5967 if (static_branch_unlikely(&enable_evmcs))
5968 evmcs_touch_msr_bitmap();
5971 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5972 * have the write-low and read-high bitmap offsets the wrong way round.
5973 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5975 if (msr <= 0x1fff) {
5976 if (type & MSR_TYPE_R)
5978 __set_bit(msr, msr_bitmap + 0x000 / f);
5980 if (type & MSR_TYPE_W)
5982 __set_bit(msr, msr_bitmap + 0x800 / f);
5984 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5986 if (type & MSR_TYPE_R)
5988 __set_bit(msr, msr_bitmap + 0x400 / f);
5990 if (type & MSR_TYPE_W)
5992 __set_bit(msr, msr_bitmap + 0xc00 / f);
5997 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5998 u32 msr, int type, bool value)
6001 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
6003 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
6007 * If a msr is allowed by L0, we should check whether it is allowed by L1.
6008 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
6010 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
6011 unsigned long *msr_bitmap_nested,
6014 int f = sizeof(unsigned long);
6017 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
6018 * have the write-low and read-high bitmap offsets the wrong way round.
6019 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
6021 if (msr <= 0x1fff) {
6022 if (type & MSR_TYPE_R &&
6023 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
6025 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
6027 if (type & MSR_TYPE_W &&
6028 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
6030 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
6032 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
6034 if (type & MSR_TYPE_R &&
6035 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
6037 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
6039 if (type & MSR_TYPE_W &&
6040 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
6042 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
6047 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
6051 if (cpu_has_secondary_exec_ctrls() &&
6052 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
6053 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
6054 mode |= MSR_BITMAP_MODE_X2APIC;
6055 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
6056 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
6062 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
6064 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
6069 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
6070 unsigned word = msr / BITS_PER_LONG;
6071 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
6072 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
6075 if (mode & MSR_BITMAP_MODE_X2APIC) {
6077 * TPR reads and writes can be virtualized even if virtual interrupt
6078 * delivery is not in use.
6080 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
6081 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
6082 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
6083 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
6084 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
6089 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
6091 struct vcpu_vmx *vmx = to_vmx(vcpu);
6092 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
6093 u8 mode = vmx_msr_bitmap_mode(vcpu);
6094 u8 changed = mode ^ vmx->msr_bitmap_mode;
6099 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
6100 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
6102 vmx->msr_bitmap_mode = mode;
6105 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
6107 return enable_apicv;
6110 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
6112 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6116 * Don't need to mark the APIC access page dirty; it is never
6117 * written to by the CPU during APIC virtualization.
6120 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
6121 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
6122 kvm_vcpu_mark_page_dirty(vcpu, gfn);
6125 if (nested_cpu_has_posted_intr(vmcs12)) {
6126 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
6127 kvm_vcpu_mark_page_dirty(vcpu, gfn);
6132 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
6134 struct vcpu_vmx *vmx = to_vmx(vcpu);
6139 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
6142 vmx->nested.pi_pending = false;
6143 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
6146 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
6147 if (max_irr != 256) {
6148 vapic_page = kmap(vmx->nested.virtual_apic_page);
6149 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
6150 vapic_page, &max_irr);
6151 kunmap(vmx->nested.virtual_apic_page);
6153 status = vmcs_read16(GUEST_INTR_STATUS);
6154 if ((u8)max_irr > ((u8)status & 0xff)) {
6156 status |= (u8)max_irr;
6157 vmcs_write16(GUEST_INTR_STATUS, status);
6161 nested_mark_vmcs12_pages_dirty(vcpu);
6164 static u8 vmx_get_rvi(void)
6166 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
6169 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
6171 struct vcpu_vmx *vmx = to_vmx(vcpu);
6176 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
6177 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
6178 WARN_ON_ONCE(!vmx->nested.virtual_apic_page))
6181 rvi = vmx_get_rvi();
6183 vapic_page = kmap(vmx->nested.virtual_apic_page);
6184 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
6185 kunmap(vmx->nested.virtual_apic_page);
6187 return ((rvi & 0xf0) > (vppr & 0xf0));
6190 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
6194 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
6196 if (vcpu->mode == IN_GUEST_MODE) {
6198 * The vector of interrupt to be delivered to vcpu had
6199 * been set in PIR before this function.
6201 * Following cases will be reached in this block, and
6202 * we always send a notification event in all cases as
6205 * Case 1: vcpu keeps in non-root mode. Sending a
6206 * notification event posts the interrupt to vcpu.
6208 * Case 2: vcpu exits to root mode and is still
6209 * runnable. PIR will be synced to vIRR before the
6210 * next vcpu entry. Sending a notification event in
6211 * this case has no effect, as vcpu is not in root
6214 * Case 3: vcpu exits to root mode and is blocked.
6215 * vcpu_block() has already synced PIR to vIRR and
6216 * never blocks vcpu if vIRR is not cleared. Therefore,
6217 * a blocked vcpu here does not wait for any requested
6218 * interrupts in PIR, and sending a notification event
6219 * which has no effect is safe here.
6222 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
6229 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
6232 struct vcpu_vmx *vmx = to_vmx(vcpu);
6234 if (is_guest_mode(vcpu) &&
6235 vector == vmx->nested.posted_intr_nv) {
6237 * If a posted intr is not recognized by hardware,
6238 * we will accomplish it in the next vmentry.
6240 vmx->nested.pi_pending = true;
6241 kvm_make_request(KVM_REQ_EVENT, vcpu);
6242 /* the PIR and ON have been set by L1. */
6243 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
6244 kvm_vcpu_kick(vcpu);
6250 * Send interrupt to vcpu via posted interrupt way.
6251 * 1. If target vcpu is running(non-root mode), send posted interrupt
6252 * notification to vcpu and hardware will sync PIR to vIRR atomically.
6253 * 2. If target vcpu isn't running(root mode), kick it to pick up the
6254 * interrupt from PIR in next vmentry.
6256 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
6258 struct vcpu_vmx *vmx = to_vmx(vcpu);
6261 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
6265 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
6268 /* If a previous notification has sent the IPI, nothing to do. */
6269 if (pi_test_and_set_on(&vmx->pi_desc))
6272 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
6273 kvm_vcpu_kick(vcpu);
6277 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
6278 * will not change in the lifetime of the guest.
6279 * Note that host-state that does change is set elsewhere. E.g., host-state
6280 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
6282 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
6287 unsigned long cr0, cr3, cr4;
6290 WARN_ON(cr0 & X86_CR0_TS);
6291 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
6294 * Save the most likely value for this task's CR3 in the VMCS.
6295 * We can't use __get_current_cr3_fast() because we're not atomic.
6298 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
6299 vmx->loaded_vmcs->host_state.cr3 = cr3;
6301 /* Save the most likely value for this task's CR4 in the VMCS. */
6302 cr4 = cr4_read_shadow();
6303 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
6304 vmx->loaded_vmcs->host_state.cr4 = cr4;
6306 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
6307 #ifdef CONFIG_X86_64
6309 * Load null selectors, so we can avoid reloading them in
6310 * vmx_prepare_switch_to_host(), in case userspace uses
6311 * the null selectors too (the expected case).
6313 vmcs_write16(HOST_DS_SELECTOR, 0);
6314 vmcs_write16(HOST_ES_SELECTOR, 0);
6316 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
6317 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
6319 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
6320 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
6323 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6324 vmx->host_idt_base = dt.address;
6326 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
6328 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
6329 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
6330 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
6331 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
6333 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
6334 rdmsr(MSR_IA32_CR_PAT, low32, high32);
6335 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
6338 if (cpu_has_load_ia32_efer)
6339 vmcs_write64(HOST_IA32_EFER, host_efer);
6342 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
6344 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
6346 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
6347 if (is_guest_mode(&vmx->vcpu))
6348 vmx->vcpu.arch.cr4_guest_owned_bits &=
6349 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
6350 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
6353 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
6355 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
6357 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
6358 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
6361 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
6363 /* Enable the preemption timer dynamically */
6364 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
6365 return pin_based_exec_ctrl;
6368 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
6370 struct vcpu_vmx *vmx = to_vmx(vcpu);
6372 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6373 if (cpu_has_secondary_exec_ctrls()) {
6374 if (kvm_vcpu_apicv_active(vcpu))
6375 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
6376 SECONDARY_EXEC_APIC_REGISTER_VIRT |
6377 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6379 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6380 SECONDARY_EXEC_APIC_REGISTER_VIRT |
6381 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6384 if (cpu_has_vmx_msr_bitmap())
6385 vmx_update_msr_bitmap(vcpu);
6388 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
6390 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
6392 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
6393 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
6395 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
6396 exec_control &= ~CPU_BASED_TPR_SHADOW;
6397 #ifdef CONFIG_X86_64
6398 exec_control |= CPU_BASED_CR8_STORE_EXITING |
6399 CPU_BASED_CR8_LOAD_EXITING;
6403 exec_control |= CPU_BASED_CR3_STORE_EXITING |
6404 CPU_BASED_CR3_LOAD_EXITING |
6405 CPU_BASED_INVLPG_EXITING;
6406 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
6407 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
6408 CPU_BASED_MONITOR_EXITING);
6409 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
6410 exec_control &= ~CPU_BASED_HLT_EXITING;
6411 return exec_control;
6414 static bool vmx_rdrand_supported(void)
6416 return vmcs_config.cpu_based_2nd_exec_ctrl &
6417 SECONDARY_EXEC_RDRAND_EXITING;
6420 static bool vmx_rdseed_supported(void)
6422 return vmcs_config.cpu_based_2nd_exec_ctrl &
6423 SECONDARY_EXEC_RDSEED_EXITING;
6426 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
6428 struct kvm_vcpu *vcpu = &vmx->vcpu;
6430 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
6432 if (!cpu_need_virtualize_apic_accesses(vcpu))
6433 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6435 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
6437 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
6438 enable_unrestricted_guest = 0;
6440 if (!enable_unrestricted_guest)
6441 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
6442 if (kvm_pause_in_guest(vmx->vcpu.kvm))
6443 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
6444 if (!kvm_vcpu_apicv_active(vcpu))
6445 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
6446 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6447 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6449 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
6450 * in vmx_set_cr4. */
6451 exec_control &= ~SECONDARY_EXEC_DESC;
6453 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
6455 We can NOT enable shadow_vmcs here because we don't have yet
6458 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6461 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
6463 if (vmx_xsaves_supported()) {
6464 /* Exposing XSAVES only when XSAVE is exposed */
6465 bool xsaves_enabled =
6466 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
6467 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
6469 if (!xsaves_enabled)
6470 exec_control &= ~SECONDARY_EXEC_XSAVES;
6474 vmx->nested.msrs.secondary_ctls_high |=
6475 SECONDARY_EXEC_XSAVES;
6477 vmx->nested.msrs.secondary_ctls_high &=
6478 ~SECONDARY_EXEC_XSAVES;
6482 if (vmx_rdtscp_supported()) {
6483 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
6484 if (!rdtscp_enabled)
6485 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6489 vmx->nested.msrs.secondary_ctls_high |=
6490 SECONDARY_EXEC_RDTSCP;
6492 vmx->nested.msrs.secondary_ctls_high &=
6493 ~SECONDARY_EXEC_RDTSCP;
6497 if (vmx_invpcid_supported()) {
6498 /* Exposing INVPCID only when PCID is exposed */
6499 bool invpcid_enabled =
6500 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
6501 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
6503 if (!invpcid_enabled) {
6504 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6505 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
6509 if (invpcid_enabled)
6510 vmx->nested.msrs.secondary_ctls_high |=
6511 SECONDARY_EXEC_ENABLE_INVPCID;
6513 vmx->nested.msrs.secondary_ctls_high &=
6514 ~SECONDARY_EXEC_ENABLE_INVPCID;
6518 if (vmx_rdrand_supported()) {
6519 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
6521 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
6525 vmx->nested.msrs.secondary_ctls_high |=
6526 SECONDARY_EXEC_RDRAND_EXITING;
6528 vmx->nested.msrs.secondary_ctls_high &=
6529 ~SECONDARY_EXEC_RDRAND_EXITING;
6533 if (vmx_rdseed_supported()) {
6534 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
6536 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
6540 vmx->nested.msrs.secondary_ctls_high |=
6541 SECONDARY_EXEC_RDSEED_EXITING;
6543 vmx->nested.msrs.secondary_ctls_high &=
6544 ~SECONDARY_EXEC_RDSEED_EXITING;
6548 vmx->secondary_exec_control = exec_control;
6551 static void ept_set_mmio_spte_mask(void)
6554 * EPT Misconfigurations can be generated if the value of bits 2:0
6555 * of an EPT paging-structure entry is 110b (write/execute).
6557 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
6558 VMX_EPT_MISCONFIG_WX_VALUE);
6561 #define VMX_XSS_EXIT_BITMAP 0
6563 * Sets up the vmcs for emulated real mode.
6565 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
6569 if (enable_shadow_vmcs) {
6571 * At vCPU creation, "VMWRITE to any supported field
6572 * in the VMCS" is supported, so use the more
6573 * permissive vmx_vmread_bitmap to specify both read
6574 * and write permissions for the shadow VMCS.
6576 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6577 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmread_bitmap));
6579 if (cpu_has_vmx_msr_bitmap())
6580 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
6582 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
6585 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6586 vmx->hv_deadline_tsc = -1;
6588 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6590 if (cpu_has_secondary_exec_ctrls()) {
6591 vmx_compute_secondary_exec_control(vmx);
6592 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6593 vmx->secondary_exec_control);
6596 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
6597 vmcs_write64(EOI_EXIT_BITMAP0, 0);
6598 vmcs_write64(EOI_EXIT_BITMAP1, 0);
6599 vmcs_write64(EOI_EXIT_BITMAP2, 0);
6600 vmcs_write64(EOI_EXIT_BITMAP3, 0);
6602 vmcs_write16(GUEST_INTR_STATUS, 0);
6604 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6605 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
6608 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
6609 vmcs_write32(PLE_GAP, ple_gap);
6610 vmx->ple_window = ple_window;
6611 vmx->ple_window_dirty = true;
6614 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
6615 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6616 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
6618 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
6619 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6620 vmx_set_constant_host_state(vmx);
6621 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
6622 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6624 if (cpu_has_vmx_vmfunc())
6625 vmcs_write64(VM_FUNCTION_CONTROL, 0);
6627 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
6628 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
6629 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
6630 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6631 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6633 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6634 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6636 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6637 u32 index = vmx_msr_index[i];
6638 u32 data_low, data_high;
6641 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6643 if (wrmsr_safe(index, data_low, data_high) < 0)
6645 vmx->guest_msrs[j].index = i;
6646 vmx->guest_msrs[j].data = 0;
6647 vmx->guest_msrs[j].mask = -1ull;
6651 vmx->arch_capabilities = kvm_get_arch_capabilities();
6653 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6655 /* 22.2.1, 20.8.1 */
6656 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
6658 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
6659 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
6661 set_cr4_guest_host_mask(vmx);
6663 if (vmx_xsaves_supported())
6664 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
6667 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
6668 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6671 if (cpu_has_vmx_encls_vmexit())
6672 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
6675 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
6677 struct vcpu_vmx *vmx = to_vmx(vcpu);
6678 struct msr_data apic_base_msr;
6681 vmx->rmode.vm86_active = 0;
6684 vcpu->arch.microcode_version = 0x100000000ULL;
6685 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
6686 kvm_set_cr8(vcpu, 0);
6689 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6690 MSR_IA32_APICBASE_ENABLE;
6691 if (kvm_vcpu_is_reset_bsp(vcpu))
6692 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6693 apic_base_msr.host_initiated = true;
6694 kvm_set_apic_base(vcpu, &apic_base_msr);
6697 vmx_segment_cache_clear(vmx);
6699 seg_setup(VCPU_SREG_CS);
6700 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6701 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6703 seg_setup(VCPU_SREG_DS);
6704 seg_setup(VCPU_SREG_ES);
6705 seg_setup(VCPU_SREG_FS);
6706 seg_setup(VCPU_SREG_GS);
6707 seg_setup(VCPU_SREG_SS);
6709 vmcs_write16(GUEST_TR_SELECTOR, 0);
6710 vmcs_writel(GUEST_TR_BASE, 0);
6711 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6712 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6714 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6715 vmcs_writel(GUEST_LDTR_BASE, 0);
6716 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6717 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6720 vmcs_write32(GUEST_SYSENTER_CS, 0);
6721 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6722 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6723 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6726 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6727 kvm_rip_write(vcpu, 0xfff0);
6729 vmcs_writel(GUEST_GDTR_BASE, 0);
6730 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6732 vmcs_writel(GUEST_IDTR_BASE, 0);
6733 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6735 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6736 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6737 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6738 if (kvm_mpx_supported())
6739 vmcs_write64(GUEST_BNDCFGS, 0);
6743 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
6745 if (cpu_has_vmx_tpr_shadow() && !init_event) {
6746 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6747 if (cpu_need_tpr_shadow(vcpu))
6748 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6749 __pa(vcpu->arch.apic->regs));
6750 vmcs_write32(TPR_THRESHOLD, 0);
6753 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6756 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6758 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6759 vmx->vcpu.arch.cr0 = cr0;
6760 vmx_set_cr0(vcpu, cr0); /* enter rmode */
6761 vmx_set_cr4(vcpu, 0);
6762 vmx_set_efer(vcpu, 0);
6764 update_exception_bitmap(vcpu);
6766 vpid_sync_context(vmx->vpid);
6768 vmx_clear_hlt(vcpu);
6772 * In nested virtualization, check if L1 asked to exit on external interrupts.
6773 * For most existing hypervisors, this will always return true.
6775 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6777 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6778 PIN_BASED_EXT_INTR_MASK;
6782 * In nested virtualization, check if L1 has set
6783 * VM_EXIT_ACK_INTR_ON_EXIT
6785 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6787 return get_vmcs12(vcpu)->vm_exit_controls &
6788 VM_EXIT_ACK_INTR_ON_EXIT;
6791 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6793 return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
6796 static void enable_irq_window(struct kvm_vcpu *vcpu)
6798 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6799 CPU_BASED_VIRTUAL_INTR_PENDING);
6802 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6805 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6806 enable_irq_window(vcpu);
6810 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6811 CPU_BASED_VIRTUAL_NMI_PENDING);
6814 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6816 struct vcpu_vmx *vmx = to_vmx(vcpu);
6818 int irq = vcpu->arch.interrupt.nr;
6820 trace_kvm_inj_virq(irq);
6822 ++vcpu->stat.irq_injections;
6823 if (vmx->rmode.vm86_active) {
6825 if (vcpu->arch.interrupt.soft)
6826 inc_eip = vcpu->arch.event_exit_inst_len;
6827 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6828 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6831 intr = irq | INTR_INFO_VALID_MASK;
6832 if (vcpu->arch.interrupt.soft) {
6833 intr |= INTR_TYPE_SOFT_INTR;
6834 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6835 vmx->vcpu.arch.event_exit_inst_len);
6837 intr |= INTR_TYPE_EXT_INTR;
6838 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6840 vmx_clear_hlt(vcpu);
6843 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6845 struct vcpu_vmx *vmx = to_vmx(vcpu);
6849 * Tracking the NMI-blocked state in software is built upon
6850 * finding the next open IRQ window. This, in turn, depends on
6851 * well-behaving guests: They have to keep IRQs disabled at
6852 * least as long as the NMI handler runs. Otherwise we may
6853 * cause NMI nesting, maybe breaking the guest. But as this is
6854 * highly unlikely, we can live with the residual risk.
6856 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6857 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6860 ++vcpu->stat.nmi_injections;
6861 vmx->loaded_vmcs->nmi_known_unmasked = false;
6863 if (vmx->rmode.vm86_active) {
6864 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6865 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6869 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6870 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6872 vmx_clear_hlt(vcpu);
6875 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6877 struct vcpu_vmx *vmx = to_vmx(vcpu);
6881 return vmx->loaded_vmcs->soft_vnmi_blocked;
6882 if (vmx->loaded_vmcs->nmi_known_unmasked)
6884 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6885 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6889 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6891 struct vcpu_vmx *vmx = to_vmx(vcpu);
6894 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6895 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6896 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6899 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6901 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6902 GUEST_INTR_STATE_NMI);
6904 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6905 GUEST_INTR_STATE_NMI);
6909 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6911 if (to_vmx(vcpu)->nested.nested_run_pending)
6915 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6918 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6919 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6920 | GUEST_INTR_STATE_NMI));
6923 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6925 return (!to_vmx(vcpu)->nested.nested_run_pending &&
6926 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6927 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6928 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6931 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6935 if (enable_unrestricted_guest)
6938 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6942 to_kvm_vmx(kvm)->tss_addr = addr;
6943 return init_rmode_tss(kvm);
6946 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
6948 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
6952 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6957 * Update instruction length as we may reinject the exception
6958 * from user space while in guest debugging mode.
6960 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6961 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6962 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6966 if (vcpu->guest_debug &
6967 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6984 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6985 int vec, u32 err_code)
6988 * Instruction with address size override prefix opcode 0x67
6989 * Cause the #SS fault with 0 error code in VM86 mode.
6991 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6992 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6993 if (vcpu->arch.halt_request) {
6994 vcpu->arch.halt_request = 0;
6995 return kvm_vcpu_halt(vcpu);
7003 * Forward all other exceptions that are valid in real mode.
7004 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
7005 * the required debugging infrastructure rework.
7007 kvm_queue_exception(vcpu, vec);
7012 * Trigger machine check on the host. We assume all the MSRs are already set up
7013 * by the CPU and that we still run on the same CPU as the MCE occurred on.
7014 * We pass a fake environment to the machine check handler because we want
7015 * the guest to be always treated like user space, no matter what context
7016 * it used internally.
7018 static void kvm_machine_check(void)
7020 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
7021 struct pt_regs regs = {
7022 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
7023 .flags = X86_EFLAGS_IF,
7026 do_machine_check(®s, 0);
7030 static int handle_machine_check(struct kvm_vcpu *vcpu)
7032 /* already handled by vcpu_run */
7036 static int handle_exception(struct kvm_vcpu *vcpu)
7038 struct vcpu_vmx *vmx = to_vmx(vcpu);
7039 struct kvm_run *kvm_run = vcpu->run;
7040 u32 intr_info, ex_no, error_code;
7041 unsigned long cr2, rip, dr6;
7043 enum emulation_result er;
7045 vect_info = vmx->idt_vectoring_info;
7046 intr_info = vmx->exit_intr_info;
7048 if (is_machine_check(intr_info))
7049 return handle_machine_check(vcpu);
7051 if (is_nmi(intr_info))
7052 return 1; /* already handled by vmx_vcpu_run() */
7054 if (is_invalid_opcode(intr_info))
7055 return handle_ud(vcpu);
7058 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
7059 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7061 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
7062 WARN_ON_ONCE(!enable_vmware_backdoor);
7063 er = kvm_emulate_instruction(vcpu,
7064 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
7065 if (er == EMULATE_USER_EXIT)
7067 else if (er != EMULATE_DONE)
7068 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
7073 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
7074 * MMIO, it is better to report an internal error.
7075 * See the comments in vmx_handle_exit.
7077 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
7078 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
7079 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7080 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
7081 vcpu->run->internal.ndata = 3;
7082 vcpu->run->internal.data[0] = vect_info;
7083 vcpu->run->internal.data[1] = intr_info;
7084 vcpu->run->internal.data[2] = error_code;
7088 if (is_page_fault(intr_info)) {
7089 cr2 = vmcs_readl(EXIT_QUALIFICATION);
7090 /* EPT won't cause page fault directly */
7091 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
7092 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
7095 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
7097 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
7098 return handle_rmode_exception(vcpu, ex_no, error_code);
7102 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
7105 dr6 = vmcs_readl(EXIT_QUALIFICATION);
7106 if (!(vcpu->guest_debug &
7107 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
7108 vcpu->arch.dr6 &= ~15;
7109 vcpu->arch.dr6 |= dr6 | DR6_RTM;
7110 if (is_icebp(intr_info))
7111 skip_emulated_instruction(vcpu);
7113 kvm_queue_exception(vcpu, DB_VECTOR);
7116 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
7117 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
7121 * Update instruction length as we may reinject #BP from
7122 * user space while in guest debugging mode. Reading it for
7123 * #DB as well causes no harm, it is not used in that case.
7125 vmx->vcpu.arch.event_exit_inst_len =
7126 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7127 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7128 rip = kvm_rip_read(vcpu);
7129 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
7130 kvm_run->debug.arch.exception = ex_no;
7133 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
7134 kvm_run->ex.exception = ex_no;
7135 kvm_run->ex.error_code = error_code;
7141 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
7143 ++vcpu->stat.irq_exits;
7147 static int handle_triple_fault(struct kvm_vcpu *vcpu)
7149 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7150 vcpu->mmio_needed = 0;
7154 static int handle_io(struct kvm_vcpu *vcpu)
7156 unsigned long exit_qualification;
7157 int size, in, string;
7160 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7161 string = (exit_qualification & 16) != 0;
7163 ++vcpu->stat.io_exits;
7166 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7168 port = exit_qualification >> 16;
7169 size = (exit_qualification & 7) + 1;
7170 in = (exit_qualification & 8) != 0;
7172 return kvm_fast_pio(vcpu, size, port, in);
7176 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
7179 * Patch in the VMCALL instruction:
7181 hypercall[0] = 0x0f;
7182 hypercall[1] = 0x01;
7183 hypercall[2] = 0xc1;
7186 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
7187 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
7189 if (is_guest_mode(vcpu)) {
7190 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7191 unsigned long orig_val = val;
7194 * We get here when L2 changed cr0 in a way that did not change
7195 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
7196 * but did change L0 shadowed bits. So we first calculate the
7197 * effective cr0 value that L1 would like to write into the
7198 * hardware. It consists of the L2-owned bits from the new
7199 * value combined with the L1-owned bits from L1's guest_cr0.
7201 val = (val & ~vmcs12->cr0_guest_host_mask) |
7202 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
7204 if (!nested_guest_cr0_valid(vcpu, val))
7207 if (kvm_set_cr0(vcpu, val))
7209 vmcs_writel(CR0_READ_SHADOW, orig_val);
7212 if (to_vmx(vcpu)->nested.vmxon &&
7213 !nested_host_cr0_valid(vcpu, val))
7216 return kvm_set_cr0(vcpu, val);
7220 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
7222 if (is_guest_mode(vcpu)) {
7223 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7224 unsigned long orig_val = val;
7226 /* analogously to handle_set_cr0 */
7227 val = (val & ~vmcs12->cr4_guest_host_mask) |
7228 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
7229 if (kvm_set_cr4(vcpu, val))
7231 vmcs_writel(CR4_READ_SHADOW, orig_val);
7234 return kvm_set_cr4(vcpu, val);
7237 static int handle_desc(struct kvm_vcpu *vcpu)
7239 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
7240 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7243 static int handle_cr(struct kvm_vcpu *vcpu)
7245 unsigned long exit_qualification, val;
7251 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7252 cr = exit_qualification & 15;
7253 reg = (exit_qualification >> 8) & 15;
7254 switch ((exit_qualification >> 4) & 3) {
7255 case 0: /* mov to cr */
7256 val = kvm_register_readl(vcpu, reg);
7257 trace_kvm_cr_write(cr, val);
7260 err = handle_set_cr0(vcpu, val);
7261 return kvm_complete_insn_gp(vcpu, err);
7263 WARN_ON_ONCE(enable_unrestricted_guest);
7264 err = kvm_set_cr3(vcpu, val);
7265 return kvm_complete_insn_gp(vcpu, err);
7267 err = handle_set_cr4(vcpu, val);
7268 return kvm_complete_insn_gp(vcpu, err);
7270 u8 cr8_prev = kvm_get_cr8(vcpu);
7272 err = kvm_set_cr8(vcpu, cr8);
7273 ret = kvm_complete_insn_gp(vcpu, err);
7274 if (lapic_in_kernel(vcpu))
7276 if (cr8_prev <= cr8)
7279 * TODO: we might be squashing a
7280 * KVM_GUESTDBG_SINGLESTEP-triggered
7281 * KVM_EXIT_DEBUG here.
7283 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
7289 WARN_ONCE(1, "Guest should always own CR0.TS");
7290 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
7291 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
7292 return kvm_skip_emulated_instruction(vcpu);
7293 case 1: /*mov from cr*/
7296 WARN_ON_ONCE(enable_unrestricted_guest);
7297 val = kvm_read_cr3(vcpu);
7298 kvm_register_write(vcpu, reg, val);
7299 trace_kvm_cr_read(cr, val);
7300 return kvm_skip_emulated_instruction(vcpu);
7302 val = kvm_get_cr8(vcpu);
7303 kvm_register_write(vcpu, reg, val);
7304 trace_kvm_cr_read(cr, val);
7305 return kvm_skip_emulated_instruction(vcpu);
7309 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
7310 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
7311 kvm_lmsw(vcpu, val);
7313 return kvm_skip_emulated_instruction(vcpu);
7317 vcpu->run->exit_reason = 0;
7318 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
7319 (int)(exit_qualification >> 4) & 3, cr);
7323 static int handle_dr(struct kvm_vcpu *vcpu)
7325 unsigned long exit_qualification;
7328 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7329 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
7331 /* First, if DR does not exist, trigger UD */
7332 if (!kvm_require_dr(vcpu, dr))
7335 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
7336 if (!kvm_require_cpl(vcpu, 0))
7338 dr7 = vmcs_readl(GUEST_DR7);
7341 * As the vm-exit takes precedence over the debug trap, we
7342 * need to emulate the latter, either for the host or the
7343 * guest debugging itself.
7345 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7346 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
7347 vcpu->run->debug.arch.dr7 = dr7;
7348 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7349 vcpu->run->debug.arch.exception = DB_VECTOR;
7350 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
7353 vcpu->arch.dr6 &= ~15;
7354 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
7355 kvm_queue_exception(vcpu, DB_VECTOR);
7360 if (vcpu->guest_debug == 0) {
7361 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7362 CPU_BASED_MOV_DR_EXITING);
7365 * No more DR vmexits; force a reload of the debug registers
7366 * and reenter on this instruction. The next vmexit will
7367 * retrieve the full state of the debug registers.
7369 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
7373 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
7374 if (exit_qualification & TYPE_MOV_FROM_DR) {
7377 if (kvm_get_dr(vcpu, dr, &val))
7379 kvm_register_write(vcpu, reg, val);
7381 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
7384 return kvm_skip_emulated_instruction(vcpu);
7387 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
7389 return vcpu->arch.dr6;
7392 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
7396 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
7398 get_debugreg(vcpu->arch.db[0], 0);
7399 get_debugreg(vcpu->arch.db[1], 1);
7400 get_debugreg(vcpu->arch.db[2], 2);
7401 get_debugreg(vcpu->arch.db[3], 3);
7402 get_debugreg(vcpu->arch.dr6, 6);
7403 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
7405 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
7406 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
7409 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
7411 vmcs_writel(GUEST_DR7, val);
7414 static int handle_cpuid(struct kvm_vcpu *vcpu)
7416 return kvm_emulate_cpuid(vcpu);
7419 static int handle_rdmsr(struct kvm_vcpu *vcpu)
7421 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7422 struct msr_data msr_info;
7424 msr_info.index = ecx;
7425 msr_info.host_initiated = false;
7426 if (vmx_get_msr(vcpu, &msr_info)) {
7427 trace_kvm_msr_read_ex(ecx);
7428 kvm_inject_gp(vcpu, 0);
7432 trace_kvm_msr_read(ecx, msr_info.data);
7434 /* FIXME: handling of bits 32:63 of rax, rdx */
7435 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
7436 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
7437 return kvm_skip_emulated_instruction(vcpu);
7440 static int handle_wrmsr(struct kvm_vcpu *vcpu)
7442 struct msr_data msr;
7443 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7444 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
7445 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
7449 msr.host_initiated = false;
7450 if (kvm_set_msr(vcpu, &msr) != 0) {
7451 trace_kvm_msr_write_ex(ecx, data);
7452 kvm_inject_gp(vcpu, 0);
7456 trace_kvm_msr_write(ecx, data);
7457 return kvm_skip_emulated_instruction(vcpu);
7460 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
7462 kvm_apic_update_ppr(vcpu);
7466 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
7468 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7469 CPU_BASED_VIRTUAL_INTR_PENDING);
7471 kvm_make_request(KVM_REQ_EVENT, vcpu);
7473 ++vcpu->stat.irq_window_exits;
7477 static int handle_halt(struct kvm_vcpu *vcpu)
7479 return kvm_emulate_halt(vcpu);
7482 static int handle_vmcall(struct kvm_vcpu *vcpu)
7484 return kvm_emulate_hypercall(vcpu);
7487 static int handle_invd(struct kvm_vcpu *vcpu)
7489 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7492 static int handle_invlpg(struct kvm_vcpu *vcpu)
7494 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7496 kvm_mmu_invlpg(vcpu, exit_qualification);
7497 return kvm_skip_emulated_instruction(vcpu);
7500 static int handle_rdpmc(struct kvm_vcpu *vcpu)
7504 err = kvm_rdpmc(vcpu);
7505 return kvm_complete_insn_gp(vcpu, err);
7508 static int handle_wbinvd(struct kvm_vcpu *vcpu)
7510 return kvm_emulate_wbinvd(vcpu);
7513 static int handle_xsetbv(struct kvm_vcpu *vcpu)
7515 u64 new_bv = kvm_read_edx_eax(vcpu);
7516 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
7518 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
7519 return kvm_skip_emulated_instruction(vcpu);
7523 static int handle_xsaves(struct kvm_vcpu *vcpu)
7525 kvm_skip_emulated_instruction(vcpu);
7526 WARN(1, "this should never happen\n");
7530 static int handle_xrstors(struct kvm_vcpu *vcpu)
7532 kvm_skip_emulated_instruction(vcpu);
7533 WARN(1, "this should never happen\n");
7537 static int handle_apic_access(struct kvm_vcpu *vcpu)
7539 if (likely(fasteoi)) {
7540 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7541 int access_type, offset;
7543 access_type = exit_qualification & APIC_ACCESS_TYPE;
7544 offset = exit_qualification & APIC_ACCESS_OFFSET;
7546 * Sane guest uses MOV to write EOI, with written value
7547 * not cared. So make a short-circuit here by avoiding
7548 * heavy instruction emulation.
7550 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
7551 (offset == APIC_EOI)) {
7552 kvm_lapic_set_eoi(vcpu);
7553 return kvm_skip_emulated_instruction(vcpu);
7556 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7559 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
7561 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7562 int vector = exit_qualification & 0xff;
7564 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
7565 kvm_apic_set_eoi_accelerated(vcpu, vector);
7569 static int handle_apic_write(struct kvm_vcpu *vcpu)
7571 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7572 u32 offset = exit_qualification & 0xfff;
7574 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
7575 kvm_apic_write_nodecode(vcpu, offset);
7579 static int handle_task_switch(struct kvm_vcpu *vcpu)
7581 struct vcpu_vmx *vmx = to_vmx(vcpu);
7582 unsigned long exit_qualification;
7583 bool has_error_code = false;
7586 int reason, type, idt_v, idt_index;
7588 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7589 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
7590 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
7592 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7594 reason = (u32)exit_qualification >> 30;
7595 if (reason == TASK_SWITCH_GATE && idt_v) {
7597 case INTR_TYPE_NMI_INTR:
7598 vcpu->arch.nmi_injected = false;
7599 vmx_set_nmi_mask(vcpu, true);
7601 case INTR_TYPE_EXT_INTR:
7602 case INTR_TYPE_SOFT_INTR:
7603 kvm_clear_interrupt_queue(vcpu);
7605 case INTR_TYPE_HARD_EXCEPTION:
7606 if (vmx->idt_vectoring_info &
7607 VECTORING_INFO_DELIVER_CODE_MASK) {
7608 has_error_code = true;
7610 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7613 case INTR_TYPE_SOFT_EXCEPTION:
7614 kvm_clear_exception_queue(vcpu);
7620 tss_selector = exit_qualification;
7622 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
7623 type != INTR_TYPE_EXT_INTR &&
7624 type != INTR_TYPE_NMI_INTR))
7625 skip_emulated_instruction(vcpu);
7627 if (kvm_task_switch(vcpu, tss_selector,
7628 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
7629 has_error_code, error_code) == EMULATE_FAIL) {
7630 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7631 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7632 vcpu->run->internal.ndata = 0;
7637 * TODO: What about debug traps on tss switch?
7638 * Are we supposed to inject them and update dr6?
7644 static int handle_ept_violation(struct kvm_vcpu *vcpu)
7646 unsigned long exit_qualification;
7650 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7653 * EPT violation happened while executing iret from NMI,
7654 * "blocked by NMI" bit has to be set before next VM entry.
7655 * There are errata that may cause this bit to not be set:
7658 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7660 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7661 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
7663 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7664 trace_kvm_page_fault(gpa, exit_qualification);
7666 /* Is it a read fault? */
7667 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
7668 ? PFERR_USER_MASK : 0;
7669 /* Is it a write fault? */
7670 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
7671 ? PFERR_WRITE_MASK : 0;
7672 /* Is it a fetch fault? */
7673 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
7674 ? PFERR_FETCH_MASK : 0;
7675 /* ept page table entry is present? */
7676 error_code |= (exit_qualification &
7677 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
7678 EPT_VIOLATION_EXECUTABLE))
7679 ? PFERR_PRESENT_MASK : 0;
7681 error_code |= (exit_qualification & 0x100) != 0 ?
7682 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
7684 vcpu->arch.exit_qualification = exit_qualification;
7685 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
7688 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
7693 * A nested guest cannot optimize MMIO vmexits, because we have an
7694 * nGPA here instead of the required GPA.
7696 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7697 if (!is_guest_mode(vcpu) &&
7698 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
7699 trace_kvm_fast_mmio(gpa);
7701 * Doing kvm_skip_emulated_instruction() depends on undefined
7702 * behavior: Intel's manual doesn't mandate
7703 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7704 * occurs and while on real hardware it was observed to be set,
7705 * other hypervisors (namely Hyper-V) don't set it, we end up
7706 * advancing IP with some random value. Disable fast mmio when
7707 * running nested and keep it for real hardware in hope that
7708 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7710 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7711 return kvm_skip_emulated_instruction(vcpu);
7713 return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) ==
7717 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7720 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7722 WARN_ON_ONCE(!enable_vnmi);
7723 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7724 CPU_BASED_VIRTUAL_NMI_PENDING);
7725 ++vcpu->stat.nmi_window_exits;
7726 kvm_make_request(KVM_REQ_EVENT, vcpu);
7731 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7733 struct vcpu_vmx *vmx = to_vmx(vcpu);
7734 enum emulation_result err = EMULATE_DONE;
7737 bool intr_window_requested;
7738 unsigned count = 130;
7741 * We should never reach the point where we are emulating L2
7742 * due to invalid guest state as that means we incorrectly
7743 * allowed a nested VMEntry with an invalid vmcs12.
7745 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
7747 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7748 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7750 while (vmx->emulation_required && count-- != 0) {
7751 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7752 return handle_interrupt_window(&vmx->vcpu);
7754 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7757 err = kvm_emulate_instruction(vcpu, 0);
7759 if (err == EMULATE_USER_EXIT) {
7760 ++vcpu->stat.mmio_exits;
7765 if (err != EMULATE_DONE)
7766 goto emulation_error;
7768 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7769 vcpu->arch.exception.pending)
7770 goto emulation_error;
7772 if (vcpu->arch.halt_request) {
7773 vcpu->arch.halt_request = 0;
7774 ret = kvm_vcpu_halt(vcpu);
7778 if (signal_pending(current))
7788 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7789 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7790 vcpu->run->internal.ndata = 0;
7794 static void grow_ple_window(struct kvm_vcpu *vcpu)
7796 struct vcpu_vmx *vmx = to_vmx(vcpu);
7797 int old = vmx->ple_window;
7799 vmx->ple_window = __grow_ple_window(old, ple_window,
7803 if (vmx->ple_window != old)
7804 vmx->ple_window_dirty = true;
7806 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7809 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7811 struct vcpu_vmx *vmx = to_vmx(vcpu);
7812 int old = vmx->ple_window;
7814 vmx->ple_window = __shrink_ple_window(old, ple_window,
7818 if (vmx->ple_window != old)
7819 vmx->ple_window_dirty = true;
7821 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7825 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7827 static void wakeup_handler(void)
7829 struct kvm_vcpu *vcpu;
7830 int cpu = smp_processor_id();
7832 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7833 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7834 blocked_vcpu_list) {
7835 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7837 if (pi_test_on(pi_desc) == 1)
7838 kvm_vcpu_kick(vcpu);
7840 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7843 static void vmx_enable_tdp(void)
7845 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7846 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7847 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7848 0ull, VMX_EPT_EXECUTABLE_MASK,
7849 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7850 VMX_EPT_RWX_MASK, 0ull);
7852 ept_set_mmio_spte_mask();
7856 static __init int hardware_setup(void)
7858 unsigned long host_bndcfgs;
7861 rdmsrl_safe(MSR_EFER, &host_efer);
7863 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7864 kvm_define_shared_msr(i, vmx_msr_index[i]);
7866 for (i = 0; i < VMX_BITMAP_NR; i++) {
7867 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7872 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7873 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7875 if (setup_vmcs_config(&vmcs_config) < 0) {
7880 if (boot_cpu_has(X86_FEATURE_NX))
7881 kvm_enable_efer_bits(EFER_NX);
7883 if (boot_cpu_has(X86_FEATURE_MPX)) {
7884 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7885 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7888 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7889 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7892 if (!cpu_has_vmx_ept() ||
7893 !cpu_has_vmx_ept_4levels() ||
7894 !cpu_has_vmx_ept_mt_wb() ||
7895 !cpu_has_vmx_invept_global())
7898 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7899 enable_ept_ad_bits = 0;
7901 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7902 enable_unrestricted_guest = 0;
7904 if (!cpu_has_vmx_flexpriority())
7905 flexpriority_enabled = 0;
7907 if (!cpu_has_virtual_nmis())
7911 * set_apic_access_page_addr() is used to reload apic access
7912 * page upon invalidation. No need to do anything if not
7913 * using the APIC_ACCESS_ADDR VMCS field.
7915 if (!flexpriority_enabled)
7916 kvm_x86_ops->set_apic_access_page_addr = NULL;
7918 if (!cpu_has_vmx_tpr_shadow())
7919 kvm_x86_ops->update_cr8_intercept = NULL;
7921 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7922 kvm_disable_largepages();
7924 #if IS_ENABLED(CONFIG_HYPERV)
7925 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7927 kvm_x86_ops->tlb_remote_flush = vmx_hv_remote_flush_tlb;
7930 if (!cpu_has_vmx_ple()) {
7933 ple_window_grow = 0;
7935 ple_window_shrink = 0;
7938 if (!cpu_has_vmx_apicv()) {
7940 kvm_x86_ops->sync_pir_to_irr = NULL;
7943 if (cpu_has_vmx_tsc_scaling()) {
7944 kvm_has_tsc_control = true;
7945 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7946 kvm_tsc_scaling_ratio_frac_bits = 48;
7949 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7957 kvm_x86_ops->get_nested_state = NULL;
7958 kvm_x86_ops->set_nested_state = NULL;
7962 * Only enable PML when hardware supports PML feature, and both EPT
7963 * and EPT A/D bit features are enabled -- PML depends on them to work.
7965 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7969 kvm_x86_ops->slot_enable_log_dirty = NULL;
7970 kvm_x86_ops->slot_disable_log_dirty = NULL;
7971 kvm_x86_ops->flush_log_dirty = NULL;
7972 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7975 if (!cpu_has_vmx_preemption_timer())
7976 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7978 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7981 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7982 cpu_preemption_timer_multi =
7983 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7985 kvm_x86_ops->set_hv_timer = NULL;
7986 kvm_x86_ops->cancel_hv_timer = NULL;
7989 if (!cpu_has_vmx_shadow_vmcs())
7990 enable_shadow_vmcs = 0;
7991 if (enable_shadow_vmcs)
7992 init_vmcs_shadow_fields();
7994 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7995 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv);
7997 kvm_mce_cap_supported |= MCG_LMCE_P;
7999 return alloc_kvm_area();
8002 for (i = 0; i < VMX_BITMAP_NR; i++)
8003 free_page((unsigned long)vmx_bitmap[i]);
8008 static __exit void hardware_unsetup(void)
8012 for (i = 0; i < VMX_BITMAP_NR; i++)
8013 free_page((unsigned long)vmx_bitmap[i]);
8019 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
8020 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
8022 static int handle_pause(struct kvm_vcpu *vcpu)
8024 if (!kvm_pause_in_guest(vcpu->kvm))
8025 grow_ple_window(vcpu);
8028 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
8029 * VM-execution control is ignored if CPL > 0. OTOH, KVM
8030 * never set PAUSE_EXITING and just set PLE if supported,
8031 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
8033 kvm_vcpu_on_spin(vcpu, true);
8034 return kvm_skip_emulated_instruction(vcpu);
8037 static int handle_nop(struct kvm_vcpu *vcpu)
8039 return kvm_skip_emulated_instruction(vcpu);
8042 static int handle_mwait(struct kvm_vcpu *vcpu)
8044 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
8045 return handle_nop(vcpu);
8048 static int handle_invalid_op(struct kvm_vcpu *vcpu)
8050 kvm_queue_exception(vcpu, UD_VECTOR);
8054 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
8059 static int handle_monitor(struct kvm_vcpu *vcpu)
8061 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
8062 return handle_nop(vcpu);
8066 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
8067 * set the success or error code of an emulated VMX instruction (as specified
8068 * by Vol 2B, VMX Instruction Reference, "Conventions"), and skip the emulated
8071 static int nested_vmx_succeed(struct kvm_vcpu *vcpu)
8073 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
8074 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
8075 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
8076 return kvm_skip_emulated_instruction(vcpu);
8079 static int nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
8081 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
8082 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
8083 X86_EFLAGS_SF | X86_EFLAGS_OF))
8085 return kvm_skip_emulated_instruction(vcpu);
8088 static int nested_vmx_failValid(struct kvm_vcpu *vcpu,
8089 u32 vm_instruction_error)
8092 * failValid writes the error number to the current VMCS, which
8093 * can't be done if there isn't a current VMCS.
8095 if (to_vmx(vcpu)->nested.current_vmptr == -1ull)
8096 return nested_vmx_failInvalid(vcpu);
8098 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
8099 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
8100 X86_EFLAGS_SF | X86_EFLAGS_OF))
8102 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
8104 * We don't need to force a shadow sync because
8105 * VM_INSTRUCTION_ERROR is not shadowed
8107 return kvm_skip_emulated_instruction(vcpu);
8110 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
8112 /* TODO: not to reset guest simply here. */
8113 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8114 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
8117 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
8119 struct vcpu_vmx *vmx =
8120 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
8122 vmx->nested.preemption_timer_expired = true;
8123 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
8124 kvm_vcpu_kick(&vmx->vcpu);
8126 return HRTIMER_NORESTART;
8130 * Decode the memory-address operand of a vmx instruction, as recorded on an
8131 * exit caused by such an instruction (run by a guest hypervisor).
8132 * On success, returns 0. When the operand is invalid, returns 1 and throws
8135 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
8136 unsigned long exit_qualification,
8137 u32 vmx_instruction_info, bool wr, gva_t *ret)
8141 struct kvm_segment s;
8144 * According to Vol. 3B, "Information for VM Exits Due to Instruction
8145 * Execution", on an exit, vmx_instruction_info holds most of the
8146 * addressing components of the operand. Only the displacement part
8147 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
8148 * For how an actual address is calculated from all these components,
8149 * refer to Vol. 1, "Operand Addressing".
8151 int scaling = vmx_instruction_info & 3;
8152 int addr_size = (vmx_instruction_info >> 7) & 7;
8153 bool is_reg = vmx_instruction_info & (1u << 10);
8154 int seg_reg = (vmx_instruction_info >> 15) & 7;
8155 int index_reg = (vmx_instruction_info >> 18) & 0xf;
8156 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
8157 int base_reg = (vmx_instruction_info >> 23) & 0xf;
8158 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
8161 kvm_queue_exception(vcpu, UD_VECTOR);
8165 /* Addr = segment_base + offset */
8166 /* offset = base + [index * scale] + displacement */
8167 off = exit_qualification; /* holds the displacement */
8169 off += kvm_register_read(vcpu, base_reg);
8171 off += kvm_register_read(vcpu, index_reg)<<scaling;
8172 vmx_get_segment(vcpu, &s, seg_reg);
8173 *ret = s.base + off;
8175 if (addr_size == 1) /* 32 bit */
8178 /* Checks for #GP/#SS exceptions. */
8180 if (is_long_mode(vcpu)) {
8181 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
8182 * non-canonical form. This is the only check on the memory
8183 * destination for long mode!
8185 exn = is_noncanonical_address(*ret, vcpu);
8186 } else if (is_protmode(vcpu)) {
8187 /* Protected mode: apply checks for segment validity in the
8189 * - segment type check (#GP(0) may be thrown)
8190 * - usability check (#GP(0)/#SS(0))
8191 * - limit check (#GP(0)/#SS(0))
8194 /* #GP(0) if the destination operand is located in a
8195 * read-only data segment or any code segment.
8197 exn = ((s.type & 0xa) == 0 || (s.type & 8));
8199 /* #GP(0) if the source operand is located in an
8200 * execute-only code segment
8202 exn = ((s.type & 0xa) == 8);
8204 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8207 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
8209 exn = (s.unusable != 0);
8210 /* Protected mode: #GP(0)/#SS(0) if the memory
8211 * operand is outside the segment limit.
8213 exn = exn || (off + sizeof(u64) > s.limit);
8216 kvm_queue_exception_e(vcpu,
8217 seg_reg == VCPU_SREG_SS ?
8218 SS_VECTOR : GP_VECTOR,
8226 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
8229 struct x86_exception e;
8231 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8232 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
8235 if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) {
8236 kvm_inject_page_fault(vcpu, &e);
8244 * Allocate a shadow VMCS and associate it with the currently loaded
8245 * VMCS, unless such a shadow VMCS already exists. The newly allocated
8246 * VMCS is also VMCLEARed, so that it is ready for use.
8248 static struct vmcs *alloc_shadow_vmcs(struct kvm_vcpu *vcpu)
8250 struct vcpu_vmx *vmx = to_vmx(vcpu);
8251 struct loaded_vmcs *loaded_vmcs = vmx->loaded_vmcs;
8254 * We should allocate a shadow vmcs for vmcs01 only when L1
8255 * executes VMXON and free it when L1 executes VMXOFF.
8256 * As it is invalid to execute VMXON twice, we shouldn't reach
8257 * here when vmcs01 already have an allocated shadow vmcs.
8259 WARN_ON(loaded_vmcs == &vmx->vmcs01 && loaded_vmcs->shadow_vmcs);
8261 if (!loaded_vmcs->shadow_vmcs) {
8262 loaded_vmcs->shadow_vmcs = alloc_vmcs(true);
8263 if (loaded_vmcs->shadow_vmcs)
8264 vmcs_clear(loaded_vmcs->shadow_vmcs);
8266 return loaded_vmcs->shadow_vmcs;
8269 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
8271 struct vcpu_vmx *vmx = to_vmx(vcpu);
8274 r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
8278 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
8279 if (!vmx->nested.cached_vmcs12)
8280 goto out_cached_vmcs12;
8282 vmx->nested.cached_shadow_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
8283 if (!vmx->nested.cached_shadow_vmcs12)
8284 goto out_cached_shadow_vmcs12;
8286 if (enable_shadow_vmcs && !alloc_shadow_vmcs(vcpu))
8287 goto out_shadow_vmcs;
8289 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
8290 HRTIMER_MODE_REL_PINNED);
8291 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
8293 vmx->nested.vpid02 = allocate_vpid();
8295 vmx->nested.vmcs02_initialized = false;
8296 vmx->nested.vmxon = true;
8300 kfree(vmx->nested.cached_shadow_vmcs12);
8302 out_cached_shadow_vmcs12:
8303 kfree(vmx->nested.cached_vmcs12);
8306 free_loaded_vmcs(&vmx->nested.vmcs02);
8313 * Emulate the VMXON instruction.
8314 * Currently, we just remember that VMX is active, and do not save or even
8315 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
8316 * do not currently need to store anything in that guest-allocated memory
8317 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
8318 * argument is different from the VMXON pointer (which the spec says they do).
8320 static int handle_vmon(struct kvm_vcpu *vcpu)
8325 struct vcpu_vmx *vmx = to_vmx(vcpu);
8326 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
8327 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
8330 * The Intel VMX Instruction Reference lists a bunch of bits that are
8331 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
8332 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
8333 * Otherwise, we should fail with #UD. But most faulting conditions
8334 * have already been checked by hardware, prior to the VM-exit for
8335 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
8336 * that bit set to 1 in non-root mode.
8338 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
8339 kvm_queue_exception(vcpu, UD_VECTOR);
8343 /* CPL=0 must be checked manually. */
8344 if (vmx_get_cpl(vcpu)) {
8345 kvm_inject_gp(vcpu, 0);
8349 if (vmx->nested.vmxon)
8350 return nested_vmx_failValid(vcpu,
8351 VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
8353 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
8354 != VMXON_NEEDED_FEATURES) {
8355 kvm_inject_gp(vcpu, 0);
8359 if (nested_vmx_get_vmptr(vcpu, &vmptr))
8364 * The first 4 bytes of VMXON region contain the supported
8365 * VMCS revision identifier
8367 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
8368 * which replaces physical address width with 32
8370 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu)))
8371 return nested_vmx_failInvalid(vcpu);
8373 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8374 if (is_error_page(page))
8375 return nested_vmx_failInvalid(vcpu);
8377 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
8379 kvm_release_page_clean(page);
8380 return nested_vmx_failInvalid(vcpu);
8383 kvm_release_page_clean(page);
8385 vmx->nested.vmxon_ptr = vmptr;
8386 ret = enter_vmx_operation(vcpu);
8390 return nested_vmx_succeed(vcpu);
8394 * Intel's VMX Instruction Reference specifies a common set of prerequisites
8395 * for running VMX instructions (except VMXON, whose prerequisites are
8396 * slightly different). It also specifies what exception to inject otherwise.
8397 * Note that many of these exceptions have priority over VM exits, so they
8398 * don't have to be checked again here.
8400 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
8402 if (!to_vmx(vcpu)->nested.vmxon) {
8403 kvm_queue_exception(vcpu, UD_VECTOR);
8407 if (vmx_get_cpl(vcpu)) {
8408 kvm_inject_gp(vcpu, 0);
8415 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
8417 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
8418 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8421 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
8423 if (vmx->nested.current_vmptr == -1ull)
8426 if (enable_shadow_vmcs) {
8427 /* copy to memory all shadowed fields in case
8428 they were modified */
8429 copy_shadow_to_vmcs12(vmx);
8430 vmx->nested.sync_shadow_vmcs = false;
8431 vmx_disable_shadow_vmcs(vmx);
8433 vmx->nested.posted_intr_nv = -1;
8435 /* Flush VMCS12 to guest memory */
8436 kvm_vcpu_write_guest_page(&vmx->vcpu,
8437 vmx->nested.current_vmptr >> PAGE_SHIFT,
8438 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
8440 vmx->nested.current_vmptr = -1ull;
8444 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
8445 * just stops using VMX.
8447 static void free_nested(struct vcpu_vmx *vmx)
8449 if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
8452 vmx->nested.vmxon = false;
8453 vmx->nested.smm.vmxon = false;
8454 free_vpid(vmx->nested.vpid02);
8455 vmx->nested.posted_intr_nv = -1;
8456 vmx->nested.current_vmptr = -1ull;
8457 if (enable_shadow_vmcs) {
8458 vmx_disable_shadow_vmcs(vmx);
8459 vmcs_clear(vmx->vmcs01.shadow_vmcs);
8460 free_vmcs(vmx->vmcs01.shadow_vmcs);
8461 vmx->vmcs01.shadow_vmcs = NULL;
8463 kfree(vmx->nested.cached_vmcs12);
8464 kfree(vmx->nested.cached_shadow_vmcs12);
8465 /* Unpin physical memory we referred to in the vmcs02 */
8466 if (vmx->nested.apic_access_page) {
8467 kvm_release_page_dirty(vmx->nested.apic_access_page);
8468 vmx->nested.apic_access_page = NULL;
8470 if (vmx->nested.virtual_apic_page) {
8471 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
8472 vmx->nested.virtual_apic_page = NULL;
8474 if (vmx->nested.pi_desc_page) {
8475 kunmap(vmx->nested.pi_desc_page);
8476 kvm_release_page_dirty(vmx->nested.pi_desc_page);
8477 vmx->nested.pi_desc_page = NULL;
8478 vmx->nested.pi_desc = NULL;
8481 free_loaded_vmcs(&vmx->nested.vmcs02);
8484 /* Emulate the VMXOFF instruction */
8485 static int handle_vmoff(struct kvm_vcpu *vcpu)
8487 if (!nested_vmx_check_permission(vcpu))
8489 free_nested(to_vmx(vcpu));
8490 return nested_vmx_succeed(vcpu);
8493 /* Emulate the VMCLEAR instruction */
8494 static int handle_vmclear(struct kvm_vcpu *vcpu)
8496 struct vcpu_vmx *vmx = to_vmx(vcpu);
8500 if (!nested_vmx_check_permission(vcpu))
8503 if (nested_vmx_get_vmptr(vcpu, &vmptr))
8506 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu)))
8507 return nested_vmx_failValid(vcpu,
8508 VMXERR_VMCLEAR_INVALID_ADDRESS);
8510 if (vmptr == vmx->nested.vmxon_ptr)
8511 return nested_vmx_failValid(vcpu,
8512 VMXERR_VMCLEAR_VMXON_POINTER);
8514 if (vmptr == vmx->nested.current_vmptr)
8515 nested_release_vmcs12(vmx);
8517 kvm_vcpu_write_guest(vcpu,
8518 vmptr + offsetof(struct vmcs12, launch_state),
8519 &zero, sizeof(zero));
8521 return nested_vmx_succeed(vcpu);
8524 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
8526 /* Emulate the VMLAUNCH instruction */
8527 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
8529 return nested_vmx_run(vcpu, true);
8532 /* Emulate the VMRESUME instruction */
8533 static int handle_vmresume(struct kvm_vcpu *vcpu)
8536 return nested_vmx_run(vcpu, false);
8540 * Read a vmcs12 field. Since these can have varying lengths and we return
8541 * one type, we chose the biggest type (u64) and zero-extend the return value
8542 * to that size. Note that the caller, handle_vmread, might need to use only
8543 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
8544 * 64-bit fields are to be returned).
8546 static inline int vmcs12_read_any(struct vmcs12 *vmcs12,
8547 unsigned long field, u64 *ret)
8549 short offset = vmcs_field_to_offset(field);
8555 p = (char *)vmcs12 + offset;
8557 switch (vmcs_field_width(field)) {
8558 case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8559 *ret = *((natural_width *)p);
8561 case VMCS_FIELD_WIDTH_U16:
8564 case VMCS_FIELD_WIDTH_U32:
8567 case VMCS_FIELD_WIDTH_U64:
8577 static inline int vmcs12_write_any(struct vmcs12 *vmcs12,
8578 unsigned long field, u64 field_value){
8579 short offset = vmcs_field_to_offset(field);
8580 char *p = (char *)vmcs12 + offset;
8584 switch (vmcs_field_width(field)) {
8585 case VMCS_FIELD_WIDTH_U16:
8586 *(u16 *)p = field_value;
8588 case VMCS_FIELD_WIDTH_U32:
8589 *(u32 *)p = field_value;
8591 case VMCS_FIELD_WIDTH_U64:
8592 *(u64 *)p = field_value;
8594 case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8595 *(natural_width *)p = field_value;
8605 * Copy the writable VMCS shadow fields back to the VMCS12, in case
8606 * they have been modified by the L1 guest. Note that the "read-only"
8607 * VM-exit information fields are actually writable if the vCPU is
8608 * configured to support "VMWRITE to any supported field in the VMCS."
8610 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
8612 const u16 *fields[] = {
8613 shadow_read_write_fields,
8614 shadow_read_only_fields
8616 const int max_fields[] = {
8617 max_shadow_read_write_fields,
8618 max_shadow_read_only_fields
8621 unsigned long field;
8623 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8627 vmcs_load(shadow_vmcs);
8629 for (q = 0; q < ARRAY_SIZE(fields); q++) {
8630 for (i = 0; i < max_fields[q]; i++) {
8631 field = fields[q][i];
8632 field_value = __vmcs_readl(field);
8633 vmcs12_write_any(get_vmcs12(&vmx->vcpu), field, field_value);
8636 * Skip the VM-exit information fields if they are read-only.
8638 if (!nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
8642 vmcs_clear(shadow_vmcs);
8643 vmcs_load(vmx->loaded_vmcs->vmcs);
8648 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
8650 const u16 *fields[] = {
8651 shadow_read_write_fields,
8652 shadow_read_only_fields
8654 const int max_fields[] = {
8655 max_shadow_read_write_fields,
8656 max_shadow_read_only_fields
8659 unsigned long field;
8660 u64 field_value = 0;
8661 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8663 vmcs_load(shadow_vmcs);
8665 for (q = 0; q < ARRAY_SIZE(fields); q++) {
8666 for (i = 0; i < max_fields[q]; i++) {
8667 field = fields[q][i];
8668 vmcs12_read_any(get_vmcs12(&vmx->vcpu), field, &field_value);
8669 __vmcs_writel(field, field_value);
8673 vmcs_clear(shadow_vmcs);
8674 vmcs_load(vmx->loaded_vmcs->vmcs);
8677 static int handle_vmread(struct kvm_vcpu *vcpu)
8679 unsigned long field;
8681 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8682 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8684 struct vmcs12 *vmcs12;
8686 if (!nested_vmx_check_permission(vcpu))
8689 if (to_vmx(vcpu)->nested.current_vmptr == -1ull)
8690 return nested_vmx_failInvalid(vcpu);
8692 if (!is_guest_mode(vcpu))
8693 vmcs12 = get_vmcs12(vcpu);
8696 * When vmcs->vmcs_link_pointer is -1ull, any VMREAD
8697 * to shadowed-field sets the ALU flags for VMfailInvalid.
8699 if (get_vmcs12(vcpu)->vmcs_link_pointer == -1ull)
8700 return nested_vmx_failInvalid(vcpu);
8701 vmcs12 = get_shadow_vmcs12(vcpu);
8704 /* Decode instruction info and find the field to read */
8705 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8706 /* Read the field, zero-extended to a u64 field_value */
8707 if (vmcs12_read_any(vmcs12, field, &field_value) < 0)
8708 return nested_vmx_failValid(vcpu,
8709 VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8712 * Now copy part of this value to register or memory, as requested.
8713 * Note that the number of bits actually copied is 32 or 64 depending
8714 * on the guest's mode (32 or 64 bit), not on the given field's length.
8716 if (vmx_instruction_info & (1u << 10)) {
8717 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
8720 if (get_vmx_mem_address(vcpu, exit_qualification,
8721 vmx_instruction_info, true, &gva))
8723 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
8724 kvm_write_guest_virt_system(vcpu, gva, &field_value,
8725 (is_long_mode(vcpu) ? 8 : 4), NULL);
8728 return nested_vmx_succeed(vcpu);
8732 static int handle_vmwrite(struct kvm_vcpu *vcpu)
8734 unsigned long field;
8736 struct vcpu_vmx *vmx = to_vmx(vcpu);
8737 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8738 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8740 /* The value to write might be 32 or 64 bits, depending on L1's long
8741 * mode, and eventually we need to write that into a field of several
8742 * possible lengths. The code below first zero-extends the value to 64
8743 * bit (field_value), and then copies only the appropriate number of
8744 * bits into the vmcs12 field.
8746 u64 field_value = 0;
8747 struct x86_exception e;
8748 struct vmcs12 *vmcs12;
8750 if (!nested_vmx_check_permission(vcpu))
8753 if (vmx->nested.current_vmptr == -1ull)
8754 return nested_vmx_failInvalid(vcpu);
8756 if (vmx_instruction_info & (1u << 10))
8757 field_value = kvm_register_readl(vcpu,
8758 (((vmx_instruction_info) >> 3) & 0xf));
8760 if (get_vmx_mem_address(vcpu, exit_qualification,
8761 vmx_instruction_info, false, &gva))
8763 if (kvm_read_guest_virt(vcpu, gva, &field_value,
8764 (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
8765 kvm_inject_page_fault(vcpu, &e);
8771 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8773 * If the vCPU supports "VMWRITE to any supported field in the
8774 * VMCS," then the "read-only" fields are actually read/write.
8776 if (vmcs_field_readonly(field) &&
8777 !nested_cpu_has_vmwrite_any_field(vcpu))
8778 return nested_vmx_failValid(vcpu,
8779 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
8781 if (!is_guest_mode(vcpu))
8782 vmcs12 = get_vmcs12(vcpu);
8785 * When vmcs->vmcs_link_pointer is -1ull, any VMWRITE
8786 * to shadowed-field sets the ALU flags for VMfailInvalid.
8788 if (get_vmcs12(vcpu)->vmcs_link_pointer == -1ull)
8789 return nested_vmx_failInvalid(vcpu);
8790 vmcs12 = get_shadow_vmcs12(vcpu);
8793 if (vmcs12_write_any(vmcs12, field, field_value) < 0)
8794 return nested_vmx_failValid(vcpu,
8795 VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8798 * Do not track vmcs12 dirty-state if in guest-mode
8799 * as we actually dirty shadow vmcs12 instead of vmcs12.
8801 if (!is_guest_mode(vcpu)) {
8803 #define SHADOW_FIELD_RW(x) case x:
8804 #include "vmx_shadow_fields.h"
8806 * The fields that can be updated by L1 without a vmexit are
8807 * always updated in the vmcs02, the others go down the slow
8808 * path of prepare_vmcs02.
8812 vmx->nested.dirty_vmcs12 = true;
8817 return nested_vmx_succeed(vcpu);
8820 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
8822 vmx->nested.current_vmptr = vmptr;
8823 if (enable_shadow_vmcs) {
8824 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
8825 SECONDARY_EXEC_SHADOW_VMCS);
8826 vmcs_write64(VMCS_LINK_POINTER,
8827 __pa(vmx->vmcs01.shadow_vmcs));
8828 vmx->nested.sync_shadow_vmcs = true;
8830 vmx->nested.dirty_vmcs12 = true;
8833 /* Emulate the VMPTRLD instruction */
8834 static int handle_vmptrld(struct kvm_vcpu *vcpu)
8836 struct vcpu_vmx *vmx = to_vmx(vcpu);
8839 if (!nested_vmx_check_permission(vcpu))
8842 if (nested_vmx_get_vmptr(vcpu, &vmptr))
8845 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu)))
8846 return nested_vmx_failValid(vcpu,
8847 VMXERR_VMPTRLD_INVALID_ADDRESS);
8849 if (vmptr == vmx->nested.vmxon_ptr)
8850 return nested_vmx_failValid(vcpu,
8851 VMXERR_VMPTRLD_VMXON_POINTER);
8853 if (vmx->nested.current_vmptr != vmptr) {
8854 struct vmcs12 *new_vmcs12;
8856 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8857 if (is_error_page(page))
8858 return nested_vmx_failInvalid(vcpu);
8860 new_vmcs12 = kmap(page);
8861 if (new_vmcs12->hdr.revision_id != VMCS12_REVISION ||
8862 (new_vmcs12->hdr.shadow_vmcs &&
8863 !nested_cpu_has_vmx_shadow_vmcs(vcpu))) {
8865 kvm_release_page_clean(page);
8866 return nested_vmx_failValid(vcpu,
8867 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
8870 nested_release_vmcs12(vmx);
8872 * Load VMCS12 from guest memory since it is not already
8875 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
8877 kvm_release_page_clean(page);
8879 set_current_vmptr(vmx, vmptr);
8882 return nested_vmx_succeed(vcpu);
8885 /* Emulate the VMPTRST instruction */
8886 static int handle_vmptrst(struct kvm_vcpu *vcpu)
8888 unsigned long exit_qual = vmcs_readl(EXIT_QUALIFICATION);
8889 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8890 gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr;
8891 struct x86_exception e;
8894 if (!nested_vmx_check_permission(vcpu))
8897 if (get_vmx_mem_address(vcpu, exit_qual, instr_info, true, &gva))
8899 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
8900 if (kvm_write_guest_virt_system(vcpu, gva, (void *)¤t_vmptr,
8901 sizeof(gpa_t), &e)) {
8902 kvm_inject_page_fault(vcpu, &e);
8905 return nested_vmx_succeed(vcpu);
8908 /* Emulate the INVEPT instruction */
8909 static int handle_invept(struct kvm_vcpu *vcpu)
8911 struct vcpu_vmx *vmx = to_vmx(vcpu);
8912 u32 vmx_instruction_info, types;
8915 struct x86_exception e;
8920 if (!(vmx->nested.msrs.secondary_ctls_high &
8921 SECONDARY_EXEC_ENABLE_EPT) ||
8922 !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
8923 kvm_queue_exception(vcpu, UD_VECTOR);
8927 if (!nested_vmx_check_permission(vcpu))
8930 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8931 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8933 types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
8935 if (type >= 32 || !(types & (1 << type)))
8936 return nested_vmx_failValid(vcpu,
8937 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8939 /* According to the Intel VMX instruction reference, the memory
8940 * operand is read even if it isn't needed (e.g., for type==global)
8942 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8943 vmx_instruction_info, false, &gva))
8945 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8946 kvm_inject_page_fault(vcpu, &e);
8951 case VMX_EPT_EXTENT_GLOBAL:
8953 * TODO: track mappings and invalidate
8954 * single context requests appropriately
8956 case VMX_EPT_EXTENT_CONTEXT:
8957 kvm_mmu_sync_roots(vcpu);
8958 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
8965 return nested_vmx_succeed(vcpu);
8968 static u16 nested_get_vpid02(struct kvm_vcpu *vcpu)
8970 struct vcpu_vmx *vmx = to_vmx(vcpu);
8972 return vmx->nested.vpid02 ? vmx->nested.vpid02 : vmx->vpid;
8975 static int handle_invvpid(struct kvm_vcpu *vcpu)
8977 struct vcpu_vmx *vmx = to_vmx(vcpu);
8978 u32 vmx_instruction_info;
8979 unsigned long type, types;
8981 struct x86_exception e;
8988 if (!(vmx->nested.msrs.secondary_ctls_high &
8989 SECONDARY_EXEC_ENABLE_VPID) ||
8990 !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
8991 kvm_queue_exception(vcpu, UD_VECTOR);
8995 if (!nested_vmx_check_permission(vcpu))
8998 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8999 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
9001 types = (vmx->nested.msrs.vpid_caps &
9002 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
9004 if (type >= 32 || !(types & (1 << type)))
9005 return nested_vmx_failValid(vcpu,
9006 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9008 /* according to the intel vmx instruction reference, the memory
9009 * operand is read even if it isn't needed (e.g., for type==global)
9011 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
9012 vmx_instruction_info, false, &gva))
9014 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
9015 kvm_inject_page_fault(vcpu, &e);
9018 if (operand.vpid >> 16)
9019 return nested_vmx_failValid(vcpu,
9020 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9022 vpid02 = nested_get_vpid02(vcpu);
9024 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
9025 if (!operand.vpid ||
9026 is_noncanonical_address(operand.gla, vcpu))
9027 return nested_vmx_failValid(vcpu,
9028 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9029 if (cpu_has_vmx_invvpid_individual_addr()) {
9030 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR,
9031 vpid02, operand.gla);
9033 __vmx_flush_tlb(vcpu, vpid02, false);
9035 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
9036 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
9038 return nested_vmx_failValid(vcpu,
9039 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9040 __vmx_flush_tlb(vcpu, vpid02, false);
9042 case VMX_VPID_EXTENT_ALL_CONTEXT:
9043 __vmx_flush_tlb(vcpu, vpid02, false);
9047 return kvm_skip_emulated_instruction(vcpu);
9050 return nested_vmx_succeed(vcpu);
9053 static int handle_invpcid(struct kvm_vcpu *vcpu)
9055 u32 vmx_instruction_info;
9059 struct x86_exception e;
9061 unsigned long roots_to_free = 0;
9067 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
9068 kvm_queue_exception(vcpu, UD_VECTOR);
9072 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9073 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
9076 kvm_inject_gp(vcpu, 0);
9080 /* According to the Intel instruction reference, the memory operand
9081 * is read even if it isn't needed (e.g., for type==all)
9083 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
9084 vmx_instruction_info, false, &gva))
9087 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
9088 kvm_inject_page_fault(vcpu, &e);
9092 if (operand.pcid >> 12 != 0) {
9093 kvm_inject_gp(vcpu, 0);
9097 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
9100 case INVPCID_TYPE_INDIV_ADDR:
9101 if ((!pcid_enabled && (operand.pcid != 0)) ||
9102 is_noncanonical_address(operand.gla, vcpu)) {
9103 kvm_inject_gp(vcpu, 0);
9106 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
9107 return kvm_skip_emulated_instruction(vcpu);
9109 case INVPCID_TYPE_SINGLE_CTXT:
9110 if (!pcid_enabled && (operand.pcid != 0)) {
9111 kvm_inject_gp(vcpu, 0);
9115 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
9116 kvm_mmu_sync_roots(vcpu);
9117 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
9120 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
9121 if (kvm_get_pcid(vcpu, vcpu->arch.mmu.prev_roots[i].cr3)
9123 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
9125 kvm_mmu_free_roots(vcpu, roots_to_free);
9127 * If neither the current cr3 nor any of the prev_roots use the
9128 * given PCID, then nothing needs to be done here because a
9129 * resync will happen anyway before switching to any other CR3.
9132 return kvm_skip_emulated_instruction(vcpu);
9134 case INVPCID_TYPE_ALL_NON_GLOBAL:
9136 * Currently, KVM doesn't mark global entries in the shadow
9137 * page tables, so a non-global flush just degenerates to a
9138 * global flush. If needed, we could optimize this later by
9139 * keeping track of global entries in shadow page tables.
9143 case INVPCID_TYPE_ALL_INCL_GLOBAL:
9144 kvm_mmu_unload(vcpu);
9145 return kvm_skip_emulated_instruction(vcpu);
9148 BUG(); /* We have already checked above that type <= 3 */
9152 static int handle_pml_full(struct kvm_vcpu *vcpu)
9154 unsigned long exit_qualification;
9156 trace_kvm_pml_full(vcpu->vcpu_id);
9158 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9161 * PML buffer FULL happened while executing iret from NMI,
9162 * "blocked by NMI" bit has to be set before next VM entry.
9164 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
9166 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
9167 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9168 GUEST_INTR_STATE_NMI);
9171 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
9172 * here.., and there's no userspace involvement needed for PML.
9177 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
9179 if (!to_vmx(vcpu)->req_immediate_exit)
9180 kvm_lapic_expired_hv_timer(vcpu);
9184 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
9186 struct vcpu_vmx *vmx = to_vmx(vcpu);
9187 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9189 /* Check for memory type validity */
9190 switch (address & VMX_EPTP_MT_MASK) {
9191 case VMX_EPTP_MT_UC:
9192 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))
9195 case VMX_EPTP_MT_WB:
9196 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))
9203 /* only 4 levels page-walk length are valid */
9204 if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
9207 /* Reserved bits should not be set */
9208 if (address >> maxphyaddr || ((address >> 7) & 0x1f))
9211 /* AD, if set, should be supported */
9212 if (address & VMX_EPTP_AD_ENABLE_BIT) {
9213 if (!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))
9220 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
9221 struct vmcs12 *vmcs12)
9223 u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
9225 bool accessed_dirty;
9226 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
9228 if (!nested_cpu_has_eptp_switching(vmcs12) ||
9229 !nested_cpu_has_ept(vmcs12))
9232 if (index >= VMFUNC_EPTP_ENTRIES)
9236 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
9237 &address, index * 8, 8))
9240 accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
9243 * If the (L2) guest does a vmfunc to the currently
9244 * active ept pointer, we don't have to do anything else
9246 if (vmcs12->ept_pointer != address) {
9247 if (!valid_ept_address(vcpu, address))
9250 kvm_mmu_unload(vcpu);
9251 mmu->ept_ad = accessed_dirty;
9252 mmu->base_role.ad_disabled = !accessed_dirty;
9253 vmcs12->ept_pointer = address;
9255 * TODO: Check what's the correct approach in case
9256 * mmu reload fails. Currently, we just let the next
9257 * reload potentially fail
9259 kvm_mmu_reload(vcpu);
9265 static int handle_vmfunc(struct kvm_vcpu *vcpu)
9267 struct vcpu_vmx *vmx = to_vmx(vcpu);
9268 struct vmcs12 *vmcs12;
9269 u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
9272 * VMFUNC is only supported for nested guests, but we always enable the
9273 * secondary control for simplicity; for non-nested mode, fake that we
9274 * didn't by injecting #UD.
9276 if (!is_guest_mode(vcpu)) {
9277 kvm_queue_exception(vcpu, UD_VECTOR);
9281 vmcs12 = get_vmcs12(vcpu);
9282 if ((vmcs12->vm_function_control & (1 << function)) == 0)
9287 if (nested_vmx_eptp_switching(vcpu, vmcs12))
9293 return kvm_skip_emulated_instruction(vcpu);
9296 nested_vmx_vmexit(vcpu, vmx->exit_reason,
9297 vmcs_read32(VM_EXIT_INTR_INFO),
9298 vmcs_readl(EXIT_QUALIFICATION));
9302 static int handle_encls(struct kvm_vcpu *vcpu)
9305 * SGX virtualization is not yet supported. There is no software
9306 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
9307 * to prevent the guest from executing ENCLS.
9309 kvm_queue_exception(vcpu, UD_VECTOR);
9314 * The exit handlers return 1 if the exit was handled fully and guest execution
9315 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
9316 * to be done to userspace and return 0.
9318 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
9319 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
9320 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
9321 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
9322 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
9323 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
9324 [EXIT_REASON_CR_ACCESS] = handle_cr,
9325 [EXIT_REASON_DR_ACCESS] = handle_dr,
9326 [EXIT_REASON_CPUID] = handle_cpuid,
9327 [EXIT_REASON_MSR_READ] = handle_rdmsr,
9328 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
9329 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
9330 [EXIT_REASON_HLT] = handle_halt,
9331 [EXIT_REASON_INVD] = handle_invd,
9332 [EXIT_REASON_INVLPG] = handle_invlpg,
9333 [EXIT_REASON_RDPMC] = handle_rdpmc,
9334 [EXIT_REASON_VMCALL] = handle_vmcall,
9335 [EXIT_REASON_VMCLEAR] = handle_vmclear,
9336 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
9337 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
9338 [EXIT_REASON_VMPTRST] = handle_vmptrst,
9339 [EXIT_REASON_VMREAD] = handle_vmread,
9340 [EXIT_REASON_VMRESUME] = handle_vmresume,
9341 [EXIT_REASON_VMWRITE] = handle_vmwrite,
9342 [EXIT_REASON_VMOFF] = handle_vmoff,
9343 [EXIT_REASON_VMON] = handle_vmon,
9344 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
9345 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
9346 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
9347 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
9348 [EXIT_REASON_WBINVD] = handle_wbinvd,
9349 [EXIT_REASON_XSETBV] = handle_xsetbv,
9350 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
9351 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
9352 [EXIT_REASON_GDTR_IDTR] = handle_desc,
9353 [EXIT_REASON_LDTR_TR] = handle_desc,
9354 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
9355 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
9356 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
9357 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
9358 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
9359 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
9360 [EXIT_REASON_INVEPT] = handle_invept,
9361 [EXIT_REASON_INVVPID] = handle_invvpid,
9362 [EXIT_REASON_RDRAND] = handle_invalid_op,
9363 [EXIT_REASON_RDSEED] = handle_invalid_op,
9364 [EXIT_REASON_XSAVES] = handle_xsaves,
9365 [EXIT_REASON_XRSTORS] = handle_xrstors,
9366 [EXIT_REASON_PML_FULL] = handle_pml_full,
9367 [EXIT_REASON_INVPCID] = handle_invpcid,
9368 [EXIT_REASON_VMFUNC] = handle_vmfunc,
9369 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
9370 [EXIT_REASON_ENCLS] = handle_encls,
9373 static const int kvm_vmx_max_exit_handlers =
9374 ARRAY_SIZE(kvm_vmx_exit_handlers);
9376 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
9377 struct vmcs12 *vmcs12)
9379 unsigned long exit_qualification;
9380 gpa_t bitmap, last_bitmap;
9385 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9386 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
9388 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9390 port = exit_qualification >> 16;
9391 size = (exit_qualification & 7) + 1;
9393 last_bitmap = (gpa_t)-1;
9398 bitmap = vmcs12->io_bitmap_a;
9399 else if (port < 0x10000)
9400 bitmap = vmcs12->io_bitmap_b;
9403 bitmap += (port & 0x7fff) / 8;
9405 if (last_bitmap != bitmap)
9406 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
9408 if (b & (1 << (port & 7)))
9413 last_bitmap = bitmap;
9420 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
9421 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
9422 * disinterest in the current event (read or write a specific MSR) by using an
9423 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
9425 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
9426 struct vmcs12 *vmcs12, u32 exit_reason)
9428 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
9431 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9435 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
9436 * for the four combinations of read/write and low/high MSR numbers.
9437 * First we need to figure out which of the four to use:
9439 bitmap = vmcs12->msr_bitmap;
9440 if (exit_reason == EXIT_REASON_MSR_WRITE)
9442 if (msr_index >= 0xc0000000) {
9443 msr_index -= 0xc0000000;
9447 /* Then read the msr_index'th bit from this bitmap: */
9448 if (msr_index < 1024*8) {
9450 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
9452 return 1 & (b >> (msr_index & 7));
9454 return true; /* let L1 handle the wrong parameter */
9458 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
9459 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
9460 * intercept (via guest_host_mask etc.) the current event.
9462 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
9463 struct vmcs12 *vmcs12)
9465 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9466 int cr = exit_qualification & 15;
9470 switch ((exit_qualification >> 4) & 3) {
9471 case 0: /* mov to cr */
9472 reg = (exit_qualification >> 8) & 15;
9473 val = kvm_register_readl(vcpu, reg);
9476 if (vmcs12->cr0_guest_host_mask &
9477 (val ^ vmcs12->cr0_read_shadow))
9481 if ((vmcs12->cr3_target_count >= 1 &&
9482 vmcs12->cr3_target_value0 == val) ||
9483 (vmcs12->cr3_target_count >= 2 &&
9484 vmcs12->cr3_target_value1 == val) ||
9485 (vmcs12->cr3_target_count >= 3 &&
9486 vmcs12->cr3_target_value2 == val) ||
9487 (vmcs12->cr3_target_count >= 4 &&
9488 vmcs12->cr3_target_value3 == val))
9490 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
9494 if (vmcs12->cr4_guest_host_mask &
9495 (vmcs12->cr4_read_shadow ^ val))
9499 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
9505 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
9506 (vmcs12->cr0_read_shadow & X86_CR0_TS))
9509 case 1: /* mov from cr */
9512 if (vmcs12->cpu_based_vm_exec_control &
9513 CPU_BASED_CR3_STORE_EXITING)
9517 if (vmcs12->cpu_based_vm_exec_control &
9518 CPU_BASED_CR8_STORE_EXITING)
9525 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
9526 * cr0. Other attempted changes are ignored, with no exit.
9528 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
9529 if (vmcs12->cr0_guest_host_mask & 0xe &
9530 (val ^ vmcs12->cr0_read_shadow))
9532 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
9533 !(vmcs12->cr0_read_shadow & 0x1) &&
9541 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu,
9542 struct vmcs12 *vmcs12, gpa_t bitmap)
9544 u32 vmx_instruction_info;
9545 unsigned long field;
9548 if (!nested_cpu_has_shadow_vmcs(vmcs12))
9551 /* Decode instruction info and find the field to access */
9552 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9553 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
9555 /* Out-of-range fields always cause a VM exit from L2 to L1 */
9559 if (kvm_vcpu_read_guest(vcpu, bitmap + field/8, &b, 1))
9562 return 1 & (b >> (field & 7));
9566 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
9567 * should handle it ourselves in L0 (and then continue L2). Only call this
9568 * when in is_guest_mode (L2).
9570 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
9572 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9573 struct vcpu_vmx *vmx = to_vmx(vcpu);
9574 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9576 if (vmx->nested.nested_run_pending)
9579 if (unlikely(vmx->fail)) {
9580 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
9581 vmcs_read32(VM_INSTRUCTION_ERROR));
9586 * The host physical addresses of some pages of guest memory
9587 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
9588 * Page). The CPU may write to these pages via their host
9589 * physical address while L2 is running, bypassing any
9590 * address-translation-based dirty tracking (e.g. EPT write
9593 * Mark them dirty on every exit from L2 to prevent them from
9594 * getting out of sync with dirty tracking.
9596 nested_mark_vmcs12_pages_dirty(vcpu);
9598 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
9599 vmcs_readl(EXIT_QUALIFICATION),
9600 vmx->idt_vectoring_info,
9602 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9605 switch (exit_reason) {
9606 case EXIT_REASON_EXCEPTION_NMI:
9607 if (is_nmi(intr_info))
9609 else if (is_page_fault(intr_info))
9610 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
9611 else if (is_debug(intr_info) &&
9613 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
9615 else if (is_breakpoint(intr_info) &&
9616 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
9618 return vmcs12->exception_bitmap &
9619 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
9620 case EXIT_REASON_EXTERNAL_INTERRUPT:
9622 case EXIT_REASON_TRIPLE_FAULT:
9624 case EXIT_REASON_PENDING_INTERRUPT:
9625 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
9626 case EXIT_REASON_NMI_WINDOW:
9627 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
9628 case EXIT_REASON_TASK_SWITCH:
9630 case EXIT_REASON_CPUID:
9632 case EXIT_REASON_HLT:
9633 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
9634 case EXIT_REASON_INVD:
9636 case EXIT_REASON_INVLPG:
9637 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9638 case EXIT_REASON_RDPMC:
9639 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
9640 case EXIT_REASON_RDRAND:
9641 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
9642 case EXIT_REASON_RDSEED:
9643 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
9644 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
9645 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
9646 case EXIT_REASON_VMREAD:
9647 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
9648 vmcs12->vmread_bitmap);
9649 case EXIT_REASON_VMWRITE:
9650 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
9651 vmcs12->vmwrite_bitmap);
9652 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
9653 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
9654 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMRESUME:
9655 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
9656 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
9658 * VMX instructions trap unconditionally. This allows L1 to
9659 * emulate them for its L2 guest, i.e., allows 3-level nesting!
9662 case EXIT_REASON_CR_ACCESS:
9663 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
9664 case EXIT_REASON_DR_ACCESS:
9665 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
9666 case EXIT_REASON_IO_INSTRUCTION:
9667 return nested_vmx_exit_handled_io(vcpu, vmcs12);
9668 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
9669 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
9670 case EXIT_REASON_MSR_READ:
9671 case EXIT_REASON_MSR_WRITE:
9672 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
9673 case EXIT_REASON_INVALID_STATE:
9675 case EXIT_REASON_MWAIT_INSTRUCTION:
9676 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
9677 case EXIT_REASON_MONITOR_TRAP_FLAG:
9678 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
9679 case EXIT_REASON_MONITOR_INSTRUCTION:
9680 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
9681 case EXIT_REASON_PAUSE_INSTRUCTION:
9682 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
9683 nested_cpu_has2(vmcs12,
9684 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
9685 case EXIT_REASON_MCE_DURING_VMENTRY:
9687 case EXIT_REASON_TPR_BELOW_THRESHOLD:
9688 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
9689 case EXIT_REASON_APIC_ACCESS:
9690 case EXIT_REASON_APIC_WRITE:
9691 case EXIT_REASON_EOI_INDUCED:
9693 * The controls for "virtualize APIC accesses," "APIC-
9694 * register virtualization," and "virtual-interrupt
9695 * delivery" only come from vmcs12.
9698 case EXIT_REASON_EPT_VIOLATION:
9700 * L0 always deals with the EPT violation. If nested EPT is
9701 * used, and the nested mmu code discovers that the address is
9702 * missing in the guest EPT table (EPT12), the EPT violation
9703 * will be injected with nested_ept_inject_page_fault()
9706 case EXIT_REASON_EPT_MISCONFIG:
9708 * L2 never uses directly L1's EPT, but rather L0's own EPT
9709 * table (shadow on EPT) or a merged EPT table that L0 built
9710 * (EPT on EPT). So any problems with the structure of the
9711 * table is L0's fault.
9714 case EXIT_REASON_INVPCID:
9716 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
9717 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9718 case EXIT_REASON_WBINVD:
9719 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
9720 case EXIT_REASON_XSETBV:
9722 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
9724 * This should never happen, since it is not possible to
9725 * set XSS to a non-zero value---neither in L1 nor in L2.
9726 * If if it were, XSS would have to be checked against
9727 * the XSS exit bitmap in vmcs12.
9729 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
9730 case EXIT_REASON_PREEMPTION_TIMER:
9732 case EXIT_REASON_PML_FULL:
9733 /* We emulate PML support to L1. */
9735 case EXIT_REASON_VMFUNC:
9736 /* VM functions are emulated through L2->L0 vmexits. */
9738 case EXIT_REASON_ENCLS:
9739 /* SGX is never exposed to L1 */
9746 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
9748 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9751 * At this point, the exit interruption info in exit_intr_info
9752 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
9753 * we need to query the in-kernel LAPIC.
9755 WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
9756 if ((exit_intr_info &
9757 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9758 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
9759 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9760 vmcs12->vm_exit_intr_error_code =
9761 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9764 nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
9765 vmcs_readl(EXIT_QUALIFICATION));
9769 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
9771 *info1 = vmcs_readl(EXIT_QUALIFICATION);
9772 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
9775 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
9778 __free_page(vmx->pml_pg);
9783 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
9785 struct vcpu_vmx *vmx = to_vmx(vcpu);
9789 pml_idx = vmcs_read16(GUEST_PML_INDEX);
9791 /* Do nothing if PML buffer is empty */
9792 if (pml_idx == (PML_ENTITY_NUM - 1))
9795 /* PML index always points to next available PML buffer entity */
9796 if (pml_idx >= PML_ENTITY_NUM)
9801 pml_buf = page_address(vmx->pml_pg);
9802 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
9805 gpa = pml_buf[pml_idx];
9806 WARN_ON(gpa & (PAGE_SIZE - 1));
9807 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
9810 /* reset PML index */
9811 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
9815 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
9816 * Called before reporting dirty_bitmap to userspace.
9818 static void kvm_flush_pml_buffers(struct kvm *kvm)
9821 struct kvm_vcpu *vcpu;
9823 * We only need to kick vcpu out of guest mode here, as PML buffer
9824 * is flushed at beginning of all VMEXITs, and it's obvious that only
9825 * vcpus running in guest are possible to have unflushed GPAs in PML
9828 kvm_for_each_vcpu(i, vcpu, kvm)
9829 kvm_vcpu_kick(vcpu);
9832 static void vmx_dump_sel(char *name, uint32_t sel)
9834 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
9835 name, vmcs_read16(sel),
9836 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
9837 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
9838 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
9841 static void vmx_dump_dtsel(char *name, uint32_t limit)
9843 pr_err("%s limit=0x%08x, base=0x%016lx\n",
9844 name, vmcs_read32(limit),
9845 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
9848 static void dump_vmcs(void)
9850 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
9851 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
9852 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
9853 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
9854 u32 secondary_exec_control = 0;
9855 unsigned long cr4 = vmcs_readl(GUEST_CR4);
9856 u64 efer = vmcs_read64(GUEST_IA32_EFER);
9859 if (cpu_has_secondary_exec_ctrls())
9860 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9862 pr_err("*** Guest State ***\n");
9863 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9864 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
9865 vmcs_readl(CR0_GUEST_HOST_MASK));
9866 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9867 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
9868 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
9869 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
9870 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
9872 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
9873 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
9874 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
9875 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
9877 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
9878 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
9879 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
9880 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
9881 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9882 vmcs_readl(GUEST_SYSENTER_ESP),
9883 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
9884 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
9885 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
9886 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
9887 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
9888 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
9889 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
9890 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
9891 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
9892 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
9893 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
9894 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
9895 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
9896 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9897 efer, vmcs_read64(GUEST_IA32_PAT));
9898 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
9899 vmcs_read64(GUEST_IA32_DEBUGCTL),
9900 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
9901 if (cpu_has_load_perf_global_ctrl &&
9902 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
9903 pr_err("PerfGlobCtl = 0x%016llx\n",
9904 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
9905 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
9906 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
9907 pr_err("Interruptibility = %08x ActivityState = %08x\n",
9908 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
9909 vmcs_read32(GUEST_ACTIVITY_STATE));
9910 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
9911 pr_err("InterruptStatus = %04x\n",
9912 vmcs_read16(GUEST_INTR_STATUS));
9914 pr_err("*** Host State ***\n");
9915 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
9916 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
9917 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9918 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
9919 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
9920 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
9921 vmcs_read16(HOST_TR_SELECTOR));
9922 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9923 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
9924 vmcs_readl(HOST_TR_BASE));
9925 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9926 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
9927 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9928 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
9929 vmcs_readl(HOST_CR4));
9930 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9931 vmcs_readl(HOST_IA32_SYSENTER_ESP),
9932 vmcs_read32(HOST_IA32_SYSENTER_CS),
9933 vmcs_readl(HOST_IA32_SYSENTER_EIP));
9934 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
9935 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9936 vmcs_read64(HOST_IA32_EFER),
9937 vmcs_read64(HOST_IA32_PAT));
9938 if (cpu_has_load_perf_global_ctrl &&
9939 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9940 pr_err("PerfGlobCtl = 0x%016llx\n",
9941 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
9943 pr_err("*** Control State ***\n");
9944 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
9945 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
9946 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
9947 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
9948 vmcs_read32(EXCEPTION_BITMAP),
9949 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
9950 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
9951 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
9952 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9953 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
9954 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
9955 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
9956 vmcs_read32(VM_EXIT_INTR_INFO),
9957 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9958 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
9959 pr_err(" reason=%08x qualification=%016lx\n",
9960 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
9961 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
9962 vmcs_read32(IDT_VECTORING_INFO_FIELD),
9963 vmcs_read32(IDT_VECTORING_ERROR_CODE));
9964 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
9965 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
9966 pr_err("TSC Multiplier = 0x%016llx\n",
9967 vmcs_read64(TSC_MULTIPLIER));
9968 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
9969 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9970 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
9971 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
9972 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
9973 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
9974 n = vmcs_read32(CR3_TARGET_COUNT);
9975 for (i = 0; i + 1 < n; i += 4)
9976 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
9977 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
9978 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
9980 pr_err("CR3 target%u=%016lx\n",
9981 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
9982 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
9983 pr_err("PLE Gap=%08x Window=%08x\n",
9984 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
9985 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
9986 pr_err("Virtual processor ID = 0x%04x\n",
9987 vmcs_read16(VIRTUAL_PROCESSOR_ID));
9991 * The guest has exited. See if we can fix it or if we need userspace
9994 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
9996 struct vcpu_vmx *vmx = to_vmx(vcpu);
9997 u32 exit_reason = vmx->exit_reason;
9998 u32 vectoring_info = vmx->idt_vectoring_info;
10000 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
10003 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
10004 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
10005 * querying dirty_bitmap, we only need to kick all vcpus out of guest
10006 * mode as if vcpus is in root mode, the PML buffer must has been
10010 vmx_flush_pml_buffer(vcpu);
10012 /* If guest state is invalid, start emulating */
10013 if (vmx->emulation_required)
10014 return handle_invalid_guest_state(vcpu);
10016 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
10017 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
10019 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
10021 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
10022 vcpu->run->fail_entry.hardware_entry_failure_reason
10027 if (unlikely(vmx->fail)) {
10028 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
10029 vcpu->run->fail_entry.hardware_entry_failure_reason
10030 = vmcs_read32(VM_INSTRUCTION_ERROR);
10036 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
10037 * delivery event since it indicates guest is accessing MMIO.
10038 * The vm-exit can be triggered again after return to guest that
10039 * will cause infinite loop.
10041 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
10042 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
10043 exit_reason != EXIT_REASON_EPT_VIOLATION &&
10044 exit_reason != EXIT_REASON_PML_FULL &&
10045 exit_reason != EXIT_REASON_TASK_SWITCH)) {
10046 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
10047 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
10048 vcpu->run->internal.ndata = 3;
10049 vcpu->run->internal.data[0] = vectoring_info;
10050 vcpu->run->internal.data[1] = exit_reason;
10051 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
10052 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
10053 vcpu->run->internal.ndata++;
10054 vcpu->run->internal.data[3] =
10055 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
10060 if (unlikely(!enable_vnmi &&
10061 vmx->loaded_vmcs->soft_vnmi_blocked)) {
10062 if (vmx_interrupt_allowed(vcpu)) {
10063 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
10064 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
10065 vcpu->arch.nmi_pending) {
10067 * This CPU don't support us in finding the end of an
10068 * NMI-blocked window if the guest runs with IRQs
10069 * disabled. So we pull the trigger after 1 s of
10070 * futile waiting, but inform the user about this.
10072 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
10073 "state on VCPU %d after 1 s timeout\n",
10074 __func__, vcpu->vcpu_id);
10075 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
10079 if (exit_reason < kvm_vmx_max_exit_handlers
10080 && kvm_vmx_exit_handlers[exit_reason])
10081 return kvm_vmx_exit_handlers[exit_reason](vcpu);
10083 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
10085 kvm_queue_exception(vcpu, UD_VECTOR);
10091 * Software based L1D cache flush which is used when microcode providing
10092 * the cache control MSR is not loaded.
10094 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
10095 * flush it is required to read in 64 KiB because the replacement algorithm
10096 * is not exactly LRU. This could be sized at runtime via topology
10097 * information but as all relevant affected CPUs have 32KiB L1D cache size
10098 * there is no point in doing so.
10100 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
10102 int size = PAGE_SIZE << L1D_CACHE_ORDER;
10105 * This code is only executed when the the flush mode is 'cond' or
10108 if (static_branch_likely(&vmx_l1d_flush_cond)) {
10112 * Clear the per-vcpu flush bit, it gets set again
10113 * either from vcpu_run() or from one of the unsafe
10116 flush_l1d = vcpu->arch.l1tf_flush_l1d;
10117 vcpu->arch.l1tf_flush_l1d = false;
10120 * Clear the per-cpu flush bit, it gets set again from
10121 * the interrupt handlers.
10123 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
10124 kvm_clear_cpu_l1tf_flush_l1d();
10130 vcpu->stat.l1d_flush++;
10132 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
10133 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
10138 /* First ensure the pages are in the TLB */
10139 "xorl %%eax, %%eax\n"
10140 ".Lpopulate_tlb:\n\t"
10141 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
10142 "addl $4096, %%eax\n\t"
10143 "cmpl %%eax, %[size]\n\t"
10144 "jne .Lpopulate_tlb\n\t"
10145 "xorl %%eax, %%eax\n\t"
10147 /* Now fill the cache */
10148 "xorl %%eax, %%eax\n"
10150 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
10151 "addl $64, %%eax\n\t"
10152 "cmpl %%eax, %[size]\n\t"
10153 "jne .Lfill_cache\n\t"
10155 :: [flush_pages] "r" (vmx_l1d_flush_pages),
10157 : "eax", "ebx", "ecx", "edx");
10160 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
10162 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10164 if (is_guest_mode(vcpu) &&
10165 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10168 if (irr == -1 || tpr < irr) {
10169 vmcs_write32(TPR_THRESHOLD, 0);
10173 vmcs_write32(TPR_THRESHOLD, irr);
10176 static void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
10178 u32 sec_exec_control;
10180 if (!lapic_in_kernel(vcpu))
10183 if (!flexpriority_enabled &&
10184 !cpu_has_vmx_virtualize_x2apic_mode())
10187 /* Postpone execution until vmcs01 is the current VMCS. */
10188 if (is_guest_mode(vcpu)) {
10189 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
10193 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
10194 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10195 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
10197 switch (kvm_get_apic_mode(vcpu)) {
10198 case LAPIC_MODE_INVALID:
10199 WARN_ONCE(true, "Invalid local APIC state");
10200 case LAPIC_MODE_DISABLED:
10202 case LAPIC_MODE_XAPIC:
10203 if (flexpriority_enabled) {
10204 sec_exec_control |=
10205 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
10206 vmx_flush_tlb(vcpu, true);
10209 case LAPIC_MODE_X2APIC:
10210 if (cpu_has_vmx_virtualize_x2apic_mode())
10211 sec_exec_control |=
10212 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
10215 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
10217 vmx_update_msr_bitmap(vcpu);
10220 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
10222 if (!is_guest_mode(vcpu)) {
10223 vmcs_write64(APIC_ACCESS_ADDR, hpa);
10224 vmx_flush_tlb(vcpu, true);
10228 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
10236 status = vmcs_read16(GUEST_INTR_STATUS);
10238 if (max_isr != old) {
10240 status |= max_isr << 8;
10241 vmcs_write16(GUEST_INTR_STATUS, status);
10245 static void vmx_set_rvi(int vector)
10253 status = vmcs_read16(GUEST_INTR_STATUS);
10254 old = (u8)status & 0xff;
10255 if ((u8)vector != old) {
10257 status |= (u8)vector;
10258 vmcs_write16(GUEST_INTR_STATUS, status);
10262 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
10265 * When running L2, updating RVI is only relevant when
10266 * vmcs12 virtual-interrupt-delivery enabled.
10267 * However, it can be enabled only when L1 also
10268 * intercepts external-interrupts and in that case
10269 * we should not update vmcs02 RVI but instead intercept
10270 * interrupt. Therefore, do nothing when running L2.
10272 if (!is_guest_mode(vcpu))
10273 vmx_set_rvi(max_irr);
10276 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
10278 struct vcpu_vmx *vmx = to_vmx(vcpu);
10280 bool max_irr_updated;
10282 WARN_ON(!vcpu->arch.apicv_active);
10283 if (pi_test_on(&vmx->pi_desc)) {
10284 pi_clear_on(&vmx->pi_desc);
10286 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
10287 * But on x86 this is just a compiler barrier anyway.
10289 smp_mb__after_atomic();
10291 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
10294 * If we are running L2 and L1 has a new pending interrupt
10295 * which can be injected, we should re-evaluate
10296 * what should be done with this new L1 interrupt.
10297 * If L1 intercepts external-interrupts, we should
10298 * exit from L2 to L1. Otherwise, interrupt should be
10299 * delivered directly to L2.
10301 if (is_guest_mode(vcpu) && max_irr_updated) {
10302 if (nested_exit_on_intr(vcpu))
10303 kvm_vcpu_exiting_guest_mode(vcpu);
10305 kvm_make_request(KVM_REQ_EVENT, vcpu);
10308 max_irr = kvm_lapic_find_highest_irr(vcpu);
10310 vmx_hwapic_irr_update(vcpu, max_irr);
10314 static u8 vmx_has_apicv_interrupt(struct kvm_vcpu *vcpu)
10316 u8 rvi = vmx_get_rvi();
10317 u8 vppr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_PROCPRI);
10319 return ((rvi & 0xf0) > (vppr & 0xf0));
10322 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
10324 if (!kvm_vcpu_apicv_active(vcpu))
10327 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
10328 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
10329 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
10330 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
10333 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
10335 struct vcpu_vmx *vmx = to_vmx(vcpu);
10337 pi_clear_on(&vmx->pi_desc);
10338 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
10341 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
10343 u32 exit_intr_info = 0;
10344 u16 basic_exit_reason = (u16)vmx->exit_reason;
10346 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
10347 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
10350 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10351 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10352 vmx->exit_intr_info = exit_intr_info;
10354 /* if exit due to PF check for async PF */
10355 if (is_page_fault(exit_intr_info))
10356 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
10358 /* Handle machine checks before interrupts are enabled */
10359 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
10360 is_machine_check(exit_intr_info))
10361 kvm_machine_check();
10363 /* We need to handle NMIs before interrupts are enabled */
10364 if (is_nmi(exit_intr_info)) {
10365 kvm_before_interrupt(&vmx->vcpu);
10367 kvm_after_interrupt(&vmx->vcpu);
10371 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
10373 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10375 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
10376 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
10377 unsigned int vector;
10378 unsigned long entry;
10380 struct vcpu_vmx *vmx = to_vmx(vcpu);
10381 #ifdef CONFIG_X86_64
10385 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
10386 desc = (gate_desc *)vmx->host_idt_base + vector;
10387 entry = gate_offset(desc);
10389 #ifdef CONFIG_X86_64
10390 "mov %%" _ASM_SP ", %[sp]\n\t"
10391 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
10396 __ASM_SIZE(push) " $%c[cs]\n\t"
10399 #ifdef CONFIG_X86_64
10402 ASM_CALL_CONSTRAINT
10404 THUNK_TARGET(entry),
10405 [ss]"i"(__KERNEL_DS),
10406 [cs]"i"(__KERNEL_CS)
10410 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
10412 static bool vmx_has_emulated_msr(int index)
10415 case MSR_IA32_SMBASE:
10417 * We cannot do SMM unless we can run the guest in big
10420 return enable_unrestricted_guest || emulate_invalid_guest_state;
10421 case MSR_AMD64_VIRT_SPEC_CTRL:
10422 /* This is AMD only. */
10429 static bool vmx_mpx_supported(void)
10431 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
10432 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
10435 static bool vmx_xsaves_supported(void)
10437 return vmcs_config.cpu_based_2nd_exec_ctrl &
10438 SECONDARY_EXEC_XSAVES;
10441 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
10443 u32 exit_intr_info;
10446 bool idtv_info_valid;
10448 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
10451 if (vmx->loaded_vmcs->nmi_known_unmasked)
10454 * Can't use vmx->exit_intr_info since we're not sure what
10455 * the exit reason is.
10457 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10458 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
10459 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
10461 * SDM 3: 27.7.1.2 (September 2008)
10462 * Re-set bit "block by NMI" before VM entry if vmexit caused by
10463 * a guest IRET fault.
10464 * SDM 3: 23.2.2 (September 2008)
10465 * Bit 12 is undefined in any of the following cases:
10466 * If the VM exit sets the valid bit in the IDT-vectoring
10467 * information field.
10468 * If the VM exit is due to a double fault.
10470 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
10471 vector != DF_VECTOR && !idtv_info_valid)
10472 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
10473 GUEST_INTR_STATE_NMI);
10475 vmx->loaded_vmcs->nmi_known_unmasked =
10476 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
10477 & GUEST_INTR_STATE_NMI);
10478 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
10479 vmx->loaded_vmcs->vnmi_blocked_time +=
10480 ktime_to_ns(ktime_sub(ktime_get(),
10481 vmx->loaded_vmcs->entry_time));
10484 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
10485 u32 idt_vectoring_info,
10486 int instr_len_field,
10487 int error_code_field)
10491 bool idtv_info_valid;
10493 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
10495 vcpu->arch.nmi_injected = false;
10496 kvm_clear_exception_queue(vcpu);
10497 kvm_clear_interrupt_queue(vcpu);
10499 if (!idtv_info_valid)
10502 kvm_make_request(KVM_REQ_EVENT, vcpu);
10504 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
10505 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
10508 case INTR_TYPE_NMI_INTR:
10509 vcpu->arch.nmi_injected = true;
10511 * SDM 3: 27.7.1.2 (September 2008)
10512 * Clear bit "block by NMI" before VM entry if a NMI
10513 * delivery faulted.
10515 vmx_set_nmi_mask(vcpu, false);
10517 case INTR_TYPE_SOFT_EXCEPTION:
10518 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
10520 case INTR_TYPE_HARD_EXCEPTION:
10521 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
10522 u32 err = vmcs_read32(error_code_field);
10523 kvm_requeue_exception_e(vcpu, vector, err);
10525 kvm_requeue_exception(vcpu, vector);
10527 case INTR_TYPE_SOFT_INTR:
10528 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
10530 case INTR_TYPE_EXT_INTR:
10531 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
10538 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
10540 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
10541 VM_EXIT_INSTRUCTION_LEN,
10542 IDT_VECTORING_ERROR_CODE);
10545 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
10547 __vmx_complete_interrupts(vcpu,
10548 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
10549 VM_ENTRY_INSTRUCTION_LEN,
10550 VM_ENTRY_EXCEPTION_ERROR_CODE);
10552 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10555 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
10558 struct perf_guest_switch_msr *msrs;
10560 msrs = perf_guest_get_msrs(&nr_msrs);
10565 for (i = 0; i < nr_msrs; i++)
10566 if (msrs[i].host == msrs[i].guest)
10567 clear_atomic_switch_msr(vmx, msrs[i].msr);
10569 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
10570 msrs[i].host, false);
10573 static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
10575 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
10576 if (!vmx->loaded_vmcs->hv_timer_armed)
10577 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10578 PIN_BASED_VMX_PREEMPTION_TIMER);
10579 vmx->loaded_vmcs->hv_timer_armed = true;
10582 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
10584 struct vcpu_vmx *vmx = to_vmx(vcpu);
10588 if (vmx->req_immediate_exit) {
10589 vmx_arm_hv_timer(vmx, 0);
10593 if (vmx->hv_deadline_tsc != -1) {
10595 if (vmx->hv_deadline_tsc > tscl)
10596 /* set_hv_timer ensures the delta fits in 32-bits */
10597 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
10598 cpu_preemption_timer_multi);
10602 vmx_arm_hv_timer(vmx, delta_tsc);
10606 if (vmx->loaded_vmcs->hv_timer_armed)
10607 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10608 PIN_BASED_VMX_PREEMPTION_TIMER);
10609 vmx->loaded_vmcs->hv_timer_armed = false;
10612 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
10614 struct vcpu_vmx *vmx = to_vmx(vcpu);
10615 unsigned long cr3, cr4, evmcs_rsp;
10617 /* Record the guest's net vcpu time for enforced NMI injections. */
10618 if (unlikely(!enable_vnmi &&
10619 vmx->loaded_vmcs->soft_vnmi_blocked))
10620 vmx->loaded_vmcs->entry_time = ktime_get();
10622 /* Don't enter VMX if guest state is invalid, let the exit handler
10623 start emulation until we arrive back to a valid state */
10624 if (vmx->emulation_required)
10627 if (vmx->ple_window_dirty) {
10628 vmx->ple_window_dirty = false;
10629 vmcs_write32(PLE_WINDOW, vmx->ple_window);
10632 if (vmx->nested.sync_shadow_vmcs) {
10633 copy_vmcs12_to_shadow(vmx);
10634 vmx->nested.sync_shadow_vmcs = false;
10637 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
10638 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
10639 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
10640 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
10642 cr3 = __get_current_cr3_fast();
10643 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
10644 vmcs_writel(HOST_CR3, cr3);
10645 vmx->loaded_vmcs->host_state.cr3 = cr3;
10648 cr4 = cr4_read_shadow();
10649 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
10650 vmcs_writel(HOST_CR4, cr4);
10651 vmx->loaded_vmcs->host_state.cr4 = cr4;
10654 /* When single-stepping over STI and MOV SS, we must clear the
10655 * corresponding interruptibility bits in the guest state. Otherwise
10656 * vmentry fails as it then expects bit 14 (BS) in pending debug
10657 * exceptions being set, but that's not correct for the guest debugging
10659 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10660 vmx_set_interrupt_shadow(vcpu, 0);
10662 if (static_cpu_has(X86_FEATURE_PKU) &&
10663 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
10664 vcpu->arch.pkru != vmx->host_pkru)
10665 __write_pkru(vcpu->arch.pkru);
10667 atomic_switch_perf_msrs(vmx);
10669 vmx_update_hv_timer(vcpu);
10672 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
10673 * it's non-zero. Since vmentry is serialising on affected CPUs, there
10674 * is no need to worry about the conditional branch over the wrmsr
10675 * being speculatively taken.
10677 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
10679 vmx->__launched = vmx->loaded_vmcs->launched;
10681 evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
10682 (unsigned long)¤t_evmcs->host_rsp : 0;
10684 if (static_branch_unlikely(&vmx_l1d_should_flush))
10685 vmx_l1d_flush(vcpu);
10688 /* Store host registers */
10689 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
10690 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
10691 "push %%" _ASM_CX " \n\t"
10692 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10694 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10695 /* Avoid VMWRITE when Enlightened VMCS is in use */
10696 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
10698 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
10701 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
10703 /* Reload cr2 if changed */
10704 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
10705 "mov %%cr2, %%" _ASM_DX " \n\t"
10706 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
10708 "mov %%" _ASM_AX", %%cr2 \n\t"
10710 /* Check if vmlaunch of vmresume is needed */
10711 "cmpl $0, %c[launched](%0) \n\t"
10712 /* Load guest registers. Don't clobber flags. */
10713 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
10714 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
10715 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
10716 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
10717 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
10718 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
10719 #ifdef CONFIG_X86_64
10720 "mov %c[r8](%0), %%r8 \n\t"
10721 "mov %c[r9](%0), %%r9 \n\t"
10722 "mov %c[r10](%0), %%r10 \n\t"
10723 "mov %c[r11](%0), %%r11 \n\t"
10724 "mov %c[r12](%0), %%r12 \n\t"
10725 "mov %c[r13](%0), %%r13 \n\t"
10726 "mov %c[r14](%0), %%r14 \n\t"
10727 "mov %c[r15](%0), %%r15 \n\t"
10729 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
10731 /* Enter guest mode */
10733 __ex(ASM_VMX_VMLAUNCH) "\n\t"
10735 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
10737 /* Save guest registers, load host registers, keep flags */
10738 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
10740 "setbe %c[fail](%0)\n\t"
10741 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
10742 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
10743 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
10744 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
10745 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
10746 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
10747 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
10748 #ifdef CONFIG_X86_64
10749 "mov %%r8, %c[r8](%0) \n\t"
10750 "mov %%r9, %c[r9](%0) \n\t"
10751 "mov %%r10, %c[r10](%0) \n\t"
10752 "mov %%r11, %c[r11](%0) \n\t"
10753 "mov %%r12, %c[r12](%0) \n\t"
10754 "mov %%r13, %c[r13](%0) \n\t"
10755 "mov %%r14, %c[r14](%0) \n\t"
10756 "mov %%r15, %c[r15](%0) \n\t"
10757 "xor %%r8d, %%r8d \n\t"
10758 "xor %%r9d, %%r9d \n\t"
10759 "xor %%r10d, %%r10d \n\t"
10760 "xor %%r11d, %%r11d \n\t"
10761 "xor %%r12d, %%r12d \n\t"
10762 "xor %%r13d, %%r13d \n\t"
10763 "xor %%r14d, %%r14d \n\t"
10764 "xor %%r15d, %%r15d \n\t"
10766 "mov %%cr2, %%" _ASM_AX " \n\t"
10767 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
10769 "xor %%eax, %%eax \n\t"
10770 "xor %%ebx, %%ebx \n\t"
10771 "xor %%esi, %%esi \n\t"
10772 "xor %%edi, %%edi \n\t"
10773 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
10774 ".pushsection .rodata \n\t"
10775 ".global vmx_return \n\t"
10776 "vmx_return: " _ASM_PTR " 2b \n\t"
10778 : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
10779 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
10780 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
10781 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
10782 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
10783 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
10784 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
10785 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
10786 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
10787 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
10788 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
10789 #ifdef CONFIG_X86_64
10790 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
10791 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
10792 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
10793 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
10794 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
10795 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
10796 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
10797 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
10799 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
10800 [wordsize]"i"(sizeof(ulong))
10802 #ifdef CONFIG_X86_64
10803 , "rax", "rbx", "rdi"
10804 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
10806 , "eax", "ebx", "edi"
10811 * We do not use IBRS in the kernel. If this vCPU has used the
10812 * SPEC_CTRL MSR it may have left it on; save the value and
10813 * turn it off. This is much more efficient than blindly adding
10814 * it to the atomic save/restore list. Especially as the former
10815 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
10817 * For non-nested case:
10818 * If the L01 MSR bitmap does not intercept the MSR, then we need to
10822 * If the L02 MSR bitmap does not intercept the MSR, then we need to
10825 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
10826 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
10828 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
10830 /* Eliminate branch target predictions from guest mode */
10833 /* All fields are clean at this point */
10834 if (static_branch_unlikely(&enable_evmcs))
10835 current_evmcs->hv_clean_fields |=
10836 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
10838 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
10839 if (vmx->host_debugctlmsr)
10840 update_debugctlmsr(vmx->host_debugctlmsr);
10842 #ifndef CONFIG_X86_64
10844 * The sysexit path does not restore ds/es, so we must set them to
10845 * a reasonable value ourselves.
10847 * We can't defer this to vmx_prepare_switch_to_host() since that
10848 * function may be executed in interrupt context, which saves and
10849 * restore segments around it, nullifying its effect.
10851 loadsegment(ds, __USER_DS);
10852 loadsegment(es, __USER_DS);
10855 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
10856 | (1 << VCPU_EXREG_RFLAGS)
10857 | (1 << VCPU_EXREG_PDPTR)
10858 | (1 << VCPU_EXREG_SEGMENTS)
10859 | (1 << VCPU_EXREG_CR3));
10860 vcpu->arch.regs_dirty = 0;
10863 * eager fpu is enabled if PKEY is supported and CR4 is switched
10864 * back on host, so it is safe to read guest PKRU from current
10867 if (static_cpu_has(X86_FEATURE_PKU) &&
10868 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
10869 vcpu->arch.pkru = __read_pkru();
10870 if (vcpu->arch.pkru != vmx->host_pkru)
10871 __write_pkru(vmx->host_pkru);
10874 vmx->nested.nested_run_pending = 0;
10875 vmx->idt_vectoring_info = 0;
10877 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
10878 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10881 vmx->loaded_vmcs->launched = 1;
10882 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
10884 vmx_complete_atomic_exit(vmx);
10885 vmx_recover_nmi_blocking(vmx);
10886 vmx_complete_interrupts(vmx);
10888 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
10890 static struct kvm *vmx_vm_alloc(void)
10892 struct kvm_vmx *kvm_vmx = vzalloc(sizeof(struct kvm_vmx));
10893 return &kvm_vmx->kvm;
10896 static void vmx_vm_free(struct kvm *kvm)
10898 vfree(to_kvm_vmx(kvm));
10901 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
10903 struct vcpu_vmx *vmx = to_vmx(vcpu);
10906 if (vmx->loaded_vmcs == vmcs)
10910 vmx_vcpu_put(vcpu);
10911 vmx->loaded_vmcs = vmcs;
10912 vmx_vcpu_load(vcpu, cpu);
10915 vm_entry_controls_reset_shadow(vmx);
10916 vm_exit_controls_reset_shadow(vmx);
10917 vmx_segment_cache_clear(vmx);
10921 * Ensure that the current vmcs of the logical processor is the
10922 * vmcs01 of the vcpu before calling free_nested().
10924 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
10926 struct vcpu_vmx *vmx = to_vmx(vcpu);
10929 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10934 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
10936 struct vcpu_vmx *vmx = to_vmx(vcpu);
10939 vmx_destroy_pml_buffer(vmx);
10940 free_vpid(vmx->vpid);
10941 leave_guest_mode(vcpu);
10942 vmx_free_vcpu_nested(vcpu);
10943 free_loaded_vmcs(vmx->loaded_vmcs);
10944 kfree(vmx->guest_msrs);
10945 kvm_vcpu_uninit(vcpu);
10946 kmem_cache_free(kvm_vcpu_cache, vmx);
10949 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
10952 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
10953 unsigned long *msr_bitmap;
10957 return ERR_PTR(-ENOMEM);
10959 vmx->vpid = allocate_vpid();
10961 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
10968 * If PML is turned on, failure on enabling PML just results in failure
10969 * of creating the vcpu, therefore we can simplify PML logic (by
10970 * avoiding dealing with cases, such as enabling PML partially on vcpus
10971 * for the guest, etc.
10974 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
10979 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
10980 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
10983 if (!vmx->guest_msrs)
10986 err = alloc_loaded_vmcs(&vmx->vmcs01);
10990 msr_bitmap = vmx->vmcs01.msr_bitmap;
10991 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
10992 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
10993 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
10994 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
10995 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
10996 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
10997 vmx->msr_bitmap_mode = 0;
10999 vmx->loaded_vmcs = &vmx->vmcs01;
11001 vmx_vcpu_load(&vmx->vcpu, cpu);
11002 vmx->vcpu.cpu = cpu;
11003 vmx_vcpu_setup(vmx);
11004 vmx_vcpu_put(&vmx->vcpu);
11006 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
11007 err = alloc_apic_access_page(kvm);
11012 if (enable_ept && !enable_unrestricted_guest) {
11013 err = init_rmode_identity_map(kvm);
11019 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
11020 kvm_vcpu_apicv_active(&vmx->vcpu));
11022 vmx->nested.posted_intr_nv = -1;
11023 vmx->nested.current_vmptr = -1ull;
11025 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
11028 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
11029 * or POSTED_INTR_WAKEUP_VECTOR.
11031 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
11032 vmx->pi_desc.sn = 1;
11037 free_loaded_vmcs(vmx->loaded_vmcs);
11039 kfree(vmx->guest_msrs);
11041 vmx_destroy_pml_buffer(vmx);
11043 kvm_vcpu_uninit(&vmx->vcpu);
11045 free_vpid(vmx->vpid);
11046 kmem_cache_free(kvm_vcpu_cache, vmx);
11047 return ERR_PTR(err);
11050 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
11051 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
11053 static int vmx_vm_init(struct kvm *kvm)
11055 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
11058 kvm->arch.pause_in_guest = true;
11060 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
11061 switch (l1tf_mitigation) {
11062 case L1TF_MITIGATION_OFF:
11063 case L1TF_MITIGATION_FLUSH_NOWARN:
11064 /* 'I explicitly don't care' is set */
11066 case L1TF_MITIGATION_FLUSH:
11067 case L1TF_MITIGATION_FLUSH_NOSMT:
11068 case L1TF_MITIGATION_FULL:
11070 * Warn upon starting the first VM in a potentially
11071 * insecure environment.
11073 if (cpu_smt_control == CPU_SMT_ENABLED)
11074 pr_warn_once(L1TF_MSG_SMT);
11075 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
11076 pr_warn_once(L1TF_MSG_L1D);
11078 case L1TF_MITIGATION_FULL_FORCE:
11079 /* Flush is enforced */
11086 static void __init vmx_check_processor_compat(void *rtn)
11088 struct vmcs_config vmcs_conf;
11091 if (setup_vmcs_config(&vmcs_conf) < 0)
11092 *(int *)rtn = -EIO;
11093 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, enable_apicv);
11094 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
11095 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
11096 smp_processor_id());
11097 *(int *)rtn = -EIO;
11101 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
11106 /* For VT-d and EPT combination
11107 * 1. MMIO: always map as UC
11108 * 2. EPT with VT-d:
11109 * a. VT-d without snooping control feature: can't guarantee the
11110 * result, try to trust guest.
11111 * b. VT-d with snooping control feature: snooping control feature of
11112 * VT-d engine can guarantee the cache correctness. Just set it
11113 * to WB to keep consistent with host. So the same as item 3.
11114 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
11115 * consistent with host MTRR
11118 cache = MTRR_TYPE_UNCACHABLE;
11122 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
11123 ipat = VMX_EPT_IPAT_BIT;
11124 cache = MTRR_TYPE_WRBACK;
11128 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
11129 ipat = VMX_EPT_IPAT_BIT;
11130 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
11131 cache = MTRR_TYPE_WRBACK;
11133 cache = MTRR_TYPE_UNCACHABLE;
11137 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
11140 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
11143 static int vmx_get_lpage_level(void)
11145 if (enable_ept && !cpu_has_vmx_ept_1g_page())
11146 return PT_DIRECTORY_LEVEL;
11148 /* For shadow and EPT supported 1GB page */
11149 return PT_PDPE_LEVEL;
11152 static void vmcs_set_secondary_exec_control(u32 new_ctl)
11155 * These bits in the secondary execution controls field
11156 * are dynamic, the others are mostly based on the hypervisor
11157 * architecture and the guest's CPUID. Do not touch the
11161 SECONDARY_EXEC_SHADOW_VMCS |
11162 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
11163 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
11164 SECONDARY_EXEC_DESC;
11166 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
11168 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
11169 (new_ctl & ~mask) | (cur_ctl & mask));
11173 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
11174 * (indicating "allowed-1") if they are supported in the guest's CPUID.
11176 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
11178 struct vcpu_vmx *vmx = to_vmx(vcpu);
11179 struct kvm_cpuid_entry2 *entry;
11181 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
11182 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
11184 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
11185 if (entry && (entry->_reg & (_cpuid_mask))) \
11186 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
11189 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
11190 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
11191 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
11192 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
11193 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
11194 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
11195 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
11196 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
11197 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
11198 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
11199 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
11200 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
11201 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
11202 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
11203 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
11205 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
11206 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
11207 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
11208 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
11209 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
11210 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
11212 #undef cr4_fixed1_update
11215 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
11217 struct vcpu_vmx *vmx = to_vmx(vcpu);
11219 if (kvm_mpx_supported()) {
11220 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
11223 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
11224 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
11226 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
11227 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
11232 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
11234 struct vcpu_vmx *vmx = to_vmx(vcpu);
11236 if (cpu_has_secondary_exec_ctrls()) {
11237 vmx_compute_secondary_exec_control(vmx);
11238 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
11241 if (nested_vmx_allowed(vcpu))
11242 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11243 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
11245 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11246 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
11248 if (nested_vmx_allowed(vcpu)) {
11249 nested_vmx_cr_fixed1_bits_update(vcpu);
11250 nested_vmx_entry_exit_ctls_update(vcpu);
11254 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
11256 if (func == 1 && nested)
11257 entry->ecx |= bit(X86_FEATURE_VMX);
11260 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
11261 struct x86_exception *fault)
11263 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11264 struct vcpu_vmx *vmx = to_vmx(vcpu);
11266 unsigned long exit_qualification = vcpu->arch.exit_qualification;
11268 if (vmx->nested.pml_full) {
11269 exit_reason = EXIT_REASON_PML_FULL;
11270 vmx->nested.pml_full = false;
11271 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
11272 } else if (fault->error_code & PFERR_RSVD_MASK)
11273 exit_reason = EXIT_REASON_EPT_MISCONFIG;
11275 exit_reason = EXIT_REASON_EPT_VIOLATION;
11277 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
11278 vmcs12->guest_physical_address = fault->address;
11281 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
11283 return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
11286 /* Callbacks for nested_ept_init_mmu_context: */
11288 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
11290 /* return the page table to be shadowed - in our case, EPT12 */
11291 return get_vmcs12(vcpu)->ept_pointer;
11294 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
11296 WARN_ON(mmu_is_nested(vcpu));
11298 kvm_init_shadow_ept_mmu(vcpu,
11299 to_vmx(vcpu)->nested.msrs.ept_caps &
11300 VMX_EPT_EXECUTE_ONLY_BIT,
11301 nested_ept_ad_enabled(vcpu),
11302 nested_ept_get_cr3(vcpu));
11303 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
11304 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
11305 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
11307 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
11310 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
11312 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
11315 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
11318 bool inequality, bit;
11320 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
11322 (error_code & vmcs12->page_fault_error_code_mask) !=
11323 vmcs12->page_fault_error_code_match;
11324 return inequality ^ bit;
11327 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
11328 struct x86_exception *fault)
11330 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11332 WARN_ON(!is_guest_mode(vcpu));
11334 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
11335 !to_vmx(vcpu)->nested.nested_run_pending) {
11336 vmcs12->vm_exit_intr_error_code = fault->error_code;
11337 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11338 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
11339 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
11342 kvm_inject_page_fault(vcpu, fault);
11346 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
11347 struct vmcs12 *vmcs12);
11349 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
11351 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11352 struct vcpu_vmx *vmx = to_vmx(vcpu);
11356 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11358 * Translate L1 physical address to host physical
11359 * address for vmcs02. Keep the page pinned, so this
11360 * physical address remains valid. We keep a reference
11361 * to it so we can release it later.
11363 if (vmx->nested.apic_access_page) { /* shouldn't happen */
11364 kvm_release_page_dirty(vmx->nested.apic_access_page);
11365 vmx->nested.apic_access_page = NULL;
11367 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
11369 * If translation failed, no matter: This feature asks
11370 * to exit when accessing the given address, and if it
11371 * can never be accessed, this feature won't do
11374 if (!is_error_page(page)) {
11375 vmx->nested.apic_access_page = page;
11376 hpa = page_to_phys(vmx->nested.apic_access_page);
11377 vmcs_write64(APIC_ACCESS_ADDR, hpa);
11379 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
11380 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
11384 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
11385 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
11386 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11387 vmx->nested.virtual_apic_page = NULL;
11389 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
11392 * If translation failed, VM entry will fail because
11393 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
11394 * Failing the vm entry is _not_ what the processor
11395 * does but it's basically the only possibility we
11396 * have. We could still enter the guest if CR8 load
11397 * exits are enabled, CR8 store exits are enabled, and
11398 * virtualize APIC access is disabled; in this case
11399 * the processor would never use the TPR shadow and we
11400 * could simply clear the bit from the execution
11401 * control. But such a configuration is useless, so
11402 * let's keep the code simple.
11404 if (!is_error_page(page)) {
11405 vmx->nested.virtual_apic_page = page;
11406 hpa = page_to_phys(vmx->nested.virtual_apic_page);
11407 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
11411 if (nested_cpu_has_posted_intr(vmcs12)) {
11412 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
11413 kunmap(vmx->nested.pi_desc_page);
11414 kvm_release_page_dirty(vmx->nested.pi_desc_page);
11415 vmx->nested.pi_desc_page = NULL;
11417 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
11418 if (is_error_page(page))
11420 vmx->nested.pi_desc_page = page;
11421 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
11422 vmx->nested.pi_desc =
11423 (struct pi_desc *)((void *)vmx->nested.pi_desc +
11424 (unsigned long)(vmcs12->posted_intr_desc_addr &
11426 vmcs_write64(POSTED_INTR_DESC_ADDR,
11427 page_to_phys(vmx->nested.pi_desc_page) +
11428 (unsigned long)(vmcs12->posted_intr_desc_addr &
11431 if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
11432 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
11433 CPU_BASED_USE_MSR_BITMAPS);
11435 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
11436 CPU_BASED_USE_MSR_BITMAPS);
11439 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
11441 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
11442 struct vcpu_vmx *vmx = to_vmx(vcpu);
11445 * A timer value of zero is architecturally guaranteed to cause
11446 * a VMExit prior to executing any instructions in the guest.
11448 if (preemption_timeout == 0) {
11449 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
11453 if (vcpu->arch.virtual_tsc_khz == 0)
11456 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11457 preemption_timeout *= 1000000;
11458 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
11459 hrtimer_start(&vmx->nested.preemption_timer,
11460 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
11463 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
11464 struct vmcs12 *vmcs12)
11466 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
11469 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
11470 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
11476 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
11477 struct vmcs12 *vmcs12)
11479 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
11482 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
11488 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
11489 struct vmcs12 *vmcs12)
11491 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
11494 if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
11501 * Merge L0's and L1's MSR bitmap, return false to indicate that
11502 * we do not use the hardware.
11504 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
11505 struct vmcs12 *vmcs12)
11509 unsigned long *msr_bitmap_l1;
11510 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
11512 * pred_cmd & spec_ctrl are trying to verify two things:
11514 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
11515 * ensures that we do not accidentally generate an L02 MSR bitmap
11516 * from the L12 MSR bitmap that is too permissive.
11517 * 2. That L1 or L2s have actually used the MSR. This avoids
11518 * unnecessarily merging of the bitmap if the MSR is unused. This
11519 * works properly because we only update the L01 MSR bitmap lazily.
11520 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
11521 * updated to reflect this when L1 (or its L2s) actually write to
11524 bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
11525 bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
11527 /* Nothing to do if the MSR bitmap is not in use. */
11528 if (!cpu_has_vmx_msr_bitmap() ||
11529 !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
11532 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11533 !pred_cmd && !spec_ctrl)
11536 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
11537 if (is_error_page(page))
11540 msr_bitmap_l1 = (unsigned long *)kmap(page);
11541 if (nested_cpu_has_apic_reg_virt(vmcs12)) {
11543 * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
11544 * just lets the processor take the value from the virtual-APIC page;
11545 * take those 256 bits directly from the L1 bitmap.
11547 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
11548 unsigned word = msr / BITS_PER_LONG;
11549 msr_bitmap_l0[word] = msr_bitmap_l1[word];
11550 msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
11553 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
11554 unsigned word = msr / BITS_PER_LONG;
11555 msr_bitmap_l0[word] = ~0;
11556 msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
11560 nested_vmx_disable_intercept_for_msr(
11561 msr_bitmap_l1, msr_bitmap_l0,
11562 X2APIC_MSR(APIC_TASKPRI),
11565 if (nested_cpu_has_vid(vmcs12)) {
11566 nested_vmx_disable_intercept_for_msr(
11567 msr_bitmap_l1, msr_bitmap_l0,
11568 X2APIC_MSR(APIC_EOI),
11570 nested_vmx_disable_intercept_for_msr(
11571 msr_bitmap_l1, msr_bitmap_l0,
11572 X2APIC_MSR(APIC_SELF_IPI),
11577 nested_vmx_disable_intercept_for_msr(
11578 msr_bitmap_l1, msr_bitmap_l0,
11579 MSR_IA32_SPEC_CTRL,
11580 MSR_TYPE_R | MSR_TYPE_W);
11583 nested_vmx_disable_intercept_for_msr(
11584 msr_bitmap_l1, msr_bitmap_l0,
11589 kvm_release_page_clean(page);
11594 static void nested_cache_shadow_vmcs12(struct kvm_vcpu *vcpu,
11595 struct vmcs12 *vmcs12)
11597 struct vmcs12 *shadow;
11600 if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
11601 vmcs12->vmcs_link_pointer == -1ull)
11604 shadow = get_shadow_vmcs12(vcpu);
11605 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->vmcs_link_pointer);
11607 memcpy(shadow, kmap(page), VMCS12_SIZE);
11610 kvm_release_page_clean(page);
11613 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu *vcpu,
11614 struct vmcs12 *vmcs12)
11616 struct vcpu_vmx *vmx = to_vmx(vcpu);
11618 if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
11619 vmcs12->vmcs_link_pointer == -1ull)
11622 kvm_write_guest(vmx->vcpu.kvm, vmcs12->vmcs_link_pointer,
11623 get_shadow_vmcs12(vcpu), VMCS12_SIZE);
11626 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
11627 struct vmcs12 *vmcs12)
11629 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
11630 !page_address_valid(vcpu, vmcs12->apic_access_addr))
11636 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
11637 struct vmcs12 *vmcs12)
11639 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11640 !nested_cpu_has_apic_reg_virt(vmcs12) &&
11641 !nested_cpu_has_vid(vmcs12) &&
11642 !nested_cpu_has_posted_intr(vmcs12))
11646 * If virtualize x2apic mode is enabled,
11647 * virtualize apic access must be disabled.
11649 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11650 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
11654 * If virtual interrupt delivery is enabled,
11655 * we must exit on external interrupts.
11657 if (nested_cpu_has_vid(vmcs12) &&
11658 !nested_exit_on_intr(vcpu))
11662 * bits 15:8 should be zero in posted_intr_nv,
11663 * the descriptor address has been already checked
11664 * in nested_get_vmcs12_pages.
11666 * bits 5:0 of posted_intr_desc_addr should be zero.
11668 if (nested_cpu_has_posted_intr(vmcs12) &&
11669 (!nested_cpu_has_vid(vmcs12) ||
11670 !nested_exit_intr_ack_set(vcpu) ||
11671 (vmcs12->posted_intr_nv & 0xff00) ||
11672 (vmcs12->posted_intr_desc_addr & 0x3f) ||
11673 (!page_address_valid(vcpu, vmcs12->posted_intr_desc_addr))))
11676 /* tpr shadow is needed by all apicv features. */
11677 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
11683 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
11684 unsigned long count_field,
11685 unsigned long addr_field)
11687 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11691 if (vmcs12_read_any(vmcs12, count_field, &count) ||
11692 vmcs12_read_any(vmcs12, addr_field, &addr)) {
11698 maxphyaddr = cpuid_maxphyaddr(vcpu);
11699 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
11700 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
11701 pr_debug_ratelimited(
11702 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
11703 addr_field, maxphyaddr, count, addr);
11709 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
11710 struct vmcs12 *vmcs12)
11712 if (vmcs12->vm_exit_msr_load_count == 0 &&
11713 vmcs12->vm_exit_msr_store_count == 0 &&
11714 vmcs12->vm_entry_msr_load_count == 0)
11715 return 0; /* Fast path */
11716 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
11717 VM_EXIT_MSR_LOAD_ADDR) ||
11718 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
11719 VM_EXIT_MSR_STORE_ADDR) ||
11720 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
11721 VM_ENTRY_MSR_LOAD_ADDR))
11726 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
11727 struct vmcs12 *vmcs12)
11729 if (!nested_cpu_has_pml(vmcs12))
11732 if (!nested_cpu_has_ept(vmcs12) ||
11733 !page_address_valid(vcpu, vmcs12->pml_address))
11739 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu *vcpu,
11740 struct vmcs12 *vmcs12)
11742 if (!nested_cpu_has_shadow_vmcs(vmcs12))
11745 if (!page_address_valid(vcpu, vmcs12->vmread_bitmap) ||
11746 !page_address_valid(vcpu, vmcs12->vmwrite_bitmap))
11752 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
11753 struct vmx_msr_entry *e)
11755 /* x2APIC MSR accesses are not allowed */
11756 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
11758 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
11759 e->index == MSR_IA32_UCODE_REV)
11761 if (e->reserved != 0)
11766 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
11767 struct vmx_msr_entry *e)
11769 if (e->index == MSR_FS_BASE ||
11770 e->index == MSR_GS_BASE ||
11771 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
11772 nested_vmx_msr_check_common(vcpu, e))
11777 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
11778 struct vmx_msr_entry *e)
11780 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
11781 nested_vmx_msr_check_common(vcpu, e))
11787 * Load guest's/host's msr at nested entry/exit.
11788 * return 0 for success, entry index for failure.
11790 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11793 struct vmx_msr_entry e;
11794 struct msr_data msr;
11796 msr.host_initiated = false;
11797 for (i = 0; i < count; i++) {
11798 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
11800 pr_debug_ratelimited(
11801 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11802 __func__, i, gpa + i * sizeof(e));
11805 if (nested_vmx_load_msr_check(vcpu, &e)) {
11806 pr_debug_ratelimited(
11807 "%s check failed (%u, 0x%x, 0x%x)\n",
11808 __func__, i, e.index, e.reserved);
11811 msr.index = e.index;
11812 msr.data = e.value;
11813 if (kvm_set_msr(vcpu, &msr)) {
11814 pr_debug_ratelimited(
11815 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11816 __func__, i, e.index, e.value);
11825 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11828 struct vmx_msr_entry e;
11830 for (i = 0; i < count; i++) {
11831 struct msr_data msr_info;
11832 if (kvm_vcpu_read_guest(vcpu,
11833 gpa + i * sizeof(e),
11834 &e, 2 * sizeof(u32))) {
11835 pr_debug_ratelimited(
11836 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11837 __func__, i, gpa + i * sizeof(e));
11840 if (nested_vmx_store_msr_check(vcpu, &e)) {
11841 pr_debug_ratelimited(
11842 "%s check failed (%u, 0x%x, 0x%x)\n",
11843 __func__, i, e.index, e.reserved);
11846 msr_info.host_initiated = false;
11847 msr_info.index = e.index;
11848 if (kvm_get_msr(vcpu, &msr_info)) {
11849 pr_debug_ratelimited(
11850 "%s cannot read MSR (%u, 0x%x)\n",
11851 __func__, i, e.index);
11854 if (kvm_vcpu_write_guest(vcpu,
11855 gpa + i * sizeof(e) +
11856 offsetof(struct vmx_msr_entry, value),
11857 &msr_info.data, sizeof(msr_info.data))) {
11858 pr_debug_ratelimited(
11859 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11860 __func__, i, e.index, msr_info.data);
11867 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
11869 unsigned long invalid_mask;
11871 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
11872 return (val & invalid_mask) == 0;
11876 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
11877 * emulating VM entry into a guest with EPT enabled.
11878 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11879 * is assigned to entry_failure_code on failure.
11881 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
11882 u32 *entry_failure_code)
11884 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
11885 if (!nested_cr3_valid(vcpu, cr3)) {
11886 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11891 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
11892 * must not be dereferenced.
11894 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
11896 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
11897 *entry_failure_code = ENTRY_FAIL_PDPTE;
11904 kvm_mmu_new_cr3(vcpu, cr3, false);
11906 vcpu->arch.cr3 = cr3;
11907 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
11909 kvm_init_mmu(vcpu, false);
11915 * Returns if KVM is able to config CPU to tag TLB entries
11916 * populated by L2 differently than TLB entries populated
11919 * If L1 uses EPT, then TLB entries are tagged with different EPTP.
11921 * If L1 uses VPID and we allocated a vpid02, TLB entries are tagged
11922 * with different VPID (L1 entries are tagged with vmx->vpid
11923 * while L2 entries are tagged with vmx->nested.vpid02).
11925 static bool nested_has_guest_tlb_tag(struct kvm_vcpu *vcpu)
11927 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11929 return nested_cpu_has_ept(vmcs12) ||
11930 (nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02);
11933 static u64 nested_vmx_calc_efer(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
11935 if (vmx->nested.nested_run_pending &&
11936 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
11937 return vmcs12->guest_ia32_efer;
11938 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
11939 return vmx->vcpu.arch.efer | (EFER_LMA | EFER_LME);
11941 return vmx->vcpu.arch.efer & ~(EFER_LMA | EFER_LME);
11944 static void prepare_vmcs02_constant_state(struct vcpu_vmx *vmx)
11947 * If vmcs02 hasn't been initialized, set the constant vmcs02 state
11948 * according to L0's settings (vmcs12 is irrelevant here). Host
11949 * fields that come from L0 and are not constant, e.g. HOST_CR3,
11950 * will be set as needed prior to VMLAUNCH/VMRESUME.
11952 if (vmx->nested.vmcs02_initialized)
11954 vmx->nested.vmcs02_initialized = true;
11956 /* All VMFUNCs are currently emulated through L0 vmexits. */
11957 if (cpu_has_vmx_vmfunc())
11958 vmcs_write64(VM_FUNCTION_CONTROL, 0);
11960 if (cpu_has_vmx_posted_intr())
11961 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
11963 if (cpu_has_vmx_msr_bitmap())
11964 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
11967 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
11970 * Set the MSR load/store lists to match L0's settings. Only the
11971 * addresses are constant (for vmcs02), the counts can change based
11972 * on L2's behavior, e.g. switching to/from long mode.
11974 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
11975 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
11976 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
11978 vmx_set_constant_host_state(vmx);
11981 static void prepare_vmcs02_early_full(struct vcpu_vmx *vmx,
11982 struct vmcs12 *vmcs12)
11984 prepare_vmcs02_constant_state(vmx);
11986 vmcs_write64(VMCS_LINK_POINTER, -1ull);
11989 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
11990 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
11992 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
11996 static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
11998 u32 exec_control, vmcs12_exec_ctrl;
11999 u64 guest_efer = nested_vmx_calc_efer(vmx, vmcs12);
12001 if (vmx->nested.dirty_vmcs12)
12002 prepare_vmcs02_early_full(vmx, vmcs12);
12005 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
12006 * entry, but only if the current (host) sp changed from the value
12007 * we wrote last (vmx->host_rsp). This cache is no longer relevant
12008 * if we switch vmcs, and rather than hold a separate cache per vmcs,
12009 * here we just force the write to happen on entry.
12016 exec_control = vmcs12->pin_based_vm_exec_control;
12018 /* Preemption timer setting is computed directly in vmx_vcpu_run. */
12019 exec_control |= vmcs_config.pin_based_exec_ctrl;
12020 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
12021 vmx->loaded_vmcs->hv_timer_armed = false;
12023 /* Posted interrupts setting is only taken from vmcs12. */
12024 if (nested_cpu_has_posted_intr(vmcs12)) {
12025 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
12026 vmx->nested.pi_pending = false;
12028 exec_control &= ~PIN_BASED_POSTED_INTR;
12030 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
12035 exec_control = vmx_exec_control(vmx); /* L0's desires */
12036 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
12037 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
12038 exec_control &= ~CPU_BASED_TPR_SHADOW;
12039 exec_control |= vmcs12->cpu_based_vm_exec_control;
12042 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
12043 * nested_get_vmcs12_pages can't fix it up, the illegal value
12044 * will result in a VM entry failure.
12046 if (exec_control & CPU_BASED_TPR_SHADOW) {
12047 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
12048 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
12050 #ifdef CONFIG_X86_64
12051 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
12052 CPU_BASED_CR8_STORE_EXITING;
12057 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
12058 * for I/O port accesses.
12060 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
12061 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
12062 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
12065 * SECONDARY EXEC CONTROLS
12067 if (cpu_has_secondary_exec_ctrls()) {
12068 exec_control = vmx->secondary_exec_control;
12070 /* Take the following fields only from vmcs12 */
12071 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
12072 SECONDARY_EXEC_ENABLE_INVPCID |
12073 SECONDARY_EXEC_RDTSCP |
12074 SECONDARY_EXEC_XSAVES |
12075 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
12076 SECONDARY_EXEC_APIC_REGISTER_VIRT |
12077 SECONDARY_EXEC_ENABLE_VMFUNC);
12078 if (nested_cpu_has(vmcs12,
12079 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
12080 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
12081 ~SECONDARY_EXEC_ENABLE_PML;
12082 exec_control |= vmcs12_exec_ctrl;
12085 /* VMCS shadowing for L2 is emulated for now */
12086 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
12088 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
12089 vmcs_write16(GUEST_INTR_STATUS,
12090 vmcs12->guest_intr_status);
12093 * Write an illegal value to APIC_ACCESS_ADDR. Later,
12094 * nested_get_vmcs12_pages will either fix it up or
12095 * remove the VM execution control.
12097 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
12098 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
12100 if (exec_control & SECONDARY_EXEC_ENCLS_EXITING)
12101 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
12103 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
12109 * vmcs12's VM_{ENTRY,EXIT}_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE
12110 * are emulated by vmx_set_efer() in prepare_vmcs02(), but speculate
12111 * on the related bits (if supported by the CPU) in the hope that
12112 * we can avoid VMWrites during vmx_set_efer().
12114 exec_control = (vmcs12->vm_entry_controls | vmcs_config.vmentry_ctrl) &
12115 ~VM_ENTRY_IA32E_MODE & ~VM_ENTRY_LOAD_IA32_EFER;
12116 if (cpu_has_load_ia32_efer) {
12117 if (guest_efer & EFER_LMA)
12118 exec_control |= VM_ENTRY_IA32E_MODE;
12119 if (guest_efer != host_efer)
12120 exec_control |= VM_ENTRY_LOAD_IA32_EFER;
12122 vm_entry_controls_init(vmx, exec_control);
12127 * L2->L1 exit controls are emulated - the hardware exit is to L0 so
12128 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
12129 * bits may be modified by vmx_set_efer() in prepare_vmcs02().
12131 exec_control = vmcs_config.vmexit_ctrl;
12132 if (cpu_has_load_ia32_efer && guest_efer != host_efer)
12133 exec_control |= VM_EXIT_LOAD_IA32_EFER;
12134 vm_exit_controls_init(vmx, exec_control);
12137 * Conceptually we want to copy the PML address and index from
12138 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
12139 * since we always flush the log on each vmexit and never change
12140 * the PML address (once set), this happens to be equivalent to
12141 * simply resetting the index in vmcs02.
12144 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
12147 * Interrupt/Exception Fields
12149 if (vmx->nested.nested_run_pending) {
12150 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
12151 vmcs12->vm_entry_intr_info_field);
12152 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
12153 vmcs12->vm_entry_exception_error_code);
12154 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
12155 vmcs12->vm_entry_instruction_len);
12156 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
12157 vmcs12->guest_interruptibility_info);
12158 vmx->loaded_vmcs->nmi_known_unmasked =
12159 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
12161 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
12165 static void prepare_vmcs02_full(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
12167 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
12168 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
12169 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
12170 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
12171 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
12172 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
12173 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
12174 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
12175 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
12176 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
12177 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
12178 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
12179 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
12180 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
12181 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
12182 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
12183 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
12184 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
12185 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
12186 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
12187 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
12188 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
12189 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
12190 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
12191 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
12192 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
12193 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
12194 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
12195 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
12196 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
12197 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
12199 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
12200 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
12201 vmcs12->guest_pending_dbg_exceptions);
12202 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
12203 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
12205 if (nested_cpu_has_xsaves(vmcs12))
12206 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
12209 * Whether page-faults are trapped is determined by a combination of
12210 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
12211 * If enable_ept, L0 doesn't care about page faults and we should
12212 * set all of these to L1's desires. However, if !enable_ept, L0 does
12213 * care about (at least some) page faults, and because it is not easy
12214 * (if at all possible?) to merge L0 and L1's desires, we simply ask
12215 * to exit on each and every L2 page fault. This is done by setting
12216 * MASK=MATCH=0 and (see below) EB.PF=1.
12217 * Note that below we don't need special code to set EB.PF beyond the
12218 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
12219 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
12220 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
12222 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
12223 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
12224 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
12225 enable_ept ? vmcs12->page_fault_error_code_match : 0);
12227 if (cpu_has_vmx_apicv()) {
12228 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
12229 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
12230 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
12231 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
12234 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
12235 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
12237 set_cr4_guest_host_mask(vmx);
12239 if (kvm_mpx_supported()) {
12240 if (vmx->nested.nested_run_pending &&
12241 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
12242 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
12244 vmcs_write64(GUEST_BNDCFGS, vmx->nested.vmcs01_guest_bndcfgs);
12248 * L1 may access the L2's PDPTR, so save them to construct vmcs12
12251 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
12252 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
12253 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
12254 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
12259 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
12260 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
12261 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
12262 * guest in a way that will both be appropriate to L1's requests, and our
12263 * needs. In addition to modifying the active vmcs (which is vmcs02), this
12264 * function also has additional necessary side-effects, like setting various
12265 * vcpu->arch fields.
12266 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
12267 * is assigned to entry_failure_code on failure.
12269 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12270 u32 *entry_failure_code)
12272 struct vcpu_vmx *vmx = to_vmx(vcpu);
12274 if (vmx->nested.dirty_vmcs12) {
12275 prepare_vmcs02_full(vmx, vmcs12);
12276 vmx->nested.dirty_vmcs12 = false;
12280 * First, the fields that are shadowed. This must be kept in sync
12281 * with vmx_shadow_fields.h.
12284 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
12285 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
12286 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
12287 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
12288 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
12290 if (vmx->nested.nested_run_pending &&
12291 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
12292 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
12293 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
12295 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
12296 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
12298 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
12300 vmx->nested.preemption_timer_expired = false;
12301 if (nested_cpu_has_preemption_timer(vmcs12))
12302 vmx_start_preemption_timer(vcpu);
12304 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
12305 * bitwise-or of what L1 wants to trap for L2, and what we want to
12306 * trap. Note that CR0.TS also needs updating - we do this later.
12308 update_exception_bitmap(vcpu);
12309 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
12310 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
12312 if (vmx->nested.nested_run_pending &&
12313 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
12314 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
12315 vcpu->arch.pat = vmcs12->guest_ia32_pat;
12316 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
12317 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
12320 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
12322 if (kvm_has_tsc_control)
12323 decache_tsc_multiplier(vmx);
12327 * There is no direct mapping between vpid02 and vpid12, the
12328 * vpid02 is per-vCPU for L0 and reused while the value of
12329 * vpid12 is changed w/ one invvpid during nested vmentry.
12330 * The vpid12 is allocated by L1 for L2, so it will not
12331 * influence global bitmap(for vpid01 and vpid02 allocation)
12332 * even if spawn a lot of nested vCPUs.
12334 if (nested_cpu_has_vpid(vmcs12) && nested_has_guest_tlb_tag(vcpu)) {
12335 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
12336 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
12337 __vmx_flush_tlb(vcpu, nested_get_vpid02(vcpu), false);
12341 * If L1 use EPT, then L0 needs to execute INVEPT on
12342 * EPTP02 instead of EPTP01. Therefore, delay TLB
12343 * flush until vmcs02->eptp is fully updated by
12344 * KVM_REQ_LOAD_CR3. Note that this assumes
12345 * KVM_REQ_TLB_FLUSH is evaluated after
12346 * KVM_REQ_LOAD_CR3 in vcpu_enter_guest().
12348 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
12352 if (nested_cpu_has_ept(vmcs12))
12353 nested_ept_init_mmu_context(vcpu);
12354 else if (nested_cpu_has2(vmcs12,
12355 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
12356 vmx_flush_tlb(vcpu, true);
12359 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
12360 * bits which we consider mandatory enabled.
12361 * The CR0_READ_SHADOW is what L2 should have expected to read given
12362 * the specifications by L1; It's not enough to take
12363 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
12364 * have more bits than L1 expected.
12366 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
12367 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
12369 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
12370 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
12372 vcpu->arch.efer = nested_vmx_calc_efer(vmx, vmcs12);
12373 /* Note: may modify VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
12374 vmx_set_efer(vcpu, vcpu->arch.efer);
12377 * Guest state is invalid and unrestricted guest is disabled,
12378 * which means L1 attempted VMEntry to L2 with invalid state.
12379 * Fail the VMEntry.
12381 if (vmx->emulation_required) {
12382 *entry_failure_code = ENTRY_FAIL_DEFAULT;
12386 /* Shadow page tables on either EPT or shadow page tables. */
12387 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
12388 entry_failure_code))
12392 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
12394 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
12395 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
12399 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
12401 if (!nested_cpu_has_nmi_exiting(vmcs12) &&
12402 nested_cpu_has_virtual_nmis(vmcs12))
12405 if (!nested_cpu_has_virtual_nmis(vmcs12) &&
12406 nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING))
12412 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12414 struct vcpu_vmx *vmx = to_vmx(vcpu);
12417 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
12418 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
12419 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12421 if (nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id)
12422 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12424 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
12425 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12427 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
12428 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12430 if (nested_vmx_check_apic_access_controls(vcpu, vmcs12))
12431 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12433 if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
12434 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12436 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
12437 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12439 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
12440 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12442 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
12443 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12445 if (nested_vmx_check_shadow_vmcs_controls(vcpu, vmcs12))
12446 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12448 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
12449 vmx->nested.msrs.procbased_ctls_low,
12450 vmx->nested.msrs.procbased_ctls_high) ||
12451 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
12452 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
12453 vmx->nested.msrs.secondary_ctls_low,
12454 vmx->nested.msrs.secondary_ctls_high)) ||
12455 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
12456 vmx->nested.msrs.pinbased_ctls_low,
12457 vmx->nested.msrs.pinbased_ctls_high) ||
12458 !vmx_control_verify(vmcs12->vm_exit_controls,
12459 vmx->nested.msrs.exit_ctls_low,
12460 vmx->nested.msrs.exit_ctls_high) ||
12461 !vmx_control_verify(vmcs12->vm_entry_controls,
12462 vmx->nested.msrs.entry_ctls_low,
12463 vmx->nested.msrs.entry_ctls_high))
12464 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12466 if (nested_vmx_check_nmi_controls(vmcs12))
12467 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12469 if (nested_cpu_has_vmfunc(vmcs12)) {
12470 if (vmcs12->vm_function_control &
12471 ~vmx->nested.msrs.vmfunc_controls)
12472 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12474 if (nested_cpu_has_eptp_switching(vmcs12)) {
12475 if (!nested_cpu_has_ept(vmcs12) ||
12476 !page_address_valid(vcpu, vmcs12->eptp_list_address))
12477 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12481 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
12482 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12484 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
12485 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
12486 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
12487 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
12490 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
12491 * IA32_EFER MSR must be 0 in the field for that register. In addition,
12492 * the values of the LMA and LME bits in the field must each be that of
12493 * the host address-space size VM-exit control.
12495 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
12496 ia32e = (vmcs12->vm_exit_controls &
12497 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
12498 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
12499 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
12500 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
12501 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
12505 * From the Intel SDM, volume 3:
12506 * Fields relevant to VM-entry event injection must be set properly.
12507 * These fields are the VM-entry interruption-information field, the
12508 * VM-entry exception error code, and the VM-entry instruction length.
12510 if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) {
12511 u32 intr_info = vmcs12->vm_entry_intr_info_field;
12512 u8 vector = intr_info & INTR_INFO_VECTOR_MASK;
12513 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK;
12514 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK;
12515 bool should_have_error_code;
12516 bool urg = nested_cpu_has2(vmcs12,
12517 SECONDARY_EXEC_UNRESTRICTED_GUEST);
12518 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE;
12520 /* VM-entry interruption-info field: interruption type */
12521 if (intr_type == INTR_TYPE_RESERVED ||
12522 (intr_type == INTR_TYPE_OTHER_EVENT &&
12523 !nested_cpu_supports_monitor_trap_flag(vcpu)))
12524 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12526 /* VM-entry interruption-info field: vector */
12527 if ((intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) ||
12528 (intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) ||
12529 (intr_type == INTR_TYPE_OTHER_EVENT && vector != 0))
12530 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12532 /* VM-entry interruption-info field: deliver error code */
12533 should_have_error_code =
12534 intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode &&
12535 x86_exception_has_error_code(vector);
12536 if (has_error_code != should_have_error_code)
12537 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12539 /* VM-entry exception error code */
12540 if (has_error_code &&
12541 vmcs12->vm_entry_exception_error_code & GENMASK(31, 15))
12542 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12544 /* VM-entry interruption-info field: reserved bits */
12545 if (intr_info & INTR_INFO_RESVD_BITS_MASK)
12546 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12548 /* VM-entry instruction length */
12549 switch (intr_type) {
12550 case INTR_TYPE_SOFT_EXCEPTION:
12551 case INTR_TYPE_SOFT_INTR:
12552 case INTR_TYPE_PRIV_SW_EXCEPTION:
12553 if ((vmcs12->vm_entry_instruction_len > 15) ||
12554 (vmcs12->vm_entry_instruction_len == 0 &&
12555 !nested_cpu_has_zero_length_injection(vcpu)))
12556 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12560 if (nested_cpu_has_ept(vmcs12) &&
12561 !valid_ept_address(vcpu, vmcs12->ept_pointer))
12562 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12567 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu,
12568 struct vmcs12 *vmcs12)
12572 struct vmcs12 *shadow;
12574 if (vmcs12->vmcs_link_pointer == -1ull)
12577 if (!page_address_valid(vcpu, vmcs12->vmcs_link_pointer))
12580 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->vmcs_link_pointer);
12581 if (is_error_page(page))
12585 shadow = kmap(page);
12586 if (shadow->hdr.revision_id != VMCS12_REVISION ||
12587 shadow->hdr.shadow_vmcs != nested_cpu_has_shadow_vmcs(vmcs12))
12590 kvm_release_page_clean(page);
12594 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12599 *exit_qual = ENTRY_FAIL_DEFAULT;
12601 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
12602 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
12605 if (nested_vmx_check_vmcs_link_ptr(vcpu, vmcs12)) {
12606 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
12611 * If the load IA32_EFER VM-entry control is 1, the following checks
12612 * are performed on the field for the IA32_EFER MSR:
12613 * - Bits reserved in the IA32_EFER MSR must be 0.
12614 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
12615 * the IA-32e mode guest VM-exit control. It must also be identical
12616 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
12619 if (to_vmx(vcpu)->nested.nested_run_pending &&
12620 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
12621 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
12622 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
12623 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
12624 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
12625 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
12629 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
12630 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
12631 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
12637 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
12638 struct vmcs12 *vmcs12);
12641 * If from_vmentry is false, this is being called from state restore (either RSM
12642 * or KVM_SET_NESTED_STATE). Otherwise it's called from vmlaunch/vmresume.
12644 static int nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
12647 struct vcpu_vmx *vmx = to_vmx(vcpu);
12648 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12649 bool evaluate_pending_interrupts;
12650 u32 exit_reason = EXIT_REASON_INVALID_STATE;
12653 evaluate_pending_interrupts = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
12654 (CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_VIRTUAL_NMI_PENDING);
12655 if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu))
12656 evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu);
12658 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
12659 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
12660 if (kvm_mpx_supported() &&
12661 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
12662 vmx->nested.vmcs01_guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
12664 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
12666 prepare_vmcs02_early(vmx, vmcs12);
12668 if (from_vmentry) {
12669 nested_get_vmcs12_pages(vcpu);
12671 if (check_vmentry_postreqs(vcpu, vmcs12, &exit_qual))
12672 goto vmentry_fail_vmexit;
12675 enter_guest_mode(vcpu);
12676 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12677 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
12679 if (prepare_vmcs02(vcpu, vmcs12, &exit_qual))
12680 goto vmentry_fail_vmexit_guest_mode;
12682 if (from_vmentry) {
12683 exit_reason = EXIT_REASON_MSR_LOAD_FAIL;
12684 exit_qual = nested_vmx_load_msr(vcpu,
12685 vmcs12->vm_entry_msr_load_addr,
12686 vmcs12->vm_entry_msr_load_count);
12688 goto vmentry_fail_vmexit_guest_mode;
12691 * The MMU is not initialized to point at the right entities yet and
12692 * "get pages" would need to read data from the guest (i.e. we will
12693 * need to perform gpa to hpa translation). Request a call
12694 * to nested_get_vmcs12_pages before the next VM-entry. The MSRs
12695 * have already been set at vmentry time and should not be reset.
12697 kvm_make_request(KVM_REQ_GET_VMCS12_PAGES, vcpu);
12701 * If L1 had a pending IRQ/NMI until it executed
12702 * VMLAUNCH/VMRESUME which wasn't delivered because it was
12703 * disallowed (e.g. interrupts disabled), L0 needs to
12704 * evaluate if this pending event should cause an exit from L2
12705 * to L1 or delivered directly to L2 (e.g. In case L1 don't
12706 * intercept EXTERNAL_INTERRUPT).
12708 * Usually this would be handled by the processor noticing an
12709 * IRQ/NMI window request, or checking RVI during evaluation of
12710 * pending virtual interrupts. However, this setting was done
12711 * on VMCS01 and now VMCS02 is active instead. Thus, we force L0
12712 * to perform pending event evaluation by requesting a KVM_REQ_EVENT.
12714 if (unlikely(evaluate_pending_interrupts))
12715 kvm_make_request(KVM_REQ_EVENT, vcpu);
12718 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
12719 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
12720 * returned as far as L1 is concerned. It will only return (and set
12721 * the success flag) when L2 exits (see nested_vmx_vmexit()).
12726 * A failed consistency check that leads to a VMExit during L1's
12727 * VMEnter to L2 is a variation of a normal VMexit, as explained in
12728 * 26.7 "VM-entry failures during or after loading guest state".
12730 vmentry_fail_vmexit_guest_mode:
12731 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12732 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
12733 leave_guest_mode(vcpu);
12735 vmentry_fail_vmexit:
12736 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12741 load_vmcs12_host_state(vcpu, vmcs12);
12742 vmcs12->vm_exit_reason = exit_reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
12743 vmcs12->exit_qualification = exit_qual;
12744 if (enable_shadow_vmcs)
12745 vmx->nested.sync_shadow_vmcs = true;
12750 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
12751 * for running an L2 nested guest.
12753 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
12755 struct vmcs12 *vmcs12;
12756 struct vcpu_vmx *vmx = to_vmx(vcpu);
12757 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
12760 if (!nested_vmx_check_permission(vcpu))
12763 if (vmx->nested.current_vmptr == -1ull)
12764 return nested_vmx_failInvalid(vcpu);
12766 vmcs12 = get_vmcs12(vcpu);
12769 * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact
12770 * that there *is* a valid VMCS pointer, RFLAGS.CF is set
12771 * rather than RFLAGS.ZF, and no error number is stored to the
12772 * VM-instruction error field.
12774 if (vmcs12->hdr.shadow_vmcs)
12775 return nested_vmx_failInvalid(vcpu);
12777 if (enable_shadow_vmcs)
12778 copy_shadow_to_vmcs12(vmx);
12781 * The nested entry process starts with enforcing various prerequisites
12782 * on vmcs12 as required by the Intel SDM, and act appropriately when
12783 * they fail: As the SDM explains, some conditions should cause the
12784 * instruction to fail, while others will cause the instruction to seem
12785 * to succeed, but return an EXIT_REASON_INVALID_STATE.
12786 * To speed up the normal (success) code path, we should avoid checking
12787 * for misconfigurations which will anyway be caught by the processor
12788 * when using the merged vmcs02.
12790 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS)
12791 return nested_vmx_failValid(vcpu,
12792 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
12794 if (vmcs12->launch_state == launch)
12795 return nested_vmx_failValid(vcpu,
12796 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
12797 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
12799 ret = check_vmentry_prereqs(vcpu, vmcs12);
12801 return nested_vmx_failValid(vcpu, ret);
12804 * We're finally done with prerequisite checking, and can start with
12805 * the nested entry.
12808 vmx->nested.nested_run_pending = 1;
12809 ret = nested_vmx_enter_non_root_mode(vcpu, true);
12811 vmx->nested.nested_run_pending = 0;
12815 /* Hide L1D cache contents from the nested guest. */
12816 vmx->vcpu.arch.l1tf_flush_l1d = true;
12819 * Must happen outside of nested_vmx_enter_non_root_mode() as it will
12820 * also be used as part of restoring nVMX state for
12821 * snapshot restore (migration).
12823 * In this flow, it is assumed that vmcs12 cache was
12824 * trasferred as part of captured nVMX state and should
12825 * therefore not be read from guest memory (which may not
12826 * exist on destination host yet).
12828 nested_cache_shadow_vmcs12(vcpu, vmcs12);
12831 * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
12832 * by event injection, halt vcpu.
12834 if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
12835 !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK)) {
12836 vmx->nested.nested_run_pending = 0;
12837 return kvm_vcpu_halt(vcpu);
12843 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
12844 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
12845 * This function returns the new value we should put in vmcs12.guest_cr0.
12846 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
12847 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
12848 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
12849 * didn't trap the bit, because if L1 did, so would L0).
12850 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
12851 * been modified by L2, and L1 knows it. So just leave the old value of
12852 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
12853 * isn't relevant, because if L0 traps this bit it can set it to anything.
12854 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
12855 * changed these bits, and therefore they need to be updated, but L0
12856 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
12857 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
12859 static inline unsigned long
12860 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12863 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
12864 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
12865 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
12866 vcpu->arch.cr0_guest_owned_bits));
12869 static inline unsigned long
12870 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12873 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
12874 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
12875 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
12876 vcpu->arch.cr4_guest_owned_bits));
12879 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
12880 struct vmcs12 *vmcs12)
12885 if (vcpu->arch.exception.injected) {
12886 nr = vcpu->arch.exception.nr;
12887 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
12889 if (kvm_exception_is_soft(nr)) {
12890 vmcs12->vm_exit_instruction_len =
12891 vcpu->arch.event_exit_inst_len;
12892 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
12894 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
12896 if (vcpu->arch.exception.has_error_code) {
12897 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
12898 vmcs12->idt_vectoring_error_code =
12899 vcpu->arch.exception.error_code;
12902 vmcs12->idt_vectoring_info_field = idt_vectoring;
12903 } else if (vcpu->arch.nmi_injected) {
12904 vmcs12->idt_vectoring_info_field =
12905 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
12906 } else if (vcpu->arch.interrupt.injected) {
12907 nr = vcpu->arch.interrupt.nr;
12908 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
12910 if (vcpu->arch.interrupt.soft) {
12911 idt_vectoring |= INTR_TYPE_SOFT_INTR;
12912 vmcs12->vm_entry_instruction_len =
12913 vcpu->arch.event_exit_inst_len;
12915 idt_vectoring |= INTR_TYPE_EXT_INTR;
12917 vmcs12->idt_vectoring_info_field = idt_vectoring;
12921 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
12923 struct vcpu_vmx *vmx = to_vmx(vcpu);
12924 unsigned long exit_qual;
12925 bool block_nested_events =
12926 vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
12928 if (vcpu->arch.exception.pending &&
12929 nested_vmx_check_exception(vcpu, &exit_qual)) {
12930 if (block_nested_events)
12932 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
12936 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
12937 vmx->nested.preemption_timer_expired) {
12938 if (block_nested_events)
12940 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
12944 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
12945 if (block_nested_events)
12947 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
12948 NMI_VECTOR | INTR_TYPE_NMI_INTR |
12949 INTR_INFO_VALID_MASK, 0);
12951 * The NMI-triggered VM exit counts as injection:
12952 * clear this one and block further NMIs.
12954 vcpu->arch.nmi_pending = 0;
12955 vmx_set_nmi_mask(vcpu, true);
12959 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
12960 nested_exit_on_intr(vcpu)) {
12961 if (block_nested_events)
12963 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
12967 vmx_complete_nested_posted_interrupt(vcpu);
12971 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
12973 to_vmx(vcpu)->req_immediate_exit = true;
12976 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
12978 ktime_t remaining =
12979 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
12982 if (ktime_to_ns(remaining) <= 0)
12985 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
12986 do_div(value, 1000000);
12987 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
12991 * Update the guest state fields of vmcs12 to reflect changes that
12992 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
12993 * VM-entry controls is also updated, since this is really a guest
12996 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12998 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
12999 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
13001 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
13002 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
13003 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
13005 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
13006 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
13007 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
13008 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
13009 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
13010 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
13011 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
13012 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
13013 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
13014 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
13015 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
13016 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
13017 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
13018 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
13019 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
13020 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
13021 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
13022 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
13023 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
13024 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
13025 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
13026 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
13027 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
13028 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
13029 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
13030 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
13031 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
13032 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
13033 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
13034 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
13035 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
13036 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
13037 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
13038 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
13039 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
13040 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
13042 vmcs12->guest_interruptibility_info =
13043 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
13044 vmcs12->guest_pending_dbg_exceptions =
13045 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
13046 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
13047 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
13049 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
13051 if (nested_cpu_has_preemption_timer(vmcs12)) {
13052 if (vmcs12->vm_exit_controls &
13053 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
13054 vmcs12->vmx_preemption_timer_value =
13055 vmx_get_preemption_timer_value(vcpu);
13056 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
13060 * In some cases (usually, nested EPT), L2 is allowed to change its
13061 * own CR3 without exiting. If it has changed it, we must keep it.
13062 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
13063 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
13065 * Additionally, restore L2's PDPTR to vmcs12.
13068 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
13069 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
13070 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
13071 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
13072 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
13075 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
13077 if (nested_cpu_has_vid(vmcs12))
13078 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
13080 vmcs12->vm_entry_controls =
13081 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
13082 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
13084 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
13085 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
13086 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
13089 /* TODO: These cannot have changed unless we have MSR bitmaps and
13090 * the relevant bit asks not to trap the change */
13091 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
13092 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
13093 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
13094 vmcs12->guest_ia32_efer = vcpu->arch.efer;
13095 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
13096 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
13097 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
13098 if (kvm_mpx_supported())
13099 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
13103 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
13104 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
13105 * and this function updates it to reflect the changes to the guest state while
13106 * L2 was running (and perhaps made some exits which were handled directly by L0
13107 * without going back to L1), and to reflect the exit reason.
13108 * Note that we do not have to copy here all VMCS fields, just those that
13109 * could have changed by the L2 guest or the exit - i.e., the guest-state and
13110 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
13111 * which already writes to vmcs12 directly.
13113 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
13114 u32 exit_reason, u32 exit_intr_info,
13115 unsigned long exit_qualification)
13117 /* update guest state fields: */
13118 sync_vmcs12(vcpu, vmcs12);
13120 /* update exit information fields: */
13122 vmcs12->vm_exit_reason = exit_reason;
13123 vmcs12->exit_qualification = exit_qualification;
13124 vmcs12->vm_exit_intr_info = exit_intr_info;
13126 vmcs12->idt_vectoring_info_field = 0;
13127 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
13128 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
13130 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
13131 vmcs12->launch_state = 1;
13133 /* vm_entry_intr_info_field is cleared on exit. Emulate this
13134 * instead of reading the real value. */
13135 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
13138 * Transfer the event that L0 or L1 may wanted to inject into
13139 * L2 to IDT_VECTORING_INFO_FIELD.
13141 vmcs12_save_pending_event(vcpu, vmcs12);
13145 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
13146 * preserved above and would only end up incorrectly in L1.
13148 vcpu->arch.nmi_injected = false;
13149 kvm_clear_exception_queue(vcpu);
13150 kvm_clear_interrupt_queue(vcpu);
13154 * A part of what we need to when the nested L2 guest exits and we want to
13155 * run its L1 parent, is to reset L1's guest state to the host state specified
13157 * This function is to be called not only on normal nested exit, but also on
13158 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
13159 * Failures During or After Loading Guest State").
13160 * This function should be called when the active VMCS is L1's (vmcs01).
13162 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
13163 struct vmcs12 *vmcs12)
13165 struct kvm_segment seg;
13166 u32 entry_failure_code;
13168 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
13169 vcpu->arch.efer = vmcs12->host_ia32_efer;
13170 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
13171 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
13173 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
13174 vmx_set_efer(vcpu, vcpu->arch.efer);
13176 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
13177 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
13178 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
13179 vmx_set_interrupt_shadow(vcpu, 0);
13182 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
13183 * actually changed, because vmx_set_cr0 refers to efer set above.
13185 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
13186 * (KVM doesn't change it);
13188 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
13189 vmx_set_cr0(vcpu, vmcs12->host_cr0);
13191 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
13192 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
13193 vmx_set_cr4(vcpu, vmcs12->host_cr4);
13195 nested_ept_uninit_mmu_context(vcpu);
13198 * Only PDPTE load can fail as the value of cr3 was checked on entry and
13199 * couldn't have changed.
13201 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
13202 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
13205 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
13208 * If vmcs01 doesn't use VPID, CPU flushes TLB on every
13209 * VMEntry/VMExit. Thus, no need to flush TLB.
13211 * If vmcs12 doesn't use VPID, L1 expects TLB to be
13212 * flushed on every VMEntry/VMExit.
13214 * Otherwise, we can preserve TLB entries as long as we are
13215 * able to tag L1 TLB entries differently than L2 TLB entries.
13217 * If vmcs12 uses EPT, we need to execute this flush on EPTP01
13218 * and therefore we request the TLB flush to happen only after VMCS EPTP
13219 * has been set by KVM_REQ_LOAD_CR3.
13222 (!nested_cpu_has_vpid(vmcs12) || !nested_has_guest_tlb_tag(vcpu))) {
13223 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
13226 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
13227 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
13228 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
13229 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
13230 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
13231 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
13232 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
13234 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
13235 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
13236 vmcs_write64(GUEST_BNDCFGS, 0);
13238 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
13239 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
13240 vcpu->arch.pat = vmcs12->host_ia32_pat;
13242 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
13243 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
13244 vmcs12->host_ia32_perf_global_ctrl);
13246 /* Set L1 segment info according to Intel SDM
13247 27.5.2 Loading Host Segment and Descriptor-Table Registers */
13248 seg = (struct kvm_segment) {
13250 .limit = 0xFFFFFFFF,
13251 .selector = vmcs12->host_cs_selector,
13257 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
13261 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
13262 seg = (struct kvm_segment) {
13264 .limit = 0xFFFFFFFF,
13271 seg.selector = vmcs12->host_ds_selector;
13272 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
13273 seg.selector = vmcs12->host_es_selector;
13274 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
13275 seg.selector = vmcs12->host_ss_selector;
13276 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
13277 seg.selector = vmcs12->host_fs_selector;
13278 seg.base = vmcs12->host_fs_base;
13279 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
13280 seg.selector = vmcs12->host_gs_selector;
13281 seg.base = vmcs12->host_gs_base;
13282 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
13283 seg = (struct kvm_segment) {
13284 .base = vmcs12->host_tr_base,
13286 .selector = vmcs12->host_tr_selector,
13290 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
13292 kvm_set_dr(vcpu, 7, 0x400);
13293 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
13295 if (cpu_has_vmx_msr_bitmap())
13296 vmx_update_msr_bitmap(vcpu);
13298 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
13299 vmcs12->vm_exit_msr_load_count))
13300 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
13303 static inline u64 nested_vmx_get_vmcs01_guest_efer(struct vcpu_vmx *vmx)
13305 struct shared_msr_entry *efer_msr;
13308 if (vm_entry_controls_get(vmx) & VM_ENTRY_LOAD_IA32_EFER)
13309 return vmcs_read64(GUEST_IA32_EFER);
13311 if (cpu_has_load_ia32_efer)
13314 for (i = 0; i < vmx->msr_autoload.guest.nr; ++i) {
13315 if (vmx->msr_autoload.guest.val[i].index == MSR_EFER)
13316 return vmx->msr_autoload.guest.val[i].value;
13319 efer_msr = find_msr_entry(vmx, MSR_EFER);
13321 return efer_msr->data;
13326 static void nested_vmx_restore_host_state(struct kvm_vcpu *vcpu)
13328 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
13329 struct vcpu_vmx *vmx = to_vmx(vcpu);
13330 struct vmx_msr_entry g, h;
13331 struct msr_data msr;
13335 vcpu->arch.pat = vmcs_read64(GUEST_IA32_PAT);
13337 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
13339 * L1's host DR7 is lost if KVM_GUESTDBG_USE_HW_BP is set
13340 * as vmcs01.GUEST_DR7 contains a userspace defined value
13341 * and vcpu->arch.dr7 is not squirreled away before the
13342 * nested VMENTER (not worth adding a variable in nested_vmx).
13344 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
13345 kvm_set_dr(vcpu, 7, DR7_FIXED_1);
13347 WARN_ON(kvm_set_dr(vcpu, 7, vmcs_readl(GUEST_DR7)));
13351 * Note that calling vmx_set_{efer,cr0,cr4} is important as they
13352 * handle a variety of side effects to KVM's software model.
13354 vmx_set_efer(vcpu, nested_vmx_get_vmcs01_guest_efer(vmx));
13356 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
13357 vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW));
13359 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
13360 vmx_set_cr4(vcpu, vmcs_readl(CR4_READ_SHADOW));
13362 nested_ept_uninit_mmu_context(vcpu);
13363 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
13364 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
13367 * Use ept_save_pdptrs(vcpu) to load the MMU's cached PDPTRs
13368 * from vmcs01 (if necessary). The PDPTRs are not loaded on
13369 * VMFail, like everything else we just need to ensure our
13370 * software model is up-to-date.
13372 ept_save_pdptrs(vcpu);
13374 kvm_mmu_reset_context(vcpu);
13376 if (cpu_has_vmx_msr_bitmap())
13377 vmx_update_msr_bitmap(vcpu);
13380 * This nasty bit of open coding is a compromise between blindly
13381 * loading L1's MSRs using the exit load lists (incorrect emulation
13382 * of VMFail), leaving the nested VM's MSRs in the software model
13383 * (incorrect behavior) and snapshotting the modified MSRs (too
13384 * expensive since the lists are unbound by hardware). For each
13385 * MSR that was (prematurely) loaded from the nested VMEntry load
13386 * list, reload it from the exit load list if it exists and differs
13387 * from the guest value. The intent is to stuff host state as
13388 * silently as possible, not to fully process the exit load list.
13390 msr.host_initiated = false;
13391 for (i = 0; i < vmcs12->vm_entry_msr_load_count; i++) {
13392 gpa = vmcs12->vm_entry_msr_load_addr + (i * sizeof(g));
13393 if (kvm_vcpu_read_guest(vcpu, gpa, &g, sizeof(g))) {
13394 pr_debug_ratelimited(
13395 "%s read MSR index failed (%u, 0x%08llx)\n",
13400 for (j = 0; j < vmcs12->vm_exit_msr_load_count; j++) {
13401 gpa = vmcs12->vm_exit_msr_load_addr + (j * sizeof(h));
13402 if (kvm_vcpu_read_guest(vcpu, gpa, &h, sizeof(h))) {
13403 pr_debug_ratelimited(
13404 "%s read MSR failed (%u, 0x%08llx)\n",
13408 if (h.index != g.index)
13410 if (h.value == g.value)
13413 if (nested_vmx_load_msr_check(vcpu, &h)) {
13414 pr_debug_ratelimited(
13415 "%s check failed (%u, 0x%x, 0x%x)\n",
13416 __func__, j, h.index, h.reserved);
13420 msr.index = h.index;
13421 msr.data = h.value;
13422 if (kvm_set_msr(vcpu, &msr)) {
13423 pr_debug_ratelimited(
13424 "%s WRMSR failed (%u, 0x%x, 0x%llx)\n",
13425 __func__, j, h.index, h.value);
13434 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
13438 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
13439 * and modify vmcs12 to make it see what it would expect to see there if
13440 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
13442 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
13443 u32 exit_intr_info,
13444 unsigned long exit_qualification)
13446 struct vcpu_vmx *vmx = to_vmx(vcpu);
13447 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
13449 /* trying to cancel vmlaunch/vmresume is a bug */
13450 WARN_ON_ONCE(vmx->nested.nested_run_pending);
13453 * The only expected VM-instruction error is "VM entry with
13454 * invalid control field(s)." Anything else indicates a
13457 WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
13458 VMXERR_ENTRY_INVALID_CONTROL_FIELD));
13460 leave_guest_mode(vcpu);
13462 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
13463 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
13465 if (likely(!vmx->fail)) {
13466 if (exit_reason == -1)
13467 sync_vmcs12(vcpu, vmcs12);
13469 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
13470 exit_qualification);
13473 * Must happen outside of sync_vmcs12() as it will
13474 * also be used to capture vmcs12 cache as part of
13475 * capturing nVMX state for snapshot (migration).
13477 * Otherwise, this flush will dirty guest memory at a
13478 * point it is already assumed by user-space to be
13481 nested_flush_cached_shadow_vmcs12(vcpu, vmcs12);
13483 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
13484 vmcs12->vm_exit_msr_store_count))
13485 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
13488 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
13490 /* Update any VMCS fields that might have changed while L2 ran */
13491 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
13492 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
13493 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
13495 if (kvm_has_tsc_control)
13496 decache_tsc_multiplier(vmx);
13498 if (vmx->nested.change_vmcs01_virtual_apic_mode) {
13499 vmx->nested.change_vmcs01_virtual_apic_mode = false;
13500 vmx_set_virtual_apic_mode(vcpu);
13501 } else if (!nested_cpu_has_ept(vmcs12) &&
13502 nested_cpu_has2(vmcs12,
13503 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
13504 vmx_flush_tlb(vcpu, true);
13507 /* This is needed for same reason as it was needed in prepare_vmcs02 */
13510 /* Unpin physical memory we referred to in vmcs02 */
13511 if (vmx->nested.apic_access_page) {
13512 kvm_release_page_dirty(vmx->nested.apic_access_page);
13513 vmx->nested.apic_access_page = NULL;
13515 if (vmx->nested.virtual_apic_page) {
13516 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
13517 vmx->nested.virtual_apic_page = NULL;
13519 if (vmx->nested.pi_desc_page) {
13520 kunmap(vmx->nested.pi_desc_page);
13521 kvm_release_page_dirty(vmx->nested.pi_desc_page);
13522 vmx->nested.pi_desc_page = NULL;
13523 vmx->nested.pi_desc = NULL;
13527 * We are now running in L2, mmu_notifier will force to reload the
13528 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
13530 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
13532 if (enable_shadow_vmcs && exit_reason != -1)
13533 vmx->nested.sync_shadow_vmcs = true;
13535 /* in case we halted in L2 */
13536 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13538 if (likely(!vmx->fail)) {
13540 * TODO: SDM says that with acknowledge interrupt on
13541 * exit, bit 31 of the VM-exit interrupt information
13542 * (valid interrupt) is always set to 1 on
13543 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
13544 * need kvm_cpu_has_interrupt(). See the commit
13545 * message for details.
13547 if (nested_exit_intr_ack_set(vcpu) &&
13548 exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
13549 kvm_cpu_has_interrupt(vcpu)) {
13550 int irq = kvm_cpu_get_interrupt(vcpu);
13552 vmcs12->vm_exit_intr_info = irq |
13553 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
13556 if (exit_reason != -1)
13557 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
13558 vmcs12->exit_qualification,
13559 vmcs12->idt_vectoring_info_field,
13560 vmcs12->vm_exit_intr_info,
13561 vmcs12->vm_exit_intr_error_code,
13564 load_vmcs12_host_state(vcpu, vmcs12);
13570 * After an early L2 VM-entry failure, we're now back
13571 * in L1 which thinks it just finished a VMLAUNCH or
13572 * VMRESUME instruction, so we need to set the failure
13573 * flag and the VM-instruction error field of the VMCS
13574 * accordingly, and skip the emulated instruction.
13576 (void)nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
13579 * Restore L1's host state to KVM's software model. We're here
13580 * because a consistency check was caught by hardware, which
13581 * means some amount of guest state has been propagated to KVM's
13582 * model and needs to be unwound to the host's state.
13584 nested_vmx_restore_host_state(vcpu);
13590 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
13592 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
13594 if (is_guest_mode(vcpu)) {
13595 to_vmx(vcpu)->nested.nested_run_pending = 0;
13596 nested_vmx_vmexit(vcpu, -1, 0, 0);
13598 free_nested(to_vmx(vcpu));
13601 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
13602 struct x86_instruction_info *info,
13603 enum x86_intercept_stage stage)
13605 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
13606 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
13609 * RDPID causes #UD if disabled through secondary execution controls.
13610 * Because it is marked as EmulateOnUD, we need to intercept it here.
13612 if (info->intercept == x86_intercept_rdtscp &&
13613 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
13614 ctxt->exception.vector = UD_VECTOR;
13615 ctxt->exception.error_code_valid = false;
13616 return X86EMUL_PROPAGATE_FAULT;
13619 /* TODO: check more intercepts... */
13620 return X86EMUL_CONTINUE;
13623 #ifdef CONFIG_X86_64
13624 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
13625 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
13626 u64 divisor, u64 *result)
13628 u64 low = a << shift, high = a >> (64 - shift);
13630 /* To avoid the overflow on divq */
13631 if (high >= divisor)
13634 /* Low hold the result, high hold rem which is discarded */
13635 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
13636 "rm" (divisor), "0" (low), "1" (high));
13642 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
13644 struct vcpu_vmx *vmx;
13645 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
13647 if (kvm_mwait_in_guest(vcpu->kvm))
13648 return -EOPNOTSUPP;
13650 vmx = to_vmx(vcpu);
13652 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
13653 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
13654 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns);
13656 if (delta_tsc > lapic_timer_advance_cycles)
13657 delta_tsc -= lapic_timer_advance_cycles;
13661 /* Convert to host delta tsc if tsc scaling is enabled */
13662 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
13663 u64_shl_div_u64(delta_tsc,
13664 kvm_tsc_scaling_ratio_frac_bits,
13665 vcpu->arch.tsc_scaling_ratio,
13670 * If the delta tsc can't fit in the 32 bit after the multi shift,
13671 * we can't use the preemption timer.
13672 * It's possible that it fits on later vmentries, but checking
13673 * on every vmentry is costly so we just use an hrtimer.
13675 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
13678 vmx->hv_deadline_tsc = tscl + delta_tsc;
13679 return delta_tsc == 0;
13682 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
13684 to_vmx(vcpu)->hv_deadline_tsc = -1;
13688 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
13690 if (!kvm_pause_in_guest(vcpu->kvm))
13691 shrink_ple_window(vcpu);
13694 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
13695 struct kvm_memory_slot *slot)
13697 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
13698 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
13701 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
13702 struct kvm_memory_slot *slot)
13704 kvm_mmu_slot_set_dirty(kvm, slot);
13707 static void vmx_flush_log_dirty(struct kvm *kvm)
13709 kvm_flush_pml_buffers(kvm);
13712 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
13714 struct vmcs12 *vmcs12;
13715 struct vcpu_vmx *vmx = to_vmx(vcpu);
13717 struct page *page = NULL;
13720 if (is_guest_mode(vcpu)) {
13721 WARN_ON_ONCE(vmx->nested.pml_full);
13724 * Check if PML is enabled for the nested guest.
13725 * Whether eptp bit 6 is set is already checked
13726 * as part of A/D emulation.
13728 vmcs12 = get_vmcs12(vcpu);
13729 if (!nested_cpu_has_pml(vmcs12))
13732 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
13733 vmx->nested.pml_full = true;
13737 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
13739 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
13740 if (is_error_page(page))
13743 pml_address = kmap(page);
13744 pml_address[vmcs12->guest_pml_index--] = gpa;
13746 kvm_release_page_clean(page);
13752 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
13753 struct kvm_memory_slot *memslot,
13754 gfn_t offset, unsigned long mask)
13756 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
13759 static void __pi_post_block(struct kvm_vcpu *vcpu)
13761 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
13762 struct pi_desc old, new;
13766 old.control = new.control = pi_desc->control;
13767 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
13768 "Wakeup handler not enabled while the VCPU is blocked\n");
13770 dest = cpu_physical_id(vcpu->cpu);
13772 if (x2apic_enabled())
13775 new.ndst = (dest << 8) & 0xFF00;
13777 /* set 'NV' to 'notification vector' */
13778 new.nv = POSTED_INTR_VECTOR;
13779 } while (cmpxchg64(&pi_desc->control, old.control,
13780 new.control) != old.control);
13782 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
13783 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13784 list_del(&vcpu->blocked_vcpu_list);
13785 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13786 vcpu->pre_pcpu = -1;
13791 * This routine does the following things for vCPU which is going
13792 * to be blocked if VT-d PI is enabled.
13793 * - Store the vCPU to the wakeup list, so when interrupts happen
13794 * we can find the right vCPU to wake up.
13795 * - Change the Posted-interrupt descriptor as below:
13796 * 'NDST' <-- vcpu->pre_pcpu
13797 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
13798 * - If 'ON' is set during this process, which means at least one
13799 * interrupt is posted for this vCPU, we cannot block it, in
13800 * this case, return 1, otherwise, return 0.
13803 static int pi_pre_block(struct kvm_vcpu *vcpu)
13806 struct pi_desc old, new;
13807 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
13809 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
13810 !irq_remapping_cap(IRQ_POSTING_CAP) ||
13811 !kvm_vcpu_apicv_active(vcpu))
13814 WARN_ON(irqs_disabled());
13815 local_irq_disable();
13816 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
13817 vcpu->pre_pcpu = vcpu->cpu;
13818 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13819 list_add_tail(&vcpu->blocked_vcpu_list,
13820 &per_cpu(blocked_vcpu_on_cpu,
13822 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13826 old.control = new.control = pi_desc->control;
13828 WARN((pi_desc->sn == 1),
13829 "Warning: SN field of posted-interrupts "
13830 "is set before blocking\n");
13833 * Since vCPU can be preempted during this process,
13834 * vcpu->cpu could be different with pre_pcpu, we
13835 * need to set pre_pcpu as the destination of wakeup
13836 * notification event, then we can find the right vCPU
13837 * to wakeup in wakeup handler if interrupts happen
13838 * when the vCPU is in blocked state.
13840 dest = cpu_physical_id(vcpu->pre_pcpu);
13842 if (x2apic_enabled())
13845 new.ndst = (dest << 8) & 0xFF00;
13847 /* set 'NV' to 'wakeup vector' */
13848 new.nv = POSTED_INTR_WAKEUP_VECTOR;
13849 } while (cmpxchg64(&pi_desc->control, old.control,
13850 new.control) != old.control);
13852 /* We should not block the vCPU if an interrupt is posted for it. */
13853 if (pi_test_on(pi_desc) == 1)
13854 __pi_post_block(vcpu);
13856 local_irq_enable();
13857 return (vcpu->pre_pcpu == -1);
13860 static int vmx_pre_block(struct kvm_vcpu *vcpu)
13862 if (pi_pre_block(vcpu))
13865 if (kvm_lapic_hv_timer_in_use(vcpu))
13866 kvm_lapic_switch_to_sw_timer(vcpu);
13871 static void pi_post_block(struct kvm_vcpu *vcpu)
13873 if (vcpu->pre_pcpu == -1)
13876 WARN_ON(irqs_disabled());
13877 local_irq_disable();
13878 __pi_post_block(vcpu);
13879 local_irq_enable();
13882 static void vmx_post_block(struct kvm_vcpu *vcpu)
13884 if (kvm_x86_ops->set_hv_timer)
13885 kvm_lapic_switch_to_hv_timer(vcpu);
13887 pi_post_block(vcpu);
13891 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
13894 * @host_irq: host irq of the interrupt
13895 * @guest_irq: gsi of the interrupt
13896 * @set: set or unset PI
13897 * returns 0 on success, < 0 on failure
13899 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
13900 uint32_t guest_irq, bool set)
13902 struct kvm_kernel_irq_routing_entry *e;
13903 struct kvm_irq_routing_table *irq_rt;
13904 struct kvm_lapic_irq irq;
13905 struct kvm_vcpu *vcpu;
13906 struct vcpu_data vcpu_info;
13909 if (!kvm_arch_has_assigned_device(kvm) ||
13910 !irq_remapping_cap(IRQ_POSTING_CAP) ||
13911 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
13914 idx = srcu_read_lock(&kvm->irq_srcu);
13915 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
13916 if (guest_irq >= irq_rt->nr_rt_entries ||
13917 hlist_empty(&irq_rt->map[guest_irq])) {
13918 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
13919 guest_irq, irq_rt->nr_rt_entries);
13923 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
13924 if (e->type != KVM_IRQ_ROUTING_MSI)
13927 * VT-d PI cannot support posting multicast/broadcast
13928 * interrupts to a vCPU, we still use interrupt remapping
13929 * for these kind of interrupts.
13931 * For lowest-priority interrupts, we only support
13932 * those with single CPU as the destination, e.g. user
13933 * configures the interrupts via /proc/irq or uses
13934 * irqbalance to make the interrupts single-CPU.
13936 * We will support full lowest-priority interrupt later.
13939 kvm_set_msi_irq(kvm, e, &irq);
13940 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
13942 * Make sure the IRTE is in remapped mode if
13943 * we don't handle it in posted mode.
13945 ret = irq_set_vcpu_affinity(host_irq, NULL);
13948 "failed to back to remapped mode, irq: %u\n",
13956 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
13957 vcpu_info.vector = irq.vector;
13959 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
13960 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
13963 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
13965 ret = irq_set_vcpu_affinity(host_irq, NULL);
13968 printk(KERN_INFO "%s: failed to update PI IRTE\n",
13976 srcu_read_unlock(&kvm->irq_srcu, idx);
13980 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
13982 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
13983 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
13984 FEATURE_CONTROL_LMCE;
13986 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
13987 ~FEATURE_CONTROL_LMCE;
13990 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
13992 /* we need a nested vmexit to enter SMM, postpone if run is pending */
13993 if (to_vmx(vcpu)->nested.nested_run_pending)
13998 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
14000 struct vcpu_vmx *vmx = to_vmx(vcpu);
14002 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
14003 if (vmx->nested.smm.guest_mode)
14004 nested_vmx_vmexit(vcpu, -1, 0, 0);
14006 vmx->nested.smm.vmxon = vmx->nested.vmxon;
14007 vmx->nested.vmxon = false;
14008 vmx_clear_hlt(vcpu);
14012 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
14014 struct vcpu_vmx *vmx = to_vmx(vcpu);
14017 if (vmx->nested.smm.vmxon) {
14018 vmx->nested.vmxon = true;
14019 vmx->nested.smm.vmxon = false;
14022 if (vmx->nested.smm.guest_mode) {
14023 vcpu->arch.hflags &= ~HF_SMM_MASK;
14024 ret = nested_vmx_enter_non_root_mode(vcpu, false);
14025 vcpu->arch.hflags |= HF_SMM_MASK;
14029 vmx->nested.smm.guest_mode = false;
14034 static int enable_smi_window(struct kvm_vcpu *vcpu)
14039 static int vmx_get_nested_state(struct kvm_vcpu *vcpu,
14040 struct kvm_nested_state __user *user_kvm_nested_state,
14041 u32 user_data_size)
14043 struct vcpu_vmx *vmx;
14044 struct vmcs12 *vmcs12;
14045 struct kvm_nested_state kvm_state = {
14048 .size = sizeof(kvm_state),
14049 .vmx.vmxon_pa = -1ull,
14050 .vmx.vmcs_pa = -1ull,
14054 return kvm_state.size + 2 * VMCS12_SIZE;
14056 vmx = to_vmx(vcpu);
14057 vmcs12 = get_vmcs12(vcpu);
14058 if (nested_vmx_allowed(vcpu) &&
14059 (vmx->nested.vmxon || vmx->nested.smm.vmxon)) {
14060 kvm_state.vmx.vmxon_pa = vmx->nested.vmxon_ptr;
14061 kvm_state.vmx.vmcs_pa = vmx->nested.current_vmptr;
14063 if (vmx->nested.current_vmptr != -1ull) {
14064 kvm_state.size += VMCS12_SIZE;
14066 if (is_guest_mode(vcpu) &&
14067 nested_cpu_has_shadow_vmcs(vmcs12) &&
14068 vmcs12->vmcs_link_pointer != -1ull)
14069 kvm_state.size += VMCS12_SIZE;
14072 if (vmx->nested.smm.vmxon)
14073 kvm_state.vmx.smm.flags |= KVM_STATE_NESTED_SMM_VMXON;
14075 if (vmx->nested.smm.guest_mode)
14076 kvm_state.vmx.smm.flags |= KVM_STATE_NESTED_SMM_GUEST_MODE;
14078 if (is_guest_mode(vcpu)) {
14079 kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE;
14081 if (vmx->nested.nested_run_pending)
14082 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING;
14086 if (user_data_size < kvm_state.size)
14089 if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state)))
14092 if (vmx->nested.current_vmptr == -1ull)
14096 * When running L2, the authoritative vmcs12 state is in the
14097 * vmcs02. When running L1, the authoritative vmcs12 state is
14098 * in the shadow vmcs linked to vmcs01, unless
14099 * sync_shadow_vmcs is set, in which case, the authoritative
14100 * vmcs12 state is in the vmcs12 already.
14102 if (is_guest_mode(vcpu))
14103 sync_vmcs12(vcpu, vmcs12);
14104 else if (enable_shadow_vmcs && !vmx->nested.sync_shadow_vmcs)
14105 copy_shadow_to_vmcs12(vmx);
14107 if (copy_to_user(user_kvm_nested_state->data, vmcs12, sizeof(*vmcs12)))
14110 if (nested_cpu_has_shadow_vmcs(vmcs12) &&
14111 vmcs12->vmcs_link_pointer != -1ull) {
14112 if (copy_to_user(user_kvm_nested_state->data + VMCS12_SIZE,
14113 get_shadow_vmcs12(vcpu), sizeof(*vmcs12)))
14118 return kvm_state.size;
14121 static int vmx_set_nested_state(struct kvm_vcpu *vcpu,
14122 struct kvm_nested_state __user *user_kvm_nested_state,
14123 struct kvm_nested_state *kvm_state)
14125 struct vcpu_vmx *vmx = to_vmx(vcpu);
14126 struct vmcs12 *vmcs12;
14130 if (kvm_state->format != 0)
14133 if (!nested_vmx_allowed(vcpu))
14134 return kvm_state->vmx.vmxon_pa == -1ull ? 0 : -EINVAL;
14136 if (kvm_state->vmx.vmxon_pa == -1ull) {
14137 if (kvm_state->vmx.smm.flags)
14140 if (kvm_state->vmx.vmcs_pa != -1ull)
14143 vmx_leave_nested(vcpu);
14147 if (!page_address_valid(vcpu, kvm_state->vmx.vmxon_pa))
14150 if (kvm_state->size < sizeof(kvm_state) + sizeof(*vmcs12))
14153 if (kvm_state->vmx.vmcs_pa == kvm_state->vmx.vmxon_pa ||
14154 !page_address_valid(vcpu, kvm_state->vmx.vmcs_pa))
14157 if ((kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
14158 (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
14161 if (kvm_state->vmx.smm.flags &
14162 ~(KVM_STATE_NESTED_SMM_GUEST_MODE | KVM_STATE_NESTED_SMM_VMXON))
14166 * SMM temporarily disables VMX, so we cannot be in guest mode,
14167 * nor can VMLAUNCH/VMRESUME be pending. Outside SMM, SMM flags
14170 if (is_smm(vcpu) ? kvm_state->flags : kvm_state->vmx.smm.flags)
14173 if ((kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
14174 !(kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON))
14177 vmx_leave_nested(vcpu);
14178 if (kvm_state->vmx.vmxon_pa == -1ull)
14181 vmx->nested.vmxon_ptr = kvm_state->vmx.vmxon_pa;
14182 ret = enter_vmx_operation(vcpu);
14186 set_current_vmptr(vmx, kvm_state->vmx.vmcs_pa);
14188 if (kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON) {
14189 vmx->nested.smm.vmxon = true;
14190 vmx->nested.vmxon = false;
14192 if (kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE)
14193 vmx->nested.smm.guest_mode = true;
14196 vmcs12 = get_vmcs12(vcpu);
14197 if (copy_from_user(vmcs12, user_kvm_nested_state->data, sizeof(*vmcs12)))
14200 if (vmcs12->hdr.revision_id != VMCS12_REVISION)
14203 if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
14206 vmx->nested.nested_run_pending =
14207 !!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);
14209 if (nested_cpu_has_shadow_vmcs(vmcs12) &&
14210 vmcs12->vmcs_link_pointer != -1ull) {
14211 struct vmcs12 *shadow_vmcs12 = get_shadow_vmcs12(vcpu);
14212 if (kvm_state->size < sizeof(kvm_state) + 2 * sizeof(*vmcs12))
14215 if (copy_from_user(shadow_vmcs12,
14216 user_kvm_nested_state->data + VMCS12_SIZE,
14220 if (shadow_vmcs12->hdr.revision_id != VMCS12_REVISION ||
14221 !shadow_vmcs12->hdr.shadow_vmcs)
14225 if (check_vmentry_prereqs(vcpu, vmcs12) ||
14226 check_vmentry_postreqs(vcpu, vmcs12, &exit_qual))
14229 vmx->nested.dirty_vmcs12 = true;
14230 ret = nested_vmx_enter_non_root_mode(vcpu, false);
14237 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
14238 .cpu_has_kvm_support = cpu_has_kvm_support,
14239 .disabled_by_bios = vmx_disabled_by_bios,
14240 .hardware_setup = hardware_setup,
14241 .hardware_unsetup = hardware_unsetup,
14242 .check_processor_compatibility = vmx_check_processor_compat,
14243 .hardware_enable = hardware_enable,
14244 .hardware_disable = hardware_disable,
14245 .cpu_has_accelerated_tpr = report_flexpriority,
14246 .has_emulated_msr = vmx_has_emulated_msr,
14248 .vm_init = vmx_vm_init,
14249 .vm_alloc = vmx_vm_alloc,
14250 .vm_free = vmx_vm_free,
14252 .vcpu_create = vmx_create_vcpu,
14253 .vcpu_free = vmx_free_vcpu,
14254 .vcpu_reset = vmx_vcpu_reset,
14256 .prepare_guest_switch = vmx_prepare_switch_to_guest,
14257 .vcpu_load = vmx_vcpu_load,
14258 .vcpu_put = vmx_vcpu_put,
14260 .update_bp_intercept = update_exception_bitmap,
14261 .get_msr_feature = vmx_get_msr_feature,
14262 .get_msr = vmx_get_msr,
14263 .set_msr = vmx_set_msr,
14264 .get_segment_base = vmx_get_segment_base,
14265 .get_segment = vmx_get_segment,
14266 .set_segment = vmx_set_segment,
14267 .get_cpl = vmx_get_cpl,
14268 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
14269 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
14270 .decache_cr3 = vmx_decache_cr3,
14271 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
14272 .set_cr0 = vmx_set_cr0,
14273 .set_cr3 = vmx_set_cr3,
14274 .set_cr4 = vmx_set_cr4,
14275 .set_efer = vmx_set_efer,
14276 .get_idt = vmx_get_idt,
14277 .set_idt = vmx_set_idt,
14278 .get_gdt = vmx_get_gdt,
14279 .set_gdt = vmx_set_gdt,
14280 .get_dr6 = vmx_get_dr6,
14281 .set_dr6 = vmx_set_dr6,
14282 .set_dr7 = vmx_set_dr7,
14283 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
14284 .cache_reg = vmx_cache_reg,
14285 .get_rflags = vmx_get_rflags,
14286 .set_rflags = vmx_set_rflags,
14288 .tlb_flush = vmx_flush_tlb,
14289 .tlb_flush_gva = vmx_flush_tlb_gva,
14291 .run = vmx_vcpu_run,
14292 .handle_exit = vmx_handle_exit,
14293 .skip_emulated_instruction = skip_emulated_instruction,
14294 .set_interrupt_shadow = vmx_set_interrupt_shadow,
14295 .get_interrupt_shadow = vmx_get_interrupt_shadow,
14296 .patch_hypercall = vmx_patch_hypercall,
14297 .set_irq = vmx_inject_irq,
14298 .set_nmi = vmx_inject_nmi,
14299 .queue_exception = vmx_queue_exception,
14300 .cancel_injection = vmx_cancel_injection,
14301 .interrupt_allowed = vmx_interrupt_allowed,
14302 .nmi_allowed = vmx_nmi_allowed,
14303 .get_nmi_mask = vmx_get_nmi_mask,
14304 .set_nmi_mask = vmx_set_nmi_mask,
14305 .enable_nmi_window = enable_nmi_window,
14306 .enable_irq_window = enable_irq_window,
14307 .update_cr8_intercept = update_cr8_intercept,
14308 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
14309 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
14310 .get_enable_apicv = vmx_get_enable_apicv,
14311 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
14312 .load_eoi_exitmap = vmx_load_eoi_exitmap,
14313 .apicv_post_state_restore = vmx_apicv_post_state_restore,
14314 .hwapic_irr_update = vmx_hwapic_irr_update,
14315 .hwapic_isr_update = vmx_hwapic_isr_update,
14316 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
14317 .sync_pir_to_irr = vmx_sync_pir_to_irr,
14318 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
14320 .set_tss_addr = vmx_set_tss_addr,
14321 .set_identity_map_addr = vmx_set_identity_map_addr,
14322 .get_tdp_level = get_ept_level,
14323 .get_mt_mask = vmx_get_mt_mask,
14325 .get_exit_info = vmx_get_exit_info,
14327 .get_lpage_level = vmx_get_lpage_level,
14329 .cpuid_update = vmx_cpuid_update,
14331 .rdtscp_supported = vmx_rdtscp_supported,
14332 .invpcid_supported = vmx_invpcid_supported,
14334 .set_supported_cpuid = vmx_set_supported_cpuid,
14336 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
14338 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
14339 .write_tsc_offset = vmx_write_tsc_offset,
14341 .set_tdp_cr3 = vmx_set_cr3,
14343 .check_intercept = vmx_check_intercept,
14344 .handle_external_intr = vmx_handle_external_intr,
14345 .mpx_supported = vmx_mpx_supported,
14346 .xsaves_supported = vmx_xsaves_supported,
14347 .umip_emulated = vmx_umip_emulated,
14349 .check_nested_events = vmx_check_nested_events,
14350 .request_immediate_exit = vmx_request_immediate_exit,
14352 .sched_in = vmx_sched_in,
14354 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
14355 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
14356 .flush_log_dirty = vmx_flush_log_dirty,
14357 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
14358 .write_log_dirty = vmx_write_pml_buffer,
14360 .pre_block = vmx_pre_block,
14361 .post_block = vmx_post_block,
14363 .pmu_ops = &intel_pmu_ops,
14365 .update_pi_irte = vmx_update_pi_irte,
14367 #ifdef CONFIG_X86_64
14368 .set_hv_timer = vmx_set_hv_timer,
14369 .cancel_hv_timer = vmx_cancel_hv_timer,
14372 .setup_mce = vmx_setup_mce,
14374 .get_nested_state = vmx_get_nested_state,
14375 .set_nested_state = vmx_set_nested_state,
14376 .get_vmcs12_pages = nested_get_vmcs12_pages,
14378 .smi_allowed = vmx_smi_allowed,
14379 .pre_enter_smm = vmx_pre_enter_smm,
14380 .pre_leave_smm = vmx_pre_leave_smm,
14381 .enable_smi_window = enable_smi_window,
14384 static void vmx_cleanup_l1d_flush(void)
14386 if (vmx_l1d_flush_pages) {
14387 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
14388 vmx_l1d_flush_pages = NULL;
14390 /* Restore state so sysfs ignores VMX */
14391 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
14394 static void vmx_exit(void)
14396 #ifdef CONFIG_KEXEC_CORE
14397 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
14403 #if IS_ENABLED(CONFIG_HYPERV)
14404 if (static_branch_unlikely(&enable_evmcs)) {
14406 struct hv_vp_assist_page *vp_ap;
14408 * Reset everything to support using non-enlightened VMCS
14409 * access later (e.g. when we reload the module with
14410 * enlightened_vmcs=0)
14412 for_each_online_cpu(cpu) {
14413 vp_ap = hv_get_vp_assist_page(cpu);
14418 vp_ap->current_nested_vmcs = 0;
14419 vp_ap->enlighten_vmentry = 0;
14422 static_branch_disable(&enable_evmcs);
14425 vmx_cleanup_l1d_flush();
14427 module_exit(vmx_exit);
14429 static int __init vmx_init(void)
14433 #if IS_ENABLED(CONFIG_HYPERV)
14435 * Enlightened VMCS usage should be recommended and the host needs
14436 * to support eVMCS v1 or above. We can also disable eVMCS support
14437 * with module parameter.
14439 if (enlightened_vmcs &&
14440 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
14441 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
14442 KVM_EVMCS_VERSION) {
14445 /* Check that we have assist pages on all online CPUs */
14446 for_each_online_cpu(cpu) {
14447 if (!hv_get_vp_assist_page(cpu)) {
14448 enlightened_vmcs = false;
14453 if (enlightened_vmcs) {
14454 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
14455 static_branch_enable(&enable_evmcs);
14458 enlightened_vmcs = false;
14462 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
14463 __alignof__(struct vcpu_vmx), THIS_MODULE);
14468 * Must be called after kvm_init() so enable_ept is properly set
14469 * up. Hand the parameter mitigation value in which was stored in
14470 * the pre module init parser. If no parameter was given, it will
14471 * contain 'auto' which will be turned into the default 'cond'
14474 if (boot_cpu_has(X86_BUG_L1TF)) {
14475 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
14482 #ifdef CONFIG_KEXEC_CORE
14483 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
14484 crash_vmclear_local_loaded_vmcss);
14486 vmx_check_vmcs12_offsets();
14490 module_init(vmx_init);