arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include "kvm_cache_regs.h"
  38 #include "x86.h"
  39
  40 #include <asm/cpu.h>
  41 #include <asm/io.h>
  42 #include <asm/desc.h>
  43 #include <asm/vmx.h>
  44 #include <asm/virtext.h>
  45 #include <asm/mce.h>
  46 #include <asm/fpu/internal.h>
  47 #include <asm/perf_event.h>
  48 #include <asm/debugreg.h>
  49 #include <asm/kexec.h>
  50 #include <asm/apic.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/mmu_context.h>
  53
  54 #include "trace.h"
  55 #include "pmu.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58 #define __ex_clear(x, reg) \
  59         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  60
  61 MODULE_AUTHOR("Qumranet");
  62 MODULE_LICENSE("GPL");
  63
  64 static const struct x86_cpu_id vmx_cpu_id[] = {
  65         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  66         {}
  67 };
  68 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  69
  70 static bool __read_mostly enable_vpid = 1;
  71 module_param_named(vpid, enable_vpid, bool, 0444);
  72
  73 static bool __read_mostly flexpriority_enabled = 1;
  74 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_ept = 1;
  77 module_param_named(ept, enable_ept, bool, S_IRUGO);
  78
  79 static bool __read_mostly enable_unrestricted_guest = 1;
  80 module_param_named(unrestricted_guest,
  81                         enable_unrestricted_guest, bool, S_IRUGO);
  82
  83 static bool __read_mostly enable_ept_ad_bits = 1;
  84 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  85
  86 static bool __read_mostly emulate_invalid_guest_state = true;
  87 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 113 static int __read_mostly cpu_preemption_timer_multi;
 114 static bool __read_mostly enable_preemption_timer = 1;
 115 #ifdef CONFIG_X86_64
 116 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 117 #endif
 118
 119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 121 #define KVM_VM_CR0_ALWAYS_ON                                            \
 122         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 123 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 124         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 125          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 126
 127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 129
 130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 131
 132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 133
 134 /*
 135  * Hyper-V requires all of these, so mark them as supported even though
 136  * they are just treated the same as all-context.
 137  */
 138 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 139         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 140         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 141         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 143
 144 /*
 145  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 146  * ple_gap:    upper bound on the amount of time between two successive
 147  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 148  *             According to test, this time is usually smaller than 128 cycles.
 149  * ple_window: upper bound on the amount of time a guest is allowed to execute
 150  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 151  *             less than 2^12 cycles
 152  * Time is measured based on a counter that runs at the same rate as the TSC,
 153  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 154  */
 155 #define KVM_VMX_DEFAULT_PLE_GAP           128
 156 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 160                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 161
 162 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 163 module_param(ple_gap, int, S_IRUGO);
 164
 165 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 166 module_param(ple_window, int, S_IRUGO);
 167
 168 /* Default doubles per-vcpu window every exit. */
 169 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 170 module_param(ple_window_grow, int, S_IRUGO);
 171
 172 /* Default resets per-vcpu window every exit to ple_window. */
 173 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 174 module_param(ple_window_shrink, int, S_IRUGO);
 175
 176 /* Default is to compute the maximum so we can never overflow. */
 177 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 178 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, int, S_IRUGO);
 180
 181 extern const ulong vmx_return;
 182
 183 #define NR_AUTOLOAD_MSRS 8
 184 #define VMCS02_POOL_SIZE 1
 185
 186 struct vmcs {
 187         u32 revision_id;
 188         u32 abort;
 189         char data[0];
 190 };
 191
 192 /*
 193  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 194  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 195  * loaded on this CPU (so we can clear them if the CPU goes down).
 196  */
 197 struct loaded_vmcs {
 198         struct vmcs *vmcs;
 199         struct vmcs *shadow_vmcs;
 200         int cpu;
 201         bool launched;
 202         bool nmi_known_unmasked;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 ept_pointer;
 247         u64 eoi_exit_bitmap0;
 248         u64 eoi_exit_bitmap1;
 249         u64 eoi_exit_bitmap2;
 250         u64 eoi_exit_bitmap3;
 251         u64 xss_exit_bitmap;
 252         u64 guest_physical_address;
 253         u64 vmcs_link_pointer;
 254         u64 pml_address;
 255         u64 guest_ia32_debugctl;
 256         u64 guest_ia32_pat;
 257         u64 guest_ia32_efer;
 258         u64 guest_ia32_perf_global_ctrl;
 259         u64 guest_pdptr0;
 260         u64 guest_pdptr1;
 261         u64 guest_pdptr2;
 262         u64 guest_pdptr3;
 263         u64 guest_bndcfgs;
 264         u64 host_ia32_pat;
 265         u64 host_ia32_efer;
 266         u64 host_ia32_perf_global_ctrl;
 267         u64 padding64[8]; /* room for future expansion */
 268         /*
 269          * To allow migration of L1 (complete with its L2 guests) between
 270          * machines of different natural widths (32 or 64 bit), we cannot have
 271          * unsigned long fields with no explict size. We use u64 (aliased
 272          * natural_width) instead. Luckily, x86 is little-endian.
 273          */
 274         natural_width cr0_guest_host_mask;
 275         natural_width cr4_guest_host_mask;
 276         natural_width cr0_read_shadow;
 277         natural_width cr4_read_shadow;
 278         natural_width cr3_target_value0;
 279         natural_width cr3_target_value1;
 280         natural_width cr3_target_value2;
 281         natural_width cr3_target_value3;
 282         natural_width exit_qualification;
 283         natural_width guest_linear_address;
 284         natural_width guest_cr0;
 285         natural_width guest_cr3;
 286         natural_width guest_cr4;
 287         natural_width guest_es_base;
 288         natural_width guest_cs_base;
 289         natural_width guest_ss_base;
 290         natural_width guest_ds_base;
 291         natural_width guest_fs_base;
 292         natural_width guest_gs_base;
 293         natural_width guest_ldtr_base;
 294         natural_width guest_tr_base;
 295         natural_width guest_gdtr_base;
 296         natural_width guest_idtr_base;
 297         natural_width guest_dr7;
 298         natural_width guest_rsp;
 299         natural_width guest_rip;
 300         natural_width guest_rflags;
 301         natural_width guest_pending_dbg_exceptions;
 302         natural_width guest_sysenter_esp;
 303         natural_width guest_sysenter_eip;
 304         natural_width host_cr0;
 305         natural_width host_cr3;
 306         natural_width host_cr4;
 307         natural_width host_fs_base;
 308         natural_width host_gs_base;
 309         natural_width host_tr_base;
 310         natural_width host_gdtr_base;
 311         natural_width host_idtr_base;
 312         natural_width host_ia32_sysenter_esp;
 313         natural_width host_ia32_sysenter_eip;
 314         natural_width host_rsp;
 315         natural_width host_rip;
 316         natural_width paddingl[8]; /* room for future expansion */
 317         u32 pin_based_vm_exec_control;
 318         u32 cpu_based_vm_exec_control;
 319         u32 exception_bitmap;
 320         u32 page_fault_error_code_mask;
 321         u32 page_fault_error_code_match;
 322         u32 cr3_target_count;
 323         u32 vm_exit_controls;
 324         u32 vm_exit_msr_store_count;
 325         u32 vm_exit_msr_load_count;
 326         u32 vm_entry_controls;
 327         u32 vm_entry_msr_load_count;
 328         u32 vm_entry_intr_info_field;
 329         u32 vm_entry_exception_error_code;
 330         u32 vm_entry_instruction_len;
 331         u32 tpr_threshold;
 332         u32 secondary_vm_exec_control;
 333         u32 vm_instruction_error;
 334         u32 vm_exit_reason;
 335         u32 vm_exit_intr_info;
 336         u32 vm_exit_intr_error_code;
 337         u32 idt_vectoring_info_field;
 338         u32 idt_vectoring_error_code;
 339         u32 vm_exit_instruction_len;
 340         u32 vmx_instruction_info;
 341         u32 guest_es_limit;
 342         u32 guest_cs_limit;
 343         u32 guest_ss_limit;
 344         u32 guest_ds_limit;
 345         u32 guest_fs_limit;
 346         u32 guest_gs_limit;
 347         u32 guest_ldtr_limit;
 348         u32 guest_tr_limit;
 349         u32 guest_gdtr_limit;
 350         u32 guest_idtr_limit;
 351         u32 guest_es_ar_bytes;
 352         u32 guest_cs_ar_bytes;
 353         u32 guest_ss_ar_bytes;
 354         u32 guest_ds_ar_bytes;
 355         u32 guest_fs_ar_bytes;
 356         u32 guest_gs_ar_bytes;
 357         u32 guest_ldtr_ar_bytes;
 358         u32 guest_tr_ar_bytes;
 359         u32 guest_interruptibility_info;
 360         u32 guest_activity_state;
 361         u32 guest_sysenter_cs;
 362         u32 host_ia32_sysenter_cs;
 363         u32 vmx_preemption_timer_value;
 364         u32 padding32[7]; /* room for future expansion */
 365         u16 virtual_processor_id;
 366         u16 posted_intr_nv;
 367         u16 guest_es_selector;
 368         u16 guest_cs_selector;
 369         u16 guest_ss_selector;
 370         u16 guest_ds_selector;
 371         u16 guest_fs_selector;
 372         u16 guest_gs_selector;
 373         u16 guest_ldtr_selector;
 374         u16 guest_tr_selector;
 375         u16 guest_intr_status;
 376         u16 guest_pml_index;
 377         u16 host_es_selector;
 378         u16 host_cs_selector;
 379         u16 host_ss_selector;
 380         u16 host_ds_selector;
 381         u16 host_fs_selector;
 382         u16 host_gs_selector;
 383         u16 host_tr_selector;
 384 };
 385
 386 /*
 387  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 388  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 389  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 390  */
 391 #define VMCS12_REVISION 0x11e57ed0
 392
 393 /*
 394  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 395  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 396  * current implementation, 4K are reserved to avoid future complications.
 397  */
 398 #define VMCS12_SIZE 0x1000
 399
 400 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 401 struct vmcs02_list {
 402         struct list_head list;
 403         gpa_t vmptr;
 404         struct loaded_vmcs vmcs02;
 405 };
 406
 407 /*
 408  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 409  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 410  */
 411 struct nested_vmx {
 412         /* Has the level1 guest done vmxon? */
 413         bool vmxon;
 414         gpa_t vmxon_ptr;
 415         bool pml_full;
 416
 417         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 418         gpa_t current_vmptr;
 419         /* The host-usable pointer to the above */
 420         struct page *current_vmcs12_page;
 421         struct vmcs12 *current_vmcs12;
 422         /*
 423          * Cache of the guest's VMCS, existing outside of guest memory.
 424          * Loaded from guest memory during VMPTRLD. Flushed to guest
 425          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 426          */
 427         struct vmcs12 *cached_vmcs12;
 428         /*
 429          * Indicates if the shadow vmcs must be updated with the
 430          * data hold by vmcs12
 431          */
 432         bool sync_shadow_vmcs;
 433
 434         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 435         struct list_head vmcs02_pool;
 436         int vmcs02_num;
 437         bool change_vmcs01_virtual_x2apic_mode;
 438         /* L2 must run next, and mustn't decide to exit to L1. */
 439         bool nested_run_pending;
 440         /*
 441          * Guest pages referred to in vmcs02 with host-physical pointers, so
 442          * we must keep them pinned while L2 runs.
 443          */
 444         struct page *apic_access_page;
 445         struct page *virtual_apic_page;
 446         struct page *pi_desc_page;
 447         struct pi_desc *pi_desc;
 448         bool pi_pending;
 449         u16 posted_intr_nv;
 450
 451         unsigned long *msr_bitmap;
 452
 453         struct hrtimer preemption_timer;
 454         bool preemption_timer_expired;
 455
 456         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 457         u64 vmcs01_debugctl;
 458
 459         u16 vpid02;
 460         u16 last_vpid;
 461
 462         /*
 463          * We only store the "true" versions of the VMX capability MSRs. We
 464          * generate the "non-true" versions by setting the must-be-1 bits
 465          * according to the SDM.
 466          */
 467         u32 nested_vmx_procbased_ctls_low;
 468         u32 nested_vmx_procbased_ctls_high;
 469         u32 nested_vmx_secondary_ctls_low;
 470         u32 nested_vmx_secondary_ctls_high;
 471         u32 nested_vmx_pinbased_ctls_low;
 472         u32 nested_vmx_pinbased_ctls_high;
 473         u32 nested_vmx_exit_ctls_low;
 474         u32 nested_vmx_exit_ctls_high;
 475         u32 nested_vmx_entry_ctls_low;
 476         u32 nested_vmx_entry_ctls_high;
 477         u32 nested_vmx_misc_low;
 478         u32 nested_vmx_misc_high;
 479         u32 nested_vmx_ept_caps;
 480         u32 nested_vmx_vpid_caps;
 481         u64 nested_vmx_basic;
 482         u64 nested_vmx_cr0_fixed0;
 483         u64 nested_vmx_cr0_fixed1;
 484         u64 nested_vmx_cr4_fixed0;
 485         u64 nested_vmx_cr4_fixed1;
 486         u64 nested_vmx_vmcs_enum;
 487 };
 488
 489 #define POSTED_INTR_ON  0
 490 #define POSTED_INTR_SN  1
 491
 492 /* Posted-Interrupt Descriptor */
 493 struct pi_desc {
 494         u32 pir[8];     /* Posted interrupt requested */
 495         union {
 496                 struct {
 497                                 /* bit 256 - Outstanding Notification */
 498                         u16     on      : 1,
 499                                 /* bit 257 - Suppress Notification */
 500                                 sn      : 1,
 501                                 /* bit 271:258 - Reserved */
 502                                 rsvd_1  : 14;
 503                                 /* bit 279:272 - Notification Vector */
 504                         u8      nv;
 505                                 /* bit 287:280 - Reserved */
 506                         u8      rsvd_2;
 507                                 /* bit 319:288 - Notification Destination */
 508                         u32     ndst;
 509                 };
 510                 u64 control;
 511         };
 512         u32 rsvd[6];
 513 } __aligned(64);
 514
 515 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 516 {
 517         return test_and_set_bit(POSTED_INTR_ON,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 522 {
 523         return test_and_clear_bit(POSTED_INTR_ON,
 524                         (unsigned long *)&pi_desc->control);
 525 }
 526
 527 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 528 {
 529         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 530 }
 531
 532 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 533 {
 534         return clear_bit(POSTED_INTR_SN,
 535                         (unsigned long *)&pi_desc->control);
 536 }
 537
 538 static inline void pi_set_sn(struct pi_desc *pi_desc)
 539 {
 540         return set_bit(POSTED_INTR_SN,
 541                         (unsigned long *)&pi_desc->control);
 542 }
 543
 544 static inline void pi_clear_on(struct pi_desc *pi_desc)
 545 {
 546         clear_bit(POSTED_INTR_ON,
 547                   (unsigned long *)&pi_desc->control);
 548 }
 549
 550 static inline int pi_test_on(struct pi_desc *pi_desc)
 551 {
 552         return test_bit(POSTED_INTR_ON,
 553                         (unsigned long *)&pi_desc->control);
 554 }
 555
 556 static inline int pi_test_sn(struct pi_desc *pi_desc)
 557 {
 558         return test_bit(POSTED_INTR_SN,
 559                         (unsigned long *)&pi_desc->control);
 560 }
 561
 562 struct vcpu_vmx {
 563         struct kvm_vcpu       vcpu;
 564         unsigned long         host_rsp;
 565         u8                    fail;
 566         u32                   exit_intr_info;
 567         u32                   idt_vectoring_info;
 568         ulong                 rflags;
 569         struct shared_msr_entry *guest_msrs;
 570         int                   nmsrs;
 571         int                   save_nmsrs;
 572         unsigned long         host_idt_base;
 573 #ifdef CONFIG_X86_64
 574         u64                   msr_host_kernel_gs_base;
 575         u64                   msr_guest_kernel_gs_base;
 576 #endif
 577         u32 vm_entry_controls_shadow;
 578         u32 vm_exit_controls_shadow;
 579         /*
 580          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 581          * non-nested (L1) guest, it always points to vmcs01. For a nested
 582          * guest (L2), it points to a different VMCS.
 583          */
 584         struct loaded_vmcs    vmcs01;
 585         struct loaded_vmcs   *loaded_vmcs;
 586         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 587         struct msr_autoload {
 588                 unsigned nr;
 589                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 590                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 591         } msr_autoload;
 592         struct {
 593                 int           loaded;
 594                 u16           fs_sel, gs_sel, ldt_sel;
 595 #ifdef CONFIG_X86_64
 596                 u16           ds_sel, es_sel;
 597 #endif
 598                 int           gs_ldt_reload_needed;
 599                 int           fs_reload_needed;
 600                 u64           msr_host_bndcfgs;
 601                 unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 602                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 603         } host_state;
 604         struct {
 605                 int vm86_active;
 606                 ulong save_rflags;
 607                 struct kvm_segment segs[8];
 608         } rmode;
 609         struct {
 610                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 611                 struct kvm_save_segment {
 612                         u16 selector;
 613                         unsigned long base;
 614                         u32 limit;
 615                         u32 ar;
 616                 } seg[8];
 617         } segment_cache;
 618         int vpid;
 619         bool emulation_required;
 620
 621         u32 exit_reason;
 622
 623         /* Posted interrupt descriptor */
 624         struct pi_desc pi_desc;
 625
 626         /* Support for a guest hypervisor (nested VMX) */
 627         struct nested_vmx nested;
 628
 629         /* Dynamic PLE window. */
 630         int ple_window;
 631         bool ple_window_dirty;
 632
 633         /* Support for PML */
 634 #define PML_ENTITY_NUM          512
 635         struct page *pml_pg;
 636
 637         /* apic deadline value in host tsc */
 638         u64 hv_deadline_tsc;
 639
 640         u64 current_tsc_ratio;
 641
 642         bool guest_pkru_valid;
 643         u32 guest_pkru;
 644         u32 host_pkru;
 645
 646         /*
 647          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 648          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 649          * in msr_ia32_feature_control_valid_bits.
 650          */
 651         u64 msr_ia32_feature_control;
 652         u64 msr_ia32_feature_control_valid_bits;
 653 };
 654
 655 enum segment_cache_field {
 656         SEG_FIELD_SEL = 0,
 657         SEG_FIELD_BASE = 1,
 658         SEG_FIELD_LIMIT = 2,
 659         SEG_FIELD_AR = 3,
 660
 661         SEG_FIELD_NR = 4
 662 };
 663
 664 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 665 {
 666         return container_of(vcpu, struct vcpu_vmx, vcpu);
 667 }
 668
 669 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 670 {
 671         return &(to_vmx(vcpu)->pi_desc);
 672 }
 673
 674 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 675 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 676 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 677                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 678
 679
 680 static unsigned long shadow_read_only_fields[] = {
 681         /*
 682          * We do NOT shadow fields that are modified when L0
 683          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 684          * VMXON...) executed by L1.
 685          * For example, VM_INSTRUCTION_ERROR is read
 686          * by L1 if a vmx instruction fails (part of the error path).
 687          * Note the code assumes this logic. If for some reason
 688          * we start shadowing these fields then we need to
 689          * force a shadow sync when L0 emulates vmx instructions
 690          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 691          * by nested_vmx_failValid)
 692          */
 693         VM_EXIT_REASON,
 694         VM_EXIT_INTR_INFO,
 695         VM_EXIT_INSTRUCTION_LEN,
 696         IDT_VECTORING_INFO_FIELD,
 697         IDT_VECTORING_ERROR_CODE,
 698         VM_EXIT_INTR_ERROR_CODE,
 699         EXIT_QUALIFICATION,
 700         GUEST_LINEAR_ADDRESS,
 701         GUEST_PHYSICAL_ADDRESS
 702 };
 703 static int max_shadow_read_only_fields =
 704         ARRAY_SIZE(shadow_read_only_fields);
 705
 706 static unsigned long shadow_read_write_fields[] = {
 707         TPR_THRESHOLD,
 708         GUEST_RIP,
 709         GUEST_RSP,
 710         GUEST_CR0,
 711         GUEST_CR3,
 712         GUEST_CR4,
 713         GUEST_INTERRUPTIBILITY_INFO,
 714         GUEST_RFLAGS,
 715         GUEST_CS_SELECTOR,
 716         GUEST_CS_AR_BYTES,
 717         GUEST_CS_LIMIT,
 718         GUEST_CS_BASE,
 719         GUEST_ES_BASE,
 720         GUEST_BNDCFGS,
 721         CR0_GUEST_HOST_MASK,
 722         CR0_READ_SHADOW,
 723         CR4_READ_SHADOW,
 724         TSC_OFFSET,
 725         EXCEPTION_BITMAP,
 726         CPU_BASED_VM_EXEC_CONTROL,
 727         VM_ENTRY_EXCEPTION_ERROR_CODE,
 728         VM_ENTRY_INTR_INFO_FIELD,
 729         VM_ENTRY_INSTRUCTION_LEN,
 730         VM_ENTRY_EXCEPTION_ERROR_CODE,
 731         HOST_FS_BASE,
 732         HOST_GS_BASE,
 733         HOST_FS_SELECTOR,
 734         HOST_GS_SELECTOR
 735 };
 736 static int max_shadow_read_write_fields =
 737         ARRAY_SIZE(shadow_read_write_fields);
 738
 739 static const unsigned short vmcs_field_to_offset_table[] = {
 740         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 741         FIELD(POSTED_INTR_NV, posted_intr_nv),
 742         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 743         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 744         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 745         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 746         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 747         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 748         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 749         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 750         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 751         FIELD(GUEST_PML_INDEX, guest_pml_index),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(EPT_POINTER, ept_pointer),
 770         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 771         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 772         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 773         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 774         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 775         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 776         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 777         FIELD64(PML_ADDRESS, pml_address),
 778         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 779         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 780         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 781         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 782         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 783         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 784         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 785         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 786         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 787         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 788         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 789         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 790         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 791         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 792         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 793         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 794         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 795         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 796         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 797         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 798         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 799         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 800         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 801         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 802         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 803         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 804         FIELD(TPR_THRESHOLD, tpr_threshold),
 805         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 806         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 807         FIELD(VM_EXIT_REASON, vm_exit_reason),
 808         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 809         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 810         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 811         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 812         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 813         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 814         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 815         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 816         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 817         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 818         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 819         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 820         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 821         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 822         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 823         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 824         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 825         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 826         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 827         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 828         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 829         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 830         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 831         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 832         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 833         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 834         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 835         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 836         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 837         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 838         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 839         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 840         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 841         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 842         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 843         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 844         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 845         FIELD(EXIT_QUALIFICATION, exit_qualification),
 846         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 847         FIELD(GUEST_CR0, guest_cr0),
 848         FIELD(GUEST_CR3, guest_cr3),
 849         FIELD(GUEST_CR4, guest_cr4),
 850         FIELD(GUEST_ES_BASE, guest_es_base),
 851         FIELD(GUEST_CS_BASE, guest_cs_base),
 852         FIELD(GUEST_SS_BASE, guest_ss_base),
 853         FIELD(GUEST_DS_BASE, guest_ds_base),
 854         FIELD(GUEST_FS_BASE, guest_fs_base),
 855         FIELD(GUEST_GS_BASE, guest_gs_base),
 856         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 857         FIELD(GUEST_TR_BASE, guest_tr_base),
 858         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 859         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 860         FIELD(GUEST_DR7, guest_dr7),
 861         FIELD(GUEST_RSP, guest_rsp),
 862         FIELD(GUEST_RIP, guest_rip),
 863         FIELD(GUEST_RFLAGS, guest_rflags),
 864         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 865         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 866         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 867         FIELD(HOST_CR0, host_cr0),
 868         FIELD(HOST_CR3, host_cr3),
 869         FIELD(HOST_CR4, host_cr4),
 870         FIELD(HOST_FS_BASE, host_fs_base),
 871         FIELD(HOST_GS_BASE, host_gs_base),
 872         FIELD(HOST_TR_BASE, host_tr_base),
 873         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 874         FIELD(HOST_IDTR_BASE, host_idtr_base),
 875         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 876         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 877         FIELD(HOST_RSP, host_rsp),
 878         FIELD(HOST_RIP, host_rip),
 879 };
 880
 881 static inline short vmcs_field_to_offset(unsigned long field)
 882 {
 883         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 884
 885         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 886             vmcs_field_to_offset_table[field] == 0)
 887                 return -ENOENT;
 888
 889         return vmcs_field_to_offset_table[field];
 890 }
 891
 892 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 893 {
 894         return to_vmx(vcpu)->nested.cached_vmcs12;
 895 }
 896
 897 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 898 {
 899         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 900         if (is_error_page(page))
 901                 return NULL;
 902
 903         return page;
 904 }
 905
 906 static void nested_release_page(struct page *page)
 907 {
 908         kvm_release_page_dirty(page);
 909 }
 910
 911 static void nested_release_page_clean(struct page *page)
 912 {
 913         kvm_release_page_clean(page);
 914 }
 915
 916 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
 917 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 918 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 919 static bool vmx_xsaves_supported(void);
 920 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 921 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 922                             struct kvm_segment *var, int seg);
 923 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 924                             struct kvm_segment *var, int seg);
 925 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 926 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 927 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 928 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 929 static int alloc_identity_pagetable(struct kvm *kvm);
 930
 931 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 932 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 933 /*
 934  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 935  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 936  */
 937 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 938
 939 /*
 940  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 941  * can find which vCPU should be waken up.
 942  */
 943 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 944 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 945
 946 enum {
 947         VMX_IO_BITMAP_A,
 948         VMX_IO_BITMAP_B,
 949         VMX_MSR_BITMAP_LEGACY,
 950         VMX_MSR_BITMAP_LONGMODE,
 951         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 952         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 953         VMX_MSR_BITMAP_LEGACY_X2APIC,
 954         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 955         VMX_VMREAD_BITMAP,
 956         VMX_VMWRITE_BITMAP,
 957         VMX_BITMAP_NR
 958 };
 959
 960 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 961
 962 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 963 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 964 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 965 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 966 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 967 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 968 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 969 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 970 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 971 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 972
 973 static bool cpu_has_load_ia32_efer;
 974 static bool cpu_has_load_perf_global_ctrl;
 975
 976 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 977 static DEFINE_SPINLOCK(vmx_vpid_lock);
 978
 979 static struct vmcs_config {
 980         int size;
 981         int order;
 982         u32 basic_cap;
 983         u32 revision_id;
 984         u32 pin_based_exec_ctrl;
 985         u32 cpu_based_exec_ctrl;
 986         u32 cpu_based_2nd_exec_ctrl;
 987         u32 vmexit_ctrl;
 988         u32 vmentry_ctrl;
 989 } vmcs_config;
 990
 991 static struct vmx_capability {
 992         u32 ept;
 993         u32 vpid;
 994 } vmx_capability;
 995
 996 #define VMX_SEGMENT_FIELD(seg)                                  \
 997         [VCPU_SREG_##seg] = {                                   \
 998                 .selector = GUEST_##seg##_SELECTOR,             \
 999                 .base = GUEST_##seg##_BASE,                     \
1000                 .limit = GUEST_##seg##_LIMIT,                   \
1001                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1002         }
1003
1004 static const struct kvm_vmx_segment_field {
1005         unsigned selector;
1006         unsigned base;
1007         unsigned limit;
1008         unsigned ar_bytes;
1009 } kvm_vmx_segment_fields[] = {
1010         VMX_SEGMENT_FIELD(CS),
1011         VMX_SEGMENT_FIELD(DS),
1012         VMX_SEGMENT_FIELD(ES),
1013         VMX_SEGMENT_FIELD(FS),
1014         VMX_SEGMENT_FIELD(GS),
1015         VMX_SEGMENT_FIELD(SS),
1016         VMX_SEGMENT_FIELD(TR),
1017         VMX_SEGMENT_FIELD(LDTR),
1018 };
1019
1020 static u64 host_efer;
1021
1022 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1023
1024 /*
1025  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1026  * away by decrementing the array size.
1027  */
1028 static const u32 vmx_msr_index[] = {
1029 #ifdef CONFIG_X86_64
1030         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1031 #endif
1032         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1033 };
1034
1035 static inline bool is_exception_n(u32 intr_info, u8 vector)
1036 {
1037         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1038                              INTR_INFO_VALID_MASK)) ==
1039                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1040 }
1041
1042 static inline bool is_debug(u32 intr_info)
1043 {
1044         return is_exception_n(intr_info, DB_VECTOR);
1045 }
1046
1047 static inline bool is_breakpoint(u32 intr_info)
1048 {
1049         return is_exception_n(intr_info, BP_VECTOR);
1050 }
1051
1052 static inline bool is_page_fault(u32 intr_info)
1053 {
1054         return is_exception_n(intr_info, PF_VECTOR);
1055 }
1056
1057 static inline bool is_no_device(u32 intr_info)
1058 {
1059         return is_exception_n(intr_info, NM_VECTOR);
1060 }
1061
1062 static inline bool is_invalid_opcode(u32 intr_info)
1063 {
1064         return is_exception_n(intr_info, UD_VECTOR);
1065 }
1066
1067 static inline bool is_external_interrupt(u32 intr_info)
1068 {
1069         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1070                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1071 }
1072
1073 static inline bool is_machine_check(u32 intr_info)
1074 {
1075         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1076                              INTR_INFO_VALID_MASK)) ==
1077                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1078 }
1079
1080 static inline bool cpu_has_vmx_msr_bitmap(void)
1081 {
1082         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1083 }
1084
1085 static inline bool cpu_has_vmx_tpr_shadow(void)
1086 {
1087         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1088 }
1089
1090 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1091 {
1092         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1093 }
1094
1095 static inline bool cpu_has_secondary_exec_ctrls(void)
1096 {
1097         return vmcs_config.cpu_based_exec_ctrl &
1098                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1099 }
1100
1101 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1102 {
1103         return vmcs_config.cpu_based_2nd_exec_ctrl &
1104                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1105 }
1106
1107 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1108 {
1109         return vmcs_config.cpu_based_2nd_exec_ctrl &
1110                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1111 }
1112
1113 static inline bool cpu_has_vmx_apic_register_virt(void)
1114 {
1115         return vmcs_config.cpu_based_2nd_exec_ctrl &
1116                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1117 }
1118
1119 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1120 {
1121         return vmcs_config.cpu_based_2nd_exec_ctrl &
1122                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1123 }
1124
1125 /*
1126  * Comment's format: document - errata name - stepping - processor name.
1127  * Refer from
1128  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1129  */
1130 static u32 vmx_preemption_cpu_tfms[] = {
1131 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1132 0x000206E6,
1133 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1134 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1135 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1136 0x00020652,
1137 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1138 0x00020655,
1139 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1140 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1141 /*
1142  * 320767.pdf - AAP86  - B1 -
1143  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1144  */
1145 0x000106E5,
1146 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1147 0x000106A0,
1148 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1149 0x000106A1,
1150 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1151 0x000106A4,
1152  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1153  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1154  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1155 0x000106A5,
1156 };
1157
1158 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1159 {
1160         u32 eax = cpuid_eax(0x00000001), i;
1161
1162         /* Clear the reserved bits */
1163         eax &= ~(0x3U << 14 | 0xfU << 28);
1164         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1165                 if (eax == vmx_preemption_cpu_tfms[i])
1166                         return true;
1167
1168         return false;
1169 }
1170
1171 static inline bool cpu_has_vmx_preemption_timer(void)
1172 {
1173         return vmcs_config.pin_based_exec_ctrl &
1174                 PIN_BASED_VMX_PREEMPTION_TIMER;
1175 }
1176
1177 static inline bool cpu_has_vmx_posted_intr(void)
1178 {
1179         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1180                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1181 }
1182
1183 static inline bool cpu_has_vmx_apicv(void)
1184 {
1185         return cpu_has_vmx_apic_register_virt() &&
1186                 cpu_has_vmx_virtual_intr_delivery() &&
1187                 cpu_has_vmx_posted_intr();
1188 }
1189
1190 static inline bool cpu_has_vmx_flexpriority(void)
1191 {
1192         return cpu_has_vmx_tpr_shadow() &&
1193                 cpu_has_vmx_virtualize_apic_accesses();
1194 }
1195
1196 static inline bool cpu_has_vmx_ept_execute_only(void)
1197 {
1198         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1199 }
1200
1201 static inline bool cpu_has_vmx_ept_2m_page(void)
1202 {
1203         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1204 }
1205
1206 static inline bool cpu_has_vmx_ept_1g_page(void)
1207 {
1208         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1209 }
1210
1211 static inline bool cpu_has_vmx_ept_4levels(void)
1212 {
1213         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1214 }
1215
1216 static inline bool cpu_has_vmx_ept_ad_bits(void)
1217 {
1218         return vmx_capability.ept & VMX_EPT_AD_BIT;
1219 }
1220
1221 static inline bool cpu_has_vmx_invept_context(void)
1222 {
1223         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1224 }
1225
1226 static inline bool cpu_has_vmx_invept_global(void)
1227 {
1228         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1229 }
1230
1231 static inline bool cpu_has_vmx_invvpid_single(void)
1232 {
1233         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1234 }
1235
1236 static inline bool cpu_has_vmx_invvpid_global(void)
1237 {
1238         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1239 }
1240
1241 static inline bool cpu_has_vmx_invvpid(void)
1242 {
1243         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1244 }
1245
1246 static inline bool cpu_has_vmx_ept(void)
1247 {
1248         return vmcs_config.cpu_based_2nd_exec_ctrl &
1249                 SECONDARY_EXEC_ENABLE_EPT;
1250 }
1251
1252 static inline bool cpu_has_vmx_unrestricted_guest(void)
1253 {
1254         return vmcs_config.cpu_based_2nd_exec_ctrl &
1255                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1256 }
1257
1258 static inline bool cpu_has_vmx_ple(void)
1259 {
1260         return vmcs_config.cpu_based_2nd_exec_ctrl &
1261                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1262 }
1263
1264 static inline bool cpu_has_vmx_basic_inout(void)
1265 {
1266         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1267 }
1268
1269 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1270 {
1271         return flexpriority_enabled && lapic_in_kernel(vcpu);
1272 }
1273
1274 static inline bool cpu_has_vmx_vpid(void)
1275 {
1276         return vmcs_config.cpu_based_2nd_exec_ctrl &
1277                 SECONDARY_EXEC_ENABLE_VPID;
1278 }
1279
1280 static inline bool cpu_has_vmx_rdtscp(void)
1281 {
1282         return vmcs_config.cpu_based_2nd_exec_ctrl &
1283                 SECONDARY_EXEC_RDTSCP;
1284 }
1285
1286 static inline bool cpu_has_vmx_invpcid(void)
1287 {
1288         return vmcs_config.cpu_based_2nd_exec_ctrl &
1289                 SECONDARY_EXEC_ENABLE_INVPCID;
1290 }
1291
1292 static inline bool cpu_has_vmx_wbinvd_exit(void)
1293 {
1294         return vmcs_config.cpu_based_2nd_exec_ctrl &
1295                 SECONDARY_EXEC_WBINVD_EXITING;
1296 }
1297
1298 static inline bool cpu_has_vmx_shadow_vmcs(void)
1299 {
1300         u64 vmx_msr;
1301         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1302         /* check if the cpu supports writing r/o exit information fields */
1303         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1304                 return false;
1305
1306         return vmcs_config.cpu_based_2nd_exec_ctrl &
1307                 SECONDARY_EXEC_SHADOW_VMCS;
1308 }
1309
1310 static inline bool cpu_has_vmx_pml(void)
1311 {
1312         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1313 }
1314
1315 static inline bool cpu_has_vmx_tsc_scaling(void)
1316 {
1317         return vmcs_config.cpu_based_2nd_exec_ctrl &
1318                 SECONDARY_EXEC_TSC_SCALING;
1319 }
1320
1321 static inline bool report_flexpriority(void)
1322 {
1323         return flexpriority_enabled;
1324 }
1325
1326 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1327 {
1328         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1329 }
1330
1331 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1332 {
1333         return vmcs12->cpu_based_vm_exec_control & bit;
1334 }
1335
1336 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1337 {
1338         return (vmcs12->cpu_based_vm_exec_control &
1339                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1340                 (vmcs12->secondary_vm_exec_control & bit);
1341 }
1342
1343 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1344 {
1345         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1346 }
1347
1348 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1349 {
1350         return vmcs12->pin_based_vm_exec_control &
1351                 PIN_BASED_VMX_PREEMPTION_TIMER;
1352 }
1353
1354 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1355 {
1356         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1357 }
1358
1359 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1360 {
1361         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1362                 vmx_xsaves_supported();
1363 }
1364
1365 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1366 {
1367         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1368 }
1369
1370 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1371 {
1372         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1373 }
1374
1375 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1376 {
1377         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1378 }
1379
1380 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1381 {
1382         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1383 }
1384
1385 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1386 {
1387         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1388 }
1389
1390 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1391 {
1392         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1393 }
1394
1395 static inline bool is_nmi(u32 intr_info)
1396 {
1397         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1398                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1399 }
1400
1401 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1402                               u32 exit_intr_info,
1403                               unsigned long exit_qualification);
1404 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1405                         struct vmcs12 *vmcs12,
1406                         u32 reason, unsigned long qualification);
1407
1408 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1409 {
1410         int i;
1411
1412         for (i = 0; i < vmx->nmsrs; ++i)
1413                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1414                         return i;
1415         return -1;
1416 }
1417
1418 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1419 {
1420     struct {
1421         u64 vpid : 16;
1422         u64 rsvd : 48;
1423         u64 gva;
1424     } operand = { vpid, 0, gva };
1425
1426     asm volatile (__ex(ASM_VMX_INVVPID)
1427                   /* CF==1 or ZF==1 --> rc = -1 */
1428                   "; ja 1f ; ud2 ; 1:"
1429                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1430 }
1431
1432 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1433 {
1434         struct {
1435                 u64 eptp, gpa;
1436         } operand = {eptp, gpa};
1437
1438         asm volatile (__ex(ASM_VMX_INVEPT)
1439                         /* CF==1 or ZF==1 --> rc = -1 */
1440                         "; ja 1f ; ud2 ; 1:\n"
1441                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1442 }
1443
1444 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1445 {
1446         int i;
1447
1448         i = __find_msr_index(vmx, msr);
1449         if (i >= 0)
1450                 return &vmx->guest_msrs[i];
1451         return NULL;
1452 }
1453
1454 static void vmcs_clear(struct vmcs *vmcs)
1455 {
1456         u64 phys_addr = __pa(vmcs);
1457         u8 error;
1458
1459         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1460                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1461                       : "cc", "memory");
1462         if (error)
1463                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1464                        vmcs, phys_addr);
1465 }
1466
1467 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1468 {
1469         vmcs_clear(loaded_vmcs->vmcs);
1470         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1471                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1472         loaded_vmcs->cpu = -1;
1473         loaded_vmcs->launched = 0;
1474 }
1475
1476 static void vmcs_load(struct vmcs *vmcs)
1477 {
1478         u64 phys_addr = __pa(vmcs);
1479         u8 error;
1480
1481         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1482                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1483                         : "cc", "memory");
1484         if (error)
1485                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1486                        vmcs, phys_addr);
1487 }
1488
1489 #ifdef CONFIG_KEXEC_CORE
1490 /*
1491  * This bitmap is used to indicate whether the vmclear
1492  * operation is enabled on all cpus. All disabled by
1493  * default.
1494  */
1495 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1496
1497 static inline void crash_enable_local_vmclear(int cpu)
1498 {
1499         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1500 }
1501
1502 static inline void crash_disable_local_vmclear(int cpu)
1503 {
1504         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1505 }
1506
1507 static inline int crash_local_vmclear_enabled(int cpu)
1508 {
1509         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1510 }
1511
1512 static void crash_vmclear_local_loaded_vmcss(void)
1513 {
1514         int cpu = raw_smp_processor_id();
1515         struct loaded_vmcs *v;
1516
1517         if (!crash_local_vmclear_enabled(cpu))
1518                 return;
1519
1520         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1521                             loaded_vmcss_on_cpu_link)
1522                 vmcs_clear(v->vmcs);
1523 }
1524 #else
1525 static inline void crash_enable_local_vmclear(int cpu) { }
1526 static inline void crash_disable_local_vmclear(int cpu) { }
1527 #endif /* CONFIG_KEXEC_CORE */
1528
1529 static void __loaded_vmcs_clear(void *arg)
1530 {
1531         struct loaded_vmcs *loaded_vmcs = arg;
1532         int cpu = raw_smp_processor_id();
1533
1534         if (loaded_vmcs->cpu != cpu)
1535                 return; /* vcpu migration can race with cpu offline */
1536         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1537                 per_cpu(current_vmcs, cpu) = NULL;
1538         crash_disable_local_vmclear(cpu);
1539         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1540
1541         /*
1542          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1543          * is before setting loaded_vmcs->vcpu to -1 which is done in
1544          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1545          * then adds the vmcs into percpu list before it is deleted.
1546          */
1547         smp_wmb();
1548
1549         loaded_vmcs_init(loaded_vmcs);
1550         crash_enable_local_vmclear(cpu);
1551 }
1552
1553 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1554 {
1555         int cpu = loaded_vmcs->cpu;
1556
1557         if (cpu != -1)
1558                 smp_call_function_single(cpu,
1559                          __loaded_vmcs_clear, loaded_vmcs, 1);
1560 }
1561
1562 static inline void vpid_sync_vcpu_single(int vpid)
1563 {
1564         if (vpid == 0)
1565                 return;
1566
1567         if (cpu_has_vmx_invvpid_single())
1568                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1569 }
1570
1571 static inline void vpid_sync_vcpu_global(void)
1572 {
1573         if (cpu_has_vmx_invvpid_global())
1574                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1575 }
1576
1577 static inline void vpid_sync_context(int vpid)
1578 {
1579         if (cpu_has_vmx_invvpid_single())
1580                 vpid_sync_vcpu_single(vpid);
1581         else
1582                 vpid_sync_vcpu_global();
1583 }
1584
1585 static inline void ept_sync_global(void)
1586 {
1587         if (cpu_has_vmx_invept_global())
1588                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1589 }
1590
1591 static inline void ept_sync_context(u64 eptp)
1592 {
1593         if (enable_ept) {
1594                 if (cpu_has_vmx_invept_context())
1595                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1596                 else
1597                         ept_sync_global();
1598         }
1599 }
1600
1601 static __always_inline void vmcs_check16(unsigned long field)
1602 {
1603         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1604                          "16-bit accessor invalid for 64-bit field");
1605         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1606                          "16-bit accessor invalid for 64-bit high field");
1607         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1608                          "16-bit accessor invalid for 32-bit high field");
1609         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1610                          "16-bit accessor invalid for natural width field");
1611 }
1612
1613 static __always_inline void vmcs_check32(unsigned long field)
1614 {
1615         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1616                          "32-bit accessor invalid for 16-bit field");
1617         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1618                          "32-bit accessor invalid for natural width field");
1619 }
1620
1621 static __always_inline void vmcs_check64(unsigned long field)
1622 {
1623         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1624                          "64-bit accessor invalid for 16-bit field");
1625         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1626                          "64-bit accessor invalid for 64-bit high field");
1627         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1628                          "64-bit accessor invalid for 32-bit field");
1629         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1630                          "64-bit accessor invalid for natural width field");
1631 }
1632
1633 static __always_inline void vmcs_checkl(unsigned long field)
1634 {
1635         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1636                          "Natural width accessor invalid for 16-bit field");
1637         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1638                          "Natural width accessor invalid for 64-bit field");
1639         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1640                          "Natural width accessor invalid for 64-bit high field");
1641         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1642                          "Natural width accessor invalid for 32-bit field");
1643 }
1644
1645 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1646 {
1647         unsigned long value;
1648
1649         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1650                       : "=a"(value) : "d"(field) : "cc");
1651         return value;
1652 }
1653
1654 static __always_inline u16 vmcs_read16(unsigned long field)
1655 {
1656         vmcs_check16(field);
1657         return __vmcs_readl(field);
1658 }
1659
1660 static __always_inline u32 vmcs_read32(unsigned long field)
1661 {
1662         vmcs_check32(field);
1663         return __vmcs_readl(field);
1664 }
1665
1666 static __always_inline u64 vmcs_read64(unsigned long field)
1667 {
1668         vmcs_check64(field);
1669 #ifdef CONFIG_X86_64
1670         return __vmcs_readl(field);
1671 #else
1672         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1673 #endif
1674 }
1675
1676 static __always_inline unsigned long vmcs_readl(unsigned long field)
1677 {
1678         vmcs_checkl(field);
1679         return __vmcs_readl(field);
1680 }
1681
1682 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1683 {
1684         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1685                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1686         dump_stack();
1687 }
1688
1689 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1690 {
1691         u8 error;
1692
1693         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1694                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1695         if (unlikely(error))
1696                 vmwrite_error(field, value);
1697 }
1698
1699 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1700 {
1701         vmcs_check16(field);
1702         __vmcs_writel(field, value);
1703 }
1704
1705 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1706 {
1707         vmcs_check32(field);
1708         __vmcs_writel(field, value);
1709 }
1710
1711 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1712 {
1713         vmcs_check64(field);
1714         __vmcs_writel(field, value);
1715 #ifndef CONFIG_X86_64
1716         asm volatile ("");
1717         __vmcs_writel(field+1, value >> 32);
1718 #endif
1719 }
1720
1721 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1722 {
1723         vmcs_checkl(field);
1724         __vmcs_writel(field, value);
1725 }
1726
1727 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1728 {
1729         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1730                          "vmcs_clear_bits does not support 64-bit fields");
1731         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1732 }
1733
1734 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1735 {
1736         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1737                          "vmcs_set_bits does not support 64-bit fields");
1738         __vmcs_writel(field, __vmcs_readl(field) | mask);
1739 }
1740
1741 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1742 {
1743         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1744 }
1745
1746 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1747 {
1748         vmcs_write32(VM_ENTRY_CONTROLS, val);
1749         vmx->vm_entry_controls_shadow = val;
1750 }
1751
1752 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1753 {
1754         if (vmx->vm_entry_controls_shadow != val)
1755                 vm_entry_controls_init(vmx, val);
1756 }
1757
1758 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1759 {
1760         return vmx->vm_entry_controls_shadow;
1761 }
1762
1763
1764 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1765 {
1766         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1767 }
1768
1769 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1770 {
1771         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1772 }
1773
1774 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1775 {
1776         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1777 }
1778
1779 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1780 {
1781         vmcs_write32(VM_EXIT_CONTROLS, val);
1782         vmx->vm_exit_controls_shadow = val;
1783 }
1784
1785 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1786 {
1787         if (vmx->vm_exit_controls_shadow != val)
1788                 vm_exit_controls_init(vmx, val);
1789 }
1790
1791 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1792 {
1793         return vmx->vm_exit_controls_shadow;
1794 }
1795
1796
1797 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1798 {
1799         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1800 }
1801
1802 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1803 {
1804         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1805 }
1806
1807 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1808 {
1809         vmx->segment_cache.bitmask = 0;
1810 }
1811
1812 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1813                                        unsigned field)
1814 {
1815         bool ret;
1816         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1817
1818         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1819                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1820                 vmx->segment_cache.bitmask = 0;
1821         }
1822         ret = vmx->segment_cache.bitmask & mask;
1823         vmx->segment_cache.bitmask |= mask;
1824         return ret;
1825 }
1826
1827 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1828 {
1829         u16 *p = &vmx->segment_cache.seg[seg].selector;
1830
1831         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1832                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1833         return *p;
1834 }
1835
1836 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1837 {
1838         ulong *p = &vmx->segment_cache.seg[seg].base;
1839
1840         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1841                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1842         return *p;
1843 }
1844
1845 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1846 {
1847         u32 *p = &vmx->segment_cache.seg[seg].limit;
1848
1849         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1850                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1851         return *p;
1852 }
1853
1854 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1855 {
1856         u32 *p = &vmx->segment_cache.seg[seg].ar;
1857
1858         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1859                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1860         return *p;
1861 }
1862
1863 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1864 {
1865         u32 eb;
1866
1867         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1868              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1869         if ((vcpu->guest_debug &
1870              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1871             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1872                 eb |= 1u << BP_VECTOR;
1873         if (to_vmx(vcpu)->rmode.vm86_active)
1874                 eb = ~0;
1875         if (enable_ept)
1876                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1877
1878         /* When we are running a nested L2 guest and L1 specified for it a
1879          * certain exception bitmap, we must trap the same exceptions and pass
1880          * them to L1. When running L2, we will only handle the exceptions
1881          * specified above if L1 did not want them.
1882          */
1883         if (is_guest_mode(vcpu))
1884                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1885
1886         vmcs_write32(EXCEPTION_BITMAP, eb);
1887 }
1888
1889 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1890                 unsigned long entry, unsigned long exit)
1891 {
1892         vm_entry_controls_clearbit(vmx, entry);
1893         vm_exit_controls_clearbit(vmx, exit);
1894 }
1895
1896 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1897 {
1898         unsigned i;
1899         struct msr_autoload *m = &vmx->msr_autoload;
1900
1901         switch (msr) {
1902         case MSR_EFER:
1903                 if (cpu_has_load_ia32_efer) {
1904                         clear_atomic_switch_msr_special(vmx,
1905                                         VM_ENTRY_LOAD_IA32_EFER,
1906                                         VM_EXIT_LOAD_IA32_EFER);
1907                         return;
1908                 }
1909                 break;
1910         case MSR_CORE_PERF_GLOBAL_CTRL:
1911                 if (cpu_has_load_perf_global_ctrl) {
1912                         clear_atomic_switch_msr_special(vmx,
1913                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1914                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1915                         return;
1916                 }
1917                 break;
1918         }
1919
1920         for (i = 0; i < m->nr; ++i)
1921                 if (m->guest[i].index == msr)
1922                         break;
1923
1924         if (i == m->nr)
1925                 return;
1926         --m->nr;
1927         m->guest[i] = m->guest[m->nr];
1928         m->host[i] = m->host[m->nr];
1929         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1930         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1931 }
1932
1933 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1934                 unsigned long entry, unsigned long exit,
1935                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1936                 u64 guest_val, u64 host_val)
1937 {
1938         vmcs_write64(guest_val_vmcs, guest_val);
1939         vmcs_write64(host_val_vmcs, host_val);
1940         vm_entry_controls_setbit(vmx, entry);
1941         vm_exit_controls_setbit(vmx, exit);
1942 }
1943
1944 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1945                                   u64 guest_val, u64 host_val)
1946 {
1947         unsigned i;
1948         struct msr_autoload *m = &vmx->msr_autoload;
1949
1950         switch (msr) {
1951         case MSR_EFER:
1952                 if (cpu_has_load_ia32_efer) {
1953                         add_atomic_switch_msr_special(vmx,
1954                                         VM_ENTRY_LOAD_IA32_EFER,
1955                                         VM_EXIT_LOAD_IA32_EFER,
1956                                         GUEST_IA32_EFER,
1957                                         HOST_IA32_EFER,
1958                                         guest_val, host_val);
1959                         return;
1960                 }
1961                 break;
1962         case MSR_CORE_PERF_GLOBAL_CTRL:
1963                 if (cpu_has_load_perf_global_ctrl) {
1964                         add_atomic_switch_msr_special(vmx,
1965                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1966                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1967                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1968                                         HOST_IA32_PERF_GLOBAL_CTRL,
1969                                         guest_val, host_val);
1970                         return;
1971                 }
1972                 break;
1973         case MSR_IA32_PEBS_ENABLE:
1974                 /* PEBS needs a quiescent period after being disabled (to write
1975                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1976                  * provide that period, so a CPU could write host's record into
1977                  * guest's memory.
1978                  */
1979                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1980         }
1981
1982         for (i = 0; i < m->nr; ++i)
1983                 if (m->guest[i].index == msr)
1984                         break;
1985
1986         if (i == NR_AUTOLOAD_MSRS) {
1987                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1988                                 "Can't add msr %x\n", msr);
1989                 return;
1990         } else if (i == m->nr) {
1991                 ++m->nr;
1992                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1993                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1994         }
1995
1996         m->guest[i].index = msr;
1997         m->guest[i].value = guest_val;
1998         m->host[i].index = msr;
1999         m->host[i].value = host_val;
2000 }
2001
2002 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2003 {
2004         u64 guest_efer = vmx->vcpu.arch.efer;
2005         u64 ignore_bits = 0;
2006
2007         if (!enable_ept) {
2008                 /*
2009                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2010                  * host CPUID is more efficient than testing guest CPUID
2011                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2012                  */
2013                 if (boot_cpu_has(X86_FEATURE_SMEP))
2014                         guest_efer |= EFER_NX;
2015                 else if (!(guest_efer & EFER_NX))
2016                         ignore_bits |= EFER_NX;
2017         }
2018
2019         /*
2020          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2021          */
2022         ignore_bits |= EFER_SCE;
2023 #ifdef CONFIG_X86_64
2024         ignore_bits |= EFER_LMA | EFER_LME;
2025         /* SCE is meaningful only in long mode on Intel */
2026         if (guest_efer & EFER_LMA)
2027                 ignore_bits &= ~(u64)EFER_SCE;
2028 #endif
2029
2030         clear_atomic_switch_msr(vmx, MSR_EFER);
2031
2032         /*
2033          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2034          * On CPUs that support "load IA32_EFER", always switch EFER
2035          * atomically, since it's faster than switching it manually.
2036          */
2037         if (cpu_has_load_ia32_efer ||
2038             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2039                 if (!(guest_efer & EFER_LMA))
2040                         guest_efer &= ~EFER_LME;
2041                 if (guest_efer != host_efer)
2042                         add_atomic_switch_msr(vmx, MSR_EFER,
2043                                               guest_efer, host_efer);
2044                 return false;
2045         } else {
2046                 guest_efer &= ~ignore_bits;
2047                 guest_efer |= host_efer & ignore_bits;
2048
2049                 vmx->guest_msrs[efer_offset].data = guest_efer;
2050                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2051
2052                 return true;
2053         }
2054 }
2055
2056 #ifdef CONFIG_X86_32
2057 /*
2058  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2059  * VMCS rather than the segment table.  KVM uses this helper to figure
2060  * out the current bases to poke them into the VMCS before entry.
2061  */
2062 static unsigned long segment_base(u16 selector)
2063 {
2064         struct desc_struct *table;
2065         unsigned long v;
2066
2067         if (!(selector & ~SEGMENT_RPL_MASK))
2068                 return 0;
2069
2070         table = get_current_gdt_ro();
2071
2072         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2073                 u16 ldt_selector = kvm_read_ldt();
2074
2075                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2076                         return 0;
2077
2078                 table = (struct desc_struct *)segment_base(ldt_selector);
2079         }
2080         v = get_desc_base(&table[selector >> 3]);
2081         return v;
2082 }
2083 #endif
2084
2085 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2086 {
2087         struct vcpu_vmx *vmx = to_vmx(vcpu);
2088         int i;
2089
2090         if (vmx->host_state.loaded)
2091                 return;
2092
2093         vmx->host_state.loaded = 1;
2094         /*
2095          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2096          * allow segment selectors with cpl > 0 or ti == 1.
2097          */
2098         vmx->host_state.ldt_sel = kvm_read_ldt();
2099         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2100         savesegment(fs, vmx->host_state.fs_sel);
2101         if (!(vmx->host_state.fs_sel & 7)) {
2102                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2103                 vmx->host_state.fs_reload_needed = 0;
2104         } else {
2105                 vmcs_write16(HOST_FS_SELECTOR, 0);
2106                 vmx->host_state.fs_reload_needed = 1;
2107         }
2108         savesegment(gs, vmx->host_state.gs_sel);
2109         if (!(vmx->host_state.gs_sel & 7))
2110                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2111         else {
2112                 vmcs_write16(HOST_GS_SELECTOR, 0);
2113                 vmx->host_state.gs_ldt_reload_needed = 1;
2114         }
2115
2116 #ifdef CONFIG_X86_64
2117         savesegment(ds, vmx->host_state.ds_sel);
2118         savesegment(es, vmx->host_state.es_sel);
2119 #endif
2120
2121 #ifdef CONFIG_X86_64
2122         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2123         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2124 #else
2125         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2126         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2127 #endif
2128
2129 #ifdef CONFIG_X86_64
2130         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2131         if (is_long_mode(&vmx->vcpu))
2132                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2133 #endif
2134         if (boot_cpu_has(X86_FEATURE_MPX))
2135                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2136         for (i = 0; i < vmx->save_nmsrs; ++i)
2137                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2138                                    vmx->guest_msrs[i].data,
2139                                    vmx->guest_msrs[i].mask);
2140 }
2141
2142 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2143 {
2144         if (!vmx->host_state.loaded)
2145                 return;
2146
2147         ++vmx->vcpu.stat.host_state_reload;
2148         vmx->host_state.loaded = 0;
2149 #ifdef CONFIG_X86_64
2150         if (is_long_mode(&vmx->vcpu))
2151                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2152 #endif
2153         if (vmx->host_state.gs_ldt_reload_needed) {
2154                 kvm_load_ldt(vmx->host_state.ldt_sel);
2155 #ifdef CONFIG_X86_64
2156                 load_gs_index(vmx->host_state.gs_sel);
2157 #else
2158                 loadsegment(gs, vmx->host_state.gs_sel);
2159 #endif
2160         }
2161         if (vmx->host_state.fs_reload_needed)
2162                 loadsegment(fs, vmx->host_state.fs_sel);
2163 #ifdef CONFIG_X86_64
2164         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2165                 loadsegment(ds, vmx->host_state.ds_sel);
2166                 loadsegment(es, vmx->host_state.es_sel);
2167         }
2168 #endif
2169         invalidate_tss_limit();
2170 #ifdef CONFIG_X86_64
2171         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2172 #endif
2173         if (vmx->host_state.msr_host_bndcfgs)
2174                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2175         load_fixmap_gdt(raw_smp_processor_id());
2176 }
2177
2178 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2179 {
2180         preempt_disable();
2181         __vmx_load_host_state(vmx);
2182         preempt_enable();
2183 }
2184
2185 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2186 {
2187         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2188         struct pi_desc old, new;
2189         unsigned int dest;
2190
2191         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2192                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2193                 !kvm_vcpu_apicv_active(vcpu))
2194                 return;
2195
2196         do {
2197                 old.control = new.control = pi_desc->control;
2198
2199                 /*
2200                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2201                  * are two possible cases:
2202                  * 1. After running 'pre_block', context switch
2203                  *    happened. For this case, 'sn' was set in
2204                  *    vmx_vcpu_put(), so we need to clear it here.
2205                  * 2. After running 'pre_block', we were blocked,
2206                  *    and woken up by some other guy. For this case,
2207                  *    we don't need to do anything, 'pi_post_block'
2208                  *    will do everything for us. However, we cannot
2209                  *    check whether it is case #1 or case #2 here
2210                  *    (maybe, not needed), so we also clear sn here,
2211                  *    I think it is not a big deal.
2212                  */
2213                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2214                         if (vcpu->cpu != cpu) {
2215                                 dest = cpu_physical_id(cpu);
2216
2217                                 if (x2apic_enabled())
2218                                         new.ndst = dest;
2219                                 else
2220                                         new.ndst = (dest << 8) & 0xFF00;
2221                         }
2222
2223                         /* set 'NV' to 'notification vector' */
2224                         new.nv = POSTED_INTR_VECTOR;
2225                 }
2226
2227                 /* Allow posting non-urgent interrupts */
2228                 new.sn = 0;
2229         } while (cmpxchg(&pi_desc->control, old.control,
2230                         new.control) != old.control);
2231 }
2232
2233 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2234 {
2235         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2236         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2237 }
2238
2239 /*
2240  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2241  * vcpu mutex is already taken.
2242  */
2243 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2244 {
2245         struct vcpu_vmx *vmx = to_vmx(vcpu);
2246         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2247
2248         if (!already_loaded) {
2249                 loaded_vmcs_clear(vmx->loaded_vmcs);
2250                 local_irq_disable();
2251                 crash_disable_local_vmclear(cpu);
2252
2253                 /*
2254                  * Read loaded_vmcs->cpu should be before fetching
2255                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2256                  * See the comments in __loaded_vmcs_clear().
2257                  */
2258                 smp_rmb();
2259
2260                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2261                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2262                 crash_enable_local_vmclear(cpu);
2263                 local_irq_enable();
2264         }
2265
2266         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2267                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2268                 vmcs_load(vmx->loaded_vmcs->vmcs);
2269         }
2270
2271         if (!already_loaded) {
2272                 void *gdt = get_current_gdt_ro();
2273                 unsigned long sysenter_esp;
2274
2275                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2276
2277                 /*
2278                  * Linux uses per-cpu TSS and GDT, so set these when switching
2279                  * processors.  See 22.2.4.
2280                  */
2281                 vmcs_writel(HOST_TR_BASE,
2282                             (unsigned long)this_cpu_ptr(&cpu_tss));
2283                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2284
2285                 /*
2286                  * VM exits change the host TR limit to 0x67 after a VM
2287                  * exit.  This is okay, since 0x67 covers everything except
2288                  * the IO bitmap and have have code to handle the IO bitmap
2289                  * being lost after a VM exit.
2290                  */
2291                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2292
2293                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2294                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2295
2296                 vmx->loaded_vmcs->cpu = cpu;
2297         }
2298
2299         /* Setup TSC multiplier */
2300         if (kvm_has_tsc_control &&
2301             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2302                 decache_tsc_multiplier(vmx);
2303
2304         vmx_vcpu_pi_load(vcpu, cpu);
2305         vmx->host_pkru = read_pkru();
2306 }
2307
2308 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2309 {
2310         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2311
2312         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2313                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2314                 !kvm_vcpu_apicv_active(vcpu))
2315                 return;
2316
2317         /* Set SN when the vCPU is preempted */
2318         if (vcpu->preempted)
2319                 pi_set_sn(pi_desc);
2320 }
2321
2322 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2323 {
2324         vmx_vcpu_pi_put(vcpu);
2325
2326         __vmx_load_host_state(to_vmx(vcpu));
2327 }
2328
2329 static bool emulation_required(struct kvm_vcpu *vcpu)
2330 {
2331         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2332 }
2333
2334 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2335
2336 /*
2337  * Return the cr0 value that a nested guest would read. This is a combination
2338  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2339  * its hypervisor (cr0_read_shadow).
2340  */
2341 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2342 {
2343         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2344                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2345 }
2346 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2347 {
2348         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2349                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2350 }
2351
2352 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2353 {
2354         unsigned long rflags, save_rflags;
2355
2356         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2357                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2358                 rflags = vmcs_readl(GUEST_RFLAGS);
2359                 if (to_vmx(vcpu)->rmode.vm86_active) {
2360                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2361                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2362                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2363                 }
2364                 to_vmx(vcpu)->rflags = rflags;
2365         }
2366         return to_vmx(vcpu)->rflags;
2367 }
2368
2369 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2370 {
2371         unsigned long old_rflags = vmx_get_rflags(vcpu);
2372
2373         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2374         to_vmx(vcpu)->rflags = rflags;
2375         if (to_vmx(vcpu)->rmode.vm86_active) {
2376                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2377                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2378         }
2379         vmcs_writel(GUEST_RFLAGS, rflags);
2380
2381         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2382                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2383 }
2384
2385 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2386 {
2387         return to_vmx(vcpu)->guest_pkru;
2388 }
2389
2390 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2391 {
2392         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2393         int ret = 0;
2394
2395         if (interruptibility & GUEST_INTR_STATE_STI)
2396                 ret |= KVM_X86_SHADOW_INT_STI;
2397         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2398                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2399
2400         return ret;
2401 }
2402
2403 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2404 {
2405         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2406         u32 interruptibility = interruptibility_old;
2407
2408         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2409
2410         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2411                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2412         else if (mask & KVM_X86_SHADOW_INT_STI)
2413                 interruptibility |= GUEST_INTR_STATE_STI;
2414
2415         if ((interruptibility != interruptibility_old))
2416                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2417 }
2418
2419 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2420 {
2421         unsigned long rip;
2422
2423         rip = kvm_rip_read(vcpu);
2424         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2425         kvm_rip_write(vcpu, rip);
2426
2427         /* skipping an emulated instruction also counts */
2428         vmx_set_interrupt_shadow(vcpu, 0);
2429 }
2430
2431 /*
2432  * KVM wants to inject page-faults which it got to the guest. This function
2433  * checks whether in a nested guest, we need to inject them to L1 or L2.
2434  */
2435 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu)
2436 {
2437         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2438         unsigned int nr = vcpu->arch.exception.nr;
2439
2440         if (!((vmcs12->exception_bitmap & (1u << nr)) ||
2441                 (nr == PF_VECTOR && vcpu->arch.exception.nested_apf)))
2442                 return 0;
2443
2444         if (vcpu->arch.exception.nested_apf) {
2445                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2446                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
2447                         PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
2448                         INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
2449                         vcpu->arch.apf.nested_apf_token);
2450                 return 1;
2451         }
2452
2453         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2454         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
2455                           vmcs_read32(VM_EXIT_INTR_INFO),
2456                           vmcs_readl(EXIT_QUALIFICATION));
2457         return 1;
2458 }
2459
2460 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2461 {
2462         struct vcpu_vmx *vmx = to_vmx(vcpu);
2463         unsigned nr = vcpu->arch.exception.nr;
2464         bool has_error_code = vcpu->arch.exception.has_error_code;
2465         bool reinject = vcpu->arch.exception.reinject;
2466         u32 error_code = vcpu->arch.exception.error_code;
2467         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2468
2469         if (!reinject && is_guest_mode(vcpu) &&
2470             nested_vmx_check_exception(vcpu))
2471                 return;
2472
2473         if (has_error_code) {
2474                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2475                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2476         }
2477
2478         if (vmx->rmode.vm86_active) {
2479                 int inc_eip = 0;
2480                 if (kvm_exception_is_soft(nr))
2481                         inc_eip = vcpu->arch.event_exit_inst_len;
2482                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2483                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2484                 return;
2485         }
2486
2487         if (kvm_exception_is_soft(nr)) {
2488                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2489                              vmx->vcpu.arch.event_exit_inst_len);
2490                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2491         } else
2492                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2493
2494         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2495 }
2496
2497 static bool vmx_rdtscp_supported(void)
2498 {
2499         return cpu_has_vmx_rdtscp();
2500 }
2501
2502 static bool vmx_invpcid_supported(void)
2503 {
2504         return cpu_has_vmx_invpcid() && enable_ept;
2505 }
2506
2507 /*
2508  * Swap MSR entry in host/guest MSR entry array.
2509  */
2510 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2511 {
2512         struct shared_msr_entry tmp;
2513
2514         tmp = vmx->guest_msrs[to];
2515         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2516         vmx->guest_msrs[from] = tmp;
2517 }
2518
2519 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2520 {
2521         unsigned long *msr_bitmap;
2522
2523         if (is_guest_mode(vcpu))
2524                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2525         else if (cpu_has_secondary_exec_ctrls() &&
2526                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2527                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2528                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2529                         if (is_long_mode(vcpu))
2530                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2531                         else
2532                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2533                 } else {
2534                         if (is_long_mode(vcpu))
2535                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2536                         else
2537                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2538                 }
2539         } else {
2540                 if (is_long_mode(vcpu))
2541                         msr_bitmap = vmx_msr_bitmap_longmode;
2542                 else
2543                         msr_bitmap = vmx_msr_bitmap_legacy;
2544         }
2545
2546         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2547 }
2548
2549 /*
2550  * Set up the vmcs to automatically save and restore system
2551  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2552  * mode, as fiddling with msrs is very expensive.
2553  */
2554 static void setup_msrs(struct vcpu_vmx *vmx)
2555 {
2556         int save_nmsrs, index;
2557
2558         save_nmsrs = 0;
2559 #ifdef CONFIG_X86_64
2560         if (is_long_mode(&vmx->vcpu)) {
2561                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2562                 if (index >= 0)
2563                         move_msr_up(vmx, index, save_nmsrs++);
2564                 index = __find_msr_index(vmx, MSR_LSTAR);
2565                 if (index >= 0)
2566                         move_msr_up(vmx, index, save_nmsrs++);
2567                 index = __find_msr_index(vmx, MSR_CSTAR);
2568                 if (index >= 0)
2569                         move_msr_up(vmx, index, save_nmsrs++);
2570                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2571                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2572                         move_msr_up(vmx, index, save_nmsrs++);
2573                 /*
2574                  * MSR_STAR is only needed on long mode guests, and only
2575                  * if efer.sce is enabled.
2576                  */
2577                 index = __find_msr_index(vmx, MSR_STAR);
2578                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2579                         move_msr_up(vmx, index, save_nmsrs++);
2580         }
2581 #endif
2582         index = __find_msr_index(vmx, MSR_EFER);
2583         if (index >= 0 && update_transition_efer(vmx, index))
2584                 move_msr_up(vmx, index, save_nmsrs++);
2585
2586         vmx->save_nmsrs = save_nmsrs;
2587
2588         if (cpu_has_vmx_msr_bitmap())
2589                 vmx_set_msr_bitmap(&vmx->vcpu);
2590 }
2591
2592 /*
2593  * reads and returns guest's timestamp counter "register"
2594  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2595  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2596  */
2597 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2598 {
2599         u64 host_tsc, tsc_offset;
2600
2601         host_tsc = rdtsc();
2602         tsc_offset = vmcs_read64(TSC_OFFSET);
2603         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2604 }
2605
2606 /*
2607  * writes 'offset' into guest's timestamp counter offset register
2608  */
2609 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2610 {
2611         if (is_guest_mode(vcpu)) {
2612                 /*
2613                  * We're here if L1 chose not to trap WRMSR to TSC. According
2614                  * to the spec, this should set L1's TSC; The offset that L1
2615                  * set for L2 remains unchanged, and still needs to be added
2616                  * to the newly set TSC to get L2's TSC.
2617                  */
2618                 struct vmcs12 *vmcs12;
2619                 /* recalculate vmcs02.TSC_OFFSET: */
2620                 vmcs12 = get_vmcs12(vcpu);
2621                 vmcs_write64(TSC_OFFSET, offset +
2622                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2623                          vmcs12->tsc_offset : 0));
2624         } else {
2625                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2626                                            vmcs_read64(TSC_OFFSET), offset);
2627                 vmcs_write64(TSC_OFFSET, offset);
2628         }
2629 }
2630
2631 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2632 {
2633         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2634         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2635 }
2636
2637 /*
2638  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2639  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2640  * all guests if the "nested" module option is off, and can also be disabled
2641  * for a single guest by disabling its VMX cpuid bit.
2642  */
2643 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2644 {
2645         return nested && guest_cpuid_has_vmx(vcpu);
2646 }
2647
2648 /*
2649  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2650  * returned for the various VMX controls MSRs when nested VMX is enabled.
2651  * The same values should also be used to verify that vmcs12 control fields are
2652  * valid during nested entry from L1 to L2.
2653  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2654  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2655  * bit in the high half is on if the corresponding bit in the control field
2656  * may be on. See also vmx_control_verify().
2657  */
2658 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2659 {
2660         /*
2661          * Note that as a general rule, the high half of the MSRs (bits in
2662          * the control fields which may be 1) should be initialized by the
2663          * intersection of the underlying hardware's MSR (i.e., features which
2664          * can be supported) and the list of features we want to expose -
2665          * because they are known to be properly supported in our code.
2666          * Also, usually, the low half of the MSRs (bits which must be 1) can
2667          * be set to 0, meaning that L1 may turn off any of these bits. The
2668          * reason is that if one of these bits is necessary, it will appear
2669          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2670          * fields of vmcs01 and vmcs02, will turn these bits off - and
2671          * nested_vmx_exit_reflected() will not pass related exits to L1.
2672          * These rules have exceptions below.
2673          */
2674
2675         /* pin-based controls */
2676         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2677                 vmx->nested.nested_vmx_pinbased_ctls_low,
2678                 vmx->nested.nested_vmx_pinbased_ctls_high);
2679         vmx->nested.nested_vmx_pinbased_ctls_low |=
2680                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2681         vmx->nested.nested_vmx_pinbased_ctls_high &=
2682                 PIN_BASED_EXT_INTR_MASK |
2683                 PIN_BASED_NMI_EXITING |
2684                 PIN_BASED_VIRTUAL_NMIS;
2685         vmx->nested.nested_vmx_pinbased_ctls_high |=
2686                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2687                 PIN_BASED_VMX_PREEMPTION_TIMER;
2688         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2689                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2690                         PIN_BASED_POSTED_INTR;
2691
2692         /* exit controls */
2693         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2694                 vmx->nested.nested_vmx_exit_ctls_low,
2695                 vmx->nested.nested_vmx_exit_ctls_high);
2696         vmx->nested.nested_vmx_exit_ctls_low =
2697                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2698
2699         vmx->nested.nested_vmx_exit_ctls_high &=
2700 #ifdef CONFIG_X86_64
2701                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2702 #endif
2703                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2704         vmx->nested.nested_vmx_exit_ctls_high |=
2705                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2706                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2707                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2708
2709         if (kvm_mpx_supported())
2710                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2711
2712         /* We support free control of debug control saving. */
2713         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2714
2715         /* entry controls */
2716         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2717                 vmx->nested.nested_vmx_entry_ctls_low,
2718                 vmx->nested.nested_vmx_entry_ctls_high);
2719         vmx->nested.nested_vmx_entry_ctls_low =
2720                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2721         vmx->nested.nested_vmx_entry_ctls_high &=
2722 #ifdef CONFIG_X86_64
2723                 VM_ENTRY_IA32E_MODE |
2724 #endif
2725                 VM_ENTRY_LOAD_IA32_PAT;
2726         vmx->nested.nested_vmx_entry_ctls_high |=
2727                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2728         if (kvm_mpx_supported())
2729                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2730
2731         /* We support free control of debug control loading. */
2732         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2733
2734         /* cpu-based controls */
2735         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2736                 vmx->nested.nested_vmx_procbased_ctls_low,
2737                 vmx->nested.nested_vmx_procbased_ctls_high);
2738         vmx->nested.nested_vmx_procbased_ctls_low =
2739                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2740         vmx->nested.nested_vmx_procbased_ctls_high &=
2741                 CPU_BASED_VIRTUAL_INTR_PENDING |
2742                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2743                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2744                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2745                 CPU_BASED_CR3_STORE_EXITING |
2746 #ifdef CONFIG_X86_64
2747                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2748 #endif
2749                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2750                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2751                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2752                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2753                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2754         /*
2755          * We can allow some features even when not supported by the
2756          * hardware. For example, L1 can specify an MSR bitmap - and we
2757          * can use it to avoid exits to L1 - even when L0 runs L2
2758          * without MSR bitmaps.
2759          */
2760         vmx->nested.nested_vmx_procbased_ctls_high |=
2761                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2762                 CPU_BASED_USE_MSR_BITMAPS;
2763
2764         /* We support free control of CR3 access interception. */
2765         vmx->nested.nested_vmx_procbased_ctls_low &=
2766                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2767
2768         /* secondary cpu-based controls */
2769         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2770                 vmx->nested.nested_vmx_secondary_ctls_low,
2771                 vmx->nested.nested_vmx_secondary_ctls_high);
2772         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2773         vmx->nested.nested_vmx_secondary_ctls_high &=
2774                 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
2775                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2776                 SECONDARY_EXEC_RDTSCP |
2777                 SECONDARY_EXEC_DESC |
2778                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2779                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2780                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2781                 SECONDARY_EXEC_WBINVD_EXITING |
2782                 SECONDARY_EXEC_XSAVES;
2783
2784         if (enable_ept) {
2785                 /* nested EPT: emulate EPT also to L1 */
2786                 vmx->nested.nested_vmx_secondary_ctls_high |=
2787                         SECONDARY_EXEC_ENABLE_EPT;
2788                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2789                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2790                 if (cpu_has_vmx_ept_execute_only())
2791                         vmx->nested.nested_vmx_ept_caps |=
2792                                 VMX_EPT_EXECUTE_ONLY_BIT;
2793                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2794                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2795                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2796                         VMX_EPT_1GB_PAGE_BIT;
2797                 if (enable_ept_ad_bits) {
2798                         vmx->nested.nested_vmx_secondary_ctls_high |=
2799                                 SECONDARY_EXEC_ENABLE_PML;
2800                         vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2801                 }
2802         } else
2803                 vmx->nested.nested_vmx_ept_caps = 0;
2804
2805         /*
2806          * Old versions of KVM use the single-context version without
2807          * checking for support, so declare that it is supported even
2808          * though it is treated as global context.  The alternative is
2809          * not failing the single-context invvpid, and it is worse.
2810          */
2811         if (enable_vpid) {
2812                 vmx->nested.nested_vmx_secondary_ctls_high |=
2813                         SECONDARY_EXEC_ENABLE_VPID;
2814                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2815                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2816         } else
2817                 vmx->nested.nested_vmx_vpid_caps = 0;
2818
2819         if (enable_unrestricted_guest)
2820                 vmx->nested.nested_vmx_secondary_ctls_high |=
2821                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2822
2823         /* miscellaneous data */
2824         rdmsr(MSR_IA32_VMX_MISC,
2825                 vmx->nested.nested_vmx_misc_low,
2826                 vmx->nested.nested_vmx_misc_high);
2827         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2828         vmx->nested.nested_vmx_misc_low |=
2829                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2830                 VMX_MISC_ACTIVITY_HLT;
2831         vmx->nested.nested_vmx_misc_high = 0;
2832
2833         /*
2834          * This MSR reports some information about VMX support. We
2835          * should return information about the VMX we emulate for the
2836          * guest, and the VMCS structure we give it - not about the
2837          * VMX support of the underlying hardware.
2838          */
2839         vmx->nested.nested_vmx_basic =
2840                 VMCS12_REVISION |
2841                 VMX_BASIC_TRUE_CTLS |
2842                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2843                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2844
2845         if (cpu_has_vmx_basic_inout())
2846                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2847
2848         /*
2849          * These MSRs specify bits which the guest must keep fixed on
2850          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2851          * We picked the standard core2 setting.
2852          */
2853 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2854 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2855         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2856         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2857
2858         /* These MSRs specify bits which the guest must keep fixed off. */
2859         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2860         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2861
2862         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2863         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2864 }
2865
2866 /*
2867  * if fixed0[i] == 1: val[i] must be 1
2868  * if fixed1[i] == 0: val[i] must be 0
2869  */
2870 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2871 {
2872         return ((val & fixed1) | fixed0) == val;
2873 }
2874
2875 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2876 {
2877         return fixed_bits_valid(control, low, high);
2878 }
2879
2880 static inline u64 vmx_control_msr(u32 low, u32 high)
2881 {
2882         return low | ((u64)high << 32);
2883 }
2884
2885 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2886 {
2887         superset &= mask;
2888         subset &= mask;
2889
2890         return (superset | subset) == superset;
2891 }
2892
2893 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2894 {
2895         const u64 feature_and_reserved =
2896                 /* feature (except bit 48; see below) */
2897                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2898                 /* reserved */
2899                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2900         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2901
2902         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2903                 return -EINVAL;
2904
2905         /*
2906          * KVM does not emulate a version of VMX that constrains physical
2907          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2908          */
2909         if (data & BIT_ULL(48))
2910                 return -EINVAL;
2911
2912         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2913             vmx_basic_vmcs_revision_id(data))
2914                 return -EINVAL;
2915
2916         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2917                 return -EINVAL;
2918
2919         vmx->nested.nested_vmx_basic = data;
2920         return 0;
2921 }
2922
2923 static int
2924 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2925 {
2926         u64 supported;
2927         u32 *lowp, *highp;
2928
2929         switch (msr_index) {
2930         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2931                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2932                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2933                 break;
2934         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2935                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2936                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2937                 break;
2938         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2939                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2940                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2941                 break;
2942         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2943                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2944                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2945                 break;
2946         case MSR_IA32_VMX_PROCBASED_CTLS2:
2947                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2948                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2949                 break;
2950         default:
2951                 BUG();
2952         }
2953
2954         supported = vmx_control_msr(*lowp, *highp);
2955
2956         /* Check must-be-1 bits are still 1. */
2957         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2958                 return -EINVAL;
2959
2960         /* Check must-be-0 bits are still 0. */
2961         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2962                 return -EINVAL;
2963
2964         *lowp = data;
2965         *highp = data >> 32;
2966         return 0;
2967 }
2968
2969 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2970 {
2971         const u64 feature_and_reserved_bits =
2972                 /* feature */
2973                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2974                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2975                 /* reserved */
2976                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2977         u64 vmx_misc;
2978
2979         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2980                                    vmx->nested.nested_vmx_misc_high);
2981
2982         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2983                 return -EINVAL;
2984
2985         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2986              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2987             vmx_misc_preemption_timer_rate(data) !=
2988             vmx_misc_preemption_timer_rate(vmx_misc))
2989                 return -EINVAL;
2990
2991         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2992                 return -EINVAL;
2993
2994         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2995                 return -EINVAL;
2996
2997         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2998                 return -EINVAL;
2999
3000         vmx->nested.nested_vmx_misc_low = data;
3001         vmx->nested.nested_vmx_misc_high = data >> 32;
3002         return 0;
3003 }
3004
3005 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3006 {
3007         u64 vmx_ept_vpid_cap;
3008
3009         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3010                                            vmx->nested.nested_vmx_vpid_caps);
3011
3012         /* Every bit is either reserved or a feature bit. */
3013         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3014                 return -EINVAL;
3015
3016         vmx->nested.nested_vmx_ept_caps = data;
3017         vmx->nested.nested_vmx_vpid_caps = data >> 32;
3018         return 0;
3019 }
3020
3021 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3022 {
3023         u64 *msr;
3024
3025         switch (msr_index) {
3026         case MSR_IA32_VMX_CR0_FIXED0:
3027                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3028                 break;
3029         case MSR_IA32_VMX_CR4_FIXED0:
3030                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3031                 break;
3032         default:
3033                 BUG();
3034         }
3035
3036         /*
3037          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3038          * must be 1 in the restored value.
3039          */
3040         if (!is_bitwise_subset(data, *msr, -1ULL))
3041                 return -EINVAL;
3042
3043         *msr = data;
3044         return 0;
3045 }
3046
3047 /*
3048  * Called when userspace is restoring VMX MSRs.
3049  *
3050  * Returns 0 on success, non-0 otherwise.
3051  */
3052 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3053 {
3054         struct vcpu_vmx *vmx = to_vmx(vcpu);
3055
3056         switch (msr_index) {
3057         case MSR_IA32_VMX_BASIC:
3058                 return vmx_restore_vmx_basic(vmx, data);
3059         case MSR_IA32_VMX_PINBASED_CTLS:
3060         case MSR_IA32_VMX_PROCBASED_CTLS:
3061         case MSR_IA32_VMX_EXIT_CTLS:
3062         case MSR_IA32_VMX_ENTRY_CTLS:
3063                 /*
3064                  * The "non-true" VMX capability MSRs are generated from the
3065                  * "true" MSRs, so we do not support restoring them directly.
3066                  *
3067                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3068                  * should restore the "true" MSRs with the must-be-1 bits
3069                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3070                  * DEFAULT SETTINGS".
3071                  */
3072                 return -EINVAL;
3073         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3074         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3075         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3076         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3077         case MSR_IA32_VMX_PROCBASED_CTLS2:
3078                 return vmx_restore_control_msr(vmx, msr_index, data);
3079         case MSR_IA32_VMX_MISC:
3080                 return vmx_restore_vmx_misc(vmx, data);
3081         case MSR_IA32_VMX_CR0_FIXED0:
3082         case MSR_IA32_VMX_CR4_FIXED0:
3083                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3084         case MSR_IA32_VMX_CR0_FIXED1:
3085         case MSR_IA32_VMX_CR4_FIXED1:
3086                 /*
3087                  * These MSRs are generated based on the vCPU's CPUID, so we
3088                  * do not support restoring them directly.
3089                  */
3090                 return -EINVAL;
3091         case MSR_IA32_VMX_EPT_VPID_CAP:
3092                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3093         case MSR_IA32_VMX_VMCS_ENUM:
3094                 vmx->nested.nested_vmx_vmcs_enum = data;
3095                 return 0;
3096         default:
3097                 /*
3098                  * The rest of the VMX capability MSRs do not support restore.
3099                  */
3100                 return -EINVAL;
3101         }
3102 }
3103
3104 /* Returns 0 on success, non-0 otherwise. */
3105 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3106 {
3107         struct vcpu_vmx *vmx = to_vmx(vcpu);
3108
3109         switch (msr_index) {
3110         case MSR_IA32_VMX_BASIC:
3111                 *pdata = vmx->nested.nested_vmx_basic;
3112                 break;
3113         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3114         case MSR_IA32_VMX_PINBASED_CTLS:
3115                 *pdata = vmx_control_msr(
3116                         vmx->nested.nested_vmx_pinbased_ctls_low,
3117                         vmx->nested.nested_vmx_pinbased_ctls_high);
3118                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3119                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3120                 break;
3121         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3122         case MSR_IA32_VMX_PROCBASED_CTLS:
3123                 *pdata = vmx_control_msr(
3124                         vmx->nested.nested_vmx_procbased_ctls_low,
3125                         vmx->nested.nested_vmx_procbased_ctls_high);
3126                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3127                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3128                 break;
3129         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3130         case MSR_IA32_VMX_EXIT_CTLS:
3131                 *pdata = vmx_control_msr(
3132                         vmx->nested.nested_vmx_exit_ctls_low,
3133                         vmx->nested.nested_vmx_exit_ctls_high);
3134                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3135                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3136                 break;
3137         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3138         case MSR_IA32_VMX_ENTRY_CTLS:
3139                 *pdata = vmx_control_msr(
3140                         vmx->nested.nested_vmx_entry_ctls_low,
3141                         vmx->nested.nested_vmx_entry_ctls_high);
3142                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3143                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3144                 break;
3145         case MSR_IA32_VMX_MISC:
3146                 *pdata = vmx_control_msr(
3147                         vmx->nested.nested_vmx_misc_low,
3148                         vmx->nested.nested_vmx_misc_high);
3149                 break;
3150         case MSR_IA32_VMX_CR0_FIXED0:
3151                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3152                 break;
3153         case MSR_IA32_VMX_CR0_FIXED1:
3154                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3155                 break;
3156         case MSR_IA32_VMX_CR4_FIXED0:
3157                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3158                 break;
3159         case MSR_IA32_VMX_CR4_FIXED1:
3160                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3161                 break;
3162         case MSR_IA32_VMX_VMCS_ENUM:
3163                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3164                 break;
3165         case MSR_IA32_VMX_PROCBASED_CTLS2:
3166                 *pdata = vmx_control_msr(
3167                         vmx->nested.nested_vmx_secondary_ctls_low,
3168                         vmx->nested.nested_vmx_secondary_ctls_high);
3169                 break;
3170         case MSR_IA32_VMX_EPT_VPID_CAP:
3171                 *pdata = vmx->nested.nested_vmx_ept_caps |
3172                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3173                 break;
3174         default:
3175                 return 1;
3176         }
3177
3178         return 0;
3179 }
3180
3181 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3182                                                  uint64_t val)
3183 {
3184         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3185
3186         return !(val & ~valid_bits);
3187 }
3188
3189 /*
3190  * Reads an msr value (of 'msr_index') into 'pdata'.
3191  * Returns 0 on success, non-0 otherwise.
3192  * Assumes vcpu_load() was already called.
3193  */
3194 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3195 {
3196         struct shared_msr_entry *msr;
3197
3198         switch (msr_info->index) {
3199 #ifdef CONFIG_X86_64
3200         case MSR_FS_BASE:
3201                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3202                 break;
3203         case MSR_GS_BASE:
3204                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3205                 break;
3206         case MSR_KERNEL_GS_BASE:
3207                 vmx_load_host_state(to_vmx(vcpu));
3208                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3209                 break;
3210 #endif
3211         case MSR_EFER:
3212                 return kvm_get_msr_common(vcpu, msr_info);
3213         case MSR_IA32_TSC:
3214                 msr_info->data = guest_read_tsc(vcpu);
3215                 break;
3216         case MSR_IA32_SYSENTER_CS:
3217                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3218                 break;
3219         case MSR_IA32_SYSENTER_EIP:
3220                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3221                 break;
3222         case MSR_IA32_SYSENTER_ESP:
3223                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3224                 break;
3225         case MSR_IA32_BNDCFGS:
3226                 if (!kvm_mpx_supported() ||
3227                     (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3228                         return 1;
3229                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3230                 break;
3231         case MSR_IA32_MCG_EXT_CTL:
3232                 if (!msr_info->host_initiated &&
3233                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3234                       FEATURE_CONTROL_LMCE))
3235                         return 1;
3236                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3237                 break;
3238         case MSR_IA32_FEATURE_CONTROL:
3239                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3240                 break;
3241         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3242                 if (!nested_vmx_allowed(vcpu))
3243                         return 1;
3244                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3245         case MSR_IA32_XSS:
3246                 if (!vmx_xsaves_supported())
3247                         return 1;
3248                 msr_info->data = vcpu->arch.ia32_xss;
3249                 break;
3250         case MSR_TSC_AUX:
3251                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3252                         return 1;
3253                 /* Otherwise falls through */
3254         default:
3255                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3256                 if (msr) {
3257                         msr_info->data = msr->data;
3258                         break;
3259                 }
3260                 return kvm_get_msr_common(vcpu, msr_info);
3261         }
3262
3263         return 0;
3264 }
3265
3266 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3267
3268 /*
3269  * Writes msr value into into the appropriate "register".
3270  * Returns 0 on success, non-0 otherwise.
3271  * Assumes vcpu_load() was already called.
3272  */
3273 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3274 {
3275         struct vcpu_vmx *vmx = to_vmx(vcpu);
3276         struct shared_msr_entry *msr;
3277         int ret = 0;
3278         u32 msr_index = msr_info->index;
3279         u64 data = msr_info->data;
3280
3281         switch (msr_index) {
3282         case MSR_EFER:
3283                 ret = kvm_set_msr_common(vcpu, msr_info);
3284                 break;
3285 #ifdef CONFIG_X86_64
3286         case MSR_FS_BASE:
3287                 vmx_segment_cache_clear(vmx);
3288                 vmcs_writel(GUEST_FS_BASE, data);
3289                 break;
3290         case MSR_GS_BASE:
3291                 vmx_segment_cache_clear(vmx);
3292                 vmcs_writel(GUEST_GS_BASE, data);
3293                 break;
3294         case MSR_KERNEL_GS_BASE:
3295                 vmx_load_host_state(vmx);
3296                 vmx->msr_guest_kernel_gs_base = data;
3297                 break;
3298 #endif
3299         case MSR_IA32_SYSENTER_CS:
3300                 vmcs_write32(GUEST_SYSENTER_CS, data);
3301                 break;
3302         case MSR_IA32_SYSENTER_EIP:
3303                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3304                 break;
3305         case MSR_IA32_SYSENTER_ESP:
3306                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3307                 break;
3308         case MSR_IA32_BNDCFGS:
3309                 if (!kvm_mpx_supported() ||
3310                     (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3311                         return 1;
3312                 if (is_noncanonical_address(data & PAGE_MASK) ||
3313                     (data & MSR_IA32_BNDCFGS_RSVD))
3314                         return 1;
3315                 vmcs_write64(GUEST_BNDCFGS, data);
3316                 break;
3317         case MSR_IA32_TSC:
3318                 kvm_write_tsc(vcpu, msr_info);
3319                 break;
3320         case MSR_IA32_CR_PAT:
3321                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3322                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3323                                 return 1;
3324                         vmcs_write64(GUEST_IA32_PAT, data);
3325                         vcpu->arch.pat = data;
3326                         break;
3327                 }
3328                 ret = kvm_set_msr_common(vcpu, msr_info);
3329                 break;
3330         case MSR_IA32_TSC_ADJUST:
3331                 ret = kvm_set_msr_common(vcpu, msr_info);
3332                 break;
3333         case MSR_IA32_MCG_EXT_CTL:
3334                 if ((!msr_info->host_initiated &&
3335                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3336                        FEATURE_CONTROL_LMCE)) ||
3337                     (data & ~MCG_EXT_CTL_LMCE_EN))
3338                         return 1;
3339                 vcpu->arch.mcg_ext_ctl = data;
3340                 break;
3341         case MSR_IA32_FEATURE_CONTROL:
3342                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3343                     (to_vmx(vcpu)->msr_ia32_feature_control &
3344                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3345                         return 1;
3346                 vmx->msr_ia32_feature_control = data;
3347                 if (msr_info->host_initiated && data == 0)
3348                         vmx_leave_nested(vcpu);
3349                 break;
3350         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3351                 if (!msr_info->host_initiated)
3352                         return 1; /* they are read-only */
3353                 if (!nested_vmx_allowed(vcpu))
3354                         return 1;
3355                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3356         case MSR_IA32_XSS:
3357                 if (!vmx_xsaves_supported())
3358                         return 1;
3359                 /*
3360                  * The only supported bit as of Skylake is bit 8, but
3361                  * it is not supported on KVM.
3362                  */
3363                 if (data != 0)
3364                         return 1;
3365                 vcpu->arch.ia32_xss = data;
3366                 if (vcpu->arch.ia32_xss != host_xss)
3367                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3368                                 vcpu->arch.ia32_xss, host_xss);
3369                 else
3370                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3371                 break;
3372         case MSR_TSC_AUX:
3373                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3374                         return 1;
3375                 /* Check reserved bit, higher 32 bits should be zero */
3376                 if ((data >> 32) != 0)
3377                         return 1;
3378                 /* Otherwise falls through */
3379         default:
3380                 msr = find_msr_entry(vmx, msr_index);
3381                 if (msr) {
3382                         u64 old_msr_data = msr->data;
3383                         msr->data = data;
3384                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3385                                 preempt_disable();
3386                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3387                                                          msr->mask);
3388                                 preempt_enable();
3389                                 if (ret)
3390                                         msr->data = old_msr_data;
3391                         }
3392                         break;
3393                 }
3394                 ret = kvm_set_msr_common(vcpu, msr_info);
3395         }
3396
3397         return ret;
3398 }
3399
3400 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3401 {
3402         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3403         switch (reg) {
3404         case VCPU_REGS_RSP:
3405                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3406                 break;
3407         case VCPU_REGS_RIP:
3408                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3409                 break;
3410         case VCPU_EXREG_PDPTR:
3411                 if (enable_ept)
3412                         ept_save_pdptrs(vcpu);
3413                 break;
3414         default:
3415                 break;
3416         }
3417 }
3418
3419 static __init int cpu_has_kvm_support(void)
3420 {
3421         return cpu_has_vmx();
3422 }
3423
3424 static __init int vmx_disabled_by_bios(void)
3425 {
3426         u64 msr;
3427
3428         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3429         if (msr & FEATURE_CONTROL_LOCKED) {
3430                 /* launched w/ TXT and VMX disabled */
3431                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3432                         && tboot_enabled())
3433                         return 1;
3434                 /* launched w/o TXT and VMX only enabled w/ TXT */
3435                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3436                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3437                         && !tboot_enabled()) {
3438                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3439                                 "activate TXT before enabling KVM\n");
3440                         return 1;
3441                 }
3442                 /* launched w/o TXT and VMX disabled */
3443                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3444                         && !tboot_enabled())
3445                         return 1;
3446         }
3447
3448         return 0;
3449 }
3450
3451 static void kvm_cpu_vmxon(u64 addr)
3452 {
3453         cr4_set_bits(X86_CR4_VMXE);
3454         intel_pt_handle_vmx(1);
3455
3456         asm volatile (ASM_VMX_VMXON_RAX
3457                         : : "a"(&addr), "m"(addr)
3458                         : "memory", "cc");
3459 }
3460
3461 static int hardware_enable(void)
3462 {
3463         int cpu = raw_smp_processor_id();
3464         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3465         u64 old, test_bits;
3466
3467         if (cr4_read_shadow() & X86_CR4_VMXE)
3468                 return -EBUSY;
3469
3470         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3471         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3472         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3473
3474         /*
3475          * Now we can enable the vmclear operation in kdump
3476          * since the loaded_vmcss_on_cpu list on this cpu
3477          * has been initialized.
3478          *
3479          * Though the cpu is not in VMX operation now, there
3480          * is no problem to enable the vmclear operation
3481          * for the loaded_vmcss_on_cpu list is empty!
3482          */
3483         crash_enable_local_vmclear(cpu);
3484
3485         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3486
3487         test_bits = FEATURE_CONTROL_LOCKED;
3488         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3489         if (tboot_enabled())
3490                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3491
3492         if ((old & test_bits) != test_bits) {
3493                 /* enable and lock */
3494                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3495         }
3496         kvm_cpu_vmxon(phys_addr);
3497         ept_sync_global();
3498
3499         return 0;
3500 }
3501
3502 static void vmclear_local_loaded_vmcss(void)
3503 {
3504         int cpu = raw_smp_processor_id();
3505         struct loaded_vmcs *v, *n;
3506
3507         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3508                                  loaded_vmcss_on_cpu_link)
3509                 __loaded_vmcs_clear(v);
3510 }
3511
3512
3513 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3514  * tricks.
3515  */
3516 static void kvm_cpu_vmxoff(void)
3517 {
3518         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3519
3520         intel_pt_handle_vmx(0);
3521         cr4_clear_bits(X86_CR4_VMXE);
3522 }
3523
3524 static void hardware_disable(void)
3525 {
3526         vmclear_local_loaded_vmcss();
3527         kvm_cpu_vmxoff();
3528 }
3529
3530 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3531                                       u32 msr, u32 *result)
3532 {
3533         u32 vmx_msr_low, vmx_msr_high;
3534         u32 ctl = ctl_min | ctl_opt;
3535
3536         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3537
3538         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3539         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3540
3541         /* Ensure minimum (required) set of control bits are supported. */
3542         if (ctl_min & ~ctl)
3543                 return -EIO;
3544
3545         *result = ctl;
3546         return 0;
3547 }
3548
3549 static __init bool allow_1_setting(u32 msr, u32 ctl)
3550 {
3551         u32 vmx_msr_low, vmx_msr_high;
3552
3553         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3554         return vmx_msr_high & ctl;
3555 }
3556
3557 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3558 {
3559         u32 vmx_msr_low, vmx_msr_high;
3560         u32 min, opt, min2, opt2;
3561         u32 _pin_based_exec_control = 0;
3562         u32 _cpu_based_exec_control = 0;
3563         u32 _cpu_based_2nd_exec_control = 0;
3564         u32 _vmexit_control = 0;
3565         u32 _vmentry_control = 0;
3566
3567         min = CPU_BASED_HLT_EXITING |
3568 #ifdef CONFIG_X86_64
3569               CPU_BASED_CR8_LOAD_EXITING |
3570               CPU_BASED_CR8_STORE_EXITING |
3571 #endif
3572               CPU_BASED_CR3_LOAD_EXITING |
3573               CPU_BASED_CR3_STORE_EXITING |
3574               CPU_BASED_USE_IO_BITMAPS |
3575               CPU_BASED_MOV_DR_EXITING |
3576               CPU_BASED_USE_TSC_OFFSETING |
3577               CPU_BASED_INVLPG_EXITING |
3578               CPU_BASED_RDPMC_EXITING;
3579
3580         if (!kvm_mwait_in_guest())
3581                 min |= CPU_BASED_MWAIT_EXITING |
3582                         CPU_BASED_MONITOR_EXITING;
3583
3584         opt = CPU_BASED_TPR_SHADOW |
3585               CPU_BASED_USE_MSR_BITMAPS |
3586               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3587         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3588                                 &_cpu_based_exec_control) < 0)
3589                 return -EIO;
3590 #ifdef CONFIG_X86_64
3591         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3592                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3593                                            ~CPU_BASED_CR8_STORE_EXITING;
3594 #endif
3595         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3596                 min2 = 0;
3597                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3598                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3599                         SECONDARY_EXEC_WBINVD_EXITING |
3600                         SECONDARY_EXEC_ENABLE_VPID |
3601                         SECONDARY_EXEC_ENABLE_EPT |
3602                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3603                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3604                         SECONDARY_EXEC_RDTSCP |
3605                         SECONDARY_EXEC_ENABLE_INVPCID |
3606                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3607                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3608                         SECONDARY_EXEC_SHADOW_VMCS |
3609                         SECONDARY_EXEC_XSAVES |
3610                         SECONDARY_EXEC_ENABLE_PML |
3611                         SECONDARY_EXEC_TSC_SCALING;
3612                 if (adjust_vmx_controls(min2, opt2,
3613                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3614                                         &_cpu_based_2nd_exec_control) < 0)
3615                         return -EIO;
3616         }
3617 #ifndef CONFIG_X86_64
3618         if (!(_cpu_based_2nd_exec_control &
3619                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3620                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3621 #endif
3622
3623         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3624                 _cpu_based_2nd_exec_control &= ~(
3625                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3626                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3627                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3628
3629         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3630                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3631                    enabled */
3632                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3633                                              CPU_BASED_CR3_STORE_EXITING |
3634                                              CPU_BASED_INVLPG_EXITING);
3635                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3636                       vmx_capability.ept, vmx_capability.vpid);
3637         }
3638
3639         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3640 #ifdef CONFIG_X86_64
3641         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3642 #endif
3643         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3644                 VM_EXIT_CLEAR_BNDCFGS;
3645         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3646                                 &_vmexit_control) < 0)
3647                 return -EIO;
3648
3649         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3650                 PIN_BASED_VIRTUAL_NMIS;
3651         opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3652         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3653                                 &_pin_based_exec_control) < 0)
3654                 return -EIO;
3655
3656         if (cpu_has_broken_vmx_preemption_timer())
3657                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3658         if (!(_cpu_based_2nd_exec_control &
3659                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3660                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3661
3662         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3663         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3664         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3665                                 &_vmentry_control) < 0)
3666                 return -EIO;
3667
3668         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3669
3670         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3671         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3672                 return -EIO;
3673
3674 #ifdef CONFIG_X86_64
3675         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3676         if (vmx_msr_high & (1u<<16))
3677                 return -EIO;
3678 #endif
3679
3680         /* Require Write-Back (WB) memory type for VMCS accesses. */
3681         if (((vmx_msr_high >> 18) & 15) != 6)
3682                 return -EIO;
3683
3684         vmcs_conf->size = vmx_msr_high & 0x1fff;
3685         vmcs_conf->order = get_order(vmcs_conf->size);
3686         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3687         vmcs_conf->revision_id = vmx_msr_low;
3688
3689         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3690         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3691         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3692         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3693         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3694
3695         cpu_has_load_ia32_efer =
3696                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3697                                 VM_ENTRY_LOAD_IA32_EFER)
3698                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3699                                    VM_EXIT_LOAD_IA32_EFER);
3700
3701         cpu_has_load_perf_global_ctrl =
3702                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3703                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3704                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3705                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3706
3707         /*
3708          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3709          * but due to errata below it can't be used. Workaround is to use
3710          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3711          *
3712          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3713          *
3714          * AAK155             (model 26)
3715          * AAP115             (model 30)
3716          * AAT100             (model 37)
3717          * BC86,AAY89,BD102   (model 44)
3718          * BA97               (model 46)
3719          *
3720          */
3721         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3722                 switch (boot_cpu_data.x86_model) {
3723                 case 26:
3724                 case 30:
3725                 case 37:
3726                 case 44:
3727                 case 46:
3728                         cpu_has_load_perf_global_ctrl = false;
3729                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3730                                         "does not work properly. Using workaround\n");
3731                         break;
3732                 default:
3733                         break;
3734                 }
3735         }
3736
3737         if (boot_cpu_has(X86_FEATURE_XSAVES))
3738                 rdmsrl(MSR_IA32_XSS, host_xss);
3739
3740         return 0;
3741 }
3742
3743 static struct vmcs *alloc_vmcs_cpu(int cpu)
3744 {
3745         int node = cpu_to_node(cpu);
3746         struct page *pages;
3747         struct vmcs *vmcs;
3748
3749         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3750         if (!pages)
3751                 return NULL;
3752         vmcs = page_address(pages);
3753         memset(vmcs, 0, vmcs_config.size);
3754         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3755         return vmcs;
3756 }
3757
3758 static struct vmcs *alloc_vmcs(void)
3759 {
3760         return alloc_vmcs_cpu(raw_smp_processor_id());
3761 }
3762
3763 static void free_vmcs(struct vmcs *vmcs)
3764 {
3765         free_pages((unsigned long)vmcs, vmcs_config.order);
3766 }
3767
3768 /*
3769  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3770  */
3771 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3772 {
3773         if (!loaded_vmcs->vmcs)
3774                 return;
3775         loaded_vmcs_clear(loaded_vmcs);
3776         free_vmcs(loaded_vmcs->vmcs);
3777         loaded_vmcs->vmcs = NULL;
3778         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3779 }
3780
3781 static void free_kvm_area(void)
3782 {
3783         int cpu;
3784
3785         for_each_possible_cpu(cpu) {
3786                 free_vmcs(per_cpu(vmxarea, cpu));
3787                 per_cpu(vmxarea, cpu) = NULL;
3788         }
3789 }
3790
3791 enum vmcs_field_type {
3792         VMCS_FIELD_TYPE_U16 = 0,
3793         VMCS_FIELD_TYPE_U64 = 1,
3794         VMCS_FIELD_TYPE_U32 = 2,
3795         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3796 };
3797
3798 static inline int vmcs_field_type(unsigned long field)
3799 {
3800         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
3801                 return VMCS_FIELD_TYPE_U32;
3802         return (field >> 13) & 0x3 ;
3803 }
3804
3805 static inline int vmcs_field_readonly(unsigned long field)
3806 {
3807         return (((field >> 10) & 0x3) == 1);
3808 }
3809
3810 static void init_vmcs_shadow_fields(void)
3811 {
3812         int i, j;
3813
3814         /* No checks for read only fields yet */
3815
3816         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3817                 switch (shadow_read_write_fields[i]) {
3818                 case GUEST_BNDCFGS:
3819                         if (!kvm_mpx_supported())
3820                                 continue;
3821                         break;
3822                 default:
3823                         break;
3824                 }
3825
3826                 if (j < i)
3827                         shadow_read_write_fields[j] =
3828                                 shadow_read_write_fields[i];
3829                 j++;
3830         }
3831         max_shadow_read_write_fields = j;
3832
3833         /* shadowed fields guest access without vmexit */
3834         for (i = 0; i < max_shadow_read_write_fields; i++) {
3835                 unsigned long field = shadow_read_write_fields[i];
3836
3837                 clear_bit(field, vmx_vmwrite_bitmap);
3838                 clear_bit(field, vmx_vmread_bitmap);
3839                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3840                         clear_bit(field + 1, vmx_vmwrite_bitmap);
3841                         clear_bit(field + 1, vmx_vmread_bitmap);
3842                 }
3843         }
3844         for (i = 0; i < max_shadow_read_only_fields; i++) {
3845                 unsigned long field = shadow_read_only_fields[i];
3846
3847                 clear_bit(field, vmx_vmread_bitmap);
3848                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3849                         clear_bit(field + 1, vmx_vmread_bitmap);
3850         }
3851 }
3852
3853 static __init int alloc_kvm_area(void)
3854 {
3855         int cpu;
3856
3857         for_each_possible_cpu(cpu) {
3858                 struct vmcs *vmcs;
3859
3860                 vmcs = alloc_vmcs_cpu(cpu);
3861                 if (!vmcs) {
3862                         free_kvm_area();
3863                         return -ENOMEM;
3864                 }
3865
3866                 per_cpu(vmxarea, cpu) = vmcs;
3867         }
3868         return 0;
3869 }
3870
3871 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3872                 struct kvm_segment *save)
3873 {
3874         if (!emulate_invalid_guest_state) {
3875                 /*
3876                  * CS and SS RPL should be equal during guest entry according
3877                  * to VMX spec, but in reality it is not always so. Since vcpu
3878                  * is in the middle of the transition from real mode to
3879                  * protected mode it is safe to assume that RPL 0 is a good
3880                  * default value.
3881                  */
3882                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3883                         save->selector &= ~SEGMENT_RPL_MASK;
3884                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3885                 save->s = 1;
3886         }
3887         vmx_set_segment(vcpu, save, seg);
3888 }
3889
3890 static void enter_pmode(struct kvm_vcpu *vcpu)
3891 {
3892         unsigned long flags;
3893         struct vcpu_vmx *vmx = to_vmx(vcpu);
3894
3895         /*
3896          * Update real mode segment cache. It may be not up-to-date if sement
3897          * register was written while vcpu was in a guest mode.
3898          */
3899         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3900         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3901         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3902         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3903         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3904         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3905
3906         vmx->rmode.vm86_active = 0;
3907
3908         vmx_segment_cache_clear(vmx);
3909
3910         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3911
3912         flags = vmcs_readl(GUEST_RFLAGS);
3913         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3914         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3915         vmcs_writel(GUEST_RFLAGS, flags);
3916
3917         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3918                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3919
3920         update_exception_bitmap(vcpu);
3921
3922         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3923         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3924         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3925         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3926         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3927         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3928 }
3929
3930 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3931 {
3932         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3933         struct kvm_segment var = *save;
3934
3935         var.dpl = 0x3;
3936         if (seg == VCPU_SREG_CS)
3937                 var.type = 0x3;
3938
3939         if (!emulate_invalid_guest_state) {
3940                 var.selector = var.base >> 4;
3941                 var.base = var.base & 0xffff0;
3942                 var.limit = 0xffff;
3943                 var.g = 0;
3944                 var.db = 0;
3945                 var.present = 1;
3946                 var.s = 1;
3947                 var.l = 0;
3948                 var.unusable = 0;
3949                 var.type = 0x3;
3950                 var.avl = 0;
3951                 if (save->base & 0xf)
3952                         printk_once(KERN_WARNING "kvm: segment base is not "
3953                                         "paragraph aligned when entering "
3954                                         "protected mode (seg=%d)", seg);
3955         }
3956
3957         vmcs_write16(sf->selector, var.selector);
3958         vmcs_writel(sf->base, var.base);
3959         vmcs_write32(sf->limit, var.limit);
3960         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3961 }
3962
3963 static void enter_rmode(struct kvm_vcpu *vcpu)
3964 {
3965         unsigned long flags;
3966         struct vcpu_vmx *vmx = to_vmx(vcpu);
3967
3968         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3969         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3970         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3971         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3972         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3973         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3974         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3975
3976         vmx->rmode.vm86_active = 1;
3977
3978         /*
3979          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3980          * vcpu. Warn the user that an update is overdue.
3981          */
3982         if (!vcpu->kvm->arch.tss_addr)
3983                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3984                              "called before entering vcpu\n");
3985
3986         vmx_segment_cache_clear(vmx);
3987
3988         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3989         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3990         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3991
3992         flags = vmcs_readl(GUEST_RFLAGS);
3993         vmx->rmode.save_rflags = flags;
3994
3995         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3996
3997         vmcs_writel(GUEST_RFLAGS, flags);
3998         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3999         update_exception_bitmap(vcpu);
4000
4001         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4002         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4003         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4004         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4005         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4006         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4007
4008         kvm_mmu_reset_context(vcpu);
4009 }
4010
4011 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4012 {
4013         struct vcpu_vmx *vmx = to_vmx(vcpu);
4014         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4015
4016         if (!msr)
4017                 return;
4018
4019         /*
4020          * Force kernel_gs_base reloading before EFER changes, as control
4021          * of this msr depends on is_long_mode().
4022          */
4023         vmx_load_host_state(to_vmx(vcpu));
4024         vcpu->arch.efer = efer;
4025         if (efer & EFER_LMA) {
4026                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4027                 msr->data = efer;
4028         } else {
4029                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4030
4031                 msr->data = efer & ~EFER_LME;
4032         }
4033         setup_msrs(vmx);
4034 }
4035
4036 #ifdef CONFIG_X86_64
4037
4038 static void enter_lmode(struct kvm_vcpu *vcpu)
4039 {
4040         u32 guest_tr_ar;
4041
4042         vmx_segment_cache_clear(to_vmx(vcpu));
4043
4044         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4045         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4046                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4047                                      __func__);
4048                 vmcs_write32(GUEST_TR_AR_BYTES,
4049                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4050                              | VMX_AR_TYPE_BUSY_64_TSS);
4051         }
4052         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4053 }
4054
4055 static void exit_lmode(struct kvm_vcpu *vcpu)
4056 {
4057         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4058         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4059 }
4060
4061 #endif
4062
4063 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4064 {
4065         if (enable_ept) {
4066                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4067                         return;
4068                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4069         } else {
4070                 vpid_sync_context(vpid);
4071         }
4072 }
4073
4074 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4075 {
4076         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4077 }
4078
4079 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4080 {
4081         if (enable_ept)
4082                 vmx_flush_tlb(vcpu);
4083 }
4084
4085 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4086 {
4087         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4088
4089         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4090         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4091 }
4092
4093 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4094 {
4095         if (enable_ept && is_paging(vcpu))
4096                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4097         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4098 }
4099
4100 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4101 {
4102         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4103
4104         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4105         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4106 }
4107
4108 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4109 {
4110         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4111
4112         if (!test_bit(VCPU_EXREG_PDPTR,
4113                       (unsigned long *)&vcpu->arch.regs_dirty))
4114                 return;
4115
4116         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4117                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4118                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4119                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4120                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4121         }
4122 }
4123
4124 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4125 {
4126         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4127
4128         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4129                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4130                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4131                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4132                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4133         }
4134
4135         __set_bit(VCPU_EXREG_PDPTR,
4136                   (unsigned long *)&vcpu->arch.regs_avail);
4137         __set_bit(VCPU_EXREG_PDPTR,
4138                   (unsigned long *)&vcpu->arch.regs_dirty);
4139 }
4140
4141 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4142 {
4143         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4144         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4145         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4146
4147         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4148                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4149             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4150                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4151
4152         return fixed_bits_valid(val, fixed0, fixed1);
4153 }
4154
4155 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4156 {
4157         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4158         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4159
4160         return fixed_bits_valid(val, fixed0, fixed1);
4161 }
4162
4163 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4164 {
4165         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4166         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4167
4168         return fixed_bits_valid(val, fixed0, fixed1);
4169 }
4170
4171 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4172 #define nested_guest_cr4_valid  nested_cr4_valid
4173 #define nested_host_cr4_valid   nested_cr4_valid
4174
4175 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4176
4177 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4178                                         unsigned long cr0,
4179                                         struct kvm_vcpu *vcpu)
4180 {
4181         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4182                 vmx_decache_cr3(vcpu);
4183         if (!(cr0 & X86_CR0_PG)) {
4184                 /* From paging/starting to nonpaging */
4185                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4186                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4187                              (CPU_BASED_CR3_LOAD_EXITING |
4188                               CPU_BASED_CR3_STORE_EXITING));
4189                 vcpu->arch.cr0 = cr0;
4190                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4191         } else if (!is_paging(vcpu)) {
4192                 /* From nonpaging to paging */
4193                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4194                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4195                              ~(CPU_BASED_CR3_LOAD_EXITING |
4196                                CPU_BASED_CR3_STORE_EXITING));
4197                 vcpu->arch.cr0 = cr0;
4198                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4199         }
4200
4201         if (!(cr0 & X86_CR0_WP))
4202                 *hw_cr0 &= ~X86_CR0_WP;
4203 }
4204
4205 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4206 {
4207         struct vcpu_vmx *vmx = to_vmx(vcpu);
4208         unsigned long hw_cr0;
4209
4210         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4211         if (enable_unrestricted_guest)
4212                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4213         else {
4214                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4215
4216                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4217                         enter_pmode(vcpu);
4218
4219                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4220                         enter_rmode(vcpu);
4221         }
4222
4223 #ifdef CONFIG_X86_64
4224         if (vcpu->arch.efer & EFER_LME) {
4225                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4226                         enter_lmode(vcpu);
4227                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4228                         exit_lmode(vcpu);
4229         }
4230 #endif
4231
4232         if (enable_ept)
4233                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4234
4235         vmcs_writel(CR0_READ_SHADOW, cr0);
4236         vmcs_writel(GUEST_CR0, hw_cr0);
4237         vcpu->arch.cr0 = cr0;
4238
4239         /* depends on vcpu->arch.cr0 to be set to a new value */
4240         vmx->emulation_required = emulation_required(vcpu);
4241 }
4242
4243 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4244 {
4245         u64 eptp;
4246
4247         /* TODO write the value reading from MSR */
4248         eptp = VMX_EPT_DEFAULT_MT |
4249                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4250         if (enable_ept_ad_bits &&
4251             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4252                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4253         eptp |= (root_hpa & PAGE_MASK);
4254
4255         return eptp;
4256 }
4257
4258 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4259 {
4260         unsigned long guest_cr3;
4261         u64 eptp;
4262
4263         guest_cr3 = cr3;
4264         if (enable_ept) {
4265                 eptp = construct_eptp(vcpu, cr3);
4266                 vmcs_write64(EPT_POINTER, eptp);
4267                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4268                         guest_cr3 = kvm_read_cr3(vcpu);
4269                 else
4270                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4271                 ept_load_pdptrs(vcpu);
4272         }
4273
4274         vmx_flush_tlb(vcpu);
4275         vmcs_writel(GUEST_CR3, guest_cr3);
4276 }
4277
4278 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4279 {
4280         /*
4281          * Pass through host's Machine Check Enable value to hw_cr4, which
4282          * is in force while we are in guest mode.  Do not let guests control
4283          * this bit, even if host CR4.MCE == 0.
4284          */
4285         unsigned long hw_cr4 =
4286                 (cr4_read_shadow() & X86_CR4_MCE) |
4287                 (cr4 & ~X86_CR4_MCE) |
4288                 (to_vmx(vcpu)->rmode.vm86_active ?
4289                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4290
4291         if (cr4 & X86_CR4_VMXE) {
4292                 /*
4293                  * To use VMXON (and later other VMX instructions), a guest
4294                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4295                  * So basically the check on whether to allow nested VMX
4296                  * is here.
4297                  */
4298                 if (!nested_vmx_allowed(vcpu))
4299                         return 1;
4300         }
4301
4302         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4303                 return 1;
4304
4305         vcpu->arch.cr4 = cr4;
4306         if (enable_ept) {
4307                 if (!is_paging(vcpu)) {
4308                         hw_cr4 &= ~X86_CR4_PAE;
4309                         hw_cr4 |= X86_CR4_PSE;
4310                 } else if (!(cr4 & X86_CR4_PAE)) {
4311                         hw_cr4 &= ~X86_CR4_PAE;
4312                 }
4313         }
4314
4315         if (!enable_unrestricted_guest && !is_paging(vcpu))
4316                 /*
4317                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4318                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4319                  * to be manually disabled when guest switches to non-paging
4320                  * mode.
4321                  *
4322                  * If !enable_unrestricted_guest, the CPU is always running
4323                  * with CR0.PG=1 and CR4 needs to be modified.
4324                  * If enable_unrestricted_guest, the CPU automatically
4325                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4326                  */
4327                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4328
4329         vmcs_writel(CR4_READ_SHADOW, cr4);
4330         vmcs_writel(GUEST_CR4, hw_cr4);
4331         return 0;
4332 }
4333
4334 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4335                             struct kvm_segment *var, int seg)
4336 {
4337         struct vcpu_vmx *vmx = to_vmx(vcpu);
4338         u32 ar;
4339
4340         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4341                 *var = vmx->rmode.segs[seg];
4342                 if (seg == VCPU_SREG_TR
4343                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4344                         return;
4345                 var->base = vmx_read_guest_seg_base(vmx, seg);
4346                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4347                 return;
4348         }
4349         var->base = vmx_read_guest_seg_base(vmx, seg);
4350         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4351         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4352         ar = vmx_read_guest_seg_ar(vmx, seg);
4353         var->unusable = (ar >> 16) & 1;
4354         var->type = ar & 15;
4355         var->s = (ar >> 4) & 1;
4356         var->dpl = (ar >> 5) & 3;
4357         /*
4358          * Some userspaces do not preserve unusable property. Since usable
4359          * segment has to be present according to VMX spec we can use present
4360          * property to amend userspace bug by making unusable segment always
4361          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4362          * segment as unusable.
4363          */
4364         var->present = !var->unusable;
4365         var->avl = (ar >> 12) & 1;
4366         var->l = (ar >> 13) & 1;
4367         var->db = (ar >> 14) & 1;
4368         var->g = (ar >> 15) & 1;
4369 }
4370
4371 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4372 {
4373         struct kvm_segment s;
4374
4375         if (to_vmx(vcpu)->rmode.vm86_active) {
4376                 vmx_get_segment(vcpu, &s, seg);
4377                 return s.base;
4378         }
4379         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4380 }
4381
4382 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4383 {
4384         struct vcpu_vmx *vmx = to_vmx(vcpu);
4385
4386         if (unlikely(vmx->rmode.vm86_active))
4387                 return 0;
4388         else {
4389                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4390                 return VMX_AR_DPL(ar);
4391         }
4392 }
4393
4394 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4395 {
4396         u32 ar;
4397
4398         if (var->unusable || !var->present)
4399                 ar = 1 << 16;
4400         else {
4401                 ar = var->type & 15;
4402                 ar |= (var->s & 1) << 4;
4403                 ar |= (var->dpl & 3) << 5;
4404                 ar |= (var->present & 1) << 7;
4405                 ar |= (var->avl & 1) << 12;
4406                 ar |= (var->l & 1) << 13;
4407                 ar |= (var->db & 1) << 14;
4408                 ar |= (var->g & 1) << 15;
4409         }
4410
4411         return ar;
4412 }
4413
4414 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4415                             struct kvm_segment *var, int seg)
4416 {
4417         struct vcpu_vmx *vmx = to_vmx(vcpu);
4418         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4419
4420         vmx_segment_cache_clear(vmx);
4421
4422         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4423                 vmx->rmode.segs[seg] = *var;
4424                 if (seg == VCPU_SREG_TR)
4425                         vmcs_write16(sf->selector, var->selector);
4426                 else if (var->s)
4427                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4428                 goto out;
4429         }
4430
4431         vmcs_writel(sf->base, var->base);
4432         vmcs_write32(sf->limit, var->limit);
4433         vmcs_write16(sf->selector, var->selector);
4434
4435         /*
4436          *   Fix the "Accessed" bit in AR field of segment registers for older
4437          * qemu binaries.
4438          *   IA32 arch specifies that at the time of processor reset the
4439          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4440          * is setting it to 0 in the userland code. This causes invalid guest
4441          * state vmexit when "unrestricted guest" mode is turned on.
4442          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4443          * tree. Newer qemu binaries with that qemu fix would not need this
4444          * kvm hack.
4445          */
4446         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4447                 var->type |= 0x1; /* Accessed */
4448
4449         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4450
4451 out:
4452         vmx->emulation_required = emulation_required(vcpu);
4453 }
4454
4455 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4456 {
4457         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4458
4459         *db = (ar >> 14) & 1;
4460         *l = (ar >> 13) & 1;
4461 }
4462
4463 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4464 {
4465         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4466         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4467 }
4468
4469 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4470 {
4471         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4472         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4473 }
4474
4475 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4476 {
4477         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4478         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4479 }
4480
4481 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4482 {
4483         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4484         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4485 }
4486
4487 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4488 {
4489         struct kvm_segment var;
4490         u32 ar;
4491
4492         vmx_get_segment(vcpu, &var, seg);
4493         var.dpl = 0x3;
4494         if (seg == VCPU_SREG_CS)
4495                 var.type = 0x3;
4496         ar = vmx_segment_access_rights(&var);
4497
4498         if (var.base != (var.selector << 4))
4499                 return false;
4500         if (var.limit != 0xffff)
4501                 return false;
4502         if (ar != 0xf3)
4503                 return false;
4504
4505         return true;
4506 }
4507
4508 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4509 {
4510         struct kvm_segment cs;
4511         unsigned int cs_rpl;
4512
4513         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4514         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4515
4516         if (cs.unusable)
4517                 return false;
4518         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4519                 return false;
4520         if (!cs.s)
4521                 return false;
4522         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4523                 if (cs.dpl > cs_rpl)
4524                         return false;
4525         } else {
4526                 if (cs.dpl != cs_rpl)
4527                         return false;
4528         }
4529         if (!cs.present)
4530                 return false;
4531
4532         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4533         return true;
4534 }
4535
4536 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4537 {
4538         struct kvm_segment ss;
4539         unsigned int ss_rpl;
4540
4541         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4542         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4543
4544         if (ss.unusable)
4545                 return true;
4546         if (ss.type != 3 && ss.type != 7)
4547                 return false;
4548         if (!ss.s)
4549                 return false;
4550         if (ss.dpl != ss_rpl) /* DPL != RPL */
4551                 return false;
4552         if (!ss.present)
4553                 return false;
4554
4555         return true;
4556 }
4557
4558 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4559 {
4560         struct kvm_segment var;
4561         unsigned int rpl;
4562
4563         vmx_get_segment(vcpu, &var, seg);
4564         rpl = var.selector & SEGMENT_RPL_MASK;
4565
4566         if (var.unusable)
4567                 return true;
4568         if (!var.s)
4569                 return false;
4570         if (!var.present)
4571                 return false;
4572         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4573                 if (var.dpl < rpl) /* DPL < RPL */
4574                         return false;
4575         }
4576
4577         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4578          * rights flags
4579          */
4580         return true;
4581 }
4582
4583 static bool tr_valid(struct kvm_vcpu *vcpu)
4584 {
4585         struct kvm_segment tr;
4586
4587         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4588
4589         if (tr.unusable)
4590                 return false;
4591         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4592                 return false;
4593         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4594                 return false;
4595         if (!tr.present)
4596                 return false;
4597
4598         return true;
4599 }
4600
4601 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4602 {
4603         struct kvm_segment ldtr;
4604
4605         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4606
4607         if (ldtr.unusable)
4608                 return true;
4609         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4610                 return false;
4611         if (ldtr.type != 2)
4612                 return false;
4613         if (!ldtr.present)
4614                 return false;
4615
4616         return true;
4617 }
4618
4619 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4620 {
4621         struct kvm_segment cs, ss;
4622
4623         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4624         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4625
4626         return ((cs.selector & SEGMENT_RPL_MASK) ==
4627                  (ss.selector & SEGMENT_RPL_MASK));
4628 }
4629
4630 /*
4631  * Check if guest state is valid. Returns true if valid, false if
4632  * not.
4633  * We assume that registers are always usable
4634  */
4635 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4636 {
4637         if (enable_unrestricted_guest)
4638                 return true;
4639
4640         /* real mode guest state checks */
4641         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4642                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4643                         return false;
4644                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4645                         return false;
4646                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4647                         return false;
4648                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4649                         return false;
4650                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4651                         return false;
4652                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4653                         return false;
4654         } else {
4655         /* protected mode guest state checks */
4656                 if (!cs_ss_rpl_check(vcpu))
4657                         return false;
4658                 if (!code_segment_valid(vcpu))
4659                         return false;
4660                 if (!stack_segment_valid(vcpu))
4661                         return false;
4662                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4663                         return false;
4664                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4665                         return false;
4666                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4667                         return false;
4668                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4669                         return false;
4670                 if (!tr_valid(vcpu))
4671                         return false;
4672                 if (!ldtr_valid(vcpu))
4673                         return false;
4674         }
4675         /* TODO:
4676          * - Add checks on RIP
4677          * - Add checks on RFLAGS
4678          */
4679
4680         return true;
4681 }
4682
4683 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4684 {
4685         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4686 }
4687
4688 static int init_rmode_tss(struct kvm *kvm)
4689 {
4690         gfn_t fn;
4691         u16 data = 0;
4692         int idx, r;
4693
4694         idx = srcu_read_lock(&kvm->srcu);
4695         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4696         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4697         if (r < 0)
4698                 goto out;
4699         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4700         r = kvm_write_guest_page(kvm, fn++, &data,
4701                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4702         if (r < 0)
4703                 goto out;
4704         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4705         if (r < 0)
4706                 goto out;
4707         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4708         if (r < 0)
4709                 goto out;
4710         data = ~0;
4711         r = kvm_write_guest_page(kvm, fn, &data,
4712                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4713                                  sizeof(u8));
4714 out:
4715         srcu_read_unlock(&kvm->srcu, idx);
4716         return r;
4717 }
4718
4719 static int init_rmode_identity_map(struct kvm *kvm)
4720 {
4721         int i, idx, r = 0;
4722         kvm_pfn_t identity_map_pfn;
4723         u32 tmp;
4724
4725         if (!enable_ept)
4726                 return 0;
4727
4728         /* Protect kvm->arch.ept_identity_pagetable_done. */
4729         mutex_lock(&kvm->slots_lock);
4730
4731         if (likely(kvm->arch.ept_identity_pagetable_done))
4732                 goto out2;
4733
4734         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4735
4736         r = alloc_identity_pagetable(kvm);
4737         if (r < 0)
4738                 goto out2;
4739
4740         idx = srcu_read_lock(&kvm->srcu);
4741         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4742         if (r < 0)
4743                 goto out;
4744         /* Set up identity-mapping pagetable for EPT in real mode */
4745         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4746                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4747                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4748                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4749                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4750                 if (r < 0)
4751                         goto out;
4752         }
4753         kvm->arch.ept_identity_pagetable_done = true;
4754
4755 out:
4756         srcu_read_unlock(&kvm->srcu, idx);
4757
4758 out2:
4759         mutex_unlock(&kvm->slots_lock);
4760         return r;
4761 }
4762
4763 static void seg_setup(int seg)
4764 {
4765         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4766         unsigned int ar;
4767
4768         vmcs_write16(sf->selector, 0);
4769         vmcs_writel(sf->base, 0);
4770         vmcs_write32(sf->limit, 0xffff);
4771         ar = 0x93;
4772         if (seg == VCPU_SREG_CS)
4773                 ar |= 0x08; /* code segment */
4774
4775         vmcs_write32(sf->ar_bytes, ar);
4776 }
4777
4778 static int alloc_apic_access_page(struct kvm *kvm)
4779 {
4780         struct page *page;
4781         int r = 0;
4782
4783         mutex_lock(&kvm->slots_lock);
4784         if (kvm->arch.apic_access_page_done)
4785                 goto out;
4786         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4787                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4788         if (r)
4789                 goto out;
4790
4791         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4792         if (is_error_page(page)) {
4793                 r = -EFAULT;
4794                 goto out;
4795         }
4796
4797         /*
4798          * Do not pin the page in memory, so that memory hot-unplug
4799          * is able to migrate it.
4800          */
4801         put_page(page);
4802         kvm->arch.apic_access_page_done = true;
4803 out:
4804         mutex_unlock(&kvm->slots_lock);
4805         return r;
4806 }
4807
4808 static int alloc_identity_pagetable(struct kvm *kvm)
4809 {
4810         /* Called with kvm->slots_lock held. */
4811
4812         int r = 0;
4813
4814         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4815
4816         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4817                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4818
4819         return r;
4820 }
4821
4822 static int allocate_vpid(void)
4823 {
4824         int vpid;
4825
4826         if (!enable_vpid)
4827                 return 0;
4828         spin_lock(&vmx_vpid_lock);
4829         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4830         if (vpid < VMX_NR_VPIDS)
4831                 __set_bit(vpid, vmx_vpid_bitmap);
4832         else
4833                 vpid = 0;
4834         spin_unlock(&vmx_vpid_lock);
4835         return vpid;
4836 }
4837
4838 static void free_vpid(int vpid)
4839 {
4840         if (!enable_vpid || vpid == 0)
4841                 return;
4842         spin_lock(&vmx_vpid_lock);
4843         __clear_bit(vpid, vmx_vpid_bitmap);
4844         spin_unlock(&vmx_vpid_lock);
4845 }
4846
4847 #define MSR_TYPE_R      1
4848 #define MSR_TYPE_W      2
4849 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4850                                                 u32 msr, int type)
4851 {
4852         int f = sizeof(unsigned long);
4853
4854         if (!cpu_has_vmx_msr_bitmap())
4855                 return;
4856
4857         /*
4858          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4859          * have the write-low and read-high bitmap offsets the wrong way round.
4860          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4861          */
4862         if (msr <= 0x1fff) {
4863                 if (type & MSR_TYPE_R)
4864                         /* read-low */
4865                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4866
4867                 if (type & MSR_TYPE_W)
4868                         /* write-low */
4869                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4870
4871         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4872                 msr &= 0x1fff;
4873                 if (type & MSR_TYPE_R)
4874                         /* read-high */
4875                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4876
4877                 if (type & MSR_TYPE_W)
4878                         /* write-high */
4879                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4880
4881         }
4882 }
4883
4884 /*
4885  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4886  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4887  */
4888 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4889                                                unsigned long *msr_bitmap_nested,
4890                                                u32 msr, int type)
4891 {
4892         int f = sizeof(unsigned long);
4893
4894         if (!cpu_has_vmx_msr_bitmap()) {
4895                 WARN_ON(1);
4896                 return;
4897         }
4898
4899         /*
4900          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4901          * have the write-low and read-high bitmap offsets the wrong way round.
4902          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4903          */
4904         if (msr <= 0x1fff) {
4905                 if (type & MSR_TYPE_R &&
4906                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4907                         /* read-low */
4908                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4909
4910                 if (type & MSR_TYPE_W &&
4911                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4912                         /* write-low */
4913                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4914
4915         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4916                 msr &= 0x1fff;
4917                 if (type & MSR_TYPE_R &&
4918                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4919                         /* read-high */
4920                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4921
4922                 if (type & MSR_TYPE_W &&
4923                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4924                         /* write-high */
4925                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4926
4927         }
4928 }
4929
4930 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4931 {
4932         if (!longmode_only)
4933                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4934                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4935         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4936                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4937 }
4938
4939 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4940 {
4941         if (apicv_active) {
4942                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4943                                 msr, type);
4944                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4945                                 msr, type);
4946         } else {
4947                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4948                                 msr, type);
4949                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4950                                 msr, type);
4951         }
4952 }
4953
4954 static bool vmx_get_enable_apicv(void)
4955 {
4956         return enable_apicv;
4957 }
4958
4959 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4960 {
4961         struct vcpu_vmx *vmx = to_vmx(vcpu);
4962         int max_irr;
4963         void *vapic_page;
4964         u16 status;
4965
4966         if (vmx->nested.pi_desc &&
4967             vmx->nested.pi_pending) {
4968                 vmx->nested.pi_pending = false;
4969                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4970                         return;
4971
4972                 max_irr = find_last_bit(
4973                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4974
4975                 if (max_irr == 256)
4976                         return;
4977
4978                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4979                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4980                 kunmap(vmx->nested.virtual_apic_page);
4981
4982                 status = vmcs_read16(GUEST_INTR_STATUS);
4983                 if ((u8)max_irr > ((u8)status & 0xff)) {
4984                         status &= ~0xff;
4985                         status |= (u8)max_irr;
4986                         vmcs_write16(GUEST_INTR_STATUS, status);
4987                 }
4988         }
4989 }
4990
4991 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
4992                                                      bool nested)
4993 {
4994 #ifdef CONFIG_SMP
4995         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
4996
4997         if (vcpu->mode == IN_GUEST_MODE) {
4998                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4999
5000                 /*
5001                  * Currently, we don't support urgent interrupt,
5002                  * all interrupts are recognized as non-urgent
5003                  * interrupt, so we cannot post interrupts when
5004                  * 'SN' is set.
5005                  *
5006                  * If the vcpu is in guest mode, it means it is
5007                  * running instead of being scheduled out and
5008                  * waiting in the run queue, and that's the only
5009                  * case when 'SN' is set currently, warning if
5010                  * 'SN' is set.
5011                  */
5012                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
5013
5014                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5015                 return true;
5016         }
5017 #endif
5018         return false;
5019 }
5020
5021 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5022                                                 int vector)
5023 {
5024         struct vcpu_vmx *vmx = to_vmx(vcpu);
5025
5026         if (is_guest_mode(vcpu) &&
5027             vector == vmx->nested.posted_intr_nv) {
5028                 /* the PIR and ON have been set by L1. */
5029                 kvm_vcpu_trigger_posted_interrupt(vcpu, true);
5030                 /*
5031                  * If a posted intr is not recognized by hardware,
5032                  * we will accomplish it in the next vmentry.
5033                  */
5034                 vmx->nested.pi_pending = true;
5035                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5036                 return 0;
5037         }
5038         return -1;
5039 }
5040 /*
5041  * Send interrupt to vcpu via posted interrupt way.
5042  * 1. If target vcpu is running(non-root mode), send posted interrupt
5043  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5044  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5045  * interrupt from PIR in next vmentry.
5046  */
5047 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5048 {
5049         struct vcpu_vmx *vmx = to_vmx(vcpu);
5050         int r;
5051
5052         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5053         if (!r)
5054                 return;
5055
5056         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5057                 return;
5058
5059         /* If a previous notification has sent the IPI, nothing to do.  */
5060         if (pi_test_and_set_on(&vmx->pi_desc))
5061                 return;
5062
5063         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5064                 kvm_vcpu_kick(vcpu);
5065 }
5066
5067 /*
5068  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5069  * will not change in the lifetime of the guest.
5070  * Note that host-state that does change is set elsewhere. E.g., host-state
5071  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5072  */
5073 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5074 {
5075         u32 low32, high32;
5076         unsigned long tmpl;
5077         struct desc_ptr dt;
5078         unsigned long cr0, cr3, cr4;
5079
5080         cr0 = read_cr0();
5081         WARN_ON(cr0 & X86_CR0_TS);
5082         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5083
5084         /*
5085          * Save the most likely value for this task's CR3 in the VMCS.
5086          * We can't use __get_current_cr3_fast() because we're not atomic.
5087          */
5088         cr3 = __read_cr3();
5089         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5090         vmx->host_state.vmcs_host_cr3 = cr3;
5091
5092         /* Save the most likely value for this task's CR4 in the VMCS. */
5093         cr4 = cr4_read_shadow();
5094         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5095         vmx->host_state.vmcs_host_cr4 = cr4;
5096
5097         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5098 #ifdef CONFIG_X86_64
5099         /*
5100          * Load null selectors, so we can avoid reloading them in
5101          * __vmx_load_host_state(), in case userspace uses the null selectors
5102          * too (the expected case).
5103          */
5104         vmcs_write16(HOST_DS_SELECTOR, 0);
5105         vmcs_write16(HOST_ES_SELECTOR, 0);
5106 #else
5107         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5108         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5109 #endif
5110         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5111         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5112
5113         native_store_idt(&dt);
5114         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5115         vmx->host_idt_base = dt.address;
5116
5117         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5118
5119         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5120         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5121         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5122         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5123
5124         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5125                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5126                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5127         }
5128 }
5129
5130 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5131 {
5132         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5133         if (enable_ept)
5134                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5135         if (is_guest_mode(&vmx->vcpu))
5136                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5137                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5138         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5139 }
5140
5141 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5142 {
5143         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5144
5145         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5146                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5147         /* Enable the preemption timer dynamically */
5148         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5149         return pin_based_exec_ctrl;
5150 }
5151
5152 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5153 {
5154         struct vcpu_vmx *vmx = to_vmx(vcpu);
5155
5156         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5157         if (cpu_has_secondary_exec_ctrls()) {
5158                 if (kvm_vcpu_apicv_active(vcpu))
5159                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5160                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5161                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5162                 else
5163                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5164                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5165                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5166         }
5167
5168         if (cpu_has_vmx_msr_bitmap())
5169                 vmx_set_msr_bitmap(vcpu);
5170 }
5171
5172 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5173 {
5174         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5175
5176         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5177                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5178
5179         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5180                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5181 #ifdef CONFIG_X86_64
5182                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5183                                 CPU_BASED_CR8_LOAD_EXITING;
5184 #endif
5185         }
5186         if (!enable_ept)
5187                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5188                                 CPU_BASED_CR3_LOAD_EXITING  |
5189                                 CPU_BASED_INVLPG_EXITING;
5190         return exec_control;
5191 }
5192
5193 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5194 {
5195         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5196         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5197                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5198         if (vmx->vpid == 0)
5199                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5200         if (!enable_ept) {
5201                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5202                 enable_unrestricted_guest = 0;
5203                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5204                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5205         }
5206         if (!enable_unrestricted_guest)
5207                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5208         if (!ple_gap)
5209                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5210         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5211                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5212                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5213         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5214         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5215            (handle_vmptrld).
5216            We can NOT enable shadow_vmcs here because we don't have yet
5217            a current VMCS12
5218         */
5219         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5220
5221         if (!enable_pml)
5222                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5223
5224         return exec_control;
5225 }
5226
5227 static void ept_set_mmio_spte_mask(void)
5228 {
5229         /*
5230          * EPT Misconfigurations can be generated if the value of bits 2:0
5231          * of an EPT paging-structure entry is 110b (write/execute).
5232          */
5233         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5234                                    VMX_EPT_MISCONFIG_WX_VALUE);
5235 }
5236
5237 #define VMX_XSS_EXIT_BITMAP 0
5238 /*
5239  * Sets up the vmcs for emulated real mode.
5240  */
5241 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5242 {
5243 #ifdef CONFIG_X86_64
5244         unsigned long a;
5245 #endif
5246         int i;
5247
5248         /* I/O */
5249         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5250         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5251
5252         if (enable_shadow_vmcs) {
5253                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5254                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5255         }
5256         if (cpu_has_vmx_msr_bitmap())
5257                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5258
5259         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5260
5261         /* Control */
5262         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5263         vmx->hv_deadline_tsc = -1;
5264
5265         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5266
5267         if (cpu_has_secondary_exec_ctrls()) {
5268                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5269                                 vmx_secondary_exec_control(vmx));
5270         }
5271
5272         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5273                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5274                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5275                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5276                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5277
5278                 vmcs_write16(GUEST_INTR_STATUS, 0);
5279
5280                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5281                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5282         }
5283
5284         if (ple_gap) {
5285                 vmcs_write32(PLE_GAP, ple_gap);
5286                 vmx->ple_window = ple_window;
5287                 vmx->ple_window_dirty = true;
5288         }
5289
5290         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5291         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5292         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5293
5294         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5295         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5296         vmx_set_constant_host_state(vmx);
5297 #ifdef CONFIG_X86_64
5298         rdmsrl(MSR_FS_BASE, a);
5299         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5300         rdmsrl(MSR_GS_BASE, a);
5301         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5302 #else
5303         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5304         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5305 #endif
5306
5307         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5308         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5309         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5310         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5311         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5312
5313         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5314                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5315
5316         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5317                 u32 index = vmx_msr_index[i];
5318                 u32 data_low, data_high;
5319                 int j = vmx->nmsrs;
5320
5321                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5322                         continue;
5323                 if (wrmsr_safe(index, data_low, data_high) < 0)
5324                         continue;
5325                 vmx->guest_msrs[j].index = i;
5326                 vmx->guest_msrs[j].data = 0;
5327                 vmx->guest_msrs[j].mask = -1ull;
5328                 ++vmx->nmsrs;
5329         }
5330
5331
5332         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5333
5334         /* 22.2.1, 20.8.1 */
5335         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5336
5337         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5338         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5339
5340         set_cr4_guest_host_mask(vmx);
5341
5342         if (vmx_xsaves_supported())
5343                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5344
5345         if (enable_pml) {
5346                 ASSERT(vmx->pml_pg);
5347                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5348                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5349         }
5350
5351         return 0;
5352 }
5353
5354 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5355 {
5356         struct vcpu_vmx *vmx = to_vmx(vcpu);
5357         struct msr_data apic_base_msr;
5358         u64 cr0;
5359
5360         vmx->rmode.vm86_active = 0;
5361
5362         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5363         kvm_set_cr8(vcpu, 0);
5364
5365         if (!init_event) {
5366                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5367                                      MSR_IA32_APICBASE_ENABLE;
5368                 if (kvm_vcpu_is_reset_bsp(vcpu))
5369                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5370                 apic_base_msr.host_initiated = true;
5371                 kvm_set_apic_base(vcpu, &apic_base_msr);
5372         }
5373
5374         vmx_segment_cache_clear(vmx);
5375
5376         seg_setup(VCPU_SREG_CS);
5377         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5378         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5379
5380         seg_setup(VCPU_SREG_DS);
5381         seg_setup(VCPU_SREG_ES);
5382         seg_setup(VCPU_SREG_FS);
5383         seg_setup(VCPU_SREG_GS);
5384         seg_setup(VCPU_SREG_SS);
5385
5386         vmcs_write16(GUEST_TR_SELECTOR, 0);
5387         vmcs_writel(GUEST_TR_BASE, 0);
5388         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5389         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5390
5391         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5392         vmcs_writel(GUEST_LDTR_BASE, 0);
5393         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5394         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5395
5396         if (!init_event) {
5397                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5398                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5399                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5400                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5401         }
5402
5403         vmcs_writel(GUEST_RFLAGS, 0x02);
5404         kvm_rip_write(vcpu, 0xfff0);
5405
5406         vmcs_writel(GUEST_GDTR_BASE, 0);
5407         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5408
5409         vmcs_writel(GUEST_IDTR_BASE, 0);
5410         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5411
5412         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5413         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5414         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5415
5416         setup_msrs(vmx);
5417
5418         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5419
5420         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5421                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5422                 if (cpu_need_tpr_shadow(vcpu))
5423                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5424                                      __pa(vcpu->arch.apic->regs));
5425                 vmcs_write32(TPR_THRESHOLD, 0);
5426         }
5427
5428         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5429
5430         if (kvm_vcpu_apicv_active(vcpu))
5431                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5432
5433         if (vmx->vpid != 0)
5434                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5435
5436         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5437         vmx->vcpu.arch.cr0 = cr0;
5438         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5439         vmx_set_cr4(vcpu, 0);
5440         vmx_set_efer(vcpu, 0);
5441
5442         update_exception_bitmap(vcpu);
5443
5444         vpid_sync_context(vmx->vpid);
5445 }
5446
5447 /*
5448  * In nested virtualization, check if L1 asked to exit on external interrupts.
5449  * For most existing hypervisors, this will always return true.
5450  */
5451 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5452 {
5453         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5454                 PIN_BASED_EXT_INTR_MASK;
5455 }
5456
5457 /*
5458  * In nested virtualization, check if L1 has set
5459  * VM_EXIT_ACK_INTR_ON_EXIT
5460  */
5461 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5462 {
5463         return get_vmcs12(vcpu)->vm_exit_controls &
5464                 VM_EXIT_ACK_INTR_ON_EXIT;
5465 }
5466
5467 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5468 {
5469         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5470                 PIN_BASED_NMI_EXITING;
5471 }
5472
5473 static void enable_irq_window(struct kvm_vcpu *vcpu)
5474 {
5475         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5476                       CPU_BASED_VIRTUAL_INTR_PENDING);
5477 }
5478
5479 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5480 {
5481         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5482                 enable_irq_window(vcpu);
5483                 return;
5484         }
5485
5486         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5487                       CPU_BASED_VIRTUAL_NMI_PENDING);
5488 }
5489
5490 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5491 {
5492         struct vcpu_vmx *vmx = to_vmx(vcpu);
5493         uint32_t intr;
5494         int irq = vcpu->arch.interrupt.nr;
5495
5496         trace_kvm_inj_virq(irq);
5497
5498         ++vcpu->stat.irq_injections;
5499         if (vmx->rmode.vm86_active) {
5500                 int inc_eip = 0;
5501                 if (vcpu->arch.interrupt.soft)
5502                         inc_eip = vcpu->arch.event_exit_inst_len;
5503                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5504                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5505                 return;
5506         }
5507         intr = irq | INTR_INFO_VALID_MASK;
5508         if (vcpu->arch.interrupt.soft) {
5509                 intr |= INTR_TYPE_SOFT_INTR;
5510                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5511                              vmx->vcpu.arch.event_exit_inst_len);
5512         } else
5513                 intr |= INTR_TYPE_EXT_INTR;
5514         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5515 }
5516
5517 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5518 {
5519         struct vcpu_vmx *vmx = to_vmx(vcpu);
5520
5521         ++vcpu->stat.nmi_injections;
5522         vmx->loaded_vmcs->nmi_known_unmasked = false;
5523
5524         if (vmx->rmode.vm86_active) {
5525                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5526                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5527                 return;
5528         }
5529
5530         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5531                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5532 }
5533
5534 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5535 {
5536         struct vcpu_vmx *vmx = to_vmx(vcpu);
5537         bool masked;
5538
5539         if (vmx->loaded_vmcs->nmi_known_unmasked)
5540                 return false;
5541         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5542         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5543         return masked;
5544 }
5545
5546 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5547 {
5548         struct vcpu_vmx *vmx = to_vmx(vcpu);
5549
5550         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5551         if (masked)
5552                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5553                               GUEST_INTR_STATE_NMI);
5554         else
5555                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5556                                 GUEST_INTR_STATE_NMI);
5557 }
5558
5559 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5560 {
5561         if (to_vmx(vcpu)->nested.nested_run_pending)
5562                 return 0;
5563
5564         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5565                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5566                    | GUEST_INTR_STATE_NMI));
5567 }
5568
5569 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5570 {
5571         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5572                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5573                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5574                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5575 }
5576
5577 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5578 {
5579         int ret;
5580
5581         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5582                                     PAGE_SIZE * 3);
5583         if (ret)
5584                 return ret;
5585         kvm->arch.tss_addr = addr;
5586         return init_rmode_tss(kvm);
5587 }
5588
5589 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5590 {
5591         switch (vec) {
5592         case BP_VECTOR:
5593                 /*
5594                  * Update instruction length as we may reinject the exception
5595                  * from user space while in guest debugging mode.
5596                  */
5597                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5598                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5599                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5600                         return false;
5601                 /* fall through */
5602         case DB_VECTOR:
5603                 if (vcpu->guest_debug &
5604                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5605                         return false;
5606                 /* fall through */
5607         case DE_VECTOR:
5608         case OF_VECTOR:
5609         case BR_VECTOR:
5610         case UD_VECTOR:
5611         case DF_VECTOR:
5612         case SS_VECTOR:
5613         case GP_VECTOR:
5614         case MF_VECTOR:
5615                 return true;
5616         break;
5617         }
5618         return false;
5619 }
5620
5621 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5622                                   int vec, u32 err_code)
5623 {
5624         /*
5625          * Instruction with address size override prefix opcode 0x67
5626          * Cause the #SS fault with 0 error code in VM86 mode.
5627          */
5628         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5629                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5630                         if (vcpu->arch.halt_request) {
5631                                 vcpu->arch.halt_request = 0;
5632                                 return kvm_vcpu_halt(vcpu);
5633                         }
5634                         return 1;
5635                 }
5636                 return 0;
5637         }
5638
5639         /*
5640          * Forward all other exceptions that are valid in real mode.
5641          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5642          *        the required debugging infrastructure rework.
5643          */
5644         kvm_queue_exception(vcpu, vec);
5645         return 1;
5646 }
5647
5648 /*
5649  * Trigger machine check on the host. We assume all the MSRs are already set up
5650  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5651  * We pass a fake environment to the machine check handler because we want
5652  * the guest to be always treated like user space, no matter what context
5653  * it used internally.
5654  */
5655 static void kvm_machine_check(void)
5656 {
5657 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5658         struct pt_regs regs = {
5659                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5660                 .flags = X86_EFLAGS_IF,
5661         };
5662
5663         do_machine_check(&regs, 0);
5664 #endif
5665 }
5666
5667 static int handle_machine_check(struct kvm_vcpu *vcpu)
5668 {
5669         /* already handled by vcpu_run */
5670         return 1;
5671 }
5672
5673 static int handle_exception(struct kvm_vcpu *vcpu)
5674 {
5675         struct vcpu_vmx *vmx = to_vmx(vcpu);
5676         struct kvm_run *kvm_run = vcpu->run;
5677         u32 intr_info, ex_no, error_code;
5678         unsigned long cr2, rip, dr6;
5679         u32 vect_info;
5680         enum emulation_result er;
5681
5682         vect_info = vmx->idt_vectoring_info;
5683         intr_info = vmx->exit_intr_info;
5684
5685         if (is_machine_check(intr_info))
5686                 return handle_machine_check(vcpu);
5687
5688         if (is_nmi(intr_info))
5689                 return 1;  /* already handled by vmx_vcpu_run() */
5690
5691         if (is_invalid_opcode(intr_info)) {
5692                 if (is_guest_mode(vcpu)) {
5693                         kvm_queue_exception(vcpu, UD_VECTOR);
5694                         return 1;
5695                 }
5696                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5697                 if (er != EMULATE_DONE)
5698                         kvm_queue_exception(vcpu, UD_VECTOR);
5699                 return 1;
5700         }
5701
5702         error_code = 0;
5703         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5704                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5705
5706         /*
5707          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5708          * MMIO, it is better to report an internal error.
5709          * See the comments in vmx_handle_exit.
5710          */
5711         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5712             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5713                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5714                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5715                 vcpu->run->internal.ndata = 3;
5716                 vcpu->run->internal.data[0] = vect_info;
5717                 vcpu->run->internal.data[1] = intr_info;
5718                 vcpu->run->internal.data[2] = error_code;
5719                 return 0;
5720         }
5721
5722         if (is_page_fault(intr_info)) {
5723                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5724                 /* EPT won't cause page fault directly */
5725                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5726                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
5727                                 true);
5728         }
5729
5730         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5731
5732         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5733                 return handle_rmode_exception(vcpu, ex_no, error_code);
5734
5735         switch (ex_no) {
5736         case AC_VECTOR:
5737                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5738                 return 1;
5739         case DB_VECTOR:
5740                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5741                 if (!(vcpu->guest_debug &
5742                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5743                         vcpu->arch.dr6 &= ~15;
5744                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5745                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5746                                 skip_emulated_instruction(vcpu);
5747
5748                         kvm_queue_exception(vcpu, DB_VECTOR);
5749                         return 1;
5750                 }
5751                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5752                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5753                 /* fall through */
5754         case BP_VECTOR:
5755                 /*
5756                  * Update instruction length as we may reinject #BP from
5757                  * user space while in guest debugging mode. Reading it for
5758                  * #DB as well causes no harm, it is not used in that case.
5759                  */
5760                 vmx->vcpu.arch.event_exit_inst_len =
5761                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5762                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5763                 rip = kvm_rip_read(vcpu);
5764                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5765                 kvm_run->debug.arch.exception = ex_no;
5766                 break;
5767         default:
5768                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5769                 kvm_run->ex.exception = ex_no;
5770                 kvm_run->ex.error_code = error_code;
5771                 break;
5772         }
5773         return 0;
5774 }
5775
5776 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5777 {
5778         ++vcpu->stat.irq_exits;
5779         return 1;
5780 }
5781
5782 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5783 {
5784         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5785         return 0;
5786 }
5787
5788 static int handle_io(struct kvm_vcpu *vcpu)
5789 {
5790         unsigned long exit_qualification;
5791         int size, in, string, ret;
5792         unsigned port;
5793
5794         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5795         string = (exit_qualification & 16) != 0;
5796         in = (exit_qualification & 8) != 0;
5797
5798         ++vcpu->stat.io_exits;
5799
5800         if (string || in)
5801                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5802
5803         port = exit_qualification >> 16;
5804         size = (exit_qualification & 7) + 1;
5805
5806         ret = kvm_skip_emulated_instruction(vcpu);
5807
5808         /*
5809          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5810          * KVM_EXIT_DEBUG here.
5811          */
5812         return kvm_fast_pio_out(vcpu, size, port) && ret;
5813 }
5814
5815 static void
5816 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5817 {
5818         /*
5819          * Patch in the VMCALL instruction:
5820          */
5821         hypercall[0] = 0x0f;
5822         hypercall[1] = 0x01;
5823         hypercall[2] = 0xc1;
5824 }
5825
5826 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5827 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5828 {
5829         if (is_guest_mode(vcpu)) {
5830                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5831                 unsigned long orig_val = val;
5832
5833                 /*
5834                  * We get here when L2 changed cr0 in a way that did not change
5835                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5836                  * but did change L0 shadowed bits. So we first calculate the
5837                  * effective cr0 value that L1 would like to write into the
5838                  * hardware. It consists of the L2-owned bits from the new
5839                  * value combined with the L1-owned bits from L1's guest_cr0.
5840                  */
5841                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5842                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5843
5844                 if (!nested_guest_cr0_valid(vcpu, val))
5845                         return 1;
5846
5847                 if (kvm_set_cr0(vcpu, val))
5848                         return 1;
5849                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5850                 return 0;
5851         } else {
5852                 if (to_vmx(vcpu)->nested.vmxon &&
5853                     !nested_host_cr0_valid(vcpu, val))
5854                         return 1;
5855
5856                 return kvm_set_cr0(vcpu, val);
5857         }
5858 }
5859
5860 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5861 {
5862         if (is_guest_mode(vcpu)) {
5863                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5864                 unsigned long orig_val = val;
5865
5866                 /* analogously to handle_set_cr0 */
5867                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5868                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5869                 if (kvm_set_cr4(vcpu, val))
5870                         return 1;
5871                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5872                 return 0;
5873         } else
5874                 return kvm_set_cr4(vcpu, val);
5875 }
5876
5877 static int handle_cr(struct kvm_vcpu *vcpu)
5878 {
5879         unsigned long exit_qualification, val;
5880         int cr;
5881         int reg;
5882         int err;
5883         int ret;
5884
5885         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5886         cr = exit_qualification & 15;
5887         reg = (exit_qualification >> 8) & 15;
5888         switch ((exit_qualification >> 4) & 3) {
5889         case 0: /* mov to cr */
5890                 val = kvm_register_readl(vcpu, reg);
5891                 trace_kvm_cr_write(cr, val);
5892                 switch (cr) {
5893                 case 0:
5894                         err = handle_set_cr0(vcpu, val);
5895                         return kvm_complete_insn_gp(vcpu, err);
5896                 case 3:
5897                         err = kvm_set_cr3(vcpu, val);
5898                         return kvm_complete_insn_gp(vcpu, err);
5899                 case 4:
5900                         err = handle_set_cr4(vcpu, val);
5901                         return kvm_complete_insn_gp(vcpu, err);
5902                 case 8: {
5903                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5904                                 u8 cr8 = (u8)val;
5905                                 err = kvm_set_cr8(vcpu, cr8);
5906                                 ret = kvm_complete_insn_gp(vcpu, err);
5907                                 if (lapic_in_kernel(vcpu))
5908                                         return ret;
5909                                 if (cr8_prev <= cr8)
5910                                         return ret;
5911                                 /*
5912                                  * TODO: we might be squashing a
5913                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5914                                  * KVM_EXIT_DEBUG here.
5915                                  */
5916                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5917                                 return 0;
5918                         }
5919                 }
5920                 break;
5921         case 2: /* clts */
5922                 WARN_ONCE(1, "Guest should always own CR0.TS");
5923                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5924                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5925                 return kvm_skip_emulated_instruction(vcpu);
5926         case 1: /*mov from cr*/
5927                 switch (cr) {
5928                 case 3:
5929                         val = kvm_read_cr3(vcpu);
5930                         kvm_register_write(vcpu, reg, val);
5931                         trace_kvm_cr_read(cr, val);
5932                         return kvm_skip_emulated_instruction(vcpu);
5933                 case 8:
5934                         val = kvm_get_cr8(vcpu);
5935                         kvm_register_write(vcpu, reg, val);
5936                         trace_kvm_cr_read(cr, val);
5937                         return kvm_skip_emulated_instruction(vcpu);
5938                 }
5939                 break;
5940         case 3: /* lmsw */
5941                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5942                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5943                 kvm_lmsw(vcpu, val);
5944
5945                 return kvm_skip_emulated_instruction(vcpu);
5946         default:
5947                 break;
5948         }
5949         vcpu->run->exit_reason = 0;
5950         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5951                (int)(exit_qualification >> 4) & 3, cr);
5952         return 0;
5953 }
5954
5955 static int handle_dr(struct kvm_vcpu *vcpu)
5956 {
5957         unsigned long exit_qualification;
5958         int dr, dr7, reg;
5959
5960         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5961         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5962
5963         /* First, if DR does not exist, trigger UD */
5964         if (!kvm_require_dr(vcpu, dr))
5965                 return 1;
5966
5967         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5968         if (!kvm_require_cpl(vcpu, 0))
5969                 return 1;
5970         dr7 = vmcs_readl(GUEST_DR7);
5971         if (dr7 & DR7_GD) {
5972                 /*
5973                  * As the vm-exit takes precedence over the debug trap, we
5974                  * need to emulate the latter, either for the host or the
5975                  * guest debugging itself.
5976                  */
5977                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5978                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5979                         vcpu->run->debug.arch.dr7 = dr7;
5980                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5981                         vcpu->run->debug.arch.exception = DB_VECTOR;
5982                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5983                         return 0;
5984                 } else {
5985                         vcpu->arch.dr6 &= ~15;
5986                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5987                         kvm_queue_exception(vcpu, DB_VECTOR);
5988                         return 1;
5989                 }
5990         }
5991
5992         if (vcpu->guest_debug == 0) {
5993                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5994                                 CPU_BASED_MOV_DR_EXITING);
5995
5996                 /*
5997                  * No more DR vmexits; force a reload of the debug registers
5998                  * and reenter on this instruction.  The next vmexit will
5999                  * retrieve the full state of the debug registers.
6000                  */
6001                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6002                 return 1;
6003         }
6004
6005         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6006         if (exit_qualification & TYPE_MOV_FROM_DR) {
6007                 unsigned long val;
6008
6009                 if (kvm_get_dr(vcpu, dr, &val))
6010                         return 1;
6011                 kvm_register_write(vcpu, reg, val);
6012         } else
6013                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6014                         return 1;
6015
6016         return kvm_skip_emulated_instruction(vcpu);
6017 }
6018
6019 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6020 {
6021         return vcpu->arch.dr6;
6022 }
6023
6024 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6025 {
6026 }
6027
6028 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6029 {
6030         get_debugreg(vcpu->arch.db[0], 0);
6031         get_debugreg(vcpu->arch.db[1], 1);
6032         get_debugreg(vcpu->arch.db[2], 2);
6033         get_debugreg(vcpu->arch.db[3], 3);
6034         get_debugreg(vcpu->arch.dr6, 6);
6035         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6036
6037         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6038         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6039 }
6040
6041 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6042 {
6043         vmcs_writel(GUEST_DR7, val);
6044 }
6045
6046 static int handle_cpuid(struct kvm_vcpu *vcpu)
6047 {
6048         return kvm_emulate_cpuid(vcpu);
6049 }
6050
6051 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6052 {
6053         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6054         struct msr_data msr_info;
6055
6056         msr_info.index = ecx;
6057         msr_info.host_initiated = false;
6058         if (vmx_get_msr(vcpu, &msr_info)) {
6059                 trace_kvm_msr_read_ex(ecx);
6060                 kvm_inject_gp(vcpu, 0);
6061                 return 1;
6062         }
6063
6064         trace_kvm_msr_read(ecx, msr_info.data);
6065
6066         /* FIXME: handling of bits 32:63 of rax, rdx */
6067         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6068         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6069         return kvm_skip_emulated_instruction(vcpu);
6070 }
6071
6072 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6073 {
6074         struct msr_data msr;
6075         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6076         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6077                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6078
6079         msr.data = data;
6080         msr.index = ecx;
6081         msr.host_initiated = false;
6082         if (kvm_set_msr(vcpu, &msr) != 0) {
6083                 trace_kvm_msr_write_ex(ecx, data);
6084                 kvm_inject_gp(vcpu, 0);
6085                 return 1;
6086         }
6087
6088         trace_kvm_msr_write(ecx, data);
6089         return kvm_skip_emulated_instruction(vcpu);
6090 }
6091
6092 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6093 {
6094         kvm_apic_update_ppr(vcpu);
6095         return 1;
6096 }
6097
6098 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6099 {
6100         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6101                         CPU_BASED_VIRTUAL_INTR_PENDING);
6102
6103         kvm_make_request(KVM_REQ_EVENT, vcpu);
6104
6105         ++vcpu->stat.irq_window_exits;
6106         return 1;
6107 }
6108
6109 static int handle_halt(struct kvm_vcpu *vcpu)
6110 {
6111         return kvm_emulate_halt(vcpu);
6112 }
6113
6114 static int handle_vmcall(struct kvm_vcpu *vcpu)
6115 {
6116         return kvm_emulate_hypercall(vcpu);
6117 }
6118
6119 static int handle_invd(struct kvm_vcpu *vcpu)
6120 {
6121         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6122 }
6123
6124 static int handle_invlpg(struct kvm_vcpu *vcpu)
6125 {
6126         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6127
6128         kvm_mmu_invlpg(vcpu, exit_qualification);
6129         return kvm_skip_emulated_instruction(vcpu);
6130 }
6131
6132 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6133 {
6134         int err;
6135
6136         err = kvm_rdpmc(vcpu);
6137         return kvm_complete_insn_gp(vcpu, err);
6138 }
6139
6140 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6141 {
6142         return kvm_emulate_wbinvd(vcpu);
6143 }
6144
6145 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6146 {
6147         u64 new_bv = kvm_read_edx_eax(vcpu);
6148         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6149
6150         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6151                 return kvm_skip_emulated_instruction(vcpu);
6152         return 1;
6153 }
6154
6155 static int handle_xsaves(struct kvm_vcpu *vcpu)
6156 {
6157         kvm_skip_emulated_instruction(vcpu);
6158         WARN(1, "this should never happen\n");
6159         return 1;
6160 }
6161
6162 static int handle_xrstors(struct kvm_vcpu *vcpu)
6163 {
6164         kvm_skip_emulated_instruction(vcpu);
6165         WARN(1, "this should never happen\n");
6166         return 1;
6167 }
6168
6169 static int handle_apic_access(struct kvm_vcpu *vcpu)
6170 {
6171         if (likely(fasteoi)) {
6172                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6173                 int access_type, offset;
6174
6175                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6176                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6177                 /*
6178                  * Sane guest uses MOV to write EOI, with written value
6179                  * not cared. So make a short-circuit here by avoiding
6180                  * heavy instruction emulation.
6181                  */
6182                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6183                     (offset == APIC_EOI)) {
6184                         kvm_lapic_set_eoi(vcpu);
6185                         return kvm_skip_emulated_instruction(vcpu);
6186                 }
6187         }
6188         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6189 }
6190
6191 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6192 {
6193         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6194         int vector = exit_qualification & 0xff;
6195
6196         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6197         kvm_apic_set_eoi_accelerated(vcpu, vector);
6198         return 1;
6199 }
6200
6201 static int handle_apic_write(struct kvm_vcpu *vcpu)
6202 {
6203         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6204         u32 offset = exit_qualification & 0xfff;
6205
6206         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6207         kvm_apic_write_nodecode(vcpu, offset);
6208         return 1;
6209 }
6210
6211 static int handle_task_switch(struct kvm_vcpu *vcpu)
6212 {
6213         struct vcpu_vmx *vmx = to_vmx(vcpu);
6214         unsigned long exit_qualification;
6215         bool has_error_code = false;
6216         u32 error_code = 0;
6217         u16 tss_selector;
6218         int reason, type, idt_v, idt_index;
6219
6220         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6221         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6222         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6223
6224         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6225
6226         reason = (u32)exit_qualification >> 30;
6227         if (reason == TASK_SWITCH_GATE && idt_v) {
6228                 switch (type) {
6229                 case INTR_TYPE_NMI_INTR:
6230                         vcpu->arch.nmi_injected = false;
6231                         vmx_set_nmi_mask(vcpu, true);
6232                         break;
6233                 case INTR_TYPE_EXT_INTR:
6234                 case INTR_TYPE_SOFT_INTR:
6235                         kvm_clear_interrupt_queue(vcpu);
6236                         break;
6237                 case INTR_TYPE_HARD_EXCEPTION:
6238                         if (vmx->idt_vectoring_info &
6239                             VECTORING_INFO_DELIVER_CODE_MASK) {
6240                                 has_error_code = true;
6241                                 error_code =
6242                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6243                         }
6244                         /* fall through */
6245                 case INTR_TYPE_SOFT_EXCEPTION:
6246                         kvm_clear_exception_queue(vcpu);
6247                         break;
6248                 default:
6249                         break;
6250                 }
6251         }
6252         tss_selector = exit_qualification;
6253
6254         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6255                        type != INTR_TYPE_EXT_INTR &&
6256                        type != INTR_TYPE_NMI_INTR))
6257                 skip_emulated_instruction(vcpu);
6258
6259         if (kvm_task_switch(vcpu, tss_selector,
6260                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6261                             has_error_code, error_code) == EMULATE_FAIL) {
6262                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6263                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6264                 vcpu->run->internal.ndata = 0;
6265                 return 0;
6266         }
6267
6268         /*
6269          * TODO: What about debug traps on tss switch?
6270          *       Are we supposed to inject them and update dr6?
6271          */
6272
6273         return 1;
6274 }
6275
6276 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6277 {
6278         unsigned long exit_qualification;
6279         gpa_t gpa;
6280         u32 error_code;
6281
6282         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6283
6284         /*
6285          * EPT violation happened while executing iret from NMI,
6286          * "blocked by NMI" bit has to be set before next VM entry.
6287          * There are errata that may cause this bit to not be set:
6288          * AAK134, BY25.
6289          */
6290         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6291                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6292                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6293
6294         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6295         trace_kvm_page_fault(gpa, exit_qualification);
6296
6297         /* Is it a read fault? */
6298         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6299                      ? PFERR_USER_MASK : 0;
6300         /* Is it a write fault? */
6301         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6302                       ? PFERR_WRITE_MASK : 0;
6303         /* Is it a fetch fault? */
6304         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6305                       ? PFERR_FETCH_MASK : 0;
6306         /* ept page table entry is present? */
6307         error_code |= (exit_qualification &
6308                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6309                         EPT_VIOLATION_EXECUTABLE))
6310                       ? PFERR_PRESENT_MASK : 0;
6311
6312         vcpu->arch.gpa_available = true;
6313         vcpu->arch.exit_qualification = exit_qualification;
6314
6315         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6316 }
6317
6318 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6319 {
6320         int ret;
6321         gpa_t gpa;
6322
6323         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6324         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6325                 trace_kvm_fast_mmio(gpa);
6326                 return kvm_skip_emulated_instruction(vcpu);
6327         }
6328
6329         ret = handle_mmio_page_fault(vcpu, gpa, true);
6330         vcpu->arch.gpa_available = true;
6331         if (likely(ret == RET_MMIO_PF_EMULATE))
6332                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6333                                               EMULATE_DONE;
6334
6335         if (unlikely(ret == RET_MMIO_PF_INVALID))
6336                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6337
6338         if (unlikely(ret == RET_MMIO_PF_RETRY))
6339                 return 1;
6340
6341         /* It is the real ept misconfig */
6342         WARN_ON(1);
6343
6344         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6345         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6346
6347         return 0;
6348 }
6349
6350 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6351 {
6352         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6353                         CPU_BASED_VIRTUAL_NMI_PENDING);
6354         ++vcpu->stat.nmi_window_exits;
6355         kvm_make_request(KVM_REQ_EVENT, vcpu);
6356
6357         return 1;
6358 }
6359
6360 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6361 {
6362         struct vcpu_vmx *vmx = to_vmx(vcpu);
6363         enum emulation_result err = EMULATE_DONE;
6364         int ret = 1;
6365         u32 cpu_exec_ctrl;
6366         bool intr_window_requested;
6367         unsigned count = 130;
6368
6369         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6370         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6371
6372         while (vmx->emulation_required && count-- != 0) {
6373                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6374                         return handle_interrupt_window(&vmx->vcpu);
6375
6376                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6377                         return 1;
6378
6379                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6380
6381                 if (err == EMULATE_USER_EXIT) {
6382                         ++vcpu->stat.mmio_exits;
6383                         ret = 0;
6384                         goto out;
6385                 }
6386
6387                 if (err != EMULATE_DONE) {
6388                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6389                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6390                         vcpu->run->internal.ndata = 0;
6391                         return 0;
6392                 }
6393
6394                 if (vcpu->arch.halt_request) {
6395                         vcpu->arch.halt_request = 0;
6396                         ret = kvm_vcpu_halt(vcpu);
6397                         goto out;
6398                 }
6399
6400                 if (signal_pending(current))
6401                         goto out;
6402                 if (need_resched())
6403                         schedule();
6404         }
6405
6406 out:
6407         return ret;
6408 }
6409
6410 static int __grow_ple_window(int val)
6411 {
6412         if (ple_window_grow < 1)
6413                 return ple_window;
6414
6415         val = min(val, ple_window_actual_max);
6416
6417         if (ple_window_grow < ple_window)
6418                 val *= ple_window_grow;
6419         else
6420                 val += ple_window_grow;
6421
6422         return val;
6423 }
6424
6425 static int __shrink_ple_window(int val, int modifier, int minimum)
6426 {
6427         if (modifier < 1)
6428                 return ple_window;
6429
6430         if (modifier < ple_window)
6431                 val /= modifier;
6432         else
6433                 val -= modifier;
6434
6435         return max(val, minimum);
6436 }
6437
6438 static void grow_ple_window(struct kvm_vcpu *vcpu)
6439 {
6440         struct vcpu_vmx *vmx = to_vmx(vcpu);
6441         int old = vmx->ple_window;
6442
6443         vmx->ple_window = __grow_ple_window(old);
6444
6445         if (vmx->ple_window != old)
6446                 vmx->ple_window_dirty = true;
6447
6448         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6449 }
6450
6451 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6452 {
6453         struct vcpu_vmx *vmx = to_vmx(vcpu);
6454         int old = vmx->ple_window;
6455
6456         vmx->ple_window = __shrink_ple_window(old,
6457                                               ple_window_shrink, ple_window);
6458
6459         if (vmx->ple_window != old)
6460                 vmx->ple_window_dirty = true;
6461
6462         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6463 }
6464
6465 /*
6466  * ple_window_actual_max is computed to be one grow_ple_window() below
6467  * ple_window_max. (See __grow_ple_window for the reason.)
6468  * This prevents overflows, because ple_window_max is int.
6469  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6470  * this process.
6471  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6472  */
6473 static void update_ple_window_actual_max(void)
6474 {
6475         ple_window_actual_max =
6476                         __shrink_ple_window(max(ple_window_max, ple_window),
6477                                             ple_window_grow, INT_MIN);
6478 }
6479
6480 /*
6481  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6482  */
6483 static void wakeup_handler(void)
6484 {
6485         struct kvm_vcpu *vcpu;
6486         int cpu = smp_processor_id();
6487
6488         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6489         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6490                         blocked_vcpu_list) {
6491                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6492
6493                 if (pi_test_on(pi_desc) == 1)
6494                         kvm_vcpu_kick(vcpu);
6495         }
6496         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6497 }
6498
6499 void vmx_enable_tdp(void)
6500 {
6501         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6502                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6503                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6504                 0ull, VMX_EPT_EXECUTABLE_MASK,
6505                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6506                 VMX_EPT_RWX_MASK);
6507
6508         ept_set_mmio_spte_mask();
6509         kvm_enable_tdp();
6510 }
6511
6512 static __init int hardware_setup(void)
6513 {
6514         int r = -ENOMEM, i, msr;
6515
6516         rdmsrl_safe(MSR_EFER, &host_efer);
6517
6518         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6519                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6520
6521         for (i = 0; i < VMX_BITMAP_NR; i++) {
6522                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6523                 if (!vmx_bitmap[i])
6524                         goto out;
6525         }
6526
6527         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6528         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6529         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6530
6531         /*
6532          * Allow direct access to the PC debug port (it is often used for I/O
6533          * delays, but the vmexits simply slow things down).
6534          */
6535         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6536         clear_bit(0x80, vmx_io_bitmap_a);
6537
6538         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6539
6540         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6541         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6542
6543         if (setup_vmcs_config(&vmcs_config) < 0) {
6544                 r = -EIO;
6545                 goto out;
6546         }
6547
6548         if (boot_cpu_has(X86_FEATURE_NX))
6549                 kvm_enable_efer_bits(EFER_NX);
6550
6551         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6552                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6553                 enable_vpid = 0;
6554
6555         if (!cpu_has_vmx_shadow_vmcs())
6556                 enable_shadow_vmcs = 0;
6557         if (enable_shadow_vmcs)
6558                 init_vmcs_shadow_fields();
6559
6560         if (!cpu_has_vmx_ept() ||
6561             !cpu_has_vmx_ept_4levels()) {
6562                 enable_ept = 0;
6563                 enable_unrestricted_guest = 0;
6564                 enable_ept_ad_bits = 0;
6565         }
6566
6567         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6568                 enable_ept_ad_bits = 0;
6569
6570         if (!cpu_has_vmx_unrestricted_guest())
6571                 enable_unrestricted_guest = 0;
6572
6573         if (!cpu_has_vmx_flexpriority())
6574                 flexpriority_enabled = 0;
6575
6576         /*
6577          * set_apic_access_page_addr() is used to reload apic access
6578          * page upon invalidation.  No need to do anything if not
6579          * using the APIC_ACCESS_ADDR VMCS field.
6580          */
6581         if (!flexpriority_enabled)
6582                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6583
6584         if (!cpu_has_vmx_tpr_shadow())
6585                 kvm_x86_ops->update_cr8_intercept = NULL;
6586
6587         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6588                 kvm_disable_largepages();
6589
6590         if (!cpu_has_vmx_ple())
6591                 ple_gap = 0;
6592
6593         if (!cpu_has_vmx_apicv()) {
6594                 enable_apicv = 0;
6595                 kvm_x86_ops->sync_pir_to_irr = NULL;
6596         }
6597
6598         if (cpu_has_vmx_tsc_scaling()) {
6599                 kvm_has_tsc_control = true;
6600                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6601                 kvm_tsc_scaling_ratio_frac_bits = 48;
6602         }
6603
6604         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6605         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6606         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6607         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6608         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6609         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6610
6611         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6612                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6613         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6614                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6615         memcpy(vmx_msr_bitmap_legacy_x2apic,
6616                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6617         memcpy(vmx_msr_bitmap_longmode_x2apic,
6618                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6619
6620         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6621
6622         for (msr = 0x800; msr <= 0x8ff; msr++) {
6623                 if (msr == 0x839 /* TMCCT */)
6624                         continue;
6625                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6626         }
6627
6628         /*
6629          * TPR reads and writes can be virtualized even if virtual interrupt
6630          * delivery is not in use.
6631          */
6632         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6633         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6634
6635         /* EOI */
6636         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6637         /* SELF-IPI */
6638         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6639
6640         if (enable_ept)
6641                 vmx_enable_tdp();
6642         else
6643                 kvm_disable_tdp();
6644
6645         update_ple_window_actual_max();
6646
6647         /*
6648          * Only enable PML when hardware supports PML feature, and both EPT
6649          * and EPT A/D bit features are enabled -- PML depends on them to work.
6650          */
6651         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6652                 enable_pml = 0;
6653
6654         if (!enable_pml) {
6655                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6656                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6657                 kvm_x86_ops->flush_log_dirty = NULL;
6658                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6659         }
6660
6661         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6662                 u64 vmx_msr;
6663
6664                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6665                 cpu_preemption_timer_multi =
6666                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6667         } else {
6668                 kvm_x86_ops->set_hv_timer = NULL;
6669                 kvm_x86_ops->cancel_hv_timer = NULL;
6670         }
6671
6672         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6673
6674         kvm_mce_cap_supported |= MCG_LMCE_P;
6675
6676         return alloc_kvm_area();
6677
6678 out:
6679         for (i = 0; i < VMX_BITMAP_NR; i++)
6680                 free_page((unsigned long)vmx_bitmap[i]);
6681
6682     return r;
6683 }
6684
6685 static __exit void hardware_unsetup(void)
6686 {
6687         int i;
6688
6689         for (i = 0; i < VMX_BITMAP_NR; i++)
6690                 free_page((unsigned long)vmx_bitmap[i]);
6691
6692         free_kvm_area();
6693 }
6694
6695 /*
6696  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6697  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6698  */
6699 static int handle_pause(struct kvm_vcpu *vcpu)
6700 {
6701         if (ple_gap)
6702                 grow_ple_window(vcpu);
6703
6704         kvm_vcpu_on_spin(vcpu);
6705         return kvm_skip_emulated_instruction(vcpu);
6706 }
6707
6708 static int handle_nop(struct kvm_vcpu *vcpu)
6709 {
6710         return kvm_skip_emulated_instruction(vcpu);
6711 }
6712
6713 static int handle_mwait(struct kvm_vcpu *vcpu)
6714 {
6715         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6716         return handle_nop(vcpu);
6717 }
6718
6719 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6720 {
6721         return 1;
6722 }
6723
6724 static int handle_monitor(struct kvm_vcpu *vcpu)
6725 {
6726         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6727         return handle_nop(vcpu);
6728 }
6729
6730 /*
6731  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6732  * We could reuse a single VMCS for all the L2 guests, but we also want the
6733  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6734  * allows keeping them loaded on the processor, and in the future will allow
6735  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6736  * every entry if they never change.
6737  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6738  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6739  *
6740  * The following functions allocate and free a vmcs02 in this pool.
6741  */
6742
6743 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6744 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6745 {
6746         struct vmcs02_list *item;
6747         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6748                 if (item->vmptr == vmx->nested.current_vmptr) {
6749                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6750                         return &item->vmcs02;
6751                 }
6752
6753         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6754                 /* Recycle the least recently used VMCS. */
6755                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6756                                        struct vmcs02_list, list);
6757                 item->vmptr = vmx->nested.current_vmptr;
6758                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6759                 return &item->vmcs02;
6760         }
6761
6762         /* Create a new VMCS */
6763         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6764         if (!item)
6765                 return NULL;
6766         item->vmcs02.vmcs = alloc_vmcs();
6767         item->vmcs02.shadow_vmcs = NULL;
6768         if (!item->vmcs02.vmcs) {
6769                 kfree(item);
6770                 return NULL;
6771         }
6772         loaded_vmcs_init(&item->vmcs02);
6773         item->vmptr = vmx->nested.current_vmptr;
6774         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6775         vmx->nested.vmcs02_num++;
6776         return &item->vmcs02;
6777 }
6778
6779 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6780 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6781 {
6782         struct vmcs02_list *item;
6783         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6784                 if (item->vmptr == vmptr) {
6785                         free_loaded_vmcs(&item->vmcs02);
6786                         list_del(&item->list);
6787                         kfree(item);
6788                         vmx->nested.vmcs02_num--;
6789                         return;
6790                 }
6791 }
6792
6793 /*
6794  * Free all VMCSs saved for this vcpu, except the one pointed by
6795  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6796  * must be &vmx->vmcs01.
6797  */
6798 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6799 {
6800         struct vmcs02_list *item, *n;
6801
6802         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6803         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6804                 /*
6805                  * Something will leak if the above WARN triggers.  Better than
6806                  * a use-after-free.
6807                  */
6808                 if (vmx->loaded_vmcs == &item->vmcs02)
6809                         continue;
6810
6811                 free_loaded_vmcs(&item->vmcs02);
6812                 list_del(&item->list);
6813                 kfree(item);
6814                 vmx->nested.vmcs02_num--;
6815         }
6816 }
6817
6818 /*
6819  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6820  * set the success or error code of an emulated VMX instruction, as specified
6821  * by Vol 2B, VMX Instruction Reference, "Conventions".
6822  */
6823 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6824 {
6825         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6826                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6827                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6828 }
6829
6830 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6831 {
6832         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6833                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6834                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6835                         | X86_EFLAGS_CF);
6836 }
6837
6838 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6839                                         u32 vm_instruction_error)
6840 {
6841         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6842                 /*
6843                  * failValid writes the error number to the current VMCS, which
6844                  * can't be done there isn't a current VMCS.
6845                  */
6846                 nested_vmx_failInvalid(vcpu);
6847                 return;
6848         }
6849         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6850                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6851                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6852                         | X86_EFLAGS_ZF);
6853         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6854         /*
6855          * We don't need to force a shadow sync because
6856          * VM_INSTRUCTION_ERROR is not shadowed
6857          */
6858 }
6859
6860 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6861 {
6862         /* TODO: not to reset guest simply here. */
6863         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6864         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6865 }
6866
6867 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6868 {
6869         struct vcpu_vmx *vmx =
6870                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6871
6872         vmx->nested.preemption_timer_expired = true;
6873         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6874         kvm_vcpu_kick(&vmx->vcpu);
6875
6876         return HRTIMER_NORESTART;
6877 }
6878
6879 /*
6880  * Decode the memory-address operand of a vmx instruction, as recorded on an
6881  * exit caused by such an instruction (run by a guest hypervisor).
6882  * On success, returns 0. When the operand is invalid, returns 1 and throws
6883  * #UD or #GP.
6884  */
6885 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6886                                  unsigned long exit_qualification,
6887                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6888 {
6889         gva_t off;
6890         bool exn;
6891         struct kvm_segment s;
6892
6893         /*
6894          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6895          * Execution", on an exit, vmx_instruction_info holds most of the
6896          * addressing components of the operand. Only the displacement part
6897          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6898          * For how an actual address is calculated from all these components,
6899          * refer to Vol. 1, "Operand Addressing".
6900          */
6901         int  scaling = vmx_instruction_info & 3;
6902         int  addr_size = (vmx_instruction_info >> 7) & 7;
6903         bool is_reg = vmx_instruction_info & (1u << 10);
6904         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6905         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6906         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6907         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6908         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6909
6910         if (is_reg) {
6911                 kvm_queue_exception(vcpu, UD_VECTOR);
6912                 return 1;
6913         }
6914
6915         /* Addr = segment_base + offset */
6916         /* offset = base + [index * scale] + displacement */
6917         off = exit_qualification; /* holds the displacement */
6918         if (base_is_valid)
6919                 off += kvm_register_read(vcpu, base_reg);
6920         if (index_is_valid)
6921                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6922         vmx_get_segment(vcpu, &s, seg_reg);
6923         *ret = s.base + off;
6924
6925         if (addr_size == 1) /* 32 bit */
6926                 *ret &= 0xffffffff;
6927
6928         /* Checks for #GP/#SS exceptions. */
6929         exn = false;
6930         if (is_long_mode(vcpu)) {
6931                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6932                  * non-canonical form. This is the only check on the memory
6933                  * destination for long mode!
6934                  */
6935                 exn = is_noncanonical_address(*ret);
6936         } else if (is_protmode(vcpu)) {
6937                 /* Protected mode: apply checks for segment validity in the
6938                  * following order:
6939                  * - segment type check (#GP(0) may be thrown)
6940                  * - usability check (#GP(0)/#SS(0))
6941                  * - limit check (#GP(0)/#SS(0))
6942                  */
6943                 if (wr)
6944                         /* #GP(0) if the destination operand is located in a
6945                          * read-only data segment or any code segment.
6946                          */
6947                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6948                 else
6949                         /* #GP(0) if the source operand is located in an
6950                          * execute-only code segment
6951                          */
6952                         exn = ((s.type & 0xa) == 8);
6953                 if (exn) {
6954                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6955                         return 1;
6956                 }
6957                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6958                  */
6959                 exn = (s.unusable != 0);
6960                 /* Protected mode: #GP(0)/#SS(0) if the memory
6961                  * operand is outside the segment limit.
6962                  */
6963                 exn = exn || (off + sizeof(u64) > s.limit);
6964         }
6965         if (exn) {
6966                 kvm_queue_exception_e(vcpu,
6967                                       seg_reg == VCPU_SREG_SS ?
6968                                                 SS_VECTOR : GP_VECTOR,
6969                                       0);
6970                 return 1;
6971         }
6972
6973         return 0;
6974 }
6975
6976 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
6977 {
6978         gva_t gva;
6979         struct x86_exception e;
6980
6981         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6982                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6983                 return 1;
6984
6985         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
6986                                 sizeof(*vmpointer), &e)) {
6987                 kvm_inject_page_fault(vcpu, &e);
6988                 return 1;
6989         }
6990
6991         return 0;
6992 }
6993
6994 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
6995 {
6996         struct vcpu_vmx *vmx = to_vmx(vcpu);
6997         struct vmcs *shadow_vmcs;
6998
6999         if (cpu_has_vmx_msr_bitmap()) {
7000                 vmx->nested.msr_bitmap =
7001                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7002                 if (!vmx->nested.msr_bitmap)
7003                         goto out_msr_bitmap;
7004         }
7005
7006         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7007         if (!vmx->nested.cached_vmcs12)
7008                 goto out_cached_vmcs12;
7009
7010         if (enable_shadow_vmcs) {
7011                 shadow_vmcs = alloc_vmcs();
7012                 if (!shadow_vmcs)
7013                         goto out_shadow_vmcs;
7014                 /* mark vmcs as shadow */
7015                 shadow_vmcs->revision_id |= (1u << 31);
7016                 /* init shadow vmcs */
7017                 vmcs_clear(shadow_vmcs);
7018                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7019         }
7020
7021         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7022         vmx->nested.vmcs02_num = 0;
7023
7024         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7025                      HRTIMER_MODE_REL_PINNED);
7026         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7027
7028         vmx->nested.vmxon = true;
7029         return 0;
7030
7031 out_shadow_vmcs:
7032         kfree(vmx->nested.cached_vmcs12);
7033
7034 out_cached_vmcs12:
7035         free_page((unsigned long)vmx->nested.msr_bitmap);
7036
7037 out_msr_bitmap:
7038         return -ENOMEM;
7039 }
7040
7041 /*
7042  * Emulate the VMXON instruction.
7043  * Currently, we just remember that VMX is active, and do not save or even
7044  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7045  * do not currently need to store anything in that guest-allocated memory
7046  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7047  * argument is different from the VMXON pointer (which the spec says they do).
7048  */
7049 static int handle_vmon(struct kvm_vcpu *vcpu)
7050 {
7051         int ret;
7052         gpa_t vmptr;
7053         struct page *page;
7054         struct vcpu_vmx *vmx = to_vmx(vcpu);
7055         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7056                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7057
7058         /*
7059          * The Intel VMX Instruction Reference lists a bunch of bits that are
7060          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7061          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7062          * Otherwise, we should fail with #UD.  But most faulting conditions
7063          * have already been checked by hardware, prior to the VM-exit for
7064          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7065          * that bit set to 1 in non-root mode.
7066          */
7067         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7068                 kvm_queue_exception(vcpu, UD_VECTOR);
7069                 return 1;
7070         }
7071
7072         if (vmx->nested.vmxon) {
7073                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7074                 return kvm_skip_emulated_instruction(vcpu);
7075         }
7076
7077         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7078                         != VMXON_NEEDED_FEATURES) {
7079                 kvm_inject_gp(vcpu, 0);
7080                 return 1;
7081         }
7082
7083         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7084                 return 1;
7085
7086         /*
7087          * SDM 3: 24.11.5
7088          * The first 4 bytes of VMXON region contain the supported
7089          * VMCS revision identifier
7090          *
7091          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7092          * which replaces physical address width with 32
7093          */
7094         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7095                 nested_vmx_failInvalid(vcpu);
7096                 return kvm_skip_emulated_instruction(vcpu);
7097         }
7098
7099         page = nested_get_page(vcpu, vmptr);
7100         if (page == NULL) {
7101                 nested_vmx_failInvalid(vcpu);
7102                 return kvm_skip_emulated_instruction(vcpu);
7103         }
7104         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7105                 kunmap(page);
7106                 nested_release_page_clean(page);
7107                 nested_vmx_failInvalid(vcpu);
7108                 return kvm_skip_emulated_instruction(vcpu);
7109         }
7110         kunmap(page);
7111         nested_release_page_clean(page);
7112
7113         vmx->nested.vmxon_ptr = vmptr;
7114         ret = enter_vmx_operation(vcpu);
7115         if (ret)
7116                 return ret;
7117
7118         nested_vmx_succeed(vcpu);
7119         return kvm_skip_emulated_instruction(vcpu);
7120 }
7121
7122 /*
7123  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7124  * for running VMX instructions (except VMXON, whose prerequisites are
7125  * slightly different). It also specifies what exception to inject otherwise.
7126  * Note that many of these exceptions have priority over VM exits, so they
7127  * don't have to be checked again here.
7128  */
7129 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7130 {
7131         if (!to_vmx(vcpu)->nested.vmxon) {
7132                 kvm_queue_exception(vcpu, UD_VECTOR);
7133                 return 0;
7134         }
7135         return 1;
7136 }
7137
7138 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7139 {
7140         if (vmx->nested.current_vmptr == -1ull)
7141                 return;
7142
7143         /* current_vmptr and current_vmcs12 are always set/reset together */
7144         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7145                 return;
7146
7147         if (enable_shadow_vmcs) {
7148                 /* copy to memory all shadowed fields in case
7149                    they were modified */
7150                 copy_shadow_to_vmcs12(vmx);
7151                 vmx->nested.sync_shadow_vmcs = false;
7152                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7153                                 SECONDARY_EXEC_SHADOW_VMCS);
7154                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7155         }
7156         vmx->nested.posted_intr_nv = -1;
7157
7158         /* Flush VMCS12 to guest memory */
7159         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7160                VMCS12_SIZE);
7161
7162         kunmap(vmx->nested.current_vmcs12_page);
7163         nested_release_page(vmx->nested.current_vmcs12_page);
7164         vmx->nested.current_vmptr = -1ull;
7165         vmx->nested.current_vmcs12 = NULL;
7166 }
7167
7168 /*
7169  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7170  * just stops using VMX.
7171  */
7172 static void free_nested(struct vcpu_vmx *vmx)
7173 {
7174         if (!vmx->nested.vmxon)
7175                 return;
7176
7177         vmx->nested.vmxon = false;
7178         free_vpid(vmx->nested.vpid02);
7179         nested_release_vmcs12(vmx);
7180         if (vmx->nested.msr_bitmap) {
7181                 free_page((unsigned long)vmx->nested.msr_bitmap);
7182                 vmx->nested.msr_bitmap = NULL;
7183         }
7184         if (enable_shadow_vmcs) {
7185                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7186                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7187                 vmx->vmcs01.shadow_vmcs = NULL;
7188         }
7189         kfree(vmx->nested.cached_vmcs12);
7190         /* Unpin physical memory we referred to in current vmcs02 */
7191         if (vmx->nested.apic_access_page) {
7192                 nested_release_page(vmx->nested.apic_access_page);
7193                 vmx->nested.apic_access_page = NULL;
7194         }
7195         if (vmx->nested.virtual_apic_page) {
7196                 nested_release_page(vmx->nested.virtual_apic_page);
7197                 vmx->nested.virtual_apic_page = NULL;
7198         }
7199         if (vmx->nested.pi_desc_page) {
7200                 kunmap(vmx->nested.pi_desc_page);
7201                 nested_release_page(vmx->nested.pi_desc_page);
7202                 vmx->nested.pi_desc_page = NULL;
7203                 vmx->nested.pi_desc = NULL;
7204         }
7205
7206         nested_free_all_saved_vmcss(vmx);
7207 }
7208
7209 /* Emulate the VMXOFF instruction */
7210 static int handle_vmoff(struct kvm_vcpu *vcpu)
7211 {
7212         if (!nested_vmx_check_permission(vcpu))
7213                 return 1;
7214         free_nested(to_vmx(vcpu));
7215         nested_vmx_succeed(vcpu);
7216         return kvm_skip_emulated_instruction(vcpu);
7217 }
7218
7219 /* Emulate the VMCLEAR instruction */
7220 static int handle_vmclear(struct kvm_vcpu *vcpu)
7221 {
7222         struct vcpu_vmx *vmx = to_vmx(vcpu);
7223         u32 zero = 0;
7224         gpa_t vmptr;
7225
7226         if (!nested_vmx_check_permission(vcpu))
7227                 return 1;
7228
7229         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7230                 return 1;
7231
7232         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7233                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7234                 return kvm_skip_emulated_instruction(vcpu);
7235         }
7236
7237         if (vmptr == vmx->nested.vmxon_ptr) {
7238                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7239                 return kvm_skip_emulated_instruction(vcpu);
7240         }
7241
7242         if (vmptr == vmx->nested.current_vmptr)
7243                 nested_release_vmcs12(vmx);
7244
7245         kvm_vcpu_write_guest(vcpu,
7246                         vmptr + offsetof(struct vmcs12, launch_state),
7247                         &zero, sizeof(zero));
7248
7249         nested_free_vmcs02(vmx, vmptr);
7250
7251         nested_vmx_succeed(vcpu);
7252         return kvm_skip_emulated_instruction(vcpu);
7253 }
7254
7255 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7256
7257 /* Emulate the VMLAUNCH instruction */
7258 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7259 {
7260         return nested_vmx_run(vcpu, true);
7261 }
7262
7263 /* Emulate the VMRESUME instruction */
7264 static int handle_vmresume(struct kvm_vcpu *vcpu)
7265 {
7266
7267         return nested_vmx_run(vcpu, false);
7268 }
7269
7270 /*
7271  * Read a vmcs12 field. Since these can have varying lengths and we return
7272  * one type, we chose the biggest type (u64) and zero-extend the return value
7273  * to that size. Note that the caller, handle_vmread, might need to use only
7274  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7275  * 64-bit fields are to be returned).
7276  */
7277 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7278                                   unsigned long field, u64 *ret)
7279 {
7280         short offset = vmcs_field_to_offset(field);
7281         char *p;
7282
7283         if (offset < 0)
7284                 return offset;
7285
7286         p = ((char *)(get_vmcs12(vcpu))) + offset;
7287
7288         switch (vmcs_field_type(field)) {
7289         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7290                 *ret = *((natural_width *)p);
7291                 return 0;
7292         case VMCS_FIELD_TYPE_U16:
7293                 *ret = *((u16 *)p);
7294                 return 0;
7295         case VMCS_FIELD_TYPE_U32:
7296                 *ret = *((u32 *)p);
7297                 return 0;
7298         case VMCS_FIELD_TYPE_U64:
7299                 *ret = *((u64 *)p);
7300                 return 0;
7301         default:
7302                 WARN_ON(1);
7303                 return -ENOENT;
7304         }
7305 }
7306
7307
7308 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7309                                    unsigned long field, u64 field_value){
7310         short offset = vmcs_field_to_offset(field);
7311         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7312         if (offset < 0)
7313                 return offset;
7314
7315         switch (vmcs_field_type(field)) {
7316         case VMCS_FIELD_TYPE_U16:
7317                 *(u16 *)p = field_value;
7318                 return 0;
7319         case VMCS_FIELD_TYPE_U32:
7320                 *(u32 *)p = field_value;
7321                 return 0;
7322         case VMCS_FIELD_TYPE_U64:
7323                 *(u64 *)p = field_value;
7324                 return 0;
7325         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7326                 *(natural_width *)p = field_value;
7327                 return 0;
7328         default:
7329                 WARN_ON(1);
7330                 return -ENOENT;
7331         }
7332
7333 }
7334
7335 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7336 {
7337         int i;
7338         unsigned long field;
7339         u64 field_value;
7340         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7341         const unsigned long *fields = shadow_read_write_fields;
7342         const int num_fields = max_shadow_read_write_fields;
7343
7344         preempt_disable();
7345
7346         vmcs_load(shadow_vmcs);
7347
7348         for (i = 0; i < num_fields; i++) {
7349                 field = fields[i];
7350                 switch (vmcs_field_type(field)) {
7351                 case VMCS_FIELD_TYPE_U16:
7352                         field_value = vmcs_read16(field);
7353                         break;
7354                 case VMCS_FIELD_TYPE_U32:
7355                         field_value = vmcs_read32(field);
7356                         break;
7357                 case VMCS_FIELD_TYPE_U64:
7358                         field_value = vmcs_read64(field);
7359                         break;
7360                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7361                         field_value = vmcs_readl(field);
7362                         break;
7363                 default:
7364                         WARN_ON(1);
7365                         continue;
7366                 }
7367                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7368         }
7369
7370         vmcs_clear(shadow_vmcs);
7371         vmcs_load(vmx->loaded_vmcs->vmcs);
7372
7373         preempt_enable();
7374 }
7375
7376 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7377 {
7378         const unsigned long *fields[] = {
7379                 shadow_read_write_fields,
7380                 shadow_read_only_fields
7381         };
7382         const int max_fields[] = {
7383                 max_shadow_read_write_fields,
7384                 max_shadow_read_only_fields
7385         };
7386         int i, q;
7387         unsigned long field;
7388         u64 field_value = 0;
7389         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7390
7391         vmcs_load(shadow_vmcs);
7392
7393         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7394                 for (i = 0; i < max_fields[q]; i++) {
7395                         field = fields[q][i];
7396                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7397
7398                         switch (vmcs_field_type(field)) {
7399                         case VMCS_FIELD_TYPE_U16:
7400                                 vmcs_write16(field, (u16)field_value);
7401                                 break;
7402                         case VMCS_FIELD_TYPE_U32:
7403                                 vmcs_write32(field, (u32)field_value);
7404                                 break;
7405                         case VMCS_FIELD_TYPE_U64:
7406                                 vmcs_write64(field, (u64)field_value);
7407                                 break;
7408                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7409                                 vmcs_writel(field, (long)field_value);
7410                                 break;
7411                         default:
7412                                 WARN_ON(1);
7413                                 break;
7414                         }
7415                 }
7416         }
7417
7418         vmcs_clear(shadow_vmcs);
7419         vmcs_load(vmx->loaded_vmcs->vmcs);
7420 }
7421
7422 /*
7423  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7424  * used before) all generate the same failure when it is missing.
7425  */
7426 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7427 {
7428         struct vcpu_vmx *vmx = to_vmx(vcpu);
7429         if (vmx->nested.current_vmptr == -1ull) {
7430                 nested_vmx_failInvalid(vcpu);
7431                 return 0;
7432         }
7433         return 1;
7434 }
7435
7436 static int handle_vmread(struct kvm_vcpu *vcpu)
7437 {
7438         unsigned long field;
7439         u64 field_value;
7440         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7441         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7442         gva_t gva = 0;
7443
7444         if (!nested_vmx_check_permission(vcpu))
7445                 return 1;
7446
7447         if (!nested_vmx_check_vmcs12(vcpu))
7448                 return kvm_skip_emulated_instruction(vcpu);
7449
7450         /* Decode instruction info and find the field to read */
7451         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7452         /* Read the field, zero-extended to a u64 field_value */
7453         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7454                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7455                 return kvm_skip_emulated_instruction(vcpu);
7456         }
7457         /*
7458          * Now copy part of this value to register or memory, as requested.
7459          * Note that the number of bits actually copied is 32 or 64 depending
7460          * on the guest's mode (32 or 64 bit), not on the given field's length.
7461          */
7462         if (vmx_instruction_info & (1u << 10)) {
7463                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7464                         field_value);
7465         } else {
7466                 if (get_vmx_mem_address(vcpu, exit_qualification,
7467                                 vmx_instruction_info, true, &gva))
7468                         return 1;
7469                 /* _system ok, as hardware has verified cpl=0 */
7470                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7471                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7472         }
7473
7474         nested_vmx_succeed(vcpu);
7475         return kvm_skip_emulated_instruction(vcpu);
7476 }
7477
7478
7479 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7480 {
7481         unsigned long field;
7482         gva_t gva;
7483         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7484         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7485         /* The value to write might be 32 or 64 bits, depending on L1's long
7486          * mode, and eventually we need to write that into a field of several
7487          * possible lengths. The code below first zero-extends the value to 64
7488          * bit (field_value), and then copies only the appropriate number of
7489          * bits into the vmcs12 field.
7490          */
7491         u64 field_value = 0;
7492         struct x86_exception e;
7493
7494         if (!nested_vmx_check_permission(vcpu))
7495                 return 1;
7496
7497         if (!nested_vmx_check_vmcs12(vcpu))
7498                 return kvm_skip_emulated_instruction(vcpu);
7499
7500         if (vmx_instruction_info & (1u << 10))
7501                 field_value = kvm_register_readl(vcpu,
7502                         (((vmx_instruction_info) >> 3) & 0xf));
7503         else {
7504                 if (get_vmx_mem_address(vcpu, exit_qualification,
7505                                 vmx_instruction_info, false, &gva))
7506                         return 1;
7507                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7508                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7509                         kvm_inject_page_fault(vcpu, &e);
7510                         return 1;
7511                 }
7512         }
7513
7514
7515         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7516         if (vmcs_field_readonly(field)) {
7517                 nested_vmx_failValid(vcpu,
7518                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7519                 return kvm_skip_emulated_instruction(vcpu);
7520         }
7521
7522         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7523                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7524                 return kvm_skip_emulated_instruction(vcpu);
7525         }
7526
7527         nested_vmx_succeed(vcpu);
7528         return kvm_skip_emulated_instruction(vcpu);
7529 }
7530
7531 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7532 {
7533         vmx->nested.current_vmptr = vmptr;
7534         if (enable_shadow_vmcs) {
7535                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7536                               SECONDARY_EXEC_SHADOW_VMCS);
7537                 vmcs_write64(VMCS_LINK_POINTER,
7538                              __pa(vmx->vmcs01.shadow_vmcs));
7539                 vmx->nested.sync_shadow_vmcs = true;
7540         }
7541 }
7542
7543 /* Emulate the VMPTRLD instruction */
7544 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7545 {
7546         struct vcpu_vmx *vmx = to_vmx(vcpu);
7547         gpa_t vmptr;
7548
7549         if (!nested_vmx_check_permission(vcpu))
7550                 return 1;
7551
7552         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7553                 return 1;
7554
7555         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7556                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7557                 return kvm_skip_emulated_instruction(vcpu);
7558         }
7559
7560         if (vmptr == vmx->nested.vmxon_ptr) {
7561                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7562                 return kvm_skip_emulated_instruction(vcpu);
7563         }
7564
7565         if (vmx->nested.current_vmptr != vmptr) {
7566                 struct vmcs12 *new_vmcs12;
7567                 struct page *page;
7568                 page = nested_get_page(vcpu, vmptr);
7569                 if (page == NULL) {
7570                         nested_vmx_failInvalid(vcpu);
7571                         return kvm_skip_emulated_instruction(vcpu);
7572                 }
7573                 new_vmcs12 = kmap(page);
7574                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7575                         kunmap(page);
7576                         nested_release_page_clean(page);
7577                         nested_vmx_failValid(vcpu,
7578                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7579                         return kvm_skip_emulated_instruction(vcpu);
7580                 }
7581
7582                 nested_release_vmcs12(vmx);
7583                 vmx->nested.current_vmcs12 = new_vmcs12;
7584                 vmx->nested.current_vmcs12_page = page;
7585                 /*
7586                  * Load VMCS12 from guest memory since it is not already
7587                  * cached.
7588                  */
7589                 memcpy(vmx->nested.cached_vmcs12,
7590                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7591                 set_current_vmptr(vmx, vmptr);
7592         }
7593
7594         nested_vmx_succeed(vcpu);
7595         return kvm_skip_emulated_instruction(vcpu);
7596 }
7597
7598 /* Emulate the VMPTRST instruction */
7599 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7600 {
7601         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7602         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7603         gva_t vmcs_gva;
7604         struct x86_exception e;
7605
7606         if (!nested_vmx_check_permission(vcpu))
7607                 return 1;
7608
7609         if (get_vmx_mem_address(vcpu, exit_qualification,
7610                         vmx_instruction_info, true, &vmcs_gva))
7611                 return 1;
7612         /* ok to use *_system, as hardware has verified cpl=0 */
7613         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7614                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7615                                  sizeof(u64), &e)) {
7616                 kvm_inject_page_fault(vcpu, &e);
7617                 return 1;
7618         }
7619         nested_vmx_succeed(vcpu);
7620         return kvm_skip_emulated_instruction(vcpu);
7621 }
7622
7623 /* Emulate the INVEPT instruction */
7624 static int handle_invept(struct kvm_vcpu *vcpu)
7625 {
7626         struct vcpu_vmx *vmx = to_vmx(vcpu);
7627         u32 vmx_instruction_info, types;
7628         unsigned long type;
7629         gva_t gva;
7630         struct x86_exception e;
7631         struct {
7632                 u64 eptp, gpa;
7633         } operand;
7634
7635         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7636               SECONDARY_EXEC_ENABLE_EPT) ||
7637             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7638                 kvm_queue_exception(vcpu, UD_VECTOR);
7639                 return 1;
7640         }
7641
7642         if (!nested_vmx_check_permission(vcpu))
7643                 return 1;
7644
7645         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7646         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7647
7648         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7649
7650         if (type >= 32 || !(types & (1 << type))) {
7651                 nested_vmx_failValid(vcpu,
7652                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7653                 return kvm_skip_emulated_instruction(vcpu);
7654         }
7655
7656         /* According to the Intel VMX instruction reference, the memory
7657          * operand is read even if it isn't needed (e.g., for type==global)
7658          */
7659         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7660                         vmx_instruction_info, false, &gva))
7661                 return 1;
7662         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7663                                 sizeof(operand), &e)) {
7664                 kvm_inject_page_fault(vcpu, &e);
7665                 return 1;
7666         }
7667
7668         switch (type) {
7669         case VMX_EPT_EXTENT_GLOBAL:
7670         /*
7671          * TODO: track mappings and invalidate
7672          * single context requests appropriately
7673          */
7674         case VMX_EPT_EXTENT_CONTEXT:
7675                 kvm_mmu_sync_roots(vcpu);
7676                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7677                 nested_vmx_succeed(vcpu);
7678                 break;
7679         default:
7680                 BUG_ON(1);
7681                 break;
7682         }
7683
7684         return kvm_skip_emulated_instruction(vcpu);
7685 }
7686
7687 static int handle_invvpid(struct kvm_vcpu *vcpu)
7688 {
7689         struct vcpu_vmx *vmx = to_vmx(vcpu);
7690         u32 vmx_instruction_info;
7691         unsigned long type, types;
7692         gva_t gva;
7693         struct x86_exception e;
7694         struct {
7695                 u64 vpid;
7696                 u64 gla;
7697         } operand;
7698
7699         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7700               SECONDARY_EXEC_ENABLE_VPID) ||
7701                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7702                 kvm_queue_exception(vcpu, UD_VECTOR);
7703                 return 1;
7704         }
7705
7706         if (!nested_vmx_check_permission(vcpu))
7707                 return 1;
7708
7709         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7710         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7711
7712         types = (vmx->nested.nested_vmx_vpid_caps &
7713                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7714
7715         if (type >= 32 || !(types & (1 << type))) {
7716                 nested_vmx_failValid(vcpu,
7717                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7718                 return kvm_skip_emulated_instruction(vcpu);
7719         }
7720
7721         /* according to the intel vmx instruction reference, the memory
7722          * operand is read even if it isn't needed (e.g., for type==global)
7723          */
7724         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7725                         vmx_instruction_info, false, &gva))
7726                 return 1;
7727         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7728                                 sizeof(operand), &e)) {
7729                 kvm_inject_page_fault(vcpu, &e);
7730                 return 1;
7731         }
7732         if (operand.vpid >> 16) {
7733                 nested_vmx_failValid(vcpu,
7734                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7735                 return kvm_skip_emulated_instruction(vcpu);
7736         }
7737
7738         switch (type) {
7739         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7740                 if (is_noncanonical_address(operand.gla)) {
7741                         nested_vmx_failValid(vcpu,
7742                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7743                         return kvm_skip_emulated_instruction(vcpu);
7744                 }
7745                 /* fall through */
7746         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7747         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7748                 if (!operand.vpid) {
7749                         nested_vmx_failValid(vcpu,
7750                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7751                         return kvm_skip_emulated_instruction(vcpu);
7752                 }
7753                 break;
7754         case VMX_VPID_EXTENT_ALL_CONTEXT:
7755                 break;
7756         default:
7757                 WARN_ON_ONCE(1);
7758                 return kvm_skip_emulated_instruction(vcpu);
7759         }
7760
7761         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7762         nested_vmx_succeed(vcpu);
7763
7764         return kvm_skip_emulated_instruction(vcpu);
7765 }
7766
7767 static int handle_pml_full(struct kvm_vcpu *vcpu)
7768 {
7769         unsigned long exit_qualification;
7770
7771         trace_kvm_pml_full(vcpu->vcpu_id);
7772
7773         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7774
7775         /*
7776          * PML buffer FULL happened while executing iret from NMI,
7777          * "blocked by NMI" bit has to be set before next VM entry.
7778          */
7779         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7780                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7781                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7782                                 GUEST_INTR_STATE_NMI);
7783
7784         /*
7785          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7786          * here.., and there's no userspace involvement needed for PML.
7787          */
7788         return 1;
7789 }
7790
7791 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7792 {
7793         kvm_lapic_expired_hv_timer(vcpu);
7794         return 1;
7795 }
7796
7797 /*
7798  * The exit handlers return 1 if the exit was handled fully and guest execution
7799  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7800  * to be done to userspace and return 0.
7801  */
7802 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7803         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7804         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7805         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7806         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7807         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7808         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7809         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7810         [EXIT_REASON_CPUID]                   = handle_cpuid,
7811         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7812         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7813         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7814         [EXIT_REASON_HLT]                     = handle_halt,
7815         [EXIT_REASON_INVD]                    = handle_invd,
7816         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7817         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7818         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7819         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7820         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7821         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7822         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7823         [EXIT_REASON_VMREAD]                  = handle_vmread,
7824         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7825         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7826         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7827         [EXIT_REASON_VMON]                    = handle_vmon,
7828         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7829         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7830         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7831         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7832         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7833         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7834         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7835         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7836         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7837         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7838         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7839         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7840         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7841         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7842         [EXIT_REASON_INVEPT]                  = handle_invept,
7843         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7844         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7845         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7846         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7847         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7848 };
7849
7850 static const int kvm_vmx_max_exit_handlers =
7851         ARRAY_SIZE(kvm_vmx_exit_handlers);
7852
7853 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7854                                        struct vmcs12 *vmcs12)
7855 {
7856         unsigned long exit_qualification;
7857         gpa_t bitmap, last_bitmap;
7858         unsigned int port;
7859         int size;
7860         u8 b;
7861
7862         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7863                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7864
7865         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7866
7867         port = exit_qualification >> 16;
7868         size = (exit_qualification & 7) + 1;
7869
7870         last_bitmap = (gpa_t)-1;
7871         b = -1;
7872
7873         while (size > 0) {
7874                 if (port < 0x8000)
7875                         bitmap = vmcs12->io_bitmap_a;
7876                 else if (port < 0x10000)
7877                         bitmap = vmcs12->io_bitmap_b;
7878                 else
7879                         return true;
7880                 bitmap += (port & 0x7fff) / 8;
7881
7882                 if (last_bitmap != bitmap)
7883                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7884                                 return true;
7885                 if (b & (1 << (port & 7)))
7886                         return true;
7887
7888                 port++;
7889                 size--;
7890                 last_bitmap = bitmap;
7891         }
7892
7893         return false;
7894 }
7895
7896 /*
7897  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7898  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7899  * disinterest in the current event (read or write a specific MSR) by using an
7900  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7901  */
7902 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7903         struct vmcs12 *vmcs12, u32 exit_reason)
7904 {
7905         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7906         gpa_t bitmap;
7907
7908         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7909                 return true;
7910
7911         /*
7912          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7913          * for the four combinations of read/write and low/high MSR numbers.
7914          * First we need to figure out which of the four to use:
7915          */
7916         bitmap = vmcs12->msr_bitmap;
7917         if (exit_reason == EXIT_REASON_MSR_WRITE)
7918                 bitmap += 2048;
7919         if (msr_index >= 0xc0000000) {
7920                 msr_index -= 0xc0000000;
7921                 bitmap += 1024;
7922         }
7923
7924         /* Then read the msr_index'th bit from this bitmap: */
7925         if (msr_index < 1024*8) {
7926                 unsigned char b;
7927                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7928                         return true;
7929                 return 1 & (b >> (msr_index & 7));
7930         } else
7931                 return true; /* let L1 handle the wrong parameter */
7932 }
7933
7934 /*
7935  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7936  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7937  * intercept (via guest_host_mask etc.) the current event.
7938  */
7939 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7940         struct vmcs12 *vmcs12)
7941 {
7942         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7943         int cr = exit_qualification & 15;
7944         int reg;
7945         unsigned long val;
7946
7947         switch ((exit_qualification >> 4) & 3) {
7948         case 0: /* mov to cr */
7949                 reg = (exit_qualification >> 8) & 15;
7950                 val = kvm_register_readl(vcpu, reg);
7951                 switch (cr) {
7952                 case 0:
7953                         if (vmcs12->cr0_guest_host_mask &
7954                             (val ^ vmcs12->cr0_read_shadow))
7955                                 return true;
7956                         break;
7957                 case 3:
7958                         if ((vmcs12->cr3_target_count >= 1 &&
7959                                         vmcs12->cr3_target_value0 == val) ||
7960                                 (vmcs12->cr3_target_count >= 2 &&
7961                                         vmcs12->cr3_target_value1 == val) ||
7962                                 (vmcs12->cr3_target_count >= 3 &&
7963                                         vmcs12->cr3_target_value2 == val) ||
7964                                 (vmcs12->cr3_target_count >= 4 &&
7965                                         vmcs12->cr3_target_value3 == val))
7966                                 return false;
7967                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7968                                 return true;
7969                         break;
7970                 case 4:
7971                         if (vmcs12->cr4_guest_host_mask &
7972                             (vmcs12->cr4_read_shadow ^ val))
7973                                 return true;
7974                         break;
7975                 case 8:
7976                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7977                                 return true;
7978                         break;
7979                 }
7980                 break;
7981         case 2: /* clts */
7982                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7983                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7984                         return true;
7985                 break;
7986         case 1: /* mov from cr */
7987                 switch (cr) {
7988                 case 3:
7989                         if (vmcs12->cpu_based_vm_exec_control &
7990                             CPU_BASED_CR3_STORE_EXITING)
7991                                 return true;
7992                         break;
7993                 case 8:
7994                         if (vmcs12->cpu_based_vm_exec_control &
7995                             CPU_BASED_CR8_STORE_EXITING)
7996                                 return true;
7997                         break;
7998                 }
7999                 break;
8000         case 3: /* lmsw */
8001                 /*
8002                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8003                  * cr0. Other attempted changes are ignored, with no exit.
8004                  */
8005                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8006                 if (vmcs12->cr0_guest_host_mask & 0xe &
8007                     (val ^ vmcs12->cr0_read_shadow))
8008                         return true;
8009                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8010                     !(vmcs12->cr0_read_shadow & 0x1) &&
8011                     (val & 0x1))
8012                         return true;
8013                 break;
8014         }
8015         return false;
8016 }
8017
8018 /*
8019  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8020  * should handle it ourselves in L0 (and then continue L2). Only call this
8021  * when in is_guest_mode (L2).
8022  */
8023 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8024 {
8025         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8026         struct vcpu_vmx *vmx = to_vmx(vcpu);
8027         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8028
8029         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8030                                 vmcs_readl(EXIT_QUALIFICATION),
8031                                 vmx->idt_vectoring_info,
8032                                 intr_info,
8033                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8034                                 KVM_ISA_VMX);
8035
8036         if (vmx->nested.nested_run_pending)
8037                 return false;
8038
8039         if (unlikely(vmx->fail)) {
8040                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8041                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8042                 return true;
8043         }
8044
8045         switch (exit_reason) {
8046         case EXIT_REASON_EXCEPTION_NMI:
8047                 if (is_nmi(intr_info))
8048                         return false;
8049                 else if (is_page_fault(intr_info))
8050                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8051                 else if (is_no_device(intr_info) &&
8052                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8053                         return false;
8054                 else if (is_debug(intr_info) &&
8055                          vcpu->guest_debug &
8056                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8057                         return false;
8058                 else if (is_breakpoint(intr_info) &&
8059                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8060                         return false;
8061                 return vmcs12->exception_bitmap &
8062                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8063         case EXIT_REASON_EXTERNAL_INTERRUPT:
8064                 return false;
8065         case EXIT_REASON_TRIPLE_FAULT:
8066                 return true;
8067         case EXIT_REASON_PENDING_INTERRUPT:
8068                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8069         case EXIT_REASON_NMI_WINDOW:
8070                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8071         case EXIT_REASON_TASK_SWITCH:
8072                 return true;
8073         case EXIT_REASON_CPUID:
8074                 return true;
8075         case EXIT_REASON_HLT:
8076                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8077         case EXIT_REASON_INVD:
8078                 return true;
8079         case EXIT_REASON_INVLPG:
8080                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8081         case EXIT_REASON_RDPMC:
8082                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8083         case EXIT_REASON_RDRAND:
8084                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8085         case EXIT_REASON_RDSEED:
8086                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8087         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8088                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8089         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8090         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8091         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8092         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8093         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8094         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8095                 /*
8096                  * VMX instructions trap unconditionally. This allows L1 to
8097                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8098                  */
8099                 return true;
8100         case EXIT_REASON_CR_ACCESS:
8101                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8102         case EXIT_REASON_DR_ACCESS:
8103                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8104         case EXIT_REASON_IO_INSTRUCTION:
8105                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8106         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8107                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8108         case EXIT_REASON_MSR_READ:
8109         case EXIT_REASON_MSR_WRITE:
8110                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8111         case EXIT_REASON_INVALID_STATE:
8112                 return true;
8113         case EXIT_REASON_MWAIT_INSTRUCTION:
8114                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8115         case EXIT_REASON_MONITOR_TRAP_FLAG:
8116                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8117         case EXIT_REASON_MONITOR_INSTRUCTION:
8118                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8119         case EXIT_REASON_PAUSE_INSTRUCTION:
8120                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8121                         nested_cpu_has2(vmcs12,
8122                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8123         case EXIT_REASON_MCE_DURING_VMENTRY:
8124                 return false;
8125         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8126                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8127         case EXIT_REASON_APIC_ACCESS:
8128                 return nested_cpu_has2(vmcs12,
8129                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8130         case EXIT_REASON_APIC_WRITE:
8131         case EXIT_REASON_EOI_INDUCED:
8132                 /* apic_write and eoi_induced should exit unconditionally. */
8133                 return true;
8134         case EXIT_REASON_EPT_VIOLATION:
8135                 /*
8136                  * L0 always deals with the EPT violation. If nested EPT is
8137                  * used, and the nested mmu code discovers that the address is
8138                  * missing in the guest EPT table (EPT12), the EPT violation
8139                  * will be injected with nested_ept_inject_page_fault()
8140                  */
8141                 return false;
8142         case EXIT_REASON_EPT_MISCONFIG:
8143                 /*
8144                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8145                  * table (shadow on EPT) or a merged EPT table that L0 built
8146                  * (EPT on EPT). So any problems with the structure of the
8147                  * table is L0's fault.
8148                  */
8149                 return false;
8150         case EXIT_REASON_WBINVD:
8151                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8152         case EXIT_REASON_XSETBV:
8153                 return true;
8154         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8155                 /*
8156                  * This should never happen, since it is not possible to
8157                  * set XSS to a non-zero value---neither in L1 nor in L2.
8158                  * If if it were, XSS would have to be checked against
8159                  * the XSS exit bitmap in vmcs12.
8160                  */
8161                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8162         case EXIT_REASON_PREEMPTION_TIMER:
8163                 return false;
8164         case EXIT_REASON_PML_FULL:
8165                 /* We emulate PML support to L1. */
8166                 return false;
8167         default:
8168                 return true;
8169         }
8170 }
8171
8172 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8173 {
8174         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8175
8176         /*
8177          * At this point, the exit interruption info in exit_intr_info
8178          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
8179          * we need to query the in-kernel LAPIC.
8180          */
8181         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8182         if ((exit_intr_info &
8183              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8184             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8185                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8186                 vmcs12->vm_exit_intr_error_code =
8187                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8188         }
8189
8190         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8191                           vmcs_readl(EXIT_QUALIFICATION));
8192         return 1;
8193 }
8194
8195 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8196 {
8197         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8198         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8199 }
8200
8201 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8202 {
8203         if (vmx->pml_pg) {
8204                 __free_page(vmx->pml_pg);
8205                 vmx->pml_pg = NULL;
8206         }
8207 }
8208
8209 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8210 {
8211         struct vcpu_vmx *vmx = to_vmx(vcpu);
8212         u64 *pml_buf;
8213         u16 pml_idx;
8214
8215         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8216
8217         /* Do nothing if PML buffer is empty */
8218         if (pml_idx == (PML_ENTITY_NUM - 1))
8219                 return;
8220
8221         /* PML index always points to next available PML buffer entity */
8222         if (pml_idx >= PML_ENTITY_NUM)
8223                 pml_idx = 0;
8224         else
8225                 pml_idx++;
8226
8227         pml_buf = page_address(vmx->pml_pg);
8228         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8229                 u64 gpa;
8230
8231                 gpa = pml_buf[pml_idx];
8232                 WARN_ON(gpa & (PAGE_SIZE - 1));
8233                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8234         }
8235
8236         /* reset PML index */
8237         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8238 }
8239
8240 /*
8241  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8242  * Called before reporting dirty_bitmap to userspace.
8243  */
8244 static void kvm_flush_pml_buffers(struct kvm *kvm)
8245 {
8246         int i;
8247         struct kvm_vcpu *vcpu;
8248         /*
8249          * We only need to kick vcpu out of guest mode here, as PML buffer
8250          * is flushed at beginning of all VMEXITs, and it's obvious that only
8251          * vcpus running in guest are possible to have unflushed GPAs in PML
8252          * buffer.
8253          */
8254         kvm_for_each_vcpu(i, vcpu, kvm)
8255                 kvm_vcpu_kick(vcpu);
8256 }
8257
8258 static void vmx_dump_sel(char *name, uint32_t sel)
8259 {
8260         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8261                name, vmcs_read16(sel),
8262                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8263                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8264                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8265 }
8266
8267 static void vmx_dump_dtsel(char *name, uint32_t limit)
8268 {
8269         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8270                name, vmcs_read32(limit),
8271                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8272 }
8273
8274 static void dump_vmcs(void)
8275 {
8276         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8277         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8278         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8279         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8280         u32 secondary_exec_control = 0;
8281         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8282         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8283         int i, n;
8284
8285         if (cpu_has_secondary_exec_ctrls())
8286                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8287
8288         pr_err("*** Guest State ***\n");
8289         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8290                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8291                vmcs_readl(CR0_GUEST_HOST_MASK));
8292         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8293                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8294         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8295         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8296             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8297         {
8298                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8299                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8300                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8301                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8302         }
8303         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8304                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8305         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8306                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8307         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8308                vmcs_readl(GUEST_SYSENTER_ESP),
8309                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8310         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8311         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8312         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8313         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8314         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8315         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8316         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8317         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8318         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8319         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8320         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8321             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8322                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8323                        efer, vmcs_read64(GUEST_IA32_PAT));
8324         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8325                vmcs_read64(GUEST_IA32_DEBUGCTL),
8326                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8327         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8328                 pr_err("PerfGlobCtl = 0x%016llx\n",
8329                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8330         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8331                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8332         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8333                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8334                vmcs_read32(GUEST_ACTIVITY_STATE));
8335         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8336                 pr_err("InterruptStatus = %04x\n",
8337                        vmcs_read16(GUEST_INTR_STATUS));
8338
8339         pr_err("*** Host State ***\n");
8340         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8341                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8342         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8343                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8344                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8345                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8346                vmcs_read16(HOST_TR_SELECTOR));
8347         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8348                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8349                vmcs_readl(HOST_TR_BASE));
8350         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8351                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8352         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8353                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8354                vmcs_readl(HOST_CR4));
8355         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8356                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8357                vmcs_read32(HOST_IA32_SYSENTER_CS),
8358                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8359         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8360                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8361                        vmcs_read64(HOST_IA32_EFER),
8362                        vmcs_read64(HOST_IA32_PAT));
8363         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8364                 pr_err("PerfGlobCtl = 0x%016llx\n",
8365                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8366
8367         pr_err("*** Control State ***\n");
8368         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8369                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8370         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8371         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8372                vmcs_read32(EXCEPTION_BITMAP),
8373                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8374                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8375         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8376                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8377                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8378                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8379         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8380                vmcs_read32(VM_EXIT_INTR_INFO),
8381                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8382                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8383         pr_err("        reason=%08x qualification=%016lx\n",
8384                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8385         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8386                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8387                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8388         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8389         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8390                 pr_err("TSC Multiplier = 0x%016llx\n",
8391                        vmcs_read64(TSC_MULTIPLIER));
8392         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8393                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8394         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8395                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8396         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8397                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8398         n = vmcs_read32(CR3_TARGET_COUNT);
8399         for (i = 0; i + 1 < n; i += 4)
8400                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8401                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8402                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8403         if (i < n)
8404                 pr_err("CR3 target%u=%016lx\n",
8405                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8406         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8407                 pr_err("PLE Gap=%08x Window=%08x\n",
8408                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8409         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8410                 pr_err("Virtual processor ID = 0x%04x\n",
8411                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8412 }
8413
8414 /*
8415  * The guest has exited.  See if we can fix it or if we need userspace
8416  * assistance.
8417  */
8418 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8419 {
8420         struct vcpu_vmx *vmx = to_vmx(vcpu);
8421         u32 exit_reason = vmx->exit_reason;
8422         u32 vectoring_info = vmx->idt_vectoring_info;
8423
8424         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8425         vcpu->arch.gpa_available = false;
8426
8427         /*
8428          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8429          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8430          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8431          * mode as if vcpus is in root mode, the PML buffer must has been
8432          * flushed already.
8433          */
8434         if (enable_pml)
8435                 vmx_flush_pml_buffer(vcpu);
8436
8437         /* If guest state is invalid, start emulating */
8438         if (vmx->emulation_required)
8439                 return handle_invalid_guest_state(vcpu);
8440
8441         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
8442                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
8443
8444         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8445                 dump_vmcs();
8446                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8447                 vcpu->run->fail_entry.hardware_entry_failure_reason
8448                         = exit_reason;
8449                 return 0;
8450         }
8451
8452         if (unlikely(vmx->fail)) {
8453                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8454                 vcpu->run->fail_entry.hardware_entry_failure_reason
8455                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8456                 return 0;
8457         }
8458
8459         /*
8460          * Note:
8461          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8462          * delivery event since it indicates guest is accessing MMIO.
8463          * The vm-exit can be triggered again after return to guest that
8464          * will cause infinite loop.
8465          */
8466         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8467                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8468                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8469                         exit_reason != EXIT_REASON_PML_FULL &&
8470                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8471                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8472                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8473                 vcpu->run->internal.ndata = 3;
8474                 vcpu->run->internal.data[0] = vectoring_info;
8475                 vcpu->run->internal.data[1] = exit_reason;
8476                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8477                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8478                         vcpu->run->internal.ndata++;
8479                         vcpu->run->internal.data[3] =
8480                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8481                 }
8482                 return 0;
8483         }
8484
8485         if (exit_reason < kvm_vmx_max_exit_handlers
8486             && kvm_vmx_exit_handlers[exit_reason])
8487                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8488         else {
8489                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8490                                 exit_reason);
8491                 kvm_queue_exception(vcpu, UD_VECTOR);
8492                 return 1;
8493         }
8494 }
8495
8496 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8497 {
8498         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8499
8500         if (is_guest_mode(vcpu) &&
8501                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8502                 return;
8503
8504         if (irr == -1 || tpr < irr) {
8505                 vmcs_write32(TPR_THRESHOLD, 0);
8506                 return;
8507         }
8508
8509         vmcs_write32(TPR_THRESHOLD, irr);
8510 }
8511
8512 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8513 {
8514         u32 sec_exec_control;
8515
8516         /* Postpone execution until vmcs01 is the current VMCS. */
8517         if (is_guest_mode(vcpu)) {
8518                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8519                 return;
8520         }
8521
8522         if (!cpu_has_vmx_virtualize_x2apic_mode())
8523                 return;
8524
8525         if (!cpu_need_tpr_shadow(vcpu))
8526                 return;
8527
8528         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8529
8530         if (set) {
8531                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8532                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8533         } else {
8534                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8535                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8536                 vmx_flush_tlb_ept_only(vcpu);
8537         }
8538         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8539
8540         vmx_set_msr_bitmap(vcpu);
8541 }
8542
8543 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8544 {
8545         struct vcpu_vmx *vmx = to_vmx(vcpu);
8546
8547         /*
8548          * Currently we do not handle the nested case where L2 has an
8549          * APIC access page of its own; that page is still pinned.
8550          * Hence, we skip the case where the VCPU is in guest mode _and_
8551          * L1 prepared an APIC access page for L2.
8552          *
8553          * For the case where L1 and L2 share the same APIC access page
8554          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8555          * in the vmcs12), this function will only update either the vmcs01
8556          * or the vmcs02.  If the former, the vmcs02 will be updated by
8557          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8558          * the next L2->L1 exit.
8559          */
8560         if (!is_guest_mode(vcpu) ||
8561             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8562                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8563                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8564                 vmx_flush_tlb_ept_only(vcpu);
8565         }
8566 }
8567
8568 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8569 {
8570         u16 status;
8571         u8 old;
8572
8573         if (max_isr == -1)
8574                 max_isr = 0;
8575
8576         status = vmcs_read16(GUEST_INTR_STATUS);
8577         old = status >> 8;
8578         if (max_isr != old) {
8579                 status &= 0xff;
8580                 status |= max_isr << 8;
8581                 vmcs_write16(GUEST_INTR_STATUS, status);
8582         }
8583 }
8584
8585 static void vmx_set_rvi(int vector)
8586 {
8587         u16 status;
8588         u8 old;
8589
8590         if (vector == -1)
8591                 vector = 0;
8592
8593         status = vmcs_read16(GUEST_INTR_STATUS);
8594         old = (u8)status & 0xff;
8595         if ((u8)vector != old) {
8596                 status &= ~0xff;
8597                 status |= (u8)vector;
8598                 vmcs_write16(GUEST_INTR_STATUS, status);
8599         }
8600 }
8601
8602 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8603 {
8604         if (!is_guest_mode(vcpu)) {
8605                 vmx_set_rvi(max_irr);
8606                 return;
8607         }
8608
8609         if (max_irr == -1)
8610                 return;
8611
8612         /*
8613          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8614          * handles it.
8615          */
8616         if (nested_exit_on_intr(vcpu))
8617                 return;
8618
8619         /*
8620          * Else, fall back to pre-APICv interrupt injection since L2
8621          * is run without virtual interrupt delivery.
8622          */
8623         if (!kvm_event_needs_reinjection(vcpu) &&
8624             vmx_interrupt_allowed(vcpu)) {
8625                 kvm_queue_interrupt(vcpu, max_irr, false);
8626                 vmx_inject_irq(vcpu);
8627         }
8628 }
8629
8630 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8631 {
8632         struct vcpu_vmx *vmx = to_vmx(vcpu);
8633         int max_irr;
8634
8635         WARN_ON(!vcpu->arch.apicv_active);
8636         if (pi_test_on(&vmx->pi_desc)) {
8637                 pi_clear_on(&vmx->pi_desc);
8638                 /*
8639                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8640                  * But on x86 this is just a compiler barrier anyway.
8641                  */
8642                 smp_mb__after_atomic();
8643                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8644         } else {
8645                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8646         }
8647         vmx_hwapic_irr_update(vcpu, max_irr);
8648         return max_irr;
8649 }
8650
8651 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8652 {
8653         if (!kvm_vcpu_apicv_active(vcpu))
8654                 return;
8655
8656         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8657         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8658         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8659         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8660 }
8661
8662 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8663 {
8664         struct vcpu_vmx *vmx = to_vmx(vcpu);
8665
8666         pi_clear_on(&vmx->pi_desc);
8667         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8668 }
8669
8670 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8671 {
8672         u32 exit_intr_info = 0;
8673         u16 basic_exit_reason = (u16)vmx->exit_reason;
8674
8675         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8676               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
8677                 return;
8678
8679         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
8680                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8681         vmx->exit_intr_info = exit_intr_info;
8682
8683         /* if exit due to PF check for async PF */
8684         if (is_page_fault(exit_intr_info))
8685                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
8686
8687         /* Handle machine checks before interrupts are enabled */
8688         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
8689             is_machine_check(exit_intr_info))
8690                 kvm_machine_check();
8691
8692         /* We need to handle NMIs before interrupts are enabled */
8693         if (is_nmi(exit_intr_info)) {
8694                 kvm_before_handle_nmi(&vmx->vcpu);
8695                 asm("int $2");
8696                 kvm_after_handle_nmi(&vmx->vcpu);
8697         }
8698 }
8699
8700 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8701 {
8702         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8703         register void *__sp asm(_ASM_SP);
8704
8705         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8706                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8707                 unsigned int vector;
8708                 unsigned long entry;
8709                 gate_desc *desc;
8710                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8711 #ifdef CONFIG_X86_64
8712                 unsigned long tmp;
8713 #endif
8714
8715                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8716                 desc = (gate_desc *)vmx->host_idt_base + vector;
8717                 entry = gate_offset(*desc);
8718                 asm volatile(
8719 #ifdef CONFIG_X86_64
8720                         "mov %%" _ASM_SP ", %[sp]\n\t"
8721                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8722                         "push $%c[ss]\n\t"
8723                         "push %[sp]\n\t"
8724 #endif
8725                         "pushf\n\t"
8726                         __ASM_SIZE(push) " $%c[cs]\n\t"
8727                         "call *%[entry]\n\t"
8728                         :
8729 #ifdef CONFIG_X86_64
8730                         [sp]"=&r"(tmp),
8731 #endif
8732                         "+r"(__sp)
8733                         :
8734                         [entry]"r"(entry),
8735                         [ss]"i"(__KERNEL_DS),
8736                         [cs]"i"(__KERNEL_CS)
8737                         );
8738         }
8739 }
8740 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
8741
8742 static bool vmx_has_high_real_mode_segbase(void)
8743 {
8744         return enable_unrestricted_guest || emulate_invalid_guest_state;
8745 }
8746
8747 static bool vmx_mpx_supported(void)
8748 {
8749         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8750                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8751 }
8752
8753 static bool vmx_xsaves_supported(void)
8754 {
8755         return vmcs_config.cpu_based_2nd_exec_ctrl &
8756                 SECONDARY_EXEC_XSAVES;
8757 }
8758
8759 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8760 {
8761         u32 exit_intr_info;
8762         bool unblock_nmi;
8763         u8 vector;
8764         bool idtv_info_valid;
8765
8766         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8767
8768         if (vmx->loaded_vmcs->nmi_known_unmasked)
8769                 return;
8770         /*
8771          * Can't use vmx->exit_intr_info since we're not sure what
8772          * the exit reason is.
8773          */
8774         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8775         unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8776         vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8777         /*
8778          * SDM 3: 27.7.1.2 (September 2008)
8779          * Re-set bit "block by NMI" before VM entry if vmexit caused by
8780          * a guest IRET fault.
8781          * SDM 3: 23.2.2 (September 2008)
8782          * Bit 12 is undefined in any of the following cases:
8783          *  If the VM exit sets the valid bit in the IDT-vectoring
8784          *   information field.
8785          *  If the VM exit is due to a double fault.
8786          */
8787         if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8788             vector != DF_VECTOR && !idtv_info_valid)
8789                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8790                               GUEST_INTR_STATE_NMI);
8791         else
8792                 vmx->loaded_vmcs->nmi_known_unmasked =
8793                         !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8794                           & GUEST_INTR_STATE_NMI);
8795 }
8796
8797 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8798                                       u32 idt_vectoring_info,
8799                                       int instr_len_field,
8800                                       int error_code_field)
8801 {
8802         u8 vector;
8803         int type;
8804         bool idtv_info_valid;
8805
8806         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8807
8808         vcpu->arch.nmi_injected = false;
8809         kvm_clear_exception_queue(vcpu);
8810         kvm_clear_interrupt_queue(vcpu);
8811
8812         if (!idtv_info_valid)
8813                 return;
8814
8815         kvm_make_request(KVM_REQ_EVENT, vcpu);
8816
8817         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8818         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8819
8820         switch (type) {
8821         case INTR_TYPE_NMI_INTR:
8822                 vcpu->arch.nmi_injected = true;
8823                 /*
8824                  * SDM 3: 27.7.1.2 (September 2008)
8825                  * Clear bit "block by NMI" before VM entry if a NMI
8826                  * delivery faulted.
8827                  */
8828                 vmx_set_nmi_mask(vcpu, false);
8829                 break;
8830         case INTR_TYPE_SOFT_EXCEPTION:
8831                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8832                 /* fall through */
8833         case INTR_TYPE_HARD_EXCEPTION:
8834                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8835                         u32 err = vmcs_read32(error_code_field);
8836                         kvm_requeue_exception_e(vcpu, vector, err);
8837                 } else
8838                         kvm_requeue_exception(vcpu, vector);
8839                 break;
8840         case INTR_TYPE_SOFT_INTR:
8841                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8842                 /* fall through */
8843         case INTR_TYPE_EXT_INTR:
8844                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8845                 break;
8846         default:
8847                 break;
8848         }
8849 }
8850
8851 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8852 {
8853         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8854                                   VM_EXIT_INSTRUCTION_LEN,
8855                                   IDT_VECTORING_ERROR_CODE);
8856 }
8857
8858 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8859 {
8860         __vmx_complete_interrupts(vcpu,
8861                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8862                                   VM_ENTRY_INSTRUCTION_LEN,
8863                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8864
8865         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8866 }
8867
8868 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8869 {
8870         int i, nr_msrs;
8871         struct perf_guest_switch_msr *msrs;
8872
8873         msrs = perf_guest_get_msrs(&nr_msrs);
8874
8875         if (!msrs)
8876                 return;
8877
8878         for (i = 0; i < nr_msrs; i++)
8879                 if (msrs[i].host == msrs[i].guest)
8880                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8881                 else
8882                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8883                                         msrs[i].host);
8884 }
8885
8886 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8887 {
8888         struct vcpu_vmx *vmx = to_vmx(vcpu);
8889         u64 tscl;
8890         u32 delta_tsc;
8891
8892         if (vmx->hv_deadline_tsc == -1)
8893                 return;
8894
8895         tscl = rdtsc();
8896         if (vmx->hv_deadline_tsc > tscl)
8897                 /* sure to be 32 bit only because checked on set_hv_timer */
8898                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8899                         cpu_preemption_timer_multi);
8900         else
8901                 delta_tsc = 0;
8902
8903         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8904 }
8905
8906 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8907 {
8908         struct vcpu_vmx *vmx = to_vmx(vcpu);
8909         unsigned long debugctlmsr, cr3, cr4;
8910
8911         /* Don't enter VMX if guest state is invalid, let the exit handler
8912            start emulation until we arrive back to a valid state */
8913         if (vmx->emulation_required)
8914                 return;
8915
8916         if (vmx->ple_window_dirty) {
8917                 vmx->ple_window_dirty = false;
8918                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8919         }
8920
8921         if (vmx->nested.sync_shadow_vmcs) {
8922                 copy_vmcs12_to_shadow(vmx);
8923                 vmx->nested.sync_shadow_vmcs = false;
8924         }
8925
8926         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8927                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8928         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8929                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8930
8931         cr3 = __get_current_cr3_fast();
8932         if (unlikely(cr3 != vmx->host_state.vmcs_host_cr3)) {
8933                 vmcs_writel(HOST_CR3, cr3);
8934                 vmx->host_state.vmcs_host_cr3 = cr3;
8935         }
8936
8937         cr4 = cr4_read_shadow();
8938         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8939                 vmcs_writel(HOST_CR4, cr4);
8940                 vmx->host_state.vmcs_host_cr4 = cr4;
8941         }
8942
8943         /* When single-stepping over STI and MOV SS, we must clear the
8944          * corresponding interruptibility bits in the guest state. Otherwise
8945          * vmentry fails as it then expects bit 14 (BS) in pending debug
8946          * exceptions being set, but that's not correct for the guest debugging
8947          * case. */
8948         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8949                 vmx_set_interrupt_shadow(vcpu, 0);
8950
8951         if (vmx->guest_pkru_valid)
8952                 __write_pkru(vmx->guest_pkru);
8953
8954         atomic_switch_perf_msrs(vmx);
8955         debugctlmsr = get_debugctlmsr();
8956
8957         vmx_arm_hv_timer(vcpu);
8958
8959         vmx->__launched = vmx->loaded_vmcs->launched;
8960         asm(
8961                 /* Store host registers */
8962                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8963                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8964                 "push %%" _ASM_CX " \n\t"
8965                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8966                 "je 1f \n\t"
8967                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8968                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8969                 "1: \n\t"
8970                 /* Reload cr2 if changed */
8971                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8972                 "mov %%cr2, %%" _ASM_DX " \n\t"
8973                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8974                 "je 2f \n\t"
8975                 "mov %%" _ASM_AX", %%cr2 \n\t"
8976                 "2: \n\t"
8977                 /* Check if vmlaunch of vmresume is needed */
8978                 "cmpl $0, %c[launched](%0) \n\t"
8979                 /* Load guest registers.  Don't clobber flags. */
8980                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8981                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8982                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8983                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8984                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8985                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8986 #ifdef CONFIG_X86_64
8987                 "mov %c[r8](%0),  %%r8  \n\t"
8988                 "mov %c[r9](%0),  %%r9  \n\t"
8989                 "mov %c[r10](%0), %%r10 \n\t"
8990                 "mov %c[r11](%0), %%r11 \n\t"
8991                 "mov %c[r12](%0), %%r12 \n\t"
8992                 "mov %c[r13](%0), %%r13 \n\t"
8993                 "mov %c[r14](%0), %%r14 \n\t"
8994                 "mov %c[r15](%0), %%r15 \n\t"
8995 #endif
8996                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8997
8998                 /* Enter guest mode */
8999                 "jne 1f \n\t"
9000                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9001                 "jmp 2f \n\t"
9002                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9003                 "2: "
9004                 /* Save guest registers, load host registers, keep flags */
9005                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9006                 "pop %0 \n\t"
9007                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9008                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9009                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9010                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9011                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9012                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9013                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9014 #ifdef CONFIG_X86_64
9015                 "mov %%r8,  %c[r8](%0) \n\t"
9016                 "mov %%r9,  %c[r9](%0) \n\t"
9017                 "mov %%r10, %c[r10](%0) \n\t"
9018                 "mov %%r11, %c[r11](%0) \n\t"
9019                 "mov %%r12, %c[r12](%0) \n\t"
9020                 "mov %%r13, %c[r13](%0) \n\t"
9021                 "mov %%r14, %c[r14](%0) \n\t"
9022                 "mov %%r15, %c[r15](%0) \n\t"
9023 #endif
9024                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9025                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9026
9027                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9028                 "setbe %c[fail](%0) \n\t"
9029                 ".pushsection .rodata \n\t"
9030                 ".global vmx_return \n\t"
9031                 "vmx_return: " _ASM_PTR " 2b \n\t"
9032                 ".popsection"
9033               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9034                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9035                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9036                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9037                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9038                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9039                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9040                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9041                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9042                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9043                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9044 #ifdef CONFIG_X86_64
9045                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9046                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9047                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9048                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9049                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9050                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9051                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9052                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9053 #endif
9054                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9055                 [wordsize]"i"(sizeof(ulong))
9056               : "cc", "memory"
9057 #ifdef CONFIG_X86_64
9058                 , "rax", "rbx", "rdi", "rsi"
9059                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9060 #else
9061                 , "eax", "ebx", "edi", "esi"
9062 #endif
9063               );
9064
9065         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9066         if (debugctlmsr)
9067                 update_debugctlmsr(debugctlmsr);
9068
9069 #ifndef CONFIG_X86_64
9070         /*
9071          * The sysexit path does not restore ds/es, so we must set them to
9072          * a reasonable value ourselves.
9073          *
9074          * We can't defer this to vmx_load_host_state() since that function
9075          * may be executed in interrupt context, which saves and restore segments
9076          * around it, nullifying its effect.
9077          */
9078         loadsegment(ds, __USER_DS);
9079         loadsegment(es, __USER_DS);
9080 #endif
9081
9082         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9083                                   | (1 << VCPU_EXREG_RFLAGS)
9084                                   | (1 << VCPU_EXREG_PDPTR)
9085                                   | (1 << VCPU_EXREG_SEGMENTS)
9086                                   | (1 << VCPU_EXREG_CR3));
9087         vcpu->arch.regs_dirty = 0;
9088
9089         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9090
9091         vmx->loaded_vmcs->launched = 1;
9092
9093         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9094
9095         /*
9096          * eager fpu is enabled if PKEY is supported and CR4 is switched
9097          * back on host, so it is safe to read guest PKRU from current
9098          * XSAVE.
9099          */
9100         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9101                 vmx->guest_pkru = __read_pkru();
9102                 if (vmx->guest_pkru != vmx->host_pkru) {
9103                         vmx->guest_pkru_valid = true;
9104                         __write_pkru(vmx->host_pkru);
9105                 } else
9106                         vmx->guest_pkru_valid = false;
9107         }
9108
9109         /*
9110          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9111          * we did not inject a still-pending event to L1 now because of
9112          * nested_run_pending, we need to re-enable this bit.
9113          */
9114         if (vmx->nested.nested_run_pending)
9115                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9116
9117         vmx->nested.nested_run_pending = 0;
9118
9119         vmx_complete_atomic_exit(vmx);
9120         vmx_recover_nmi_blocking(vmx);
9121         vmx_complete_interrupts(vmx);
9122 }
9123 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9124
9125 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9126 {
9127         struct vcpu_vmx *vmx = to_vmx(vcpu);
9128         int cpu;
9129
9130         if (vmx->loaded_vmcs == vmcs)
9131                 return;
9132
9133         cpu = get_cpu();
9134         vmx->loaded_vmcs = vmcs;
9135         vmx_vcpu_put(vcpu);
9136         vmx_vcpu_load(vcpu, cpu);
9137         vcpu->cpu = cpu;
9138         put_cpu();
9139 }
9140
9141 /*
9142  * Ensure that the current vmcs of the logical processor is the
9143  * vmcs01 of the vcpu before calling free_nested().
9144  */
9145 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9146 {
9147        struct vcpu_vmx *vmx = to_vmx(vcpu);
9148        int r;
9149
9150        r = vcpu_load(vcpu);
9151        BUG_ON(r);
9152        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9153        free_nested(vmx);
9154        vcpu_put(vcpu);
9155 }
9156
9157 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9158 {
9159         struct vcpu_vmx *vmx = to_vmx(vcpu);
9160
9161         if (enable_pml)
9162                 vmx_destroy_pml_buffer(vmx);
9163         free_vpid(vmx->vpid);
9164         leave_guest_mode(vcpu);
9165         vmx_free_vcpu_nested(vcpu);
9166         free_loaded_vmcs(vmx->loaded_vmcs);
9167         kfree(vmx->guest_msrs);
9168         kvm_vcpu_uninit(vcpu);
9169         kmem_cache_free(kvm_vcpu_cache, vmx);
9170 }
9171
9172 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9173 {
9174         int err;
9175         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9176         int cpu;
9177
9178         if (!vmx)
9179                 return ERR_PTR(-ENOMEM);
9180
9181         vmx->vpid = allocate_vpid();
9182
9183         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9184         if (err)
9185                 goto free_vcpu;
9186
9187         err = -ENOMEM;
9188
9189         /*
9190          * If PML is turned on, failure on enabling PML just results in failure
9191          * of creating the vcpu, therefore we can simplify PML logic (by
9192          * avoiding dealing with cases, such as enabling PML partially on vcpus
9193          * for the guest, etc.
9194          */
9195         if (enable_pml) {
9196                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9197                 if (!vmx->pml_pg)
9198                         goto uninit_vcpu;
9199         }
9200
9201         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9202         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9203                      > PAGE_SIZE);
9204
9205         if (!vmx->guest_msrs)
9206                 goto free_pml;
9207
9208         vmx->loaded_vmcs = &vmx->vmcs01;
9209         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9210         vmx->loaded_vmcs->shadow_vmcs = NULL;
9211         if (!vmx->loaded_vmcs->vmcs)
9212                 goto free_msrs;
9213         loaded_vmcs_init(vmx->loaded_vmcs);
9214
9215         cpu = get_cpu();
9216         vmx_vcpu_load(&vmx->vcpu, cpu);
9217         vmx->vcpu.cpu = cpu;
9218         err = vmx_vcpu_setup(vmx);
9219         vmx_vcpu_put(&vmx->vcpu);
9220         put_cpu();
9221         if (err)
9222                 goto free_vmcs;
9223         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9224                 err = alloc_apic_access_page(kvm);
9225                 if (err)
9226                         goto free_vmcs;
9227         }
9228
9229         if (enable_ept) {
9230                 if (!kvm->arch.ept_identity_map_addr)
9231                         kvm->arch.ept_identity_map_addr =
9232                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9233                 err = init_rmode_identity_map(kvm);
9234                 if (err)
9235                         goto free_vmcs;
9236         }
9237
9238         if (nested) {
9239                 nested_vmx_setup_ctls_msrs(vmx);
9240                 vmx->nested.vpid02 = allocate_vpid();
9241         }
9242
9243         vmx->nested.posted_intr_nv = -1;
9244         vmx->nested.current_vmptr = -1ull;
9245         vmx->nested.current_vmcs12 = NULL;
9246
9247         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9248
9249         return &vmx->vcpu;
9250
9251 free_vmcs:
9252         free_vpid(vmx->nested.vpid02);
9253         free_loaded_vmcs(vmx->loaded_vmcs);
9254 free_msrs:
9255         kfree(vmx->guest_msrs);
9256 free_pml:
9257         vmx_destroy_pml_buffer(vmx);
9258 uninit_vcpu:
9259         kvm_vcpu_uninit(&vmx->vcpu);
9260 free_vcpu:
9261         free_vpid(vmx->vpid);
9262         kmem_cache_free(kvm_vcpu_cache, vmx);
9263         return ERR_PTR(err);
9264 }
9265
9266 static void __init vmx_check_processor_compat(void *rtn)
9267 {
9268         struct vmcs_config vmcs_conf;
9269
9270         *(int *)rtn = 0;
9271         if (setup_vmcs_config(&vmcs_conf) < 0)
9272                 *(int *)rtn = -EIO;
9273         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9274                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9275                                 smp_processor_id());
9276                 *(int *)rtn = -EIO;
9277         }
9278 }
9279
9280 static int get_ept_level(void)
9281 {
9282         return VMX_EPT_DEFAULT_GAW + 1;
9283 }
9284
9285 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9286 {
9287         u8 cache;
9288         u64 ipat = 0;
9289
9290         /* For VT-d and EPT combination
9291          * 1. MMIO: always map as UC
9292          * 2. EPT with VT-d:
9293          *   a. VT-d without snooping control feature: can't guarantee the
9294          *      result, try to trust guest.
9295          *   b. VT-d with snooping control feature: snooping control feature of
9296          *      VT-d engine can guarantee the cache correctness. Just set it
9297          *      to WB to keep consistent with host. So the same as item 3.
9298          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9299          *    consistent with host MTRR
9300          */
9301         if (is_mmio) {
9302                 cache = MTRR_TYPE_UNCACHABLE;
9303                 goto exit;
9304         }
9305
9306         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9307                 ipat = VMX_EPT_IPAT_BIT;
9308                 cache = MTRR_TYPE_WRBACK;
9309                 goto exit;
9310         }
9311
9312         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9313                 ipat = VMX_EPT_IPAT_BIT;
9314                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9315                         cache = MTRR_TYPE_WRBACK;
9316                 else
9317                         cache = MTRR_TYPE_UNCACHABLE;
9318                 goto exit;
9319         }
9320
9321         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9322
9323 exit:
9324         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9325 }
9326
9327 static int vmx_get_lpage_level(void)
9328 {
9329         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9330                 return PT_DIRECTORY_LEVEL;
9331         else
9332                 /* For shadow and EPT supported 1GB page */
9333                 return PT_PDPE_LEVEL;
9334 }
9335
9336 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9337 {
9338         /*
9339          * These bits in the secondary execution controls field
9340          * are dynamic, the others are mostly based on the hypervisor
9341          * architecture and the guest's CPUID.  Do not touch the
9342          * dynamic bits.
9343          */
9344         u32 mask =
9345                 SECONDARY_EXEC_SHADOW_VMCS |
9346                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9347                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9348
9349         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9350
9351         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9352                      (new_ctl & ~mask) | (cur_ctl & mask));
9353 }
9354
9355 /*
9356  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9357  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9358  */
9359 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9360 {
9361         struct vcpu_vmx *vmx = to_vmx(vcpu);
9362         struct kvm_cpuid_entry2 *entry;
9363
9364         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9365         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9366
9367 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9368         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9369                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9370 } while (0)
9371
9372         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9373         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9374         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9375         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9376         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9377         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9378         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9379         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9380         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9381         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9382         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9383         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9384         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9385         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9386         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9387
9388         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9389         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9390         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9391         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9392         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9393         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9394         cr4_fixed1_update(bit(11),            ecx, bit(2));
9395
9396 #undef cr4_fixed1_update
9397 }
9398
9399 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9400 {
9401         struct kvm_cpuid_entry2 *best;
9402         struct vcpu_vmx *vmx = to_vmx(vcpu);
9403         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9404
9405         if (vmx_rdtscp_supported()) {
9406                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9407                 if (!rdtscp_enabled)
9408                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9409
9410                 if (nested) {
9411                         if (rdtscp_enabled)
9412                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9413                                         SECONDARY_EXEC_RDTSCP;
9414                         else
9415                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9416                                         ~SECONDARY_EXEC_RDTSCP;
9417                 }
9418         }
9419
9420         /* Exposing INVPCID only when PCID is exposed */
9421         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9422         if (vmx_invpcid_supported() &&
9423             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9424             !guest_cpuid_has_pcid(vcpu))) {
9425                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9426
9427                 if (best)
9428                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9429         }
9430
9431         if (cpu_has_secondary_exec_ctrls())
9432                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9433
9434         if (nested_vmx_allowed(vcpu))
9435                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9436                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9437         else
9438                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9439                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9440
9441         if (nested_vmx_allowed(vcpu))
9442                 nested_vmx_cr_fixed1_bits_update(vcpu);
9443 }
9444
9445 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9446 {
9447         if (func == 1 && nested)
9448                 entry->ecx |= bit(X86_FEATURE_VMX);
9449 }
9450
9451 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9452                 struct x86_exception *fault)
9453 {
9454         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9455         struct vcpu_vmx *vmx = to_vmx(vcpu);
9456         u32 exit_reason;
9457         unsigned long exit_qualification = vcpu->arch.exit_qualification;
9458
9459         if (vmx->nested.pml_full) {
9460                 exit_reason = EXIT_REASON_PML_FULL;
9461                 vmx->nested.pml_full = false;
9462                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9463         } else if (fault->error_code & PFERR_RSVD_MASK)
9464                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9465         else
9466                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9467
9468         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9469         vmcs12->guest_physical_address = fault->address;
9470 }
9471
9472 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9473 {
9474         return nested_ept_get_cr3(vcpu) & VMX_EPT_AD_ENABLE_BIT;
9475 }
9476
9477 /* Callbacks for nested_ept_init_mmu_context: */
9478
9479 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9480 {
9481         /* return the page table to be shadowed - in our case, EPT12 */
9482         return get_vmcs12(vcpu)->ept_pointer;
9483 }
9484
9485 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9486 {
9487         bool wants_ad;
9488
9489         WARN_ON(mmu_is_nested(vcpu));
9490         wants_ad = nested_ept_ad_enabled(vcpu);
9491         if (wants_ad && !enable_ept_ad_bits)
9492                 return 1;
9493
9494         kvm_mmu_unload(vcpu);
9495         kvm_init_shadow_ept_mmu(vcpu,
9496                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9497                         VMX_EPT_EXECUTE_ONLY_BIT,
9498                         wants_ad);
9499         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9500         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9501         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9502
9503         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9504         return 0;
9505 }
9506
9507 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9508 {
9509         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9510 }
9511
9512 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9513                                             u16 error_code)
9514 {
9515         bool inequality, bit;
9516
9517         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9518         inequality =
9519                 (error_code & vmcs12->page_fault_error_code_mask) !=
9520                  vmcs12->page_fault_error_code_match;
9521         return inequality ^ bit;
9522 }
9523
9524 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9525                 struct x86_exception *fault)
9526 {
9527         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9528
9529         WARN_ON(!is_guest_mode(vcpu));
9530
9531         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code)) {
9532                 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9533                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9534                                   vmcs_read32(VM_EXIT_INTR_INFO),
9535                                   vmcs_readl(EXIT_QUALIFICATION));
9536         } else {
9537                 kvm_inject_page_fault(vcpu, fault);
9538         }
9539 }
9540
9541 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9542                                                struct vmcs12 *vmcs12);
9543
9544 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9545                                         struct vmcs12 *vmcs12)
9546 {
9547         struct vcpu_vmx *vmx = to_vmx(vcpu);
9548         u64 hpa;
9549
9550         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9551                 /*
9552                  * Translate L1 physical address to host physical
9553                  * address for vmcs02. Keep the page pinned, so this
9554                  * physical address remains valid. We keep a reference
9555                  * to it so we can release it later.
9556                  */
9557                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9558                         nested_release_page(vmx->nested.apic_access_page);
9559                 vmx->nested.apic_access_page =
9560                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9561                 /*
9562                  * If translation failed, no matter: This feature asks
9563                  * to exit when accessing the given address, and if it
9564                  * can never be accessed, this feature won't do
9565                  * anything anyway.
9566                  */
9567                 if (vmx->nested.apic_access_page) {
9568                         hpa = page_to_phys(vmx->nested.apic_access_page);
9569                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9570                 } else {
9571                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9572                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9573                 }
9574         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9575                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9576                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9577                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9578                 kvm_vcpu_reload_apic_access_page(vcpu);
9579         }
9580
9581         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9582                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9583                         nested_release_page(vmx->nested.virtual_apic_page);
9584                 vmx->nested.virtual_apic_page =
9585                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9586
9587                 /*
9588                  * If translation failed, VM entry will fail because
9589                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9590                  * Failing the vm entry is _not_ what the processor
9591                  * does but it's basically the only possibility we
9592                  * have.  We could still enter the guest if CR8 load
9593                  * exits are enabled, CR8 store exits are enabled, and
9594                  * virtualize APIC access is disabled; in this case
9595                  * the processor would never use the TPR shadow and we
9596                  * could simply clear the bit from the execution
9597                  * control.  But such a configuration is useless, so
9598                  * let's keep the code simple.
9599                  */
9600                 if (vmx->nested.virtual_apic_page) {
9601                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9602                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9603                 }
9604         }
9605
9606         if (nested_cpu_has_posted_intr(vmcs12)) {
9607                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9608                         kunmap(vmx->nested.pi_desc_page);
9609                         nested_release_page(vmx->nested.pi_desc_page);
9610                 }
9611                 vmx->nested.pi_desc_page =
9612                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9613                 vmx->nested.pi_desc =
9614                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9615                 if (!vmx->nested.pi_desc) {
9616                         nested_release_page_clean(vmx->nested.pi_desc_page);
9617                         return;
9618                 }
9619                 vmx->nested.pi_desc =
9620                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9621                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9622                         (PAGE_SIZE - 1)));
9623                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9624                         page_to_phys(vmx->nested.pi_desc_page) +
9625                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9626                         (PAGE_SIZE - 1)));
9627         }
9628         if (cpu_has_vmx_msr_bitmap() &&
9629             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9630             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9631                 ;
9632         else
9633                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9634                                 CPU_BASED_USE_MSR_BITMAPS);
9635 }
9636
9637 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9638 {
9639         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9640         struct vcpu_vmx *vmx = to_vmx(vcpu);
9641
9642         if (vcpu->arch.virtual_tsc_khz == 0)
9643                 return;
9644
9645         /* Make sure short timeouts reliably trigger an immediate vmexit.
9646          * hrtimer_start does not guarantee this. */
9647         if (preemption_timeout <= 1) {
9648                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9649                 return;
9650         }
9651
9652         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9653         preemption_timeout *= 1000000;
9654         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9655         hrtimer_start(&vmx->nested.preemption_timer,
9656                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9657 }
9658
9659 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9660                                                struct vmcs12 *vmcs12)
9661 {
9662         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9663                 return 0;
9664
9665         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9666             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9667                 return -EINVAL;
9668
9669         return 0;
9670 }
9671
9672 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9673                                                 struct vmcs12 *vmcs12)
9674 {
9675         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9676                 return 0;
9677
9678         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
9679                 return -EINVAL;
9680
9681         return 0;
9682 }
9683
9684 /*
9685  * Merge L0's and L1's MSR bitmap, return false to indicate that
9686  * we do not use the hardware.
9687  */
9688 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9689                                                struct vmcs12 *vmcs12)
9690 {
9691         int msr;
9692         struct page *page;
9693         unsigned long *msr_bitmap_l1;
9694         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9695
9696         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9697         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9698                 return false;
9699
9700         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9701         if (!page)
9702                 return false;
9703         msr_bitmap_l1 = (unsigned long *)kmap(page);
9704
9705         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9706
9707         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9708                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9709                         for (msr = 0x800; msr <= 0x8ff; msr++)
9710                                 nested_vmx_disable_intercept_for_msr(
9711                                         msr_bitmap_l1, msr_bitmap_l0,
9712                                         msr, MSR_TYPE_R);
9713
9714                 nested_vmx_disable_intercept_for_msr(
9715                                 msr_bitmap_l1, msr_bitmap_l0,
9716                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9717                                 MSR_TYPE_R | MSR_TYPE_W);
9718
9719                 if (nested_cpu_has_vid(vmcs12)) {
9720                         nested_vmx_disable_intercept_for_msr(
9721                                 msr_bitmap_l1, msr_bitmap_l0,
9722                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9723                                 MSR_TYPE_W);
9724                         nested_vmx_disable_intercept_for_msr(
9725                                 msr_bitmap_l1, msr_bitmap_l0,
9726                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9727                                 MSR_TYPE_W);
9728                 }
9729         }
9730         kunmap(page);
9731         nested_release_page_clean(page);
9732
9733         return true;
9734 }
9735
9736 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9737                                            struct vmcs12 *vmcs12)
9738 {
9739         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9740             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9741             !nested_cpu_has_vid(vmcs12) &&
9742             !nested_cpu_has_posted_intr(vmcs12))
9743                 return 0;
9744
9745         /*
9746          * If virtualize x2apic mode is enabled,
9747          * virtualize apic access must be disabled.
9748          */
9749         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9750             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9751                 return -EINVAL;
9752
9753         /*
9754          * If virtual interrupt delivery is enabled,
9755          * we must exit on external interrupts.
9756          */
9757         if (nested_cpu_has_vid(vmcs12) &&
9758            !nested_exit_on_intr(vcpu))
9759                 return -EINVAL;
9760
9761         /*
9762          * bits 15:8 should be zero in posted_intr_nv,
9763          * the descriptor address has been already checked
9764          * in nested_get_vmcs12_pages.
9765          */
9766         if (nested_cpu_has_posted_intr(vmcs12) &&
9767            (!nested_cpu_has_vid(vmcs12) ||
9768             !nested_exit_intr_ack_set(vcpu) ||
9769             vmcs12->posted_intr_nv & 0xff00))
9770                 return -EINVAL;
9771
9772         /* tpr shadow is needed by all apicv features. */
9773         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9774                 return -EINVAL;
9775
9776         return 0;
9777 }
9778
9779 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9780                                        unsigned long count_field,
9781                                        unsigned long addr_field)
9782 {
9783         int maxphyaddr;
9784         u64 count, addr;
9785
9786         if (vmcs12_read_any(vcpu, count_field, &count) ||
9787             vmcs12_read_any(vcpu, addr_field, &addr)) {
9788                 WARN_ON(1);
9789                 return -EINVAL;
9790         }
9791         if (count == 0)
9792                 return 0;
9793         maxphyaddr = cpuid_maxphyaddr(vcpu);
9794         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9795             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9796                 pr_debug_ratelimited(
9797                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9798                         addr_field, maxphyaddr, count, addr);
9799                 return -EINVAL;
9800         }
9801         return 0;
9802 }
9803
9804 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9805                                                 struct vmcs12 *vmcs12)
9806 {
9807         if (vmcs12->vm_exit_msr_load_count == 0 &&
9808             vmcs12->vm_exit_msr_store_count == 0 &&
9809             vmcs12->vm_entry_msr_load_count == 0)
9810                 return 0; /* Fast path */
9811         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9812                                         VM_EXIT_MSR_LOAD_ADDR) ||
9813             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9814                                         VM_EXIT_MSR_STORE_ADDR) ||
9815             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9816                                         VM_ENTRY_MSR_LOAD_ADDR))
9817                 return -EINVAL;
9818         return 0;
9819 }
9820
9821 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9822                                          struct vmcs12 *vmcs12)
9823 {
9824         u64 address = vmcs12->pml_address;
9825         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9826
9827         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9828                 if (!nested_cpu_has_ept(vmcs12) ||
9829                     !IS_ALIGNED(address, 4096)  ||
9830                     address >> maxphyaddr)
9831                         return -EINVAL;
9832         }
9833
9834         return 0;
9835 }
9836
9837 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9838                                        struct vmx_msr_entry *e)
9839 {
9840         /* x2APIC MSR accesses are not allowed */
9841         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9842                 return -EINVAL;
9843         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9844             e->index == MSR_IA32_UCODE_REV)
9845                 return -EINVAL;
9846         if (e->reserved != 0)
9847                 return -EINVAL;
9848         return 0;
9849 }
9850
9851 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9852                                      struct vmx_msr_entry *e)
9853 {
9854         if (e->index == MSR_FS_BASE ||
9855             e->index == MSR_GS_BASE ||
9856             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9857             nested_vmx_msr_check_common(vcpu, e))
9858                 return -EINVAL;
9859         return 0;
9860 }
9861
9862 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9863                                       struct vmx_msr_entry *e)
9864 {
9865         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9866             nested_vmx_msr_check_common(vcpu, e))
9867                 return -EINVAL;
9868         return 0;
9869 }
9870
9871 /*
9872  * Load guest's/host's msr at nested entry/exit.
9873  * return 0 for success, entry index for failure.
9874  */
9875 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9876 {
9877         u32 i;
9878         struct vmx_msr_entry e;
9879         struct msr_data msr;
9880
9881         msr.host_initiated = false;
9882         for (i = 0; i < count; i++) {
9883                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9884                                         &e, sizeof(e))) {
9885                         pr_debug_ratelimited(
9886                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9887                                 __func__, i, gpa + i * sizeof(e));
9888                         goto fail;
9889                 }
9890                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9891                         pr_debug_ratelimited(
9892                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9893                                 __func__, i, e.index, e.reserved);
9894                         goto fail;
9895                 }
9896                 msr.index = e.index;
9897                 msr.data = e.value;
9898                 if (kvm_set_msr(vcpu, &msr)) {
9899                         pr_debug_ratelimited(
9900                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9901                                 __func__, i, e.index, e.value);
9902                         goto fail;
9903                 }
9904         }
9905         return 0;
9906 fail:
9907         return i + 1;
9908 }
9909
9910 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9911 {
9912         u32 i;
9913         struct vmx_msr_entry e;
9914
9915         for (i = 0; i < count; i++) {
9916                 struct msr_data msr_info;
9917                 if (kvm_vcpu_read_guest(vcpu,
9918                                         gpa + i * sizeof(e),
9919                                         &e, 2 * sizeof(u32))) {
9920                         pr_debug_ratelimited(
9921                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9922                                 __func__, i, gpa + i * sizeof(e));
9923                         return -EINVAL;
9924                 }
9925                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9926                         pr_debug_ratelimited(
9927                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9928                                 __func__, i, e.index, e.reserved);
9929                         return -EINVAL;
9930                 }
9931                 msr_info.host_initiated = false;
9932                 msr_info.index = e.index;
9933                 if (kvm_get_msr(vcpu, &msr_info)) {
9934                         pr_debug_ratelimited(
9935                                 "%s cannot read MSR (%u, 0x%x)\n",
9936                                 __func__, i, e.index);
9937                         return -EINVAL;
9938                 }
9939                 if (kvm_vcpu_write_guest(vcpu,
9940                                          gpa + i * sizeof(e) +
9941                                              offsetof(struct vmx_msr_entry, value),
9942                                          &msr_info.data, sizeof(msr_info.data))) {
9943                         pr_debug_ratelimited(
9944                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9945                                 __func__, i, e.index, msr_info.data);
9946                         return -EINVAL;
9947                 }
9948         }
9949         return 0;
9950 }
9951
9952 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9953 {
9954         unsigned long invalid_mask;
9955
9956         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9957         return (val & invalid_mask) == 0;
9958 }
9959
9960 /*
9961  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9962  * emulating VM entry into a guest with EPT enabled.
9963  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9964  * is assigned to entry_failure_code on failure.
9965  */
9966 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9967                                u32 *entry_failure_code)
9968 {
9969         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9970                 if (!nested_cr3_valid(vcpu, cr3)) {
9971                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9972                         return 1;
9973                 }
9974
9975                 /*
9976                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9977                  * must not be dereferenced.
9978                  */
9979                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9980                     !nested_ept) {
9981                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9982                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9983                                 return 1;
9984                         }
9985                 }
9986
9987                 vcpu->arch.cr3 = cr3;
9988                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9989         }
9990
9991         kvm_mmu_reset_context(vcpu);
9992         return 0;
9993 }
9994
9995 /*
9996  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9997  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9998  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9999  * guest in a way that will both be appropriate to L1's requests, and our
10000  * needs. In addition to modifying the active vmcs (which is vmcs02), this
10001  * function also has additional necessary side-effects, like setting various
10002  * vcpu->arch fields.
10003  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10004  * is assigned to entry_failure_code on failure.
10005  */
10006 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10007                           bool from_vmentry, u32 *entry_failure_code)
10008 {
10009         struct vcpu_vmx *vmx = to_vmx(vcpu);
10010         u32 exec_control, vmcs12_exec_ctrl;
10011
10012         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10013         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10014         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10015         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10016         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10017         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10018         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10019         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10020         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10021         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10022         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10023         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10024         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10025         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10026         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10027         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10028         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10029         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10030         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10031         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10032         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10033         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10034         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10035         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10036         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10037         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10038         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10039         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10040         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10041         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10042         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10043         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10044         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10045         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10046         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10047         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10048
10049         if (from_vmentry &&
10050             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10051                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10052                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10053         } else {
10054                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10055                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10056         }
10057         if (from_vmentry) {
10058                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10059                              vmcs12->vm_entry_intr_info_field);
10060                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10061                              vmcs12->vm_entry_exception_error_code);
10062                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10063                              vmcs12->vm_entry_instruction_len);
10064                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10065                              vmcs12->guest_interruptibility_info);
10066                 vmx->loaded_vmcs->nmi_known_unmasked =
10067                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
10068         } else {
10069                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10070         }
10071         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10072         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10073         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10074                 vmcs12->guest_pending_dbg_exceptions);
10075         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10076         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10077
10078         if (nested_cpu_has_xsaves(vmcs12))
10079                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10080         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10081
10082         exec_control = vmcs12->pin_based_vm_exec_control;
10083
10084         /* Preemption timer setting is only taken from vmcs01.  */
10085         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10086         exec_control |= vmcs_config.pin_based_exec_ctrl;
10087         if (vmx->hv_deadline_tsc == -1)
10088                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10089
10090         /* Posted interrupts setting is only taken from vmcs12.  */
10091         if (nested_cpu_has_posted_intr(vmcs12)) {
10092                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10093                 vmx->nested.pi_pending = false;
10094                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10095         } else {
10096                 exec_control &= ~PIN_BASED_POSTED_INTR;
10097         }
10098
10099         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10100
10101         vmx->nested.preemption_timer_expired = false;
10102         if (nested_cpu_has_preemption_timer(vmcs12))
10103                 vmx_start_preemption_timer(vcpu);
10104
10105         /*
10106          * Whether page-faults are trapped is determined by a combination of
10107          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10108          * If enable_ept, L0 doesn't care about page faults and we should
10109          * set all of these to L1's desires. However, if !enable_ept, L0 does
10110          * care about (at least some) page faults, and because it is not easy
10111          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10112          * to exit on each and every L2 page fault. This is done by setting
10113          * MASK=MATCH=0 and (see below) EB.PF=1.
10114          * Note that below we don't need special code to set EB.PF beyond the
10115          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10116          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10117          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10118          *
10119          * A problem with this approach (when !enable_ept) is that L1 may be
10120          * injected with more page faults than it asked for. This could have
10121          * caused problems, but in practice existing hypervisors don't care.
10122          * To fix this, we will need to emulate the PFEC checking (on the L1
10123          * page tables), using walk_addr(), when injecting PFs to L1.
10124          */
10125         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10126                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10127         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10128                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10129
10130         if (cpu_has_secondary_exec_ctrls()) {
10131                 exec_control = vmx_secondary_exec_control(vmx);
10132
10133                 /* Take the following fields only from vmcs12 */
10134                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10135                                   SECONDARY_EXEC_RDTSCP |
10136                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10137                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10138                 if (nested_cpu_has(vmcs12,
10139                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10140                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10141                                 ~SECONDARY_EXEC_ENABLE_PML;
10142                         exec_control |= vmcs12_exec_ctrl;
10143                 }
10144
10145                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10146                         vmcs_write64(EOI_EXIT_BITMAP0,
10147                                 vmcs12->eoi_exit_bitmap0);
10148                         vmcs_write64(EOI_EXIT_BITMAP1,
10149                                 vmcs12->eoi_exit_bitmap1);
10150                         vmcs_write64(EOI_EXIT_BITMAP2,
10151                                 vmcs12->eoi_exit_bitmap2);
10152                         vmcs_write64(EOI_EXIT_BITMAP3,
10153                                 vmcs12->eoi_exit_bitmap3);
10154                         vmcs_write16(GUEST_INTR_STATUS,
10155                                 vmcs12->guest_intr_status);
10156                 }
10157
10158                 /*
10159                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10160                  * nested_get_vmcs12_pages will either fix it up or
10161                  * remove the VM execution control.
10162                  */
10163                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10164                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10165
10166                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10167         }
10168
10169
10170         /*
10171          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10172          * Some constant fields are set here by vmx_set_constant_host_state().
10173          * Other fields are different per CPU, and will be set later when
10174          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10175          */
10176         vmx_set_constant_host_state(vmx);
10177
10178         /*
10179          * Set the MSR load/store lists to match L0's settings.
10180          */
10181         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10182         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10183         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10184         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10185         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10186
10187         /*
10188          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10189          * entry, but only if the current (host) sp changed from the value
10190          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10191          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10192          * here we just force the write to happen on entry.
10193          */
10194         vmx->host_rsp = 0;
10195
10196         exec_control = vmx_exec_control(vmx); /* L0's desires */
10197         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10198         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10199         exec_control &= ~CPU_BASED_TPR_SHADOW;
10200         exec_control |= vmcs12->cpu_based_vm_exec_control;
10201
10202         /*
10203          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10204          * nested_get_vmcs12_pages can't fix it up, the illegal value
10205          * will result in a VM entry failure.
10206          */
10207         if (exec_control & CPU_BASED_TPR_SHADOW) {
10208                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10209                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10210         }
10211
10212         /*
10213          * Merging of IO bitmap not currently supported.
10214          * Rather, exit every time.
10215          */
10216         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10217         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10218
10219         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10220
10221         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10222          * bitwise-or of what L1 wants to trap for L2, and what we want to
10223          * trap. Note that CR0.TS also needs updating - we do this later.
10224          */
10225         update_exception_bitmap(vcpu);
10226         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10227         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10228
10229         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10230          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10231          * bits are further modified by vmx_set_efer() below.
10232          */
10233         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10234
10235         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10236          * emulated by vmx_set_efer(), below.
10237          */
10238         vm_entry_controls_init(vmx,
10239                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10240                         ~VM_ENTRY_IA32E_MODE) |
10241                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10242
10243         if (from_vmentry &&
10244             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10245                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10246                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10247         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10248                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10249         }
10250
10251         set_cr4_guest_host_mask(vmx);
10252
10253         if (from_vmentry &&
10254             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10255                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10256
10257         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10258                 vmcs_write64(TSC_OFFSET,
10259                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10260         else
10261                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10262         if (kvm_has_tsc_control)
10263                 decache_tsc_multiplier(vmx);
10264
10265         if (enable_vpid) {
10266                 /*
10267                  * There is no direct mapping between vpid02 and vpid12, the
10268                  * vpid02 is per-vCPU for L0 and reused while the value of
10269                  * vpid12 is changed w/ one invvpid during nested vmentry.
10270                  * The vpid12 is allocated by L1 for L2, so it will not
10271                  * influence global bitmap(for vpid01 and vpid02 allocation)
10272                  * even if spawn a lot of nested vCPUs.
10273                  */
10274                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10275                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10276                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10277                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10278                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10279                         }
10280                 } else {
10281                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10282                         vmx_flush_tlb(vcpu);
10283                 }
10284
10285         }
10286
10287         if (enable_pml) {
10288                 /*
10289                  * Conceptually we want to copy the PML address and index from
10290                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10291                  * since we always flush the log on each vmexit, this happens
10292                  * to be equivalent to simply resetting the fields in vmcs02.
10293                  */
10294                 ASSERT(vmx->pml_pg);
10295                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10296                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10297         }
10298
10299         if (nested_cpu_has_ept(vmcs12)) {
10300                 if (nested_ept_init_mmu_context(vcpu)) {
10301                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10302                         return 1;
10303                 }
10304         } else if (nested_cpu_has2(vmcs12,
10305                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10306                 vmx_flush_tlb_ept_only(vcpu);
10307         }
10308
10309         /*
10310          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10311          * bits which we consider mandatory enabled.
10312          * The CR0_READ_SHADOW is what L2 should have expected to read given
10313          * the specifications by L1; It's not enough to take
10314          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10315          * have more bits than L1 expected.
10316          */
10317         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10318         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10319
10320         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10321         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10322
10323         if (from_vmentry &&
10324             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10325                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10326         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10327                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10328         else
10329                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10330         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10331         vmx_set_efer(vcpu, vcpu->arch.efer);
10332
10333         /* Shadow page tables on either EPT or shadow page tables. */
10334         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10335                                 entry_failure_code))
10336                 return 1;
10337
10338         if (!enable_ept)
10339                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10340
10341         /*
10342          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10343          */
10344         if (enable_ept) {
10345                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10346                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10347                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10348                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10349         }
10350
10351         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10352         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10353         return 0;
10354 }
10355
10356 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10357 {
10358         struct vcpu_vmx *vmx = to_vmx(vcpu);
10359
10360         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10361             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10362                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10363
10364         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10365                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10366
10367         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10368                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10369
10370         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10371                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10372
10373         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10374                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10375
10376         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10377                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10378
10379         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10380                                 vmx->nested.nested_vmx_procbased_ctls_low,
10381                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10382             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10383              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10384                                  vmx->nested.nested_vmx_secondary_ctls_low,
10385                                  vmx->nested.nested_vmx_secondary_ctls_high)) ||
10386             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10387                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10388                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10389             !vmx_control_verify(vmcs12->vm_exit_controls,
10390                                 vmx->nested.nested_vmx_exit_ctls_low,
10391                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10392             !vmx_control_verify(vmcs12->vm_entry_controls,
10393                                 vmx->nested.nested_vmx_entry_ctls_low,
10394                                 vmx->nested.nested_vmx_entry_ctls_high))
10395                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10396
10397         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10398                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10399
10400         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10401             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10402             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10403                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10404
10405         return 0;
10406 }
10407
10408 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10409                                   u32 *exit_qual)
10410 {
10411         bool ia32e;
10412
10413         *exit_qual = ENTRY_FAIL_DEFAULT;
10414
10415         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10416             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10417                 return 1;
10418
10419         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10420             vmcs12->vmcs_link_pointer != -1ull) {
10421                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10422                 return 1;
10423         }
10424
10425         /*
10426          * If the load IA32_EFER VM-entry control is 1, the following checks
10427          * are performed on the field for the IA32_EFER MSR:
10428          * - Bits reserved in the IA32_EFER MSR must be 0.
10429          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10430          *   the IA-32e mode guest VM-exit control. It must also be identical
10431          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10432          *   CR0.PG) is 1.
10433          */
10434         if (to_vmx(vcpu)->nested.nested_run_pending &&
10435             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10436                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10437                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10438                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10439                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10440                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10441                         return 1;
10442         }
10443
10444         /*
10445          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10446          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10447          * the values of the LMA and LME bits in the field must each be that of
10448          * the host address-space size VM-exit control.
10449          */
10450         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10451                 ia32e = (vmcs12->vm_exit_controls &
10452                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10453                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10454                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10455                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10456                         return 1;
10457         }
10458
10459         return 0;
10460 }
10461
10462 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10463 {
10464         struct vcpu_vmx *vmx = to_vmx(vcpu);
10465         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10466         struct loaded_vmcs *vmcs02;
10467         u32 msr_entry_idx;
10468         u32 exit_qual;
10469
10470         vmcs02 = nested_get_current_vmcs02(vmx);
10471         if (!vmcs02)
10472                 return -ENOMEM;
10473
10474         enter_guest_mode(vcpu);
10475
10476         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10477                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10478
10479         vmx_switch_vmcs(vcpu, vmcs02);
10480         vmx_segment_cache_clear(vmx);
10481
10482         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10483                 leave_guest_mode(vcpu);
10484                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10485                 nested_vmx_entry_failure(vcpu, vmcs12,
10486                                          EXIT_REASON_INVALID_STATE, exit_qual);
10487                 return 1;
10488         }
10489
10490         nested_get_vmcs12_pages(vcpu, vmcs12);
10491
10492         msr_entry_idx = nested_vmx_load_msr(vcpu,
10493                                             vmcs12->vm_entry_msr_load_addr,
10494                                             vmcs12->vm_entry_msr_load_count);
10495         if (msr_entry_idx) {
10496                 leave_guest_mode(vcpu);
10497                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10498                 nested_vmx_entry_failure(vcpu, vmcs12,
10499                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10500                 return 1;
10501         }
10502
10503         /*
10504          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10505          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10506          * returned as far as L1 is concerned. It will only return (and set
10507          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10508          */
10509         return 0;
10510 }
10511
10512 /*
10513  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10514  * for running an L2 nested guest.
10515  */
10516 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10517 {
10518         struct vmcs12 *vmcs12;
10519         struct vcpu_vmx *vmx = to_vmx(vcpu);
10520         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
10521         u32 exit_qual;
10522         int ret;
10523
10524         if (!nested_vmx_check_permission(vcpu))
10525                 return 1;
10526
10527         if (!nested_vmx_check_vmcs12(vcpu))
10528                 goto out;
10529
10530         vmcs12 = get_vmcs12(vcpu);
10531
10532         if (enable_shadow_vmcs)
10533                 copy_shadow_to_vmcs12(vmx);
10534
10535         /*
10536          * The nested entry process starts with enforcing various prerequisites
10537          * on vmcs12 as required by the Intel SDM, and act appropriately when
10538          * they fail: As the SDM explains, some conditions should cause the
10539          * instruction to fail, while others will cause the instruction to seem
10540          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10541          * To speed up the normal (success) code path, we should avoid checking
10542          * for misconfigurations which will anyway be caught by the processor
10543          * when using the merged vmcs02.
10544          */
10545         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
10546                 nested_vmx_failValid(vcpu,
10547                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
10548                 goto out;
10549         }
10550
10551         if (vmcs12->launch_state == launch) {
10552                 nested_vmx_failValid(vcpu,
10553                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10554                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10555                 goto out;
10556         }
10557
10558         ret = check_vmentry_prereqs(vcpu, vmcs12);
10559         if (ret) {
10560                 nested_vmx_failValid(vcpu, ret);
10561                 goto out;
10562         }
10563
10564         /*
10565          * After this point, the trap flag no longer triggers a singlestep trap
10566          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10567          * This is not 100% correct; for performance reasons, we delegate most
10568          * of the checks on host state to the processor.  If those fail,
10569          * the singlestep trap is missed.
10570          */
10571         skip_emulated_instruction(vcpu);
10572
10573         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10574         if (ret) {
10575                 nested_vmx_entry_failure(vcpu, vmcs12,
10576                                          EXIT_REASON_INVALID_STATE, exit_qual);
10577                 return 1;
10578         }
10579
10580         /*
10581          * We're finally done with prerequisite checking, and can start with
10582          * the nested entry.
10583          */
10584
10585         ret = enter_vmx_non_root_mode(vcpu, true);
10586         if (ret)
10587                 return ret;
10588
10589         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10590                 return kvm_vcpu_halt(vcpu);
10591
10592         vmx->nested.nested_run_pending = 1;
10593
10594         return 1;
10595
10596 out:
10597         return kvm_skip_emulated_instruction(vcpu);
10598 }
10599
10600 /*
10601  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10602  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10603  * This function returns the new value we should put in vmcs12.guest_cr0.
10604  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10605  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10606  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10607  *     didn't trap the bit, because if L1 did, so would L0).
10608  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10609  *     been modified by L2, and L1 knows it. So just leave the old value of
10610  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10611  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10612  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10613  *     changed these bits, and therefore they need to be updated, but L0
10614  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10615  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10616  */
10617 static inline unsigned long
10618 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10619 {
10620         return
10621         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10622         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10623         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10624                         vcpu->arch.cr0_guest_owned_bits));
10625 }
10626
10627 static inline unsigned long
10628 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10629 {
10630         return
10631         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10632         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10633         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10634                         vcpu->arch.cr4_guest_owned_bits));
10635 }
10636
10637 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10638                                        struct vmcs12 *vmcs12)
10639 {
10640         u32 idt_vectoring;
10641         unsigned int nr;
10642
10643         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10644                 nr = vcpu->arch.exception.nr;
10645                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10646
10647                 if (kvm_exception_is_soft(nr)) {
10648                         vmcs12->vm_exit_instruction_len =
10649                                 vcpu->arch.event_exit_inst_len;
10650                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10651                 } else
10652                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10653
10654                 if (vcpu->arch.exception.has_error_code) {
10655                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10656                         vmcs12->idt_vectoring_error_code =
10657                                 vcpu->arch.exception.error_code;
10658                 }
10659
10660                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10661         } else if (vcpu->arch.nmi_injected) {
10662                 vmcs12->idt_vectoring_info_field =
10663                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10664         } else if (vcpu->arch.interrupt.pending) {
10665                 nr = vcpu->arch.interrupt.nr;
10666                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10667
10668                 if (vcpu->arch.interrupt.soft) {
10669                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10670                         vmcs12->vm_entry_instruction_len =
10671                                 vcpu->arch.event_exit_inst_len;
10672                 } else
10673                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10674
10675                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10676         }
10677 }
10678
10679 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10680 {
10681         struct vcpu_vmx *vmx = to_vmx(vcpu);
10682
10683         if (vcpu->arch.exception.pending ||
10684                 vcpu->arch.nmi_injected ||
10685                 vcpu->arch.interrupt.pending)
10686                 return -EBUSY;
10687
10688         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10689             vmx->nested.preemption_timer_expired) {
10690                 if (vmx->nested.nested_run_pending)
10691                         return -EBUSY;
10692                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10693                 return 0;
10694         }
10695
10696         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10697                 if (vmx->nested.nested_run_pending)
10698                         return -EBUSY;
10699                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10700                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10701                                   INTR_INFO_VALID_MASK, 0);
10702                 /*
10703                  * The NMI-triggered VM exit counts as injection:
10704                  * clear this one and block further NMIs.
10705                  */
10706                 vcpu->arch.nmi_pending = 0;
10707                 vmx_set_nmi_mask(vcpu, true);
10708                 return 0;
10709         }
10710
10711         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10712             nested_exit_on_intr(vcpu)) {
10713                 if (vmx->nested.nested_run_pending)
10714                         return -EBUSY;
10715                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10716                 return 0;
10717         }
10718
10719         vmx_complete_nested_posted_interrupt(vcpu);
10720         return 0;
10721 }
10722
10723 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10724 {
10725         ktime_t remaining =
10726                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10727         u64 value;
10728
10729         if (ktime_to_ns(remaining) <= 0)
10730                 return 0;
10731
10732         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10733         do_div(value, 1000000);
10734         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10735 }
10736
10737 /*
10738  * Update the guest state fields of vmcs12 to reflect changes that
10739  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10740  * VM-entry controls is also updated, since this is really a guest
10741  * state bit.)
10742  */
10743 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10744 {
10745         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10746         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10747
10748         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10749         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10750         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10751
10752         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10753         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10754         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10755         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10756         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10757         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10758         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10759         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10760         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10761         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10762         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10763         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10764         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10765         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10766         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10767         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10768         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10769         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10770         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10771         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10772         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10773         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10774         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10775         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10776         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10777         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10778         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10779         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10780         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10781         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10782         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10783         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10784         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10785         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10786         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10787         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10788
10789         vmcs12->guest_interruptibility_info =
10790                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10791         vmcs12->guest_pending_dbg_exceptions =
10792                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10793         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10794                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10795         else
10796                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10797
10798         if (nested_cpu_has_preemption_timer(vmcs12)) {
10799                 if (vmcs12->vm_exit_controls &
10800                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10801                         vmcs12->vmx_preemption_timer_value =
10802                                 vmx_get_preemption_timer_value(vcpu);
10803                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10804         }
10805
10806         /*
10807          * In some cases (usually, nested EPT), L2 is allowed to change its
10808          * own CR3 without exiting. If it has changed it, we must keep it.
10809          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10810          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10811          *
10812          * Additionally, restore L2's PDPTR to vmcs12.
10813          */
10814         if (enable_ept) {
10815                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10816                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10817                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10818                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10819                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10820         }
10821
10822         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10823
10824         if (nested_cpu_has_vid(vmcs12))
10825                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10826
10827         vmcs12->vm_entry_controls =
10828                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10829                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10830
10831         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10832                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10833                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10834         }
10835
10836         /* TODO: These cannot have changed unless we have MSR bitmaps and
10837          * the relevant bit asks not to trap the change */
10838         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10839                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10840         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10841                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10842         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10843         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10844         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10845         if (kvm_mpx_supported())
10846                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10847 }
10848
10849 /*
10850  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10851  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10852  * and this function updates it to reflect the changes to the guest state while
10853  * L2 was running (and perhaps made some exits which were handled directly by L0
10854  * without going back to L1), and to reflect the exit reason.
10855  * Note that we do not have to copy here all VMCS fields, just those that
10856  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10857  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10858  * which already writes to vmcs12 directly.
10859  */
10860 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10861                            u32 exit_reason, u32 exit_intr_info,
10862                            unsigned long exit_qualification)
10863 {
10864         /* update guest state fields: */
10865         sync_vmcs12(vcpu, vmcs12);
10866
10867         /* update exit information fields: */
10868
10869         vmcs12->vm_exit_reason = exit_reason;
10870         vmcs12->exit_qualification = exit_qualification;
10871         vmcs12->vm_exit_intr_info = exit_intr_info;
10872
10873         vmcs12->idt_vectoring_info_field = 0;
10874         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10875         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10876
10877         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10878                 vmcs12->launch_state = 1;
10879
10880                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10881                  * instead of reading the real value. */
10882                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10883
10884                 /*
10885                  * Transfer the event that L0 or L1 may wanted to inject into
10886                  * L2 to IDT_VECTORING_INFO_FIELD.
10887                  */
10888                 vmcs12_save_pending_event(vcpu, vmcs12);
10889         }
10890
10891         /*
10892          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10893          * preserved above and would only end up incorrectly in L1.
10894          */
10895         vcpu->arch.nmi_injected = false;
10896         kvm_clear_exception_queue(vcpu);
10897         kvm_clear_interrupt_queue(vcpu);
10898 }
10899
10900 /*
10901  * A part of what we need to when the nested L2 guest exits and we want to
10902  * run its L1 parent, is to reset L1's guest state to the host state specified
10903  * in vmcs12.
10904  * This function is to be called not only on normal nested exit, but also on
10905  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10906  * Failures During or After Loading Guest State").
10907  * This function should be called when the active VMCS is L1's (vmcs01).
10908  */
10909 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10910                                    struct vmcs12 *vmcs12)
10911 {
10912         struct kvm_segment seg;
10913         u32 entry_failure_code;
10914
10915         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10916                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10917         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10918                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10919         else
10920                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10921         vmx_set_efer(vcpu, vcpu->arch.efer);
10922
10923         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10924         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10925         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10926         /*
10927          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10928          * actually changed, because vmx_set_cr0 refers to efer set above.
10929          *
10930          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10931          * (KVM doesn't change it);
10932          */
10933         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10934         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10935
10936         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10937         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10938         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10939
10940         nested_ept_uninit_mmu_context(vcpu);
10941
10942         /*
10943          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10944          * couldn't have changed.
10945          */
10946         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10947                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10948
10949         if (!enable_ept)
10950                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10951
10952         if (enable_vpid) {
10953                 /*
10954                  * Trivially support vpid by letting L2s share their parent
10955                  * L1's vpid. TODO: move to a more elaborate solution, giving
10956                  * each L2 its own vpid and exposing the vpid feature to L1.
10957                  */
10958                 vmx_flush_tlb(vcpu);
10959         }
10960         /* Restore posted intr vector. */
10961         if (nested_cpu_has_posted_intr(vmcs12))
10962                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10963
10964         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10965         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10966         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10967         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10968         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10969
10970         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10971         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10972                 vmcs_write64(GUEST_BNDCFGS, 0);
10973
10974         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10975                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10976                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10977         }
10978         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10979                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10980                         vmcs12->host_ia32_perf_global_ctrl);
10981
10982         /* Set L1 segment info according to Intel SDM
10983             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10984         seg = (struct kvm_segment) {
10985                 .base = 0,
10986                 .limit = 0xFFFFFFFF,
10987                 .selector = vmcs12->host_cs_selector,
10988                 .type = 11,
10989                 .present = 1,
10990                 .s = 1,
10991                 .g = 1
10992         };
10993         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10994                 seg.l = 1;
10995         else
10996                 seg.db = 1;
10997         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10998         seg = (struct kvm_segment) {
10999                 .base = 0,
11000                 .limit = 0xFFFFFFFF,
11001                 .type = 3,
11002                 .present = 1,
11003                 .s = 1,
11004                 .db = 1,
11005                 .g = 1
11006         };
11007         seg.selector = vmcs12->host_ds_selector;
11008         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11009         seg.selector = vmcs12->host_es_selector;
11010         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11011         seg.selector = vmcs12->host_ss_selector;
11012         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11013         seg.selector = vmcs12->host_fs_selector;
11014         seg.base = vmcs12->host_fs_base;
11015         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11016         seg.selector = vmcs12->host_gs_selector;
11017         seg.base = vmcs12->host_gs_base;
11018         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11019         seg = (struct kvm_segment) {
11020                 .base = vmcs12->host_tr_base,
11021                 .limit = 0x67,
11022                 .selector = vmcs12->host_tr_selector,
11023                 .type = 11,
11024                 .present = 1
11025         };
11026         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11027
11028         kvm_set_dr(vcpu, 7, 0x400);
11029         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11030
11031         if (cpu_has_vmx_msr_bitmap())
11032                 vmx_set_msr_bitmap(vcpu);
11033
11034         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11035                                 vmcs12->vm_exit_msr_load_count))
11036                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11037 }
11038
11039 /*
11040  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11041  * and modify vmcs12 to make it see what it would expect to see there if
11042  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11043  */
11044 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11045                               u32 exit_intr_info,
11046                               unsigned long exit_qualification)
11047 {
11048         struct vcpu_vmx *vmx = to_vmx(vcpu);
11049         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11050         u32 vm_inst_error = 0;
11051
11052         /* trying to cancel vmlaunch/vmresume is a bug */
11053         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11054
11055         leave_guest_mode(vcpu);
11056         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11057                        exit_qualification);
11058
11059         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11060                                  vmcs12->vm_exit_msr_store_count))
11061                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11062
11063         if (unlikely(vmx->fail))
11064                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11065
11066         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11067
11068         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11069             && nested_exit_intr_ack_set(vcpu)) {
11070                 int irq = kvm_cpu_get_interrupt(vcpu);
11071                 WARN_ON(irq < 0);
11072                 vmcs12->vm_exit_intr_info = irq |
11073                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11074         }
11075
11076         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11077                                        vmcs12->exit_qualification,
11078                                        vmcs12->idt_vectoring_info_field,
11079                                        vmcs12->vm_exit_intr_info,
11080                                        vmcs12->vm_exit_intr_error_code,
11081                                        KVM_ISA_VMX);
11082
11083         vm_entry_controls_reset_shadow(vmx);
11084         vm_exit_controls_reset_shadow(vmx);
11085         vmx_segment_cache_clear(vmx);
11086
11087         /* if no vmcs02 cache requested, remove the one we used */
11088         if (VMCS02_POOL_SIZE == 0)
11089                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11090
11091         load_vmcs12_host_state(vcpu, vmcs12);
11092
11093         /* Update any VMCS fields that might have changed while L2 ran */
11094         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11095         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11096         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11097         if (vmx->hv_deadline_tsc == -1)
11098                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11099                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11100         else
11101                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11102                               PIN_BASED_VMX_PREEMPTION_TIMER);
11103         if (kvm_has_tsc_control)
11104                 decache_tsc_multiplier(vmx);
11105
11106         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11107                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11108                 vmx_set_virtual_x2apic_mode(vcpu,
11109                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11110         } else if (!nested_cpu_has_ept(vmcs12) &&
11111                    nested_cpu_has2(vmcs12,
11112                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11113                 vmx_flush_tlb_ept_only(vcpu);
11114         }
11115
11116         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11117         vmx->host_rsp = 0;
11118
11119         /* Unpin physical memory we referred to in vmcs02 */
11120         if (vmx->nested.apic_access_page) {
11121                 nested_release_page(vmx->nested.apic_access_page);
11122                 vmx->nested.apic_access_page = NULL;
11123         }
11124         if (vmx->nested.virtual_apic_page) {
11125                 nested_release_page(vmx->nested.virtual_apic_page);
11126                 vmx->nested.virtual_apic_page = NULL;
11127         }
11128         if (vmx->nested.pi_desc_page) {
11129                 kunmap(vmx->nested.pi_desc_page);
11130                 nested_release_page(vmx->nested.pi_desc_page);
11131                 vmx->nested.pi_desc_page = NULL;
11132                 vmx->nested.pi_desc = NULL;
11133         }
11134
11135         /*
11136          * We are now running in L2, mmu_notifier will force to reload the
11137          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11138          */
11139         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11140
11141         /*
11142          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11143          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11144          * success or failure flag accordingly.
11145          */
11146         if (unlikely(vmx->fail)) {
11147                 vmx->fail = 0;
11148                 nested_vmx_failValid(vcpu, vm_inst_error);
11149         } else
11150                 nested_vmx_succeed(vcpu);
11151         if (enable_shadow_vmcs)
11152                 vmx->nested.sync_shadow_vmcs = true;
11153
11154         /* in case we halted in L2 */
11155         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11156 }
11157
11158 /*
11159  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11160  */
11161 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11162 {
11163         if (is_guest_mode(vcpu)) {
11164                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11165                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11166         }
11167         free_nested(to_vmx(vcpu));
11168 }
11169
11170 /*
11171  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11172  * 23.7 "VM-entry failures during or after loading guest state" (this also
11173  * lists the acceptable exit-reason and exit-qualification parameters).
11174  * It should only be called before L2 actually succeeded to run, and when
11175  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11176  */
11177 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11178                         struct vmcs12 *vmcs12,
11179                         u32 reason, unsigned long qualification)
11180 {
11181         load_vmcs12_host_state(vcpu, vmcs12);
11182         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11183         vmcs12->exit_qualification = qualification;
11184         nested_vmx_succeed(vcpu);
11185         if (enable_shadow_vmcs)
11186                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11187 }
11188
11189 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11190                                struct x86_instruction_info *info,
11191                                enum x86_intercept_stage stage)
11192 {
11193         return X86EMUL_CONTINUE;
11194 }
11195
11196 #ifdef CONFIG_X86_64
11197 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11198 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11199                                   u64 divisor, u64 *result)
11200 {
11201         u64 low = a << shift, high = a >> (64 - shift);
11202
11203         /* To avoid the overflow on divq */
11204         if (high >= divisor)
11205                 return 1;
11206
11207         /* Low hold the result, high hold rem which is discarded */
11208         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11209             "rm" (divisor), "0" (low), "1" (high));
11210         *result = low;
11211
11212         return 0;
11213 }
11214
11215 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11216 {
11217         struct vcpu_vmx *vmx = to_vmx(vcpu);
11218         u64 tscl = rdtsc();
11219         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11220         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11221
11222         /* Convert to host delta tsc if tsc scaling is enabled */
11223         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11224                         u64_shl_div_u64(delta_tsc,
11225                                 kvm_tsc_scaling_ratio_frac_bits,
11226                                 vcpu->arch.tsc_scaling_ratio,
11227                                 &delta_tsc))
11228                 return -ERANGE;
11229
11230         /*
11231          * If the delta tsc can't fit in the 32 bit after the multi shift,
11232          * we can't use the preemption timer.
11233          * It's possible that it fits on later vmentries, but checking
11234          * on every vmentry is costly so we just use an hrtimer.
11235          */
11236         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11237                 return -ERANGE;
11238
11239         vmx->hv_deadline_tsc = tscl + delta_tsc;
11240         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11241                         PIN_BASED_VMX_PREEMPTION_TIMER);
11242
11243         return delta_tsc == 0;
11244 }
11245
11246 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11247 {
11248         struct vcpu_vmx *vmx = to_vmx(vcpu);
11249         vmx->hv_deadline_tsc = -1;
11250         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11251                         PIN_BASED_VMX_PREEMPTION_TIMER);
11252 }
11253 #endif
11254
11255 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11256 {
11257         if (ple_gap)
11258                 shrink_ple_window(vcpu);
11259 }
11260
11261 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11262                                      struct kvm_memory_slot *slot)
11263 {
11264         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11265         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11266 }
11267
11268 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11269                                        struct kvm_memory_slot *slot)
11270 {
11271         kvm_mmu_slot_set_dirty(kvm, slot);
11272 }
11273
11274 static void vmx_flush_log_dirty(struct kvm *kvm)
11275 {
11276         kvm_flush_pml_buffers(kvm);
11277 }
11278
11279 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11280 {
11281         struct vmcs12 *vmcs12;
11282         struct vcpu_vmx *vmx = to_vmx(vcpu);
11283         gpa_t gpa;
11284         struct page *page = NULL;
11285         u64 *pml_address;
11286
11287         if (is_guest_mode(vcpu)) {
11288                 WARN_ON_ONCE(vmx->nested.pml_full);
11289
11290                 /*
11291                  * Check if PML is enabled for the nested guest.
11292                  * Whether eptp bit 6 is set is already checked
11293                  * as part of A/D emulation.
11294                  */
11295                 vmcs12 = get_vmcs12(vcpu);
11296                 if (!nested_cpu_has_pml(vmcs12))
11297                         return 0;
11298
11299                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11300                         vmx->nested.pml_full = true;
11301                         return 1;
11302                 }
11303
11304                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11305
11306                 page = nested_get_page(vcpu, vmcs12->pml_address);
11307                 if (!page)
11308                         return 0;
11309
11310                 pml_address = kmap(page);
11311                 pml_address[vmcs12->guest_pml_index--] = gpa;
11312                 kunmap(page);
11313                 nested_release_page_clean(page);
11314         }
11315
11316         return 0;
11317 }
11318
11319 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11320                                            struct kvm_memory_slot *memslot,
11321                                            gfn_t offset, unsigned long mask)
11322 {
11323         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11324 }
11325
11326 /*
11327  * This routine does the following things for vCPU which is going
11328  * to be blocked if VT-d PI is enabled.
11329  * - Store the vCPU to the wakeup list, so when interrupts happen
11330  *   we can find the right vCPU to wake up.
11331  * - Change the Posted-interrupt descriptor as below:
11332  *      'NDST' <-- vcpu->pre_pcpu
11333  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11334  * - If 'ON' is set during this process, which means at least one
11335  *   interrupt is posted for this vCPU, we cannot block it, in
11336  *   this case, return 1, otherwise, return 0.
11337  *
11338  */
11339 static int pi_pre_block(struct kvm_vcpu *vcpu)
11340 {
11341         unsigned long flags;
11342         unsigned int dest;
11343         struct pi_desc old, new;
11344         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11345
11346         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11347                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11348                 !kvm_vcpu_apicv_active(vcpu))
11349                 return 0;
11350
11351         vcpu->pre_pcpu = vcpu->cpu;
11352         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11353                           vcpu->pre_pcpu), flags);
11354         list_add_tail(&vcpu->blocked_vcpu_list,
11355                       &per_cpu(blocked_vcpu_on_cpu,
11356                       vcpu->pre_pcpu));
11357         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11358                                vcpu->pre_pcpu), flags);
11359
11360         do {
11361                 old.control = new.control = pi_desc->control;
11362
11363                 /*
11364                  * We should not block the vCPU if
11365                  * an interrupt is posted for it.
11366                  */
11367                 if (pi_test_on(pi_desc) == 1) {
11368                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11369                                           vcpu->pre_pcpu), flags);
11370                         list_del(&vcpu->blocked_vcpu_list);
11371                         spin_unlock_irqrestore(
11372                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11373                                         vcpu->pre_pcpu), flags);
11374                         vcpu->pre_pcpu = -1;
11375
11376                         return 1;
11377                 }
11378
11379                 WARN((pi_desc->sn == 1),
11380                      "Warning: SN field of posted-interrupts "
11381                      "is set before blocking\n");
11382
11383                 /*
11384                  * Since vCPU can be preempted during this process,
11385                  * vcpu->cpu could be different with pre_pcpu, we
11386                  * need to set pre_pcpu as the destination of wakeup
11387                  * notification event, then we can find the right vCPU
11388                  * to wakeup in wakeup handler if interrupts happen
11389                  * when the vCPU is in blocked state.
11390                  */
11391                 dest = cpu_physical_id(vcpu->pre_pcpu);
11392
11393                 if (x2apic_enabled())
11394                         new.ndst = dest;
11395                 else
11396                         new.ndst = (dest << 8) & 0xFF00;
11397
11398                 /* set 'NV' to 'wakeup vector' */
11399                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11400         } while (cmpxchg(&pi_desc->control, old.control,
11401                         new.control) != old.control);
11402
11403         return 0;
11404 }
11405
11406 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11407 {
11408         if (pi_pre_block(vcpu))
11409                 return 1;
11410
11411         if (kvm_lapic_hv_timer_in_use(vcpu))
11412                 kvm_lapic_switch_to_sw_timer(vcpu);
11413
11414         return 0;
11415 }
11416
11417 static void pi_post_block(struct kvm_vcpu *vcpu)
11418 {
11419         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11420         struct pi_desc old, new;
11421         unsigned int dest;
11422         unsigned long flags;
11423
11424         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11425                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11426                 !kvm_vcpu_apicv_active(vcpu))
11427                 return;
11428
11429         do {
11430                 old.control = new.control = pi_desc->control;
11431
11432                 dest = cpu_physical_id(vcpu->cpu);
11433
11434                 if (x2apic_enabled())
11435                         new.ndst = dest;
11436                 else
11437                         new.ndst = (dest << 8) & 0xFF00;
11438
11439                 /* Allow posting non-urgent interrupts */
11440                 new.sn = 0;
11441
11442                 /* set 'NV' to 'notification vector' */
11443                 new.nv = POSTED_INTR_VECTOR;
11444         } while (cmpxchg(&pi_desc->control, old.control,
11445                         new.control) != old.control);
11446
11447         if(vcpu->pre_pcpu != -1) {
11448                 spin_lock_irqsave(
11449                         &per_cpu(blocked_vcpu_on_cpu_lock,
11450                         vcpu->pre_pcpu), flags);
11451                 list_del(&vcpu->blocked_vcpu_list);
11452                 spin_unlock_irqrestore(
11453                         &per_cpu(blocked_vcpu_on_cpu_lock,
11454                         vcpu->pre_pcpu), flags);
11455                 vcpu->pre_pcpu = -1;
11456         }
11457 }
11458
11459 static void vmx_post_block(struct kvm_vcpu *vcpu)
11460 {
11461         if (kvm_x86_ops->set_hv_timer)
11462                 kvm_lapic_switch_to_hv_timer(vcpu);
11463
11464         pi_post_block(vcpu);
11465 }
11466
11467 /*
11468  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11469  *
11470  * @kvm: kvm
11471  * @host_irq: host irq of the interrupt
11472  * @guest_irq: gsi of the interrupt
11473  * @set: set or unset PI
11474  * returns 0 on success, < 0 on failure
11475  */
11476 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11477                               uint32_t guest_irq, bool set)
11478 {
11479         struct kvm_kernel_irq_routing_entry *e;
11480         struct kvm_irq_routing_table *irq_rt;
11481         struct kvm_lapic_irq irq;
11482         struct kvm_vcpu *vcpu;
11483         struct vcpu_data vcpu_info;
11484         int idx, ret = -EINVAL;
11485
11486         if (!kvm_arch_has_assigned_device(kvm) ||
11487                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11488                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11489                 return 0;
11490
11491         idx = srcu_read_lock(&kvm->irq_srcu);
11492         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11493         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11494
11495         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11496                 if (e->type != KVM_IRQ_ROUTING_MSI)
11497                         continue;
11498                 /*
11499                  * VT-d PI cannot support posting multicast/broadcast
11500                  * interrupts to a vCPU, we still use interrupt remapping
11501                  * for these kind of interrupts.
11502                  *
11503                  * For lowest-priority interrupts, we only support
11504                  * those with single CPU as the destination, e.g. user
11505                  * configures the interrupts via /proc/irq or uses
11506                  * irqbalance to make the interrupts single-CPU.
11507                  *
11508                  * We will support full lowest-priority interrupt later.
11509                  */
11510
11511                 kvm_set_msi_irq(kvm, e, &irq);
11512                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11513                         /*
11514                          * Make sure the IRTE is in remapped mode if
11515                          * we don't handle it in posted mode.
11516                          */
11517                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11518                         if (ret < 0) {
11519                                 printk(KERN_INFO
11520                                    "failed to back to remapped mode, irq: %u\n",
11521                                    host_irq);
11522                                 goto out;
11523                         }
11524
11525                         continue;
11526                 }
11527
11528                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11529                 vcpu_info.vector = irq.vector;
11530
11531                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11532                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11533
11534                 if (set)
11535                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11536                 else {
11537                         /* suppress notification event before unposting */
11538                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11539                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11540                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11541                 }
11542
11543                 if (ret < 0) {
11544                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11545                                         __func__);
11546                         goto out;
11547                 }
11548         }
11549
11550         ret = 0;
11551 out:
11552         srcu_read_unlock(&kvm->irq_srcu, idx);
11553         return ret;
11554 }
11555
11556 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11557 {
11558         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11559                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11560                         FEATURE_CONTROL_LMCE;
11561         else
11562                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11563                         ~FEATURE_CONTROL_LMCE;
11564 }
11565
11566 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11567         .cpu_has_kvm_support = cpu_has_kvm_support,
11568         .disabled_by_bios = vmx_disabled_by_bios,
11569         .hardware_setup = hardware_setup,
11570         .hardware_unsetup = hardware_unsetup,
11571         .check_processor_compatibility = vmx_check_processor_compat,
11572         .hardware_enable = hardware_enable,
11573         .hardware_disable = hardware_disable,
11574         .cpu_has_accelerated_tpr = report_flexpriority,
11575         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11576
11577         .vcpu_create = vmx_create_vcpu,
11578         .vcpu_free = vmx_free_vcpu,
11579         .vcpu_reset = vmx_vcpu_reset,
11580
11581         .prepare_guest_switch = vmx_save_host_state,
11582         .vcpu_load = vmx_vcpu_load,
11583         .vcpu_put = vmx_vcpu_put,
11584
11585         .update_bp_intercept = update_exception_bitmap,
11586         .get_msr = vmx_get_msr,
11587         .set_msr = vmx_set_msr,
11588         .get_segment_base = vmx_get_segment_base,
11589         .get_segment = vmx_get_segment,
11590         .set_segment = vmx_set_segment,
11591         .get_cpl = vmx_get_cpl,
11592         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11593         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11594         .decache_cr3 = vmx_decache_cr3,
11595         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11596         .set_cr0 = vmx_set_cr0,
11597         .set_cr3 = vmx_set_cr3,
11598         .set_cr4 = vmx_set_cr4,
11599         .set_efer = vmx_set_efer,
11600         .get_idt = vmx_get_idt,
11601         .set_idt = vmx_set_idt,
11602         .get_gdt = vmx_get_gdt,
11603         .set_gdt = vmx_set_gdt,
11604         .get_dr6 = vmx_get_dr6,
11605         .set_dr6 = vmx_set_dr6,
11606         .set_dr7 = vmx_set_dr7,
11607         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11608         .cache_reg = vmx_cache_reg,
11609         .get_rflags = vmx_get_rflags,
11610         .set_rflags = vmx_set_rflags,
11611
11612         .get_pkru = vmx_get_pkru,
11613
11614         .tlb_flush = vmx_flush_tlb,
11615
11616         .run = vmx_vcpu_run,
11617         .handle_exit = vmx_handle_exit,
11618         .skip_emulated_instruction = skip_emulated_instruction,
11619         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11620         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11621         .patch_hypercall = vmx_patch_hypercall,
11622         .set_irq = vmx_inject_irq,
11623         .set_nmi = vmx_inject_nmi,
11624         .queue_exception = vmx_queue_exception,
11625         .cancel_injection = vmx_cancel_injection,
11626         .interrupt_allowed = vmx_interrupt_allowed,
11627         .nmi_allowed = vmx_nmi_allowed,
11628         .get_nmi_mask = vmx_get_nmi_mask,
11629         .set_nmi_mask = vmx_set_nmi_mask,
11630         .enable_nmi_window = enable_nmi_window,
11631         .enable_irq_window = enable_irq_window,
11632         .update_cr8_intercept = update_cr8_intercept,
11633         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11634         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11635         .get_enable_apicv = vmx_get_enable_apicv,
11636         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11637         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11638         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11639         .hwapic_irr_update = vmx_hwapic_irr_update,
11640         .hwapic_isr_update = vmx_hwapic_isr_update,
11641         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11642         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11643
11644         .set_tss_addr = vmx_set_tss_addr,
11645         .get_tdp_level = get_ept_level,
11646         .get_mt_mask = vmx_get_mt_mask,
11647
11648         .get_exit_info = vmx_get_exit_info,
11649
11650         .get_lpage_level = vmx_get_lpage_level,
11651
11652         .cpuid_update = vmx_cpuid_update,
11653
11654         .rdtscp_supported = vmx_rdtscp_supported,
11655         .invpcid_supported = vmx_invpcid_supported,
11656
11657         .set_supported_cpuid = vmx_set_supported_cpuid,
11658
11659         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11660
11661         .write_tsc_offset = vmx_write_tsc_offset,
11662
11663         .set_tdp_cr3 = vmx_set_cr3,
11664
11665         .check_intercept = vmx_check_intercept,
11666         .handle_external_intr = vmx_handle_external_intr,
11667         .mpx_supported = vmx_mpx_supported,
11668         .xsaves_supported = vmx_xsaves_supported,
11669
11670         .check_nested_events = vmx_check_nested_events,
11671
11672         .sched_in = vmx_sched_in,
11673
11674         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11675         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11676         .flush_log_dirty = vmx_flush_log_dirty,
11677         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11678         .write_log_dirty = vmx_write_pml_buffer,
11679
11680         .pre_block = vmx_pre_block,
11681         .post_block = vmx_post_block,
11682
11683         .pmu_ops = &intel_pmu_ops,
11684
11685         .update_pi_irte = vmx_update_pi_irte,
11686
11687 #ifdef CONFIG_X86_64
11688         .set_hv_timer = vmx_set_hv_timer,
11689         .cancel_hv_timer = vmx_cancel_hv_timer,
11690 #endif
11691
11692         .setup_mce = vmx_setup_mce,
11693 };
11694
11695 static int __init vmx_init(void)
11696 {
11697         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11698                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11699         if (r)
11700                 return r;
11701
11702 #ifdef CONFIG_KEXEC_CORE
11703         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11704                            crash_vmclear_local_loaded_vmcss);
11705 #endif
11706
11707         return 0;
11708 }
11709
11710 static void __exit vmx_exit(void)
11711 {
11712 #ifdef CONFIG_KEXEC_CORE
11713         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11714         synchronize_rcu();
11715 #endif
11716
11717         kvm_exit();
11718 }
11719
11720 module_init(vmx_init)
11721 module_exit(vmx_exit)