1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_H
3 #define __KVM_X86_VMX_H
5 #include <linux/kvm_host.h>
8 #include <asm/intel_pt.h>
10 #include "capabilities.h"
11 #include "../kvm_cache_regs.h"
12 #include "posted_intr.h"
16 #include "run_flags.h"
22 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
25 #define MAX_NR_USER_RETURN_MSRS 7
27 #define MAX_NR_USER_RETURN_MSRS 4
30 #define MAX_NR_LOADSTORE_MSRS 8
34 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS];
38 bool load_into_hardware;
43 enum segment_cache_field {
52 #define RTIT_ADDR_RANGE 4
60 u64 addr_a[RTIT_ADDR_RANGE];
61 u64 addr_b[RTIT_ADDR_RANGE];
66 u32 num_address_ranges;
67 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
72 union vmx_exit_reason {
85 u32 bus_lock_detected : 1;
87 u32 smi_pending_mtf : 1;
88 u32 smi_from_vmx_root : 1;
90 u32 failed_vmentry : 1;
95 #define vcpu_to_lbr_desc(vcpu) (&to_vmx(vcpu)->lbr_desc)
96 #define vcpu_to_lbr_records(vcpu) (&to_vmx(vcpu)->lbr_desc.records)
98 bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu);
99 bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu);
101 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu);
102 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu);
105 /* Basic info about guest LBR records. */
106 struct x86_pmu_lbr records;
109 * Emulate LBR feature via passthrough LBR registers when the
110 * per-vcpu guest LBR event is scheduled on the current pcpu.
112 * The records may be inaccurate if the host reclaims the LBR.
114 struct perf_event *event;
116 /* True if LBRs are marked as not intercepted in the MSR bitmap */
117 bool msr_passthrough;
121 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
122 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
125 /* Has the level1 guest done vmxon? */
130 /* The guest-physical address of the current VMCS L1 keeps for L2 */
133 * Cache of the guest's VMCS, existing outside of guest memory.
134 * Loaded from guest memory during VMPTRLD. Flushed to guest
135 * memory during VMCLEAR and VMPTRLD.
137 struct vmcs12 *cached_vmcs12;
139 * Cache of the guest's shadow VMCS, existing outside of guest
140 * memory. Loaded from guest memory during VM entry. Flushed
141 * to guest memory during VM exit.
143 struct vmcs12 *cached_shadow_vmcs12;
146 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer
148 struct gfn_to_hva_cache shadow_vmcs12_cache;
151 * GPA to HVA cache for VMCS12
153 struct gfn_to_hva_cache vmcs12_cache;
156 * Indicates if the shadow vmcs or enlightened vmcs must be updated
157 * with the data held by struct vmcs12.
159 bool need_vmcs12_to_shadow_sync;
163 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to
164 * changes in MSR bitmap for L1 or switching to a different L2. Note,
165 * this flag can only be used reliably in conjunction with a paravirt L1
166 * which informs L0 whether any changes to MSR bitmap for L2 were done
169 bool force_msr_bitmap_recalc;
172 * Indicates lazily loaded guest state has not yet been decached from
175 bool need_sync_vmcs02_to_vmcs12_rare;
178 * vmcs02 has been initialized, i.e. state that is constant for
179 * vmcs02 has been written to the backing VMCS. Initialization
180 * is delayed until L1 actually attempts to run a nested VM.
182 bool vmcs02_initialized;
184 bool change_vmcs01_virtual_apic_mode;
185 bool reload_vmcs01_apic_access_page;
186 bool update_vmcs01_cpu_dirty_logging;
187 bool update_vmcs01_apicv_status;
190 * Enlightened VMCS has been enabled. It does not mean that L1 has to
191 * use it. However, VMX features available to L1 will be limited based
192 * on what the enlightened VMCS supports.
194 bool enlightened_vmcs_enabled;
196 /* L2 must run next, and mustn't decide to exit to L1. */
197 bool nested_run_pending;
199 /* Pending MTF VM-exit into L1. */
202 struct loaded_vmcs vmcs02;
205 * Guest pages referred to in the vmcs02 with host-physical
206 * pointers, so we must keep them pinned while L2 runs.
208 struct page *apic_access_page;
209 struct kvm_host_map virtual_apic_map;
210 struct kvm_host_map pi_desc_map;
212 struct kvm_host_map msr_bitmap_map;
214 struct pi_desc *pi_desc;
218 struct hrtimer preemption_timer;
219 u64 preemption_timer_deadline;
220 bool has_preemption_timer_deadline;
221 bool preemption_timer_expired;
223 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
225 u64 vmcs01_guest_bndcfgs;
227 /* to migrate it to L1 if L2 writes to L1's CR8 directly */
228 int l1_tpr_threshold;
233 struct nested_vmx_msrs msrs;
235 /* SMM related state */
237 /* in VMX operation on SMM entry? */
239 /* in guest mode on SMM entry? */
243 gpa_t hv_evmcs_vmptr;
244 struct kvm_host_map hv_evmcs_map;
245 struct hv_enlightened_vmcs *hv_evmcs;
249 struct kvm_vcpu vcpu;
251 u8 x2apic_msr_bitmap_mode;
254 * If true, host state has been stored in vmx->loaded_vmcs for
255 * the CPU registers that only need to be switched when transitioning
256 * to/from the kernel, and the registers have been loaded with guest
257 * values. If false, host state is loaded in the CPU registers
258 * and vmx->loaded_vmcs->host_state is invalid.
260 bool guest_state_loaded;
262 unsigned long exit_qualification;
264 u32 idt_vectoring_info;
268 * User return MSRs are always emulated when enabled in the guest, but
269 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside
270 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to
271 * be loaded into hardware if those conditions aren't met.
273 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
274 bool guest_uret_msrs_loaded;
276 u64 msr_host_kernel_gs_base;
277 u64 msr_guest_kernel_gs_base;
281 u32 msr_ia32_umwait_control;
284 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
285 * non-nested (L1) guest, it always points to vmcs01. For a nested
286 * guest (L2), it points to a different VMCS.
288 struct loaded_vmcs vmcs01;
289 struct loaded_vmcs *loaded_vmcs;
291 struct msr_autoload {
292 struct vmx_msrs guest;
293 struct vmx_msrs host;
296 struct msr_autostore {
297 struct vmx_msrs guest;
303 struct kvm_segment segs[8];
306 u32 bitmask; /* 4 bits per segment (1 bit per field) */
307 struct kvm_save_segment {
315 bool emulation_required;
317 union vmx_exit_reason exit_reason;
319 /* Posted interrupt descriptor */
320 struct pi_desc pi_desc;
322 /* Used if this vCPU is waiting for PI notification wakeup. */
323 struct list_head pi_wakeup_list;
325 /* Support for a guest hypervisor (nested VMX) */
326 struct nested_vmx nested;
328 /* Dynamic PLE window. */
329 unsigned int ple_window;
330 bool ple_window_dirty;
332 bool req_immediate_exit;
334 /* Support for PML */
335 #define PML_ENTITY_NUM 512
338 /* apic deadline value in host tsc */
341 unsigned long host_debugctlmsr;
344 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
345 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
346 * in msr_ia32_feature_control_valid_bits.
348 u64 msr_ia32_feature_control;
349 u64 msr_ia32_feature_control_valid_bits;
350 /* SGX Launch Control public key hash */
351 u64 msr_ia32_sgxlepubkeyhash[4];
352 u64 msr_ia32_mcu_opt_ctrl;
353 bool disable_fb_clear;
355 struct pt_desc pt_desc;
356 struct lbr_desc lbr_desc;
358 /* Save desired MSR intercept (read: pass-through) state */
359 #define MAX_POSSIBLE_PASSTHROUGH_MSRS 15
361 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
362 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
363 } shadow_msr_intercept;
369 unsigned int tss_addr;
370 bool ept_identity_pagetable_done;
371 gpa_t ept_identity_map_addr;
374 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
375 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
376 struct loaded_vmcs *buddy);
377 int allocate_vpid(void);
378 void free_vpid(int vpid);
379 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
380 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
381 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
382 unsigned long fs_base, unsigned long gs_base);
383 int vmx_get_cpl(struct kvm_vcpu *vcpu);
384 bool vmx_emulation_required(struct kvm_vcpu *vcpu);
385 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
386 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
387 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
388 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
389 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
390 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
391 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
392 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
393 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
394 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
395 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
396 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level);
398 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu);
399 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu);
400 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
401 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
402 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
403 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
404 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
405 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
406 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
407 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
408 void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags);
409 unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx);
410 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs,
412 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
413 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
415 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
416 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
418 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu);
419 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu);
421 static inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr,
422 int type, bool value)
425 vmx_enable_intercept_for_msr(vcpu, msr, type);
427 vmx_disable_intercept_for_msr(vcpu, msr, type);
430 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu);
433 * Note, early Intel manuals have the write-low and read-high bitmap offsets
434 * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and
435 * 0xc0000000-0xc0001fff. The former (low) uses bytes 0-0x3ff for reads and
436 * 0x800-0xbff for writes. The latter (high) uses 0x400-0x7ff for reads and
437 * 0xc00-0xfff for writes. MSRs not covered by either of the ranges always
440 #define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base) \
441 static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap, \
444 int f = sizeof(unsigned long); \
447 return bitop##_bit(msr, bitmap + base / f); \
448 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) \
449 return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \
450 return (rtype)true; \
452 #define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop) \
453 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0x0) \
454 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800)
456 BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test)
457 BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear)
458 BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set)
460 static inline u8 vmx_get_rvi(void)
462 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
465 #define BUILD_CONTROLS_SHADOW(lname, uname) \
466 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
468 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
469 vmcs_write32(uname, val); \
470 vmx->loaded_vmcs->controls_shadow.lname = val; \
473 static inline u32 __##lname##_controls_get(struct loaded_vmcs *vmcs) \
475 return vmcs->controls_shadow.lname; \
477 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \
479 return __##lname##_controls_get(vmx->loaded_vmcs); \
481 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \
483 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
485 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
487 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
489 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
490 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
491 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
492 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
493 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
496 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the
497 * cache on demand. Other registers not listed here are synced to
498 * the cache immediately after VM-Exit.
500 #define VMX_REGS_LAZY_LOAD_SET ((1 << VCPU_REGS_RIP) | \
501 (1 << VCPU_REGS_RSP) | \
502 (1 << VCPU_EXREG_RFLAGS) | \
503 (1 << VCPU_EXREG_PDPTR) | \
504 (1 << VCPU_EXREG_SEGMENTS) | \
505 (1 << VCPU_EXREG_CR0) | \
506 (1 << VCPU_EXREG_CR3) | \
507 (1 << VCPU_EXREG_CR4) | \
508 (1 << VCPU_EXREG_EXIT_INFO_1) | \
509 (1 << VCPU_EXREG_EXIT_INFO_2))
511 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
513 return container_of(kvm, struct kvm_vmx, kvm);
516 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
518 return container_of(vcpu, struct vcpu_vmx, vcpu);
521 static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
523 struct vcpu_vmx *vmx = to_vmx(vcpu);
525 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) {
526 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
527 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
529 return vmx->exit_qualification;
532 static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
534 struct vcpu_vmx *vmx = to_vmx(vcpu);
536 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) {
537 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
538 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
540 return vmx->exit_intr_info;
543 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
544 void free_vmcs(struct vmcs *vmcs);
545 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
546 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
547 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
549 static inline struct vmcs *alloc_vmcs(bool shadow)
551 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
555 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
557 return secondary_exec_controls_get(vmx) &
558 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
561 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
566 return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits;
569 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
571 return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
572 (secondary_exec_controls_get(to_vmx(vcpu)) &
573 SECONDARY_EXEC_UNRESTRICTED_GUEST));
576 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
577 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
579 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
582 void dump_vmcs(struct kvm_vcpu *vcpu);
584 static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info)
586 return (vmx_instr_info >> 28) & 0xf;
589 #endif /* __KVM_X86_VMX_H */