1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_H
3 #define __KVM_X86_VMX_H
5 #include <linux/kvm_host.h>
8 #include <asm/intel_pt.h>
10 #include "capabilities.h"
11 #include "kvm_cache_regs.h"
12 #include "posted_intr.h"
17 extern const u32 vmx_msr_index[];
23 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
26 #define MAX_NR_USER_RETURN_MSRS 7
28 #define MAX_NR_USER_RETURN_MSRS 4
31 #define MAX_NR_LOADSTORE_MSRS 8
35 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS];
39 unsigned int slot; /* The MSR's slot in kvm_user_return_msrs. */
44 enum segment_cache_field {
53 #define RTIT_ADDR_RANGE 4
61 u64 addr_a[RTIT_ADDR_RANGE];
62 u64 addr_b[RTIT_ADDR_RANGE];
68 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
74 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
75 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
78 /* Has the level1 guest done vmxon? */
83 /* The guest-physical address of the current VMCS L1 keeps for L2 */
86 * Cache of the guest's VMCS, existing outside of guest memory.
87 * Loaded from guest memory during VMPTRLD. Flushed to guest
88 * memory during VMCLEAR and VMPTRLD.
90 struct vmcs12 *cached_vmcs12;
92 * Cache of the guest's shadow VMCS, existing outside of guest
93 * memory. Loaded from guest memory during VM entry. Flushed
94 * to guest memory during VM exit.
96 struct vmcs12 *cached_shadow_vmcs12;
99 * Indicates if the shadow vmcs or enlightened vmcs must be updated
100 * with the data held by struct vmcs12.
102 bool need_vmcs12_to_shadow_sync;
106 * Indicates lazily loaded guest state has not yet been decached from
109 bool need_sync_vmcs02_to_vmcs12_rare;
112 * vmcs02 has been initialized, i.e. state that is constant for
113 * vmcs02 has been written to the backing VMCS. Initialization
114 * is delayed until L1 actually attempts to run a nested VM.
116 bool vmcs02_initialized;
118 bool change_vmcs01_virtual_apic_mode;
119 bool reload_vmcs01_apic_access_page;
122 * Enlightened VMCS has been enabled. It does not mean that L1 has to
123 * use it. However, VMX features available to L1 will be limited based
124 * on what the enlightened VMCS supports.
126 bool enlightened_vmcs_enabled;
128 /* L2 must run next, and mustn't decide to exit to L1. */
129 bool nested_run_pending;
131 /* Pending MTF VM-exit into L1. */
134 struct loaded_vmcs vmcs02;
137 * Guest pages referred to in the vmcs02 with host-physical
138 * pointers, so we must keep them pinned while L2 runs.
140 struct page *apic_access_page;
141 struct kvm_host_map virtual_apic_map;
142 struct kvm_host_map pi_desc_map;
144 struct kvm_host_map msr_bitmap_map;
146 struct pi_desc *pi_desc;
150 struct hrtimer preemption_timer;
151 u64 preemption_timer_deadline;
152 bool has_preemption_timer_deadline;
153 bool preemption_timer_expired;
155 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
157 u64 vmcs01_guest_bndcfgs;
159 /* to migrate it to L1 if L2 writes to L1's CR8 directly */
160 int l1_tpr_threshold;
165 struct nested_vmx_msrs msrs;
167 /* SMM related state */
169 /* in VMX operation on SMM entry? */
171 /* in guest mode on SMM entry? */
175 gpa_t hv_evmcs_vmptr;
176 struct kvm_host_map hv_evmcs_map;
177 struct hv_enlightened_vmcs *hv_evmcs;
181 struct kvm_vcpu vcpu;
186 * If true, host state has been stored in vmx->loaded_vmcs for
187 * the CPU registers that only need to be switched when transitioning
188 * to/from the kernel, and the registers have been loaded with guest
189 * values. If false, host state is loaded in the CPU registers
190 * and vmx->loaded_vmcs->host_state is invalid.
192 bool guest_state_loaded;
194 unsigned long exit_qualification;
196 u32 idt_vectoring_info;
199 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
201 int nr_active_uret_msrs;
202 bool guest_uret_msrs_loaded;
204 u64 msr_host_kernel_gs_base;
205 u64 msr_guest_kernel_gs_base;
209 u32 msr_ia32_umwait_control;
211 u32 secondary_exec_control;
214 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
215 * non-nested (L1) guest, it always points to vmcs01. For a nested
216 * guest (L2), it points to a different VMCS.
218 struct loaded_vmcs vmcs01;
219 struct loaded_vmcs *loaded_vmcs;
221 struct msr_autoload {
222 struct vmx_msrs guest;
223 struct vmx_msrs host;
226 struct msr_autostore {
227 struct vmx_msrs guest;
233 struct kvm_segment segs[8];
236 u32 bitmask; /* 4 bits per segment (1 bit per field) */
237 struct kvm_save_segment {
245 bool emulation_required;
249 /* Posted interrupt descriptor */
250 struct pi_desc pi_desc;
252 /* Support for a guest hypervisor (nested VMX) */
253 struct nested_vmx nested;
255 /* Dynamic PLE window. */
256 unsigned int ple_window;
257 bool ple_window_dirty;
259 bool req_immediate_exit;
261 /* Support for PML */
262 #define PML_ENTITY_NUM 512
265 /* apic deadline value in host tsc */
268 u64 current_tsc_ratio;
270 unsigned long host_debugctlmsr;
273 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
274 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
275 * in msr_ia32_feature_control_valid_bits.
277 u64 msr_ia32_feature_control;
278 u64 msr_ia32_feature_control_valid_bits;
281 struct pt_desc pt_desc;
284 enum ept_pointers_status {
285 EPT_POINTERS_CHECK = 0,
286 EPT_POINTERS_MATCH = 1,
287 EPT_POINTERS_MISMATCH = 2
293 unsigned int tss_addr;
294 bool ept_identity_pagetable_done;
295 gpa_t ept_identity_map_addr;
297 enum ept_pointers_status ept_pointers_match;
298 spinlock_t ept_pointer_lock;
301 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
302 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
303 struct loaded_vmcs *buddy);
304 int allocate_vpid(void);
305 void free_vpid(int vpid);
306 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
307 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
308 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
309 unsigned long fs_base, unsigned long gs_base);
310 int vmx_get_cpl(struct kvm_vcpu *vcpu);
311 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
312 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
313 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
314 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
315 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
316 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
317 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
318 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
319 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
320 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
321 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
322 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa,
325 void update_exception_bitmap(struct kvm_vcpu *vcpu);
326 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
327 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
328 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
329 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
330 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
331 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
332 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
333 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);
334 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
335 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
336 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
338 static inline u8 vmx_get_rvi(void)
340 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
343 #define BUILD_CONTROLS_SHADOW(lname, uname) \
344 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
346 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
347 vmcs_write32(uname, val); \
348 vmx->loaded_vmcs->controls_shadow.lname = val; \
351 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \
353 return vmx->loaded_vmcs->controls_shadow.lname; \
355 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \
357 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
359 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
361 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
363 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
364 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
365 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
366 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
367 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
369 static inline void vmx_register_cache_reset(struct kvm_vcpu *vcpu)
371 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
372 | (1 << VCPU_EXREG_RFLAGS)
373 | (1 << VCPU_EXREG_PDPTR)
374 | (1 << VCPU_EXREG_SEGMENTS)
375 | (1 << VCPU_EXREG_CR0)
376 | (1 << VCPU_EXREG_CR3)
377 | (1 << VCPU_EXREG_CR4)
378 | (1 << VCPU_EXREG_EXIT_INFO_1)
379 | (1 << VCPU_EXREG_EXIT_INFO_2));
380 vcpu->arch.regs_dirty = 0;
383 static inline u32 vmx_vmentry_ctrl(void)
385 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
386 if (vmx_pt_mode_is_system())
387 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
388 VM_ENTRY_LOAD_IA32_RTIT_CTL);
389 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
390 return vmentry_ctrl &
391 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
394 static inline u32 vmx_vmexit_ctrl(void)
396 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
397 if (vmx_pt_mode_is_system())
398 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
399 VM_EXIT_CLEAR_IA32_RTIT_CTL);
400 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
402 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
405 u32 vmx_exec_control(struct vcpu_vmx *vmx);
406 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx);
408 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
410 return container_of(kvm, struct kvm_vmx, kvm);
413 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
415 return container_of(vcpu, struct vcpu_vmx, vcpu);
418 static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
420 struct vcpu_vmx *vmx = to_vmx(vcpu);
422 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) {
423 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
424 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
426 return vmx->exit_qualification;
429 static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
431 struct vcpu_vmx *vmx = to_vmx(vcpu);
433 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) {
434 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
435 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
437 return vmx->exit_intr_info;
440 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
441 void free_vmcs(struct vmcs *vmcs);
442 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
443 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
444 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
446 static inline struct vmcs *alloc_vmcs(bool shadow)
448 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
452 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
454 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
455 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
458 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
460 return vmx->secondary_exec_control &
461 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
464 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
466 return !enable_ept || cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits;
469 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
471 return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
472 (secondary_exec_controls_get(to_vmx(vcpu)) &
473 SECONDARY_EXEC_UNRESTRICTED_GUEST));
476 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
477 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
479 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
482 void dump_vmcs(void);
484 #endif /* __KVM_X86_VMX_H */