1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_H
3 #define __KVM_X86_VMX_H
5 #include <linux/kvm_host.h>
8 #include <asm/intel_pt.h>
10 #include "capabilities.h"
11 #include "kvm_cache_regs.h"
12 #include "posted_intr.h"
21 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
24 #define MAX_NR_USER_RETURN_MSRS 7
26 #define MAX_NR_USER_RETURN_MSRS 4
29 #define MAX_NR_LOADSTORE_MSRS 8
33 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS];
37 bool load_into_hardware;
42 enum segment_cache_field {
51 #define RTIT_ADDR_RANGE 4
59 u64 addr_a[RTIT_ADDR_RANGE];
60 u64 addr_b[RTIT_ADDR_RANGE];
65 u32 num_address_ranges;
66 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
71 union vmx_exit_reason {
84 u32 bus_lock_detected : 1;
86 u32 smi_pending_mtf : 1;
87 u32 smi_from_vmx_root : 1;
89 u32 failed_vmentry : 1;
94 #define vcpu_to_lbr_desc(vcpu) (&to_vmx(vcpu)->lbr_desc)
95 #define vcpu_to_lbr_records(vcpu) (&to_vmx(vcpu)->lbr_desc.records)
97 bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu);
98 bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu);
100 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu);
101 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu);
104 /* Basic info about guest LBR records. */
105 struct x86_pmu_lbr records;
108 * Emulate LBR feature via passthrough LBR registers when the
109 * per-vcpu guest LBR event is scheduled on the current pcpu.
111 * The records may be inaccurate if the host reclaims the LBR.
113 struct perf_event *event;
115 /* True if LBRs are marked as not intercepted in the MSR bitmap */
116 bool msr_passthrough;
120 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
121 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
124 /* Has the level1 guest done vmxon? */
129 /* The guest-physical address of the current VMCS L1 keeps for L2 */
132 * Cache of the guest's VMCS, existing outside of guest memory.
133 * Loaded from guest memory during VMPTRLD. Flushed to guest
134 * memory during VMCLEAR and VMPTRLD.
136 struct vmcs12 *cached_vmcs12;
138 * Cache of the guest's shadow VMCS, existing outside of guest
139 * memory. Loaded from guest memory during VM entry. Flushed
140 * to guest memory during VM exit.
142 struct vmcs12 *cached_shadow_vmcs12;
145 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer
147 struct gfn_to_hva_cache shadow_vmcs12_cache;
150 * GPA to HVA cache for VMCS12
152 struct gfn_to_hva_cache vmcs12_cache;
155 * Indicates if the shadow vmcs or enlightened vmcs must be updated
156 * with the data held by struct vmcs12.
158 bool need_vmcs12_to_shadow_sync;
162 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to
163 * changes in MSR bitmap for L1 or switching to a different L2. Note,
164 * this flag can only be used reliably in conjunction with a paravirt L1
165 * which informs L0 whether any changes to MSR bitmap for L2 were done
168 bool force_msr_bitmap_recalc;
171 * Indicates lazily loaded guest state has not yet been decached from
174 bool need_sync_vmcs02_to_vmcs12_rare;
177 * vmcs02 has been initialized, i.e. state that is constant for
178 * vmcs02 has been written to the backing VMCS. Initialization
179 * is delayed until L1 actually attempts to run a nested VM.
181 bool vmcs02_initialized;
183 bool change_vmcs01_virtual_apic_mode;
184 bool reload_vmcs01_apic_access_page;
185 bool update_vmcs01_cpu_dirty_logging;
188 * Enlightened VMCS has been enabled. It does not mean that L1 has to
189 * use it. However, VMX features available to L1 will be limited based
190 * on what the enlightened VMCS supports.
192 bool enlightened_vmcs_enabled;
194 /* L2 must run next, and mustn't decide to exit to L1. */
195 bool nested_run_pending;
197 /* Pending MTF VM-exit into L1. */
200 struct loaded_vmcs vmcs02;
203 * Guest pages referred to in the vmcs02 with host-physical
204 * pointers, so we must keep them pinned while L2 runs.
206 struct page *apic_access_page;
207 struct kvm_host_map virtual_apic_map;
208 struct kvm_host_map pi_desc_map;
210 struct kvm_host_map msr_bitmap_map;
212 struct pi_desc *pi_desc;
216 struct hrtimer preemption_timer;
217 u64 preemption_timer_deadline;
218 bool has_preemption_timer_deadline;
219 bool preemption_timer_expired;
221 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
223 u64 vmcs01_guest_bndcfgs;
225 /* to migrate it to L1 if L2 writes to L1's CR8 directly */
226 int l1_tpr_threshold;
231 struct nested_vmx_msrs msrs;
233 /* SMM related state */
235 /* in VMX operation on SMM entry? */
237 /* in guest mode on SMM entry? */
241 gpa_t hv_evmcs_vmptr;
242 struct kvm_host_map hv_evmcs_map;
243 struct hv_enlightened_vmcs *hv_evmcs;
247 struct kvm_vcpu vcpu;
249 u8 x2apic_msr_bitmap_mode;
252 * If true, host state has been stored in vmx->loaded_vmcs for
253 * the CPU registers that only need to be switched when transitioning
254 * to/from the kernel, and the registers have been loaded with guest
255 * values. If false, host state is loaded in the CPU registers
256 * and vmx->loaded_vmcs->host_state is invalid.
258 bool guest_state_loaded;
260 unsigned long exit_qualification;
262 u32 idt_vectoring_info;
266 * User return MSRs are always emulated when enabled in the guest, but
267 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside
268 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to
269 * be loaded into hardware if those conditions aren't met.
271 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
272 bool guest_uret_msrs_loaded;
274 u64 msr_host_kernel_gs_base;
275 u64 msr_guest_kernel_gs_base;
279 u32 msr_ia32_umwait_control;
282 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
283 * non-nested (L1) guest, it always points to vmcs01. For a nested
284 * guest (L2), it points to a different VMCS.
286 struct loaded_vmcs vmcs01;
287 struct loaded_vmcs *loaded_vmcs;
289 struct msr_autoload {
290 struct vmx_msrs guest;
291 struct vmx_msrs host;
294 struct msr_autostore {
295 struct vmx_msrs guest;
301 struct kvm_segment segs[8];
304 u32 bitmask; /* 4 bits per segment (1 bit per field) */
305 struct kvm_save_segment {
313 bool emulation_required;
315 union vmx_exit_reason exit_reason;
317 /* Posted interrupt descriptor */
318 struct pi_desc pi_desc;
320 /* Support for a guest hypervisor (nested VMX) */
321 struct nested_vmx nested;
323 /* Dynamic PLE window. */
324 unsigned int ple_window;
325 bool ple_window_dirty;
327 bool req_immediate_exit;
329 /* Support for PML */
330 #define PML_ENTITY_NUM 512
333 /* apic deadline value in host tsc */
336 unsigned long host_debugctlmsr;
339 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
340 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
341 * in msr_ia32_feature_control_valid_bits.
343 u64 msr_ia32_feature_control;
344 u64 msr_ia32_feature_control_valid_bits;
345 /* SGX Launch Control public key hash */
346 u64 msr_ia32_sgxlepubkeyhash[4];
348 struct pt_desc pt_desc;
349 struct lbr_desc lbr_desc;
351 /* Save desired MSR intercept (read: pass-through) state */
352 #define MAX_POSSIBLE_PASSTHROUGH_MSRS 13
354 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
355 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
356 } shadow_msr_intercept;
362 unsigned int tss_addr;
363 bool ept_identity_pagetable_done;
364 gpa_t ept_identity_map_addr;
367 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
368 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
369 struct loaded_vmcs *buddy);
370 int allocate_vpid(void);
371 void free_vpid(int vpid);
372 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
373 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
374 void vmx_set_vmcs_host_state(struct vmcs_host_state *host, unsigned long cr3,
375 u16 fs_sel, u16 gs_sel,
376 unsigned long fs_base, unsigned long gs_base);
377 int vmx_get_cpl(struct kvm_vcpu *vcpu);
378 bool vmx_emulation_required(struct kvm_vcpu *vcpu);
379 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
380 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
381 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
382 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
383 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
384 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
385 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
386 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
387 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
388 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
389 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
390 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level);
392 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu);
393 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu);
394 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
395 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
396 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
397 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
398 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
399 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
400 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
401 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
402 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
403 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
404 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
406 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
407 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
409 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu);
410 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu);
412 static inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr,
413 int type, bool value)
416 vmx_enable_intercept_for_msr(vcpu, msr, type);
418 vmx_disable_intercept_for_msr(vcpu, msr, type);
421 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu);
424 * Note, early Intel manuals have the write-low and read-high bitmap offsets
425 * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and
426 * 0xc0000000-0xc0001fff. The former (low) uses bytes 0-0x3ff for reads and
427 * 0x800-0xbff for writes. The latter (high) uses 0x400-0x7ff for reads and
428 * 0xc00-0xfff for writes. MSRs not covered by either of the ranges always
431 #define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base) \
432 static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap, \
435 int f = sizeof(unsigned long); \
438 return bitop##_bit(msr, bitmap + base / f); \
439 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) \
440 return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \
441 return (rtype)true; \
443 #define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop) \
444 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0x0) \
445 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800)
447 BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test)
448 BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear)
449 BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set)
451 static inline u8 vmx_get_rvi(void)
453 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
456 #define BUILD_CONTROLS_SHADOW(lname, uname) \
457 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
459 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
460 vmcs_write32(uname, val); \
461 vmx->loaded_vmcs->controls_shadow.lname = val; \
464 static inline u32 __##lname##_controls_get(struct loaded_vmcs *vmcs) \
466 return vmcs->controls_shadow.lname; \
468 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \
470 return __##lname##_controls_get(vmx->loaded_vmcs); \
472 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \
474 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
476 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
478 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
480 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
481 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
482 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
483 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
484 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
487 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the
488 * cache on demand. Other registers not listed here are synced to
489 * the cache immediately after VM-Exit.
491 #define VMX_REGS_LAZY_LOAD_SET ((1 << VCPU_REGS_RIP) | \
492 (1 << VCPU_REGS_RSP) | \
493 (1 << VCPU_EXREG_RFLAGS) | \
494 (1 << VCPU_EXREG_PDPTR) | \
495 (1 << VCPU_EXREG_SEGMENTS) | \
496 (1 << VCPU_EXREG_CR0) | \
497 (1 << VCPU_EXREG_CR3) | \
498 (1 << VCPU_EXREG_CR4) | \
499 (1 << VCPU_EXREG_EXIT_INFO_1) | \
500 (1 << VCPU_EXREG_EXIT_INFO_2))
502 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
504 return container_of(kvm, struct kvm_vmx, kvm);
507 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
509 return container_of(vcpu, struct vcpu_vmx, vcpu);
512 static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
514 struct vcpu_vmx *vmx = to_vmx(vcpu);
516 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) {
517 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
518 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
520 return vmx->exit_qualification;
523 static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
525 struct vcpu_vmx *vmx = to_vmx(vcpu);
527 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) {
528 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
529 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
531 return vmx->exit_intr_info;
534 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
535 void free_vmcs(struct vmcs *vmcs);
536 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
537 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
538 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
540 static inline struct vmcs *alloc_vmcs(bool shadow)
542 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
546 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
548 return secondary_exec_controls_get(vmx) &
549 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
552 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
557 return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits;
560 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
562 return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
563 (secondary_exec_controls_get(to_vmx(vcpu)) &
564 SECONDARY_EXEC_UNRESTRICTED_GUEST));
567 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
568 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
570 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
573 void dump_vmcs(struct kvm_vcpu *vcpu);
575 static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info)
577 return (vmx_instr_info >> 28) & 0xf;
580 #endif /* __KVM_X86_VMX_H */