1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/highmem.h>
17 #include <linux/hrtimer.h>
18 #include <linux/kernel.h>
19 #include <linux/kvm_host.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/mod_devicetable.h>
24 #include <linux/objtool.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
30 #include <linux/entry-kvm.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/debugreg.h>
38 #include <asm/fpu/api.h>
39 #include <asm/idtentry.h>
41 #include <asm/irq_remapping.h>
42 #include <asm/kexec.h>
43 #include <asm/perf_event.h>
44 #include <asm/mmu_context.h>
45 #include <asm/mshyperv.h>
46 #include <asm/mwait.h>
47 #include <asm/spec-ctrl.h>
48 #include <asm/virtext.h>
51 #include "capabilities.h"
55 #include "kvm_onhyperv.h"
57 #include "kvm_cache_regs.h"
69 MODULE_AUTHOR("Qumranet");
70 MODULE_LICENSE("GPL");
73 static const struct x86_cpu_id vmx_cpu_id[] = {
74 X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
77 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
80 bool __read_mostly enable_vpid = 1;
81 module_param_named(vpid, enable_vpid, bool, 0444);
83 static bool __read_mostly enable_vnmi = 1;
84 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
86 bool __read_mostly flexpriority_enabled = 1;
87 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
89 bool __read_mostly enable_ept = 1;
90 module_param_named(ept, enable_ept, bool, S_IRUGO);
92 bool __read_mostly enable_unrestricted_guest = 1;
93 module_param_named(unrestricted_guest,
94 enable_unrestricted_guest, bool, S_IRUGO);
96 bool __read_mostly enable_ept_ad_bits = 1;
97 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
99 static bool __read_mostly emulate_invalid_guest_state = true;
100 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
102 static bool __read_mostly fasteoi = 1;
103 module_param(fasteoi, bool, S_IRUGO);
105 module_param(enable_apicv, bool, S_IRUGO);
108 * If nested=1, nested virtualization is supported, i.e., guests may use
109 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
110 * use VMX instructions.
112 static bool __read_mostly nested = 1;
113 module_param(nested, bool, S_IRUGO);
115 bool __read_mostly enable_pml = 1;
116 module_param_named(pml, enable_pml, bool, S_IRUGO);
118 static bool __read_mostly dump_invalid_vmcs = 0;
119 module_param(dump_invalid_vmcs, bool, 0644);
121 #define MSR_BITMAP_MODE_X2APIC 1
122 #define MSR_BITMAP_MODE_X2APIC_APICV 2
124 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
126 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
127 static int __read_mostly cpu_preemption_timer_multi;
128 static bool __read_mostly enable_preemption_timer = 1;
130 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
133 extern bool __read_mostly allow_smaller_maxphyaddr;
134 module_param(allow_smaller_maxphyaddr, bool, S_IRUGO);
136 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
137 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
138 #define KVM_VM_CR0_ALWAYS_ON \
139 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
141 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
142 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
143 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
145 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
147 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
148 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
149 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
150 RTIT_STATUS_BYTECNT))
153 * List of MSRs that can be directly passed to the guest.
154 * In addition to these x2apic and PT MSRs are handled specially.
156 static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = {
165 MSR_IA32_SYSENTER_CS,
166 MSR_IA32_SYSENTER_ESP,
167 MSR_IA32_SYSENTER_EIP,
169 MSR_CORE_C3_RESIDENCY,
170 MSR_CORE_C6_RESIDENCY,
171 MSR_CORE_C7_RESIDENCY,
175 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
176 * ple_gap: upper bound on the amount of time between two successive
177 * executions of PAUSE in a loop. Also indicate if ple enabled.
178 * According to test, this time is usually smaller than 128 cycles.
179 * ple_window: upper bound on the amount of time a guest is allowed to execute
180 * in a PAUSE loop. Tests indicate that most spinlocks are held for
181 * less than 2^12 cycles
182 * Time is measured based on a counter that runs at the same rate as the TSC,
183 * refer SDM volume 3b section 21.6.13 & 22.1.3.
185 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
186 module_param(ple_gap, uint, 0444);
188 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
189 module_param(ple_window, uint, 0444);
191 /* Default doubles per-vcpu window every exit. */
192 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
193 module_param(ple_window_grow, uint, 0444);
195 /* Default resets per-vcpu window every exit to ple_window. */
196 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
197 module_param(ple_window_shrink, uint, 0444);
199 /* Default is to compute the maximum so we can never overflow. */
200 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
201 module_param(ple_window_max, uint, 0444);
203 /* Default is SYSTEM mode, 1 for host-guest mode */
204 int __read_mostly pt_mode = PT_MODE_SYSTEM;
205 module_param(pt_mode, int, S_IRUGO);
207 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
208 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
209 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
211 /* Storage for pre module init parameter parsing */
212 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
214 static const struct {
217 } vmentry_l1d_param[] = {
218 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
219 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
220 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
221 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
222 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
223 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
226 #define L1D_CACHE_ORDER 4
227 static void *vmx_l1d_flush_pages;
229 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
234 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
235 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
240 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
244 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
247 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
248 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
249 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
254 /* If set to auto use the default l1tf mitigation method */
255 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
256 switch (l1tf_mitigation) {
257 case L1TF_MITIGATION_OFF:
258 l1tf = VMENTER_L1D_FLUSH_NEVER;
260 case L1TF_MITIGATION_FLUSH_NOWARN:
261 case L1TF_MITIGATION_FLUSH:
262 case L1TF_MITIGATION_FLUSH_NOSMT:
263 l1tf = VMENTER_L1D_FLUSH_COND;
265 case L1TF_MITIGATION_FULL:
266 case L1TF_MITIGATION_FULL_FORCE:
267 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
270 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
271 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
274 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
275 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
277 * This allocation for vmx_l1d_flush_pages is not tied to a VM
278 * lifetime and so should not be charged to a memcg.
280 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
283 vmx_l1d_flush_pages = page_address(page);
286 * Initialize each page with a different pattern in
287 * order to protect against KSM in the nested
288 * virtualization case.
290 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
291 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
296 l1tf_vmx_mitigation = l1tf;
298 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
299 static_branch_enable(&vmx_l1d_should_flush);
301 static_branch_disable(&vmx_l1d_should_flush);
303 if (l1tf == VMENTER_L1D_FLUSH_COND)
304 static_branch_enable(&vmx_l1d_flush_cond);
306 static_branch_disable(&vmx_l1d_flush_cond);
310 static int vmentry_l1d_flush_parse(const char *s)
315 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
316 if (vmentry_l1d_param[i].for_parse &&
317 sysfs_streq(s, vmentry_l1d_param[i].option))
324 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
328 l1tf = vmentry_l1d_flush_parse(s);
332 if (!boot_cpu_has(X86_BUG_L1TF))
336 * Has vmx_init() run already? If not then this is the pre init
337 * parameter parsing. In that case just store the value and let
338 * vmx_init() do the proper setup after enable_ept has been
341 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
342 vmentry_l1d_flush_param = l1tf;
346 mutex_lock(&vmx_l1d_flush_mutex);
347 ret = vmx_setup_l1d_flush(l1tf);
348 mutex_unlock(&vmx_l1d_flush_mutex);
352 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
354 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
355 return sprintf(s, "???\n");
357 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
360 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
361 .set = vmentry_l1d_flush_set,
362 .get = vmentry_l1d_flush_get,
364 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
366 static u32 vmx_segment_access_rights(struct kvm_segment *var);
368 void vmx_vmexit(void);
370 #define vmx_insn_failed(fmt...) \
373 pr_warn_ratelimited(fmt); \
376 asmlinkage void vmread_error(unsigned long field, bool fault)
379 kvm_spurious_fault();
381 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
384 noinline void vmwrite_error(unsigned long field, unsigned long value)
386 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
387 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
390 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
392 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
395 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
397 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
400 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
402 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
406 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
408 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
412 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
413 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
415 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
416 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
418 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
420 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
421 static DEFINE_SPINLOCK(vmx_vpid_lock);
423 struct vmcs_config vmcs_config;
424 struct vmx_capability vmx_capability;
426 #define VMX_SEGMENT_FIELD(seg) \
427 [VCPU_SREG_##seg] = { \
428 .selector = GUEST_##seg##_SELECTOR, \
429 .base = GUEST_##seg##_BASE, \
430 .limit = GUEST_##seg##_LIMIT, \
431 .ar_bytes = GUEST_##seg##_AR_BYTES, \
434 static const struct kvm_vmx_segment_field {
439 } kvm_vmx_segment_fields[] = {
440 VMX_SEGMENT_FIELD(CS),
441 VMX_SEGMENT_FIELD(DS),
442 VMX_SEGMENT_FIELD(ES),
443 VMX_SEGMENT_FIELD(FS),
444 VMX_SEGMENT_FIELD(GS),
445 VMX_SEGMENT_FIELD(SS),
446 VMX_SEGMENT_FIELD(TR),
447 VMX_SEGMENT_FIELD(LDTR),
450 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
452 vmx->segment_cache.bitmask = 0;
455 static unsigned long host_idt_base;
457 #if IS_ENABLED(CONFIG_HYPERV)
458 static bool __read_mostly enlightened_vmcs = true;
459 module_param(enlightened_vmcs, bool, 0444);
461 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
463 struct hv_enlightened_vmcs *evmcs;
464 struct hv_partition_assist_pg **p_hv_pa_pg =
465 &to_kvm_hv(vcpu->kvm)->hv_pa_pg;
467 * Synthetic VM-Exit is not enabled in current code and so All
468 * evmcs in singe VM shares same assist page.
471 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
476 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
478 evmcs->partition_assist_page =
480 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
481 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
486 #endif /* IS_ENABLED(CONFIG_HYPERV) */
489 * Comment's format: document - errata name - stepping - processor name.
491 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
493 static u32 vmx_preemption_cpu_tfms[] = {
494 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
496 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
497 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
498 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
500 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
502 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
503 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
505 * 320767.pdf - AAP86 - B1 -
506 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
509 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
511 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
513 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
515 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
516 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
517 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
519 /* Xeon E3-1220 V2 */
523 static inline bool cpu_has_broken_vmx_preemption_timer(void)
525 u32 eax = cpuid_eax(0x00000001), i;
527 /* Clear the reserved bits */
528 eax &= ~(0x3U << 14 | 0xfU << 28);
529 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
530 if (eax == vmx_preemption_cpu_tfms[i])
536 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
538 return flexpriority_enabled && lapic_in_kernel(vcpu);
541 static inline bool report_flexpriority(void)
543 return flexpriority_enabled;
546 static int possible_passthrough_msr_slot(u32 msr)
550 for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++)
551 if (vmx_possible_passthrough_msrs[i] == msr)
557 static bool is_valid_passthrough_msr(u32 msr)
562 case 0x800 ... 0x8ff:
563 /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */
565 case MSR_IA32_RTIT_STATUS:
566 case MSR_IA32_RTIT_OUTPUT_BASE:
567 case MSR_IA32_RTIT_OUTPUT_MASK:
568 case MSR_IA32_RTIT_CR3_MATCH:
569 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
570 /* PT MSRs. These are handled in pt_update_intercept_for_msr() */
573 case MSR_LBR_INFO_0 ... MSR_LBR_INFO_0 + 31:
574 case MSR_LBR_NHM_FROM ... MSR_LBR_NHM_FROM + 31:
575 case MSR_LBR_NHM_TO ... MSR_LBR_NHM_TO + 31:
576 case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8:
577 case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8:
578 /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */
582 r = possible_passthrough_msr_slot(msr) != -ENOENT;
584 WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr);
589 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
593 i = kvm_find_user_return_msr(msr);
595 return &vmx->guest_uret_msrs[i];
599 static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx,
600 struct vmx_uret_msr *msr, u64 data)
602 unsigned int slot = msr - vmx->guest_uret_msrs;
605 u64 old_msr_data = msr->data;
607 if (msr->load_into_hardware) {
609 ret = kvm_set_user_return_msr(slot, msr->data, msr->mask);
612 msr->data = old_msr_data;
617 #ifdef CONFIG_KEXEC_CORE
618 static void crash_vmclear_local_loaded_vmcss(void)
620 int cpu = raw_smp_processor_id();
621 struct loaded_vmcs *v;
623 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
624 loaded_vmcss_on_cpu_link)
627 #endif /* CONFIG_KEXEC_CORE */
629 static void __loaded_vmcs_clear(void *arg)
631 struct loaded_vmcs *loaded_vmcs = arg;
632 int cpu = raw_smp_processor_id();
634 if (loaded_vmcs->cpu != cpu)
635 return; /* vcpu migration can race with cpu offline */
636 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
637 per_cpu(current_vmcs, cpu) = NULL;
639 vmcs_clear(loaded_vmcs->vmcs);
640 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
641 vmcs_clear(loaded_vmcs->shadow_vmcs);
643 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
646 * Ensure all writes to loaded_vmcs, including deleting it from its
647 * current percpu list, complete before setting loaded_vmcs->vcpu to
648 * -1, otherwise a different cpu can see vcpu == -1 first and add
649 * loaded_vmcs to its percpu list before it's deleted from this cpu's
650 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
654 loaded_vmcs->cpu = -1;
655 loaded_vmcs->launched = 0;
658 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
660 int cpu = loaded_vmcs->cpu;
663 smp_call_function_single(cpu,
664 __loaded_vmcs_clear, loaded_vmcs, 1);
667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
671 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
673 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
674 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
675 vmx->segment_cache.bitmask = 0;
677 ret = vmx->segment_cache.bitmask & mask;
678 vmx->segment_cache.bitmask |= mask;
682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
684 u16 *p = &vmx->segment_cache.seg[seg].selector;
686 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
687 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
693 ulong *p = &vmx->segment_cache.seg[seg].base;
695 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
696 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
702 u32 *p = &vmx->segment_cache.seg[seg].limit;
704 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
705 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
711 u32 *p = &vmx->segment_cache.seg[seg].ar;
713 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
714 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
718 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu)
722 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
723 (1u << DB_VECTOR) | (1u << AC_VECTOR);
725 * Guest access to VMware backdoor ports could legitimately
726 * trigger #GP because of TSS I/O permission bitmap.
727 * We intercept those #GP and allow access to them anyway
730 if (enable_vmware_backdoor)
731 eb |= (1u << GP_VECTOR);
732 if ((vcpu->guest_debug &
733 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
734 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
735 eb |= 1u << BP_VECTOR;
736 if (to_vmx(vcpu)->rmode.vm86_active)
738 if (!vmx_need_pf_intercept(vcpu))
739 eb &= ~(1u << PF_VECTOR);
741 /* When we are running a nested L2 guest and L1 specified for it a
742 * certain exception bitmap, we must trap the same exceptions and pass
743 * them to L1. When running L2, we will only handle the exceptions
744 * specified above if L1 did not want them.
746 if (is_guest_mode(vcpu))
747 eb |= get_vmcs12(vcpu)->exception_bitmap;
749 int mask = 0, match = 0;
751 if (enable_ept && (eb & (1u << PF_VECTOR))) {
753 * If EPT is enabled, #PF is currently only intercepted
754 * if MAXPHYADDR is smaller on the guest than on the
755 * host. In that case we only care about present,
756 * non-reserved faults. For vmcs02, however, PFEC_MASK
757 * and PFEC_MATCH are set in prepare_vmcs02_rare.
759 mask = PFERR_PRESENT_MASK | PFERR_RSVD_MASK;
760 match = PFERR_PRESENT_MASK;
762 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
763 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, match);
766 vmcs_write32(EXCEPTION_BITMAP, eb);
770 * Check if MSR is intercepted for currently loaded MSR bitmap.
772 static bool msr_write_intercepted(struct vcpu_vmx *vmx, u32 msr)
774 if (!(exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS))
777 return vmx_test_msr_bitmap_write(vmx->loaded_vmcs->msr_bitmap,
781 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
782 unsigned long entry, unsigned long exit)
784 vm_entry_controls_clearbit(vmx, entry);
785 vm_exit_controls_clearbit(vmx, exit);
788 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr)
792 for (i = 0; i < m->nr; ++i) {
793 if (m->val[i].index == msr)
799 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
802 struct msr_autoload *m = &vmx->msr_autoload;
806 if (cpu_has_load_ia32_efer()) {
807 clear_atomic_switch_msr_special(vmx,
808 VM_ENTRY_LOAD_IA32_EFER,
809 VM_EXIT_LOAD_IA32_EFER);
813 case MSR_CORE_PERF_GLOBAL_CTRL:
814 if (cpu_has_load_perf_global_ctrl()) {
815 clear_atomic_switch_msr_special(vmx,
816 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
817 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
822 i = vmx_find_loadstore_msr_slot(&m->guest, msr);
826 m->guest.val[i] = m->guest.val[m->guest.nr];
827 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
830 i = vmx_find_loadstore_msr_slot(&m->host, msr);
835 m->host.val[i] = m->host.val[m->host.nr];
836 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
839 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
840 unsigned long entry, unsigned long exit,
841 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
842 u64 guest_val, u64 host_val)
844 vmcs_write64(guest_val_vmcs, guest_val);
845 if (host_val_vmcs != HOST_IA32_EFER)
846 vmcs_write64(host_val_vmcs, host_val);
847 vm_entry_controls_setbit(vmx, entry);
848 vm_exit_controls_setbit(vmx, exit);
851 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
852 u64 guest_val, u64 host_val, bool entry_only)
855 struct msr_autoload *m = &vmx->msr_autoload;
859 if (cpu_has_load_ia32_efer()) {
860 add_atomic_switch_msr_special(vmx,
861 VM_ENTRY_LOAD_IA32_EFER,
862 VM_EXIT_LOAD_IA32_EFER,
865 guest_val, host_val);
869 case MSR_CORE_PERF_GLOBAL_CTRL:
870 if (cpu_has_load_perf_global_ctrl()) {
871 add_atomic_switch_msr_special(vmx,
872 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
873 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
874 GUEST_IA32_PERF_GLOBAL_CTRL,
875 HOST_IA32_PERF_GLOBAL_CTRL,
876 guest_val, host_val);
880 case MSR_IA32_PEBS_ENABLE:
881 /* PEBS needs a quiescent period after being disabled (to write
882 * a record). Disabling PEBS through VMX MSR swapping doesn't
883 * provide that period, so a CPU could write host's record into
886 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
889 i = vmx_find_loadstore_msr_slot(&m->guest, msr);
891 j = vmx_find_loadstore_msr_slot(&m->host, msr);
893 if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) ||
894 (j < 0 && m->host.nr == MAX_NR_LOADSTORE_MSRS)) {
895 printk_once(KERN_WARNING "Not enough msr switch entries. "
896 "Can't add msr %x\n", msr);
901 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
903 m->guest.val[i].index = msr;
904 m->guest.val[i].value = guest_val;
911 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
913 m->host.val[j].index = msr;
914 m->host.val[j].value = host_val;
917 static bool update_transition_efer(struct vcpu_vmx *vmx)
919 u64 guest_efer = vmx->vcpu.arch.efer;
923 /* Shadow paging assumes NX to be available. */
925 guest_efer |= EFER_NX;
928 * LMA and LME handled by hardware; SCE meaningless outside long mode.
930 ignore_bits |= EFER_SCE;
932 ignore_bits |= EFER_LMA | EFER_LME;
933 /* SCE is meaningful only in long mode on Intel */
934 if (guest_efer & EFER_LMA)
935 ignore_bits &= ~(u64)EFER_SCE;
939 * On EPT, we can't emulate NX, so we must switch EFER atomically.
940 * On CPUs that support "load IA32_EFER", always switch EFER
941 * atomically, since it's faster than switching it manually.
943 if (cpu_has_load_ia32_efer() ||
944 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
945 if (!(guest_efer & EFER_LMA))
946 guest_efer &= ~EFER_LME;
947 if (guest_efer != host_efer)
948 add_atomic_switch_msr(vmx, MSR_EFER,
949 guest_efer, host_efer, false);
951 clear_atomic_switch_msr(vmx, MSR_EFER);
955 i = kvm_find_user_return_msr(MSR_EFER);
959 clear_atomic_switch_msr(vmx, MSR_EFER);
961 guest_efer &= ~ignore_bits;
962 guest_efer |= host_efer & ignore_bits;
964 vmx->guest_uret_msrs[i].data = guest_efer;
965 vmx->guest_uret_msrs[i].mask = ~ignore_bits;
972 * On 32-bit kernels, VM exits still load the FS and GS bases from the
973 * VMCS rather than the segment table. KVM uses this helper to figure
974 * out the current bases to poke them into the VMCS before entry.
976 static unsigned long segment_base(u16 selector)
978 struct desc_struct *table;
981 if (!(selector & ~SEGMENT_RPL_MASK))
984 table = get_current_gdt_ro();
986 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
987 u16 ldt_selector = kvm_read_ldt();
989 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
992 table = (struct desc_struct *)segment_base(ldt_selector);
994 v = get_desc_base(&table[selector >> 3]);
999 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1001 return vmx_pt_mode_is_host_guest() &&
1002 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1005 static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base)
1007 /* The base must be 128-byte aligned and a legal physical address. */
1008 return kvm_vcpu_is_legal_aligned_gpa(vcpu, base, 128);
1011 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1015 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1016 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1017 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1018 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1019 for (i = 0; i < addr_range; i++) {
1020 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1021 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1025 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1029 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1030 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1031 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1032 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1033 for (i = 0; i < addr_range; i++) {
1034 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1035 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1039 static void pt_guest_enter(struct vcpu_vmx *vmx)
1041 if (vmx_pt_mode_is_system())
1045 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1046 * Save host state before VM entry.
1048 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1049 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1050 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1051 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1052 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1056 static void pt_guest_exit(struct vcpu_vmx *vmx)
1058 if (vmx_pt_mode_is_system())
1061 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1062 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1063 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1067 * KVM requires VM_EXIT_CLEAR_IA32_RTIT_CTL to expose PT to the guest,
1068 * i.e. RTIT_CTL is always cleared on VM-Exit. Restore it if necessary.
1070 if (vmx->pt_desc.host.ctl)
1071 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1074 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1075 unsigned long fs_base, unsigned long gs_base)
1077 if (unlikely(fs_sel != host->fs_sel)) {
1079 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1081 vmcs_write16(HOST_FS_SELECTOR, 0);
1082 host->fs_sel = fs_sel;
1084 if (unlikely(gs_sel != host->gs_sel)) {
1086 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1088 vmcs_write16(HOST_GS_SELECTOR, 0);
1089 host->gs_sel = gs_sel;
1091 if (unlikely(fs_base != host->fs_base)) {
1092 vmcs_writel(HOST_FS_BASE, fs_base);
1093 host->fs_base = fs_base;
1095 if (unlikely(gs_base != host->gs_base)) {
1096 vmcs_writel(HOST_GS_BASE, gs_base);
1097 host->gs_base = gs_base;
1101 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1103 struct vcpu_vmx *vmx = to_vmx(vcpu);
1104 struct vmcs_host_state *host_state;
1105 #ifdef CONFIG_X86_64
1106 int cpu = raw_smp_processor_id();
1108 unsigned long fs_base, gs_base;
1112 vmx->req_immediate_exit = false;
1115 * Note that guest MSRs to be saved/restored can also be changed
1116 * when guest state is loaded. This happens when guest transitions
1117 * to/from long-mode by setting MSR_EFER.LMA.
1119 if (!vmx->guest_uret_msrs_loaded) {
1120 vmx->guest_uret_msrs_loaded = true;
1121 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
1122 if (!vmx->guest_uret_msrs[i].load_into_hardware)
1125 kvm_set_user_return_msr(i,
1126 vmx->guest_uret_msrs[i].data,
1127 vmx->guest_uret_msrs[i].mask);
1131 if (vmx->nested.need_vmcs12_to_shadow_sync)
1132 nested_sync_vmcs12_to_shadow(vcpu);
1134 if (vmx->guest_state_loaded)
1137 host_state = &vmx->loaded_vmcs->host_state;
1140 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1141 * allow segment selectors with cpl > 0 or ti == 1.
1143 host_state->ldt_sel = kvm_read_ldt();
1145 #ifdef CONFIG_X86_64
1146 savesegment(ds, host_state->ds_sel);
1147 savesegment(es, host_state->es_sel);
1149 gs_base = cpu_kernelmode_gs_base(cpu);
1150 if (likely(is_64bit_mm(current->mm))) {
1151 current_save_fsgs();
1152 fs_sel = current->thread.fsindex;
1153 gs_sel = current->thread.gsindex;
1154 fs_base = current->thread.fsbase;
1155 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1157 savesegment(fs, fs_sel);
1158 savesegment(gs, gs_sel);
1159 fs_base = read_msr(MSR_FS_BASE);
1160 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1163 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1165 savesegment(fs, fs_sel);
1166 savesegment(gs, gs_sel);
1167 fs_base = segment_base(fs_sel);
1168 gs_base = segment_base(gs_sel);
1171 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1172 vmx->guest_state_loaded = true;
1175 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1177 struct vmcs_host_state *host_state;
1179 if (!vmx->guest_state_loaded)
1182 host_state = &vmx->loaded_vmcs->host_state;
1184 ++vmx->vcpu.stat.host_state_reload;
1186 #ifdef CONFIG_X86_64
1187 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1189 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1190 kvm_load_ldt(host_state->ldt_sel);
1191 #ifdef CONFIG_X86_64
1192 load_gs_index(host_state->gs_sel);
1194 loadsegment(gs, host_state->gs_sel);
1197 if (host_state->fs_sel & 7)
1198 loadsegment(fs, host_state->fs_sel);
1199 #ifdef CONFIG_X86_64
1200 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1201 loadsegment(ds, host_state->ds_sel);
1202 loadsegment(es, host_state->es_sel);
1205 invalidate_tss_limit();
1206 #ifdef CONFIG_X86_64
1207 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1209 load_fixmap_gdt(raw_smp_processor_id());
1210 vmx->guest_state_loaded = false;
1211 vmx->guest_uret_msrs_loaded = false;
1214 #ifdef CONFIG_X86_64
1215 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1218 if (vmx->guest_state_loaded)
1219 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1221 return vmx->msr_guest_kernel_gs_base;
1224 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1227 if (vmx->guest_state_loaded)
1228 wrmsrl(MSR_KERNEL_GS_BASE, data);
1230 vmx->msr_guest_kernel_gs_base = data;
1234 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1235 struct loaded_vmcs *buddy)
1237 struct vcpu_vmx *vmx = to_vmx(vcpu);
1238 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1241 if (!already_loaded) {
1242 loaded_vmcs_clear(vmx->loaded_vmcs);
1243 local_irq_disable();
1246 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1247 * this cpu's percpu list, otherwise it may not yet be deleted
1248 * from its previous cpu's percpu list. Pairs with the
1249 * smb_wmb() in __loaded_vmcs_clear().
1253 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1254 &per_cpu(loaded_vmcss_on_cpu, cpu));
1258 prev = per_cpu(current_vmcs, cpu);
1259 if (prev != vmx->loaded_vmcs->vmcs) {
1260 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1261 vmcs_load(vmx->loaded_vmcs->vmcs);
1264 * No indirect branch prediction barrier needed when switching
1265 * the active VMCS within a guest, e.g. on nested VM-Enter.
1266 * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1268 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1269 indirect_branch_prediction_barrier();
1272 if (!already_loaded) {
1273 void *gdt = get_current_gdt_ro();
1274 unsigned long sysenter_esp;
1277 * Flush all EPTP/VPID contexts, the new pCPU may have stale
1278 * TLB entries from its previous association with the vCPU.
1280 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1283 * Linux uses per-cpu TSS and GDT, so set these when switching
1284 * processors. See 22.2.4.
1286 vmcs_writel(HOST_TR_BASE,
1287 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1288 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1290 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1291 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1293 vmx->loaded_vmcs->cpu = cpu;
1298 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1299 * vcpu mutex is already taken.
1301 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1303 struct vcpu_vmx *vmx = to_vmx(vcpu);
1305 vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1307 vmx_vcpu_pi_load(vcpu, cpu);
1309 vmx->host_debugctlmsr = get_debugctlmsr();
1312 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1314 vmx_vcpu_pi_put(vcpu);
1316 vmx_prepare_switch_to_host(to_vmx(vcpu));
1319 bool vmx_emulation_required(struct kvm_vcpu *vcpu)
1321 return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu);
1324 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1326 struct vcpu_vmx *vmx = to_vmx(vcpu);
1327 unsigned long rflags, save_rflags;
1329 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1330 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1331 rflags = vmcs_readl(GUEST_RFLAGS);
1332 if (vmx->rmode.vm86_active) {
1333 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1334 save_rflags = vmx->rmode.save_rflags;
1335 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1337 vmx->rflags = rflags;
1342 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1344 struct vcpu_vmx *vmx = to_vmx(vcpu);
1345 unsigned long old_rflags;
1347 if (is_unrestricted_guest(vcpu)) {
1348 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1349 vmx->rflags = rflags;
1350 vmcs_writel(GUEST_RFLAGS, rflags);
1354 old_rflags = vmx_get_rflags(vcpu);
1355 vmx->rflags = rflags;
1356 if (vmx->rmode.vm86_active) {
1357 vmx->rmode.save_rflags = rflags;
1358 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1360 vmcs_writel(GUEST_RFLAGS, rflags);
1362 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1363 vmx->emulation_required = vmx_emulation_required(vcpu);
1366 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1368 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1371 if (interruptibility & GUEST_INTR_STATE_STI)
1372 ret |= KVM_X86_SHADOW_INT_STI;
1373 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1374 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1379 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1381 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1382 u32 interruptibility = interruptibility_old;
1384 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1386 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1387 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1388 else if (mask & KVM_X86_SHADOW_INT_STI)
1389 interruptibility |= GUEST_INTR_STATE_STI;
1391 if ((interruptibility != interruptibility_old))
1392 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1395 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1397 struct vcpu_vmx *vmx = to_vmx(vcpu);
1398 unsigned long value;
1401 * Any MSR write that attempts to change bits marked reserved will
1404 if (data & vmx->pt_desc.ctl_bitmask)
1408 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1409 * result in a #GP unless the same write also clears TraceEn.
1411 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1412 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1416 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1417 * and FabricEn would cause #GP, if
1418 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1420 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1421 !(data & RTIT_CTL_FABRIC_EN) &&
1422 !intel_pt_validate_cap(vmx->pt_desc.caps,
1423 PT_CAP_single_range_output))
1427 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1428 * utilize encodings marked reserved will cause a #GP fault.
1430 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1431 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1432 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1433 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1435 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1436 PT_CAP_cycle_thresholds);
1437 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1438 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1439 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1441 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1442 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1443 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1444 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1448 * If ADDRx_CFG is reserved or the encodings is >2 will
1449 * cause a #GP fault.
1451 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1452 if ((value && (vmx->pt_desc.num_address_ranges < 1)) || (value > 2))
1454 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1455 if ((value && (vmx->pt_desc.num_address_ranges < 2)) || (value > 2))
1457 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1458 if ((value && (vmx->pt_desc.num_address_ranges < 3)) || (value > 2))
1460 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1461 if ((value && (vmx->pt_desc.num_address_ranges < 4)) || (value > 2))
1467 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
1470 * Emulation of instructions in SGX enclaves is impossible as RIP does
1471 * not point tthe failing instruction, and even if it did, the code
1472 * stream is inaccessible. Inject #UD instead of exiting to userspace
1473 * so that guest userspace can't DoS the guest simply by triggering
1474 * emulation (enclaves are CPL3 only).
1476 if (to_vmx(vcpu)->exit_reason.enclave_mode) {
1477 kvm_queue_exception(vcpu, UD_VECTOR);
1483 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1485 union vmx_exit_reason exit_reason = to_vmx(vcpu)->exit_reason;
1486 unsigned long rip, orig_rip;
1490 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1491 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1492 * set when EPT misconfig occurs. In practice, real hardware updates
1493 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1494 * (namely Hyper-V) don't set it due to it being undefined behavior,
1495 * i.e. we end up advancing IP with some random value.
1497 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1498 exit_reason.basic != EXIT_REASON_EPT_MISCONFIG) {
1499 instr_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1502 * Emulating an enclave's instructions isn't supported as KVM
1503 * cannot access the enclave's memory or its true RIP, e.g. the
1504 * vmcs.GUEST_RIP points at the exit point of the enclave, not
1505 * the RIP that actually triggered the VM-Exit. But, because
1506 * most instructions that cause VM-Exit will #UD in an enclave,
1507 * most instruction-based VM-Exits simply do not occur.
1509 * There are a few exceptions, notably the debug instructions
1510 * INT1ICEBRK and INT3, as they are allowed in debug enclaves
1511 * and generate #DB/#BP as expected, which KVM might intercept.
1512 * But again, the CPU does the dirty work and saves an instr
1513 * length of zero so VMMs don't shoot themselves in the foot.
1514 * WARN if KVM tries to skip a non-zero length instruction on
1515 * a VM-Exit from an enclave.
1520 WARN(exit_reason.enclave_mode,
1521 "KVM: skipping instruction after SGX enclave VM-Exit");
1523 orig_rip = kvm_rip_read(vcpu);
1524 rip = orig_rip + instr_len;
1525 #ifdef CONFIG_X86_64
1527 * We need to mask out the high 32 bits of RIP if not in 64-bit
1528 * mode, but just finding out that we are in 64-bit mode is
1529 * quite expensive. Only do it if there was a carry.
1531 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1534 kvm_rip_write(vcpu, rip);
1536 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1541 /* skipping an emulated instruction also counts */
1542 vmx_set_interrupt_shadow(vcpu, 0);
1548 * Recognizes a pending MTF VM-exit and records the nested state for later
1551 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1553 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1554 struct vcpu_vmx *vmx = to_vmx(vcpu);
1556 if (!is_guest_mode(vcpu))
1560 * Per the SDM, MTF takes priority over debug-trap exceptions besides
1561 * T-bit traps. As instruction emulation is completed (i.e. at the
1562 * instruction boundary), any #DB exception pending delivery must be a
1563 * debug-trap. Record the pending MTF state to be delivered in
1564 * vmx_check_nested_events().
1566 if (nested_cpu_has_mtf(vmcs12) &&
1567 (!vcpu->arch.exception.pending ||
1568 vcpu->arch.exception.nr == DB_VECTOR))
1569 vmx->nested.mtf_pending = true;
1571 vmx->nested.mtf_pending = false;
1574 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1576 vmx_update_emulated_instruction(vcpu);
1577 return skip_emulated_instruction(vcpu);
1580 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1583 * Ensure that we clear the HLT state in the VMCS. We don't need to
1584 * explicitly skip the instruction because if the HLT state is set,
1585 * then the instruction is already executing and RIP has already been
1588 if (kvm_hlt_in_guest(vcpu->kvm) &&
1589 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1590 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1593 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1595 struct vcpu_vmx *vmx = to_vmx(vcpu);
1596 unsigned nr = vcpu->arch.exception.nr;
1597 bool has_error_code = vcpu->arch.exception.has_error_code;
1598 u32 error_code = vcpu->arch.exception.error_code;
1599 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1601 kvm_deliver_exception_payload(vcpu);
1603 if (has_error_code) {
1604 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1605 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1608 if (vmx->rmode.vm86_active) {
1610 if (kvm_exception_is_soft(nr))
1611 inc_eip = vcpu->arch.event_exit_inst_len;
1612 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1616 WARN_ON_ONCE(vmx->emulation_required);
1618 if (kvm_exception_is_soft(nr)) {
1619 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1620 vmx->vcpu.arch.event_exit_inst_len);
1621 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1623 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1625 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1627 vmx_clear_hlt(vcpu);
1630 static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr,
1631 bool load_into_hardware)
1633 struct vmx_uret_msr *uret_msr;
1635 uret_msr = vmx_find_uret_msr(vmx, msr);
1639 uret_msr->load_into_hardware = load_into_hardware;
1643 * Configuring user return MSRs to automatically save, load, and restore MSRs
1644 * that need to be shoved into hardware when running the guest. Note, omitting
1645 * an MSR here does _NOT_ mean it's not emulated, only that it will not be
1646 * loaded into hardware when running the guest.
1648 static void vmx_setup_uret_msrs(struct vcpu_vmx *vmx)
1650 #ifdef CONFIG_X86_64
1651 bool load_syscall_msrs;
1654 * The SYSCALL MSRs are only needed on long mode guests, and only
1655 * when EFER.SCE is set.
1657 load_syscall_msrs = is_long_mode(&vmx->vcpu) &&
1658 (vmx->vcpu.arch.efer & EFER_SCE);
1660 vmx_setup_uret_msr(vmx, MSR_STAR, load_syscall_msrs);
1661 vmx_setup_uret_msr(vmx, MSR_LSTAR, load_syscall_msrs);
1662 vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK, load_syscall_msrs);
1664 vmx_setup_uret_msr(vmx, MSR_EFER, update_transition_efer(vmx));
1666 vmx_setup_uret_msr(vmx, MSR_TSC_AUX,
1667 guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP) ||
1668 guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDPID));
1671 * hle=0, rtm=0, tsx_ctrl=1 can be found with some combinations of new
1672 * kernel and old userspace. If those guests run on a tsx=off host, do
1673 * allow guests to use TSX_CTRL, but don't change the value in hardware
1674 * so that TSX remains always disabled.
1676 vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL, boot_cpu_has(X86_FEATURE_RTM));
1679 * The set of MSRs to load may have changed, reload MSRs before the
1682 vmx->guest_uret_msrs_loaded = false;
1685 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1687 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1689 if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING))
1690 return vmcs12->tsc_offset;
1695 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1697 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1699 if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING) &&
1700 nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
1701 return vmcs12->tsc_multiplier;
1703 return kvm_default_tsc_scaling_ratio;
1706 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1708 vmcs_write64(TSC_OFFSET, offset);
1711 static void vmx_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1713 vmcs_write64(TSC_MULTIPLIER, multiplier);
1717 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1718 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1719 * all guests if the "nested" module option is off, and can also be disabled
1720 * for a single guest by disabling its VMX cpuid bit.
1722 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1724 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1727 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1730 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1732 return !(val & ~valid_bits);
1735 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1737 switch (msr->index) {
1738 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1741 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1742 case MSR_IA32_PERF_CAPABILITIES:
1743 msr->data = vmx_get_perf_capabilities();
1746 return KVM_MSR_RET_INVALID;
1751 * Reads an msr value (of 'msr_index') into 'pdata'.
1752 * Returns 0 on success, non-0 otherwise.
1753 * Assumes vcpu_load() was already called.
1755 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1757 struct vcpu_vmx *vmx = to_vmx(vcpu);
1758 struct vmx_uret_msr *msr;
1761 switch (msr_info->index) {
1762 #ifdef CONFIG_X86_64
1764 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1767 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1769 case MSR_KERNEL_GS_BASE:
1770 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1774 return kvm_get_msr_common(vcpu, msr_info);
1775 case MSR_IA32_TSX_CTRL:
1776 if (!msr_info->host_initiated &&
1777 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1780 case MSR_IA32_UMWAIT_CONTROL:
1781 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1784 msr_info->data = vmx->msr_ia32_umwait_control;
1786 case MSR_IA32_SPEC_CTRL:
1787 if (!msr_info->host_initiated &&
1788 !guest_has_spec_ctrl_msr(vcpu))
1791 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1793 case MSR_IA32_SYSENTER_CS:
1794 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1796 case MSR_IA32_SYSENTER_EIP:
1797 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1799 case MSR_IA32_SYSENTER_ESP:
1800 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1802 case MSR_IA32_BNDCFGS:
1803 if (!kvm_mpx_supported() ||
1804 (!msr_info->host_initiated &&
1805 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1807 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1809 case MSR_IA32_MCG_EXT_CTL:
1810 if (!msr_info->host_initiated &&
1811 !(vmx->msr_ia32_feature_control &
1812 FEAT_CTL_LMCE_ENABLED))
1814 msr_info->data = vcpu->arch.mcg_ext_ctl;
1816 case MSR_IA32_FEAT_CTL:
1817 msr_info->data = vmx->msr_ia32_feature_control;
1819 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
1820 if (!msr_info->host_initiated &&
1821 !guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
1823 msr_info->data = to_vmx(vcpu)->msr_ia32_sgxlepubkeyhash
1824 [msr_info->index - MSR_IA32_SGXLEPUBKEYHASH0];
1826 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1827 if (!nested_vmx_allowed(vcpu))
1829 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1833 * Enlightened VMCS v1 doesn't have certain VMCS fields but
1834 * instead of just ignoring the features, different Hyper-V
1835 * versions are either trying to use them and fail or do some
1836 * sanity checking and refuse to boot. Filter all unsupported
1839 if (!msr_info->host_initiated &&
1840 vmx->nested.enlightened_vmcs_enabled)
1841 nested_evmcs_filter_control_msr(msr_info->index,
1844 case MSR_IA32_RTIT_CTL:
1845 if (!vmx_pt_mode_is_host_guest())
1847 msr_info->data = vmx->pt_desc.guest.ctl;
1849 case MSR_IA32_RTIT_STATUS:
1850 if (!vmx_pt_mode_is_host_guest())
1852 msr_info->data = vmx->pt_desc.guest.status;
1854 case MSR_IA32_RTIT_CR3_MATCH:
1855 if (!vmx_pt_mode_is_host_guest() ||
1856 !intel_pt_validate_cap(vmx->pt_desc.caps,
1857 PT_CAP_cr3_filtering))
1859 msr_info->data = vmx->pt_desc.guest.cr3_match;
1861 case MSR_IA32_RTIT_OUTPUT_BASE:
1862 if (!vmx_pt_mode_is_host_guest() ||
1863 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1864 PT_CAP_topa_output) &&
1865 !intel_pt_validate_cap(vmx->pt_desc.caps,
1866 PT_CAP_single_range_output)))
1868 msr_info->data = vmx->pt_desc.guest.output_base;
1870 case MSR_IA32_RTIT_OUTPUT_MASK:
1871 if (!vmx_pt_mode_is_host_guest() ||
1872 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1873 PT_CAP_topa_output) &&
1874 !intel_pt_validate_cap(vmx->pt_desc.caps,
1875 PT_CAP_single_range_output)))
1877 msr_info->data = vmx->pt_desc.guest.output_mask;
1879 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1880 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1881 if (!vmx_pt_mode_is_host_guest() ||
1882 (index >= 2 * vmx->pt_desc.num_address_ranges))
1885 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1887 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1889 case MSR_IA32_DEBUGCTLMSR:
1890 msr_info->data = vmcs_read64(GUEST_IA32_DEBUGCTL);
1894 msr = vmx_find_uret_msr(vmx, msr_info->index);
1896 msr_info->data = msr->data;
1899 return kvm_get_msr_common(vcpu, msr_info);
1905 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1908 #ifdef CONFIG_X86_64
1909 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1912 return (unsigned long)data;
1915 static u64 vcpu_supported_debugctl(struct kvm_vcpu *vcpu)
1917 u64 debugctl = vmx_supported_debugctl();
1919 if (!intel_pmu_lbr_is_enabled(vcpu))
1920 debugctl &= ~DEBUGCTLMSR_LBR_MASK;
1922 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1923 debugctl &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1929 * Writes msr value into the appropriate "register".
1930 * Returns 0 on success, non-0 otherwise.
1931 * Assumes vcpu_load() was already called.
1933 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1935 struct vcpu_vmx *vmx = to_vmx(vcpu);
1936 struct vmx_uret_msr *msr;
1938 u32 msr_index = msr_info->index;
1939 u64 data = msr_info->data;
1942 switch (msr_index) {
1944 ret = kvm_set_msr_common(vcpu, msr_info);
1946 #ifdef CONFIG_X86_64
1948 vmx_segment_cache_clear(vmx);
1949 vmcs_writel(GUEST_FS_BASE, data);
1952 vmx_segment_cache_clear(vmx);
1953 vmcs_writel(GUEST_GS_BASE, data);
1955 case MSR_KERNEL_GS_BASE:
1956 vmx_write_guest_kernel_gs_base(vmx, data);
1959 case MSR_IA32_SYSENTER_CS:
1960 if (is_guest_mode(vcpu))
1961 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1962 vmcs_write32(GUEST_SYSENTER_CS, data);
1964 case MSR_IA32_SYSENTER_EIP:
1965 if (is_guest_mode(vcpu)) {
1966 data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1967 get_vmcs12(vcpu)->guest_sysenter_eip = data;
1969 vmcs_writel(GUEST_SYSENTER_EIP, data);
1971 case MSR_IA32_SYSENTER_ESP:
1972 if (is_guest_mode(vcpu)) {
1973 data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1974 get_vmcs12(vcpu)->guest_sysenter_esp = data;
1976 vmcs_writel(GUEST_SYSENTER_ESP, data);
1978 case MSR_IA32_DEBUGCTLMSR: {
1979 u64 invalid = data & ~vcpu_supported_debugctl(vcpu);
1980 if (invalid & (DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR)) {
1981 if (report_ignored_msrs)
1982 vcpu_unimpl(vcpu, "%s: BTF|LBR in IA32_DEBUGCTLMSR 0x%llx, nop\n",
1984 data &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1985 invalid &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1991 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1992 VM_EXIT_SAVE_DEBUG_CONTROLS)
1993 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1995 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
1996 if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event &&
1997 (data & DEBUGCTLMSR_LBR))
1998 intel_pmu_create_guest_lbr_event(vcpu);
2001 case MSR_IA32_BNDCFGS:
2002 if (!kvm_mpx_supported() ||
2003 (!msr_info->host_initiated &&
2004 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2006 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2007 (data & MSR_IA32_BNDCFGS_RSVD))
2009 vmcs_write64(GUEST_BNDCFGS, data);
2011 case MSR_IA32_UMWAIT_CONTROL:
2012 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2015 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2016 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2019 vmx->msr_ia32_umwait_control = data;
2021 case MSR_IA32_SPEC_CTRL:
2022 if (!msr_info->host_initiated &&
2023 !guest_has_spec_ctrl_msr(vcpu))
2026 if (kvm_spec_ctrl_test_value(data))
2029 vmx->spec_ctrl = data;
2035 * When it's written (to non-zero) for the first time, pass
2039 * The handling of the MSR bitmap for L2 guests is done in
2040 * nested_vmx_prepare_msr_bitmap. We should not touch the
2041 * vmcs02.msr_bitmap here since it gets completely overwritten
2042 * in the merging. We update the vmcs01 here for L1 as well
2043 * since it will end up touching the MSR anyway now.
2045 vmx_disable_intercept_for_msr(vcpu,
2049 case MSR_IA32_TSX_CTRL:
2050 if (!msr_info->host_initiated &&
2051 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2053 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2056 case MSR_IA32_PRED_CMD:
2057 if (!msr_info->host_initiated &&
2058 !guest_has_pred_cmd_msr(vcpu))
2061 if (data & ~PRED_CMD_IBPB)
2063 if (!boot_cpu_has(X86_FEATURE_IBPB))
2068 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2072 * When it's written (to non-zero) for the first time, pass
2076 * The handling of the MSR bitmap for L2 guests is done in
2077 * nested_vmx_prepare_msr_bitmap. We should not touch the
2078 * vmcs02.msr_bitmap here since it gets completely overwritten
2081 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
2083 case MSR_IA32_CR_PAT:
2084 if (!kvm_pat_valid(data))
2087 if (is_guest_mode(vcpu) &&
2088 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2089 get_vmcs12(vcpu)->guest_ia32_pat = data;
2091 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2092 vmcs_write64(GUEST_IA32_PAT, data);
2093 vcpu->arch.pat = data;
2096 ret = kvm_set_msr_common(vcpu, msr_info);
2098 case MSR_IA32_TSC_ADJUST:
2099 ret = kvm_set_msr_common(vcpu, msr_info);
2101 case MSR_IA32_MCG_EXT_CTL:
2102 if ((!msr_info->host_initiated &&
2103 !(to_vmx(vcpu)->msr_ia32_feature_control &
2104 FEAT_CTL_LMCE_ENABLED)) ||
2105 (data & ~MCG_EXT_CTL_LMCE_EN))
2107 vcpu->arch.mcg_ext_ctl = data;
2109 case MSR_IA32_FEAT_CTL:
2110 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2111 (to_vmx(vcpu)->msr_ia32_feature_control &
2112 FEAT_CTL_LOCKED && !msr_info->host_initiated))
2114 vmx->msr_ia32_feature_control = data;
2115 if (msr_info->host_initiated && data == 0)
2116 vmx_leave_nested(vcpu);
2118 /* SGX may be enabled/disabled by guest's firmware */
2119 vmx_write_encls_bitmap(vcpu, NULL);
2121 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
2123 * On real hardware, the LE hash MSRs are writable before
2124 * the firmware sets bit 0 in MSR 0x7a ("activating" SGX),
2125 * at which point SGX related bits in IA32_FEATURE_CONTROL
2128 * KVM does not emulate SGX activation for simplicity, so
2129 * allow writes to the LE hash MSRs if IA32_FEATURE_CONTROL
2130 * is unlocked. This is technically not architectural
2131 * behavior, but it's close enough.
2133 if (!msr_info->host_initiated &&
2134 (!guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC) ||
2135 ((vmx->msr_ia32_feature_control & FEAT_CTL_LOCKED) &&
2136 !(vmx->msr_ia32_feature_control & FEAT_CTL_SGX_LC_ENABLED))))
2138 vmx->msr_ia32_sgxlepubkeyhash
2139 [msr_index - MSR_IA32_SGXLEPUBKEYHASH0] = data;
2141 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2142 if (!msr_info->host_initiated)
2143 return 1; /* they are read-only */
2144 if (!nested_vmx_allowed(vcpu))
2146 return vmx_set_vmx_msr(vcpu, msr_index, data);
2147 case MSR_IA32_RTIT_CTL:
2148 if (!vmx_pt_mode_is_host_guest() ||
2149 vmx_rtit_ctl_check(vcpu, data) ||
2152 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2153 vmx->pt_desc.guest.ctl = data;
2154 pt_update_intercept_for_msr(vcpu);
2156 case MSR_IA32_RTIT_STATUS:
2157 if (!pt_can_write_msr(vmx))
2159 if (data & MSR_IA32_RTIT_STATUS_MASK)
2161 vmx->pt_desc.guest.status = data;
2163 case MSR_IA32_RTIT_CR3_MATCH:
2164 if (!pt_can_write_msr(vmx))
2166 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2167 PT_CAP_cr3_filtering))
2169 vmx->pt_desc.guest.cr3_match = data;
2171 case MSR_IA32_RTIT_OUTPUT_BASE:
2172 if (!pt_can_write_msr(vmx))
2174 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2175 PT_CAP_topa_output) &&
2176 !intel_pt_validate_cap(vmx->pt_desc.caps,
2177 PT_CAP_single_range_output))
2179 if (!pt_output_base_valid(vcpu, data))
2181 vmx->pt_desc.guest.output_base = data;
2183 case MSR_IA32_RTIT_OUTPUT_MASK:
2184 if (!pt_can_write_msr(vmx))
2186 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2187 PT_CAP_topa_output) &&
2188 !intel_pt_validate_cap(vmx->pt_desc.caps,
2189 PT_CAP_single_range_output))
2191 vmx->pt_desc.guest.output_mask = data;
2193 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2194 if (!pt_can_write_msr(vmx))
2196 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2197 if (index >= 2 * vmx->pt_desc.num_address_ranges)
2199 if (is_noncanonical_address(data, vcpu))
2202 vmx->pt_desc.guest.addr_b[index / 2] = data;
2204 vmx->pt_desc.guest.addr_a[index / 2] = data;
2206 case MSR_IA32_PERF_CAPABILITIES:
2207 if (data && !vcpu_to_pmu(vcpu)->version)
2209 if (data & PMU_CAP_LBR_FMT) {
2210 if ((data & PMU_CAP_LBR_FMT) !=
2211 (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
2213 if (!intel_pmu_lbr_is_compatible(vcpu))
2216 ret = kvm_set_msr_common(vcpu, msr_info);
2221 msr = vmx_find_uret_msr(vmx, msr_index);
2223 ret = vmx_set_guest_uret_msr(vmx, msr, data);
2225 ret = kvm_set_msr_common(vcpu, msr_info);
2231 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2233 unsigned long guest_owned_bits;
2235 kvm_register_mark_available(vcpu, reg);
2239 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2242 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2244 case VCPU_EXREG_PDPTR:
2246 ept_save_pdptrs(vcpu);
2248 case VCPU_EXREG_CR0:
2249 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2251 vcpu->arch.cr0 &= ~guest_owned_bits;
2252 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2254 case VCPU_EXREG_CR3:
2256 * When intercepting CR3 loads, e.g. for shadowing paging, KVM's
2257 * CR3 is loaded into hardware, not the guest's CR3.
2259 if (!(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_CR3_LOAD_EXITING))
2260 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2262 case VCPU_EXREG_CR4:
2263 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2265 vcpu->arch.cr4 &= ~guest_owned_bits;
2266 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2269 KVM_BUG_ON(1, vcpu->kvm);
2274 static __init int cpu_has_kvm_support(void)
2276 return cpu_has_vmx();
2279 static __init int vmx_disabled_by_bios(void)
2281 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2282 !boot_cpu_has(X86_FEATURE_VMX);
2285 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2289 cr4_set_bits(X86_CR4_VMXE);
2291 asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2292 _ASM_EXTABLE(1b, %l[fault])
2293 : : [vmxon_pointer] "m"(vmxon_pointer)
2298 WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2299 rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2300 cr4_clear_bits(X86_CR4_VMXE);
2305 static int hardware_enable(void)
2307 int cpu = raw_smp_processor_id();
2308 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2311 if (cr4_read_shadow() & X86_CR4_VMXE)
2315 * This can happen if we hot-added a CPU but failed to allocate
2316 * VP assist page for it.
2318 if (static_branch_unlikely(&enable_evmcs) &&
2319 !hv_get_vp_assist_page(cpu))
2322 intel_pt_handle_vmx(1);
2324 r = kvm_cpu_vmxon(phys_addr);
2326 intel_pt_handle_vmx(0);
2336 static void vmclear_local_loaded_vmcss(void)
2338 int cpu = raw_smp_processor_id();
2339 struct loaded_vmcs *v, *n;
2341 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2342 loaded_vmcss_on_cpu_link)
2343 __loaded_vmcs_clear(v);
2346 static void hardware_disable(void)
2348 vmclear_local_loaded_vmcss();
2351 kvm_spurious_fault();
2353 intel_pt_handle_vmx(0);
2357 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2358 * directly instead of going through cpu_has(), to ensure KVM is trapping
2359 * ENCLS whenever it's supported in hardware. It does not matter whether
2360 * the host OS supports or has enabled SGX.
2362 static bool cpu_has_sgx(void)
2364 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2367 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2368 u32 msr, u32 *result)
2370 u32 vmx_msr_low, vmx_msr_high;
2371 u32 ctl = ctl_min | ctl_opt;
2373 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2375 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2376 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2378 /* Ensure minimum (required) set of control bits are supported. */
2386 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2387 struct vmx_capability *vmx_cap)
2389 u32 vmx_msr_low, vmx_msr_high;
2390 u32 min, opt, min2, opt2;
2391 u32 _pin_based_exec_control = 0;
2392 u32 _cpu_based_exec_control = 0;
2393 u32 _cpu_based_2nd_exec_control = 0;
2394 u32 _vmexit_control = 0;
2395 u32 _vmentry_control = 0;
2397 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2398 min = CPU_BASED_HLT_EXITING |
2399 #ifdef CONFIG_X86_64
2400 CPU_BASED_CR8_LOAD_EXITING |
2401 CPU_BASED_CR8_STORE_EXITING |
2403 CPU_BASED_CR3_LOAD_EXITING |
2404 CPU_BASED_CR3_STORE_EXITING |
2405 CPU_BASED_UNCOND_IO_EXITING |
2406 CPU_BASED_MOV_DR_EXITING |
2407 CPU_BASED_USE_TSC_OFFSETTING |
2408 CPU_BASED_MWAIT_EXITING |
2409 CPU_BASED_MONITOR_EXITING |
2410 CPU_BASED_INVLPG_EXITING |
2411 CPU_BASED_RDPMC_EXITING;
2413 opt = CPU_BASED_TPR_SHADOW |
2414 CPU_BASED_USE_MSR_BITMAPS |
2415 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2416 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2417 &_cpu_based_exec_control) < 0)
2419 #ifdef CONFIG_X86_64
2420 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2421 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2422 ~CPU_BASED_CR8_STORE_EXITING;
2424 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2426 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2427 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2428 SECONDARY_EXEC_WBINVD_EXITING |
2429 SECONDARY_EXEC_ENABLE_VPID |
2430 SECONDARY_EXEC_ENABLE_EPT |
2431 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2432 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2433 SECONDARY_EXEC_DESC |
2434 SECONDARY_EXEC_ENABLE_RDTSCP |
2435 SECONDARY_EXEC_ENABLE_INVPCID |
2436 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2437 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2438 SECONDARY_EXEC_SHADOW_VMCS |
2439 SECONDARY_EXEC_XSAVES |
2440 SECONDARY_EXEC_RDSEED_EXITING |
2441 SECONDARY_EXEC_RDRAND_EXITING |
2442 SECONDARY_EXEC_ENABLE_PML |
2443 SECONDARY_EXEC_TSC_SCALING |
2444 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2445 SECONDARY_EXEC_PT_USE_GPA |
2446 SECONDARY_EXEC_PT_CONCEAL_VMX |
2447 SECONDARY_EXEC_ENABLE_VMFUNC |
2448 SECONDARY_EXEC_BUS_LOCK_DETECTION;
2450 opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2451 if (adjust_vmx_controls(min2, opt2,
2452 MSR_IA32_VMX_PROCBASED_CTLS2,
2453 &_cpu_based_2nd_exec_control) < 0)
2456 #ifndef CONFIG_X86_64
2457 if (!(_cpu_based_2nd_exec_control &
2458 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2459 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2462 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2463 _cpu_based_2nd_exec_control &= ~(
2464 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2465 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2466 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2468 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2469 &vmx_cap->ept, &vmx_cap->vpid);
2471 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2472 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2474 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2475 CPU_BASED_CR3_STORE_EXITING |
2476 CPU_BASED_INVLPG_EXITING);
2477 } else if (vmx_cap->ept) {
2479 pr_warn_once("EPT CAP should not exist if not support "
2480 "1-setting enable EPT VM-execution control\n");
2482 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2485 pr_warn_once("VPID CAP should not exist if not support "
2486 "1-setting enable VPID VM-execution control\n");
2489 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2490 #ifdef CONFIG_X86_64
2491 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2493 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2494 VM_EXIT_LOAD_IA32_PAT |
2495 VM_EXIT_LOAD_IA32_EFER |
2496 VM_EXIT_CLEAR_BNDCFGS |
2497 VM_EXIT_PT_CONCEAL_PIP |
2498 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2499 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2500 &_vmexit_control) < 0)
2503 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2504 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2505 PIN_BASED_VMX_PREEMPTION_TIMER;
2506 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2507 &_pin_based_exec_control) < 0)
2510 if (cpu_has_broken_vmx_preemption_timer())
2511 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2512 if (!(_cpu_based_2nd_exec_control &
2513 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2514 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2516 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2517 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2518 VM_ENTRY_LOAD_IA32_PAT |
2519 VM_ENTRY_LOAD_IA32_EFER |
2520 VM_ENTRY_LOAD_BNDCFGS |
2521 VM_ENTRY_PT_CONCEAL_PIP |
2522 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2523 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2524 &_vmentry_control) < 0)
2528 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2529 * can't be used due to an errata where VM Exit may incorrectly clear
2530 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2531 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2533 if (boot_cpu_data.x86 == 0x6) {
2534 switch (boot_cpu_data.x86_model) {
2535 case 26: /* AAK155 */
2536 case 30: /* AAP115 */
2537 case 37: /* AAT100 */
2538 case 44: /* BC86,AAY89,BD102 */
2540 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2541 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2542 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2543 "does not work properly. Using workaround\n");
2551 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2553 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2554 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2557 #ifdef CONFIG_X86_64
2558 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2559 if (vmx_msr_high & (1u<<16))
2563 /* Require Write-Back (WB) memory type for VMCS accesses. */
2564 if (((vmx_msr_high >> 18) & 15) != 6)
2567 vmcs_conf->size = vmx_msr_high & 0x1fff;
2568 vmcs_conf->order = get_order(vmcs_conf->size);
2569 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2571 vmcs_conf->revision_id = vmx_msr_low;
2573 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2574 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2575 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2576 vmcs_conf->vmexit_ctrl = _vmexit_control;
2577 vmcs_conf->vmentry_ctrl = _vmentry_control;
2579 #if IS_ENABLED(CONFIG_HYPERV)
2580 if (enlightened_vmcs)
2581 evmcs_sanitize_exec_ctrls(vmcs_conf);
2587 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2589 int node = cpu_to_node(cpu);
2593 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2596 vmcs = page_address(pages);
2597 memset(vmcs, 0, vmcs_config.size);
2599 /* KVM supports Enlightened VMCS v1 only */
2600 if (static_branch_unlikely(&enable_evmcs))
2601 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2603 vmcs->hdr.revision_id = vmcs_config.revision_id;
2606 vmcs->hdr.shadow_vmcs = 1;
2610 void free_vmcs(struct vmcs *vmcs)
2612 free_pages((unsigned long)vmcs, vmcs_config.order);
2616 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2618 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2620 if (!loaded_vmcs->vmcs)
2622 loaded_vmcs_clear(loaded_vmcs);
2623 free_vmcs(loaded_vmcs->vmcs);
2624 loaded_vmcs->vmcs = NULL;
2625 if (loaded_vmcs->msr_bitmap)
2626 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2627 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2630 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2632 loaded_vmcs->vmcs = alloc_vmcs(false);
2633 if (!loaded_vmcs->vmcs)
2636 vmcs_clear(loaded_vmcs->vmcs);
2638 loaded_vmcs->shadow_vmcs = NULL;
2639 loaded_vmcs->hv_timer_soft_disabled = false;
2640 loaded_vmcs->cpu = -1;
2641 loaded_vmcs->launched = 0;
2643 if (cpu_has_vmx_msr_bitmap()) {
2644 loaded_vmcs->msr_bitmap = (unsigned long *)
2645 __get_free_page(GFP_KERNEL_ACCOUNT);
2646 if (!loaded_vmcs->msr_bitmap)
2648 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2650 if (IS_ENABLED(CONFIG_HYPERV) &&
2651 static_branch_unlikely(&enable_evmcs) &&
2652 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2653 struct hv_enlightened_vmcs *evmcs =
2654 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2656 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2660 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2661 memset(&loaded_vmcs->controls_shadow, 0,
2662 sizeof(struct vmcs_controls_shadow));
2667 free_loaded_vmcs(loaded_vmcs);
2671 static void free_kvm_area(void)
2675 for_each_possible_cpu(cpu) {
2676 free_vmcs(per_cpu(vmxarea, cpu));
2677 per_cpu(vmxarea, cpu) = NULL;
2681 static __init int alloc_kvm_area(void)
2685 for_each_possible_cpu(cpu) {
2688 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2695 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2696 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2697 * revision_id reported by MSR_IA32_VMX_BASIC.
2699 * However, even though not explicitly documented by
2700 * TLFS, VMXArea passed as VMXON argument should
2701 * still be marked with revision_id reported by
2704 if (static_branch_unlikely(&enable_evmcs))
2705 vmcs->hdr.revision_id = vmcs_config.revision_id;
2707 per_cpu(vmxarea, cpu) = vmcs;
2712 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2713 struct kvm_segment *save)
2715 if (!emulate_invalid_guest_state) {
2717 * CS and SS RPL should be equal during guest entry according
2718 * to VMX spec, but in reality it is not always so. Since vcpu
2719 * is in the middle of the transition from real mode to
2720 * protected mode it is safe to assume that RPL 0 is a good
2723 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2724 save->selector &= ~SEGMENT_RPL_MASK;
2725 save->dpl = save->selector & SEGMENT_RPL_MASK;
2728 __vmx_set_segment(vcpu, save, seg);
2731 static void enter_pmode(struct kvm_vcpu *vcpu)
2733 unsigned long flags;
2734 struct vcpu_vmx *vmx = to_vmx(vcpu);
2737 * Update real mode segment cache. It may be not up-to-date if segment
2738 * register was written while vcpu was in a guest mode.
2740 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2741 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2742 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2743 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2744 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2745 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2747 vmx->rmode.vm86_active = 0;
2749 __vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2751 flags = vmcs_readl(GUEST_RFLAGS);
2752 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2753 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2754 vmcs_writel(GUEST_RFLAGS, flags);
2756 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2757 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2759 vmx_update_exception_bitmap(vcpu);
2761 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2762 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2763 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2764 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2765 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2766 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2769 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2771 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2772 struct kvm_segment var = *save;
2775 if (seg == VCPU_SREG_CS)
2778 if (!emulate_invalid_guest_state) {
2779 var.selector = var.base >> 4;
2780 var.base = var.base & 0xffff0;
2790 if (save->base & 0xf)
2791 printk_once(KERN_WARNING "kvm: segment base is not "
2792 "paragraph aligned when entering "
2793 "protected mode (seg=%d)", seg);
2796 vmcs_write16(sf->selector, var.selector);
2797 vmcs_writel(sf->base, var.base);
2798 vmcs_write32(sf->limit, var.limit);
2799 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2802 static void enter_rmode(struct kvm_vcpu *vcpu)
2804 unsigned long flags;
2805 struct vcpu_vmx *vmx = to_vmx(vcpu);
2806 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2808 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2809 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2810 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2811 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2812 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2813 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2814 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2816 vmx->rmode.vm86_active = 1;
2819 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2820 * vcpu. Warn the user that an update is overdue.
2822 if (!kvm_vmx->tss_addr)
2823 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2824 "called before entering vcpu\n");
2826 vmx_segment_cache_clear(vmx);
2828 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2829 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2830 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2832 flags = vmcs_readl(GUEST_RFLAGS);
2833 vmx->rmode.save_rflags = flags;
2835 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2837 vmcs_writel(GUEST_RFLAGS, flags);
2838 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2839 vmx_update_exception_bitmap(vcpu);
2841 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2842 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2843 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2844 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2845 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2846 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2849 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2851 struct vcpu_vmx *vmx = to_vmx(vcpu);
2852 struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER);
2854 /* Nothing to do if hardware doesn't support EFER. */
2858 vcpu->arch.efer = efer;
2859 if (efer & EFER_LMA) {
2860 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2863 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2865 msr->data = efer & ~EFER_LME;
2867 vmx_setup_uret_msrs(vmx);
2871 #ifdef CONFIG_X86_64
2873 static void enter_lmode(struct kvm_vcpu *vcpu)
2877 vmx_segment_cache_clear(to_vmx(vcpu));
2879 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2880 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2881 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2883 vmcs_write32(GUEST_TR_AR_BYTES,
2884 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2885 | VMX_AR_TYPE_BUSY_64_TSS);
2887 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2890 static void exit_lmode(struct kvm_vcpu *vcpu)
2892 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2893 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2898 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2900 struct vcpu_vmx *vmx = to_vmx(vcpu);
2903 * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2904 * the CPU is not required to invalidate guest-physical mappings on
2905 * VM-Entry, even if VPID is disabled. Guest-physical mappings are
2906 * associated with the root EPT structure and not any particular VPID
2907 * (INVVPID also isn't required to invalidate guest-physical mappings).
2911 } else if (enable_vpid) {
2912 if (cpu_has_vmx_invvpid_global()) {
2913 vpid_sync_vcpu_global();
2915 vpid_sync_vcpu_single(vmx->vpid);
2916 vpid_sync_vcpu_single(vmx->nested.vpid02);
2921 static inline int vmx_get_current_vpid(struct kvm_vcpu *vcpu)
2923 if (is_guest_mode(vcpu))
2924 return nested_get_vpid02(vcpu);
2925 return to_vmx(vcpu)->vpid;
2928 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2930 struct kvm_mmu *mmu = vcpu->arch.mmu;
2931 u64 root_hpa = mmu->root_hpa;
2933 /* No flush required if the current context is invalid. */
2934 if (!VALID_PAGE(root_hpa))
2938 ept_sync_context(construct_eptp(vcpu, root_hpa,
2939 mmu->shadow_root_level));
2941 vpid_sync_context(vmx_get_current_vpid(vcpu));
2944 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2947 * vpid_sync_vcpu_addr() is a nop if vpid==0, see the comment in
2948 * vmx_flush_tlb_guest() for an explanation of why this is ok.
2950 vpid_sync_vcpu_addr(vmx_get_current_vpid(vcpu), addr);
2953 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2956 * vpid_sync_context() is a nop if vpid==0, e.g. if enable_vpid==0 or a
2957 * vpid couldn't be allocated for this vCPU. VM-Enter and VM-Exit are
2958 * required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2959 * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2960 * i.e. no explicit INVVPID is necessary.
2962 vpid_sync_context(vmx_get_current_vpid(vcpu));
2965 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2967 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2969 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2972 if (is_pae_paging(vcpu)) {
2973 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2974 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2975 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2976 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2980 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2982 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2984 if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2987 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2988 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2989 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2990 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2992 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2995 #define CR3_EXITING_BITS (CPU_BASED_CR3_LOAD_EXITING | \
2996 CPU_BASED_CR3_STORE_EXITING)
2998 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3000 struct vcpu_vmx *vmx = to_vmx(vcpu);
3001 unsigned long hw_cr0, old_cr0_pg;
3004 old_cr0_pg = kvm_read_cr0_bits(vcpu, X86_CR0_PG);
3006 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3007 if (is_unrestricted_guest(vcpu))
3008 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3010 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3012 hw_cr0 |= X86_CR0_WP;
3014 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3017 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3021 vmcs_writel(CR0_READ_SHADOW, cr0);
3022 vmcs_writel(GUEST_CR0, hw_cr0);
3023 vcpu->arch.cr0 = cr0;
3024 kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3026 #ifdef CONFIG_X86_64
3027 if (vcpu->arch.efer & EFER_LME) {
3028 if (!old_cr0_pg && (cr0 & X86_CR0_PG))
3030 else if (old_cr0_pg && !(cr0 & X86_CR0_PG))
3035 if (enable_ept && !is_unrestricted_guest(vcpu)) {
3037 * Ensure KVM has an up-to-date snapshot of the guest's CR3. If
3038 * the below code _enables_ CR3 exiting, vmx_cache_reg() will
3039 * (correctly) stop reading vmcs.GUEST_CR3 because it thinks
3040 * KVM's CR3 is installed.
3042 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
3043 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
3046 * When running with EPT but not unrestricted guest, KVM must
3047 * intercept CR3 accesses when paging is _disabled_. This is
3048 * necessary because restricted guests can't actually run with
3049 * paging disabled, and so KVM stuffs its own CR3 in order to
3050 * run the guest when identity mapped page tables.
3052 * Do _NOT_ check the old CR0.PG, e.g. to optimize away the
3053 * update, it may be stale with respect to CR3 interception,
3054 * e.g. after nested VM-Enter.
3056 * Lastly, honor L1's desires, i.e. intercept CR3 loads and/or
3057 * stores to forward them to L1, even if KVM does not need to
3058 * intercept them to preserve its identity mapped page tables.
3060 if (!(cr0 & X86_CR0_PG)) {
3061 exec_controls_setbit(vmx, CR3_EXITING_BITS);
3062 } else if (!is_guest_mode(vcpu)) {
3063 exec_controls_clearbit(vmx, CR3_EXITING_BITS);
3065 tmp = exec_controls_get(vmx);
3066 tmp &= ~CR3_EXITING_BITS;
3067 tmp |= get_vmcs12(vcpu)->cpu_based_vm_exec_control & CR3_EXITING_BITS;
3068 exec_controls_set(vmx, tmp);
3071 /* Note, vmx_set_cr4() consumes the new vcpu->arch.cr0. */
3072 if ((old_cr0_pg ^ cr0) & X86_CR0_PG)
3073 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3076 /* depends on vcpu->arch.cr0 to be set to a new value */
3077 vmx->emulation_required = vmx_emulation_required(vcpu);
3080 static int vmx_get_max_tdp_level(void)
3082 if (cpu_has_vmx_ept_5levels())
3087 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level)
3089 u64 eptp = VMX_EPTP_MT_WB;
3091 eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3093 if (enable_ept_ad_bits &&
3094 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3095 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3101 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3104 struct kvm *kvm = vcpu->kvm;
3105 bool update_guest_cr3 = true;
3106 unsigned long guest_cr3;
3110 eptp = construct_eptp(vcpu, root_hpa, root_level);
3111 vmcs_write64(EPT_POINTER, eptp);
3113 hv_track_root_tdp(vcpu, root_hpa);
3115 if (!enable_unrestricted_guest && !is_paging(vcpu))
3116 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3117 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3118 guest_cr3 = vcpu->arch.cr3;
3119 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3120 update_guest_cr3 = false;
3121 vmx_ept_load_pdptrs(vcpu);
3123 guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu);
3126 if (update_guest_cr3)
3127 vmcs_writel(GUEST_CR3, guest_cr3);
3130 static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3133 * We operate under the default treatment of SMM, so VMX cannot be
3134 * enabled under SMM. Note, whether or not VMXE is allowed at all is
3135 * handled by kvm_is_valid_cr4().
3137 if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu))
3140 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3146 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3148 unsigned long old_cr4 = vcpu->arch.cr4;
3149 struct vcpu_vmx *vmx = to_vmx(vcpu);
3151 * Pass through host's Machine Check Enable value to hw_cr4, which
3152 * is in force while we are in guest mode. Do not let guests control
3153 * this bit, even if host CR4.MCE == 0.
3155 unsigned long hw_cr4;
3157 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3158 if (is_unrestricted_guest(vcpu))
3159 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3160 else if (vmx->rmode.vm86_active)
3161 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3163 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3165 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3166 if (cr4 & X86_CR4_UMIP) {
3167 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3168 hw_cr4 &= ~X86_CR4_UMIP;
3169 } else if (!is_guest_mode(vcpu) ||
3170 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3171 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3175 vcpu->arch.cr4 = cr4;
3176 kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3178 if (!is_unrestricted_guest(vcpu)) {
3180 if (!is_paging(vcpu)) {
3181 hw_cr4 &= ~X86_CR4_PAE;
3182 hw_cr4 |= X86_CR4_PSE;
3183 } else if (!(cr4 & X86_CR4_PAE)) {
3184 hw_cr4 &= ~X86_CR4_PAE;
3189 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3190 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3191 * to be manually disabled when guest switches to non-paging
3194 * If !enable_unrestricted_guest, the CPU is always running
3195 * with CR0.PG=1 and CR4 needs to be modified.
3196 * If enable_unrestricted_guest, the CPU automatically
3197 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3199 if (!is_paging(vcpu))
3200 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3203 vmcs_writel(CR4_READ_SHADOW, cr4);
3204 vmcs_writel(GUEST_CR4, hw_cr4);
3206 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
3207 kvm_update_cpuid_runtime(vcpu);
3210 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3212 struct vcpu_vmx *vmx = to_vmx(vcpu);
3215 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3216 *var = vmx->rmode.segs[seg];
3217 if (seg == VCPU_SREG_TR
3218 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3220 var->base = vmx_read_guest_seg_base(vmx, seg);
3221 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3224 var->base = vmx_read_guest_seg_base(vmx, seg);
3225 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3226 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3227 ar = vmx_read_guest_seg_ar(vmx, seg);
3228 var->unusable = (ar >> 16) & 1;
3229 var->type = ar & 15;
3230 var->s = (ar >> 4) & 1;
3231 var->dpl = (ar >> 5) & 3;
3233 * Some userspaces do not preserve unusable property. Since usable
3234 * segment has to be present according to VMX spec we can use present
3235 * property to amend userspace bug by making unusable segment always
3236 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3237 * segment as unusable.
3239 var->present = !var->unusable;
3240 var->avl = (ar >> 12) & 1;
3241 var->l = (ar >> 13) & 1;
3242 var->db = (ar >> 14) & 1;
3243 var->g = (ar >> 15) & 1;
3246 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3248 struct kvm_segment s;
3250 if (to_vmx(vcpu)->rmode.vm86_active) {
3251 vmx_get_segment(vcpu, &s, seg);
3254 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3257 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3259 struct vcpu_vmx *vmx = to_vmx(vcpu);
3261 if (unlikely(vmx->rmode.vm86_active))
3264 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3265 return VMX_AR_DPL(ar);
3269 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3273 if (var->unusable || !var->present)
3276 ar = var->type & 15;
3277 ar |= (var->s & 1) << 4;
3278 ar |= (var->dpl & 3) << 5;
3279 ar |= (var->present & 1) << 7;
3280 ar |= (var->avl & 1) << 12;
3281 ar |= (var->l & 1) << 13;
3282 ar |= (var->db & 1) << 14;
3283 ar |= (var->g & 1) << 15;
3289 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3291 struct vcpu_vmx *vmx = to_vmx(vcpu);
3292 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3294 vmx_segment_cache_clear(vmx);
3296 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3297 vmx->rmode.segs[seg] = *var;
3298 if (seg == VCPU_SREG_TR)
3299 vmcs_write16(sf->selector, var->selector);
3301 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3305 vmcs_writel(sf->base, var->base);
3306 vmcs_write32(sf->limit, var->limit);
3307 vmcs_write16(sf->selector, var->selector);
3310 * Fix the "Accessed" bit in AR field of segment registers for older
3312 * IA32 arch specifies that at the time of processor reset the
3313 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3314 * is setting it to 0 in the userland code. This causes invalid guest
3315 * state vmexit when "unrestricted guest" mode is turned on.
3316 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3317 * tree. Newer qemu binaries with that qemu fix would not need this
3320 if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3321 var->type |= 0x1; /* Accessed */
3323 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3326 static void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3328 __vmx_set_segment(vcpu, var, seg);
3330 to_vmx(vcpu)->emulation_required = vmx_emulation_required(vcpu);
3333 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3335 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3337 *db = (ar >> 14) & 1;
3338 *l = (ar >> 13) & 1;
3341 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3343 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3344 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3347 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3349 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3350 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3353 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3355 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3356 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3359 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3361 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3362 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3365 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3367 struct kvm_segment var;
3370 vmx_get_segment(vcpu, &var, seg);
3372 if (seg == VCPU_SREG_CS)
3374 ar = vmx_segment_access_rights(&var);
3376 if (var.base != (var.selector << 4))
3378 if (var.limit != 0xffff)
3386 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3388 struct kvm_segment cs;
3389 unsigned int cs_rpl;
3391 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3392 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3396 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3400 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3401 if (cs.dpl > cs_rpl)
3404 if (cs.dpl != cs_rpl)
3410 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3414 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3416 struct kvm_segment ss;
3417 unsigned int ss_rpl;
3419 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3420 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3424 if (ss.type != 3 && ss.type != 7)
3428 if (ss.dpl != ss_rpl) /* DPL != RPL */
3436 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3438 struct kvm_segment var;
3441 vmx_get_segment(vcpu, &var, seg);
3442 rpl = var.selector & SEGMENT_RPL_MASK;
3450 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3451 if (var.dpl < rpl) /* DPL < RPL */
3455 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3461 static bool tr_valid(struct kvm_vcpu *vcpu)
3463 struct kvm_segment tr;
3465 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3469 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3471 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3479 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3481 struct kvm_segment ldtr;
3483 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3487 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3497 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3499 struct kvm_segment cs, ss;
3501 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3502 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3504 return ((cs.selector & SEGMENT_RPL_MASK) ==
3505 (ss.selector & SEGMENT_RPL_MASK));
3509 * Check if guest state is valid. Returns true if valid, false if
3511 * We assume that registers are always usable
3513 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu)
3515 /* real mode guest state checks */
3516 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3517 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3519 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3521 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3523 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3525 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3527 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3530 /* protected mode guest state checks */
3531 if (!cs_ss_rpl_check(vcpu))
3533 if (!code_segment_valid(vcpu))
3535 if (!stack_segment_valid(vcpu))
3537 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3539 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3541 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3543 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3545 if (!tr_valid(vcpu))
3547 if (!ldtr_valid(vcpu))
3551 * - Add checks on RIP
3552 * - Add checks on RFLAGS
3558 static int init_rmode_tss(struct kvm *kvm, void __user *ua)
3560 const void *zero_page = (const void *) __va(page_to_phys(ZERO_PAGE(0)));
3564 for (i = 0; i < 3; i++) {
3565 if (__copy_to_user(ua + PAGE_SIZE * i, zero_page, PAGE_SIZE))
3569 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3570 if (__copy_to_user(ua + TSS_IOPB_BASE_OFFSET, &data, sizeof(u16)))
3574 if (__copy_to_user(ua + RMODE_TSS_SIZE - 1, &data, sizeof(u8)))
3580 static int init_rmode_identity_map(struct kvm *kvm)
3582 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3587 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3588 mutex_lock(&kvm->slots_lock);
3590 if (likely(kvm_vmx->ept_identity_pagetable_done))
3593 if (!kvm_vmx->ept_identity_map_addr)
3594 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3596 uaddr = __x86_set_memory_region(kvm,
3597 IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3598 kvm_vmx->ept_identity_map_addr,
3600 if (IS_ERR(uaddr)) {
3605 /* Set up identity-mapping pagetable for EPT in real mode */
3606 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3607 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3608 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3609 if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) {
3614 kvm_vmx->ept_identity_pagetable_done = true;
3617 mutex_unlock(&kvm->slots_lock);
3621 static void seg_setup(int seg)
3623 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3626 vmcs_write16(sf->selector, 0);
3627 vmcs_writel(sf->base, 0);
3628 vmcs_write32(sf->limit, 0xffff);
3630 if (seg == VCPU_SREG_CS)
3631 ar |= 0x08; /* code segment */
3633 vmcs_write32(sf->ar_bytes, ar);
3636 static int alloc_apic_access_page(struct kvm *kvm)
3642 mutex_lock(&kvm->slots_lock);
3643 if (kvm->arch.apic_access_memslot_enabled)
3645 hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3646 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3652 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3653 if (is_error_page(page)) {
3659 * Do not pin the page in memory, so that memory hot-unplug
3660 * is able to migrate it.
3663 kvm->arch.apic_access_memslot_enabled = true;
3665 mutex_unlock(&kvm->slots_lock);
3669 int allocate_vpid(void)
3675 spin_lock(&vmx_vpid_lock);
3676 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3677 if (vpid < VMX_NR_VPIDS)
3678 __set_bit(vpid, vmx_vpid_bitmap);
3681 spin_unlock(&vmx_vpid_lock);
3685 void free_vpid(int vpid)
3687 if (!enable_vpid || vpid == 0)
3689 spin_lock(&vmx_vpid_lock);
3690 __clear_bit(vpid, vmx_vpid_bitmap);
3691 spin_unlock(&vmx_vpid_lock);
3694 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3696 struct vcpu_vmx *vmx = to_vmx(vcpu);
3697 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3699 if (!cpu_has_vmx_msr_bitmap())
3702 if (static_branch_unlikely(&enable_evmcs))
3703 evmcs_touch_msr_bitmap();
3706 * Mark the desired intercept state in shadow bitmap, this is needed
3707 * for resync when the MSR filters change.
3709 if (is_valid_passthrough_msr(msr)) {
3710 int idx = possible_passthrough_msr_slot(msr);
3712 if (idx != -ENOENT) {
3713 if (type & MSR_TYPE_R)
3714 clear_bit(idx, vmx->shadow_msr_intercept.read);
3715 if (type & MSR_TYPE_W)
3716 clear_bit(idx, vmx->shadow_msr_intercept.write);
3720 if ((type & MSR_TYPE_R) &&
3721 !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) {
3722 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3723 type &= ~MSR_TYPE_R;
3726 if ((type & MSR_TYPE_W) &&
3727 !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) {
3728 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3729 type &= ~MSR_TYPE_W;
3732 if (type & MSR_TYPE_R)
3733 vmx_clear_msr_bitmap_read(msr_bitmap, msr);
3735 if (type & MSR_TYPE_W)
3736 vmx_clear_msr_bitmap_write(msr_bitmap, msr);
3739 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3741 struct vcpu_vmx *vmx = to_vmx(vcpu);
3742 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3744 if (!cpu_has_vmx_msr_bitmap())
3747 if (static_branch_unlikely(&enable_evmcs))
3748 evmcs_touch_msr_bitmap();
3751 * Mark the desired intercept state in shadow bitmap, this is needed
3752 * for resync when the MSR filter changes.
3754 if (is_valid_passthrough_msr(msr)) {
3755 int idx = possible_passthrough_msr_slot(msr);
3757 if (idx != -ENOENT) {
3758 if (type & MSR_TYPE_R)
3759 set_bit(idx, vmx->shadow_msr_intercept.read);
3760 if (type & MSR_TYPE_W)
3761 set_bit(idx, vmx->shadow_msr_intercept.write);
3765 if (type & MSR_TYPE_R)
3766 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3768 if (type & MSR_TYPE_W)
3769 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3772 static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode)
3774 unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
3775 unsigned long read_intercept;
3778 read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3780 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3781 unsigned int read_idx = msr / BITS_PER_LONG;
3782 unsigned int write_idx = read_idx + (0x800 / sizeof(long));
3784 msr_bitmap[read_idx] = read_intercept;
3785 msr_bitmap[write_idx] = ~0ul;
3789 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
3791 struct vcpu_vmx *vmx = to_vmx(vcpu);
3794 if (!cpu_has_vmx_msr_bitmap())
3797 if (cpu_has_secondary_exec_ctrls() &&
3798 (secondary_exec_controls_get(vmx) &
3799 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3800 mode = MSR_BITMAP_MODE_X2APIC;
3801 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3802 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3807 if (mode == vmx->x2apic_msr_bitmap_mode)
3810 vmx->x2apic_msr_bitmap_mode = mode;
3812 vmx_reset_x2apic_msrs(vcpu, mode);
3815 * TPR reads and writes can be virtualized even if virtual interrupt
3816 * delivery is not in use.
3818 vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
3819 !(mode & MSR_BITMAP_MODE_X2APIC));
3821 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3822 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
3823 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3824 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3828 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu)
3830 struct vcpu_vmx *vmx = to_vmx(vcpu);
3831 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3834 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
3835 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
3836 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
3837 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
3838 for (i = 0; i < vmx->pt_desc.num_address_ranges; i++) {
3839 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3840 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3844 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3846 struct vcpu_vmx *vmx = to_vmx(vcpu);
3851 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3852 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3853 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3856 rvi = vmx_get_rvi();
3858 vapic_page = vmx->nested.virtual_apic_map.hva;
3859 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3861 return ((rvi & 0xf0) > (vppr & 0xf0));
3864 static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
3866 struct vcpu_vmx *vmx = to_vmx(vcpu);
3870 * Set intercept permissions for all potentially passed through MSRs
3871 * again. They will automatically get filtered through the MSR filter,
3872 * so we are back in sync after this.
3874 for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
3875 u32 msr = vmx_possible_passthrough_msrs[i];
3876 bool read = test_bit(i, vmx->shadow_msr_intercept.read);
3877 bool write = test_bit(i, vmx->shadow_msr_intercept.write);
3879 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
3880 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
3883 pt_update_intercept_for_msr(vcpu);
3886 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3890 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3892 if (vcpu->mode == IN_GUEST_MODE) {
3894 * The vector of interrupt to be delivered to vcpu had
3895 * been set in PIR before this function.
3897 * Following cases will be reached in this block, and
3898 * we always send a notification event in all cases as
3901 * Case 1: vcpu keeps in non-root mode. Sending a
3902 * notification event posts the interrupt to vcpu.
3904 * Case 2: vcpu exits to root mode and is still
3905 * runnable. PIR will be synced to vIRR before the
3906 * next vcpu entry. Sending a notification event in
3907 * this case has no effect, as vcpu is not in root
3910 * Case 3: vcpu exits to root mode and is blocked.
3911 * vcpu_block() has already synced PIR to vIRR and
3912 * never blocks vcpu if vIRR is not cleared. Therefore,
3913 * a blocked vcpu here does not wait for any requested
3914 * interrupts in PIR, and sending a notification event
3915 * which has no effect is safe here.
3918 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3925 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3928 struct vcpu_vmx *vmx = to_vmx(vcpu);
3930 if (is_guest_mode(vcpu) &&
3931 vector == vmx->nested.posted_intr_nv) {
3933 * If a posted intr is not recognized by hardware,
3934 * we will accomplish it in the next vmentry.
3936 vmx->nested.pi_pending = true;
3937 kvm_make_request(KVM_REQ_EVENT, vcpu);
3938 /* the PIR and ON have been set by L1. */
3939 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3940 kvm_vcpu_kick(vcpu);
3946 * Send interrupt to vcpu via posted interrupt way.
3947 * 1. If target vcpu is running(non-root mode), send posted interrupt
3948 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3949 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3950 * interrupt from PIR in next vmentry.
3952 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3954 struct vcpu_vmx *vmx = to_vmx(vcpu);
3957 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3961 if (!vcpu->arch.apicv_active)
3964 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3967 /* If a previous notification has sent the IPI, nothing to do. */
3968 if (pi_test_and_set_on(&vmx->pi_desc))
3971 if (vcpu != kvm_get_running_vcpu() &&
3972 !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3973 kvm_vcpu_kick(vcpu);
3979 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3980 * will not change in the lifetime of the guest.
3981 * Note that host-state that does change is set elsewhere. E.g., host-state
3982 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3984 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3988 unsigned long cr0, cr3, cr4;
3991 WARN_ON(cr0 & X86_CR0_TS);
3992 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3995 * Save the most likely value for this task's CR3 in the VMCS.
3996 * We can't use __get_current_cr3_fast() because we're not atomic.
3999 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
4000 vmx->loaded_vmcs->host_state.cr3 = cr3;
4002 /* Save the most likely value for this task's CR4 in the VMCS. */
4003 cr4 = cr4_read_shadow();
4004 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4005 vmx->loaded_vmcs->host_state.cr4 = cr4;
4007 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4008 #ifdef CONFIG_X86_64
4010 * Load null selectors, so we can avoid reloading them in
4011 * vmx_prepare_switch_to_host(), in case userspace uses
4012 * the null selectors too (the expected case).
4014 vmcs_write16(HOST_DS_SELECTOR, 0);
4015 vmcs_write16(HOST_ES_SELECTOR, 0);
4017 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4018 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4020 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4021 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4023 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
4025 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4027 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4028 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4029 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4030 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4032 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4033 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4034 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4037 if (cpu_has_load_ia32_efer())
4038 vmcs_write64(HOST_IA32_EFER, host_efer);
4041 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4043 struct kvm_vcpu *vcpu = &vmx->vcpu;
4045 vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
4046 ~vcpu->arch.cr4_guest_rsvd_bits;
4048 vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4049 if (is_guest_mode(&vmx->vcpu))
4050 vcpu->arch.cr4_guest_owned_bits &=
4051 ~get_vmcs12(vcpu)->cr4_guest_host_mask;
4052 vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits);
4055 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4057 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4059 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4060 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4063 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4065 if (!enable_preemption_timer)
4066 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4068 return pin_based_exec_ctrl;
4071 static u32 vmx_vmentry_ctrl(void)
4073 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
4075 if (vmx_pt_mode_is_system())
4076 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
4077 VM_ENTRY_LOAD_IA32_RTIT_CTL);
4078 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4079 return vmentry_ctrl &
4080 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
4083 static u32 vmx_vmexit_ctrl(void)
4085 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
4087 if (vmx_pt_mode_is_system())
4088 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
4089 VM_EXIT_CLEAR_IA32_RTIT_CTL);
4090 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4091 return vmexit_ctrl &
4092 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
4095 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4097 struct vcpu_vmx *vmx = to_vmx(vcpu);
4099 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4100 if (cpu_has_secondary_exec_ctrls()) {
4101 if (kvm_vcpu_apicv_active(vcpu))
4102 secondary_exec_controls_setbit(vmx,
4103 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4104 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4106 secondary_exec_controls_clearbit(vmx,
4107 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4108 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4111 vmx_update_msr_bitmap_x2apic(vcpu);
4114 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4116 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4118 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4119 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4121 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4122 exec_control &= ~CPU_BASED_TPR_SHADOW;
4123 #ifdef CONFIG_X86_64
4124 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4125 CPU_BASED_CR8_LOAD_EXITING;
4129 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4130 CPU_BASED_CR3_LOAD_EXITING |
4131 CPU_BASED_INVLPG_EXITING;
4132 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4133 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4134 CPU_BASED_MONITOR_EXITING);
4135 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4136 exec_control &= ~CPU_BASED_HLT_EXITING;
4137 return exec_control;
4141 * Adjust a single secondary execution control bit to intercept/allow an
4142 * instruction in the guest. This is usually done based on whether or not a
4143 * feature has been exposed to the guest in order to correctly emulate faults.
4146 vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control,
4147 u32 control, bool enabled, bool exiting)
4150 * If the control is for an opt-in feature, clear the control if the
4151 * feature is not exposed to the guest, i.e. not enabled. If the
4152 * control is opt-out, i.e. an exiting control, clear the control if
4153 * the feature _is_ exposed to the guest, i.e. exiting/interception is
4154 * disabled for the associated instruction. Note, the caller is
4155 * responsible presetting exec_control to set all supported bits.
4157 if (enabled == exiting)
4158 *exec_control &= ~control;
4161 * Update the nested MSR settings so that a nested VMM can/can't set
4162 * controls for features that are/aren't exposed to the guest.
4166 vmx->nested.msrs.secondary_ctls_high |= control;
4168 vmx->nested.msrs.secondary_ctls_high &= ~control;
4173 * Wrapper macro for the common case of adjusting a secondary execution control
4174 * based on a single guest CPUID bit, with a dedicated feature bit. This also
4175 * verifies that the control is actually supported by KVM and hardware.
4177 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \
4181 if (cpu_has_vmx_##name()) { \
4182 __enabled = guest_cpuid_has(&(vmx)->vcpu, \
4183 X86_FEATURE_##feat_name); \
4184 vmx_adjust_secondary_exec_control(vmx, exec_control, \
4185 SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \
4189 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */
4190 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \
4191 vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false)
4193 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \
4194 vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true)
4196 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4198 struct kvm_vcpu *vcpu = &vmx->vcpu;
4200 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4202 if (vmx_pt_mode_is_system())
4203 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4204 if (!cpu_need_virtualize_apic_accesses(vcpu))
4205 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4207 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4209 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4210 enable_unrestricted_guest = 0;
4212 if (!enable_unrestricted_guest)
4213 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4214 if (kvm_pause_in_guest(vmx->vcpu.kvm))
4215 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4216 if (!kvm_vcpu_apicv_active(vcpu))
4217 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4218 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4219 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4221 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4222 * in vmx_set_cr4. */
4223 exec_control &= ~SECONDARY_EXEC_DESC;
4225 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4227 We can NOT enable shadow_vmcs here because we don't have yet
4230 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4233 * PML is enabled/disabled when dirty logging of memsmlots changes, but
4234 * it needs to be set here when dirty logging is already active, e.g.
4235 * if this vCPU was created after dirty logging was enabled.
4237 if (!vcpu->kvm->arch.cpu_dirty_logging_count)
4238 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4240 if (cpu_has_vmx_xsaves()) {
4241 /* Exposing XSAVES only when XSAVE is exposed */
4242 bool xsaves_enabled =
4243 boot_cpu_has(X86_FEATURE_XSAVE) &&
4244 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4245 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4247 vcpu->arch.xsaves_enabled = xsaves_enabled;
4249 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4250 SECONDARY_EXEC_XSAVES,
4251 xsaves_enabled, false);
4255 * RDPID is also gated by ENABLE_RDTSCP, turn on the control if either
4256 * feature is exposed to the guest. This creates a virtualization hole
4257 * if both are supported in hardware but only one is exposed to the
4258 * guest, but letting the guest execute RDTSCP or RDPID when either one
4259 * is advertised is preferable to emulating the advertised instruction
4260 * in KVM on #UD, and obviously better than incorrectly injecting #UD.
4262 if (cpu_has_vmx_rdtscp()) {
4263 bool rdpid_or_rdtscp_enabled =
4264 guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) ||
4265 guest_cpuid_has(vcpu, X86_FEATURE_RDPID);
4267 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4268 SECONDARY_EXEC_ENABLE_RDTSCP,
4269 rdpid_or_rdtscp_enabled, false);
4271 vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID);
4273 vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND);
4274 vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED);
4276 vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG,
4277 ENABLE_USR_WAIT_PAUSE, false);
4279 if (!vcpu->kvm->arch.bus_lock_detection_enabled)
4280 exec_control &= ~SECONDARY_EXEC_BUS_LOCK_DETECTION;
4282 return exec_control;
4285 #define VMX_XSS_EXIT_BITMAP 0
4287 static void init_vmcs(struct vcpu_vmx *vmx)
4290 nested_vmx_set_vmcs_shadowing_bitmap();
4292 if (cpu_has_vmx_msr_bitmap())
4293 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4295 vmcs_write64(VMCS_LINK_POINTER, INVALID_GPA); /* 22.3.1.5 */
4298 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4300 exec_controls_set(vmx, vmx_exec_control(vmx));
4302 if (cpu_has_secondary_exec_ctrls())
4303 secondary_exec_controls_set(vmx, vmx_secondary_exec_control(vmx));
4305 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4306 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4307 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4308 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4309 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4311 vmcs_write16(GUEST_INTR_STATUS, 0);
4313 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4314 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4317 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4318 vmcs_write32(PLE_GAP, ple_gap);
4319 vmx->ple_window = ple_window;
4320 vmx->ple_window_dirty = true;
4323 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4324 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4325 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4327 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4328 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4329 vmx_set_constant_host_state(vmx);
4330 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4331 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4333 if (cpu_has_vmx_vmfunc())
4334 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4336 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4337 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4338 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4339 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4340 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4342 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4343 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4345 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4347 /* 22.2.1, 20.8.1 */
4348 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4350 vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4351 vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4353 set_cr4_guest_host_mask(vmx);
4356 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4358 if (cpu_has_vmx_xsaves())
4359 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4362 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4363 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4366 vmx_write_encls_bitmap(&vmx->vcpu, NULL);
4368 if (vmx_pt_mode_is_host_guest()) {
4369 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4370 /* Bit[6~0] are forced to 1, writes are ignored. */
4371 vmx->pt_desc.guest.output_mask = 0x7F;
4372 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4375 vmcs_write32(GUEST_SYSENTER_CS, 0);
4376 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4377 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4378 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4380 if (cpu_has_vmx_tpr_shadow()) {
4381 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4382 if (cpu_need_tpr_shadow(&vmx->vcpu))
4383 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4384 __pa(vmx->vcpu.arch.apic->regs));
4385 vmcs_write32(TPR_THRESHOLD, 0);
4388 vmx_setup_uret_msrs(vmx);
4391 static void __vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4393 struct vcpu_vmx *vmx = to_vmx(vcpu);
4398 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
4400 vcpu_setup_sgx_lepubkeyhash(vcpu);
4402 vmx->nested.posted_intr_nv = -1;
4403 vmx->nested.vmxon_ptr = INVALID_GPA;
4404 vmx->nested.current_vmptr = INVALID_GPA;
4405 vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
4407 vcpu->arch.microcode_version = 0x100000000ULL;
4408 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
4411 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
4412 * or POSTED_INTR_WAKEUP_VECTOR.
4414 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
4415 vmx->pi_desc.sn = 1;
4418 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4420 struct vcpu_vmx *vmx = to_vmx(vcpu);
4423 __vmx_vcpu_reset(vcpu);
4425 vmx->rmode.vm86_active = 0;
4428 vmx->msr_ia32_umwait_control = 0;
4430 vmx->hv_deadline_tsc = -1;
4431 kvm_set_cr8(vcpu, 0);
4433 vmx_segment_cache_clear(vmx);
4434 kvm_register_mark_available(vcpu, VCPU_EXREG_SEGMENTS);
4436 seg_setup(VCPU_SREG_CS);
4437 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4438 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4440 seg_setup(VCPU_SREG_DS);
4441 seg_setup(VCPU_SREG_ES);
4442 seg_setup(VCPU_SREG_FS);
4443 seg_setup(VCPU_SREG_GS);
4444 seg_setup(VCPU_SREG_SS);
4446 vmcs_write16(GUEST_TR_SELECTOR, 0);
4447 vmcs_writel(GUEST_TR_BASE, 0);
4448 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4449 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4451 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4452 vmcs_writel(GUEST_LDTR_BASE, 0);
4453 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4454 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4456 vmcs_writel(GUEST_GDTR_BASE, 0);
4457 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4459 vmcs_writel(GUEST_IDTR_BASE, 0);
4460 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4462 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4463 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4464 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4465 if (kvm_mpx_supported())
4466 vmcs_write64(GUEST_BNDCFGS, 0);
4468 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4470 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4472 vpid_sync_context(vmx->vpid);
4475 static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
4477 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4480 static void vmx_enable_nmi_window(struct kvm_vcpu *vcpu)
4483 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4484 vmx_enable_irq_window(vcpu);
4488 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4491 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4493 struct vcpu_vmx *vmx = to_vmx(vcpu);
4495 int irq = vcpu->arch.interrupt.nr;
4497 trace_kvm_inj_virq(irq);
4499 ++vcpu->stat.irq_injections;
4500 if (vmx->rmode.vm86_active) {
4502 if (vcpu->arch.interrupt.soft)
4503 inc_eip = vcpu->arch.event_exit_inst_len;
4504 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4507 intr = irq | INTR_INFO_VALID_MASK;
4508 if (vcpu->arch.interrupt.soft) {
4509 intr |= INTR_TYPE_SOFT_INTR;
4510 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4511 vmx->vcpu.arch.event_exit_inst_len);
4513 intr |= INTR_TYPE_EXT_INTR;
4514 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4516 vmx_clear_hlt(vcpu);
4519 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4521 struct vcpu_vmx *vmx = to_vmx(vcpu);
4525 * Tracking the NMI-blocked state in software is built upon
4526 * finding the next open IRQ window. This, in turn, depends on
4527 * well-behaving guests: They have to keep IRQs disabled at
4528 * least as long as the NMI handler runs. Otherwise we may
4529 * cause NMI nesting, maybe breaking the guest. But as this is
4530 * highly unlikely, we can live with the residual risk.
4532 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4533 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4536 ++vcpu->stat.nmi_injections;
4537 vmx->loaded_vmcs->nmi_known_unmasked = false;
4539 if (vmx->rmode.vm86_active) {
4540 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4544 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4545 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4547 vmx_clear_hlt(vcpu);
4550 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4552 struct vcpu_vmx *vmx = to_vmx(vcpu);
4556 return vmx->loaded_vmcs->soft_vnmi_blocked;
4557 if (vmx->loaded_vmcs->nmi_known_unmasked)
4559 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4560 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4564 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4566 struct vcpu_vmx *vmx = to_vmx(vcpu);
4569 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4570 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4571 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4574 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4576 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4577 GUEST_INTR_STATE_NMI);
4579 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4580 GUEST_INTR_STATE_NMI);
4584 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4586 if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4589 if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4592 return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4593 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4594 GUEST_INTR_STATE_NMI));
4597 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4599 if (to_vmx(vcpu)->nested.nested_run_pending)
4602 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
4603 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4606 return !vmx_nmi_blocked(vcpu);
4609 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4611 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4614 return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4615 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4616 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4619 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4621 if (to_vmx(vcpu)->nested.nested_run_pending)
4625 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4626 * e.g. if the IRQ arrived asynchronously after checking nested events.
4628 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4631 return !vmx_interrupt_blocked(vcpu);
4634 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4638 if (enable_unrestricted_guest)
4641 mutex_lock(&kvm->slots_lock);
4642 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4644 mutex_unlock(&kvm->slots_lock);
4647 return PTR_ERR(ret);
4649 to_kvm_vmx(kvm)->tss_addr = addr;
4651 return init_rmode_tss(kvm, ret);
4654 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4656 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4660 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4665 * Update instruction length as we may reinject the exception
4666 * from user space while in guest debugging mode.
4668 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4669 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4670 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4674 return !(vcpu->guest_debug &
4675 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4689 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4690 int vec, u32 err_code)
4693 * Instruction with address size override prefix opcode 0x67
4694 * Cause the #SS fault with 0 error code in VM86 mode.
4696 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4697 if (kvm_emulate_instruction(vcpu, 0)) {
4698 if (vcpu->arch.halt_request) {
4699 vcpu->arch.halt_request = 0;
4700 return kvm_vcpu_halt(vcpu);
4708 * Forward all other exceptions that are valid in real mode.
4709 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4710 * the required debugging infrastructure rework.
4712 kvm_queue_exception(vcpu, vec);
4716 static int handle_machine_check(struct kvm_vcpu *vcpu)
4718 /* handled by vmx_vcpu_run() */
4723 * If the host has split lock detection disabled, then #AC is
4724 * unconditionally injected into the guest, which is the pre split lock
4725 * detection behaviour.
4727 * If the host has split lock detection enabled then #AC is
4728 * only injected into the guest when:
4729 * - Guest CPL == 3 (user mode)
4730 * - Guest has #AC detection enabled in CR0
4731 * - Guest EFLAGS has AC bit set
4733 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu)
4735 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4738 return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4739 (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4742 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4744 struct vcpu_vmx *vmx = to_vmx(vcpu);
4745 struct kvm_run *kvm_run = vcpu->run;
4746 u32 intr_info, ex_no, error_code;
4747 unsigned long cr2, dr6;
4750 vect_info = vmx->idt_vectoring_info;
4751 intr_info = vmx_get_intr_info(vcpu);
4753 if (is_machine_check(intr_info) || is_nmi(intr_info))
4754 return 1; /* handled by handle_exception_nmi_irqoff() */
4756 if (is_invalid_opcode(intr_info))
4757 return handle_ud(vcpu);
4760 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4761 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4763 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4764 WARN_ON_ONCE(!enable_vmware_backdoor);
4767 * VMware backdoor emulation on #GP interception only handles
4768 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4769 * error code on #GP.
4772 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4775 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4779 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4780 * MMIO, it is better to report an internal error.
4781 * See the comments in vmx_handle_exit.
4783 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4784 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4785 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4786 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4787 vcpu->run->internal.ndata = 4;
4788 vcpu->run->internal.data[0] = vect_info;
4789 vcpu->run->internal.data[1] = intr_info;
4790 vcpu->run->internal.data[2] = error_code;
4791 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4795 if (is_page_fault(intr_info)) {
4796 cr2 = vmx_get_exit_qual(vcpu);
4797 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4799 * EPT will cause page fault only if we need to
4800 * detect illegal GPAs.
4802 WARN_ON_ONCE(!allow_smaller_maxphyaddr);
4803 kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4806 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4809 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4811 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4812 return handle_rmode_exception(vcpu, ex_no, error_code);
4816 dr6 = vmx_get_exit_qual(vcpu);
4817 if (!(vcpu->guest_debug &
4818 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4819 if (is_icebp(intr_info))
4820 WARN_ON(!skip_emulated_instruction(vcpu));
4822 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4825 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
4826 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4830 * Update instruction length as we may reinject #BP from
4831 * user space while in guest debugging mode. Reading it for
4832 * #DB as well causes no harm, it is not used in that case.
4834 vmx->vcpu.arch.event_exit_inst_len =
4835 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4836 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4837 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4838 kvm_run->debug.arch.exception = ex_no;
4841 if (vmx_guest_inject_ac(vcpu)) {
4842 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4847 * Handle split lock. Depending on detection mode this will
4848 * either warn and disable split lock detection for this
4849 * task or force SIGBUS on it.
4851 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4855 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4856 kvm_run->ex.exception = ex_no;
4857 kvm_run->ex.error_code = error_code;
4863 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4865 ++vcpu->stat.irq_exits;
4869 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4871 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4872 vcpu->mmio_needed = 0;
4876 static int handle_io(struct kvm_vcpu *vcpu)
4878 unsigned long exit_qualification;
4879 int size, in, string;
4882 exit_qualification = vmx_get_exit_qual(vcpu);
4883 string = (exit_qualification & 16) != 0;
4885 ++vcpu->stat.io_exits;
4888 return kvm_emulate_instruction(vcpu, 0);
4890 port = exit_qualification >> 16;
4891 size = (exit_qualification & 7) + 1;
4892 in = (exit_qualification & 8) != 0;
4894 return kvm_fast_pio(vcpu, size, port, in);
4898 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4901 * Patch in the VMCALL instruction:
4903 hypercall[0] = 0x0f;
4904 hypercall[1] = 0x01;
4905 hypercall[2] = 0xc1;
4908 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4909 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4911 if (is_guest_mode(vcpu)) {
4912 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4913 unsigned long orig_val = val;
4916 * We get here when L2 changed cr0 in a way that did not change
4917 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4918 * but did change L0 shadowed bits. So we first calculate the
4919 * effective cr0 value that L1 would like to write into the
4920 * hardware. It consists of the L2-owned bits from the new
4921 * value combined with the L1-owned bits from L1's guest_cr0.
4923 val = (val & ~vmcs12->cr0_guest_host_mask) |
4924 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4926 if (!nested_guest_cr0_valid(vcpu, val))
4929 if (kvm_set_cr0(vcpu, val))
4931 vmcs_writel(CR0_READ_SHADOW, orig_val);
4934 if (to_vmx(vcpu)->nested.vmxon &&
4935 !nested_host_cr0_valid(vcpu, val))
4938 return kvm_set_cr0(vcpu, val);
4942 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4944 if (is_guest_mode(vcpu)) {
4945 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4946 unsigned long orig_val = val;
4948 /* analogously to handle_set_cr0 */
4949 val = (val & ~vmcs12->cr4_guest_host_mask) |
4950 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4951 if (kvm_set_cr4(vcpu, val))
4953 vmcs_writel(CR4_READ_SHADOW, orig_val);
4956 return kvm_set_cr4(vcpu, val);
4959 static int handle_desc(struct kvm_vcpu *vcpu)
4961 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4962 return kvm_emulate_instruction(vcpu, 0);
4965 static int handle_cr(struct kvm_vcpu *vcpu)
4967 unsigned long exit_qualification, val;
4973 exit_qualification = vmx_get_exit_qual(vcpu);
4974 cr = exit_qualification & 15;
4975 reg = (exit_qualification >> 8) & 15;
4976 switch ((exit_qualification >> 4) & 3) {
4977 case 0: /* mov to cr */
4978 val = kvm_register_read(vcpu, reg);
4979 trace_kvm_cr_write(cr, val);
4982 err = handle_set_cr0(vcpu, val);
4983 return kvm_complete_insn_gp(vcpu, err);
4985 WARN_ON_ONCE(enable_unrestricted_guest);
4987 err = kvm_set_cr3(vcpu, val);
4988 return kvm_complete_insn_gp(vcpu, err);
4990 err = handle_set_cr4(vcpu, val);
4991 return kvm_complete_insn_gp(vcpu, err);
4993 u8 cr8_prev = kvm_get_cr8(vcpu);
4995 err = kvm_set_cr8(vcpu, cr8);
4996 ret = kvm_complete_insn_gp(vcpu, err);
4997 if (lapic_in_kernel(vcpu))
4999 if (cr8_prev <= cr8)
5002 * TODO: we might be squashing a
5003 * KVM_GUESTDBG_SINGLESTEP-triggered
5004 * KVM_EXIT_DEBUG here.
5006 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5012 KVM_BUG(1, vcpu->kvm, "Guest always owns CR0.TS");
5014 case 1: /*mov from cr*/
5017 WARN_ON_ONCE(enable_unrestricted_guest);
5019 val = kvm_read_cr3(vcpu);
5020 kvm_register_write(vcpu, reg, val);
5021 trace_kvm_cr_read(cr, val);
5022 return kvm_skip_emulated_instruction(vcpu);
5024 val = kvm_get_cr8(vcpu);
5025 kvm_register_write(vcpu, reg, val);
5026 trace_kvm_cr_read(cr, val);
5027 return kvm_skip_emulated_instruction(vcpu);
5031 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5032 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5033 kvm_lmsw(vcpu, val);
5035 return kvm_skip_emulated_instruction(vcpu);
5039 vcpu->run->exit_reason = 0;
5040 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5041 (int)(exit_qualification >> 4) & 3, cr);
5045 static int handle_dr(struct kvm_vcpu *vcpu)
5047 unsigned long exit_qualification;
5051 exit_qualification = vmx_get_exit_qual(vcpu);
5052 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5054 /* First, if DR does not exist, trigger UD */
5055 if (!kvm_require_dr(vcpu, dr))
5058 if (kvm_x86_ops.get_cpl(vcpu) > 0)
5061 dr7 = vmcs_readl(GUEST_DR7);
5064 * As the vm-exit takes precedence over the debug trap, we
5065 * need to emulate the latter, either for the host or the
5066 * guest debugging itself.
5068 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5069 vcpu->run->debug.arch.dr6 = DR6_BD | DR6_ACTIVE_LOW;
5070 vcpu->run->debug.arch.dr7 = dr7;
5071 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5072 vcpu->run->debug.arch.exception = DB_VECTOR;
5073 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5076 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5081 if (vcpu->guest_debug == 0) {
5082 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5085 * No more DR vmexits; force a reload of the debug registers
5086 * and reenter on this instruction. The next vmexit will
5087 * retrieve the full state of the debug registers.
5089 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5093 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5094 if (exit_qualification & TYPE_MOV_FROM_DR) {
5097 kvm_get_dr(vcpu, dr, &val);
5098 kvm_register_write(vcpu, reg, val);
5101 err = kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg));
5105 return kvm_complete_insn_gp(vcpu, err);
5108 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5110 get_debugreg(vcpu->arch.db[0], 0);
5111 get_debugreg(vcpu->arch.db[1], 1);
5112 get_debugreg(vcpu->arch.db[2], 2);
5113 get_debugreg(vcpu->arch.db[3], 3);
5114 get_debugreg(vcpu->arch.dr6, 6);
5115 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5117 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5118 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5121 * exc_debug expects dr6 to be cleared after it runs, avoid that it sees
5122 * a stale dr6 from the guest.
5124 set_debugreg(DR6_RESERVED, 6);
5127 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5129 vmcs_writel(GUEST_DR7, val);
5132 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5134 kvm_apic_update_ppr(vcpu);
5138 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5140 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5142 kvm_make_request(KVM_REQ_EVENT, vcpu);
5144 ++vcpu->stat.irq_window_exits;
5148 static int handle_invlpg(struct kvm_vcpu *vcpu)
5150 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5152 kvm_mmu_invlpg(vcpu, exit_qualification);
5153 return kvm_skip_emulated_instruction(vcpu);
5156 static int handle_apic_access(struct kvm_vcpu *vcpu)
5158 if (likely(fasteoi)) {
5159 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5160 int access_type, offset;
5162 access_type = exit_qualification & APIC_ACCESS_TYPE;
5163 offset = exit_qualification & APIC_ACCESS_OFFSET;
5165 * Sane guest uses MOV to write EOI, with written value
5166 * not cared. So make a short-circuit here by avoiding
5167 * heavy instruction emulation.
5169 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5170 (offset == APIC_EOI)) {
5171 kvm_lapic_set_eoi(vcpu);
5172 return kvm_skip_emulated_instruction(vcpu);
5175 return kvm_emulate_instruction(vcpu, 0);
5178 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5180 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5181 int vector = exit_qualification & 0xff;
5183 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5184 kvm_apic_set_eoi_accelerated(vcpu, vector);
5188 static int handle_apic_write(struct kvm_vcpu *vcpu)
5190 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5191 u32 offset = exit_qualification & 0xfff;
5193 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5194 kvm_apic_write_nodecode(vcpu, offset);
5198 static int handle_task_switch(struct kvm_vcpu *vcpu)
5200 struct vcpu_vmx *vmx = to_vmx(vcpu);
5201 unsigned long exit_qualification;
5202 bool has_error_code = false;
5205 int reason, type, idt_v, idt_index;
5207 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5208 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5209 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5211 exit_qualification = vmx_get_exit_qual(vcpu);
5213 reason = (u32)exit_qualification >> 30;
5214 if (reason == TASK_SWITCH_GATE && idt_v) {
5216 case INTR_TYPE_NMI_INTR:
5217 vcpu->arch.nmi_injected = false;
5218 vmx_set_nmi_mask(vcpu, true);
5220 case INTR_TYPE_EXT_INTR:
5221 case INTR_TYPE_SOFT_INTR:
5222 kvm_clear_interrupt_queue(vcpu);
5224 case INTR_TYPE_HARD_EXCEPTION:
5225 if (vmx->idt_vectoring_info &
5226 VECTORING_INFO_DELIVER_CODE_MASK) {
5227 has_error_code = true;
5229 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5232 case INTR_TYPE_SOFT_EXCEPTION:
5233 kvm_clear_exception_queue(vcpu);
5239 tss_selector = exit_qualification;
5241 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5242 type != INTR_TYPE_EXT_INTR &&
5243 type != INTR_TYPE_NMI_INTR))
5244 WARN_ON(!skip_emulated_instruction(vcpu));
5247 * TODO: What about debug traps on tss switch?
5248 * Are we supposed to inject them and update dr6?
5250 return kvm_task_switch(vcpu, tss_selector,
5251 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5252 reason, has_error_code, error_code);
5255 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5257 unsigned long exit_qualification;
5261 exit_qualification = vmx_get_exit_qual(vcpu);
5264 * EPT violation happened while executing iret from NMI,
5265 * "blocked by NMI" bit has to be set before next VM entry.
5266 * There are errata that may cause this bit to not be set:
5269 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5271 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5272 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5274 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5275 trace_kvm_page_fault(gpa, exit_qualification);
5277 /* Is it a read fault? */
5278 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5279 ? PFERR_USER_MASK : 0;
5280 /* Is it a write fault? */
5281 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5282 ? PFERR_WRITE_MASK : 0;
5283 /* Is it a fetch fault? */
5284 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5285 ? PFERR_FETCH_MASK : 0;
5286 /* ept page table entry is present? */
5287 error_code |= (exit_qualification &
5288 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5289 EPT_VIOLATION_EXECUTABLE))
5290 ? PFERR_PRESENT_MASK : 0;
5292 error_code |= (exit_qualification & EPT_VIOLATION_GVA_TRANSLATED) != 0 ?
5293 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5295 vcpu->arch.exit_qualification = exit_qualification;
5298 * Check that the GPA doesn't exceed physical memory limits, as that is
5299 * a guest page fault. We have to emulate the instruction here, because
5300 * if the illegal address is that of a paging structure, then
5301 * EPT_VIOLATION_ACC_WRITE bit is set. Alternatively, if supported we
5302 * would also use advanced VM-exit information for EPT violations to
5303 * reconstruct the page fault error code.
5305 if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa)))
5306 return kvm_emulate_instruction(vcpu, 0);
5308 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5311 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5315 if (!vmx_can_emulate_instruction(vcpu, NULL, 0))
5319 * A nested guest cannot optimize MMIO vmexits, because we have an
5320 * nGPA here instead of the required GPA.
5322 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5323 if (!is_guest_mode(vcpu) &&
5324 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5325 trace_kvm_fast_mmio(gpa);
5326 return kvm_skip_emulated_instruction(vcpu);
5329 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5332 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5334 if (KVM_BUG_ON(!enable_vnmi, vcpu->kvm))
5337 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5338 ++vcpu->stat.nmi_window_exits;
5339 kvm_make_request(KVM_REQ_EVENT, vcpu);
5344 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5346 struct vcpu_vmx *vmx = to_vmx(vcpu);
5347 bool intr_window_requested;
5348 unsigned count = 130;
5350 intr_window_requested = exec_controls_get(vmx) &
5351 CPU_BASED_INTR_WINDOW_EXITING;
5353 while (vmx->emulation_required && count-- != 0) {
5354 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5355 return handle_interrupt_window(&vmx->vcpu);
5357 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5360 if (!kvm_emulate_instruction(vcpu, 0))
5363 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5364 vcpu->arch.exception.pending) {
5365 kvm_prepare_emulation_failure_exit(vcpu);
5369 if (vcpu->arch.halt_request) {
5370 vcpu->arch.halt_request = 0;
5371 return kvm_vcpu_halt(vcpu);
5375 * Note, return 1 and not 0, vcpu_run() will invoke
5376 * xfer_to_guest_mode() which will create a proper return
5379 if (__xfer_to_guest_mode_work_pending())
5386 static void grow_ple_window(struct kvm_vcpu *vcpu)
5388 struct vcpu_vmx *vmx = to_vmx(vcpu);
5389 unsigned int old = vmx->ple_window;
5391 vmx->ple_window = __grow_ple_window(old, ple_window,
5395 if (vmx->ple_window != old) {
5396 vmx->ple_window_dirty = true;
5397 trace_kvm_ple_window_update(vcpu->vcpu_id,
5398 vmx->ple_window, old);
5402 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5404 struct vcpu_vmx *vmx = to_vmx(vcpu);
5405 unsigned int old = vmx->ple_window;
5407 vmx->ple_window = __shrink_ple_window(old, ple_window,
5411 if (vmx->ple_window != old) {
5412 vmx->ple_window_dirty = true;
5413 trace_kvm_ple_window_update(vcpu->vcpu_id,
5414 vmx->ple_window, old);
5419 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5420 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5422 static int handle_pause(struct kvm_vcpu *vcpu)
5424 if (!kvm_pause_in_guest(vcpu->kvm))
5425 grow_ple_window(vcpu);
5428 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5429 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5430 * never set PAUSE_EXITING and just set PLE if supported,
5431 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5433 kvm_vcpu_on_spin(vcpu, true);
5434 return kvm_skip_emulated_instruction(vcpu);
5437 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5442 static int handle_invpcid(struct kvm_vcpu *vcpu)
5444 u32 vmx_instruction_info;
5453 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5454 kvm_queue_exception(vcpu, UD_VECTOR);
5458 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5459 gpr_index = vmx_get_instr_info_reg2(vmx_instruction_info);
5460 type = kvm_register_read(vcpu, gpr_index);
5462 /* According to the Intel instruction reference, the memory operand
5463 * is read even if it isn't needed (e.g., for type==all)
5465 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5466 vmx_instruction_info, false,
5467 sizeof(operand), &gva))
5470 return kvm_handle_invpcid(vcpu, type, gva);
5473 static int handle_pml_full(struct kvm_vcpu *vcpu)
5475 unsigned long exit_qualification;
5477 trace_kvm_pml_full(vcpu->vcpu_id);
5479 exit_qualification = vmx_get_exit_qual(vcpu);
5482 * PML buffer FULL happened while executing iret from NMI,
5483 * "blocked by NMI" bit has to be set before next VM entry.
5485 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5487 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5488 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5489 GUEST_INTR_STATE_NMI);
5492 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5493 * here.., and there's no userspace involvement needed for PML.
5498 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5500 struct vcpu_vmx *vmx = to_vmx(vcpu);
5502 if (!vmx->req_immediate_exit &&
5503 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5504 kvm_lapic_expired_hv_timer(vcpu);
5505 return EXIT_FASTPATH_REENTER_GUEST;
5508 return EXIT_FASTPATH_NONE;
5511 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5513 handle_fastpath_preemption_timer(vcpu);
5518 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5519 * are overwritten by nested_vmx_setup() when nested=1.
5521 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5523 kvm_queue_exception(vcpu, UD_VECTOR);
5527 #ifndef CONFIG_X86_SGX_KVM
5528 static int handle_encls(struct kvm_vcpu *vcpu)
5531 * SGX virtualization is disabled. There is no software enable bit for
5532 * SGX, so KVM intercepts all ENCLS leafs and injects a #UD to prevent
5533 * the guest from executing ENCLS (when SGX is supported by hardware).
5535 kvm_queue_exception(vcpu, UD_VECTOR);
5538 #endif /* CONFIG_X86_SGX_KVM */
5540 static int handle_bus_lock_vmexit(struct kvm_vcpu *vcpu)
5543 * Hardware may or may not set the BUS_LOCK_DETECTED flag on BUS_LOCK
5544 * VM-Exits. Unconditionally set the flag here and leave the handling to
5545 * vmx_handle_exit().
5547 to_vmx(vcpu)->exit_reason.bus_lock_detected = true;
5552 * The exit handlers return 1 if the exit was handled fully and guest execution
5553 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5554 * to be done to userspace and return 0.
5556 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5557 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5558 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5559 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5560 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5561 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5562 [EXIT_REASON_CR_ACCESS] = handle_cr,
5563 [EXIT_REASON_DR_ACCESS] = handle_dr,
5564 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5565 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5566 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
5567 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
5568 [EXIT_REASON_HLT] = kvm_emulate_halt,
5569 [EXIT_REASON_INVD] = kvm_emulate_invd,
5570 [EXIT_REASON_INVLPG] = handle_invlpg,
5571 [EXIT_REASON_RDPMC] = kvm_emulate_rdpmc,
5572 [EXIT_REASON_VMCALL] = kvm_emulate_hypercall,
5573 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5574 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5575 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5576 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5577 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5578 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5579 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5580 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5581 [EXIT_REASON_VMON] = handle_vmx_instruction,
5582 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5583 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5584 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5585 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5586 [EXIT_REASON_WBINVD] = kvm_emulate_wbinvd,
5587 [EXIT_REASON_XSETBV] = kvm_emulate_xsetbv,
5588 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5589 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5590 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5591 [EXIT_REASON_LDTR_TR] = handle_desc,
5592 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5593 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5594 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5595 [EXIT_REASON_MWAIT_INSTRUCTION] = kvm_emulate_mwait,
5596 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5597 [EXIT_REASON_MONITOR_INSTRUCTION] = kvm_emulate_monitor,
5598 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5599 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5600 [EXIT_REASON_RDRAND] = kvm_handle_invalid_op,
5601 [EXIT_REASON_RDSEED] = kvm_handle_invalid_op,
5602 [EXIT_REASON_PML_FULL] = handle_pml_full,
5603 [EXIT_REASON_INVPCID] = handle_invpcid,
5604 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5605 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5606 [EXIT_REASON_ENCLS] = handle_encls,
5607 [EXIT_REASON_BUS_LOCK] = handle_bus_lock_vmexit,
5610 static const int kvm_vmx_max_exit_handlers =
5611 ARRAY_SIZE(kvm_vmx_exit_handlers);
5613 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
5614 u64 *info1, u64 *info2,
5615 u32 *intr_info, u32 *error_code)
5617 struct vcpu_vmx *vmx = to_vmx(vcpu);
5619 *reason = vmx->exit_reason.full;
5620 *info1 = vmx_get_exit_qual(vcpu);
5621 if (!(vmx->exit_reason.failed_vmentry)) {
5622 *info2 = vmx->idt_vectoring_info;
5623 *intr_info = vmx_get_intr_info(vcpu);
5624 if (is_exception_with_error_code(*intr_info))
5625 *error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5635 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5638 __free_page(vmx->pml_pg);
5643 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5645 struct vcpu_vmx *vmx = to_vmx(vcpu);
5649 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5651 /* Do nothing if PML buffer is empty */
5652 if (pml_idx == (PML_ENTITY_NUM - 1))
5655 /* PML index always points to next available PML buffer entity */
5656 if (pml_idx >= PML_ENTITY_NUM)
5661 pml_buf = page_address(vmx->pml_pg);
5662 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5665 gpa = pml_buf[pml_idx];
5666 WARN_ON(gpa & (PAGE_SIZE - 1));
5667 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5670 /* reset PML index */
5671 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5674 static void vmx_dump_sel(char *name, uint32_t sel)
5676 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5677 name, vmcs_read16(sel),
5678 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5679 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5680 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5683 static void vmx_dump_dtsel(char *name, uint32_t limit)
5685 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5686 name, vmcs_read32(limit),
5687 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5690 static void vmx_dump_msrs(char *name, struct vmx_msrs *m)
5693 struct vmx_msr_entry *e;
5695 pr_err("MSR %s:\n", name);
5696 for (i = 0, e = m->val; i < m->nr; ++i, ++e)
5697 pr_err(" %2d: msr=0x%08x value=0x%016llx\n", i, e->index, e->value);
5700 void dump_vmcs(struct kvm_vcpu *vcpu)
5702 struct vcpu_vmx *vmx = to_vmx(vcpu);
5703 u32 vmentry_ctl, vmexit_ctl;
5704 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5708 if (!dump_invalid_vmcs) {
5709 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5713 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5714 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5715 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5716 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5717 cr4 = vmcs_readl(GUEST_CR4);
5718 secondary_exec_control = 0;
5719 if (cpu_has_secondary_exec_ctrls())
5720 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5722 pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
5723 vmx->loaded_vmcs->vmcs, vcpu->arch.last_vmentry_cpu);
5724 pr_err("*** Guest State ***\n");
5725 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5726 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5727 vmcs_readl(CR0_GUEST_HOST_MASK));
5728 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5729 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5730 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5731 if (cpu_has_vmx_ept()) {
5732 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5733 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5734 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5735 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5737 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5738 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5739 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5740 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5741 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5742 vmcs_readl(GUEST_SYSENTER_ESP),
5743 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5744 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5745 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5746 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5747 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5748 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5749 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5750 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5751 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5752 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5753 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5754 efer_slot = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, MSR_EFER);
5755 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_EFER)
5756 pr_err("EFER= 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER));
5757 else if (efer_slot >= 0)
5758 pr_err("EFER= 0x%016llx (autoload)\n",
5759 vmx->msr_autoload.guest.val[efer_slot].value);
5760 else if (vmentry_ctl & VM_ENTRY_IA32E_MODE)
5761 pr_err("EFER= 0x%016llx (effective)\n",
5762 vcpu->arch.efer | (EFER_LMA | EFER_LME));
5764 pr_err("EFER= 0x%016llx (effective)\n",
5765 vcpu->arch.efer & ~(EFER_LMA | EFER_LME));
5766 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PAT)
5767 pr_err("PAT = 0x%016llx\n", vmcs_read64(GUEST_IA32_PAT));
5768 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5769 vmcs_read64(GUEST_IA32_DEBUGCTL),
5770 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5771 if (cpu_has_load_perf_global_ctrl() &&
5772 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5773 pr_err("PerfGlobCtl = 0x%016llx\n",
5774 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5775 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5776 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5777 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5778 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5779 vmcs_read32(GUEST_ACTIVITY_STATE));
5780 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5781 pr_err("InterruptStatus = %04x\n",
5782 vmcs_read16(GUEST_INTR_STATUS));
5783 if (vmcs_read32(VM_ENTRY_MSR_LOAD_COUNT) > 0)
5784 vmx_dump_msrs("guest autoload", &vmx->msr_autoload.guest);
5785 if (vmcs_read32(VM_EXIT_MSR_STORE_COUNT) > 0)
5786 vmx_dump_msrs("guest autostore", &vmx->msr_autostore.guest);
5788 pr_err("*** Host State ***\n");
5789 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5790 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5791 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5792 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5793 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5794 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5795 vmcs_read16(HOST_TR_SELECTOR));
5796 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5797 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5798 vmcs_readl(HOST_TR_BASE));
5799 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5800 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5801 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5802 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5803 vmcs_readl(HOST_CR4));
5804 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5805 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5806 vmcs_read32(HOST_IA32_SYSENTER_CS),
5807 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5808 if (vmexit_ctl & VM_EXIT_LOAD_IA32_EFER)
5809 pr_err("EFER= 0x%016llx\n", vmcs_read64(HOST_IA32_EFER));
5810 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PAT)
5811 pr_err("PAT = 0x%016llx\n", vmcs_read64(HOST_IA32_PAT));
5812 if (cpu_has_load_perf_global_ctrl() &&
5813 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5814 pr_err("PerfGlobCtl = 0x%016llx\n",
5815 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5816 if (vmcs_read32(VM_EXIT_MSR_LOAD_COUNT) > 0)
5817 vmx_dump_msrs("host autoload", &vmx->msr_autoload.host);
5819 pr_err("*** Control State ***\n");
5820 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5821 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5822 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5823 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5824 vmcs_read32(EXCEPTION_BITMAP),
5825 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5826 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5827 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5828 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5829 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5830 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5831 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5832 vmcs_read32(VM_EXIT_INTR_INFO),
5833 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5834 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5835 pr_err(" reason=%08x qualification=%016lx\n",
5836 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5837 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5838 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5839 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5840 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5841 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5842 pr_err("TSC Multiplier = 0x%016llx\n",
5843 vmcs_read64(TSC_MULTIPLIER));
5844 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5845 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5846 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5847 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5849 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5850 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5851 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5852 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5854 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5855 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5856 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5857 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5858 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5859 pr_err("PLE Gap=%08x Window=%08x\n",
5860 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5861 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5862 pr_err("Virtual processor ID = 0x%04x\n",
5863 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5867 * The guest has exited. See if we can fix it or if we need userspace
5870 static int __vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5872 struct vcpu_vmx *vmx = to_vmx(vcpu);
5873 union vmx_exit_reason exit_reason = vmx->exit_reason;
5874 u32 vectoring_info = vmx->idt_vectoring_info;
5875 u16 exit_handler_index;
5878 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5879 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5880 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5881 * mode as if vcpus is in root mode, the PML buffer must has been
5882 * flushed already. Note, PML is never enabled in hardware while
5885 if (enable_pml && !is_guest_mode(vcpu))
5886 vmx_flush_pml_buffer(vcpu);
5889 * We should never reach this point with a pending nested VM-Enter, and
5890 * more specifically emulation of L2 due to invalid guest state (see
5891 * below) should never happen as that means we incorrectly allowed a
5892 * nested VM-Enter with an invalid vmcs12.
5894 if (KVM_BUG_ON(vmx->nested.nested_run_pending, vcpu->kvm))
5897 /* If guest state is invalid, start emulating */
5898 if (vmx->emulation_required)
5899 return handle_invalid_guest_state(vcpu);
5901 if (is_guest_mode(vcpu)) {
5903 * PML is never enabled when running L2, bail immediately if a
5904 * PML full exit occurs as something is horribly wrong.
5906 if (exit_reason.basic == EXIT_REASON_PML_FULL)
5907 goto unexpected_vmexit;
5910 * The host physical addresses of some pages of guest memory
5911 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5912 * Page). The CPU may write to these pages via their host
5913 * physical address while L2 is running, bypassing any
5914 * address-translation-based dirty tracking (e.g. EPT write
5917 * Mark them dirty on every exit from L2 to prevent them from
5918 * getting out of sync with dirty tracking.
5920 nested_mark_vmcs12_pages_dirty(vcpu);
5922 if (nested_vmx_reflect_vmexit(vcpu))
5926 if (exit_reason.failed_vmentry) {
5928 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5929 vcpu->run->fail_entry.hardware_entry_failure_reason
5931 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5935 if (unlikely(vmx->fail)) {
5937 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5938 vcpu->run->fail_entry.hardware_entry_failure_reason
5939 = vmcs_read32(VM_INSTRUCTION_ERROR);
5940 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5946 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5947 * delivery event since it indicates guest is accessing MMIO.
5948 * The vm-exit can be triggered again after return to guest that
5949 * will cause infinite loop.
5951 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5952 (exit_reason.basic != EXIT_REASON_EXCEPTION_NMI &&
5953 exit_reason.basic != EXIT_REASON_EPT_VIOLATION &&
5954 exit_reason.basic != EXIT_REASON_PML_FULL &&
5955 exit_reason.basic != EXIT_REASON_APIC_ACCESS &&
5956 exit_reason.basic != EXIT_REASON_TASK_SWITCH)) {
5959 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5960 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5961 vcpu->run->internal.data[0] = vectoring_info;
5962 vcpu->run->internal.data[1] = exit_reason.full;
5963 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5964 if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG) {
5965 vcpu->run->internal.data[ndata++] =
5966 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5968 vcpu->run->internal.data[ndata++] = vcpu->arch.last_vmentry_cpu;
5969 vcpu->run->internal.ndata = ndata;
5973 if (unlikely(!enable_vnmi &&
5974 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5975 if (!vmx_interrupt_blocked(vcpu)) {
5976 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5977 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5978 vcpu->arch.nmi_pending) {
5980 * This CPU don't support us in finding the end of an
5981 * NMI-blocked window if the guest runs with IRQs
5982 * disabled. So we pull the trigger after 1 s of
5983 * futile waiting, but inform the user about this.
5985 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5986 "state on VCPU %d after 1 s timeout\n",
5987 __func__, vcpu->vcpu_id);
5988 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5992 if (exit_fastpath != EXIT_FASTPATH_NONE)
5995 if (exit_reason.basic >= kvm_vmx_max_exit_handlers)
5996 goto unexpected_vmexit;
5997 #ifdef CONFIG_RETPOLINE
5998 if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
5999 return kvm_emulate_wrmsr(vcpu);
6000 else if (exit_reason.basic == EXIT_REASON_PREEMPTION_TIMER)
6001 return handle_preemption_timer(vcpu);
6002 else if (exit_reason.basic == EXIT_REASON_INTERRUPT_WINDOW)
6003 return handle_interrupt_window(vcpu);
6004 else if (exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6005 return handle_external_interrupt(vcpu);
6006 else if (exit_reason.basic == EXIT_REASON_HLT)
6007 return kvm_emulate_halt(vcpu);
6008 else if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG)
6009 return handle_ept_misconfig(vcpu);
6012 exit_handler_index = array_index_nospec((u16)exit_reason.basic,
6013 kvm_vmx_max_exit_handlers);
6014 if (!kvm_vmx_exit_handlers[exit_handler_index])
6015 goto unexpected_vmexit;
6017 return kvm_vmx_exit_handlers[exit_handler_index](vcpu);
6020 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
6023 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6024 vcpu->run->internal.suberror =
6025 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6026 vcpu->run->internal.ndata = 2;
6027 vcpu->run->internal.data[0] = exit_reason.full;
6028 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6032 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6034 int ret = __vmx_handle_exit(vcpu, exit_fastpath);
6037 * Exit to user space when bus lock detected to inform that there is
6038 * a bus lock in guest.
6040 if (to_vmx(vcpu)->exit_reason.bus_lock_detected) {
6042 vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
6044 vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
6051 * Software based L1D cache flush which is used when microcode providing
6052 * the cache control MSR is not loaded.
6054 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6055 * flush it is required to read in 64 KiB because the replacement algorithm
6056 * is not exactly LRU. This could be sized at runtime via topology
6057 * information but as all relevant affected CPUs have 32KiB L1D cache size
6058 * there is no point in doing so.
6060 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6062 int size = PAGE_SIZE << L1D_CACHE_ORDER;
6065 * This code is only executed when the the flush mode is 'cond' or
6068 if (static_branch_likely(&vmx_l1d_flush_cond)) {
6072 * Clear the per-vcpu flush bit, it gets set again
6073 * either from vcpu_run() or from one of the unsafe
6076 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6077 vcpu->arch.l1tf_flush_l1d = false;
6080 * Clear the per-cpu flush bit, it gets set again from
6081 * the interrupt handlers.
6083 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6084 kvm_clear_cpu_l1tf_flush_l1d();
6090 vcpu->stat.l1d_flush++;
6092 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6093 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6098 /* First ensure the pages are in the TLB */
6099 "xorl %%eax, %%eax\n"
6100 ".Lpopulate_tlb:\n\t"
6101 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6102 "addl $4096, %%eax\n\t"
6103 "cmpl %%eax, %[size]\n\t"
6104 "jne .Lpopulate_tlb\n\t"
6105 "xorl %%eax, %%eax\n\t"
6107 /* Now fill the cache */
6108 "xorl %%eax, %%eax\n"
6110 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6111 "addl $64, %%eax\n\t"
6112 "cmpl %%eax, %[size]\n\t"
6113 "jne .Lfill_cache\n\t"
6115 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6117 : "eax", "ebx", "ecx", "edx");
6120 static void vmx_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6122 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6125 if (is_guest_mode(vcpu) &&
6126 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6129 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6130 if (is_guest_mode(vcpu))
6131 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6133 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6136 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6138 struct vcpu_vmx *vmx = to_vmx(vcpu);
6139 u32 sec_exec_control;
6141 if (!lapic_in_kernel(vcpu))
6144 if (!flexpriority_enabled &&
6145 !cpu_has_vmx_virtualize_x2apic_mode())
6148 /* Postpone execution until vmcs01 is the current VMCS. */
6149 if (is_guest_mode(vcpu)) {
6150 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6154 sec_exec_control = secondary_exec_controls_get(vmx);
6155 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6156 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6158 switch (kvm_get_apic_mode(vcpu)) {
6159 case LAPIC_MODE_INVALID:
6160 WARN_ONCE(true, "Invalid local APIC state");
6162 case LAPIC_MODE_DISABLED:
6164 case LAPIC_MODE_XAPIC:
6165 if (flexpriority_enabled) {
6167 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6168 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6171 * Flush the TLB, reloading the APIC access page will
6172 * only do so if its physical address has changed, but
6173 * the guest may have inserted a non-APIC mapping into
6174 * the TLB while the APIC access page was disabled.
6176 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6179 case LAPIC_MODE_X2APIC:
6180 if (cpu_has_vmx_virtualize_x2apic_mode())
6182 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6185 secondary_exec_controls_set(vmx, sec_exec_control);
6187 vmx_update_msr_bitmap_x2apic(vcpu);
6190 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6194 /* Defer reload until vmcs01 is the current VMCS. */
6195 if (is_guest_mode(vcpu)) {
6196 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6200 if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6201 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6204 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6205 if (is_error_page(page))
6208 vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6209 vmx_flush_tlb_current(vcpu);
6212 * Do not pin apic access page in memory, the MMU notifier
6213 * will call us again if it is migrated or swapped out.
6218 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6226 status = vmcs_read16(GUEST_INTR_STATUS);
6228 if (max_isr != old) {
6230 status |= max_isr << 8;
6231 vmcs_write16(GUEST_INTR_STATUS, status);
6235 static void vmx_set_rvi(int vector)
6243 status = vmcs_read16(GUEST_INTR_STATUS);
6244 old = (u8)status & 0xff;
6245 if ((u8)vector != old) {
6247 status |= (u8)vector;
6248 vmcs_write16(GUEST_INTR_STATUS, status);
6252 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6255 * When running L2, updating RVI is only relevant when
6256 * vmcs12 virtual-interrupt-delivery enabled.
6257 * However, it can be enabled only when L1 also
6258 * intercepts external-interrupts and in that case
6259 * we should not update vmcs02 RVI but instead intercept
6260 * interrupt. Therefore, do nothing when running L2.
6262 if (!is_guest_mode(vcpu))
6263 vmx_set_rvi(max_irr);
6266 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6268 struct vcpu_vmx *vmx = to_vmx(vcpu);
6270 bool got_posted_interrupt;
6272 if (KVM_BUG_ON(!enable_apicv, vcpu->kvm))
6275 if (pi_test_on(&vmx->pi_desc)) {
6276 pi_clear_on(&vmx->pi_desc);
6278 * IOMMU can write to PID.ON, so the barrier matters even on UP.
6279 * But on x86 this is just a compiler barrier anyway.
6281 smp_mb__after_atomic();
6282 got_posted_interrupt =
6283 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6285 max_irr = kvm_lapic_find_highest_irr(vcpu);
6286 got_posted_interrupt = false;
6290 * Newly recognized interrupts are injected via either virtual interrupt
6291 * delivery (RVI) or KVM_REQ_EVENT. Virtual interrupt delivery is
6292 * disabled in two cases:
6294 * 1) If L2 is running and the vCPU has a new pending interrupt. If L1
6295 * wants to exit on interrupts, KVM_REQ_EVENT is needed to synthesize a
6296 * VM-Exit to L1. If L1 doesn't want to exit, the interrupt is injected
6297 * into L2, but KVM doesn't use virtual interrupt delivery to inject
6298 * interrupts into L2, and so KVM_REQ_EVENT is again needed.
6300 * 2) If APICv is disabled for this vCPU, assigned devices may still
6301 * attempt to post interrupts. The posted interrupt vector will cause
6302 * a VM-Exit and the subsequent entry will call sync_pir_to_irr.
6304 if (!is_guest_mode(vcpu) && kvm_vcpu_apicv_active(vcpu))
6305 vmx_set_rvi(max_irr);
6306 else if (got_posted_interrupt)
6307 kvm_make_request(KVM_REQ_EVENT, vcpu);
6312 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6314 if (!kvm_vcpu_apicv_active(vcpu))
6317 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6318 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6319 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6320 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6323 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6325 struct vcpu_vmx *vmx = to_vmx(vcpu);
6327 pi_clear_on(&vmx->pi_desc);
6328 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6331 void vmx_do_interrupt_nmi_irqoff(unsigned long entry);
6333 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu,
6334 unsigned long entry)
6336 kvm_before_interrupt(vcpu);
6337 vmx_do_interrupt_nmi_irqoff(entry);
6338 kvm_after_interrupt(vcpu);
6341 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6343 const unsigned long nmi_entry = (unsigned long)asm_exc_nmi_noist;
6344 u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6346 /* if exit due to PF check for async PF */
6347 if (is_page_fault(intr_info))
6348 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6349 /* Handle machine checks before interrupts are enabled */
6350 else if (is_machine_check(intr_info))
6351 kvm_machine_check();
6352 /* We need to handle NMIs before interrupts are enabled */
6353 else if (is_nmi(intr_info))
6354 handle_interrupt_nmi_irqoff(&vmx->vcpu, nmi_entry);
6357 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6359 u32 intr_info = vmx_get_intr_info(vcpu);
6360 unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK;
6361 gate_desc *desc = (gate_desc *)host_idt_base + vector;
6363 if (KVM_BUG(!is_external_intr(intr_info), vcpu->kvm,
6364 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6367 handle_interrupt_nmi_irqoff(vcpu, gate_offset(desc));
6370 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6372 struct vcpu_vmx *vmx = to_vmx(vcpu);
6374 if (vmx->emulation_required)
6377 if (vmx->exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6378 handle_external_interrupt_irqoff(vcpu);
6379 else if (vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI)
6380 handle_exception_nmi_irqoff(vmx);
6384 * The kvm parameter can be NULL (module initialization, or invocation before
6385 * VM creation). Be sure to check the kvm parameter before using it.
6387 static bool vmx_has_emulated_msr(struct kvm *kvm, u32 index)
6390 case MSR_IA32_SMBASE:
6392 * We cannot do SMM unless we can run the guest in big
6395 return enable_unrestricted_guest || emulate_invalid_guest_state;
6396 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6398 case MSR_AMD64_VIRT_SPEC_CTRL:
6399 case MSR_AMD64_TSC_RATIO:
6400 /* This is AMD only. */
6407 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6412 bool idtv_info_valid;
6414 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6417 if (vmx->loaded_vmcs->nmi_known_unmasked)
6420 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6421 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6422 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6424 * SDM 3: 27.7.1.2 (September 2008)
6425 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6426 * a guest IRET fault.
6427 * SDM 3: 23.2.2 (September 2008)
6428 * Bit 12 is undefined in any of the following cases:
6429 * If the VM exit sets the valid bit in the IDT-vectoring
6430 * information field.
6431 * If the VM exit is due to a double fault.
6433 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6434 vector != DF_VECTOR && !idtv_info_valid)
6435 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6436 GUEST_INTR_STATE_NMI);
6438 vmx->loaded_vmcs->nmi_known_unmasked =
6439 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6440 & GUEST_INTR_STATE_NMI);
6441 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6442 vmx->loaded_vmcs->vnmi_blocked_time +=
6443 ktime_to_ns(ktime_sub(ktime_get(),
6444 vmx->loaded_vmcs->entry_time));
6447 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6448 u32 idt_vectoring_info,
6449 int instr_len_field,
6450 int error_code_field)
6454 bool idtv_info_valid;
6456 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6458 vcpu->arch.nmi_injected = false;
6459 kvm_clear_exception_queue(vcpu);
6460 kvm_clear_interrupt_queue(vcpu);
6462 if (!idtv_info_valid)
6465 kvm_make_request(KVM_REQ_EVENT, vcpu);
6467 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6468 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6471 case INTR_TYPE_NMI_INTR:
6472 vcpu->arch.nmi_injected = true;
6474 * SDM 3: 27.7.1.2 (September 2008)
6475 * Clear bit "block by NMI" before VM entry if a NMI
6478 vmx_set_nmi_mask(vcpu, false);
6480 case INTR_TYPE_SOFT_EXCEPTION:
6481 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6483 case INTR_TYPE_HARD_EXCEPTION:
6484 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6485 u32 err = vmcs_read32(error_code_field);
6486 kvm_requeue_exception_e(vcpu, vector, err);
6488 kvm_requeue_exception(vcpu, vector);
6490 case INTR_TYPE_SOFT_INTR:
6491 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6493 case INTR_TYPE_EXT_INTR:
6494 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6501 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6503 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6504 VM_EXIT_INSTRUCTION_LEN,
6505 IDT_VECTORING_ERROR_CODE);
6508 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6510 __vmx_complete_interrupts(vcpu,
6511 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6512 VM_ENTRY_INSTRUCTION_LEN,
6513 VM_ENTRY_EXCEPTION_ERROR_CODE);
6515 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6518 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6521 struct perf_guest_switch_msr *msrs;
6523 /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
6524 msrs = perf_guest_get_msrs(&nr_msrs);
6528 for (i = 0; i < nr_msrs; i++)
6529 if (msrs[i].host == msrs[i].guest)
6530 clear_atomic_switch_msr(vmx, msrs[i].msr);
6532 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6533 msrs[i].host, false);
6536 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6538 struct vcpu_vmx *vmx = to_vmx(vcpu);
6542 if (vmx->req_immediate_exit) {
6543 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6544 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6545 } else if (vmx->hv_deadline_tsc != -1) {
6547 if (vmx->hv_deadline_tsc > tscl)
6548 /* set_hv_timer ensures the delta fits in 32-bits */
6549 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6550 cpu_preemption_timer_multi);
6554 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6555 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6556 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6557 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6558 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6562 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6564 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6565 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6566 vmcs_writel(HOST_RSP, host_rsp);
6570 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6572 switch (to_vmx(vcpu)->exit_reason.basic) {
6573 case EXIT_REASON_MSR_WRITE:
6574 return handle_fastpath_set_msr_irqoff(vcpu);
6575 case EXIT_REASON_PREEMPTION_TIMER:
6576 return handle_fastpath_preemption_timer(vcpu);
6578 return EXIT_FASTPATH_NONE;
6582 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6583 struct vcpu_vmx *vmx)
6585 kvm_guest_enter_irqoff();
6587 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6588 if (static_branch_unlikely(&vmx_l1d_should_flush))
6589 vmx_l1d_flush(vcpu);
6590 else if (static_branch_unlikely(&mds_user_clear))
6591 mds_clear_cpu_buffers();
6593 if (vcpu->arch.cr2 != native_read_cr2())
6594 native_write_cr2(vcpu->arch.cr2);
6596 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6597 vmx->loaded_vmcs->launched);
6599 vcpu->arch.cr2 = native_read_cr2();
6601 kvm_guest_exit_irqoff();
6604 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6606 struct vcpu_vmx *vmx = to_vmx(vcpu);
6607 unsigned long cr3, cr4;
6609 /* Record the guest's net vcpu time for enforced NMI injections. */
6610 if (unlikely(!enable_vnmi &&
6611 vmx->loaded_vmcs->soft_vnmi_blocked))
6612 vmx->loaded_vmcs->entry_time = ktime_get();
6615 * Don't enter VMX if guest state is invalid, let the exit handler
6616 * start emulation until we arrive back to a valid state. Synthesize a
6617 * consistency check VM-Exit due to invalid guest state and bail.
6619 if (unlikely(vmx->emulation_required)) {
6621 /* We don't emulate invalid state of a nested guest */
6622 vmx->fail = is_guest_mode(vcpu);
6624 vmx->exit_reason.full = EXIT_REASON_INVALID_STATE;
6625 vmx->exit_reason.failed_vmentry = 1;
6626 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
6627 vmx->exit_qualification = ENTRY_FAIL_DEFAULT;
6628 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
6629 vmx->exit_intr_info = 0;
6630 return EXIT_FASTPATH_NONE;
6633 trace_kvm_entry(vcpu);
6635 if (vmx->ple_window_dirty) {
6636 vmx->ple_window_dirty = false;
6637 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6641 * We did this in prepare_switch_to_guest, because it needs to
6642 * be within srcu_read_lock.
6644 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6646 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6647 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6648 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6649 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6651 cr3 = __get_current_cr3_fast();
6652 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6653 vmcs_writel(HOST_CR3, cr3);
6654 vmx->loaded_vmcs->host_state.cr3 = cr3;
6657 cr4 = cr4_read_shadow();
6658 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6659 vmcs_writel(HOST_CR4, cr4);
6660 vmx->loaded_vmcs->host_state.cr4 = cr4;
6663 /* When KVM_DEBUGREG_WONT_EXIT, dr6 is accessible in guest. */
6664 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
6665 set_debugreg(vcpu->arch.dr6, 6);
6667 /* When single-stepping over STI and MOV SS, we must clear the
6668 * corresponding interruptibility bits in the guest state. Otherwise
6669 * vmentry fails as it then expects bit 14 (BS) in pending debug
6670 * exceptions being set, but that's not correct for the guest debugging
6672 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6673 vmx_set_interrupt_shadow(vcpu, 0);
6675 kvm_load_guest_xsave_state(vcpu);
6677 pt_guest_enter(vmx);
6679 atomic_switch_perf_msrs(vmx);
6680 if (intel_pmu_lbr_is_enabled(vcpu))
6681 vmx_passthrough_lbr_msrs(vcpu);
6683 if (enable_preemption_timer)
6684 vmx_update_hv_timer(vcpu);
6686 kvm_wait_lapic_expire(vcpu);
6689 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6690 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6691 * is no need to worry about the conditional branch over the wrmsr
6692 * being speculatively taken.
6694 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6696 /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6697 vmx_vcpu_enter_exit(vcpu, vmx);
6700 * We do not use IBRS in the kernel. If this vCPU has used the
6701 * SPEC_CTRL MSR it may have left it on; save the value and
6702 * turn it off. This is much more efficient than blindly adding
6703 * it to the atomic save/restore list. Especially as the former
6704 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6706 * For non-nested case:
6707 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6711 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6714 if (unlikely(!msr_write_intercepted(vmx, MSR_IA32_SPEC_CTRL)))
6715 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6717 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6719 /* All fields are clean at this point */
6720 if (static_branch_unlikely(&enable_evmcs)) {
6721 current_evmcs->hv_clean_fields |=
6722 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6724 current_evmcs->hv_vp_id = kvm_hv_get_vpindex(vcpu);
6727 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6728 if (vmx->host_debugctlmsr)
6729 update_debugctlmsr(vmx->host_debugctlmsr);
6731 #ifndef CONFIG_X86_64
6733 * The sysexit path does not restore ds/es, so we must set them to
6734 * a reasonable value ourselves.
6736 * We can't defer this to vmx_prepare_switch_to_host() since that
6737 * function may be executed in interrupt context, which saves and
6738 * restore segments around it, nullifying its effect.
6740 loadsegment(ds, __USER_DS);
6741 loadsegment(es, __USER_DS);
6744 vmx_register_cache_reset(vcpu);
6748 kvm_load_host_xsave_state(vcpu);
6750 if (is_guest_mode(vcpu)) {
6752 * Track VMLAUNCH/VMRESUME that have made past guest state
6755 if (vmx->nested.nested_run_pending &&
6756 !vmx->exit_reason.failed_vmentry)
6757 ++vcpu->stat.nested_run;
6759 vmx->nested.nested_run_pending = 0;
6762 vmx->idt_vectoring_info = 0;
6764 if (unlikely(vmx->fail)) {
6765 vmx->exit_reason.full = 0xdead;
6766 return EXIT_FASTPATH_NONE;
6769 vmx->exit_reason.full = vmcs_read32(VM_EXIT_REASON);
6770 if (unlikely((u16)vmx->exit_reason.basic == EXIT_REASON_MCE_DURING_VMENTRY))
6771 kvm_machine_check();
6773 if (likely(!vmx->exit_reason.failed_vmentry))
6774 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6776 trace_kvm_exit(vcpu, KVM_ISA_VMX);
6778 if (unlikely(vmx->exit_reason.failed_vmentry))
6779 return EXIT_FASTPATH_NONE;
6781 vmx->loaded_vmcs->launched = 1;
6783 vmx_recover_nmi_blocking(vmx);
6784 vmx_complete_interrupts(vmx);
6786 if (is_guest_mode(vcpu))
6787 return EXIT_FASTPATH_NONE;
6789 return vmx_exit_handlers_fastpath(vcpu);
6792 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6794 struct vcpu_vmx *vmx = to_vmx(vcpu);
6797 vmx_destroy_pml_buffer(vmx);
6798 free_vpid(vmx->vpid);
6799 nested_vmx_free_vcpu(vcpu);
6800 free_loaded_vmcs(vmx->loaded_vmcs);
6803 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6805 struct vmx_uret_msr *tsx_ctrl;
6806 struct vcpu_vmx *vmx;
6809 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6814 vmx->vpid = allocate_vpid();
6817 * If PML is turned on, failure on enabling PML just results in failure
6818 * of creating the vcpu, therefore we can simplify PML logic (by
6819 * avoiding dealing with cases, such as enabling PML partially on vcpus
6820 * for the guest), etc.
6823 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6828 for (i = 0; i < kvm_nr_uret_msrs; ++i)
6829 vmx->guest_uret_msrs[i].mask = -1ull;
6830 if (boot_cpu_has(X86_FEATURE_RTM)) {
6832 * TSX_CTRL_CPUID_CLEAR is handled in the CPUID interception.
6833 * Keep the host value unchanged to avoid changing CPUID bits
6834 * under the host kernel's feet.
6836 tsx_ctrl = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
6838 tsx_ctrl->mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6841 err = alloc_loaded_vmcs(&vmx->vmcs01);
6845 /* The MSR bitmap starts with all ones */
6846 bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6847 bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6849 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
6850 #ifdef CONFIG_X86_64
6851 vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
6852 vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
6853 vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6855 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6856 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6857 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6858 if (kvm_cstate_in_guest(vcpu->kvm)) {
6859 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
6860 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6861 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6862 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6865 vmx->loaded_vmcs = &vmx->vmcs01;
6867 if (cpu_need_virtualize_apic_accesses(vcpu)) {
6868 err = alloc_apic_access_page(vcpu->kvm);
6873 if (enable_ept && !enable_unrestricted_guest) {
6874 err = init_rmode_identity_map(vcpu->kvm);
6882 free_loaded_vmcs(vmx->loaded_vmcs);
6884 vmx_destroy_pml_buffer(vmx);
6886 free_vpid(vmx->vpid);
6890 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6891 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6893 static int vmx_vm_init(struct kvm *kvm)
6896 kvm->arch.pause_in_guest = true;
6898 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6899 switch (l1tf_mitigation) {
6900 case L1TF_MITIGATION_OFF:
6901 case L1TF_MITIGATION_FLUSH_NOWARN:
6902 /* 'I explicitly don't care' is set */
6904 case L1TF_MITIGATION_FLUSH:
6905 case L1TF_MITIGATION_FLUSH_NOSMT:
6906 case L1TF_MITIGATION_FULL:
6908 * Warn upon starting the first VM in a potentially
6909 * insecure environment.
6911 if (sched_smt_active())
6912 pr_warn_once(L1TF_MSG_SMT);
6913 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6914 pr_warn_once(L1TF_MSG_L1D);
6916 case L1TF_MITIGATION_FULL_FORCE:
6917 /* Flush is enforced */
6924 static int __init vmx_check_processor_compat(void)
6926 struct vmcs_config vmcs_conf;
6927 struct vmx_capability vmx_cap;
6929 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6930 !this_cpu_has(X86_FEATURE_VMX)) {
6931 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6935 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6938 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6939 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6940 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6941 smp_processor_id());
6947 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6951 /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6952 * memory aliases with conflicting memory types and sometimes MCEs.
6953 * We have to be careful as to what are honored and when.
6955 * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to
6956 * UC. The effective memory type is UC or WC depending on guest PAT.
6957 * This was historically the source of MCEs and we want to be
6960 * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6961 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The
6962 * EPT memory type is set to WB. The effective memory type is forced
6965 * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The
6966 * EPT memory type is used to emulate guest CD/MTRR.
6970 return MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6972 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm))
6973 return (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT) | VMX_EPT_IPAT_BIT;
6975 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6976 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6977 cache = MTRR_TYPE_WRBACK;
6979 cache = MTRR_TYPE_UNCACHABLE;
6981 return (cache << VMX_EPT_MT_EPTE_SHIFT) | VMX_EPT_IPAT_BIT;
6984 return kvm_mtrr_get_guest_memory_type(vcpu, gfn) << VMX_EPT_MT_EPTE_SHIFT;
6987 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx, u32 new_ctl)
6990 * These bits in the secondary execution controls field
6991 * are dynamic, the others are mostly based on the hypervisor
6992 * architecture and the guest's CPUID. Do not touch the
6996 SECONDARY_EXEC_SHADOW_VMCS |
6997 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6998 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6999 SECONDARY_EXEC_DESC;
7001 u32 cur_ctl = secondary_exec_controls_get(vmx);
7003 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7007 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7008 * (indicating "allowed-1") if they are supported in the guest's CPUID.
7010 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7012 struct vcpu_vmx *vmx = to_vmx(vcpu);
7013 struct kvm_cpuid_entry2 *entry;
7015 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7016 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7018 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
7019 if (entry && (entry->_reg & (_cpuid_mask))) \
7020 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
7023 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7024 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME));
7025 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME));
7026 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC));
7027 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE));
7028 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE));
7029 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE));
7030 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE));
7031 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE));
7032 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR));
7033 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7034 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX));
7035 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX));
7036 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID));
7037 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE));
7039 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7040 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE));
7041 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP));
7042 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP));
7043 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU));
7044 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP));
7045 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57));
7047 #undef cr4_fixed1_update
7050 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7052 struct vcpu_vmx *vmx = to_vmx(vcpu);
7054 if (kvm_mpx_supported()) {
7055 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7058 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7059 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7061 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7062 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7067 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7069 struct vcpu_vmx *vmx = to_vmx(vcpu);
7070 struct kvm_cpuid_entry2 *best = NULL;
7073 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7074 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7077 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7078 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7079 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7080 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7083 /* Get the number of configurable Address Ranges for filtering */
7084 vmx->pt_desc.num_address_ranges = intel_pt_validate_cap(vmx->pt_desc.caps,
7085 PT_CAP_num_address_ranges);
7087 /* Initialize and clear the no dependency bits */
7088 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7089 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC |
7090 RTIT_CTL_BRANCH_EN);
7093 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7094 * will inject an #GP
7096 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7097 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7100 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7101 * PSBFreq can be set
7103 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7104 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7105 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7108 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn and MTCFreq can be set
7110 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7111 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7112 RTIT_CTL_MTC_RANGE);
7114 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7115 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7116 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7119 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7120 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7121 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7123 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7124 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7125 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7127 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabricEn can be set */
7128 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7129 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7131 /* unmask address range configure area */
7132 for (i = 0; i < vmx->pt_desc.num_address_ranges; i++)
7133 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7136 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7138 struct vcpu_vmx *vmx = to_vmx(vcpu);
7140 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7141 vcpu->arch.xsaves_enabled = false;
7143 vmx_setup_uret_msrs(vmx);
7145 if (cpu_has_secondary_exec_ctrls())
7146 vmcs_set_secondary_exec_control(vmx,
7147 vmx_secondary_exec_control(vmx));
7149 if (nested_vmx_allowed(vcpu))
7150 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7151 FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7152 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7154 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7155 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7156 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7158 if (nested_vmx_allowed(vcpu)) {
7159 nested_vmx_cr_fixed1_bits_update(vcpu);
7160 nested_vmx_entry_exit_ctls_update(vcpu);
7163 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7164 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7165 update_intel_pt_cfg(vcpu);
7167 if (boot_cpu_has(X86_FEATURE_RTM)) {
7168 struct vmx_uret_msr *msr;
7169 msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
7171 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7172 vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7176 set_cr4_guest_host_mask(vmx);
7178 vmx_write_encls_bitmap(vcpu, NULL);
7179 if (guest_cpuid_has(vcpu, X86_FEATURE_SGX))
7180 vmx->msr_ia32_feature_control_valid_bits |= FEAT_CTL_SGX_ENABLED;
7182 vmx->msr_ia32_feature_control_valid_bits &= ~FEAT_CTL_SGX_ENABLED;
7184 if (guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
7185 vmx->msr_ia32_feature_control_valid_bits |=
7186 FEAT_CTL_SGX_LC_ENABLED;
7188 vmx->msr_ia32_feature_control_valid_bits &=
7189 ~FEAT_CTL_SGX_LC_ENABLED;
7191 /* Refresh #PF interception to account for MAXPHYADDR changes. */
7192 vmx_update_exception_bitmap(vcpu);
7195 static __init void vmx_set_cpu_caps(void)
7201 kvm_cpu_cap_set(X86_FEATURE_VMX);
7204 if (kvm_mpx_supported())
7205 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7206 if (!cpu_has_vmx_invpcid())
7207 kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
7208 if (vmx_pt_mode_is_host_guest())
7209 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7212 kvm_cpu_cap_clear(X86_FEATURE_SGX);
7213 kvm_cpu_cap_clear(X86_FEATURE_SGX_LC);
7214 kvm_cpu_cap_clear(X86_FEATURE_SGX1);
7215 kvm_cpu_cap_clear(X86_FEATURE_SGX2);
7218 if (vmx_umip_emulated())
7219 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7223 if (!cpu_has_vmx_xsaves())
7224 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7226 /* CPUID 0x80000001 and 0x7 (RDPID) */
7227 if (!cpu_has_vmx_rdtscp()) {
7228 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7229 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
7232 if (cpu_has_vmx_waitpkg())
7233 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7236 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7238 to_vmx(vcpu)->req_immediate_exit = true;
7241 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7242 struct x86_instruction_info *info)
7244 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7245 unsigned short port;
7249 if (info->intercept == x86_intercept_in ||
7250 info->intercept == x86_intercept_ins) {
7251 port = info->src_val;
7252 size = info->dst_bytes;
7254 port = info->dst_val;
7255 size = info->src_bytes;
7259 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7260 * VM-exits depend on the 'unconditional IO exiting' VM-execution
7263 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7265 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7266 intercept = nested_cpu_has(vmcs12,
7267 CPU_BASED_UNCOND_IO_EXITING);
7269 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7271 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7272 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7275 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7276 struct x86_instruction_info *info,
7277 enum x86_intercept_stage stage,
7278 struct x86_exception *exception)
7280 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7282 switch (info->intercept) {
7284 * RDPID causes #UD if disabled through secondary execution controls.
7285 * Because it is marked as EmulateOnUD, we need to intercept it here.
7286 * Note, RDPID is hidden behind ENABLE_RDTSCP.
7288 case x86_intercept_rdpid:
7289 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) {
7290 exception->vector = UD_VECTOR;
7291 exception->error_code_valid = false;
7292 return X86EMUL_PROPAGATE_FAULT;
7296 case x86_intercept_in:
7297 case x86_intercept_ins:
7298 case x86_intercept_out:
7299 case x86_intercept_outs:
7300 return vmx_check_intercept_io(vcpu, info);
7302 case x86_intercept_lgdt:
7303 case x86_intercept_lidt:
7304 case x86_intercept_lldt:
7305 case x86_intercept_ltr:
7306 case x86_intercept_sgdt:
7307 case x86_intercept_sidt:
7308 case x86_intercept_sldt:
7309 case x86_intercept_str:
7310 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7311 return X86EMUL_CONTINUE;
7313 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7316 /* TODO: check more intercepts... */
7321 return X86EMUL_UNHANDLEABLE;
7324 #ifdef CONFIG_X86_64
7325 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7326 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7327 u64 divisor, u64 *result)
7329 u64 low = a << shift, high = a >> (64 - shift);
7331 /* To avoid the overflow on divq */
7332 if (high >= divisor)
7335 /* Low hold the result, high hold rem which is discarded */
7336 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7337 "rm" (divisor), "0" (low), "1" (high));
7343 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7346 struct vcpu_vmx *vmx;
7347 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7348 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7352 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7353 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7354 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7355 ktimer->timer_advance_ns);
7357 if (delta_tsc > lapic_timer_advance_cycles)
7358 delta_tsc -= lapic_timer_advance_cycles;
7362 /* Convert to host delta tsc if tsc scaling is enabled */
7363 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7364 delta_tsc && u64_shl_div_u64(delta_tsc,
7365 kvm_tsc_scaling_ratio_frac_bits,
7366 vcpu->arch.l1_tsc_scaling_ratio, &delta_tsc))
7370 * If the delta tsc can't fit in the 32 bit after the multi shift,
7371 * we can't use the preemption timer.
7372 * It's possible that it fits on later vmentries, but checking
7373 * on every vmentry is costly so we just use an hrtimer.
7375 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7378 vmx->hv_deadline_tsc = tscl + delta_tsc;
7379 *expired = !delta_tsc;
7383 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7385 to_vmx(vcpu)->hv_deadline_tsc = -1;
7389 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7391 if (!kvm_pause_in_guest(vcpu->kvm))
7392 shrink_ple_window(vcpu);
7395 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu)
7397 struct vcpu_vmx *vmx = to_vmx(vcpu);
7399 if (is_guest_mode(vcpu)) {
7400 vmx->nested.update_vmcs01_cpu_dirty_logging = true;
7405 * Note, cpu_dirty_logging_count can be changed concurrent with this
7406 * code, but in that case another update request will be made and so
7407 * the guest will never run with a stale PML value.
7409 if (vcpu->kvm->arch.cpu_dirty_logging_count)
7410 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7412 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7415 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7417 if (pi_pre_block(vcpu))
7420 if (kvm_lapic_hv_timer_in_use(vcpu))
7421 kvm_lapic_switch_to_sw_timer(vcpu);
7426 static void vmx_post_block(struct kvm_vcpu *vcpu)
7428 if (kvm_x86_ops.set_hv_timer)
7429 kvm_lapic_switch_to_hv_timer(vcpu);
7431 pi_post_block(vcpu);
7434 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7436 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7437 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7438 FEAT_CTL_LMCE_ENABLED;
7440 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7441 ~FEAT_CTL_LMCE_ENABLED;
7444 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7446 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7447 if (to_vmx(vcpu)->nested.nested_run_pending)
7449 return !is_smm(vcpu);
7452 static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7454 struct vcpu_vmx *vmx = to_vmx(vcpu);
7456 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7457 if (vmx->nested.smm.guest_mode)
7458 nested_vmx_vmexit(vcpu, -1, 0, 0);
7460 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7461 vmx->nested.vmxon = false;
7462 vmx_clear_hlt(vcpu);
7466 static int vmx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7468 struct vcpu_vmx *vmx = to_vmx(vcpu);
7471 if (vmx->nested.smm.vmxon) {
7472 vmx->nested.vmxon = true;
7473 vmx->nested.smm.vmxon = false;
7476 if (vmx->nested.smm.guest_mode) {
7477 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7481 vmx->nested.smm.guest_mode = false;
7486 static void vmx_enable_smi_window(struct kvm_vcpu *vcpu)
7488 /* RSM will cause a vmexit anyway. */
7491 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7493 return to_vmx(vcpu)->nested.vmxon && !is_guest_mode(vcpu);
7496 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7498 if (is_guest_mode(vcpu)) {
7499 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7501 if (hrtimer_try_to_cancel(timer) == 1)
7502 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7506 static void hardware_unsetup(void)
7508 kvm_set_posted_intr_wakeup_handler(NULL);
7511 nested_vmx_hardware_unsetup();
7516 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7518 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7519 BIT(APICV_INHIBIT_REASON_ABSENT) |
7520 BIT(APICV_INHIBIT_REASON_HYPERV) |
7521 BIT(APICV_INHIBIT_REASON_BLOCKIRQ);
7523 return supported & BIT(bit);
7526 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7527 .name = "kvm_intel",
7529 .hardware_unsetup = hardware_unsetup,
7531 .hardware_enable = hardware_enable,
7532 .hardware_disable = hardware_disable,
7533 .cpu_has_accelerated_tpr = report_flexpriority,
7534 .has_emulated_msr = vmx_has_emulated_msr,
7536 .vm_size = sizeof(struct kvm_vmx),
7537 .vm_init = vmx_vm_init,
7539 .vcpu_create = vmx_create_vcpu,
7540 .vcpu_free = vmx_free_vcpu,
7541 .vcpu_reset = vmx_vcpu_reset,
7543 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7544 .vcpu_load = vmx_vcpu_load,
7545 .vcpu_put = vmx_vcpu_put,
7547 .update_exception_bitmap = vmx_update_exception_bitmap,
7548 .get_msr_feature = vmx_get_msr_feature,
7549 .get_msr = vmx_get_msr,
7550 .set_msr = vmx_set_msr,
7551 .get_segment_base = vmx_get_segment_base,
7552 .get_segment = vmx_get_segment,
7553 .set_segment = vmx_set_segment,
7554 .get_cpl = vmx_get_cpl,
7555 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7556 .set_cr0 = vmx_set_cr0,
7557 .is_valid_cr4 = vmx_is_valid_cr4,
7558 .set_cr4 = vmx_set_cr4,
7559 .set_efer = vmx_set_efer,
7560 .get_idt = vmx_get_idt,
7561 .set_idt = vmx_set_idt,
7562 .get_gdt = vmx_get_gdt,
7563 .set_gdt = vmx_set_gdt,
7564 .set_dr7 = vmx_set_dr7,
7565 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7566 .cache_reg = vmx_cache_reg,
7567 .get_rflags = vmx_get_rflags,
7568 .set_rflags = vmx_set_rflags,
7570 .tlb_flush_all = vmx_flush_tlb_all,
7571 .tlb_flush_current = vmx_flush_tlb_current,
7572 .tlb_flush_gva = vmx_flush_tlb_gva,
7573 .tlb_flush_guest = vmx_flush_tlb_guest,
7575 .run = vmx_vcpu_run,
7576 .handle_exit = vmx_handle_exit,
7577 .skip_emulated_instruction = vmx_skip_emulated_instruction,
7578 .update_emulated_instruction = vmx_update_emulated_instruction,
7579 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7580 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7581 .patch_hypercall = vmx_patch_hypercall,
7582 .set_irq = vmx_inject_irq,
7583 .set_nmi = vmx_inject_nmi,
7584 .queue_exception = vmx_queue_exception,
7585 .cancel_injection = vmx_cancel_injection,
7586 .interrupt_allowed = vmx_interrupt_allowed,
7587 .nmi_allowed = vmx_nmi_allowed,
7588 .get_nmi_mask = vmx_get_nmi_mask,
7589 .set_nmi_mask = vmx_set_nmi_mask,
7590 .enable_nmi_window = vmx_enable_nmi_window,
7591 .enable_irq_window = vmx_enable_irq_window,
7592 .update_cr8_intercept = vmx_update_cr8_intercept,
7593 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7594 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7595 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7596 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7597 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7598 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7599 .hwapic_irr_update = vmx_hwapic_irr_update,
7600 .hwapic_isr_update = vmx_hwapic_isr_update,
7601 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7602 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7603 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7604 .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
7606 .set_tss_addr = vmx_set_tss_addr,
7607 .set_identity_map_addr = vmx_set_identity_map_addr,
7608 .get_mt_mask = vmx_get_mt_mask,
7610 .get_exit_info = vmx_get_exit_info,
7612 .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7614 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7616 .get_l2_tsc_offset = vmx_get_l2_tsc_offset,
7617 .get_l2_tsc_multiplier = vmx_get_l2_tsc_multiplier,
7618 .write_tsc_offset = vmx_write_tsc_offset,
7619 .write_tsc_multiplier = vmx_write_tsc_multiplier,
7621 .load_mmu_pgd = vmx_load_mmu_pgd,
7623 .check_intercept = vmx_check_intercept,
7624 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7626 .request_immediate_exit = vmx_request_immediate_exit,
7628 .sched_in = vmx_sched_in,
7630 .cpu_dirty_log_size = PML_ENTITY_NUM,
7631 .update_cpu_dirty_logging = vmx_update_cpu_dirty_logging,
7633 .pre_block = vmx_pre_block,
7634 .post_block = vmx_post_block,
7636 .pmu_ops = &intel_pmu_ops,
7637 .nested_ops = &vmx_nested_ops,
7639 .update_pi_irte = pi_update_irte,
7640 .start_assignment = vmx_pi_start_assignment,
7642 #ifdef CONFIG_X86_64
7643 .set_hv_timer = vmx_set_hv_timer,
7644 .cancel_hv_timer = vmx_cancel_hv_timer,
7647 .setup_mce = vmx_setup_mce,
7649 .smi_allowed = vmx_smi_allowed,
7650 .enter_smm = vmx_enter_smm,
7651 .leave_smm = vmx_leave_smm,
7652 .enable_smi_window = vmx_enable_smi_window,
7654 .can_emulate_instruction = vmx_can_emulate_instruction,
7655 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7656 .migrate_timers = vmx_migrate_timers,
7658 .msr_filter_changed = vmx_msr_filter_changed,
7659 .complete_emulated_msr = kvm_complete_insn_gp,
7661 .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector,
7664 static __init void vmx_setup_user_return_msrs(void)
7668 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
7669 * will emulate SYSCALL in legacy mode if the vendor string in guest
7670 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
7671 * support this emulation, MSR_STAR is included in the list for i386,
7672 * but is never loaded into hardware. MSR_CSTAR is also never loaded
7673 * into hardware and is here purely for emulation purposes.
7675 const u32 vmx_uret_msrs_list[] = {
7676 #ifdef CONFIG_X86_64
7677 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
7679 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
7684 BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
7686 for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
7687 kvm_add_user_return_msr(vmx_uret_msrs_list[i]);
7690 static __init int hardware_setup(void)
7692 unsigned long host_bndcfgs;
7694 int r, ept_lpage_level;
7697 host_idt_base = dt.address;
7699 vmx_setup_user_return_msrs();
7701 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7704 if (boot_cpu_has(X86_FEATURE_NX))
7705 kvm_enable_efer_bits(EFER_NX);
7707 if (boot_cpu_has(X86_FEATURE_MPX)) {
7708 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7709 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7712 if (!cpu_has_vmx_mpx())
7713 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7714 XFEATURE_MASK_BNDCSR);
7716 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7717 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7720 if (!cpu_has_vmx_ept() ||
7721 !cpu_has_vmx_ept_4levels() ||
7722 !cpu_has_vmx_ept_mt_wb() ||
7723 !cpu_has_vmx_invept_global())
7726 /* NX support is required for shadow paging. */
7727 if (!enable_ept && !boot_cpu_has(X86_FEATURE_NX)) {
7728 pr_err_ratelimited("kvm: NX (Execute Disable) not supported\n");
7732 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7733 enable_ept_ad_bits = 0;
7735 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7736 enable_unrestricted_guest = 0;
7738 if (!cpu_has_vmx_flexpriority())
7739 flexpriority_enabled = 0;
7741 if (!cpu_has_virtual_nmis())
7745 * set_apic_access_page_addr() is used to reload apic access
7746 * page upon invalidation. No need to do anything if not
7747 * using the APIC_ACCESS_ADDR VMCS field.
7749 if (!flexpriority_enabled)
7750 vmx_x86_ops.set_apic_access_page_addr = NULL;
7752 if (!cpu_has_vmx_tpr_shadow())
7753 vmx_x86_ops.update_cr8_intercept = NULL;
7755 #if IS_ENABLED(CONFIG_HYPERV)
7756 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7758 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7759 vmx_x86_ops.tlb_remote_flush_with_range =
7760 hv_remote_flush_tlb_with_range;
7764 if (!cpu_has_vmx_ple()) {
7767 ple_window_grow = 0;
7769 ple_window_shrink = 0;
7772 if (!cpu_has_vmx_apicv())
7775 vmx_x86_ops.sync_pir_to_irr = NULL;
7777 if (cpu_has_vmx_tsc_scaling()) {
7778 kvm_has_tsc_control = true;
7779 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7780 kvm_tsc_scaling_ratio_frac_bits = 48;
7783 kvm_has_bus_lock_exit = cpu_has_vmx_bus_lock_detection();
7785 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7788 kvm_mmu_set_ept_masks(enable_ept_ad_bits,
7789 cpu_has_vmx_ept_execute_only());
7792 ept_lpage_level = 0;
7793 else if (cpu_has_vmx_ept_1g_page())
7794 ept_lpage_level = PG_LEVEL_1G;
7795 else if (cpu_has_vmx_ept_2m_page())
7796 ept_lpage_level = PG_LEVEL_2M;
7798 ept_lpage_level = PG_LEVEL_4K;
7799 kvm_configure_mmu(enable_ept, 0, vmx_get_max_tdp_level(),
7803 * Only enable PML when hardware supports PML feature, and both EPT
7804 * and EPT A/D bit features are enabled -- PML depends on them to work.
7806 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7810 vmx_x86_ops.cpu_dirty_log_size = 0;
7812 if (!cpu_has_vmx_preemption_timer())
7813 enable_preemption_timer = false;
7815 if (enable_preemption_timer) {
7816 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7819 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7820 cpu_preemption_timer_multi =
7821 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7824 use_timer_freq = (u64)tsc_khz * 1000;
7825 use_timer_freq >>= cpu_preemption_timer_multi;
7828 * KVM "disables" the preemption timer by setting it to its max
7829 * value. Don't use the timer if it might cause spurious exits
7830 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7832 if (use_timer_freq > 0xffffffffu / 10)
7833 enable_preemption_timer = false;
7836 if (!enable_preemption_timer) {
7837 vmx_x86_ops.set_hv_timer = NULL;
7838 vmx_x86_ops.cancel_hv_timer = NULL;
7839 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
7842 kvm_mce_cap_supported |= MCG_LMCE_P;
7844 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7846 if (!enable_ept || !cpu_has_vmx_intel_pt())
7847 pt_mode = PT_MODE_SYSTEM;
7849 setup_default_sgx_lepubkeyhash();
7852 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7853 vmx_capability.ept);
7855 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7862 r = alloc_kvm_area();
7864 nested_vmx_hardware_unsetup();
7866 kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler);
7871 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
7872 .cpu_has_kvm_support = cpu_has_kvm_support,
7873 .disabled_by_bios = vmx_disabled_by_bios,
7874 .check_processor_compatibility = vmx_check_processor_compat,
7875 .hardware_setup = hardware_setup,
7877 .runtime_ops = &vmx_x86_ops,
7880 static void vmx_cleanup_l1d_flush(void)
7882 if (vmx_l1d_flush_pages) {
7883 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7884 vmx_l1d_flush_pages = NULL;
7886 /* Restore state so sysfs ignores VMX */
7887 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7890 static void vmx_exit(void)
7892 #ifdef CONFIG_KEXEC_CORE
7893 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7899 #if IS_ENABLED(CONFIG_HYPERV)
7900 if (static_branch_unlikely(&enable_evmcs)) {
7902 struct hv_vp_assist_page *vp_ap;
7904 * Reset everything to support using non-enlightened VMCS
7905 * access later (e.g. when we reload the module with
7906 * enlightened_vmcs=0)
7908 for_each_online_cpu(cpu) {
7909 vp_ap = hv_get_vp_assist_page(cpu);
7914 vp_ap->nested_control.features.directhypercall = 0;
7915 vp_ap->current_nested_vmcs = 0;
7916 vp_ap->enlighten_vmentry = 0;
7919 static_branch_disable(&enable_evmcs);
7922 vmx_cleanup_l1d_flush();
7924 allow_smaller_maxphyaddr = false;
7926 module_exit(vmx_exit);
7928 static int __init vmx_init(void)
7932 #if IS_ENABLED(CONFIG_HYPERV)
7934 * Enlightened VMCS usage should be recommended and the host needs
7935 * to support eVMCS v1 or above. We can also disable eVMCS support
7936 * with module parameter.
7938 if (enlightened_vmcs &&
7939 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7940 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7941 KVM_EVMCS_VERSION) {
7944 /* Check that we have assist pages on all online CPUs */
7945 for_each_online_cpu(cpu) {
7946 if (!hv_get_vp_assist_page(cpu)) {
7947 enlightened_vmcs = false;
7952 if (enlightened_vmcs) {
7953 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7954 static_branch_enable(&enable_evmcs);
7957 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7958 vmx_x86_ops.enable_direct_tlbflush
7959 = hv_enable_direct_tlbflush;
7962 enlightened_vmcs = false;
7966 r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
7967 __alignof__(struct vcpu_vmx), THIS_MODULE);
7972 * Must be called after kvm_init() so enable_ept is properly set
7973 * up. Hand the parameter mitigation value in which was stored in
7974 * the pre module init parser. If no parameter was given, it will
7975 * contain 'auto' which will be turned into the default 'cond'
7978 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7984 for_each_possible_cpu(cpu) {
7985 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
7990 #ifdef CONFIG_KEXEC_CORE
7991 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7992 crash_vmclear_local_loaded_vmcss);
7994 vmx_check_vmcs12_offsets();
7997 * Shadow paging doesn't have a (further) performance penalty
7998 * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it
8002 allow_smaller_maxphyaddr = true;
8006 module_init(vmx_init);