1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/frame.h>
17 #include <linux/highmem.h>
18 #include <linux/hrtimer.h>
19 #include <linux/kernel.h>
20 #include <linux/kvm_host.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/mod_devicetable.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
34 #include <asm/debugreg.h>
36 #include <asm/fpu/internal.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/kexec.h>
40 #include <asm/perf_event.h>
42 #include <asm/mmu_context.h>
43 #include <asm/mshyperv.h>
44 #include <asm/spec-ctrl.h>
45 #include <asm/virtext.h>
48 #include "capabilities.h"
52 #include "kvm_cache_regs.h"
64 MODULE_AUTHOR("Qumranet");
65 MODULE_LICENSE("GPL");
68 static const struct x86_cpu_id vmx_cpu_id[] = {
69 X86_FEATURE_MATCH(X86_FEATURE_VMX),
72 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
75 bool __read_mostly enable_vpid = 1;
76 module_param_named(vpid, enable_vpid, bool, 0444);
78 static bool __read_mostly enable_vnmi = 1;
79 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
81 bool __read_mostly flexpriority_enabled = 1;
82 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
84 bool __read_mostly enable_ept = 1;
85 module_param_named(ept, enable_ept, bool, S_IRUGO);
87 bool __read_mostly enable_unrestricted_guest = 1;
88 module_param_named(unrestricted_guest,
89 enable_unrestricted_guest, bool, S_IRUGO);
91 bool __read_mostly enable_ept_ad_bits = 1;
92 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
94 static bool __read_mostly emulate_invalid_guest_state = true;
95 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
97 static bool __read_mostly fasteoi = 1;
98 module_param(fasteoi, bool, S_IRUGO);
100 bool __read_mostly enable_apicv = 1;
101 module_param(enable_apicv, bool, S_IRUGO);
104 * If nested=1, nested virtualization is supported, i.e., guests may use
105 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
106 * use VMX instructions.
108 static bool __read_mostly nested = 1;
109 module_param(nested, bool, S_IRUGO);
111 bool __read_mostly enable_pml = 1;
112 module_param_named(pml, enable_pml, bool, S_IRUGO);
114 static bool __read_mostly dump_invalid_vmcs = 0;
115 module_param(dump_invalid_vmcs, bool, 0644);
117 #define MSR_BITMAP_MODE_X2APIC 1
118 #define MSR_BITMAP_MODE_X2APIC_APICV 2
120 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
122 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
123 static int __read_mostly cpu_preemption_timer_multi;
124 static bool __read_mostly enable_preemption_timer = 1;
126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
131 #define KVM_VM_CR0_ALWAYS_ON \
132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
134 #define KVM_CR4_GUEST_OWNED_BITS \
135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
147 RTIT_STATUS_BYTECNT))
149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
153 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
154 * ple_gap: upper bound on the amount of time between two successive
155 * executions of PAUSE in a loop. Also indicate if ple enabled.
156 * According to test, this time is usually smaller than 128 cycles.
157 * ple_window: upper bound on the amount of time a guest is allowed to execute
158 * in a PAUSE loop. Tests indicate that most spinlocks are held for
159 * less than 2^12 cycles
160 * Time is measured based on a counter that runs at the same rate as the TSC,
161 * refer SDM volume 3b section 21.6.13 & 22.1.3.
163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
164 module_param(ple_gap, uint, 0444);
166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167 module_param(ple_window, uint, 0444);
169 /* Default doubles per-vcpu window every exit. */
170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
171 module_param(ple_window_grow, uint, 0444);
173 /* Default resets per-vcpu window every exit to ple_window. */
174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
175 module_param(ple_window_shrink, uint, 0444);
177 /* Default is to compute the maximum so we can never overflow. */
178 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179 module_param(ple_window_max, uint, 0444);
181 /* Default is SYSTEM mode, 1 for host-guest mode */
182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
183 module_param(pt_mode, int, S_IRUGO);
185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
189 /* Storage for pre module init parameter parsing */
190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
192 static const struct {
195 } vmentry_l1d_param[] = {
196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
198 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
204 #define L1D_CACHE_ORDER 4
205 static void *vmx_l1d_flush_pages;
207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
212 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
218 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
222 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
225 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
226 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
227 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
232 /* If set to auto use the default l1tf mitigation method */
233 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
234 switch (l1tf_mitigation) {
235 case L1TF_MITIGATION_OFF:
236 l1tf = VMENTER_L1D_FLUSH_NEVER;
238 case L1TF_MITIGATION_FLUSH_NOWARN:
239 case L1TF_MITIGATION_FLUSH:
240 case L1TF_MITIGATION_FLUSH_NOSMT:
241 l1tf = VMENTER_L1D_FLUSH_COND;
243 case L1TF_MITIGATION_FULL:
244 case L1TF_MITIGATION_FULL_FORCE:
245 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
248 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
249 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
252 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
253 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
255 * This allocation for vmx_l1d_flush_pages is not tied to a VM
256 * lifetime and so should not be charged to a memcg.
258 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
261 vmx_l1d_flush_pages = page_address(page);
264 * Initialize each page with a different pattern in
265 * order to protect against KSM in the nested
266 * virtualization case.
268 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
269 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
274 l1tf_vmx_mitigation = l1tf;
276 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
277 static_branch_enable(&vmx_l1d_should_flush);
279 static_branch_disable(&vmx_l1d_should_flush);
281 if (l1tf == VMENTER_L1D_FLUSH_COND)
282 static_branch_enable(&vmx_l1d_flush_cond);
284 static_branch_disable(&vmx_l1d_flush_cond);
288 static int vmentry_l1d_flush_parse(const char *s)
293 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
294 if (vmentry_l1d_param[i].for_parse &&
295 sysfs_streq(s, vmentry_l1d_param[i].option))
302 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
306 l1tf = vmentry_l1d_flush_parse(s);
310 if (!boot_cpu_has(X86_BUG_L1TF))
314 * Has vmx_init() run already? If not then this is the pre init
315 * parameter parsing. In that case just store the value and let
316 * vmx_init() do the proper setup after enable_ept has been
319 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
320 vmentry_l1d_flush_param = l1tf;
324 mutex_lock(&vmx_l1d_flush_mutex);
325 ret = vmx_setup_l1d_flush(l1tf);
326 mutex_unlock(&vmx_l1d_flush_mutex);
330 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
332 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
333 return sprintf(s, "???\n");
335 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
338 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
339 .set = vmentry_l1d_flush_set,
340 .get = vmentry_l1d_flush_get,
342 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
344 static bool guest_state_valid(struct kvm_vcpu *vcpu);
345 static u32 vmx_segment_access_rights(struct kvm_segment *var);
346 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
349 void vmx_vmexit(void);
351 #define vmx_insn_failed(fmt...) \
354 pr_warn_ratelimited(fmt); \
357 asmlinkage void vmread_error(unsigned long field, bool fault)
360 kvm_spurious_fault();
362 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
365 noinline void vmwrite_error(unsigned long field, unsigned long value)
367 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
368 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
371 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
373 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
376 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
378 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
381 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
383 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
387 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
389 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
393 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
394 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
396 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
397 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
399 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
402 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
403 * can find which vCPU should be waken up.
405 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
406 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
408 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
409 static DEFINE_SPINLOCK(vmx_vpid_lock);
411 struct vmcs_config vmcs_config;
412 struct vmx_capability vmx_capability;
414 #define VMX_SEGMENT_FIELD(seg) \
415 [VCPU_SREG_##seg] = { \
416 .selector = GUEST_##seg##_SELECTOR, \
417 .base = GUEST_##seg##_BASE, \
418 .limit = GUEST_##seg##_LIMIT, \
419 .ar_bytes = GUEST_##seg##_AR_BYTES, \
422 static const struct kvm_vmx_segment_field {
427 } kvm_vmx_segment_fields[] = {
428 VMX_SEGMENT_FIELD(CS),
429 VMX_SEGMENT_FIELD(DS),
430 VMX_SEGMENT_FIELD(ES),
431 VMX_SEGMENT_FIELD(FS),
432 VMX_SEGMENT_FIELD(GS),
433 VMX_SEGMENT_FIELD(SS),
434 VMX_SEGMENT_FIELD(TR),
435 VMX_SEGMENT_FIELD(LDTR),
439 static unsigned long host_idt_base;
442 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
443 * will emulate SYSCALL in legacy mode if the vendor string in guest
444 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
445 * support this emulation, IA32_STAR must always be included in
446 * vmx_msr_index[], even in i386 builds.
448 const u32 vmx_msr_index[] = {
450 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
452 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
456 #if IS_ENABLED(CONFIG_HYPERV)
457 static bool __read_mostly enlightened_vmcs = true;
458 module_param(enlightened_vmcs, bool, 0444);
460 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
461 static void check_ept_pointer_match(struct kvm *kvm)
463 struct kvm_vcpu *vcpu;
464 u64 tmp_eptp = INVALID_PAGE;
467 kvm_for_each_vcpu(i, vcpu, kvm) {
468 if (!VALID_PAGE(tmp_eptp)) {
469 tmp_eptp = to_vmx(vcpu)->ept_pointer;
470 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
471 to_kvm_vmx(kvm)->ept_pointers_match
472 = EPT_POINTERS_MISMATCH;
477 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
480 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
483 struct kvm_tlb_range *range = data;
485 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
489 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
490 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
492 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
495 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
496 * of the base of EPT PML4 table, strip off EPT configuration
500 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
501 kvm_fill_hv_flush_list_func, (void *)range);
503 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
506 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
507 struct kvm_tlb_range *range)
509 struct kvm_vcpu *vcpu;
512 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
514 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
515 check_ept_pointer_match(kvm);
517 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
518 kvm_for_each_vcpu(i, vcpu, kvm) {
519 /* If ept_pointer is invalid pointer, bypass flush request. */
520 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
521 ret |= __hv_remote_flush_tlb_with_range(
525 ret = __hv_remote_flush_tlb_with_range(kvm,
526 kvm_get_vcpu(kvm, 0), range);
529 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
532 static int hv_remote_flush_tlb(struct kvm *kvm)
534 return hv_remote_flush_tlb_with_range(kvm, NULL);
537 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
539 struct hv_enlightened_vmcs *evmcs;
540 struct hv_partition_assist_pg **p_hv_pa_pg =
541 &vcpu->kvm->arch.hyperv.hv_pa_pg;
543 * Synthetic VM-Exit is not enabled in current code and so All
544 * evmcs in singe VM shares same assist page.
547 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
552 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
554 evmcs->partition_assist_page =
556 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
557 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
562 #endif /* IS_ENABLED(CONFIG_HYPERV) */
565 * Comment's format: document - errata name - stepping - processor name.
567 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
569 static u32 vmx_preemption_cpu_tfms[] = {
570 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
572 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
573 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
574 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
576 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
578 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
579 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
581 * 320767.pdf - AAP86 - B1 -
582 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
585 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
587 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
589 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
591 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
592 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
593 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
595 /* Xeon E3-1220 V2 */
599 static inline bool cpu_has_broken_vmx_preemption_timer(void)
601 u32 eax = cpuid_eax(0x00000001), i;
603 /* Clear the reserved bits */
604 eax &= ~(0x3U << 14 | 0xfU << 28);
605 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
606 if (eax == vmx_preemption_cpu_tfms[i])
612 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
614 return flexpriority_enabled && lapic_in_kernel(vcpu);
617 static inline bool report_flexpriority(void)
619 return flexpriority_enabled;
622 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
626 for (i = 0; i < vmx->nmsrs; ++i)
627 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
632 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
636 i = __find_msr_index(vmx, msr);
638 return &vmx->guest_msrs[i];
642 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
646 u64 old_msr_data = msr->data;
648 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
650 ret = kvm_set_shared_msr(msr->index, msr->data,
654 msr->data = old_msr_data;
659 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
661 vmcs_clear(loaded_vmcs->vmcs);
662 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
663 vmcs_clear(loaded_vmcs->shadow_vmcs);
664 loaded_vmcs->cpu = -1;
665 loaded_vmcs->launched = 0;
668 #ifdef CONFIG_KEXEC_CORE
670 * This bitmap is used to indicate whether the vmclear
671 * operation is enabled on all cpus. All disabled by
674 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
676 static inline void crash_enable_local_vmclear(int cpu)
678 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
681 static inline void crash_disable_local_vmclear(int cpu)
683 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
686 static inline int crash_local_vmclear_enabled(int cpu)
688 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
691 static void crash_vmclear_local_loaded_vmcss(void)
693 int cpu = raw_smp_processor_id();
694 struct loaded_vmcs *v;
696 if (!crash_local_vmclear_enabled(cpu))
699 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
700 loaded_vmcss_on_cpu_link)
704 static inline void crash_enable_local_vmclear(int cpu) { }
705 static inline void crash_disable_local_vmclear(int cpu) { }
706 #endif /* CONFIG_KEXEC_CORE */
708 static void __loaded_vmcs_clear(void *arg)
710 struct loaded_vmcs *loaded_vmcs = arg;
711 int cpu = raw_smp_processor_id();
713 if (loaded_vmcs->cpu != cpu)
714 return; /* vcpu migration can race with cpu offline */
715 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
716 per_cpu(current_vmcs, cpu) = NULL;
717 crash_disable_local_vmclear(cpu);
718 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
721 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
722 * is before setting loaded_vmcs->vcpu to -1 which is done in
723 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
724 * then adds the vmcs into percpu list before it is deleted.
728 loaded_vmcs_init(loaded_vmcs);
729 crash_enable_local_vmclear(cpu);
732 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
734 int cpu = loaded_vmcs->cpu;
737 smp_call_function_single(cpu,
738 __loaded_vmcs_clear, loaded_vmcs, 1);
741 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
745 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
747 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
748 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
749 vmx->segment_cache.bitmask = 0;
751 ret = vmx->segment_cache.bitmask & mask;
752 vmx->segment_cache.bitmask |= mask;
756 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
758 u16 *p = &vmx->segment_cache.seg[seg].selector;
760 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
761 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
765 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
767 ulong *p = &vmx->segment_cache.seg[seg].base;
769 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
770 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
774 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
776 u32 *p = &vmx->segment_cache.seg[seg].limit;
778 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
779 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
783 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
785 u32 *p = &vmx->segment_cache.seg[seg].ar;
787 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
788 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
792 void update_exception_bitmap(struct kvm_vcpu *vcpu)
796 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
797 (1u << DB_VECTOR) | (1u << AC_VECTOR);
799 * Guest access to VMware backdoor ports could legitimately
800 * trigger #GP because of TSS I/O permission bitmap.
801 * We intercept those #GP and allow access to them anyway
804 if (enable_vmware_backdoor)
805 eb |= (1u << GP_VECTOR);
806 if ((vcpu->guest_debug &
807 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
808 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
809 eb |= 1u << BP_VECTOR;
810 if (to_vmx(vcpu)->rmode.vm86_active)
813 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
815 /* When we are running a nested L2 guest and L1 specified for it a
816 * certain exception bitmap, we must trap the same exceptions and pass
817 * them to L1. When running L2, we will only handle the exceptions
818 * specified above if L1 did not want them.
820 if (is_guest_mode(vcpu))
821 eb |= get_vmcs12(vcpu)->exception_bitmap;
823 vmcs_write32(EXCEPTION_BITMAP, eb);
827 * Check if MSR is intercepted for currently loaded MSR bitmap.
829 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
831 unsigned long *msr_bitmap;
832 int f = sizeof(unsigned long);
834 if (!cpu_has_vmx_msr_bitmap())
837 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
840 return !!test_bit(msr, msr_bitmap + 0x800 / f);
841 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
843 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
849 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
850 unsigned long entry, unsigned long exit)
852 vm_entry_controls_clearbit(vmx, entry);
853 vm_exit_controls_clearbit(vmx, exit);
856 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
860 for (i = 0; i < m->nr; ++i) {
861 if (m->val[i].index == msr)
867 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
870 struct msr_autoload *m = &vmx->msr_autoload;
874 if (cpu_has_load_ia32_efer()) {
875 clear_atomic_switch_msr_special(vmx,
876 VM_ENTRY_LOAD_IA32_EFER,
877 VM_EXIT_LOAD_IA32_EFER);
881 case MSR_CORE_PERF_GLOBAL_CTRL:
882 if (cpu_has_load_perf_global_ctrl()) {
883 clear_atomic_switch_msr_special(vmx,
884 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
885 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
890 i = vmx_find_msr_index(&m->guest, msr);
894 m->guest.val[i] = m->guest.val[m->guest.nr];
895 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
898 i = vmx_find_msr_index(&m->host, msr);
903 m->host.val[i] = m->host.val[m->host.nr];
904 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
907 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
908 unsigned long entry, unsigned long exit,
909 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
910 u64 guest_val, u64 host_val)
912 vmcs_write64(guest_val_vmcs, guest_val);
913 if (host_val_vmcs != HOST_IA32_EFER)
914 vmcs_write64(host_val_vmcs, host_val);
915 vm_entry_controls_setbit(vmx, entry);
916 vm_exit_controls_setbit(vmx, exit);
919 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
920 u64 guest_val, u64 host_val, bool entry_only)
923 struct msr_autoload *m = &vmx->msr_autoload;
927 if (cpu_has_load_ia32_efer()) {
928 add_atomic_switch_msr_special(vmx,
929 VM_ENTRY_LOAD_IA32_EFER,
930 VM_EXIT_LOAD_IA32_EFER,
933 guest_val, host_val);
937 case MSR_CORE_PERF_GLOBAL_CTRL:
938 if (cpu_has_load_perf_global_ctrl()) {
939 add_atomic_switch_msr_special(vmx,
940 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
941 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
942 GUEST_IA32_PERF_GLOBAL_CTRL,
943 HOST_IA32_PERF_GLOBAL_CTRL,
944 guest_val, host_val);
948 case MSR_IA32_PEBS_ENABLE:
949 /* PEBS needs a quiescent period after being disabled (to write
950 * a record). Disabling PEBS through VMX MSR swapping doesn't
951 * provide that period, so a CPU could write host's record into
954 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
957 i = vmx_find_msr_index(&m->guest, msr);
959 j = vmx_find_msr_index(&m->host, msr);
961 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
962 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) {
963 printk_once(KERN_WARNING "Not enough msr switch entries. "
964 "Can't add msr %x\n", msr);
969 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
971 m->guest.val[i].index = msr;
972 m->guest.val[i].value = guest_val;
979 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
981 m->host.val[j].index = msr;
982 m->host.val[j].value = host_val;
985 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
987 u64 guest_efer = vmx->vcpu.arch.efer;
990 /* Shadow paging assumes NX to be available. */
992 guest_efer |= EFER_NX;
995 * LMA and LME handled by hardware; SCE meaningless outside long mode.
997 ignore_bits |= EFER_SCE;
999 ignore_bits |= EFER_LMA | EFER_LME;
1000 /* SCE is meaningful only in long mode on Intel */
1001 if (guest_efer & EFER_LMA)
1002 ignore_bits &= ~(u64)EFER_SCE;
1006 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1007 * On CPUs that support "load IA32_EFER", always switch EFER
1008 * atomically, since it's faster than switching it manually.
1010 if (cpu_has_load_ia32_efer() ||
1011 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1012 if (!(guest_efer & EFER_LMA))
1013 guest_efer &= ~EFER_LME;
1014 if (guest_efer != host_efer)
1015 add_atomic_switch_msr(vmx, MSR_EFER,
1016 guest_efer, host_efer, false);
1018 clear_atomic_switch_msr(vmx, MSR_EFER);
1021 clear_atomic_switch_msr(vmx, MSR_EFER);
1023 guest_efer &= ~ignore_bits;
1024 guest_efer |= host_efer & ignore_bits;
1026 vmx->guest_msrs[efer_offset].data = guest_efer;
1027 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1033 #ifdef CONFIG_X86_32
1035 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1036 * VMCS rather than the segment table. KVM uses this helper to figure
1037 * out the current bases to poke them into the VMCS before entry.
1039 static unsigned long segment_base(u16 selector)
1041 struct desc_struct *table;
1044 if (!(selector & ~SEGMENT_RPL_MASK))
1047 table = get_current_gdt_ro();
1049 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1050 u16 ldt_selector = kvm_read_ldt();
1052 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1055 table = (struct desc_struct *)segment_base(ldt_selector);
1057 v = get_desc_base(&table[selector >> 3]);
1062 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1064 return (pt_mode == PT_MODE_HOST_GUEST) &&
1065 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1068 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1072 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1073 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1074 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1075 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1076 for (i = 0; i < addr_range; i++) {
1077 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1078 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1082 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1086 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1087 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1088 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1089 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1090 for (i = 0; i < addr_range; i++) {
1091 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1092 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1096 static void pt_guest_enter(struct vcpu_vmx *vmx)
1098 if (pt_mode == PT_MODE_SYSTEM)
1102 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1103 * Save host state before VM entry.
1105 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1106 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1107 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1108 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1109 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1113 static void pt_guest_exit(struct vcpu_vmx *vmx)
1115 if (pt_mode == PT_MODE_SYSTEM)
1118 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1119 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1120 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1123 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1124 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1127 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1128 unsigned long fs_base, unsigned long gs_base)
1130 if (unlikely(fs_sel != host->fs_sel)) {
1132 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1134 vmcs_write16(HOST_FS_SELECTOR, 0);
1135 host->fs_sel = fs_sel;
1137 if (unlikely(gs_sel != host->gs_sel)) {
1139 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1141 vmcs_write16(HOST_GS_SELECTOR, 0);
1142 host->gs_sel = gs_sel;
1144 if (unlikely(fs_base != host->fs_base)) {
1145 vmcs_writel(HOST_FS_BASE, fs_base);
1146 host->fs_base = fs_base;
1148 if (unlikely(gs_base != host->gs_base)) {
1149 vmcs_writel(HOST_GS_BASE, gs_base);
1150 host->gs_base = gs_base;
1154 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1156 struct vcpu_vmx *vmx = to_vmx(vcpu);
1157 struct vmcs_host_state *host_state;
1158 #ifdef CONFIG_X86_64
1159 int cpu = raw_smp_processor_id();
1161 unsigned long fs_base, gs_base;
1165 vmx->req_immediate_exit = false;
1168 * Note that guest MSRs to be saved/restored can also be changed
1169 * when guest state is loaded. This happens when guest transitions
1170 * to/from long-mode by setting MSR_EFER.LMA.
1172 if (!vmx->guest_msrs_ready) {
1173 vmx->guest_msrs_ready = true;
1174 for (i = 0; i < vmx->save_nmsrs; ++i)
1175 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1176 vmx->guest_msrs[i].data,
1177 vmx->guest_msrs[i].mask);
1181 if (vmx->nested.need_vmcs12_to_shadow_sync)
1182 nested_sync_vmcs12_to_shadow(vcpu);
1184 if (vmx->guest_state_loaded)
1187 host_state = &vmx->loaded_vmcs->host_state;
1190 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1191 * allow segment selectors with cpl > 0 or ti == 1.
1193 host_state->ldt_sel = kvm_read_ldt();
1195 #ifdef CONFIG_X86_64
1196 savesegment(ds, host_state->ds_sel);
1197 savesegment(es, host_state->es_sel);
1199 gs_base = cpu_kernelmode_gs_base(cpu);
1200 if (likely(is_64bit_mm(current->mm))) {
1201 save_fsgs_for_kvm();
1202 fs_sel = current->thread.fsindex;
1203 gs_sel = current->thread.gsindex;
1204 fs_base = current->thread.fsbase;
1205 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1207 savesegment(fs, fs_sel);
1208 savesegment(gs, gs_sel);
1209 fs_base = read_msr(MSR_FS_BASE);
1210 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1213 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1215 savesegment(fs, fs_sel);
1216 savesegment(gs, gs_sel);
1217 fs_base = segment_base(fs_sel);
1218 gs_base = segment_base(gs_sel);
1221 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1222 vmx->guest_state_loaded = true;
1225 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1227 struct vmcs_host_state *host_state;
1229 if (!vmx->guest_state_loaded)
1232 host_state = &vmx->loaded_vmcs->host_state;
1234 ++vmx->vcpu.stat.host_state_reload;
1236 #ifdef CONFIG_X86_64
1237 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1239 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1240 kvm_load_ldt(host_state->ldt_sel);
1241 #ifdef CONFIG_X86_64
1242 load_gs_index(host_state->gs_sel);
1244 loadsegment(gs, host_state->gs_sel);
1247 if (host_state->fs_sel & 7)
1248 loadsegment(fs, host_state->fs_sel);
1249 #ifdef CONFIG_X86_64
1250 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1251 loadsegment(ds, host_state->ds_sel);
1252 loadsegment(es, host_state->es_sel);
1255 invalidate_tss_limit();
1256 #ifdef CONFIG_X86_64
1257 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1259 load_fixmap_gdt(raw_smp_processor_id());
1260 vmx->guest_state_loaded = false;
1261 vmx->guest_msrs_ready = false;
1264 #ifdef CONFIG_X86_64
1265 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1268 if (vmx->guest_state_loaded)
1269 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1271 return vmx->msr_guest_kernel_gs_base;
1274 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1277 if (vmx->guest_state_loaded)
1278 wrmsrl(MSR_KERNEL_GS_BASE, data);
1280 vmx->msr_guest_kernel_gs_base = data;
1284 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1286 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1287 struct pi_desc old, new;
1291 * In case of hot-plug or hot-unplug, we may have to undo
1292 * vmx_vcpu_pi_put even if there is no assigned device. And we
1293 * always keep PI.NDST up to date for simplicity: it makes the
1294 * code easier, and CPU migration is not a fast path.
1296 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1300 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1301 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1302 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1303 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1306 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1307 pi_clear_sn(pi_desc);
1308 goto after_clear_sn;
1311 /* The full case. */
1313 old.control = new.control = pi_desc->control;
1315 dest = cpu_physical_id(cpu);
1317 if (x2apic_enabled())
1320 new.ndst = (dest << 8) & 0xFF00;
1323 } while (cmpxchg64(&pi_desc->control, old.control,
1324 new.control) != old.control);
1329 * Clear SN before reading the bitmap. The VT-d firmware
1330 * writes the bitmap and reads SN atomically (5.2.3 in the
1331 * spec), so it doesn't really have a memory barrier that
1332 * pairs with this, but we cannot do that and we need one.
1334 smp_mb__after_atomic();
1336 if (!pi_is_pir_empty(pi_desc))
1340 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1342 struct vcpu_vmx *vmx = to_vmx(vcpu);
1343 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1345 if (!already_loaded) {
1346 loaded_vmcs_clear(vmx->loaded_vmcs);
1347 local_irq_disable();
1348 crash_disable_local_vmclear(cpu);
1351 * Read loaded_vmcs->cpu should be before fetching
1352 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1353 * See the comments in __loaded_vmcs_clear().
1357 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1358 &per_cpu(loaded_vmcss_on_cpu, cpu));
1359 crash_enable_local_vmclear(cpu);
1363 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1364 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1365 vmcs_load(vmx->loaded_vmcs->vmcs);
1366 indirect_branch_prediction_barrier();
1369 if (!already_loaded) {
1370 void *gdt = get_current_gdt_ro();
1371 unsigned long sysenter_esp;
1373 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1376 * Linux uses per-cpu TSS and GDT, so set these when switching
1377 * processors. See 22.2.4.
1379 vmcs_writel(HOST_TR_BASE,
1380 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1381 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1383 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1384 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1386 vmx->loaded_vmcs->cpu = cpu;
1389 /* Setup TSC multiplier */
1390 if (kvm_has_tsc_control &&
1391 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1392 decache_tsc_multiplier(vmx);
1396 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1397 * vcpu mutex is already taken.
1399 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1401 struct vcpu_vmx *vmx = to_vmx(vcpu);
1403 vmx_vcpu_load_vmcs(vcpu, cpu);
1405 vmx_vcpu_pi_load(vcpu, cpu);
1407 vmx->host_pkru = read_pkru();
1408 vmx->host_debugctlmsr = get_debugctlmsr();
1411 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1413 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1415 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1416 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1417 !kvm_vcpu_apicv_active(vcpu))
1420 /* Set SN when the vCPU is preempted */
1421 if (vcpu->preempted)
1425 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1427 vmx_vcpu_pi_put(vcpu);
1429 vmx_prepare_switch_to_host(to_vmx(vcpu));
1432 static bool emulation_required(struct kvm_vcpu *vcpu)
1434 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1437 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1439 struct vcpu_vmx *vmx = to_vmx(vcpu);
1440 unsigned long rflags, save_rflags;
1442 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1443 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1444 rflags = vmcs_readl(GUEST_RFLAGS);
1445 if (vmx->rmode.vm86_active) {
1446 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1447 save_rflags = vmx->rmode.save_rflags;
1448 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1450 vmx->rflags = rflags;
1455 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1457 struct vcpu_vmx *vmx = to_vmx(vcpu);
1458 unsigned long old_rflags;
1460 if (enable_unrestricted_guest) {
1461 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1462 vmx->rflags = rflags;
1463 vmcs_writel(GUEST_RFLAGS, rflags);
1467 old_rflags = vmx_get_rflags(vcpu);
1468 vmx->rflags = rflags;
1469 if (vmx->rmode.vm86_active) {
1470 vmx->rmode.save_rflags = rflags;
1471 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1473 vmcs_writel(GUEST_RFLAGS, rflags);
1475 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1476 vmx->emulation_required = emulation_required(vcpu);
1479 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1481 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1484 if (interruptibility & GUEST_INTR_STATE_STI)
1485 ret |= KVM_X86_SHADOW_INT_STI;
1486 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1487 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1492 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1494 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1495 u32 interruptibility = interruptibility_old;
1497 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1499 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1500 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1501 else if (mask & KVM_X86_SHADOW_INT_STI)
1502 interruptibility |= GUEST_INTR_STATE_STI;
1504 if ((interruptibility != interruptibility_old))
1505 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1508 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1510 struct vcpu_vmx *vmx = to_vmx(vcpu);
1511 unsigned long value;
1514 * Any MSR write that attempts to change bits marked reserved will
1517 if (data & vmx->pt_desc.ctl_bitmask)
1521 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1522 * result in a #GP unless the same write also clears TraceEn.
1524 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1525 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1529 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1530 * and FabricEn would cause #GP, if
1531 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1533 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1534 !(data & RTIT_CTL_FABRIC_EN) &&
1535 !intel_pt_validate_cap(vmx->pt_desc.caps,
1536 PT_CAP_single_range_output))
1540 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1541 * utilize encodings marked reserved will casue a #GP fault.
1543 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1544 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1545 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1546 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1548 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1549 PT_CAP_cycle_thresholds);
1550 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1551 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1552 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1554 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1555 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1556 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1557 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1561 * If ADDRx_CFG is reserved or the encodings is >2 will
1562 * cause a #GP fault.
1564 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1565 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1567 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1568 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1570 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1571 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1573 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1574 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1580 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1585 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1586 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1587 * set when EPT misconfig occurs. In practice, real hardware updates
1588 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1589 * (namely Hyper-V) don't set it due to it being undefined behavior,
1590 * i.e. we end up advancing IP with some random value.
1592 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1593 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1594 rip = kvm_rip_read(vcpu);
1595 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1596 kvm_rip_write(vcpu, rip);
1598 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1602 /* skipping an emulated instruction also counts */
1603 vmx_set_interrupt_shadow(vcpu, 0);
1610 * Recognizes a pending MTF VM-exit and records the nested state for later
1613 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1615 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1616 struct vcpu_vmx *vmx = to_vmx(vcpu);
1618 if (!is_guest_mode(vcpu))
1622 * Per the SDM, MTF takes priority over debug-trap exceptions besides
1623 * T-bit traps. As instruction emulation is completed (i.e. at the
1624 * instruction boundary), any #DB exception pending delivery must be a
1625 * debug-trap. Record the pending MTF state to be delivered in
1626 * vmx_check_nested_events().
1628 if (nested_cpu_has_mtf(vmcs12) &&
1629 (!vcpu->arch.exception.pending ||
1630 vcpu->arch.exception.nr == DB_VECTOR))
1631 vmx->nested.mtf_pending = true;
1633 vmx->nested.mtf_pending = false;
1636 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1638 vmx_update_emulated_instruction(vcpu);
1639 return skip_emulated_instruction(vcpu);
1642 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1645 * Ensure that we clear the HLT state in the VMCS. We don't need to
1646 * explicitly skip the instruction because if the HLT state is set,
1647 * then the instruction is already executing and RIP has already been
1650 if (kvm_hlt_in_guest(vcpu->kvm) &&
1651 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1652 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1655 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1657 struct vcpu_vmx *vmx = to_vmx(vcpu);
1658 unsigned nr = vcpu->arch.exception.nr;
1659 bool has_error_code = vcpu->arch.exception.has_error_code;
1660 u32 error_code = vcpu->arch.exception.error_code;
1661 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1663 kvm_deliver_exception_payload(vcpu);
1665 if (has_error_code) {
1666 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1667 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1670 if (vmx->rmode.vm86_active) {
1672 if (kvm_exception_is_soft(nr))
1673 inc_eip = vcpu->arch.event_exit_inst_len;
1674 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1678 WARN_ON_ONCE(vmx->emulation_required);
1680 if (kvm_exception_is_soft(nr)) {
1681 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1682 vmx->vcpu.arch.event_exit_inst_len);
1683 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1685 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1687 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1689 vmx_clear_hlt(vcpu);
1692 static bool vmx_rdtscp_supported(void)
1694 return cpu_has_vmx_rdtscp();
1697 static bool vmx_invpcid_supported(void)
1699 return cpu_has_vmx_invpcid();
1703 * Swap MSR entry in host/guest MSR entry array.
1705 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1707 struct shared_msr_entry tmp;
1709 tmp = vmx->guest_msrs[to];
1710 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1711 vmx->guest_msrs[from] = tmp;
1715 * Set up the vmcs to automatically save and restore system
1716 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1717 * mode, as fiddling with msrs is very expensive.
1719 static void setup_msrs(struct vcpu_vmx *vmx)
1721 int save_nmsrs, index;
1724 #ifdef CONFIG_X86_64
1726 * The SYSCALL MSRs are only needed on long mode guests, and only
1727 * when EFER.SCE is set.
1729 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1730 index = __find_msr_index(vmx, MSR_STAR);
1732 move_msr_up(vmx, index, save_nmsrs++);
1733 index = __find_msr_index(vmx, MSR_LSTAR);
1735 move_msr_up(vmx, index, save_nmsrs++);
1736 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1738 move_msr_up(vmx, index, save_nmsrs++);
1741 index = __find_msr_index(vmx, MSR_EFER);
1742 if (index >= 0 && update_transition_efer(vmx, index))
1743 move_msr_up(vmx, index, save_nmsrs++);
1744 index = __find_msr_index(vmx, MSR_TSC_AUX);
1745 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1746 move_msr_up(vmx, index, save_nmsrs++);
1747 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1749 move_msr_up(vmx, index, save_nmsrs++);
1751 vmx->save_nmsrs = save_nmsrs;
1752 vmx->guest_msrs_ready = false;
1754 if (cpu_has_vmx_msr_bitmap())
1755 vmx_update_msr_bitmap(&vmx->vcpu);
1758 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1760 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1762 if (is_guest_mode(vcpu) &&
1763 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1764 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1766 return vcpu->arch.tsc_offset;
1769 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1771 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1772 u64 g_tsc_offset = 0;
1775 * We're here if L1 chose not to trap WRMSR to TSC. According
1776 * to the spec, this should set L1's TSC; The offset that L1
1777 * set for L2 remains unchanged, and still needs to be added
1778 * to the newly set TSC to get L2's TSC.
1780 if (is_guest_mode(vcpu) &&
1781 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1782 g_tsc_offset = vmcs12->tsc_offset;
1784 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1785 vcpu->arch.tsc_offset - g_tsc_offset,
1787 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1788 return offset + g_tsc_offset;
1792 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1793 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1794 * all guests if the "nested" module option is off, and can also be disabled
1795 * for a single guest by disabling its VMX cpuid bit.
1797 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1799 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1802 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1805 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1807 return !(val & ~valid_bits);
1810 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1812 switch (msr->index) {
1813 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1816 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1823 * Reads an msr value (of 'msr_index') into 'pdata'.
1824 * Returns 0 on success, non-0 otherwise.
1825 * Assumes vcpu_load() was already called.
1827 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1829 struct vcpu_vmx *vmx = to_vmx(vcpu);
1830 struct shared_msr_entry *msr;
1833 switch (msr_info->index) {
1834 #ifdef CONFIG_X86_64
1836 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1839 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1841 case MSR_KERNEL_GS_BASE:
1842 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1846 return kvm_get_msr_common(vcpu, msr_info);
1847 case MSR_IA32_TSX_CTRL:
1848 if (!msr_info->host_initiated &&
1849 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1851 goto find_shared_msr;
1852 case MSR_IA32_UMWAIT_CONTROL:
1853 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1856 msr_info->data = vmx->msr_ia32_umwait_control;
1858 case MSR_IA32_SPEC_CTRL:
1859 if (!msr_info->host_initiated &&
1860 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1863 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1865 case MSR_IA32_SYSENTER_CS:
1866 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1868 case MSR_IA32_SYSENTER_EIP:
1869 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1871 case MSR_IA32_SYSENTER_ESP:
1872 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1874 case MSR_IA32_BNDCFGS:
1875 if (!kvm_mpx_supported() ||
1876 (!msr_info->host_initiated &&
1877 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1879 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1881 case MSR_IA32_MCG_EXT_CTL:
1882 if (!msr_info->host_initiated &&
1883 !(vmx->msr_ia32_feature_control &
1884 FEAT_CTL_LMCE_ENABLED))
1886 msr_info->data = vcpu->arch.mcg_ext_ctl;
1888 case MSR_IA32_FEAT_CTL:
1889 msr_info->data = vmx->msr_ia32_feature_control;
1891 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1892 if (!nested_vmx_allowed(vcpu))
1894 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1898 * Enlightened VMCS v1 doesn't have certain fields, but buggy
1899 * Hyper-V versions are still trying to use corresponding
1900 * features when they are exposed. Filter out the essential
1903 if (!msr_info->host_initiated &&
1904 vmx->nested.enlightened_vmcs_enabled)
1905 nested_evmcs_filter_control_msr(msr_info->index,
1908 case MSR_IA32_RTIT_CTL:
1909 if (pt_mode != PT_MODE_HOST_GUEST)
1911 msr_info->data = vmx->pt_desc.guest.ctl;
1913 case MSR_IA32_RTIT_STATUS:
1914 if (pt_mode != PT_MODE_HOST_GUEST)
1916 msr_info->data = vmx->pt_desc.guest.status;
1918 case MSR_IA32_RTIT_CR3_MATCH:
1919 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1920 !intel_pt_validate_cap(vmx->pt_desc.caps,
1921 PT_CAP_cr3_filtering))
1923 msr_info->data = vmx->pt_desc.guest.cr3_match;
1925 case MSR_IA32_RTIT_OUTPUT_BASE:
1926 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1927 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1928 PT_CAP_topa_output) &&
1929 !intel_pt_validate_cap(vmx->pt_desc.caps,
1930 PT_CAP_single_range_output)))
1932 msr_info->data = vmx->pt_desc.guest.output_base;
1934 case MSR_IA32_RTIT_OUTPUT_MASK:
1935 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1936 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1937 PT_CAP_topa_output) &&
1938 !intel_pt_validate_cap(vmx->pt_desc.caps,
1939 PT_CAP_single_range_output)))
1941 msr_info->data = vmx->pt_desc.guest.output_mask;
1943 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1944 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1945 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1946 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1947 PT_CAP_num_address_ranges)))
1950 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1952 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1955 if (!msr_info->host_initiated &&
1956 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1958 goto find_shared_msr;
1961 msr = find_msr_entry(vmx, msr_info->index);
1963 msr_info->data = msr->data;
1966 return kvm_get_msr_common(vcpu, msr_info);
1973 * Writes msr value into the appropriate "register".
1974 * Returns 0 on success, non-0 otherwise.
1975 * Assumes vcpu_load() was already called.
1977 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1979 struct vcpu_vmx *vmx = to_vmx(vcpu);
1980 struct shared_msr_entry *msr;
1982 u32 msr_index = msr_info->index;
1983 u64 data = msr_info->data;
1986 switch (msr_index) {
1988 ret = kvm_set_msr_common(vcpu, msr_info);
1990 #ifdef CONFIG_X86_64
1992 vmx_segment_cache_clear(vmx);
1993 vmcs_writel(GUEST_FS_BASE, data);
1996 vmx_segment_cache_clear(vmx);
1997 vmcs_writel(GUEST_GS_BASE, data);
1999 case MSR_KERNEL_GS_BASE:
2000 vmx_write_guest_kernel_gs_base(vmx, data);
2003 case MSR_IA32_SYSENTER_CS:
2004 if (is_guest_mode(vcpu))
2005 get_vmcs12(vcpu)->guest_sysenter_cs = data;
2006 vmcs_write32(GUEST_SYSENTER_CS, data);
2008 case MSR_IA32_SYSENTER_EIP:
2009 if (is_guest_mode(vcpu))
2010 get_vmcs12(vcpu)->guest_sysenter_eip = data;
2011 vmcs_writel(GUEST_SYSENTER_EIP, data);
2013 case MSR_IA32_SYSENTER_ESP:
2014 if (is_guest_mode(vcpu))
2015 get_vmcs12(vcpu)->guest_sysenter_esp = data;
2016 vmcs_writel(GUEST_SYSENTER_ESP, data);
2018 case MSR_IA32_DEBUGCTLMSR:
2019 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
2020 VM_EXIT_SAVE_DEBUG_CONTROLS)
2021 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2023 ret = kvm_set_msr_common(vcpu, msr_info);
2026 case MSR_IA32_BNDCFGS:
2027 if (!kvm_mpx_supported() ||
2028 (!msr_info->host_initiated &&
2029 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2031 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2032 (data & MSR_IA32_BNDCFGS_RSVD))
2034 vmcs_write64(GUEST_BNDCFGS, data);
2036 case MSR_IA32_UMWAIT_CONTROL:
2037 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2040 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2041 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2044 vmx->msr_ia32_umwait_control = data;
2046 case MSR_IA32_SPEC_CTRL:
2047 if (!msr_info->host_initiated &&
2048 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2051 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
2054 vmx->spec_ctrl = data;
2060 * When it's written (to non-zero) for the first time, pass
2064 * The handling of the MSR bitmap for L2 guests is done in
2065 * nested_vmx_prepare_msr_bitmap. We should not touch the
2066 * vmcs02.msr_bitmap here since it gets completely overwritten
2067 * in the merging. We update the vmcs01 here for L1 as well
2068 * since it will end up touching the MSR anyway now.
2070 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2074 case MSR_IA32_TSX_CTRL:
2075 if (!msr_info->host_initiated &&
2076 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2078 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2080 goto find_shared_msr;
2081 case MSR_IA32_PRED_CMD:
2082 if (!msr_info->host_initiated &&
2083 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2086 if (data & ~PRED_CMD_IBPB)
2088 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2093 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2097 * When it's written (to non-zero) for the first time, pass
2101 * The handling of the MSR bitmap for L2 guests is done in
2102 * nested_vmx_prepare_msr_bitmap. We should not touch the
2103 * vmcs02.msr_bitmap here since it gets completely overwritten
2106 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2109 case MSR_IA32_CR_PAT:
2110 if (!kvm_pat_valid(data))
2113 if (is_guest_mode(vcpu) &&
2114 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2115 get_vmcs12(vcpu)->guest_ia32_pat = data;
2117 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2118 vmcs_write64(GUEST_IA32_PAT, data);
2119 vcpu->arch.pat = data;
2122 ret = kvm_set_msr_common(vcpu, msr_info);
2124 case MSR_IA32_TSC_ADJUST:
2125 ret = kvm_set_msr_common(vcpu, msr_info);
2127 case MSR_IA32_MCG_EXT_CTL:
2128 if ((!msr_info->host_initiated &&
2129 !(to_vmx(vcpu)->msr_ia32_feature_control &
2130 FEAT_CTL_LMCE_ENABLED)) ||
2131 (data & ~MCG_EXT_CTL_LMCE_EN))
2133 vcpu->arch.mcg_ext_ctl = data;
2135 case MSR_IA32_FEAT_CTL:
2136 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2137 (to_vmx(vcpu)->msr_ia32_feature_control &
2138 FEAT_CTL_LOCKED && !msr_info->host_initiated))
2140 vmx->msr_ia32_feature_control = data;
2141 if (msr_info->host_initiated && data == 0)
2142 vmx_leave_nested(vcpu);
2144 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2145 if (!msr_info->host_initiated)
2146 return 1; /* they are read-only */
2147 if (!nested_vmx_allowed(vcpu))
2149 return vmx_set_vmx_msr(vcpu, msr_index, data);
2150 case MSR_IA32_RTIT_CTL:
2151 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2152 vmx_rtit_ctl_check(vcpu, data) ||
2155 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2156 vmx->pt_desc.guest.ctl = data;
2157 pt_update_intercept_for_msr(vmx);
2159 case MSR_IA32_RTIT_STATUS:
2160 if (!pt_can_write_msr(vmx))
2162 if (data & MSR_IA32_RTIT_STATUS_MASK)
2164 vmx->pt_desc.guest.status = data;
2166 case MSR_IA32_RTIT_CR3_MATCH:
2167 if (!pt_can_write_msr(vmx))
2169 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2170 PT_CAP_cr3_filtering))
2172 vmx->pt_desc.guest.cr3_match = data;
2174 case MSR_IA32_RTIT_OUTPUT_BASE:
2175 if (!pt_can_write_msr(vmx))
2177 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2178 PT_CAP_topa_output) &&
2179 !intel_pt_validate_cap(vmx->pt_desc.caps,
2180 PT_CAP_single_range_output))
2182 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
2184 vmx->pt_desc.guest.output_base = data;
2186 case MSR_IA32_RTIT_OUTPUT_MASK:
2187 if (!pt_can_write_msr(vmx))
2189 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2190 PT_CAP_topa_output) &&
2191 !intel_pt_validate_cap(vmx->pt_desc.caps,
2192 PT_CAP_single_range_output))
2194 vmx->pt_desc.guest.output_mask = data;
2196 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2197 if (!pt_can_write_msr(vmx))
2199 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2200 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2201 PT_CAP_num_address_ranges))
2203 if (is_noncanonical_address(data, vcpu))
2206 vmx->pt_desc.guest.addr_b[index / 2] = data;
2208 vmx->pt_desc.guest.addr_a[index / 2] = data;
2211 if (!msr_info->host_initiated &&
2212 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2214 /* Check reserved bit, higher 32 bits should be zero */
2215 if ((data >> 32) != 0)
2217 goto find_shared_msr;
2221 msr = find_msr_entry(vmx, msr_index);
2223 ret = vmx_set_guest_msr(vmx, msr, data);
2225 ret = kvm_set_msr_common(vcpu, msr_info);
2231 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2233 kvm_register_mark_available(vcpu, reg);
2237 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2240 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2242 case VCPU_EXREG_PDPTR:
2244 ept_save_pdptrs(vcpu);
2246 case VCPU_EXREG_CR3:
2247 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2248 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2256 static __init int cpu_has_kvm_support(void)
2258 return cpu_has_vmx();
2261 static __init int vmx_disabled_by_bios(void)
2263 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2264 !boot_cpu_has(X86_FEATURE_VMX);
2267 static void kvm_cpu_vmxon(u64 addr)
2269 cr4_set_bits(X86_CR4_VMXE);
2270 intel_pt_handle_vmx(1);
2272 asm volatile ("vmxon %0" : : "m"(addr));
2275 static int hardware_enable(void)
2277 int cpu = raw_smp_processor_id();
2278 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2280 if (cr4_read_shadow() & X86_CR4_VMXE)
2284 * This can happen if we hot-added a CPU but failed to allocate
2285 * VP assist page for it.
2287 if (static_branch_unlikely(&enable_evmcs) &&
2288 !hv_get_vp_assist_page(cpu))
2291 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2292 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2293 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2296 * Now we can enable the vmclear operation in kdump
2297 * since the loaded_vmcss_on_cpu list on this cpu
2298 * has been initialized.
2300 * Though the cpu is not in VMX operation now, there
2301 * is no problem to enable the vmclear operation
2302 * for the loaded_vmcss_on_cpu list is empty!
2304 crash_enable_local_vmclear(cpu);
2306 kvm_cpu_vmxon(phys_addr);
2313 static void vmclear_local_loaded_vmcss(void)
2315 int cpu = raw_smp_processor_id();
2316 struct loaded_vmcs *v, *n;
2318 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2319 loaded_vmcss_on_cpu_link)
2320 __loaded_vmcs_clear(v);
2324 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2327 static void kvm_cpu_vmxoff(void)
2329 asm volatile (__ex("vmxoff"));
2331 intel_pt_handle_vmx(0);
2332 cr4_clear_bits(X86_CR4_VMXE);
2335 static void hardware_disable(void)
2337 vmclear_local_loaded_vmcss();
2342 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2343 * directly instead of going through cpu_has(), to ensure KVM is trapping
2344 * ENCLS whenever it's supported in hardware. It does not matter whether
2345 * the host OS supports or has enabled SGX.
2347 static bool cpu_has_sgx(void)
2349 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2352 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2353 u32 msr, u32 *result)
2355 u32 vmx_msr_low, vmx_msr_high;
2356 u32 ctl = ctl_min | ctl_opt;
2358 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2360 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2361 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2363 /* Ensure minimum (required) set of control bits are supported. */
2371 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2372 struct vmx_capability *vmx_cap)
2374 u32 vmx_msr_low, vmx_msr_high;
2375 u32 min, opt, min2, opt2;
2376 u32 _pin_based_exec_control = 0;
2377 u32 _cpu_based_exec_control = 0;
2378 u32 _cpu_based_2nd_exec_control = 0;
2379 u32 _vmexit_control = 0;
2380 u32 _vmentry_control = 0;
2382 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2383 min = CPU_BASED_HLT_EXITING |
2384 #ifdef CONFIG_X86_64
2385 CPU_BASED_CR8_LOAD_EXITING |
2386 CPU_BASED_CR8_STORE_EXITING |
2388 CPU_BASED_CR3_LOAD_EXITING |
2389 CPU_BASED_CR3_STORE_EXITING |
2390 CPU_BASED_UNCOND_IO_EXITING |
2391 CPU_BASED_MOV_DR_EXITING |
2392 CPU_BASED_USE_TSC_OFFSETTING |
2393 CPU_BASED_MWAIT_EXITING |
2394 CPU_BASED_MONITOR_EXITING |
2395 CPU_BASED_INVLPG_EXITING |
2396 CPU_BASED_RDPMC_EXITING;
2398 opt = CPU_BASED_TPR_SHADOW |
2399 CPU_BASED_USE_MSR_BITMAPS |
2400 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2401 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2402 &_cpu_based_exec_control) < 0)
2404 #ifdef CONFIG_X86_64
2405 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2406 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2407 ~CPU_BASED_CR8_STORE_EXITING;
2409 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2411 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2412 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2413 SECONDARY_EXEC_WBINVD_EXITING |
2414 SECONDARY_EXEC_ENABLE_VPID |
2415 SECONDARY_EXEC_ENABLE_EPT |
2416 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2417 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2418 SECONDARY_EXEC_DESC |
2419 SECONDARY_EXEC_RDTSCP |
2420 SECONDARY_EXEC_ENABLE_INVPCID |
2421 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2422 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2423 SECONDARY_EXEC_SHADOW_VMCS |
2424 SECONDARY_EXEC_XSAVES |
2425 SECONDARY_EXEC_RDSEED_EXITING |
2426 SECONDARY_EXEC_RDRAND_EXITING |
2427 SECONDARY_EXEC_ENABLE_PML |
2428 SECONDARY_EXEC_TSC_SCALING |
2429 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2430 SECONDARY_EXEC_PT_USE_GPA |
2431 SECONDARY_EXEC_PT_CONCEAL_VMX |
2432 SECONDARY_EXEC_ENABLE_VMFUNC;
2434 opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2435 if (adjust_vmx_controls(min2, opt2,
2436 MSR_IA32_VMX_PROCBASED_CTLS2,
2437 &_cpu_based_2nd_exec_control) < 0)
2440 #ifndef CONFIG_X86_64
2441 if (!(_cpu_based_2nd_exec_control &
2442 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2443 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2446 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2447 _cpu_based_2nd_exec_control &= ~(
2448 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2449 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2450 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2452 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2453 &vmx_cap->ept, &vmx_cap->vpid);
2455 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2456 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2458 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2459 CPU_BASED_CR3_STORE_EXITING |
2460 CPU_BASED_INVLPG_EXITING);
2461 } else if (vmx_cap->ept) {
2463 pr_warn_once("EPT CAP should not exist if not support "
2464 "1-setting enable EPT VM-execution control\n");
2466 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2469 pr_warn_once("VPID CAP should not exist if not support "
2470 "1-setting enable VPID VM-execution control\n");
2473 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2474 #ifdef CONFIG_X86_64
2475 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2477 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2478 VM_EXIT_LOAD_IA32_PAT |
2479 VM_EXIT_LOAD_IA32_EFER |
2480 VM_EXIT_CLEAR_BNDCFGS |
2481 VM_EXIT_PT_CONCEAL_PIP |
2482 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2483 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2484 &_vmexit_control) < 0)
2487 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2488 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2489 PIN_BASED_VMX_PREEMPTION_TIMER;
2490 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2491 &_pin_based_exec_control) < 0)
2494 if (cpu_has_broken_vmx_preemption_timer())
2495 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2496 if (!(_cpu_based_2nd_exec_control &
2497 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2498 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2500 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2501 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2502 VM_ENTRY_LOAD_IA32_PAT |
2503 VM_ENTRY_LOAD_IA32_EFER |
2504 VM_ENTRY_LOAD_BNDCFGS |
2505 VM_ENTRY_PT_CONCEAL_PIP |
2506 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2507 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2508 &_vmentry_control) < 0)
2512 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2513 * can't be used due to an errata where VM Exit may incorrectly clear
2514 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2515 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2517 if (boot_cpu_data.x86 == 0x6) {
2518 switch (boot_cpu_data.x86_model) {
2519 case 26: /* AAK155 */
2520 case 30: /* AAP115 */
2521 case 37: /* AAT100 */
2522 case 44: /* BC86,AAY89,BD102 */
2524 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2525 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2526 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2527 "does not work properly. Using workaround\n");
2535 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2537 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2538 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2541 #ifdef CONFIG_X86_64
2542 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2543 if (vmx_msr_high & (1u<<16))
2547 /* Require Write-Back (WB) memory type for VMCS accesses. */
2548 if (((vmx_msr_high >> 18) & 15) != 6)
2551 vmcs_conf->size = vmx_msr_high & 0x1fff;
2552 vmcs_conf->order = get_order(vmcs_conf->size);
2553 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2555 vmcs_conf->revision_id = vmx_msr_low;
2557 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2558 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2559 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2560 vmcs_conf->vmexit_ctrl = _vmexit_control;
2561 vmcs_conf->vmentry_ctrl = _vmentry_control;
2563 if (static_branch_unlikely(&enable_evmcs))
2564 evmcs_sanitize_exec_ctrls(vmcs_conf);
2569 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2571 int node = cpu_to_node(cpu);
2575 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2578 vmcs = page_address(pages);
2579 memset(vmcs, 0, vmcs_config.size);
2581 /* KVM supports Enlightened VMCS v1 only */
2582 if (static_branch_unlikely(&enable_evmcs))
2583 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2585 vmcs->hdr.revision_id = vmcs_config.revision_id;
2588 vmcs->hdr.shadow_vmcs = 1;
2592 void free_vmcs(struct vmcs *vmcs)
2594 free_pages((unsigned long)vmcs, vmcs_config.order);
2598 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2600 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2602 if (!loaded_vmcs->vmcs)
2604 loaded_vmcs_clear(loaded_vmcs);
2605 free_vmcs(loaded_vmcs->vmcs);
2606 loaded_vmcs->vmcs = NULL;
2607 if (loaded_vmcs->msr_bitmap)
2608 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2609 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2612 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2614 loaded_vmcs->vmcs = alloc_vmcs(false);
2615 if (!loaded_vmcs->vmcs)
2618 loaded_vmcs->shadow_vmcs = NULL;
2619 loaded_vmcs->hv_timer_soft_disabled = false;
2620 loaded_vmcs_init(loaded_vmcs);
2622 if (cpu_has_vmx_msr_bitmap()) {
2623 loaded_vmcs->msr_bitmap = (unsigned long *)
2624 __get_free_page(GFP_KERNEL_ACCOUNT);
2625 if (!loaded_vmcs->msr_bitmap)
2627 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2629 if (IS_ENABLED(CONFIG_HYPERV) &&
2630 static_branch_unlikely(&enable_evmcs) &&
2631 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2632 struct hv_enlightened_vmcs *evmcs =
2633 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2635 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2639 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2640 memset(&loaded_vmcs->controls_shadow, 0,
2641 sizeof(struct vmcs_controls_shadow));
2646 free_loaded_vmcs(loaded_vmcs);
2650 static void free_kvm_area(void)
2654 for_each_possible_cpu(cpu) {
2655 free_vmcs(per_cpu(vmxarea, cpu));
2656 per_cpu(vmxarea, cpu) = NULL;
2660 static __init int alloc_kvm_area(void)
2664 for_each_possible_cpu(cpu) {
2667 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2674 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2675 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2676 * revision_id reported by MSR_IA32_VMX_BASIC.
2678 * However, even though not explicitly documented by
2679 * TLFS, VMXArea passed as VMXON argument should
2680 * still be marked with revision_id reported by
2683 if (static_branch_unlikely(&enable_evmcs))
2684 vmcs->hdr.revision_id = vmcs_config.revision_id;
2686 per_cpu(vmxarea, cpu) = vmcs;
2691 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2692 struct kvm_segment *save)
2694 if (!emulate_invalid_guest_state) {
2696 * CS and SS RPL should be equal during guest entry according
2697 * to VMX spec, but in reality it is not always so. Since vcpu
2698 * is in the middle of the transition from real mode to
2699 * protected mode it is safe to assume that RPL 0 is a good
2702 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2703 save->selector &= ~SEGMENT_RPL_MASK;
2704 save->dpl = save->selector & SEGMENT_RPL_MASK;
2707 vmx_set_segment(vcpu, save, seg);
2710 static void enter_pmode(struct kvm_vcpu *vcpu)
2712 unsigned long flags;
2713 struct vcpu_vmx *vmx = to_vmx(vcpu);
2716 * Update real mode segment cache. It may be not up-to-date if sement
2717 * register was written while vcpu was in a guest mode.
2719 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2720 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2721 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2722 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2723 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2724 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2726 vmx->rmode.vm86_active = 0;
2728 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2730 flags = vmcs_readl(GUEST_RFLAGS);
2731 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2732 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2733 vmcs_writel(GUEST_RFLAGS, flags);
2735 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2736 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2738 update_exception_bitmap(vcpu);
2740 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2741 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2742 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2743 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2744 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2745 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2748 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2750 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2751 struct kvm_segment var = *save;
2754 if (seg == VCPU_SREG_CS)
2757 if (!emulate_invalid_guest_state) {
2758 var.selector = var.base >> 4;
2759 var.base = var.base & 0xffff0;
2769 if (save->base & 0xf)
2770 printk_once(KERN_WARNING "kvm: segment base is not "
2771 "paragraph aligned when entering "
2772 "protected mode (seg=%d)", seg);
2775 vmcs_write16(sf->selector, var.selector);
2776 vmcs_writel(sf->base, var.base);
2777 vmcs_write32(sf->limit, var.limit);
2778 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2781 static void enter_rmode(struct kvm_vcpu *vcpu)
2783 unsigned long flags;
2784 struct vcpu_vmx *vmx = to_vmx(vcpu);
2785 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2787 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2788 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2789 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2790 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2791 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2792 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2793 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2795 vmx->rmode.vm86_active = 1;
2798 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2799 * vcpu. Warn the user that an update is overdue.
2801 if (!kvm_vmx->tss_addr)
2802 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2803 "called before entering vcpu\n");
2805 vmx_segment_cache_clear(vmx);
2807 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2808 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2809 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2811 flags = vmcs_readl(GUEST_RFLAGS);
2812 vmx->rmode.save_rflags = flags;
2814 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2816 vmcs_writel(GUEST_RFLAGS, flags);
2817 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2818 update_exception_bitmap(vcpu);
2820 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2821 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2822 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2823 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2824 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2825 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2827 kvm_mmu_reset_context(vcpu);
2830 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2832 struct vcpu_vmx *vmx = to_vmx(vcpu);
2833 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2838 vcpu->arch.efer = efer;
2839 if (efer & EFER_LMA) {
2840 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2843 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2845 msr->data = efer & ~EFER_LME;
2850 #ifdef CONFIG_X86_64
2852 static void enter_lmode(struct kvm_vcpu *vcpu)
2856 vmx_segment_cache_clear(to_vmx(vcpu));
2858 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2859 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2860 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2862 vmcs_write32(GUEST_TR_AR_BYTES,
2863 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2864 | VMX_AR_TYPE_BUSY_64_TSS);
2866 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2869 static void exit_lmode(struct kvm_vcpu *vcpu)
2871 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2872 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2877 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2879 int vpid = to_vmx(vcpu)->vpid;
2881 if (!vpid_sync_vcpu_addr(vpid, addr))
2882 vpid_sync_context(vpid);
2885 * If VPIDs are not supported or enabled, then the above is a no-op.
2886 * But we don't really need a TLB flush in that case anyway, because
2887 * each VM entry/exit includes an implicit flush when VPID is 0.
2891 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2893 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2895 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2896 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2899 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2901 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2903 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2904 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2907 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2909 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2911 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2914 if (is_pae_paging(vcpu)) {
2915 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2916 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2917 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2918 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2922 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2924 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2926 if (is_pae_paging(vcpu)) {
2927 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2928 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2929 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2930 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2933 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2936 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2938 struct kvm_vcpu *vcpu)
2940 struct vcpu_vmx *vmx = to_vmx(vcpu);
2942 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2943 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2944 if (!(cr0 & X86_CR0_PG)) {
2945 /* From paging/starting to nonpaging */
2946 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2947 CPU_BASED_CR3_STORE_EXITING);
2948 vcpu->arch.cr0 = cr0;
2949 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2950 } else if (!is_paging(vcpu)) {
2951 /* From nonpaging to paging */
2952 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2953 CPU_BASED_CR3_STORE_EXITING);
2954 vcpu->arch.cr0 = cr0;
2955 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2958 if (!(cr0 & X86_CR0_WP))
2959 *hw_cr0 &= ~X86_CR0_WP;
2962 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2964 struct vcpu_vmx *vmx = to_vmx(vcpu);
2965 unsigned long hw_cr0;
2967 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2968 if (enable_unrestricted_guest)
2969 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2971 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2973 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2976 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2980 #ifdef CONFIG_X86_64
2981 if (vcpu->arch.efer & EFER_LME) {
2982 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2984 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2989 if (enable_ept && !enable_unrestricted_guest)
2990 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2992 vmcs_writel(CR0_READ_SHADOW, cr0);
2993 vmcs_writel(GUEST_CR0, hw_cr0);
2994 vcpu->arch.cr0 = cr0;
2996 /* depends on vcpu->arch.cr0 to be set to a new value */
2997 vmx->emulation_required = emulation_required(vcpu);
3000 static int get_ept_level(struct kvm_vcpu *vcpu)
3002 /* Nested EPT currently only supports 4-level walks. */
3003 if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu)))
3005 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
3010 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
3012 u64 eptp = VMX_EPTP_MT_WB;
3014 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3016 if (enable_ept_ad_bits &&
3017 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3018 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3019 eptp |= (root_hpa & PAGE_MASK);
3024 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3026 struct kvm *kvm = vcpu->kvm;
3027 bool update_guest_cr3 = true;
3028 unsigned long guest_cr3;
3033 eptp = construct_eptp(vcpu, cr3);
3034 vmcs_write64(EPT_POINTER, eptp);
3036 if (kvm_x86_ops->tlb_remote_flush) {
3037 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3038 to_vmx(vcpu)->ept_pointer = eptp;
3039 to_kvm_vmx(kvm)->ept_pointers_match
3040 = EPT_POINTERS_CHECK;
3041 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3044 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3045 if (is_guest_mode(vcpu))
3046 update_guest_cr3 = false;
3047 else if (!enable_unrestricted_guest && !is_paging(vcpu))
3048 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3049 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3050 guest_cr3 = vcpu->arch.cr3;
3051 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3052 update_guest_cr3 = false;
3053 ept_load_pdptrs(vcpu);
3056 if (update_guest_cr3)
3057 vmcs_writel(GUEST_CR3, guest_cr3);
3060 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3062 struct vcpu_vmx *vmx = to_vmx(vcpu);
3064 * Pass through host's Machine Check Enable value to hw_cr4, which
3065 * is in force while we are in guest mode. Do not let guests control
3066 * this bit, even if host CR4.MCE == 0.
3068 unsigned long hw_cr4;
3070 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3071 if (enable_unrestricted_guest)
3072 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3073 else if (vmx->rmode.vm86_active)
3074 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3076 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3078 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3079 if (cr4 & X86_CR4_UMIP) {
3080 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3081 hw_cr4 &= ~X86_CR4_UMIP;
3082 } else if (!is_guest_mode(vcpu) ||
3083 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3084 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3088 if (cr4 & X86_CR4_VMXE) {
3090 * To use VMXON (and later other VMX instructions), a guest
3091 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3092 * So basically the check on whether to allow nested VMX
3093 * is here. We operate under the default treatment of SMM,
3094 * so VMX cannot be enabled under SMM.
3096 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3100 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3103 vcpu->arch.cr4 = cr4;
3105 if (!enable_unrestricted_guest) {
3107 if (!is_paging(vcpu)) {
3108 hw_cr4 &= ~X86_CR4_PAE;
3109 hw_cr4 |= X86_CR4_PSE;
3110 } else if (!(cr4 & X86_CR4_PAE)) {
3111 hw_cr4 &= ~X86_CR4_PAE;
3116 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3117 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3118 * to be manually disabled when guest switches to non-paging
3121 * If !enable_unrestricted_guest, the CPU is always running
3122 * with CR0.PG=1 and CR4 needs to be modified.
3123 * If enable_unrestricted_guest, the CPU automatically
3124 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3126 if (!is_paging(vcpu))
3127 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3130 vmcs_writel(CR4_READ_SHADOW, cr4);
3131 vmcs_writel(GUEST_CR4, hw_cr4);
3135 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3137 struct vcpu_vmx *vmx = to_vmx(vcpu);
3140 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3141 *var = vmx->rmode.segs[seg];
3142 if (seg == VCPU_SREG_TR
3143 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3145 var->base = vmx_read_guest_seg_base(vmx, seg);
3146 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3149 var->base = vmx_read_guest_seg_base(vmx, seg);
3150 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3151 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3152 ar = vmx_read_guest_seg_ar(vmx, seg);
3153 var->unusable = (ar >> 16) & 1;
3154 var->type = ar & 15;
3155 var->s = (ar >> 4) & 1;
3156 var->dpl = (ar >> 5) & 3;
3158 * Some userspaces do not preserve unusable property. Since usable
3159 * segment has to be present according to VMX spec we can use present
3160 * property to amend userspace bug by making unusable segment always
3161 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3162 * segment as unusable.
3164 var->present = !var->unusable;
3165 var->avl = (ar >> 12) & 1;
3166 var->l = (ar >> 13) & 1;
3167 var->db = (ar >> 14) & 1;
3168 var->g = (ar >> 15) & 1;
3171 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3173 struct kvm_segment s;
3175 if (to_vmx(vcpu)->rmode.vm86_active) {
3176 vmx_get_segment(vcpu, &s, seg);
3179 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3182 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3184 struct vcpu_vmx *vmx = to_vmx(vcpu);
3186 if (unlikely(vmx->rmode.vm86_active))
3189 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3190 return VMX_AR_DPL(ar);
3194 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3198 if (var->unusable || !var->present)
3201 ar = var->type & 15;
3202 ar |= (var->s & 1) << 4;
3203 ar |= (var->dpl & 3) << 5;
3204 ar |= (var->present & 1) << 7;
3205 ar |= (var->avl & 1) << 12;
3206 ar |= (var->l & 1) << 13;
3207 ar |= (var->db & 1) << 14;
3208 ar |= (var->g & 1) << 15;
3214 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3216 struct vcpu_vmx *vmx = to_vmx(vcpu);
3217 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3219 vmx_segment_cache_clear(vmx);
3221 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3222 vmx->rmode.segs[seg] = *var;
3223 if (seg == VCPU_SREG_TR)
3224 vmcs_write16(sf->selector, var->selector);
3226 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3230 vmcs_writel(sf->base, var->base);
3231 vmcs_write32(sf->limit, var->limit);
3232 vmcs_write16(sf->selector, var->selector);
3235 * Fix the "Accessed" bit in AR field of segment registers for older
3237 * IA32 arch specifies that at the time of processor reset the
3238 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3239 * is setting it to 0 in the userland code. This causes invalid guest
3240 * state vmexit when "unrestricted guest" mode is turned on.
3241 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3242 * tree. Newer qemu binaries with that qemu fix would not need this
3245 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3246 var->type |= 0x1; /* Accessed */
3248 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3251 vmx->emulation_required = emulation_required(vcpu);
3254 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3256 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3258 *db = (ar >> 14) & 1;
3259 *l = (ar >> 13) & 1;
3262 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3264 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3265 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3268 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3270 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3271 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3274 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3276 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3277 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3280 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3282 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3283 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3286 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3288 struct kvm_segment var;
3291 vmx_get_segment(vcpu, &var, seg);
3293 if (seg == VCPU_SREG_CS)
3295 ar = vmx_segment_access_rights(&var);
3297 if (var.base != (var.selector << 4))
3299 if (var.limit != 0xffff)
3307 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3309 struct kvm_segment cs;
3310 unsigned int cs_rpl;
3312 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3313 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3317 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3321 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3322 if (cs.dpl > cs_rpl)
3325 if (cs.dpl != cs_rpl)
3331 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3335 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3337 struct kvm_segment ss;
3338 unsigned int ss_rpl;
3340 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3341 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3345 if (ss.type != 3 && ss.type != 7)
3349 if (ss.dpl != ss_rpl) /* DPL != RPL */
3357 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3359 struct kvm_segment var;
3362 vmx_get_segment(vcpu, &var, seg);
3363 rpl = var.selector & SEGMENT_RPL_MASK;
3371 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3372 if (var.dpl < rpl) /* DPL < RPL */
3376 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3382 static bool tr_valid(struct kvm_vcpu *vcpu)
3384 struct kvm_segment tr;
3386 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3390 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3392 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3400 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3402 struct kvm_segment ldtr;
3404 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3408 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3418 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3420 struct kvm_segment cs, ss;
3422 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3423 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3425 return ((cs.selector & SEGMENT_RPL_MASK) ==
3426 (ss.selector & SEGMENT_RPL_MASK));
3430 * Check if guest state is valid. Returns true if valid, false if
3432 * We assume that registers are always usable
3434 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3436 if (enable_unrestricted_guest)
3439 /* real mode guest state checks */
3440 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3441 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3443 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3445 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3447 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3449 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3451 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3454 /* protected mode guest state checks */
3455 if (!cs_ss_rpl_check(vcpu))
3457 if (!code_segment_valid(vcpu))
3459 if (!stack_segment_valid(vcpu))
3461 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3463 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3465 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3467 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3469 if (!tr_valid(vcpu))
3471 if (!ldtr_valid(vcpu))
3475 * - Add checks on RIP
3476 * - Add checks on RFLAGS
3482 static int init_rmode_tss(struct kvm *kvm)
3488 idx = srcu_read_lock(&kvm->srcu);
3489 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3490 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3493 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3494 r = kvm_write_guest_page(kvm, fn++, &data,
3495 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3498 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3501 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3505 r = kvm_write_guest_page(kvm, fn, &data,
3506 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3509 srcu_read_unlock(&kvm->srcu, idx);
3513 static int init_rmode_identity_map(struct kvm *kvm)
3515 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3517 kvm_pfn_t identity_map_pfn;
3520 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3521 mutex_lock(&kvm->slots_lock);
3523 if (likely(kvm_vmx->ept_identity_pagetable_done))
3526 if (!kvm_vmx->ept_identity_map_addr)
3527 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3528 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3530 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3531 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3535 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3538 /* Set up identity-mapping pagetable for EPT in real mode */
3539 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3540 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3541 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3542 r = kvm_write_guest_page(kvm, identity_map_pfn,
3543 &tmp, i * sizeof(tmp), sizeof(tmp));
3547 kvm_vmx->ept_identity_pagetable_done = true;
3550 mutex_unlock(&kvm->slots_lock);
3554 static void seg_setup(int seg)
3556 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3559 vmcs_write16(sf->selector, 0);
3560 vmcs_writel(sf->base, 0);
3561 vmcs_write32(sf->limit, 0xffff);
3563 if (seg == VCPU_SREG_CS)
3564 ar |= 0x08; /* code segment */
3566 vmcs_write32(sf->ar_bytes, ar);
3569 static int alloc_apic_access_page(struct kvm *kvm)
3574 mutex_lock(&kvm->slots_lock);
3575 if (kvm->arch.apic_access_page_done)
3577 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3578 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3582 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3583 if (is_error_page(page)) {
3589 * Do not pin the page in memory, so that memory hot-unplug
3590 * is able to migrate it.
3593 kvm->arch.apic_access_page_done = true;
3595 mutex_unlock(&kvm->slots_lock);
3599 int allocate_vpid(void)
3605 spin_lock(&vmx_vpid_lock);
3606 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3607 if (vpid < VMX_NR_VPIDS)
3608 __set_bit(vpid, vmx_vpid_bitmap);
3611 spin_unlock(&vmx_vpid_lock);
3615 void free_vpid(int vpid)
3617 if (!enable_vpid || vpid == 0)
3619 spin_lock(&vmx_vpid_lock);
3620 __clear_bit(vpid, vmx_vpid_bitmap);
3621 spin_unlock(&vmx_vpid_lock);
3624 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3627 int f = sizeof(unsigned long);
3629 if (!cpu_has_vmx_msr_bitmap())
3632 if (static_branch_unlikely(&enable_evmcs))
3633 evmcs_touch_msr_bitmap();
3636 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3637 * have the write-low and read-high bitmap offsets the wrong way round.
3638 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3640 if (msr <= 0x1fff) {
3641 if (type & MSR_TYPE_R)
3643 __clear_bit(msr, msr_bitmap + 0x000 / f);
3645 if (type & MSR_TYPE_W)
3647 __clear_bit(msr, msr_bitmap + 0x800 / f);
3649 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3651 if (type & MSR_TYPE_R)
3653 __clear_bit(msr, msr_bitmap + 0x400 / f);
3655 if (type & MSR_TYPE_W)
3657 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3662 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3665 int f = sizeof(unsigned long);
3667 if (!cpu_has_vmx_msr_bitmap())
3670 if (static_branch_unlikely(&enable_evmcs))
3671 evmcs_touch_msr_bitmap();
3674 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3675 * have the write-low and read-high bitmap offsets the wrong way round.
3676 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3678 if (msr <= 0x1fff) {
3679 if (type & MSR_TYPE_R)
3681 __set_bit(msr, msr_bitmap + 0x000 / f);
3683 if (type & MSR_TYPE_W)
3685 __set_bit(msr, msr_bitmap + 0x800 / f);
3687 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3689 if (type & MSR_TYPE_R)
3691 __set_bit(msr, msr_bitmap + 0x400 / f);
3693 if (type & MSR_TYPE_W)
3695 __set_bit(msr, msr_bitmap + 0xc00 / f);
3700 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3701 u32 msr, int type, bool value)
3704 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3706 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3709 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3713 if (cpu_has_secondary_exec_ctrls() &&
3714 (secondary_exec_controls_get(to_vmx(vcpu)) &
3715 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3716 mode |= MSR_BITMAP_MODE_X2APIC;
3717 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3718 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3724 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3729 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3730 unsigned word = msr / BITS_PER_LONG;
3731 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3732 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3735 if (mode & MSR_BITMAP_MODE_X2APIC) {
3737 * TPR reads and writes can be virtualized even if virtual interrupt
3738 * delivery is not in use.
3740 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3741 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3742 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3743 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3744 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3749 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3751 struct vcpu_vmx *vmx = to_vmx(vcpu);
3752 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3753 u8 mode = vmx_msr_bitmap_mode(vcpu);
3754 u8 changed = mode ^ vmx->msr_bitmap_mode;
3759 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3760 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3762 vmx->msr_bitmap_mode = mode;
3765 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3767 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3768 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3771 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3773 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3775 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3777 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3779 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3780 vmx_set_intercept_for_msr(msr_bitmap,
3781 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3782 vmx_set_intercept_for_msr(msr_bitmap,
3783 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3787 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3789 struct vcpu_vmx *vmx = to_vmx(vcpu);
3794 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3795 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3796 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3799 rvi = vmx_get_rvi();
3801 vapic_page = vmx->nested.virtual_apic_map.hva;
3802 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3804 return ((rvi & 0xf0) > (vppr & 0xf0));
3807 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3811 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3813 if (vcpu->mode == IN_GUEST_MODE) {
3815 * The vector of interrupt to be delivered to vcpu had
3816 * been set in PIR before this function.
3818 * Following cases will be reached in this block, and
3819 * we always send a notification event in all cases as
3822 * Case 1: vcpu keeps in non-root mode. Sending a
3823 * notification event posts the interrupt to vcpu.
3825 * Case 2: vcpu exits to root mode and is still
3826 * runnable. PIR will be synced to vIRR before the
3827 * next vcpu entry. Sending a notification event in
3828 * this case has no effect, as vcpu is not in root
3831 * Case 3: vcpu exits to root mode and is blocked.
3832 * vcpu_block() has already synced PIR to vIRR and
3833 * never blocks vcpu if vIRR is not cleared. Therefore,
3834 * a blocked vcpu here does not wait for any requested
3835 * interrupts in PIR, and sending a notification event
3836 * which has no effect is safe here.
3839 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3846 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3849 struct vcpu_vmx *vmx = to_vmx(vcpu);
3851 if (is_guest_mode(vcpu) &&
3852 vector == vmx->nested.posted_intr_nv) {
3854 * If a posted intr is not recognized by hardware,
3855 * we will accomplish it in the next vmentry.
3857 vmx->nested.pi_pending = true;
3858 kvm_make_request(KVM_REQ_EVENT, vcpu);
3859 /* the PIR and ON have been set by L1. */
3860 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3861 kvm_vcpu_kick(vcpu);
3867 * Send interrupt to vcpu via posted interrupt way.
3868 * 1. If target vcpu is running(non-root mode), send posted interrupt
3869 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3870 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3871 * interrupt from PIR in next vmentry.
3873 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3875 struct vcpu_vmx *vmx = to_vmx(vcpu);
3878 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3882 if (!vcpu->arch.apicv_active)
3885 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3888 /* If a previous notification has sent the IPI, nothing to do. */
3889 if (pi_test_and_set_on(&vmx->pi_desc))
3892 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3893 kvm_vcpu_kick(vcpu);
3899 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3900 * will not change in the lifetime of the guest.
3901 * Note that host-state that does change is set elsewhere. E.g., host-state
3902 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3904 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3908 unsigned long cr0, cr3, cr4;
3911 WARN_ON(cr0 & X86_CR0_TS);
3912 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3915 * Save the most likely value for this task's CR3 in the VMCS.
3916 * We can't use __get_current_cr3_fast() because we're not atomic.
3919 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
3920 vmx->loaded_vmcs->host_state.cr3 = cr3;
3922 /* Save the most likely value for this task's CR4 in the VMCS. */
3923 cr4 = cr4_read_shadow();
3924 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
3925 vmx->loaded_vmcs->host_state.cr4 = cr4;
3927 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3928 #ifdef CONFIG_X86_64
3930 * Load null selectors, so we can avoid reloading them in
3931 * vmx_prepare_switch_to_host(), in case userspace uses
3932 * the null selectors too (the expected case).
3934 vmcs_write16(HOST_DS_SELECTOR, 0);
3935 vmcs_write16(HOST_ES_SELECTOR, 0);
3937 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3938 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3940 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3941 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3943 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
3945 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3947 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3948 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3949 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3950 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3952 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3953 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3954 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3957 if (cpu_has_load_ia32_efer())
3958 vmcs_write64(HOST_IA32_EFER, host_efer);
3961 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3963 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3965 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3966 if (is_guest_mode(&vmx->vcpu))
3967 vmx->vcpu.arch.cr4_guest_owned_bits &=
3968 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3969 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3972 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3974 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3976 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3977 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3980 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3982 if (!enable_preemption_timer)
3983 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3985 return pin_based_exec_ctrl;
3988 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3990 struct vcpu_vmx *vmx = to_vmx(vcpu);
3992 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3993 if (cpu_has_secondary_exec_ctrls()) {
3994 if (kvm_vcpu_apicv_active(vcpu))
3995 secondary_exec_controls_setbit(vmx,
3996 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3997 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3999 secondary_exec_controls_clearbit(vmx,
4000 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4001 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4004 if (cpu_has_vmx_msr_bitmap())
4005 vmx_update_msr_bitmap(vcpu);
4008 u32 vmx_exec_control(struct vcpu_vmx *vmx)
4010 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4012 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4013 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4015 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4016 exec_control &= ~CPU_BASED_TPR_SHADOW;
4017 #ifdef CONFIG_X86_64
4018 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4019 CPU_BASED_CR8_LOAD_EXITING;
4023 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4024 CPU_BASED_CR3_LOAD_EXITING |
4025 CPU_BASED_INVLPG_EXITING;
4026 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4027 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4028 CPU_BASED_MONITOR_EXITING);
4029 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4030 exec_control &= ~CPU_BASED_HLT_EXITING;
4031 return exec_control;
4035 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4037 struct kvm_vcpu *vcpu = &vmx->vcpu;
4039 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4041 if (pt_mode == PT_MODE_SYSTEM)
4042 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4043 if (!cpu_need_virtualize_apic_accesses(vcpu))
4044 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4046 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4048 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4049 enable_unrestricted_guest = 0;
4051 if (!enable_unrestricted_guest)
4052 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4053 if (kvm_pause_in_guest(vmx->vcpu.kvm))
4054 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4055 if (!kvm_vcpu_apicv_active(vcpu))
4056 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4057 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4058 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4060 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4061 * in vmx_set_cr4. */
4062 exec_control &= ~SECONDARY_EXEC_DESC;
4064 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4066 We can NOT enable shadow_vmcs here because we don't have yet
4069 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4072 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4074 if (vmx_xsaves_supported()) {
4075 /* Exposing XSAVES only when XSAVE is exposed */
4076 bool xsaves_enabled =
4077 boot_cpu_has(X86_FEATURE_XSAVE) &&
4078 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4079 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4081 vcpu->arch.xsaves_enabled = xsaves_enabled;
4083 if (!xsaves_enabled)
4084 exec_control &= ~SECONDARY_EXEC_XSAVES;
4088 vmx->nested.msrs.secondary_ctls_high |=
4089 SECONDARY_EXEC_XSAVES;
4091 vmx->nested.msrs.secondary_ctls_high &=
4092 ~SECONDARY_EXEC_XSAVES;
4096 if (vmx_rdtscp_supported()) {
4097 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4098 if (!rdtscp_enabled)
4099 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4103 vmx->nested.msrs.secondary_ctls_high |=
4104 SECONDARY_EXEC_RDTSCP;
4106 vmx->nested.msrs.secondary_ctls_high &=
4107 ~SECONDARY_EXEC_RDTSCP;
4111 if (vmx_invpcid_supported()) {
4112 /* Exposing INVPCID only when PCID is exposed */
4113 bool invpcid_enabled =
4114 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4115 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4117 if (!invpcid_enabled) {
4118 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4119 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4123 if (invpcid_enabled)
4124 vmx->nested.msrs.secondary_ctls_high |=
4125 SECONDARY_EXEC_ENABLE_INVPCID;
4127 vmx->nested.msrs.secondary_ctls_high &=
4128 ~SECONDARY_EXEC_ENABLE_INVPCID;
4132 if (vmx_rdrand_supported()) {
4133 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4135 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4139 vmx->nested.msrs.secondary_ctls_high |=
4140 SECONDARY_EXEC_RDRAND_EXITING;
4142 vmx->nested.msrs.secondary_ctls_high &=
4143 ~SECONDARY_EXEC_RDRAND_EXITING;
4147 if (vmx_rdseed_supported()) {
4148 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4150 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4154 vmx->nested.msrs.secondary_ctls_high |=
4155 SECONDARY_EXEC_RDSEED_EXITING;
4157 vmx->nested.msrs.secondary_ctls_high &=
4158 ~SECONDARY_EXEC_RDSEED_EXITING;
4162 if (vmx_waitpkg_supported()) {
4163 bool waitpkg_enabled =
4164 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4166 if (!waitpkg_enabled)
4167 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4170 if (waitpkg_enabled)
4171 vmx->nested.msrs.secondary_ctls_high |=
4172 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4174 vmx->nested.msrs.secondary_ctls_high &=
4175 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4179 vmx->secondary_exec_control = exec_control;
4182 static void ept_set_mmio_spte_mask(void)
4185 * EPT Misconfigurations can be generated if the value of bits 2:0
4186 * of an EPT paging-structure entry is 110b (write/execute).
4188 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4189 VMX_EPT_MISCONFIG_WX_VALUE, 0);
4192 #define VMX_XSS_EXIT_BITMAP 0
4195 * Noting that the initialization of Guest-state Area of VMCS is in
4198 static void init_vmcs(struct vcpu_vmx *vmx)
4201 nested_vmx_set_vmcs_shadowing_bitmap();
4203 if (cpu_has_vmx_msr_bitmap())
4204 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4206 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4209 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4211 exec_controls_set(vmx, vmx_exec_control(vmx));
4213 if (cpu_has_secondary_exec_ctrls()) {
4214 vmx_compute_secondary_exec_control(vmx);
4215 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4218 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4219 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4220 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4221 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4222 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4224 vmcs_write16(GUEST_INTR_STATUS, 0);
4226 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4227 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4230 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4231 vmcs_write32(PLE_GAP, ple_gap);
4232 vmx->ple_window = ple_window;
4233 vmx->ple_window_dirty = true;
4236 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4237 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4238 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4240 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4241 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4242 vmx_set_constant_host_state(vmx);
4243 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4244 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4246 if (cpu_has_vmx_vmfunc())
4247 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4249 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4250 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4251 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4252 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4253 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4255 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4256 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4258 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4260 /* 22.2.1, 20.8.1 */
4261 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4263 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4264 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4266 set_cr4_guest_host_mask(vmx);
4269 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4271 if (vmx_xsaves_supported())
4272 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4275 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4276 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4279 if (cpu_has_vmx_encls_vmexit())
4280 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4282 if (pt_mode == PT_MODE_HOST_GUEST) {
4283 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4284 /* Bit[6~0] are forced to 1, writes are ignored. */
4285 vmx->pt_desc.guest.output_mask = 0x7F;
4286 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4290 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4292 struct vcpu_vmx *vmx = to_vmx(vcpu);
4293 struct msr_data apic_base_msr;
4296 vmx->rmode.vm86_active = 0;
4299 vmx->msr_ia32_umwait_control = 0;
4301 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4302 vmx->hv_deadline_tsc = -1;
4303 kvm_set_cr8(vcpu, 0);
4306 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4307 MSR_IA32_APICBASE_ENABLE;
4308 if (kvm_vcpu_is_reset_bsp(vcpu))
4309 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4310 apic_base_msr.host_initiated = true;
4311 kvm_set_apic_base(vcpu, &apic_base_msr);
4314 vmx_segment_cache_clear(vmx);
4316 seg_setup(VCPU_SREG_CS);
4317 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4318 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4320 seg_setup(VCPU_SREG_DS);
4321 seg_setup(VCPU_SREG_ES);
4322 seg_setup(VCPU_SREG_FS);
4323 seg_setup(VCPU_SREG_GS);
4324 seg_setup(VCPU_SREG_SS);
4326 vmcs_write16(GUEST_TR_SELECTOR, 0);
4327 vmcs_writel(GUEST_TR_BASE, 0);
4328 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4329 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4331 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4332 vmcs_writel(GUEST_LDTR_BASE, 0);
4333 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4334 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4337 vmcs_write32(GUEST_SYSENTER_CS, 0);
4338 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4339 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4340 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4343 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4344 kvm_rip_write(vcpu, 0xfff0);
4346 vmcs_writel(GUEST_GDTR_BASE, 0);
4347 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4349 vmcs_writel(GUEST_IDTR_BASE, 0);
4350 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4352 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4353 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4354 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4355 if (kvm_mpx_supported())
4356 vmcs_write64(GUEST_BNDCFGS, 0);
4360 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4362 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4363 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4364 if (cpu_need_tpr_shadow(vcpu))
4365 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4366 __pa(vcpu->arch.apic->regs));
4367 vmcs_write32(TPR_THRESHOLD, 0);
4370 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4372 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4373 vmx->vcpu.arch.cr0 = cr0;
4374 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4375 vmx_set_cr4(vcpu, 0);
4376 vmx_set_efer(vcpu, 0);
4378 update_exception_bitmap(vcpu);
4380 vpid_sync_context(vmx->vpid);
4382 vmx_clear_hlt(vcpu);
4385 static void enable_irq_window(struct kvm_vcpu *vcpu)
4387 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4390 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4393 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4394 enable_irq_window(vcpu);
4398 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4401 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4403 struct vcpu_vmx *vmx = to_vmx(vcpu);
4405 int irq = vcpu->arch.interrupt.nr;
4407 trace_kvm_inj_virq(irq);
4409 ++vcpu->stat.irq_injections;
4410 if (vmx->rmode.vm86_active) {
4412 if (vcpu->arch.interrupt.soft)
4413 inc_eip = vcpu->arch.event_exit_inst_len;
4414 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4417 intr = irq | INTR_INFO_VALID_MASK;
4418 if (vcpu->arch.interrupt.soft) {
4419 intr |= INTR_TYPE_SOFT_INTR;
4420 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4421 vmx->vcpu.arch.event_exit_inst_len);
4423 intr |= INTR_TYPE_EXT_INTR;
4424 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4426 vmx_clear_hlt(vcpu);
4429 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4431 struct vcpu_vmx *vmx = to_vmx(vcpu);
4435 * Tracking the NMI-blocked state in software is built upon
4436 * finding the next open IRQ window. This, in turn, depends on
4437 * well-behaving guests: They have to keep IRQs disabled at
4438 * least as long as the NMI handler runs. Otherwise we may
4439 * cause NMI nesting, maybe breaking the guest. But as this is
4440 * highly unlikely, we can live with the residual risk.
4442 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4443 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4446 ++vcpu->stat.nmi_injections;
4447 vmx->loaded_vmcs->nmi_known_unmasked = false;
4449 if (vmx->rmode.vm86_active) {
4450 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4454 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4455 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4457 vmx_clear_hlt(vcpu);
4460 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4462 struct vcpu_vmx *vmx = to_vmx(vcpu);
4466 return vmx->loaded_vmcs->soft_vnmi_blocked;
4467 if (vmx->loaded_vmcs->nmi_known_unmasked)
4469 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4470 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4474 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4476 struct vcpu_vmx *vmx = to_vmx(vcpu);
4479 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4480 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4481 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4484 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4486 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4487 GUEST_INTR_STATE_NMI);
4489 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4490 GUEST_INTR_STATE_NMI);
4494 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4496 if (to_vmx(vcpu)->nested.nested_run_pending)
4500 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4503 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4504 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4505 | GUEST_INTR_STATE_NMI));
4508 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4510 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4511 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4512 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4513 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4516 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4520 if (enable_unrestricted_guest)
4523 mutex_lock(&kvm->slots_lock);
4524 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4526 mutex_unlock(&kvm->slots_lock);
4530 to_kvm_vmx(kvm)->tss_addr = addr;
4531 return init_rmode_tss(kvm);
4534 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4536 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4540 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4545 * Update instruction length as we may reinject the exception
4546 * from user space while in guest debugging mode.
4548 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4549 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4550 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4554 if (vcpu->guest_debug &
4555 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4572 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4573 int vec, u32 err_code)
4576 * Instruction with address size override prefix opcode 0x67
4577 * Cause the #SS fault with 0 error code in VM86 mode.
4579 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4580 if (kvm_emulate_instruction(vcpu, 0)) {
4581 if (vcpu->arch.halt_request) {
4582 vcpu->arch.halt_request = 0;
4583 return kvm_vcpu_halt(vcpu);
4591 * Forward all other exceptions that are valid in real mode.
4592 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4593 * the required debugging infrastructure rework.
4595 kvm_queue_exception(vcpu, vec);
4600 * Trigger machine check on the host. We assume all the MSRs are already set up
4601 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4602 * We pass a fake environment to the machine check handler because we want
4603 * the guest to be always treated like user space, no matter what context
4604 * it used internally.
4606 static void kvm_machine_check(void)
4608 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4609 struct pt_regs regs = {
4610 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4611 .flags = X86_EFLAGS_IF,
4614 do_machine_check(®s, 0);
4618 static int handle_machine_check(struct kvm_vcpu *vcpu)
4620 /* handled by vmx_vcpu_run() */
4624 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4626 struct vcpu_vmx *vmx = to_vmx(vcpu);
4627 struct kvm_run *kvm_run = vcpu->run;
4628 u32 intr_info, ex_no, error_code;
4629 unsigned long cr2, rip, dr6;
4632 vect_info = vmx->idt_vectoring_info;
4633 intr_info = vmx->exit_intr_info;
4635 if (is_machine_check(intr_info) || is_nmi(intr_info))
4636 return 1; /* handled by handle_exception_nmi_irqoff() */
4638 if (is_invalid_opcode(intr_info))
4639 return handle_ud(vcpu);
4642 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4643 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4645 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4646 WARN_ON_ONCE(!enable_vmware_backdoor);
4649 * VMware backdoor emulation on #GP interception only handles
4650 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4651 * error code on #GP.
4654 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4657 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4661 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4662 * MMIO, it is better to report an internal error.
4663 * See the comments in vmx_handle_exit.
4665 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4666 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4667 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4668 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4669 vcpu->run->internal.ndata = 3;
4670 vcpu->run->internal.data[0] = vect_info;
4671 vcpu->run->internal.data[1] = intr_info;
4672 vcpu->run->internal.data[2] = error_code;
4676 if (is_page_fault(intr_info)) {
4677 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4678 /* EPT won't cause page fault directly */
4679 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4680 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4683 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4685 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4686 return handle_rmode_exception(vcpu, ex_no, error_code);
4690 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4693 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4694 if (!(vcpu->guest_debug &
4695 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4696 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4697 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4698 if (is_icebp(intr_info))
4699 WARN_ON(!skip_emulated_instruction(vcpu));
4701 kvm_queue_exception(vcpu, DB_VECTOR);
4704 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4705 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4709 * Update instruction length as we may reinject #BP from
4710 * user space while in guest debugging mode. Reading it for
4711 * #DB as well causes no harm, it is not used in that case.
4713 vmx->vcpu.arch.event_exit_inst_len =
4714 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4715 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4716 rip = kvm_rip_read(vcpu);
4717 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4718 kvm_run->debug.arch.exception = ex_no;
4721 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4722 kvm_run->ex.exception = ex_no;
4723 kvm_run->ex.error_code = error_code;
4729 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4731 ++vcpu->stat.irq_exits;
4735 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4737 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4738 vcpu->mmio_needed = 0;
4742 static int handle_io(struct kvm_vcpu *vcpu)
4744 unsigned long exit_qualification;
4745 int size, in, string;
4748 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4749 string = (exit_qualification & 16) != 0;
4751 ++vcpu->stat.io_exits;
4754 return kvm_emulate_instruction(vcpu, 0);
4756 port = exit_qualification >> 16;
4757 size = (exit_qualification & 7) + 1;
4758 in = (exit_qualification & 8) != 0;
4760 return kvm_fast_pio(vcpu, size, port, in);
4764 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4767 * Patch in the VMCALL instruction:
4769 hypercall[0] = 0x0f;
4770 hypercall[1] = 0x01;
4771 hypercall[2] = 0xc1;
4774 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4775 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4777 if (is_guest_mode(vcpu)) {
4778 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4779 unsigned long orig_val = val;
4782 * We get here when L2 changed cr0 in a way that did not change
4783 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4784 * but did change L0 shadowed bits. So we first calculate the
4785 * effective cr0 value that L1 would like to write into the
4786 * hardware. It consists of the L2-owned bits from the new
4787 * value combined with the L1-owned bits from L1's guest_cr0.
4789 val = (val & ~vmcs12->cr0_guest_host_mask) |
4790 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4792 if (!nested_guest_cr0_valid(vcpu, val))
4795 if (kvm_set_cr0(vcpu, val))
4797 vmcs_writel(CR0_READ_SHADOW, orig_val);
4800 if (to_vmx(vcpu)->nested.vmxon &&
4801 !nested_host_cr0_valid(vcpu, val))
4804 return kvm_set_cr0(vcpu, val);
4808 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4810 if (is_guest_mode(vcpu)) {
4811 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4812 unsigned long orig_val = val;
4814 /* analogously to handle_set_cr0 */
4815 val = (val & ~vmcs12->cr4_guest_host_mask) |
4816 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4817 if (kvm_set_cr4(vcpu, val))
4819 vmcs_writel(CR4_READ_SHADOW, orig_val);
4822 return kvm_set_cr4(vcpu, val);
4825 static int handle_desc(struct kvm_vcpu *vcpu)
4827 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4828 return kvm_emulate_instruction(vcpu, 0);
4831 static int handle_cr(struct kvm_vcpu *vcpu)
4833 unsigned long exit_qualification, val;
4839 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4840 cr = exit_qualification & 15;
4841 reg = (exit_qualification >> 8) & 15;
4842 switch ((exit_qualification >> 4) & 3) {
4843 case 0: /* mov to cr */
4844 val = kvm_register_readl(vcpu, reg);
4845 trace_kvm_cr_write(cr, val);
4848 err = handle_set_cr0(vcpu, val);
4849 return kvm_complete_insn_gp(vcpu, err);
4851 WARN_ON_ONCE(enable_unrestricted_guest);
4852 err = kvm_set_cr3(vcpu, val);
4853 return kvm_complete_insn_gp(vcpu, err);
4855 err = handle_set_cr4(vcpu, val);
4856 return kvm_complete_insn_gp(vcpu, err);
4858 u8 cr8_prev = kvm_get_cr8(vcpu);
4860 err = kvm_set_cr8(vcpu, cr8);
4861 ret = kvm_complete_insn_gp(vcpu, err);
4862 if (lapic_in_kernel(vcpu))
4864 if (cr8_prev <= cr8)
4867 * TODO: we might be squashing a
4868 * KVM_GUESTDBG_SINGLESTEP-triggered
4869 * KVM_EXIT_DEBUG here.
4871 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4877 WARN_ONCE(1, "Guest should always own CR0.TS");
4878 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4879 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4880 return kvm_skip_emulated_instruction(vcpu);
4881 case 1: /*mov from cr*/
4884 WARN_ON_ONCE(enable_unrestricted_guest);
4885 val = kvm_read_cr3(vcpu);
4886 kvm_register_write(vcpu, reg, val);
4887 trace_kvm_cr_read(cr, val);
4888 return kvm_skip_emulated_instruction(vcpu);
4890 val = kvm_get_cr8(vcpu);
4891 kvm_register_write(vcpu, reg, val);
4892 trace_kvm_cr_read(cr, val);
4893 return kvm_skip_emulated_instruction(vcpu);
4897 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4898 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4899 kvm_lmsw(vcpu, val);
4901 return kvm_skip_emulated_instruction(vcpu);
4905 vcpu->run->exit_reason = 0;
4906 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4907 (int)(exit_qualification >> 4) & 3, cr);
4911 static int handle_dr(struct kvm_vcpu *vcpu)
4913 unsigned long exit_qualification;
4916 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4917 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4919 /* First, if DR does not exist, trigger UD */
4920 if (!kvm_require_dr(vcpu, dr))
4923 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4924 if (!kvm_require_cpl(vcpu, 0))
4926 dr7 = vmcs_readl(GUEST_DR7);
4929 * As the vm-exit takes precedence over the debug trap, we
4930 * need to emulate the latter, either for the host or the
4931 * guest debugging itself.
4933 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4934 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4935 vcpu->run->debug.arch.dr7 = dr7;
4936 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4937 vcpu->run->debug.arch.exception = DB_VECTOR;
4938 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4941 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4942 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4943 kvm_queue_exception(vcpu, DB_VECTOR);
4948 if (vcpu->guest_debug == 0) {
4949 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4952 * No more DR vmexits; force a reload of the debug registers
4953 * and reenter on this instruction. The next vmexit will
4954 * retrieve the full state of the debug registers.
4956 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4960 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4961 if (exit_qualification & TYPE_MOV_FROM_DR) {
4964 if (kvm_get_dr(vcpu, dr, &val))
4966 kvm_register_write(vcpu, reg, val);
4968 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4971 return kvm_skip_emulated_instruction(vcpu);
4974 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4976 return vcpu->arch.dr6;
4979 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4983 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4985 get_debugreg(vcpu->arch.db[0], 0);
4986 get_debugreg(vcpu->arch.db[1], 1);
4987 get_debugreg(vcpu->arch.db[2], 2);
4988 get_debugreg(vcpu->arch.db[3], 3);
4989 get_debugreg(vcpu->arch.dr6, 6);
4990 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4992 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4993 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4996 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4998 vmcs_writel(GUEST_DR7, val);
5001 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5003 kvm_apic_update_ppr(vcpu);
5007 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5009 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5011 kvm_make_request(KVM_REQ_EVENT, vcpu);
5013 ++vcpu->stat.irq_window_exits;
5017 static int handle_vmcall(struct kvm_vcpu *vcpu)
5019 return kvm_emulate_hypercall(vcpu);
5022 static int handle_invd(struct kvm_vcpu *vcpu)
5024 return kvm_emulate_instruction(vcpu, 0);
5027 static int handle_invlpg(struct kvm_vcpu *vcpu)
5029 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5031 kvm_mmu_invlpg(vcpu, exit_qualification);
5032 return kvm_skip_emulated_instruction(vcpu);
5035 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5039 err = kvm_rdpmc(vcpu);
5040 return kvm_complete_insn_gp(vcpu, err);
5043 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5045 return kvm_emulate_wbinvd(vcpu);
5048 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5050 u64 new_bv = kvm_read_edx_eax(vcpu);
5051 u32 index = kvm_rcx_read(vcpu);
5053 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5054 return kvm_skip_emulated_instruction(vcpu);
5058 static int handle_apic_access(struct kvm_vcpu *vcpu)
5060 if (likely(fasteoi)) {
5061 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5062 int access_type, offset;
5064 access_type = exit_qualification & APIC_ACCESS_TYPE;
5065 offset = exit_qualification & APIC_ACCESS_OFFSET;
5067 * Sane guest uses MOV to write EOI, with written value
5068 * not cared. So make a short-circuit here by avoiding
5069 * heavy instruction emulation.
5071 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5072 (offset == APIC_EOI)) {
5073 kvm_lapic_set_eoi(vcpu);
5074 return kvm_skip_emulated_instruction(vcpu);
5077 return kvm_emulate_instruction(vcpu, 0);
5080 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5082 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5083 int vector = exit_qualification & 0xff;
5085 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5086 kvm_apic_set_eoi_accelerated(vcpu, vector);
5090 static int handle_apic_write(struct kvm_vcpu *vcpu)
5092 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5093 u32 offset = exit_qualification & 0xfff;
5095 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5096 kvm_apic_write_nodecode(vcpu, offset);
5100 static int handle_task_switch(struct kvm_vcpu *vcpu)
5102 struct vcpu_vmx *vmx = to_vmx(vcpu);
5103 unsigned long exit_qualification;
5104 bool has_error_code = false;
5107 int reason, type, idt_v, idt_index;
5109 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5110 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5111 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5113 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5115 reason = (u32)exit_qualification >> 30;
5116 if (reason == TASK_SWITCH_GATE && idt_v) {
5118 case INTR_TYPE_NMI_INTR:
5119 vcpu->arch.nmi_injected = false;
5120 vmx_set_nmi_mask(vcpu, true);
5122 case INTR_TYPE_EXT_INTR:
5123 case INTR_TYPE_SOFT_INTR:
5124 kvm_clear_interrupt_queue(vcpu);
5126 case INTR_TYPE_HARD_EXCEPTION:
5127 if (vmx->idt_vectoring_info &
5128 VECTORING_INFO_DELIVER_CODE_MASK) {
5129 has_error_code = true;
5131 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5134 case INTR_TYPE_SOFT_EXCEPTION:
5135 kvm_clear_exception_queue(vcpu);
5141 tss_selector = exit_qualification;
5143 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5144 type != INTR_TYPE_EXT_INTR &&
5145 type != INTR_TYPE_NMI_INTR))
5146 WARN_ON(!skip_emulated_instruction(vcpu));
5149 * TODO: What about debug traps on tss switch?
5150 * Are we supposed to inject them and update dr6?
5152 return kvm_task_switch(vcpu, tss_selector,
5153 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5154 reason, has_error_code, error_code);
5157 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5159 unsigned long exit_qualification;
5163 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5166 * EPT violation happened while executing iret from NMI,
5167 * "blocked by NMI" bit has to be set before next VM entry.
5168 * There are errata that may cause this bit to not be set:
5171 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5173 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5174 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5176 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5177 trace_kvm_page_fault(gpa, exit_qualification);
5179 /* Is it a read fault? */
5180 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5181 ? PFERR_USER_MASK : 0;
5182 /* Is it a write fault? */
5183 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5184 ? PFERR_WRITE_MASK : 0;
5185 /* Is it a fetch fault? */
5186 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5187 ? PFERR_FETCH_MASK : 0;
5188 /* ept page table entry is present? */
5189 error_code |= (exit_qualification &
5190 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5191 EPT_VIOLATION_EXECUTABLE))
5192 ? PFERR_PRESENT_MASK : 0;
5194 error_code |= (exit_qualification & 0x100) != 0 ?
5195 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5197 vcpu->arch.exit_qualification = exit_qualification;
5198 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5201 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5206 * A nested guest cannot optimize MMIO vmexits, because we have an
5207 * nGPA here instead of the required GPA.
5209 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5210 if (!is_guest_mode(vcpu) &&
5211 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5212 trace_kvm_fast_mmio(gpa);
5213 return kvm_skip_emulated_instruction(vcpu);
5216 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5219 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5221 WARN_ON_ONCE(!enable_vnmi);
5222 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5223 ++vcpu->stat.nmi_window_exits;
5224 kvm_make_request(KVM_REQ_EVENT, vcpu);
5229 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5231 struct vcpu_vmx *vmx = to_vmx(vcpu);
5232 bool intr_window_requested;
5233 unsigned count = 130;
5236 * We should never reach the point where we are emulating L2
5237 * due to invalid guest state as that means we incorrectly
5238 * allowed a nested VMEntry with an invalid vmcs12.
5240 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5242 intr_window_requested = exec_controls_get(vmx) &
5243 CPU_BASED_INTR_WINDOW_EXITING;
5245 while (vmx->emulation_required && count-- != 0) {
5246 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5247 return handle_interrupt_window(&vmx->vcpu);
5249 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5252 if (!kvm_emulate_instruction(vcpu, 0))
5255 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5256 vcpu->arch.exception.pending) {
5257 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5258 vcpu->run->internal.suberror =
5259 KVM_INTERNAL_ERROR_EMULATION;
5260 vcpu->run->internal.ndata = 0;
5264 if (vcpu->arch.halt_request) {
5265 vcpu->arch.halt_request = 0;
5266 return kvm_vcpu_halt(vcpu);
5270 * Note, return 1 and not 0, vcpu_run() is responsible for
5271 * morphing the pending signal into the proper return code.
5273 if (signal_pending(current))
5283 static void grow_ple_window(struct kvm_vcpu *vcpu)
5285 struct vcpu_vmx *vmx = to_vmx(vcpu);
5286 unsigned int old = vmx->ple_window;
5288 vmx->ple_window = __grow_ple_window(old, ple_window,
5292 if (vmx->ple_window != old) {
5293 vmx->ple_window_dirty = true;
5294 trace_kvm_ple_window_update(vcpu->vcpu_id,
5295 vmx->ple_window, old);
5299 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5301 struct vcpu_vmx *vmx = to_vmx(vcpu);
5302 unsigned int old = vmx->ple_window;
5304 vmx->ple_window = __shrink_ple_window(old, ple_window,
5308 if (vmx->ple_window != old) {
5309 vmx->ple_window_dirty = true;
5310 trace_kvm_ple_window_update(vcpu->vcpu_id,
5311 vmx->ple_window, old);
5316 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5318 static void wakeup_handler(void)
5320 struct kvm_vcpu *vcpu;
5321 int cpu = smp_processor_id();
5323 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5324 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5325 blocked_vcpu_list) {
5326 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5328 if (pi_test_on(pi_desc) == 1)
5329 kvm_vcpu_kick(vcpu);
5331 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5334 static void vmx_enable_tdp(void)
5336 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5337 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5338 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5339 0ull, VMX_EPT_EXECUTABLE_MASK,
5340 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5341 VMX_EPT_RWX_MASK, 0ull);
5343 ept_set_mmio_spte_mask();
5348 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5349 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5351 static int handle_pause(struct kvm_vcpu *vcpu)
5353 if (!kvm_pause_in_guest(vcpu->kvm))
5354 grow_ple_window(vcpu);
5357 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5358 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5359 * never set PAUSE_EXITING and just set PLE if supported,
5360 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5362 kvm_vcpu_on_spin(vcpu, true);
5363 return kvm_skip_emulated_instruction(vcpu);
5366 static int handle_nop(struct kvm_vcpu *vcpu)
5368 return kvm_skip_emulated_instruction(vcpu);
5371 static int handle_mwait(struct kvm_vcpu *vcpu)
5373 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5374 return handle_nop(vcpu);
5377 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5379 kvm_queue_exception(vcpu, UD_VECTOR);
5383 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5388 static int handle_monitor(struct kvm_vcpu *vcpu)
5390 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5391 return handle_nop(vcpu);
5394 static int handle_invpcid(struct kvm_vcpu *vcpu)
5396 u32 vmx_instruction_info;
5400 struct x86_exception e;
5402 unsigned long roots_to_free = 0;
5408 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5409 kvm_queue_exception(vcpu, UD_VECTOR);
5413 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5414 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5417 kvm_inject_gp(vcpu, 0);
5421 /* According to the Intel instruction reference, the memory operand
5422 * is read even if it isn't needed (e.g., for type==all)
5424 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5425 vmx_instruction_info, false,
5426 sizeof(operand), &gva))
5429 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5430 kvm_inject_page_fault(vcpu, &e);
5434 if (operand.pcid >> 12 != 0) {
5435 kvm_inject_gp(vcpu, 0);
5439 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5442 case INVPCID_TYPE_INDIV_ADDR:
5443 if ((!pcid_enabled && (operand.pcid != 0)) ||
5444 is_noncanonical_address(operand.gla, vcpu)) {
5445 kvm_inject_gp(vcpu, 0);
5448 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5449 return kvm_skip_emulated_instruction(vcpu);
5451 case INVPCID_TYPE_SINGLE_CTXT:
5452 if (!pcid_enabled && (operand.pcid != 0)) {
5453 kvm_inject_gp(vcpu, 0);
5457 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5458 kvm_mmu_sync_roots(vcpu);
5459 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5462 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5463 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5465 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5467 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5469 * If neither the current cr3 nor any of the prev_roots use the
5470 * given PCID, then nothing needs to be done here because a
5471 * resync will happen anyway before switching to any other CR3.
5474 return kvm_skip_emulated_instruction(vcpu);
5476 case INVPCID_TYPE_ALL_NON_GLOBAL:
5478 * Currently, KVM doesn't mark global entries in the shadow
5479 * page tables, so a non-global flush just degenerates to a
5480 * global flush. If needed, we could optimize this later by
5481 * keeping track of global entries in shadow page tables.
5485 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5486 kvm_mmu_unload(vcpu);
5487 return kvm_skip_emulated_instruction(vcpu);
5490 BUG(); /* We have already checked above that type <= 3 */
5494 static int handle_pml_full(struct kvm_vcpu *vcpu)
5496 unsigned long exit_qualification;
5498 trace_kvm_pml_full(vcpu->vcpu_id);
5500 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5503 * PML buffer FULL happened while executing iret from NMI,
5504 * "blocked by NMI" bit has to be set before next VM entry.
5506 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5508 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5509 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5510 GUEST_INTR_STATE_NMI);
5513 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5514 * here.., and there's no userspace involvement needed for PML.
5519 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5521 struct vcpu_vmx *vmx = to_vmx(vcpu);
5523 if (!vmx->req_immediate_exit &&
5524 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5525 kvm_lapic_expired_hv_timer(vcpu);
5531 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5532 * are overwritten by nested_vmx_setup() when nested=1.
5534 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5536 kvm_queue_exception(vcpu, UD_VECTOR);
5540 static int handle_encls(struct kvm_vcpu *vcpu)
5543 * SGX virtualization is not yet supported. There is no software
5544 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5545 * to prevent the guest from executing ENCLS.
5547 kvm_queue_exception(vcpu, UD_VECTOR);
5552 * The exit handlers return 1 if the exit was handled fully and guest execution
5553 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5554 * to be done to userspace and return 0.
5556 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5557 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5558 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5559 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5560 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5561 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5562 [EXIT_REASON_CR_ACCESS] = handle_cr,
5563 [EXIT_REASON_DR_ACCESS] = handle_dr,
5564 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5565 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5566 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
5567 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
5568 [EXIT_REASON_HLT] = kvm_emulate_halt,
5569 [EXIT_REASON_INVD] = handle_invd,
5570 [EXIT_REASON_INVLPG] = handle_invlpg,
5571 [EXIT_REASON_RDPMC] = handle_rdpmc,
5572 [EXIT_REASON_VMCALL] = handle_vmcall,
5573 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5574 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5575 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5576 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5577 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5578 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5579 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5580 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5581 [EXIT_REASON_VMON] = handle_vmx_instruction,
5582 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5583 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5584 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5585 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5586 [EXIT_REASON_WBINVD] = handle_wbinvd,
5587 [EXIT_REASON_XSETBV] = handle_xsetbv,
5588 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5589 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5590 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5591 [EXIT_REASON_LDTR_TR] = handle_desc,
5592 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5593 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5594 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5595 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5596 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5597 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5598 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5599 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5600 [EXIT_REASON_RDRAND] = handle_invalid_op,
5601 [EXIT_REASON_RDSEED] = handle_invalid_op,
5602 [EXIT_REASON_PML_FULL] = handle_pml_full,
5603 [EXIT_REASON_INVPCID] = handle_invpcid,
5604 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5605 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5606 [EXIT_REASON_ENCLS] = handle_encls,
5609 static const int kvm_vmx_max_exit_handlers =
5610 ARRAY_SIZE(kvm_vmx_exit_handlers);
5612 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5614 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5615 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5618 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5621 __free_page(vmx->pml_pg);
5626 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5628 struct vcpu_vmx *vmx = to_vmx(vcpu);
5632 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5634 /* Do nothing if PML buffer is empty */
5635 if (pml_idx == (PML_ENTITY_NUM - 1))
5638 /* PML index always points to next available PML buffer entity */
5639 if (pml_idx >= PML_ENTITY_NUM)
5644 pml_buf = page_address(vmx->pml_pg);
5645 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5648 gpa = pml_buf[pml_idx];
5649 WARN_ON(gpa & (PAGE_SIZE - 1));
5650 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5653 /* reset PML index */
5654 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5658 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5659 * Called before reporting dirty_bitmap to userspace.
5661 static void kvm_flush_pml_buffers(struct kvm *kvm)
5664 struct kvm_vcpu *vcpu;
5666 * We only need to kick vcpu out of guest mode here, as PML buffer
5667 * is flushed at beginning of all VMEXITs, and it's obvious that only
5668 * vcpus running in guest are possible to have unflushed GPAs in PML
5671 kvm_for_each_vcpu(i, vcpu, kvm)
5672 kvm_vcpu_kick(vcpu);
5675 static void vmx_dump_sel(char *name, uint32_t sel)
5677 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5678 name, vmcs_read16(sel),
5679 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5680 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5681 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5684 static void vmx_dump_dtsel(char *name, uint32_t limit)
5686 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5687 name, vmcs_read32(limit),
5688 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5691 void dump_vmcs(void)
5693 u32 vmentry_ctl, vmexit_ctl;
5694 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5699 if (!dump_invalid_vmcs) {
5700 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5704 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5705 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5706 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5707 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5708 cr4 = vmcs_readl(GUEST_CR4);
5709 efer = vmcs_read64(GUEST_IA32_EFER);
5710 secondary_exec_control = 0;
5711 if (cpu_has_secondary_exec_ctrls())
5712 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5714 pr_err("*** Guest State ***\n");
5715 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5716 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5717 vmcs_readl(CR0_GUEST_HOST_MASK));
5718 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5719 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5720 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5721 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5722 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5724 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5725 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5726 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5727 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5729 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5730 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5731 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5732 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5733 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5734 vmcs_readl(GUEST_SYSENTER_ESP),
5735 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5736 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5737 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5738 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5739 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5740 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5741 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5742 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5743 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5744 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5745 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5746 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5747 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5748 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5749 efer, vmcs_read64(GUEST_IA32_PAT));
5750 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5751 vmcs_read64(GUEST_IA32_DEBUGCTL),
5752 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5753 if (cpu_has_load_perf_global_ctrl() &&
5754 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5755 pr_err("PerfGlobCtl = 0x%016llx\n",
5756 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5757 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5758 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5759 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5760 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5761 vmcs_read32(GUEST_ACTIVITY_STATE));
5762 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5763 pr_err("InterruptStatus = %04x\n",
5764 vmcs_read16(GUEST_INTR_STATUS));
5766 pr_err("*** Host State ***\n");
5767 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5768 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5769 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5770 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5771 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5772 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5773 vmcs_read16(HOST_TR_SELECTOR));
5774 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5775 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5776 vmcs_readl(HOST_TR_BASE));
5777 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5778 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5779 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5780 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5781 vmcs_readl(HOST_CR4));
5782 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5783 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5784 vmcs_read32(HOST_IA32_SYSENTER_CS),
5785 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5786 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5787 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5788 vmcs_read64(HOST_IA32_EFER),
5789 vmcs_read64(HOST_IA32_PAT));
5790 if (cpu_has_load_perf_global_ctrl() &&
5791 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5792 pr_err("PerfGlobCtl = 0x%016llx\n",
5793 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5795 pr_err("*** Control State ***\n");
5796 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5797 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5798 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5799 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5800 vmcs_read32(EXCEPTION_BITMAP),
5801 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5802 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5803 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5804 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5805 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5806 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5807 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5808 vmcs_read32(VM_EXIT_INTR_INFO),
5809 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5810 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5811 pr_err(" reason=%08x qualification=%016lx\n",
5812 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5813 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5814 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5815 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5816 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5817 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5818 pr_err("TSC Multiplier = 0x%016llx\n",
5819 vmcs_read64(TSC_MULTIPLIER));
5820 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5821 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5822 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5823 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5825 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5826 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5827 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5828 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5830 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5831 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5832 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5833 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5834 n = vmcs_read32(CR3_TARGET_COUNT);
5835 for (i = 0; i + 1 < n; i += 4)
5836 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5837 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5838 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5840 pr_err("CR3 target%u=%016lx\n",
5841 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5842 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5843 pr_err("PLE Gap=%08x Window=%08x\n",
5844 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5845 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5846 pr_err("Virtual processor ID = 0x%04x\n",
5847 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5851 * The guest has exited. See if we can fix it or if we need userspace
5854 static int vmx_handle_exit(struct kvm_vcpu *vcpu,
5855 enum exit_fastpath_completion exit_fastpath)
5857 struct vcpu_vmx *vmx = to_vmx(vcpu);
5858 u32 exit_reason = vmx->exit_reason;
5859 u32 vectoring_info = vmx->idt_vectoring_info;
5861 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5864 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5865 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5866 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5867 * mode as if vcpus is in root mode, the PML buffer must has been
5871 vmx_flush_pml_buffer(vcpu);
5873 /* If guest state is invalid, start emulating */
5874 if (vmx->emulation_required)
5875 return handle_invalid_guest_state(vcpu);
5877 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5878 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5880 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5882 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5883 vcpu->run->fail_entry.hardware_entry_failure_reason
5888 if (unlikely(vmx->fail)) {
5890 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5891 vcpu->run->fail_entry.hardware_entry_failure_reason
5892 = vmcs_read32(VM_INSTRUCTION_ERROR);
5898 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5899 * delivery event since it indicates guest is accessing MMIO.
5900 * The vm-exit can be triggered again after return to guest that
5901 * will cause infinite loop.
5903 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5904 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5905 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5906 exit_reason != EXIT_REASON_PML_FULL &&
5907 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5908 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5909 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5910 vcpu->run->internal.ndata = 3;
5911 vcpu->run->internal.data[0] = vectoring_info;
5912 vcpu->run->internal.data[1] = exit_reason;
5913 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5914 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5915 vcpu->run->internal.ndata++;
5916 vcpu->run->internal.data[3] =
5917 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5922 if (unlikely(!enable_vnmi &&
5923 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5924 if (vmx_interrupt_allowed(vcpu)) {
5925 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5926 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5927 vcpu->arch.nmi_pending) {
5929 * This CPU don't support us in finding the end of an
5930 * NMI-blocked window if the guest runs with IRQs
5931 * disabled. So we pull the trigger after 1 s of
5932 * futile waiting, but inform the user about this.
5934 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5935 "state on VCPU %d after 1 s timeout\n",
5936 __func__, vcpu->vcpu_id);
5937 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5941 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5942 kvm_skip_emulated_instruction(vcpu);
5946 if (exit_reason >= kvm_vmx_max_exit_handlers)
5947 goto unexpected_vmexit;
5948 #ifdef CONFIG_RETPOLINE
5949 if (exit_reason == EXIT_REASON_MSR_WRITE)
5950 return kvm_emulate_wrmsr(vcpu);
5951 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5952 return handle_preemption_timer(vcpu);
5953 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
5954 return handle_interrupt_window(vcpu);
5955 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5956 return handle_external_interrupt(vcpu);
5957 else if (exit_reason == EXIT_REASON_HLT)
5958 return kvm_emulate_halt(vcpu);
5959 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5960 return handle_ept_misconfig(vcpu);
5963 exit_reason = array_index_nospec(exit_reason,
5964 kvm_vmx_max_exit_handlers);
5965 if (!kvm_vmx_exit_handlers[exit_reason])
5966 goto unexpected_vmexit;
5968 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5971 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
5973 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5974 vcpu->run->internal.suberror =
5975 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5976 vcpu->run->internal.ndata = 1;
5977 vcpu->run->internal.data[0] = exit_reason;
5982 * Software based L1D cache flush which is used when microcode providing
5983 * the cache control MSR is not loaded.
5985 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5986 * flush it is required to read in 64 KiB because the replacement algorithm
5987 * is not exactly LRU. This could be sized at runtime via topology
5988 * information but as all relevant affected CPUs have 32KiB L1D cache size
5989 * there is no point in doing so.
5991 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5993 int size = PAGE_SIZE << L1D_CACHE_ORDER;
5996 * This code is only executed when the the flush mode is 'cond' or
5999 if (static_branch_likely(&vmx_l1d_flush_cond)) {
6003 * Clear the per-vcpu flush bit, it gets set again
6004 * either from vcpu_run() or from one of the unsafe
6007 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6008 vcpu->arch.l1tf_flush_l1d = false;
6011 * Clear the per-cpu flush bit, it gets set again from
6012 * the interrupt handlers.
6014 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6015 kvm_clear_cpu_l1tf_flush_l1d();
6021 vcpu->stat.l1d_flush++;
6023 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6024 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6029 /* First ensure the pages are in the TLB */
6030 "xorl %%eax, %%eax\n"
6031 ".Lpopulate_tlb:\n\t"
6032 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6033 "addl $4096, %%eax\n\t"
6034 "cmpl %%eax, %[size]\n\t"
6035 "jne .Lpopulate_tlb\n\t"
6036 "xorl %%eax, %%eax\n\t"
6038 /* Now fill the cache */
6039 "xorl %%eax, %%eax\n"
6041 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6042 "addl $64, %%eax\n\t"
6043 "cmpl %%eax, %[size]\n\t"
6044 "jne .Lfill_cache\n\t"
6046 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6048 : "eax", "ebx", "ecx", "edx");
6051 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6053 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6056 if (is_guest_mode(vcpu) &&
6057 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6060 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6061 if (is_guest_mode(vcpu))
6062 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6064 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6067 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6069 struct vcpu_vmx *vmx = to_vmx(vcpu);
6070 u32 sec_exec_control;
6072 if (!lapic_in_kernel(vcpu))
6075 if (!flexpriority_enabled &&
6076 !cpu_has_vmx_virtualize_x2apic_mode())
6079 /* Postpone execution until vmcs01 is the current VMCS. */
6080 if (is_guest_mode(vcpu)) {
6081 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6085 sec_exec_control = secondary_exec_controls_get(vmx);
6086 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6087 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6089 switch (kvm_get_apic_mode(vcpu)) {
6090 case LAPIC_MODE_INVALID:
6091 WARN_ONCE(true, "Invalid local APIC state");
6092 case LAPIC_MODE_DISABLED:
6094 case LAPIC_MODE_XAPIC:
6095 if (flexpriority_enabled) {
6097 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6098 vmx_flush_tlb(vcpu, true);
6101 case LAPIC_MODE_X2APIC:
6102 if (cpu_has_vmx_virtualize_x2apic_mode())
6104 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6107 secondary_exec_controls_set(vmx, sec_exec_control);
6109 vmx_update_msr_bitmap(vcpu);
6112 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6114 if (!is_guest_mode(vcpu)) {
6115 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6116 vmx_flush_tlb(vcpu, true);
6120 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6128 status = vmcs_read16(GUEST_INTR_STATUS);
6130 if (max_isr != old) {
6132 status |= max_isr << 8;
6133 vmcs_write16(GUEST_INTR_STATUS, status);
6137 static void vmx_set_rvi(int vector)
6145 status = vmcs_read16(GUEST_INTR_STATUS);
6146 old = (u8)status & 0xff;
6147 if ((u8)vector != old) {
6149 status |= (u8)vector;
6150 vmcs_write16(GUEST_INTR_STATUS, status);
6154 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6157 * When running L2, updating RVI is only relevant when
6158 * vmcs12 virtual-interrupt-delivery enabled.
6159 * However, it can be enabled only when L1 also
6160 * intercepts external-interrupts and in that case
6161 * we should not update vmcs02 RVI but instead intercept
6162 * interrupt. Therefore, do nothing when running L2.
6164 if (!is_guest_mode(vcpu))
6165 vmx_set_rvi(max_irr);
6168 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6170 struct vcpu_vmx *vmx = to_vmx(vcpu);
6172 bool max_irr_updated;
6174 WARN_ON(!vcpu->arch.apicv_active);
6175 if (pi_test_on(&vmx->pi_desc)) {
6176 pi_clear_on(&vmx->pi_desc);
6178 * IOMMU can write to PID.ON, so the barrier matters even on UP.
6179 * But on x86 this is just a compiler barrier anyway.
6181 smp_mb__after_atomic();
6183 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6186 * If we are running L2 and L1 has a new pending interrupt
6187 * which can be injected, we should re-evaluate
6188 * what should be done with this new L1 interrupt.
6189 * If L1 intercepts external-interrupts, we should
6190 * exit from L2 to L1. Otherwise, interrupt should be
6191 * delivered directly to L2.
6193 if (is_guest_mode(vcpu) && max_irr_updated) {
6194 if (nested_exit_on_intr(vcpu))
6195 kvm_vcpu_exiting_guest_mode(vcpu);
6197 kvm_make_request(KVM_REQ_EVENT, vcpu);
6200 max_irr = kvm_lapic_find_highest_irr(vcpu);
6202 vmx_hwapic_irr_update(vcpu, max_irr);
6206 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6208 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6210 return pi_test_on(pi_desc) ||
6211 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6214 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6216 if (!kvm_vcpu_apicv_active(vcpu))
6219 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6220 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6221 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6222 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6225 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6227 struct vcpu_vmx *vmx = to_vmx(vcpu);
6229 pi_clear_on(&vmx->pi_desc);
6230 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6233 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6235 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6237 /* if exit due to PF check for async PF */
6238 if (is_page_fault(vmx->exit_intr_info))
6239 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6241 /* Handle machine checks before interrupts are enabled */
6242 if (is_machine_check(vmx->exit_intr_info))
6243 kvm_machine_check();
6245 /* We need to handle NMIs before interrupts are enabled */
6246 if (is_nmi(vmx->exit_intr_info)) {
6247 kvm_before_interrupt(&vmx->vcpu);
6249 kvm_after_interrupt(&vmx->vcpu);
6253 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6255 unsigned int vector;
6256 unsigned long entry;
6257 #ifdef CONFIG_X86_64
6263 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6264 if (WARN_ONCE(!is_external_intr(intr_info),
6265 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6268 vector = intr_info & INTR_INFO_VECTOR_MASK;
6269 desc = (gate_desc *)host_idt_base + vector;
6270 entry = gate_offset(desc);
6272 kvm_before_interrupt(vcpu);
6275 #ifdef CONFIG_X86_64
6276 "mov %%" _ASM_SP ", %[sp]\n\t"
6277 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6282 __ASM_SIZE(push) " $%c[cs]\n\t"
6285 #ifdef CONFIG_X86_64
6290 THUNK_TARGET(entry),
6291 [ss]"i"(__KERNEL_DS),
6292 [cs]"i"(__KERNEL_CS)
6295 kvm_after_interrupt(vcpu);
6297 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6299 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6300 enum exit_fastpath_completion *exit_fastpath)
6302 struct vcpu_vmx *vmx = to_vmx(vcpu);
6304 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6305 handle_external_interrupt_irqoff(vcpu);
6306 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6307 handle_exception_nmi_irqoff(vmx);
6308 else if (!is_guest_mode(vcpu) &&
6309 vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6310 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
6313 static bool vmx_has_emulated_msr(int index)
6316 case MSR_IA32_SMBASE:
6318 * We cannot do SMM unless we can run the guest in big
6321 return enable_unrestricted_guest || emulate_invalid_guest_state;
6322 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6324 case MSR_AMD64_VIRT_SPEC_CTRL:
6325 /* This is AMD only. */
6332 static bool vmx_pt_supported(void)
6334 return pt_mode == PT_MODE_HOST_GUEST;
6337 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6342 bool idtv_info_valid;
6344 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6347 if (vmx->loaded_vmcs->nmi_known_unmasked)
6350 * Can't use vmx->exit_intr_info since we're not sure what
6351 * the exit reason is.
6353 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6354 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6355 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6357 * SDM 3: 27.7.1.2 (September 2008)
6358 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6359 * a guest IRET fault.
6360 * SDM 3: 23.2.2 (September 2008)
6361 * Bit 12 is undefined in any of the following cases:
6362 * If the VM exit sets the valid bit in the IDT-vectoring
6363 * information field.
6364 * If the VM exit is due to a double fault.
6366 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6367 vector != DF_VECTOR && !idtv_info_valid)
6368 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6369 GUEST_INTR_STATE_NMI);
6371 vmx->loaded_vmcs->nmi_known_unmasked =
6372 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6373 & GUEST_INTR_STATE_NMI);
6374 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6375 vmx->loaded_vmcs->vnmi_blocked_time +=
6376 ktime_to_ns(ktime_sub(ktime_get(),
6377 vmx->loaded_vmcs->entry_time));
6380 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6381 u32 idt_vectoring_info,
6382 int instr_len_field,
6383 int error_code_field)
6387 bool idtv_info_valid;
6389 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6391 vcpu->arch.nmi_injected = false;
6392 kvm_clear_exception_queue(vcpu);
6393 kvm_clear_interrupt_queue(vcpu);
6395 if (!idtv_info_valid)
6398 kvm_make_request(KVM_REQ_EVENT, vcpu);
6400 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6401 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6404 case INTR_TYPE_NMI_INTR:
6405 vcpu->arch.nmi_injected = true;
6407 * SDM 3: 27.7.1.2 (September 2008)
6408 * Clear bit "block by NMI" before VM entry if a NMI
6411 vmx_set_nmi_mask(vcpu, false);
6413 case INTR_TYPE_SOFT_EXCEPTION:
6414 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6416 case INTR_TYPE_HARD_EXCEPTION:
6417 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6418 u32 err = vmcs_read32(error_code_field);
6419 kvm_requeue_exception_e(vcpu, vector, err);
6421 kvm_requeue_exception(vcpu, vector);
6423 case INTR_TYPE_SOFT_INTR:
6424 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6426 case INTR_TYPE_EXT_INTR:
6427 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6434 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6436 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6437 VM_EXIT_INSTRUCTION_LEN,
6438 IDT_VECTORING_ERROR_CODE);
6441 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6443 __vmx_complete_interrupts(vcpu,
6444 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6445 VM_ENTRY_INSTRUCTION_LEN,
6446 VM_ENTRY_EXCEPTION_ERROR_CODE);
6448 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6451 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6454 struct perf_guest_switch_msr *msrs;
6456 msrs = perf_guest_get_msrs(&nr_msrs);
6461 for (i = 0; i < nr_msrs; i++)
6462 if (msrs[i].host == msrs[i].guest)
6463 clear_atomic_switch_msr(vmx, msrs[i].msr);
6465 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6466 msrs[i].host, false);
6469 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6471 u32 host_umwait_control;
6473 if (!vmx_has_waitpkg(vmx))
6476 host_umwait_control = get_umwait_control_msr();
6478 if (vmx->msr_ia32_umwait_control != host_umwait_control)
6479 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6480 vmx->msr_ia32_umwait_control,
6481 host_umwait_control, false);
6483 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6486 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6488 struct vcpu_vmx *vmx = to_vmx(vcpu);
6492 if (vmx->req_immediate_exit) {
6493 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6494 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6495 } else if (vmx->hv_deadline_tsc != -1) {
6497 if (vmx->hv_deadline_tsc > tscl)
6498 /* set_hv_timer ensures the delta fits in 32-bits */
6499 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6500 cpu_preemption_timer_multi);
6504 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6505 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6506 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6507 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6508 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6512 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6514 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6515 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6516 vmcs_writel(HOST_RSP, host_rsp);
6520 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6522 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6524 struct vcpu_vmx *vmx = to_vmx(vcpu);
6525 unsigned long cr3, cr4;
6527 /* Record the guest's net vcpu time for enforced NMI injections. */
6528 if (unlikely(!enable_vnmi &&
6529 vmx->loaded_vmcs->soft_vnmi_blocked))
6530 vmx->loaded_vmcs->entry_time = ktime_get();
6532 /* Don't enter VMX if guest state is invalid, let the exit handler
6533 start emulation until we arrive back to a valid state */
6534 if (vmx->emulation_required)
6537 if (vmx->ple_window_dirty) {
6538 vmx->ple_window_dirty = false;
6539 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6543 * We did this in prepare_switch_to_guest, because it needs to
6544 * be within srcu_read_lock.
6546 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6548 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6549 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6550 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6551 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6553 cr3 = __get_current_cr3_fast();
6554 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6555 vmcs_writel(HOST_CR3, cr3);
6556 vmx->loaded_vmcs->host_state.cr3 = cr3;
6559 cr4 = cr4_read_shadow();
6560 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6561 vmcs_writel(HOST_CR4, cr4);
6562 vmx->loaded_vmcs->host_state.cr4 = cr4;
6565 /* When single-stepping over STI and MOV SS, we must clear the
6566 * corresponding interruptibility bits in the guest state. Otherwise
6567 * vmentry fails as it then expects bit 14 (BS) in pending debug
6568 * exceptions being set, but that's not correct for the guest debugging
6570 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6571 vmx_set_interrupt_shadow(vcpu, 0);
6573 kvm_load_guest_xsave_state(vcpu);
6575 if (static_cpu_has(X86_FEATURE_PKU) &&
6576 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6577 vcpu->arch.pkru != vmx->host_pkru)
6578 __write_pkru(vcpu->arch.pkru);
6580 pt_guest_enter(vmx);
6582 atomic_switch_perf_msrs(vmx);
6583 atomic_switch_umwait_control_msr(vmx);
6585 if (enable_preemption_timer)
6586 vmx_update_hv_timer(vcpu);
6588 if (lapic_in_kernel(vcpu) &&
6589 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6590 kvm_wait_lapic_expire(vcpu);
6593 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6594 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6595 * is no need to worry about the conditional branch over the wrmsr
6596 * being speculatively taken.
6598 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6600 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6601 if (static_branch_unlikely(&vmx_l1d_should_flush))
6602 vmx_l1d_flush(vcpu);
6603 else if (static_branch_unlikely(&mds_user_clear))
6604 mds_clear_cpu_buffers();
6606 if (vcpu->arch.cr2 != read_cr2())
6607 write_cr2(vcpu->arch.cr2);
6609 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6610 vmx->loaded_vmcs->launched);
6612 vcpu->arch.cr2 = read_cr2();
6615 * We do not use IBRS in the kernel. If this vCPU has used the
6616 * SPEC_CTRL MSR it may have left it on; save the value and
6617 * turn it off. This is much more efficient than blindly adding
6618 * it to the atomic save/restore list. Especially as the former
6619 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6621 * For non-nested case:
6622 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6626 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6629 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6630 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6632 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6634 /* All fields are clean at this point */
6635 if (static_branch_unlikely(&enable_evmcs))
6636 current_evmcs->hv_clean_fields |=
6637 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6639 if (static_branch_unlikely(&enable_evmcs))
6640 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6642 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6643 if (vmx->host_debugctlmsr)
6644 update_debugctlmsr(vmx->host_debugctlmsr);
6646 #ifndef CONFIG_X86_64
6648 * The sysexit path does not restore ds/es, so we must set them to
6649 * a reasonable value ourselves.
6651 * We can't defer this to vmx_prepare_switch_to_host() since that
6652 * function may be executed in interrupt context, which saves and
6653 * restore segments around it, nullifying its effect.
6655 loadsegment(ds, __USER_DS);
6656 loadsegment(es, __USER_DS);
6659 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6660 | (1 << VCPU_EXREG_RFLAGS)
6661 | (1 << VCPU_EXREG_PDPTR)
6662 | (1 << VCPU_EXREG_SEGMENTS)
6663 | (1 << VCPU_EXREG_CR3));
6664 vcpu->arch.regs_dirty = 0;
6669 * eager fpu is enabled if PKEY is supported and CR4 is switched
6670 * back on host, so it is safe to read guest PKRU from current
6673 if (static_cpu_has(X86_FEATURE_PKU) &&
6674 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6675 vcpu->arch.pkru = rdpkru();
6676 if (vcpu->arch.pkru != vmx->host_pkru)
6677 __write_pkru(vmx->host_pkru);
6680 kvm_load_host_xsave_state(vcpu);
6682 vmx->nested.nested_run_pending = 0;
6683 vmx->idt_vectoring_info = 0;
6685 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6686 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6687 kvm_machine_check();
6689 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6692 vmx->loaded_vmcs->launched = 1;
6693 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6695 vmx_recover_nmi_blocking(vmx);
6696 vmx_complete_interrupts(vmx);
6699 static struct kvm *vmx_vm_alloc(void)
6701 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6702 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6704 return &kvm_vmx->kvm;
6707 static void vmx_vm_free(struct kvm *kvm)
6709 kfree(kvm->arch.hyperv.hv_pa_pg);
6710 vfree(to_kvm_vmx(kvm));
6713 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6715 struct vcpu_vmx *vmx = to_vmx(vcpu);
6718 vmx_destroy_pml_buffer(vmx);
6719 free_vpid(vmx->vpid);
6720 nested_vmx_free_vcpu(vcpu);
6721 free_loaded_vmcs(vmx->loaded_vmcs);
6724 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6726 struct vcpu_vmx *vmx;
6727 unsigned long *msr_bitmap;
6730 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6735 vmx->vpid = allocate_vpid();
6738 * If PML is turned on, failure on enabling PML just results in failure
6739 * of creating the vcpu, therefore we can simplify PML logic (by
6740 * avoiding dealing with cases, such as enabling PML partially on vcpus
6741 * for the guest), etc.
6744 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6749 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
6751 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6752 u32 index = vmx_msr_index[i];
6753 u32 data_low, data_high;
6756 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6758 if (wrmsr_safe(index, data_low, data_high) < 0)
6761 vmx->guest_msrs[j].index = i;
6762 vmx->guest_msrs[j].data = 0;
6764 case MSR_IA32_TSX_CTRL:
6766 * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6767 * let's avoid changing CPUID bits under the host
6770 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6773 vmx->guest_msrs[j].mask = -1ull;
6779 err = alloc_loaded_vmcs(&vmx->vmcs01);
6783 msr_bitmap = vmx->vmcs01.msr_bitmap;
6784 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6785 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6786 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6787 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6788 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6789 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6790 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6791 if (kvm_cstate_in_guest(vcpu->kvm)) {
6792 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6793 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6794 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6795 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6797 vmx->msr_bitmap_mode = 0;
6799 vmx->loaded_vmcs = &vmx->vmcs01;
6801 vmx_vcpu_load(vcpu, cpu);
6806 if (cpu_need_virtualize_apic_accesses(vcpu)) {
6807 err = alloc_apic_access_page(vcpu->kvm);
6812 if (enable_ept && !enable_unrestricted_guest) {
6813 err = init_rmode_identity_map(vcpu->kvm);
6819 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6820 vmx_capability.ept);
6822 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6824 vmx->nested.posted_intr_nv = -1;
6825 vmx->nested.current_vmptr = -1ull;
6827 vcpu->arch.microcode_version = 0x100000000ULL;
6828 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6831 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6832 * or POSTED_INTR_WAKEUP_VECTOR.
6834 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6835 vmx->pi_desc.sn = 1;
6837 vmx->ept_pointer = INVALID_PAGE;
6842 free_loaded_vmcs(vmx->loaded_vmcs);
6844 vmx_destroy_pml_buffer(vmx);
6846 free_vpid(vmx->vpid);
6850 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6851 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6853 static int vmx_vm_init(struct kvm *kvm)
6855 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6858 kvm->arch.pause_in_guest = true;
6860 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6861 switch (l1tf_mitigation) {
6862 case L1TF_MITIGATION_OFF:
6863 case L1TF_MITIGATION_FLUSH_NOWARN:
6864 /* 'I explicitly don't care' is set */
6866 case L1TF_MITIGATION_FLUSH:
6867 case L1TF_MITIGATION_FLUSH_NOSMT:
6868 case L1TF_MITIGATION_FULL:
6870 * Warn upon starting the first VM in a potentially
6871 * insecure environment.
6873 if (sched_smt_active())
6874 pr_warn_once(L1TF_MSG_SMT);
6875 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6876 pr_warn_once(L1TF_MSG_L1D);
6878 case L1TF_MITIGATION_FULL_FORCE:
6879 /* Flush is enforced */
6883 kvm_apicv_init(kvm, enable_apicv);
6887 static int __init vmx_check_processor_compat(void)
6889 struct vmcs_config vmcs_conf;
6890 struct vmx_capability vmx_cap;
6892 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6893 !this_cpu_has(X86_FEATURE_VMX)) {
6894 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6898 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6901 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6902 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6903 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6904 smp_processor_id());
6910 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6915 /* For VT-d and EPT combination
6916 * 1. MMIO: always map as UC
6918 * a. VT-d without snooping control feature: can't guarantee the
6919 * result, try to trust guest.
6920 * b. VT-d with snooping control feature: snooping control feature of
6921 * VT-d engine can guarantee the cache correctness. Just set it
6922 * to WB to keep consistent with host. So the same as item 3.
6923 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6924 * consistent with host MTRR
6927 cache = MTRR_TYPE_UNCACHABLE;
6931 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6932 ipat = VMX_EPT_IPAT_BIT;
6933 cache = MTRR_TYPE_WRBACK;
6937 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6938 ipat = VMX_EPT_IPAT_BIT;
6939 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6940 cache = MTRR_TYPE_WRBACK;
6942 cache = MTRR_TYPE_UNCACHABLE;
6946 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6949 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6952 static int vmx_get_lpage_level(void)
6954 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6955 return PT_DIRECTORY_LEVEL;
6957 /* For shadow and EPT supported 1GB page */
6958 return PT_PDPE_LEVEL;
6961 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6964 * These bits in the secondary execution controls field
6965 * are dynamic, the others are mostly based on the hypervisor
6966 * architecture and the guest's CPUID. Do not touch the
6970 SECONDARY_EXEC_SHADOW_VMCS |
6971 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6972 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6973 SECONDARY_EXEC_DESC;
6975 u32 new_ctl = vmx->secondary_exec_control;
6976 u32 cur_ctl = secondary_exec_controls_get(vmx);
6978 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6982 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6983 * (indicating "allowed-1") if they are supported in the guest's CPUID.
6985 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6987 struct vcpu_vmx *vmx = to_vmx(vcpu);
6988 struct kvm_cpuid_entry2 *entry;
6990 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6991 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6993 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6994 if (entry && (entry->_reg & (_cpuid_mask))) \
6995 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6998 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6999 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME));
7000 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME));
7001 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC));
7002 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE));
7003 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE));
7004 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE));
7005 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE));
7006 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE));
7007 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR));
7008 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7009 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX));
7010 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX));
7011 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID));
7012 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE));
7014 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7015 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE));
7016 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP));
7017 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP));
7018 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU));
7019 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP));
7020 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57));
7022 #undef cr4_fixed1_update
7025 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7027 struct vcpu_vmx *vmx = to_vmx(vcpu);
7029 if (kvm_mpx_supported()) {
7030 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7033 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7034 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7036 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7037 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7042 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7044 struct vcpu_vmx *vmx = to_vmx(vcpu);
7045 struct kvm_cpuid_entry2 *best = NULL;
7048 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7049 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7052 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7053 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7054 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7055 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7058 /* Get the number of configurable Address Ranges for filtering */
7059 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7060 PT_CAP_num_address_ranges);
7062 /* Initialize and clear the no dependency bits */
7063 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7064 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7067 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7068 * will inject an #GP
7070 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7071 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7074 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7075 * PSBFreq can be set
7077 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7078 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7079 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7082 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7083 * MTCFreq can be set
7085 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7086 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7087 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7089 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7090 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7091 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7094 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7095 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7096 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7098 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7099 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7100 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7102 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7103 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7104 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7106 /* unmask address range configure area */
7107 for (i = 0; i < vmx->pt_desc.addr_range; i++)
7108 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7111 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7113 struct vcpu_vmx *vmx = to_vmx(vcpu);
7115 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7116 vcpu->arch.xsaves_enabled = false;
7118 if (cpu_has_secondary_exec_ctrls()) {
7119 vmx_compute_secondary_exec_control(vmx);
7120 vmcs_set_secondary_exec_control(vmx);
7123 if (nested_vmx_allowed(vcpu))
7124 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7125 FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7126 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7128 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7129 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7130 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7132 if (nested_vmx_allowed(vcpu)) {
7133 nested_vmx_cr_fixed1_bits_update(vcpu);
7134 nested_vmx_entry_exit_ctls_update(vcpu);
7137 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7138 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7139 update_intel_pt_cfg(vcpu);
7141 if (boot_cpu_has(X86_FEATURE_RTM)) {
7142 struct shared_msr_entry *msr;
7143 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7145 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7146 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7151 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7153 if (func == 1 && nested)
7154 entry->ecx |= feature_bit(VMX);
7157 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7159 to_vmx(vcpu)->req_immediate_exit = true;
7162 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7163 struct x86_instruction_info *info)
7165 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7166 unsigned short port;
7170 if (info->intercept == x86_intercept_in ||
7171 info->intercept == x86_intercept_ins) {
7172 port = info->src_val;
7173 size = info->dst_bytes;
7175 port = info->dst_val;
7176 size = info->src_bytes;
7180 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7181 * VM-exits depend on the 'unconditional IO exiting' VM-execution
7184 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7186 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7187 intercept = nested_cpu_has(vmcs12,
7188 CPU_BASED_UNCOND_IO_EXITING);
7190 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7192 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7193 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7196 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7197 struct x86_instruction_info *info,
7198 enum x86_intercept_stage stage)
7200 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7201 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7203 switch (info->intercept) {
7205 * RDPID causes #UD if disabled through secondary execution controls.
7206 * Because it is marked as EmulateOnUD, we need to intercept it here.
7208 case x86_intercept_rdtscp:
7209 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7210 ctxt->exception.vector = UD_VECTOR;
7211 ctxt->exception.error_code_valid = false;
7212 return X86EMUL_PROPAGATE_FAULT;
7216 case x86_intercept_in:
7217 case x86_intercept_ins:
7218 case x86_intercept_out:
7219 case x86_intercept_outs:
7220 return vmx_check_intercept_io(vcpu, info);
7222 case x86_intercept_lgdt:
7223 case x86_intercept_lidt:
7224 case x86_intercept_lldt:
7225 case x86_intercept_ltr:
7226 case x86_intercept_sgdt:
7227 case x86_intercept_sidt:
7228 case x86_intercept_sldt:
7229 case x86_intercept_str:
7230 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7231 return X86EMUL_CONTINUE;
7233 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7236 /* TODO: check more intercepts... */
7241 return X86EMUL_UNHANDLEABLE;
7244 #ifdef CONFIG_X86_64
7245 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7246 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7247 u64 divisor, u64 *result)
7249 u64 low = a << shift, high = a >> (64 - shift);
7251 /* To avoid the overflow on divq */
7252 if (high >= divisor)
7255 /* Low hold the result, high hold rem which is discarded */
7256 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7257 "rm" (divisor), "0" (low), "1" (high));
7263 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7266 struct vcpu_vmx *vmx;
7267 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7268 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7270 if (kvm_mwait_in_guest(vcpu->kvm) ||
7271 kvm_can_post_timer_interrupt(vcpu))
7276 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7277 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7278 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7279 ktimer->timer_advance_ns);
7281 if (delta_tsc > lapic_timer_advance_cycles)
7282 delta_tsc -= lapic_timer_advance_cycles;
7286 /* Convert to host delta tsc if tsc scaling is enabled */
7287 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7288 delta_tsc && u64_shl_div_u64(delta_tsc,
7289 kvm_tsc_scaling_ratio_frac_bits,
7290 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7294 * If the delta tsc can't fit in the 32 bit after the multi shift,
7295 * we can't use the preemption timer.
7296 * It's possible that it fits on later vmentries, but checking
7297 * on every vmentry is costly so we just use an hrtimer.
7299 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7302 vmx->hv_deadline_tsc = tscl + delta_tsc;
7303 *expired = !delta_tsc;
7307 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7309 to_vmx(vcpu)->hv_deadline_tsc = -1;
7313 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7315 if (!kvm_pause_in_guest(vcpu->kvm))
7316 shrink_ple_window(vcpu);
7319 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7320 struct kvm_memory_slot *slot)
7322 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7323 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7326 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7327 struct kvm_memory_slot *slot)
7329 kvm_mmu_slot_set_dirty(kvm, slot);
7332 static void vmx_flush_log_dirty(struct kvm *kvm)
7334 kvm_flush_pml_buffers(kvm);
7337 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7339 struct vmcs12 *vmcs12;
7340 struct vcpu_vmx *vmx = to_vmx(vcpu);
7343 if (is_guest_mode(vcpu)) {
7344 WARN_ON_ONCE(vmx->nested.pml_full);
7347 * Check if PML is enabled for the nested guest.
7348 * Whether eptp bit 6 is set is already checked
7349 * as part of A/D emulation.
7351 vmcs12 = get_vmcs12(vcpu);
7352 if (!nested_cpu_has_pml(vmcs12))
7355 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7356 vmx->nested.pml_full = true;
7360 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7361 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7363 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7364 offset_in_page(dst), sizeof(gpa)))
7367 vmcs12->guest_pml_index--;
7373 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7374 struct kvm_memory_slot *memslot,
7375 gfn_t offset, unsigned long mask)
7377 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7380 static void __pi_post_block(struct kvm_vcpu *vcpu)
7382 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7383 struct pi_desc old, new;
7387 old.control = new.control = pi_desc->control;
7388 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7389 "Wakeup handler not enabled while the VCPU is blocked\n");
7391 dest = cpu_physical_id(vcpu->cpu);
7393 if (x2apic_enabled())
7396 new.ndst = (dest << 8) & 0xFF00;
7398 /* set 'NV' to 'notification vector' */
7399 new.nv = POSTED_INTR_VECTOR;
7400 } while (cmpxchg64(&pi_desc->control, old.control,
7401 new.control) != old.control);
7403 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7404 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7405 list_del(&vcpu->blocked_vcpu_list);
7406 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7407 vcpu->pre_pcpu = -1;
7412 * This routine does the following things for vCPU which is going
7413 * to be blocked if VT-d PI is enabled.
7414 * - Store the vCPU to the wakeup list, so when interrupts happen
7415 * we can find the right vCPU to wake up.
7416 * - Change the Posted-interrupt descriptor as below:
7417 * 'NDST' <-- vcpu->pre_pcpu
7418 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7419 * - If 'ON' is set during this process, which means at least one
7420 * interrupt is posted for this vCPU, we cannot block it, in
7421 * this case, return 1, otherwise, return 0.
7424 static int pi_pre_block(struct kvm_vcpu *vcpu)
7427 struct pi_desc old, new;
7428 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7430 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7431 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7432 !kvm_vcpu_apicv_active(vcpu))
7435 WARN_ON(irqs_disabled());
7436 local_irq_disable();
7437 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7438 vcpu->pre_pcpu = vcpu->cpu;
7439 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7440 list_add_tail(&vcpu->blocked_vcpu_list,
7441 &per_cpu(blocked_vcpu_on_cpu,
7443 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7447 old.control = new.control = pi_desc->control;
7449 WARN((pi_desc->sn == 1),
7450 "Warning: SN field of posted-interrupts "
7451 "is set before blocking\n");
7454 * Since vCPU can be preempted during this process,
7455 * vcpu->cpu could be different with pre_pcpu, we
7456 * need to set pre_pcpu as the destination of wakeup
7457 * notification event, then we can find the right vCPU
7458 * to wakeup in wakeup handler if interrupts happen
7459 * when the vCPU is in blocked state.
7461 dest = cpu_physical_id(vcpu->pre_pcpu);
7463 if (x2apic_enabled())
7466 new.ndst = (dest << 8) & 0xFF00;
7468 /* set 'NV' to 'wakeup vector' */
7469 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7470 } while (cmpxchg64(&pi_desc->control, old.control,
7471 new.control) != old.control);
7473 /* We should not block the vCPU if an interrupt is posted for it. */
7474 if (pi_test_on(pi_desc) == 1)
7475 __pi_post_block(vcpu);
7478 return (vcpu->pre_pcpu == -1);
7481 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7483 if (pi_pre_block(vcpu))
7486 if (kvm_lapic_hv_timer_in_use(vcpu))
7487 kvm_lapic_switch_to_sw_timer(vcpu);
7492 static void pi_post_block(struct kvm_vcpu *vcpu)
7494 if (vcpu->pre_pcpu == -1)
7497 WARN_ON(irqs_disabled());
7498 local_irq_disable();
7499 __pi_post_block(vcpu);
7503 static void vmx_post_block(struct kvm_vcpu *vcpu)
7505 if (kvm_x86_ops->set_hv_timer)
7506 kvm_lapic_switch_to_hv_timer(vcpu);
7508 pi_post_block(vcpu);
7512 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7515 * @host_irq: host irq of the interrupt
7516 * @guest_irq: gsi of the interrupt
7517 * @set: set or unset PI
7518 * returns 0 on success, < 0 on failure
7520 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7521 uint32_t guest_irq, bool set)
7523 struct kvm_kernel_irq_routing_entry *e;
7524 struct kvm_irq_routing_table *irq_rt;
7525 struct kvm_lapic_irq irq;
7526 struct kvm_vcpu *vcpu;
7527 struct vcpu_data vcpu_info;
7530 if (!kvm_arch_has_assigned_device(kvm) ||
7531 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7532 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7535 idx = srcu_read_lock(&kvm->irq_srcu);
7536 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7537 if (guest_irq >= irq_rt->nr_rt_entries ||
7538 hlist_empty(&irq_rt->map[guest_irq])) {
7539 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7540 guest_irq, irq_rt->nr_rt_entries);
7544 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7545 if (e->type != KVM_IRQ_ROUTING_MSI)
7548 * VT-d PI cannot support posting multicast/broadcast
7549 * interrupts to a vCPU, we still use interrupt remapping
7550 * for these kind of interrupts.
7552 * For lowest-priority interrupts, we only support
7553 * those with single CPU as the destination, e.g. user
7554 * configures the interrupts via /proc/irq or uses
7555 * irqbalance to make the interrupts single-CPU.
7557 * We will support full lowest-priority interrupt later.
7559 * In addition, we can only inject generic interrupts using
7560 * the PI mechanism, refuse to route others through it.
7563 kvm_set_msi_irq(kvm, e, &irq);
7564 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7565 !kvm_irq_is_postable(&irq)) {
7567 * Make sure the IRTE is in remapped mode if
7568 * we don't handle it in posted mode.
7570 ret = irq_set_vcpu_affinity(host_irq, NULL);
7573 "failed to back to remapped mode, irq: %u\n",
7581 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7582 vcpu_info.vector = irq.vector;
7584 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7585 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7588 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7590 ret = irq_set_vcpu_affinity(host_irq, NULL);
7593 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7601 srcu_read_unlock(&kvm->irq_srcu, idx);
7605 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7607 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7608 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7609 FEAT_CTL_LMCE_ENABLED;
7611 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7612 ~FEAT_CTL_LMCE_ENABLED;
7615 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7617 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7618 if (to_vmx(vcpu)->nested.nested_run_pending)
7623 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7625 struct vcpu_vmx *vmx = to_vmx(vcpu);
7627 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7628 if (vmx->nested.smm.guest_mode)
7629 nested_vmx_vmexit(vcpu, -1, 0, 0);
7631 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7632 vmx->nested.vmxon = false;
7633 vmx_clear_hlt(vcpu);
7637 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7639 struct vcpu_vmx *vmx = to_vmx(vcpu);
7642 if (vmx->nested.smm.vmxon) {
7643 vmx->nested.vmxon = true;
7644 vmx->nested.smm.vmxon = false;
7647 if (vmx->nested.smm.guest_mode) {
7648 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7652 vmx->nested.smm.guest_mode = false;
7657 static int enable_smi_window(struct kvm_vcpu *vcpu)
7662 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7667 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7669 return to_vmx(vcpu)->nested.vmxon;
7672 static __init int hardware_setup(void)
7674 unsigned long host_bndcfgs;
7678 rdmsrl_safe(MSR_EFER, &host_efer);
7681 host_idt_base = dt.address;
7683 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7684 kvm_define_shared_msr(i, vmx_msr_index[i]);
7686 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7689 if (boot_cpu_has(X86_FEATURE_NX))
7690 kvm_enable_efer_bits(EFER_NX);
7692 if (boot_cpu_has(X86_FEATURE_MPX)) {
7693 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7694 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7697 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7698 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7701 if (!cpu_has_vmx_ept() ||
7702 !cpu_has_vmx_ept_4levels() ||
7703 !cpu_has_vmx_ept_mt_wb() ||
7704 !cpu_has_vmx_invept_global())
7707 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7708 enable_ept_ad_bits = 0;
7710 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7711 enable_unrestricted_guest = 0;
7713 if (!cpu_has_vmx_flexpriority())
7714 flexpriority_enabled = 0;
7716 if (!cpu_has_virtual_nmis())
7720 * set_apic_access_page_addr() is used to reload apic access
7721 * page upon invalidation. No need to do anything if not
7722 * using the APIC_ACCESS_ADDR VMCS field.
7724 if (!flexpriority_enabled)
7725 kvm_x86_ops->set_apic_access_page_addr = NULL;
7727 if (!cpu_has_vmx_tpr_shadow())
7728 kvm_x86_ops->update_cr8_intercept = NULL;
7730 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7731 kvm_disable_largepages();
7733 #if IS_ENABLED(CONFIG_HYPERV)
7734 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7736 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7737 kvm_x86_ops->tlb_remote_flush_with_range =
7738 hv_remote_flush_tlb_with_range;
7742 if (!cpu_has_vmx_ple()) {
7745 ple_window_grow = 0;
7747 ple_window_shrink = 0;
7750 if (!cpu_has_vmx_apicv()) {
7752 kvm_x86_ops->sync_pir_to_irr = NULL;
7755 if (cpu_has_vmx_tsc_scaling()) {
7756 kvm_has_tsc_control = true;
7757 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7758 kvm_tsc_scaling_ratio_frac_bits = 48;
7761 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7769 * Only enable PML when hardware supports PML feature, and both EPT
7770 * and EPT A/D bit features are enabled -- PML depends on them to work.
7772 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7776 kvm_x86_ops->slot_enable_log_dirty = NULL;
7777 kvm_x86_ops->slot_disable_log_dirty = NULL;
7778 kvm_x86_ops->flush_log_dirty = NULL;
7779 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7782 if (!cpu_has_vmx_preemption_timer())
7783 enable_preemption_timer = false;
7785 if (enable_preemption_timer) {
7786 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7789 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7790 cpu_preemption_timer_multi =
7791 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7794 use_timer_freq = (u64)tsc_khz * 1000;
7795 use_timer_freq >>= cpu_preemption_timer_multi;
7798 * KVM "disables" the preemption timer by setting it to its max
7799 * value. Don't use the timer if it might cause spurious exits
7800 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7802 if (use_timer_freq > 0xffffffffu / 10)
7803 enable_preemption_timer = false;
7806 if (!enable_preemption_timer) {
7807 kvm_x86_ops->set_hv_timer = NULL;
7808 kvm_x86_ops->cancel_hv_timer = NULL;
7809 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7812 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7814 kvm_mce_cap_supported |= MCG_LMCE_P;
7816 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7818 if (!enable_ept || !cpu_has_vmx_intel_pt())
7819 pt_mode = PT_MODE_SYSTEM;
7822 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7823 vmx_capability.ept);
7825 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7830 r = alloc_kvm_area();
7832 nested_vmx_hardware_unsetup();
7836 static __exit void hardware_unsetup(void)
7839 nested_vmx_hardware_unsetup();
7844 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7846 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7847 BIT(APICV_INHIBIT_REASON_HYPERV);
7849 return supported & BIT(bit);
7852 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7853 .cpu_has_kvm_support = cpu_has_kvm_support,
7854 .disabled_by_bios = vmx_disabled_by_bios,
7855 .hardware_setup = hardware_setup,
7856 .hardware_unsetup = hardware_unsetup,
7857 .check_processor_compatibility = vmx_check_processor_compat,
7858 .hardware_enable = hardware_enable,
7859 .hardware_disable = hardware_disable,
7860 .cpu_has_accelerated_tpr = report_flexpriority,
7861 .has_emulated_msr = vmx_has_emulated_msr,
7863 .vm_init = vmx_vm_init,
7864 .vm_alloc = vmx_vm_alloc,
7865 .vm_free = vmx_vm_free,
7867 .vcpu_create = vmx_create_vcpu,
7868 .vcpu_free = vmx_free_vcpu,
7869 .vcpu_reset = vmx_vcpu_reset,
7871 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7872 .vcpu_load = vmx_vcpu_load,
7873 .vcpu_put = vmx_vcpu_put,
7875 .update_bp_intercept = update_exception_bitmap,
7876 .get_msr_feature = vmx_get_msr_feature,
7877 .get_msr = vmx_get_msr,
7878 .set_msr = vmx_set_msr,
7879 .get_segment_base = vmx_get_segment_base,
7880 .get_segment = vmx_get_segment,
7881 .set_segment = vmx_set_segment,
7882 .get_cpl = vmx_get_cpl,
7883 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7884 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7885 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7886 .set_cr0 = vmx_set_cr0,
7887 .set_cr3 = vmx_set_cr3,
7888 .set_cr4 = vmx_set_cr4,
7889 .set_efer = vmx_set_efer,
7890 .get_idt = vmx_get_idt,
7891 .set_idt = vmx_set_idt,
7892 .get_gdt = vmx_get_gdt,
7893 .set_gdt = vmx_set_gdt,
7894 .get_dr6 = vmx_get_dr6,
7895 .set_dr6 = vmx_set_dr6,
7896 .set_dr7 = vmx_set_dr7,
7897 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7898 .cache_reg = vmx_cache_reg,
7899 .get_rflags = vmx_get_rflags,
7900 .set_rflags = vmx_set_rflags,
7902 .tlb_flush = vmx_flush_tlb,
7903 .tlb_flush_gva = vmx_flush_tlb_gva,
7905 .run = vmx_vcpu_run,
7906 .handle_exit = vmx_handle_exit,
7907 .skip_emulated_instruction = vmx_skip_emulated_instruction,
7908 .update_emulated_instruction = vmx_update_emulated_instruction,
7909 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7910 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7911 .patch_hypercall = vmx_patch_hypercall,
7912 .set_irq = vmx_inject_irq,
7913 .set_nmi = vmx_inject_nmi,
7914 .queue_exception = vmx_queue_exception,
7915 .cancel_injection = vmx_cancel_injection,
7916 .interrupt_allowed = vmx_interrupt_allowed,
7917 .nmi_allowed = vmx_nmi_allowed,
7918 .get_nmi_mask = vmx_get_nmi_mask,
7919 .set_nmi_mask = vmx_set_nmi_mask,
7920 .enable_nmi_window = enable_nmi_window,
7921 .enable_irq_window = enable_irq_window,
7922 .update_cr8_intercept = update_cr8_intercept,
7923 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7924 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7925 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7926 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7927 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7928 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7929 .hwapic_irr_update = vmx_hwapic_irr_update,
7930 .hwapic_isr_update = vmx_hwapic_isr_update,
7931 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7932 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7933 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7934 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7936 .set_tss_addr = vmx_set_tss_addr,
7937 .set_identity_map_addr = vmx_set_identity_map_addr,
7938 .get_tdp_level = get_ept_level,
7939 .get_mt_mask = vmx_get_mt_mask,
7941 .get_exit_info = vmx_get_exit_info,
7943 .get_lpage_level = vmx_get_lpage_level,
7945 .cpuid_update = vmx_cpuid_update,
7947 .rdtscp_supported = vmx_rdtscp_supported,
7948 .invpcid_supported = vmx_invpcid_supported,
7950 .set_supported_cpuid = vmx_set_supported_cpuid,
7952 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7954 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7955 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7957 .set_tdp_cr3 = vmx_set_cr3,
7959 .check_intercept = vmx_check_intercept,
7960 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7961 .mpx_supported = vmx_mpx_supported,
7962 .xsaves_supported = vmx_xsaves_supported,
7963 .umip_emulated = vmx_umip_emulated,
7964 .pt_supported = vmx_pt_supported,
7965 .pku_supported = vmx_pku_supported,
7967 .request_immediate_exit = vmx_request_immediate_exit,
7969 .sched_in = vmx_sched_in,
7971 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7972 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7973 .flush_log_dirty = vmx_flush_log_dirty,
7974 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7975 .write_log_dirty = vmx_write_pml_buffer,
7977 .pre_block = vmx_pre_block,
7978 .post_block = vmx_post_block,
7980 .pmu_ops = &intel_pmu_ops,
7982 .update_pi_irte = vmx_update_pi_irte,
7984 #ifdef CONFIG_X86_64
7985 .set_hv_timer = vmx_set_hv_timer,
7986 .cancel_hv_timer = vmx_cancel_hv_timer,
7989 .setup_mce = vmx_setup_mce,
7991 .smi_allowed = vmx_smi_allowed,
7992 .pre_enter_smm = vmx_pre_enter_smm,
7993 .pre_leave_smm = vmx_pre_leave_smm,
7994 .enable_smi_window = enable_smi_window,
7996 .check_nested_events = NULL,
7997 .get_nested_state = NULL,
7998 .set_nested_state = NULL,
7999 .get_vmcs12_pages = NULL,
8000 .nested_enable_evmcs = NULL,
8001 .nested_get_evmcs_version = NULL,
8002 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
8003 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
8006 static void vmx_cleanup_l1d_flush(void)
8008 if (vmx_l1d_flush_pages) {
8009 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
8010 vmx_l1d_flush_pages = NULL;
8012 /* Restore state so sysfs ignores VMX */
8013 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
8016 static void vmx_exit(void)
8018 #ifdef CONFIG_KEXEC_CORE
8019 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8025 #if IS_ENABLED(CONFIG_HYPERV)
8026 if (static_branch_unlikely(&enable_evmcs)) {
8028 struct hv_vp_assist_page *vp_ap;
8030 * Reset everything to support using non-enlightened VMCS
8031 * access later (e.g. when we reload the module with
8032 * enlightened_vmcs=0)
8034 for_each_online_cpu(cpu) {
8035 vp_ap = hv_get_vp_assist_page(cpu);
8040 vp_ap->nested_control.features.directhypercall = 0;
8041 vp_ap->current_nested_vmcs = 0;
8042 vp_ap->enlighten_vmentry = 0;
8045 static_branch_disable(&enable_evmcs);
8048 vmx_cleanup_l1d_flush();
8050 module_exit(vmx_exit);
8052 static int __init vmx_init(void)
8056 #if IS_ENABLED(CONFIG_HYPERV)
8058 * Enlightened VMCS usage should be recommended and the host needs
8059 * to support eVMCS v1 or above. We can also disable eVMCS support
8060 * with module parameter.
8062 if (enlightened_vmcs &&
8063 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8064 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8065 KVM_EVMCS_VERSION) {
8068 /* Check that we have assist pages on all online CPUs */
8069 for_each_online_cpu(cpu) {
8070 if (!hv_get_vp_assist_page(cpu)) {
8071 enlightened_vmcs = false;
8076 if (enlightened_vmcs) {
8077 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8078 static_branch_enable(&enable_evmcs);
8081 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8082 vmx_x86_ops.enable_direct_tlbflush
8083 = hv_enable_direct_tlbflush;
8086 enlightened_vmcs = false;
8090 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8091 __alignof__(struct vcpu_vmx), THIS_MODULE);
8096 * Must be called after kvm_init() so enable_ept is properly set
8097 * up. Hand the parameter mitigation value in which was stored in
8098 * the pre module init parser. If no parameter was given, it will
8099 * contain 'auto' which will be turned into the default 'cond'
8102 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8108 #ifdef CONFIG_KEXEC_CORE
8109 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8110 crash_vmclear_local_loaded_vmcss);
8112 vmx_check_vmcs12_offsets();
8116 module_init(vmx_init);