arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/highmem.h>
  17 #include <linux/hrtimer.h>
  18 #include <linux/kernel.h>
  19 #include <linux/kvm_host.h>
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/mod_devicetable.h>
  23 #include <linux/mm.h>
  24 #include <linux/objtool.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30 #include <linux/entry-kvm.h>
  31
  32 #include <asm/apic.h>
  33 #include <asm/asm.h>
  34 #include <asm/cpu.h>
  35 #include <asm/cpu_device_id.h>
  36 #include <asm/debugreg.h>
  37 #include <asm/desc.h>
  38 #include <asm/fpu/internal.h>
  39 #include <asm/idtentry.h>
  40 #include <asm/io.h>
  41 #include <asm/irq_remapping.h>
  42 #include <asm/kexec.h>
  43 #include <asm/perf_event.h>
  44 #include <asm/mmu_context.h>
  45 #include <asm/mshyperv.h>
  46 #include <asm/mwait.h>
  47 #include <asm/spec-ctrl.h>
  48 #include <asm/virtext.h>
  49 #include <asm/vmx.h>
  50
  51 #include "capabilities.h"
  52 #include "cpuid.h"
  53 #include "evmcs.h"
  54 #include "hyperv.h"
  55 #include "kvm_onhyperv.h"
  56 #include "irq.h"
  57 #include "kvm_cache_regs.h"
  58 #include "lapic.h"
  59 #include "mmu.h"
  60 #include "nested.h"
  61 #include "pmu.h"
  62 #include "sgx.h"
  63 #include "trace.h"
  64 #include "vmcs.h"
  65 #include "vmcs12.h"
  66 #include "vmx.h"
  67 #include "x86.h"
  68
  69 MODULE_AUTHOR("Qumranet");
  70 MODULE_LICENSE("GPL");
  71
  72 #ifdef MODULE
  73 static const struct x86_cpu_id vmx_cpu_id[] = {
  74         X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
  75         {}
  76 };
  77 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  78 #endif
  79
  80 bool __read_mostly enable_vpid = 1;
  81 module_param_named(vpid, enable_vpid, bool, 0444);
  82
  83 static bool __read_mostly enable_vnmi = 1;
  84 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  85
  86 bool __read_mostly flexpriority_enabled = 1;
  87 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_ept = 1;
  90 module_param_named(ept, enable_ept, bool, S_IRUGO);
  91
  92 bool __read_mostly enable_unrestricted_guest = 1;
  93 module_param_named(unrestricted_guest,
  94                         enable_unrestricted_guest, bool, S_IRUGO);
  95
  96 bool __read_mostly enable_ept_ad_bits = 1;
  97 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  98
  99 static bool __read_mostly emulate_invalid_guest_state = true;
 100 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
 101
 102 static bool __read_mostly fasteoi = 1;
 103 module_param(fasteoi, bool, S_IRUGO);
 104
 105 module_param(enable_apicv, bool, S_IRUGO);
 106
 107 /*
 108  * If nested=1, nested virtualization is supported, i.e., guests may use
 109  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 110  * use VMX instructions.
 111  */
 112 static bool __read_mostly nested = 1;
 113 module_param(nested, bool, S_IRUGO);
 114
 115 bool __read_mostly enable_pml = 1;
 116 module_param_named(pml, enable_pml, bool, S_IRUGO);
 117
 118 static bool __read_mostly dump_invalid_vmcs = 0;
 119 module_param(dump_invalid_vmcs, bool, 0644);
 120
 121 #define MSR_BITMAP_MODE_X2APIC          1
 122 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 123
 124 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 125
 126 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 127 static int __read_mostly cpu_preemption_timer_multi;
 128 static bool __read_mostly enable_preemption_timer = 1;
 129 #ifdef CONFIG_X86_64
 130 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 131 #endif
 132
 133 extern bool __read_mostly allow_smaller_maxphyaddr;
 134 module_param(allow_smaller_maxphyaddr, bool, S_IRUGO);
 135
 136 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 137 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 138 #define KVM_VM_CR0_ALWAYS_ON                            \
 139         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 140
 141 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 142 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 143 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 144
 145 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 146
 147 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 148         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 149         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 150         RTIT_STATUS_BYTECNT))
 151
 152 /*
 153  * List of MSRs that can be directly passed to the guest.
 154  * In addition to these x2apic and PT MSRs are handled specially.
 155  */
 156 static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = {
 157         MSR_IA32_SPEC_CTRL,
 158         MSR_IA32_PRED_CMD,
 159         MSR_IA32_TSC,
 160 #ifdef CONFIG_X86_64
 161         MSR_FS_BASE,
 162         MSR_GS_BASE,
 163         MSR_KERNEL_GS_BASE,
 164 #endif
 165         MSR_IA32_SYSENTER_CS,
 166         MSR_IA32_SYSENTER_ESP,
 167         MSR_IA32_SYSENTER_EIP,
 168         MSR_CORE_C1_RES,
 169         MSR_CORE_C3_RESIDENCY,
 170         MSR_CORE_C6_RESIDENCY,
 171         MSR_CORE_C7_RESIDENCY,
 172 };
 173
 174 /*
 175  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 176  * ple_gap:    upper bound on the amount of time between two successive
 177  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 178  *             According to test, this time is usually smaller than 128 cycles.
 179  * ple_window: upper bound on the amount of time a guest is allowed to execute
 180  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 181  *             less than 2^12 cycles
 182  * Time is measured based on a counter that runs at the same rate as the TSC,
 183  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 184  */
 185 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 186 module_param(ple_gap, uint, 0444);
 187
 188 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 189 module_param(ple_window, uint, 0444);
 190
 191 /* Default doubles per-vcpu window every exit. */
 192 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 193 module_param(ple_window_grow, uint, 0444);
 194
 195 /* Default resets per-vcpu window every exit to ple_window. */
 196 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 197 module_param(ple_window_shrink, uint, 0444);
 198
 199 /* Default is to compute the maximum so we can never overflow. */
 200 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 201 module_param(ple_window_max, uint, 0444);
 202
 203 /* Default is SYSTEM mode, 1 for host-guest mode */
 204 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 205 module_param(pt_mode, int, S_IRUGO);
 206
 207 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 208 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 209 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 210
 211 /* Storage for pre module init parameter parsing */
 212 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 213
 214 static const struct {
 215         const char *option;
 216         bool for_parse;
 217 } vmentry_l1d_param[] = {
 218         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 219         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 220         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 221         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 222         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 223         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 224 };
 225
 226 #define L1D_CACHE_ORDER 4
 227 static void *vmx_l1d_flush_pages;
 228
 229 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 230 {
 231         struct page *page;
 232         unsigned int i;
 233
 234         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 235                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 236                 return 0;
 237         }
 238
 239         if (!enable_ept) {
 240                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 241                 return 0;
 242         }
 243
 244         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 245                 u64 msr;
 246
 247                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 248                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 249                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 250                         return 0;
 251                 }
 252         }
 253
 254         /* If set to auto use the default l1tf mitigation method */
 255         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 256                 switch (l1tf_mitigation) {
 257                 case L1TF_MITIGATION_OFF:
 258                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 259                         break;
 260                 case L1TF_MITIGATION_FLUSH_NOWARN:
 261                 case L1TF_MITIGATION_FLUSH:
 262                 case L1TF_MITIGATION_FLUSH_NOSMT:
 263                         l1tf = VMENTER_L1D_FLUSH_COND;
 264                         break;
 265                 case L1TF_MITIGATION_FULL:
 266                 case L1TF_MITIGATION_FULL_FORCE:
 267                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 268                         break;
 269                 }
 270         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 271                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 272         }
 273
 274         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 275             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 276                 /*
 277                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 278                  * lifetime and so should not be charged to a memcg.
 279                  */
 280                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 281                 if (!page)
 282                         return -ENOMEM;
 283                 vmx_l1d_flush_pages = page_address(page);
 284
 285                 /*
 286                  * Initialize each page with a different pattern in
 287                  * order to protect against KSM in the nested
 288                  * virtualization case.
 289                  */
 290                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 291                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 292                                PAGE_SIZE);
 293                 }
 294         }
 295
 296         l1tf_vmx_mitigation = l1tf;
 297
 298         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 299                 static_branch_enable(&vmx_l1d_should_flush);
 300         else
 301                 static_branch_disable(&vmx_l1d_should_flush);
 302
 303         if (l1tf == VMENTER_L1D_FLUSH_COND)
 304                 static_branch_enable(&vmx_l1d_flush_cond);
 305         else
 306                 static_branch_disable(&vmx_l1d_flush_cond);
 307         return 0;
 308 }
 309
 310 static int vmentry_l1d_flush_parse(const char *s)
 311 {
 312         unsigned int i;
 313
 314         if (s) {
 315                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 316                         if (vmentry_l1d_param[i].for_parse &&
 317                             sysfs_streq(s, vmentry_l1d_param[i].option))
 318                                 return i;
 319                 }
 320         }
 321         return -EINVAL;
 322 }
 323
 324 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 325 {
 326         int l1tf, ret;
 327
 328         l1tf = vmentry_l1d_flush_parse(s);
 329         if (l1tf < 0)
 330                 return l1tf;
 331
 332         if (!boot_cpu_has(X86_BUG_L1TF))
 333                 return 0;
 334
 335         /*
 336          * Has vmx_init() run already? If not then this is the pre init
 337          * parameter parsing. In that case just store the value and let
 338          * vmx_init() do the proper setup after enable_ept has been
 339          * established.
 340          */
 341         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 342                 vmentry_l1d_flush_param = l1tf;
 343                 return 0;
 344         }
 345
 346         mutex_lock(&vmx_l1d_flush_mutex);
 347         ret = vmx_setup_l1d_flush(l1tf);
 348         mutex_unlock(&vmx_l1d_flush_mutex);
 349         return ret;
 350 }
 351
 352 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 353 {
 354         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 355                 return sprintf(s, "???\n");
 356
 357         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 358 }
 359
 360 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 361         .set = vmentry_l1d_flush_set,
 362         .get = vmentry_l1d_flush_get,
 363 };
 364 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 365
 366 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 367
 368 void vmx_vmexit(void);
 369
 370 #define vmx_insn_failed(fmt...)         \
 371 do {                                    \
 372         WARN_ONCE(1, fmt);              \
 373         pr_warn_ratelimited(fmt);       \
 374 } while (0)
 375
 376 asmlinkage void vmread_error(unsigned long field, bool fault)
 377 {
 378         if (fault)
 379                 kvm_spurious_fault();
 380         else
 381                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 382 }
 383
 384 noinline void vmwrite_error(unsigned long field, unsigned long value)
 385 {
 386         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 387                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 388 }
 389
 390 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 391 {
 392         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 393 }
 394
 395 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 396 {
 397         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 398 }
 399
 400 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 401 {
 402         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 403                         ext, vpid, gva);
 404 }
 405
 406 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 407 {
 408         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 409                         ext, eptp, gpa);
 410 }
 411
 412 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 413 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 414 /*
 415  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 416  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 417  */
 418 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 419
 420 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 421 static DEFINE_SPINLOCK(vmx_vpid_lock);
 422
 423 struct vmcs_config vmcs_config;
 424 struct vmx_capability vmx_capability;
 425
 426 #define VMX_SEGMENT_FIELD(seg)                                  \
 427         [VCPU_SREG_##seg] = {                                   \
 428                 .selector = GUEST_##seg##_SELECTOR,             \
 429                 .base = GUEST_##seg##_BASE,                     \
 430                 .limit = GUEST_##seg##_LIMIT,                   \
 431                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 432         }
 433
 434 static const struct kvm_vmx_segment_field {
 435         unsigned selector;
 436         unsigned base;
 437         unsigned limit;
 438         unsigned ar_bytes;
 439 } kvm_vmx_segment_fields[] = {
 440         VMX_SEGMENT_FIELD(CS),
 441         VMX_SEGMENT_FIELD(DS),
 442         VMX_SEGMENT_FIELD(ES),
 443         VMX_SEGMENT_FIELD(FS),
 444         VMX_SEGMENT_FIELD(GS),
 445         VMX_SEGMENT_FIELD(SS),
 446         VMX_SEGMENT_FIELD(TR),
 447         VMX_SEGMENT_FIELD(LDTR),
 448 };
 449
 450 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
 451 {
 452         vmx->segment_cache.bitmask = 0;
 453 }
 454
 455 static unsigned long host_idt_base;
 456
 457 #if IS_ENABLED(CONFIG_HYPERV)
 458 static bool __read_mostly enlightened_vmcs = true;
 459 module_param(enlightened_vmcs, bool, 0444);
 460
 461 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 462 {
 463         struct hv_enlightened_vmcs *evmcs;
 464         struct hv_partition_assist_pg **p_hv_pa_pg =
 465                         &to_kvm_hv(vcpu->kvm)->hv_pa_pg;
 466         /*
 467          * Synthetic VM-Exit is not enabled in current code and so All
 468          * evmcs in singe VM shares same assist page.
 469          */
 470         if (!*p_hv_pa_pg)
 471                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
 472
 473         if (!*p_hv_pa_pg)
 474                 return -ENOMEM;
 475
 476         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 477
 478         evmcs->partition_assist_page =
 479                 __pa(*p_hv_pa_pg);
 480         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 481         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 482
 483         return 0;
 484 }
 485
 486 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 487
 488 /*
 489  * Comment's format: document - errata name - stepping - processor name.
 490  * Refer from
 491  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 492  */
 493 static u32 vmx_preemption_cpu_tfms[] = {
 494 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 495 0x000206E6,
 496 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 497 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 498 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 499 0x00020652,
 500 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 501 0x00020655,
 502 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 503 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 504 /*
 505  * 320767.pdf - AAP86  - B1 -
 506  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 507  */
 508 0x000106E5,
 509 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 510 0x000106A0,
 511 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 512 0x000106A1,
 513 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 514 0x000106A4,
 515  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 516  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 517  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 518 0x000106A5,
 519  /* Xeon E3-1220 V2 */
 520 0x000306A8,
 521 };
 522
 523 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 524 {
 525         u32 eax = cpuid_eax(0x00000001), i;
 526
 527         /* Clear the reserved bits */
 528         eax &= ~(0x3U << 14 | 0xfU << 28);
 529         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 530                 if (eax == vmx_preemption_cpu_tfms[i])
 531                         return true;
 532
 533         return false;
 534 }
 535
 536 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 537 {
 538         return flexpriority_enabled && lapic_in_kernel(vcpu);
 539 }
 540
 541 static inline bool report_flexpriority(void)
 542 {
 543         return flexpriority_enabled;
 544 }
 545
 546 static int possible_passthrough_msr_slot(u32 msr)
 547 {
 548         u32 i;
 549
 550         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++)
 551                 if (vmx_possible_passthrough_msrs[i] == msr)
 552                         return i;
 553
 554         return -ENOENT;
 555 }
 556
 557 static bool is_valid_passthrough_msr(u32 msr)
 558 {
 559         bool r;
 560
 561         switch (msr) {
 562         case 0x800 ... 0x8ff:
 563                 /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */
 564                 return true;
 565         case MSR_IA32_RTIT_STATUS:
 566         case MSR_IA32_RTIT_OUTPUT_BASE:
 567         case MSR_IA32_RTIT_OUTPUT_MASK:
 568         case MSR_IA32_RTIT_CR3_MATCH:
 569         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
 570                 /* PT MSRs. These are handled in pt_update_intercept_for_msr() */
 571         case MSR_LBR_SELECT:
 572         case MSR_LBR_TOS:
 573         case MSR_LBR_INFO_0 ... MSR_LBR_INFO_0 + 31:
 574         case MSR_LBR_NHM_FROM ... MSR_LBR_NHM_FROM + 31:
 575         case MSR_LBR_NHM_TO ... MSR_LBR_NHM_TO + 31:
 576         case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8:
 577         case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8:
 578                 /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */
 579                 return true;
 580         }
 581
 582         r = possible_passthrough_msr_slot(msr) != -ENOENT;
 583
 584         WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr);
 585
 586         return r;
 587 }
 588
 589 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
 590 {
 591         int i;
 592
 593         i = kvm_find_user_return_msr(msr);
 594         if (i >= 0)
 595                 return &vmx->guest_uret_msrs[i];
 596         return NULL;
 597 }
 598
 599 static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx,
 600                                   struct vmx_uret_msr *msr, u64 data)
 601 {
 602         unsigned int slot = msr - vmx->guest_uret_msrs;
 603         int ret = 0;
 604
 605         u64 old_msr_data = msr->data;
 606         msr->data = data;
 607         if (msr->load_into_hardware) {
 608                 preempt_disable();
 609                 ret = kvm_set_user_return_msr(slot, msr->data, msr->mask);
 610                 preempt_enable();
 611                 if (ret)
 612                         msr->data = old_msr_data;
 613         }
 614         return ret;
 615 }
 616
 617 #ifdef CONFIG_KEXEC_CORE
 618 static void crash_vmclear_local_loaded_vmcss(void)
 619 {
 620         int cpu = raw_smp_processor_id();
 621         struct loaded_vmcs *v;
 622
 623         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 624                             loaded_vmcss_on_cpu_link)
 625                 vmcs_clear(v->vmcs);
 626 }
 627 #endif /* CONFIG_KEXEC_CORE */
 628
 629 static void __loaded_vmcs_clear(void *arg)
 630 {
 631         struct loaded_vmcs *loaded_vmcs = arg;
 632         int cpu = raw_smp_processor_id();
 633
 634         if (loaded_vmcs->cpu != cpu)
 635                 return; /* vcpu migration can race with cpu offline */
 636         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 637                 per_cpu(current_vmcs, cpu) = NULL;
 638
 639         vmcs_clear(loaded_vmcs->vmcs);
 640         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 641                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 642
 643         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 644
 645         /*
 646          * Ensure all writes to loaded_vmcs, including deleting it from its
 647          * current percpu list, complete before setting loaded_vmcs->vcpu to
 648          * -1, otherwise a different cpu can see vcpu == -1 first and add
 649          * loaded_vmcs to its percpu list before it's deleted from this cpu's
 650          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
 651          */
 652         smp_wmb();
 653
 654         loaded_vmcs->cpu = -1;
 655         loaded_vmcs->launched = 0;
 656 }
 657
 658 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 659 {
 660         int cpu = loaded_vmcs->cpu;
 661
 662         if (cpu != -1)
 663                 smp_call_function_single(cpu,
 664                          __loaded_vmcs_clear, loaded_vmcs, 1);
 665 }
 666
 667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 668                                        unsigned field)
 669 {
 670         bool ret;
 671         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 672
 673         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
 674                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
 675                 vmx->segment_cache.bitmask = 0;
 676         }
 677         ret = vmx->segment_cache.bitmask & mask;
 678         vmx->segment_cache.bitmask |= mask;
 679         return ret;
 680 }
 681
 682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 683 {
 684         u16 *p = &vmx->segment_cache.seg[seg].selector;
 685
 686         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 687                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 688         return *p;
 689 }
 690
 691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 692 {
 693         ulong *p = &vmx->segment_cache.seg[seg].base;
 694
 695         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 696                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 697         return *p;
 698 }
 699
 700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 701 {
 702         u32 *p = &vmx->segment_cache.seg[seg].limit;
 703
 704         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 705                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 706         return *p;
 707 }
 708
 709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 710 {
 711         u32 *p = &vmx->segment_cache.seg[seg].ar;
 712
 713         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 714                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 715         return *p;
 716 }
 717
 718 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu)
 719 {
 720         u32 eb;
 721
 722         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 723              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 724         /*
 725          * Guest access to VMware backdoor ports could legitimately
 726          * trigger #GP because of TSS I/O permission bitmap.
 727          * We intercept those #GP and allow access to them anyway
 728          * as VMware does.
 729          */
 730         if (enable_vmware_backdoor)
 731                 eb |= (1u << GP_VECTOR);
 732         if ((vcpu->guest_debug &
 733              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 734             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 735                 eb |= 1u << BP_VECTOR;
 736         if (to_vmx(vcpu)->rmode.vm86_active)
 737                 eb = ~0;
 738         if (!vmx_need_pf_intercept(vcpu))
 739                 eb &= ~(1u << PF_VECTOR);
 740
 741         /* When we are running a nested L2 guest and L1 specified for it a
 742          * certain exception bitmap, we must trap the same exceptions and pass
 743          * them to L1. When running L2, we will only handle the exceptions
 744          * specified above if L1 did not want them.
 745          */
 746         if (is_guest_mode(vcpu))
 747                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 748         else {
 749                 int mask = 0, match = 0;
 750
 751                 if (enable_ept && (eb & (1u << PF_VECTOR))) {
 752                         /*
 753                          * If EPT is enabled, #PF is currently only intercepted
 754                          * if MAXPHYADDR is smaller on the guest than on the
 755                          * host.  In that case we only care about present,
 756                          * non-reserved faults.  For vmcs02, however, PFEC_MASK
 757                          * and PFEC_MATCH are set in prepare_vmcs02_rare.
 758                          */
 759                         mask = PFERR_PRESENT_MASK | PFERR_RSVD_MASK;
 760                         match = PFERR_PRESENT_MASK;
 761                 }
 762                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
 763                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, match);
 764         }
 765
 766         vmcs_write32(EXCEPTION_BITMAP, eb);
 767 }
 768
 769 /*
 770  * Check if MSR is intercepted for currently loaded MSR bitmap.
 771  */
 772 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 773 {
 774         unsigned long *msr_bitmap;
 775         int f = sizeof(unsigned long);
 776
 777         if (!cpu_has_vmx_msr_bitmap())
 778                 return true;
 779
 780         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 781
 782         if (msr <= 0x1fff) {
 783                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 784         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 785                 msr &= 0x1fff;
 786                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 787         }
 788
 789         return true;
 790 }
 791
 792 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 793                 unsigned long entry, unsigned long exit)
 794 {
 795         vm_entry_controls_clearbit(vmx, entry);
 796         vm_exit_controls_clearbit(vmx, exit);
 797 }
 798
 799 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr)
 800 {
 801         unsigned int i;
 802
 803         for (i = 0; i < m->nr; ++i) {
 804                 if (m->val[i].index == msr)
 805                         return i;
 806         }
 807         return -ENOENT;
 808 }
 809
 810 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 811 {
 812         int i;
 813         struct msr_autoload *m = &vmx->msr_autoload;
 814
 815         switch (msr) {
 816         case MSR_EFER:
 817                 if (cpu_has_load_ia32_efer()) {
 818                         clear_atomic_switch_msr_special(vmx,
 819                                         VM_ENTRY_LOAD_IA32_EFER,
 820                                         VM_EXIT_LOAD_IA32_EFER);
 821                         return;
 822                 }
 823                 break;
 824         case MSR_CORE_PERF_GLOBAL_CTRL:
 825                 if (cpu_has_load_perf_global_ctrl()) {
 826                         clear_atomic_switch_msr_special(vmx,
 827                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 828                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 829                         return;
 830                 }
 831                 break;
 832         }
 833         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
 834         if (i < 0)
 835                 goto skip_guest;
 836         --m->guest.nr;
 837         m->guest.val[i] = m->guest.val[m->guest.nr];
 838         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 839
 840 skip_guest:
 841         i = vmx_find_loadstore_msr_slot(&m->host, msr);
 842         if (i < 0)
 843                 return;
 844
 845         --m->host.nr;
 846         m->host.val[i] = m->host.val[m->host.nr];
 847         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 848 }
 849
 850 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 851                 unsigned long entry, unsigned long exit,
 852                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 853                 u64 guest_val, u64 host_val)
 854 {
 855         vmcs_write64(guest_val_vmcs, guest_val);
 856         if (host_val_vmcs != HOST_IA32_EFER)
 857                 vmcs_write64(host_val_vmcs, host_val);
 858         vm_entry_controls_setbit(vmx, entry);
 859         vm_exit_controls_setbit(vmx, exit);
 860 }
 861
 862 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 863                                   u64 guest_val, u64 host_val, bool entry_only)
 864 {
 865         int i, j = 0;
 866         struct msr_autoload *m = &vmx->msr_autoload;
 867
 868         switch (msr) {
 869         case MSR_EFER:
 870                 if (cpu_has_load_ia32_efer()) {
 871                         add_atomic_switch_msr_special(vmx,
 872                                         VM_ENTRY_LOAD_IA32_EFER,
 873                                         VM_EXIT_LOAD_IA32_EFER,
 874                                         GUEST_IA32_EFER,
 875                                         HOST_IA32_EFER,
 876                                         guest_val, host_val);
 877                         return;
 878                 }
 879                 break;
 880         case MSR_CORE_PERF_GLOBAL_CTRL:
 881                 if (cpu_has_load_perf_global_ctrl()) {
 882                         add_atomic_switch_msr_special(vmx,
 883                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 884                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 885                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 886                                         HOST_IA32_PERF_GLOBAL_CTRL,
 887                                         guest_val, host_val);
 888                         return;
 889                 }
 890                 break;
 891         case MSR_IA32_PEBS_ENABLE:
 892                 /* PEBS needs a quiescent period after being disabled (to write
 893                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 894                  * provide that period, so a CPU could write host's record into
 895                  * guest's memory.
 896                  */
 897                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 898         }
 899
 900         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
 901         if (!entry_only)
 902                 j = vmx_find_loadstore_msr_slot(&m->host, msr);
 903
 904         if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) ||
 905             (j < 0 &&  m->host.nr == MAX_NR_LOADSTORE_MSRS)) {
 906                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 907                                 "Can't add msr %x\n", msr);
 908                 return;
 909         }
 910         if (i < 0) {
 911                 i = m->guest.nr++;
 912                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 913         }
 914         m->guest.val[i].index = msr;
 915         m->guest.val[i].value = guest_val;
 916
 917         if (entry_only)
 918                 return;
 919
 920         if (j < 0) {
 921                 j = m->host.nr++;
 922                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 923         }
 924         m->host.val[j].index = msr;
 925         m->host.val[j].value = host_val;
 926 }
 927
 928 static bool update_transition_efer(struct vcpu_vmx *vmx)
 929 {
 930         u64 guest_efer = vmx->vcpu.arch.efer;
 931         u64 ignore_bits = 0;
 932         int i;
 933
 934         /* Shadow paging assumes NX to be available.  */
 935         if (!enable_ept)
 936                 guest_efer |= EFER_NX;
 937
 938         /*
 939          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 940          */
 941         ignore_bits |= EFER_SCE;
 942 #ifdef CONFIG_X86_64
 943         ignore_bits |= EFER_LMA | EFER_LME;
 944         /* SCE is meaningful only in long mode on Intel */
 945         if (guest_efer & EFER_LMA)
 946                 ignore_bits &= ~(u64)EFER_SCE;
 947 #endif
 948
 949         /*
 950          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 951          * On CPUs that support "load IA32_EFER", always switch EFER
 952          * atomically, since it's faster than switching it manually.
 953          */
 954         if (cpu_has_load_ia32_efer() ||
 955             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 956                 if (!(guest_efer & EFER_LMA))
 957                         guest_efer &= ~EFER_LME;
 958                 if (guest_efer != host_efer)
 959                         add_atomic_switch_msr(vmx, MSR_EFER,
 960                                               guest_efer, host_efer, false);
 961                 else
 962                         clear_atomic_switch_msr(vmx, MSR_EFER);
 963                 return false;
 964         }
 965
 966         i = kvm_find_user_return_msr(MSR_EFER);
 967         if (i < 0)
 968                 return false;
 969
 970         clear_atomic_switch_msr(vmx, MSR_EFER);
 971
 972         guest_efer &= ~ignore_bits;
 973         guest_efer |= host_efer & ignore_bits;
 974
 975         vmx->guest_uret_msrs[i].data = guest_efer;
 976         vmx->guest_uret_msrs[i].mask = ~ignore_bits;
 977
 978         return true;
 979 }
 980
 981 #ifdef CONFIG_X86_32
 982 /*
 983  * On 32-bit kernels, VM exits still load the FS and GS bases from the
 984  * VMCS rather than the segment table.  KVM uses this helper to figure
 985  * out the current bases to poke them into the VMCS before entry.
 986  */
 987 static unsigned long segment_base(u16 selector)
 988 {
 989         struct desc_struct *table;
 990         unsigned long v;
 991
 992         if (!(selector & ~SEGMENT_RPL_MASK))
 993                 return 0;
 994
 995         table = get_current_gdt_ro();
 996
 997         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
 998                 u16 ldt_selector = kvm_read_ldt();
 999
1000                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1001                         return 0;
1002
1003                 table = (struct desc_struct *)segment_base(ldt_selector);
1004         }
1005         v = get_desc_base(&table[selector >> 3]);
1006         return v;
1007 }
1008 #endif
1009
1010 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1011 {
1012         return vmx_pt_mode_is_host_guest() &&
1013                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1014 }
1015
1016 static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base)
1017 {
1018         /* The base must be 128-byte aligned and a legal physical address. */
1019         return kvm_vcpu_is_legal_aligned_gpa(vcpu, base, 128);
1020 }
1021
1022 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1023 {
1024         u32 i;
1025
1026         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1027         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1028         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1029         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1030         for (i = 0; i < addr_range; i++) {
1031                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1032                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1033         }
1034 }
1035
1036 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1037 {
1038         u32 i;
1039
1040         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1041         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1042         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1043         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1044         for (i = 0; i < addr_range; i++) {
1045                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1046                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1047         }
1048 }
1049
1050 static void pt_guest_enter(struct vcpu_vmx *vmx)
1051 {
1052         if (vmx_pt_mode_is_system())
1053                 return;
1054
1055         /*
1056          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1057          * Save host state before VM entry.
1058          */
1059         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1060         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1061                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1062                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1063                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1064         }
1065 }
1066
1067 static void pt_guest_exit(struct vcpu_vmx *vmx)
1068 {
1069         if (vmx_pt_mode_is_system())
1070                 return;
1071
1072         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1073                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1074                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1075         }
1076
1077         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1078         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1079 }
1080
1081 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1082                         unsigned long fs_base, unsigned long gs_base)
1083 {
1084         if (unlikely(fs_sel != host->fs_sel)) {
1085                 if (!(fs_sel & 7))
1086                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1087                 else
1088                         vmcs_write16(HOST_FS_SELECTOR, 0);
1089                 host->fs_sel = fs_sel;
1090         }
1091         if (unlikely(gs_sel != host->gs_sel)) {
1092                 if (!(gs_sel & 7))
1093                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1094                 else
1095                         vmcs_write16(HOST_GS_SELECTOR, 0);
1096                 host->gs_sel = gs_sel;
1097         }
1098         if (unlikely(fs_base != host->fs_base)) {
1099                 vmcs_writel(HOST_FS_BASE, fs_base);
1100                 host->fs_base = fs_base;
1101         }
1102         if (unlikely(gs_base != host->gs_base)) {
1103                 vmcs_writel(HOST_GS_BASE, gs_base);
1104                 host->gs_base = gs_base;
1105         }
1106 }
1107
1108 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1109 {
1110         struct vcpu_vmx *vmx = to_vmx(vcpu);
1111         struct vmcs_host_state *host_state;
1112 #ifdef CONFIG_X86_64
1113         int cpu = raw_smp_processor_id();
1114 #endif
1115         unsigned long fs_base, gs_base;
1116         u16 fs_sel, gs_sel;
1117         int i;
1118
1119         vmx->req_immediate_exit = false;
1120
1121         /*
1122          * Note that guest MSRs to be saved/restored can also be changed
1123          * when guest state is loaded. This happens when guest transitions
1124          * to/from long-mode by setting MSR_EFER.LMA.
1125          */
1126         if (!vmx->guest_uret_msrs_loaded) {
1127                 vmx->guest_uret_msrs_loaded = true;
1128                 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
1129                         if (!vmx->guest_uret_msrs[i].load_into_hardware)
1130                                 continue;
1131
1132                         kvm_set_user_return_msr(i,
1133                                                 vmx->guest_uret_msrs[i].data,
1134                                                 vmx->guest_uret_msrs[i].mask);
1135                 }
1136         }
1137
1138         if (vmx->nested.need_vmcs12_to_shadow_sync)
1139                 nested_sync_vmcs12_to_shadow(vcpu);
1140
1141         if (vmx->guest_state_loaded)
1142                 return;
1143
1144         host_state = &vmx->loaded_vmcs->host_state;
1145
1146         /*
1147          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1148          * allow segment selectors with cpl > 0 or ti == 1.
1149          */
1150         host_state->ldt_sel = kvm_read_ldt();
1151
1152 #ifdef CONFIG_X86_64
1153         savesegment(ds, host_state->ds_sel);
1154         savesegment(es, host_state->es_sel);
1155
1156         gs_base = cpu_kernelmode_gs_base(cpu);
1157         if (likely(is_64bit_mm(current->mm))) {
1158                 current_save_fsgs();
1159                 fs_sel = current->thread.fsindex;
1160                 gs_sel = current->thread.gsindex;
1161                 fs_base = current->thread.fsbase;
1162                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1163         } else {
1164                 savesegment(fs, fs_sel);
1165                 savesegment(gs, gs_sel);
1166                 fs_base = read_msr(MSR_FS_BASE);
1167                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1168         }
1169
1170         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1171 #else
1172         savesegment(fs, fs_sel);
1173         savesegment(gs, gs_sel);
1174         fs_base = segment_base(fs_sel);
1175         gs_base = segment_base(gs_sel);
1176 #endif
1177
1178         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1179         vmx->guest_state_loaded = true;
1180 }
1181
1182 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1183 {
1184         struct vmcs_host_state *host_state;
1185
1186         if (!vmx->guest_state_loaded)
1187                 return;
1188
1189         host_state = &vmx->loaded_vmcs->host_state;
1190
1191         ++vmx->vcpu.stat.host_state_reload;
1192
1193 #ifdef CONFIG_X86_64
1194         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1195 #endif
1196         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1197                 kvm_load_ldt(host_state->ldt_sel);
1198 #ifdef CONFIG_X86_64
1199                 load_gs_index(host_state->gs_sel);
1200 #else
1201                 loadsegment(gs, host_state->gs_sel);
1202 #endif
1203         }
1204         if (host_state->fs_sel & 7)
1205                 loadsegment(fs, host_state->fs_sel);
1206 #ifdef CONFIG_X86_64
1207         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1208                 loadsegment(ds, host_state->ds_sel);
1209                 loadsegment(es, host_state->es_sel);
1210         }
1211 #endif
1212         invalidate_tss_limit();
1213 #ifdef CONFIG_X86_64
1214         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1215 #endif
1216         load_fixmap_gdt(raw_smp_processor_id());
1217         vmx->guest_state_loaded = false;
1218         vmx->guest_uret_msrs_loaded = false;
1219 }
1220
1221 #ifdef CONFIG_X86_64
1222 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1223 {
1224         preempt_disable();
1225         if (vmx->guest_state_loaded)
1226                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1227         preempt_enable();
1228         return vmx->msr_guest_kernel_gs_base;
1229 }
1230
1231 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1232 {
1233         preempt_disable();
1234         if (vmx->guest_state_loaded)
1235                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1236         preempt_enable();
1237         vmx->msr_guest_kernel_gs_base = data;
1238 }
1239 #endif
1240
1241 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1242                         struct loaded_vmcs *buddy)
1243 {
1244         struct vcpu_vmx *vmx = to_vmx(vcpu);
1245         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1246         struct vmcs *prev;
1247
1248         if (!already_loaded) {
1249                 loaded_vmcs_clear(vmx->loaded_vmcs);
1250                 local_irq_disable();
1251
1252                 /*
1253                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1254                  * this cpu's percpu list, otherwise it may not yet be deleted
1255                  * from its previous cpu's percpu list.  Pairs with the
1256                  * smb_wmb() in __loaded_vmcs_clear().
1257                  */
1258                 smp_rmb();
1259
1260                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1261                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1262                 local_irq_enable();
1263         }
1264
1265         prev = per_cpu(current_vmcs, cpu);
1266         if (prev != vmx->loaded_vmcs->vmcs) {
1267                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1268                 vmcs_load(vmx->loaded_vmcs->vmcs);
1269
1270                 /*
1271                  * No indirect branch prediction barrier needed when switching
1272                  * the active VMCS within a guest, e.g. on nested VM-Enter.
1273                  * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1274                  */
1275                 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1276                         indirect_branch_prediction_barrier();
1277         }
1278
1279         if (!already_loaded) {
1280                 void *gdt = get_current_gdt_ro();
1281                 unsigned long sysenter_esp;
1282
1283                 /*
1284                  * Flush all EPTP/VPID contexts, the new pCPU may have stale
1285                  * TLB entries from its previous association with the vCPU.
1286                  */
1287                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1288
1289                 /*
1290                  * Linux uses per-cpu TSS and GDT, so set these when switching
1291                  * processors.  See 22.2.4.
1292                  */
1293                 vmcs_writel(HOST_TR_BASE,
1294                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1295                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1296
1297                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1298                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1299
1300                 vmx->loaded_vmcs->cpu = cpu;
1301         }
1302 }
1303
1304 /*
1305  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1306  * vcpu mutex is already taken.
1307  */
1308 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1309 {
1310         struct vcpu_vmx *vmx = to_vmx(vcpu);
1311
1312         vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1313
1314         vmx_vcpu_pi_load(vcpu, cpu);
1315
1316         vmx->host_debugctlmsr = get_debugctlmsr();
1317 }
1318
1319 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1320 {
1321         vmx_vcpu_pi_put(vcpu);
1322
1323         vmx_prepare_switch_to_host(to_vmx(vcpu));
1324 }
1325
1326 static bool emulation_required(struct kvm_vcpu *vcpu)
1327 {
1328         return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu);
1329 }
1330
1331 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1332 {
1333         struct vcpu_vmx *vmx = to_vmx(vcpu);
1334         unsigned long rflags, save_rflags;
1335
1336         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1337                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1338                 rflags = vmcs_readl(GUEST_RFLAGS);
1339                 if (vmx->rmode.vm86_active) {
1340                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1341                         save_rflags = vmx->rmode.save_rflags;
1342                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1343                 }
1344                 vmx->rflags = rflags;
1345         }
1346         return vmx->rflags;
1347 }
1348
1349 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1350 {
1351         struct vcpu_vmx *vmx = to_vmx(vcpu);
1352         unsigned long old_rflags;
1353
1354         if (is_unrestricted_guest(vcpu)) {
1355                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1356                 vmx->rflags = rflags;
1357                 vmcs_writel(GUEST_RFLAGS, rflags);
1358                 return;
1359         }
1360
1361         old_rflags = vmx_get_rflags(vcpu);
1362         vmx->rflags = rflags;
1363         if (vmx->rmode.vm86_active) {
1364                 vmx->rmode.save_rflags = rflags;
1365                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1366         }
1367         vmcs_writel(GUEST_RFLAGS, rflags);
1368
1369         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1370                 vmx->emulation_required = emulation_required(vcpu);
1371 }
1372
1373 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1374 {
1375         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1376         int ret = 0;
1377
1378         if (interruptibility & GUEST_INTR_STATE_STI)
1379                 ret |= KVM_X86_SHADOW_INT_STI;
1380         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1381                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1382
1383         return ret;
1384 }
1385
1386 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1387 {
1388         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1389         u32 interruptibility = interruptibility_old;
1390
1391         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1392
1393         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1394                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1395         else if (mask & KVM_X86_SHADOW_INT_STI)
1396                 interruptibility |= GUEST_INTR_STATE_STI;
1397
1398         if ((interruptibility != interruptibility_old))
1399                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1400 }
1401
1402 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1403 {
1404         struct vcpu_vmx *vmx = to_vmx(vcpu);
1405         unsigned long value;
1406
1407         /*
1408          * Any MSR write that attempts to change bits marked reserved will
1409          * case a #GP fault.
1410          */
1411         if (data & vmx->pt_desc.ctl_bitmask)
1412                 return 1;
1413
1414         /*
1415          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1416          * result in a #GP unless the same write also clears TraceEn.
1417          */
1418         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1419                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1420                 return 1;
1421
1422         /*
1423          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1424          * and FabricEn would cause #GP, if
1425          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1426          */
1427         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1428                 !(data & RTIT_CTL_FABRIC_EN) &&
1429                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1430                                         PT_CAP_single_range_output))
1431                 return 1;
1432
1433         /*
1434          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1435          * utilize encodings marked reserved will cause a #GP fault.
1436          */
1437         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1438         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1439                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1440                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1441                 return 1;
1442         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1443                                                 PT_CAP_cycle_thresholds);
1444         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1445                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1446                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1447                 return 1;
1448         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1449         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1450                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1451                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1452                 return 1;
1453
1454         /*
1455          * If ADDRx_CFG is reserved or the encodings is >2 will
1456          * cause a #GP fault.
1457          */
1458         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1459         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1460                 return 1;
1461         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1462         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1463                 return 1;
1464         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1465         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1466                 return 1;
1467         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1468         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1469                 return 1;
1470
1471         return 0;
1472 }
1473
1474 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
1475 {
1476         /*
1477          * Emulation of instructions in SGX enclaves is impossible as RIP does
1478          * not point  tthe failing instruction, and even if it did, the code
1479          * stream is inaccessible.  Inject #UD instead of exiting to userspace
1480          * so that guest userspace can't DoS the guest simply by triggering
1481          * emulation (enclaves are CPL3 only).
1482          */
1483         if (to_vmx(vcpu)->exit_reason.enclave_mode) {
1484                 kvm_queue_exception(vcpu, UD_VECTOR);
1485                 return false;
1486         }
1487         return true;
1488 }
1489
1490 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1491 {
1492         union vmx_exit_reason exit_reason = to_vmx(vcpu)->exit_reason;
1493         unsigned long rip, orig_rip;
1494         u32 instr_len;
1495
1496         /*
1497          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1498          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1499          * set when EPT misconfig occurs.  In practice, real hardware updates
1500          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1501          * (namely Hyper-V) don't set it due to it being undefined behavior,
1502          * i.e. we end up advancing IP with some random value.
1503          */
1504         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1505             exit_reason.basic != EXIT_REASON_EPT_MISCONFIG) {
1506                 instr_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1507
1508                 /*
1509                  * Emulating an enclave's instructions isn't supported as KVM
1510                  * cannot access the enclave's memory or its true RIP, e.g. the
1511                  * vmcs.GUEST_RIP points at the exit point of the enclave, not
1512                  * the RIP that actually triggered the VM-Exit.  But, because
1513                  * most instructions that cause VM-Exit will #UD in an enclave,
1514                  * most instruction-based VM-Exits simply do not occur.
1515                  *
1516                  * There are a few exceptions, notably the debug instructions
1517                  * INT1ICEBRK and INT3, as they are allowed in debug enclaves
1518                  * and generate #DB/#BP as expected, which KVM might intercept.
1519                  * But again, the CPU does the dirty work and saves an instr
1520                  * length of zero so VMMs don't shoot themselves in the foot.
1521                  * WARN if KVM tries to skip a non-zero length instruction on
1522                  * a VM-Exit from an enclave.
1523                  */
1524                 if (!instr_len)
1525                         goto rip_updated;
1526
1527                 WARN(exit_reason.enclave_mode,
1528                      "KVM: skipping instruction after SGX enclave VM-Exit");
1529
1530                 orig_rip = kvm_rip_read(vcpu);
1531                 rip = orig_rip + instr_len;
1532 #ifdef CONFIG_X86_64
1533                 /*
1534                  * We need to mask out the high 32 bits of RIP if not in 64-bit
1535                  * mode, but just finding out that we are in 64-bit mode is
1536                  * quite expensive.  Only do it if there was a carry.
1537                  */
1538                 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1539                         rip = (u32)rip;
1540 #endif
1541                 kvm_rip_write(vcpu, rip);
1542         } else {
1543                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1544                         return 0;
1545         }
1546
1547 rip_updated:
1548         /* skipping an emulated instruction also counts */
1549         vmx_set_interrupt_shadow(vcpu, 0);
1550
1551         return 1;
1552 }
1553
1554 /*
1555  * Recognizes a pending MTF VM-exit and records the nested state for later
1556  * delivery.
1557  */
1558 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1559 {
1560         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1561         struct vcpu_vmx *vmx = to_vmx(vcpu);
1562
1563         if (!is_guest_mode(vcpu))
1564                 return;
1565
1566         /*
1567          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1568          * T-bit traps. As instruction emulation is completed (i.e. at the
1569          * instruction boundary), any #DB exception pending delivery must be a
1570          * debug-trap. Record the pending MTF state to be delivered in
1571          * vmx_check_nested_events().
1572          */
1573         if (nested_cpu_has_mtf(vmcs12) &&
1574             (!vcpu->arch.exception.pending ||
1575              vcpu->arch.exception.nr == DB_VECTOR))
1576                 vmx->nested.mtf_pending = true;
1577         else
1578                 vmx->nested.mtf_pending = false;
1579 }
1580
1581 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1582 {
1583         vmx_update_emulated_instruction(vcpu);
1584         return skip_emulated_instruction(vcpu);
1585 }
1586
1587 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1588 {
1589         /*
1590          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1591          * explicitly skip the instruction because if the HLT state is set,
1592          * then the instruction is already executing and RIP has already been
1593          * advanced.
1594          */
1595         if (kvm_hlt_in_guest(vcpu->kvm) &&
1596                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1597                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1598 }
1599
1600 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1601 {
1602         struct vcpu_vmx *vmx = to_vmx(vcpu);
1603         unsigned nr = vcpu->arch.exception.nr;
1604         bool has_error_code = vcpu->arch.exception.has_error_code;
1605         u32 error_code = vcpu->arch.exception.error_code;
1606         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1607
1608         kvm_deliver_exception_payload(vcpu);
1609
1610         if (has_error_code) {
1611                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1612                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1613         }
1614
1615         if (vmx->rmode.vm86_active) {
1616                 int inc_eip = 0;
1617                 if (kvm_exception_is_soft(nr))
1618                         inc_eip = vcpu->arch.event_exit_inst_len;
1619                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1620                 return;
1621         }
1622
1623         WARN_ON_ONCE(vmx->emulation_required);
1624
1625         if (kvm_exception_is_soft(nr)) {
1626                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1627                              vmx->vcpu.arch.event_exit_inst_len);
1628                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1629         } else
1630                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1631
1632         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1633
1634         vmx_clear_hlt(vcpu);
1635 }
1636
1637 static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr,
1638                                bool load_into_hardware)
1639 {
1640         struct vmx_uret_msr *uret_msr;
1641
1642         uret_msr = vmx_find_uret_msr(vmx, msr);
1643         if (!uret_msr)
1644                 return;
1645
1646         uret_msr->load_into_hardware = load_into_hardware;
1647 }
1648
1649 /*
1650  * Configuring user return MSRs to automatically save, load, and restore MSRs
1651  * that need to be shoved into hardware when running the guest.  Note, omitting
1652  * an MSR here does _NOT_ mean it's not emulated, only that it will not be
1653  * loaded into hardware when running the guest.
1654  */
1655 static void vmx_setup_uret_msrs(struct vcpu_vmx *vmx)
1656 {
1657 #ifdef CONFIG_X86_64
1658         bool load_syscall_msrs;
1659
1660         /*
1661          * The SYSCALL MSRs are only needed on long mode guests, and only
1662          * when EFER.SCE is set.
1663          */
1664         load_syscall_msrs = is_long_mode(&vmx->vcpu) &&
1665                             (vmx->vcpu.arch.efer & EFER_SCE);
1666
1667         vmx_setup_uret_msr(vmx, MSR_STAR, load_syscall_msrs);
1668         vmx_setup_uret_msr(vmx, MSR_LSTAR, load_syscall_msrs);
1669         vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK, load_syscall_msrs);
1670 #endif
1671         vmx_setup_uret_msr(vmx, MSR_EFER, update_transition_efer(vmx));
1672
1673         vmx_setup_uret_msr(vmx, MSR_TSC_AUX,
1674                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP) ||
1675                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDPID));
1676
1677         /*
1678          * hle=0, rtm=0, tsx_ctrl=1 can be found with some combinations of new
1679          * kernel and old userspace.  If those guests run on a tsx=off host, do
1680          * allow guests to use TSX_CTRL, but don't change the value in hardware
1681          * so that TSX remains always disabled.
1682          */
1683         vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL, boot_cpu_has(X86_FEATURE_RTM));
1684
1685         /*
1686          * The set of MSRs to load may have changed, reload MSRs before the
1687          * next VM-Enter.
1688          */
1689         vmx->guest_uret_msrs_loaded = false;
1690 }
1691
1692 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1693 {
1694         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1695
1696         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING))
1697                 return vmcs12->tsc_offset;
1698
1699         return 0;
1700 }
1701
1702 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1703 {
1704         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1705
1706         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING) &&
1707             nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
1708                 return vmcs12->tsc_multiplier;
1709
1710         return kvm_default_tsc_scaling_ratio;
1711 }
1712
1713 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1714 {
1715         vmcs_write64(TSC_OFFSET, offset);
1716 }
1717
1718 static void vmx_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1719 {
1720         vmcs_write64(TSC_MULTIPLIER, multiplier);
1721 }
1722
1723 /*
1724  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1725  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1726  * all guests if the "nested" module option is off, and can also be disabled
1727  * for a single guest by disabling its VMX cpuid bit.
1728  */
1729 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1730 {
1731         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1732 }
1733
1734 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1735                                                  uint64_t val)
1736 {
1737         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1738
1739         return !(val & ~valid_bits);
1740 }
1741
1742 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1743 {
1744         switch (msr->index) {
1745         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1746                 if (!nested)
1747                         return 1;
1748                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1749         case MSR_IA32_PERF_CAPABILITIES:
1750                 msr->data = vmx_get_perf_capabilities();
1751                 return 0;
1752         default:
1753                 return KVM_MSR_RET_INVALID;
1754         }
1755 }
1756
1757 /*
1758  * Reads an msr value (of 'msr_index') into 'pdata'.
1759  * Returns 0 on success, non-0 otherwise.
1760  * Assumes vcpu_load() was already called.
1761  */
1762 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1763 {
1764         struct vcpu_vmx *vmx = to_vmx(vcpu);
1765         struct vmx_uret_msr *msr;
1766         u32 index;
1767
1768         switch (msr_info->index) {
1769 #ifdef CONFIG_X86_64
1770         case MSR_FS_BASE:
1771                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1772                 break;
1773         case MSR_GS_BASE:
1774                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1775                 break;
1776         case MSR_KERNEL_GS_BASE:
1777                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1778                 break;
1779 #endif
1780         case MSR_EFER:
1781                 return kvm_get_msr_common(vcpu, msr_info);
1782         case MSR_IA32_TSX_CTRL:
1783                 if (!msr_info->host_initiated &&
1784                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1785                         return 1;
1786                 goto find_uret_msr;
1787         case MSR_IA32_UMWAIT_CONTROL:
1788                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1789                         return 1;
1790
1791                 msr_info->data = vmx->msr_ia32_umwait_control;
1792                 break;
1793         case MSR_IA32_SPEC_CTRL:
1794                 if (!msr_info->host_initiated &&
1795                     !guest_has_spec_ctrl_msr(vcpu))
1796                         return 1;
1797
1798                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1799                 break;
1800         case MSR_IA32_SYSENTER_CS:
1801                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1802                 break;
1803         case MSR_IA32_SYSENTER_EIP:
1804                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1805                 break;
1806         case MSR_IA32_SYSENTER_ESP:
1807                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1808                 break;
1809         case MSR_IA32_BNDCFGS:
1810                 if (!kvm_mpx_supported() ||
1811                     (!msr_info->host_initiated &&
1812                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1813                         return 1;
1814                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1815                 break;
1816         case MSR_IA32_MCG_EXT_CTL:
1817                 if (!msr_info->host_initiated &&
1818                     !(vmx->msr_ia32_feature_control &
1819                       FEAT_CTL_LMCE_ENABLED))
1820                         return 1;
1821                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1822                 break;
1823         case MSR_IA32_FEAT_CTL:
1824                 msr_info->data = vmx->msr_ia32_feature_control;
1825                 break;
1826         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
1827                 if (!msr_info->host_initiated &&
1828                     !guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
1829                         return 1;
1830                 msr_info->data = to_vmx(vcpu)->msr_ia32_sgxlepubkeyhash
1831                         [msr_info->index - MSR_IA32_SGXLEPUBKEYHASH0];
1832                 break;
1833         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1834                 if (!nested_vmx_allowed(vcpu))
1835                         return 1;
1836                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1837                                     &msr_info->data))
1838                         return 1;
1839                 /*
1840                  * Enlightened VMCS v1 doesn't have certain fields, but buggy
1841                  * Hyper-V versions are still trying to use corresponding
1842                  * features when they are exposed. Filter out the essential
1843                  * minimum.
1844                  */
1845                 if (!msr_info->host_initiated &&
1846                     vmx->nested.enlightened_vmcs_enabled)
1847                         nested_evmcs_filter_control_msr(msr_info->index,
1848                                                         &msr_info->data);
1849                 break;
1850         case MSR_IA32_RTIT_CTL:
1851                 if (!vmx_pt_mode_is_host_guest())
1852                         return 1;
1853                 msr_info->data = vmx->pt_desc.guest.ctl;
1854                 break;
1855         case MSR_IA32_RTIT_STATUS:
1856                 if (!vmx_pt_mode_is_host_guest())
1857                         return 1;
1858                 msr_info->data = vmx->pt_desc.guest.status;
1859                 break;
1860         case MSR_IA32_RTIT_CR3_MATCH:
1861                 if (!vmx_pt_mode_is_host_guest() ||
1862                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1863                                                 PT_CAP_cr3_filtering))
1864                         return 1;
1865                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1866                 break;
1867         case MSR_IA32_RTIT_OUTPUT_BASE:
1868                 if (!vmx_pt_mode_is_host_guest() ||
1869                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1870                                         PT_CAP_topa_output) &&
1871                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1872                                         PT_CAP_single_range_output)))
1873                         return 1;
1874                 msr_info->data = vmx->pt_desc.guest.output_base;
1875                 break;
1876         case MSR_IA32_RTIT_OUTPUT_MASK:
1877                 if (!vmx_pt_mode_is_host_guest() ||
1878                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1879                                         PT_CAP_topa_output) &&
1880                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1881                                         PT_CAP_single_range_output)))
1882                         return 1;
1883                 msr_info->data = vmx->pt_desc.guest.output_mask;
1884                 break;
1885         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1886                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1887                 if (!vmx_pt_mode_is_host_guest() ||
1888                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1889                                         PT_CAP_num_address_ranges)))
1890                         return 1;
1891                 if (index % 2)
1892                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1893                 else
1894                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1895                 break;
1896         case MSR_IA32_DEBUGCTLMSR:
1897                 msr_info->data = vmcs_read64(GUEST_IA32_DEBUGCTL);
1898                 break;
1899         default:
1900         find_uret_msr:
1901                 msr = vmx_find_uret_msr(vmx, msr_info->index);
1902                 if (msr) {
1903                         msr_info->data = msr->data;
1904                         break;
1905                 }
1906                 return kvm_get_msr_common(vcpu, msr_info);
1907         }
1908
1909         return 0;
1910 }
1911
1912 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1913                                                     u64 data)
1914 {
1915 #ifdef CONFIG_X86_64
1916         if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1917                 return (u32)data;
1918 #endif
1919         return (unsigned long)data;
1920 }
1921
1922 static u64 vcpu_supported_debugctl(struct kvm_vcpu *vcpu)
1923 {
1924         u64 debugctl = vmx_supported_debugctl();
1925
1926         if (!intel_pmu_lbr_is_enabled(vcpu))
1927                 debugctl &= ~DEBUGCTLMSR_LBR_MASK;
1928
1929         if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1930                 debugctl &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1931
1932         return debugctl;
1933 }
1934
1935 /*
1936  * Writes msr value into the appropriate "register".
1937  * Returns 0 on success, non-0 otherwise.
1938  * Assumes vcpu_load() was already called.
1939  */
1940 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1941 {
1942         struct vcpu_vmx *vmx = to_vmx(vcpu);
1943         struct vmx_uret_msr *msr;
1944         int ret = 0;
1945         u32 msr_index = msr_info->index;
1946         u64 data = msr_info->data;
1947         u32 index;
1948
1949         switch (msr_index) {
1950         case MSR_EFER:
1951                 ret = kvm_set_msr_common(vcpu, msr_info);
1952                 break;
1953 #ifdef CONFIG_X86_64
1954         case MSR_FS_BASE:
1955                 vmx_segment_cache_clear(vmx);
1956                 vmcs_writel(GUEST_FS_BASE, data);
1957                 break;
1958         case MSR_GS_BASE:
1959                 vmx_segment_cache_clear(vmx);
1960                 vmcs_writel(GUEST_GS_BASE, data);
1961                 break;
1962         case MSR_KERNEL_GS_BASE:
1963                 vmx_write_guest_kernel_gs_base(vmx, data);
1964                 break;
1965 #endif
1966         case MSR_IA32_SYSENTER_CS:
1967                 if (is_guest_mode(vcpu))
1968                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1969                 vmcs_write32(GUEST_SYSENTER_CS, data);
1970                 break;
1971         case MSR_IA32_SYSENTER_EIP:
1972                 if (is_guest_mode(vcpu)) {
1973                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1974                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1975                 }
1976                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1977                 break;
1978         case MSR_IA32_SYSENTER_ESP:
1979                 if (is_guest_mode(vcpu)) {
1980                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1981                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1982                 }
1983                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1984                 break;
1985         case MSR_IA32_DEBUGCTLMSR: {
1986                 u64 invalid = data & ~vcpu_supported_debugctl(vcpu);
1987                 if (invalid & (DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR)) {
1988                         if (report_ignored_msrs)
1989                                 vcpu_unimpl(vcpu, "%s: BTF|LBR in IA32_DEBUGCTLMSR 0x%llx, nop\n",
1990                                             __func__, data);
1991                         data &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1992                         invalid &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1993                 }
1994
1995                 if (invalid)
1996                         return 1;
1997
1998                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1999                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
2000                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2001
2002                 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
2003                 if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event &&
2004                     (data & DEBUGCTLMSR_LBR))
2005                         intel_pmu_create_guest_lbr_event(vcpu);
2006                 return 0;
2007         }
2008         case MSR_IA32_BNDCFGS:
2009                 if (!kvm_mpx_supported() ||
2010                     (!msr_info->host_initiated &&
2011                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2012                         return 1;
2013                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2014                     (data & MSR_IA32_BNDCFGS_RSVD))
2015                         return 1;
2016                 vmcs_write64(GUEST_BNDCFGS, data);
2017                 break;
2018         case MSR_IA32_UMWAIT_CONTROL:
2019                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2020                         return 1;
2021
2022                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2023                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2024                         return 1;
2025
2026                 vmx->msr_ia32_umwait_control = data;
2027                 break;
2028         case MSR_IA32_SPEC_CTRL:
2029                 if (!msr_info->host_initiated &&
2030                     !guest_has_spec_ctrl_msr(vcpu))
2031                         return 1;
2032
2033                 if (kvm_spec_ctrl_test_value(data))
2034                         return 1;
2035
2036                 vmx->spec_ctrl = data;
2037                 if (!data)
2038                         break;
2039
2040                 /*
2041                  * For non-nested:
2042                  * When it's written (to non-zero) for the first time, pass
2043                  * it through.
2044                  *
2045                  * For nested:
2046                  * The handling of the MSR bitmap for L2 guests is done in
2047                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2048                  * vmcs02.msr_bitmap here since it gets completely overwritten
2049                  * in the merging. We update the vmcs01 here for L1 as well
2050                  * since it will end up touching the MSR anyway now.
2051                  */
2052                 vmx_disable_intercept_for_msr(vcpu,
2053                                               MSR_IA32_SPEC_CTRL,
2054                                               MSR_TYPE_RW);
2055                 break;
2056         case MSR_IA32_TSX_CTRL:
2057                 if (!msr_info->host_initiated &&
2058                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2059                         return 1;
2060                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2061                         return 1;
2062                 goto find_uret_msr;
2063         case MSR_IA32_PRED_CMD:
2064                 if (!msr_info->host_initiated &&
2065                     !guest_has_pred_cmd_msr(vcpu))
2066                         return 1;
2067
2068                 if (data & ~PRED_CMD_IBPB)
2069                         return 1;
2070                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2071                         return 1;
2072                 if (!data)
2073                         break;
2074
2075                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2076
2077                 /*
2078                  * For non-nested:
2079                  * When it's written (to non-zero) for the first time, pass
2080                  * it through.
2081                  *
2082                  * For nested:
2083                  * The handling of the MSR bitmap for L2 guests is done in
2084                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2085                  * vmcs02.msr_bitmap here since it gets completely overwritten
2086                  * in the merging.
2087                  */
2088                 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
2089                 break;
2090         case MSR_IA32_CR_PAT:
2091                 if (!kvm_pat_valid(data))
2092                         return 1;
2093
2094                 if (is_guest_mode(vcpu) &&
2095                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2096                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2097
2098                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2099                         vmcs_write64(GUEST_IA32_PAT, data);
2100                         vcpu->arch.pat = data;
2101                         break;
2102                 }
2103                 ret = kvm_set_msr_common(vcpu, msr_info);
2104                 break;
2105         case MSR_IA32_TSC_ADJUST:
2106                 ret = kvm_set_msr_common(vcpu, msr_info);
2107                 break;
2108         case MSR_IA32_MCG_EXT_CTL:
2109                 if ((!msr_info->host_initiated &&
2110                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2111                        FEAT_CTL_LMCE_ENABLED)) ||
2112                     (data & ~MCG_EXT_CTL_LMCE_EN))
2113                         return 1;
2114                 vcpu->arch.mcg_ext_ctl = data;
2115                 break;
2116         case MSR_IA32_FEAT_CTL:
2117                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2118                     (to_vmx(vcpu)->msr_ia32_feature_control &
2119                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2120                         return 1;
2121                 vmx->msr_ia32_feature_control = data;
2122                 if (msr_info->host_initiated && data == 0)
2123                         vmx_leave_nested(vcpu);
2124
2125                 /* SGX may be enabled/disabled by guest's firmware */
2126                 vmx_write_encls_bitmap(vcpu, NULL);
2127                 break;
2128         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
2129                 /*
2130                  * On real hardware, the LE hash MSRs are writable before
2131                  * the firmware sets bit 0 in MSR 0x7a ("activating" SGX),
2132                  * at which point SGX related bits in IA32_FEATURE_CONTROL
2133                  * become writable.
2134                  *
2135                  * KVM does not emulate SGX activation for simplicity, so
2136                  * allow writes to the LE hash MSRs if IA32_FEATURE_CONTROL
2137                  * is unlocked.  This is technically not architectural
2138                  * behavior, but it's close enough.
2139                  */
2140                 if (!msr_info->host_initiated &&
2141                     (!guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC) ||
2142                     ((vmx->msr_ia32_feature_control & FEAT_CTL_LOCKED) &&
2143                     !(vmx->msr_ia32_feature_control & FEAT_CTL_SGX_LC_ENABLED))))
2144                         return 1;
2145                 vmx->msr_ia32_sgxlepubkeyhash
2146                         [msr_index - MSR_IA32_SGXLEPUBKEYHASH0] = data;
2147                 break;
2148         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2149                 if (!msr_info->host_initiated)
2150                         return 1; /* they are read-only */
2151                 if (!nested_vmx_allowed(vcpu))
2152                         return 1;
2153                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2154         case MSR_IA32_RTIT_CTL:
2155                 if (!vmx_pt_mode_is_host_guest() ||
2156                         vmx_rtit_ctl_check(vcpu, data) ||
2157                         vmx->nested.vmxon)
2158                         return 1;
2159                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2160                 vmx->pt_desc.guest.ctl = data;
2161                 pt_update_intercept_for_msr(vcpu);
2162                 break;
2163         case MSR_IA32_RTIT_STATUS:
2164                 if (!pt_can_write_msr(vmx))
2165                         return 1;
2166                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2167                         return 1;
2168                 vmx->pt_desc.guest.status = data;
2169                 break;
2170         case MSR_IA32_RTIT_CR3_MATCH:
2171                 if (!pt_can_write_msr(vmx))
2172                         return 1;
2173                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2174                                            PT_CAP_cr3_filtering))
2175                         return 1;
2176                 vmx->pt_desc.guest.cr3_match = data;
2177                 break;
2178         case MSR_IA32_RTIT_OUTPUT_BASE:
2179                 if (!pt_can_write_msr(vmx))
2180                         return 1;
2181                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2182                                            PT_CAP_topa_output) &&
2183                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2184                                            PT_CAP_single_range_output))
2185                         return 1;
2186                 if (!pt_output_base_valid(vcpu, data))
2187                         return 1;
2188                 vmx->pt_desc.guest.output_base = data;
2189                 break;
2190         case MSR_IA32_RTIT_OUTPUT_MASK:
2191                 if (!pt_can_write_msr(vmx))
2192                         return 1;
2193                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2194                                            PT_CAP_topa_output) &&
2195                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2196                                            PT_CAP_single_range_output))
2197                         return 1;
2198                 vmx->pt_desc.guest.output_mask = data;
2199                 break;
2200         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2201                 if (!pt_can_write_msr(vmx))
2202                         return 1;
2203                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2204                 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2205                                                        PT_CAP_num_address_ranges))
2206                         return 1;
2207                 if (is_noncanonical_address(data, vcpu))
2208                         return 1;
2209                 if (index % 2)
2210                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2211                 else
2212                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2213                 break;
2214         case MSR_IA32_PERF_CAPABILITIES:
2215                 if (data && !vcpu_to_pmu(vcpu)->version)
2216                         return 1;
2217                 if (data & PMU_CAP_LBR_FMT) {
2218                         if ((data & PMU_CAP_LBR_FMT) !=
2219                             (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
2220                                 return 1;
2221                         if (!intel_pmu_lbr_is_compatible(vcpu))
2222                                 return 1;
2223                 }
2224                 ret = kvm_set_msr_common(vcpu, msr_info);
2225                 break;
2226
2227         default:
2228         find_uret_msr:
2229                 msr = vmx_find_uret_msr(vmx, msr_index);
2230                 if (msr)
2231                         ret = vmx_set_guest_uret_msr(vmx, msr, data);
2232                 else
2233                         ret = kvm_set_msr_common(vcpu, msr_info);
2234         }
2235
2236         return ret;
2237 }
2238
2239 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2240 {
2241         unsigned long guest_owned_bits;
2242
2243         kvm_register_mark_available(vcpu, reg);
2244
2245         switch (reg) {
2246         case VCPU_REGS_RSP:
2247                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2248                 break;
2249         case VCPU_REGS_RIP:
2250                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2251                 break;
2252         case VCPU_EXREG_PDPTR:
2253                 if (enable_ept)
2254                         ept_save_pdptrs(vcpu);
2255                 break;
2256         case VCPU_EXREG_CR0:
2257                 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2258
2259                 vcpu->arch.cr0 &= ~guest_owned_bits;
2260                 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2261                 break;
2262         case VCPU_EXREG_CR3:
2263                 /*
2264                  * When intercepting CR3 loads, e.g. for shadowing paging, KVM's
2265                  * CR3 is loaded into hardware, not the guest's CR3.
2266                  */
2267                 if (!(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_CR3_LOAD_EXITING))
2268                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2269                 break;
2270         case VCPU_EXREG_CR4:
2271                 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2272
2273                 vcpu->arch.cr4 &= ~guest_owned_bits;
2274                 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2275                 break;
2276         default:
2277                 KVM_BUG_ON(1, vcpu->kvm);
2278                 break;
2279         }
2280 }
2281
2282 static __init int cpu_has_kvm_support(void)
2283 {
2284         return cpu_has_vmx();
2285 }
2286
2287 static __init int vmx_disabled_by_bios(void)
2288 {
2289         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2290                !boot_cpu_has(X86_FEATURE_VMX);
2291 }
2292
2293 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2294 {
2295         u64 msr;
2296
2297         cr4_set_bits(X86_CR4_VMXE);
2298
2299         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2300                           _ASM_EXTABLE(1b, %l[fault])
2301                           : : [vmxon_pointer] "m"(vmxon_pointer)
2302                           : : fault);
2303         return 0;
2304
2305 fault:
2306         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2307                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2308         cr4_clear_bits(X86_CR4_VMXE);
2309
2310         return -EFAULT;
2311 }
2312
2313 static int hardware_enable(void)
2314 {
2315         int cpu = raw_smp_processor_id();
2316         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2317         int r;
2318
2319         if (cr4_read_shadow() & X86_CR4_VMXE)
2320                 return -EBUSY;
2321
2322         /*
2323          * This can happen if we hot-added a CPU but failed to allocate
2324          * VP assist page for it.
2325          */
2326         if (static_branch_unlikely(&enable_evmcs) &&
2327             !hv_get_vp_assist_page(cpu))
2328                 return -EFAULT;
2329
2330         intel_pt_handle_vmx(1);
2331
2332         r = kvm_cpu_vmxon(phys_addr);
2333         if (r) {
2334                 intel_pt_handle_vmx(0);
2335                 return r;
2336         }
2337
2338         if (enable_ept)
2339                 ept_sync_global();
2340
2341         return 0;
2342 }
2343
2344 static void vmclear_local_loaded_vmcss(void)
2345 {
2346         int cpu = raw_smp_processor_id();
2347         struct loaded_vmcs *v, *n;
2348
2349         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2350                                  loaded_vmcss_on_cpu_link)
2351                 __loaded_vmcs_clear(v);
2352 }
2353
2354 static void hardware_disable(void)
2355 {
2356         vmclear_local_loaded_vmcss();
2357
2358         if (cpu_vmxoff())
2359                 kvm_spurious_fault();
2360
2361         intel_pt_handle_vmx(0);
2362 }
2363
2364 /*
2365  * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2366  * directly instead of going through cpu_has(), to ensure KVM is trapping
2367  * ENCLS whenever it's supported in hardware.  It does not matter whether
2368  * the host OS supports or has enabled SGX.
2369  */
2370 static bool cpu_has_sgx(void)
2371 {
2372         return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2373 }
2374
2375 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2376                                       u32 msr, u32 *result)
2377 {
2378         u32 vmx_msr_low, vmx_msr_high;
2379         u32 ctl = ctl_min | ctl_opt;
2380
2381         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2382
2383         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2384         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2385
2386         /* Ensure minimum (required) set of control bits are supported. */
2387         if (ctl_min & ~ctl)
2388                 return -EIO;
2389
2390         *result = ctl;
2391         return 0;
2392 }
2393
2394 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2395                                     struct vmx_capability *vmx_cap)
2396 {
2397         u32 vmx_msr_low, vmx_msr_high;
2398         u32 min, opt, min2, opt2;
2399         u32 _pin_based_exec_control = 0;
2400         u32 _cpu_based_exec_control = 0;
2401         u32 _cpu_based_2nd_exec_control = 0;
2402         u32 _vmexit_control = 0;
2403         u32 _vmentry_control = 0;
2404
2405         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2406         min = CPU_BASED_HLT_EXITING |
2407 #ifdef CONFIG_X86_64
2408               CPU_BASED_CR8_LOAD_EXITING |
2409               CPU_BASED_CR8_STORE_EXITING |
2410 #endif
2411               CPU_BASED_CR3_LOAD_EXITING |
2412               CPU_BASED_CR3_STORE_EXITING |
2413               CPU_BASED_UNCOND_IO_EXITING |
2414               CPU_BASED_MOV_DR_EXITING |
2415               CPU_BASED_USE_TSC_OFFSETTING |
2416               CPU_BASED_MWAIT_EXITING |
2417               CPU_BASED_MONITOR_EXITING |
2418               CPU_BASED_INVLPG_EXITING |
2419               CPU_BASED_RDPMC_EXITING;
2420
2421         opt = CPU_BASED_TPR_SHADOW |
2422               CPU_BASED_USE_MSR_BITMAPS |
2423               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2424         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2425                                 &_cpu_based_exec_control) < 0)
2426                 return -EIO;
2427 #ifdef CONFIG_X86_64
2428         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2429                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2430                                            ~CPU_BASED_CR8_STORE_EXITING;
2431 #endif
2432         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2433                 min2 = 0;
2434                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2435                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2436                         SECONDARY_EXEC_WBINVD_EXITING |
2437                         SECONDARY_EXEC_ENABLE_VPID |
2438                         SECONDARY_EXEC_ENABLE_EPT |
2439                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2440                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2441                         SECONDARY_EXEC_DESC |
2442                         SECONDARY_EXEC_ENABLE_RDTSCP |
2443                         SECONDARY_EXEC_ENABLE_INVPCID |
2444                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2445                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2446                         SECONDARY_EXEC_SHADOW_VMCS |
2447                         SECONDARY_EXEC_XSAVES |
2448                         SECONDARY_EXEC_RDSEED_EXITING |
2449                         SECONDARY_EXEC_RDRAND_EXITING |
2450                         SECONDARY_EXEC_ENABLE_PML |
2451                         SECONDARY_EXEC_TSC_SCALING |
2452                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2453                         SECONDARY_EXEC_PT_USE_GPA |
2454                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2455                         SECONDARY_EXEC_ENABLE_VMFUNC |
2456                         SECONDARY_EXEC_BUS_LOCK_DETECTION;
2457                 if (cpu_has_sgx())
2458                         opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2459                 if (adjust_vmx_controls(min2, opt2,
2460                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2461                                         &_cpu_based_2nd_exec_control) < 0)
2462                         return -EIO;
2463         }
2464 #ifndef CONFIG_X86_64
2465         if (!(_cpu_based_2nd_exec_control &
2466                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2467                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2468 #endif
2469
2470         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2471                 _cpu_based_2nd_exec_control &= ~(
2472                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2473                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2474                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2475
2476         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2477                 &vmx_cap->ept, &vmx_cap->vpid);
2478
2479         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2480                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2481                    enabled */
2482                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2483                                              CPU_BASED_CR3_STORE_EXITING |
2484                                              CPU_BASED_INVLPG_EXITING);
2485         } else if (vmx_cap->ept) {
2486                 vmx_cap->ept = 0;
2487                 pr_warn_once("EPT CAP should not exist if not support "
2488                                 "1-setting enable EPT VM-execution control\n");
2489         }
2490         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2491                 vmx_cap->vpid) {
2492                 vmx_cap->vpid = 0;
2493                 pr_warn_once("VPID CAP should not exist if not support "
2494                                 "1-setting enable VPID VM-execution control\n");
2495         }
2496
2497         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2498 #ifdef CONFIG_X86_64
2499         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2500 #endif
2501         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2502               VM_EXIT_LOAD_IA32_PAT |
2503               VM_EXIT_LOAD_IA32_EFER |
2504               VM_EXIT_CLEAR_BNDCFGS |
2505               VM_EXIT_PT_CONCEAL_PIP |
2506               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2507         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2508                                 &_vmexit_control) < 0)
2509                 return -EIO;
2510
2511         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2512         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2513                  PIN_BASED_VMX_PREEMPTION_TIMER;
2514         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2515                                 &_pin_based_exec_control) < 0)
2516                 return -EIO;
2517
2518         if (cpu_has_broken_vmx_preemption_timer())
2519                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2520         if (!(_cpu_based_2nd_exec_control &
2521                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2522                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2523
2524         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2525         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2526               VM_ENTRY_LOAD_IA32_PAT |
2527               VM_ENTRY_LOAD_IA32_EFER |
2528               VM_ENTRY_LOAD_BNDCFGS |
2529               VM_ENTRY_PT_CONCEAL_PIP |
2530               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2531         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2532                                 &_vmentry_control) < 0)
2533                 return -EIO;
2534
2535         /*
2536          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2537          * can't be used due to an errata where VM Exit may incorrectly clear
2538          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2539          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2540          */
2541         if (boot_cpu_data.x86 == 0x6) {
2542                 switch (boot_cpu_data.x86_model) {
2543                 case 26: /* AAK155 */
2544                 case 30: /* AAP115 */
2545                 case 37: /* AAT100 */
2546                 case 44: /* BC86,AAY89,BD102 */
2547                 case 46: /* BA97 */
2548                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2549                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2550                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2551                                         "does not work properly. Using workaround\n");
2552                         break;
2553                 default:
2554                         break;
2555                 }
2556         }
2557
2558
2559         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2560
2561         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2562         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2563                 return -EIO;
2564
2565 #ifdef CONFIG_X86_64
2566         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2567         if (vmx_msr_high & (1u<<16))
2568                 return -EIO;
2569 #endif
2570
2571         /* Require Write-Back (WB) memory type for VMCS accesses. */
2572         if (((vmx_msr_high >> 18) & 15) != 6)
2573                 return -EIO;
2574
2575         vmcs_conf->size = vmx_msr_high & 0x1fff;
2576         vmcs_conf->order = get_order(vmcs_conf->size);
2577         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2578
2579         vmcs_conf->revision_id = vmx_msr_low;
2580
2581         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2582         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2583         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2584         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2585         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2586
2587 #if IS_ENABLED(CONFIG_HYPERV)
2588         if (enlightened_vmcs)
2589                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2590 #endif
2591
2592         return 0;
2593 }
2594
2595 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2596 {
2597         int node = cpu_to_node(cpu);
2598         struct page *pages;
2599         struct vmcs *vmcs;
2600
2601         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2602         if (!pages)
2603                 return NULL;
2604         vmcs = page_address(pages);
2605         memset(vmcs, 0, vmcs_config.size);
2606
2607         /* KVM supports Enlightened VMCS v1 only */
2608         if (static_branch_unlikely(&enable_evmcs))
2609                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2610         else
2611                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2612
2613         if (shadow)
2614                 vmcs->hdr.shadow_vmcs = 1;
2615         return vmcs;
2616 }
2617
2618 void free_vmcs(struct vmcs *vmcs)
2619 {
2620         free_pages((unsigned long)vmcs, vmcs_config.order);
2621 }
2622
2623 /*
2624  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2625  */
2626 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2627 {
2628         if (!loaded_vmcs->vmcs)
2629                 return;
2630         loaded_vmcs_clear(loaded_vmcs);
2631         free_vmcs(loaded_vmcs->vmcs);
2632         loaded_vmcs->vmcs = NULL;
2633         if (loaded_vmcs->msr_bitmap)
2634                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2635         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2636 }
2637
2638 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2639 {
2640         loaded_vmcs->vmcs = alloc_vmcs(false);
2641         if (!loaded_vmcs->vmcs)
2642                 return -ENOMEM;
2643
2644         vmcs_clear(loaded_vmcs->vmcs);
2645
2646         loaded_vmcs->shadow_vmcs = NULL;
2647         loaded_vmcs->hv_timer_soft_disabled = false;
2648         loaded_vmcs->cpu = -1;
2649         loaded_vmcs->launched = 0;
2650
2651         if (cpu_has_vmx_msr_bitmap()) {
2652                 loaded_vmcs->msr_bitmap = (unsigned long *)
2653                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2654                 if (!loaded_vmcs->msr_bitmap)
2655                         goto out_vmcs;
2656                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2657
2658                 if (IS_ENABLED(CONFIG_HYPERV) &&
2659                     static_branch_unlikely(&enable_evmcs) &&
2660                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2661                         struct hv_enlightened_vmcs *evmcs =
2662                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2663
2664                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2665                 }
2666         }
2667
2668         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2669         memset(&loaded_vmcs->controls_shadow, 0,
2670                 sizeof(struct vmcs_controls_shadow));
2671
2672         return 0;
2673
2674 out_vmcs:
2675         free_loaded_vmcs(loaded_vmcs);
2676         return -ENOMEM;
2677 }
2678
2679 static void free_kvm_area(void)
2680 {
2681         int cpu;
2682
2683         for_each_possible_cpu(cpu) {
2684                 free_vmcs(per_cpu(vmxarea, cpu));
2685                 per_cpu(vmxarea, cpu) = NULL;
2686         }
2687 }
2688
2689 static __init int alloc_kvm_area(void)
2690 {
2691         int cpu;
2692
2693         for_each_possible_cpu(cpu) {
2694                 struct vmcs *vmcs;
2695
2696                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2697                 if (!vmcs) {
2698                         free_kvm_area();
2699                         return -ENOMEM;
2700                 }
2701
2702                 /*
2703                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2704                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2705                  * revision_id reported by MSR_IA32_VMX_BASIC.
2706                  *
2707                  * However, even though not explicitly documented by
2708                  * TLFS, VMXArea passed as VMXON argument should
2709                  * still be marked with revision_id reported by
2710                  * physical CPU.
2711                  */
2712                 if (static_branch_unlikely(&enable_evmcs))
2713                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2714
2715                 per_cpu(vmxarea, cpu) = vmcs;
2716         }
2717         return 0;
2718 }
2719
2720 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2721                 struct kvm_segment *save)
2722 {
2723         if (!emulate_invalid_guest_state) {
2724                 /*
2725                  * CS and SS RPL should be equal during guest entry according
2726                  * to VMX spec, but in reality it is not always so. Since vcpu
2727                  * is in the middle of the transition from real mode to
2728                  * protected mode it is safe to assume that RPL 0 is a good
2729                  * default value.
2730                  */
2731                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2732                         save->selector &= ~SEGMENT_RPL_MASK;
2733                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2734                 save->s = 1;
2735         }
2736         __vmx_set_segment(vcpu, save, seg);
2737 }
2738
2739 static void enter_pmode(struct kvm_vcpu *vcpu)
2740 {
2741         unsigned long flags;
2742         struct vcpu_vmx *vmx = to_vmx(vcpu);
2743
2744         /*
2745          * Update real mode segment cache. It may be not up-to-date if segment
2746          * register was written while vcpu was in a guest mode.
2747          */
2748         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2749         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2750         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2751         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2752         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2753         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2754
2755         vmx->rmode.vm86_active = 0;
2756
2757         __vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2758
2759         flags = vmcs_readl(GUEST_RFLAGS);
2760         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2761         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2762         vmcs_writel(GUEST_RFLAGS, flags);
2763
2764         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2765                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2766
2767         vmx_update_exception_bitmap(vcpu);
2768
2769         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2770         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2771         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2772         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2773         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2774         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2775 }
2776
2777 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2778 {
2779         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2780         struct kvm_segment var = *save;
2781
2782         var.dpl = 0x3;
2783         if (seg == VCPU_SREG_CS)
2784                 var.type = 0x3;
2785
2786         if (!emulate_invalid_guest_state) {
2787                 var.selector = var.base >> 4;
2788                 var.base = var.base & 0xffff0;
2789                 var.limit = 0xffff;
2790                 var.g = 0;
2791                 var.db = 0;
2792                 var.present = 1;
2793                 var.s = 1;
2794                 var.l = 0;
2795                 var.unusable = 0;
2796                 var.type = 0x3;
2797                 var.avl = 0;
2798                 if (save->base & 0xf)
2799                         printk_once(KERN_WARNING "kvm: segment base is not "
2800                                         "paragraph aligned when entering "
2801                                         "protected mode (seg=%d)", seg);
2802         }
2803
2804         vmcs_write16(sf->selector, var.selector);
2805         vmcs_writel(sf->base, var.base);
2806         vmcs_write32(sf->limit, var.limit);
2807         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2808 }
2809
2810 static void enter_rmode(struct kvm_vcpu *vcpu)
2811 {
2812         unsigned long flags;
2813         struct vcpu_vmx *vmx = to_vmx(vcpu);
2814         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2815
2816         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2817         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2818         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2819         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2820         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2821         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2822         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2823
2824         vmx->rmode.vm86_active = 1;
2825
2826         /*
2827          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2828          * vcpu. Warn the user that an update is overdue.
2829          */
2830         if (!kvm_vmx->tss_addr)
2831                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2832                              "called before entering vcpu\n");
2833
2834         vmx_segment_cache_clear(vmx);
2835
2836         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2837         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2838         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2839
2840         flags = vmcs_readl(GUEST_RFLAGS);
2841         vmx->rmode.save_rflags = flags;
2842
2843         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2844
2845         vmcs_writel(GUEST_RFLAGS, flags);
2846         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2847         vmx_update_exception_bitmap(vcpu);
2848
2849         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2850         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2851         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2852         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2853         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2854         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2855 }
2856
2857 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2858 {
2859         struct vcpu_vmx *vmx = to_vmx(vcpu);
2860         struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER);
2861
2862         /* Nothing to do if hardware doesn't support EFER. */
2863         if (!msr)
2864                 return 0;
2865
2866         vcpu->arch.efer = efer;
2867         if (efer & EFER_LMA) {
2868                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2869                 msr->data = efer;
2870         } else {
2871                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2872
2873                 msr->data = efer & ~EFER_LME;
2874         }
2875         vmx_setup_uret_msrs(vmx);
2876         return 0;
2877 }
2878
2879 #ifdef CONFIG_X86_64
2880
2881 static void enter_lmode(struct kvm_vcpu *vcpu)
2882 {
2883         u32 guest_tr_ar;
2884
2885         vmx_segment_cache_clear(to_vmx(vcpu));
2886
2887         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2888         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2889                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2890                                      __func__);
2891                 vmcs_write32(GUEST_TR_AR_BYTES,
2892                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2893                              | VMX_AR_TYPE_BUSY_64_TSS);
2894         }
2895         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2896 }
2897
2898 static void exit_lmode(struct kvm_vcpu *vcpu)
2899 {
2900         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2901         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2902 }
2903
2904 #endif
2905
2906 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2907 {
2908         struct vcpu_vmx *vmx = to_vmx(vcpu);
2909
2910         /*
2911          * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2912          * the CPU is not required to invalidate guest-physical mappings on
2913          * VM-Entry, even if VPID is disabled.  Guest-physical mappings are
2914          * associated with the root EPT structure and not any particular VPID
2915          * (INVVPID also isn't required to invalidate guest-physical mappings).
2916          */
2917         if (enable_ept) {
2918                 ept_sync_global();
2919         } else if (enable_vpid) {
2920                 if (cpu_has_vmx_invvpid_global()) {
2921                         vpid_sync_vcpu_global();
2922                 } else {
2923                         vpid_sync_vcpu_single(vmx->vpid);
2924                         vpid_sync_vcpu_single(vmx->nested.vpid02);
2925                 }
2926         }
2927 }
2928
2929 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2930 {
2931         struct kvm_mmu *mmu = vcpu->arch.mmu;
2932         u64 root_hpa = mmu->root_hpa;
2933
2934         /* No flush required if the current context is invalid. */
2935         if (!VALID_PAGE(root_hpa))
2936                 return;
2937
2938         if (enable_ept)
2939                 ept_sync_context(construct_eptp(vcpu, root_hpa,
2940                                                 mmu->shadow_root_level));
2941         else if (!is_guest_mode(vcpu))
2942                 vpid_sync_context(to_vmx(vcpu)->vpid);
2943         else
2944                 vpid_sync_context(nested_get_vpid02(vcpu));
2945 }
2946
2947 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2948 {
2949         /*
2950          * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2951          * vmx_flush_tlb_guest() for an explanation of why this is ok.
2952          */
2953         vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2954 }
2955
2956 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2957 {
2958         /*
2959          * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2960          * or a vpid couldn't be allocated for this vCPU.  VM-Enter and VM-Exit
2961          * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2962          * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2963          * i.e. no explicit INVVPID is necessary.
2964          */
2965         vpid_sync_context(to_vmx(vcpu)->vpid);
2966 }
2967
2968 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2969 {
2970         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2971
2972         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2973                 return;
2974
2975         if (is_pae_paging(vcpu)) {
2976                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2977                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2978                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2979                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2980         }
2981 }
2982
2983 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2984 {
2985         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2986
2987         if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2988                 return;
2989
2990         mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2991         mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2992         mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2993         mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2994
2995         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2996 }
2997
2998 #define CR3_EXITING_BITS (CPU_BASED_CR3_LOAD_EXITING | \
2999                           CPU_BASED_CR3_STORE_EXITING)
3000
3001 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3002 {
3003         struct vcpu_vmx *vmx = to_vmx(vcpu);
3004         unsigned long hw_cr0, old_cr0_pg;
3005         u32 tmp;
3006
3007         old_cr0_pg = kvm_read_cr0_bits(vcpu, X86_CR0_PG);
3008
3009         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3010         if (is_unrestricted_guest(vcpu))
3011                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3012         else {
3013                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3014                 if (!enable_ept)
3015                         hw_cr0 |= X86_CR0_WP;
3016
3017                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3018                         enter_pmode(vcpu);
3019
3020                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3021                         enter_rmode(vcpu);
3022         }
3023
3024         vmcs_writel(CR0_READ_SHADOW, cr0);
3025         vmcs_writel(GUEST_CR0, hw_cr0);
3026         vcpu->arch.cr0 = cr0;
3027         kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3028
3029 #ifdef CONFIG_X86_64
3030         if (vcpu->arch.efer & EFER_LME) {
3031                 if (!old_cr0_pg && (cr0 & X86_CR0_PG))
3032                         enter_lmode(vcpu);
3033                 else if (old_cr0_pg && !(cr0 & X86_CR0_PG))
3034                         exit_lmode(vcpu);
3035         }
3036 #endif
3037
3038         if (enable_ept && !is_unrestricted_guest(vcpu)) {
3039                 /*
3040                  * Ensure KVM has an up-to-date snapshot of the guest's CR3.  If
3041                  * the below code _enables_ CR3 exiting, vmx_cache_reg() will
3042                  * (correctly) stop reading vmcs.GUEST_CR3 because it thinks
3043                  * KVM's CR3 is installed.
3044                  */
3045                 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
3046                         vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
3047
3048                 /*
3049                  * When running with EPT but not unrestricted guest, KVM must
3050                  * intercept CR3 accesses when paging is _disabled_.  This is
3051                  * necessary because restricted guests can't actually run with
3052                  * paging disabled, and so KVM stuffs its own CR3 in order to
3053                  * run the guest when identity mapped page tables.
3054                  *
3055                  * Do _NOT_ check the old CR0.PG, e.g. to optimize away the
3056                  * update, it may be stale with respect to CR3 interception,
3057                  * e.g. after nested VM-Enter.
3058                  *
3059                  * Lastly, honor L1's desires, i.e. intercept CR3 loads and/or
3060                  * stores to forward them to L1, even if KVM does not need to
3061                  * intercept them to preserve its identity mapped page tables.
3062                  */
3063                 if (!(cr0 & X86_CR0_PG)) {
3064                         exec_controls_setbit(vmx, CR3_EXITING_BITS);
3065                 } else if (!is_guest_mode(vcpu)) {
3066                         exec_controls_clearbit(vmx, CR3_EXITING_BITS);
3067                 } else {
3068                         tmp = exec_controls_get(vmx);
3069                         tmp &= ~CR3_EXITING_BITS;
3070                         tmp |= get_vmcs12(vcpu)->cpu_based_vm_exec_control & CR3_EXITING_BITS;
3071                         exec_controls_set(vmx, tmp);
3072                 }
3073
3074                 /* Note, vmx_set_cr4() consumes the new vcpu->arch.cr0. */
3075                 if ((old_cr0_pg ^ cr0) & X86_CR0_PG)
3076                         vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3077         }
3078
3079         /* depends on vcpu->arch.cr0 to be set to a new value */
3080         vmx->emulation_required = emulation_required(vcpu);
3081 }
3082
3083 static int vmx_get_max_tdp_level(void)
3084 {
3085         if (cpu_has_vmx_ept_5levels())
3086                 return 5;
3087         return 4;
3088 }
3089
3090 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level)
3091 {
3092         u64 eptp = VMX_EPTP_MT_WB;
3093
3094         eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3095
3096         if (enable_ept_ad_bits &&
3097             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3098                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3099         eptp |= root_hpa;
3100
3101         return eptp;
3102 }
3103
3104 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3105                              int root_level)
3106 {
3107         struct kvm *kvm = vcpu->kvm;
3108         bool update_guest_cr3 = true;
3109         unsigned long guest_cr3;
3110         u64 eptp;
3111
3112         if (enable_ept) {
3113                 eptp = construct_eptp(vcpu, root_hpa, root_level);
3114                 vmcs_write64(EPT_POINTER, eptp);
3115
3116                 hv_track_root_tdp(vcpu, root_hpa);
3117
3118                 if (!enable_unrestricted_guest && !is_paging(vcpu))
3119                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3120                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3121                         guest_cr3 = vcpu->arch.cr3;
3122                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3123                         update_guest_cr3 = false;
3124                 vmx_ept_load_pdptrs(vcpu);
3125         } else {
3126                 guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu);
3127         }
3128
3129         if (update_guest_cr3)
3130                 vmcs_writel(GUEST_CR3, guest_cr3);
3131 }
3132
3133 static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3134 {
3135         /*
3136          * We operate under the default treatment of SMM, so VMX cannot be
3137          * enabled under SMM.  Note, whether or not VMXE is allowed at all is
3138          * handled by kvm_is_valid_cr4().
3139          */
3140         if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu))
3141                 return false;
3142
3143         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3144                 return false;
3145
3146         return true;
3147 }
3148
3149 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3150 {
3151         unsigned long old_cr4 = vcpu->arch.cr4;
3152         struct vcpu_vmx *vmx = to_vmx(vcpu);
3153         /*
3154          * Pass through host's Machine Check Enable value to hw_cr4, which
3155          * is in force while we are in guest mode.  Do not let guests control
3156          * this bit, even if host CR4.MCE == 0.
3157          */
3158         unsigned long hw_cr4;
3159
3160         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3161         if (is_unrestricted_guest(vcpu))
3162                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3163         else if (vmx->rmode.vm86_active)
3164                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3165         else
3166                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3167
3168         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3169                 if (cr4 & X86_CR4_UMIP) {
3170                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3171                         hw_cr4 &= ~X86_CR4_UMIP;
3172                 } else if (!is_guest_mode(vcpu) ||
3173                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3174                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3175                 }
3176         }
3177
3178         vcpu->arch.cr4 = cr4;
3179         kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3180
3181         if (!is_unrestricted_guest(vcpu)) {
3182                 if (enable_ept) {
3183                         if (!is_paging(vcpu)) {
3184                                 hw_cr4 &= ~X86_CR4_PAE;
3185                                 hw_cr4 |= X86_CR4_PSE;
3186                         } else if (!(cr4 & X86_CR4_PAE)) {
3187                                 hw_cr4 &= ~X86_CR4_PAE;
3188                         }
3189                 }
3190
3191                 /*
3192                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3193                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3194                  * to be manually disabled when guest switches to non-paging
3195                  * mode.
3196                  *
3197                  * If !enable_unrestricted_guest, the CPU is always running
3198                  * with CR0.PG=1 and CR4 needs to be modified.
3199                  * If enable_unrestricted_guest, the CPU automatically
3200                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3201                  */
3202                 if (!is_paging(vcpu))
3203                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3204         }
3205
3206         vmcs_writel(CR4_READ_SHADOW, cr4);
3207         vmcs_writel(GUEST_CR4, hw_cr4);
3208
3209         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
3210                 kvm_update_cpuid_runtime(vcpu);
3211 }
3212
3213 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3214 {
3215         struct vcpu_vmx *vmx = to_vmx(vcpu);
3216         u32 ar;
3217
3218         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3219                 *var = vmx->rmode.segs[seg];
3220                 if (seg == VCPU_SREG_TR
3221                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3222                         return;
3223                 var->base = vmx_read_guest_seg_base(vmx, seg);
3224                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3225                 return;
3226         }
3227         var->base = vmx_read_guest_seg_base(vmx, seg);
3228         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3229         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3230         ar = vmx_read_guest_seg_ar(vmx, seg);
3231         var->unusable = (ar >> 16) & 1;
3232         var->type = ar & 15;
3233         var->s = (ar >> 4) & 1;
3234         var->dpl = (ar >> 5) & 3;
3235         /*
3236          * Some userspaces do not preserve unusable property. Since usable
3237          * segment has to be present according to VMX spec we can use present
3238          * property to amend userspace bug by making unusable segment always
3239          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3240          * segment as unusable.
3241          */
3242         var->present = !var->unusable;
3243         var->avl = (ar >> 12) & 1;
3244         var->l = (ar >> 13) & 1;
3245         var->db = (ar >> 14) & 1;
3246         var->g = (ar >> 15) & 1;
3247 }
3248
3249 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3250 {
3251         struct kvm_segment s;
3252
3253         if (to_vmx(vcpu)->rmode.vm86_active) {
3254                 vmx_get_segment(vcpu, &s, seg);
3255                 return s.base;
3256         }
3257         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3258 }
3259
3260 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3261 {
3262         struct vcpu_vmx *vmx = to_vmx(vcpu);
3263
3264         if (unlikely(vmx->rmode.vm86_active))
3265                 return 0;
3266         else {
3267                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3268                 return VMX_AR_DPL(ar);
3269         }
3270 }
3271
3272 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3273 {
3274         u32 ar;
3275
3276         if (var->unusable || !var->present)
3277                 ar = 1 << 16;
3278         else {
3279                 ar = var->type & 15;
3280                 ar |= (var->s & 1) << 4;
3281                 ar |= (var->dpl & 3) << 5;
3282                 ar |= (var->present & 1) << 7;
3283                 ar |= (var->avl & 1) << 12;
3284                 ar |= (var->l & 1) << 13;
3285                 ar |= (var->db & 1) << 14;
3286                 ar |= (var->g & 1) << 15;
3287         }
3288
3289         return ar;
3290 }
3291
3292 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3293 {
3294         struct vcpu_vmx *vmx = to_vmx(vcpu);
3295         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3296
3297         vmx_segment_cache_clear(vmx);
3298
3299         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3300                 vmx->rmode.segs[seg] = *var;
3301                 if (seg == VCPU_SREG_TR)
3302                         vmcs_write16(sf->selector, var->selector);
3303                 else if (var->s)
3304                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3305                 return;
3306         }
3307
3308         vmcs_writel(sf->base, var->base);
3309         vmcs_write32(sf->limit, var->limit);
3310         vmcs_write16(sf->selector, var->selector);
3311
3312         /*
3313          *   Fix the "Accessed" bit in AR field of segment registers for older
3314          * qemu binaries.
3315          *   IA32 arch specifies that at the time of processor reset the
3316          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3317          * is setting it to 0 in the userland code. This causes invalid guest
3318          * state vmexit when "unrestricted guest" mode is turned on.
3319          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3320          * tree. Newer qemu binaries with that qemu fix would not need this
3321          * kvm hack.
3322          */
3323         if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3324                 var->type |= 0x1; /* Accessed */
3325
3326         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3327 }
3328
3329 static void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3330 {
3331         __vmx_set_segment(vcpu, var, seg);
3332
3333         to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
3334 }
3335
3336 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3337 {
3338         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3339
3340         *db = (ar >> 14) & 1;
3341         *l = (ar >> 13) & 1;
3342 }
3343
3344 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3345 {
3346         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3347         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3348 }
3349
3350 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3351 {
3352         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3353         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3354 }
3355
3356 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3357 {
3358         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3359         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3360 }
3361
3362 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3363 {
3364         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3365         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3366 }
3367
3368 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3369 {
3370         struct kvm_segment var;
3371         u32 ar;
3372
3373         vmx_get_segment(vcpu, &var, seg);
3374         var.dpl = 0x3;
3375         if (seg == VCPU_SREG_CS)
3376                 var.type = 0x3;
3377         ar = vmx_segment_access_rights(&var);
3378
3379         if (var.base != (var.selector << 4))
3380                 return false;
3381         if (var.limit != 0xffff)
3382                 return false;
3383         if (ar != 0xf3)
3384                 return false;
3385
3386         return true;
3387 }
3388
3389 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3390 {
3391         struct kvm_segment cs;
3392         unsigned int cs_rpl;
3393
3394         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3395         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3396
3397         if (cs.unusable)
3398                 return false;
3399         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3400                 return false;
3401         if (!cs.s)
3402                 return false;
3403         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3404                 if (cs.dpl > cs_rpl)
3405                         return false;
3406         } else {
3407                 if (cs.dpl != cs_rpl)
3408                         return false;
3409         }
3410         if (!cs.present)
3411                 return false;
3412
3413         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3414         return true;
3415 }
3416
3417 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3418 {
3419         struct kvm_segment ss;
3420         unsigned int ss_rpl;
3421
3422         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3423         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3424
3425         if (ss.unusable)
3426                 return true;
3427         if (ss.type != 3 && ss.type != 7)
3428                 return false;
3429         if (!ss.s)
3430                 return false;
3431         if (ss.dpl != ss_rpl) /* DPL != RPL */
3432                 return false;
3433         if (!ss.present)
3434                 return false;
3435
3436         return true;
3437 }
3438
3439 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3440 {
3441         struct kvm_segment var;
3442         unsigned int rpl;
3443
3444         vmx_get_segment(vcpu, &var, seg);
3445         rpl = var.selector & SEGMENT_RPL_MASK;
3446
3447         if (var.unusable)
3448                 return true;
3449         if (!var.s)
3450                 return false;
3451         if (!var.present)
3452                 return false;
3453         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3454                 if (var.dpl < rpl) /* DPL < RPL */
3455                         return false;
3456         }
3457
3458         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3459          * rights flags
3460          */
3461         return true;
3462 }
3463
3464 static bool tr_valid(struct kvm_vcpu *vcpu)
3465 {
3466         struct kvm_segment tr;
3467
3468         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3469
3470         if (tr.unusable)
3471                 return false;
3472         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3473                 return false;
3474         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3475                 return false;
3476         if (!tr.present)
3477                 return false;
3478
3479         return true;
3480 }
3481
3482 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3483 {
3484         struct kvm_segment ldtr;
3485
3486         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3487
3488         if (ldtr.unusable)
3489                 return true;
3490         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3491                 return false;
3492         if (ldtr.type != 2)
3493                 return false;
3494         if (!ldtr.present)
3495                 return false;
3496
3497         return true;
3498 }
3499
3500 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3501 {
3502         struct kvm_segment cs, ss;
3503
3504         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3505         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3506
3507         return ((cs.selector & SEGMENT_RPL_MASK) ==
3508                  (ss.selector & SEGMENT_RPL_MASK));
3509 }
3510
3511 /*
3512  * Check if guest state is valid. Returns true if valid, false if
3513  * not.
3514  * We assume that registers are always usable
3515  */
3516 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu)
3517 {
3518         /* real mode guest state checks */
3519         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3520                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3521                         return false;
3522                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3523                         return false;
3524                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3525                         return false;
3526                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3527                         return false;
3528                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3529                         return false;
3530                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3531                         return false;
3532         } else {
3533         /* protected mode guest state checks */
3534                 if (!cs_ss_rpl_check(vcpu))
3535                         return false;
3536                 if (!code_segment_valid(vcpu))
3537                         return false;
3538                 if (!stack_segment_valid(vcpu))
3539                         return false;
3540                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3541                         return false;
3542                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3543                         return false;
3544                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3545                         return false;
3546                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3547                         return false;
3548                 if (!tr_valid(vcpu))
3549                         return false;
3550                 if (!ldtr_valid(vcpu))
3551                         return false;
3552         }
3553         /* TODO:
3554          * - Add checks on RIP
3555          * - Add checks on RFLAGS
3556          */
3557
3558         return true;
3559 }
3560
3561 static int init_rmode_tss(struct kvm *kvm, void __user *ua)
3562 {
3563         const void *zero_page = (const void *) __va(page_to_phys(ZERO_PAGE(0)));
3564         u16 data;
3565         int i;
3566
3567         for (i = 0; i < 3; i++) {
3568                 if (__copy_to_user(ua + PAGE_SIZE * i, zero_page, PAGE_SIZE))
3569                         return -EFAULT;
3570         }
3571
3572         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3573         if (__copy_to_user(ua + TSS_IOPB_BASE_OFFSET, &data, sizeof(u16)))
3574                 return -EFAULT;
3575
3576         data = ~0;
3577         if (__copy_to_user(ua + RMODE_TSS_SIZE - 1, &data, sizeof(u8)))
3578                 return -EFAULT;
3579
3580         return 0;
3581 }
3582
3583 static int init_rmode_identity_map(struct kvm *kvm)
3584 {
3585         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3586         int i, r = 0;
3587         void __user *uaddr;
3588         u32 tmp;
3589
3590         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3591         mutex_lock(&kvm->slots_lock);
3592
3593         if (likely(kvm_vmx->ept_identity_pagetable_done))
3594                 goto out;
3595
3596         if (!kvm_vmx->ept_identity_map_addr)
3597                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3598
3599         uaddr = __x86_set_memory_region(kvm,
3600                                         IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3601                                         kvm_vmx->ept_identity_map_addr,
3602                                         PAGE_SIZE);
3603         if (IS_ERR(uaddr)) {
3604                 r = PTR_ERR(uaddr);
3605                 goto out;
3606         }
3607
3608         /* Set up identity-mapping pagetable for EPT in real mode */
3609         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3610                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3611                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3612                 if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) {
3613                         r = -EFAULT;
3614                         goto out;
3615                 }
3616         }
3617         kvm_vmx->ept_identity_pagetable_done = true;
3618
3619 out:
3620         mutex_unlock(&kvm->slots_lock);
3621         return r;
3622 }
3623
3624 static void seg_setup(int seg)
3625 {
3626         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3627         unsigned int ar;
3628
3629         vmcs_write16(sf->selector, 0);
3630         vmcs_writel(sf->base, 0);
3631         vmcs_write32(sf->limit, 0xffff);
3632         ar = 0x93;
3633         if (seg == VCPU_SREG_CS)
3634                 ar |= 0x08; /* code segment */
3635
3636         vmcs_write32(sf->ar_bytes, ar);
3637 }
3638
3639 static int alloc_apic_access_page(struct kvm *kvm)
3640 {
3641         struct page *page;
3642         void __user *hva;
3643         int ret = 0;
3644
3645         mutex_lock(&kvm->slots_lock);
3646         if (kvm->arch.apic_access_memslot_enabled)
3647                 goto out;
3648         hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3649                                       APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3650         if (IS_ERR(hva)) {
3651                 ret = PTR_ERR(hva);
3652                 goto out;
3653         }
3654
3655         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3656         if (is_error_page(page)) {
3657                 ret = -EFAULT;
3658                 goto out;
3659         }
3660
3661         /*
3662          * Do not pin the page in memory, so that memory hot-unplug
3663          * is able to migrate it.
3664          */
3665         put_page(page);
3666         kvm->arch.apic_access_memslot_enabled = true;
3667 out:
3668         mutex_unlock(&kvm->slots_lock);
3669         return ret;
3670 }
3671
3672 int allocate_vpid(void)
3673 {
3674         int vpid;
3675
3676         if (!enable_vpid)
3677                 return 0;
3678         spin_lock(&vmx_vpid_lock);
3679         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3680         if (vpid < VMX_NR_VPIDS)
3681                 __set_bit(vpid, vmx_vpid_bitmap);
3682         else
3683                 vpid = 0;
3684         spin_unlock(&vmx_vpid_lock);
3685         return vpid;
3686 }
3687
3688 void free_vpid(int vpid)
3689 {
3690         if (!enable_vpid || vpid == 0)
3691                 return;
3692         spin_lock(&vmx_vpid_lock);
3693         __clear_bit(vpid, vmx_vpid_bitmap);
3694         spin_unlock(&vmx_vpid_lock);
3695 }
3696
3697 static void vmx_clear_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3698 {
3699         int f = sizeof(unsigned long);
3700
3701         if (msr <= 0x1fff)
3702                 __clear_bit(msr, msr_bitmap + 0x000 / f);
3703         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3704                 __clear_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3705 }
3706
3707 static void vmx_clear_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3708 {
3709         int f = sizeof(unsigned long);
3710
3711         if (msr <= 0x1fff)
3712                 __clear_bit(msr, msr_bitmap + 0x800 / f);
3713         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3714                 __clear_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3715 }
3716
3717 static void vmx_set_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3718 {
3719         int f = sizeof(unsigned long);
3720
3721         if (msr <= 0x1fff)
3722                 __set_bit(msr, msr_bitmap + 0x000 / f);
3723         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3724                 __set_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3725 }
3726
3727 static void vmx_set_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3728 {
3729         int f = sizeof(unsigned long);
3730
3731         if (msr <= 0x1fff)
3732                 __set_bit(msr, msr_bitmap + 0x800 / f);
3733         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3734                 __set_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3735 }
3736
3737 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3738 {
3739         struct vcpu_vmx *vmx = to_vmx(vcpu);
3740         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3741
3742         if (!cpu_has_vmx_msr_bitmap())
3743                 return;
3744
3745         if (static_branch_unlikely(&enable_evmcs))
3746                 evmcs_touch_msr_bitmap();
3747
3748         /*
3749          * Mark the desired intercept state in shadow bitmap, this is needed
3750          * for resync when the MSR filters change.
3751         */
3752         if (is_valid_passthrough_msr(msr)) {
3753                 int idx = possible_passthrough_msr_slot(msr);
3754
3755                 if (idx != -ENOENT) {
3756                         if (type & MSR_TYPE_R)
3757                                 clear_bit(idx, vmx->shadow_msr_intercept.read);
3758                         if (type & MSR_TYPE_W)
3759                                 clear_bit(idx, vmx->shadow_msr_intercept.write);
3760                 }
3761         }
3762
3763         if ((type & MSR_TYPE_R) &&
3764             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) {
3765                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3766                 type &= ~MSR_TYPE_R;
3767         }
3768
3769         if ((type & MSR_TYPE_W) &&
3770             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) {
3771                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3772                 type &= ~MSR_TYPE_W;
3773         }
3774
3775         if (type & MSR_TYPE_R)
3776                 vmx_clear_msr_bitmap_read(msr_bitmap, msr);
3777
3778         if (type & MSR_TYPE_W)
3779                 vmx_clear_msr_bitmap_write(msr_bitmap, msr);
3780 }
3781
3782 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3783 {
3784         struct vcpu_vmx *vmx = to_vmx(vcpu);
3785         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3786
3787         if (!cpu_has_vmx_msr_bitmap())
3788                 return;
3789
3790         if (static_branch_unlikely(&enable_evmcs))
3791                 evmcs_touch_msr_bitmap();
3792
3793         /*
3794          * Mark the desired intercept state in shadow bitmap, this is needed
3795          * for resync when the MSR filter changes.
3796         */
3797         if (is_valid_passthrough_msr(msr)) {
3798                 int idx = possible_passthrough_msr_slot(msr);
3799
3800                 if (idx != -ENOENT) {
3801                         if (type & MSR_TYPE_R)
3802                                 set_bit(idx, vmx->shadow_msr_intercept.read);
3803                         if (type & MSR_TYPE_W)
3804                                 set_bit(idx, vmx->shadow_msr_intercept.write);
3805                 }
3806         }
3807
3808         if (type & MSR_TYPE_R)
3809                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3810
3811         if (type & MSR_TYPE_W)
3812                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3813 }
3814
3815 static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode)
3816 {
3817         unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
3818         unsigned long read_intercept;
3819         int msr;
3820
3821         read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3822
3823         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3824                 unsigned int read_idx = msr / BITS_PER_LONG;
3825                 unsigned int write_idx = read_idx + (0x800 / sizeof(long));
3826
3827                 msr_bitmap[read_idx] = read_intercept;
3828                 msr_bitmap[write_idx] = ~0ul;
3829         }
3830 }
3831
3832 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
3833 {
3834         struct vcpu_vmx *vmx = to_vmx(vcpu);
3835         u8 mode;
3836
3837         if (!cpu_has_vmx_msr_bitmap())
3838                 return;
3839
3840         if (cpu_has_secondary_exec_ctrls() &&
3841             (secondary_exec_controls_get(vmx) &
3842              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3843                 mode = MSR_BITMAP_MODE_X2APIC;
3844                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3845                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3846         } else {
3847                 mode = 0;
3848         }
3849
3850         if (mode == vmx->x2apic_msr_bitmap_mode)
3851                 return;
3852
3853         vmx->x2apic_msr_bitmap_mode = mode;
3854
3855         vmx_reset_x2apic_msrs(vcpu, mode);
3856
3857         /*
3858          * TPR reads and writes can be virtualized even if virtual interrupt
3859          * delivery is not in use.
3860          */
3861         vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
3862                                   !(mode & MSR_BITMAP_MODE_X2APIC));
3863
3864         if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3865                 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
3866                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3867                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3868         }
3869 }
3870
3871 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu)
3872 {
3873         struct vcpu_vmx *vmx = to_vmx(vcpu);
3874         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3875         u32 i;
3876
3877         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
3878         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
3879         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
3880         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
3881         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3882                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3883                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3884         }
3885 }
3886
3887 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3888 {
3889         struct vcpu_vmx *vmx = to_vmx(vcpu);
3890         void *vapic_page;
3891         u32 vppr;
3892         int rvi;
3893
3894         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3895                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3896                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3897                 return false;
3898
3899         rvi = vmx_get_rvi();
3900
3901         vapic_page = vmx->nested.virtual_apic_map.hva;
3902         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3903
3904         return ((rvi & 0xf0) > (vppr & 0xf0));
3905 }
3906
3907 static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
3908 {
3909         struct vcpu_vmx *vmx = to_vmx(vcpu);
3910         u32 i;
3911
3912         /*
3913          * Set intercept permissions for all potentially passed through MSRs
3914          * again. They will automatically get filtered through the MSR filter,
3915          * so we are back in sync after this.
3916          */
3917         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
3918                 u32 msr = vmx_possible_passthrough_msrs[i];
3919                 bool read = test_bit(i, vmx->shadow_msr_intercept.read);
3920                 bool write = test_bit(i, vmx->shadow_msr_intercept.write);
3921
3922                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
3923                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
3924         }
3925
3926         pt_update_intercept_for_msr(vcpu);
3927 }
3928
3929 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3930                                                      bool nested)
3931 {
3932 #ifdef CONFIG_SMP
3933         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3934
3935         if (vcpu->mode == IN_GUEST_MODE) {
3936                 /*
3937                  * The vector of interrupt to be delivered to vcpu had
3938                  * been set in PIR before this function.
3939                  *
3940                  * Following cases will be reached in this block, and
3941                  * we always send a notification event in all cases as
3942                  * explained below.
3943                  *
3944                  * Case 1: vcpu keeps in non-root mode. Sending a
3945                  * notification event posts the interrupt to vcpu.
3946                  *
3947                  * Case 2: vcpu exits to root mode and is still
3948                  * runnable. PIR will be synced to vIRR before the
3949                  * next vcpu entry. Sending a notification event in
3950                  * this case has no effect, as vcpu is not in root
3951                  * mode.
3952                  *
3953                  * Case 3: vcpu exits to root mode and is blocked.
3954                  * vcpu_block() has already synced PIR to vIRR and
3955                  * never blocks vcpu if vIRR is not cleared. Therefore,
3956                  * a blocked vcpu here does not wait for any requested
3957                  * interrupts in PIR, and sending a notification event
3958                  * which has no effect is safe here.
3959                  */
3960
3961                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3962                 return true;
3963         }
3964 #endif
3965         return false;
3966 }
3967
3968 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3969                                                 int vector)
3970 {
3971         struct vcpu_vmx *vmx = to_vmx(vcpu);
3972
3973         if (is_guest_mode(vcpu) &&
3974             vector == vmx->nested.posted_intr_nv) {
3975                 /*
3976                  * If a posted intr is not recognized by hardware,
3977                  * we will accomplish it in the next vmentry.
3978                  */
3979                 vmx->nested.pi_pending = true;
3980                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3981                 /* the PIR and ON have been set by L1. */
3982                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3983                         kvm_vcpu_kick(vcpu);
3984                 return 0;
3985         }
3986         return -1;
3987 }
3988 /*
3989  * Send interrupt to vcpu via posted interrupt way.
3990  * 1. If target vcpu is running(non-root mode), send posted interrupt
3991  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3992  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3993  * interrupt from PIR in next vmentry.
3994  */
3995 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3996 {
3997         struct vcpu_vmx *vmx = to_vmx(vcpu);
3998         int r;
3999
4000         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4001         if (!r)
4002                 return 0;
4003
4004         if (!vcpu->arch.apicv_active)
4005                 return -1;
4006
4007         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4008                 return 0;
4009
4010         /* If a previous notification has sent the IPI, nothing to do.  */
4011         if (pi_test_and_set_on(&vmx->pi_desc))
4012                 return 0;
4013
4014         if (vcpu != kvm_get_running_vcpu() &&
4015             !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
4016                 kvm_vcpu_kick(vcpu);
4017
4018         return 0;
4019 }
4020
4021 /*
4022  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4023  * will not change in the lifetime of the guest.
4024  * Note that host-state that does change is set elsewhere. E.g., host-state
4025  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4026  */
4027 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4028 {
4029         u32 low32, high32;
4030         unsigned long tmpl;
4031         unsigned long cr0, cr3, cr4;
4032
4033         cr0 = read_cr0();
4034         WARN_ON(cr0 & X86_CR0_TS);
4035         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
4036
4037         /*
4038          * Save the most likely value for this task's CR3 in the VMCS.
4039          * We can't use __get_current_cr3_fast() because we're not atomic.
4040          */
4041         cr3 = __read_cr3();
4042         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
4043         vmx->loaded_vmcs->host_state.cr3 = cr3;
4044
4045         /* Save the most likely value for this task's CR4 in the VMCS. */
4046         cr4 = cr4_read_shadow();
4047         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4048         vmx->loaded_vmcs->host_state.cr4 = cr4;
4049
4050         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4051 #ifdef CONFIG_X86_64
4052         /*
4053          * Load null selectors, so we can avoid reloading them in
4054          * vmx_prepare_switch_to_host(), in case userspace uses
4055          * the null selectors too (the expected case).
4056          */
4057         vmcs_write16(HOST_DS_SELECTOR, 0);
4058         vmcs_write16(HOST_ES_SELECTOR, 0);
4059 #else
4060         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4061         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4062 #endif
4063         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4064         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4065
4066         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
4067
4068         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4069
4070         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4071         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4072         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4073         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4074
4075         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4076                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4077                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4078         }
4079
4080         if (cpu_has_load_ia32_efer())
4081                 vmcs_write64(HOST_IA32_EFER, host_efer);
4082 }
4083
4084 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4085 {
4086         struct kvm_vcpu *vcpu = &vmx->vcpu;
4087
4088         vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
4089                                           ~vcpu->arch.cr4_guest_rsvd_bits;
4090         if (!enable_ept)
4091                 vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4092         if (is_guest_mode(&vmx->vcpu))
4093                 vcpu->arch.cr4_guest_owned_bits &=
4094                         ~get_vmcs12(vcpu)->cr4_guest_host_mask;
4095         vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits);
4096 }
4097
4098 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4099 {
4100         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4101
4102         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4103                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4104
4105         if (!enable_vnmi)
4106                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4107
4108         if (!enable_preemption_timer)
4109                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4110
4111         return pin_based_exec_ctrl;
4112 }
4113
4114 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4115 {
4116         struct vcpu_vmx *vmx = to_vmx(vcpu);
4117
4118         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4119         if (cpu_has_secondary_exec_ctrls()) {
4120                 if (kvm_vcpu_apicv_active(vcpu))
4121                         secondary_exec_controls_setbit(vmx,
4122                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4123                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4124                 else
4125                         secondary_exec_controls_clearbit(vmx,
4126                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4127                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4128         }
4129
4130         vmx_update_msr_bitmap_x2apic(vcpu);
4131 }
4132
4133 u32 vmx_exec_control(struct vcpu_vmx *vmx)
4134 {
4135         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4136
4137         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4138                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4139
4140         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4141                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4142 #ifdef CONFIG_X86_64
4143                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4144                                 CPU_BASED_CR8_LOAD_EXITING;
4145 #endif
4146         }
4147         if (!enable_ept)
4148                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4149                                 CPU_BASED_CR3_LOAD_EXITING  |
4150                                 CPU_BASED_INVLPG_EXITING;
4151         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4152                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4153                                 CPU_BASED_MONITOR_EXITING);
4154         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4155                 exec_control &= ~CPU_BASED_HLT_EXITING;
4156         return exec_control;
4157 }
4158
4159 /*
4160  * Adjust a single secondary execution control bit to intercept/allow an
4161  * instruction in the guest.  This is usually done based on whether or not a
4162  * feature has been exposed to the guest in order to correctly emulate faults.
4163  */
4164 static inline void
4165 vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control,
4166                                   u32 control, bool enabled, bool exiting)
4167 {
4168         /*
4169          * If the control is for an opt-in feature, clear the control if the
4170          * feature is not exposed to the guest, i.e. not enabled.  If the
4171          * control is opt-out, i.e. an exiting control, clear the control if
4172          * the feature _is_ exposed to the guest, i.e. exiting/interception is
4173          * disabled for the associated instruction.  Note, the caller is
4174          * responsible presetting exec_control to set all supported bits.
4175          */
4176         if (enabled == exiting)
4177                 *exec_control &= ~control;
4178
4179         /*
4180          * Update the nested MSR settings so that a nested VMM can/can't set
4181          * controls for features that are/aren't exposed to the guest.
4182          */
4183         if (nested) {
4184                 if (enabled)
4185                         vmx->nested.msrs.secondary_ctls_high |= control;
4186                 else
4187                         vmx->nested.msrs.secondary_ctls_high &= ~control;
4188         }
4189 }
4190
4191 /*
4192  * Wrapper macro for the common case of adjusting a secondary execution control
4193  * based on a single guest CPUID bit, with a dedicated feature bit.  This also
4194  * verifies that the control is actually supported by KVM and hardware.
4195  */
4196 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \
4197 ({                                                                       \
4198         bool __enabled;                                                  \
4199                                                                          \
4200         if (cpu_has_vmx_##name()) {                                      \
4201                 __enabled = guest_cpuid_has(&(vmx)->vcpu,                \
4202                                             X86_FEATURE_##feat_name);    \
4203                 vmx_adjust_secondary_exec_control(vmx, exec_control,     \
4204                         SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \
4205         }                                                                \
4206 })
4207
4208 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */
4209 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \
4210         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false)
4211
4212 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \
4213         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true)
4214
4215 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4216 {
4217         struct kvm_vcpu *vcpu = &vmx->vcpu;
4218
4219         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4220
4221         if (vmx_pt_mode_is_system())
4222                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4223         if (!cpu_need_virtualize_apic_accesses(vcpu))
4224                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4225         if (vmx->vpid == 0)
4226                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4227         if (!enable_ept) {
4228                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4229                 enable_unrestricted_guest = 0;
4230         }
4231         if (!enable_unrestricted_guest)
4232                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4233         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4234                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4235         if (!kvm_vcpu_apicv_active(vcpu))
4236                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4237                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4238         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4239
4240         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4241          * in vmx_set_cr4.  */
4242         exec_control &= ~SECONDARY_EXEC_DESC;
4243
4244         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4245            (handle_vmptrld).
4246            We can NOT enable shadow_vmcs here because we don't have yet
4247            a current VMCS12
4248         */
4249         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4250
4251         /*
4252          * PML is enabled/disabled when dirty logging of memsmlots changes, but
4253          * it needs to be set here when dirty logging is already active, e.g.
4254          * if this vCPU was created after dirty logging was enabled.
4255          */
4256         if (!vcpu->kvm->arch.cpu_dirty_logging_count)
4257                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4258
4259         if (cpu_has_vmx_xsaves()) {
4260                 /* Exposing XSAVES only when XSAVE is exposed */
4261                 bool xsaves_enabled =
4262                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4263                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4264                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4265
4266                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4267
4268                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4269                                                   SECONDARY_EXEC_XSAVES,
4270                                                   xsaves_enabled, false);
4271         }
4272
4273         /*
4274          * RDPID is also gated by ENABLE_RDTSCP, turn on the control if either
4275          * feature is exposed to the guest.  This creates a virtualization hole
4276          * if both are supported in hardware but only one is exposed to the
4277          * guest, but letting the guest execute RDTSCP or RDPID when either one
4278          * is advertised is preferable to emulating the advertised instruction
4279          * in KVM on #UD, and obviously better than incorrectly injecting #UD.
4280          */
4281         if (cpu_has_vmx_rdtscp()) {
4282                 bool rdpid_or_rdtscp_enabled =
4283                         guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) ||
4284                         guest_cpuid_has(vcpu, X86_FEATURE_RDPID);
4285
4286                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4287                                                   SECONDARY_EXEC_ENABLE_RDTSCP,
4288                                                   rdpid_or_rdtscp_enabled, false);
4289         }
4290         vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID);
4291
4292         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND);
4293         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED);
4294
4295         vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG,
4296                                     ENABLE_USR_WAIT_PAUSE, false);
4297
4298         if (!vcpu->kvm->arch.bus_lock_detection_enabled)
4299                 exec_control &= ~SECONDARY_EXEC_BUS_LOCK_DETECTION;
4300
4301         vmx->secondary_exec_control = exec_control;
4302 }
4303
4304 #define VMX_XSS_EXIT_BITMAP 0
4305
4306 /*
4307  * Noting that the initialization of Guest-state Area of VMCS is in
4308  * vmx_vcpu_reset().
4309  */
4310 static void init_vmcs(struct vcpu_vmx *vmx)
4311 {
4312         if (nested)
4313                 nested_vmx_set_vmcs_shadowing_bitmap();
4314
4315         if (cpu_has_vmx_msr_bitmap())
4316                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4317
4318         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4319
4320         /* Control */
4321         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4322
4323         exec_controls_set(vmx, vmx_exec_control(vmx));
4324
4325         if (cpu_has_secondary_exec_ctrls()) {
4326                 vmx_compute_secondary_exec_control(vmx);
4327                 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4328         }
4329
4330         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4331                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4332                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4333                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4334                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4335
4336                 vmcs_write16(GUEST_INTR_STATUS, 0);
4337
4338                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4339                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4340         }
4341
4342         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4343                 vmcs_write32(PLE_GAP, ple_gap);
4344                 vmx->ple_window = ple_window;
4345                 vmx->ple_window_dirty = true;
4346         }
4347
4348         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4349         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4350         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4351
4352         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4353         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4354         vmx_set_constant_host_state(vmx);
4355         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4356         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4357
4358         if (cpu_has_vmx_vmfunc())
4359                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4360
4361         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4362         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4363         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4364         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4365         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4366
4367         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4368                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4369
4370         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4371
4372         /* 22.2.1, 20.8.1 */
4373         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4374
4375         vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4376         vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4377
4378         set_cr4_guest_host_mask(vmx);
4379
4380         if (vmx->vpid != 0)
4381                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4382
4383         if (cpu_has_vmx_xsaves())
4384                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4385
4386         if (enable_pml) {
4387                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4388                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4389         }
4390
4391         vmx_write_encls_bitmap(&vmx->vcpu, NULL);
4392
4393         if (vmx_pt_mode_is_host_guest()) {
4394                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4395                 /* Bit[6~0] are forced to 1, writes are ignored. */
4396                 vmx->pt_desc.guest.output_mask = 0x7F;
4397                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4398         }
4399
4400         vmcs_write32(GUEST_SYSENTER_CS, 0);
4401         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4402         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4403         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4404
4405         if (cpu_has_vmx_tpr_shadow()) {
4406                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4407                 if (cpu_need_tpr_shadow(&vmx->vcpu))
4408                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4409                                      __pa(vmx->vcpu.arch.apic->regs));
4410                 vmcs_write32(TPR_THRESHOLD, 0);
4411         }
4412
4413         vmx_setup_uret_msrs(vmx);
4414 }
4415
4416 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4417 {
4418         struct vcpu_vmx *vmx = to_vmx(vcpu);
4419
4420         vmx->rmode.vm86_active = 0;
4421         vmx->spec_ctrl = 0;
4422
4423         vmx->msr_ia32_umwait_control = 0;
4424
4425         vmx->hv_deadline_tsc = -1;
4426         kvm_set_cr8(vcpu, 0);
4427
4428         vmx_segment_cache_clear(vmx);
4429
4430         seg_setup(VCPU_SREG_CS);
4431         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4432         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4433
4434         seg_setup(VCPU_SREG_DS);
4435         seg_setup(VCPU_SREG_ES);
4436         seg_setup(VCPU_SREG_FS);
4437         seg_setup(VCPU_SREG_GS);
4438         seg_setup(VCPU_SREG_SS);
4439
4440         vmcs_write16(GUEST_TR_SELECTOR, 0);
4441         vmcs_writel(GUEST_TR_BASE, 0);
4442         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4443         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4444
4445         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4446         vmcs_writel(GUEST_LDTR_BASE, 0);
4447         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4448         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4449
4450         vmcs_writel(GUEST_GDTR_BASE, 0);
4451         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4452
4453         vmcs_writel(GUEST_IDTR_BASE, 0);
4454         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4455
4456         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4457         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4458         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4459         if (kvm_mpx_supported())
4460                 vmcs_write64(GUEST_BNDCFGS, 0);
4461
4462         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4463
4464         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4465
4466         vpid_sync_context(vmx->vpid);
4467 }
4468
4469 static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
4470 {
4471         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4472 }
4473
4474 static void vmx_enable_nmi_window(struct kvm_vcpu *vcpu)
4475 {
4476         if (!enable_vnmi ||
4477             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4478                 vmx_enable_irq_window(vcpu);
4479                 return;
4480         }
4481
4482         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4483 }
4484
4485 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4486 {
4487         struct vcpu_vmx *vmx = to_vmx(vcpu);
4488         uint32_t intr;
4489         int irq = vcpu->arch.interrupt.nr;
4490
4491         trace_kvm_inj_virq(irq);
4492
4493         ++vcpu->stat.irq_injections;
4494         if (vmx->rmode.vm86_active) {
4495                 int inc_eip = 0;
4496                 if (vcpu->arch.interrupt.soft)
4497                         inc_eip = vcpu->arch.event_exit_inst_len;
4498                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4499                 return;
4500         }
4501         intr = irq | INTR_INFO_VALID_MASK;
4502         if (vcpu->arch.interrupt.soft) {
4503                 intr |= INTR_TYPE_SOFT_INTR;
4504                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4505                              vmx->vcpu.arch.event_exit_inst_len);
4506         } else
4507                 intr |= INTR_TYPE_EXT_INTR;
4508         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4509
4510         vmx_clear_hlt(vcpu);
4511 }
4512
4513 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4514 {
4515         struct vcpu_vmx *vmx = to_vmx(vcpu);
4516
4517         if (!enable_vnmi) {
4518                 /*
4519                  * Tracking the NMI-blocked state in software is built upon
4520                  * finding the next open IRQ window. This, in turn, depends on
4521                  * well-behaving guests: They have to keep IRQs disabled at
4522                  * least as long as the NMI handler runs. Otherwise we may
4523                  * cause NMI nesting, maybe breaking the guest. But as this is
4524                  * highly unlikely, we can live with the residual risk.
4525                  */
4526                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4527                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4528         }
4529
4530         ++vcpu->stat.nmi_injections;
4531         vmx->loaded_vmcs->nmi_known_unmasked = false;
4532
4533         if (vmx->rmode.vm86_active) {
4534                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4535                 return;
4536         }
4537
4538         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4539                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4540
4541         vmx_clear_hlt(vcpu);
4542 }
4543
4544 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4545 {
4546         struct vcpu_vmx *vmx = to_vmx(vcpu);
4547         bool masked;
4548
4549         if (!enable_vnmi)
4550                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4551         if (vmx->loaded_vmcs->nmi_known_unmasked)
4552                 return false;
4553         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4554         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4555         return masked;
4556 }
4557
4558 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4559 {
4560         struct vcpu_vmx *vmx = to_vmx(vcpu);
4561
4562         if (!enable_vnmi) {
4563                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4564                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4565                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4566                 }
4567         } else {
4568                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4569                 if (masked)
4570                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4571                                       GUEST_INTR_STATE_NMI);
4572                 else
4573                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4574                                         GUEST_INTR_STATE_NMI);
4575         }
4576 }
4577
4578 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4579 {
4580         if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4581                 return false;
4582
4583         if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4584                 return true;
4585
4586         return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4587                 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4588                  GUEST_INTR_STATE_NMI));
4589 }
4590
4591 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4592 {
4593         if (to_vmx(vcpu)->nested.nested_run_pending)
4594                 return -EBUSY;
4595
4596         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
4597         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4598                 return -EBUSY;
4599
4600         return !vmx_nmi_blocked(vcpu);
4601 }
4602
4603 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4604 {
4605         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4606                 return false;
4607
4608         return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4609                (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4610                 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4611 }
4612
4613 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4614 {
4615         if (to_vmx(vcpu)->nested.nested_run_pending)
4616                 return -EBUSY;
4617
4618        /*
4619         * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4620         * e.g. if the IRQ arrived asynchronously after checking nested events.
4621         */
4622         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4623                 return -EBUSY;
4624
4625         return !vmx_interrupt_blocked(vcpu);
4626 }
4627
4628 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4629 {
4630         void __user *ret;
4631
4632         if (enable_unrestricted_guest)
4633                 return 0;
4634
4635         mutex_lock(&kvm->slots_lock);
4636         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4637                                       PAGE_SIZE * 3);
4638         mutex_unlock(&kvm->slots_lock);
4639
4640         if (IS_ERR(ret))
4641                 return PTR_ERR(ret);
4642
4643         to_kvm_vmx(kvm)->tss_addr = addr;
4644
4645         return init_rmode_tss(kvm, ret);
4646 }
4647
4648 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4649 {
4650         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4651         return 0;
4652 }
4653
4654 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4655 {
4656         switch (vec) {
4657         case BP_VECTOR:
4658                 /*
4659                  * Update instruction length as we may reinject the exception
4660                  * from user space while in guest debugging mode.
4661                  */
4662                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4663                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4664                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4665                         return false;
4666                 fallthrough;
4667         case DB_VECTOR:
4668                 return !(vcpu->guest_debug &
4669                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4670         case DE_VECTOR:
4671         case OF_VECTOR:
4672         case BR_VECTOR:
4673         case UD_VECTOR:
4674         case DF_VECTOR:
4675         case SS_VECTOR:
4676         case GP_VECTOR:
4677         case MF_VECTOR:
4678                 return true;
4679         }
4680         return false;
4681 }
4682
4683 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4684                                   int vec, u32 err_code)
4685 {
4686         /*
4687          * Instruction with address size override prefix opcode 0x67
4688          * Cause the #SS fault with 0 error code in VM86 mode.
4689          */
4690         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4691                 if (kvm_emulate_instruction(vcpu, 0)) {
4692                         if (vcpu->arch.halt_request) {
4693                                 vcpu->arch.halt_request = 0;
4694                                 return kvm_vcpu_halt(vcpu);
4695                         }
4696                         return 1;
4697                 }
4698                 return 0;
4699         }
4700
4701         /*
4702          * Forward all other exceptions that are valid in real mode.
4703          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4704          *        the required debugging infrastructure rework.
4705          */
4706         kvm_queue_exception(vcpu, vec);
4707         return 1;
4708 }
4709
4710 static int handle_machine_check(struct kvm_vcpu *vcpu)
4711 {
4712         /* handled by vmx_vcpu_run() */
4713         return 1;
4714 }
4715
4716 /*
4717  * If the host has split lock detection disabled, then #AC is
4718  * unconditionally injected into the guest, which is the pre split lock
4719  * detection behaviour.
4720  *
4721  * If the host has split lock detection enabled then #AC is
4722  * only injected into the guest when:
4723  *  - Guest CPL == 3 (user mode)
4724  *  - Guest has #AC detection enabled in CR0
4725  *  - Guest EFLAGS has AC bit set
4726  */
4727 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu)
4728 {
4729         if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4730                 return true;
4731
4732         return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4733                (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4734 }
4735
4736 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4737 {
4738         struct vcpu_vmx *vmx = to_vmx(vcpu);
4739         struct kvm_run *kvm_run = vcpu->run;
4740         u32 intr_info, ex_no, error_code;
4741         unsigned long cr2, dr6;
4742         u32 vect_info;
4743
4744         vect_info = vmx->idt_vectoring_info;
4745         intr_info = vmx_get_intr_info(vcpu);
4746
4747         if (is_machine_check(intr_info) || is_nmi(intr_info))
4748                 return 1; /* handled by handle_exception_nmi_irqoff() */
4749
4750         if (is_invalid_opcode(intr_info))
4751                 return handle_ud(vcpu);
4752
4753         error_code = 0;
4754         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4755                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4756
4757         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4758                 WARN_ON_ONCE(!enable_vmware_backdoor);
4759
4760                 /*
4761                  * VMware backdoor emulation on #GP interception only handles
4762                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4763                  * error code on #GP.
4764                  */
4765                 if (error_code) {
4766                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4767                         return 1;
4768                 }
4769                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4770         }
4771
4772         /*
4773          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4774          * MMIO, it is better to report an internal error.
4775          * See the comments in vmx_handle_exit.
4776          */
4777         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4778             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4779                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4780                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4781                 vcpu->run->internal.ndata = 4;
4782                 vcpu->run->internal.data[0] = vect_info;
4783                 vcpu->run->internal.data[1] = intr_info;
4784                 vcpu->run->internal.data[2] = error_code;
4785                 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4786                 return 0;
4787         }
4788
4789         if (is_page_fault(intr_info)) {
4790                 cr2 = vmx_get_exit_qual(vcpu);
4791                 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4792                         /*
4793                          * EPT will cause page fault only if we need to
4794                          * detect illegal GPAs.
4795                          */
4796                         WARN_ON_ONCE(!allow_smaller_maxphyaddr);
4797                         kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4798                         return 1;
4799                 } else
4800                         return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4801         }
4802
4803         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4804
4805         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4806                 return handle_rmode_exception(vcpu, ex_no, error_code);
4807
4808         switch (ex_no) {
4809         case DB_VECTOR:
4810                 dr6 = vmx_get_exit_qual(vcpu);
4811                 if (!(vcpu->guest_debug &
4812                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4813                         if (is_icebp(intr_info))
4814                                 WARN_ON(!skip_emulated_instruction(vcpu));
4815
4816                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4817                         return 1;
4818                 }
4819                 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
4820                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4821                 fallthrough;
4822         case BP_VECTOR:
4823                 /*
4824                  * Update instruction length as we may reinject #BP from
4825                  * user space while in guest debugging mode. Reading it for
4826                  * #DB as well causes no harm, it is not used in that case.
4827                  */
4828                 vmx->vcpu.arch.event_exit_inst_len =
4829                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4830                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4831                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4832                 kvm_run->debug.arch.exception = ex_no;
4833                 break;
4834         case AC_VECTOR:
4835                 if (vmx_guest_inject_ac(vcpu)) {
4836                         kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4837                         return 1;
4838                 }
4839
4840                 /*
4841                  * Handle split lock. Depending on detection mode this will
4842                  * either warn and disable split lock detection for this
4843                  * task or force SIGBUS on it.
4844                  */
4845                 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4846                         return 1;
4847                 fallthrough;
4848         default:
4849                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4850                 kvm_run->ex.exception = ex_no;
4851                 kvm_run->ex.error_code = error_code;
4852                 break;
4853         }
4854         return 0;
4855 }
4856
4857 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4858 {
4859         ++vcpu->stat.irq_exits;
4860         return 1;
4861 }
4862
4863 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4864 {
4865         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4866         vcpu->mmio_needed = 0;
4867         return 0;
4868 }
4869
4870 static int handle_io(struct kvm_vcpu *vcpu)
4871 {
4872         unsigned long exit_qualification;
4873         int size, in, string;
4874         unsigned port;
4875
4876         exit_qualification = vmx_get_exit_qual(vcpu);
4877         string = (exit_qualification & 16) != 0;
4878
4879         ++vcpu->stat.io_exits;
4880
4881         if (string)
4882                 return kvm_emulate_instruction(vcpu, 0);
4883
4884         port = exit_qualification >> 16;
4885         size = (exit_qualification & 7) + 1;
4886         in = (exit_qualification & 8) != 0;
4887
4888         return kvm_fast_pio(vcpu, size, port, in);
4889 }
4890
4891 static void
4892 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4893 {
4894         /*
4895          * Patch in the VMCALL instruction:
4896          */
4897         hypercall[0] = 0x0f;
4898         hypercall[1] = 0x01;
4899         hypercall[2] = 0xc1;
4900 }
4901
4902 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4903 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4904 {
4905         if (is_guest_mode(vcpu)) {
4906                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4907                 unsigned long orig_val = val;
4908
4909                 /*
4910                  * We get here when L2 changed cr0 in a way that did not change
4911                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4912                  * but did change L0 shadowed bits. So we first calculate the
4913                  * effective cr0 value that L1 would like to write into the
4914                  * hardware. It consists of the L2-owned bits from the new
4915                  * value combined with the L1-owned bits from L1's guest_cr0.
4916                  */
4917                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4918                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4919
4920                 if (!nested_guest_cr0_valid(vcpu, val))
4921                         return 1;
4922
4923                 if (kvm_set_cr0(vcpu, val))
4924                         return 1;
4925                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4926                 return 0;
4927         } else {
4928                 if (to_vmx(vcpu)->nested.vmxon &&
4929                     !nested_host_cr0_valid(vcpu, val))
4930                         return 1;
4931
4932                 return kvm_set_cr0(vcpu, val);
4933         }
4934 }
4935
4936 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4937 {
4938         if (is_guest_mode(vcpu)) {
4939                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4940                 unsigned long orig_val = val;
4941
4942                 /* analogously to handle_set_cr0 */
4943                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4944                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4945                 if (kvm_set_cr4(vcpu, val))
4946                         return 1;
4947                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4948                 return 0;
4949         } else
4950                 return kvm_set_cr4(vcpu, val);
4951 }
4952
4953 static int handle_desc(struct kvm_vcpu *vcpu)
4954 {
4955         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4956         return kvm_emulate_instruction(vcpu, 0);
4957 }
4958
4959 static int handle_cr(struct kvm_vcpu *vcpu)
4960 {
4961         unsigned long exit_qualification, val;
4962         int cr;
4963         int reg;
4964         int err;
4965         int ret;
4966
4967         exit_qualification = vmx_get_exit_qual(vcpu);
4968         cr = exit_qualification & 15;
4969         reg = (exit_qualification >> 8) & 15;
4970         switch ((exit_qualification >> 4) & 3) {
4971         case 0: /* mov to cr */
4972                 val = kvm_register_read(vcpu, reg);
4973                 trace_kvm_cr_write(cr, val);
4974                 switch (cr) {
4975                 case 0:
4976                         err = handle_set_cr0(vcpu, val);
4977                         return kvm_complete_insn_gp(vcpu, err);
4978                 case 3:
4979                         WARN_ON_ONCE(enable_unrestricted_guest);
4980
4981                         err = kvm_set_cr3(vcpu, val);
4982                         return kvm_complete_insn_gp(vcpu, err);
4983                 case 4:
4984                         err = handle_set_cr4(vcpu, val);
4985                         return kvm_complete_insn_gp(vcpu, err);
4986                 case 8: {
4987                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4988                                 u8 cr8 = (u8)val;
4989                                 err = kvm_set_cr8(vcpu, cr8);
4990                                 ret = kvm_complete_insn_gp(vcpu, err);
4991                                 if (lapic_in_kernel(vcpu))
4992                                         return ret;
4993                                 if (cr8_prev <= cr8)
4994                                         return ret;
4995                                 /*
4996                                  * TODO: we might be squashing a
4997                                  * KVM_GUESTDBG_SINGLESTEP-triggered
4998                                  * KVM_EXIT_DEBUG here.
4999                                  */
5000                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5001                                 return 0;
5002                         }
5003                 }
5004                 break;
5005         case 2: /* clts */
5006                 KVM_BUG(1, vcpu->kvm, "Guest always owns CR0.TS");
5007                 return -EIO;
5008         case 1: /*mov from cr*/
5009                 switch (cr) {
5010                 case 3:
5011                         WARN_ON_ONCE(enable_unrestricted_guest);
5012
5013                         val = kvm_read_cr3(vcpu);
5014                         kvm_register_write(vcpu, reg, val);
5015                         trace_kvm_cr_read(cr, val);
5016                         return kvm_skip_emulated_instruction(vcpu);
5017                 case 8:
5018                         val = kvm_get_cr8(vcpu);
5019                         kvm_register_write(vcpu, reg, val);
5020                         trace_kvm_cr_read(cr, val);
5021                         return kvm_skip_emulated_instruction(vcpu);
5022                 }
5023                 break;
5024         case 3: /* lmsw */
5025                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5026                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5027                 kvm_lmsw(vcpu, val);
5028
5029                 return kvm_skip_emulated_instruction(vcpu);
5030         default:
5031                 break;
5032         }
5033         vcpu->run->exit_reason = 0;
5034         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5035                (int)(exit_qualification >> 4) & 3, cr);
5036         return 0;
5037 }
5038
5039 static int handle_dr(struct kvm_vcpu *vcpu)
5040 {
5041         unsigned long exit_qualification;
5042         int dr, dr7, reg;
5043         int err = 1;
5044
5045         exit_qualification = vmx_get_exit_qual(vcpu);
5046         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5047
5048         /* First, if DR does not exist, trigger UD */
5049         if (!kvm_require_dr(vcpu, dr))
5050                 return 1;
5051
5052         if (kvm_x86_ops.get_cpl(vcpu) > 0)
5053                 goto out;
5054
5055         dr7 = vmcs_readl(GUEST_DR7);
5056         if (dr7 & DR7_GD) {
5057                 /*
5058                  * As the vm-exit takes precedence over the debug trap, we
5059                  * need to emulate the latter, either for the host or the
5060                  * guest debugging itself.
5061                  */
5062                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5063                         vcpu->run->debug.arch.dr6 = DR6_BD | DR6_ACTIVE_LOW;
5064                         vcpu->run->debug.arch.dr7 = dr7;
5065                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5066                         vcpu->run->debug.arch.exception = DB_VECTOR;
5067                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5068                         return 0;
5069                 } else {
5070                         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5071                         return 1;
5072                 }
5073         }
5074
5075         if (vcpu->guest_debug == 0) {
5076                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5077
5078                 /*
5079                  * No more DR vmexits; force a reload of the debug registers
5080                  * and reenter on this instruction.  The next vmexit will
5081                  * retrieve the full state of the debug registers.
5082                  */
5083                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5084                 return 1;
5085         }
5086
5087         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5088         if (exit_qualification & TYPE_MOV_FROM_DR) {
5089                 unsigned long val;
5090
5091                 kvm_get_dr(vcpu, dr, &val);
5092                 kvm_register_write(vcpu, reg, val);
5093                 err = 0;
5094         } else {
5095                 err = kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg));
5096         }
5097
5098 out:
5099         return kvm_complete_insn_gp(vcpu, err);
5100 }
5101
5102 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5103 {
5104         get_debugreg(vcpu->arch.db[0], 0);
5105         get_debugreg(vcpu->arch.db[1], 1);
5106         get_debugreg(vcpu->arch.db[2], 2);
5107         get_debugreg(vcpu->arch.db[3], 3);
5108         get_debugreg(vcpu->arch.dr6, 6);
5109         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5110
5111         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5112         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5113 }
5114
5115 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5116 {
5117         vmcs_writel(GUEST_DR7, val);
5118 }
5119
5120 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5121 {
5122         kvm_apic_update_ppr(vcpu);
5123         return 1;
5124 }
5125
5126 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5127 {
5128         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5129
5130         kvm_make_request(KVM_REQ_EVENT, vcpu);
5131
5132         ++vcpu->stat.irq_window_exits;
5133         return 1;
5134 }
5135
5136 static int handle_invlpg(struct kvm_vcpu *vcpu)
5137 {
5138         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5139
5140         kvm_mmu_invlpg(vcpu, exit_qualification);
5141         return kvm_skip_emulated_instruction(vcpu);
5142 }
5143
5144 static int handle_apic_access(struct kvm_vcpu *vcpu)
5145 {
5146         if (likely(fasteoi)) {
5147                 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5148                 int access_type, offset;
5149
5150                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5151                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5152                 /*
5153                  * Sane guest uses MOV to write EOI, with written value
5154                  * not cared. So make a short-circuit here by avoiding
5155                  * heavy instruction emulation.
5156                  */
5157                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5158                     (offset == APIC_EOI)) {
5159                         kvm_lapic_set_eoi(vcpu);
5160                         return kvm_skip_emulated_instruction(vcpu);
5161                 }
5162         }
5163         return kvm_emulate_instruction(vcpu, 0);
5164 }
5165
5166 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5167 {
5168         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5169         int vector = exit_qualification & 0xff;
5170
5171         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5172         kvm_apic_set_eoi_accelerated(vcpu, vector);
5173         return 1;
5174 }
5175
5176 static int handle_apic_write(struct kvm_vcpu *vcpu)
5177 {
5178         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5179         u32 offset = exit_qualification & 0xfff;
5180
5181         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5182         kvm_apic_write_nodecode(vcpu, offset);
5183         return 1;
5184 }
5185
5186 static int handle_task_switch(struct kvm_vcpu *vcpu)
5187 {
5188         struct vcpu_vmx *vmx = to_vmx(vcpu);
5189         unsigned long exit_qualification;
5190         bool has_error_code = false;
5191         u32 error_code = 0;
5192         u16 tss_selector;
5193         int reason, type, idt_v, idt_index;
5194
5195         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5196         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5197         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5198
5199         exit_qualification = vmx_get_exit_qual(vcpu);
5200
5201         reason = (u32)exit_qualification >> 30;
5202         if (reason == TASK_SWITCH_GATE && idt_v) {
5203                 switch (type) {
5204                 case INTR_TYPE_NMI_INTR:
5205                         vcpu->arch.nmi_injected = false;
5206                         vmx_set_nmi_mask(vcpu, true);
5207                         break;
5208                 case INTR_TYPE_EXT_INTR:
5209                 case INTR_TYPE_SOFT_INTR:
5210                         kvm_clear_interrupt_queue(vcpu);
5211                         break;
5212                 case INTR_TYPE_HARD_EXCEPTION:
5213                         if (vmx->idt_vectoring_info &
5214                             VECTORING_INFO_DELIVER_CODE_MASK) {
5215                                 has_error_code = true;
5216                                 error_code =
5217                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5218                         }
5219                         fallthrough;
5220                 case INTR_TYPE_SOFT_EXCEPTION:
5221                         kvm_clear_exception_queue(vcpu);
5222                         break;
5223                 default:
5224                         break;
5225                 }
5226         }
5227         tss_selector = exit_qualification;
5228
5229         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5230                        type != INTR_TYPE_EXT_INTR &&
5231                        type != INTR_TYPE_NMI_INTR))
5232                 WARN_ON(!skip_emulated_instruction(vcpu));
5233
5234         /*
5235          * TODO: What about debug traps on tss switch?
5236          *       Are we supposed to inject them and update dr6?
5237          */
5238         return kvm_task_switch(vcpu, tss_selector,
5239                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5240                                reason, has_error_code, error_code);
5241 }
5242
5243 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5244 {
5245         unsigned long exit_qualification;
5246         gpa_t gpa;
5247         u64 error_code;
5248
5249         exit_qualification = vmx_get_exit_qual(vcpu);
5250
5251         /*
5252          * EPT violation happened while executing iret from NMI,
5253          * "blocked by NMI" bit has to be set before next VM entry.
5254          * There are errata that may cause this bit to not be set:
5255          * AAK134, BY25.
5256          */
5257         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5258                         enable_vnmi &&
5259                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5260                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5261
5262         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5263         trace_kvm_page_fault(gpa, exit_qualification);
5264
5265         /* Is it a read fault? */
5266         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5267                      ? PFERR_USER_MASK : 0;
5268         /* Is it a write fault? */
5269         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5270                       ? PFERR_WRITE_MASK : 0;
5271         /* Is it a fetch fault? */
5272         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5273                       ? PFERR_FETCH_MASK : 0;
5274         /* ept page table entry is present? */
5275         error_code |= (exit_qualification &
5276                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5277                         EPT_VIOLATION_EXECUTABLE))
5278                       ? PFERR_PRESENT_MASK : 0;
5279
5280         error_code |= (exit_qualification & EPT_VIOLATION_GVA_TRANSLATED) != 0 ?
5281                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5282
5283         vcpu->arch.exit_qualification = exit_qualification;
5284
5285         /*
5286          * Check that the GPA doesn't exceed physical memory limits, as that is
5287          * a guest page fault.  We have to emulate the instruction here, because
5288          * if the illegal address is that of a paging structure, then
5289          * EPT_VIOLATION_ACC_WRITE bit is set.  Alternatively, if supported we
5290          * would also use advanced VM-exit information for EPT violations to
5291          * reconstruct the page fault error code.
5292          */
5293         if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa)))
5294                 return kvm_emulate_instruction(vcpu, 0);
5295
5296         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5297 }
5298
5299 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5300 {
5301         gpa_t gpa;
5302
5303         if (!vmx_can_emulate_instruction(vcpu, NULL, 0))
5304                 return 1;
5305
5306         /*
5307          * A nested guest cannot optimize MMIO vmexits, because we have an
5308          * nGPA here instead of the required GPA.
5309          */
5310         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5311         if (!is_guest_mode(vcpu) &&
5312             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5313                 trace_kvm_fast_mmio(gpa);
5314                 return kvm_skip_emulated_instruction(vcpu);
5315         }
5316
5317         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5318 }
5319
5320 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5321 {
5322         if (KVM_BUG_ON(!enable_vnmi, vcpu->kvm))
5323                 return -EIO;
5324
5325         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5326         ++vcpu->stat.nmi_window_exits;
5327         kvm_make_request(KVM_REQ_EVENT, vcpu);
5328
5329         return 1;
5330 }
5331
5332 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5333 {
5334         struct vcpu_vmx *vmx = to_vmx(vcpu);
5335         bool intr_window_requested;
5336         unsigned count = 130;
5337
5338         intr_window_requested = exec_controls_get(vmx) &
5339                                 CPU_BASED_INTR_WINDOW_EXITING;
5340
5341         while (vmx->emulation_required && count-- != 0) {
5342                 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5343                         return handle_interrupt_window(&vmx->vcpu);
5344
5345                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5346                         return 1;
5347
5348                 if (!kvm_emulate_instruction(vcpu, 0))
5349                         return 0;
5350
5351                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5352                     vcpu->arch.exception.pending) {
5353                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5354                         vcpu->run->internal.suberror =
5355                                                 KVM_INTERNAL_ERROR_EMULATION;
5356                         vcpu->run->internal.ndata = 0;
5357                         return 0;
5358                 }
5359
5360                 if (vcpu->arch.halt_request) {
5361                         vcpu->arch.halt_request = 0;
5362                         return kvm_vcpu_halt(vcpu);
5363                 }
5364
5365                 /*
5366                  * Note, return 1 and not 0, vcpu_run() will invoke
5367                  * xfer_to_guest_mode() which will create a proper return
5368                  * code.
5369                  */
5370                 if (__xfer_to_guest_mode_work_pending())
5371                         return 1;
5372         }
5373
5374         return 1;
5375 }
5376
5377 static void grow_ple_window(struct kvm_vcpu *vcpu)
5378 {
5379         struct vcpu_vmx *vmx = to_vmx(vcpu);
5380         unsigned int old = vmx->ple_window;
5381
5382         vmx->ple_window = __grow_ple_window(old, ple_window,
5383                                             ple_window_grow,
5384                                             ple_window_max);
5385
5386         if (vmx->ple_window != old) {
5387                 vmx->ple_window_dirty = true;
5388                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5389                                             vmx->ple_window, old);
5390         }
5391 }
5392
5393 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5394 {
5395         struct vcpu_vmx *vmx = to_vmx(vcpu);
5396         unsigned int old = vmx->ple_window;
5397
5398         vmx->ple_window = __shrink_ple_window(old, ple_window,
5399                                               ple_window_shrink,
5400                                               ple_window);
5401
5402         if (vmx->ple_window != old) {
5403                 vmx->ple_window_dirty = true;
5404                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5405                                             vmx->ple_window, old);
5406         }
5407 }
5408
5409 /*
5410  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5411  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5412  */
5413 static int handle_pause(struct kvm_vcpu *vcpu)
5414 {
5415         if (!kvm_pause_in_guest(vcpu->kvm))
5416                 grow_ple_window(vcpu);
5417
5418         /*
5419          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5420          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5421          * never set PAUSE_EXITING and just set PLE if supported,
5422          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5423          */
5424         kvm_vcpu_on_spin(vcpu, true);
5425         return kvm_skip_emulated_instruction(vcpu);
5426 }
5427
5428 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5429 {
5430         return 1;
5431 }
5432
5433 static int handle_invpcid(struct kvm_vcpu *vcpu)
5434 {
5435         u32 vmx_instruction_info;
5436         unsigned long type;
5437         gva_t gva;
5438         struct {
5439                 u64 pcid;
5440                 u64 gla;
5441         } operand;
5442
5443         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5444                 kvm_queue_exception(vcpu, UD_VECTOR);
5445                 return 1;
5446         }
5447
5448         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5449         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
5450
5451         if (type > 3) {
5452                 kvm_inject_gp(vcpu, 0);
5453                 return 1;
5454         }
5455
5456         /* According to the Intel instruction reference, the memory operand
5457          * is read even if it isn't needed (e.g., for type==all)
5458          */
5459         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5460                                 vmx_instruction_info, false,
5461                                 sizeof(operand), &gva))
5462                 return 1;
5463
5464         return kvm_handle_invpcid(vcpu, type, gva);
5465 }
5466
5467 static int handle_pml_full(struct kvm_vcpu *vcpu)
5468 {
5469         unsigned long exit_qualification;
5470
5471         trace_kvm_pml_full(vcpu->vcpu_id);
5472
5473         exit_qualification = vmx_get_exit_qual(vcpu);
5474
5475         /*
5476          * PML buffer FULL happened while executing iret from NMI,
5477          * "blocked by NMI" bit has to be set before next VM entry.
5478          */
5479         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5480                         enable_vnmi &&
5481                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5482                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5483                                 GUEST_INTR_STATE_NMI);
5484
5485         /*
5486          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5487          * here.., and there's no userspace involvement needed for PML.
5488          */
5489         return 1;
5490 }
5491
5492 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5493 {
5494         struct vcpu_vmx *vmx = to_vmx(vcpu);
5495
5496         if (!vmx->req_immediate_exit &&
5497             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5498                 kvm_lapic_expired_hv_timer(vcpu);
5499                 return EXIT_FASTPATH_REENTER_GUEST;
5500         }
5501
5502         return EXIT_FASTPATH_NONE;
5503 }
5504
5505 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5506 {
5507         handle_fastpath_preemption_timer(vcpu);
5508         return 1;
5509 }
5510
5511 /*
5512  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5513  * are overwritten by nested_vmx_setup() when nested=1.
5514  */
5515 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5516 {
5517         kvm_queue_exception(vcpu, UD_VECTOR);
5518         return 1;
5519 }
5520
5521 #ifndef CONFIG_X86_SGX_KVM
5522 static int handle_encls(struct kvm_vcpu *vcpu)
5523 {
5524         /*
5525          * SGX virtualization is disabled.  There is no software enable bit for
5526          * SGX, so KVM intercepts all ENCLS leafs and injects a #UD to prevent
5527          * the guest from executing ENCLS (when SGX is supported by hardware).
5528          */
5529         kvm_queue_exception(vcpu, UD_VECTOR);
5530         return 1;
5531 }
5532 #endif /* CONFIG_X86_SGX_KVM */
5533
5534 static int handle_bus_lock_vmexit(struct kvm_vcpu *vcpu)
5535 {
5536         vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
5537         vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
5538         return 0;
5539 }
5540
5541 /*
5542  * The exit handlers return 1 if the exit was handled fully and guest execution
5543  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5544  * to be done to userspace and return 0.
5545  */
5546 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5547         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5548         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5549         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5550         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5551         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5552         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5553         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5554         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5555         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5556         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5557         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5558         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5559         [EXIT_REASON_INVD]                    = kvm_emulate_invd,
5560         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5561         [EXIT_REASON_RDPMC]                   = kvm_emulate_rdpmc,
5562         [EXIT_REASON_VMCALL]                  = kvm_emulate_hypercall,
5563         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5564         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5565         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5566         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5567         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5568         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5569         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5570         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5571         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5572         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5573         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5574         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5575         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5576         [EXIT_REASON_WBINVD]                  = kvm_emulate_wbinvd,
5577         [EXIT_REASON_XSETBV]                  = kvm_emulate_xsetbv,
5578         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5579         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5580         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5581         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5582         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5583         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5584         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5585         [EXIT_REASON_MWAIT_INSTRUCTION]       = kvm_emulate_mwait,
5586         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5587         [EXIT_REASON_MONITOR_INSTRUCTION]     = kvm_emulate_monitor,
5588         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5589         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5590         [EXIT_REASON_RDRAND]                  = kvm_handle_invalid_op,
5591         [EXIT_REASON_RDSEED]                  = kvm_handle_invalid_op,
5592         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5593         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5594         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5595         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5596         [EXIT_REASON_ENCLS]                   = handle_encls,
5597         [EXIT_REASON_BUS_LOCK]                = handle_bus_lock_vmexit,
5598 };
5599
5600 static const int kvm_vmx_max_exit_handlers =
5601         ARRAY_SIZE(kvm_vmx_exit_handlers);
5602
5603 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
5604                               u32 *intr_info, u32 *error_code)
5605 {
5606         struct vcpu_vmx *vmx = to_vmx(vcpu);
5607
5608         *info1 = vmx_get_exit_qual(vcpu);
5609         if (!(vmx->exit_reason.failed_vmentry)) {
5610                 *info2 = vmx->idt_vectoring_info;
5611                 *intr_info = vmx_get_intr_info(vcpu);
5612                 if (is_exception_with_error_code(*intr_info))
5613                         *error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5614                 else
5615                         *error_code = 0;
5616         } else {
5617                 *info2 = 0;
5618                 *intr_info = 0;
5619                 *error_code = 0;
5620         }
5621 }
5622
5623 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5624 {
5625         if (vmx->pml_pg) {
5626                 __free_page(vmx->pml_pg);
5627                 vmx->pml_pg = NULL;
5628         }
5629 }
5630
5631 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5632 {
5633         struct vcpu_vmx *vmx = to_vmx(vcpu);
5634         u64 *pml_buf;
5635         u16 pml_idx;
5636
5637         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5638
5639         /* Do nothing if PML buffer is empty */
5640         if (pml_idx == (PML_ENTITY_NUM - 1))
5641                 return;
5642
5643         /* PML index always points to next available PML buffer entity */
5644         if (pml_idx >= PML_ENTITY_NUM)
5645                 pml_idx = 0;
5646         else
5647                 pml_idx++;
5648
5649         pml_buf = page_address(vmx->pml_pg);
5650         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5651                 u64 gpa;
5652
5653                 gpa = pml_buf[pml_idx];
5654                 WARN_ON(gpa & (PAGE_SIZE - 1));
5655                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5656         }
5657
5658         /* reset PML index */
5659         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5660 }
5661
5662 static void vmx_dump_sel(char *name, uint32_t sel)
5663 {
5664         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5665                name, vmcs_read16(sel),
5666                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5667                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5668                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5669 }
5670
5671 static void vmx_dump_dtsel(char *name, uint32_t limit)
5672 {
5673         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5674                name, vmcs_read32(limit),
5675                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5676 }
5677
5678 static void vmx_dump_msrs(char *name, struct vmx_msrs *m)
5679 {
5680         unsigned int i;
5681         struct vmx_msr_entry *e;
5682
5683         pr_err("MSR %s:\n", name);
5684         for (i = 0, e = m->val; i < m->nr; ++i, ++e)
5685                 pr_err("  %2d: msr=0x%08x value=0x%016llx\n", i, e->index, e->value);
5686 }
5687
5688 void dump_vmcs(struct kvm_vcpu *vcpu)
5689 {
5690         struct vcpu_vmx *vmx = to_vmx(vcpu);
5691         u32 vmentry_ctl, vmexit_ctl;
5692         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5693         unsigned long cr4;
5694         int efer_slot;
5695
5696         if (!dump_invalid_vmcs) {
5697                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5698                 return;
5699         }
5700
5701         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5702         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5703         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5704         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5705         cr4 = vmcs_readl(GUEST_CR4);
5706         secondary_exec_control = 0;
5707         if (cpu_has_secondary_exec_ctrls())
5708                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5709
5710         pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
5711                vmx->loaded_vmcs->vmcs, vcpu->arch.last_vmentry_cpu);
5712         pr_err("*** Guest State ***\n");
5713         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5714                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5715                vmcs_readl(CR0_GUEST_HOST_MASK));
5716         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5717                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5718         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5719         if (cpu_has_vmx_ept()) {
5720                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5721                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5722                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5723                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5724         }
5725         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5726                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5727         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5728                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5729         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5730                vmcs_readl(GUEST_SYSENTER_ESP),
5731                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5732         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5733         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5734         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5735         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5736         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5737         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5738         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5739         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5740         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5741         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5742         efer_slot = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, MSR_EFER);
5743         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_EFER)
5744                 pr_err("EFER= 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER));
5745         else if (efer_slot >= 0)
5746                 pr_err("EFER= 0x%016llx (autoload)\n",
5747                        vmx->msr_autoload.guest.val[efer_slot].value);
5748         else if (vmentry_ctl & VM_ENTRY_IA32E_MODE)
5749                 pr_err("EFER= 0x%016llx (effective)\n",
5750                        vcpu->arch.efer | (EFER_LMA | EFER_LME));
5751         else
5752                 pr_err("EFER= 0x%016llx (effective)\n",
5753                        vcpu->arch.efer & ~(EFER_LMA | EFER_LME));
5754         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PAT)
5755                 pr_err("PAT = 0x%016llx\n", vmcs_read64(GUEST_IA32_PAT));
5756         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5757                vmcs_read64(GUEST_IA32_DEBUGCTL),
5758                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5759         if (cpu_has_load_perf_global_ctrl() &&
5760             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5761                 pr_err("PerfGlobCtl = 0x%016llx\n",
5762                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5763         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5764                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5765         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5766                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5767                vmcs_read32(GUEST_ACTIVITY_STATE));
5768         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5769                 pr_err("InterruptStatus = %04x\n",
5770                        vmcs_read16(GUEST_INTR_STATUS));
5771         if (vmcs_read32(VM_ENTRY_MSR_LOAD_COUNT) > 0)
5772                 vmx_dump_msrs("guest autoload", &vmx->msr_autoload.guest);
5773         if (vmcs_read32(VM_EXIT_MSR_STORE_COUNT) > 0)
5774                 vmx_dump_msrs("guest autostore", &vmx->msr_autostore.guest);
5775
5776         pr_err("*** Host State ***\n");
5777         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5778                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5779         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5780                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5781                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5782                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5783                vmcs_read16(HOST_TR_SELECTOR));
5784         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5785                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5786                vmcs_readl(HOST_TR_BASE));
5787         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5788                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5789         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5790                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5791                vmcs_readl(HOST_CR4));
5792         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5793                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5794                vmcs_read32(HOST_IA32_SYSENTER_CS),
5795                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5796         if (vmexit_ctl & VM_EXIT_LOAD_IA32_EFER)
5797                 pr_err("EFER= 0x%016llx\n", vmcs_read64(HOST_IA32_EFER));
5798         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PAT)
5799                 pr_err("PAT = 0x%016llx\n", vmcs_read64(HOST_IA32_PAT));
5800         if (cpu_has_load_perf_global_ctrl() &&
5801             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5802                 pr_err("PerfGlobCtl = 0x%016llx\n",
5803                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5804         if (vmcs_read32(VM_EXIT_MSR_LOAD_COUNT) > 0)
5805                 vmx_dump_msrs("host autoload", &vmx->msr_autoload.host);
5806
5807         pr_err("*** Control State ***\n");
5808         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5809                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5810         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5811         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5812                vmcs_read32(EXCEPTION_BITMAP),
5813                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5814                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5815         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5816                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5817                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5818                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5819         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5820                vmcs_read32(VM_EXIT_INTR_INFO),
5821                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5822                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5823         pr_err("        reason=%08x qualification=%016lx\n",
5824                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5825         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5826                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5827                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5828         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5829         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5830                 pr_err("TSC Multiplier = 0x%016llx\n",
5831                        vmcs_read64(TSC_MULTIPLIER));
5832         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5833                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5834                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5835                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5836                 }
5837                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5838                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5839                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5840                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5841         }
5842         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5843                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5844         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5845                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5846         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5847                 pr_err("PLE Gap=%08x Window=%08x\n",
5848                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5849         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5850                 pr_err("Virtual processor ID = 0x%04x\n",
5851                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5852 }
5853
5854 /*
5855  * The guest has exited.  See if we can fix it or if we need userspace
5856  * assistance.
5857  */
5858 static int __vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5859 {
5860         struct vcpu_vmx *vmx = to_vmx(vcpu);
5861         union vmx_exit_reason exit_reason = vmx->exit_reason;
5862         u32 vectoring_info = vmx->idt_vectoring_info;
5863         u16 exit_handler_index;
5864
5865         /*
5866          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5867          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5868          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5869          * mode as if vcpus is in root mode, the PML buffer must has been
5870          * flushed already.  Note, PML is never enabled in hardware while
5871          * running L2.
5872          */
5873         if (enable_pml && !is_guest_mode(vcpu))
5874                 vmx_flush_pml_buffer(vcpu);
5875
5876         /*
5877          * We should never reach this point with a pending nested VM-Enter, and
5878          * more specifically emulation of L2 due to invalid guest state (see
5879          * below) should never happen as that means we incorrectly allowed a
5880          * nested VM-Enter with an invalid vmcs12.
5881          */
5882         if (KVM_BUG_ON(vmx->nested.nested_run_pending, vcpu->kvm))
5883                 return -EIO;
5884
5885         /* If guest state is invalid, start emulating */
5886         if (vmx->emulation_required)
5887                 return handle_invalid_guest_state(vcpu);
5888
5889         if (is_guest_mode(vcpu)) {
5890                 /*
5891                  * PML is never enabled when running L2, bail immediately if a
5892                  * PML full exit occurs as something is horribly wrong.
5893                  */
5894                 if (exit_reason.basic == EXIT_REASON_PML_FULL)
5895                         goto unexpected_vmexit;
5896
5897                 /*
5898                  * The host physical addresses of some pages of guest memory
5899                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5900                  * Page). The CPU may write to these pages via their host
5901                  * physical address while L2 is running, bypassing any
5902                  * address-translation-based dirty tracking (e.g. EPT write
5903                  * protection).
5904                  *
5905                  * Mark them dirty on every exit from L2 to prevent them from
5906                  * getting out of sync with dirty tracking.
5907                  */
5908                 nested_mark_vmcs12_pages_dirty(vcpu);
5909
5910                 if (nested_vmx_reflect_vmexit(vcpu))
5911                         return 1;
5912         }
5913
5914         if (exit_reason.failed_vmentry) {
5915                 dump_vmcs(vcpu);
5916                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5917                 vcpu->run->fail_entry.hardware_entry_failure_reason
5918                         = exit_reason.full;
5919                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5920                 return 0;
5921         }
5922
5923         if (unlikely(vmx->fail)) {
5924                 dump_vmcs(vcpu);
5925                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5926                 vcpu->run->fail_entry.hardware_entry_failure_reason
5927                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5928                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5929                 return 0;
5930         }
5931
5932         /*
5933          * Note:
5934          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5935          * delivery event since it indicates guest is accessing MMIO.
5936          * The vm-exit can be triggered again after return to guest that
5937          * will cause infinite loop.
5938          */
5939         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5940             (exit_reason.basic != EXIT_REASON_EXCEPTION_NMI &&
5941              exit_reason.basic != EXIT_REASON_EPT_VIOLATION &&
5942              exit_reason.basic != EXIT_REASON_PML_FULL &&
5943              exit_reason.basic != EXIT_REASON_APIC_ACCESS &&
5944              exit_reason.basic != EXIT_REASON_TASK_SWITCH)) {
5945                 int ndata = 3;
5946
5947                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5948                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5949                 vcpu->run->internal.data[0] = vectoring_info;
5950                 vcpu->run->internal.data[1] = exit_reason.full;
5951                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5952                 if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG) {
5953                         vcpu->run->internal.data[ndata++] =
5954                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5955                 }
5956                 vcpu->run->internal.data[ndata++] = vcpu->arch.last_vmentry_cpu;
5957                 vcpu->run->internal.ndata = ndata;
5958                 return 0;
5959         }
5960
5961         if (unlikely(!enable_vnmi &&
5962                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5963                 if (!vmx_interrupt_blocked(vcpu)) {
5964                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5965                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5966                            vcpu->arch.nmi_pending) {
5967                         /*
5968                          * This CPU don't support us in finding the end of an
5969                          * NMI-blocked window if the guest runs with IRQs
5970                          * disabled. So we pull the trigger after 1 s of
5971                          * futile waiting, but inform the user about this.
5972                          */
5973                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5974                                "state on VCPU %d after 1 s timeout\n",
5975                                __func__, vcpu->vcpu_id);
5976                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5977                 }
5978         }
5979
5980         if (exit_fastpath != EXIT_FASTPATH_NONE)
5981                 return 1;
5982
5983         if (exit_reason.basic >= kvm_vmx_max_exit_handlers)
5984                 goto unexpected_vmexit;
5985 #ifdef CONFIG_RETPOLINE
5986         if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
5987                 return kvm_emulate_wrmsr(vcpu);
5988         else if (exit_reason.basic == EXIT_REASON_PREEMPTION_TIMER)
5989                 return handle_preemption_timer(vcpu);
5990         else if (exit_reason.basic == EXIT_REASON_INTERRUPT_WINDOW)
5991                 return handle_interrupt_window(vcpu);
5992         else if (exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
5993                 return handle_external_interrupt(vcpu);
5994         else if (exit_reason.basic == EXIT_REASON_HLT)
5995                 return kvm_emulate_halt(vcpu);
5996         else if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG)
5997                 return handle_ept_misconfig(vcpu);
5998 #endif
5999
6000         exit_handler_index = array_index_nospec((u16)exit_reason.basic,
6001                                                 kvm_vmx_max_exit_handlers);
6002         if (!kvm_vmx_exit_handlers[exit_handler_index])
6003                 goto unexpected_vmexit;
6004
6005         return kvm_vmx_exit_handlers[exit_handler_index](vcpu);
6006
6007 unexpected_vmexit:
6008         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
6009                     exit_reason.full);
6010         dump_vmcs(vcpu);
6011         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6012         vcpu->run->internal.suberror =
6013                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6014         vcpu->run->internal.ndata = 2;
6015         vcpu->run->internal.data[0] = exit_reason.full;
6016         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6017         return 0;
6018 }
6019
6020 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6021 {
6022         int ret = __vmx_handle_exit(vcpu, exit_fastpath);
6023
6024         /*
6025          * Even when current exit reason is handled by KVM internally, we
6026          * still need to exit to user space when bus lock detected to inform
6027          * that there is a bus lock in guest.
6028          */
6029         if (to_vmx(vcpu)->exit_reason.bus_lock_detected) {
6030                 if (ret > 0)
6031                         vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
6032
6033                 vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
6034                 return 0;
6035         }
6036         return ret;
6037 }
6038
6039 /*
6040  * Software based L1D cache flush which is used when microcode providing
6041  * the cache control MSR is not loaded.
6042  *
6043  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6044  * flush it is required to read in 64 KiB because the replacement algorithm
6045  * is not exactly LRU. This could be sized at runtime via topology
6046  * information but as all relevant affected CPUs have 32KiB L1D cache size
6047  * there is no point in doing so.
6048  */
6049 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6050 {
6051         int size = PAGE_SIZE << L1D_CACHE_ORDER;
6052
6053         /*
6054          * This code is only executed when the the flush mode is 'cond' or
6055          * 'always'
6056          */
6057         if (static_branch_likely(&vmx_l1d_flush_cond)) {
6058                 bool flush_l1d;
6059
6060                 /*
6061                  * Clear the per-vcpu flush bit, it gets set again
6062                  * either from vcpu_run() or from one of the unsafe
6063                  * VMEXIT handlers.
6064                  */
6065                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6066                 vcpu->arch.l1tf_flush_l1d = false;
6067
6068                 /*
6069                  * Clear the per-cpu flush bit, it gets set again from
6070                  * the interrupt handlers.
6071                  */
6072                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6073                 kvm_clear_cpu_l1tf_flush_l1d();
6074
6075                 if (!flush_l1d)
6076                         return;
6077         }
6078
6079         vcpu->stat.l1d_flush++;
6080
6081         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6082                 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6083                 return;
6084         }
6085
6086         asm volatile(
6087                 /* First ensure the pages are in the TLB */
6088                 "xorl   %%eax, %%eax\n"
6089                 ".Lpopulate_tlb:\n\t"
6090                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6091                 "addl   $4096, %%eax\n\t"
6092                 "cmpl   %%eax, %[size]\n\t"
6093                 "jne    .Lpopulate_tlb\n\t"
6094                 "xorl   %%eax, %%eax\n\t"
6095                 "cpuid\n\t"
6096                 /* Now fill the cache */
6097                 "xorl   %%eax, %%eax\n"
6098                 ".Lfill_cache:\n"
6099                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6100                 "addl   $64, %%eax\n\t"
6101                 "cmpl   %%eax, %[size]\n\t"
6102                 "jne    .Lfill_cache\n\t"
6103                 "lfence\n"
6104                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6105                     [size] "r" (size)
6106                 : "eax", "ebx", "ecx", "edx");
6107 }
6108
6109 static void vmx_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6110 {
6111         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6112         int tpr_threshold;
6113
6114         if (is_guest_mode(vcpu) &&
6115                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6116                 return;
6117
6118         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6119         if (is_guest_mode(vcpu))
6120                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6121         else
6122                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6123 }
6124
6125 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6126 {
6127         struct vcpu_vmx *vmx = to_vmx(vcpu);
6128         u32 sec_exec_control;
6129
6130         if (!lapic_in_kernel(vcpu))
6131                 return;
6132
6133         if (!flexpriority_enabled &&
6134             !cpu_has_vmx_virtualize_x2apic_mode())
6135                 return;
6136
6137         /* Postpone execution until vmcs01 is the current VMCS. */
6138         if (is_guest_mode(vcpu)) {
6139                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6140                 return;
6141         }
6142
6143         sec_exec_control = secondary_exec_controls_get(vmx);
6144         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6145                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6146
6147         switch (kvm_get_apic_mode(vcpu)) {
6148         case LAPIC_MODE_INVALID:
6149                 WARN_ONCE(true, "Invalid local APIC state");
6150                 break;
6151         case LAPIC_MODE_DISABLED:
6152                 break;
6153         case LAPIC_MODE_XAPIC:
6154                 if (flexpriority_enabled) {
6155                         sec_exec_control |=
6156                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6157                         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6158
6159                         /*
6160                          * Flush the TLB, reloading the APIC access page will
6161                          * only do so if its physical address has changed, but
6162                          * the guest may have inserted a non-APIC mapping into
6163                          * the TLB while the APIC access page was disabled.
6164                          */
6165                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6166                 }
6167                 break;
6168         case LAPIC_MODE_X2APIC:
6169                 if (cpu_has_vmx_virtualize_x2apic_mode())
6170                         sec_exec_control |=
6171                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6172                 break;
6173         }
6174         secondary_exec_controls_set(vmx, sec_exec_control);
6175
6176         vmx_update_msr_bitmap_x2apic(vcpu);
6177 }
6178
6179 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6180 {
6181         struct page *page;
6182
6183         /* Defer reload until vmcs01 is the current VMCS. */
6184         if (is_guest_mode(vcpu)) {
6185                 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6186                 return;
6187         }
6188
6189         if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6190             SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6191                 return;
6192
6193         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6194         if (is_error_page(page))
6195                 return;
6196
6197         vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6198         vmx_flush_tlb_current(vcpu);
6199
6200         /*
6201          * Do not pin apic access page in memory, the MMU notifier
6202          * will call us again if it is migrated or swapped out.
6203          */
6204         put_page(page);
6205 }
6206
6207 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6208 {
6209         u16 status;
6210         u8 old;
6211
6212         if (max_isr == -1)
6213                 max_isr = 0;
6214
6215         status = vmcs_read16(GUEST_INTR_STATUS);
6216         old = status >> 8;
6217         if (max_isr != old) {
6218                 status &= 0xff;
6219                 status |= max_isr << 8;
6220                 vmcs_write16(GUEST_INTR_STATUS, status);
6221         }
6222 }
6223
6224 static void vmx_set_rvi(int vector)
6225 {
6226         u16 status;
6227         u8 old;
6228
6229         if (vector == -1)
6230                 vector = 0;
6231
6232         status = vmcs_read16(GUEST_INTR_STATUS);
6233         old = (u8)status & 0xff;
6234         if ((u8)vector != old) {
6235                 status &= ~0xff;
6236                 status |= (u8)vector;
6237                 vmcs_write16(GUEST_INTR_STATUS, status);
6238         }
6239 }
6240
6241 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6242 {
6243         /*
6244          * When running L2, updating RVI is only relevant when
6245          * vmcs12 virtual-interrupt-delivery enabled.
6246          * However, it can be enabled only when L1 also
6247          * intercepts external-interrupts and in that case
6248          * we should not update vmcs02 RVI but instead intercept
6249          * interrupt. Therefore, do nothing when running L2.
6250          */
6251         if (!is_guest_mode(vcpu))
6252                 vmx_set_rvi(max_irr);
6253 }
6254
6255 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6256 {
6257         struct vcpu_vmx *vmx = to_vmx(vcpu);
6258         int max_irr;
6259         bool max_irr_updated;
6260
6261         if (KVM_BUG_ON(!vcpu->arch.apicv_active, vcpu->kvm))
6262                 return -EIO;
6263
6264         if (pi_test_on(&vmx->pi_desc)) {
6265                 pi_clear_on(&vmx->pi_desc);
6266                 /*
6267                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6268                  * But on x86 this is just a compiler barrier anyway.
6269                  */
6270                 smp_mb__after_atomic();
6271                 max_irr_updated =
6272                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6273
6274                 /*
6275                  * If we are running L2 and L1 has a new pending interrupt
6276                  * which can be injected, we should re-evaluate
6277                  * what should be done with this new L1 interrupt.
6278                  * If L1 intercepts external-interrupts, we should
6279                  * exit from L2 to L1. Otherwise, interrupt should be
6280                  * delivered directly to L2.
6281                  */
6282                 if (is_guest_mode(vcpu) && max_irr_updated) {
6283                         if (nested_exit_on_intr(vcpu))
6284                                 kvm_vcpu_exiting_guest_mode(vcpu);
6285                         else
6286                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6287                 }
6288         } else {
6289                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6290         }
6291         vmx_hwapic_irr_update(vcpu, max_irr);
6292         return max_irr;
6293 }
6294
6295 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6296 {
6297         if (!kvm_vcpu_apicv_active(vcpu))
6298                 return;
6299
6300         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6301         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6302         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6303         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6304 }
6305
6306 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6307 {
6308         struct vcpu_vmx *vmx = to_vmx(vcpu);
6309
6310         pi_clear_on(&vmx->pi_desc);
6311         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6312 }
6313
6314 void vmx_do_interrupt_nmi_irqoff(unsigned long entry);
6315
6316 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu,
6317                                         unsigned long entry)
6318 {
6319         kvm_before_interrupt(vcpu);
6320         vmx_do_interrupt_nmi_irqoff(entry);
6321         kvm_after_interrupt(vcpu);
6322 }
6323
6324 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6325 {
6326         const unsigned long nmi_entry = (unsigned long)asm_exc_nmi_noist;
6327         u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6328
6329         /* if exit due to PF check for async PF */
6330         if (is_page_fault(intr_info))
6331                 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6332         /* Handle machine checks before interrupts are enabled */
6333         else if (is_machine_check(intr_info))
6334                 kvm_machine_check();
6335         /* We need to handle NMIs before interrupts are enabled */
6336         else if (is_nmi(intr_info))
6337                 handle_interrupt_nmi_irqoff(&vmx->vcpu, nmi_entry);
6338 }
6339
6340 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6341 {
6342         u32 intr_info = vmx_get_intr_info(vcpu);
6343         unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK;
6344         gate_desc *desc = (gate_desc *)host_idt_base + vector;
6345
6346         if (KVM_BUG(!is_external_intr(intr_info), vcpu->kvm,
6347             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6348                 return;
6349
6350         handle_interrupt_nmi_irqoff(vcpu, gate_offset(desc));
6351 }
6352
6353 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6354 {
6355         struct vcpu_vmx *vmx = to_vmx(vcpu);
6356
6357         if (vmx->exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6358                 handle_external_interrupt_irqoff(vcpu);
6359         else if (vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI)
6360                 handle_exception_nmi_irqoff(vmx);
6361 }
6362
6363 /*
6364  * The kvm parameter can be NULL (module initialization, or invocation before
6365  * VM creation). Be sure to check the kvm parameter before using it.
6366  */
6367 static bool vmx_has_emulated_msr(struct kvm *kvm, u32 index)
6368 {
6369         switch (index) {
6370         case MSR_IA32_SMBASE:
6371                 /*
6372                  * We cannot do SMM unless we can run the guest in big
6373                  * real mode.
6374                  */
6375                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6376         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6377                 return nested;
6378         case MSR_AMD64_VIRT_SPEC_CTRL:
6379                 /* This is AMD only.  */
6380                 return false;
6381         default:
6382                 return true;
6383         }
6384 }
6385
6386 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6387 {
6388         u32 exit_intr_info;
6389         bool unblock_nmi;
6390         u8 vector;
6391         bool idtv_info_valid;
6392
6393         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6394
6395         if (enable_vnmi) {
6396                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6397                         return;
6398
6399                 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6400                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6401                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6402                 /*
6403                  * SDM 3: 27.7.1.2 (September 2008)
6404                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6405                  * a guest IRET fault.
6406                  * SDM 3: 23.2.2 (September 2008)
6407                  * Bit 12 is undefined in any of the following cases:
6408                  *  If the VM exit sets the valid bit in the IDT-vectoring
6409                  *   information field.
6410                  *  If the VM exit is due to a double fault.
6411                  */
6412                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6413                     vector != DF_VECTOR && !idtv_info_valid)
6414                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6415                                       GUEST_INTR_STATE_NMI);
6416                 else
6417                         vmx->loaded_vmcs->nmi_known_unmasked =
6418                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6419                                   & GUEST_INTR_STATE_NMI);
6420         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6421                 vmx->loaded_vmcs->vnmi_blocked_time +=
6422                         ktime_to_ns(ktime_sub(ktime_get(),
6423                                               vmx->loaded_vmcs->entry_time));
6424 }
6425
6426 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6427                                       u32 idt_vectoring_info,
6428                                       int instr_len_field,
6429                                       int error_code_field)
6430 {
6431         u8 vector;
6432         int type;
6433         bool idtv_info_valid;
6434
6435         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6436
6437         vcpu->arch.nmi_injected = false;
6438         kvm_clear_exception_queue(vcpu);
6439         kvm_clear_interrupt_queue(vcpu);
6440
6441         if (!idtv_info_valid)
6442                 return;
6443
6444         kvm_make_request(KVM_REQ_EVENT, vcpu);
6445
6446         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6447         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6448
6449         switch (type) {
6450         case INTR_TYPE_NMI_INTR:
6451                 vcpu->arch.nmi_injected = true;
6452                 /*
6453                  * SDM 3: 27.7.1.2 (September 2008)
6454                  * Clear bit "block by NMI" before VM entry if a NMI
6455                  * delivery faulted.
6456                  */
6457                 vmx_set_nmi_mask(vcpu, false);
6458                 break;
6459         case INTR_TYPE_SOFT_EXCEPTION:
6460                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6461                 fallthrough;
6462         case INTR_TYPE_HARD_EXCEPTION:
6463                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6464                         u32 err = vmcs_read32(error_code_field);
6465                         kvm_requeue_exception_e(vcpu, vector, err);
6466                 } else
6467                         kvm_requeue_exception(vcpu, vector);
6468                 break;
6469         case INTR_TYPE_SOFT_INTR:
6470                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6471                 fallthrough;
6472         case INTR_TYPE_EXT_INTR:
6473                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6474                 break;
6475         default:
6476                 break;
6477         }
6478 }
6479
6480 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6481 {
6482         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6483                                   VM_EXIT_INSTRUCTION_LEN,
6484                                   IDT_VECTORING_ERROR_CODE);
6485 }
6486
6487 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6488 {
6489         __vmx_complete_interrupts(vcpu,
6490                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6491                                   VM_ENTRY_INSTRUCTION_LEN,
6492                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6493
6494         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6495 }
6496
6497 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6498 {
6499         int i, nr_msrs;
6500         struct perf_guest_switch_msr *msrs;
6501
6502         /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
6503         msrs = perf_guest_get_msrs(&nr_msrs);
6504         if (!msrs)
6505                 return;
6506
6507         for (i = 0; i < nr_msrs; i++)
6508                 if (msrs[i].host == msrs[i].guest)
6509                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6510                 else
6511                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6512                                         msrs[i].host, false);
6513 }
6514
6515 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6516 {
6517         struct vcpu_vmx *vmx = to_vmx(vcpu);
6518         u64 tscl;
6519         u32 delta_tsc;
6520
6521         if (vmx->req_immediate_exit) {
6522                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6523                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6524         } else if (vmx->hv_deadline_tsc != -1) {
6525                 tscl = rdtsc();
6526                 if (vmx->hv_deadline_tsc > tscl)
6527                         /* set_hv_timer ensures the delta fits in 32-bits */
6528                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6529                                 cpu_preemption_timer_multi);
6530                 else
6531                         delta_tsc = 0;
6532
6533                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6534                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6535         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6536                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6537                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6538         }
6539 }
6540
6541 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6542 {
6543         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6544                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6545                 vmcs_writel(HOST_RSP, host_rsp);
6546         }
6547 }
6548
6549 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6550 {
6551         switch (to_vmx(vcpu)->exit_reason.basic) {
6552         case EXIT_REASON_MSR_WRITE:
6553                 return handle_fastpath_set_msr_irqoff(vcpu);
6554         case EXIT_REASON_PREEMPTION_TIMER:
6555                 return handle_fastpath_preemption_timer(vcpu);
6556         default:
6557                 return EXIT_FASTPATH_NONE;
6558         }
6559 }
6560
6561 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6562                                         struct vcpu_vmx *vmx)
6563 {
6564         kvm_guest_enter_irqoff();
6565
6566         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6567         if (static_branch_unlikely(&vmx_l1d_should_flush))
6568                 vmx_l1d_flush(vcpu);
6569         else if (static_branch_unlikely(&mds_user_clear))
6570                 mds_clear_cpu_buffers();
6571
6572         if (vcpu->arch.cr2 != native_read_cr2())
6573                 native_write_cr2(vcpu->arch.cr2);
6574
6575         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6576                                    vmx->loaded_vmcs->launched);
6577
6578         vcpu->arch.cr2 = native_read_cr2();
6579
6580         kvm_guest_exit_irqoff();
6581 }
6582
6583 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6584 {
6585         struct vcpu_vmx *vmx = to_vmx(vcpu);
6586         unsigned long cr3, cr4;
6587
6588         /* Record the guest's net vcpu time for enforced NMI injections. */
6589         if (unlikely(!enable_vnmi &&
6590                      vmx->loaded_vmcs->soft_vnmi_blocked))
6591                 vmx->loaded_vmcs->entry_time = ktime_get();
6592
6593         /* Don't enter VMX if guest state is invalid, let the exit handler
6594            start emulation until we arrive back to a valid state */
6595         if (vmx->emulation_required)
6596                 return EXIT_FASTPATH_NONE;
6597
6598         trace_kvm_entry(vcpu);
6599
6600         if (vmx->ple_window_dirty) {
6601                 vmx->ple_window_dirty = false;
6602                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6603         }
6604
6605         /*
6606          * We did this in prepare_switch_to_guest, because it needs to
6607          * be within srcu_read_lock.
6608          */
6609         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6610
6611         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6612                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6613         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6614                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6615
6616         cr3 = __get_current_cr3_fast();
6617         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6618                 vmcs_writel(HOST_CR3, cr3);
6619                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6620         }
6621
6622         cr4 = cr4_read_shadow();
6623         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6624                 vmcs_writel(HOST_CR4, cr4);
6625                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6626         }
6627
6628         /* When single-stepping over STI and MOV SS, we must clear the
6629          * corresponding interruptibility bits in the guest state. Otherwise
6630          * vmentry fails as it then expects bit 14 (BS) in pending debug
6631          * exceptions being set, but that's not correct for the guest debugging
6632          * case. */
6633         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6634                 vmx_set_interrupt_shadow(vcpu, 0);
6635
6636         kvm_load_guest_xsave_state(vcpu);
6637
6638         pt_guest_enter(vmx);
6639
6640         atomic_switch_perf_msrs(vmx);
6641         if (intel_pmu_lbr_is_enabled(vcpu))
6642                 vmx_passthrough_lbr_msrs(vcpu);
6643
6644         if (enable_preemption_timer)
6645                 vmx_update_hv_timer(vcpu);
6646
6647         kvm_wait_lapic_expire(vcpu);
6648
6649         /*
6650          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6651          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6652          * is no need to worry about the conditional branch over the wrmsr
6653          * being speculatively taken.
6654          */
6655         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6656
6657         /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6658         vmx_vcpu_enter_exit(vcpu, vmx);
6659
6660         /*
6661          * We do not use IBRS in the kernel. If this vCPU has used the
6662          * SPEC_CTRL MSR it may have left it on; save the value and
6663          * turn it off. This is much more efficient than blindly adding
6664          * it to the atomic save/restore list. Especially as the former
6665          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6666          *
6667          * For non-nested case:
6668          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6669          * save it.
6670          *
6671          * For nested case:
6672          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6673          * save it.
6674          */
6675         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6676                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6677
6678         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6679
6680         /* All fields are clean at this point */
6681         if (static_branch_unlikely(&enable_evmcs)) {
6682                 current_evmcs->hv_clean_fields |=
6683                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6684
6685                 current_evmcs->hv_vp_id = kvm_hv_get_vpindex(vcpu);
6686         }
6687
6688         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6689         if (vmx->host_debugctlmsr)
6690                 update_debugctlmsr(vmx->host_debugctlmsr);
6691
6692 #ifndef CONFIG_X86_64
6693         /*
6694          * The sysexit path does not restore ds/es, so we must set them to
6695          * a reasonable value ourselves.
6696          *
6697          * We can't defer this to vmx_prepare_switch_to_host() since that
6698          * function may be executed in interrupt context, which saves and
6699          * restore segments around it, nullifying its effect.
6700          */
6701         loadsegment(ds, __USER_DS);
6702         loadsegment(es, __USER_DS);
6703 #endif
6704
6705         vmx_register_cache_reset(vcpu);
6706
6707         pt_guest_exit(vmx);
6708
6709         kvm_load_host_xsave_state(vcpu);
6710
6711         if (is_guest_mode(vcpu)) {
6712                 /*
6713                  * Track VMLAUNCH/VMRESUME that have made past guest state
6714                  * checking.
6715                  */
6716                 if (vmx->nested.nested_run_pending &&
6717                     !vmx->exit_reason.failed_vmentry)
6718                         ++vcpu->stat.nested_run;
6719
6720                 vmx->nested.nested_run_pending = 0;
6721         }
6722
6723         vmx->idt_vectoring_info = 0;
6724
6725         if (unlikely(vmx->fail)) {
6726                 vmx->exit_reason.full = 0xdead;
6727                 return EXIT_FASTPATH_NONE;
6728         }
6729
6730         vmx->exit_reason.full = vmcs_read32(VM_EXIT_REASON);
6731         if (unlikely((u16)vmx->exit_reason.basic == EXIT_REASON_MCE_DURING_VMENTRY))
6732                 kvm_machine_check();
6733
6734         if (likely(!vmx->exit_reason.failed_vmentry))
6735                 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6736
6737         trace_kvm_exit(vmx->exit_reason.full, vcpu, KVM_ISA_VMX);
6738
6739         if (unlikely(vmx->exit_reason.failed_vmentry))
6740                 return EXIT_FASTPATH_NONE;
6741
6742         vmx->loaded_vmcs->launched = 1;
6743
6744         vmx_recover_nmi_blocking(vmx);
6745         vmx_complete_interrupts(vmx);
6746
6747         if (is_guest_mode(vcpu))
6748                 return EXIT_FASTPATH_NONE;
6749
6750         return vmx_exit_handlers_fastpath(vcpu);
6751 }
6752
6753 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6754 {
6755         struct vcpu_vmx *vmx = to_vmx(vcpu);
6756
6757         if (enable_pml)
6758                 vmx_destroy_pml_buffer(vmx);
6759         free_vpid(vmx->vpid);
6760         nested_vmx_free_vcpu(vcpu);
6761         free_loaded_vmcs(vmx->loaded_vmcs);
6762 }
6763
6764 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6765 {
6766         struct vmx_uret_msr *tsx_ctrl;
6767         struct vcpu_vmx *vmx;
6768         int i, cpu, err;
6769
6770         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6771         vmx = to_vmx(vcpu);
6772
6773         err = -ENOMEM;
6774
6775         vmx->vpid = allocate_vpid();
6776
6777         /*
6778          * If PML is turned on, failure on enabling PML just results in failure
6779          * of creating the vcpu, therefore we can simplify PML logic (by
6780          * avoiding dealing with cases, such as enabling PML partially on vcpus
6781          * for the guest), etc.
6782          */
6783         if (enable_pml) {
6784                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6785                 if (!vmx->pml_pg)
6786                         goto free_vpid;
6787         }
6788
6789         for (i = 0; i < kvm_nr_uret_msrs; ++i) {
6790                 vmx->guest_uret_msrs[i].data = 0;
6791                 vmx->guest_uret_msrs[i].mask = -1ull;
6792         }
6793         if (boot_cpu_has(X86_FEATURE_RTM)) {
6794                 /*
6795                  * TSX_CTRL_CPUID_CLEAR is handled in the CPUID interception.
6796                  * Keep the host value unchanged to avoid changing CPUID bits
6797                  * under the host kernel's feet.
6798                  */
6799                 tsx_ctrl = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
6800                 if (tsx_ctrl)
6801                         vmx->guest_uret_msrs[i].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6802         }
6803
6804         err = alloc_loaded_vmcs(&vmx->vmcs01);
6805         if (err < 0)
6806                 goto free_pml;
6807
6808         /* The MSR bitmap starts with all ones */
6809         bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6810         bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6811
6812         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
6813 #ifdef CONFIG_X86_64
6814         vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
6815         vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
6816         vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6817 #endif
6818         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6819         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6820         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6821         if (kvm_cstate_in_guest(vcpu->kvm)) {
6822                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
6823                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6824                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6825                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6826         }
6827
6828         vmx->loaded_vmcs = &vmx->vmcs01;
6829         cpu = get_cpu();
6830         vmx_vcpu_load(vcpu, cpu);
6831         vcpu->cpu = cpu;
6832         init_vmcs(vmx);
6833         vmx_vcpu_put(vcpu);
6834         put_cpu();
6835         if (cpu_need_virtualize_apic_accesses(vcpu)) {
6836                 err = alloc_apic_access_page(vcpu->kvm);
6837                 if (err)
6838                         goto free_vmcs;
6839         }
6840
6841         if (enable_ept && !enable_unrestricted_guest) {
6842                 err = init_rmode_identity_map(vcpu->kvm);
6843                 if (err)
6844                         goto free_vmcs;
6845         }
6846
6847         if (nested)
6848                 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
6849         else
6850                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6851
6852         vcpu_setup_sgx_lepubkeyhash(vcpu);
6853
6854         vmx->nested.posted_intr_nv = -1;
6855         vmx->nested.current_vmptr = -1ull;
6856         vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
6857
6858         vcpu->arch.microcode_version = 0x100000000ULL;
6859         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6860
6861         /*
6862          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6863          * or POSTED_INTR_WAKEUP_VECTOR.
6864          */
6865         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6866         vmx->pi_desc.sn = 1;
6867
6868         return 0;
6869
6870 free_vmcs:
6871         free_loaded_vmcs(vmx->loaded_vmcs);
6872 free_pml:
6873         vmx_destroy_pml_buffer(vmx);
6874 free_vpid:
6875         free_vpid(vmx->vpid);
6876         return err;
6877 }
6878
6879 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6880 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6881
6882 static int vmx_vm_init(struct kvm *kvm)
6883 {
6884         if (!ple_gap)
6885                 kvm->arch.pause_in_guest = true;
6886
6887         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6888                 switch (l1tf_mitigation) {
6889                 case L1TF_MITIGATION_OFF:
6890                 case L1TF_MITIGATION_FLUSH_NOWARN:
6891                         /* 'I explicitly don't care' is set */
6892                         break;
6893                 case L1TF_MITIGATION_FLUSH:
6894                 case L1TF_MITIGATION_FLUSH_NOSMT:
6895                 case L1TF_MITIGATION_FULL:
6896                         /*
6897                          * Warn upon starting the first VM in a potentially
6898                          * insecure environment.
6899                          */
6900                         if (sched_smt_active())
6901                                 pr_warn_once(L1TF_MSG_SMT);
6902                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6903                                 pr_warn_once(L1TF_MSG_L1D);
6904                         break;
6905                 case L1TF_MITIGATION_FULL_FORCE:
6906                         /* Flush is enforced */
6907                         break;
6908                 }
6909         }
6910         return 0;
6911 }
6912
6913 static int __init vmx_check_processor_compat(void)
6914 {
6915         struct vmcs_config vmcs_conf;
6916         struct vmx_capability vmx_cap;
6917
6918         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6919             !this_cpu_has(X86_FEATURE_VMX)) {
6920                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6921                 return -EIO;
6922         }
6923
6924         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6925                 return -EIO;
6926         if (nested)
6927                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6928         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6929                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6930                                 smp_processor_id());
6931                 return -EIO;
6932         }
6933         return 0;
6934 }
6935
6936 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6937 {
6938         u8 cache;
6939         u64 ipat = 0;
6940
6941         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6942          * memory aliases with conflicting memory types and sometimes MCEs.
6943          * We have to be careful as to what are honored and when.
6944          *
6945          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
6946          * UC.  The effective memory type is UC or WC depending on guest PAT.
6947          * This was historically the source of MCEs and we want to be
6948          * conservative.
6949          *
6950          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6951          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
6952          * EPT memory type is set to WB.  The effective memory type is forced
6953          * WB.
6954          *
6955          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
6956          * EPT memory type is used to emulate guest CD/MTRR.
6957          */
6958
6959         if (is_mmio) {
6960                 cache = MTRR_TYPE_UNCACHABLE;
6961                 goto exit;
6962         }
6963
6964         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6965                 ipat = VMX_EPT_IPAT_BIT;
6966                 cache = MTRR_TYPE_WRBACK;
6967                 goto exit;
6968         }
6969
6970         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6971                 ipat = VMX_EPT_IPAT_BIT;
6972                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6973                         cache = MTRR_TYPE_WRBACK;
6974                 else
6975                         cache = MTRR_TYPE_UNCACHABLE;
6976                 goto exit;
6977         }
6978
6979         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6980
6981 exit:
6982         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6983 }
6984
6985 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6986 {
6987         /*
6988          * These bits in the secondary execution controls field
6989          * are dynamic, the others are mostly based on the hypervisor
6990          * architecture and the guest's CPUID.  Do not touch the
6991          * dynamic bits.
6992          */
6993         u32 mask =
6994                 SECONDARY_EXEC_SHADOW_VMCS |
6995                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6996                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6997                 SECONDARY_EXEC_DESC;
6998
6999         u32 new_ctl = vmx->secondary_exec_control;
7000         u32 cur_ctl = secondary_exec_controls_get(vmx);
7001
7002         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7003 }
7004
7005 /*
7006  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7007  * (indicating "allowed-1") if they are supported in the guest's CPUID.
7008  */
7009 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7010 {
7011         struct vcpu_vmx *vmx = to_vmx(vcpu);
7012         struct kvm_cpuid_entry2 *entry;
7013
7014         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7015         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7016
7017 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
7018         if (entry && (entry->_reg & (_cpuid_mask)))                     \
7019                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
7020 } while (0)
7021
7022         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7023         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
7024         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
7025         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
7026         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
7027         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
7028         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
7029         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
7030         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
7031         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
7032         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7033         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
7034         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
7035         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
7036         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
7037
7038         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7039         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
7040         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
7041         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
7042         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
7043         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
7044         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
7045
7046 #undef cr4_fixed1_update
7047 }
7048
7049 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7050 {
7051         struct vcpu_vmx *vmx = to_vmx(vcpu);
7052
7053         if (kvm_mpx_supported()) {
7054                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7055
7056                 if (mpx_enabled) {
7057                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7058                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7059                 } else {
7060                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7061                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7062                 }
7063         }
7064 }
7065
7066 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7067 {
7068         struct vcpu_vmx *vmx = to_vmx(vcpu);
7069         struct kvm_cpuid_entry2 *best = NULL;
7070         int i;
7071
7072         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7073                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7074                 if (!best)
7075                         return;
7076                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7077                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7078                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7079                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7080         }
7081
7082         /* Get the number of configurable Address Ranges for filtering */
7083         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7084                                                 PT_CAP_num_address_ranges);
7085
7086         /* Initialize and clear the no dependency bits */
7087         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7088                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7089
7090         /*
7091          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7092          * will inject an #GP
7093          */
7094         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7095                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7096
7097         /*
7098          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7099          * PSBFreq can be set
7100          */
7101         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7102                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7103                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7104
7105         /*
7106          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7107          * MTCFreq can be set
7108          */
7109         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7110                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7111                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7112
7113         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7114         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7115                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7116                                                         RTIT_CTL_PTW_EN);
7117
7118         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7119         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7120                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7121
7122         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7123         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7124                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7125
7126         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabricEn can be set */
7127         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7128                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7129
7130         /* unmask address range configure area */
7131         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7132                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7133 }
7134
7135 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7136 {
7137         struct vcpu_vmx *vmx = to_vmx(vcpu);
7138
7139         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7140         vcpu->arch.xsaves_enabled = false;
7141
7142         vmx_setup_uret_msrs(vmx);
7143
7144         if (cpu_has_secondary_exec_ctrls()) {
7145                 vmx_compute_secondary_exec_control(vmx);
7146                 vmcs_set_secondary_exec_control(vmx);
7147         }
7148
7149         if (nested_vmx_allowed(vcpu))
7150                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7151                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7152                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7153         else
7154                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7155                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7156                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7157
7158         if (nested_vmx_allowed(vcpu)) {
7159                 nested_vmx_cr_fixed1_bits_update(vcpu);
7160                 nested_vmx_entry_exit_ctls_update(vcpu);
7161         }
7162
7163         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7164                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7165                 update_intel_pt_cfg(vcpu);
7166
7167         if (boot_cpu_has(X86_FEATURE_RTM)) {
7168                 struct vmx_uret_msr *msr;
7169                 msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
7170                 if (msr) {
7171                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7172                         vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7173                 }
7174         }
7175
7176         set_cr4_guest_host_mask(vmx);
7177
7178         vmx_write_encls_bitmap(vcpu, NULL);
7179         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX))
7180                 vmx->msr_ia32_feature_control_valid_bits |= FEAT_CTL_SGX_ENABLED;
7181         else
7182                 vmx->msr_ia32_feature_control_valid_bits &= ~FEAT_CTL_SGX_ENABLED;
7183
7184         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
7185                 vmx->msr_ia32_feature_control_valid_bits |=
7186                         FEAT_CTL_SGX_LC_ENABLED;
7187         else
7188                 vmx->msr_ia32_feature_control_valid_bits &=
7189                         ~FEAT_CTL_SGX_LC_ENABLED;
7190
7191         /* Refresh #PF interception to account for MAXPHYADDR changes. */
7192         vmx_update_exception_bitmap(vcpu);
7193 }
7194
7195 static __init void vmx_set_cpu_caps(void)
7196 {
7197         kvm_set_cpu_caps();
7198
7199         /* CPUID 0x1 */
7200         if (nested)
7201                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7202
7203         /* CPUID 0x7 */
7204         if (kvm_mpx_supported())
7205                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7206         if (!cpu_has_vmx_invpcid())
7207                 kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
7208         if (vmx_pt_mode_is_host_guest())
7209                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7210
7211         if (!enable_sgx) {
7212                 kvm_cpu_cap_clear(X86_FEATURE_SGX);
7213                 kvm_cpu_cap_clear(X86_FEATURE_SGX_LC);
7214                 kvm_cpu_cap_clear(X86_FEATURE_SGX1);
7215                 kvm_cpu_cap_clear(X86_FEATURE_SGX2);
7216         }
7217
7218         if (vmx_umip_emulated())
7219                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7220
7221         /* CPUID 0xD.1 */
7222         supported_xss = 0;
7223         if (!cpu_has_vmx_xsaves())
7224                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7225
7226         /* CPUID 0x80000001 and 0x7 (RDPID) */
7227         if (!cpu_has_vmx_rdtscp()) {
7228                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7229                 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
7230         }
7231
7232         if (cpu_has_vmx_waitpkg())
7233                 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7234 }
7235
7236 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7237 {
7238         to_vmx(vcpu)->req_immediate_exit = true;
7239 }
7240
7241 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7242                                   struct x86_instruction_info *info)
7243 {
7244         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7245         unsigned short port;
7246         bool intercept;
7247         int size;
7248
7249         if (info->intercept == x86_intercept_in ||
7250             info->intercept == x86_intercept_ins) {
7251                 port = info->src_val;
7252                 size = info->dst_bytes;
7253         } else {
7254                 port = info->dst_val;
7255                 size = info->src_bytes;
7256         }
7257
7258         /*
7259          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7260          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7261          * control.
7262          *
7263          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7264          */
7265         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7266                 intercept = nested_cpu_has(vmcs12,
7267                                            CPU_BASED_UNCOND_IO_EXITING);
7268         else
7269                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7270
7271         /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7272         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7273 }
7274
7275 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7276                                struct x86_instruction_info *info,
7277                                enum x86_intercept_stage stage,
7278                                struct x86_exception *exception)
7279 {
7280         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7281
7282         switch (info->intercept) {
7283         /*
7284          * RDPID causes #UD if disabled through secondary execution controls.
7285          * Because it is marked as EmulateOnUD, we need to intercept it here.
7286          * Note, RDPID is hidden behind ENABLE_RDTSCP.
7287          */
7288         case x86_intercept_rdpid:
7289                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) {
7290                         exception->vector = UD_VECTOR;
7291                         exception->error_code_valid = false;
7292                         return X86EMUL_PROPAGATE_FAULT;
7293                 }
7294                 break;
7295
7296         case x86_intercept_in:
7297         case x86_intercept_ins:
7298         case x86_intercept_out:
7299         case x86_intercept_outs:
7300                 return vmx_check_intercept_io(vcpu, info);
7301
7302         case x86_intercept_lgdt:
7303         case x86_intercept_lidt:
7304         case x86_intercept_lldt:
7305         case x86_intercept_ltr:
7306         case x86_intercept_sgdt:
7307         case x86_intercept_sidt:
7308         case x86_intercept_sldt:
7309         case x86_intercept_str:
7310                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7311                         return X86EMUL_CONTINUE;
7312
7313                 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7314                 break;
7315
7316         /* TODO: check more intercepts... */
7317         default:
7318                 break;
7319         }
7320
7321         return X86EMUL_UNHANDLEABLE;
7322 }
7323
7324 #ifdef CONFIG_X86_64
7325 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7326 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7327                                   u64 divisor, u64 *result)
7328 {
7329         u64 low = a << shift, high = a >> (64 - shift);
7330
7331         /* To avoid the overflow on divq */
7332         if (high >= divisor)
7333                 return 1;
7334
7335         /* Low hold the result, high hold rem which is discarded */
7336         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7337             "rm" (divisor), "0" (low), "1" (high));
7338         *result = low;
7339
7340         return 0;
7341 }
7342
7343 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7344                             bool *expired)
7345 {
7346         struct vcpu_vmx *vmx;
7347         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7348         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7349
7350         vmx = to_vmx(vcpu);
7351         tscl = rdtsc();
7352         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7353         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7354         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7355                                                     ktimer->timer_advance_ns);
7356
7357         if (delta_tsc > lapic_timer_advance_cycles)
7358                 delta_tsc -= lapic_timer_advance_cycles;
7359         else
7360                 delta_tsc = 0;
7361
7362         /* Convert to host delta tsc if tsc scaling is enabled */
7363         if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7364             delta_tsc && u64_shl_div_u64(delta_tsc,
7365                                 kvm_tsc_scaling_ratio_frac_bits,
7366                                 vcpu->arch.l1_tsc_scaling_ratio, &delta_tsc))
7367                 return -ERANGE;
7368
7369         /*
7370          * If the delta tsc can't fit in the 32 bit after the multi shift,
7371          * we can't use the preemption timer.
7372          * It's possible that it fits on later vmentries, but checking
7373          * on every vmentry is costly so we just use an hrtimer.
7374          */
7375         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7376                 return -ERANGE;
7377
7378         vmx->hv_deadline_tsc = tscl + delta_tsc;
7379         *expired = !delta_tsc;
7380         return 0;
7381 }
7382
7383 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7384 {
7385         to_vmx(vcpu)->hv_deadline_tsc = -1;
7386 }
7387 #endif
7388
7389 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7390 {
7391         if (!kvm_pause_in_guest(vcpu->kvm))
7392                 shrink_ple_window(vcpu);
7393 }
7394
7395 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu)
7396 {
7397         struct vcpu_vmx *vmx = to_vmx(vcpu);
7398
7399         if (is_guest_mode(vcpu)) {
7400                 vmx->nested.update_vmcs01_cpu_dirty_logging = true;
7401                 return;
7402         }
7403
7404         /*
7405          * Note, cpu_dirty_logging_count can be changed concurrent with this
7406          * code, but in that case another update request will be made and so
7407          * the guest will never run with a stale PML value.
7408          */
7409         if (vcpu->kvm->arch.cpu_dirty_logging_count)
7410                 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7411         else
7412                 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7413 }
7414
7415 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7416 {
7417         if (pi_pre_block(vcpu))
7418                 return 1;
7419
7420         if (kvm_lapic_hv_timer_in_use(vcpu))
7421                 kvm_lapic_switch_to_sw_timer(vcpu);
7422
7423         return 0;
7424 }
7425
7426 static void vmx_post_block(struct kvm_vcpu *vcpu)
7427 {
7428         if (kvm_x86_ops.set_hv_timer)
7429                 kvm_lapic_switch_to_hv_timer(vcpu);
7430
7431         pi_post_block(vcpu);
7432 }
7433
7434 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7435 {
7436         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7437                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7438                         FEAT_CTL_LMCE_ENABLED;
7439         else
7440                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7441                         ~FEAT_CTL_LMCE_ENABLED;
7442 }
7443
7444 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7445 {
7446         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7447         if (to_vmx(vcpu)->nested.nested_run_pending)
7448                 return -EBUSY;
7449         return !is_smm(vcpu);
7450 }
7451
7452 static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7453 {
7454         struct vcpu_vmx *vmx = to_vmx(vcpu);
7455
7456         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7457         if (vmx->nested.smm.guest_mode)
7458                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7459
7460         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7461         vmx->nested.vmxon = false;
7462         vmx_clear_hlt(vcpu);
7463         return 0;
7464 }
7465
7466 static int vmx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7467 {
7468         struct vcpu_vmx *vmx = to_vmx(vcpu);
7469         int ret;
7470
7471         if (vmx->nested.smm.vmxon) {
7472                 vmx->nested.vmxon = true;
7473                 vmx->nested.smm.vmxon = false;
7474         }
7475
7476         if (vmx->nested.smm.guest_mode) {
7477                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7478                 if (ret)
7479                         return ret;
7480
7481                 vmx->nested.smm.guest_mode = false;
7482         }
7483         return 0;
7484 }
7485
7486 static void vmx_enable_smi_window(struct kvm_vcpu *vcpu)
7487 {
7488         /* RSM will cause a vmexit anyway.  */
7489 }
7490
7491 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7492 {
7493         return to_vmx(vcpu)->nested.vmxon && !is_guest_mode(vcpu);
7494 }
7495
7496 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7497 {
7498         if (is_guest_mode(vcpu)) {
7499                 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7500
7501                 if (hrtimer_try_to_cancel(timer) == 1)
7502                         hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7503         }
7504 }
7505
7506 static void hardware_unsetup(void)
7507 {
7508         if (nested)
7509                 nested_vmx_hardware_unsetup();
7510
7511         free_kvm_area();
7512 }
7513
7514 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7515 {
7516         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7517                           BIT(APICV_INHIBIT_REASON_HYPERV);
7518
7519         return supported & BIT(bit);
7520 }
7521
7522 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7523         .hardware_unsetup = hardware_unsetup,
7524
7525         .hardware_enable = hardware_enable,
7526         .hardware_disable = hardware_disable,
7527         .cpu_has_accelerated_tpr = report_flexpriority,
7528         .has_emulated_msr = vmx_has_emulated_msr,
7529
7530         .vm_size = sizeof(struct kvm_vmx),
7531         .vm_init = vmx_vm_init,
7532
7533         .vcpu_create = vmx_create_vcpu,
7534         .vcpu_free = vmx_free_vcpu,
7535         .vcpu_reset = vmx_vcpu_reset,
7536
7537         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7538         .vcpu_load = vmx_vcpu_load,
7539         .vcpu_put = vmx_vcpu_put,
7540
7541         .update_exception_bitmap = vmx_update_exception_bitmap,
7542         .get_msr_feature = vmx_get_msr_feature,
7543         .get_msr = vmx_get_msr,
7544         .set_msr = vmx_set_msr,
7545         .get_segment_base = vmx_get_segment_base,
7546         .get_segment = vmx_get_segment,
7547         .set_segment = vmx_set_segment,
7548         .get_cpl = vmx_get_cpl,
7549         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7550         .set_cr0 = vmx_set_cr0,
7551         .is_valid_cr4 = vmx_is_valid_cr4,
7552         .set_cr4 = vmx_set_cr4,
7553         .set_efer = vmx_set_efer,
7554         .get_idt = vmx_get_idt,
7555         .set_idt = vmx_set_idt,
7556         .get_gdt = vmx_get_gdt,
7557         .set_gdt = vmx_set_gdt,
7558         .set_dr7 = vmx_set_dr7,
7559         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7560         .cache_reg = vmx_cache_reg,
7561         .get_rflags = vmx_get_rflags,
7562         .set_rflags = vmx_set_rflags,
7563
7564         .tlb_flush_all = vmx_flush_tlb_all,
7565         .tlb_flush_current = vmx_flush_tlb_current,
7566         .tlb_flush_gva = vmx_flush_tlb_gva,
7567         .tlb_flush_guest = vmx_flush_tlb_guest,
7568
7569         .run = vmx_vcpu_run,
7570         .handle_exit = vmx_handle_exit,
7571         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7572         .update_emulated_instruction = vmx_update_emulated_instruction,
7573         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7574         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7575         .patch_hypercall = vmx_patch_hypercall,
7576         .set_irq = vmx_inject_irq,
7577         .set_nmi = vmx_inject_nmi,
7578         .queue_exception = vmx_queue_exception,
7579         .cancel_injection = vmx_cancel_injection,
7580         .interrupt_allowed = vmx_interrupt_allowed,
7581         .nmi_allowed = vmx_nmi_allowed,
7582         .get_nmi_mask = vmx_get_nmi_mask,
7583         .set_nmi_mask = vmx_set_nmi_mask,
7584         .enable_nmi_window = vmx_enable_nmi_window,
7585         .enable_irq_window = vmx_enable_irq_window,
7586         .update_cr8_intercept = vmx_update_cr8_intercept,
7587         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7588         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7589         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7590         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7591         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7592         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7593         .hwapic_irr_update = vmx_hwapic_irr_update,
7594         .hwapic_isr_update = vmx_hwapic_isr_update,
7595         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7596         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7597         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7598         .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
7599
7600         .set_tss_addr = vmx_set_tss_addr,
7601         .set_identity_map_addr = vmx_set_identity_map_addr,
7602         .get_mt_mask = vmx_get_mt_mask,
7603
7604         .get_exit_info = vmx_get_exit_info,
7605
7606         .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7607
7608         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7609
7610         .get_l2_tsc_offset = vmx_get_l2_tsc_offset,
7611         .get_l2_tsc_multiplier = vmx_get_l2_tsc_multiplier,
7612         .write_tsc_offset = vmx_write_tsc_offset,
7613         .write_tsc_multiplier = vmx_write_tsc_multiplier,
7614
7615         .load_mmu_pgd = vmx_load_mmu_pgd,
7616
7617         .check_intercept = vmx_check_intercept,
7618         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7619
7620         .request_immediate_exit = vmx_request_immediate_exit,
7621
7622         .sched_in = vmx_sched_in,
7623
7624         .cpu_dirty_log_size = PML_ENTITY_NUM,
7625         .update_cpu_dirty_logging = vmx_update_cpu_dirty_logging,
7626
7627         .pre_block = vmx_pre_block,
7628         .post_block = vmx_post_block,
7629
7630         .pmu_ops = &intel_pmu_ops,
7631         .nested_ops = &vmx_nested_ops,
7632
7633         .update_pi_irte = pi_update_irte,
7634         .start_assignment = vmx_pi_start_assignment,
7635
7636 #ifdef CONFIG_X86_64
7637         .set_hv_timer = vmx_set_hv_timer,
7638         .cancel_hv_timer = vmx_cancel_hv_timer,
7639 #endif
7640
7641         .setup_mce = vmx_setup_mce,
7642
7643         .smi_allowed = vmx_smi_allowed,
7644         .enter_smm = vmx_enter_smm,
7645         .leave_smm = vmx_leave_smm,
7646         .enable_smi_window = vmx_enable_smi_window,
7647
7648         .can_emulate_instruction = vmx_can_emulate_instruction,
7649         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7650         .migrate_timers = vmx_migrate_timers,
7651
7652         .msr_filter_changed = vmx_msr_filter_changed,
7653         .complete_emulated_msr = kvm_complete_insn_gp,
7654
7655         .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector,
7656 };
7657
7658 static __init void vmx_setup_user_return_msrs(void)
7659 {
7660
7661         /*
7662          * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
7663          * will emulate SYSCALL in legacy mode if the vendor string in guest
7664          * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
7665          * support this emulation, MSR_STAR is included in the list for i386,
7666          * but is never loaded into hardware.  MSR_CSTAR is also never loaded
7667          * into hardware and is here purely for emulation purposes.
7668          */
7669         const u32 vmx_uret_msrs_list[] = {
7670         #ifdef CONFIG_X86_64
7671                 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
7672         #endif
7673                 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
7674                 MSR_IA32_TSX_CTRL,
7675         };
7676         int i;
7677
7678         BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
7679
7680         for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
7681                 kvm_add_user_return_msr(vmx_uret_msrs_list[i]);
7682 }
7683
7684 static __init int hardware_setup(void)
7685 {
7686         unsigned long host_bndcfgs;
7687         struct desc_ptr dt;
7688         int r, ept_lpage_level;
7689
7690         store_idt(&dt);
7691         host_idt_base = dt.address;
7692
7693         vmx_setup_user_return_msrs();
7694
7695         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7696                 return -EIO;
7697
7698         if (boot_cpu_has(X86_FEATURE_NX))
7699                 kvm_enable_efer_bits(EFER_NX);
7700
7701         if (boot_cpu_has(X86_FEATURE_MPX)) {
7702                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7703                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7704         }
7705
7706         if (!cpu_has_vmx_mpx())
7707                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7708                                     XFEATURE_MASK_BNDCSR);
7709
7710         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7711             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7712                 enable_vpid = 0;
7713
7714         if (!cpu_has_vmx_ept() ||
7715             !cpu_has_vmx_ept_4levels() ||
7716             !cpu_has_vmx_ept_mt_wb() ||
7717             !cpu_has_vmx_invept_global())
7718                 enable_ept = 0;
7719
7720         /* NX support is required for shadow paging. */
7721         if (!enable_ept && !boot_cpu_has(X86_FEATURE_NX)) {
7722                 pr_err_ratelimited("kvm: NX (Execute Disable) not supported\n");
7723                 return -EOPNOTSUPP;
7724         }
7725
7726         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7727                 enable_ept_ad_bits = 0;
7728
7729         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7730                 enable_unrestricted_guest = 0;
7731
7732         if (!cpu_has_vmx_flexpriority())
7733                 flexpriority_enabled = 0;
7734
7735         if (!cpu_has_virtual_nmis())
7736                 enable_vnmi = 0;
7737
7738         /*
7739          * set_apic_access_page_addr() is used to reload apic access
7740          * page upon invalidation.  No need to do anything if not
7741          * using the APIC_ACCESS_ADDR VMCS field.
7742          */
7743         if (!flexpriority_enabled)
7744                 vmx_x86_ops.set_apic_access_page_addr = NULL;
7745
7746         if (!cpu_has_vmx_tpr_shadow())
7747                 vmx_x86_ops.update_cr8_intercept = NULL;
7748
7749 #if IS_ENABLED(CONFIG_HYPERV)
7750         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7751             && enable_ept) {
7752                 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7753                 vmx_x86_ops.tlb_remote_flush_with_range =
7754                                 hv_remote_flush_tlb_with_range;
7755         }
7756 #endif
7757
7758         if (!cpu_has_vmx_ple()) {
7759                 ple_gap = 0;
7760                 ple_window = 0;
7761                 ple_window_grow = 0;
7762                 ple_window_max = 0;
7763                 ple_window_shrink = 0;
7764         }
7765
7766         if (!cpu_has_vmx_apicv()) {
7767                 enable_apicv = 0;
7768                 vmx_x86_ops.sync_pir_to_irr = NULL;
7769         }
7770
7771         if (cpu_has_vmx_tsc_scaling()) {
7772                 kvm_has_tsc_control = true;
7773                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7774                 kvm_tsc_scaling_ratio_frac_bits = 48;
7775         }
7776
7777         kvm_has_bus_lock_exit = cpu_has_vmx_bus_lock_detection();
7778
7779         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7780
7781         if (enable_ept)
7782                 kvm_mmu_set_ept_masks(enable_ept_ad_bits,
7783                                       cpu_has_vmx_ept_execute_only());
7784
7785         if (!enable_ept)
7786                 ept_lpage_level = 0;
7787         else if (cpu_has_vmx_ept_1g_page())
7788                 ept_lpage_level = PG_LEVEL_1G;
7789         else if (cpu_has_vmx_ept_2m_page())
7790                 ept_lpage_level = PG_LEVEL_2M;
7791         else
7792                 ept_lpage_level = PG_LEVEL_4K;
7793         kvm_configure_mmu(enable_ept, vmx_get_max_tdp_level(), ept_lpage_level);
7794
7795         /*
7796          * Only enable PML when hardware supports PML feature, and both EPT
7797          * and EPT A/D bit features are enabled -- PML depends on them to work.
7798          */
7799         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7800                 enable_pml = 0;
7801
7802         if (!enable_pml)
7803                 vmx_x86_ops.cpu_dirty_log_size = 0;
7804
7805         if (!cpu_has_vmx_preemption_timer())
7806                 enable_preemption_timer = false;
7807
7808         if (enable_preemption_timer) {
7809                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7810                 u64 vmx_msr;
7811
7812                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7813                 cpu_preemption_timer_multi =
7814                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7815
7816                 if (tsc_khz)
7817                         use_timer_freq = (u64)tsc_khz * 1000;
7818                 use_timer_freq >>= cpu_preemption_timer_multi;
7819
7820                 /*
7821                  * KVM "disables" the preemption timer by setting it to its max
7822                  * value.  Don't use the timer if it might cause spurious exits
7823                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7824                  */
7825                 if (use_timer_freq > 0xffffffffu / 10)
7826                         enable_preemption_timer = false;
7827         }
7828
7829         if (!enable_preemption_timer) {
7830                 vmx_x86_ops.set_hv_timer = NULL;
7831                 vmx_x86_ops.cancel_hv_timer = NULL;
7832                 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
7833         }
7834
7835         kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler);
7836
7837         kvm_mce_cap_supported |= MCG_LMCE_P;
7838
7839         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7840                 return -EINVAL;
7841         if (!enable_ept || !cpu_has_vmx_intel_pt())
7842                 pt_mode = PT_MODE_SYSTEM;
7843
7844         setup_default_sgx_lepubkeyhash();
7845
7846         if (nested) {
7847                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7848                                            vmx_capability.ept);
7849
7850                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7851                 if (r)
7852                         return r;
7853         }
7854
7855         vmx_set_cpu_caps();
7856
7857         r = alloc_kvm_area();
7858         if (r)
7859                 nested_vmx_hardware_unsetup();
7860         return r;
7861 }
7862
7863 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
7864         .cpu_has_kvm_support = cpu_has_kvm_support,
7865         .disabled_by_bios = vmx_disabled_by_bios,
7866         .check_processor_compatibility = vmx_check_processor_compat,
7867         .hardware_setup = hardware_setup,
7868
7869         .runtime_ops = &vmx_x86_ops,
7870 };
7871
7872 static void vmx_cleanup_l1d_flush(void)
7873 {
7874         if (vmx_l1d_flush_pages) {
7875                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7876                 vmx_l1d_flush_pages = NULL;
7877         }
7878         /* Restore state so sysfs ignores VMX */
7879         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7880 }
7881
7882 static void vmx_exit(void)
7883 {
7884 #ifdef CONFIG_KEXEC_CORE
7885         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7886         synchronize_rcu();
7887 #endif
7888
7889         kvm_exit();
7890
7891 #if IS_ENABLED(CONFIG_HYPERV)
7892         if (static_branch_unlikely(&enable_evmcs)) {
7893                 int cpu;
7894                 struct hv_vp_assist_page *vp_ap;
7895                 /*
7896                  * Reset everything to support using non-enlightened VMCS
7897                  * access later (e.g. when we reload the module with
7898                  * enlightened_vmcs=0)
7899                  */
7900                 for_each_online_cpu(cpu) {
7901                         vp_ap = hv_get_vp_assist_page(cpu);
7902
7903                         if (!vp_ap)
7904                                 continue;
7905
7906                         vp_ap->nested_control.features.directhypercall = 0;
7907                         vp_ap->current_nested_vmcs = 0;
7908                         vp_ap->enlighten_vmentry = 0;
7909                 }
7910
7911                 static_branch_disable(&enable_evmcs);
7912         }
7913 #endif
7914         vmx_cleanup_l1d_flush();
7915
7916         allow_smaller_maxphyaddr = false;
7917 }
7918 module_exit(vmx_exit);
7919
7920 static int __init vmx_init(void)
7921 {
7922         int r, cpu;
7923
7924 #if IS_ENABLED(CONFIG_HYPERV)
7925         /*
7926          * Enlightened VMCS usage should be recommended and the host needs
7927          * to support eVMCS v1 or above. We can also disable eVMCS support
7928          * with module parameter.
7929          */
7930         if (enlightened_vmcs &&
7931             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7932             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7933             KVM_EVMCS_VERSION) {
7934                 int cpu;
7935
7936                 /* Check that we have assist pages on all online CPUs */
7937                 for_each_online_cpu(cpu) {
7938                         if (!hv_get_vp_assist_page(cpu)) {
7939                                 enlightened_vmcs = false;
7940                                 break;
7941                         }
7942                 }
7943
7944                 if (enlightened_vmcs) {
7945                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7946                         static_branch_enable(&enable_evmcs);
7947                 }
7948
7949                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7950                         vmx_x86_ops.enable_direct_tlbflush
7951                                 = hv_enable_direct_tlbflush;
7952
7953         } else {
7954                 enlightened_vmcs = false;
7955         }
7956 #endif
7957
7958         r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
7959                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7960         if (r)
7961                 return r;
7962
7963         /*
7964          * Must be called after kvm_init() so enable_ept is properly set
7965          * up. Hand the parameter mitigation value in which was stored in
7966          * the pre module init parser. If no parameter was given, it will
7967          * contain 'auto' which will be turned into the default 'cond'
7968          * mitigation mode.
7969          */
7970         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7971         if (r) {
7972                 vmx_exit();
7973                 return r;
7974         }
7975
7976         for_each_possible_cpu(cpu) {
7977                 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
7978
7979                 pi_init_cpu(cpu);
7980         }
7981
7982 #ifdef CONFIG_KEXEC_CORE
7983         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7984                            crash_vmclear_local_loaded_vmcss);
7985 #endif
7986         vmx_check_vmcs12_offsets();
7987
7988         /*
7989          * Shadow paging doesn't have a (further) performance penalty
7990          * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it
7991          * by default
7992          */
7993         if (!enable_ept)
7994                 allow_smaller_maxphyaddr = true;
7995
7996         return 0;
7997 }
7998 module_init(vmx_init);