arch/x86/kvm/vmx/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include <linux/frame.h>
  20 #include <linux/highmem.h>
  21 #include <linux/hrtimer.h>
  22 #include <linux/kernel.h>
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/mod_devicetable.h>
  27 #include <linux/mm.h>
  28 #include <linux/sched.h>
  29 #include <linux/sched/smt.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include <linux/trace_events.h>
  33
  34 #include <asm/apic.h>
  35 #include <asm/asm.h>
  36 #include <asm/cpu.h>
  37 #include <asm/debugreg.h>
  38 #include <asm/desc.h>
  39 #include <asm/fpu/internal.h>
  40 #include <asm/io.h>
  41 #include <asm/irq_remapping.h>
  42 #include <asm/kexec.h>
  43 #include <asm/perf_event.h>
  44 #include <asm/mce.h>
  45 #include <asm/mmu_context.h>
  46 #include <asm/mshyperv.h>
  47 #include <asm/spec-ctrl.h>
  48 #include <asm/virtext.h>
  49 #include <asm/vmx.h>
  50
  51 #include "capabilities.h"
  52 #include "cpuid.h"
  53 #include "evmcs.h"
  54 #include "irq.h"
  55 #include "kvm_cache_regs.h"
  56 #include "lapic.h"
  57 #include "mmu.h"
  58 #include "nested.h"
  59 #include "ops.h"
  60 #include "pmu.h"
  61 #include "trace.h"
  62 #include "vmcs.h"
  63 #include "vmcs12.h"
  64 #include "vmx.h"
  65 #include "x86.h"
  66
  67 MODULE_AUTHOR("Qumranet");
  68 MODULE_LICENSE("GPL");
  69
  70 static const struct x86_cpu_id vmx_cpu_id[] = {
  71         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  72         {}
  73 };
  74 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  75
  76 bool __read_mostly enable_vpid = 1;
  77 module_param_named(vpid, enable_vpid, bool, 0444);
  78
  79 static bool __read_mostly enable_vnmi = 1;
  80 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  81
  82 bool __read_mostly flexpriority_enabled = 1;
  83 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  84
  85 bool __read_mostly enable_ept = 1;
  86 module_param_named(ept, enable_ept, bool, S_IRUGO);
  87
  88 bool __read_mostly enable_unrestricted_guest = 1;
  89 module_param_named(unrestricted_guest,
  90                         enable_unrestricted_guest, bool, S_IRUGO);
  91
  92 bool __read_mostly enable_ept_ad_bits = 1;
  93 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  94
  95 static bool __read_mostly emulate_invalid_guest_state = true;
  96 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  97
  98 static bool __read_mostly fasteoi = 1;
  99 module_param(fasteoi, bool, S_IRUGO);
 100
 101 static bool __read_mostly enable_apicv = 1;
 102 module_param(enable_apicv, bool, S_IRUGO);
 103
 104 /*
 105  * If nested=1, nested virtualization is supported, i.e., guests may use
 106  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 107  * use VMX instructions.
 108  */
 109 static bool __read_mostly nested = 1;
 110 module_param(nested, bool, S_IRUGO);
 111
 112 static u64 __read_mostly host_xss;
 113
 114 bool __read_mostly enable_pml = 1;
 115 module_param_named(pml, enable_pml, bool, S_IRUGO);
 116
 117 #define MSR_BITMAP_MODE_X2APIC          1
 118 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 119
 120 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 121
 122 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 123 static int __read_mostly cpu_preemption_timer_multi;
 124 static bool __read_mostly enable_preemption_timer = 1;
 125 #ifdef CONFIG_X86_64
 126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 127 #endif
 128
 129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 131 #define KVM_VM_CR0_ALWAYS_ON                            \
 132         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 133          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 134 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 135         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 136          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 137
 138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 141
 142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 143
 144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 145         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 146         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 147         RTIT_STATUS_BYTECNT))
 148
 149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
 150         (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
 151
 152 /*
 153  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 154  * ple_gap:    upper bound on the amount of time between two successive
 155  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 156  *             According to test, this time is usually smaller than 128 cycles.
 157  * ple_window: upper bound on the amount of time a guest is allowed to execute
 158  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 159  *             less than 2^12 cycles
 160  * Time is measured based on a counter that runs at the same rate as the TSC,
 161  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 162  */
 163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, uint, 0444);
 165
 166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, uint, 0444);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, uint, 0444);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, uint, 0444);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, uint, 0444);
 180
 181 /* Default is SYSTEM mode, 1 for host-guest mode */
 182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 183 module_param(pt_mode, int, S_IRUGO);
 184
 185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 188
 189 /* Storage for pre module init parameter parsing */
 190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 191
 192 static const struct {
 193         const char *option;
 194         bool for_parse;
 195 } vmentry_l1d_param[] = {
 196         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 197         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 198         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 199         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 200         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 201         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 202 };
 203
 204 #define L1D_CACHE_ORDER 4
 205 static void *vmx_l1d_flush_pages;
 206
 207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 208 {
 209         struct page *page;
 210         unsigned int i;
 211
 212         if (!enable_ept) {
 213                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 214                 return 0;
 215         }
 216
 217         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 218                 u64 msr;
 219
 220                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 221                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 222                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 223                         return 0;
 224                 }
 225         }
 226
 227         /* If set to auto use the default l1tf mitigation method */
 228         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 229                 switch (l1tf_mitigation) {
 230                 case L1TF_MITIGATION_OFF:
 231                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 232                         break;
 233                 case L1TF_MITIGATION_FLUSH_NOWARN:
 234                 case L1TF_MITIGATION_FLUSH:
 235                 case L1TF_MITIGATION_FLUSH_NOSMT:
 236                         l1tf = VMENTER_L1D_FLUSH_COND;
 237                         break;
 238                 case L1TF_MITIGATION_FULL:
 239                 case L1TF_MITIGATION_FULL_FORCE:
 240                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 241                         break;
 242                 }
 243         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 244                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 245         }
 246
 247         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 248             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 249                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 250                 if (!page)
 251                         return -ENOMEM;
 252                 vmx_l1d_flush_pages = page_address(page);
 253
 254                 /*
 255                  * Initialize each page with a different pattern in
 256                  * order to protect against KSM in the nested
 257                  * virtualization case.
 258                  */
 259                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 260                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 261                                PAGE_SIZE);
 262                 }
 263         }
 264
 265         l1tf_vmx_mitigation = l1tf;
 266
 267         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 268                 static_branch_enable(&vmx_l1d_should_flush);
 269         else
 270                 static_branch_disable(&vmx_l1d_should_flush);
 271
 272         if (l1tf == VMENTER_L1D_FLUSH_COND)
 273                 static_branch_enable(&vmx_l1d_flush_cond);
 274         else
 275                 static_branch_disable(&vmx_l1d_flush_cond);
 276         return 0;
 277 }
 278
 279 static int vmentry_l1d_flush_parse(const char *s)
 280 {
 281         unsigned int i;
 282
 283         if (s) {
 284                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 285                         if (vmentry_l1d_param[i].for_parse &&
 286                             sysfs_streq(s, vmentry_l1d_param[i].option))
 287                                 return i;
 288                 }
 289         }
 290         return -EINVAL;
 291 }
 292
 293 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 294 {
 295         int l1tf, ret;
 296
 297         l1tf = vmentry_l1d_flush_parse(s);
 298         if (l1tf < 0)
 299                 return l1tf;
 300
 301         if (!boot_cpu_has(X86_BUG_L1TF))
 302                 return 0;
 303
 304         /*
 305          * Has vmx_init() run already? If not then this is the pre init
 306          * parameter parsing. In that case just store the value and let
 307          * vmx_init() do the proper setup after enable_ept has been
 308          * established.
 309          */
 310         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 311                 vmentry_l1d_flush_param = l1tf;
 312                 return 0;
 313         }
 314
 315         mutex_lock(&vmx_l1d_flush_mutex);
 316         ret = vmx_setup_l1d_flush(l1tf);
 317         mutex_unlock(&vmx_l1d_flush_mutex);
 318         return ret;
 319 }
 320
 321 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 322 {
 323         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 324                 return sprintf(s, "???\n");
 325
 326         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 327 }
 328
 329 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 330         .set = vmentry_l1d_flush_set,
 331         .get = vmentry_l1d_flush_get,
 332 };
 333 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 334
 335 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 336 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 337 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 338                                                           u32 msr, int type);
 339
 340 void vmx_vmexit(void);
 341
 342 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 343 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 344 /*
 345  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 346  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 347  */
 348 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 349
 350 /*
 351  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 352  * can find which vCPU should be waken up.
 353  */
 354 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 355 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 356
 357 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 358 static DEFINE_SPINLOCK(vmx_vpid_lock);
 359
 360 struct vmcs_config vmcs_config;
 361 struct vmx_capability vmx_capability;
 362
 363 #define VMX_SEGMENT_FIELD(seg)                                  \
 364         [VCPU_SREG_##seg] = {                                   \
 365                 .selector = GUEST_##seg##_SELECTOR,             \
 366                 .base = GUEST_##seg##_BASE,                     \
 367                 .limit = GUEST_##seg##_LIMIT,                   \
 368                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 369         }
 370
 371 static const struct kvm_vmx_segment_field {
 372         unsigned selector;
 373         unsigned base;
 374         unsigned limit;
 375         unsigned ar_bytes;
 376 } kvm_vmx_segment_fields[] = {
 377         VMX_SEGMENT_FIELD(CS),
 378         VMX_SEGMENT_FIELD(DS),
 379         VMX_SEGMENT_FIELD(ES),
 380         VMX_SEGMENT_FIELD(FS),
 381         VMX_SEGMENT_FIELD(GS),
 382         VMX_SEGMENT_FIELD(SS),
 383         VMX_SEGMENT_FIELD(TR),
 384         VMX_SEGMENT_FIELD(LDTR),
 385 };
 386
 387 u64 host_efer;
 388
 389 /*
 390  * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
 391  * will emulate SYSCALL in legacy mode if the vendor string in guest
 392  * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
 393  * support this emulation, IA32_STAR must always be included in
 394  * vmx_msr_index[], even in i386 builds.
 395  */
 396 const u32 vmx_msr_index[] = {
 397 #ifdef CONFIG_X86_64
 398         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 399 #endif
 400         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 401 };
 402
 403 #if IS_ENABLED(CONFIG_HYPERV)
 404 static bool __read_mostly enlightened_vmcs = true;
 405 module_param(enlightened_vmcs, bool, 0444);
 406
 407 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
 408 static void check_ept_pointer_match(struct kvm *kvm)
 409 {
 410         struct kvm_vcpu *vcpu;
 411         u64 tmp_eptp = INVALID_PAGE;
 412         int i;
 413
 414         kvm_for_each_vcpu(i, vcpu, kvm) {
 415                 if (!VALID_PAGE(tmp_eptp)) {
 416                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
 417                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
 418                         to_kvm_vmx(kvm)->ept_pointers_match
 419                                 = EPT_POINTERS_MISMATCH;
 420                         return;
 421                 }
 422         }
 423
 424         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
 425 }
 426
 427 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
 428                 void *data)
 429 {
 430         struct kvm_tlb_range *range = data;
 431
 432         return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
 433                         range->pages);
 434 }
 435
 436 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
 437                 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
 438 {
 439         u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
 440
 441         /*
 442          * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
 443          * of the base of EPT PML4 table, strip off EPT configuration
 444          * information.
 445          */
 446         if (range)
 447                 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
 448                                 kvm_fill_hv_flush_list_func, (void *)range);
 449         else
 450                 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
 451 }
 452
 453 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
 454                 struct kvm_tlb_range *range)
 455 {
 456         struct kvm_vcpu *vcpu;
 457         int ret = 0, i;
 458
 459         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 460
 461         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
 462                 check_ept_pointer_match(kvm);
 463
 464         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
 465                 kvm_for_each_vcpu(i, vcpu, kvm) {
 466                         /* If ept_pointer is invalid pointer, bypass flush request. */
 467                         if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
 468                                 ret |= __hv_remote_flush_tlb_with_range(
 469                                         kvm, vcpu, range);
 470                 }
 471         } else {
 472                 ret = __hv_remote_flush_tlb_with_range(kvm,
 473                                 kvm_get_vcpu(kvm, 0), range);
 474         }
 475
 476         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 477         return ret;
 478 }
 479 static int hv_remote_flush_tlb(struct kvm *kvm)
 480 {
 481         return hv_remote_flush_tlb_with_range(kvm, NULL);
 482 }
 483
 484 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 485
 486 /*
 487  * Comment's format: document - errata name - stepping - processor name.
 488  * Refer from
 489  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 490  */
 491 static u32 vmx_preemption_cpu_tfms[] = {
 492 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 493 0x000206E6,
 494 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 495 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 496 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 497 0x00020652,
 498 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 499 0x00020655,
 500 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 501 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 502 /*
 503  * 320767.pdf - AAP86  - B1 -
 504  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 505  */
 506 0x000106E5,
 507 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 508 0x000106A0,
 509 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 510 0x000106A1,
 511 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 512 0x000106A4,
 513  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 514  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 515  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 516 0x000106A5,
 517  /* Xeon E3-1220 V2 */
 518 0x000306A8,
 519 };
 520
 521 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 522 {
 523         u32 eax = cpuid_eax(0x00000001), i;
 524
 525         /* Clear the reserved bits */
 526         eax &= ~(0x3U << 14 | 0xfU << 28);
 527         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 528                 if (eax == vmx_preemption_cpu_tfms[i])
 529                         return true;
 530
 531         return false;
 532 }
 533
 534 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 535 {
 536         return flexpriority_enabled && lapic_in_kernel(vcpu);
 537 }
 538
 539 static inline bool report_flexpriority(void)
 540 {
 541         return flexpriority_enabled;
 542 }
 543
 544 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 545 {
 546         int i;
 547
 548         for (i = 0; i < vmx->nmsrs; ++i)
 549                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 550                         return i;
 551         return -1;
 552 }
 553
 554 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 555 {
 556         int i;
 557
 558         i = __find_msr_index(vmx, msr);
 559         if (i >= 0)
 560                 return &vmx->guest_msrs[i];
 561         return NULL;
 562 }
 563
 564 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 565 {
 566         vmcs_clear(loaded_vmcs->vmcs);
 567         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 568                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 569         loaded_vmcs->cpu = -1;
 570         loaded_vmcs->launched = 0;
 571 }
 572
 573 #ifdef CONFIG_KEXEC_CORE
 574 /*
 575  * This bitmap is used to indicate whether the vmclear
 576  * operation is enabled on all cpus. All disabled by
 577  * default.
 578  */
 579 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
 580
 581 static inline void crash_enable_local_vmclear(int cpu)
 582 {
 583         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
 584 }
 585
 586 static inline void crash_disable_local_vmclear(int cpu)
 587 {
 588         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
 589 }
 590
 591 static inline int crash_local_vmclear_enabled(int cpu)
 592 {
 593         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
 594 }
 595
 596 static void crash_vmclear_local_loaded_vmcss(void)
 597 {
 598         int cpu = raw_smp_processor_id();
 599         struct loaded_vmcs *v;
 600
 601         if (!crash_local_vmclear_enabled(cpu))
 602                 return;
 603
 604         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 605                             loaded_vmcss_on_cpu_link)
 606                 vmcs_clear(v->vmcs);
 607 }
 608 #else
 609 static inline void crash_enable_local_vmclear(int cpu) { }
 610 static inline void crash_disable_local_vmclear(int cpu) { }
 611 #endif /* CONFIG_KEXEC_CORE */
 612
 613 static void __loaded_vmcs_clear(void *arg)
 614 {
 615         struct loaded_vmcs *loaded_vmcs = arg;
 616         int cpu = raw_smp_processor_id();
 617
 618         if (loaded_vmcs->cpu != cpu)
 619                 return; /* vcpu migration can race with cpu offline */
 620         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 621                 per_cpu(current_vmcs, cpu) = NULL;
 622         crash_disable_local_vmclear(cpu);
 623         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 624
 625         /*
 626          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
 627          * is before setting loaded_vmcs->vcpu to -1 which is done in
 628          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
 629          * then adds the vmcs into percpu list before it is deleted.
 630          */
 631         smp_wmb();
 632
 633         loaded_vmcs_init(loaded_vmcs);
 634         crash_enable_local_vmclear(cpu);
 635 }
 636
 637 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 638 {
 639         int cpu = loaded_vmcs->cpu;
 640
 641         if (cpu != -1)
 642                 smp_call_function_single(cpu,
 643                          __loaded_vmcs_clear, loaded_vmcs, 1);
 644 }
 645
 646 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 647                                        unsigned field)
 648 {
 649         bool ret;
 650         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 651
 652         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
 653                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
 654                 vmx->segment_cache.bitmask = 0;
 655         }
 656         ret = vmx->segment_cache.bitmask & mask;
 657         vmx->segment_cache.bitmask |= mask;
 658         return ret;
 659 }
 660
 661 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 662 {
 663         u16 *p = &vmx->segment_cache.seg[seg].selector;
 664
 665         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 666                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 667         return *p;
 668 }
 669
 670 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 671 {
 672         ulong *p = &vmx->segment_cache.seg[seg].base;
 673
 674         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 675                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 676         return *p;
 677 }
 678
 679 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 680 {
 681         u32 *p = &vmx->segment_cache.seg[seg].limit;
 682
 683         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 684                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 685         return *p;
 686 }
 687
 688 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 689 {
 690         u32 *p = &vmx->segment_cache.seg[seg].ar;
 691
 692         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 693                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 694         return *p;
 695 }
 696
 697 void update_exception_bitmap(struct kvm_vcpu *vcpu)
 698 {
 699         u32 eb;
 700
 701         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 702              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 703         /*
 704          * Guest access to VMware backdoor ports could legitimately
 705          * trigger #GP because of TSS I/O permission bitmap.
 706          * We intercept those #GP and allow access to them anyway
 707          * as VMware does.
 708          */
 709         if (enable_vmware_backdoor)
 710                 eb |= (1u << GP_VECTOR);
 711         if ((vcpu->guest_debug &
 712              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 713             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 714                 eb |= 1u << BP_VECTOR;
 715         if (to_vmx(vcpu)->rmode.vm86_active)
 716                 eb = ~0;
 717         if (enable_ept)
 718                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 719
 720         /* When we are running a nested L2 guest and L1 specified for it a
 721          * certain exception bitmap, we must trap the same exceptions and pass
 722          * them to L1. When running L2, we will only handle the exceptions
 723          * specified above if L1 did not want them.
 724          */
 725         if (is_guest_mode(vcpu))
 726                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 727
 728         vmcs_write32(EXCEPTION_BITMAP, eb);
 729 }
 730
 731 /*
 732  * Check if MSR is intercepted for currently loaded MSR bitmap.
 733  */
 734 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 735 {
 736         unsigned long *msr_bitmap;
 737         int f = sizeof(unsigned long);
 738
 739         if (!cpu_has_vmx_msr_bitmap())
 740                 return true;
 741
 742         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 743
 744         if (msr <= 0x1fff) {
 745                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 746         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 747                 msr &= 0x1fff;
 748                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 749         }
 750
 751         return true;
 752 }
 753
 754 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 755                 unsigned long entry, unsigned long exit)
 756 {
 757         vm_entry_controls_clearbit(vmx, entry);
 758         vm_exit_controls_clearbit(vmx, exit);
 759 }
 760
 761 static int find_msr(struct vmx_msrs *m, unsigned int msr)
 762 {
 763         unsigned int i;
 764
 765         for (i = 0; i < m->nr; ++i) {
 766                 if (m->val[i].index == msr)
 767                         return i;
 768         }
 769         return -ENOENT;
 770 }
 771
 772 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 773 {
 774         int i;
 775         struct msr_autoload *m = &vmx->msr_autoload;
 776
 777         switch (msr) {
 778         case MSR_EFER:
 779                 if (cpu_has_load_ia32_efer()) {
 780                         clear_atomic_switch_msr_special(vmx,
 781                                         VM_ENTRY_LOAD_IA32_EFER,
 782                                         VM_EXIT_LOAD_IA32_EFER);
 783                         return;
 784                 }
 785                 break;
 786         case MSR_CORE_PERF_GLOBAL_CTRL:
 787                 if (cpu_has_load_perf_global_ctrl()) {
 788                         clear_atomic_switch_msr_special(vmx,
 789                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 790                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 791                         return;
 792                 }
 793                 break;
 794         }
 795         i = find_msr(&m->guest, msr);
 796         if (i < 0)
 797                 goto skip_guest;
 798         --m->guest.nr;
 799         m->guest.val[i] = m->guest.val[m->guest.nr];
 800         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 801
 802 skip_guest:
 803         i = find_msr(&m->host, msr);
 804         if (i < 0)
 805                 return;
 806
 807         --m->host.nr;
 808         m->host.val[i] = m->host.val[m->host.nr];
 809         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 810 }
 811
 812 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 813                 unsigned long entry, unsigned long exit,
 814                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 815                 u64 guest_val, u64 host_val)
 816 {
 817         vmcs_write64(guest_val_vmcs, guest_val);
 818         if (host_val_vmcs != HOST_IA32_EFER)
 819                 vmcs_write64(host_val_vmcs, host_val);
 820         vm_entry_controls_setbit(vmx, entry);
 821         vm_exit_controls_setbit(vmx, exit);
 822 }
 823
 824 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 825                                   u64 guest_val, u64 host_val, bool entry_only)
 826 {
 827         int i, j = 0;
 828         struct msr_autoload *m = &vmx->msr_autoload;
 829
 830         switch (msr) {
 831         case MSR_EFER:
 832                 if (cpu_has_load_ia32_efer()) {
 833                         add_atomic_switch_msr_special(vmx,
 834                                         VM_ENTRY_LOAD_IA32_EFER,
 835                                         VM_EXIT_LOAD_IA32_EFER,
 836                                         GUEST_IA32_EFER,
 837                                         HOST_IA32_EFER,
 838                                         guest_val, host_val);
 839                         return;
 840                 }
 841                 break;
 842         case MSR_CORE_PERF_GLOBAL_CTRL:
 843                 if (cpu_has_load_perf_global_ctrl()) {
 844                         add_atomic_switch_msr_special(vmx,
 845                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 846                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 847                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 848                                         HOST_IA32_PERF_GLOBAL_CTRL,
 849                                         guest_val, host_val);
 850                         return;
 851                 }
 852                 break;
 853         case MSR_IA32_PEBS_ENABLE:
 854                 /* PEBS needs a quiescent period after being disabled (to write
 855                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 856                  * provide that period, so a CPU could write host's record into
 857                  * guest's memory.
 858                  */
 859                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 860         }
 861
 862         i = find_msr(&m->guest, msr);
 863         if (!entry_only)
 864                 j = find_msr(&m->host, msr);
 865
 866         if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
 867                 (j < 0 &&  m->host.nr == NR_AUTOLOAD_MSRS)) {
 868                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 869                                 "Can't add msr %x\n", msr);
 870                 return;
 871         }
 872         if (i < 0) {
 873                 i = m->guest.nr++;
 874                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 875         }
 876         m->guest.val[i].index = msr;
 877         m->guest.val[i].value = guest_val;
 878
 879         if (entry_only)
 880                 return;
 881
 882         if (j < 0) {
 883                 j = m->host.nr++;
 884                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 885         }
 886         m->host.val[j].index = msr;
 887         m->host.val[j].value = host_val;
 888 }
 889
 890 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 891 {
 892         u64 guest_efer = vmx->vcpu.arch.efer;
 893         u64 ignore_bits = 0;
 894
 895         if (!enable_ept) {
 896                 /*
 897                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
 898                  * host CPUID is more efficient than testing guest CPUID
 899                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
 900                  */
 901                 if (boot_cpu_has(X86_FEATURE_SMEP))
 902                         guest_efer |= EFER_NX;
 903                 else if (!(guest_efer & EFER_NX))
 904                         ignore_bits |= EFER_NX;
 905         }
 906
 907         /*
 908          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 909          */
 910         ignore_bits |= EFER_SCE;
 911 #ifdef CONFIG_X86_64
 912         ignore_bits |= EFER_LMA | EFER_LME;
 913         /* SCE is meaningful only in long mode on Intel */
 914         if (guest_efer & EFER_LMA)
 915                 ignore_bits &= ~(u64)EFER_SCE;
 916 #endif
 917
 918         /*
 919          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 920          * On CPUs that support "load IA32_EFER", always switch EFER
 921          * atomically, since it's faster than switching it manually.
 922          */
 923         if (cpu_has_load_ia32_efer() ||
 924             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 925                 if (!(guest_efer & EFER_LMA))
 926                         guest_efer &= ~EFER_LME;
 927                 if (guest_efer != host_efer)
 928                         add_atomic_switch_msr(vmx, MSR_EFER,
 929                                               guest_efer, host_efer, false);
 930                 else
 931                         clear_atomic_switch_msr(vmx, MSR_EFER);
 932                 return false;
 933         } else {
 934                 clear_atomic_switch_msr(vmx, MSR_EFER);
 935
 936                 guest_efer &= ~ignore_bits;
 937                 guest_efer |= host_efer & ignore_bits;
 938
 939                 vmx->guest_msrs[efer_offset].data = guest_efer;
 940                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 941
 942                 return true;
 943         }
 944 }
 945
 946 #ifdef CONFIG_X86_32
 947 /*
 948  * On 32-bit kernels, VM exits still load the FS and GS bases from the
 949  * VMCS rather than the segment table.  KVM uses this helper to figure
 950  * out the current bases to poke them into the VMCS before entry.
 951  */
 952 static unsigned long segment_base(u16 selector)
 953 {
 954         struct desc_struct *table;
 955         unsigned long v;
 956
 957         if (!(selector & ~SEGMENT_RPL_MASK))
 958                 return 0;
 959
 960         table = get_current_gdt_ro();
 961
 962         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
 963                 u16 ldt_selector = kvm_read_ldt();
 964
 965                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
 966                         return 0;
 967
 968                 table = (struct desc_struct *)segment_base(ldt_selector);
 969         }
 970         v = get_desc_base(&table[selector >> 3]);
 971         return v;
 972 }
 973 #endif
 974
 975 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
 976 {
 977         u32 i;
 978
 979         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
 980         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
 981         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
 982         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
 983         for (i = 0; i < addr_range; i++) {
 984                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
 985                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
 986         }
 987 }
 988
 989 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
 990 {
 991         u32 i;
 992
 993         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
 994         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
 995         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
 996         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
 997         for (i = 0; i < addr_range; i++) {
 998                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
 999                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1000         }
1001 }
1002
1003 static void pt_guest_enter(struct vcpu_vmx *vmx)
1004 {
1005         if (pt_mode == PT_MODE_SYSTEM)
1006                 return;
1007
1008         /*
1009          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1010          * Save host state before VM entry.
1011          */
1012         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1013         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1014                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1015                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1016                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1017         }
1018 }
1019
1020 static void pt_guest_exit(struct vcpu_vmx *vmx)
1021 {
1022         if (pt_mode == PT_MODE_SYSTEM)
1023                 return;
1024
1025         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1026                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1027                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1028         }
1029
1030         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1031         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1032 }
1033
1034 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1035 {
1036         struct vcpu_vmx *vmx = to_vmx(vcpu);
1037         struct vmcs_host_state *host_state;
1038 #ifdef CONFIG_X86_64
1039         int cpu = raw_smp_processor_id();
1040 #endif
1041         unsigned long fs_base, gs_base;
1042         u16 fs_sel, gs_sel;
1043         int i;
1044
1045         vmx->req_immediate_exit = false;
1046
1047         /*
1048          * Note that guest MSRs to be saved/restored can also be changed
1049          * when guest state is loaded. This happens when guest transitions
1050          * to/from long-mode by setting MSR_EFER.LMA.
1051          */
1052         if (!vmx->loaded_cpu_state || vmx->guest_msrs_dirty) {
1053                 vmx->guest_msrs_dirty = false;
1054                 for (i = 0; i < vmx->save_nmsrs; ++i)
1055                         kvm_set_shared_msr(vmx->guest_msrs[i].index,
1056                                            vmx->guest_msrs[i].data,
1057                                            vmx->guest_msrs[i].mask);
1058
1059         }
1060
1061         if (vmx->loaded_cpu_state)
1062                 return;
1063
1064         vmx->loaded_cpu_state = vmx->loaded_vmcs;
1065         host_state = &vmx->loaded_cpu_state->host_state;
1066
1067         /*
1068          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1069          * allow segment selectors with cpl > 0 or ti == 1.
1070          */
1071         host_state->ldt_sel = kvm_read_ldt();
1072
1073 #ifdef CONFIG_X86_64
1074         savesegment(ds, host_state->ds_sel);
1075         savesegment(es, host_state->es_sel);
1076
1077         gs_base = cpu_kernelmode_gs_base(cpu);
1078         if (likely(is_64bit_mm(current->mm))) {
1079                 save_fsgs_for_kvm();
1080                 fs_sel = current->thread.fsindex;
1081                 gs_sel = current->thread.gsindex;
1082                 fs_base = current->thread.fsbase;
1083                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1084         } else {
1085                 savesegment(fs, fs_sel);
1086                 savesegment(gs, gs_sel);
1087                 fs_base = read_msr(MSR_FS_BASE);
1088                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1089         }
1090
1091         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1092 #else
1093         savesegment(fs, fs_sel);
1094         savesegment(gs, gs_sel);
1095         fs_base = segment_base(fs_sel);
1096         gs_base = segment_base(gs_sel);
1097 #endif
1098
1099         if (unlikely(fs_sel != host_state->fs_sel)) {
1100                 if (!(fs_sel & 7))
1101                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1102                 else
1103                         vmcs_write16(HOST_FS_SELECTOR, 0);
1104                 host_state->fs_sel = fs_sel;
1105         }
1106         if (unlikely(gs_sel != host_state->gs_sel)) {
1107                 if (!(gs_sel & 7))
1108                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1109                 else
1110                         vmcs_write16(HOST_GS_SELECTOR, 0);
1111                 host_state->gs_sel = gs_sel;
1112         }
1113         if (unlikely(fs_base != host_state->fs_base)) {
1114                 vmcs_writel(HOST_FS_BASE, fs_base);
1115                 host_state->fs_base = fs_base;
1116         }
1117         if (unlikely(gs_base != host_state->gs_base)) {
1118                 vmcs_writel(HOST_GS_BASE, gs_base);
1119                 host_state->gs_base = gs_base;
1120         }
1121 }
1122
1123 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1124 {
1125         struct vmcs_host_state *host_state;
1126
1127         if (!vmx->loaded_cpu_state)
1128                 return;
1129
1130         WARN_ON_ONCE(vmx->loaded_cpu_state != vmx->loaded_vmcs);
1131         host_state = &vmx->loaded_cpu_state->host_state;
1132
1133         ++vmx->vcpu.stat.host_state_reload;
1134         vmx->loaded_cpu_state = NULL;
1135
1136 #ifdef CONFIG_X86_64
1137         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1138 #endif
1139         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1140                 kvm_load_ldt(host_state->ldt_sel);
1141 #ifdef CONFIG_X86_64
1142                 load_gs_index(host_state->gs_sel);
1143 #else
1144                 loadsegment(gs, host_state->gs_sel);
1145 #endif
1146         }
1147         if (host_state->fs_sel & 7)
1148                 loadsegment(fs, host_state->fs_sel);
1149 #ifdef CONFIG_X86_64
1150         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1151                 loadsegment(ds, host_state->ds_sel);
1152                 loadsegment(es, host_state->es_sel);
1153         }
1154 #endif
1155         invalidate_tss_limit();
1156 #ifdef CONFIG_X86_64
1157         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1158 #endif
1159         load_fixmap_gdt(raw_smp_processor_id());
1160 }
1161
1162 #ifdef CONFIG_X86_64
1163 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1164 {
1165         preempt_disable();
1166         if (vmx->loaded_cpu_state)
1167                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1168         preempt_enable();
1169         return vmx->msr_guest_kernel_gs_base;
1170 }
1171
1172 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1173 {
1174         preempt_disable();
1175         if (vmx->loaded_cpu_state)
1176                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1177         preempt_enable();
1178         vmx->msr_guest_kernel_gs_base = data;
1179 }
1180 #endif
1181
1182 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1183 {
1184         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1185         struct pi_desc old, new;
1186         unsigned int dest;
1187
1188         /*
1189          * In case of hot-plug or hot-unplug, we may have to undo
1190          * vmx_vcpu_pi_put even if there is no assigned device.  And we
1191          * always keep PI.NDST up to date for simplicity: it makes the
1192          * code easier, and CPU migration is not a fast path.
1193          */
1194         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1195                 return;
1196
1197         /* The full case.  */
1198         do {
1199                 old.control = new.control = pi_desc->control;
1200
1201                 dest = cpu_physical_id(cpu);
1202
1203                 if (x2apic_enabled())
1204                         new.ndst = dest;
1205                 else
1206                         new.ndst = (dest << 8) & 0xFF00;
1207
1208                 new.sn = 0;
1209         } while (cmpxchg64(&pi_desc->control, old.control,
1210                            new.control) != old.control);
1211
1212         /*
1213          * Clear SN before reading the bitmap.  The VT-d firmware
1214          * writes the bitmap and reads SN atomically (5.2.3 in the
1215          * spec), so it doesn't really have a memory barrier that
1216          * pairs with this, but we cannot do that and we need one.
1217          */
1218         smp_mb__after_atomic();
1219
1220         if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
1221                 pi_set_on(pi_desc);
1222 }
1223
1224 /*
1225  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1226  * vcpu mutex is already taken.
1227  */
1228 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1229 {
1230         struct vcpu_vmx *vmx = to_vmx(vcpu);
1231         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1232
1233         if (!already_loaded) {
1234                 loaded_vmcs_clear(vmx->loaded_vmcs);
1235                 local_irq_disable();
1236                 crash_disable_local_vmclear(cpu);
1237
1238                 /*
1239                  * Read loaded_vmcs->cpu should be before fetching
1240                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1241                  * See the comments in __loaded_vmcs_clear().
1242                  */
1243                 smp_rmb();
1244
1245                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1246                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1247                 crash_enable_local_vmclear(cpu);
1248                 local_irq_enable();
1249         }
1250
1251         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1252                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1253                 vmcs_load(vmx->loaded_vmcs->vmcs);
1254                 indirect_branch_prediction_barrier();
1255         }
1256
1257         if (!already_loaded) {
1258                 void *gdt = get_current_gdt_ro();
1259                 unsigned long sysenter_esp;
1260
1261                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1262
1263                 /*
1264                  * Linux uses per-cpu TSS and GDT, so set these when switching
1265                  * processors.  See 22.2.4.
1266                  */
1267                 vmcs_writel(HOST_TR_BASE,
1268                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1269                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1270
1271                 /*
1272                  * VM exits change the host TR limit to 0x67 after a VM
1273                  * exit.  This is okay, since 0x67 covers everything except
1274                  * the IO bitmap and have have code to handle the IO bitmap
1275                  * being lost after a VM exit.
1276                  */
1277                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1278
1279                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1280                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1281
1282                 vmx->loaded_vmcs->cpu = cpu;
1283         }
1284
1285         /* Setup TSC multiplier */
1286         if (kvm_has_tsc_control &&
1287             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1288                 decache_tsc_multiplier(vmx);
1289
1290         vmx_vcpu_pi_load(vcpu, cpu);
1291         vmx->host_pkru = read_pkru();
1292         vmx->host_debugctlmsr = get_debugctlmsr();
1293 }
1294
1295 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1296 {
1297         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1298
1299         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1300                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
1301                 !kvm_vcpu_apicv_active(vcpu))
1302                 return;
1303
1304         /* Set SN when the vCPU is preempted */
1305         if (vcpu->preempted)
1306                 pi_set_sn(pi_desc);
1307 }
1308
1309 void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1310 {
1311         vmx_vcpu_pi_put(vcpu);
1312
1313         vmx_prepare_switch_to_host(to_vmx(vcpu));
1314 }
1315
1316 static bool emulation_required(struct kvm_vcpu *vcpu)
1317 {
1318         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1319 }
1320
1321 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1322
1323 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1324 {
1325         unsigned long rflags, save_rflags;
1326
1327         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1328                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1329                 rflags = vmcs_readl(GUEST_RFLAGS);
1330                 if (to_vmx(vcpu)->rmode.vm86_active) {
1331                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1332                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1333                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1334                 }
1335                 to_vmx(vcpu)->rflags = rflags;
1336         }
1337         return to_vmx(vcpu)->rflags;
1338 }
1339
1340 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1341 {
1342         unsigned long old_rflags = vmx_get_rflags(vcpu);
1343
1344         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1345         to_vmx(vcpu)->rflags = rflags;
1346         if (to_vmx(vcpu)->rmode.vm86_active) {
1347                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1348                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1349         }
1350         vmcs_writel(GUEST_RFLAGS, rflags);
1351
1352         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1353                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
1354 }
1355
1356 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1357 {
1358         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1359         int ret = 0;
1360
1361         if (interruptibility & GUEST_INTR_STATE_STI)
1362                 ret |= KVM_X86_SHADOW_INT_STI;
1363         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1364                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1365
1366         return ret;
1367 }
1368
1369 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1370 {
1371         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1372         u32 interruptibility = interruptibility_old;
1373
1374         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1375
1376         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1377                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1378         else if (mask & KVM_X86_SHADOW_INT_STI)
1379                 interruptibility |= GUEST_INTR_STATE_STI;
1380
1381         if ((interruptibility != interruptibility_old))
1382                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1383 }
1384
1385 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1386 {
1387         struct vcpu_vmx *vmx = to_vmx(vcpu);
1388         unsigned long value;
1389
1390         /*
1391          * Any MSR write that attempts to change bits marked reserved will
1392          * case a #GP fault.
1393          */
1394         if (data & vmx->pt_desc.ctl_bitmask)
1395                 return 1;
1396
1397         /*
1398          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1399          * result in a #GP unless the same write also clears TraceEn.
1400          */
1401         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1402                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1403                 return 1;
1404
1405         /*
1406          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1407          * and FabricEn would cause #GP, if
1408          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1409          */
1410         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1411                 !(data & RTIT_CTL_FABRIC_EN) &&
1412                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1413                                         PT_CAP_single_range_output))
1414                 return 1;
1415
1416         /*
1417          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1418          * utilize encodings marked reserved will casue a #GP fault.
1419          */
1420         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1421         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1422                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1423                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1424                 return 1;
1425         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1426                                                 PT_CAP_cycle_thresholds);
1427         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1428                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1429                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1430                 return 1;
1431         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1432         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1433                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1434                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1435                 return 1;
1436
1437         /*
1438          * If ADDRx_CFG is reserved or the encodings is >2 will
1439          * cause a #GP fault.
1440          */
1441         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1442         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1443                 return 1;
1444         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1445         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1446                 return 1;
1447         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1448         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1449                 return 1;
1450         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1451         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1452                 return 1;
1453
1454         return 0;
1455 }
1456
1457
1458 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1459 {
1460         unsigned long rip;
1461
1462         rip = kvm_rip_read(vcpu);
1463         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1464         kvm_rip_write(vcpu, rip);
1465
1466         /* skipping an emulated instruction also counts */
1467         vmx_set_interrupt_shadow(vcpu, 0);
1468 }
1469
1470 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1471 {
1472         /*
1473          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1474          * explicitly skip the instruction because if the HLT state is set,
1475          * then the instruction is already executing and RIP has already been
1476          * advanced.
1477          */
1478         if (kvm_hlt_in_guest(vcpu->kvm) &&
1479                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1480                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1481 }
1482
1483 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1484 {
1485         struct vcpu_vmx *vmx = to_vmx(vcpu);
1486         unsigned nr = vcpu->arch.exception.nr;
1487         bool has_error_code = vcpu->arch.exception.has_error_code;
1488         u32 error_code = vcpu->arch.exception.error_code;
1489         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1490
1491         kvm_deliver_exception_payload(vcpu);
1492
1493         if (has_error_code) {
1494                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1495                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1496         }
1497
1498         if (vmx->rmode.vm86_active) {
1499                 int inc_eip = 0;
1500                 if (kvm_exception_is_soft(nr))
1501                         inc_eip = vcpu->arch.event_exit_inst_len;
1502                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1503                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1504                 return;
1505         }
1506
1507         WARN_ON_ONCE(vmx->emulation_required);
1508
1509         if (kvm_exception_is_soft(nr)) {
1510                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1511                              vmx->vcpu.arch.event_exit_inst_len);
1512                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1513         } else
1514                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1515
1516         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1517
1518         vmx_clear_hlt(vcpu);
1519 }
1520
1521 static bool vmx_rdtscp_supported(void)
1522 {
1523         return cpu_has_vmx_rdtscp();
1524 }
1525
1526 static bool vmx_invpcid_supported(void)
1527 {
1528         return cpu_has_vmx_invpcid();
1529 }
1530
1531 /*
1532  * Swap MSR entry in host/guest MSR entry array.
1533  */
1534 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1535 {
1536         struct shared_msr_entry tmp;
1537
1538         tmp = vmx->guest_msrs[to];
1539         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1540         vmx->guest_msrs[from] = tmp;
1541 }
1542
1543 /*
1544  * Set up the vmcs to automatically save and restore system
1545  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1546  * mode, as fiddling with msrs is very expensive.
1547  */
1548 static void setup_msrs(struct vcpu_vmx *vmx)
1549 {
1550         int save_nmsrs, index;
1551
1552         save_nmsrs = 0;
1553 #ifdef CONFIG_X86_64
1554         /*
1555          * The SYSCALL MSRs are only needed on long mode guests, and only
1556          * when EFER.SCE is set.
1557          */
1558         if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1559                 index = __find_msr_index(vmx, MSR_STAR);
1560                 if (index >= 0)
1561                         move_msr_up(vmx, index, save_nmsrs++);
1562                 index = __find_msr_index(vmx, MSR_LSTAR);
1563                 if (index >= 0)
1564                         move_msr_up(vmx, index, save_nmsrs++);
1565                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1566                 if (index >= 0)
1567                         move_msr_up(vmx, index, save_nmsrs++);
1568         }
1569 #endif
1570         index = __find_msr_index(vmx, MSR_EFER);
1571         if (index >= 0 && update_transition_efer(vmx, index))
1572                 move_msr_up(vmx, index, save_nmsrs++);
1573         index = __find_msr_index(vmx, MSR_TSC_AUX);
1574         if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1575                 move_msr_up(vmx, index, save_nmsrs++);
1576
1577         vmx->save_nmsrs = save_nmsrs;
1578         vmx->guest_msrs_dirty = true;
1579
1580         if (cpu_has_vmx_msr_bitmap())
1581                 vmx_update_msr_bitmap(&vmx->vcpu);
1582 }
1583
1584 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1585 {
1586         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1587
1588         if (is_guest_mode(vcpu) &&
1589             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1590                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1591
1592         return vcpu->arch.tsc_offset;
1593 }
1594
1595 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1596 {
1597         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1598         u64 g_tsc_offset = 0;
1599
1600         /*
1601          * We're here if L1 chose not to trap WRMSR to TSC. According
1602          * to the spec, this should set L1's TSC; The offset that L1
1603          * set for L2 remains unchanged, and still needs to be added
1604          * to the newly set TSC to get L2's TSC.
1605          */
1606         if (is_guest_mode(vcpu) &&
1607             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1608                 g_tsc_offset = vmcs12->tsc_offset;
1609
1610         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1611                                    vcpu->arch.tsc_offset - g_tsc_offset,
1612                                    offset);
1613         vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1614         return offset + g_tsc_offset;
1615 }
1616
1617 /*
1618  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1619  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1620  * all guests if the "nested" module option is off, and can also be disabled
1621  * for a single guest by disabling its VMX cpuid bit.
1622  */
1623 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1624 {
1625         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1626 }
1627
1628 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1629                                                  uint64_t val)
1630 {
1631         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1632
1633         return !(val & ~valid_bits);
1634 }
1635
1636 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1637 {
1638         switch (msr->index) {
1639         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1640                 if (!nested)
1641                         return 1;
1642                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1643         default:
1644                 return 1;
1645         }
1646
1647         return 0;
1648 }
1649
1650 /*
1651  * Reads an msr value (of 'msr_index') into 'pdata'.
1652  * Returns 0 on success, non-0 otherwise.
1653  * Assumes vcpu_load() was already called.
1654  */
1655 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1656 {
1657         struct vcpu_vmx *vmx = to_vmx(vcpu);
1658         struct shared_msr_entry *msr;
1659         u32 index;
1660
1661         switch (msr_info->index) {
1662 #ifdef CONFIG_X86_64
1663         case MSR_FS_BASE:
1664                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1665                 break;
1666         case MSR_GS_BASE:
1667                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1668                 break;
1669         case MSR_KERNEL_GS_BASE:
1670                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1671                 break;
1672 #endif
1673         case MSR_EFER:
1674                 return kvm_get_msr_common(vcpu, msr_info);
1675         case MSR_IA32_SPEC_CTRL:
1676                 if (!msr_info->host_initiated &&
1677                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1678                         return 1;
1679
1680                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1681                 break;
1682         case MSR_IA32_ARCH_CAPABILITIES:
1683                 if (!msr_info->host_initiated &&
1684                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
1685                         return 1;
1686                 msr_info->data = to_vmx(vcpu)->arch_capabilities;
1687                 break;
1688         case MSR_IA32_SYSENTER_CS:
1689                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1690                 break;
1691         case MSR_IA32_SYSENTER_EIP:
1692                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1693                 break;
1694         case MSR_IA32_SYSENTER_ESP:
1695                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1696                 break;
1697         case MSR_IA32_BNDCFGS:
1698                 if (!kvm_mpx_supported() ||
1699                     (!msr_info->host_initiated &&
1700                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1701                         return 1;
1702                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1703                 break;
1704         case MSR_IA32_MCG_EXT_CTL:
1705                 if (!msr_info->host_initiated &&
1706                     !(vmx->msr_ia32_feature_control &
1707                       FEATURE_CONTROL_LMCE))
1708                         return 1;
1709                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1710                 break;
1711         case MSR_IA32_FEATURE_CONTROL:
1712                 msr_info->data = vmx->msr_ia32_feature_control;
1713                 break;
1714         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1715                 if (!nested_vmx_allowed(vcpu))
1716                         return 1;
1717                 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1718                                        &msr_info->data);
1719         case MSR_IA32_XSS:
1720                 if (!vmx_xsaves_supported())
1721                         return 1;
1722                 msr_info->data = vcpu->arch.ia32_xss;
1723                 break;
1724         case MSR_IA32_RTIT_CTL:
1725                 if (pt_mode != PT_MODE_HOST_GUEST)
1726                         return 1;
1727                 msr_info->data = vmx->pt_desc.guest.ctl;
1728                 break;
1729         case MSR_IA32_RTIT_STATUS:
1730                 if (pt_mode != PT_MODE_HOST_GUEST)
1731                         return 1;
1732                 msr_info->data = vmx->pt_desc.guest.status;
1733                 break;
1734         case MSR_IA32_RTIT_CR3_MATCH:
1735                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1736                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1737                                                 PT_CAP_cr3_filtering))
1738                         return 1;
1739                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1740                 break;
1741         case MSR_IA32_RTIT_OUTPUT_BASE:
1742                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1743                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1744                                         PT_CAP_topa_output) &&
1745                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1746                                         PT_CAP_single_range_output)))
1747                         return 1;
1748                 msr_info->data = vmx->pt_desc.guest.output_base;
1749                 break;
1750         case MSR_IA32_RTIT_OUTPUT_MASK:
1751                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1752                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1753                                         PT_CAP_topa_output) &&
1754                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1755                                         PT_CAP_single_range_output)))
1756                         return 1;
1757                 msr_info->data = vmx->pt_desc.guest.output_mask;
1758                 break;
1759         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1760                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1761                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1762                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1763                                         PT_CAP_num_address_ranges)))
1764                         return 1;
1765                 if (index % 2)
1766                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1767                 else
1768                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1769                 break;
1770         case MSR_TSC_AUX:
1771                 if (!msr_info->host_initiated &&
1772                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1773                         return 1;
1774                 /* Else, falls through */
1775         default:
1776                 msr = find_msr_entry(vmx, msr_info->index);
1777                 if (msr) {
1778                         msr_info->data = msr->data;
1779                         break;
1780                 }
1781                 return kvm_get_msr_common(vcpu, msr_info);
1782         }
1783
1784         return 0;
1785 }
1786
1787 /*
1788  * Writes msr value into into the appropriate "register".
1789  * Returns 0 on success, non-0 otherwise.
1790  * Assumes vcpu_load() was already called.
1791  */
1792 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1793 {
1794         struct vcpu_vmx *vmx = to_vmx(vcpu);
1795         struct shared_msr_entry *msr;
1796         int ret = 0;
1797         u32 msr_index = msr_info->index;
1798         u64 data = msr_info->data;
1799         u32 index;
1800
1801         switch (msr_index) {
1802         case MSR_EFER:
1803                 ret = kvm_set_msr_common(vcpu, msr_info);
1804                 break;
1805 #ifdef CONFIG_X86_64
1806         case MSR_FS_BASE:
1807                 vmx_segment_cache_clear(vmx);
1808                 vmcs_writel(GUEST_FS_BASE, data);
1809                 break;
1810         case MSR_GS_BASE:
1811                 vmx_segment_cache_clear(vmx);
1812                 vmcs_writel(GUEST_GS_BASE, data);
1813                 break;
1814         case MSR_KERNEL_GS_BASE:
1815                 vmx_write_guest_kernel_gs_base(vmx, data);
1816                 break;
1817 #endif
1818         case MSR_IA32_SYSENTER_CS:
1819                 vmcs_write32(GUEST_SYSENTER_CS, data);
1820                 break;
1821         case MSR_IA32_SYSENTER_EIP:
1822                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1823                 break;
1824         case MSR_IA32_SYSENTER_ESP:
1825                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1826                 break;
1827         case MSR_IA32_BNDCFGS:
1828                 if (!kvm_mpx_supported() ||
1829                     (!msr_info->host_initiated &&
1830                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1831                         return 1;
1832                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1833                     (data & MSR_IA32_BNDCFGS_RSVD))
1834                         return 1;
1835                 vmcs_write64(GUEST_BNDCFGS, data);
1836                 break;
1837         case MSR_IA32_SPEC_CTRL:
1838                 if (!msr_info->host_initiated &&
1839                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1840                         return 1;
1841
1842                 /* The STIBP bit doesn't fault even if it's not advertised */
1843                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
1844                         return 1;
1845
1846                 vmx->spec_ctrl = data;
1847
1848                 if (!data)
1849                         break;
1850
1851                 /*
1852                  * For non-nested:
1853                  * When it's written (to non-zero) for the first time, pass
1854                  * it through.
1855                  *
1856                  * For nested:
1857                  * The handling of the MSR bitmap for L2 guests is done in
1858                  * nested_vmx_merge_msr_bitmap. We should not touch the
1859                  * vmcs02.msr_bitmap here since it gets completely overwritten
1860                  * in the merging. We update the vmcs01 here for L1 as well
1861                  * since it will end up touching the MSR anyway now.
1862                  */
1863                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
1864                                               MSR_IA32_SPEC_CTRL,
1865                                               MSR_TYPE_RW);
1866                 break;
1867         case MSR_IA32_PRED_CMD:
1868                 if (!msr_info->host_initiated &&
1869                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1870                         return 1;
1871
1872                 if (data & ~PRED_CMD_IBPB)
1873                         return 1;
1874
1875                 if (!data)
1876                         break;
1877
1878                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
1879
1880                 /*
1881                  * For non-nested:
1882                  * When it's written (to non-zero) for the first time, pass
1883                  * it through.
1884                  *
1885                  * For nested:
1886                  * The handling of the MSR bitmap for L2 guests is done in
1887                  * nested_vmx_merge_msr_bitmap. We should not touch the
1888                  * vmcs02.msr_bitmap here since it gets completely overwritten
1889                  * in the merging.
1890                  */
1891                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
1892                                               MSR_TYPE_W);
1893                 break;
1894         case MSR_IA32_ARCH_CAPABILITIES:
1895                 if (!msr_info->host_initiated)
1896                         return 1;
1897                 vmx->arch_capabilities = data;
1898                 break;
1899         case MSR_IA32_CR_PAT:
1900                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1901                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
1902                                 return 1;
1903                         vmcs_write64(GUEST_IA32_PAT, data);
1904                         vcpu->arch.pat = data;
1905                         break;
1906                 }
1907                 ret = kvm_set_msr_common(vcpu, msr_info);
1908                 break;
1909         case MSR_IA32_TSC_ADJUST:
1910                 ret = kvm_set_msr_common(vcpu, msr_info);
1911                 break;
1912         case MSR_IA32_MCG_EXT_CTL:
1913                 if ((!msr_info->host_initiated &&
1914                      !(to_vmx(vcpu)->msr_ia32_feature_control &
1915                        FEATURE_CONTROL_LMCE)) ||
1916                     (data & ~MCG_EXT_CTL_LMCE_EN))
1917                         return 1;
1918                 vcpu->arch.mcg_ext_ctl = data;
1919                 break;
1920         case MSR_IA32_FEATURE_CONTROL:
1921                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
1922                     (to_vmx(vcpu)->msr_ia32_feature_control &
1923                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
1924                         return 1;
1925                 vmx->msr_ia32_feature_control = data;
1926                 if (msr_info->host_initiated && data == 0)
1927                         vmx_leave_nested(vcpu);
1928                 break;
1929         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1930                 if (!msr_info->host_initiated)
1931                         return 1; /* they are read-only */
1932                 if (!nested_vmx_allowed(vcpu))
1933                         return 1;
1934                 return vmx_set_vmx_msr(vcpu, msr_index, data);
1935         case MSR_IA32_XSS:
1936                 if (!vmx_xsaves_supported())
1937                         return 1;
1938                 /*
1939                  * The only supported bit as of Skylake is bit 8, but
1940                  * it is not supported on KVM.
1941                  */
1942                 if (data != 0)
1943                         return 1;
1944                 vcpu->arch.ia32_xss = data;
1945                 if (vcpu->arch.ia32_xss != host_xss)
1946                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
1947                                 vcpu->arch.ia32_xss, host_xss, false);
1948                 else
1949                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
1950                 break;
1951         case MSR_IA32_RTIT_CTL:
1952                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1953                         vmx_rtit_ctl_check(vcpu, data) ||
1954                         vmx->nested.vmxon)
1955                         return 1;
1956                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
1957                 vmx->pt_desc.guest.ctl = data;
1958                 pt_update_intercept_for_msr(vmx);
1959                 break;
1960         case MSR_IA32_RTIT_STATUS:
1961                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1962                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1963                         (data & MSR_IA32_RTIT_STATUS_MASK))
1964                         return 1;
1965                 vmx->pt_desc.guest.status = data;
1966                 break;
1967         case MSR_IA32_RTIT_CR3_MATCH:
1968                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1969                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1970                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1971                                                 PT_CAP_cr3_filtering))
1972                         return 1;
1973                 vmx->pt_desc.guest.cr3_match = data;
1974                 break;
1975         case MSR_IA32_RTIT_OUTPUT_BASE:
1976                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1977                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1978                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1979                                         PT_CAP_topa_output) &&
1980                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1981                                         PT_CAP_single_range_output)) ||
1982                         (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
1983                         return 1;
1984                 vmx->pt_desc.guest.output_base = data;
1985                 break;
1986         case MSR_IA32_RTIT_OUTPUT_MASK:
1987                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1988                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1989                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1990                                         PT_CAP_topa_output) &&
1991                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1992                                         PT_CAP_single_range_output)))
1993                         return 1;
1994                 vmx->pt_desc.guest.output_mask = data;
1995                 break;
1996         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1997                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1998                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1999                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2000                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2001                                         PT_CAP_num_address_ranges)))
2002                         return 1;
2003                 if (index % 2)
2004                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2005                 else
2006                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2007                 break;
2008         case MSR_TSC_AUX:
2009                 if (!msr_info->host_initiated &&
2010                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2011                         return 1;
2012                 /* Check reserved bit, higher 32 bits should be zero */
2013                 if ((data >> 32) != 0)
2014                         return 1;
2015                 /* Else, falls through */
2016         default:
2017                 msr = find_msr_entry(vmx, msr_index);
2018                 if (msr) {
2019                         u64 old_msr_data = msr->data;
2020                         msr->data = data;
2021                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2022                                 preempt_disable();
2023                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2024                                                          msr->mask);
2025                                 preempt_enable();
2026                                 if (ret)
2027                                         msr->data = old_msr_data;
2028                         }
2029                         break;
2030                 }
2031                 ret = kvm_set_msr_common(vcpu, msr_info);
2032         }
2033
2034         return ret;
2035 }
2036
2037 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2038 {
2039         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2040         switch (reg) {
2041         case VCPU_REGS_RSP:
2042                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2043                 break;
2044         case VCPU_REGS_RIP:
2045                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2046                 break;
2047         case VCPU_EXREG_PDPTR:
2048                 if (enable_ept)
2049                         ept_save_pdptrs(vcpu);
2050                 break;
2051         default:
2052                 break;
2053         }
2054 }
2055
2056 static __init int cpu_has_kvm_support(void)
2057 {
2058         return cpu_has_vmx();
2059 }
2060
2061 static __init int vmx_disabled_by_bios(void)
2062 {
2063         u64 msr;
2064
2065         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2066         if (msr & FEATURE_CONTROL_LOCKED) {
2067                 /* launched w/ TXT and VMX disabled */
2068                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2069                         && tboot_enabled())
2070                         return 1;
2071                 /* launched w/o TXT and VMX only enabled w/ TXT */
2072                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2073                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2074                         && !tboot_enabled()) {
2075                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2076                                 "activate TXT before enabling KVM\n");
2077                         return 1;
2078                 }
2079                 /* launched w/o TXT and VMX disabled */
2080                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2081                         && !tboot_enabled())
2082                         return 1;
2083         }
2084
2085         return 0;
2086 }
2087
2088 static void kvm_cpu_vmxon(u64 addr)
2089 {
2090         cr4_set_bits(X86_CR4_VMXE);
2091         intel_pt_handle_vmx(1);
2092
2093         asm volatile ("vmxon %0" : : "m"(addr));
2094 }
2095
2096 static int hardware_enable(void)
2097 {
2098         int cpu = raw_smp_processor_id();
2099         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2100         u64 old, test_bits;
2101
2102         if (cr4_read_shadow() & X86_CR4_VMXE)
2103                 return -EBUSY;
2104
2105         /*
2106          * This can happen if we hot-added a CPU but failed to allocate
2107          * VP assist page for it.
2108          */
2109         if (static_branch_unlikely(&enable_evmcs) &&
2110             !hv_get_vp_assist_page(cpu))
2111                 return -EFAULT;
2112
2113         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2114         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2115         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2116
2117         /*
2118          * Now we can enable the vmclear operation in kdump
2119          * since the loaded_vmcss_on_cpu list on this cpu
2120          * has been initialized.
2121          *
2122          * Though the cpu is not in VMX operation now, there
2123          * is no problem to enable the vmclear operation
2124          * for the loaded_vmcss_on_cpu list is empty!
2125          */
2126         crash_enable_local_vmclear(cpu);
2127
2128         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2129
2130         test_bits = FEATURE_CONTROL_LOCKED;
2131         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2132         if (tboot_enabled())
2133                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2134
2135         if ((old & test_bits) != test_bits) {
2136                 /* enable and lock */
2137                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2138         }
2139         kvm_cpu_vmxon(phys_addr);
2140         if (enable_ept)
2141                 ept_sync_global();
2142
2143         return 0;
2144 }
2145
2146 static void vmclear_local_loaded_vmcss(void)
2147 {
2148         int cpu = raw_smp_processor_id();
2149         struct loaded_vmcs *v, *n;
2150
2151         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2152                                  loaded_vmcss_on_cpu_link)
2153                 __loaded_vmcs_clear(v);
2154 }
2155
2156
2157 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2158  * tricks.
2159  */
2160 static void kvm_cpu_vmxoff(void)
2161 {
2162         asm volatile (__ex("vmxoff"));
2163
2164         intel_pt_handle_vmx(0);
2165         cr4_clear_bits(X86_CR4_VMXE);
2166 }
2167
2168 static void hardware_disable(void)
2169 {
2170         vmclear_local_loaded_vmcss();
2171         kvm_cpu_vmxoff();
2172 }
2173
2174 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2175                                       u32 msr, u32 *result)
2176 {
2177         u32 vmx_msr_low, vmx_msr_high;
2178         u32 ctl = ctl_min | ctl_opt;
2179
2180         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2181
2182         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2183         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2184
2185         /* Ensure minimum (required) set of control bits are supported. */
2186         if (ctl_min & ~ctl)
2187                 return -EIO;
2188
2189         *result = ctl;
2190         return 0;
2191 }
2192
2193 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2194                                     struct vmx_capability *vmx_cap)
2195 {
2196         u32 vmx_msr_low, vmx_msr_high;
2197         u32 min, opt, min2, opt2;
2198         u32 _pin_based_exec_control = 0;
2199         u32 _cpu_based_exec_control = 0;
2200         u32 _cpu_based_2nd_exec_control = 0;
2201         u32 _vmexit_control = 0;
2202         u32 _vmentry_control = 0;
2203
2204         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2205         min = CPU_BASED_HLT_EXITING |
2206 #ifdef CONFIG_X86_64
2207               CPU_BASED_CR8_LOAD_EXITING |
2208               CPU_BASED_CR8_STORE_EXITING |
2209 #endif
2210               CPU_BASED_CR3_LOAD_EXITING |
2211               CPU_BASED_CR3_STORE_EXITING |
2212               CPU_BASED_UNCOND_IO_EXITING |
2213               CPU_BASED_MOV_DR_EXITING |
2214               CPU_BASED_USE_TSC_OFFSETING |
2215               CPU_BASED_MWAIT_EXITING |
2216               CPU_BASED_MONITOR_EXITING |
2217               CPU_BASED_INVLPG_EXITING |
2218               CPU_BASED_RDPMC_EXITING;
2219
2220         opt = CPU_BASED_TPR_SHADOW |
2221               CPU_BASED_USE_MSR_BITMAPS |
2222               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2223         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2224                                 &_cpu_based_exec_control) < 0)
2225                 return -EIO;
2226 #ifdef CONFIG_X86_64
2227         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2228                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2229                                            ~CPU_BASED_CR8_STORE_EXITING;
2230 #endif
2231         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2232                 min2 = 0;
2233                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2234                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2235                         SECONDARY_EXEC_WBINVD_EXITING |
2236                         SECONDARY_EXEC_ENABLE_VPID |
2237                         SECONDARY_EXEC_ENABLE_EPT |
2238                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2239                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2240                         SECONDARY_EXEC_DESC |
2241                         SECONDARY_EXEC_RDTSCP |
2242                         SECONDARY_EXEC_ENABLE_INVPCID |
2243                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2244                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2245                         SECONDARY_EXEC_SHADOW_VMCS |
2246                         SECONDARY_EXEC_XSAVES |
2247                         SECONDARY_EXEC_RDSEED_EXITING |
2248                         SECONDARY_EXEC_RDRAND_EXITING |
2249                         SECONDARY_EXEC_ENABLE_PML |
2250                         SECONDARY_EXEC_TSC_SCALING |
2251                         SECONDARY_EXEC_PT_USE_GPA |
2252                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2253                         SECONDARY_EXEC_ENABLE_VMFUNC |
2254                         SECONDARY_EXEC_ENCLS_EXITING;
2255                 if (adjust_vmx_controls(min2, opt2,
2256                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2257                                         &_cpu_based_2nd_exec_control) < 0)
2258                         return -EIO;
2259         }
2260 #ifndef CONFIG_X86_64
2261         if (!(_cpu_based_2nd_exec_control &
2262                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2263                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2264 #endif
2265
2266         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2267                 _cpu_based_2nd_exec_control &= ~(
2268                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2269                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2270                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2271
2272         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2273                 &vmx_cap->ept, &vmx_cap->vpid);
2274
2275         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2276                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2277                    enabled */
2278                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2279                                              CPU_BASED_CR3_STORE_EXITING |
2280                                              CPU_BASED_INVLPG_EXITING);
2281         } else if (vmx_cap->ept) {
2282                 vmx_cap->ept = 0;
2283                 pr_warn_once("EPT CAP should not exist if not support "
2284                                 "1-setting enable EPT VM-execution control\n");
2285         }
2286         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2287                 vmx_cap->vpid) {
2288                 vmx_cap->vpid = 0;
2289                 pr_warn_once("VPID CAP should not exist if not support "
2290                                 "1-setting enable VPID VM-execution control\n");
2291         }
2292
2293         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2294 #ifdef CONFIG_X86_64
2295         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2296 #endif
2297         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2298               VM_EXIT_SAVE_IA32_PAT |
2299               VM_EXIT_LOAD_IA32_PAT |
2300               VM_EXIT_LOAD_IA32_EFER |
2301               VM_EXIT_CLEAR_BNDCFGS |
2302               VM_EXIT_PT_CONCEAL_PIP |
2303               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2304         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2305                                 &_vmexit_control) < 0)
2306                 return -EIO;
2307
2308         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2309         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2310                  PIN_BASED_VMX_PREEMPTION_TIMER;
2311         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2312                                 &_pin_based_exec_control) < 0)
2313                 return -EIO;
2314
2315         if (cpu_has_broken_vmx_preemption_timer())
2316                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2317         if (!(_cpu_based_2nd_exec_control &
2318                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2319                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2320
2321         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2322         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2323               VM_ENTRY_LOAD_IA32_PAT |
2324               VM_ENTRY_LOAD_IA32_EFER |
2325               VM_ENTRY_LOAD_BNDCFGS |
2326               VM_ENTRY_PT_CONCEAL_PIP |
2327               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2328         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2329                                 &_vmentry_control) < 0)
2330                 return -EIO;
2331
2332         /*
2333          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2334          * can't be used due to an errata where VM Exit may incorrectly clear
2335          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2336          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2337          */
2338         if (boot_cpu_data.x86 == 0x6) {
2339                 switch (boot_cpu_data.x86_model) {
2340                 case 26: /* AAK155 */
2341                 case 30: /* AAP115 */
2342                 case 37: /* AAT100 */
2343                 case 44: /* BC86,AAY89,BD102 */
2344                 case 46: /* BA97 */
2345                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2346                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2347                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2348                                         "does not work properly. Using workaround\n");
2349                         break;
2350                 default:
2351                         break;
2352                 }
2353         }
2354
2355
2356         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2357
2358         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2359         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2360                 return -EIO;
2361
2362 #ifdef CONFIG_X86_64
2363         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2364         if (vmx_msr_high & (1u<<16))
2365                 return -EIO;
2366 #endif
2367
2368         /* Require Write-Back (WB) memory type for VMCS accesses. */
2369         if (((vmx_msr_high >> 18) & 15) != 6)
2370                 return -EIO;
2371
2372         vmcs_conf->size = vmx_msr_high & 0x1fff;
2373         vmcs_conf->order = get_order(vmcs_conf->size);
2374         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2375
2376         vmcs_conf->revision_id = vmx_msr_low;
2377
2378         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2379         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2380         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2381         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2382         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2383
2384         if (static_branch_unlikely(&enable_evmcs))
2385                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2386
2387         return 0;
2388 }
2389
2390 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu)
2391 {
2392         int node = cpu_to_node(cpu);
2393         struct page *pages;
2394         struct vmcs *vmcs;
2395
2396         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
2397         if (!pages)
2398                 return NULL;
2399         vmcs = page_address(pages);
2400         memset(vmcs, 0, vmcs_config.size);
2401
2402         /* KVM supports Enlightened VMCS v1 only */
2403         if (static_branch_unlikely(&enable_evmcs))
2404                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2405         else
2406                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2407
2408         if (shadow)
2409                 vmcs->hdr.shadow_vmcs = 1;
2410         return vmcs;
2411 }
2412
2413 void free_vmcs(struct vmcs *vmcs)
2414 {
2415         free_pages((unsigned long)vmcs, vmcs_config.order);
2416 }
2417
2418 /*
2419  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2420  */
2421 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2422 {
2423         if (!loaded_vmcs->vmcs)
2424                 return;
2425         loaded_vmcs_clear(loaded_vmcs);
2426         free_vmcs(loaded_vmcs->vmcs);
2427         loaded_vmcs->vmcs = NULL;
2428         if (loaded_vmcs->msr_bitmap)
2429                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2430         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2431 }
2432
2433 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2434 {
2435         loaded_vmcs->vmcs = alloc_vmcs(false);
2436         if (!loaded_vmcs->vmcs)
2437                 return -ENOMEM;
2438
2439         loaded_vmcs->shadow_vmcs = NULL;
2440         loaded_vmcs_init(loaded_vmcs);
2441
2442         if (cpu_has_vmx_msr_bitmap()) {
2443                 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
2444                 if (!loaded_vmcs->msr_bitmap)
2445                         goto out_vmcs;
2446                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2447
2448                 if (IS_ENABLED(CONFIG_HYPERV) &&
2449                     static_branch_unlikely(&enable_evmcs) &&
2450                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2451                         struct hv_enlightened_vmcs *evmcs =
2452                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2453
2454                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2455                 }
2456         }
2457
2458         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2459
2460         return 0;
2461
2462 out_vmcs:
2463         free_loaded_vmcs(loaded_vmcs);
2464         return -ENOMEM;
2465 }
2466
2467 static void free_kvm_area(void)
2468 {
2469         int cpu;
2470
2471         for_each_possible_cpu(cpu) {
2472                 free_vmcs(per_cpu(vmxarea, cpu));
2473                 per_cpu(vmxarea, cpu) = NULL;
2474         }
2475 }
2476
2477 static __init int alloc_kvm_area(void)
2478 {
2479         int cpu;
2480
2481         for_each_possible_cpu(cpu) {
2482                 struct vmcs *vmcs;
2483
2484                 vmcs = alloc_vmcs_cpu(false, cpu);
2485                 if (!vmcs) {
2486                         free_kvm_area();
2487                         return -ENOMEM;
2488                 }
2489
2490                 /*
2491                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2492                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2493                  * revision_id reported by MSR_IA32_VMX_BASIC.
2494                  *
2495                  * However, even though not explicitly documented by
2496                  * TLFS, VMXArea passed as VMXON argument should
2497                  * still be marked with revision_id reported by
2498                  * physical CPU.
2499                  */
2500                 if (static_branch_unlikely(&enable_evmcs))
2501                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2502
2503                 per_cpu(vmxarea, cpu) = vmcs;
2504         }
2505         return 0;
2506 }
2507
2508 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2509                 struct kvm_segment *save)
2510 {
2511         if (!emulate_invalid_guest_state) {
2512                 /*
2513                  * CS and SS RPL should be equal during guest entry according
2514                  * to VMX spec, but in reality it is not always so. Since vcpu
2515                  * is in the middle of the transition from real mode to
2516                  * protected mode it is safe to assume that RPL 0 is a good
2517                  * default value.
2518                  */
2519                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2520                         save->selector &= ~SEGMENT_RPL_MASK;
2521                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2522                 save->s = 1;
2523         }
2524         vmx_set_segment(vcpu, save, seg);
2525 }
2526
2527 static void enter_pmode(struct kvm_vcpu *vcpu)
2528 {
2529         unsigned long flags;
2530         struct vcpu_vmx *vmx = to_vmx(vcpu);
2531
2532         /*
2533          * Update real mode segment cache. It may be not up-to-date if sement
2534          * register was written while vcpu was in a guest mode.
2535          */
2536         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2537         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2538         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2539         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2540         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2541         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2542
2543         vmx->rmode.vm86_active = 0;
2544
2545         vmx_segment_cache_clear(vmx);
2546
2547         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2548
2549         flags = vmcs_readl(GUEST_RFLAGS);
2550         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2551         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2552         vmcs_writel(GUEST_RFLAGS, flags);
2553
2554         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2555                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2556
2557         update_exception_bitmap(vcpu);
2558
2559         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2560         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2561         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2562         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2563         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2564         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2565 }
2566
2567 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2568 {
2569         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2570         struct kvm_segment var = *save;
2571
2572         var.dpl = 0x3;
2573         if (seg == VCPU_SREG_CS)
2574                 var.type = 0x3;
2575
2576         if (!emulate_invalid_guest_state) {
2577                 var.selector = var.base >> 4;
2578                 var.base = var.base & 0xffff0;
2579                 var.limit = 0xffff;
2580                 var.g = 0;
2581                 var.db = 0;
2582                 var.present = 1;
2583                 var.s = 1;
2584                 var.l = 0;
2585                 var.unusable = 0;
2586                 var.type = 0x3;
2587                 var.avl = 0;
2588                 if (save->base & 0xf)
2589                         printk_once(KERN_WARNING "kvm: segment base is not "
2590                                         "paragraph aligned when entering "
2591                                         "protected mode (seg=%d)", seg);
2592         }
2593
2594         vmcs_write16(sf->selector, var.selector);
2595         vmcs_writel(sf->base, var.base);
2596         vmcs_write32(sf->limit, var.limit);
2597         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2598 }
2599
2600 static void enter_rmode(struct kvm_vcpu *vcpu)
2601 {
2602         unsigned long flags;
2603         struct vcpu_vmx *vmx = to_vmx(vcpu);
2604         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2605
2606         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2607         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2608         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2609         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2610         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2611         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2612         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2613
2614         vmx->rmode.vm86_active = 1;
2615
2616         /*
2617          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2618          * vcpu. Warn the user that an update is overdue.
2619          */
2620         if (!kvm_vmx->tss_addr)
2621                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2622                              "called before entering vcpu\n");
2623
2624         vmx_segment_cache_clear(vmx);
2625
2626         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2627         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2628         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2629
2630         flags = vmcs_readl(GUEST_RFLAGS);
2631         vmx->rmode.save_rflags = flags;
2632
2633         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2634
2635         vmcs_writel(GUEST_RFLAGS, flags);
2636         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2637         update_exception_bitmap(vcpu);
2638
2639         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2640         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2641         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2642         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2643         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2644         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2645
2646         kvm_mmu_reset_context(vcpu);
2647 }
2648
2649 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2650 {
2651         struct vcpu_vmx *vmx = to_vmx(vcpu);
2652         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2653
2654         if (!msr)
2655                 return;
2656
2657         vcpu->arch.efer = efer;
2658         if (efer & EFER_LMA) {
2659                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2660                 msr->data = efer;
2661         } else {
2662                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2663
2664                 msr->data = efer & ~EFER_LME;
2665         }
2666         setup_msrs(vmx);
2667 }
2668
2669 #ifdef CONFIG_X86_64
2670
2671 static void enter_lmode(struct kvm_vcpu *vcpu)
2672 {
2673         u32 guest_tr_ar;
2674
2675         vmx_segment_cache_clear(to_vmx(vcpu));
2676
2677         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2678         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2679                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2680                                      __func__);
2681                 vmcs_write32(GUEST_TR_AR_BYTES,
2682                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2683                              | VMX_AR_TYPE_BUSY_64_TSS);
2684         }
2685         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2686 }
2687
2688 static void exit_lmode(struct kvm_vcpu *vcpu)
2689 {
2690         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2691         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2692 }
2693
2694 #endif
2695
2696 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2697 {
2698         int vpid = to_vmx(vcpu)->vpid;
2699
2700         if (!vpid_sync_vcpu_addr(vpid, addr))
2701                 vpid_sync_context(vpid);
2702
2703         /*
2704          * If VPIDs are not supported or enabled, then the above is a no-op.
2705          * But we don't really need a TLB flush in that case anyway, because
2706          * each VM entry/exit includes an implicit flush when VPID is 0.
2707          */
2708 }
2709
2710 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2711 {
2712         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2713
2714         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2715         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2716 }
2717
2718 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2719 {
2720         if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2721                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2722         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2723 }
2724
2725 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2726 {
2727         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2728
2729         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2730         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2731 }
2732
2733 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2734 {
2735         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2736
2737         if (!test_bit(VCPU_EXREG_PDPTR,
2738                       (unsigned long *)&vcpu->arch.regs_dirty))
2739                 return;
2740
2741         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2742                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2743                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2744                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2745                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2746         }
2747 }
2748
2749 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2750 {
2751         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2752
2753         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2754                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2755                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2756                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2757                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2758         }
2759
2760         __set_bit(VCPU_EXREG_PDPTR,
2761                   (unsigned long *)&vcpu->arch.regs_avail);
2762         __set_bit(VCPU_EXREG_PDPTR,
2763                   (unsigned long *)&vcpu->arch.regs_dirty);
2764 }
2765
2766 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2767                                         unsigned long cr0,
2768                                         struct kvm_vcpu *vcpu)
2769 {
2770         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2771                 vmx_decache_cr3(vcpu);
2772         if (!(cr0 & X86_CR0_PG)) {
2773                 /* From paging/starting to nonpaging */
2774                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2775                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2776                              (CPU_BASED_CR3_LOAD_EXITING |
2777                               CPU_BASED_CR3_STORE_EXITING));
2778                 vcpu->arch.cr0 = cr0;
2779                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2780         } else if (!is_paging(vcpu)) {
2781                 /* From nonpaging to paging */
2782                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2783                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2784                              ~(CPU_BASED_CR3_LOAD_EXITING |
2785                                CPU_BASED_CR3_STORE_EXITING));
2786                 vcpu->arch.cr0 = cr0;
2787                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2788         }
2789
2790         if (!(cr0 & X86_CR0_WP))
2791                 *hw_cr0 &= ~X86_CR0_WP;
2792 }
2793
2794 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2795 {
2796         struct vcpu_vmx *vmx = to_vmx(vcpu);
2797         unsigned long hw_cr0;
2798
2799         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2800         if (enable_unrestricted_guest)
2801                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2802         else {
2803                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2804
2805                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2806                         enter_pmode(vcpu);
2807
2808                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2809                         enter_rmode(vcpu);
2810         }
2811
2812 #ifdef CONFIG_X86_64
2813         if (vcpu->arch.efer & EFER_LME) {
2814                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2815                         enter_lmode(vcpu);
2816                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2817                         exit_lmode(vcpu);
2818         }
2819 #endif
2820
2821         if (enable_ept && !enable_unrestricted_guest)
2822                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2823
2824         vmcs_writel(CR0_READ_SHADOW, cr0);
2825         vmcs_writel(GUEST_CR0, hw_cr0);
2826         vcpu->arch.cr0 = cr0;
2827
2828         /* depends on vcpu->arch.cr0 to be set to a new value */
2829         vmx->emulation_required = emulation_required(vcpu);
2830 }
2831
2832 static int get_ept_level(struct kvm_vcpu *vcpu)
2833 {
2834         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2835                 return 5;
2836         return 4;
2837 }
2838
2839 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2840 {
2841         u64 eptp = VMX_EPTP_MT_WB;
2842
2843         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2844
2845         if (enable_ept_ad_bits &&
2846             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2847                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2848         eptp |= (root_hpa & PAGE_MASK);
2849
2850         return eptp;
2851 }
2852
2853 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2854 {
2855         struct kvm *kvm = vcpu->kvm;
2856         unsigned long guest_cr3;
2857         u64 eptp;
2858
2859         guest_cr3 = cr3;
2860         if (enable_ept) {
2861                 eptp = construct_eptp(vcpu, cr3);
2862                 vmcs_write64(EPT_POINTER, eptp);
2863
2864                 if (kvm_x86_ops->tlb_remote_flush) {
2865                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2866                         to_vmx(vcpu)->ept_pointer = eptp;
2867                         to_kvm_vmx(kvm)->ept_pointers_match
2868                                 = EPT_POINTERS_CHECK;
2869                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2870                 }
2871
2872                 if (enable_unrestricted_guest || is_paging(vcpu) ||
2873                     is_guest_mode(vcpu))
2874                         guest_cr3 = kvm_read_cr3(vcpu);
2875                 else
2876                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
2877                 ept_load_pdptrs(vcpu);
2878         }
2879
2880         vmcs_writel(GUEST_CR3, guest_cr3);
2881 }
2882
2883 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2884 {
2885         /*
2886          * Pass through host's Machine Check Enable value to hw_cr4, which
2887          * is in force while we are in guest mode.  Do not let guests control
2888          * this bit, even if host CR4.MCE == 0.
2889          */
2890         unsigned long hw_cr4;
2891
2892         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
2893         if (enable_unrestricted_guest)
2894                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
2895         else if (to_vmx(vcpu)->rmode.vm86_active)
2896                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
2897         else
2898                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
2899
2900         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
2901                 if (cr4 & X86_CR4_UMIP) {
2902                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
2903                                 SECONDARY_EXEC_DESC);
2904                         hw_cr4 &= ~X86_CR4_UMIP;
2905                 } else if (!is_guest_mode(vcpu) ||
2906                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
2907                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
2908                                         SECONDARY_EXEC_DESC);
2909         }
2910
2911         if (cr4 & X86_CR4_VMXE) {
2912                 /*
2913                  * To use VMXON (and later other VMX instructions), a guest
2914                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
2915                  * So basically the check on whether to allow nested VMX
2916                  * is here.  We operate under the default treatment of SMM,
2917                  * so VMX cannot be enabled under SMM.
2918                  */
2919                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
2920                         return 1;
2921         }
2922
2923         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
2924                 return 1;
2925
2926         vcpu->arch.cr4 = cr4;
2927
2928         if (!enable_unrestricted_guest) {
2929                 if (enable_ept) {
2930                         if (!is_paging(vcpu)) {
2931                                 hw_cr4 &= ~X86_CR4_PAE;
2932                                 hw_cr4 |= X86_CR4_PSE;
2933                         } else if (!(cr4 & X86_CR4_PAE)) {
2934                                 hw_cr4 &= ~X86_CR4_PAE;
2935                         }
2936                 }
2937
2938                 /*
2939                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
2940                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
2941                  * to be manually disabled when guest switches to non-paging
2942                  * mode.
2943                  *
2944                  * If !enable_unrestricted_guest, the CPU is always running
2945                  * with CR0.PG=1 and CR4 needs to be modified.
2946                  * If enable_unrestricted_guest, the CPU automatically
2947                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
2948                  */
2949                 if (!is_paging(vcpu))
2950                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
2951         }
2952
2953         vmcs_writel(CR4_READ_SHADOW, cr4);
2954         vmcs_writel(GUEST_CR4, hw_cr4);
2955         return 0;
2956 }
2957
2958 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
2959 {
2960         struct vcpu_vmx *vmx = to_vmx(vcpu);
2961         u32 ar;
2962
2963         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
2964                 *var = vmx->rmode.segs[seg];
2965                 if (seg == VCPU_SREG_TR
2966                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2967                         return;
2968                 var->base = vmx_read_guest_seg_base(vmx, seg);
2969                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2970                 return;
2971         }
2972         var->base = vmx_read_guest_seg_base(vmx, seg);
2973         var->limit = vmx_read_guest_seg_limit(vmx, seg);
2974         var->selector = vmx_read_guest_seg_selector(vmx, seg);
2975         ar = vmx_read_guest_seg_ar(vmx, seg);
2976         var->unusable = (ar >> 16) & 1;
2977         var->type = ar & 15;
2978         var->s = (ar >> 4) & 1;
2979         var->dpl = (ar >> 5) & 3;
2980         /*
2981          * Some userspaces do not preserve unusable property. Since usable
2982          * segment has to be present according to VMX spec we can use present
2983          * property to amend userspace bug by making unusable segment always
2984          * nonpresent. vmx_segment_access_rights() already marks nonpresent
2985          * segment as unusable.
2986          */
2987         var->present = !var->unusable;
2988         var->avl = (ar >> 12) & 1;
2989         var->l = (ar >> 13) & 1;
2990         var->db = (ar >> 14) & 1;
2991         var->g = (ar >> 15) & 1;
2992 }
2993
2994 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2995 {
2996         struct kvm_segment s;
2997
2998         if (to_vmx(vcpu)->rmode.vm86_active) {
2999                 vmx_get_segment(vcpu, &s, seg);
3000                 return s.base;
3001         }
3002         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3003 }
3004
3005 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3006 {
3007         struct vcpu_vmx *vmx = to_vmx(vcpu);
3008
3009         if (unlikely(vmx->rmode.vm86_active))
3010                 return 0;
3011         else {
3012                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3013                 return VMX_AR_DPL(ar);
3014         }
3015 }
3016
3017 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3018 {
3019         u32 ar;
3020
3021         if (var->unusable || !var->present)
3022                 ar = 1 << 16;
3023         else {
3024                 ar = var->type & 15;
3025                 ar |= (var->s & 1) << 4;
3026                 ar |= (var->dpl & 3) << 5;
3027                 ar |= (var->present & 1) << 7;
3028                 ar |= (var->avl & 1) << 12;
3029                 ar |= (var->l & 1) << 13;
3030                 ar |= (var->db & 1) << 14;
3031                 ar |= (var->g & 1) << 15;
3032         }
3033
3034         return ar;
3035 }
3036
3037 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3038 {
3039         struct vcpu_vmx *vmx = to_vmx(vcpu);
3040         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3041
3042         vmx_segment_cache_clear(vmx);
3043
3044         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3045                 vmx->rmode.segs[seg] = *var;
3046                 if (seg == VCPU_SREG_TR)
3047                         vmcs_write16(sf->selector, var->selector);
3048                 else if (var->s)
3049                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3050                 goto out;
3051         }
3052
3053         vmcs_writel(sf->base, var->base);
3054         vmcs_write32(sf->limit, var->limit);
3055         vmcs_write16(sf->selector, var->selector);
3056
3057         /*
3058          *   Fix the "Accessed" bit in AR field of segment registers for older
3059          * qemu binaries.
3060          *   IA32 arch specifies that at the time of processor reset the
3061          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3062          * is setting it to 0 in the userland code. This causes invalid guest
3063          * state vmexit when "unrestricted guest" mode is turned on.
3064          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3065          * tree. Newer qemu binaries with that qemu fix would not need this
3066          * kvm hack.
3067          */
3068         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3069                 var->type |= 0x1; /* Accessed */
3070
3071         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3072
3073 out:
3074         vmx->emulation_required = emulation_required(vcpu);
3075 }
3076
3077 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3078 {
3079         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3080
3081         *db = (ar >> 14) & 1;
3082         *l = (ar >> 13) & 1;
3083 }
3084
3085 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3086 {
3087         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3088         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3089 }
3090
3091 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3092 {
3093         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3094         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3095 }
3096
3097 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3098 {
3099         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3100         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3101 }
3102
3103 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3104 {
3105         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3106         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3107 }
3108
3109 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3110 {
3111         struct kvm_segment var;
3112         u32 ar;
3113
3114         vmx_get_segment(vcpu, &var, seg);
3115         var.dpl = 0x3;
3116         if (seg == VCPU_SREG_CS)
3117                 var.type = 0x3;
3118         ar = vmx_segment_access_rights(&var);
3119
3120         if (var.base != (var.selector << 4))
3121                 return false;
3122         if (var.limit != 0xffff)
3123                 return false;
3124         if (ar != 0xf3)
3125                 return false;
3126
3127         return true;
3128 }
3129
3130 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3131 {
3132         struct kvm_segment cs;
3133         unsigned int cs_rpl;
3134
3135         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3136         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3137
3138         if (cs.unusable)
3139                 return false;
3140         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3141                 return false;
3142         if (!cs.s)
3143                 return false;
3144         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3145                 if (cs.dpl > cs_rpl)
3146                         return false;
3147         } else {
3148                 if (cs.dpl != cs_rpl)
3149                         return false;
3150         }
3151         if (!cs.present)
3152                 return false;
3153
3154         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3155         return true;
3156 }
3157
3158 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3159 {
3160         struct kvm_segment ss;
3161         unsigned int ss_rpl;
3162
3163         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3164         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3165
3166         if (ss.unusable)
3167                 return true;
3168         if (ss.type != 3 && ss.type != 7)
3169                 return false;
3170         if (!ss.s)
3171                 return false;
3172         if (ss.dpl != ss_rpl) /* DPL != RPL */
3173                 return false;
3174         if (!ss.present)
3175                 return false;
3176
3177         return true;
3178 }
3179
3180 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3181 {
3182         struct kvm_segment var;
3183         unsigned int rpl;
3184
3185         vmx_get_segment(vcpu, &var, seg);
3186         rpl = var.selector & SEGMENT_RPL_MASK;
3187
3188         if (var.unusable)
3189                 return true;
3190         if (!var.s)
3191                 return false;
3192         if (!var.present)
3193                 return false;
3194         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3195                 if (var.dpl < rpl) /* DPL < RPL */
3196                         return false;
3197         }
3198
3199         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3200          * rights flags
3201          */
3202         return true;
3203 }
3204
3205 static bool tr_valid(struct kvm_vcpu *vcpu)
3206 {
3207         struct kvm_segment tr;
3208
3209         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3210
3211         if (tr.unusable)
3212                 return false;
3213         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3214                 return false;
3215         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3216                 return false;
3217         if (!tr.present)
3218                 return false;
3219
3220         return true;
3221 }
3222
3223 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3224 {
3225         struct kvm_segment ldtr;
3226
3227         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3228
3229         if (ldtr.unusable)
3230                 return true;
3231         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3232                 return false;
3233         if (ldtr.type != 2)
3234                 return false;
3235         if (!ldtr.present)
3236                 return false;
3237
3238         return true;
3239 }
3240
3241 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3242 {
3243         struct kvm_segment cs, ss;
3244
3245         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3246         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3247
3248         return ((cs.selector & SEGMENT_RPL_MASK) ==
3249                  (ss.selector & SEGMENT_RPL_MASK));
3250 }
3251
3252 /*
3253  * Check if guest state is valid. Returns true if valid, false if
3254  * not.
3255  * We assume that registers are always usable
3256  */
3257 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3258 {
3259         if (enable_unrestricted_guest)
3260                 return true;
3261
3262         /* real mode guest state checks */
3263         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3264                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3265                         return false;
3266                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3267                         return false;
3268                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3269                         return false;
3270                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3271                         return false;
3272                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3273                         return false;
3274                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3275                         return false;
3276         } else {
3277         /* protected mode guest state checks */
3278                 if (!cs_ss_rpl_check(vcpu))
3279                         return false;
3280                 if (!code_segment_valid(vcpu))
3281                         return false;
3282                 if (!stack_segment_valid(vcpu))
3283                         return false;
3284                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3285                         return false;
3286                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3287                         return false;
3288                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3289                         return false;
3290                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3291                         return false;
3292                 if (!tr_valid(vcpu))
3293                         return false;
3294                 if (!ldtr_valid(vcpu))
3295                         return false;
3296         }
3297         /* TODO:
3298          * - Add checks on RIP
3299          * - Add checks on RFLAGS
3300          */
3301
3302         return true;
3303 }
3304
3305 static int init_rmode_tss(struct kvm *kvm)
3306 {
3307         gfn_t fn;
3308         u16 data = 0;
3309         int idx, r;
3310
3311         idx = srcu_read_lock(&kvm->srcu);
3312         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3313         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3314         if (r < 0)
3315                 goto out;
3316         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3317         r = kvm_write_guest_page(kvm, fn++, &data,
3318                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3319         if (r < 0)
3320                 goto out;
3321         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3322         if (r < 0)
3323                 goto out;
3324         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3325         if (r < 0)
3326                 goto out;
3327         data = ~0;
3328         r = kvm_write_guest_page(kvm, fn, &data,
3329                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3330                                  sizeof(u8));
3331 out:
3332         srcu_read_unlock(&kvm->srcu, idx);
3333         return r;
3334 }
3335
3336 static int init_rmode_identity_map(struct kvm *kvm)
3337 {
3338         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3339         int i, idx, r = 0;
3340         kvm_pfn_t identity_map_pfn;
3341         u32 tmp;
3342
3343         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3344         mutex_lock(&kvm->slots_lock);
3345
3346         if (likely(kvm_vmx->ept_identity_pagetable_done))
3347                 goto out2;
3348
3349         if (!kvm_vmx->ept_identity_map_addr)
3350                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3351         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3352
3353         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3354                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3355         if (r < 0)
3356                 goto out2;
3357
3358         idx = srcu_read_lock(&kvm->srcu);
3359         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3360         if (r < 0)
3361                 goto out;
3362         /* Set up identity-mapping pagetable for EPT in real mode */
3363         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3364                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3365                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3366                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3367                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3368                 if (r < 0)
3369                         goto out;
3370         }
3371         kvm_vmx->ept_identity_pagetable_done = true;
3372
3373 out:
3374         srcu_read_unlock(&kvm->srcu, idx);
3375
3376 out2:
3377         mutex_unlock(&kvm->slots_lock);
3378         return r;
3379 }
3380
3381 static void seg_setup(int seg)
3382 {
3383         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3384         unsigned int ar;
3385
3386         vmcs_write16(sf->selector, 0);
3387         vmcs_writel(sf->base, 0);
3388         vmcs_write32(sf->limit, 0xffff);
3389         ar = 0x93;
3390         if (seg == VCPU_SREG_CS)
3391                 ar |= 0x08; /* code segment */
3392
3393         vmcs_write32(sf->ar_bytes, ar);
3394 }
3395
3396 static int alloc_apic_access_page(struct kvm *kvm)
3397 {
3398         struct page *page;
3399         int r = 0;
3400
3401         mutex_lock(&kvm->slots_lock);
3402         if (kvm->arch.apic_access_page_done)
3403                 goto out;
3404         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3405                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3406         if (r)
3407                 goto out;
3408
3409         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3410         if (is_error_page(page)) {
3411                 r = -EFAULT;
3412                 goto out;
3413         }
3414
3415         /*
3416          * Do not pin the page in memory, so that memory hot-unplug
3417          * is able to migrate it.
3418          */
3419         put_page(page);
3420         kvm->arch.apic_access_page_done = true;
3421 out:
3422         mutex_unlock(&kvm->slots_lock);
3423         return r;
3424 }
3425
3426 int allocate_vpid(void)
3427 {
3428         int vpid;
3429
3430         if (!enable_vpid)
3431                 return 0;
3432         spin_lock(&vmx_vpid_lock);
3433         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3434         if (vpid < VMX_NR_VPIDS)
3435                 __set_bit(vpid, vmx_vpid_bitmap);
3436         else
3437                 vpid = 0;
3438         spin_unlock(&vmx_vpid_lock);
3439         return vpid;
3440 }
3441
3442 void free_vpid(int vpid)
3443 {
3444         if (!enable_vpid || vpid == 0)
3445                 return;
3446         spin_lock(&vmx_vpid_lock);
3447         __clear_bit(vpid, vmx_vpid_bitmap);
3448         spin_unlock(&vmx_vpid_lock);
3449 }
3450
3451 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3452                                                           u32 msr, int type)
3453 {
3454         int f = sizeof(unsigned long);
3455
3456         if (!cpu_has_vmx_msr_bitmap())
3457                 return;
3458
3459         if (static_branch_unlikely(&enable_evmcs))
3460                 evmcs_touch_msr_bitmap();
3461
3462         /*
3463          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3464          * have the write-low and read-high bitmap offsets the wrong way round.
3465          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3466          */
3467         if (msr <= 0x1fff) {
3468                 if (type & MSR_TYPE_R)
3469                         /* read-low */
3470                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3471
3472                 if (type & MSR_TYPE_W)
3473                         /* write-low */
3474                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3475
3476         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3477                 msr &= 0x1fff;
3478                 if (type & MSR_TYPE_R)
3479                         /* read-high */
3480                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3481
3482                 if (type & MSR_TYPE_W)
3483                         /* write-high */
3484                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3485
3486         }
3487 }
3488
3489 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3490                                                          u32 msr, int type)
3491 {
3492         int f = sizeof(unsigned long);
3493
3494         if (!cpu_has_vmx_msr_bitmap())
3495                 return;
3496
3497         if (static_branch_unlikely(&enable_evmcs))
3498                 evmcs_touch_msr_bitmap();
3499
3500         /*
3501          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3502          * have the write-low and read-high bitmap offsets the wrong way round.
3503          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3504          */
3505         if (msr <= 0x1fff) {
3506                 if (type & MSR_TYPE_R)
3507                         /* read-low */
3508                         __set_bit(msr, msr_bitmap + 0x000 / f);
3509
3510                 if (type & MSR_TYPE_W)
3511                         /* write-low */
3512                         __set_bit(msr, msr_bitmap + 0x800 / f);
3513
3514         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3515                 msr &= 0x1fff;
3516                 if (type & MSR_TYPE_R)
3517                         /* read-high */
3518                         __set_bit(msr, msr_bitmap + 0x400 / f);
3519
3520                 if (type & MSR_TYPE_W)
3521                         /* write-high */
3522                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3523
3524         }
3525 }
3526
3527 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3528                                                       u32 msr, int type, bool value)
3529 {
3530         if (value)
3531                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3532         else
3533                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3534 }
3535
3536 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3537 {
3538         u8 mode = 0;
3539
3540         if (cpu_has_secondary_exec_ctrls() &&
3541             (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
3542              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3543                 mode |= MSR_BITMAP_MODE_X2APIC;
3544                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3545                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3546         }
3547
3548         return mode;
3549 }
3550
3551 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3552                                          u8 mode)
3553 {
3554         int msr;
3555
3556         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3557                 unsigned word = msr / BITS_PER_LONG;
3558                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3559                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3560         }
3561
3562         if (mode & MSR_BITMAP_MODE_X2APIC) {
3563                 /*
3564                  * TPR reads and writes can be virtualized even if virtual interrupt
3565                  * delivery is not in use.
3566                  */
3567                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3568                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3569                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3570                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3571                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3572                 }
3573         }
3574 }
3575
3576 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3577 {
3578         struct vcpu_vmx *vmx = to_vmx(vcpu);
3579         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3580         u8 mode = vmx_msr_bitmap_mode(vcpu);
3581         u8 changed = mode ^ vmx->msr_bitmap_mode;
3582
3583         if (!changed)
3584                 return;
3585
3586         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3587                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3588
3589         vmx->msr_bitmap_mode = mode;
3590 }
3591
3592 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3593 {
3594         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3595         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3596         u32 i;
3597
3598         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3599                                                         MSR_TYPE_RW, flag);
3600         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3601                                                         MSR_TYPE_RW, flag);
3602         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3603                                                         MSR_TYPE_RW, flag);
3604         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3605                                                         MSR_TYPE_RW, flag);
3606         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3607                 vmx_set_intercept_for_msr(msr_bitmap,
3608                         MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3609                 vmx_set_intercept_for_msr(msr_bitmap,
3610                         MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3611         }
3612 }
3613
3614 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
3615 {
3616         return enable_apicv;
3617 }
3618
3619 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3620 {
3621         struct vcpu_vmx *vmx = to_vmx(vcpu);
3622         void *vapic_page;
3623         u32 vppr;
3624         int rvi;
3625
3626         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3627                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3628                 WARN_ON_ONCE(!vmx->nested.virtual_apic_page))
3629                 return false;
3630
3631         rvi = vmx_get_rvi();
3632
3633         vapic_page = kmap(vmx->nested.virtual_apic_page);
3634         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3635         kunmap(vmx->nested.virtual_apic_page);
3636
3637         return ((rvi & 0xf0) > (vppr & 0xf0));
3638 }
3639
3640 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3641                                                      bool nested)
3642 {
3643 #ifdef CONFIG_SMP
3644         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3645
3646         if (vcpu->mode == IN_GUEST_MODE) {
3647                 /*
3648                  * The vector of interrupt to be delivered to vcpu had
3649                  * been set in PIR before this function.
3650                  *
3651                  * Following cases will be reached in this block, and
3652                  * we always send a notification event in all cases as
3653                  * explained below.
3654                  *
3655                  * Case 1: vcpu keeps in non-root mode. Sending a
3656                  * notification event posts the interrupt to vcpu.
3657                  *
3658                  * Case 2: vcpu exits to root mode and is still
3659                  * runnable. PIR will be synced to vIRR before the
3660                  * next vcpu entry. Sending a notification event in
3661                  * this case has no effect, as vcpu is not in root
3662                  * mode.
3663                  *
3664                  * Case 3: vcpu exits to root mode and is blocked.
3665                  * vcpu_block() has already synced PIR to vIRR and
3666                  * never blocks vcpu if vIRR is not cleared. Therefore,
3667                  * a blocked vcpu here does not wait for any requested
3668                  * interrupts in PIR, and sending a notification event
3669                  * which has no effect is safe here.
3670                  */
3671
3672                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3673                 return true;
3674         }
3675 #endif
3676         return false;
3677 }
3678
3679 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3680                                                 int vector)
3681 {
3682         struct vcpu_vmx *vmx = to_vmx(vcpu);
3683
3684         if (is_guest_mode(vcpu) &&
3685             vector == vmx->nested.posted_intr_nv) {
3686                 /*
3687                  * If a posted intr is not recognized by hardware,
3688                  * we will accomplish it in the next vmentry.
3689                  */
3690                 vmx->nested.pi_pending = true;
3691                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3692                 /* the PIR and ON have been set by L1. */
3693                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3694                         kvm_vcpu_kick(vcpu);
3695                 return 0;
3696         }
3697         return -1;
3698 }
3699 /*
3700  * Send interrupt to vcpu via posted interrupt way.
3701  * 1. If target vcpu is running(non-root mode), send posted interrupt
3702  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3703  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3704  * interrupt from PIR in next vmentry.
3705  */
3706 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3707 {
3708         struct vcpu_vmx *vmx = to_vmx(vcpu);
3709         int r;
3710
3711         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3712         if (!r)
3713                 return;
3714
3715         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3716                 return;
3717
3718         /* If a previous notification has sent the IPI, nothing to do.  */
3719         if (pi_test_and_set_on(&vmx->pi_desc))
3720                 return;
3721
3722         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3723                 kvm_vcpu_kick(vcpu);
3724 }
3725
3726 /*
3727  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3728  * will not change in the lifetime of the guest.
3729  * Note that host-state that does change is set elsewhere. E.g., host-state
3730  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3731  */
3732 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3733 {
3734         u32 low32, high32;
3735         unsigned long tmpl;
3736         struct desc_ptr dt;
3737         unsigned long cr0, cr3, cr4;
3738
3739         cr0 = read_cr0();
3740         WARN_ON(cr0 & X86_CR0_TS);
3741         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3742
3743         /*
3744          * Save the most likely value for this task's CR3 in the VMCS.
3745          * We can't use __get_current_cr3_fast() because we're not atomic.
3746          */
3747         cr3 = __read_cr3();
3748         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
3749         vmx->loaded_vmcs->host_state.cr3 = cr3;
3750
3751         /* Save the most likely value for this task's CR4 in the VMCS. */
3752         cr4 = cr4_read_shadow();
3753         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
3754         vmx->loaded_vmcs->host_state.cr4 = cr4;
3755
3756         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3757 #ifdef CONFIG_X86_64
3758         /*
3759          * Load null selectors, so we can avoid reloading them in
3760          * vmx_prepare_switch_to_host(), in case userspace uses
3761          * the null selectors too (the expected case).
3762          */
3763         vmcs_write16(HOST_DS_SELECTOR, 0);
3764         vmcs_write16(HOST_ES_SELECTOR, 0);
3765 #else
3766         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3767         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3768 #endif
3769         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3770         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3771
3772         store_idt(&dt);
3773         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3774         vmx->host_idt_base = dt.address;
3775
3776         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3777
3778         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3779         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3780         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3781         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3782
3783         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3784                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3785                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3786         }
3787
3788         if (cpu_has_load_ia32_efer())
3789                 vmcs_write64(HOST_IA32_EFER, host_efer);
3790 }
3791
3792 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3793 {
3794         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3795         if (enable_ept)
3796                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3797         if (is_guest_mode(&vmx->vcpu))
3798                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3799                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3800         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3801 }
3802
3803 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3804 {
3805         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3806
3807         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3808                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3809
3810         if (!enable_vnmi)
3811                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3812
3813         /* Enable the preemption timer dynamically */
3814         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3815         return pin_based_exec_ctrl;
3816 }
3817
3818 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3819 {
3820         struct vcpu_vmx *vmx = to_vmx(vcpu);
3821
3822         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
3823         if (cpu_has_secondary_exec_ctrls()) {
3824                 if (kvm_vcpu_apicv_active(vcpu))
3825                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
3826                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
3827                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3828                 else
3829                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
3830                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3831                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3832         }
3833
3834         if (cpu_has_vmx_msr_bitmap())
3835                 vmx_update_msr_bitmap(vcpu);
3836 }
3837
3838 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3839 {
3840         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3841
3842         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3843                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3844
3845         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3846                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3847 #ifdef CONFIG_X86_64
3848                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3849                                 CPU_BASED_CR8_LOAD_EXITING;
3850 #endif
3851         }
3852         if (!enable_ept)
3853                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3854                                 CPU_BASED_CR3_LOAD_EXITING  |
3855                                 CPU_BASED_INVLPG_EXITING;
3856         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3857                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3858                                 CPU_BASED_MONITOR_EXITING);
3859         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3860                 exec_control &= ~CPU_BASED_HLT_EXITING;
3861         return exec_control;
3862 }
3863
3864
3865 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
3866 {
3867         struct kvm_vcpu *vcpu = &vmx->vcpu;
3868
3869         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3870
3871         if (pt_mode == PT_MODE_SYSTEM)
3872                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
3873         if (!cpu_need_virtualize_apic_accesses(vcpu))
3874                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3875         if (vmx->vpid == 0)
3876                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3877         if (!enable_ept) {
3878                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3879                 enable_unrestricted_guest = 0;
3880         }
3881         if (!enable_unrestricted_guest)
3882                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3883         if (kvm_pause_in_guest(vmx->vcpu.kvm))
3884                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3885         if (!kvm_vcpu_apicv_active(vcpu))
3886                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3887                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3888         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
3889
3890         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
3891          * in vmx_set_cr4.  */
3892         exec_control &= ~SECONDARY_EXEC_DESC;
3893
3894         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
3895            (handle_vmptrld).
3896            We can NOT enable shadow_vmcs here because we don't have yet
3897            a current VMCS12
3898         */
3899         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
3900
3901         if (!enable_pml)
3902                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
3903
3904         if (vmx_xsaves_supported()) {
3905                 /* Exposing XSAVES only when XSAVE is exposed */
3906                 bool xsaves_enabled =
3907                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3908                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
3909
3910                 if (!xsaves_enabled)
3911                         exec_control &= ~SECONDARY_EXEC_XSAVES;
3912
3913                 if (nested) {
3914                         if (xsaves_enabled)
3915                                 vmx->nested.msrs.secondary_ctls_high |=
3916                                         SECONDARY_EXEC_XSAVES;
3917                         else
3918                                 vmx->nested.msrs.secondary_ctls_high &=
3919                                         ~SECONDARY_EXEC_XSAVES;
3920                 }
3921         }
3922
3923         if (vmx_rdtscp_supported()) {
3924                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
3925                 if (!rdtscp_enabled)
3926                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
3927
3928                 if (nested) {
3929                         if (rdtscp_enabled)
3930                                 vmx->nested.msrs.secondary_ctls_high |=
3931                                         SECONDARY_EXEC_RDTSCP;
3932                         else
3933                                 vmx->nested.msrs.secondary_ctls_high &=
3934                                         ~SECONDARY_EXEC_RDTSCP;
3935                 }
3936         }
3937
3938         if (vmx_invpcid_supported()) {
3939                 /* Exposing INVPCID only when PCID is exposed */
3940                 bool invpcid_enabled =
3941                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
3942                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
3943
3944                 if (!invpcid_enabled) {
3945                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3946                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
3947                 }
3948
3949                 if (nested) {
3950                         if (invpcid_enabled)
3951                                 vmx->nested.msrs.secondary_ctls_high |=
3952                                         SECONDARY_EXEC_ENABLE_INVPCID;
3953                         else
3954                                 vmx->nested.msrs.secondary_ctls_high &=
3955                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
3956                 }
3957         }
3958
3959         if (vmx_rdrand_supported()) {
3960                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
3961                 if (rdrand_enabled)
3962                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
3963
3964                 if (nested) {
3965                         if (rdrand_enabled)
3966                                 vmx->nested.msrs.secondary_ctls_high |=
3967                                         SECONDARY_EXEC_RDRAND_EXITING;
3968                         else
3969                                 vmx->nested.msrs.secondary_ctls_high &=
3970                                         ~SECONDARY_EXEC_RDRAND_EXITING;
3971                 }
3972         }
3973
3974         if (vmx_rdseed_supported()) {
3975                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
3976                 if (rdseed_enabled)
3977                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
3978
3979                 if (nested) {
3980                         if (rdseed_enabled)
3981                                 vmx->nested.msrs.secondary_ctls_high |=
3982                                         SECONDARY_EXEC_RDSEED_EXITING;
3983                         else
3984                                 vmx->nested.msrs.secondary_ctls_high &=
3985                                         ~SECONDARY_EXEC_RDSEED_EXITING;
3986                 }
3987         }
3988
3989         vmx->secondary_exec_control = exec_control;
3990 }
3991
3992 static void ept_set_mmio_spte_mask(void)
3993 {
3994         /*
3995          * EPT Misconfigurations can be generated if the value of bits 2:0
3996          * of an EPT paging-structure entry is 110b (write/execute).
3997          */
3998         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
3999                                    VMX_EPT_MISCONFIG_WX_VALUE);
4000 }
4001
4002 #define VMX_XSS_EXIT_BITMAP 0
4003
4004 /*
4005  * Sets up the vmcs for emulated real mode.
4006  */
4007 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4008 {
4009         int i;
4010
4011         if (nested)
4012                 nested_vmx_vcpu_setup();
4013
4014         if (cpu_has_vmx_msr_bitmap())
4015                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4016
4017         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4018
4019         /* Control */
4020         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4021         vmx->hv_deadline_tsc = -1;
4022
4023         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4024
4025         if (cpu_has_secondary_exec_ctrls()) {
4026                 vmx_compute_secondary_exec_control(vmx);
4027                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4028                              vmx->secondary_exec_control);
4029         }
4030
4031         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4032                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4033                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4034                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4035                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4036
4037                 vmcs_write16(GUEST_INTR_STATUS, 0);
4038
4039                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4040                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4041         }
4042
4043         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4044                 vmcs_write32(PLE_GAP, ple_gap);
4045                 vmx->ple_window = ple_window;
4046                 vmx->ple_window_dirty = true;
4047         }
4048
4049         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4050         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4051         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4052
4053         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4054         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4055         vmx_set_constant_host_state(vmx);
4056         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4057         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4058
4059         if (cpu_has_vmx_vmfunc())
4060                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4061
4062         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4063         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4064         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4065         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4066         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4067
4068         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4069                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4070
4071         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4072                 u32 index = vmx_msr_index[i];
4073                 u32 data_low, data_high;
4074                 int j = vmx->nmsrs;
4075
4076                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4077                         continue;
4078                 if (wrmsr_safe(index, data_low, data_high) < 0)
4079                         continue;
4080                 vmx->guest_msrs[j].index = i;
4081                 vmx->guest_msrs[j].data = 0;
4082                 vmx->guest_msrs[j].mask = -1ull;
4083                 ++vmx->nmsrs;
4084         }
4085
4086         vmx->arch_capabilities = kvm_get_arch_capabilities();
4087
4088         vm_exit_controls_init(vmx, vmx_vmexit_ctrl());
4089
4090         /* 22.2.1, 20.8.1 */
4091         vm_entry_controls_init(vmx, vmx_vmentry_ctrl());
4092
4093         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4094         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4095
4096         set_cr4_guest_host_mask(vmx);
4097
4098         if (vmx_xsaves_supported())
4099                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4100
4101         if (enable_pml) {
4102                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4103                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4104         }
4105
4106         if (cpu_has_vmx_encls_vmexit())
4107                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4108
4109         if (pt_mode == PT_MODE_HOST_GUEST) {
4110                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4111                 /* Bit[6~0] are forced to 1, writes are ignored. */
4112                 vmx->pt_desc.guest.output_mask = 0x7F;
4113                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4114         }
4115 }
4116
4117 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4118 {
4119         struct vcpu_vmx *vmx = to_vmx(vcpu);
4120         struct msr_data apic_base_msr;
4121         u64 cr0;
4122
4123         vmx->rmode.vm86_active = 0;
4124         vmx->spec_ctrl = 0;
4125
4126         vcpu->arch.microcode_version = 0x100000000ULL;
4127         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4128         kvm_set_cr8(vcpu, 0);
4129
4130         if (!init_event) {
4131                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4132                                      MSR_IA32_APICBASE_ENABLE;
4133                 if (kvm_vcpu_is_reset_bsp(vcpu))
4134                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4135                 apic_base_msr.host_initiated = true;
4136                 kvm_set_apic_base(vcpu, &apic_base_msr);
4137         }
4138
4139         vmx_segment_cache_clear(vmx);
4140
4141         seg_setup(VCPU_SREG_CS);
4142         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4143         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4144
4145         seg_setup(VCPU_SREG_DS);
4146         seg_setup(VCPU_SREG_ES);
4147         seg_setup(VCPU_SREG_FS);
4148         seg_setup(VCPU_SREG_GS);
4149         seg_setup(VCPU_SREG_SS);
4150
4151         vmcs_write16(GUEST_TR_SELECTOR, 0);
4152         vmcs_writel(GUEST_TR_BASE, 0);
4153         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4154         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4155
4156         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4157         vmcs_writel(GUEST_LDTR_BASE, 0);
4158         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4159         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4160
4161         if (!init_event) {
4162                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4163                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4164                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4165                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4166         }
4167
4168         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4169         kvm_rip_write(vcpu, 0xfff0);
4170
4171         vmcs_writel(GUEST_GDTR_BASE, 0);
4172         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4173
4174         vmcs_writel(GUEST_IDTR_BASE, 0);
4175         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4176
4177         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4178         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4179         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4180         if (kvm_mpx_supported())
4181                 vmcs_write64(GUEST_BNDCFGS, 0);
4182
4183         setup_msrs(vmx);
4184
4185         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4186
4187         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4188                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4189                 if (cpu_need_tpr_shadow(vcpu))
4190                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4191                                      __pa(vcpu->arch.apic->regs));
4192                 vmcs_write32(TPR_THRESHOLD, 0);
4193         }
4194
4195         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4196
4197         if (vmx->vpid != 0)
4198                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4199
4200         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4201         vmx->vcpu.arch.cr0 = cr0;
4202         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4203         vmx_set_cr4(vcpu, 0);
4204         vmx_set_efer(vcpu, 0);
4205
4206         update_exception_bitmap(vcpu);
4207
4208         vpid_sync_context(vmx->vpid);
4209         if (init_event)
4210                 vmx_clear_hlt(vcpu);
4211 }
4212
4213 static void enable_irq_window(struct kvm_vcpu *vcpu)
4214 {
4215         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
4216                       CPU_BASED_VIRTUAL_INTR_PENDING);
4217 }
4218
4219 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4220 {
4221         if (!enable_vnmi ||
4222             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4223                 enable_irq_window(vcpu);
4224                 return;
4225         }
4226
4227         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
4228                       CPU_BASED_VIRTUAL_NMI_PENDING);
4229 }
4230
4231 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4232 {
4233         struct vcpu_vmx *vmx = to_vmx(vcpu);
4234         uint32_t intr;
4235         int irq = vcpu->arch.interrupt.nr;
4236
4237         trace_kvm_inj_virq(irq);
4238
4239         ++vcpu->stat.irq_injections;
4240         if (vmx->rmode.vm86_active) {
4241                 int inc_eip = 0;
4242                 if (vcpu->arch.interrupt.soft)
4243                         inc_eip = vcpu->arch.event_exit_inst_len;
4244                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4245                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4246                 return;
4247         }
4248         intr = irq | INTR_INFO_VALID_MASK;
4249         if (vcpu->arch.interrupt.soft) {
4250                 intr |= INTR_TYPE_SOFT_INTR;
4251                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4252                              vmx->vcpu.arch.event_exit_inst_len);
4253         } else
4254                 intr |= INTR_TYPE_EXT_INTR;
4255         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4256
4257         vmx_clear_hlt(vcpu);
4258 }
4259
4260 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4261 {
4262         struct vcpu_vmx *vmx = to_vmx(vcpu);
4263
4264         if (!enable_vnmi) {
4265                 /*
4266                  * Tracking the NMI-blocked state in software is built upon
4267                  * finding the next open IRQ window. This, in turn, depends on
4268                  * well-behaving guests: They have to keep IRQs disabled at
4269                  * least as long as the NMI handler runs. Otherwise we may
4270                  * cause NMI nesting, maybe breaking the guest. But as this is
4271                  * highly unlikely, we can live with the residual risk.
4272                  */
4273                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4274                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4275         }
4276
4277         ++vcpu->stat.nmi_injections;
4278         vmx->loaded_vmcs->nmi_known_unmasked = false;
4279
4280         if (vmx->rmode.vm86_active) {
4281                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4282                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4283                 return;
4284         }
4285
4286         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4287                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4288
4289         vmx_clear_hlt(vcpu);
4290 }
4291
4292 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4293 {
4294         struct vcpu_vmx *vmx = to_vmx(vcpu);
4295         bool masked;
4296
4297         if (!enable_vnmi)
4298                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4299         if (vmx->loaded_vmcs->nmi_known_unmasked)
4300                 return false;
4301         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4302         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4303         return masked;
4304 }
4305
4306 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4307 {
4308         struct vcpu_vmx *vmx = to_vmx(vcpu);
4309
4310         if (!enable_vnmi) {
4311                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4312                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4313                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4314                 }
4315         } else {
4316                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4317                 if (masked)
4318                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4319                                       GUEST_INTR_STATE_NMI);
4320                 else
4321                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4322                                         GUEST_INTR_STATE_NMI);
4323         }
4324 }
4325
4326 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4327 {
4328         if (to_vmx(vcpu)->nested.nested_run_pending)
4329                 return 0;
4330
4331         if (!enable_vnmi &&
4332             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4333                 return 0;
4334
4335         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4336                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4337                    | GUEST_INTR_STATE_NMI));
4338 }
4339
4340 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4341 {
4342         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4343                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4344                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4345                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4346 }
4347
4348 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4349 {
4350         int ret;
4351
4352         if (enable_unrestricted_guest)
4353                 return 0;
4354
4355         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4356                                     PAGE_SIZE * 3);
4357         if (ret)
4358                 return ret;
4359         to_kvm_vmx(kvm)->tss_addr = addr;
4360         return init_rmode_tss(kvm);
4361 }
4362
4363 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4364 {
4365         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4366         return 0;
4367 }
4368
4369 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4370 {
4371         switch (vec) {
4372         case BP_VECTOR:
4373                 /*
4374                  * Update instruction length as we may reinject the exception
4375                  * from user space while in guest debugging mode.
4376                  */
4377                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4378                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4379                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4380                         return false;
4381                 /* fall through */
4382         case DB_VECTOR:
4383                 if (vcpu->guest_debug &
4384                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4385                         return false;
4386                 /* fall through */
4387         case DE_VECTOR:
4388         case OF_VECTOR:
4389         case BR_VECTOR:
4390         case UD_VECTOR:
4391         case DF_VECTOR:
4392         case SS_VECTOR:
4393         case GP_VECTOR:
4394         case MF_VECTOR:
4395                 return true;
4396         break;
4397         }
4398         return false;
4399 }
4400
4401 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4402                                   int vec, u32 err_code)
4403 {
4404         /*
4405          * Instruction with address size override prefix opcode 0x67
4406          * Cause the #SS fault with 0 error code in VM86 mode.
4407          */
4408         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4409                 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4410                         if (vcpu->arch.halt_request) {
4411                                 vcpu->arch.halt_request = 0;
4412                                 return kvm_vcpu_halt(vcpu);
4413                         }
4414                         return 1;
4415                 }
4416                 return 0;
4417         }
4418
4419         /*
4420          * Forward all other exceptions that are valid in real mode.
4421          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4422          *        the required debugging infrastructure rework.
4423          */
4424         kvm_queue_exception(vcpu, vec);
4425         return 1;
4426 }
4427
4428 /*
4429  * Trigger machine check on the host. We assume all the MSRs are already set up
4430  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4431  * We pass a fake environment to the machine check handler because we want
4432  * the guest to be always treated like user space, no matter what context
4433  * it used internally.
4434  */
4435 static void kvm_machine_check(void)
4436 {
4437 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4438         struct pt_regs regs = {
4439                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4440                 .flags = X86_EFLAGS_IF,
4441         };
4442
4443         do_machine_check(&regs, 0);
4444 #endif
4445 }
4446
4447 static int handle_machine_check(struct kvm_vcpu *vcpu)
4448 {
4449         /* already handled by vcpu_run */
4450         return 1;
4451 }
4452
4453 static int handle_exception(struct kvm_vcpu *vcpu)
4454 {
4455         struct vcpu_vmx *vmx = to_vmx(vcpu);
4456         struct kvm_run *kvm_run = vcpu->run;
4457         u32 intr_info, ex_no, error_code;
4458         unsigned long cr2, rip, dr6;
4459         u32 vect_info;
4460         enum emulation_result er;
4461
4462         vect_info = vmx->idt_vectoring_info;
4463         intr_info = vmx->exit_intr_info;
4464
4465         if (is_machine_check(intr_info))
4466                 return handle_machine_check(vcpu);
4467
4468         if (is_nmi(intr_info))
4469                 return 1;  /* already handled by vmx_vcpu_run() */
4470
4471         if (is_invalid_opcode(intr_info))
4472                 return handle_ud(vcpu);
4473
4474         error_code = 0;
4475         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4476                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4477
4478         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4479                 WARN_ON_ONCE(!enable_vmware_backdoor);
4480                 er = kvm_emulate_instruction(vcpu,
4481                         EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
4482                 if (er == EMULATE_USER_EXIT)
4483                         return 0;
4484                 else if (er != EMULATE_DONE)
4485                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4486                 return 1;
4487         }
4488
4489         /*
4490          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4491          * MMIO, it is better to report an internal error.
4492          * See the comments in vmx_handle_exit.
4493          */
4494         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4495             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4496                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4497                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4498                 vcpu->run->internal.ndata = 3;
4499                 vcpu->run->internal.data[0] = vect_info;
4500                 vcpu->run->internal.data[1] = intr_info;
4501                 vcpu->run->internal.data[2] = error_code;
4502                 return 0;
4503         }
4504
4505         if (is_page_fault(intr_info)) {
4506                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4507                 /* EPT won't cause page fault directly */
4508                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4509                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4510         }
4511
4512         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4513
4514         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4515                 return handle_rmode_exception(vcpu, ex_no, error_code);
4516
4517         switch (ex_no) {
4518         case AC_VECTOR:
4519                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4520                 return 1;
4521         case DB_VECTOR:
4522                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4523                 if (!(vcpu->guest_debug &
4524                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4525                         vcpu->arch.dr6 &= ~15;
4526                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4527                         if (is_icebp(intr_info))
4528                                 skip_emulated_instruction(vcpu);
4529
4530                         kvm_queue_exception(vcpu, DB_VECTOR);
4531                         return 1;
4532                 }
4533                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4534                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4535                 /* fall through */
4536         case BP_VECTOR:
4537                 /*
4538                  * Update instruction length as we may reinject #BP from
4539                  * user space while in guest debugging mode. Reading it for
4540                  * #DB as well causes no harm, it is not used in that case.
4541                  */
4542                 vmx->vcpu.arch.event_exit_inst_len =
4543                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4544                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4545                 rip = kvm_rip_read(vcpu);
4546                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4547                 kvm_run->debug.arch.exception = ex_no;
4548                 break;
4549         default:
4550                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4551                 kvm_run->ex.exception = ex_no;
4552                 kvm_run->ex.error_code = error_code;
4553                 break;
4554         }
4555         return 0;
4556 }
4557
4558 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4559 {
4560         ++vcpu->stat.irq_exits;
4561         return 1;
4562 }
4563
4564 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4565 {
4566         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4567         vcpu->mmio_needed = 0;
4568         return 0;
4569 }
4570
4571 static int handle_io(struct kvm_vcpu *vcpu)
4572 {
4573         unsigned long exit_qualification;
4574         int size, in, string;
4575         unsigned port;
4576
4577         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4578         string = (exit_qualification & 16) != 0;
4579
4580         ++vcpu->stat.io_exits;
4581
4582         if (string)
4583                 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4584
4585         port = exit_qualification >> 16;
4586         size = (exit_qualification & 7) + 1;
4587         in = (exit_qualification & 8) != 0;
4588
4589         return kvm_fast_pio(vcpu, size, port, in);
4590 }
4591
4592 static void
4593 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4594 {
4595         /*
4596          * Patch in the VMCALL instruction:
4597          */
4598         hypercall[0] = 0x0f;
4599         hypercall[1] = 0x01;
4600         hypercall[2] = 0xc1;
4601 }
4602
4603 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4604 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4605 {
4606         if (is_guest_mode(vcpu)) {
4607                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4608                 unsigned long orig_val = val;
4609
4610                 /*
4611                  * We get here when L2 changed cr0 in a way that did not change
4612                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4613                  * but did change L0 shadowed bits. So we first calculate the
4614                  * effective cr0 value that L1 would like to write into the
4615                  * hardware. It consists of the L2-owned bits from the new
4616                  * value combined with the L1-owned bits from L1's guest_cr0.
4617                  */
4618                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4619                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4620
4621                 if (!nested_guest_cr0_valid(vcpu, val))
4622                         return 1;
4623
4624                 if (kvm_set_cr0(vcpu, val))
4625                         return 1;
4626                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4627                 return 0;
4628         } else {
4629                 if (to_vmx(vcpu)->nested.vmxon &&
4630                     !nested_host_cr0_valid(vcpu, val))
4631                         return 1;
4632
4633                 return kvm_set_cr0(vcpu, val);
4634         }
4635 }
4636
4637 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4638 {
4639         if (is_guest_mode(vcpu)) {
4640                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4641                 unsigned long orig_val = val;
4642
4643                 /* analogously to handle_set_cr0 */
4644                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4645                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4646                 if (kvm_set_cr4(vcpu, val))
4647                         return 1;
4648                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4649                 return 0;
4650         } else
4651                 return kvm_set_cr4(vcpu, val);
4652 }
4653
4654 static int handle_desc(struct kvm_vcpu *vcpu)
4655 {
4656         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4657         return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4658 }
4659
4660 static int handle_cr(struct kvm_vcpu *vcpu)
4661 {
4662         unsigned long exit_qualification, val;
4663         int cr;
4664         int reg;
4665         int err;
4666         int ret;
4667
4668         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4669         cr = exit_qualification & 15;
4670         reg = (exit_qualification >> 8) & 15;
4671         switch ((exit_qualification >> 4) & 3) {
4672         case 0: /* mov to cr */
4673                 val = kvm_register_readl(vcpu, reg);
4674                 trace_kvm_cr_write(cr, val);
4675                 switch (cr) {
4676                 case 0:
4677                         err = handle_set_cr0(vcpu, val);
4678                         return kvm_complete_insn_gp(vcpu, err);
4679                 case 3:
4680                         WARN_ON_ONCE(enable_unrestricted_guest);
4681                         err = kvm_set_cr3(vcpu, val);
4682                         return kvm_complete_insn_gp(vcpu, err);
4683                 case 4:
4684                         err = handle_set_cr4(vcpu, val);
4685                         return kvm_complete_insn_gp(vcpu, err);
4686                 case 8: {
4687                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4688                                 u8 cr8 = (u8)val;
4689                                 err = kvm_set_cr8(vcpu, cr8);
4690                                 ret = kvm_complete_insn_gp(vcpu, err);
4691                                 if (lapic_in_kernel(vcpu))
4692                                         return ret;
4693                                 if (cr8_prev <= cr8)
4694                                         return ret;
4695                                 /*
4696                                  * TODO: we might be squashing a
4697                                  * KVM_GUESTDBG_SINGLESTEP-triggered
4698                                  * KVM_EXIT_DEBUG here.
4699                                  */
4700                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4701                                 return 0;
4702                         }
4703                 }
4704                 break;
4705         case 2: /* clts */
4706                 WARN_ONCE(1, "Guest should always own CR0.TS");
4707                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4708                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4709                 return kvm_skip_emulated_instruction(vcpu);
4710         case 1: /*mov from cr*/
4711                 switch (cr) {
4712                 case 3:
4713                         WARN_ON_ONCE(enable_unrestricted_guest);
4714                         val = kvm_read_cr3(vcpu);
4715                         kvm_register_write(vcpu, reg, val);
4716                         trace_kvm_cr_read(cr, val);
4717                         return kvm_skip_emulated_instruction(vcpu);
4718                 case 8:
4719                         val = kvm_get_cr8(vcpu);
4720                         kvm_register_write(vcpu, reg, val);
4721                         trace_kvm_cr_read(cr, val);
4722                         return kvm_skip_emulated_instruction(vcpu);
4723                 }
4724                 break;
4725         case 3: /* lmsw */
4726                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4727                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4728                 kvm_lmsw(vcpu, val);
4729
4730                 return kvm_skip_emulated_instruction(vcpu);
4731         default:
4732                 break;
4733         }
4734         vcpu->run->exit_reason = 0;
4735         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4736                (int)(exit_qualification >> 4) & 3, cr);
4737         return 0;
4738 }
4739
4740 static int handle_dr(struct kvm_vcpu *vcpu)
4741 {
4742         unsigned long exit_qualification;
4743         int dr, dr7, reg;
4744
4745         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4746         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4747
4748         /* First, if DR does not exist, trigger UD */
4749         if (!kvm_require_dr(vcpu, dr))
4750                 return 1;
4751
4752         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4753         if (!kvm_require_cpl(vcpu, 0))
4754                 return 1;
4755         dr7 = vmcs_readl(GUEST_DR7);
4756         if (dr7 & DR7_GD) {
4757                 /*
4758                  * As the vm-exit takes precedence over the debug trap, we
4759                  * need to emulate the latter, either for the host or the
4760                  * guest debugging itself.
4761                  */
4762                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4763                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4764                         vcpu->run->debug.arch.dr7 = dr7;
4765                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4766                         vcpu->run->debug.arch.exception = DB_VECTOR;
4767                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4768                         return 0;
4769                 } else {
4770                         vcpu->arch.dr6 &= ~15;
4771                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4772                         kvm_queue_exception(vcpu, DB_VECTOR);
4773                         return 1;
4774                 }
4775         }
4776
4777         if (vcpu->guest_debug == 0) {
4778                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
4779                                 CPU_BASED_MOV_DR_EXITING);
4780
4781                 /*
4782                  * No more DR vmexits; force a reload of the debug registers
4783                  * and reenter on this instruction.  The next vmexit will
4784                  * retrieve the full state of the debug registers.
4785                  */
4786                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4787                 return 1;
4788         }
4789
4790         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4791         if (exit_qualification & TYPE_MOV_FROM_DR) {
4792                 unsigned long val;
4793
4794                 if (kvm_get_dr(vcpu, dr, &val))
4795                         return 1;
4796                 kvm_register_write(vcpu, reg, val);
4797         } else
4798                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4799                         return 1;
4800
4801         return kvm_skip_emulated_instruction(vcpu);
4802 }
4803
4804 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4805 {
4806         return vcpu->arch.dr6;
4807 }
4808
4809 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4810 {
4811 }
4812
4813 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4814 {
4815         get_debugreg(vcpu->arch.db[0], 0);
4816         get_debugreg(vcpu->arch.db[1], 1);
4817         get_debugreg(vcpu->arch.db[2], 2);
4818         get_debugreg(vcpu->arch.db[3], 3);
4819         get_debugreg(vcpu->arch.dr6, 6);
4820         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4821
4822         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4823         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
4824 }
4825
4826 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4827 {
4828         vmcs_writel(GUEST_DR7, val);
4829 }
4830
4831 static int handle_cpuid(struct kvm_vcpu *vcpu)
4832 {
4833         return kvm_emulate_cpuid(vcpu);
4834 }
4835
4836 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4837 {
4838         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4839         struct msr_data msr_info;
4840
4841         msr_info.index = ecx;
4842         msr_info.host_initiated = false;
4843         if (vmx_get_msr(vcpu, &msr_info)) {
4844                 trace_kvm_msr_read_ex(ecx);
4845                 kvm_inject_gp(vcpu, 0);
4846                 return 1;
4847         }
4848
4849         trace_kvm_msr_read(ecx, msr_info.data);
4850
4851         /* FIXME: handling of bits 32:63 of rax, rdx */
4852         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
4853         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
4854         return kvm_skip_emulated_instruction(vcpu);
4855 }
4856
4857 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4858 {
4859         struct msr_data msr;
4860         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4861         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4862                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4863
4864         msr.data = data;
4865         msr.index = ecx;
4866         msr.host_initiated = false;
4867         if (kvm_set_msr(vcpu, &msr) != 0) {
4868                 trace_kvm_msr_write_ex(ecx, data);
4869                 kvm_inject_gp(vcpu, 0);
4870                 return 1;
4871         }
4872
4873         trace_kvm_msr_write(ecx, data);
4874         return kvm_skip_emulated_instruction(vcpu);
4875 }
4876
4877 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4878 {
4879         kvm_apic_update_ppr(vcpu);
4880         return 1;
4881 }
4882
4883 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4884 {
4885         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
4886                         CPU_BASED_VIRTUAL_INTR_PENDING);
4887
4888         kvm_make_request(KVM_REQ_EVENT, vcpu);
4889
4890         ++vcpu->stat.irq_window_exits;
4891         return 1;
4892 }
4893
4894 static int handle_halt(struct kvm_vcpu *vcpu)
4895 {
4896         return kvm_emulate_halt(vcpu);
4897 }
4898
4899 static int handle_vmcall(struct kvm_vcpu *vcpu)
4900 {
4901         return kvm_emulate_hypercall(vcpu);
4902 }
4903
4904 static int handle_invd(struct kvm_vcpu *vcpu)
4905 {
4906         return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4907 }
4908
4909 static int handle_invlpg(struct kvm_vcpu *vcpu)
4910 {
4911         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4912
4913         kvm_mmu_invlpg(vcpu, exit_qualification);
4914         return kvm_skip_emulated_instruction(vcpu);
4915 }
4916
4917 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4918 {
4919         int err;
4920
4921         err = kvm_rdpmc(vcpu);
4922         return kvm_complete_insn_gp(vcpu, err);
4923 }
4924
4925 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4926 {
4927         return kvm_emulate_wbinvd(vcpu);
4928 }
4929
4930 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4931 {
4932         u64 new_bv = kvm_read_edx_eax(vcpu);
4933         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4934
4935         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4936                 return kvm_skip_emulated_instruction(vcpu);
4937         return 1;
4938 }
4939
4940 static int handle_xsaves(struct kvm_vcpu *vcpu)
4941 {
4942         kvm_skip_emulated_instruction(vcpu);
4943         WARN(1, "this should never happen\n");
4944         return 1;
4945 }
4946
4947 static int handle_xrstors(struct kvm_vcpu *vcpu)
4948 {
4949         kvm_skip_emulated_instruction(vcpu);
4950         WARN(1, "this should never happen\n");
4951         return 1;
4952 }
4953
4954 static int handle_apic_access(struct kvm_vcpu *vcpu)
4955 {
4956         if (likely(fasteoi)) {
4957                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4958                 int access_type, offset;
4959
4960                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4961                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4962                 /*
4963                  * Sane guest uses MOV to write EOI, with written value
4964                  * not cared. So make a short-circuit here by avoiding
4965                  * heavy instruction emulation.
4966                  */
4967                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4968                     (offset == APIC_EOI)) {
4969                         kvm_lapic_set_eoi(vcpu);
4970                         return kvm_skip_emulated_instruction(vcpu);
4971                 }
4972         }
4973         return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4974 }
4975
4976 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4977 {
4978         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4979         int vector = exit_qualification & 0xff;
4980
4981         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4982         kvm_apic_set_eoi_accelerated(vcpu, vector);
4983         return 1;
4984 }
4985
4986 static int handle_apic_write(struct kvm_vcpu *vcpu)
4987 {
4988         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4989         u32 offset = exit_qualification & 0xfff;
4990
4991         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4992         kvm_apic_write_nodecode(vcpu, offset);
4993         return 1;
4994 }
4995
4996 static int handle_task_switch(struct kvm_vcpu *vcpu)
4997 {
4998         struct vcpu_vmx *vmx = to_vmx(vcpu);
4999         unsigned long exit_qualification;
5000         bool has_error_code = false;
5001         u32 error_code = 0;
5002         u16 tss_selector;
5003         int reason, type, idt_v, idt_index;
5004
5005         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5006         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5007         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5008
5009         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5010
5011         reason = (u32)exit_qualification >> 30;
5012         if (reason == TASK_SWITCH_GATE && idt_v) {
5013                 switch (type) {
5014                 case INTR_TYPE_NMI_INTR:
5015                         vcpu->arch.nmi_injected = false;
5016                         vmx_set_nmi_mask(vcpu, true);
5017                         break;
5018                 case INTR_TYPE_EXT_INTR:
5019                 case INTR_TYPE_SOFT_INTR:
5020                         kvm_clear_interrupt_queue(vcpu);
5021                         break;
5022                 case INTR_TYPE_HARD_EXCEPTION:
5023                         if (vmx->idt_vectoring_info &
5024                             VECTORING_INFO_DELIVER_CODE_MASK) {
5025                                 has_error_code = true;
5026                                 error_code =
5027                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5028                         }
5029                         /* fall through */
5030                 case INTR_TYPE_SOFT_EXCEPTION:
5031                         kvm_clear_exception_queue(vcpu);
5032                         break;
5033                 default:
5034                         break;
5035                 }
5036         }
5037         tss_selector = exit_qualification;
5038
5039         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5040                        type != INTR_TYPE_EXT_INTR &&
5041                        type != INTR_TYPE_NMI_INTR))
5042                 skip_emulated_instruction(vcpu);
5043
5044         if (kvm_task_switch(vcpu, tss_selector,
5045                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5046                             has_error_code, error_code) == EMULATE_FAIL) {
5047                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5048                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5049                 vcpu->run->internal.ndata = 0;
5050                 return 0;
5051         }
5052
5053         /*
5054          * TODO: What about debug traps on tss switch?
5055          *       Are we supposed to inject them and update dr6?
5056          */
5057
5058         return 1;
5059 }
5060
5061 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5062 {
5063         unsigned long exit_qualification;
5064         gpa_t gpa;
5065         u64 error_code;
5066
5067         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5068
5069         /*
5070          * EPT violation happened while executing iret from NMI,
5071          * "blocked by NMI" bit has to be set before next VM entry.
5072          * There are errata that may cause this bit to not be set:
5073          * AAK134, BY25.
5074          */
5075         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5076                         enable_vnmi &&
5077                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5078                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5079
5080         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5081         trace_kvm_page_fault(gpa, exit_qualification);
5082
5083         /* Is it a read fault? */
5084         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5085                      ? PFERR_USER_MASK : 0;
5086         /* Is it a write fault? */
5087         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5088                       ? PFERR_WRITE_MASK : 0;
5089         /* Is it a fetch fault? */
5090         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5091                       ? PFERR_FETCH_MASK : 0;
5092         /* ept page table entry is present? */
5093         error_code |= (exit_qualification &
5094                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5095                         EPT_VIOLATION_EXECUTABLE))
5096                       ? PFERR_PRESENT_MASK : 0;
5097
5098         error_code |= (exit_qualification & 0x100) != 0 ?
5099                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5100
5101         vcpu->arch.exit_qualification = exit_qualification;
5102         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5103 }
5104
5105 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5106 {
5107         gpa_t gpa;
5108
5109         /*
5110          * A nested guest cannot optimize MMIO vmexits, because we have an
5111          * nGPA here instead of the required GPA.
5112          */
5113         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5114         if (!is_guest_mode(vcpu) &&
5115             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5116                 trace_kvm_fast_mmio(gpa);
5117                 /*
5118                  * Doing kvm_skip_emulated_instruction() depends on undefined
5119                  * behavior: Intel's manual doesn't mandate
5120                  * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
5121                  * occurs and while on real hardware it was observed to be set,
5122                  * other hypervisors (namely Hyper-V) don't set it, we end up
5123                  * advancing IP with some random value. Disable fast mmio when
5124                  * running nested and keep it for real hardware in hope that
5125                  * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
5126                  */
5127                 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
5128                         return kvm_skip_emulated_instruction(vcpu);
5129                 else
5130                         return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) ==
5131                                                                 EMULATE_DONE;
5132         }
5133
5134         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5135 }
5136
5137 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5138 {
5139         WARN_ON_ONCE(!enable_vnmi);
5140         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5141                         CPU_BASED_VIRTUAL_NMI_PENDING);
5142         ++vcpu->stat.nmi_window_exits;
5143         kvm_make_request(KVM_REQ_EVENT, vcpu);
5144
5145         return 1;
5146 }
5147
5148 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5149 {
5150         struct vcpu_vmx *vmx = to_vmx(vcpu);
5151         enum emulation_result err = EMULATE_DONE;
5152         int ret = 1;
5153         u32 cpu_exec_ctrl;
5154         bool intr_window_requested;
5155         unsigned count = 130;
5156
5157         /*
5158          * We should never reach the point where we are emulating L2
5159          * due to invalid guest state as that means we incorrectly
5160          * allowed a nested VMEntry with an invalid vmcs12.
5161          */
5162         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5163
5164         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5165         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5166
5167         while (vmx->emulation_required && count-- != 0) {
5168                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5169                         return handle_interrupt_window(&vmx->vcpu);
5170
5171                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5172                         return 1;
5173
5174                 err = kvm_emulate_instruction(vcpu, 0);
5175
5176                 if (err == EMULATE_USER_EXIT) {
5177                         ++vcpu->stat.mmio_exits;
5178                         ret = 0;
5179                         goto out;
5180                 }
5181
5182                 if (err != EMULATE_DONE)
5183                         goto emulation_error;
5184
5185                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5186                     vcpu->arch.exception.pending)
5187                         goto emulation_error;
5188
5189                 if (vcpu->arch.halt_request) {
5190                         vcpu->arch.halt_request = 0;
5191                         ret = kvm_vcpu_halt(vcpu);
5192                         goto out;
5193                 }
5194
5195                 if (signal_pending(current))
5196                         goto out;
5197                 if (need_resched())
5198                         schedule();
5199         }
5200
5201 out:
5202         return ret;
5203
5204 emulation_error:
5205         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5206         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5207         vcpu->run->internal.ndata = 0;
5208         return 0;
5209 }
5210
5211 static void grow_ple_window(struct kvm_vcpu *vcpu)
5212 {
5213         struct vcpu_vmx *vmx = to_vmx(vcpu);
5214         int old = vmx->ple_window;
5215
5216         vmx->ple_window = __grow_ple_window(old, ple_window,
5217                                             ple_window_grow,
5218                                             ple_window_max);
5219
5220         if (vmx->ple_window != old)
5221                 vmx->ple_window_dirty = true;
5222
5223         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5224 }
5225
5226 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5227 {
5228         struct vcpu_vmx *vmx = to_vmx(vcpu);
5229         int old = vmx->ple_window;
5230
5231         vmx->ple_window = __shrink_ple_window(old, ple_window,
5232                                               ple_window_shrink,
5233                                               ple_window);
5234
5235         if (vmx->ple_window != old)
5236                 vmx->ple_window_dirty = true;
5237
5238         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5239 }
5240
5241 /*
5242  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5243  */
5244 static void wakeup_handler(void)
5245 {
5246         struct kvm_vcpu *vcpu;
5247         int cpu = smp_processor_id();
5248
5249         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5250         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5251                         blocked_vcpu_list) {
5252                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5253
5254                 if (pi_test_on(pi_desc) == 1)
5255                         kvm_vcpu_kick(vcpu);
5256         }
5257         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5258 }
5259
5260 static void vmx_enable_tdp(void)
5261 {
5262         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5263                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5264                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5265                 0ull, VMX_EPT_EXECUTABLE_MASK,
5266                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5267                 VMX_EPT_RWX_MASK, 0ull);
5268
5269         ept_set_mmio_spte_mask();
5270         kvm_enable_tdp();
5271 }
5272
5273 /*
5274  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5275  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5276  */
5277 static int handle_pause(struct kvm_vcpu *vcpu)
5278 {
5279         if (!kvm_pause_in_guest(vcpu->kvm))
5280                 grow_ple_window(vcpu);
5281
5282         /*
5283          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5284          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5285          * never set PAUSE_EXITING and just set PLE if supported,
5286          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5287          */
5288         kvm_vcpu_on_spin(vcpu, true);
5289         return kvm_skip_emulated_instruction(vcpu);
5290 }
5291
5292 static int handle_nop(struct kvm_vcpu *vcpu)
5293 {
5294         return kvm_skip_emulated_instruction(vcpu);
5295 }
5296
5297 static int handle_mwait(struct kvm_vcpu *vcpu)
5298 {
5299         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5300         return handle_nop(vcpu);
5301 }
5302
5303 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5304 {
5305         kvm_queue_exception(vcpu, UD_VECTOR);
5306         return 1;
5307 }
5308
5309 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5310 {
5311         return 1;
5312 }
5313
5314 static int handle_monitor(struct kvm_vcpu *vcpu)
5315 {
5316         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5317         return handle_nop(vcpu);
5318 }
5319
5320 static int handle_invpcid(struct kvm_vcpu *vcpu)
5321 {
5322         u32 vmx_instruction_info;
5323         unsigned long type;
5324         bool pcid_enabled;
5325         gva_t gva;
5326         struct x86_exception e;
5327         unsigned i;
5328         unsigned long roots_to_free = 0;
5329         struct {
5330                 u64 pcid;
5331                 u64 gla;
5332         } operand;
5333
5334         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5335                 kvm_queue_exception(vcpu, UD_VECTOR);
5336                 return 1;
5337         }
5338
5339         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5340         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5341
5342         if (type > 3) {
5343                 kvm_inject_gp(vcpu, 0);
5344                 return 1;
5345         }
5346
5347         /* According to the Intel instruction reference, the memory operand
5348          * is read even if it isn't needed (e.g., for type==all)
5349          */
5350         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5351                                 vmx_instruction_info, false, &gva))
5352                 return 1;
5353
5354         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5355                 kvm_inject_page_fault(vcpu, &e);
5356                 return 1;
5357         }
5358
5359         if (operand.pcid >> 12 != 0) {
5360                 kvm_inject_gp(vcpu, 0);
5361                 return 1;
5362         }
5363
5364         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5365
5366         switch (type) {
5367         case INVPCID_TYPE_INDIV_ADDR:
5368                 if ((!pcid_enabled && (operand.pcid != 0)) ||
5369                     is_noncanonical_address(operand.gla, vcpu)) {
5370                         kvm_inject_gp(vcpu, 0);
5371                         return 1;
5372                 }
5373                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5374                 return kvm_skip_emulated_instruction(vcpu);
5375
5376         case INVPCID_TYPE_SINGLE_CTXT:
5377                 if (!pcid_enabled && (operand.pcid != 0)) {
5378                         kvm_inject_gp(vcpu, 0);
5379                         return 1;
5380                 }
5381
5382                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5383                         kvm_mmu_sync_roots(vcpu);
5384                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5385                 }
5386
5387                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5388                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5389                             == operand.pcid)
5390                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5391
5392                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5393                 /*
5394                  * If neither the current cr3 nor any of the prev_roots use the
5395                  * given PCID, then nothing needs to be done here because a
5396                  * resync will happen anyway before switching to any other CR3.
5397                  */
5398
5399                 return kvm_skip_emulated_instruction(vcpu);
5400
5401         case INVPCID_TYPE_ALL_NON_GLOBAL:
5402                 /*
5403                  * Currently, KVM doesn't mark global entries in the shadow
5404                  * page tables, so a non-global flush just degenerates to a
5405                  * global flush. If needed, we could optimize this later by
5406                  * keeping track of global entries in shadow page tables.
5407                  */
5408
5409                 /* fall-through */
5410         case INVPCID_TYPE_ALL_INCL_GLOBAL:
5411                 kvm_mmu_unload(vcpu);
5412                 return kvm_skip_emulated_instruction(vcpu);
5413
5414         default:
5415                 BUG(); /* We have already checked above that type <= 3 */
5416         }
5417 }
5418
5419 static int handle_pml_full(struct kvm_vcpu *vcpu)
5420 {
5421         unsigned long exit_qualification;
5422
5423         trace_kvm_pml_full(vcpu->vcpu_id);
5424
5425         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5426
5427         /*
5428          * PML buffer FULL happened while executing iret from NMI,
5429          * "blocked by NMI" bit has to be set before next VM entry.
5430          */
5431         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5432                         enable_vnmi &&
5433                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5434                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5435                                 GUEST_INTR_STATE_NMI);
5436
5437         /*
5438          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5439          * here.., and there's no userspace involvement needed for PML.
5440          */
5441         return 1;
5442 }
5443
5444 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5445 {
5446         if (!to_vmx(vcpu)->req_immediate_exit)
5447                 kvm_lapic_expired_hv_timer(vcpu);
5448         return 1;
5449 }
5450
5451 /*
5452  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5453  * are overwritten by nested_vmx_setup() when nested=1.
5454  */
5455 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5456 {
5457         kvm_queue_exception(vcpu, UD_VECTOR);
5458         return 1;
5459 }
5460
5461 static int handle_encls(struct kvm_vcpu *vcpu)
5462 {
5463         /*
5464          * SGX virtualization is not yet supported.  There is no software
5465          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5466          * to prevent the guest from executing ENCLS.
5467          */
5468         kvm_queue_exception(vcpu, UD_VECTOR);
5469         return 1;
5470 }
5471
5472 /*
5473  * The exit handlers return 1 if the exit was handled fully and guest execution
5474  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5475  * to be done to userspace and return 0.
5476  */
5477 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5478         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5479         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5480         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5481         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5482         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5483         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5484         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5485         [EXIT_REASON_CPUID]                   = handle_cpuid,
5486         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5487         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5488         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5489         [EXIT_REASON_HLT]                     = handle_halt,
5490         [EXIT_REASON_INVD]                    = handle_invd,
5491         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5492         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5493         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5494         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5495         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5496         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5497         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5498         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5499         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5500         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5501         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5502         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5503         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5504         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5505         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5506         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5507         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5508         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5509         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5510         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5511         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5512         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5513         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5514         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5515         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5516         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
5517         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5518         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
5519         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5520         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5521         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
5522         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
5523         [EXIT_REASON_XSAVES]                  = handle_xsaves,
5524         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
5525         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5526         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5527         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5528         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5529         [EXIT_REASON_ENCLS]                   = handle_encls,
5530 };
5531
5532 static const int kvm_vmx_max_exit_handlers =
5533         ARRAY_SIZE(kvm_vmx_exit_handlers);
5534
5535 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5536 {
5537         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5538         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5539 }
5540
5541 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5542 {
5543         if (vmx->pml_pg) {
5544                 __free_page(vmx->pml_pg);
5545                 vmx->pml_pg = NULL;
5546         }
5547 }
5548
5549 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5550 {
5551         struct vcpu_vmx *vmx = to_vmx(vcpu);
5552         u64 *pml_buf;
5553         u16 pml_idx;
5554
5555         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5556
5557         /* Do nothing if PML buffer is empty */
5558         if (pml_idx == (PML_ENTITY_NUM - 1))
5559                 return;
5560
5561         /* PML index always points to next available PML buffer entity */
5562         if (pml_idx >= PML_ENTITY_NUM)
5563                 pml_idx = 0;
5564         else
5565                 pml_idx++;
5566
5567         pml_buf = page_address(vmx->pml_pg);
5568         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5569                 u64 gpa;
5570
5571                 gpa = pml_buf[pml_idx];
5572                 WARN_ON(gpa & (PAGE_SIZE - 1));
5573                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5574         }
5575
5576         /* reset PML index */
5577         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5578 }
5579
5580 /*
5581  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5582  * Called before reporting dirty_bitmap to userspace.
5583  */
5584 static void kvm_flush_pml_buffers(struct kvm *kvm)
5585 {
5586         int i;
5587         struct kvm_vcpu *vcpu;
5588         /*
5589          * We only need to kick vcpu out of guest mode here, as PML buffer
5590          * is flushed at beginning of all VMEXITs, and it's obvious that only
5591          * vcpus running in guest are possible to have unflushed GPAs in PML
5592          * buffer.
5593          */
5594         kvm_for_each_vcpu(i, vcpu, kvm)
5595                 kvm_vcpu_kick(vcpu);
5596 }
5597
5598 static void vmx_dump_sel(char *name, uint32_t sel)
5599 {
5600         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5601                name, vmcs_read16(sel),
5602                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5603                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5604                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5605 }
5606
5607 static void vmx_dump_dtsel(char *name, uint32_t limit)
5608 {
5609         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5610                name, vmcs_read32(limit),
5611                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5612 }
5613
5614 static void dump_vmcs(void)
5615 {
5616         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5617         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5618         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5619         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5620         u32 secondary_exec_control = 0;
5621         unsigned long cr4 = vmcs_readl(GUEST_CR4);
5622         u64 efer = vmcs_read64(GUEST_IA32_EFER);
5623         int i, n;
5624
5625         if (cpu_has_secondary_exec_ctrls())
5626                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5627
5628         pr_err("*** Guest State ***\n");
5629         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5630                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5631                vmcs_readl(CR0_GUEST_HOST_MASK));
5632         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5633                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5634         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5635         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5636             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5637         {
5638                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5639                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5640                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5641                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5642         }
5643         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5644                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5645         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5646                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5647         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5648                vmcs_readl(GUEST_SYSENTER_ESP),
5649                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5650         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5651         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5652         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5653         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5654         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5655         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5656         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5657         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5658         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5659         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5660         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5661             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5662                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
5663                        efer, vmcs_read64(GUEST_IA32_PAT));
5664         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5665                vmcs_read64(GUEST_IA32_DEBUGCTL),
5666                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5667         if (cpu_has_load_perf_global_ctrl() &&
5668             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5669                 pr_err("PerfGlobCtl = 0x%016llx\n",
5670                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5671         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5672                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5673         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5674                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5675                vmcs_read32(GUEST_ACTIVITY_STATE));
5676         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5677                 pr_err("InterruptStatus = %04x\n",
5678                        vmcs_read16(GUEST_INTR_STATUS));
5679
5680         pr_err("*** Host State ***\n");
5681         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5682                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5683         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5684                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5685                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5686                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5687                vmcs_read16(HOST_TR_SELECTOR));
5688         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5689                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5690                vmcs_readl(HOST_TR_BASE));
5691         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5692                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5693         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5694                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5695                vmcs_readl(HOST_CR4));
5696         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5697                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5698                vmcs_read32(HOST_IA32_SYSENTER_CS),
5699                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5700         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5701                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
5702                        vmcs_read64(HOST_IA32_EFER),
5703                        vmcs_read64(HOST_IA32_PAT));
5704         if (cpu_has_load_perf_global_ctrl() &&
5705             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5706                 pr_err("PerfGlobCtl = 0x%016llx\n",
5707                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5708
5709         pr_err("*** Control State ***\n");
5710         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5711                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5712         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5713         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5714                vmcs_read32(EXCEPTION_BITMAP),
5715                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5716                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5717         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5718                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5719                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5720                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5721         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5722                vmcs_read32(VM_EXIT_INTR_INFO),
5723                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5724                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5725         pr_err("        reason=%08x qualification=%016lx\n",
5726                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5727         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5728                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5729                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5730         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5731         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5732                 pr_err("TSC Multiplier = 0x%016llx\n",
5733                        vmcs_read64(TSC_MULTIPLIER));
5734         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
5735                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5736         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5737                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5738         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5739                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5740         n = vmcs_read32(CR3_TARGET_COUNT);
5741         for (i = 0; i + 1 < n; i += 4)
5742                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5743                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5744                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5745         if (i < n)
5746                 pr_err("CR3 target%u=%016lx\n",
5747                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5748         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5749                 pr_err("PLE Gap=%08x Window=%08x\n",
5750                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5751         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5752                 pr_err("Virtual processor ID = 0x%04x\n",
5753                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5754 }
5755
5756 /*
5757  * The guest has exited.  See if we can fix it or if we need userspace
5758  * assistance.
5759  */
5760 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5761 {
5762         struct vcpu_vmx *vmx = to_vmx(vcpu);
5763         u32 exit_reason = vmx->exit_reason;
5764         u32 vectoring_info = vmx->idt_vectoring_info;
5765
5766         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5767
5768         /*
5769          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5770          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5771          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5772          * mode as if vcpus is in root mode, the PML buffer must has been
5773          * flushed already.
5774          */
5775         if (enable_pml)
5776                 vmx_flush_pml_buffer(vcpu);
5777
5778         /* If guest state is invalid, start emulating */
5779         if (vmx->emulation_required)
5780                 return handle_invalid_guest_state(vcpu);
5781
5782         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5783                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5784
5785         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5786                 dump_vmcs();
5787                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5788                 vcpu->run->fail_entry.hardware_entry_failure_reason
5789                         = exit_reason;
5790                 return 0;
5791         }
5792
5793         if (unlikely(vmx->fail)) {
5794                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5795                 vcpu->run->fail_entry.hardware_entry_failure_reason
5796                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5797                 return 0;
5798         }
5799
5800         /*
5801          * Note:
5802          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5803          * delivery event since it indicates guest is accessing MMIO.
5804          * The vm-exit can be triggered again after return to guest that
5805          * will cause infinite loop.
5806          */
5807         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5808                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5809                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5810                         exit_reason != EXIT_REASON_PML_FULL &&
5811                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
5812                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5813                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5814                 vcpu->run->internal.ndata = 3;
5815                 vcpu->run->internal.data[0] = vectoring_info;
5816                 vcpu->run->internal.data[1] = exit_reason;
5817                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5818                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5819                         vcpu->run->internal.ndata++;
5820                         vcpu->run->internal.data[3] =
5821                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5822                 }
5823                 return 0;
5824         }
5825
5826         if (unlikely(!enable_vnmi &&
5827                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5828                 if (vmx_interrupt_allowed(vcpu)) {
5829                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5830                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5831                            vcpu->arch.nmi_pending) {
5832                         /*
5833                          * This CPU don't support us in finding the end of an
5834                          * NMI-blocked window if the guest runs with IRQs
5835                          * disabled. So we pull the trigger after 1 s of
5836                          * futile waiting, but inform the user about this.
5837                          */
5838                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5839                                "state on VCPU %d after 1 s timeout\n",
5840                                __func__, vcpu->vcpu_id);
5841                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5842                 }
5843         }
5844
5845         if (exit_reason < kvm_vmx_max_exit_handlers
5846             && kvm_vmx_exit_handlers[exit_reason])
5847                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5848         else {
5849                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5850                                 exit_reason);
5851                 kvm_queue_exception(vcpu, UD_VECTOR);
5852                 return 1;
5853         }
5854 }
5855
5856 /*
5857  * Software based L1D cache flush which is used when microcode providing
5858  * the cache control MSR is not loaded.
5859  *
5860  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5861  * flush it is required to read in 64 KiB because the replacement algorithm
5862  * is not exactly LRU. This could be sized at runtime via topology
5863  * information but as all relevant affected CPUs have 32KiB L1D cache size
5864  * there is no point in doing so.
5865  */
5866 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5867 {
5868         int size = PAGE_SIZE << L1D_CACHE_ORDER;
5869
5870         /*
5871          * This code is only executed when the the flush mode is 'cond' or
5872          * 'always'
5873          */
5874         if (static_branch_likely(&vmx_l1d_flush_cond)) {
5875                 bool flush_l1d;
5876
5877                 /*
5878                  * Clear the per-vcpu flush bit, it gets set again
5879                  * either from vcpu_run() or from one of the unsafe
5880                  * VMEXIT handlers.
5881                  */
5882                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5883                 vcpu->arch.l1tf_flush_l1d = false;
5884
5885                 /*
5886                  * Clear the per-cpu flush bit, it gets set again from
5887                  * the interrupt handlers.
5888                  */
5889                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5890                 kvm_clear_cpu_l1tf_flush_l1d();
5891
5892                 if (!flush_l1d)
5893                         return;
5894         }
5895
5896         vcpu->stat.l1d_flush++;
5897
5898         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5899                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5900                 return;
5901         }
5902
5903         asm volatile(
5904                 /* First ensure the pages are in the TLB */
5905                 "xorl   %%eax, %%eax\n"
5906                 ".Lpopulate_tlb:\n\t"
5907                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5908                 "addl   $4096, %%eax\n\t"
5909                 "cmpl   %%eax, %[size]\n\t"
5910                 "jne    .Lpopulate_tlb\n\t"
5911                 "xorl   %%eax, %%eax\n\t"
5912                 "cpuid\n\t"
5913                 /* Now fill the cache */
5914                 "xorl   %%eax, %%eax\n"
5915                 ".Lfill_cache:\n"
5916                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5917                 "addl   $64, %%eax\n\t"
5918                 "cmpl   %%eax, %[size]\n\t"
5919                 "jne    .Lfill_cache\n\t"
5920                 "lfence\n"
5921                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
5922                     [size] "r" (size)
5923                 : "eax", "ebx", "ecx", "edx");
5924 }
5925
5926 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5927 {
5928         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5929
5930         if (is_guest_mode(vcpu) &&
5931                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
5932                 return;
5933
5934         if (irr == -1 || tpr < irr) {
5935                 vmcs_write32(TPR_THRESHOLD, 0);
5936                 return;
5937         }
5938
5939         vmcs_write32(TPR_THRESHOLD, irr);
5940 }
5941
5942 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5943 {
5944         u32 sec_exec_control;
5945
5946         if (!lapic_in_kernel(vcpu))
5947                 return;
5948
5949         if (!flexpriority_enabled &&
5950             !cpu_has_vmx_virtualize_x2apic_mode())
5951                 return;
5952
5953         /* Postpone execution until vmcs01 is the current VMCS. */
5954         if (is_guest_mode(vcpu)) {
5955                 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
5956                 return;
5957         }
5958
5959         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5960         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
5961                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
5962
5963         switch (kvm_get_apic_mode(vcpu)) {
5964         case LAPIC_MODE_INVALID:
5965                 WARN_ONCE(true, "Invalid local APIC state");
5966         case LAPIC_MODE_DISABLED:
5967                 break;
5968         case LAPIC_MODE_XAPIC:
5969                 if (flexpriority_enabled) {
5970                         sec_exec_control |=
5971                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5972                         vmx_flush_tlb(vcpu, true);
5973                 }
5974                 break;
5975         case LAPIC_MODE_X2APIC:
5976                 if (cpu_has_vmx_virtualize_x2apic_mode())
5977                         sec_exec_control |=
5978                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5979                 break;
5980         }
5981         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
5982
5983         vmx_update_msr_bitmap(vcpu);
5984 }
5985
5986 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
5987 {
5988         if (!is_guest_mode(vcpu)) {
5989                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
5990                 vmx_flush_tlb(vcpu, true);
5991         }
5992 }
5993
5994 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5995 {
5996         u16 status;
5997         u8 old;
5998
5999         if (max_isr == -1)
6000                 max_isr = 0;
6001
6002         status = vmcs_read16(GUEST_INTR_STATUS);
6003         old = status >> 8;
6004         if (max_isr != old) {
6005                 status &= 0xff;
6006                 status |= max_isr << 8;
6007                 vmcs_write16(GUEST_INTR_STATUS, status);
6008         }
6009 }
6010
6011 static void vmx_set_rvi(int vector)
6012 {
6013         u16 status;
6014         u8 old;
6015
6016         if (vector == -1)
6017                 vector = 0;
6018
6019         status = vmcs_read16(GUEST_INTR_STATUS);
6020         old = (u8)status & 0xff;
6021         if ((u8)vector != old) {
6022                 status &= ~0xff;
6023                 status |= (u8)vector;
6024                 vmcs_write16(GUEST_INTR_STATUS, status);
6025         }
6026 }
6027
6028 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6029 {
6030         /*
6031          * When running L2, updating RVI is only relevant when
6032          * vmcs12 virtual-interrupt-delivery enabled.
6033          * However, it can be enabled only when L1 also
6034          * intercepts external-interrupts and in that case
6035          * we should not update vmcs02 RVI but instead intercept
6036          * interrupt. Therefore, do nothing when running L2.
6037          */
6038         if (!is_guest_mode(vcpu))
6039                 vmx_set_rvi(max_irr);
6040 }
6041
6042 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6043 {
6044         struct vcpu_vmx *vmx = to_vmx(vcpu);
6045         int max_irr;
6046         bool max_irr_updated;
6047
6048         WARN_ON(!vcpu->arch.apicv_active);
6049         if (pi_test_on(&vmx->pi_desc)) {
6050                 pi_clear_on(&vmx->pi_desc);
6051                 /*
6052                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
6053                  * But on x86 this is just a compiler barrier anyway.
6054                  */
6055                 smp_mb__after_atomic();
6056                 max_irr_updated =
6057                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6058
6059                 /*
6060                  * If we are running L2 and L1 has a new pending interrupt
6061                  * which can be injected, we should re-evaluate
6062                  * what should be done with this new L1 interrupt.
6063                  * If L1 intercepts external-interrupts, we should
6064                  * exit from L2 to L1. Otherwise, interrupt should be
6065                  * delivered directly to L2.
6066                  */
6067                 if (is_guest_mode(vcpu) && max_irr_updated) {
6068                         if (nested_exit_on_intr(vcpu))
6069                                 kvm_vcpu_exiting_guest_mode(vcpu);
6070                         else
6071                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6072                 }
6073         } else {
6074                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6075         }
6076         vmx_hwapic_irr_update(vcpu, max_irr);
6077         return max_irr;
6078 }
6079
6080 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6081 {
6082         if (!kvm_vcpu_apicv_active(vcpu))
6083                 return;
6084
6085         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6086         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6087         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6088         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6089 }
6090
6091 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6092 {
6093         struct vcpu_vmx *vmx = to_vmx(vcpu);
6094
6095         pi_clear_on(&vmx->pi_desc);
6096         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6097 }
6098
6099 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6100 {
6101         u32 exit_intr_info = 0;
6102         u16 basic_exit_reason = (u16)vmx->exit_reason;
6103
6104         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6105               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
6106                 return;
6107
6108         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6109                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6110         vmx->exit_intr_info = exit_intr_info;
6111
6112         /* if exit due to PF check for async PF */
6113         if (is_page_fault(exit_intr_info))
6114                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6115
6116         /* Handle machine checks before interrupts are enabled */
6117         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
6118             is_machine_check(exit_intr_info))
6119                 kvm_machine_check();
6120
6121         /* We need to handle NMIs before interrupts are enabled */
6122         if (is_nmi(exit_intr_info)) {
6123                 kvm_before_interrupt(&vmx->vcpu);
6124                 asm("int $2");
6125                 kvm_after_interrupt(&vmx->vcpu);
6126         }
6127 }
6128
6129 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6130 {
6131         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6132
6133         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6134                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6135                 unsigned int vector;
6136                 unsigned long entry;
6137                 gate_desc *desc;
6138                 struct vcpu_vmx *vmx = to_vmx(vcpu);
6139 #ifdef CONFIG_X86_64
6140                 unsigned long tmp;
6141 #endif
6142
6143                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
6144                 desc = (gate_desc *)vmx->host_idt_base + vector;
6145                 entry = gate_offset(desc);
6146                 asm volatile(
6147 #ifdef CONFIG_X86_64
6148                         "mov %%" _ASM_SP ", %[sp]\n\t"
6149                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6150                         "push $%c[ss]\n\t"
6151                         "push %[sp]\n\t"
6152 #endif
6153                         "pushf\n\t"
6154                         __ASM_SIZE(push) " $%c[cs]\n\t"
6155                         CALL_NOSPEC
6156                         :
6157 #ifdef CONFIG_X86_64
6158                         [sp]"=&r"(tmp),
6159 #endif
6160                         ASM_CALL_CONSTRAINT
6161                         :
6162                         THUNK_TARGET(entry),
6163                         [ss]"i"(__KERNEL_DS),
6164                         [cs]"i"(__KERNEL_CS)
6165                         );
6166         }
6167 }
6168 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
6169
6170 static bool vmx_has_emulated_msr(int index)
6171 {
6172         switch (index) {
6173         case MSR_IA32_SMBASE:
6174                 /*
6175                  * We cannot do SMM unless we can run the guest in big
6176                  * real mode.
6177                  */
6178                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6179         case MSR_AMD64_VIRT_SPEC_CTRL:
6180                 /* This is AMD only.  */
6181                 return false;
6182         default:
6183                 return true;
6184         }
6185 }
6186
6187 static bool vmx_pt_supported(void)
6188 {
6189         return pt_mode == PT_MODE_HOST_GUEST;
6190 }
6191
6192 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6193 {
6194         u32 exit_intr_info;
6195         bool unblock_nmi;
6196         u8 vector;
6197         bool idtv_info_valid;
6198
6199         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6200
6201         if (enable_vnmi) {
6202                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6203                         return;
6204                 /*
6205                  * Can't use vmx->exit_intr_info since we're not sure what
6206                  * the exit reason is.
6207                  */
6208                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6209                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6210                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6211                 /*
6212                  * SDM 3: 27.7.1.2 (September 2008)
6213                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6214                  * a guest IRET fault.
6215                  * SDM 3: 23.2.2 (September 2008)
6216                  * Bit 12 is undefined in any of the following cases:
6217                  *  If the VM exit sets the valid bit in the IDT-vectoring
6218                  *   information field.
6219                  *  If the VM exit is due to a double fault.
6220                  */
6221                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6222                     vector != DF_VECTOR && !idtv_info_valid)
6223                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6224                                       GUEST_INTR_STATE_NMI);
6225                 else
6226                         vmx->loaded_vmcs->nmi_known_unmasked =
6227                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6228                                   & GUEST_INTR_STATE_NMI);
6229         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6230                 vmx->loaded_vmcs->vnmi_blocked_time +=
6231                         ktime_to_ns(ktime_sub(ktime_get(),
6232                                               vmx->loaded_vmcs->entry_time));
6233 }
6234
6235 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6236                                       u32 idt_vectoring_info,
6237                                       int instr_len_field,
6238                                       int error_code_field)
6239 {
6240         u8 vector;
6241         int type;
6242         bool idtv_info_valid;
6243
6244         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6245
6246         vcpu->arch.nmi_injected = false;
6247         kvm_clear_exception_queue(vcpu);
6248         kvm_clear_interrupt_queue(vcpu);
6249
6250         if (!idtv_info_valid)
6251                 return;
6252
6253         kvm_make_request(KVM_REQ_EVENT, vcpu);
6254
6255         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6256         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6257
6258         switch (type) {
6259         case INTR_TYPE_NMI_INTR:
6260                 vcpu->arch.nmi_injected = true;
6261                 /*
6262                  * SDM 3: 27.7.1.2 (September 2008)
6263                  * Clear bit "block by NMI" before VM entry if a NMI
6264                  * delivery faulted.
6265                  */
6266                 vmx_set_nmi_mask(vcpu, false);
6267                 break;
6268         case INTR_TYPE_SOFT_EXCEPTION:
6269                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6270                 /* fall through */
6271         case INTR_TYPE_HARD_EXCEPTION:
6272                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6273                         u32 err = vmcs_read32(error_code_field);
6274                         kvm_requeue_exception_e(vcpu, vector, err);
6275                 } else
6276                         kvm_requeue_exception(vcpu, vector);
6277                 break;
6278         case INTR_TYPE_SOFT_INTR:
6279                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6280                 /* fall through */
6281         case INTR_TYPE_EXT_INTR:
6282                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6283                 break;
6284         default:
6285                 break;
6286         }
6287 }
6288
6289 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6290 {
6291         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6292                                   VM_EXIT_INSTRUCTION_LEN,
6293                                   IDT_VECTORING_ERROR_CODE);
6294 }
6295
6296 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6297 {
6298         __vmx_complete_interrupts(vcpu,
6299                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6300                                   VM_ENTRY_INSTRUCTION_LEN,
6301                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6302
6303         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6304 }
6305
6306 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6307 {
6308         int i, nr_msrs;
6309         struct perf_guest_switch_msr *msrs;
6310
6311         msrs = perf_guest_get_msrs(&nr_msrs);
6312
6313         if (!msrs)
6314                 return;
6315
6316         for (i = 0; i < nr_msrs; i++)
6317                 if (msrs[i].host == msrs[i].guest)
6318                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6319                 else
6320                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6321                                         msrs[i].host, false);
6322 }
6323
6324 static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
6325 {
6326         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
6327         if (!vmx->loaded_vmcs->hv_timer_armed)
6328                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
6329                               PIN_BASED_VMX_PREEMPTION_TIMER);
6330         vmx->loaded_vmcs->hv_timer_armed = true;
6331 }
6332
6333 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6334 {
6335         struct vcpu_vmx *vmx = to_vmx(vcpu);
6336         u64 tscl;
6337         u32 delta_tsc;
6338
6339         if (vmx->req_immediate_exit) {
6340                 vmx_arm_hv_timer(vmx, 0);
6341                 return;
6342         }
6343
6344         if (vmx->hv_deadline_tsc != -1) {
6345                 tscl = rdtsc();
6346                 if (vmx->hv_deadline_tsc > tscl)
6347                         /* set_hv_timer ensures the delta fits in 32-bits */
6348                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6349                                 cpu_preemption_timer_multi);
6350                 else
6351                         delta_tsc = 0;
6352
6353                 vmx_arm_hv_timer(vmx, delta_tsc);
6354                 return;
6355         }
6356
6357         if (vmx->loaded_vmcs->hv_timer_armed)
6358                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
6359                                 PIN_BASED_VMX_PREEMPTION_TIMER);
6360         vmx->loaded_vmcs->hv_timer_armed = false;
6361 }
6362
6363 static void __vmx_vcpu_run(struct kvm_vcpu *vcpu, struct vcpu_vmx *vmx)
6364 {
6365         unsigned long evmcs_rsp;
6366
6367         vmx->__launched = vmx->loaded_vmcs->launched;
6368
6369         evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
6370                 (unsigned long)&current_evmcs->host_rsp : 0;
6371
6372         if (static_branch_unlikely(&vmx_l1d_should_flush))
6373                 vmx_l1d_flush(vcpu);
6374
6375         asm(
6376                 /* Store host registers */
6377                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6378                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6379                 "push %%" _ASM_CX " \n\t"
6380                 "sub $%c[wordsize], %%" _ASM_SP "\n\t" /* temporarily adjust RSP for CALL */
6381                 "cmp %%" _ASM_SP ", %c[host_rsp](%%" _ASM_CX ") \n\t"
6382                 "je 1f \n\t"
6383                 "mov %%" _ASM_SP ", %c[host_rsp](%%" _ASM_CX ") \n\t"
6384                 /* Avoid VMWRITE when Enlightened VMCS is in use */
6385                 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
6386                 "jz 2f \n\t"
6387                 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
6388                 "jmp 1f \n\t"
6389                 "2: \n\t"
6390                 __ex("vmwrite %%" _ASM_SP ", %%" _ASM_DX) "\n\t"
6391                 "1: \n\t"
6392                 "add $%c[wordsize], %%" _ASM_SP "\n\t" /* un-adjust RSP */
6393
6394                 /* Reload cr2 if changed */
6395                 "mov %c[cr2](%%" _ASM_CX "), %%" _ASM_AX " \n\t"
6396                 "mov %%cr2, %%" _ASM_DX " \n\t"
6397                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
6398                 "je 3f \n\t"
6399                 "mov %%" _ASM_AX", %%cr2 \n\t"
6400                 "3: \n\t"
6401                 /* Check if vmlaunch or vmresume is needed */
6402                 "cmpl $0, %c[launched](%%" _ASM_CX ") \n\t"
6403                 /* Load guest registers.  Don't clobber flags. */
6404                 "mov %c[rax](%%" _ASM_CX "), %%" _ASM_AX " \n\t"
6405                 "mov %c[rbx](%%" _ASM_CX "), %%" _ASM_BX " \n\t"
6406                 "mov %c[rdx](%%" _ASM_CX "), %%" _ASM_DX " \n\t"
6407                 "mov %c[rsi](%%" _ASM_CX "), %%" _ASM_SI " \n\t"
6408                 "mov %c[rdi](%%" _ASM_CX "), %%" _ASM_DI " \n\t"
6409                 "mov %c[rbp](%%" _ASM_CX "), %%" _ASM_BP " \n\t"
6410 #ifdef CONFIG_X86_64
6411                 "mov %c[r8](%%" _ASM_CX "),  %%r8  \n\t"
6412                 "mov %c[r9](%%" _ASM_CX "),  %%r9  \n\t"
6413                 "mov %c[r10](%%" _ASM_CX "), %%r10 \n\t"
6414                 "mov %c[r11](%%" _ASM_CX "), %%r11 \n\t"
6415                 "mov %c[r12](%%" _ASM_CX "), %%r12 \n\t"
6416                 "mov %c[r13](%%" _ASM_CX "), %%r13 \n\t"
6417                 "mov %c[r14](%%" _ASM_CX "), %%r14 \n\t"
6418                 "mov %c[r15](%%" _ASM_CX "), %%r15 \n\t"
6419 #endif
6420                 /* Load guest RCX.  This kills the vmx_vcpu pointer! */
6421                 "mov %c[rcx](%%" _ASM_CX "), %%" _ASM_CX " \n\t"
6422
6423                 /* Enter guest mode */
6424                 "call vmx_vmenter\n\t"
6425
6426                 /* Save guest's RCX to the stack placeholder (see above) */
6427                 "mov %%" _ASM_CX ", %c[wordsize](%%" _ASM_SP ") \n\t"
6428
6429                 /* Load host's RCX, i.e. the vmx_vcpu pointer */
6430                 "pop %%" _ASM_CX " \n\t"
6431
6432                 /* Set vmx->fail based on EFLAGS.{CF,ZF} */
6433                 "setbe %c[fail](%%" _ASM_CX ")\n\t"
6434
6435                 /* Save all guest registers, including RCX from the stack */
6436                 "mov %%" _ASM_AX ", %c[rax](%%" _ASM_CX ") \n\t"
6437                 "mov %%" _ASM_BX ", %c[rbx](%%" _ASM_CX ") \n\t"
6438                 __ASM_SIZE(pop) " %c[rcx](%%" _ASM_CX ") \n\t"
6439                 "mov %%" _ASM_DX ", %c[rdx](%%" _ASM_CX ") \n\t"
6440                 "mov %%" _ASM_SI ", %c[rsi](%%" _ASM_CX ") \n\t"
6441                 "mov %%" _ASM_DI ", %c[rdi](%%" _ASM_CX ") \n\t"
6442                 "mov %%" _ASM_BP ", %c[rbp](%%" _ASM_CX ") \n\t"
6443 #ifdef CONFIG_X86_64
6444                 "mov %%r8,  %c[r8](%%" _ASM_CX ") \n\t"
6445                 "mov %%r9,  %c[r9](%%" _ASM_CX ") \n\t"
6446                 "mov %%r10, %c[r10](%%" _ASM_CX ") \n\t"
6447                 "mov %%r11, %c[r11](%%" _ASM_CX ") \n\t"
6448                 "mov %%r12, %c[r12](%%" _ASM_CX ") \n\t"
6449                 "mov %%r13, %c[r13](%%" _ASM_CX ") \n\t"
6450                 "mov %%r14, %c[r14](%%" _ASM_CX ") \n\t"
6451                 "mov %%r15, %c[r15](%%" _ASM_CX ") \n\t"
6452                 /*
6453                 * Clear host registers marked as clobbered to prevent
6454                 * speculative use.
6455                 */
6456                 "xor %%r8d,  %%r8d \n\t"
6457                 "xor %%r9d,  %%r9d \n\t"
6458                 "xor %%r10d, %%r10d \n\t"
6459                 "xor %%r11d, %%r11d \n\t"
6460                 "xor %%r12d, %%r12d \n\t"
6461                 "xor %%r13d, %%r13d \n\t"
6462                 "xor %%r14d, %%r14d \n\t"
6463                 "xor %%r15d, %%r15d \n\t"
6464 #endif
6465                 "mov %%cr2, %%" _ASM_AX "   \n\t"
6466                 "mov %%" _ASM_AX ", %c[cr2](%%" _ASM_CX ") \n\t"
6467
6468                 "xor %%eax, %%eax \n\t"
6469                 "xor %%ebx, %%ebx \n\t"
6470                 "xor %%esi, %%esi \n\t"
6471                 "xor %%edi, %%edi \n\t"
6472                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
6473               : ASM_CALL_CONSTRAINT
6474               : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
6475                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6476                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6477                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6478                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6479                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6480                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6481                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6482                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6483                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6484                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6485 #ifdef CONFIG_X86_64
6486                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6487                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6488                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6489                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6490                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6491                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6492                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6493                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6494 #endif
6495                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6496                 [wordsize]"i"(sizeof(ulong))
6497               : "cc", "memory"
6498 #ifdef CONFIG_X86_64
6499                 , "rax", "rbx", "rdi"
6500                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6501 #else
6502                 , "eax", "ebx", "edi"
6503 #endif
6504               );
6505 }
6506 STACK_FRAME_NON_STANDARD(__vmx_vcpu_run);
6507
6508 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6509 {
6510         struct vcpu_vmx *vmx = to_vmx(vcpu);
6511         unsigned long cr3, cr4;
6512
6513         /* Record the guest's net vcpu time for enforced NMI injections. */
6514         if (unlikely(!enable_vnmi &&
6515                      vmx->loaded_vmcs->soft_vnmi_blocked))
6516                 vmx->loaded_vmcs->entry_time = ktime_get();
6517
6518         /* Don't enter VMX if guest state is invalid, let the exit handler
6519            start emulation until we arrive back to a valid state */
6520         if (vmx->emulation_required)
6521                 return;
6522
6523         if (vmx->ple_window_dirty) {
6524                 vmx->ple_window_dirty = false;
6525                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6526         }
6527
6528         if (vmx->nested.need_vmcs12_sync)
6529                 nested_sync_from_vmcs12(vcpu);
6530
6531         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6532                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6533         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6534                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6535
6536         cr3 = __get_current_cr3_fast();
6537         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6538                 vmcs_writel(HOST_CR3, cr3);
6539                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6540         }
6541
6542         cr4 = cr4_read_shadow();
6543         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6544                 vmcs_writel(HOST_CR4, cr4);
6545                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6546         }
6547
6548         /* When single-stepping over STI and MOV SS, we must clear the
6549          * corresponding interruptibility bits in the guest state. Otherwise
6550          * vmentry fails as it then expects bit 14 (BS) in pending debug
6551          * exceptions being set, but that's not correct for the guest debugging
6552          * case. */
6553         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6554                 vmx_set_interrupt_shadow(vcpu, 0);
6555
6556         if (static_cpu_has(X86_FEATURE_PKU) &&
6557             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6558             vcpu->arch.pkru != vmx->host_pkru)
6559                 __write_pkru(vcpu->arch.pkru);
6560
6561         pt_guest_enter(vmx);
6562
6563         atomic_switch_perf_msrs(vmx);
6564
6565         vmx_update_hv_timer(vcpu);
6566
6567         /*
6568          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6569          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6570          * is no need to worry about the conditional branch over the wrmsr
6571          * being speculatively taken.
6572          */
6573         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6574
6575         __vmx_vcpu_run(vcpu, vmx);
6576
6577         /*
6578          * We do not use IBRS in the kernel. If this vCPU has used the
6579          * SPEC_CTRL MSR it may have left it on; save the value and
6580          * turn it off. This is much more efficient than blindly adding
6581          * it to the atomic save/restore list. Especially as the former
6582          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6583          *
6584          * For non-nested case:
6585          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6586          * save it.
6587          *
6588          * For nested case:
6589          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6590          * save it.
6591          */
6592         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6593                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6594
6595         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6596
6597         /* Eliminate branch target predictions from guest mode */
6598         vmexit_fill_RSB();
6599
6600         /* All fields are clean at this point */
6601         if (static_branch_unlikely(&enable_evmcs))
6602                 current_evmcs->hv_clean_fields |=
6603                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6604
6605         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6606         if (vmx->host_debugctlmsr)
6607                 update_debugctlmsr(vmx->host_debugctlmsr);
6608
6609 #ifndef CONFIG_X86_64
6610         /*
6611          * The sysexit path does not restore ds/es, so we must set them to
6612          * a reasonable value ourselves.
6613          *
6614          * We can't defer this to vmx_prepare_switch_to_host() since that
6615          * function may be executed in interrupt context, which saves and
6616          * restore segments around it, nullifying its effect.
6617          */
6618         loadsegment(ds, __USER_DS);
6619         loadsegment(es, __USER_DS);
6620 #endif
6621
6622         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6623                                   | (1 << VCPU_EXREG_RFLAGS)
6624                                   | (1 << VCPU_EXREG_PDPTR)
6625                                   | (1 << VCPU_EXREG_SEGMENTS)
6626                                   | (1 << VCPU_EXREG_CR3));
6627         vcpu->arch.regs_dirty = 0;
6628
6629         pt_guest_exit(vmx);
6630
6631         /*
6632          * eager fpu is enabled if PKEY is supported and CR4 is switched
6633          * back on host, so it is safe to read guest PKRU from current
6634          * XSAVE.
6635          */
6636         if (static_cpu_has(X86_FEATURE_PKU) &&
6637             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6638                 vcpu->arch.pkru = __read_pkru();
6639                 if (vcpu->arch.pkru != vmx->host_pkru)
6640                         __write_pkru(vmx->host_pkru);
6641         }
6642
6643         vmx->nested.nested_run_pending = 0;
6644         vmx->idt_vectoring_info = 0;
6645
6646         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6647         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6648                 return;
6649
6650         vmx->loaded_vmcs->launched = 1;
6651         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6652
6653         vmx_complete_atomic_exit(vmx);
6654         vmx_recover_nmi_blocking(vmx);
6655         vmx_complete_interrupts(vmx);
6656 }
6657
6658 static struct kvm *vmx_vm_alloc(void)
6659 {
6660         struct kvm_vmx *kvm_vmx = vzalloc(sizeof(struct kvm_vmx));
6661         return &kvm_vmx->kvm;
6662 }
6663
6664 static void vmx_vm_free(struct kvm *kvm)
6665 {
6666         vfree(to_kvm_vmx(kvm));
6667 }
6668
6669 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6670 {
6671         struct vcpu_vmx *vmx = to_vmx(vcpu);
6672
6673         if (enable_pml)
6674                 vmx_destroy_pml_buffer(vmx);
6675         free_vpid(vmx->vpid);
6676         leave_guest_mode(vcpu);
6677         nested_vmx_free_vcpu(vcpu);
6678         free_loaded_vmcs(vmx->loaded_vmcs);
6679         kfree(vmx->guest_msrs);
6680         kvm_vcpu_uninit(vcpu);
6681         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6682         kmem_cache_free(kvm_vcpu_cache, vmx);
6683 }
6684
6685 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6686 {
6687         int err;
6688         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6689         unsigned long *msr_bitmap;
6690         int cpu;
6691
6692         if (!vmx)
6693                 return ERR_PTR(-ENOMEM);
6694
6695         vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, GFP_KERNEL);
6696         if (!vmx->vcpu.arch.guest_fpu) {
6697                 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6698                 err = -ENOMEM;
6699                 goto free_partial_vcpu;
6700         }
6701
6702         vmx->vpid = allocate_vpid();
6703
6704         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6705         if (err)
6706                 goto free_vcpu;
6707
6708         err = -ENOMEM;
6709
6710         /*
6711          * If PML is turned on, failure on enabling PML just results in failure
6712          * of creating the vcpu, therefore we can simplify PML logic (by
6713          * avoiding dealing with cases, such as enabling PML partially on vcpus
6714          * for the guest, etc.
6715          */
6716         if (enable_pml) {
6717                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
6718                 if (!vmx->pml_pg)
6719                         goto uninit_vcpu;
6720         }
6721
6722         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6723         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6724                      > PAGE_SIZE);
6725
6726         if (!vmx->guest_msrs)
6727                 goto free_pml;
6728
6729         err = alloc_loaded_vmcs(&vmx->vmcs01);
6730         if (err < 0)
6731                 goto free_msrs;
6732
6733         msr_bitmap = vmx->vmcs01.msr_bitmap;
6734         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6735         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6736         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6737         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6738         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6739         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6740         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6741         vmx->msr_bitmap_mode = 0;
6742
6743         vmx->loaded_vmcs = &vmx->vmcs01;
6744         cpu = get_cpu();
6745         vmx_vcpu_load(&vmx->vcpu, cpu);
6746         vmx->vcpu.cpu = cpu;
6747         vmx_vcpu_setup(vmx);
6748         vmx_vcpu_put(&vmx->vcpu);
6749         put_cpu();
6750         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6751                 err = alloc_apic_access_page(kvm);
6752                 if (err)
6753                         goto free_vmcs;
6754         }
6755
6756         if (enable_ept && !enable_unrestricted_guest) {
6757                 err = init_rmode_identity_map(kvm);
6758                 if (err)
6759                         goto free_vmcs;
6760         }
6761
6762         if (nested)
6763                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6764                                            vmx_capability.ept,
6765                                            kvm_vcpu_apicv_active(&vmx->vcpu));
6766         else
6767                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6768
6769         vmx->nested.posted_intr_nv = -1;
6770         vmx->nested.current_vmptr = -1ull;
6771
6772         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
6773
6774         /*
6775          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6776          * or POSTED_INTR_WAKEUP_VECTOR.
6777          */
6778         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6779         vmx->pi_desc.sn = 1;
6780
6781         vmx->ept_pointer = INVALID_PAGE;
6782
6783         return &vmx->vcpu;
6784
6785 free_vmcs:
6786         free_loaded_vmcs(vmx->loaded_vmcs);
6787 free_msrs:
6788         kfree(vmx->guest_msrs);
6789 free_pml:
6790         vmx_destroy_pml_buffer(vmx);
6791 uninit_vcpu:
6792         kvm_vcpu_uninit(&vmx->vcpu);
6793 free_vcpu:
6794         free_vpid(vmx->vpid);
6795         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6796 free_partial_vcpu:
6797         kmem_cache_free(kvm_vcpu_cache, vmx);
6798         return ERR_PTR(err);
6799 }
6800
6801 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
6802 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
6803
6804 static int vmx_vm_init(struct kvm *kvm)
6805 {
6806         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6807
6808         if (!ple_gap)
6809                 kvm->arch.pause_in_guest = true;
6810
6811         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6812                 switch (l1tf_mitigation) {
6813                 case L1TF_MITIGATION_OFF:
6814                 case L1TF_MITIGATION_FLUSH_NOWARN:
6815                         /* 'I explicitly don't care' is set */
6816                         break;
6817                 case L1TF_MITIGATION_FLUSH:
6818                 case L1TF_MITIGATION_FLUSH_NOSMT:
6819                 case L1TF_MITIGATION_FULL:
6820                         /*
6821                          * Warn upon starting the first VM in a potentially
6822                          * insecure environment.
6823                          */
6824                         if (sched_smt_active())
6825                                 pr_warn_once(L1TF_MSG_SMT);
6826                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6827                                 pr_warn_once(L1TF_MSG_L1D);
6828                         break;
6829                 case L1TF_MITIGATION_FULL_FORCE:
6830                         /* Flush is enforced */
6831                         break;
6832                 }
6833         }
6834         return 0;
6835 }
6836
6837 static void __init vmx_check_processor_compat(void *rtn)
6838 {
6839         struct vmcs_config vmcs_conf;
6840         struct vmx_capability vmx_cap;
6841
6842         *(int *)rtn = 0;
6843         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6844                 *(int *)rtn = -EIO;
6845         if (nested)
6846                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6847                                            enable_apicv);
6848         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6849                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6850                                 smp_processor_id());
6851                 *(int *)rtn = -EIO;
6852         }
6853 }
6854
6855 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6856 {
6857         u8 cache;
6858         u64 ipat = 0;
6859
6860         /* For VT-d and EPT combination
6861          * 1. MMIO: always map as UC
6862          * 2. EPT with VT-d:
6863          *   a. VT-d without snooping control feature: can't guarantee the
6864          *      result, try to trust guest.
6865          *   b. VT-d with snooping control feature: snooping control feature of
6866          *      VT-d engine can guarantee the cache correctness. Just set it
6867          *      to WB to keep consistent with host. So the same as item 3.
6868          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6869          *    consistent with host MTRR
6870          */
6871         if (is_mmio) {
6872                 cache = MTRR_TYPE_UNCACHABLE;
6873                 goto exit;
6874         }
6875
6876         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6877                 ipat = VMX_EPT_IPAT_BIT;
6878                 cache = MTRR_TYPE_WRBACK;
6879                 goto exit;
6880         }
6881
6882         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6883                 ipat = VMX_EPT_IPAT_BIT;
6884                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6885                         cache = MTRR_TYPE_WRBACK;
6886                 else
6887                         cache = MTRR_TYPE_UNCACHABLE;
6888                 goto exit;
6889         }
6890
6891         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6892
6893 exit:
6894         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6895 }
6896
6897 static int vmx_get_lpage_level(void)
6898 {
6899         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6900                 return PT_DIRECTORY_LEVEL;
6901         else
6902                 /* For shadow and EPT supported 1GB page */
6903                 return PT_PDPE_LEVEL;
6904 }
6905
6906 static void vmcs_set_secondary_exec_control(u32 new_ctl)
6907 {
6908         /*
6909          * These bits in the secondary execution controls field
6910          * are dynamic, the others are mostly based on the hypervisor
6911          * architecture and the guest's CPUID.  Do not touch the
6912          * dynamic bits.
6913          */
6914         u32 mask =
6915                 SECONDARY_EXEC_SHADOW_VMCS |
6916                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6917                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6918                 SECONDARY_EXEC_DESC;
6919
6920         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6921
6922         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6923                      (new_ctl & ~mask) | (cur_ctl & mask));
6924 }
6925
6926 /*
6927  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6928  * (indicating "allowed-1") if they are supported in the guest's CPUID.
6929  */
6930 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6931 {
6932         struct vcpu_vmx *vmx = to_vmx(vcpu);
6933         struct kvm_cpuid_entry2 *entry;
6934
6935         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6936         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6937
6938 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
6939         if (entry && (entry->_reg & (_cpuid_mask)))                     \
6940                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
6941 } while (0)
6942
6943         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6944         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
6945         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
6946         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
6947         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
6948         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
6949         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
6950         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
6951         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
6952         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
6953         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6954         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
6955         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
6956         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
6957         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
6958
6959         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6960         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
6961         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
6962         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
6963         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
6964         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
6965
6966 #undef cr4_fixed1_update
6967 }
6968
6969 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6970 {
6971         struct vcpu_vmx *vmx = to_vmx(vcpu);
6972
6973         if (kvm_mpx_supported()) {
6974                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
6975
6976                 if (mpx_enabled) {
6977                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6978                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6979                 } else {
6980                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6981                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6982                 }
6983         }
6984 }
6985
6986 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6987 {
6988         struct vcpu_vmx *vmx = to_vmx(vcpu);
6989         struct kvm_cpuid_entry2 *best = NULL;
6990         int i;
6991
6992         for (i = 0; i < PT_CPUID_LEAVES; i++) {
6993                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
6994                 if (!best)
6995                         return;
6996                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
6997                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
6998                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
6999                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7000         }
7001
7002         /* Get the number of configurable Address Ranges for filtering */
7003         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7004                                                 PT_CAP_num_address_ranges);
7005
7006         /* Initialize and clear the no dependency bits */
7007         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7008                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7009
7010         /*
7011          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7012          * will inject an #GP
7013          */
7014         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7015                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7016
7017         /*
7018          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7019          * PSBFreq can be set
7020          */
7021         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7022                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7023                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7024
7025         /*
7026          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7027          * MTCFreq can be set
7028          */
7029         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7030                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7031                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7032
7033         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7034         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7035                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7036                                                         RTIT_CTL_PTW_EN);
7037
7038         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7039         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7040                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7041
7042         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7043         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7044                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7045
7046         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7047         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7048                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7049
7050         /* unmask address range configure area */
7051         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7052                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7053 }
7054
7055 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7056 {
7057         struct vcpu_vmx *vmx = to_vmx(vcpu);
7058
7059         if (cpu_has_secondary_exec_ctrls()) {
7060                 vmx_compute_secondary_exec_control(vmx);
7061                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
7062         }
7063
7064         if (nested_vmx_allowed(vcpu))
7065                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7066                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7067         else
7068                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7069                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7070
7071         if (nested_vmx_allowed(vcpu)) {
7072                 nested_vmx_cr_fixed1_bits_update(vcpu);
7073                 nested_vmx_entry_exit_ctls_update(vcpu);
7074         }
7075
7076         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7077                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7078                 update_intel_pt_cfg(vcpu);
7079 }
7080
7081 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7082 {
7083         if (func == 1 && nested)
7084                 entry->ecx |= bit(X86_FEATURE_VMX);
7085 }
7086
7087 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7088 {
7089         to_vmx(vcpu)->req_immediate_exit = true;
7090 }
7091
7092 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7093                                struct x86_instruction_info *info,
7094                                enum x86_intercept_stage stage)
7095 {
7096         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7097         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7098
7099         /*
7100          * RDPID causes #UD if disabled through secondary execution controls.
7101          * Because it is marked as EmulateOnUD, we need to intercept it here.
7102          */
7103         if (info->intercept == x86_intercept_rdtscp &&
7104             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7105                 ctxt->exception.vector = UD_VECTOR;
7106                 ctxt->exception.error_code_valid = false;
7107                 return X86EMUL_PROPAGATE_FAULT;
7108         }
7109
7110         /* TODO: check more intercepts... */
7111         return X86EMUL_CONTINUE;
7112 }
7113
7114 #ifdef CONFIG_X86_64
7115 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7116 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7117                                   u64 divisor, u64 *result)
7118 {
7119         u64 low = a << shift, high = a >> (64 - shift);
7120
7121         /* To avoid the overflow on divq */
7122         if (high >= divisor)
7123                 return 1;
7124
7125         /* Low hold the result, high hold rem which is discarded */
7126         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7127             "rm" (divisor), "0" (low), "1" (high));
7128         *result = low;
7129
7130         return 0;
7131 }
7132
7133 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
7134 {
7135         struct vcpu_vmx *vmx;
7136         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7137
7138         if (kvm_mwait_in_guest(vcpu->kvm))
7139                 return -EOPNOTSUPP;
7140
7141         vmx = to_vmx(vcpu);
7142         tscl = rdtsc();
7143         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7144         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7145         lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns);
7146
7147         if (delta_tsc > lapic_timer_advance_cycles)
7148                 delta_tsc -= lapic_timer_advance_cycles;
7149         else
7150                 delta_tsc = 0;
7151
7152         /* Convert to host delta tsc if tsc scaling is enabled */
7153         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7154                         u64_shl_div_u64(delta_tsc,
7155                                 kvm_tsc_scaling_ratio_frac_bits,
7156                                 vcpu->arch.tsc_scaling_ratio,
7157                                 &delta_tsc))
7158                 return -ERANGE;
7159
7160         /*
7161          * If the delta tsc can't fit in the 32 bit after the multi shift,
7162          * we can't use the preemption timer.
7163          * It's possible that it fits on later vmentries, but checking
7164          * on every vmentry is costly so we just use an hrtimer.
7165          */
7166         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7167                 return -ERANGE;
7168
7169         vmx->hv_deadline_tsc = tscl + delta_tsc;
7170         return delta_tsc == 0;
7171 }
7172
7173 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7174 {
7175         to_vmx(vcpu)->hv_deadline_tsc = -1;
7176 }
7177 #endif
7178
7179 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7180 {
7181         if (!kvm_pause_in_guest(vcpu->kvm))
7182                 shrink_ple_window(vcpu);
7183 }
7184
7185 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7186                                      struct kvm_memory_slot *slot)
7187 {
7188         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7189         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7190 }
7191
7192 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7193                                        struct kvm_memory_slot *slot)
7194 {
7195         kvm_mmu_slot_set_dirty(kvm, slot);
7196 }
7197
7198 static void vmx_flush_log_dirty(struct kvm *kvm)
7199 {
7200         kvm_flush_pml_buffers(kvm);
7201 }
7202
7203 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7204 {
7205         struct vmcs12 *vmcs12;
7206         struct vcpu_vmx *vmx = to_vmx(vcpu);
7207         gpa_t gpa;
7208         struct page *page = NULL;
7209         u64 *pml_address;
7210
7211         if (is_guest_mode(vcpu)) {
7212                 WARN_ON_ONCE(vmx->nested.pml_full);
7213
7214                 /*
7215                  * Check if PML is enabled for the nested guest.
7216                  * Whether eptp bit 6 is set is already checked
7217                  * as part of A/D emulation.
7218                  */
7219                 vmcs12 = get_vmcs12(vcpu);
7220                 if (!nested_cpu_has_pml(vmcs12))
7221                         return 0;
7222
7223                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7224                         vmx->nested.pml_full = true;
7225                         return 1;
7226                 }
7227
7228                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7229
7230                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
7231                 if (is_error_page(page))
7232                         return 0;
7233
7234                 pml_address = kmap(page);
7235                 pml_address[vmcs12->guest_pml_index--] = gpa;
7236                 kunmap(page);
7237                 kvm_release_page_clean(page);
7238         }
7239
7240         return 0;
7241 }
7242
7243 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7244                                            struct kvm_memory_slot *memslot,
7245                                            gfn_t offset, unsigned long mask)
7246 {
7247         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7248 }
7249
7250 static void __pi_post_block(struct kvm_vcpu *vcpu)
7251 {
7252         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7253         struct pi_desc old, new;
7254         unsigned int dest;
7255
7256         do {
7257                 old.control = new.control = pi_desc->control;
7258                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7259                      "Wakeup handler not enabled while the VCPU is blocked\n");
7260
7261                 dest = cpu_physical_id(vcpu->cpu);
7262
7263                 if (x2apic_enabled())
7264                         new.ndst = dest;
7265                 else
7266                         new.ndst = (dest << 8) & 0xFF00;
7267
7268                 /* set 'NV' to 'notification vector' */
7269                 new.nv = POSTED_INTR_VECTOR;
7270         } while (cmpxchg64(&pi_desc->control, old.control,
7271                            new.control) != old.control);
7272
7273         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7274                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7275                 list_del(&vcpu->blocked_vcpu_list);
7276                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7277                 vcpu->pre_pcpu = -1;
7278         }
7279 }
7280
7281 /*
7282  * This routine does the following things for vCPU which is going
7283  * to be blocked if VT-d PI is enabled.
7284  * - Store the vCPU to the wakeup list, so when interrupts happen
7285  *   we can find the right vCPU to wake up.
7286  * - Change the Posted-interrupt descriptor as below:
7287  *      'NDST' <-- vcpu->pre_pcpu
7288  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7289  * - If 'ON' is set during this process, which means at least one
7290  *   interrupt is posted for this vCPU, we cannot block it, in
7291  *   this case, return 1, otherwise, return 0.
7292  *
7293  */
7294 static int pi_pre_block(struct kvm_vcpu *vcpu)
7295 {
7296         unsigned int dest;
7297         struct pi_desc old, new;
7298         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7299
7300         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7301                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
7302                 !kvm_vcpu_apicv_active(vcpu))
7303                 return 0;
7304
7305         WARN_ON(irqs_disabled());
7306         local_irq_disable();
7307         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7308                 vcpu->pre_pcpu = vcpu->cpu;
7309                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7310                 list_add_tail(&vcpu->blocked_vcpu_list,
7311                               &per_cpu(blocked_vcpu_on_cpu,
7312                                        vcpu->pre_pcpu));
7313                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7314         }
7315
7316         do {
7317                 old.control = new.control = pi_desc->control;
7318
7319                 WARN((pi_desc->sn == 1),
7320                      "Warning: SN field of posted-interrupts "
7321                      "is set before blocking\n");
7322
7323                 /*
7324                  * Since vCPU can be preempted during this process,
7325                  * vcpu->cpu could be different with pre_pcpu, we
7326                  * need to set pre_pcpu as the destination of wakeup
7327                  * notification event, then we can find the right vCPU
7328                  * to wakeup in wakeup handler if interrupts happen
7329                  * when the vCPU is in blocked state.
7330                  */
7331                 dest = cpu_physical_id(vcpu->pre_pcpu);
7332
7333                 if (x2apic_enabled())
7334                         new.ndst = dest;
7335                 else
7336                         new.ndst = (dest << 8) & 0xFF00;
7337
7338                 /* set 'NV' to 'wakeup vector' */
7339                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7340         } while (cmpxchg64(&pi_desc->control, old.control,
7341                            new.control) != old.control);
7342
7343         /* We should not block the vCPU if an interrupt is posted for it.  */
7344         if (pi_test_on(pi_desc) == 1)
7345                 __pi_post_block(vcpu);
7346
7347         local_irq_enable();
7348         return (vcpu->pre_pcpu == -1);
7349 }
7350
7351 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7352 {
7353         if (pi_pre_block(vcpu))
7354                 return 1;
7355
7356         if (kvm_lapic_hv_timer_in_use(vcpu))
7357                 kvm_lapic_switch_to_sw_timer(vcpu);
7358
7359         return 0;
7360 }
7361
7362 static void pi_post_block(struct kvm_vcpu *vcpu)
7363 {
7364         if (vcpu->pre_pcpu == -1)
7365                 return;
7366
7367         WARN_ON(irqs_disabled());
7368         local_irq_disable();
7369         __pi_post_block(vcpu);
7370         local_irq_enable();
7371 }
7372
7373 static void vmx_post_block(struct kvm_vcpu *vcpu)
7374 {
7375         if (kvm_x86_ops->set_hv_timer)
7376                 kvm_lapic_switch_to_hv_timer(vcpu);
7377
7378         pi_post_block(vcpu);
7379 }
7380
7381 /*
7382  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7383  *
7384  * @kvm: kvm
7385  * @host_irq: host irq of the interrupt
7386  * @guest_irq: gsi of the interrupt
7387  * @set: set or unset PI
7388  * returns 0 on success, < 0 on failure
7389  */
7390 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7391                               uint32_t guest_irq, bool set)
7392 {
7393         struct kvm_kernel_irq_routing_entry *e;
7394         struct kvm_irq_routing_table *irq_rt;
7395         struct kvm_lapic_irq irq;
7396         struct kvm_vcpu *vcpu;
7397         struct vcpu_data vcpu_info;
7398         int idx, ret = 0;
7399
7400         if (!kvm_arch_has_assigned_device(kvm) ||
7401                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7402                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7403                 return 0;
7404
7405         idx = srcu_read_lock(&kvm->irq_srcu);
7406         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7407         if (guest_irq >= irq_rt->nr_rt_entries ||
7408             hlist_empty(&irq_rt->map[guest_irq])) {
7409                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7410                              guest_irq, irq_rt->nr_rt_entries);
7411                 goto out;
7412         }
7413
7414         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7415                 if (e->type != KVM_IRQ_ROUTING_MSI)
7416                         continue;
7417                 /*
7418                  * VT-d PI cannot support posting multicast/broadcast
7419                  * interrupts to a vCPU, we still use interrupt remapping
7420                  * for these kind of interrupts.
7421                  *
7422                  * For lowest-priority interrupts, we only support
7423                  * those with single CPU as the destination, e.g. user
7424                  * configures the interrupts via /proc/irq or uses
7425                  * irqbalance to make the interrupts single-CPU.
7426                  *
7427                  * We will support full lowest-priority interrupt later.
7428                  */
7429
7430                 kvm_set_msi_irq(kvm, e, &irq);
7431                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
7432                         /*
7433                          * Make sure the IRTE is in remapped mode if
7434                          * we don't handle it in posted mode.
7435                          */
7436                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7437                         if (ret < 0) {
7438                                 printk(KERN_INFO
7439                                    "failed to back to remapped mode, irq: %u\n",
7440                                    host_irq);
7441                                 goto out;
7442                         }
7443
7444                         continue;
7445                 }
7446
7447                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7448                 vcpu_info.vector = irq.vector;
7449
7450                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7451                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7452
7453                 if (set)
7454                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7455                 else
7456                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7457
7458                 if (ret < 0) {
7459                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
7460                                         __func__);
7461                         goto out;
7462                 }
7463         }
7464
7465         ret = 0;
7466 out:
7467         srcu_read_unlock(&kvm->irq_srcu, idx);
7468         return ret;
7469 }
7470
7471 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7472 {
7473         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7474                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7475                         FEATURE_CONTROL_LMCE;
7476         else
7477                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7478                         ~FEATURE_CONTROL_LMCE;
7479 }
7480
7481 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7482 {
7483         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7484         if (to_vmx(vcpu)->nested.nested_run_pending)
7485                 return 0;
7486         return 1;
7487 }
7488
7489 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7490 {
7491         struct vcpu_vmx *vmx = to_vmx(vcpu);
7492
7493         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7494         if (vmx->nested.smm.guest_mode)
7495                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7496
7497         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7498         vmx->nested.vmxon = false;
7499         vmx_clear_hlt(vcpu);
7500         return 0;
7501 }
7502
7503 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
7504 {
7505         struct vcpu_vmx *vmx = to_vmx(vcpu);
7506         int ret;
7507
7508         if (vmx->nested.smm.vmxon) {
7509                 vmx->nested.vmxon = true;
7510                 vmx->nested.smm.vmxon = false;
7511         }
7512
7513         if (vmx->nested.smm.guest_mode) {
7514                 vcpu->arch.hflags &= ~HF_SMM_MASK;
7515                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7516                 vcpu->arch.hflags |= HF_SMM_MASK;
7517                 if (ret)
7518                         return ret;
7519
7520                 vmx->nested.smm.guest_mode = false;
7521         }
7522         return 0;
7523 }
7524
7525 static int enable_smi_window(struct kvm_vcpu *vcpu)
7526 {
7527         return 0;
7528 }
7529
7530 static __init int hardware_setup(void)
7531 {
7532         unsigned long host_bndcfgs;
7533         int r, i;
7534
7535         rdmsrl_safe(MSR_EFER, &host_efer);
7536
7537         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7538                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7539
7540         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7541                 return -EIO;
7542
7543         if (boot_cpu_has(X86_FEATURE_NX))
7544                 kvm_enable_efer_bits(EFER_NX);
7545
7546         if (boot_cpu_has(X86_FEATURE_MPX)) {
7547                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7548                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7549         }
7550
7551         if (boot_cpu_has(X86_FEATURE_XSAVES))
7552                 rdmsrl(MSR_IA32_XSS, host_xss);
7553
7554         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7555             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7556                 enable_vpid = 0;
7557
7558         if (!cpu_has_vmx_ept() ||
7559             !cpu_has_vmx_ept_4levels() ||
7560             !cpu_has_vmx_ept_mt_wb() ||
7561             !cpu_has_vmx_invept_global())
7562                 enable_ept = 0;
7563
7564         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7565                 enable_ept_ad_bits = 0;
7566
7567         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7568                 enable_unrestricted_guest = 0;
7569
7570         if (!cpu_has_vmx_flexpriority())
7571                 flexpriority_enabled = 0;
7572
7573         if (!cpu_has_virtual_nmis())
7574                 enable_vnmi = 0;
7575
7576         /*
7577          * set_apic_access_page_addr() is used to reload apic access
7578          * page upon invalidation.  No need to do anything if not
7579          * using the APIC_ACCESS_ADDR VMCS field.
7580          */
7581         if (!flexpriority_enabled)
7582                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7583
7584         if (!cpu_has_vmx_tpr_shadow())
7585                 kvm_x86_ops->update_cr8_intercept = NULL;
7586
7587         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7588                 kvm_disable_largepages();
7589
7590 #if IS_ENABLED(CONFIG_HYPERV)
7591         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7592             && enable_ept) {
7593                 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7594                 kvm_x86_ops->tlb_remote_flush_with_range =
7595                                 hv_remote_flush_tlb_with_range;
7596         }
7597 #endif
7598
7599         if (!cpu_has_vmx_ple()) {
7600                 ple_gap = 0;
7601                 ple_window = 0;
7602                 ple_window_grow = 0;
7603                 ple_window_max = 0;
7604                 ple_window_shrink = 0;
7605         }
7606
7607         if (!cpu_has_vmx_apicv()) {
7608                 enable_apicv = 0;
7609                 kvm_x86_ops->sync_pir_to_irr = NULL;
7610         }
7611
7612         if (cpu_has_vmx_tsc_scaling()) {
7613                 kvm_has_tsc_control = true;
7614                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7615                 kvm_tsc_scaling_ratio_frac_bits = 48;
7616         }
7617
7618         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7619
7620         if (enable_ept)
7621                 vmx_enable_tdp();
7622         else
7623                 kvm_disable_tdp();
7624
7625         /*
7626          * Only enable PML when hardware supports PML feature, and both EPT
7627          * and EPT A/D bit features are enabled -- PML depends on them to work.
7628          */
7629         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7630                 enable_pml = 0;
7631
7632         if (!enable_pml) {
7633                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7634                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7635                 kvm_x86_ops->flush_log_dirty = NULL;
7636                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7637         }
7638
7639         if (!cpu_has_vmx_preemption_timer())
7640                 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7641
7642         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7643                 u64 vmx_msr;
7644
7645                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7646                 cpu_preemption_timer_multi =
7647                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7648         } else {
7649                 kvm_x86_ops->set_hv_timer = NULL;
7650                 kvm_x86_ops->cancel_hv_timer = NULL;
7651         }
7652
7653         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7654
7655         kvm_mce_cap_supported |= MCG_LMCE_P;
7656
7657         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7658                 return -EINVAL;
7659         if (!enable_ept || !cpu_has_vmx_intel_pt())
7660                 pt_mode = PT_MODE_SYSTEM;
7661
7662         if (nested) {
7663                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7664                                            vmx_capability.ept, enable_apicv);
7665
7666                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7667                 if (r)
7668                         return r;
7669         }
7670
7671         r = alloc_kvm_area();
7672         if (r)
7673                 nested_vmx_hardware_unsetup();
7674         return r;
7675 }
7676
7677 static __exit void hardware_unsetup(void)
7678 {
7679         if (nested)
7680                 nested_vmx_hardware_unsetup();
7681
7682         free_kvm_area();
7683 }
7684
7685 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7686         .cpu_has_kvm_support = cpu_has_kvm_support,
7687         .disabled_by_bios = vmx_disabled_by_bios,
7688         .hardware_setup = hardware_setup,
7689         .hardware_unsetup = hardware_unsetup,
7690         .check_processor_compatibility = vmx_check_processor_compat,
7691         .hardware_enable = hardware_enable,
7692         .hardware_disable = hardware_disable,
7693         .cpu_has_accelerated_tpr = report_flexpriority,
7694         .has_emulated_msr = vmx_has_emulated_msr,
7695
7696         .vm_init = vmx_vm_init,
7697         .vm_alloc = vmx_vm_alloc,
7698         .vm_free = vmx_vm_free,
7699
7700         .vcpu_create = vmx_create_vcpu,
7701         .vcpu_free = vmx_free_vcpu,
7702         .vcpu_reset = vmx_vcpu_reset,
7703
7704         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7705         .vcpu_load = vmx_vcpu_load,
7706         .vcpu_put = vmx_vcpu_put,
7707
7708         .update_bp_intercept = update_exception_bitmap,
7709         .get_msr_feature = vmx_get_msr_feature,
7710         .get_msr = vmx_get_msr,
7711         .set_msr = vmx_set_msr,
7712         .get_segment_base = vmx_get_segment_base,
7713         .get_segment = vmx_get_segment,
7714         .set_segment = vmx_set_segment,
7715         .get_cpl = vmx_get_cpl,
7716         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7717         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7718         .decache_cr3 = vmx_decache_cr3,
7719         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7720         .set_cr0 = vmx_set_cr0,
7721         .set_cr3 = vmx_set_cr3,
7722         .set_cr4 = vmx_set_cr4,
7723         .set_efer = vmx_set_efer,
7724         .get_idt = vmx_get_idt,
7725         .set_idt = vmx_set_idt,
7726         .get_gdt = vmx_get_gdt,
7727         .set_gdt = vmx_set_gdt,
7728         .get_dr6 = vmx_get_dr6,
7729         .set_dr6 = vmx_set_dr6,
7730         .set_dr7 = vmx_set_dr7,
7731         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7732         .cache_reg = vmx_cache_reg,
7733         .get_rflags = vmx_get_rflags,
7734         .set_rflags = vmx_set_rflags,
7735
7736         .tlb_flush = vmx_flush_tlb,
7737         .tlb_flush_gva = vmx_flush_tlb_gva,
7738
7739         .run = vmx_vcpu_run,
7740         .handle_exit = vmx_handle_exit,
7741         .skip_emulated_instruction = skip_emulated_instruction,
7742         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7743         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7744         .patch_hypercall = vmx_patch_hypercall,
7745         .set_irq = vmx_inject_irq,
7746         .set_nmi = vmx_inject_nmi,
7747         .queue_exception = vmx_queue_exception,
7748         .cancel_injection = vmx_cancel_injection,
7749         .interrupt_allowed = vmx_interrupt_allowed,
7750         .nmi_allowed = vmx_nmi_allowed,
7751         .get_nmi_mask = vmx_get_nmi_mask,
7752         .set_nmi_mask = vmx_set_nmi_mask,
7753         .enable_nmi_window = enable_nmi_window,
7754         .enable_irq_window = enable_irq_window,
7755         .update_cr8_intercept = update_cr8_intercept,
7756         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7757         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7758         .get_enable_apicv = vmx_get_enable_apicv,
7759         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7760         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7761         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7762         .hwapic_irr_update = vmx_hwapic_irr_update,
7763         .hwapic_isr_update = vmx_hwapic_isr_update,
7764         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7765         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7766         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7767
7768         .set_tss_addr = vmx_set_tss_addr,
7769         .set_identity_map_addr = vmx_set_identity_map_addr,
7770         .get_tdp_level = get_ept_level,
7771         .get_mt_mask = vmx_get_mt_mask,
7772
7773         .get_exit_info = vmx_get_exit_info,
7774
7775         .get_lpage_level = vmx_get_lpage_level,
7776
7777         .cpuid_update = vmx_cpuid_update,
7778
7779         .rdtscp_supported = vmx_rdtscp_supported,
7780         .invpcid_supported = vmx_invpcid_supported,
7781
7782         .set_supported_cpuid = vmx_set_supported_cpuid,
7783
7784         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7785
7786         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7787         .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7788
7789         .set_tdp_cr3 = vmx_set_cr3,
7790
7791         .check_intercept = vmx_check_intercept,
7792         .handle_external_intr = vmx_handle_external_intr,
7793         .mpx_supported = vmx_mpx_supported,
7794         .xsaves_supported = vmx_xsaves_supported,
7795         .umip_emulated = vmx_umip_emulated,
7796         .pt_supported = vmx_pt_supported,
7797
7798         .request_immediate_exit = vmx_request_immediate_exit,
7799
7800         .sched_in = vmx_sched_in,
7801
7802         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7803         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7804         .flush_log_dirty = vmx_flush_log_dirty,
7805         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7806         .write_log_dirty = vmx_write_pml_buffer,
7807
7808         .pre_block = vmx_pre_block,
7809         .post_block = vmx_post_block,
7810
7811         .pmu_ops = &intel_pmu_ops,
7812
7813         .update_pi_irte = vmx_update_pi_irte,
7814
7815 #ifdef CONFIG_X86_64
7816         .set_hv_timer = vmx_set_hv_timer,
7817         .cancel_hv_timer = vmx_cancel_hv_timer,
7818 #endif
7819
7820         .setup_mce = vmx_setup_mce,
7821
7822         .smi_allowed = vmx_smi_allowed,
7823         .pre_enter_smm = vmx_pre_enter_smm,
7824         .pre_leave_smm = vmx_pre_leave_smm,
7825         .enable_smi_window = enable_smi_window,
7826
7827         .check_nested_events = NULL,
7828         .get_nested_state = NULL,
7829         .set_nested_state = NULL,
7830         .get_vmcs12_pages = NULL,
7831         .nested_enable_evmcs = NULL,
7832 };
7833
7834 static void vmx_cleanup_l1d_flush(void)
7835 {
7836         if (vmx_l1d_flush_pages) {
7837                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7838                 vmx_l1d_flush_pages = NULL;
7839         }
7840         /* Restore state so sysfs ignores VMX */
7841         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7842 }
7843
7844 static void vmx_exit(void)
7845 {
7846 #ifdef CONFIG_KEXEC_CORE
7847         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7848         synchronize_rcu();
7849 #endif
7850
7851         kvm_exit();
7852
7853 #if IS_ENABLED(CONFIG_HYPERV)
7854         if (static_branch_unlikely(&enable_evmcs)) {
7855                 int cpu;
7856                 struct hv_vp_assist_page *vp_ap;
7857                 /*
7858                  * Reset everything to support using non-enlightened VMCS
7859                  * access later (e.g. when we reload the module with
7860                  * enlightened_vmcs=0)
7861                  */
7862                 for_each_online_cpu(cpu) {
7863                         vp_ap = hv_get_vp_assist_page(cpu);
7864
7865                         if (!vp_ap)
7866                                 continue;
7867
7868                         vp_ap->current_nested_vmcs = 0;
7869                         vp_ap->enlighten_vmentry = 0;
7870                 }
7871
7872                 static_branch_disable(&enable_evmcs);
7873         }
7874 #endif
7875         vmx_cleanup_l1d_flush();
7876 }
7877 module_exit(vmx_exit);
7878
7879 static int __init vmx_init(void)
7880 {
7881         int r;
7882
7883 #if IS_ENABLED(CONFIG_HYPERV)
7884         /*
7885          * Enlightened VMCS usage should be recommended and the host needs
7886          * to support eVMCS v1 or above. We can also disable eVMCS support
7887          * with module parameter.
7888          */
7889         if (enlightened_vmcs &&
7890             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7891             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7892             KVM_EVMCS_VERSION) {
7893                 int cpu;
7894
7895                 /* Check that we have assist pages on all online CPUs */
7896                 for_each_online_cpu(cpu) {
7897                         if (!hv_get_vp_assist_page(cpu)) {
7898                                 enlightened_vmcs = false;
7899                                 break;
7900                         }
7901                 }
7902
7903                 if (enlightened_vmcs) {
7904                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7905                         static_branch_enable(&enable_evmcs);
7906                 }
7907         } else {
7908                 enlightened_vmcs = false;
7909         }
7910 #endif
7911
7912         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7913                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7914         if (r)
7915                 return r;
7916
7917         /*
7918          * Must be called after kvm_init() so enable_ept is properly set
7919          * up. Hand the parameter mitigation value in which was stored in
7920          * the pre module init parser. If no parameter was given, it will
7921          * contain 'auto' which will be turned into the default 'cond'
7922          * mitigation mode.
7923          */
7924         if (boot_cpu_has(X86_BUG_L1TF)) {
7925                 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7926                 if (r) {
7927                         vmx_exit();
7928                         return r;
7929                 }
7930         }
7931
7932 #ifdef CONFIG_KEXEC_CORE
7933         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7934                            crash_vmclear_local_loaded_vmcss);
7935 #endif
7936         vmx_check_vmcs12_offsets();
7937
7938         return 0;
7939 }
7940 module_init(vmx_init);