arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/highmem.h>
  17 #include <linux/hrtimer.h>
  18 #include <linux/kernel.h>
  19 #include <linux/kvm_host.h>
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/mod_devicetable.h>
  23 #include <linux/mm.h>
  24 #include <linux/objtool.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30 #include <linux/entry-kvm.h>
  31
  32 #include <asm/apic.h>
  33 #include <asm/asm.h>
  34 #include <asm/cpu.h>
  35 #include <asm/cpu_device_id.h>
  36 #include <asm/debugreg.h>
  37 #include <asm/desc.h>
  38 #include <asm/fpu/api.h>
  39 #include <asm/idtentry.h>
  40 #include <asm/io.h>
  41 #include <asm/irq_remapping.h>
  42 #include <asm/kexec.h>
  43 #include <asm/perf_event.h>
  44 #include <asm/mmu_context.h>
  45 #include <asm/mshyperv.h>
  46 #include <asm/mwait.h>
  47 #include <asm/spec-ctrl.h>
  48 #include <asm/virtext.h>
  49 #include <asm/vmx.h>
  50
  51 #include "capabilities.h"
  52 #include "cpuid.h"
  53 #include "evmcs.h"
  54 #include "hyperv.h"
  55 #include "kvm_onhyperv.h"
  56 #include "irq.h"
  57 #include "kvm_cache_regs.h"
  58 #include "lapic.h"
  59 #include "mmu.h"
  60 #include "nested.h"
  61 #include "pmu.h"
  62 #include "sgx.h"
  63 #include "trace.h"
  64 #include "vmcs.h"
  65 #include "vmcs12.h"
  66 #include "vmx.h"
  67 #include "x86.h"
  68
  69 MODULE_AUTHOR("Qumranet");
  70 MODULE_LICENSE("GPL");
  71
  72 #ifdef MODULE
  73 static const struct x86_cpu_id vmx_cpu_id[] = {
  74         X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
  75         {}
  76 };
  77 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  78 #endif
  79
  80 bool __read_mostly enable_vpid = 1;
  81 module_param_named(vpid, enable_vpid, bool, 0444);
  82
  83 static bool __read_mostly enable_vnmi = 1;
  84 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  85
  86 bool __read_mostly flexpriority_enabled = 1;
  87 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_ept = 1;
  90 module_param_named(ept, enable_ept, bool, S_IRUGO);
  91
  92 bool __read_mostly enable_unrestricted_guest = 1;
  93 module_param_named(unrestricted_guest,
  94                         enable_unrestricted_guest, bool, S_IRUGO);
  95
  96 bool __read_mostly enable_ept_ad_bits = 1;
  97 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  98
  99 static bool __read_mostly emulate_invalid_guest_state = true;
 100 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
 101
 102 static bool __read_mostly fasteoi = 1;
 103 module_param(fasteoi, bool, S_IRUGO);
 104
 105 module_param(enable_apicv, bool, S_IRUGO);
 106
 107 /*
 108  * If nested=1, nested virtualization is supported, i.e., guests may use
 109  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 110  * use VMX instructions.
 111  */
 112 static bool __read_mostly nested = 1;
 113 module_param(nested, bool, S_IRUGO);
 114
 115 bool __read_mostly enable_pml = 1;
 116 module_param_named(pml, enable_pml, bool, S_IRUGO);
 117
 118 static bool __read_mostly dump_invalid_vmcs = 0;
 119 module_param(dump_invalid_vmcs, bool, 0644);
 120
 121 #define MSR_BITMAP_MODE_X2APIC          1
 122 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 123
 124 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 125
 126 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 127 static int __read_mostly cpu_preemption_timer_multi;
 128 static bool __read_mostly enable_preemption_timer = 1;
 129 #ifdef CONFIG_X86_64
 130 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 131 #endif
 132
 133 extern bool __read_mostly allow_smaller_maxphyaddr;
 134 module_param(allow_smaller_maxphyaddr, bool, S_IRUGO);
 135
 136 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 137 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 138 #define KVM_VM_CR0_ALWAYS_ON                            \
 139         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 140
 141 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 142 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 143 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 144
 145 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 146
 147 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 148         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 149         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 150         RTIT_STATUS_BYTECNT))
 151
 152 /*
 153  * List of MSRs that can be directly passed to the guest.
 154  * In addition to these x2apic and PT MSRs are handled specially.
 155  */
 156 static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = {
 157         MSR_IA32_SPEC_CTRL,
 158         MSR_IA32_PRED_CMD,
 159         MSR_IA32_TSC,
 160 #ifdef CONFIG_X86_64
 161         MSR_FS_BASE,
 162         MSR_GS_BASE,
 163         MSR_KERNEL_GS_BASE,
 164 #endif
 165         MSR_IA32_SYSENTER_CS,
 166         MSR_IA32_SYSENTER_ESP,
 167         MSR_IA32_SYSENTER_EIP,
 168         MSR_CORE_C1_RES,
 169         MSR_CORE_C3_RESIDENCY,
 170         MSR_CORE_C6_RESIDENCY,
 171         MSR_CORE_C7_RESIDENCY,
 172 };
 173
 174 /*
 175  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 176  * ple_gap:    upper bound on the amount of time between two successive
 177  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 178  *             According to test, this time is usually smaller than 128 cycles.
 179  * ple_window: upper bound on the amount of time a guest is allowed to execute
 180  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 181  *             less than 2^12 cycles
 182  * Time is measured based on a counter that runs at the same rate as the TSC,
 183  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 184  */
 185 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 186 module_param(ple_gap, uint, 0444);
 187
 188 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 189 module_param(ple_window, uint, 0444);
 190
 191 /* Default doubles per-vcpu window every exit. */
 192 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 193 module_param(ple_window_grow, uint, 0444);
 194
 195 /* Default resets per-vcpu window every exit to ple_window. */
 196 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 197 module_param(ple_window_shrink, uint, 0444);
 198
 199 /* Default is to compute the maximum so we can never overflow. */
 200 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 201 module_param(ple_window_max, uint, 0444);
 202
 203 /* Default is SYSTEM mode, 1 for host-guest mode */
 204 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 205 module_param(pt_mode, int, S_IRUGO);
 206
 207 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 208 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 209 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 210
 211 /* Storage for pre module init parameter parsing */
 212 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 213
 214 static const struct {
 215         const char *option;
 216         bool for_parse;
 217 } vmentry_l1d_param[] = {
 218         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 219         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 220         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 221         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 222         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 223         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 224 };
 225
 226 #define L1D_CACHE_ORDER 4
 227 static void *vmx_l1d_flush_pages;
 228
 229 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 230 {
 231         struct page *page;
 232         unsigned int i;
 233
 234         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 235                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 236                 return 0;
 237         }
 238
 239         if (!enable_ept) {
 240                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 241                 return 0;
 242         }
 243
 244         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 245                 u64 msr;
 246
 247                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 248                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 249                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 250                         return 0;
 251                 }
 252         }
 253
 254         /* If set to auto use the default l1tf mitigation method */
 255         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 256                 switch (l1tf_mitigation) {
 257                 case L1TF_MITIGATION_OFF:
 258                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 259                         break;
 260                 case L1TF_MITIGATION_FLUSH_NOWARN:
 261                 case L1TF_MITIGATION_FLUSH:
 262                 case L1TF_MITIGATION_FLUSH_NOSMT:
 263                         l1tf = VMENTER_L1D_FLUSH_COND;
 264                         break;
 265                 case L1TF_MITIGATION_FULL:
 266                 case L1TF_MITIGATION_FULL_FORCE:
 267                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 268                         break;
 269                 }
 270         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 271                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 272         }
 273
 274         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 275             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 276                 /*
 277                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 278                  * lifetime and so should not be charged to a memcg.
 279                  */
 280                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 281                 if (!page)
 282                         return -ENOMEM;
 283                 vmx_l1d_flush_pages = page_address(page);
 284
 285                 /*
 286                  * Initialize each page with a different pattern in
 287                  * order to protect against KSM in the nested
 288                  * virtualization case.
 289                  */
 290                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 291                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 292                                PAGE_SIZE);
 293                 }
 294         }
 295
 296         l1tf_vmx_mitigation = l1tf;
 297
 298         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 299                 static_branch_enable(&vmx_l1d_should_flush);
 300         else
 301                 static_branch_disable(&vmx_l1d_should_flush);
 302
 303         if (l1tf == VMENTER_L1D_FLUSH_COND)
 304                 static_branch_enable(&vmx_l1d_flush_cond);
 305         else
 306                 static_branch_disable(&vmx_l1d_flush_cond);
 307         return 0;
 308 }
 309
 310 static int vmentry_l1d_flush_parse(const char *s)
 311 {
 312         unsigned int i;
 313
 314         if (s) {
 315                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 316                         if (vmentry_l1d_param[i].for_parse &&
 317                             sysfs_streq(s, vmentry_l1d_param[i].option))
 318                                 return i;
 319                 }
 320         }
 321         return -EINVAL;
 322 }
 323
 324 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 325 {
 326         int l1tf, ret;
 327
 328         l1tf = vmentry_l1d_flush_parse(s);
 329         if (l1tf < 0)
 330                 return l1tf;
 331
 332         if (!boot_cpu_has(X86_BUG_L1TF))
 333                 return 0;
 334
 335         /*
 336          * Has vmx_init() run already? If not then this is the pre init
 337          * parameter parsing. In that case just store the value and let
 338          * vmx_init() do the proper setup after enable_ept has been
 339          * established.
 340          */
 341         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 342                 vmentry_l1d_flush_param = l1tf;
 343                 return 0;
 344         }
 345
 346         mutex_lock(&vmx_l1d_flush_mutex);
 347         ret = vmx_setup_l1d_flush(l1tf);
 348         mutex_unlock(&vmx_l1d_flush_mutex);
 349         return ret;
 350 }
 351
 352 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 353 {
 354         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 355                 return sprintf(s, "???\n");
 356
 357         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 358 }
 359
 360 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 361         .set = vmentry_l1d_flush_set,
 362         .get = vmentry_l1d_flush_get,
 363 };
 364 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 365
 366 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 367
 368 void vmx_vmexit(void);
 369
 370 #define vmx_insn_failed(fmt...)         \
 371 do {                                    \
 372         WARN_ONCE(1, fmt);              \
 373         pr_warn_ratelimited(fmt);       \
 374 } while (0)
 375
 376 asmlinkage void vmread_error(unsigned long field, bool fault)
 377 {
 378         if (fault)
 379                 kvm_spurious_fault();
 380         else
 381                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 382 }
 383
 384 noinline void vmwrite_error(unsigned long field, unsigned long value)
 385 {
 386         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 387                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 388 }
 389
 390 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 391 {
 392         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 393 }
 394
 395 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 396 {
 397         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 398 }
 399
 400 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 401 {
 402         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 403                         ext, vpid, gva);
 404 }
 405
 406 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 407 {
 408         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 409                         ext, eptp, gpa);
 410 }
 411
 412 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 413 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 414 /*
 415  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 416  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 417  */
 418 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 419
 420 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 421 static DEFINE_SPINLOCK(vmx_vpid_lock);
 422
 423 struct vmcs_config vmcs_config;
 424 struct vmx_capability vmx_capability;
 425
 426 #define VMX_SEGMENT_FIELD(seg)                                  \
 427         [VCPU_SREG_##seg] = {                                   \
 428                 .selector = GUEST_##seg##_SELECTOR,             \
 429                 .base = GUEST_##seg##_BASE,                     \
 430                 .limit = GUEST_##seg##_LIMIT,                   \
 431                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 432         }
 433
 434 static const struct kvm_vmx_segment_field {
 435         unsigned selector;
 436         unsigned base;
 437         unsigned limit;
 438         unsigned ar_bytes;
 439 } kvm_vmx_segment_fields[] = {
 440         VMX_SEGMENT_FIELD(CS),
 441         VMX_SEGMENT_FIELD(DS),
 442         VMX_SEGMENT_FIELD(ES),
 443         VMX_SEGMENT_FIELD(FS),
 444         VMX_SEGMENT_FIELD(GS),
 445         VMX_SEGMENT_FIELD(SS),
 446         VMX_SEGMENT_FIELD(TR),
 447         VMX_SEGMENT_FIELD(LDTR),
 448 };
 449
 450 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
 451 {
 452         vmx->segment_cache.bitmask = 0;
 453 }
 454
 455 static unsigned long host_idt_base;
 456
 457 #if IS_ENABLED(CONFIG_HYPERV)
 458 static bool __read_mostly enlightened_vmcs = true;
 459 module_param(enlightened_vmcs, bool, 0444);
 460
 461 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 462 {
 463         struct hv_enlightened_vmcs *evmcs;
 464         struct hv_partition_assist_pg **p_hv_pa_pg =
 465                         &to_kvm_hv(vcpu->kvm)->hv_pa_pg;
 466         /*
 467          * Synthetic VM-Exit is not enabled in current code and so All
 468          * evmcs in singe VM shares same assist page.
 469          */
 470         if (!*p_hv_pa_pg)
 471                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
 472
 473         if (!*p_hv_pa_pg)
 474                 return -ENOMEM;
 475
 476         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 477
 478         evmcs->partition_assist_page =
 479                 __pa(*p_hv_pa_pg);
 480         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 481         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 482
 483         return 0;
 484 }
 485
 486 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 487
 488 /*
 489  * Comment's format: document - errata name - stepping - processor name.
 490  * Refer from
 491  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 492  */
 493 static u32 vmx_preemption_cpu_tfms[] = {
 494 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 495 0x000206E6,
 496 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 497 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 498 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 499 0x00020652,
 500 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 501 0x00020655,
 502 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 503 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 504 /*
 505  * 320767.pdf - AAP86  - B1 -
 506  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 507  */
 508 0x000106E5,
 509 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 510 0x000106A0,
 511 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 512 0x000106A1,
 513 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 514 0x000106A4,
 515  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 516  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 517  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 518 0x000106A5,
 519  /* Xeon E3-1220 V2 */
 520 0x000306A8,
 521 };
 522
 523 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 524 {
 525         u32 eax = cpuid_eax(0x00000001), i;
 526
 527         /* Clear the reserved bits */
 528         eax &= ~(0x3U << 14 | 0xfU << 28);
 529         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 530                 if (eax == vmx_preemption_cpu_tfms[i])
 531                         return true;
 532
 533         return false;
 534 }
 535
 536 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 537 {
 538         return flexpriority_enabled && lapic_in_kernel(vcpu);
 539 }
 540
 541 static inline bool report_flexpriority(void)
 542 {
 543         return flexpriority_enabled;
 544 }
 545
 546 static int possible_passthrough_msr_slot(u32 msr)
 547 {
 548         u32 i;
 549
 550         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++)
 551                 if (vmx_possible_passthrough_msrs[i] == msr)
 552                         return i;
 553
 554         return -ENOENT;
 555 }
 556
 557 static bool is_valid_passthrough_msr(u32 msr)
 558 {
 559         bool r;
 560
 561         switch (msr) {
 562         case 0x800 ... 0x8ff:
 563                 /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */
 564                 return true;
 565         case MSR_IA32_RTIT_STATUS:
 566         case MSR_IA32_RTIT_OUTPUT_BASE:
 567         case MSR_IA32_RTIT_OUTPUT_MASK:
 568         case MSR_IA32_RTIT_CR3_MATCH:
 569         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
 570                 /* PT MSRs. These are handled in pt_update_intercept_for_msr() */
 571         case MSR_LBR_SELECT:
 572         case MSR_LBR_TOS:
 573         case MSR_LBR_INFO_0 ... MSR_LBR_INFO_0 + 31:
 574         case MSR_LBR_NHM_FROM ... MSR_LBR_NHM_FROM + 31:
 575         case MSR_LBR_NHM_TO ... MSR_LBR_NHM_TO + 31:
 576         case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8:
 577         case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8:
 578                 /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */
 579                 return true;
 580         }
 581
 582         r = possible_passthrough_msr_slot(msr) != -ENOENT;
 583
 584         WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr);
 585
 586         return r;
 587 }
 588
 589 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
 590 {
 591         int i;
 592
 593         i = kvm_find_user_return_msr(msr);
 594         if (i >= 0)
 595                 return &vmx->guest_uret_msrs[i];
 596         return NULL;
 597 }
 598
 599 static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx,
 600                                   struct vmx_uret_msr *msr, u64 data)
 601 {
 602         unsigned int slot = msr - vmx->guest_uret_msrs;
 603         int ret = 0;
 604
 605         u64 old_msr_data = msr->data;
 606         msr->data = data;
 607         if (msr->load_into_hardware) {
 608                 preempt_disable();
 609                 ret = kvm_set_user_return_msr(slot, msr->data, msr->mask);
 610                 preempt_enable();
 611                 if (ret)
 612                         msr->data = old_msr_data;
 613         }
 614         return ret;
 615 }
 616
 617 #ifdef CONFIG_KEXEC_CORE
 618 static void crash_vmclear_local_loaded_vmcss(void)
 619 {
 620         int cpu = raw_smp_processor_id();
 621         struct loaded_vmcs *v;
 622
 623         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 624                             loaded_vmcss_on_cpu_link)
 625                 vmcs_clear(v->vmcs);
 626 }
 627 #endif /* CONFIG_KEXEC_CORE */
 628
 629 static void __loaded_vmcs_clear(void *arg)
 630 {
 631         struct loaded_vmcs *loaded_vmcs = arg;
 632         int cpu = raw_smp_processor_id();
 633
 634         if (loaded_vmcs->cpu != cpu)
 635                 return; /* vcpu migration can race with cpu offline */
 636         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 637                 per_cpu(current_vmcs, cpu) = NULL;
 638
 639         vmcs_clear(loaded_vmcs->vmcs);
 640         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 641                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 642
 643         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 644
 645         /*
 646          * Ensure all writes to loaded_vmcs, including deleting it from its
 647          * current percpu list, complete before setting loaded_vmcs->vcpu to
 648          * -1, otherwise a different cpu can see vcpu == -1 first and add
 649          * loaded_vmcs to its percpu list before it's deleted from this cpu's
 650          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
 651          */
 652         smp_wmb();
 653
 654         loaded_vmcs->cpu = -1;
 655         loaded_vmcs->launched = 0;
 656 }
 657
 658 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 659 {
 660         int cpu = loaded_vmcs->cpu;
 661
 662         if (cpu != -1)
 663                 smp_call_function_single(cpu,
 664                          __loaded_vmcs_clear, loaded_vmcs, 1);
 665 }
 666
 667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 668                                        unsigned field)
 669 {
 670         bool ret;
 671         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 672
 673         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
 674                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
 675                 vmx->segment_cache.bitmask = 0;
 676         }
 677         ret = vmx->segment_cache.bitmask & mask;
 678         vmx->segment_cache.bitmask |= mask;
 679         return ret;
 680 }
 681
 682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 683 {
 684         u16 *p = &vmx->segment_cache.seg[seg].selector;
 685
 686         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 687                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 688         return *p;
 689 }
 690
 691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 692 {
 693         ulong *p = &vmx->segment_cache.seg[seg].base;
 694
 695         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 696                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 697         return *p;
 698 }
 699
 700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 701 {
 702         u32 *p = &vmx->segment_cache.seg[seg].limit;
 703
 704         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 705                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 706         return *p;
 707 }
 708
 709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 710 {
 711         u32 *p = &vmx->segment_cache.seg[seg].ar;
 712
 713         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 714                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 715         return *p;
 716 }
 717
 718 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu)
 719 {
 720         u32 eb;
 721
 722         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 723              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 724         /*
 725          * Guest access to VMware backdoor ports could legitimately
 726          * trigger #GP because of TSS I/O permission bitmap.
 727          * We intercept those #GP and allow access to them anyway
 728          * as VMware does.
 729          */
 730         if (enable_vmware_backdoor)
 731                 eb |= (1u << GP_VECTOR);
 732         if ((vcpu->guest_debug &
 733              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 734             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 735                 eb |= 1u << BP_VECTOR;
 736         if (to_vmx(vcpu)->rmode.vm86_active)
 737                 eb = ~0;
 738         if (!vmx_need_pf_intercept(vcpu))
 739                 eb &= ~(1u << PF_VECTOR);
 740
 741         /* When we are running a nested L2 guest and L1 specified for it a
 742          * certain exception bitmap, we must trap the same exceptions and pass
 743          * them to L1. When running L2, we will only handle the exceptions
 744          * specified above if L1 did not want them.
 745          */
 746         if (is_guest_mode(vcpu))
 747                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 748         else {
 749                 int mask = 0, match = 0;
 750
 751                 if (enable_ept && (eb & (1u << PF_VECTOR))) {
 752                         /*
 753                          * If EPT is enabled, #PF is currently only intercepted
 754                          * if MAXPHYADDR is smaller on the guest than on the
 755                          * host.  In that case we only care about present,
 756                          * non-reserved faults.  For vmcs02, however, PFEC_MASK
 757                          * and PFEC_MATCH are set in prepare_vmcs02_rare.
 758                          */
 759                         mask = PFERR_PRESENT_MASK | PFERR_RSVD_MASK;
 760                         match = PFERR_PRESENT_MASK;
 761                 }
 762                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
 763                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, match);
 764         }
 765
 766         vmcs_write32(EXCEPTION_BITMAP, eb);
 767 }
 768
 769 /*
 770  * Check if MSR is intercepted for currently loaded MSR bitmap.
 771  */
 772 static bool msr_write_intercepted(struct vcpu_vmx *vmx, u32 msr)
 773 {
 774         if (!(exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS))
 775                 return true;
 776
 777         return vmx_test_msr_bitmap_write(vmx->loaded_vmcs->msr_bitmap,
 778                                          MSR_IA32_SPEC_CTRL);
 779 }
 780
 781 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 782                 unsigned long entry, unsigned long exit)
 783 {
 784         vm_entry_controls_clearbit(vmx, entry);
 785         vm_exit_controls_clearbit(vmx, exit);
 786 }
 787
 788 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr)
 789 {
 790         unsigned int i;
 791
 792         for (i = 0; i < m->nr; ++i) {
 793                 if (m->val[i].index == msr)
 794                         return i;
 795         }
 796         return -ENOENT;
 797 }
 798
 799 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 800 {
 801         int i;
 802         struct msr_autoload *m = &vmx->msr_autoload;
 803
 804         switch (msr) {
 805         case MSR_EFER:
 806                 if (cpu_has_load_ia32_efer()) {
 807                         clear_atomic_switch_msr_special(vmx,
 808                                         VM_ENTRY_LOAD_IA32_EFER,
 809                                         VM_EXIT_LOAD_IA32_EFER);
 810                         return;
 811                 }
 812                 break;
 813         case MSR_CORE_PERF_GLOBAL_CTRL:
 814                 if (cpu_has_load_perf_global_ctrl()) {
 815                         clear_atomic_switch_msr_special(vmx,
 816                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 817                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 818                         return;
 819                 }
 820                 break;
 821         }
 822         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
 823         if (i < 0)
 824                 goto skip_guest;
 825         --m->guest.nr;
 826         m->guest.val[i] = m->guest.val[m->guest.nr];
 827         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 828
 829 skip_guest:
 830         i = vmx_find_loadstore_msr_slot(&m->host, msr);
 831         if (i < 0)
 832                 return;
 833
 834         --m->host.nr;
 835         m->host.val[i] = m->host.val[m->host.nr];
 836         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 837 }
 838
 839 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 840                 unsigned long entry, unsigned long exit,
 841                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 842                 u64 guest_val, u64 host_val)
 843 {
 844         vmcs_write64(guest_val_vmcs, guest_val);
 845         if (host_val_vmcs != HOST_IA32_EFER)
 846                 vmcs_write64(host_val_vmcs, host_val);
 847         vm_entry_controls_setbit(vmx, entry);
 848         vm_exit_controls_setbit(vmx, exit);
 849 }
 850
 851 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 852                                   u64 guest_val, u64 host_val, bool entry_only)
 853 {
 854         int i, j = 0;
 855         struct msr_autoload *m = &vmx->msr_autoload;
 856
 857         switch (msr) {
 858         case MSR_EFER:
 859                 if (cpu_has_load_ia32_efer()) {
 860                         add_atomic_switch_msr_special(vmx,
 861                                         VM_ENTRY_LOAD_IA32_EFER,
 862                                         VM_EXIT_LOAD_IA32_EFER,
 863                                         GUEST_IA32_EFER,
 864                                         HOST_IA32_EFER,
 865                                         guest_val, host_val);
 866                         return;
 867                 }
 868                 break;
 869         case MSR_CORE_PERF_GLOBAL_CTRL:
 870                 if (cpu_has_load_perf_global_ctrl()) {
 871                         add_atomic_switch_msr_special(vmx,
 872                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 873                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 874                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 875                                         HOST_IA32_PERF_GLOBAL_CTRL,
 876                                         guest_val, host_val);
 877                         return;
 878                 }
 879                 break;
 880         case MSR_IA32_PEBS_ENABLE:
 881                 /* PEBS needs a quiescent period after being disabled (to write
 882                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 883                  * provide that period, so a CPU could write host's record into
 884                  * guest's memory.
 885                  */
 886                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 887         }
 888
 889         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
 890         if (!entry_only)
 891                 j = vmx_find_loadstore_msr_slot(&m->host, msr);
 892
 893         if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) ||
 894             (j < 0 &&  m->host.nr == MAX_NR_LOADSTORE_MSRS)) {
 895                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 896                                 "Can't add msr %x\n", msr);
 897                 return;
 898         }
 899         if (i < 0) {
 900                 i = m->guest.nr++;
 901                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 902         }
 903         m->guest.val[i].index = msr;
 904         m->guest.val[i].value = guest_val;
 905
 906         if (entry_only)
 907                 return;
 908
 909         if (j < 0) {
 910                 j = m->host.nr++;
 911                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 912         }
 913         m->host.val[j].index = msr;
 914         m->host.val[j].value = host_val;
 915 }
 916
 917 static bool update_transition_efer(struct vcpu_vmx *vmx)
 918 {
 919         u64 guest_efer = vmx->vcpu.arch.efer;
 920         u64 ignore_bits = 0;
 921         int i;
 922
 923         /* Shadow paging assumes NX to be available.  */
 924         if (!enable_ept)
 925                 guest_efer |= EFER_NX;
 926
 927         /*
 928          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 929          */
 930         ignore_bits |= EFER_SCE;
 931 #ifdef CONFIG_X86_64
 932         ignore_bits |= EFER_LMA | EFER_LME;
 933         /* SCE is meaningful only in long mode on Intel */
 934         if (guest_efer & EFER_LMA)
 935                 ignore_bits &= ~(u64)EFER_SCE;
 936 #endif
 937
 938         /*
 939          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 940          * On CPUs that support "load IA32_EFER", always switch EFER
 941          * atomically, since it's faster than switching it manually.
 942          */
 943         if (cpu_has_load_ia32_efer() ||
 944             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 945                 if (!(guest_efer & EFER_LMA))
 946                         guest_efer &= ~EFER_LME;
 947                 if (guest_efer != host_efer)
 948                         add_atomic_switch_msr(vmx, MSR_EFER,
 949                                               guest_efer, host_efer, false);
 950                 else
 951                         clear_atomic_switch_msr(vmx, MSR_EFER);
 952                 return false;
 953         }
 954
 955         i = kvm_find_user_return_msr(MSR_EFER);
 956         if (i < 0)
 957                 return false;
 958
 959         clear_atomic_switch_msr(vmx, MSR_EFER);
 960
 961         guest_efer &= ~ignore_bits;
 962         guest_efer |= host_efer & ignore_bits;
 963
 964         vmx->guest_uret_msrs[i].data = guest_efer;
 965         vmx->guest_uret_msrs[i].mask = ~ignore_bits;
 966
 967         return true;
 968 }
 969
 970 #ifdef CONFIG_X86_32
 971 /*
 972  * On 32-bit kernels, VM exits still load the FS and GS bases from the
 973  * VMCS rather than the segment table.  KVM uses this helper to figure
 974  * out the current bases to poke them into the VMCS before entry.
 975  */
 976 static unsigned long segment_base(u16 selector)
 977 {
 978         struct desc_struct *table;
 979         unsigned long v;
 980
 981         if (!(selector & ~SEGMENT_RPL_MASK))
 982                 return 0;
 983
 984         table = get_current_gdt_ro();
 985
 986         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
 987                 u16 ldt_selector = kvm_read_ldt();
 988
 989                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
 990                         return 0;
 991
 992                 table = (struct desc_struct *)segment_base(ldt_selector);
 993         }
 994         v = get_desc_base(&table[selector >> 3]);
 995         return v;
 996 }
 997 #endif
 998
 999 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1000 {
1001         return vmx_pt_mode_is_host_guest() &&
1002                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1003 }
1004
1005 static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base)
1006 {
1007         /* The base must be 128-byte aligned and a legal physical address. */
1008         return kvm_vcpu_is_legal_aligned_gpa(vcpu, base, 128);
1009 }
1010
1011 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1012 {
1013         u32 i;
1014
1015         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1016         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1017         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1018         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1019         for (i = 0; i < addr_range; i++) {
1020                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1021                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1022         }
1023 }
1024
1025 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1026 {
1027         u32 i;
1028
1029         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1030         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1031         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1032         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1033         for (i = 0; i < addr_range; i++) {
1034                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1035                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1036         }
1037 }
1038
1039 static void pt_guest_enter(struct vcpu_vmx *vmx)
1040 {
1041         if (vmx_pt_mode_is_system())
1042                 return;
1043
1044         /*
1045          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1046          * Save host state before VM entry.
1047          */
1048         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1049         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1050                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1051                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1052                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1053         }
1054 }
1055
1056 static void pt_guest_exit(struct vcpu_vmx *vmx)
1057 {
1058         if (vmx_pt_mode_is_system())
1059                 return;
1060
1061         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1062                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1063                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1064         }
1065
1066         /*
1067          * KVM requires VM_EXIT_CLEAR_IA32_RTIT_CTL to expose PT to the guest,
1068          * i.e. RTIT_CTL is always cleared on VM-Exit.  Restore it if necessary.
1069          */
1070         if (vmx->pt_desc.host.ctl)
1071                 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1072 }
1073
1074 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1075                         unsigned long fs_base, unsigned long gs_base)
1076 {
1077         if (unlikely(fs_sel != host->fs_sel)) {
1078                 if (!(fs_sel & 7))
1079                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1080                 else
1081                         vmcs_write16(HOST_FS_SELECTOR, 0);
1082                 host->fs_sel = fs_sel;
1083         }
1084         if (unlikely(gs_sel != host->gs_sel)) {
1085                 if (!(gs_sel & 7))
1086                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1087                 else
1088                         vmcs_write16(HOST_GS_SELECTOR, 0);
1089                 host->gs_sel = gs_sel;
1090         }
1091         if (unlikely(fs_base != host->fs_base)) {
1092                 vmcs_writel(HOST_FS_BASE, fs_base);
1093                 host->fs_base = fs_base;
1094         }
1095         if (unlikely(gs_base != host->gs_base)) {
1096                 vmcs_writel(HOST_GS_BASE, gs_base);
1097                 host->gs_base = gs_base;
1098         }
1099 }
1100
1101 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1102 {
1103         struct vcpu_vmx *vmx = to_vmx(vcpu);
1104         struct vmcs_host_state *host_state;
1105 #ifdef CONFIG_X86_64
1106         int cpu = raw_smp_processor_id();
1107 #endif
1108         unsigned long fs_base, gs_base;
1109         u16 fs_sel, gs_sel;
1110         int i;
1111
1112         vmx->req_immediate_exit = false;
1113
1114         /*
1115          * Note that guest MSRs to be saved/restored can also be changed
1116          * when guest state is loaded. This happens when guest transitions
1117          * to/from long-mode by setting MSR_EFER.LMA.
1118          */
1119         if (!vmx->guest_uret_msrs_loaded) {
1120                 vmx->guest_uret_msrs_loaded = true;
1121                 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
1122                         if (!vmx->guest_uret_msrs[i].load_into_hardware)
1123                                 continue;
1124
1125                         kvm_set_user_return_msr(i,
1126                                                 vmx->guest_uret_msrs[i].data,
1127                                                 vmx->guest_uret_msrs[i].mask);
1128                 }
1129         }
1130
1131         if (vmx->nested.need_vmcs12_to_shadow_sync)
1132                 nested_sync_vmcs12_to_shadow(vcpu);
1133
1134         if (vmx->guest_state_loaded)
1135                 return;
1136
1137         host_state = &vmx->loaded_vmcs->host_state;
1138
1139         /*
1140          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1141          * allow segment selectors with cpl > 0 or ti == 1.
1142          */
1143         host_state->ldt_sel = kvm_read_ldt();
1144
1145 #ifdef CONFIG_X86_64
1146         savesegment(ds, host_state->ds_sel);
1147         savesegment(es, host_state->es_sel);
1148
1149         gs_base = cpu_kernelmode_gs_base(cpu);
1150         if (likely(is_64bit_mm(current->mm))) {
1151                 current_save_fsgs();
1152                 fs_sel = current->thread.fsindex;
1153                 gs_sel = current->thread.gsindex;
1154                 fs_base = current->thread.fsbase;
1155                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1156         } else {
1157                 savesegment(fs, fs_sel);
1158                 savesegment(gs, gs_sel);
1159                 fs_base = read_msr(MSR_FS_BASE);
1160                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1161         }
1162
1163         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1164 #else
1165         savesegment(fs, fs_sel);
1166         savesegment(gs, gs_sel);
1167         fs_base = segment_base(fs_sel);
1168         gs_base = segment_base(gs_sel);
1169 #endif
1170
1171         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1172         vmx->guest_state_loaded = true;
1173 }
1174
1175 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1176 {
1177         struct vmcs_host_state *host_state;
1178
1179         if (!vmx->guest_state_loaded)
1180                 return;
1181
1182         host_state = &vmx->loaded_vmcs->host_state;
1183
1184         ++vmx->vcpu.stat.host_state_reload;
1185
1186 #ifdef CONFIG_X86_64
1187         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1188 #endif
1189         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1190                 kvm_load_ldt(host_state->ldt_sel);
1191 #ifdef CONFIG_X86_64
1192                 load_gs_index(host_state->gs_sel);
1193 #else
1194                 loadsegment(gs, host_state->gs_sel);
1195 #endif
1196         }
1197         if (host_state->fs_sel & 7)
1198                 loadsegment(fs, host_state->fs_sel);
1199 #ifdef CONFIG_X86_64
1200         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1201                 loadsegment(ds, host_state->ds_sel);
1202                 loadsegment(es, host_state->es_sel);
1203         }
1204 #endif
1205         invalidate_tss_limit();
1206 #ifdef CONFIG_X86_64
1207         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1208 #endif
1209         load_fixmap_gdt(raw_smp_processor_id());
1210         vmx->guest_state_loaded = false;
1211         vmx->guest_uret_msrs_loaded = false;
1212 }
1213
1214 #ifdef CONFIG_X86_64
1215 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1216 {
1217         preempt_disable();
1218         if (vmx->guest_state_loaded)
1219                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1220         preempt_enable();
1221         return vmx->msr_guest_kernel_gs_base;
1222 }
1223
1224 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1225 {
1226         preempt_disable();
1227         if (vmx->guest_state_loaded)
1228                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1229         preempt_enable();
1230         vmx->msr_guest_kernel_gs_base = data;
1231 }
1232 #endif
1233
1234 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1235                         struct loaded_vmcs *buddy)
1236 {
1237         struct vcpu_vmx *vmx = to_vmx(vcpu);
1238         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1239         struct vmcs *prev;
1240
1241         if (!already_loaded) {
1242                 loaded_vmcs_clear(vmx->loaded_vmcs);
1243                 local_irq_disable();
1244
1245                 /*
1246                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1247                  * this cpu's percpu list, otherwise it may not yet be deleted
1248                  * from its previous cpu's percpu list.  Pairs with the
1249                  * smb_wmb() in __loaded_vmcs_clear().
1250                  */
1251                 smp_rmb();
1252
1253                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1254                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1255                 local_irq_enable();
1256         }
1257
1258         prev = per_cpu(current_vmcs, cpu);
1259         if (prev != vmx->loaded_vmcs->vmcs) {
1260                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1261                 vmcs_load(vmx->loaded_vmcs->vmcs);
1262
1263                 /*
1264                  * No indirect branch prediction barrier needed when switching
1265                  * the active VMCS within a guest, e.g. on nested VM-Enter.
1266                  * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1267                  */
1268                 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1269                         indirect_branch_prediction_barrier();
1270         }
1271
1272         if (!already_loaded) {
1273                 void *gdt = get_current_gdt_ro();
1274                 unsigned long sysenter_esp;
1275
1276                 /*
1277                  * Flush all EPTP/VPID contexts, the new pCPU may have stale
1278                  * TLB entries from its previous association with the vCPU.
1279                  */
1280                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1281
1282                 /*
1283                  * Linux uses per-cpu TSS and GDT, so set these when switching
1284                  * processors.  See 22.2.4.
1285                  */
1286                 vmcs_writel(HOST_TR_BASE,
1287                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1288                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1289
1290                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1291                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1292
1293                 vmx->loaded_vmcs->cpu = cpu;
1294         }
1295 }
1296
1297 /*
1298  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1299  * vcpu mutex is already taken.
1300  */
1301 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1302 {
1303         struct vcpu_vmx *vmx = to_vmx(vcpu);
1304
1305         vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1306
1307         vmx_vcpu_pi_load(vcpu, cpu);
1308
1309         vmx->host_debugctlmsr = get_debugctlmsr();
1310 }
1311
1312 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1313 {
1314         vmx_vcpu_pi_put(vcpu);
1315
1316         vmx_prepare_switch_to_host(to_vmx(vcpu));
1317 }
1318
1319 bool vmx_emulation_required(struct kvm_vcpu *vcpu)
1320 {
1321         return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu);
1322 }
1323
1324 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1325 {
1326         struct vcpu_vmx *vmx = to_vmx(vcpu);
1327         unsigned long rflags, save_rflags;
1328
1329         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1330                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1331                 rflags = vmcs_readl(GUEST_RFLAGS);
1332                 if (vmx->rmode.vm86_active) {
1333                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1334                         save_rflags = vmx->rmode.save_rflags;
1335                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1336                 }
1337                 vmx->rflags = rflags;
1338         }
1339         return vmx->rflags;
1340 }
1341
1342 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1343 {
1344         struct vcpu_vmx *vmx = to_vmx(vcpu);
1345         unsigned long old_rflags;
1346
1347         if (is_unrestricted_guest(vcpu)) {
1348                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1349                 vmx->rflags = rflags;
1350                 vmcs_writel(GUEST_RFLAGS, rflags);
1351                 return;
1352         }
1353
1354         old_rflags = vmx_get_rflags(vcpu);
1355         vmx->rflags = rflags;
1356         if (vmx->rmode.vm86_active) {
1357                 vmx->rmode.save_rflags = rflags;
1358                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1359         }
1360         vmcs_writel(GUEST_RFLAGS, rflags);
1361
1362         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1363                 vmx->emulation_required = vmx_emulation_required(vcpu);
1364 }
1365
1366 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1367 {
1368         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1369         int ret = 0;
1370
1371         if (interruptibility & GUEST_INTR_STATE_STI)
1372                 ret |= KVM_X86_SHADOW_INT_STI;
1373         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1374                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1375
1376         return ret;
1377 }
1378
1379 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1380 {
1381         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1382         u32 interruptibility = interruptibility_old;
1383
1384         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1385
1386         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1387                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1388         else if (mask & KVM_X86_SHADOW_INT_STI)
1389                 interruptibility |= GUEST_INTR_STATE_STI;
1390
1391         if ((interruptibility != interruptibility_old))
1392                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1393 }
1394
1395 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1396 {
1397         struct vcpu_vmx *vmx = to_vmx(vcpu);
1398         unsigned long value;
1399
1400         /*
1401          * Any MSR write that attempts to change bits marked reserved will
1402          * case a #GP fault.
1403          */
1404         if (data & vmx->pt_desc.ctl_bitmask)
1405                 return 1;
1406
1407         /*
1408          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1409          * result in a #GP unless the same write also clears TraceEn.
1410          */
1411         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1412                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1413                 return 1;
1414
1415         /*
1416          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1417          * and FabricEn would cause #GP, if
1418          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1419          */
1420         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1421                 !(data & RTIT_CTL_FABRIC_EN) &&
1422                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1423                                         PT_CAP_single_range_output))
1424                 return 1;
1425
1426         /*
1427          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1428          * utilize encodings marked reserved will cause a #GP fault.
1429          */
1430         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1431         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1432                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1433                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1434                 return 1;
1435         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1436                                                 PT_CAP_cycle_thresholds);
1437         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1438                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1439                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1440                 return 1;
1441         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1442         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1443                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1444                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1445                 return 1;
1446
1447         /*
1448          * If ADDRx_CFG is reserved or the encodings is >2 will
1449          * cause a #GP fault.
1450          */
1451         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1452         if ((value && (vmx->pt_desc.num_address_ranges < 1)) || (value > 2))
1453                 return 1;
1454         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1455         if ((value && (vmx->pt_desc.num_address_ranges < 2)) || (value > 2))
1456                 return 1;
1457         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1458         if ((value && (vmx->pt_desc.num_address_ranges < 3)) || (value > 2))
1459                 return 1;
1460         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1461         if ((value && (vmx->pt_desc.num_address_ranges < 4)) || (value > 2))
1462                 return 1;
1463
1464         return 0;
1465 }
1466
1467 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
1468 {
1469         /*
1470          * Emulation of instructions in SGX enclaves is impossible as RIP does
1471          * not point  tthe failing instruction, and even if it did, the code
1472          * stream is inaccessible.  Inject #UD instead of exiting to userspace
1473          * so that guest userspace can't DoS the guest simply by triggering
1474          * emulation (enclaves are CPL3 only).
1475          */
1476         if (to_vmx(vcpu)->exit_reason.enclave_mode) {
1477                 kvm_queue_exception(vcpu, UD_VECTOR);
1478                 return false;
1479         }
1480         return true;
1481 }
1482
1483 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1484 {
1485         union vmx_exit_reason exit_reason = to_vmx(vcpu)->exit_reason;
1486         unsigned long rip, orig_rip;
1487         u32 instr_len;
1488
1489         /*
1490          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1491          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1492          * set when EPT misconfig occurs.  In practice, real hardware updates
1493          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1494          * (namely Hyper-V) don't set it due to it being undefined behavior,
1495          * i.e. we end up advancing IP with some random value.
1496          */
1497         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1498             exit_reason.basic != EXIT_REASON_EPT_MISCONFIG) {
1499                 instr_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1500
1501                 /*
1502                  * Emulating an enclave's instructions isn't supported as KVM
1503                  * cannot access the enclave's memory or its true RIP, e.g. the
1504                  * vmcs.GUEST_RIP points at the exit point of the enclave, not
1505                  * the RIP that actually triggered the VM-Exit.  But, because
1506                  * most instructions that cause VM-Exit will #UD in an enclave,
1507                  * most instruction-based VM-Exits simply do not occur.
1508                  *
1509                  * There are a few exceptions, notably the debug instructions
1510                  * INT1ICEBRK and INT3, as they are allowed in debug enclaves
1511                  * and generate #DB/#BP as expected, which KVM might intercept.
1512                  * But again, the CPU does the dirty work and saves an instr
1513                  * length of zero so VMMs don't shoot themselves in the foot.
1514                  * WARN if KVM tries to skip a non-zero length instruction on
1515                  * a VM-Exit from an enclave.
1516                  */
1517                 if (!instr_len)
1518                         goto rip_updated;
1519
1520                 WARN(exit_reason.enclave_mode,
1521                      "KVM: skipping instruction after SGX enclave VM-Exit");
1522
1523                 orig_rip = kvm_rip_read(vcpu);
1524                 rip = orig_rip + instr_len;
1525 #ifdef CONFIG_X86_64
1526                 /*
1527                  * We need to mask out the high 32 bits of RIP if not in 64-bit
1528                  * mode, but just finding out that we are in 64-bit mode is
1529                  * quite expensive.  Only do it if there was a carry.
1530                  */
1531                 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1532                         rip = (u32)rip;
1533 #endif
1534                 kvm_rip_write(vcpu, rip);
1535         } else {
1536                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1537                         return 0;
1538         }
1539
1540 rip_updated:
1541         /* skipping an emulated instruction also counts */
1542         vmx_set_interrupt_shadow(vcpu, 0);
1543
1544         return 1;
1545 }
1546
1547 /*
1548  * Recognizes a pending MTF VM-exit and records the nested state for later
1549  * delivery.
1550  */
1551 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1552 {
1553         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1554         struct vcpu_vmx *vmx = to_vmx(vcpu);
1555
1556         if (!is_guest_mode(vcpu))
1557                 return;
1558
1559         /*
1560          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1561          * T-bit traps. As instruction emulation is completed (i.e. at the
1562          * instruction boundary), any #DB exception pending delivery must be a
1563          * debug-trap. Record the pending MTF state to be delivered in
1564          * vmx_check_nested_events().
1565          */
1566         if (nested_cpu_has_mtf(vmcs12) &&
1567             (!vcpu->arch.exception.pending ||
1568              vcpu->arch.exception.nr == DB_VECTOR))
1569                 vmx->nested.mtf_pending = true;
1570         else
1571                 vmx->nested.mtf_pending = false;
1572 }
1573
1574 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1575 {
1576         vmx_update_emulated_instruction(vcpu);
1577         return skip_emulated_instruction(vcpu);
1578 }
1579
1580 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1581 {
1582         /*
1583          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1584          * explicitly skip the instruction because if the HLT state is set,
1585          * then the instruction is already executing and RIP has already been
1586          * advanced.
1587          */
1588         if (kvm_hlt_in_guest(vcpu->kvm) &&
1589                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1590                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1591 }
1592
1593 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1594 {
1595         struct vcpu_vmx *vmx = to_vmx(vcpu);
1596         unsigned nr = vcpu->arch.exception.nr;
1597         bool has_error_code = vcpu->arch.exception.has_error_code;
1598         u32 error_code = vcpu->arch.exception.error_code;
1599         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1600
1601         kvm_deliver_exception_payload(vcpu);
1602
1603         if (has_error_code) {
1604                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1605                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1606         }
1607
1608         if (vmx->rmode.vm86_active) {
1609                 int inc_eip = 0;
1610                 if (kvm_exception_is_soft(nr))
1611                         inc_eip = vcpu->arch.event_exit_inst_len;
1612                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1613                 return;
1614         }
1615
1616         WARN_ON_ONCE(vmx->emulation_required);
1617
1618         if (kvm_exception_is_soft(nr)) {
1619                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1620                              vmx->vcpu.arch.event_exit_inst_len);
1621                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1622         } else
1623                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1624
1625         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1626
1627         vmx_clear_hlt(vcpu);
1628 }
1629
1630 static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr,
1631                                bool load_into_hardware)
1632 {
1633         struct vmx_uret_msr *uret_msr;
1634
1635         uret_msr = vmx_find_uret_msr(vmx, msr);
1636         if (!uret_msr)
1637                 return;
1638
1639         uret_msr->load_into_hardware = load_into_hardware;
1640 }
1641
1642 /*
1643  * Configuring user return MSRs to automatically save, load, and restore MSRs
1644  * that need to be shoved into hardware when running the guest.  Note, omitting
1645  * an MSR here does _NOT_ mean it's not emulated, only that it will not be
1646  * loaded into hardware when running the guest.
1647  */
1648 static void vmx_setup_uret_msrs(struct vcpu_vmx *vmx)
1649 {
1650 #ifdef CONFIG_X86_64
1651         bool load_syscall_msrs;
1652
1653         /*
1654          * The SYSCALL MSRs are only needed on long mode guests, and only
1655          * when EFER.SCE is set.
1656          */
1657         load_syscall_msrs = is_long_mode(&vmx->vcpu) &&
1658                             (vmx->vcpu.arch.efer & EFER_SCE);
1659
1660         vmx_setup_uret_msr(vmx, MSR_STAR, load_syscall_msrs);
1661         vmx_setup_uret_msr(vmx, MSR_LSTAR, load_syscall_msrs);
1662         vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK, load_syscall_msrs);
1663 #endif
1664         vmx_setup_uret_msr(vmx, MSR_EFER, update_transition_efer(vmx));
1665
1666         vmx_setup_uret_msr(vmx, MSR_TSC_AUX,
1667                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP) ||
1668                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDPID));
1669
1670         /*
1671          * hle=0, rtm=0, tsx_ctrl=1 can be found with some combinations of new
1672          * kernel and old userspace.  If those guests run on a tsx=off host, do
1673          * allow guests to use TSX_CTRL, but don't change the value in hardware
1674          * so that TSX remains always disabled.
1675          */
1676         vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL, boot_cpu_has(X86_FEATURE_RTM));
1677
1678         /*
1679          * The set of MSRs to load may have changed, reload MSRs before the
1680          * next VM-Enter.
1681          */
1682         vmx->guest_uret_msrs_loaded = false;
1683 }
1684
1685 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1686 {
1687         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1688
1689         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING))
1690                 return vmcs12->tsc_offset;
1691
1692         return 0;
1693 }
1694
1695 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1696 {
1697         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1698
1699         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING) &&
1700             nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
1701                 return vmcs12->tsc_multiplier;
1702
1703         return kvm_default_tsc_scaling_ratio;
1704 }
1705
1706 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1707 {
1708         vmcs_write64(TSC_OFFSET, offset);
1709 }
1710
1711 static void vmx_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1712 {
1713         vmcs_write64(TSC_MULTIPLIER, multiplier);
1714 }
1715
1716 /*
1717  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1718  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1719  * all guests if the "nested" module option is off, and can also be disabled
1720  * for a single guest by disabling its VMX cpuid bit.
1721  */
1722 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1723 {
1724         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1725 }
1726
1727 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1728                                                  uint64_t val)
1729 {
1730         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1731
1732         return !(val & ~valid_bits);
1733 }
1734
1735 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1736 {
1737         switch (msr->index) {
1738         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1739                 if (!nested)
1740                         return 1;
1741                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1742         case MSR_IA32_PERF_CAPABILITIES:
1743                 msr->data = vmx_get_perf_capabilities();
1744                 return 0;
1745         default:
1746                 return KVM_MSR_RET_INVALID;
1747         }
1748 }
1749
1750 /*
1751  * Reads an msr value (of 'msr_index') into 'pdata'.
1752  * Returns 0 on success, non-0 otherwise.
1753  * Assumes vcpu_load() was already called.
1754  */
1755 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1756 {
1757         struct vcpu_vmx *vmx = to_vmx(vcpu);
1758         struct vmx_uret_msr *msr;
1759         u32 index;
1760
1761         switch (msr_info->index) {
1762 #ifdef CONFIG_X86_64
1763         case MSR_FS_BASE:
1764                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1765                 break;
1766         case MSR_GS_BASE:
1767                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1768                 break;
1769         case MSR_KERNEL_GS_BASE:
1770                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1771                 break;
1772 #endif
1773         case MSR_EFER:
1774                 return kvm_get_msr_common(vcpu, msr_info);
1775         case MSR_IA32_TSX_CTRL:
1776                 if (!msr_info->host_initiated &&
1777                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1778                         return 1;
1779                 goto find_uret_msr;
1780         case MSR_IA32_UMWAIT_CONTROL:
1781                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1782                         return 1;
1783
1784                 msr_info->data = vmx->msr_ia32_umwait_control;
1785                 break;
1786         case MSR_IA32_SPEC_CTRL:
1787                 if (!msr_info->host_initiated &&
1788                     !guest_has_spec_ctrl_msr(vcpu))
1789                         return 1;
1790
1791                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1792                 break;
1793         case MSR_IA32_SYSENTER_CS:
1794                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1795                 break;
1796         case MSR_IA32_SYSENTER_EIP:
1797                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1798                 break;
1799         case MSR_IA32_SYSENTER_ESP:
1800                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1801                 break;
1802         case MSR_IA32_BNDCFGS:
1803                 if (!kvm_mpx_supported() ||
1804                     (!msr_info->host_initiated &&
1805                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1806                         return 1;
1807                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1808                 break;
1809         case MSR_IA32_MCG_EXT_CTL:
1810                 if (!msr_info->host_initiated &&
1811                     !(vmx->msr_ia32_feature_control &
1812                       FEAT_CTL_LMCE_ENABLED))
1813                         return 1;
1814                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1815                 break;
1816         case MSR_IA32_FEAT_CTL:
1817                 msr_info->data = vmx->msr_ia32_feature_control;
1818                 break;
1819         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
1820                 if (!msr_info->host_initiated &&
1821                     !guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
1822                         return 1;
1823                 msr_info->data = to_vmx(vcpu)->msr_ia32_sgxlepubkeyhash
1824                         [msr_info->index - MSR_IA32_SGXLEPUBKEYHASH0];
1825                 break;
1826         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1827                 if (!nested_vmx_allowed(vcpu))
1828                         return 1;
1829                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1830                                     &msr_info->data))
1831                         return 1;
1832                 /*
1833                  * Enlightened VMCS v1 doesn't have certain VMCS fields but
1834                  * instead of just ignoring the features, different Hyper-V
1835                  * versions are either trying to use them and fail or do some
1836                  * sanity checking and refuse to boot. Filter all unsupported
1837                  * features out.
1838                  */
1839                 if (!msr_info->host_initiated &&
1840                     vmx->nested.enlightened_vmcs_enabled)
1841                         nested_evmcs_filter_control_msr(msr_info->index,
1842                                                         &msr_info->data);
1843                 break;
1844         case MSR_IA32_RTIT_CTL:
1845                 if (!vmx_pt_mode_is_host_guest())
1846                         return 1;
1847                 msr_info->data = vmx->pt_desc.guest.ctl;
1848                 break;
1849         case MSR_IA32_RTIT_STATUS:
1850                 if (!vmx_pt_mode_is_host_guest())
1851                         return 1;
1852                 msr_info->data = vmx->pt_desc.guest.status;
1853                 break;
1854         case MSR_IA32_RTIT_CR3_MATCH:
1855                 if (!vmx_pt_mode_is_host_guest() ||
1856                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1857                                                 PT_CAP_cr3_filtering))
1858                         return 1;
1859                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1860                 break;
1861         case MSR_IA32_RTIT_OUTPUT_BASE:
1862                 if (!vmx_pt_mode_is_host_guest() ||
1863                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1864                                         PT_CAP_topa_output) &&
1865                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1866                                         PT_CAP_single_range_output)))
1867                         return 1;
1868                 msr_info->data = vmx->pt_desc.guest.output_base;
1869                 break;
1870         case MSR_IA32_RTIT_OUTPUT_MASK:
1871                 if (!vmx_pt_mode_is_host_guest() ||
1872                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1873                                         PT_CAP_topa_output) &&
1874                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1875                                         PT_CAP_single_range_output)))
1876                         return 1;
1877                 msr_info->data = vmx->pt_desc.guest.output_mask;
1878                 break;
1879         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1880                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1881                 if (!vmx_pt_mode_is_host_guest() ||
1882                     (index >= 2 * vmx->pt_desc.num_address_ranges))
1883                         return 1;
1884                 if (index % 2)
1885                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1886                 else
1887                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1888                 break;
1889         case MSR_IA32_DEBUGCTLMSR:
1890                 msr_info->data = vmcs_read64(GUEST_IA32_DEBUGCTL);
1891                 break;
1892         default:
1893         find_uret_msr:
1894                 msr = vmx_find_uret_msr(vmx, msr_info->index);
1895                 if (msr) {
1896                         msr_info->data = msr->data;
1897                         break;
1898                 }
1899                 return kvm_get_msr_common(vcpu, msr_info);
1900         }
1901
1902         return 0;
1903 }
1904
1905 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1906                                                     u64 data)
1907 {
1908 #ifdef CONFIG_X86_64
1909         if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1910                 return (u32)data;
1911 #endif
1912         return (unsigned long)data;
1913 }
1914
1915 static u64 vcpu_supported_debugctl(struct kvm_vcpu *vcpu)
1916 {
1917         u64 debugctl = vmx_supported_debugctl();
1918
1919         if (!intel_pmu_lbr_is_enabled(vcpu))
1920                 debugctl &= ~DEBUGCTLMSR_LBR_MASK;
1921
1922         if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1923                 debugctl &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1924
1925         return debugctl;
1926 }
1927
1928 /*
1929  * Writes msr value into the appropriate "register".
1930  * Returns 0 on success, non-0 otherwise.
1931  * Assumes vcpu_load() was already called.
1932  */
1933 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1934 {
1935         struct vcpu_vmx *vmx = to_vmx(vcpu);
1936         struct vmx_uret_msr *msr;
1937         int ret = 0;
1938         u32 msr_index = msr_info->index;
1939         u64 data = msr_info->data;
1940         u32 index;
1941
1942         switch (msr_index) {
1943         case MSR_EFER:
1944                 ret = kvm_set_msr_common(vcpu, msr_info);
1945                 break;
1946 #ifdef CONFIG_X86_64
1947         case MSR_FS_BASE:
1948                 vmx_segment_cache_clear(vmx);
1949                 vmcs_writel(GUEST_FS_BASE, data);
1950                 break;
1951         case MSR_GS_BASE:
1952                 vmx_segment_cache_clear(vmx);
1953                 vmcs_writel(GUEST_GS_BASE, data);
1954                 break;
1955         case MSR_KERNEL_GS_BASE:
1956                 vmx_write_guest_kernel_gs_base(vmx, data);
1957                 break;
1958 #endif
1959         case MSR_IA32_SYSENTER_CS:
1960                 if (is_guest_mode(vcpu))
1961                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1962                 vmcs_write32(GUEST_SYSENTER_CS, data);
1963                 break;
1964         case MSR_IA32_SYSENTER_EIP:
1965                 if (is_guest_mode(vcpu)) {
1966                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1967                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1968                 }
1969                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1970                 break;
1971         case MSR_IA32_SYSENTER_ESP:
1972                 if (is_guest_mode(vcpu)) {
1973                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1974                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1975                 }
1976                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1977                 break;
1978         case MSR_IA32_DEBUGCTLMSR: {
1979                 u64 invalid = data & ~vcpu_supported_debugctl(vcpu);
1980                 if (invalid & (DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR)) {
1981                         if (report_ignored_msrs)
1982                                 vcpu_unimpl(vcpu, "%s: BTF|LBR in IA32_DEBUGCTLMSR 0x%llx, nop\n",
1983                                             __func__, data);
1984                         data &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1985                         invalid &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1986                 }
1987
1988                 if (invalid)
1989                         return 1;
1990
1991                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1992                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
1993                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1994
1995                 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
1996                 if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event &&
1997                     (data & DEBUGCTLMSR_LBR))
1998                         intel_pmu_create_guest_lbr_event(vcpu);
1999                 return 0;
2000         }
2001         case MSR_IA32_BNDCFGS:
2002                 if (!kvm_mpx_supported() ||
2003                     (!msr_info->host_initiated &&
2004                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2005                         return 1;
2006                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2007                     (data & MSR_IA32_BNDCFGS_RSVD))
2008                         return 1;
2009                 vmcs_write64(GUEST_BNDCFGS, data);
2010                 break;
2011         case MSR_IA32_UMWAIT_CONTROL:
2012                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2013                         return 1;
2014
2015                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2016                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2017                         return 1;
2018
2019                 vmx->msr_ia32_umwait_control = data;
2020                 break;
2021         case MSR_IA32_SPEC_CTRL:
2022                 if (!msr_info->host_initiated &&
2023                     !guest_has_spec_ctrl_msr(vcpu))
2024                         return 1;
2025
2026                 if (kvm_spec_ctrl_test_value(data))
2027                         return 1;
2028
2029                 vmx->spec_ctrl = data;
2030                 if (!data)
2031                         break;
2032
2033                 /*
2034                  * For non-nested:
2035                  * When it's written (to non-zero) for the first time, pass
2036                  * it through.
2037                  *
2038                  * For nested:
2039                  * The handling of the MSR bitmap for L2 guests is done in
2040                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2041                  * vmcs02.msr_bitmap here since it gets completely overwritten
2042                  * in the merging. We update the vmcs01 here for L1 as well
2043                  * since it will end up touching the MSR anyway now.
2044                  */
2045                 vmx_disable_intercept_for_msr(vcpu,
2046                                               MSR_IA32_SPEC_CTRL,
2047                                               MSR_TYPE_RW);
2048                 break;
2049         case MSR_IA32_TSX_CTRL:
2050                 if (!msr_info->host_initiated &&
2051                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2052                         return 1;
2053                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2054                         return 1;
2055                 goto find_uret_msr;
2056         case MSR_IA32_PRED_CMD:
2057                 if (!msr_info->host_initiated &&
2058                     !guest_has_pred_cmd_msr(vcpu))
2059                         return 1;
2060
2061                 if (data & ~PRED_CMD_IBPB)
2062                         return 1;
2063                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2064                         return 1;
2065                 if (!data)
2066                         break;
2067
2068                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2069
2070                 /*
2071                  * For non-nested:
2072                  * When it's written (to non-zero) for the first time, pass
2073                  * it through.
2074                  *
2075                  * For nested:
2076                  * The handling of the MSR bitmap for L2 guests is done in
2077                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2078                  * vmcs02.msr_bitmap here since it gets completely overwritten
2079                  * in the merging.
2080                  */
2081                 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
2082                 break;
2083         case MSR_IA32_CR_PAT:
2084                 if (!kvm_pat_valid(data))
2085                         return 1;
2086
2087                 if (is_guest_mode(vcpu) &&
2088                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2089                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2090
2091                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2092                         vmcs_write64(GUEST_IA32_PAT, data);
2093                         vcpu->arch.pat = data;
2094                         break;
2095                 }
2096                 ret = kvm_set_msr_common(vcpu, msr_info);
2097                 break;
2098         case MSR_IA32_TSC_ADJUST:
2099                 ret = kvm_set_msr_common(vcpu, msr_info);
2100                 break;
2101         case MSR_IA32_MCG_EXT_CTL:
2102                 if ((!msr_info->host_initiated &&
2103                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2104                        FEAT_CTL_LMCE_ENABLED)) ||
2105                     (data & ~MCG_EXT_CTL_LMCE_EN))
2106                         return 1;
2107                 vcpu->arch.mcg_ext_ctl = data;
2108                 break;
2109         case MSR_IA32_FEAT_CTL:
2110                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2111                     (to_vmx(vcpu)->msr_ia32_feature_control &
2112                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2113                         return 1;
2114                 vmx->msr_ia32_feature_control = data;
2115                 if (msr_info->host_initiated && data == 0)
2116                         vmx_leave_nested(vcpu);
2117
2118                 /* SGX may be enabled/disabled by guest's firmware */
2119                 vmx_write_encls_bitmap(vcpu, NULL);
2120                 break;
2121         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
2122                 /*
2123                  * On real hardware, the LE hash MSRs are writable before
2124                  * the firmware sets bit 0 in MSR 0x7a ("activating" SGX),
2125                  * at which point SGX related bits in IA32_FEATURE_CONTROL
2126                  * become writable.
2127                  *
2128                  * KVM does not emulate SGX activation for simplicity, so
2129                  * allow writes to the LE hash MSRs if IA32_FEATURE_CONTROL
2130                  * is unlocked.  This is technically not architectural
2131                  * behavior, but it's close enough.
2132                  */
2133                 if (!msr_info->host_initiated &&
2134                     (!guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC) ||
2135                     ((vmx->msr_ia32_feature_control & FEAT_CTL_LOCKED) &&
2136                     !(vmx->msr_ia32_feature_control & FEAT_CTL_SGX_LC_ENABLED))))
2137                         return 1;
2138                 vmx->msr_ia32_sgxlepubkeyhash
2139                         [msr_index - MSR_IA32_SGXLEPUBKEYHASH0] = data;
2140                 break;
2141         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2142                 if (!msr_info->host_initiated)
2143                         return 1; /* they are read-only */
2144                 if (!nested_vmx_allowed(vcpu))
2145                         return 1;
2146                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2147         case MSR_IA32_RTIT_CTL:
2148                 if (!vmx_pt_mode_is_host_guest() ||
2149                         vmx_rtit_ctl_check(vcpu, data) ||
2150                         vmx->nested.vmxon)
2151                         return 1;
2152                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2153                 vmx->pt_desc.guest.ctl = data;
2154                 pt_update_intercept_for_msr(vcpu);
2155                 break;
2156         case MSR_IA32_RTIT_STATUS:
2157                 if (!pt_can_write_msr(vmx))
2158                         return 1;
2159                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2160                         return 1;
2161                 vmx->pt_desc.guest.status = data;
2162                 break;
2163         case MSR_IA32_RTIT_CR3_MATCH:
2164                 if (!pt_can_write_msr(vmx))
2165                         return 1;
2166                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2167                                            PT_CAP_cr3_filtering))
2168                         return 1;
2169                 vmx->pt_desc.guest.cr3_match = data;
2170                 break;
2171         case MSR_IA32_RTIT_OUTPUT_BASE:
2172                 if (!pt_can_write_msr(vmx))
2173                         return 1;
2174                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2175                                            PT_CAP_topa_output) &&
2176                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2177                                            PT_CAP_single_range_output))
2178                         return 1;
2179                 if (!pt_output_base_valid(vcpu, data))
2180                         return 1;
2181                 vmx->pt_desc.guest.output_base = data;
2182                 break;
2183         case MSR_IA32_RTIT_OUTPUT_MASK:
2184                 if (!pt_can_write_msr(vmx))
2185                         return 1;
2186                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2187                                            PT_CAP_topa_output) &&
2188                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2189                                            PT_CAP_single_range_output))
2190                         return 1;
2191                 vmx->pt_desc.guest.output_mask = data;
2192                 break;
2193         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2194                 if (!pt_can_write_msr(vmx))
2195                         return 1;
2196                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2197                 if (index >= 2 * vmx->pt_desc.num_address_ranges)
2198                         return 1;
2199                 if (is_noncanonical_address(data, vcpu))
2200                         return 1;
2201                 if (index % 2)
2202                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2203                 else
2204                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2205                 break;
2206         case MSR_IA32_PERF_CAPABILITIES:
2207                 if (data && !vcpu_to_pmu(vcpu)->version)
2208                         return 1;
2209                 if (data & PMU_CAP_LBR_FMT) {
2210                         if ((data & PMU_CAP_LBR_FMT) !=
2211                             (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
2212                                 return 1;
2213                         if (!intel_pmu_lbr_is_compatible(vcpu))
2214                                 return 1;
2215                 }
2216                 ret = kvm_set_msr_common(vcpu, msr_info);
2217                 break;
2218
2219         default:
2220         find_uret_msr:
2221                 msr = vmx_find_uret_msr(vmx, msr_index);
2222                 if (msr)
2223                         ret = vmx_set_guest_uret_msr(vmx, msr, data);
2224                 else
2225                         ret = kvm_set_msr_common(vcpu, msr_info);
2226         }
2227
2228         return ret;
2229 }
2230
2231 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2232 {
2233         unsigned long guest_owned_bits;
2234
2235         kvm_register_mark_available(vcpu, reg);
2236
2237         switch (reg) {
2238         case VCPU_REGS_RSP:
2239                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2240                 break;
2241         case VCPU_REGS_RIP:
2242                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2243                 break;
2244         case VCPU_EXREG_PDPTR:
2245                 if (enable_ept)
2246                         ept_save_pdptrs(vcpu);
2247                 break;
2248         case VCPU_EXREG_CR0:
2249                 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2250
2251                 vcpu->arch.cr0 &= ~guest_owned_bits;
2252                 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2253                 break;
2254         case VCPU_EXREG_CR3:
2255                 /*
2256                  * When intercepting CR3 loads, e.g. for shadowing paging, KVM's
2257                  * CR3 is loaded into hardware, not the guest's CR3.
2258                  */
2259                 if (!(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_CR3_LOAD_EXITING))
2260                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2261                 break;
2262         case VCPU_EXREG_CR4:
2263                 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2264
2265                 vcpu->arch.cr4 &= ~guest_owned_bits;
2266                 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2267                 break;
2268         default:
2269                 KVM_BUG_ON(1, vcpu->kvm);
2270                 break;
2271         }
2272 }
2273
2274 static __init int cpu_has_kvm_support(void)
2275 {
2276         return cpu_has_vmx();
2277 }
2278
2279 static __init int vmx_disabled_by_bios(void)
2280 {
2281         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2282                !boot_cpu_has(X86_FEATURE_VMX);
2283 }
2284
2285 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2286 {
2287         u64 msr;
2288
2289         cr4_set_bits(X86_CR4_VMXE);
2290
2291         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2292                           _ASM_EXTABLE(1b, %l[fault])
2293                           : : [vmxon_pointer] "m"(vmxon_pointer)
2294                           : : fault);
2295         return 0;
2296
2297 fault:
2298         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2299                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2300         cr4_clear_bits(X86_CR4_VMXE);
2301
2302         return -EFAULT;
2303 }
2304
2305 static int hardware_enable(void)
2306 {
2307         int cpu = raw_smp_processor_id();
2308         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2309         int r;
2310
2311         if (cr4_read_shadow() & X86_CR4_VMXE)
2312                 return -EBUSY;
2313
2314         /*
2315          * This can happen if we hot-added a CPU but failed to allocate
2316          * VP assist page for it.
2317          */
2318         if (static_branch_unlikely(&enable_evmcs) &&
2319             !hv_get_vp_assist_page(cpu))
2320                 return -EFAULT;
2321
2322         intel_pt_handle_vmx(1);
2323
2324         r = kvm_cpu_vmxon(phys_addr);
2325         if (r) {
2326                 intel_pt_handle_vmx(0);
2327                 return r;
2328         }
2329
2330         if (enable_ept)
2331                 ept_sync_global();
2332
2333         return 0;
2334 }
2335
2336 static void vmclear_local_loaded_vmcss(void)
2337 {
2338         int cpu = raw_smp_processor_id();
2339         struct loaded_vmcs *v, *n;
2340
2341         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2342                                  loaded_vmcss_on_cpu_link)
2343                 __loaded_vmcs_clear(v);
2344 }
2345
2346 static void hardware_disable(void)
2347 {
2348         vmclear_local_loaded_vmcss();
2349
2350         if (cpu_vmxoff())
2351                 kvm_spurious_fault();
2352
2353         intel_pt_handle_vmx(0);
2354 }
2355
2356 /*
2357  * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2358  * directly instead of going through cpu_has(), to ensure KVM is trapping
2359  * ENCLS whenever it's supported in hardware.  It does not matter whether
2360  * the host OS supports or has enabled SGX.
2361  */
2362 static bool cpu_has_sgx(void)
2363 {
2364         return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2365 }
2366
2367 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2368                                       u32 msr, u32 *result)
2369 {
2370         u32 vmx_msr_low, vmx_msr_high;
2371         u32 ctl = ctl_min | ctl_opt;
2372
2373         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2374
2375         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2376         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2377
2378         /* Ensure minimum (required) set of control bits are supported. */
2379         if (ctl_min & ~ctl)
2380                 return -EIO;
2381
2382         *result = ctl;
2383         return 0;
2384 }
2385
2386 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2387                                     struct vmx_capability *vmx_cap)
2388 {
2389         u32 vmx_msr_low, vmx_msr_high;
2390         u32 min, opt, min2, opt2;
2391         u32 _pin_based_exec_control = 0;
2392         u32 _cpu_based_exec_control = 0;
2393         u32 _cpu_based_2nd_exec_control = 0;
2394         u32 _vmexit_control = 0;
2395         u32 _vmentry_control = 0;
2396
2397         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2398         min = CPU_BASED_HLT_EXITING |
2399 #ifdef CONFIG_X86_64
2400               CPU_BASED_CR8_LOAD_EXITING |
2401               CPU_BASED_CR8_STORE_EXITING |
2402 #endif
2403               CPU_BASED_CR3_LOAD_EXITING |
2404               CPU_BASED_CR3_STORE_EXITING |
2405               CPU_BASED_UNCOND_IO_EXITING |
2406               CPU_BASED_MOV_DR_EXITING |
2407               CPU_BASED_USE_TSC_OFFSETTING |
2408               CPU_BASED_MWAIT_EXITING |
2409               CPU_BASED_MONITOR_EXITING |
2410               CPU_BASED_INVLPG_EXITING |
2411               CPU_BASED_RDPMC_EXITING;
2412
2413         opt = CPU_BASED_TPR_SHADOW |
2414               CPU_BASED_USE_MSR_BITMAPS |
2415               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2416         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2417                                 &_cpu_based_exec_control) < 0)
2418                 return -EIO;
2419 #ifdef CONFIG_X86_64
2420         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2421                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2422                                            ~CPU_BASED_CR8_STORE_EXITING;
2423 #endif
2424         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2425                 min2 = 0;
2426                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2427                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2428                         SECONDARY_EXEC_WBINVD_EXITING |
2429                         SECONDARY_EXEC_ENABLE_VPID |
2430                         SECONDARY_EXEC_ENABLE_EPT |
2431                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2432                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2433                         SECONDARY_EXEC_DESC |
2434                         SECONDARY_EXEC_ENABLE_RDTSCP |
2435                         SECONDARY_EXEC_ENABLE_INVPCID |
2436                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2437                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2438                         SECONDARY_EXEC_SHADOW_VMCS |
2439                         SECONDARY_EXEC_XSAVES |
2440                         SECONDARY_EXEC_RDSEED_EXITING |
2441                         SECONDARY_EXEC_RDRAND_EXITING |
2442                         SECONDARY_EXEC_ENABLE_PML |
2443                         SECONDARY_EXEC_TSC_SCALING |
2444                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2445                         SECONDARY_EXEC_PT_USE_GPA |
2446                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2447                         SECONDARY_EXEC_ENABLE_VMFUNC |
2448                         SECONDARY_EXEC_BUS_LOCK_DETECTION;
2449                 if (cpu_has_sgx())
2450                         opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2451                 if (adjust_vmx_controls(min2, opt2,
2452                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2453                                         &_cpu_based_2nd_exec_control) < 0)
2454                         return -EIO;
2455         }
2456 #ifndef CONFIG_X86_64
2457         if (!(_cpu_based_2nd_exec_control &
2458                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2459                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2460 #endif
2461
2462         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2463                 _cpu_based_2nd_exec_control &= ~(
2464                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2465                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2466                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2467
2468         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2469                 &vmx_cap->ept, &vmx_cap->vpid);
2470
2471         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2472                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2473                    enabled */
2474                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2475                                              CPU_BASED_CR3_STORE_EXITING |
2476                                              CPU_BASED_INVLPG_EXITING);
2477         } else if (vmx_cap->ept) {
2478                 vmx_cap->ept = 0;
2479                 pr_warn_once("EPT CAP should not exist if not support "
2480                                 "1-setting enable EPT VM-execution control\n");
2481         }
2482         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2483                 vmx_cap->vpid) {
2484                 vmx_cap->vpid = 0;
2485                 pr_warn_once("VPID CAP should not exist if not support "
2486                                 "1-setting enable VPID VM-execution control\n");
2487         }
2488
2489         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2490 #ifdef CONFIG_X86_64
2491         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2492 #endif
2493         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2494               VM_EXIT_LOAD_IA32_PAT |
2495               VM_EXIT_LOAD_IA32_EFER |
2496               VM_EXIT_CLEAR_BNDCFGS |
2497               VM_EXIT_PT_CONCEAL_PIP |
2498               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2499         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2500                                 &_vmexit_control) < 0)
2501                 return -EIO;
2502
2503         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2504         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2505                  PIN_BASED_VMX_PREEMPTION_TIMER;
2506         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2507                                 &_pin_based_exec_control) < 0)
2508                 return -EIO;
2509
2510         if (cpu_has_broken_vmx_preemption_timer())
2511                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2512         if (!(_cpu_based_2nd_exec_control &
2513                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2514                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2515
2516         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2517         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2518               VM_ENTRY_LOAD_IA32_PAT |
2519               VM_ENTRY_LOAD_IA32_EFER |
2520               VM_ENTRY_LOAD_BNDCFGS |
2521               VM_ENTRY_PT_CONCEAL_PIP |
2522               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2523         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2524                                 &_vmentry_control) < 0)
2525                 return -EIO;
2526
2527         /*
2528          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2529          * can't be used due to an errata where VM Exit may incorrectly clear
2530          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2531          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2532          */
2533         if (boot_cpu_data.x86 == 0x6) {
2534                 switch (boot_cpu_data.x86_model) {
2535                 case 26: /* AAK155 */
2536                 case 30: /* AAP115 */
2537                 case 37: /* AAT100 */
2538                 case 44: /* BC86,AAY89,BD102 */
2539                 case 46: /* BA97 */
2540                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2541                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2542                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2543                                         "does not work properly. Using workaround\n");
2544                         break;
2545                 default:
2546                         break;
2547                 }
2548         }
2549
2550
2551         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2552
2553         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2554         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2555                 return -EIO;
2556
2557 #ifdef CONFIG_X86_64
2558         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2559         if (vmx_msr_high & (1u<<16))
2560                 return -EIO;
2561 #endif
2562
2563         /* Require Write-Back (WB) memory type for VMCS accesses. */
2564         if (((vmx_msr_high >> 18) & 15) != 6)
2565                 return -EIO;
2566
2567         vmcs_conf->size = vmx_msr_high & 0x1fff;
2568         vmcs_conf->order = get_order(vmcs_conf->size);
2569         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2570
2571         vmcs_conf->revision_id = vmx_msr_low;
2572
2573         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2574         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2575         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2576         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2577         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2578
2579 #if IS_ENABLED(CONFIG_HYPERV)
2580         if (enlightened_vmcs)
2581                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2582 #endif
2583
2584         return 0;
2585 }
2586
2587 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2588 {
2589         int node = cpu_to_node(cpu);
2590         struct page *pages;
2591         struct vmcs *vmcs;
2592
2593         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2594         if (!pages)
2595                 return NULL;
2596         vmcs = page_address(pages);
2597         memset(vmcs, 0, vmcs_config.size);
2598
2599         /* KVM supports Enlightened VMCS v1 only */
2600         if (static_branch_unlikely(&enable_evmcs))
2601                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2602         else
2603                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2604
2605         if (shadow)
2606                 vmcs->hdr.shadow_vmcs = 1;
2607         return vmcs;
2608 }
2609
2610 void free_vmcs(struct vmcs *vmcs)
2611 {
2612         free_pages((unsigned long)vmcs, vmcs_config.order);
2613 }
2614
2615 /*
2616  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2617  */
2618 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2619 {
2620         if (!loaded_vmcs->vmcs)
2621                 return;
2622         loaded_vmcs_clear(loaded_vmcs);
2623         free_vmcs(loaded_vmcs->vmcs);
2624         loaded_vmcs->vmcs = NULL;
2625         if (loaded_vmcs->msr_bitmap)
2626                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2627         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2628 }
2629
2630 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2631 {
2632         loaded_vmcs->vmcs = alloc_vmcs(false);
2633         if (!loaded_vmcs->vmcs)
2634                 return -ENOMEM;
2635
2636         vmcs_clear(loaded_vmcs->vmcs);
2637
2638         loaded_vmcs->shadow_vmcs = NULL;
2639         loaded_vmcs->hv_timer_soft_disabled = false;
2640         loaded_vmcs->cpu = -1;
2641         loaded_vmcs->launched = 0;
2642
2643         if (cpu_has_vmx_msr_bitmap()) {
2644                 loaded_vmcs->msr_bitmap = (unsigned long *)
2645                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2646                 if (!loaded_vmcs->msr_bitmap)
2647                         goto out_vmcs;
2648                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2649
2650                 if (IS_ENABLED(CONFIG_HYPERV) &&
2651                     static_branch_unlikely(&enable_evmcs) &&
2652                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2653                         struct hv_enlightened_vmcs *evmcs =
2654                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2655
2656                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2657                 }
2658         }
2659
2660         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2661         memset(&loaded_vmcs->controls_shadow, 0,
2662                 sizeof(struct vmcs_controls_shadow));
2663
2664         return 0;
2665
2666 out_vmcs:
2667         free_loaded_vmcs(loaded_vmcs);
2668         return -ENOMEM;
2669 }
2670
2671 static void free_kvm_area(void)
2672 {
2673         int cpu;
2674
2675         for_each_possible_cpu(cpu) {
2676                 free_vmcs(per_cpu(vmxarea, cpu));
2677                 per_cpu(vmxarea, cpu) = NULL;
2678         }
2679 }
2680
2681 static __init int alloc_kvm_area(void)
2682 {
2683         int cpu;
2684
2685         for_each_possible_cpu(cpu) {
2686                 struct vmcs *vmcs;
2687
2688                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2689                 if (!vmcs) {
2690                         free_kvm_area();
2691                         return -ENOMEM;
2692                 }
2693
2694                 /*
2695                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2696                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2697                  * revision_id reported by MSR_IA32_VMX_BASIC.
2698                  *
2699                  * However, even though not explicitly documented by
2700                  * TLFS, VMXArea passed as VMXON argument should
2701                  * still be marked with revision_id reported by
2702                  * physical CPU.
2703                  */
2704                 if (static_branch_unlikely(&enable_evmcs))
2705                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2706
2707                 per_cpu(vmxarea, cpu) = vmcs;
2708         }
2709         return 0;
2710 }
2711
2712 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2713                 struct kvm_segment *save)
2714 {
2715         if (!emulate_invalid_guest_state) {
2716                 /*
2717                  * CS and SS RPL should be equal during guest entry according
2718                  * to VMX spec, but in reality it is not always so. Since vcpu
2719                  * is in the middle of the transition from real mode to
2720                  * protected mode it is safe to assume that RPL 0 is a good
2721                  * default value.
2722                  */
2723                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2724                         save->selector &= ~SEGMENT_RPL_MASK;
2725                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2726                 save->s = 1;
2727         }
2728         __vmx_set_segment(vcpu, save, seg);
2729 }
2730
2731 static void enter_pmode(struct kvm_vcpu *vcpu)
2732 {
2733         unsigned long flags;
2734         struct vcpu_vmx *vmx = to_vmx(vcpu);
2735
2736         /*
2737          * Update real mode segment cache. It may be not up-to-date if segment
2738          * register was written while vcpu was in a guest mode.
2739          */
2740         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2741         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2742         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2743         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2744         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2745         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2746
2747         vmx->rmode.vm86_active = 0;
2748
2749         __vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2750
2751         flags = vmcs_readl(GUEST_RFLAGS);
2752         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2753         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2754         vmcs_writel(GUEST_RFLAGS, flags);
2755
2756         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2757                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2758
2759         vmx_update_exception_bitmap(vcpu);
2760
2761         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2762         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2763         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2764         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2765         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2766         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2767 }
2768
2769 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2770 {
2771         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2772         struct kvm_segment var = *save;
2773
2774         var.dpl = 0x3;
2775         if (seg == VCPU_SREG_CS)
2776                 var.type = 0x3;
2777
2778         if (!emulate_invalid_guest_state) {
2779                 var.selector = var.base >> 4;
2780                 var.base = var.base & 0xffff0;
2781                 var.limit = 0xffff;
2782                 var.g = 0;
2783                 var.db = 0;
2784                 var.present = 1;
2785                 var.s = 1;
2786                 var.l = 0;
2787                 var.unusable = 0;
2788                 var.type = 0x3;
2789                 var.avl = 0;
2790                 if (save->base & 0xf)
2791                         printk_once(KERN_WARNING "kvm: segment base is not "
2792                                         "paragraph aligned when entering "
2793                                         "protected mode (seg=%d)", seg);
2794         }
2795
2796         vmcs_write16(sf->selector, var.selector);
2797         vmcs_writel(sf->base, var.base);
2798         vmcs_write32(sf->limit, var.limit);
2799         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2800 }
2801
2802 static void enter_rmode(struct kvm_vcpu *vcpu)
2803 {
2804         unsigned long flags;
2805         struct vcpu_vmx *vmx = to_vmx(vcpu);
2806         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2807
2808         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2809         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2810         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2811         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2812         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2813         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2814         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2815
2816         vmx->rmode.vm86_active = 1;
2817
2818         /*
2819          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2820          * vcpu. Warn the user that an update is overdue.
2821          */
2822         if (!kvm_vmx->tss_addr)
2823                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2824                              "called before entering vcpu\n");
2825
2826         vmx_segment_cache_clear(vmx);
2827
2828         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2829         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2830         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2831
2832         flags = vmcs_readl(GUEST_RFLAGS);
2833         vmx->rmode.save_rflags = flags;
2834
2835         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2836
2837         vmcs_writel(GUEST_RFLAGS, flags);
2838         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2839         vmx_update_exception_bitmap(vcpu);
2840
2841         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2842         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2843         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2844         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2845         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2846         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2847 }
2848
2849 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2850 {
2851         struct vcpu_vmx *vmx = to_vmx(vcpu);
2852         struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER);
2853
2854         /* Nothing to do if hardware doesn't support EFER. */
2855         if (!msr)
2856                 return 0;
2857
2858         vcpu->arch.efer = efer;
2859         if (efer & EFER_LMA) {
2860                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2861                 msr->data = efer;
2862         } else {
2863                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2864
2865                 msr->data = efer & ~EFER_LME;
2866         }
2867         vmx_setup_uret_msrs(vmx);
2868         return 0;
2869 }
2870
2871 #ifdef CONFIG_X86_64
2872
2873 static void enter_lmode(struct kvm_vcpu *vcpu)
2874 {
2875         u32 guest_tr_ar;
2876
2877         vmx_segment_cache_clear(to_vmx(vcpu));
2878
2879         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2880         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2881                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2882                                      __func__);
2883                 vmcs_write32(GUEST_TR_AR_BYTES,
2884                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2885                              | VMX_AR_TYPE_BUSY_64_TSS);
2886         }
2887         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2888 }
2889
2890 static void exit_lmode(struct kvm_vcpu *vcpu)
2891 {
2892         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2893         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2894 }
2895
2896 #endif
2897
2898 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2899 {
2900         struct vcpu_vmx *vmx = to_vmx(vcpu);
2901
2902         /*
2903          * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2904          * the CPU is not required to invalidate guest-physical mappings on
2905          * VM-Entry, even if VPID is disabled.  Guest-physical mappings are
2906          * associated with the root EPT structure and not any particular VPID
2907          * (INVVPID also isn't required to invalidate guest-physical mappings).
2908          */
2909         if (enable_ept) {
2910                 ept_sync_global();
2911         } else if (enable_vpid) {
2912                 if (cpu_has_vmx_invvpid_global()) {
2913                         vpid_sync_vcpu_global();
2914                 } else {
2915                         vpid_sync_vcpu_single(vmx->vpid);
2916                         vpid_sync_vcpu_single(vmx->nested.vpid02);
2917                 }
2918         }
2919 }
2920
2921 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2922 {
2923         struct kvm_mmu *mmu = vcpu->arch.mmu;
2924         u64 root_hpa = mmu->root_hpa;
2925
2926         /* No flush required if the current context is invalid. */
2927         if (!VALID_PAGE(root_hpa))
2928                 return;
2929
2930         if (enable_ept)
2931                 ept_sync_context(construct_eptp(vcpu, root_hpa,
2932                                                 mmu->shadow_root_level));
2933         else if (!is_guest_mode(vcpu))
2934                 vpid_sync_context(to_vmx(vcpu)->vpid);
2935         else
2936                 vpid_sync_context(nested_get_vpid02(vcpu));
2937 }
2938
2939 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2940 {
2941         /*
2942          * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2943          * vmx_flush_tlb_guest() for an explanation of why this is ok.
2944          */
2945         vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2946 }
2947
2948 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2949 {
2950         /*
2951          * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2952          * or a vpid couldn't be allocated for this vCPU.  VM-Enter and VM-Exit
2953          * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2954          * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2955          * i.e. no explicit INVVPID is necessary.
2956          */
2957         vpid_sync_context(to_vmx(vcpu)->vpid);
2958 }
2959
2960 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2961 {
2962         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2963
2964         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2965                 return;
2966
2967         if (is_pae_paging(vcpu)) {
2968                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2969                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2970                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2971                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2972         }
2973 }
2974
2975 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2976 {
2977         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2978
2979         if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2980                 return;
2981
2982         mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2983         mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2984         mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2985         mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2986
2987         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2988 }
2989
2990 #define CR3_EXITING_BITS (CPU_BASED_CR3_LOAD_EXITING | \
2991                           CPU_BASED_CR3_STORE_EXITING)
2992
2993 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2994 {
2995         struct vcpu_vmx *vmx = to_vmx(vcpu);
2996         unsigned long hw_cr0, old_cr0_pg;
2997         u32 tmp;
2998
2999         old_cr0_pg = kvm_read_cr0_bits(vcpu, X86_CR0_PG);
3000
3001         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3002         if (is_unrestricted_guest(vcpu))
3003                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3004         else {
3005                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3006                 if (!enable_ept)
3007                         hw_cr0 |= X86_CR0_WP;
3008
3009                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3010                         enter_pmode(vcpu);
3011
3012                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3013                         enter_rmode(vcpu);
3014         }
3015
3016         vmcs_writel(CR0_READ_SHADOW, cr0);
3017         vmcs_writel(GUEST_CR0, hw_cr0);
3018         vcpu->arch.cr0 = cr0;
3019         kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3020
3021 #ifdef CONFIG_X86_64
3022         if (vcpu->arch.efer & EFER_LME) {
3023                 if (!old_cr0_pg && (cr0 & X86_CR0_PG))
3024                         enter_lmode(vcpu);
3025                 else if (old_cr0_pg && !(cr0 & X86_CR0_PG))
3026                         exit_lmode(vcpu);
3027         }
3028 #endif
3029
3030         if (enable_ept && !is_unrestricted_guest(vcpu)) {
3031                 /*
3032                  * Ensure KVM has an up-to-date snapshot of the guest's CR3.  If
3033                  * the below code _enables_ CR3 exiting, vmx_cache_reg() will
3034                  * (correctly) stop reading vmcs.GUEST_CR3 because it thinks
3035                  * KVM's CR3 is installed.
3036                  */
3037                 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
3038                         vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
3039
3040                 /*
3041                  * When running with EPT but not unrestricted guest, KVM must
3042                  * intercept CR3 accesses when paging is _disabled_.  This is
3043                  * necessary because restricted guests can't actually run with
3044                  * paging disabled, and so KVM stuffs its own CR3 in order to
3045                  * run the guest when identity mapped page tables.
3046                  *
3047                  * Do _NOT_ check the old CR0.PG, e.g. to optimize away the
3048                  * update, it may be stale with respect to CR3 interception,
3049                  * e.g. after nested VM-Enter.
3050                  *
3051                  * Lastly, honor L1's desires, i.e. intercept CR3 loads and/or
3052                  * stores to forward them to L1, even if KVM does not need to
3053                  * intercept them to preserve its identity mapped page tables.
3054                  */
3055                 if (!(cr0 & X86_CR0_PG)) {
3056                         exec_controls_setbit(vmx, CR3_EXITING_BITS);
3057                 } else if (!is_guest_mode(vcpu)) {
3058                         exec_controls_clearbit(vmx, CR3_EXITING_BITS);
3059                 } else {
3060                         tmp = exec_controls_get(vmx);
3061                         tmp &= ~CR3_EXITING_BITS;
3062                         tmp |= get_vmcs12(vcpu)->cpu_based_vm_exec_control & CR3_EXITING_BITS;
3063                         exec_controls_set(vmx, tmp);
3064                 }
3065
3066                 /* Note, vmx_set_cr4() consumes the new vcpu->arch.cr0. */
3067                 if ((old_cr0_pg ^ cr0) & X86_CR0_PG)
3068                         vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3069         }
3070
3071         /* depends on vcpu->arch.cr0 to be set to a new value */
3072         vmx->emulation_required = vmx_emulation_required(vcpu);
3073 }
3074
3075 static int vmx_get_max_tdp_level(void)
3076 {
3077         if (cpu_has_vmx_ept_5levels())
3078                 return 5;
3079         return 4;
3080 }
3081
3082 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level)
3083 {
3084         u64 eptp = VMX_EPTP_MT_WB;
3085
3086         eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3087
3088         if (enable_ept_ad_bits &&
3089             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3090                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3091         eptp |= root_hpa;
3092
3093         return eptp;
3094 }
3095
3096 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3097                              int root_level)
3098 {
3099         struct kvm *kvm = vcpu->kvm;
3100         bool update_guest_cr3 = true;
3101         unsigned long guest_cr3;
3102         u64 eptp;
3103
3104         if (enable_ept) {
3105                 eptp = construct_eptp(vcpu, root_hpa, root_level);
3106                 vmcs_write64(EPT_POINTER, eptp);
3107
3108                 hv_track_root_tdp(vcpu, root_hpa);
3109
3110                 if (!enable_unrestricted_guest && !is_paging(vcpu))
3111                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3112                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3113                         guest_cr3 = vcpu->arch.cr3;
3114                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3115                         update_guest_cr3 = false;
3116                 vmx_ept_load_pdptrs(vcpu);
3117         } else {
3118                 guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu);
3119         }
3120
3121         if (update_guest_cr3)
3122                 vmcs_writel(GUEST_CR3, guest_cr3);
3123 }
3124
3125 static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3126 {
3127         /*
3128          * We operate under the default treatment of SMM, so VMX cannot be
3129          * enabled under SMM.  Note, whether or not VMXE is allowed at all is
3130          * handled by kvm_is_valid_cr4().
3131          */
3132         if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu))
3133                 return false;
3134
3135         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3136                 return false;
3137
3138         return true;
3139 }
3140
3141 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3142 {
3143         unsigned long old_cr4 = vcpu->arch.cr4;
3144         struct vcpu_vmx *vmx = to_vmx(vcpu);
3145         /*
3146          * Pass through host's Machine Check Enable value to hw_cr4, which
3147          * is in force while we are in guest mode.  Do not let guests control
3148          * this bit, even if host CR4.MCE == 0.
3149          */
3150         unsigned long hw_cr4;
3151
3152         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3153         if (is_unrestricted_guest(vcpu))
3154                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3155         else if (vmx->rmode.vm86_active)
3156                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3157         else
3158                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3159
3160         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3161                 if (cr4 & X86_CR4_UMIP) {
3162                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3163                         hw_cr4 &= ~X86_CR4_UMIP;
3164                 } else if (!is_guest_mode(vcpu) ||
3165                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3166                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3167                 }
3168         }
3169
3170         vcpu->arch.cr4 = cr4;
3171         kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3172
3173         if (!is_unrestricted_guest(vcpu)) {
3174                 if (enable_ept) {
3175                         if (!is_paging(vcpu)) {
3176                                 hw_cr4 &= ~X86_CR4_PAE;
3177                                 hw_cr4 |= X86_CR4_PSE;
3178                         } else if (!(cr4 & X86_CR4_PAE)) {
3179                                 hw_cr4 &= ~X86_CR4_PAE;
3180                         }
3181                 }
3182
3183                 /*
3184                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3185                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3186                  * to be manually disabled when guest switches to non-paging
3187                  * mode.
3188                  *
3189                  * If !enable_unrestricted_guest, the CPU is always running
3190                  * with CR0.PG=1 and CR4 needs to be modified.
3191                  * If enable_unrestricted_guest, the CPU automatically
3192                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3193                  */
3194                 if (!is_paging(vcpu))
3195                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3196         }
3197
3198         vmcs_writel(CR4_READ_SHADOW, cr4);
3199         vmcs_writel(GUEST_CR4, hw_cr4);
3200
3201         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
3202                 kvm_update_cpuid_runtime(vcpu);
3203 }
3204
3205 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3206 {
3207         struct vcpu_vmx *vmx = to_vmx(vcpu);
3208         u32 ar;
3209
3210         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3211                 *var = vmx->rmode.segs[seg];
3212                 if (seg == VCPU_SREG_TR
3213                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3214                         return;
3215                 var->base = vmx_read_guest_seg_base(vmx, seg);
3216                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3217                 return;
3218         }
3219         var->base = vmx_read_guest_seg_base(vmx, seg);
3220         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3221         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3222         ar = vmx_read_guest_seg_ar(vmx, seg);
3223         var->unusable = (ar >> 16) & 1;
3224         var->type = ar & 15;
3225         var->s = (ar >> 4) & 1;
3226         var->dpl = (ar >> 5) & 3;
3227         /*
3228          * Some userspaces do not preserve unusable property. Since usable
3229          * segment has to be present according to VMX spec we can use present
3230          * property to amend userspace bug by making unusable segment always
3231          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3232          * segment as unusable.
3233          */
3234         var->present = !var->unusable;
3235         var->avl = (ar >> 12) & 1;
3236         var->l = (ar >> 13) & 1;
3237         var->db = (ar >> 14) & 1;
3238         var->g = (ar >> 15) & 1;
3239 }
3240
3241 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3242 {
3243         struct kvm_segment s;
3244
3245         if (to_vmx(vcpu)->rmode.vm86_active) {
3246                 vmx_get_segment(vcpu, &s, seg);
3247                 return s.base;
3248         }
3249         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3250 }
3251
3252 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3253 {
3254         struct vcpu_vmx *vmx = to_vmx(vcpu);
3255
3256         if (unlikely(vmx->rmode.vm86_active))
3257                 return 0;
3258         else {
3259                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3260                 return VMX_AR_DPL(ar);
3261         }
3262 }
3263
3264 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3265 {
3266         u32 ar;
3267
3268         if (var->unusable || !var->present)
3269                 ar = 1 << 16;
3270         else {
3271                 ar = var->type & 15;
3272                 ar |= (var->s & 1) << 4;
3273                 ar |= (var->dpl & 3) << 5;
3274                 ar |= (var->present & 1) << 7;
3275                 ar |= (var->avl & 1) << 12;
3276                 ar |= (var->l & 1) << 13;
3277                 ar |= (var->db & 1) << 14;
3278                 ar |= (var->g & 1) << 15;
3279         }
3280
3281         return ar;
3282 }
3283
3284 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3285 {
3286         struct vcpu_vmx *vmx = to_vmx(vcpu);
3287         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3288
3289         vmx_segment_cache_clear(vmx);
3290
3291         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3292                 vmx->rmode.segs[seg] = *var;
3293                 if (seg == VCPU_SREG_TR)
3294                         vmcs_write16(sf->selector, var->selector);
3295                 else if (var->s)
3296                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3297                 return;
3298         }
3299
3300         vmcs_writel(sf->base, var->base);
3301         vmcs_write32(sf->limit, var->limit);
3302         vmcs_write16(sf->selector, var->selector);
3303
3304         /*
3305          *   Fix the "Accessed" bit in AR field of segment registers for older
3306          * qemu binaries.
3307          *   IA32 arch specifies that at the time of processor reset the
3308          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3309          * is setting it to 0 in the userland code. This causes invalid guest
3310          * state vmexit when "unrestricted guest" mode is turned on.
3311          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3312          * tree. Newer qemu binaries with that qemu fix would not need this
3313          * kvm hack.
3314          */
3315         if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3316                 var->type |= 0x1; /* Accessed */
3317
3318         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3319 }
3320
3321 static void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3322 {
3323         __vmx_set_segment(vcpu, var, seg);
3324
3325         to_vmx(vcpu)->emulation_required = vmx_emulation_required(vcpu);
3326 }
3327
3328 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3329 {
3330         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3331
3332         *db = (ar >> 14) & 1;
3333         *l = (ar >> 13) & 1;
3334 }
3335
3336 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3337 {
3338         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3339         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3340 }
3341
3342 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3343 {
3344         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3345         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3346 }
3347
3348 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3349 {
3350         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3351         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3352 }
3353
3354 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3355 {
3356         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3357         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3358 }
3359
3360 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3361 {
3362         struct kvm_segment var;
3363         u32 ar;
3364
3365         vmx_get_segment(vcpu, &var, seg);
3366         var.dpl = 0x3;
3367         if (seg == VCPU_SREG_CS)
3368                 var.type = 0x3;
3369         ar = vmx_segment_access_rights(&var);
3370
3371         if (var.base != (var.selector << 4))
3372                 return false;
3373         if (var.limit != 0xffff)
3374                 return false;
3375         if (ar != 0xf3)
3376                 return false;
3377
3378         return true;
3379 }
3380
3381 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3382 {
3383         struct kvm_segment cs;
3384         unsigned int cs_rpl;
3385
3386         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3387         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3388
3389         if (cs.unusable)
3390                 return false;
3391         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3392                 return false;
3393         if (!cs.s)
3394                 return false;
3395         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3396                 if (cs.dpl > cs_rpl)
3397                         return false;
3398         } else {
3399                 if (cs.dpl != cs_rpl)
3400                         return false;
3401         }
3402         if (!cs.present)
3403                 return false;
3404
3405         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3406         return true;
3407 }
3408
3409 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3410 {
3411         struct kvm_segment ss;
3412         unsigned int ss_rpl;
3413
3414         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3415         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3416
3417         if (ss.unusable)
3418                 return true;
3419         if (ss.type != 3 && ss.type != 7)
3420                 return false;
3421         if (!ss.s)
3422                 return false;
3423         if (ss.dpl != ss_rpl) /* DPL != RPL */
3424                 return false;
3425         if (!ss.present)
3426                 return false;
3427
3428         return true;
3429 }
3430
3431 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3432 {
3433         struct kvm_segment var;
3434         unsigned int rpl;
3435
3436         vmx_get_segment(vcpu, &var, seg);
3437         rpl = var.selector & SEGMENT_RPL_MASK;
3438
3439         if (var.unusable)
3440                 return true;
3441         if (!var.s)
3442                 return false;
3443         if (!var.present)
3444                 return false;
3445         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3446                 if (var.dpl < rpl) /* DPL < RPL */
3447                         return false;
3448         }
3449
3450         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3451          * rights flags
3452          */
3453         return true;
3454 }
3455
3456 static bool tr_valid(struct kvm_vcpu *vcpu)
3457 {
3458         struct kvm_segment tr;
3459
3460         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3461
3462         if (tr.unusable)
3463                 return false;
3464         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3465                 return false;
3466         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3467                 return false;
3468         if (!tr.present)
3469                 return false;
3470
3471         return true;
3472 }
3473
3474 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3475 {
3476         struct kvm_segment ldtr;
3477
3478         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3479
3480         if (ldtr.unusable)
3481                 return true;
3482         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3483                 return false;
3484         if (ldtr.type != 2)
3485                 return false;
3486         if (!ldtr.present)
3487                 return false;
3488
3489         return true;
3490 }
3491
3492 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3493 {
3494         struct kvm_segment cs, ss;
3495
3496         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3497         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3498
3499         return ((cs.selector & SEGMENT_RPL_MASK) ==
3500                  (ss.selector & SEGMENT_RPL_MASK));
3501 }
3502
3503 /*
3504  * Check if guest state is valid. Returns true if valid, false if
3505  * not.
3506  * We assume that registers are always usable
3507  */
3508 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu)
3509 {
3510         /* real mode guest state checks */
3511         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3512                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3513                         return false;
3514                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3515                         return false;
3516                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3517                         return false;
3518                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3519                         return false;
3520                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3521                         return false;
3522                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3523                         return false;
3524         } else {
3525         /* protected mode guest state checks */
3526                 if (!cs_ss_rpl_check(vcpu))
3527                         return false;
3528                 if (!code_segment_valid(vcpu))
3529                         return false;
3530                 if (!stack_segment_valid(vcpu))
3531                         return false;
3532                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3533                         return false;
3534                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3535                         return false;
3536                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3537                         return false;
3538                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3539                         return false;
3540                 if (!tr_valid(vcpu))
3541                         return false;
3542                 if (!ldtr_valid(vcpu))
3543                         return false;
3544         }
3545         /* TODO:
3546          * - Add checks on RIP
3547          * - Add checks on RFLAGS
3548          */
3549
3550         return true;
3551 }
3552
3553 static int init_rmode_tss(struct kvm *kvm, void __user *ua)
3554 {
3555         const void *zero_page = (const void *) __va(page_to_phys(ZERO_PAGE(0)));
3556         u16 data;
3557         int i;
3558
3559         for (i = 0; i < 3; i++) {
3560                 if (__copy_to_user(ua + PAGE_SIZE * i, zero_page, PAGE_SIZE))
3561                         return -EFAULT;
3562         }
3563
3564         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3565         if (__copy_to_user(ua + TSS_IOPB_BASE_OFFSET, &data, sizeof(u16)))
3566                 return -EFAULT;
3567
3568         data = ~0;
3569         if (__copy_to_user(ua + RMODE_TSS_SIZE - 1, &data, sizeof(u8)))
3570                 return -EFAULT;
3571
3572         return 0;
3573 }
3574
3575 static int init_rmode_identity_map(struct kvm *kvm)
3576 {
3577         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3578         int i, r = 0;
3579         void __user *uaddr;
3580         u32 tmp;
3581
3582         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3583         mutex_lock(&kvm->slots_lock);
3584
3585         if (likely(kvm_vmx->ept_identity_pagetable_done))
3586                 goto out;
3587
3588         if (!kvm_vmx->ept_identity_map_addr)
3589                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3590
3591         uaddr = __x86_set_memory_region(kvm,
3592                                         IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3593                                         kvm_vmx->ept_identity_map_addr,
3594                                         PAGE_SIZE);
3595         if (IS_ERR(uaddr)) {
3596                 r = PTR_ERR(uaddr);
3597                 goto out;
3598         }
3599
3600         /* Set up identity-mapping pagetable for EPT in real mode */
3601         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3602                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3603                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3604                 if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) {
3605                         r = -EFAULT;
3606                         goto out;
3607                 }
3608         }
3609         kvm_vmx->ept_identity_pagetable_done = true;
3610
3611 out:
3612         mutex_unlock(&kvm->slots_lock);
3613         return r;
3614 }
3615
3616 static void seg_setup(int seg)
3617 {
3618         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3619         unsigned int ar;
3620
3621         vmcs_write16(sf->selector, 0);
3622         vmcs_writel(sf->base, 0);
3623         vmcs_write32(sf->limit, 0xffff);
3624         ar = 0x93;
3625         if (seg == VCPU_SREG_CS)
3626                 ar |= 0x08; /* code segment */
3627
3628         vmcs_write32(sf->ar_bytes, ar);
3629 }
3630
3631 static int alloc_apic_access_page(struct kvm *kvm)
3632 {
3633         struct page *page;
3634         void __user *hva;
3635         int ret = 0;
3636
3637         mutex_lock(&kvm->slots_lock);
3638         if (kvm->arch.apic_access_memslot_enabled)
3639                 goto out;
3640         hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3641                                       APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3642         if (IS_ERR(hva)) {
3643                 ret = PTR_ERR(hva);
3644                 goto out;
3645         }
3646
3647         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3648         if (is_error_page(page)) {
3649                 ret = -EFAULT;
3650                 goto out;
3651         }
3652
3653         /*
3654          * Do not pin the page in memory, so that memory hot-unplug
3655          * is able to migrate it.
3656          */
3657         put_page(page);
3658         kvm->arch.apic_access_memslot_enabled = true;
3659 out:
3660         mutex_unlock(&kvm->slots_lock);
3661         return ret;
3662 }
3663
3664 int allocate_vpid(void)
3665 {
3666         int vpid;
3667
3668         if (!enable_vpid)
3669                 return 0;
3670         spin_lock(&vmx_vpid_lock);
3671         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3672         if (vpid < VMX_NR_VPIDS)
3673                 __set_bit(vpid, vmx_vpid_bitmap);
3674         else
3675                 vpid = 0;
3676         spin_unlock(&vmx_vpid_lock);
3677         return vpid;
3678 }
3679
3680 void free_vpid(int vpid)
3681 {
3682         if (!enable_vpid || vpid == 0)
3683                 return;
3684         spin_lock(&vmx_vpid_lock);
3685         __clear_bit(vpid, vmx_vpid_bitmap);
3686         spin_unlock(&vmx_vpid_lock);
3687 }
3688
3689 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3690 {
3691         struct vcpu_vmx *vmx = to_vmx(vcpu);
3692         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3693
3694         if (!cpu_has_vmx_msr_bitmap())
3695                 return;
3696
3697         if (static_branch_unlikely(&enable_evmcs))
3698                 evmcs_touch_msr_bitmap();
3699
3700         /*
3701          * Mark the desired intercept state in shadow bitmap, this is needed
3702          * for resync when the MSR filters change.
3703         */
3704         if (is_valid_passthrough_msr(msr)) {
3705                 int idx = possible_passthrough_msr_slot(msr);
3706
3707                 if (idx != -ENOENT) {
3708                         if (type & MSR_TYPE_R)
3709                                 clear_bit(idx, vmx->shadow_msr_intercept.read);
3710                         if (type & MSR_TYPE_W)
3711                                 clear_bit(idx, vmx->shadow_msr_intercept.write);
3712                 }
3713         }
3714
3715         if ((type & MSR_TYPE_R) &&
3716             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) {
3717                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3718                 type &= ~MSR_TYPE_R;
3719         }
3720
3721         if ((type & MSR_TYPE_W) &&
3722             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) {
3723                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3724                 type &= ~MSR_TYPE_W;
3725         }
3726
3727         if (type & MSR_TYPE_R)
3728                 vmx_clear_msr_bitmap_read(msr_bitmap, msr);
3729
3730         if (type & MSR_TYPE_W)
3731                 vmx_clear_msr_bitmap_write(msr_bitmap, msr);
3732 }
3733
3734 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3735 {
3736         struct vcpu_vmx *vmx = to_vmx(vcpu);
3737         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3738
3739         if (!cpu_has_vmx_msr_bitmap())
3740                 return;
3741
3742         if (static_branch_unlikely(&enable_evmcs))
3743                 evmcs_touch_msr_bitmap();
3744
3745         /*
3746          * Mark the desired intercept state in shadow bitmap, this is needed
3747          * for resync when the MSR filter changes.
3748         */
3749         if (is_valid_passthrough_msr(msr)) {
3750                 int idx = possible_passthrough_msr_slot(msr);
3751
3752                 if (idx != -ENOENT) {
3753                         if (type & MSR_TYPE_R)
3754                                 set_bit(idx, vmx->shadow_msr_intercept.read);
3755                         if (type & MSR_TYPE_W)
3756                                 set_bit(idx, vmx->shadow_msr_intercept.write);
3757                 }
3758         }
3759
3760         if (type & MSR_TYPE_R)
3761                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3762
3763         if (type & MSR_TYPE_W)
3764                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3765 }
3766
3767 static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode)
3768 {
3769         unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
3770         unsigned long read_intercept;
3771         int msr;
3772
3773         read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3774
3775         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3776                 unsigned int read_idx = msr / BITS_PER_LONG;
3777                 unsigned int write_idx = read_idx + (0x800 / sizeof(long));
3778
3779                 msr_bitmap[read_idx] = read_intercept;
3780                 msr_bitmap[write_idx] = ~0ul;
3781         }
3782 }
3783
3784 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
3785 {
3786         struct vcpu_vmx *vmx = to_vmx(vcpu);
3787         u8 mode;
3788
3789         if (!cpu_has_vmx_msr_bitmap())
3790                 return;
3791
3792         if (cpu_has_secondary_exec_ctrls() &&
3793             (secondary_exec_controls_get(vmx) &
3794              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3795                 mode = MSR_BITMAP_MODE_X2APIC;
3796                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3797                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3798         } else {
3799                 mode = 0;
3800         }
3801
3802         if (mode == vmx->x2apic_msr_bitmap_mode)
3803                 return;
3804
3805         vmx->x2apic_msr_bitmap_mode = mode;
3806
3807         vmx_reset_x2apic_msrs(vcpu, mode);
3808
3809         /*
3810          * TPR reads and writes can be virtualized even if virtual interrupt
3811          * delivery is not in use.
3812          */
3813         vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
3814                                   !(mode & MSR_BITMAP_MODE_X2APIC));
3815
3816         if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3817                 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
3818                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3819                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3820         }
3821 }
3822
3823 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu)
3824 {
3825         struct vcpu_vmx *vmx = to_vmx(vcpu);
3826         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3827         u32 i;
3828
3829         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
3830         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
3831         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
3832         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
3833         for (i = 0; i < vmx->pt_desc.num_address_ranges; i++) {
3834                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3835                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3836         }
3837 }
3838
3839 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3840 {
3841         struct vcpu_vmx *vmx = to_vmx(vcpu);
3842         void *vapic_page;
3843         u32 vppr;
3844         int rvi;
3845
3846         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3847                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3848                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3849                 return false;
3850
3851         rvi = vmx_get_rvi();
3852
3853         vapic_page = vmx->nested.virtual_apic_map.hva;
3854         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3855
3856         return ((rvi & 0xf0) > (vppr & 0xf0));
3857 }
3858
3859 static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
3860 {
3861         struct vcpu_vmx *vmx = to_vmx(vcpu);
3862         u32 i;
3863
3864         /*
3865          * Set intercept permissions for all potentially passed through MSRs
3866          * again. They will automatically get filtered through the MSR filter,
3867          * so we are back in sync after this.
3868          */
3869         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
3870                 u32 msr = vmx_possible_passthrough_msrs[i];
3871                 bool read = test_bit(i, vmx->shadow_msr_intercept.read);
3872                 bool write = test_bit(i, vmx->shadow_msr_intercept.write);
3873
3874                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
3875                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
3876         }
3877
3878         pt_update_intercept_for_msr(vcpu);
3879 }
3880
3881 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3882                                                      bool nested)
3883 {
3884 #ifdef CONFIG_SMP
3885         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3886
3887         if (vcpu->mode == IN_GUEST_MODE) {
3888                 /*
3889                  * The vector of interrupt to be delivered to vcpu had
3890                  * been set in PIR before this function.
3891                  *
3892                  * Following cases will be reached in this block, and
3893                  * we always send a notification event in all cases as
3894                  * explained below.
3895                  *
3896                  * Case 1: vcpu keeps in non-root mode. Sending a
3897                  * notification event posts the interrupt to vcpu.
3898                  *
3899                  * Case 2: vcpu exits to root mode and is still
3900                  * runnable. PIR will be synced to vIRR before the
3901                  * next vcpu entry. Sending a notification event in
3902                  * this case has no effect, as vcpu is not in root
3903                  * mode.
3904                  *
3905                  * Case 3: vcpu exits to root mode and is blocked.
3906                  * vcpu_block() has already synced PIR to vIRR and
3907                  * never blocks vcpu if vIRR is not cleared. Therefore,
3908                  * a blocked vcpu here does not wait for any requested
3909                  * interrupts in PIR, and sending a notification event
3910                  * which has no effect is safe here.
3911                  */
3912
3913                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3914                 return true;
3915         }
3916 #endif
3917         return false;
3918 }
3919
3920 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3921                                                 int vector)
3922 {
3923         struct vcpu_vmx *vmx = to_vmx(vcpu);
3924
3925         if (is_guest_mode(vcpu) &&
3926             vector == vmx->nested.posted_intr_nv) {
3927                 /*
3928                  * If a posted intr is not recognized by hardware,
3929                  * we will accomplish it in the next vmentry.
3930                  */
3931                 vmx->nested.pi_pending = true;
3932                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3933                 /* the PIR and ON have been set by L1. */
3934                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3935                         kvm_vcpu_kick(vcpu);
3936                 return 0;
3937         }
3938         return -1;
3939 }
3940 /*
3941  * Send interrupt to vcpu via posted interrupt way.
3942  * 1. If target vcpu is running(non-root mode), send posted interrupt
3943  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3944  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3945  * interrupt from PIR in next vmentry.
3946  */
3947 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3948 {
3949         struct vcpu_vmx *vmx = to_vmx(vcpu);
3950         int r;
3951
3952         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3953         if (!r)
3954                 return 0;
3955
3956         if (!vcpu->arch.apicv_active)
3957                 return -1;
3958
3959         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3960                 return 0;
3961
3962         /* If a previous notification has sent the IPI, nothing to do.  */
3963         if (pi_test_and_set_on(&vmx->pi_desc))
3964                 return 0;
3965
3966         if (vcpu != kvm_get_running_vcpu() &&
3967             !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3968                 kvm_vcpu_kick(vcpu);
3969
3970         return 0;
3971 }
3972
3973 /*
3974  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3975  * will not change in the lifetime of the guest.
3976  * Note that host-state that does change is set elsewhere. E.g., host-state
3977  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3978  */
3979 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3980 {
3981         u32 low32, high32;
3982         unsigned long tmpl;
3983         unsigned long cr0, cr3, cr4;
3984
3985         cr0 = read_cr0();
3986         WARN_ON(cr0 & X86_CR0_TS);
3987         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3988
3989         /*
3990          * Save the most likely value for this task's CR3 in the VMCS.
3991          * We can't use __get_current_cr3_fast() because we're not atomic.
3992          */
3993         cr3 = __read_cr3();
3994         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
3995         vmx->loaded_vmcs->host_state.cr3 = cr3;
3996
3997         /* Save the most likely value for this task's CR4 in the VMCS. */
3998         cr4 = cr4_read_shadow();
3999         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4000         vmx->loaded_vmcs->host_state.cr4 = cr4;
4001
4002         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4003 #ifdef CONFIG_X86_64
4004         /*
4005          * Load null selectors, so we can avoid reloading them in
4006          * vmx_prepare_switch_to_host(), in case userspace uses
4007          * the null selectors too (the expected case).
4008          */
4009         vmcs_write16(HOST_DS_SELECTOR, 0);
4010         vmcs_write16(HOST_ES_SELECTOR, 0);
4011 #else
4012         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4013         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4014 #endif
4015         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4016         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4017
4018         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
4019
4020         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4021
4022         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4023         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4024         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4025         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4026
4027         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4028                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4029                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4030         }
4031
4032         if (cpu_has_load_ia32_efer())
4033                 vmcs_write64(HOST_IA32_EFER, host_efer);
4034 }
4035
4036 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4037 {
4038         struct kvm_vcpu *vcpu = &vmx->vcpu;
4039
4040         vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
4041                                           ~vcpu->arch.cr4_guest_rsvd_bits;
4042         if (!enable_ept)
4043                 vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4044         if (is_guest_mode(&vmx->vcpu))
4045                 vcpu->arch.cr4_guest_owned_bits &=
4046                         ~get_vmcs12(vcpu)->cr4_guest_host_mask;
4047         vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits);
4048 }
4049
4050 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4051 {
4052         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4053
4054         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4055                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4056
4057         if (!enable_vnmi)
4058                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4059
4060         if (!enable_preemption_timer)
4061                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4062
4063         return pin_based_exec_ctrl;
4064 }
4065
4066 static u32 vmx_vmentry_ctrl(void)
4067 {
4068         u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
4069
4070         if (vmx_pt_mode_is_system())
4071                 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
4072                                   VM_ENTRY_LOAD_IA32_RTIT_CTL);
4073         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4074         return vmentry_ctrl &
4075                 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
4076 }
4077
4078 static u32 vmx_vmexit_ctrl(void)
4079 {
4080         u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
4081
4082         if (vmx_pt_mode_is_system())
4083                 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
4084                                  VM_EXIT_CLEAR_IA32_RTIT_CTL);
4085         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4086         return vmexit_ctrl &
4087                 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
4088 }
4089
4090 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4091 {
4092         struct vcpu_vmx *vmx = to_vmx(vcpu);
4093
4094         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4095         if (cpu_has_secondary_exec_ctrls()) {
4096                 if (kvm_vcpu_apicv_active(vcpu))
4097                         secondary_exec_controls_setbit(vmx,
4098                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4099                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4100                 else
4101                         secondary_exec_controls_clearbit(vmx,
4102                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4103                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4104         }
4105
4106         vmx_update_msr_bitmap_x2apic(vcpu);
4107 }
4108
4109 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4110 {
4111         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4112
4113         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4114                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4115
4116         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4117                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4118 #ifdef CONFIG_X86_64
4119                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4120                                 CPU_BASED_CR8_LOAD_EXITING;
4121 #endif
4122         }
4123         if (!enable_ept)
4124                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4125                                 CPU_BASED_CR3_LOAD_EXITING  |
4126                                 CPU_BASED_INVLPG_EXITING;
4127         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4128                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4129                                 CPU_BASED_MONITOR_EXITING);
4130         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4131                 exec_control &= ~CPU_BASED_HLT_EXITING;
4132         return exec_control;
4133 }
4134
4135 /*
4136  * Adjust a single secondary execution control bit to intercept/allow an
4137  * instruction in the guest.  This is usually done based on whether or not a
4138  * feature has been exposed to the guest in order to correctly emulate faults.
4139  */
4140 static inline void
4141 vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control,
4142                                   u32 control, bool enabled, bool exiting)
4143 {
4144         /*
4145          * If the control is for an opt-in feature, clear the control if the
4146          * feature is not exposed to the guest, i.e. not enabled.  If the
4147          * control is opt-out, i.e. an exiting control, clear the control if
4148          * the feature _is_ exposed to the guest, i.e. exiting/interception is
4149          * disabled for the associated instruction.  Note, the caller is
4150          * responsible presetting exec_control to set all supported bits.
4151          */
4152         if (enabled == exiting)
4153                 *exec_control &= ~control;
4154
4155         /*
4156          * Update the nested MSR settings so that a nested VMM can/can't set
4157          * controls for features that are/aren't exposed to the guest.
4158          */
4159         if (nested) {
4160                 if (enabled)
4161                         vmx->nested.msrs.secondary_ctls_high |= control;
4162                 else
4163                         vmx->nested.msrs.secondary_ctls_high &= ~control;
4164         }
4165 }
4166
4167 /*
4168  * Wrapper macro for the common case of adjusting a secondary execution control
4169  * based on a single guest CPUID bit, with a dedicated feature bit.  This also
4170  * verifies that the control is actually supported by KVM and hardware.
4171  */
4172 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \
4173 ({                                                                       \
4174         bool __enabled;                                                  \
4175                                                                          \
4176         if (cpu_has_vmx_##name()) {                                      \
4177                 __enabled = guest_cpuid_has(&(vmx)->vcpu,                \
4178                                             X86_FEATURE_##feat_name);    \
4179                 vmx_adjust_secondary_exec_control(vmx, exec_control,     \
4180                         SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \
4181         }                                                                \
4182 })
4183
4184 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */
4185 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \
4186         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false)
4187
4188 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \
4189         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true)
4190
4191 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4192 {
4193         struct kvm_vcpu *vcpu = &vmx->vcpu;
4194
4195         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4196
4197         if (vmx_pt_mode_is_system())
4198                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4199         if (!cpu_need_virtualize_apic_accesses(vcpu))
4200                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4201         if (vmx->vpid == 0)
4202                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4203         if (!enable_ept) {
4204                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4205                 enable_unrestricted_guest = 0;
4206         }
4207         if (!enable_unrestricted_guest)
4208                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4209         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4210                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4211         if (!kvm_vcpu_apicv_active(vcpu))
4212                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4213                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4214         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4215
4216         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4217          * in vmx_set_cr4.  */
4218         exec_control &= ~SECONDARY_EXEC_DESC;
4219
4220         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4221            (handle_vmptrld).
4222            We can NOT enable shadow_vmcs here because we don't have yet
4223            a current VMCS12
4224         */
4225         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4226
4227         /*
4228          * PML is enabled/disabled when dirty logging of memsmlots changes, but
4229          * it needs to be set here when dirty logging is already active, e.g.
4230          * if this vCPU was created after dirty logging was enabled.
4231          */
4232         if (!vcpu->kvm->arch.cpu_dirty_logging_count)
4233                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4234
4235         if (cpu_has_vmx_xsaves()) {
4236                 /* Exposing XSAVES only when XSAVE is exposed */
4237                 bool xsaves_enabled =
4238                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4239                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4240                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4241
4242                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4243
4244                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4245                                                   SECONDARY_EXEC_XSAVES,
4246                                                   xsaves_enabled, false);
4247         }
4248
4249         /*
4250          * RDPID is also gated by ENABLE_RDTSCP, turn on the control if either
4251          * feature is exposed to the guest.  This creates a virtualization hole
4252          * if both are supported in hardware but only one is exposed to the
4253          * guest, but letting the guest execute RDTSCP or RDPID when either one
4254          * is advertised is preferable to emulating the advertised instruction
4255          * in KVM on #UD, and obviously better than incorrectly injecting #UD.
4256          */
4257         if (cpu_has_vmx_rdtscp()) {
4258                 bool rdpid_or_rdtscp_enabled =
4259                         guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) ||
4260                         guest_cpuid_has(vcpu, X86_FEATURE_RDPID);
4261
4262                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4263                                                   SECONDARY_EXEC_ENABLE_RDTSCP,
4264                                                   rdpid_or_rdtscp_enabled, false);
4265         }
4266         vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID);
4267
4268         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND);
4269         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED);
4270
4271         vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG,
4272                                     ENABLE_USR_WAIT_PAUSE, false);
4273
4274         if (!vcpu->kvm->arch.bus_lock_detection_enabled)
4275                 exec_control &= ~SECONDARY_EXEC_BUS_LOCK_DETECTION;
4276
4277         return exec_control;
4278 }
4279
4280 #define VMX_XSS_EXIT_BITMAP 0
4281
4282 static void init_vmcs(struct vcpu_vmx *vmx)
4283 {
4284         if (nested)
4285                 nested_vmx_set_vmcs_shadowing_bitmap();
4286
4287         if (cpu_has_vmx_msr_bitmap())
4288                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4289
4290         vmcs_write64(VMCS_LINK_POINTER, INVALID_GPA); /* 22.3.1.5 */
4291
4292         /* Control */
4293         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4294
4295         exec_controls_set(vmx, vmx_exec_control(vmx));
4296
4297         if (cpu_has_secondary_exec_ctrls())
4298                 secondary_exec_controls_set(vmx, vmx_secondary_exec_control(vmx));
4299
4300         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4301                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4302                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4303                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4304                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4305
4306                 vmcs_write16(GUEST_INTR_STATUS, 0);
4307
4308                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4309                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4310         }
4311
4312         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4313                 vmcs_write32(PLE_GAP, ple_gap);
4314                 vmx->ple_window = ple_window;
4315                 vmx->ple_window_dirty = true;
4316         }
4317
4318         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4319         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4320         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4321
4322         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4323         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4324         vmx_set_constant_host_state(vmx);
4325         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4326         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4327
4328         if (cpu_has_vmx_vmfunc())
4329                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4330
4331         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4332         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4333         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4334         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4335         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4336
4337         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4338                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4339
4340         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4341
4342         /* 22.2.1, 20.8.1 */
4343         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4344
4345         vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4346         vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4347
4348         set_cr4_guest_host_mask(vmx);
4349
4350         if (vmx->vpid != 0)
4351                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4352
4353         if (cpu_has_vmx_xsaves())
4354                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4355
4356         if (enable_pml) {
4357                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4358                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4359         }
4360
4361         vmx_write_encls_bitmap(&vmx->vcpu, NULL);
4362
4363         if (vmx_pt_mode_is_host_guest()) {
4364                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4365                 /* Bit[6~0] are forced to 1, writes are ignored. */
4366                 vmx->pt_desc.guest.output_mask = 0x7F;
4367                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4368         }
4369
4370         vmcs_write32(GUEST_SYSENTER_CS, 0);
4371         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4372         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4373         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4374
4375         if (cpu_has_vmx_tpr_shadow()) {
4376                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4377                 if (cpu_need_tpr_shadow(&vmx->vcpu))
4378                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4379                                      __pa(vmx->vcpu.arch.apic->regs));
4380                 vmcs_write32(TPR_THRESHOLD, 0);
4381         }
4382
4383         vmx_setup_uret_msrs(vmx);
4384 }
4385
4386 static void __vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4387 {
4388         struct vcpu_vmx *vmx = to_vmx(vcpu);
4389
4390         init_vmcs(vmx);
4391
4392         if (nested)
4393                 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
4394
4395         vcpu_setup_sgx_lepubkeyhash(vcpu);
4396
4397         vmx->nested.posted_intr_nv = -1;
4398         vmx->nested.vmxon_ptr = INVALID_GPA;
4399         vmx->nested.current_vmptr = INVALID_GPA;
4400         vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
4401
4402         vcpu->arch.microcode_version = 0x100000000ULL;
4403         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
4404
4405         /*
4406          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
4407          * or POSTED_INTR_WAKEUP_VECTOR.
4408          */
4409         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
4410         vmx->pi_desc.sn = 1;
4411 }
4412
4413 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4414 {
4415         struct vcpu_vmx *vmx = to_vmx(vcpu);
4416
4417         if (!init_event)
4418                 __vmx_vcpu_reset(vcpu);
4419
4420         vmx->rmode.vm86_active = 0;
4421         vmx->spec_ctrl = 0;
4422
4423         vmx->msr_ia32_umwait_control = 0;
4424
4425         vmx->hv_deadline_tsc = -1;
4426         kvm_set_cr8(vcpu, 0);
4427
4428         vmx_segment_cache_clear(vmx);
4429         kvm_register_mark_available(vcpu, VCPU_EXREG_SEGMENTS);
4430
4431         seg_setup(VCPU_SREG_CS);
4432         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4433         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4434
4435         seg_setup(VCPU_SREG_DS);
4436         seg_setup(VCPU_SREG_ES);
4437         seg_setup(VCPU_SREG_FS);
4438         seg_setup(VCPU_SREG_GS);
4439         seg_setup(VCPU_SREG_SS);
4440
4441         vmcs_write16(GUEST_TR_SELECTOR, 0);
4442         vmcs_writel(GUEST_TR_BASE, 0);
4443         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4444         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4445
4446         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4447         vmcs_writel(GUEST_LDTR_BASE, 0);
4448         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4449         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4450
4451         vmcs_writel(GUEST_GDTR_BASE, 0);
4452         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4453
4454         vmcs_writel(GUEST_IDTR_BASE, 0);
4455         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4456
4457         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4458         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4459         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4460         if (kvm_mpx_supported())
4461                 vmcs_write64(GUEST_BNDCFGS, 0);
4462
4463         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4464
4465         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4466
4467         vpid_sync_context(vmx->vpid);
4468 }
4469
4470 static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
4471 {
4472         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4473 }
4474
4475 static void vmx_enable_nmi_window(struct kvm_vcpu *vcpu)
4476 {
4477         if (!enable_vnmi ||
4478             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4479                 vmx_enable_irq_window(vcpu);
4480                 return;
4481         }
4482
4483         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4484 }
4485
4486 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4487 {
4488         struct vcpu_vmx *vmx = to_vmx(vcpu);
4489         uint32_t intr;
4490         int irq = vcpu->arch.interrupt.nr;
4491
4492         trace_kvm_inj_virq(irq);
4493
4494         ++vcpu->stat.irq_injections;
4495         if (vmx->rmode.vm86_active) {
4496                 int inc_eip = 0;
4497                 if (vcpu->arch.interrupt.soft)
4498                         inc_eip = vcpu->arch.event_exit_inst_len;
4499                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4500                 return;
4501         }
4502         intr = irq | INTR_INFO_VALID_MASK;
4503         if (vcpu->arch.interrupt.soft) {
4504                 intr |= INTR_TYPE_SOFT_INTR;
4505                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4506                              vmx->vcpu.arch.event_exit_inst_len);
4507         } else
4508                 intr |= INTR_TYPE_EXT_INTR;
4509         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4510
4511         vmx_clear_hlt(vcpu);
4512 }
4513
4514 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4515 {
4516         struct vcpu_vmx *vmx = to_vmx(vcpu);
4517
4518         if (!enable_vnmi) {
4519                 /*
4520                  * Tracking the NMI-blocked state in software is built upon
4521                  * finding the next open IRQ window. This, in turn, depends on
4522                  * well-behaving guests: They have to keep IRQs disabled at
4523                  * least as long as the NMI handler runs. Otherwise we may
4524                  * cause NMI nesting, maybe breaking the guest. But as this is
4525                  * highly unlikely, we can live with the residual risk.
4526                  */
4527                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4528                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4529         }
4530
4531         ++vcpu->stat.nmi_injections;
4532         vmx->loaded_vmcs->nmi_known_unmasked = false;
4533
4534         if (vmx->rmode.vm86_active) {
4535                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4536                 return;
4537         }
4538
4539         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4540                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4541
4542         vmx_clear_hlt(vcpu);
4543 }
4544
4545 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4546 {
4547         struct vcpu_vmx *vmx = to_vmx(vcpu);
4548         bool masked;
4549
4550         if (!enable_vnmi)
4551                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4552         if (vmx->loaded_vmcs->nmi_known_unmasked)
4553                 return false;
4554         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4555         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4556         return masked;
4557 }
4558
4559 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4560 {
4561         struct vcpu_vmx *vmx = to_vmx(vcpu);
4562
4563         if (!enable_vnmi) {
4564                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4565                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4566                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4567                 }
4568         } else {
4569                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4570                 if (masked)
4571                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4572                                       GUEST_INTR_STATE_NMI);
4573                 else
4574                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4575                                         GUEST_INTR_STATE_NMI);
4576         }
4577 }
4578
4579 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4580 {
4581         if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4582                 return false;
4583
4584         if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4585                 return true;
4586
4587         return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4588                 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4589                  GUEST_INTR_STATE_NMI));
4590 }
4591
4592 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4593 {
4594         if (to_vmx(vcpu)->nested.nested_run_pending)
4595                 return -EBUSY;
4596
4597         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
4598         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4599                 return -EBUSY;
4600
4601         return !vmx_nmi_blocked(vcpu);
4602 }
4603
4604 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4605 {
4606         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4607                 return false;
4608
4609         return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4610                (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4611                 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4612 }
4613
4614 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4615 {
4616         if (to_vmx(vcpu)->nested.nested_run_pending)
4617                 return -EBUSY;
4618
4619        /*
4620         * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4621         * e.g. if the IRQ arrived asynchronously after checking nested events.
4622         */
4623         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4624                 return -EBUSY;
4625
4626         return !vmx_interrupt_blocked(vcpu);
4627 }
4628
4629 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4630 {
4631         void __user *ret;
4632
4633         if (enable_unrestricted_guest)
4634                 return 0;
4635
4636         mutex_lock(&kvm->slots_lock);
4637         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4638                                       PAGE_SIZE * 3);
4639         mutex_unlock(&kvm->slots_lock);
4640
4641         if (IS_ERR(ret))
4642                 return PTR_ERR(ret);
4643
4644         to_kvm_vmx(kvm)->tss_addr = addr;
4645
4646         return init_rmode_tss(kvm, ret);
4647 }
4648
4649 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4650 {
4651         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4652         return 0;
4653 }
4654
4655 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4656 {
4657         switch (vec) {
4658         case BP_VECTOR:
4659                 /*
4660                  * Update instruction length as we may reinject the exception
4661                  * from user space while in guest debugging mode.
4662                  */
4663                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4664                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4665                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4666                         return false;
4667                 fallthrough;
4668         case DB_VECTOR:
4669                 return !(vcpu->guest_debug &
4670                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4671         case DE_VECTOR:
4672         case OF_VECTOR:
4673         case BR_VECTOR:
4674         case UD_VECTOR:
4675         case DF_VECTOR:
4676         case SS_VECTOR:
4677         case GP_VECTOR:
4678         case MF_VECTOR:
4679                 return true;
4680         }
4681         return false;
4682 }
4683
4684 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4685                                   int vec, u32 err_code)
4686 {
4687         /*
4688          * Instruction with address size override prefix opcode 0x67
4689          * Cause the #SS fault with 0 error code in VM86 mode.
4690          */
4691         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4692                 if (kvm_emulate_instruction(vcpu, 0)) {
4693                         if (vcpu->arch.halt_request) {
4694                                 vcpu->arch.halt_request = 0;
4695                                 return kvm_vcpu_halt(vcpu);
4696                         }
4697                         return 1;
4698                 }
4699                 return 0;
4700         }
4701
4702         /*
4703          * Forward all other exceptions that are valid in real mode.
4704          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4705          *        the required debugging infrastructure rework.
4706          */
4707         kvm_queue_exception(vcpu, vec);
4708         return 1;
4709 }
4710
4711 static int handle_machine_check(struct kvm_vcpu *vcpu)
4712 {
4713         /* handled by vmx_vcpu_run() */
4714         return 1;
4715 }
4716
4717 /*
4718  * If the host has split lock detection disabled, then #AC is
4719  * unconditionally injected into the guest, which is the pre split lock
4720  * detection behaviour.
4721  *
4722  * If the host has split lock detection enabled then #AC is
4723  * only injected into the guest when:
4724  *  - Guest CPL == 3 (user mode)
4725  *  - Guest has #AC detection enabled in CR0
4726  *  - Guest EFLAGS has AC bit set
4727  */
4728 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu)
4729 {
4730         if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4731                 return true;
4732
4733         return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4734                (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4735 }
4736
4737 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4738 {
4739         struct vcpu_vmx *vmx = to_vmx(vcpu);
4740         struct kvm_run *kvm_run = vcpu->run;
4741         u32 intr_info, ex_no, error_code;
4742         unsigned long cr2, dr6;
4743         u32 vect_info;
4744
4745         vect_info = vmx->idt_vectoring_info;
4746         intr_info = vmx_get_intr_info(vcpu);
4747
4748         if (is_machine_check(intr_info) || is_nmi(intr_info))
4749                 return 1; /* handled by handle_exception_nmi_irqoff() */
4750
4751         if (is_invalid_opcode(intr_info))
4752                 return handle_ud(vcpu);
4753
4754         error_code = 0;
4755         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4756                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4757
4758         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4759                 WARN_ON_ONCE(!enable_vmware_backdoor);
4760
4761                 /*
4762                  * VMware backdoor emulation on #GP interception only handles
4763                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4764                  * error code on #GP.
4765                  */
4766                 if (error_code) {
4767                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4768                         return 1;
4769                 }
4770                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4771         }
4772
4773         /*
4774          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4775          * MMIO, it is better to report an internal error.
4776          * See the comments in vmx_handle_exit.
4777          */
4778         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4779             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4780                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4781                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4782                 vcpu->run->internal.ndata = 4;
4783                 vcpu->run->internal.data[0] = vect_info;
4784                 vcpu->run->internal.data[1] = intr_info;
4785                 vcpu->run->internal.data[2] = error_code;
4786                 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4787                 return 0;
4788         }
4789
4790         if (is_page_fault(intr_info)) {
4791                 cr2 = vmx_get_exit_qual(vcpu);
4792                 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4793                         /*
4794                          * EPT will cause page fault only if we need to
4795                          * detect illegal GPAs.
4796                          */
4797                         WARN_ON_ONCE(!allow_smaller_maxphyaddr);
4798                         kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4799                         return 1;
4800                 } else
4801                         return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4802         }
4803
4804         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4805
4806         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4807                 return handle_rmode_exception(vcpu, ex_no, error_code);
4808
4809         switch (ex_no) {
4810         case DB_VECTOR:
4811                 dr6 = vmx_get_exit_qual(vcpu);
4812                 if (!(vcpu->guest_debug &
4813                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4814                         if (is_icebp(intr_info))
4815                                 WARN_ON(!skip_emulated_instruction(vcpu));
4816
4817                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4818                         return 1;
4819                 }
4820                 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
4821                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4822                 fallthrough;
4823         case BP_VECTOR:
4824                 /*
4825                  * Update instruction length as we may reinject #BP from
4826                  * user space while in guest debugging mode. Reading it for
4827                  * #DB as well causes no harm, it is not used in that case.
4828                  */
4829                 vmx->vcpu.arch.event_exit_inst_len =
4830                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4831                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4832                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4833                 kvm_run->debug.arch.exception = ex_no;
4834                 break;
4835         case AC_VECTOR:
4836                 if (vmx_guest_inject_ac(vcpu)) {
4837                         kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4838                         return 1;
4839                 }
4840
4841                 /*
4842                  * Handle split lock. Depending on detection mode this will
4843                  * either warn and disable split lock detection for this
4844                  * task or force SIGBUS on it.
4845                  */
4846                 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4847                         return 1;
4848                 fallthrough;
4849         default:
4850                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4851                 kvm_run->ex.exception = ex_no;
4852                 kvm_run->ex.error_code = error_code;
4853                 break;
4854         }
4855         return 0;
4856 }
4857
4858 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4859 {
4860         ++vcpu->stat.irq_exits;
4861         return 1;
4862 }
4863
4864 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4865 {
4866         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4867         vcpu->mmio_needed = 0;
4868         return 0;
4869 }
4870
4871 static int handle_io(struct kvm_vcpu *vcpu)
4872 {
4873         unsigned long exit_qualification;
4874         int size, in, string;
4875         unsigned port;
4876
4877         exit_qualification = vmx_get_exit_qual(vcpu);
4878         string = (exit_qualification & 16) != 0;
4879
4880         ++vcpu->stat.io_exits;
4881
4882         if (string)
4883                 return kvm_emulate_instruction(vcpu, 0);
4884
4885         port = exit_qualification >> 16;
4886         size = (exit_qualification & 7) + 1;
4887         in = (exit_qualification & 8) != 0;
4888
4889         return kvm_fast_pio(vcpu, size, port, in);
4890 }
4891
4892 static void
4893 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4894 {
4895         /*
4896          * Patch in the VMCALL instruction:
4897          */
4898         hypercall[0] = 0x0f;
4899         hypercall[1] = 0x01;
4900         hypercall[2] = 0xc1;
4901 }
4902
4903 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4904 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4905 {
4906         if (is_guest_mode(vcpu)) {
4907                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4908                 unsigned long orig_val = val;
4909
4910                 /*
4911                  * We get here when L2 changed cr0 in a way that did not change
4912                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4913                  * but did change L0 shadowed bits. So we first calculate the
4914                  * effective cr0 value that L1 would like to write into the
4915                  * hardware. It consists of the L2-owned bits from the new
4916                  * value combined with the L1-owned bits from L1's guest_cr0.
4917                  */
4918                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4919                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4920
4921                 if (!nested_guest_cr0_valid(vcpu, val))
4922                         return 1;
4923
4924                 if (kvm_set_cr0(vcpu, val))
4925                         return 1;
4926                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4927                 return 0;
4928         } else {
4929                 if (to_vmx(vcpu)->nested.vmxon &&
4930                     !nested_host_cr0_valid(vcpu, val))
4931                         return 1;
4932
4933                 return kvm_set_cr0(vcpu, val);
4934         }
4935 }
4936
4937 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4938 {
4939         if (is_guest_mode(vcpu)) {
4940                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4941                 unsigned long orig_val = val;
4942
4943                 /* analogously to handle_set_cr0 */
4944                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4945                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4946                 if (kvm_set_cr4(vcpu, val))
4947                         return 1;
4948                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4949                 return 0;
4950         } else
4951                 return kvm_set_cr4(vcpu, val);
4952 }
4953
4954 static int handle_desc(struct kvm_vcpu *vcpu)
4955 {
4956         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4957         return kvm_emulate_instruction(vcpu, 0);
4958 }
4959
4960 static int handle_cr(struct kvm_vcpu *vcpu)
4961 {
4962         unsigned long exit_qualification, val;
4963         int cr;
4964         int reg;
4965         int err;
4966         int ret;
4967
4968         exit_qualification = vmx_get_exit_qual(vcpu);
4969         cr = exit_qualification & 15;
4970         reg = (exit_qualification >> 8) & 15;
4971         switch ((exit_qualification >> 4) & 3) {
4972         case 0: /* mov to cr */
4973                 val = kvm_register_read(vcpu, reg);
4974                 trace_kvm_cr_write(cr, val);
4975                 switch (cr) {
4976                 case 0:
4977                         err = handle_set_cr0(vcpu, val);
4978                         return kvm_complete_insn_gp(vcpu, err);
4979                 case 3:
4980                         WARN_ON_ONCE(enable_unrestricted_guest);
4981
4982                         err = kvm_set_cr3(vcpu, val);
4983                         return kvm_complete_insn_gp(vcpu, err);
4984                 case 4:
4985                         err = handle_set_cr4(vcpu, val);
4986                         return kvm_complete_insn_gp(vcpu, err);
4987                 case 8: {
4988                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4989                                 u8 cr8 = (u8)val;
4990                                 err = kvm_set_cr8(vcpu, cr8);
4991                                 ret = kvm_complete_insn_gp(vcpu, err);
4992                                 if (lapic_in_kernel(vcpu))
4993                                         return ret;
4994                                 if (cr8_prev <= cr8)
4995                                         return ret;
4996                                 /*
4997                                  * TODO: we might be squashing a
4998                                  * KVM_GUESTDBG_SINGLESTEP-triggered
4999                                  * KVM_EXIT_DEBUG here.
5000                                  */
5001                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5002                                 return 0;
5003                         }
5004                 }
5005                 break;
5006         case 2: /* clts */
5007                 KVM_BUG(1, vcpu->kvm, "Guest always owns CR0.TS");
5008                 return -EIO;
5009         case 1: /*mov from cr*/
5010                 switch (cr) {
5011                 case 3:
5012                         WARN_ON_ONCE(enable_unrestricted_guest);
5013
5014                         val = kvm_read_cr3(vcpu);
5015                         kvm_register_write(vcpu, reg, val);
5016                         trace_kvm_cr_read(cr, val);
5017                         return kvm_skip_emulated_instruction(vcpu);
5018                 case 8:
5019                         val = kvm_get_cr8(vcpu);
5020                         kvm_register_write(vcpu, reg, val);
5021                         trace_kvm_cr_read(cr, val);
5022                         return kvm_skip_emulated_instruction(vcpu);
5023                 }
5024                 break;
5025         case 3: /* lmsw */
5026                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5027                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5028                 kvm_lmsw(vcpu, val);
5029
5030                 return kvm_skip_emulated_instruction(vcpu);
5031         default:
5032                 break;
5033         }
5034         vcpu->run->exit_reason = 0;
5035         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5036                (int)(exit_qualification >> 4) & 3, cr);
5037         return 0;
5038 }
5039
5040 static int handle_dr(struct kvm_vcpu *vcpu)
5041 {
5042         unsigned long exit_qualification;
5043         int dr, dr7, reg;
5044         int err = 1;
5045
5046         exit_qualification = vmx_get_exit_qual(vcpu);
5047         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5048
5049         /* First, if DR does not exist, trigger UD */
5050         if (!kvm_require_dr(vcpu, dr))
5051                 return 1;
5052
5053         if (kvm_x86_ops.get_cpl(vcpu) > 0)
5054                 goto out;
5055
5056         dr7 = vmcs_readl(GUEST_DR7);
5057         if (dr7 & DR7_GD) {
5058                 /*
5059                  * As the vm-exit takes precedence over the debug trap, we
5060                  * need to emulate the latter, either for the host or the
5061                  * guest debugging itself.
5062                  */
5063                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5064                         vcpu->run->debug.arch.dr6 = DR6_BD | DR6_ACTIVE_LOW;
5065                         vcpu->run->debug.arch.dr7 = dr7;
5066                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5067                         vcpu->run->debug.arch.exception = DB_VECTOR;
5068                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5069                         return 0;
5070                 } else {
5071                         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5072                         return 1;
5073                 }
5074         }
5075
5076         if (vcpu->guest_debug == 0) {
5077                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5078
5079                 /*
5080                  * No more DR vmexits; force a reload of the debug registers
5081                  * and reenter on this instruction.  The next vmexit will
5082                  * retrieve the full state of the debug registers.
5083                  */
5084                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5085                 return 1;
5086         }
5087
5088         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5089         if (exit_qualification & TYPE_MOV_FROM_DR) {
5090                 unsigned long val;
5091
5092                 kvm_get_dr(vcpu, dr, &val);
5093                 kvm_register_write(vcpu, reg, val);
5094                 err = 0;
5095         } else {
5096                 err = kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg));
5097         }
5098
5099 out:
5100         return kvm_complete_insn_gp(vcpu, err);
5101 }
5102
5103 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5104 {
5105         get_debugreg(vcpu->arch.db[0], 0);
5106         get_debugreg(vcpu->arch.db[1], 1);
5107         get_debugreg(vcpu->arch.db[2], 2);
5108         get_debugreg(vcpu->arch.db[3], 3);
5109         get_debugreg(vcpu->arch.dr6, 6);
5110         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5111
5112         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5113         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5114
5115         /*
5116          * exc_debug expects dr6 to be cleared after it runs, avoid that it sees
5117          * a stale dr6 from the guest.
5118          */
5119         set_debugreg(DR6_RESERVED, 6);
5120 }
5121
5122 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5123 {
5124         vmcs_writel(GUEST_DR7, val);
5125 }
5126
5127 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5128 {
5129         kvm_apic_update_ppr(vcpu);
5130         return 1;
5131 }
5132
5133 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5134 {
5135         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5136
5137         kvm_make_request(KVM_REQ_EVENT, vcpu);
5138
5139         ++vcpu->stat.irq_window_exits;
5140         return 1;
5141 }
5142
5143 static int handle_invlpg(struct kvm_vcpu *vcpu)
5144 {
5145         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5146
5147         kvm_mmu_invlpg(vcpu, exit_qualification);
5148         return kvm_skip_emulated_instruction(vcpu);
5149 }
5150
5151 static int handle_apic_access(struct kvm_vcpu *vcpu)
5152 {
5153         if (likely(fasteoi)) {
5154                 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5155                 int access_type, offset;
5156
5157                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5158                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5159                 /*
5160                  * Sane guest uses MOV to write EOI, with written value
5161                  * not cared. So make a short-circuit here by avoiding
5162                  * heavy instruction emulation.
5163                  */
5164                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5165                     (offset == APIC_EOI)) {
5166                         kvm_lapic_set_eoi(vcpu);
5167                         return kvm_skip_emulated_instruction(vcpu);
5168                 }
5169         }
5170         return kvm_emulate_instruction(vcpu, 0);
5171 }
5172
5173 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5174 {
5175         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5176         int vector = exit_qualification & 0xff;
5177
5178         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5179         kvm_apic_set_eoi_accelerated(vcpu, vector);
5180         return 1;
5181 }
5182
5183 static int handle_apic_write(struct kvm_vcpu *vcpu)
5184 {
5185         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5186         u32 offset = exit_qualification & 0xfff;
5187
5188         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5189         kvm_apic_write_nodecode(vcpu, offset);
5190         return 1;
5191 }
5192
5193 static int handle_task_switch(struct kvm_vcpu *vcpu)
5194 {
5195         struct vcpu_vmx *vmx = to_vmx(vcpu);
5196         unsigned long exit_qualification;
5197         bool has_error_code = false;
5198         u32 error_code = 0;
5199         u16 tss_selector;
5200         int reason, type, idt_v, idt_index;
5201
5202         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5203         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5204         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5205
5206         exit_qualification = vmx_get_exit_qual(vcpu);
5207
5208         reason = (u32)exit_qualification >> 30;
5209         if (reason == TASK_SWITCH_GATE && idt_v) {
5210                 switch (type) {
5211                 case INTR_TYPE_NMI_INTR:
5212                         vcpu->arch.nmi_injected = false;
5213                         vmx_set_nmi_mask(vcpu, true);
5214                         break;
5215                 case INTR_TYPE_EXT_INTR:
5216                 case INTR_TYPE_SOFT_INTR:
5217                         kvm_clear_interrupt_queue(vcpu);
5218                         break;
5219                 case INTR_TYPE_HARD_EXCEPTION:
5220                         if (vmx->idt_vectoring_info &
5221                             VECTORING_INFO_DELIVER_CODE_MASK) {
5222                                 has_error_code = true;
5223                                 error_code =
5224                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5225                         }
5226                         fallthrough;
5227                 case INTR_TYPE_SOFT_EXCEPTION:
5228                         kvm_clear_exception_queue(vcpu);
5229                         break;
5230                 default:
5231                         break;
5232                 }
5233         }
5234         tss_selector = exit_qualification;
5235
5236         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5237                        type != INTR_TYPE_EXT_INTR &&
5238                        type != INTR_TYPE_NMI_INTR))
5239                 WARN_ON(!skip_emulated_instruction(vcpu));
5240
5241         /*
5242          * TODO: What about debug traps on tss switch?
5243          *       Are we supposed to inject them and update dr6?
5244          */
5245         return kvm_task_switch(vcpu, tss_selector,
5246                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5247                                reason, has_error_code, error_code);
5248 }
5249
5250 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5251 {
5252         unsigned long exit_qualification;
5253         gpa_t gpa;
5254         u64 error_code;
5255
5256         exit_qualification = vmx_get_exit_qual(vcpu);
5257
5258         /*
5259          * EPT violation happened while executing iret from NMI,
5260          * "blocked by NMI" bit has to be set before next VM entry.
5261          * There are errata that may cause this bit to not be set:
5262          * AAK134, BY25.
5263          */
5264         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5265                         enable_vnmi &&
5266                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5267                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5268
5269         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5270         trace_kvm_page_fault(gpa, exit_qualification);
5271
5272         /* Is it a read fault? */
5273         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5274                      ? PFERR_USER_MASK : 0;
5275         /* Is it a write fault? */
5276         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5277                       ? PFERR_WRITE_MASK : 0;
5278         /* Is it a fetch fault? */
5279         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5280                       ? PFERR_FETCH_MASK : 0;
5281         /* ept page table entry is present? */
5282         error_code |= (exit_qualification &
5283                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5284                         EPT_VIOLATION_EXECUTABLE))
5285                       ? PFERR_PRESENT_MASK : 0;
5286
5287         error_code |= (exit_qualification & EPT_VIOLATION_GVA_TRANSLATED) != 0 ?
5288                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5289
5290         vcpu->arch.exit_qualification = exit_qualification;
5291
5292         /*
5293          * Check that the GPA doesn't exceed physical memory limits, as that is
5294          * a guest page fault.  We have to emulate the instruction here, because
5295          * if the illegal address is that of a paging structure, then
5296          * EPT_VIOLATION_ACC_WRITE bit is set.  Alternatively, if supported we
5297          * would also use advanced VM-exit information for EPT violations to
5298          * reconstruct the page fault error code.
5299          */
5300         if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa)))
5301                 return kvm_emulate_instruction(vcpu, 0);
5302
5303         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5304 }
5305
5306 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5307 {
5308         gpa_t gpa;
5309
5310         if (!vmx_can_emulate_instruction(vcpu, NULL, 0))
5311                 return 1;
5312
5313         /*
5314          * A nested guest cannot optimize MMIO vmexits, because we have an
5315          * nGPA here instead of the required GPA.
5316          */
5317         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5318         if (!is_guest_mode(vcpu) &&
5319             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5320                 trace_kvm_fast_mmio(gpa);
5321                 return kvm_skip_emulated_instruction(vcpu);
5322         }
5323
5324         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5325 }
5326
5327 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5328 {
5329         if (KVM_BUG_ON(!enable_vnmi, vcpu->kvm))
5330                 return -EIO;
5331
5332         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5333         ++vcpu->stat.nmi_window_exits;
5334         kvm_make_request(KVM_REQ_EVENT, vcpu);
5335
5336         return 1;
5337 }
5338
5339 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5340 {
5341         struct vcpu_vmx *vmx = to_vmx(vcpu);
5342         bool intr_window_requested;
5343         unsigned count = 130;
5344
5345         intr_window_requested = exec_controls_get(vmx) &
5346                                 CPU_BASED_INTR_WINDOW_EXITING;
5347
5348         while (vmx->emulation_required && count-- != 0) {
5349                 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5350                         return handle_interrupt_window(&vmx->vcpu);
5351
5352                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5353                         return 1;
5354
5355                 if (!kvm_emulate_instruction(vcpu, 0))
5356                         return 0;
5357
5358                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5359                     vcpu->arch.exception.pending) {
5360                         kvm_prepare_emulation_failure_exit(vcpu);
5361                         return 0;
5362                 }
5363
5364                 if (vcpu->arch.halt_request) {
5365                         vcpu->arch.halt_request = 0;
5366                         return kvm_vcpu_halt(vcpu);
5367                 }
5368
5369                 /*
5370                  * Note, return 1 and not 0, vcpu_run() will invoke
5371                  * xfer_to_guest_mode() which will create a proper return
5372                  * code.
5373                  */
5374                 if (__xfer_to_guest_mode_work_pending())
5375                         return 1;
5376         }
5377
5378         return 1;
5379 }
5380
5381 static void grow_ple_window(struct kvm_vcpu *vcpu)
5382 {
5383         struct vcpu_vmx *vmx = to_vmx(vcpu);
5384         unsigned int old = vmx->ple_window;
5385
5386         vmx->ple_window = __grow_ple_window(old, ple_window,
5387                                             ple_window_grow,
5388                                             ple_window_max);
5389
5390         if (vmx->ple_window != old) {
5391                 vmx->ple_window_dirty = true;
5392                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5393                                             vmx->ple_window, old);
5394         }
5395 }
5396
5397 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5398 {
5399         struct vcpu_vmx *vmx = to_vmx(vcpu);
5400         unsigned int old = vmx->ple_window;
5401
5402         vmx->ple_window = __shrink_ple_window(old, ple_window,
5403                                               ple_window_shrink,
5404                                               ple_window);
5405
5406         if (vmx->ple_window != old) {
5407                 vmx->ple_window_dirty = true;
5408                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5409                                             vmx->ple_window, old);
5410         }
5411 }
5412
5413 /*
5414  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5415  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5416  */
5417 static int handle_pause(struct kvm_vcpu *vcpu)
5418 {
5419         if (!kvm_pause_in_guest(vcpu->kvm))
5420                 grow_ple_window(vcpu);
5421
5422         /*
5423          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5424          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5425          * never set PAUSE_EXITING and just set PLE if supported,
5426          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5427          */
5428         kvm_vcpu_on_spin(vcpu, true);
5429         return kvm_skip_emulated_instruction(vcpu);
5430 }
5431
5432 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5433 {
5434         return 1;
5435 }
5436
5437 static int handle_invpcid(struct kvm_vcpu *vcpu)
5438 {
5439         u32 vmx_instruction_info;
5440         unsigned long type;
5441         gva_t gva;
5442         struct {
5443                 u64 pcid;
5444                 u64 gla;
5445         } operand;
5446         int gpr_index;
5447
5448         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5449                 kvm_queue_exception(vcpu, UD_VECTOR);
5450                 return 1;
5451         }
5452
5453         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5454         gpr_index = vmx_get_instr_info_reg2(vmx_instruction_info);
5455         type = kvm_register_read(vcpu, gpr_index);
5456
5457         /* According to the Intel instruction reference, the memory operand
5458          * is read even if it isn't needed (e.g., for type==all)
5459          */
5460         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5461                                 vmx_instruction_info, false,
5462                                 sizeof(operand), &gva))
5463                 return 1;
5464
5465         return kvm_handle_invpcid(vcpu, type, gva);
5466 }
5467
5468 static int handle_pml_full(struct kvm_vcpu *vcpu)
5469 {
5470         unsigned long exit_qualification;
5471
5472         trace_kvm_pml_full(vcpu->vcpu_id);
5473
5474         exit_qualification = vmx_get_exit_qual(vcpu);
5475
5476         /*
5477          * PML buffer FULL happened while executing iret from NMI,
5478          * "blocked by NMI" bit has to be set before next VM entry.
5479          */
5480         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5481                         enable_vnmi &&
5482                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5483                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5484                                 GUEST_INTR_STATE_NMI);
5485
5486         /*
5487          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5488          * here.., and there's no userspace involvement needed for PML.
5489          */
5490         return 1;
5491 }
5492
5493 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5494 {
5495         struct vcpu_vmx *vmx = to_vmx(vcpu);
5496
5497         if (!vmx->req_immediate_exit &&
5498             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5499                 kvm_lapic_expired_hv_timer(vcpu);
5500                 return EXIT_FASTPATH_REENTER_GUEST;
5501         }
5502
5503         return EXIT_FASTPATH_NONE;
5504 }
5505
5506 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5507 {
5508         handle_fastpath_preemption_timer(vcpu);
5509         return 1;
5510 }
5511
5512 /*
5513  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5514  * are overwritten by nested_vmx_setup() when nested=1.
5515  */
5516 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5517 {
5518         kvm_queue_exception(vcpu, UD_VECTOR);
5519         return 1;
5520 }
5521
5522 #ifndef CONFIG_X86_SGX_KVM
5523 static int handle_encls(struct kvm_vcpu *vcpu)
5524 {
5525         /*
5526          * SGX virtualization is disabled.  There is no software enable bit for
5527          * SGX, so KVM intercepts all ENCLS leafs and injects a #UD to prevent
5528          * the guest from executing ENCLS (when SGX is supported by hardware).
5529          */
5530         kvm_queue_exception(vcpu, UD_VECTOR);
5531         return 1;
5532 }
5533 #endif /* CONFIG_X86_SGX_KVM */
5534
5535 static int handle_bus_lock_vmexit(struct kvm_vcpu *vcpu)
5536 {
5537         /*
5538          * Hardware may or may not set the BUS_LOCK_DETECTED flag on BUS_LOCK
5539          * VM-Exits. Unconditionally set the flag here and leave the handling to
5540          * vmx_handle_exit().
5541          */
5542         to_vmx(vcpu)->exit_reason.bus_lock_detected = true;
5543         return 1;
5544 }
5545
5546 /*
5547  * The exit handlers return 1 if the exit was handled fully and guest execution
5548  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5549  * to be done to userspace and return 0.
5550  */
5551 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5552         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5553         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5554         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5555         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5556         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5557         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5558         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5559         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5560         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5561         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5562         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5563         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5564         [EXIT_REASON_INVD]                    = kvm_emulate_invd,
5565         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5566         [EXIT_REASON_RDPMC]                   = kvm_emulate_rdpmc,
5567         [EXIT_REASON_VMCALL]                  = kvm_emulate_hypercall,
5568         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5569         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5570         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5571         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5572         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5573         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5574         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5575         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5576         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5577         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5578         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5579         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5580         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5581         [EXIT_REASON_WBINVD]                  = kvm_emulate_wbinvd,
5582         [EXIT_REASON_XSETBV]                  = kvm_emulate_xsetbv,
5583         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5584         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5585         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5586         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5587         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5588         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5589         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5590         [EXIT_REASON_MWAIT_INSTRUCTION]       = kvm_emulate_mwait,
5591         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5592         [EXIT_REASON_MONITOR_INSTRUCTION]     = kvm_emulate_monitor,
5593         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5594         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5595         [EXIT_REASON_RDRAND]                  = kvm_handle_invalid_op,
5596         [EXIT_REASON_RDSEED]                  = kvm_handle_invalid_op,
5597         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5598         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5599         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5600         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5601         [EXIT_REASON_ENCLS]                   = handle_encls,
5602         [EXIT_REASON_BUS_LOCK]                = handle_bus_lock_vmexit,
5603 };
5604
5605 static const int kvm_vmx_max_exit_handlers =
5606         ARRAY_SIZE(kvm_vmx_exit_handlers);
5607
5608 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
5609                               u64 *info1, u64 *info2,
5610                               u32 *intr_info, u32 *error_code)
5611 {
5612         struct vcpu_vmx *vmx = to_vmx(vcpu);
5613
5614         *reason = vmx->exit_reason.full;
5615         *info1 = vmx_get_exit_qual(vcpu);
5616         if (!(vmx->exit_reason.failed_vmentry)) {
5617                 *info2 = vmx->idt_vectoring_info;
5618                 *intr_info = vmx_get_intr_info(vcpu);
5619                 if (is_exception_with_error_code(*intr_info))
5620                         *error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5621                 else
5622                         *error_code = 0;
5623         } else {
5624                 *info2 = 0;
5625                 *intr_info = 0;
5626                 *error_code = 0;
5627         }
5628 }
5629
5630 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5631 {
5632         if (vmx->pml_pg) {
5633                 __free_page(vmx->pml_pg);
5634                 vmx->pml_pg = NULL;
5635         }
5636 }
5637
5638 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5639 {
5640         struct vcpu_vmx *vmx = to_vmx(vcpu);
5641         u64 *pml_buf;
5642         u16 pml_idx;
5643
5644         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5645
5646         /* Do nothing if PML buffer is empty */
5647         if (pml_idx == (PML_ENTITY_NUM - 1))
5648                 return;
5649
5650         /* PML index always points to next available PML buffer entity */
5651         if (pml_idx >= PML_ENTITY_NUM)
5652                 pml_idx = 0;
5653         else
5654                 pml_idx++;
5655
5656         pml_buf = page_address(vmx->pml_pg);
5657         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5658                 u64 gpa;
5659
5660                 gpa = pml_buf[pml_idx];
5661                 WARN_ON(gpa & (PAGE_SIZE - 1));
5662                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5663         }
5664
5665         /* reset PML index */
5666         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5667 }
5668
5669 static void vmx_dump_sel(char *name, uint32_t sel)
5670 {
5671         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5672                name, vmcs_read16(sel),
5673                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5674                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5675                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5676 }
5677
5678 static void vmx_dump_dtsel(char *name, uint32_t limit)
5679 {
5680         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5681                name, vmcs_read32(limit),
5682                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5683 }
5684
5685 static void vmx_dump_msrs(char *name, struct vmx_msrs *m)
5686 {
5687         unsigned int i;
5688         struct vmx_msr_entry *e;
5689
5690         pr_err("MSR %s:\n", name);
5691         for (i = 0, e = m->val; i < m->nr; ++i, ++e)
5692                 pr_err("  %2d: msr=0x%08x value=0x%016llx\n", i, e->index, e->value);
5693 }
5694
5695 void dump_vmcs(struct kvm_vcpu *vcpu)
5696 {
5697         struct vcpu_vmx *vmx = to_vmx(vcpu);
5698         u32 vmentry_ctl, vmexit_ctl;
5699         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5700         unsigned long cr4;
5701         int efer_slot;
5702
5703         if (!dump_invalid_vmcs) {
5704                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5705                 return;
5706         }
5707
5708         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5709         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5710         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5711         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5712         cr4 = vmcs_readl(GUEST_CR4);
5713         secondary_exec_control = 0;
5714         if (cpu_has_secondary_exec_ctrls())
5715                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5716
5717         pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
5718                vmx->loaded_vmcs->vmcs, vcpu->arch.last_vmentry_cpu);
5719         pr_err("*** Guest State ***\n");
5720         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5721                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5722                vmcs_readl(CR0_GUEST_HOST_MASK));
5723         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5724                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5725         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5726         if (cpu_has_vmx_ept()) {
5727                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5728                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5729                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5730                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5731         }
5732         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5733                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5734         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5735                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5736         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5737                vmcs_readl(GUEST_SYSENTER_ESP),
5738                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5739         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5740         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5741         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5742         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5743         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5744         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5745         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5746         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5747         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5748         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5749         efer_slot = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, MSR_EFER);
5750         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_EFER)
5751                 pr_err("EFER= 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER));
5752         else if (efer_slot >= 0)
5753                 pr_err("EFER= 0x%016llx (autoload)\n",
5754                        vmx->msr_autoload.guest.val[efer_slot].value);
5755         else if (vmentry_ctl & VM_ENTRY_IA32E_MODE)
5756                 pr_err("EFER= 0x%016llx (effective)\n",
5757                        vcpu->arch.efer | (EFER_LMA | EFER_LME));
5758         else
5759                 pr_err("EFER= 0x%016llx (effective)\n",
5760                        vcpu->arch.efer & ~(EFER_LMA | EFER_LME));
5761         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PAT)
5762                 pr_err("PAT = 0x%016llx\n", vmcs_read64(GUEST_IA32_PAT));
5763         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5764                vmcs_read64(GUEST_IA32_DEBUGCTL),
5765                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5766         if (cpu_has_load_perf_global_ctrl() &&
5767             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5768                 pr_err("PerfGlobCtl = 0x%016llx\n",
5769                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5770         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5771                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5772         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5773                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5774                vmcs_read32(GUEST_ACTIVITY_STATE));
5775         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5776                 pr_err("InterruptStatus = %04x\n",
5777                        vmcs_read16(GUEST_INTR_STATUS));
5778         if (vmcs_read32(VM_ENTRY_MSR_LOAD_COUNT) > 0)
5779                 vmx_dump_msrs("guest autoload", &vmx->msr_autoload.guest);
5780         if (vmcs_read32(VM_EXIT_MSR_STORE_COUNT) > 0)
5781                 vmx_dump_msrs("guest autostore", &vmx->msr_autostore.guest);
5782
5783         pr_err("*** Host State ***\n");
5784         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5785                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5786         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5787                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5788                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5789                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5790                vmcs_read16(HOST_TR_SELECTOR));
5791         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5792                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5793                vmcs_readl(HOST_TR_BASE));
5794         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5795                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5796         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5797                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5798                vmcs_readl(HOST_CR4));
5799         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5800                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5801                vmcs_read32(HOST_IA32_SYSENTER_CS),
5802                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5803         if (vmexit_ctl & VM_EXIT_LOAD_IA32_EFER)
5804                 pr_err("EFER= 0x%016llx\n", vmcs_read64(HOST_IA32_EFER));
5805         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PAT)
5806                 pr_err("PAT = 0x%016llx\n", vmcs_read64(HOST_IA32_PAT));
5807         if (cpu_has_load_perf_global_ctrl() &&
5808             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5809                 pr_err("PerfGlobCtl = 0x%016llx\n",
5810                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5811         if (vmcs_read32(VM_EXIT_MSR_LOAD_COUNT) > 0)
5812                 vmx_dump_msrs("host autoload", &vmx->msr_autoload.host);
5813
5814         pr_err("*** Control State ***\n");
5815         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5816                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5817         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5818         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5819                vmcs_read32(EXCEPTION_BITMAP),
5820                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5821                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5822         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5823                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5824                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5825                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5826         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5827                vmcs_read32(VM_EXIT_INTR_INFO),
5828                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5829                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5830         pr_err("        reason=%08x qualification=%016lx\n",
5831                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5832         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5833                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5834                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5835         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5836         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5837                 pr_err("TSC Multiplier = 0x%016llx\n",
5838                        vmcs_read64(TSC_MULTIPLIER));
5839         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5840                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5841                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5842                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5843                 }
5844                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5845                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5846                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5847                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5848         }
5849         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5850                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5851         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5852                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5853         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5854                 pr_err("PLE Gap=%08x Window=%08x\n",
5855                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5856         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5857                 pr_err("Virtual processor ID = 0x%04x\n",
5858                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5859 }
5860
5861 /*
5862  * The guest has exited.  See if we can fix it or if we need userspace
5863  * assistance.
5864  */
5865 static int __vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5866 {
5867         struct vcpu_vmx *vmx = to_vmx(vcpu);
5868         union vmx_exit_reason exit_reason = vmx->exit_reason;
5869         u32 vectoring_info = vmx->idt_vectoring_info;
5870         u16 exit_handler_index;
5871
5872         /*
5873          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5874          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5875          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5876          * mode as if vcpus is in root mode, the PML buffer must has been
5877          * flushed already.  Note, PML is never enabled in hardware while
5878          * running L2.
5879          */
5880         if (enable_pml && !is_guest_mode(vcpu))
5881                 vmx_flush_pml_buffer(vcpu);
5882
5883         /*
5884          * We should never reach this point with a pending nested VM-Enter, and
5885          * more specifically emulation of L2 due to invalid guest state (see
5886          * below) should never happen as that means we incorrectly allowed a
5887          * nested VM-Enter with an invalid vmcs12.
5888          */
5889         if (KVM_BUG_ON(vmx->nested.nested_run_pending, vcpu->kvm))
5890                 return -EIO;
5891
5892         /* If guest state is invalid, start emulating */
5893         if (vmx->emulation_required)
5894                 return handle_invalid_guest_state(vcpu);
5895
5896         if (is_guest_mode(vcpu)) {
5897                 /*
5898                  * PML is never enabled when running L2, bail immediately if a
5899                  * PML full exit occurs as something is horribly wrong.
5900                  */
5901                 if (exit_reason.basic == EXIT_REASON_PML_FULL)
5902                         goto unexpected_vmexit;
5903
5904                 /*
5905                  * The host physical addresses of some pages of guest memory
5906                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5907                  * Page). The CPU may write to these pages via their host
5908                  * physical address while L2 is running, bypassing any
5909                  * address-translation-based dirty tracking (e.g. EPT write
5910                  * protection).
5911                  *
5912                  * Mark them dirty on every exit from L2 to prevent them from
5913                  * getting out of sync with dirty tracking.
5914                  */
5915                 nested_mark_vmcs12_pages_dirty(vcpu);
5916
5917                 if (nested_vmx_reflect_vmexit(vcpu))
5918                         return 1;
5919         }
5920
5921         if (exit_reason.failed_vmentry) {
5922                 dump_vmcs(vcpu);
5923                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5924                 vcpu->run->fail_entry.hardware_entry_failure_reason
5925                         = exit_reason.full;
5926                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5927                 return 0;
5928         }
5929
5930         if (unlikely(vmx->fail)) {
5931                 dump_vmcs(vcpu);
5932                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5933                 vcpu->run->fail_entry.hardware_entry_failure_reason
5934                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5935                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5936                 return 0;
5937         }
5938
5939         /*
5940          * Note:
5941          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5942          * delivery event since it indicates guest is accessing MMIO.
5943          * The vm-exit can be triggered again after return to guest that
5944          * will cause infinite loop.
5945          */
5946         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5947             (exit_reason.basic != EXIT_REASON_EXCEPTION_NMI &&
5948              exit_reason.basic != EXIT_REASON_EPT_VIOLATION &&
5949              exit_reason.basic != EXIT_REASON_PML_FULL &&
5950              exit_reason.basic != EXIT_REASON_APIC_ACCESS &&
5951              exit_reason.basic != EXIT_REASON_TASK_SWITCH)) {
5952                 int ndata = 3;
5953
5954                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5955                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5956                 vcpu->run->internal.data[0] = vectoring_info;
5957                 vcpu->run->internal.data[1] = exit_reason.full;
5958                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5959                 if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG) {
5960                         vcpu->run->internal.data[ndata++] =
5961                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5962                 }
5963                 vcpu->run->internal.data[ndata++] = vcpu->arch.last_vmentry_cpu;
5964                 vcpu->run->internal.ndata = ndata;
5965                 return 0;
5966         }
5967
5968         if (unlikely(!enable_vnmi &&
5969                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5970                 if (!vmx_interrupt_blocked(vcpu)) {
5971                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5972                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5973                            vcpu->arch.nmi_pending) {
5974                         /*
5975                          * This CPU don't support us in finding the end of an
5976                          * NMI-blocked window if the guest runs with IRQs
5977                          * disabled. So we pull the trigger after 1 s of
5978                          * futile waiting, but inform the user about this.
5979                          */
5980                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5981                                "state on VCPU %d after 1 s timeout\n",
5982                                __func__, vcpu->vcpu_id);
5983                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5984                 }
5985         }
5986
5987         if (exit_fastpath != EXIT_FASTPATH_NONE)
5988                 return 1;
5989
5990         if (exit_reason.basic >= kvm_vmx_max_exit_handlers)
5991                 goto unexpected_vmexit;
5992 #ifdef CONFIG_RETPOLINE
5993         if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
5994                 return kvm_emulate_wrmsr(vcpu);
5995         else if (exit_reason.basic == EXIT_REASON_PREEMPTION_TIMER)
5996                 return handle_preemption_timer(vcpu);
5997         else if (exit_reason.basic == EXIT_REASON_INTERRUPT_WINDOW)
5998                 return handle_interrupt_window(vcpu);
5999         else if (exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6000                 return handle_external_interrupt(vcpu);
6001         else if (exit_reason.basic == EXIT_REASON_HLT)
6002                 return kvm_emulate_halt(vcpu);
6003         else if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG)
6004                 return handle_ept_misconfig(vcpu);
6005 #endif
6006
6007         exit_handler_index = array_index_nospec((u16)exit_reason.basic,
6008                                                 kvm_vmx_max_exit_handlers);
6009         if (!kvm_vmx_exit_handlers[exit_handler_index])
6010                 goto unexpected_vmexit;
6011
6012         return kvm_vmx_exit_handlers[exit_handler_index](vcpu);
6013
6014 unexpected_vmexit:
6015         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
6016                     exit_reason.full);
6017         dump_vmcs(vcpu);
6018         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6019         vcpu->run->internal.suberror =
6020                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6021         vcpu->run->internal.ndata = 2;
6022         vcpu->run->internal.data[0] = exit_reason.full;
6023         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6024         return 0;
6025 }
6026
6027 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6028 {
6029         int ret = __vmx_handle_exit(vcpu, exit_fastpath);
6030
6031         /*
6032          * Exit to user space when bus lock detected to inform that there is
6033          * a bus lock in guest.
6034          */
6035         if (to_vmx(vcpu)->exit_reason.bus_lock_detected) {
6036                 if (ret > 0)
6037                         vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
6038
6039                 vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
6040                 return 0;
6041         }
6042         return ret;
6043 }
6044
6045 /*
6046  * Software based L1D cache flush which is used when microcode providing
6047  * the cache control MSR is not loaded.
6048  *
6049  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6050  * flush it is required to read in 64 KiB because the replacement algorithm
6051  * is not exactly LRU. This could be sized at runtime via topology
6052  * information but as all relevant affected CPUs have 32KiB L1D cache size
6053  * there is no point in doing so.
6054  */
6055 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6056 {
6057         int size = PAGE_SIZE << L1D_CACHE_ORDER;
6058
6059         /*
6060          * This code is only executed when the the flush mode is 'cond' or
6061          * 'always'
6062          */
6063         if (static_branch_likely(&vmx_l1d_flush_cond)) {
6064                 bool flush_l1d;
6065
6066                 /*
6067                  * Clear the per-vcpu flush bit, it gets set again
6068                  * either from vcpu_run() or from one of the unsafe
6069                  * VMEXIT handlers.
6070                  */
6071                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6072                 vcpu->arch.l1tf_flush_l1d = false;
6073
6074                 /*
6075                  * Clear the per-cpu flush bit, it gets set again from
6076                  * the interrupt handlers.
6077                  */
6078                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6079                 kvm_clear_cpu_l1tf_flush_l1d();
6080
6081                 if (!flush_l1d)
6082                         return;
6083         }
6084
6085         vcpu->stat.l1d_flush++;
6086
6087         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6088                 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6089                 return;
6090         }
6091
6092         asm volatile(
6093                 /* First ensure the pages are in the TLB */
6094                 "xorl   %%eax, %%eax\n"
6095                 ".Lpopulate_tlb:\n\t"
6096                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6097                 "addl   $4096, %%eax\n\t"
6098                 "cmpl   %%eax, %[size]\n\t"
6099                 "jne    .Lpopulate_tlb\n\t"
6100                 "xorl   %%eax, %%eax\n\t"
6101                 "cpuid\n\t"
6102                 /* Now fill the cache */
6103                 "xorl   %%eax, %%eax\n"
6104                 ".Lfill_cache:\n"
6105                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6106                 "addl   $64, %%eax\n\t"
6107                 "cmpl   %%eax, %[size]\n\t"
6108                 "jne    .Lfill_cache\n\t"
6109                 "lfence\n"
6110                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6111                     [size] "r" (size)
6112                 : "eax", "ebx", "ecx", "edx");
6113 }
6114
6115 static void vmx_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6116 {
6117         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6118         int tpr_threshold;
6119
6120         if (is_guest_mode(vcpu) &&
6121                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6122                 return;
6123
6124         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6125         if (is_guest_mode(vcpu))
6126                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6127         else
6128                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6129 }
6130
6131 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6132 {
6133         struct vcpu_vmx *vmx = to_vmx(vcpu);
6134         u32 sec_exec_control;
6135
6136         if (!lapic_in_kernel(vcpu))
6137                 return;
6138
6139         if (!flexpriority_enabled &&
6140             !cpu_has_vmx_virtualize_x2apic_mode())
6141                 return;
6142
6143         /* Postpone execution until vmcs01 is the current VMCS. */
6144         if (is_guest_mode(vcpu)) {
6145                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6146                 return;
6147         }
6148
6149         sec_exec_control = secondary_exec_controls_get(vmx);
6150         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6151                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6152
6153         switch (kvm_get_apic_mode(vcpu)) {
6154         case LAPIC_MODE_INVALID:
6155                 WARN_ONCE(true, "Invalid local APIC state");
6156                 break;
6157         case LAPIC_MODE_DISABLED:
6158                 break;
6159         case LAPIC_MODE_XAPIC:
6160                 if (flexpriority_enabled) {
6161                         sec_exec_control |=
6162                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6163                         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6164
6165                         /*
6166                          * Flush the TLB, reloading the APIC access page will
6167                          * only do so if its physical address has changed, but
6168                          * the guest may have inserted a non-APIC mapping into
6169                          * the TLB while the APIC access page was disabled.
6170                          */
6171                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6172                 }
6173                 break;
6174         case LAPIC_MODE_X2APIC:
6175                 if (cpu_has_vmx_virtualize_x2apic_mode())
6176                         sec_exec_control |=
6177                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6178                 break;
6179         }
6180         secondary_exec_controls_set(vmx, sec_exec_control);
6181
6182         vmx_update_msr_bitmap_x2apic(vcpu);
6183 }
6184
6185 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6186 {
6187         struct page *page;
6188
6189         /* Defer reload until vmcs01 is the current VMCS. */
6190         if (is_guest_mode(vcpu)) {
6191                 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6192                 return;
6193         }
6194
6195         if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6196             SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6197                 return;
6198
6199         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6200         if (is_error_page(page))
6201                 return;
6202
6203         vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6204         vmx_flush_tlb_current(vcpu);
6205
6206         /*
6207          * Do not pin apic access page in memory, the MMU notifier
6208          * will call us again if it is migrated or swapped out.
6209          */
6210         put_page(page);
6211 }
6212
6213 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6214 {
6215         u16 status;
6216         u8 old;
6217
6218         if (max_isr == -1)
6219                 max_isr = 0;
6220
6221         status = vmcs_read16(GUEST_INTR_STATUS);
6222         old = status >> 8;
6223         if (max_isr != old) {
6224                 status &= 0xff;
6225                 status |= max_isr << 8;
6226                 vmcs_write16(GUEST_INTR_STATUS, status);
6227         }
6228 }
6229
6230 static void vmx_set_rvi(int vector)
6231 {
6232         u16 status;
6233         u8 old;
6234
6235         if (vector == -1)
6236                 vector = 0;
6237
6238         status = vmcs_read16(GUEST_INTR_STATUS);
6239         old = (u8)status & 0xff;
6240         if ((u8)vector != old) {
6241                 status &= ~0xff;
6242                 status |= (u8)vector;
6243                 vmcs_write16(GUEST_INTR_STATUS, status);
6244         }
6245 }
6246
6247 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6248 {
6249         /*
6250          * When running L2, updating RVI is only relevant when
6251          * vmcs12 virtual-interrupt-delivery enabled.
6252          * However, it can be enabled only when L1 also
6253          * intercepts external-interrupts and in that case
6254          * we should not update vmcs02 RVI but instead intercept
6255          * interrupt. Therefore, do nothing when running L2.
6256          */
6257         if (!is_guest_mode(vcpu))
6258                 vmx_set_rvi(max_irr);
6259 }
6260
6261 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6262 {
6263         struct vcpu_vmx *vmx = to_vmx(vcpu);
6264         int max_irr;
6265         bool max_irr_updated;
6266
6267         if (KVM_BUG_ON(!vcpu->arch.apicv_active, vcpu->kvm))
6268                 return -EIO;
6269
6270         if (pi_test_on(&vmx->pi_desc)) {
6271                 pi_clear_on(&vmx->pi_desc);
6272                 /*
6273                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6274                  * But on x86 this is just a compiler barrier anyway.
6275                  */
6276                 smp_mb__after_atomic();
6277                 max_irr_updated =
6278                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6279
6280                 /*
6281                  * If we are running L2 and L1 has a new pending interrupt
6282                  * which can be injected, this may cause a vmexit or it may
6283                  * be injected into L2.  Either way, this interrupt will be
6284                  * processed via KVM_REQ_EVENT, not RVI, because we do not use
6285                  * virtual interrupt delivery to inject L1 interrupts into L2.
6286                  */
6287                 if (is_guest_mode(vcpu) && max_irr_updated)
6288                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6289         } else {
6290                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6291         }
6292         vmx_hwapic_irr_update(vcpu, max_irr);
6293         return max_irr;
6294 }
6295
6296 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6297 {
6298         if (!kvm_vcpu_apicv_active(vcpu))
6299                 return;
6300
6301         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6302         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6303         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6304         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6305 }
6306
6307 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6308 {
6309         struct vcpu_vmx *vmx = to_vmx(vcpu);
6310
6311         pi_clear_on(&vmx->pi_desc);
6312         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6313 }
6314
6315 void vmx_do_interrupt_nmi_irqoff(unsigned long entry);
6316
6317 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu,
6318                                         unsigned long entry)
6319 {
6320         kvm_before_interrupt(vcpu);
6321         vmx_do_interrupt_nmi_irqoff(entry);
6322         kvm_after_interrupt(vcpu);
6323 }
6324
6325 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6326 {
6327         const unsigned long nmi_entry = (unsigned long)asm_exc_nmi_noist;
6328         u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6329
6330         /* if exit due to PF check for async PF */
6331         if (is_page_fault(intr_info))
6332                 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6333         /* Handle machine checks before interrupts are enabled */
6334         else if (is_machine_check(intr_info))
6335                 kvm_machine_check();
6336         /* We need to handle NMIs before interrupts are enabled */
6337         else if (is_nmi(intr_info))
6338                 handle_interrupt_nmi_irqoff(&vmx->vcpu, nmi_entry);
6339 }
6340
6341 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6342 {
6343         u32 intr_info = vmx_get_intr_info(vcpu);
6344         unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK;
6345         gate_desc *desc = (gate_desc *)host_idt_base + vector;
6346
6347         if (KVM_BUG(!is_external_intr(intr_info), vcpu->kvm,
6348             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6349                 return;
6350
6351         handle_interrupt_nmi_irqoff(vcpu, gate_offset(desc));
6352 }
6353
6354 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6355 {
6356         struct vcpu_vmx *vmx = to_vmx(vcpu);
6357
6358         if (vmx->emulation_required)
6359                 return;
6360
6361         if (vmx->exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6362                 handle_external_interrupt_irqoff(vcpu);
6363         else if (vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI)
6364                 handle_exception_nmi_irqoff(vmx);
6365 }
6366
6367 /*
6368  * The kvm parameter can be NULL (module initialization, or invocation before
6369  * VM creation). Be sure to check the kvm parameter before using it.
6370  */
6371 static bool vmx_has_emulated_msr(struct kvm *kvm, u32 index)
6372 {
6373         switch (index) {
6374         case MSR_IA32_SMBASE:
6375                 /*
6376                  * We cannot do SMM unless we can run the guest in big
6377                  * real mode.
6378                  */
6379                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6380         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6381                 return nested;
6382         case MSR_AMD64_VIRT_SPEC_CTRL:
6383         case MSR_AMD64_TSC_RATIO:
6384                 /* This is AMD only.  */
6385                 return false;
6386         default:
6387                 return true;
6388         }
6389 }
6390
6391 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6392 {
6393         u32 exit_intr_info;
6394         bool unblock_nmi;
6395         u8 vector;
6396         bool idtv_info_valid;
6397
6398         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6399
6400         if (enable_vnmi) {
6401                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6402                         return;
6403
6404                 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6405                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6406                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6407                 /*
6408                  * SDM 3: 27.7.1.2 (September 2008)
6409                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6410                  * a guest IRET fault.
6411                  * SDM 3: 23.2.2 (September 2008)
6412                  * Bit 12 is undefined in any of the following cases:
6413                  *  If the VM exit sets the valid bit in the IDT-vectoring
6414                  *   information field.
6415                  *  If the VM exit is due to a double fault.
6416                  */
6417                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6418                     vector != DF_VECTOR && !idtv_info_valid)
6419                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6420                                       GUEST_INTR_STATE_NMI);
6421                 else
6422                         vmx->loaded_vmcs->nmi_known_unmasked =
6423                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6424                                   & GUEST_INTR_STATE_NMI);
6425         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6426                 vmx->loaded_vmcs->vnmi_blocked_time +=
6427                         ktime_to_ns(ktime_sub(ktime_get(),
6428                                               vmx->loaded_vmcs->entry_time));
6429 }
6430
6431 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6432                                       u32 idt_vectoring_info,
6433                                       int instr_len_field,
6434                                       int error_code_field)
6435 {
6436         u8 vector;
6437         int type;
6438         bool idtv_info_valid;
6439
6440         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6441
6442         vcpu->arch.nmi_injected = false;
6443         kvm_clear_exception_queue(vcpu);
6444         kvm_clear_interrupt_queue(vcpu);
6445
6446         if (!idtv_info_valid)
6447                 return;
6448
6449         kvm_make_request(KVM_REQ_EVENT, vcpu);
6450
6451         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6452         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6453
6454         switch (type) {
6455         case INTR_TYPE_NMI_INTR:
6456                 vcpu->arch.nmi_injected = true;
6457                 /*
6458                  * SDM 3: 27.7.1.2 (September 2008)
6459                  * Clear bit "block by NMI" before VM entry if a NMI
6460                  * delivery faulted.
6461                  */
6462                 vmx_set_nmi_mask(vcpu, false);
6463                 break;
6464         case INTR_TYPE_SOFT_EXCEPTION:
6465                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6466                 fallthrough;
6467         case INTR_TYPE_HARD_EXCEPTION:
6468                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6469                         u32 err = vmcs_read32(error_code_field);
6470                         kvm_requeue_exception_e(vcpu, vector, err);
6471                 } else
6472                         kvm_requeue_exception(vcpu, vector);
6473                 break;
6474         case INTR_TYPE_SOFT_INTR:
6475                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6476                 fallthrough;
6477         case INTR_TYPE_EXT_INTR:
6478                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6479                 break;
6480         default:
6481                 break;
6482         }
6483 }
6484
6485 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6486 {
6487         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6488                                   VM_EXIT_INSTRUCTION_LEN,
6489                                   IDT_VECTORING_ERROR_CODE);
6490 }
6491
6492 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6493 {
6494         __vmx_complete_interrupts(vcpu,
6495                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6496                                   VM_ENTRY_INSTRUCTION_LEN,
6497                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6498
6499         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6500 }
6501
6502 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6503 {
6504         int i, nr_msrs;
6505         struct perf_guest_switch_msr *msrs;
6506
6507         /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
6508         msrs = perf_guest_get_msrs(&nr_msrs);
6509         if (!msrs)
6510                 return;
6511
6512         for (i = 0; i < nr_msrs; i++)
6513                 if (msrs[i].host == msrs[i].guest)
6514                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6515                 else
6516                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6517                                         msrs[i].host, false);
6518 }
6519
6520 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6521 {
6522         struct vcpu_vmx *vmx = to_vmx(vcpu);
6523         u64 tscl;
6524         u32 delta_tsc;
6525
6526         if (vmx->req_immediate_exit) {
6527                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6528                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6529         } else if (vmx->hv_deadline_tsc != -1) {
6530                 tscl = rdtsc();
6531                 if (vmx->hv_deadline_tsc > tscl)
6532                         /* set_hv_timer ensures the delta fits in 32-bits */
6533                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6534                                 cpu_preemption_timer_multi);
6535                 else
6536                         delta_tsc = 0;
6537
6538                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6539                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6540         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6541                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6542                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6543         }
6544 }
6545
6546 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6547 {
6548         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6549                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6550                 vmcs_writel(HOST_RSP, host_rsp);
6551         }
6552 }
6553
6554 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6555 {
6556         switch (to_vmx(vcpu)->exit_reason.basic) {
6557         case EXIT_REASON_MSR_WRITE:
6558                 return handle_fastpath_set_msr_irqoff(vcpu);
6559         case EXIT_REASON_PREEMPTION_TIMER:
6560                 return handle_fastpath_preemption_timer(vcpu);
6561         default:
6562                 return EXIT_FASTPATH_NONE;
6563         }
6564 }
6565
6566 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6567                                         struct vcpu_vmx *vmx)
6568 {
6569         kvm_guest_enter_irqoff();
6570
6571         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6572         if (static_branch_unlikely(&vmx_l1d_should_flush))
6573                 vmx_l1d_flush(vcpu);
6574         else if (static_branch_unlikely(&mds_user_clear))
6575                 mds_clear_cpu_buffers();
6576
6577         if (vcpu->arch.cr2 != native_read_cr2())
6578                 native_write_cr2(vcpu->arch.cr2);
6579
6580         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6581                                    vmx->loaded_vmcs->launched);
6582
6583         vcpu->arch.cr2 = native_read_cr2();
6584
6585         kvm_guest_exit_irqoff();
6586 }
6587
6588 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6589 {
6590         struct vcpu_vmx *vmx = to_vmx(vcpu);
6591         unsigned long cr3, cr4;
6592
6593         /* Record the guest's net vcpu time for enforced NMI injections. */
6594         if (unlikely(!enable_vnmi &&
6595                      vmx->loaded_vmcs->soft_vnmi_blocked))
6596                 vmx->loaded_vmcs->entry_time = ktime_get();
6597
6598         /*
6599          * Don't enter VMX if guest state is invalid, let the exit handler
6600          * start emulation until we arrive back to a valid state.  Synthesize a
6601          * consistency check VM-Exit due to invalid guest state and bail.
6602          */
6603         if (unlikely(vmx->emulation_required)) {
6604
6605                 /* We don't emulate invalid state of a nested guest */
6606                 vmx->fail = is_guest_mode(vcpu);
6607
6608                 vmx->exit_reason.full = EXIT_REASON_INVALID_STATE;
6609                 vmx->exit_reason.failed_vmentry = 1;
6610                 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
6611                 vmx->exit_qualification = ENTRY_FAIL_DEFAULT;
6612                 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
6613                 vmx->exit_intr_info = 0;
6614                 return EXIT_FASTPATH_NONE;
6615         }
6616
6617         trace_kvm_entry(vcpu);
6618
6619         if (vmx->ple_window_dirty) {
6620                 vmx->ple_window_dirty = false;
6621                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6622         }
6623
6624         /*
6625          * We did this in prepare_switch_to_guest, because it needs to
6626          * be within srcu_read_lock.
6627          */
6628         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6629
6630         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6631                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6632         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6633                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6634
6635         cr3 = __get_current_cr3_fast();
6636         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6637                 vmcs_writel(HOST_CR3, cr3);
6638                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6639         }
6640
6641         cr4 = cr4_read_shadow();
6642         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6643                 vmcs_writel(HOST_CR4, cr4);
6644                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6645         }
6646
6647         /* When KVM_DEBUGREG_WONT_EXIT, dr6 is accessible in guest. */
6648         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
6649                 set_debugreg(vcpu->arch.dr6, 6);
6650
6651         /* When single-stepping over STI and MOV SS, we must clear the
6652          * corresponding interruptibility bits in the guest state. Otherwise
6653          * vmentry fails as it then expects bit 14 (BS) in pending debug
6654          * exceptions being set, but that's not correct for the guest debugging
6655          * case. */
6656         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6657                 vmx_set_interrupt_shadow(vcpu, 0);
6658
6659         kvm_load_guest_xsave_state(vcpu);
6660
6661         pt_guest_enter(vmx);
6662
6663         atomic_switch_perf_msrs(vmx);
6664         if (intel_pmu_lbr_is_enabled(vcpu))
6665                 vmx_passthrough_lbr_msrs(vcpu);
6666
6667         if (enable_preemption_timer)
6668                 vmx_update_hv_timer(vcpu);
6669
6670         kvm_wait_lapic_expire(vcpu);
6671
6672         /*
6673          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6674          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6675          * is no need to worry about the conditional branch over the wrmsr
6676          * being speculatively taken.
6677          */
6678         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6679
6680         /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6681         vmx_vcpu_enter_exit(vcpu, vmx);
6682
6683         /*
6684          * We do not use IBRS in the kernel. If this vCPU has used the
6685          * SPEC_CTRL MSR it may have left it on; save the value and
6686          * turn it off. This is much more efficient than blindly adding
6687          * it to the atomic save/restore list. Especially as the former
6688          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6689          *
6690          * For non-nested case:
6691          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6692          * save it.
6693          *
6694          * For nested case:
6695          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6696          * save it.
6697          */
6698         if (unlikely(!msr_write_intercepted(vmx, MSR_IA32_SPEC_CTRL)))
6699                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6700
6701         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6702
6703         /* All fields are clean at this point */
6704         if (static_branch_unlikely(&enable_evmcs)) {
6705                 current_evmcs->hv_clean_fields |=
6706                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6707
6708                 current_evmcs->hv_vp_id = kvm_hv_get_vpindex(vcpu);
6709         }
6710
6711         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6712         if (vmx->host_debugctlmsr)
6713                 update_debugctlmsr(vmx->host_debugctlmsr);
6714
6715 #ifndef CONFIG_X86_64
6716         /*
6717          * The sysexit path does not restore ds/es, so we must set them to
6718          * a reasonable value ourselves.
6719          *
6720          * We can't defer this to vmx_prepare_switch_to_host() since that
6721          * function may be executed in interrupt context, which saves and
6722          * restore segments around it, nullifying its effect.
6723          */
6724         loadsegment(ds, __USER_DS);
6725         loadsegment(es, __USER_DS);
6726 #endif
6727
6728         vmx_register_cache_reset(vcpu);
6729
6730         pt_guest_exit(vmx);
6731
6732         kvm_load_host_xsave_state(vcpu);
6733
6734         if (is_guest_mode(vcpu)) {
6735                 /*
6736                  * Track VMLAUNCH/VMRESUME that have made past guest state
6737                  * checking.
6738                  */
6739                 if (vmx->nested.nested_run_pending &&
6740                     !vmx->exit_reason.failed_vmentry)
6741                         ++vcpu->stat.nested_run;
6742
6743                 vmx->nested.nested_run_pending = 0;
6744         }
6745
6746         vmx->idt_vectoring_info = 0;
6747
6748         if (unlikely(vmx->fail)) {
6749                 vmx->exit_reason.full = 0xdead;
6750                 return EXIT_FASTPATH_NONE;
6751         }
6752
6753         vmx->exit_reason.full = vmcs_read32(VM_EXIT_REASON);
6754         if (unlikely((u16)vmx->exit_reason.basic == EXIT_REASON_MCE_DURING_VMENTRY))
6755                 kvm_machine_check();
6756
6757         if (likely(!vmx->exit_reason.failed_vmentry))
6758                 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6759
6760         trace_kvm_exit(vcpu, KVM_ISA_VMX);
6761
6762         if (unlikely(vmx->exit_reason.failed_vmentry))
6763                 return EXIT_FASTPATH_NONE;
6764
6765         vmx->loaded_vmcs->launched = 1;
6766
6767         vmx_recover_nmi_blocking(vmx);
6768         vmx_complete_interrupts(vmx);
6769
6770         if (is_guest_mode(vcpu))
6771                 return EXIT_FASTPATH_NONE;
6772
6773         return vmx_exit_handlers_fastpath(vcpu);
6774 }
6775
6776 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6777 {
6778         struct vcpu_vmx *vmx = to_vmx(vcpu);
6779
6780         if (enable_pml)
6781                 vmx_destroy_pml_buffer(vmx);
6782         free_vpid(vmx->vpid);
6783         nested_vmx_free_vcpu(vcpu);
6784         free_loaded_vmcs(vmx->loaded_vmcs);
6785 }
6786
6787 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6788 {
6789         struct vmx_uret_msr *tsx_ctrl;
6790         struct vcpu_vmx *vmx;
6791         int i, err;
6792
6793         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6794         vmx = to_vmx(vcpu);
6795
6796         err = -ENOMEM;
6797
6798         vmx->vpid = allocate_vpid();
6799
6800         /*
6801          * If PML is turned on, failure on enabling PML just results in failure
6802          * of creating the vcpu, therefore we can simplify PML logic (by
6803          * avoiding dealing with cases, such as enabling PML partially on vcpus
6804          * for the guest), etc.
6805          */
6806         if (enable_pml) {
6807                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6808                 if (!vmx->pml_pg)
6809                         goto free_vpid;
6810         }
6811
6812         for (i = 0; i < kvm_nr_uret_msrs; ++i)
6813                 vmx->guest_uret_msrs[i].mask = -1ull;
6814         if (boot_cpu_has(X86_FEATURE_RTM)) {
6815                 /*
6816                  * TSX_CTRL_CPUID_CLEAR is handled in the CPUID interception.
6817                  * Keep the host value unchanged to avoid changing CPUID bits
6818                  * under the host kernel's feet.
6819                  */
6820                 tsx_ctrl = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
6821                 if (tsx_ctrl)
6822                         tsx_ctrl->mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6823         }
6824
6825         err = alloc_loaded_vmcs(&vmx->vmcs01);
6826         if (err < 0)
6827                 goto free_pml;
6828
6829         /* The MSR bitmap starts with all ones */
6830         bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6831         bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6832
6833         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
6834 #ifdef CONFIG_X86_64
6835         vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
6836         vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
6837         vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6838 #endif
6839         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6840         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6841         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6842         if (kvm_cstate_in_guest(vcpu->kvm)) {
6843                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
6844                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6845                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6846                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6847         }
6848
6849         vmx->loaded_vmcs = &vmx->vmcs01;
6850
6851         if (cpu_need_virtualize_apic_accesses(vcpu)) {
6852                 err = alloc_apic_access_page(vcpu->kvm);
6853                 if (err)
6854                         goto free_vmcs;
6855         }
6856
6857         if (enable_ept && !enable_unrestricted_guest) {
6858                 err = init_rmode_identity_map(vcpu->kvm);
6859                 if (err)
6860                         goto free_vmcs;
6861         }
6862
6863         return 0;
6864
6865 free_vmcs:
6866         free_loaded_vmcs(vmx->loaded_vmcs);
6867 free_pml:
6868         vmx_destroy_pml_buffer(vmx);
6869 free_vpid:
6870         free_vpid(vmx->vpid);
6871         return err;
6872 }
6873
6874 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6875 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6876
6877 static int vmx_vm_init(struct kvm *kvm)
6878 {
6879         if (!ple_gap)
6880                 kvm->arch.pause_in_guest = true;
6881
6882         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6883                 switch (l1tf_mitigation) {
6884                 case L1TF_MITIGATION_OFF:
6885                 case L1TF_MITIGATION_FLUSH_NOWARN:
6886                         /* 'I explicitly don't care' is set */
6887                         break;
6888                 case L1TF_MITIGATION_FLUSH:
6889                 case L1TF_MITIGATION_FLUSH_NOSMT:
6890                 case L1TF_MITIGATION_FULL:
6891                         /*
6892                          * Warn upon starting the first VM in a potentially
6893                          * insecure environment.
6894                          */
6895                         if (sched_smt_active())
6896                                 pr_warn_once(L1TF_MSG_SMT);
6897                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6898                                 pr_warn_once(L1TF_MSG_L1D);
6899                         break;
6900                 case L1TF_MITIGATION_FULL_FORCE:
6901                         /* Flush is enforced */
6902                         break;
6903                 }
6904         }
6905         return 0;
6906 }
6907
6908 static int __init vmx_check_processor_compat(void)
6909 {
6910         struct vmcs_config vmcs_conf;
6911         struct vmx_capability vmx_cap;
6912
6913         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6914             !this_cpu_has(X86_FEATURE_VMX)) {
6915                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6916                 return -EIO;
6917         }
6918
6919         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6920                 return -EIO;
6921         if (nested)
6922                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6923         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6924                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6925                                 smp_processor_id());
6926                 return -EIO;
6927         }
6928         return 0;
6929 }
6930
6931 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6932 {
6933         u8 cache;
6934         u64 ipat = 0;
6935
6936         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6937          * memory aliases with conflicting memory types and sometimes MCEs.
6938          * We have to be careful as to what are honored and when.
6939          *
6940          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
6941          * UC.  The effective memory type is UC or WC depending on guest PAT.
6942          * This was historically the source of MCEs and we want to be
6943          * conservative.
6944          *
6945          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6946          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
6947          * EPT memory type is set to WB.  The effective memory type is forced
6948          * WB.
6949          *
6950          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
6951          * EPT memory type is used to emulate guest CD/MTRR.
6952          */
6953
6954         if (is_mmio) {
6955                 cache = MTRR_TYPE_UNCACHABLE;
6956                 goto exit;
6957         }
6958
6959         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6960                 ipat = VMX_EPT_IPAT_BIT;
6961                 cache = MTRR_TYPE_WRBACK;
6962                 goto exit;
6963         }
6964
6965         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6966                 ipat = VMX_EPT_IPAT_BIT;
6967                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6968                         cache = MTRR_TYPE_WRBACK;
6969                 else
6970                         cache = MTRR_TYPE_UNCACHABLE;
6971                 goto exit;
6972         }
6973
6974         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6975
6976 exit:
6977         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6978 }
6979
6980 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx, u32 new_ctl)
6981 {
6982         /*
6983          * These bits in the secondary execution controls field
6984          * are dynamic, the others are mostly based on the hypervisor
6985          * architecture and the guest's CPUID.  Do not touch the
6986          * dynamic bits.
6987          */
6988         u32 mask =
6989                 SECONDARY_EXEC_SHADOW_VMCS |
6990                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6991                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6992                 SECONDARY_EXEC_DESC;
6993
6994         u32 cur_ctl = secondary_exec_controls_get(vmx);
6995
6996         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6997 }
6998
6999 /*
7000  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7001  * (indicating "allowed-1") if they are supported in the guest's CPUID.
7002  */
7003 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7004 {
7005         struct vcpu_vmx *vmx = to_vmx(vcpu);
7006         struct kvm_cpuid_entry2 *entry;
7007
7008         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7009         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7010
7011 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
7012         if (entry && (entry->_reg & (_cpuid_mask)))                     \
7013                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
7014 } while (0)
7015
7016         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7017         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
7018         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
7019         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
7020         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
7021         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
7022         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
7023         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
7024         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
7025         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
7026         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7027         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
7028         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
7029         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
7030         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
7031
7032         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7033         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
7034         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
7035         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
7036         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
7037         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
7038         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
7039
7040 #undef cr4_fixed1_update
7041 }
7042
7043 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7044 {
7045         struct vcpu_vmx *vmx = to_vmx(vcpu);
7046
7047         if (kvm_mpx_supported()) {
7048                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7049
7050                 if (mpx_enabled) {
7051                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7052                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7053                 } else {
7054                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7055                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7056                 }
7057         }
7058 }
7059
7060 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7061 {
7062         struct vcpu_vmx *vmx = to_vmx(vcpu);
7063         struct kvm_cpuid_entry2 *best = NULL;
7064         int i;
7065
7066         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7067                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7068                 if (!best)
7069                         return;
7070                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7071                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7072                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7073                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7074         }
7075
7076         /* Get the number of configurable Address Ranges for filtering */
7077         vmx->pt_desc.num_address_ranges = intel_pt_validate_cap(vmx->pt_desc.caps,
7078                                                 PT_CAP_num_address_ranges);
7079
7080         /* Initialize and clear the no dependency bits */
7081         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7082                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC |
7083                         RTIT_CTL_BRANCH_EN);
7084
7085         /*
7086          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7087          * will inject an #GP
7088          */
7089         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7090                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7091
7092         /*
7093          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7094          * PSBFreq can be set
7095          */
7096         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7097                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7098                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7099
7100         /*
7101          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn and MTCFreq can be set
7102          */
7103         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7104                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7105                                               RTIT_CTL_MTC_RANGE);
7106
7107         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7108         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7109                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7110                                                         RTIT_CTL_PTW_EN);
7111
7112         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7113         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7114                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7115
7116         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7117         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7118                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7119
7120         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabricEn can be set */
7121         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7122                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7123
7124         /* unmask address range configure area */
7125         for (i = 0; i < vmx->pt_desc.num_address_ranges; i++)
7126                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7127 }
7128
7129 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7130 {
7131         struct vcpu_vmx *vmx = to_vmx(vcpu);
7132
7133         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7134         vcpu->arch.xsaves_enabled = false;
7135
7136         vmx_setup_uret_msrs(vmx);
7137
7138         if (cpu_has_secondary_exec_ctrls())
7139                 vmcs_set_secondary_exec_control(vmx,
7140                                                 vmx_secondary_exec_control(vmx));
7141
7142         if (nested_vmx_allowed(vcpu))
7143                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7144                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7145                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7146         else
7147                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7148                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7149                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7150
7151         if (nested_vmx_allowed(vcpu)) {
7152                 nested_vmx_cr_fixed1_bits_update(vcpu);
7153                 nested_vmx_entry_exit_ctls_update(vcpu);
7154         }
7155
7156         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7157                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7158                 update_intel_pt_cfg(vcpu);
7159
7160         if (boot_cpu_has(X86_FEATURE_RTM)) {
7161                 struct vmx_uret_msr *msr;
7162                 msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
7163                 if (msr) {
7164                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7165                         vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7166                 }
7167         }
7168
7169         set_cr4_guest_host_mask(vmx);
7170
7171         vmx_write_encls_bitmap(vcpu, NULL);
7172         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX))
7173                 vmx->msr_ia32_feature_control_valid_bits |= FEAT_CTL_SGX_ENABLED;
7174         else
7175                 vmx->msr_ia32_feature_control_valid_bits &= ~FEAT_CTL_SGX_ENABLED;
7176
7177         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
7178                 vmx->msr_ia32_feature_control_valid_bits |=
7179                         FEAT_CTL_SGX_LC_ENABLED;
7180         else
7181                 vmx->msr_ia32_feature_control_valid_bits &=
7182                         ~FEAT_CTL_SGX_LC_ENABLED;
7183
7184         /* Refresh #PF interception to account for MAXPHYADDR changes. */
7185         vmx_update_exception_bitmap(vcpu);
7186 }
7187
7188 static __init void vmx_set_cpu_caps(void)
7189 {
7190         kvm_set_cpu_caps();
7191
7192         /* CPUID 0x1 */
7193         if (nested)
7194                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7195
7196         /* CPUID 0x7 */
7197         if (kvm_mpx_supported())
7198                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7199         if (!cpu_has_vmx_invpcid())
7200                 kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
7201         if (vmx_pt_mode_is_host_guest())
7202                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7203
7204         if (!enable_sgx) {
7205                 kvm_cpu_cap_clear(X86_FEATURE_SGX);
7206                 kvm_cpu_cap_clear(X86_FEATURE_SGX_LC);
7207                 kvm_cpu_cap_clear(X86_FEATURE_SGX1);
7208                 kvm_cpu_cap_clear(X86_FEATURE_SGX2);
7209         }
7210
7211         if (vmx_umip_emulated())
7212                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7213
7214         /* CPUID 0xD.1 */
7215         supported_xss = 0;
7216         if (!cpu_has_vmx_xsaves())
7217                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7218
7219         /* CPUID 0x80000001 and 0x7 (RDPID) */
7220         if (!cpu_has_vmx_rdtscp()) {
7221                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7222                 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
7223         }
7224
7225         if (cpu_has_vmx_waitpkg())
7226                 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7227 }
7228
7229 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7230 {
7231         to_vmx(vcpu)->req_immediate_exit = true;
7232 }
7233
7234 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7235                                   struct x86_instruction_info *info)
7236 {
7237         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7238         unsigned short port;
7239         bool intercept;
7240         int size;
7241
7242         if (info->intercept == x86_intercept_in ||
7243             info->intercept == x86_intercept_ins) {
7244                 port = info->src_val;
7245                 size = info->dst_bytes;
7246         } else {
7247                 port = info->dst_val;
7248                 size = info->src_bytes;
7249         }
7250
7251         /*
7252          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7253          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7254          * control.
7255          *
7256          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7257          */
7258         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7259                 intercept = nested_cpu_has(vmcs12,
7260                                            CPU_BASED_UNCOND_IO_EXITING);
7261         else
7262                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7263
7264         /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7265         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7266 }
7267
7268 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7269                                struct x86_instruction_info *info,
7270                                enum x86_intercept_stage stage,
7271                                struct x86_exception *exception)
7272 {
7273         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7274
7275         switch (info->intercept) {
7276         /*
7277          * RDPID causes #UD if disabled through secondary execution controls.
7278          * Because it is marked as EmulateOnUD, we need to intercept it here.
7279          * Note, RDPID is hidden behind ENABLE_RDTSCP.
7280          */
7281         case x86_intercept_rdpid:
7282                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) {
7283                         exception->vector = UD_VECTOR;
7284                         exception->error_code_valid = false;
7285                         return X86EMUL_PROPAGATE_FAULT;
7286                 }
7287                 break;
7288
7289         case x86_intercept_in:
7290         case x86_intercept_ins:
7291         case x86_intercept_out:
7292         case x86_intercept_outs:
7293                 return vmx_check_intercept_io(vcpu, info);
7294
7295         case x86_intercept_lgdt:
7296         case x86_intercept_lidt:
7297         case x86_intercept_lldt:
7298         case x86_intercept_ltr:
7299         case x86_intercept_sgdt:
7300         case x86_intercept_sidt:
7301         case x86_intercept_sldt:
7302         case x86_intercept_str:
7303                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7304                         return X86EMUL_CONTINUE;
7305
7306                 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7307                 break;
7308
7309         /* TODO: check more intercepts... */
7310         default:
7311                 break;
7312         }
7313
7314         return X86EMUL_UNHANDLEABLE;
7315 }
7316
7317 #ifdef CONFIG_X86_64
7318 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7319 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7320                                   u64 divisor, u64 *result)
7321 {
7322         u64 low = a << shift, high = a >> (64 - shift);
7323
7324         /* To avoid the overflow on divq */
7325         if (high >= divisor)
7326                 return 1;
7327
7328         /* Low hold the result, high hold rem which is discarded */
7329         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7330             "rm" (divisor), "0" (low), "1" (high));
7331         *result = low;
7332
7333         return 0;
7334 }
7335
7336 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7337                             bool *expired)
7338 {
7339         struct vcpu_vmx *vmx;
7340         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7341         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7342
7343         vmx = to_vmx(vcpu);
7344         tscl = rdtsc();
7345         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7346         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7347         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7348                                                     ktimer->timer_advance_ns);
7349
7350         if (delta_tsc > lapic_timer_advance_cycles)
7351                 delta_tsc -= lapic_timer_advance_cycles;
7352         else
7353                 delta_tsc = 0;
7354
7355         /* Convert to host delta tsc if tsc scaling is enabled */
7356         if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7357             delta_tsc && u64_shl_div_u64(delta_tsc,
7358                                 kvm_tsc_scaling_ratio_frac_bits,
7359                                 vcpu->arch.l1_tsc_scaling_ratio, &delta_tsc))
7360                 return -ERANGE;
7361
7362         /*
7363          * If the delta tsc can't fit in the 32 bit after the multi shift,
7364          * we can't use the preemption timer.
7365          * It's possible that it fits on later vmentries, but checking
7366          * on every vmentry is costly so we just use an hrtimer.
7367          */
7368         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7369                 return -ERANGE;
7370
7371         vmx->hv_deadline_tsc = tscl + delta_tsc;
7372         *expired = !delta_tsc;
7373         return 0;
7374 }
7375
7376 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7377 {
7378         to_vmx(vcpu)->hv_deadline_tsc = -1;
7379 }
7380 #endif
7381
7382 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7383 {
7384         if (!kvm_pause_in_guest(vcpu->kvm))
7385                 shrink_ple_window(vcpu);
7386 }
7387
7388 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu)
7389 {
7390         struct vcpu_vmx *vmx = to_vmx(vcpu);
7391
7392         if (is_guest_mode(vcpu)) {
7393                 vmx->nested.update_vmcs01_cpu_dirty_logging = true;
7394                 return;
7395         }
7396
7397         /*
7398          * Note, cpu_dirty_logging_count can be changed concurrent with this
7399          * code, but in that case another update request will be made and so
7400          * the guest will never run with a stale PML value.
7401          */
7402         if (vcpu->kvm->arch.cpu_dirty_logging_count)
7403                 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7404         else
7405                 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7406 }
7407
7408 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7409 {
7410         if (pi_pre_block(vcpu))
7411                 return 1;
7412
7413         if (kvm_lapic_hv_timer_in_use(vcpu))
7414                 kvm_lapic_switch_to_sw_timer(vcpu);
7415
7416         return 0;
7417 }
7418
7419 static void vmx_post_block(struct kvm_vcpu *vcpu)
7420 {
7421         if (kvm_x86_ops.set_hv_timer)
7422                 kvm_lapic_switch_to_hv_timer(vcpu);
7423
7424         pi_post_block(vcpu);
7425 }
7426
7427 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7428 {
7429         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7430                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7431                         FEAT_CTL_LMCE_ENABLED;
7432         else
7433                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7434                         ~FEAT_CTL_LMCE_ENABLED;
7435 }
7436
7437 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7438 {
7439         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7440         if (to_vmx(vcpu)->nested.nested_run_pending)
7441                 return -EBUSY;
7442         return !is_smm(vcpu);
7443 }
7444
7445 static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7446 {
7447         struct vcpu_vmx *vmx = to_vmx(vcpu);
7448
7449         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7450         if (vmx->nested.smm.guest_mode)
7451                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7452
7453         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7454         vmx->nested.vmxon = false;
7455         vmx_clear_hlt(vcpu);
7456         return 0;
7457 }
7458
7459 static int vmx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7460 {
7461         struct vcpu_vmx *vmx = to_vmx(vcpu);
7462         int ret;
7463
7464         if (vmx->nested.smm.vmxon) {
7465                 vmx->nested.vmxon = true;
7466                 vmx->nested.smm.vmxon = false;
7467         }
7468
7469         if (vmx->nested.smm.guest_mode) {
7470                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7471                 if (ret)
7472                         return ret;
7473
7474                 vmx->nested.smm.guest_mode = false;
7475         }
7476         return 0;
7477 }
7478
7479 static void vmx_enable_smi_window(struct kvm_vcpu *vcpu)
7480 {
7481         /* RSM will cause a vmexit anyway.  */
7482 }
7483
7484 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7485 {
7486         return to_vmx(vcpu)->nested.vmxon && !is_guest_mode(vcpu);
7487 }
7488
7489 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7490 {
7491         if (is_guest_mode(vcpu)) {
7492                 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7493
7494                 if (hrtimer_try_to_cancel(timer) == 1)
7495                         hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7496         }
7497 }
7498
7499 static void hardware_unsetup(void)
7500 {
7501         kvm_set_posted_intr_wakeup_handler(NULL);
7502
7503         if (nested)
7504                 nested_vmx_hardware_unsetup();
7505
7506         free_kvm_area();
7507 }
7508
7509 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7510 {
7511         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7512                           BIT(APICV_INHIBIT_REASON_HYPERV) |
7513                           BIT(APICV_INHIBIT_REASON_BLOCKIRQ);
7514
7515         return supported & BIT(bit);
7516 }
7517
7518 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7519         .name = "kvm_intel",
7520
7521         .hardware_unsetup = hardware_unsetup,
7522
7523         .hardware_enable = hardware_enable,
7524         .hardware_disable = hardware_disable,
7525         .cpu_has_accelerated_tpr = report_flexpriority,
7526         .has_emulated_msr = vmx_has_emulated_msr,
7527
7528         .vm_size = sizeof(struct kvm_vmx),
7529         .vm_init = vmx_vm_init,
7530
7531         .vcpu_create = vmx_create_vcpu,
7532         .vcpu_free = vmx_free_vcpu,
7533         .vcpu_reset = vmx_vcpu_reset,
7534
7535         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7536         .vcpu_load = vmx_vcpu_load,
7537         .vcpu_put = vmx_vcpu_put,
7538
7539         .update_exception_bitmap = vmx_update_exception_bitmap,
7540         .get_msr_feature = vmx_get_msr_feature,
7541         .get_msr = vmx_get_msr,
7542         .set_msr = vmx_set_msr,
7543         .get_segment_base = vmx_get_segment_base,
7544         .get_segment = vmx_get_segment,
7545         .set_segment = vmx_set_segment,
7546         .get_cpl = vmx_get_cpl,
7547         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7548         .set_cr0 = vmx_set_cr0,
7549         .is_valid_cr4 = vmx_is_valid_cr4,
7550         .set_cr4 = vmx_set_cr4,
7551         .set_efer = vmx_set_efer,
7552         .get_idt = vmx_get_idt,
7553         .set_idt = vmx_set_idt,
7554         .get_gdt = vmx_get_gdt,
7555         .set_gdt = vmx_set_gdt,
7556         .set_dr7 = vmx_set_dr7,
7557         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7558         .cache_reg = vmx_cache_reg,
7559         .get_rflags = vmx_get_rflags,
7560         .set_rflags = vmx_set_rflags,
7561
7562         .tlb_flush_all = vmx_flush_tlb_all,
7563         .tlb_flush_current = vmx_flush_tlb_current,
7564         .tlb_flush_gva = vmx_flush_tlb_gva,
7565         .tlb_flush_guest = vmx_flush_tlb_guest,
7566
7567         .run = vmx_vcpu_run,
7568         .handle_exit = vmx_handle_exit,
7569         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7570         .update_emulated_instruction = vmx_update_emulated_instruction,
7571         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7572         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7573         .patch_hypercall = vmx_patch_hypercall,
7574         .set_irq = vmx_inject_irq,
7575         .set_nmi = vmx_inject_nmi,
7576         .queue_exception = vmx_queue_exception,
7577         .cancel_injection = vmx_cancel_injection,
7578         .interrupt_allowed = vmx_interrupt_allowed,
7579         .nmi_allowed = vmx_nmi_allowed,
7580         .get_nmi_mask = vmx_get_nmi_mask,
7581         .set_nmi_mask = vmx_set_nmi_mask,
7582         .enable_nmi_window = vmx_enable_nmi_window,
7583         .enable_irq_window = vmx_enable_irq_window,
7584         .update_cr8_intercept = vmx_update_cr8_intercept,
7585         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7586         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7587         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7588         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7589         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7590         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7591         .hwapic_irr_update = vmx_hwapic_irr_update,
7592         .hwapic_isr_update = vmx_hwapic_isr_update,
7593         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7594         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7595         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7596         .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
7597
7598         .set_tss_addr = vmx_set_tss_addr,
7599         .set_identity_map_addr = vmx_set_identity_map_addr,
7600         .get_mt_mask = vmx_get_mt_mask,
7601
7602         .get_exit_info = vmx_get_exit_info,
7603
7604         .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7605
7606         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7607
7608         .get_l2_tsc_offset = vmx_get_l2_tsc_offset,
7609         .get_l2_tsc_multiplier = vmx_get_l2_tsc_multiplier,
7610         .write_tsc_offset = vmx_write_tsc_offset,
7611         .write_tsc_multiplier = vmx_write_tsc_multiplier,
7612
7613         .load_mmu_pgd = vmx_load_mmu_pgd,
7614
7615         .check_intercept = vmx_check_intercept,
7616         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7617
7618         .request_immediate_exit = vmx_request_immediate_exit,
7619
7620         .sched_in = vmx_sched_in,
7621
7622         .cpu_dirty_log_size = PML_ENTITY_NUM,
7623         .update_cpu_dirty_logging = vmx_update_cpu_dirty_logging,
7624
7625         .pre_block = vmx_pre_block,
7626         .post_block = vmx_post_block,
7627
7628         .pmu_ops = &intel_pmu_ops,
7629         .nested_ops = &vmx_nested_ops,
7630
7631         .update_pi_irte = pi_update_irte,
7632         .start_assignment = vmx_pi_start_assignment,
7633
7634 #ifdef CONFIG_X86_64
7635         .set_hv_timer = vmx_set_hv_timer,
7636         .cancel_hv_timer = vmx_cancel_hv_timer,
7637 #endif
7638
7639         .setup_mce = vmx_setup_mce,
7640
7641         .smi_allowed = vmx_smi_allowed,
7642         .enter_smm = vmx_enter_smm,
7643         .leave_smm = vmx_leave_smm,
7644         .enable_smi_window = vmx_enable_smi_window,
7645
7646         .can_emulate_instruction = vmx_can_emulate_instruction,
7647         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7648         .migrate_timers = vmx_migrate_timers,
7649
7650         .msr_filter_changed = vmx_msr_filter_changed,
7651         .complete_emulated_msr = kvm_complete_insn_gp,
7652
7653         .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector,
7654 };
7655
7656 static __init void vmx_setup_user_return_msrs(void)
7657 {
7658
7659         /*
7660          * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
7661          * will emulate SYSCALL in legacy mode if the vendor string in guest
7662          * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
7663          * support this emulation, MSR_STAR is included in the list for i386,
7664          * but is never loaded into hardware.  MSR_CSTAR is also never loaded
7665          * into hardware and is here purely for emulation purposes.
7666          */
7667         const u32 vmx_uret_msrs_list[] = {
7668         #ifdef CONFIG_X86_64
7669                 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
7670         #endif
7671                 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
7672                 MSR_IA32_TSX_CTRL,
7673         };
7674         int i;
7675
7676         BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
7677
7678         for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
7679                 kvm_add_user_return_msr(vmx_uret_msrs_list[i]);
7680 }
7681
7682 static __init int hardware_setup(void)
7683 {
7684         unsigned long host_bndcfgs;
7685         struct desc_ptr dt;
7686         int r, ept_lpage_level;
7687
7688         store_idt(&dt);
7689         host_idt_base = dt.address;
7690
7691         vmx_setup_user_return_msrs();
7692
7693         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7694                 return -EIO;
7695
7696         if (boot_cpu_has(X86_FEATURE_NX))
7697                 kvm_enable_efer_bits(EFER_NX);
7698
7699         if (boot_cpu_has(X86_FEATURE_MPX)) {
7700                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7701                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7702         }
7703
7704         if (!cpu_has_vmx_mpx())
7705                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7706                                     XFEATURE_MASK_BNDCSR);
7707
7708         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7709             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7710                 enable_vpid = 0;
7711
7712         if (!cpu_has_vmx_ept() ||
7713             !cpu_has_vmx_ept_4levels() ||
7714             !cpu_has_vmx_ept_mt_wb() ||
7715             !cpu_has_vmx_invept_global())
7716                 enable_ept = 0;
7717
7718         /* NX support is required for shadow paging. */
7719         if (!enable_ept && !boot_cpu_has(X86_FEATURE_NX)) {
7720                 pr_err_ratelimited("kvm: NX (Execute Disable) not supported\n");
7721                 return -EOPNOTSUPP;
7722         }
7723
7724         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7725                 enable_ept_ad_bits = 0;
7726
7727         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7728                 enable_unrestricted_guest = 0;
7729
7730         if (!cpu_has_vmx_flexpriority())
7731                 flexpriority_enabled = 0;
7732
7733         if (!cpu_has_virtual_nmis())
7734                 enable_vnmi = 0;
7735
7736         /*
7737          * set_apic_access_page_addr() is used to reload apic access
7738          * page upon invalidation.  No need to do anything if not
7739          * using the APIC_ACCESS_ADDR VMCS field.
7740          */
7741         if (!flexpriority_enabled)
7742                 vmx_x86_ops.set_apic_access_page_addr = NULL;
7743
7744         if (!cpu_has_vmx_tpr_shadow())
7745                 vmx_x86_ops.update_cr8_intercept = NULL;
7746
7747 #if IS_ENABLED(CONFIG_HYPERV)
7748         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7749             && enable_ept) {
7750                 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7751                 vmx_x86_ops.tlb_remote_flush_with_range =
7752                                 hv_remote_flush_tlb_with_range;
7753         }
7754 #endif
7755
7756         if (!cpu_has_vmx_ple()) {
7757                 ple_gap = 0;
7758                 ple_window = 0;
7759                 ple_window_grow = 0;
7760                 ple_window_max = 0;
7761                 ple_window_shrink = 0;
7762         }
7763
7764         if (!cpu_has_vmx_apicv()) {
7765                 enable_apicv = 0;
7766                 vmx_x86_ops.sync_pir_to_irr = NULL;
7767         }
7768
7769         if (cpu_has_vmx_tsc_scaling()) {
7770                 kvm_has_tsc_control = true;
7771                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7772                 kvm_tsc_scaling_ratio_frac_bits = 48;
7773         }
7774
7775         kvm_has_bus_lock_exit = cpu_has_vmx_bus_lock_detection();
7776
7777         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7778
7779         if (enable_ept)
7780                 kvm_mmu_set_ept_masks(enable_ept_ad_bits,
7781                                       cpu_has_vmx_ept_execute_only());
7782
7783         if (!enable_ept)
7784                 ept_lpage_level = 0;
7785         else if (cpu_has_vmx_ept_1g_page())
7786                 ept_lpage_level = PG_LEVEL_1G;
7787         else if (cpu_has_vmx_ept_2m_page())
7788                 ept_lpage_level = PG_LEVEL_2M;
7789         else
7790                 ept_lpage_level = PG_LEVEL_4K;
7791         kvm_configure_mmu(enable_ept, 0, vmx_get_max_tdp_level(),
7792                           ept_lpage_level);
7793
7794         /*
7795          * Only enable PML when hardware supports PML feature, and both EPT
7796          * and EPT A/D bit features are enabled -- PML depends on them to work.
7797          */
7798         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7799                 enable_pml = 0;
7800
7801         if (!enable_pml)
7802                 vmx_x86_ops.cpu_dirty_log_size = 0;
7803
7804         if (!cpu_has_vmx_preemption_timer())
7805                 enable_preemption_timer = false;
7806
7807         if (enable_preemption_timer) {
7808                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7809                 u64 vmx_msr;
7810
7811                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7812                 cpu_preemption_timer_multi =
7813                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7814
7815                 if (tsc_khz)
7816                         use_timer_freq = (u64)tsc_khz * 1000;
7817                 use_timer_freq >>= cpu_preemption_timer_multi;
7818
7819                 /*
7820                  * KVM "disables" the preemption timer by setting it to its max
7821                  * value.  Don't use the timer if it might cause spurious exits
7822                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7823                  */
7824                 if (use_timer_freq > 0xffffffffu / 10)
7825                         enable_preemption_timer = false;
7826         }
7827
7828         if (!enable_preemption_timer) {
7829                 vmx_x86_ops.set_hv_timer = NULL;
7830                 vmx_x86_ops.cancel_hv_timer = NULL;
7831                 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
7832         }
7833
7834         kvm_mce_cap_supported |= MCG_LMCE_P;
7835
7836         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7837                 return -EINVAL;
7838         if (!enable_ept || !cpu_has_vmx_intel_pt())
7839                 pt_mode = PT_MODE_SYSTEM;
7840
7841         setup_default_sgx_lepubkeyhash();
7842
7843         if (nested) {
7844                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7845                                            vmx_capability.ept);
7846
7847                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7848                 if (r)
7849                         return r;
7850         }
7851
7852         vmx_set_cpu_caps();
7853
7854         r = alloc_kvm_area();
7855         if (r)
7856                 nested_vmx_hardware_unsetup();
7857
7858         kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler);
7859
7860         return r;
7861 }
7862
7863 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
7864         .cpu_has_kvm_support = cpu_has_kvm_support,
7865         .disabled_by_bios = vmx_disabled_by_bios,
7866         .check_processor_compatibility = vmx_check_processor_compat,
7867         .hardware_setup = hardware_setup,
7868
7869         .runtime_ops = &vmx_x86_ops,
7870 };
7871
7872 static void vmx_cleanup_l1d_flush(void)
7873 {
7874         if (vmx_l1d_flush_pages) {
7875                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7876                 vmx_l1d_flush_pages = NULL;
7877         }
7878         /* Restore state so sysfs ignores VMX */
7879         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7880 }
7881
7882 static void vmx_exit(void)
7883 {
7884 #ifdef CONFIG_KEXEC_CORE
7885         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7886         synchronize_rcu();
7887 #endif
7888
7889         kvm_exit();
7890
7891 #if IS_ENABLED(CONFIG_HYPERV)
7892         if (static_branch_unlikely(&enable_evmcs)) {
7893                 int cpu;
7894                 struct hv_vp_assist_page *vp_ap;
7895                 /*
7896                  * Reset everything to support using non-enlightened VMCS
7897                  * access later (e.g. when we reload the module with
7898                  * enlightened_vmcs=0)
7899                  */
7900                 for_each_online_cpu(cpu) {
7901                         vp_ap = hv_get_vp_assist_page(cpu);
7902
7903                         if (!vp_ap)
7904                                 continue;
7905
7906                         vp_ap->nested_control.features.directhypercall = 0;
7907                         vp_ap->current_nested_vmcs = 0;
7908                         vp_ap->enlighten_vmentry = 0;
7909                 }
7910
7911                 static_branch_disable(&enable_evmcs);
7912         }
7913 #endif
7914         vmx_cleanup_l1d_flush();
7915
7916         allow_smaller_maxphyaddr = false;
7917 }
7918 module_exit(vmx_exit);
7919
7920 static int __init vmx_init(void)
7921 {
7922         int r, cpu;
7923
7924 #if IS_ENABLED(CONFIG_HYPERV)
7925         /*
7926          * Enlightened VMCS usage should be recommended and the host needs
7927          * to support eVMCS v1 or above. We can also disable eVMCS support
7928          * with module parameter.
7929          */
7930         if (enlightened_vmcs &&
7931             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7932             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7933             KVM_EVMCS_VERSION) {
7934                 int cpu;
7935
7936                 /* Check that we have assist pages on all online CPUs */
7937                 for_each_online_cpu(cpu) {
7938                         if (!hv_get_vp_assist_page(cpu)) {
7939                                 enlightened_vmcs = false;
7940                                 break;
7941                         }
7942                 }
7943
7944                 if (enlightened_vmcs) {
7945                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7946                         static_branch_enable(&enable_evmcs);
7947                 }
7948
7949                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7950                         vmx_x86_ops.enable_direct_tlbflush
7951                                 = hv_enable_direct_tlbflush;
7952
7953         } else {
7954                 enlightened_vmcs = false;
7955         }
7956 #endif
7957
7958         r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
7959                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7960         if (r)
7961                 return r;
7962
7963         /*
7964          * Must be called after kvm_init() so enable_ept is properly set
7965          * up. Hand the parameter mitigation value in which was stored in
7966          * the pre module init parser. If no parameter was given, it will
7967          * contain 'auto' which will be turned into the default 'cond'
7968          * mitigation mode.
7969          */
7970         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7971         if (r) {
7972                 vmx_exit();
7973                 return r;
7974         }
7975
7976         for_each_possible_cpu(cpu) {
7977                 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
7978
7979                 pi_init_cpu(cpu);
7980         }
7981
7982 #ifdef CONFIG_KEXEC_CORE
7983         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7984                            crash_vmclear_local_loaded_vmcss);
7985 #endif
7986         vmx_check_vmcs12_offsets();
7987
7988         /*
7989          * Shadow paging doesn't have a (further) performance penalty
7990          * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it
7991          * by default
7992          */
7993         if (!enable_ept)
7994                 allow_smaller_maxphyaddr = true;
7995
7996         return 0;
7997 }
7998 module_init(vmx_init);