1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/highmem.h>
17 #include <linux/hrtimer.h>
18 #include <linux/kernel.h>
19 #include <linux/kvm_host.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/mod_devicetable.h>
24 #include <linux/objtool.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
30 #include <linux/entry-kvm.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/debugreg.h>
38 #include <asm/fpu/api.h>
39 #include <asm/idtentry.h>
41 #include <asm/irq_remapping.h>
42 #include <asm/kexec.h>
43 #include <asm/perf_event.h>
44 #include <asm/mmu_context.h>
45 #include <asm/mshyperv.h>
46 #include <asm/mwait.h>
47 #include <asm/spec-ctrl.h>
48 #include <asm/virtext.h>
51 #include "capabilities.h"
55 #include "kvm_onhyperv.h"
57 #include "kvm_cache_regs.h"
69 MODULE_AUTHOR("Qumranet");
70 MODULE_LICENSE("GPL");
73 static const struct x86_cpu_id vmx_cpu_id[] = {
74 X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
77 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
80 bool __read_mostly enable_vpid = 1;
81 module_param_named(vpid, enable_vpid, bool, 0444);
83 static bool __read_mostly enable_vnmi = 1;
84 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
86 bool __read_mostly flexpriority_enabled = 1;
87 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
89 bool __read_mostly enable_ept = 1;
90 module_param_named(ept, enable_ept, bool, S_IRUGO);
92 bool __read_mostly enable_unrestricted_guest = 1;
93 module_param_named(unrestricted_guest,
94 enable_unrestricted_guest, bool, S_IRUGO);
96 bool __read_mostly enable_ept_ad_bits = 1;
97 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
99 static bool __read_mostly emulate_invalid_guest_state = true;
100 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
102 static bool __read_mostly fasteoi = 1;
103 module_param(fasteoi, bool, S_IRUGO);
105 module_param(enable_apicv, bool, S_IRUGO);
108 * If nested=1, nested virtualization is supported, i.e., guests may use
109 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
110 * use VMX instructions.
112 static bool __read_mostly nested = 1;
113 module_param(nested, bool, S_IRUGO);
115 bool __read_mostly enable_pml = 1;
116 module_param_named(pml, enable_pml, bool, S_IRUGO);
118 static bool __read_mostly dump_invalid_vmcs = 0;
119 module_param(dump_invalid_vmcs, bool, 0644);
121 #define MSR_BITMAP_MODE_X2APIC 1
122 #define MSR_BITMAP_MODE_X2APIC_APICV 2
124 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
126 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
127 static int __read_mostly cpu_preemption_timer_multi;
128 static bool __read_mostly enable_preemption_timer = 1;
130 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
133 extern bool __read_mostly allow_smaller_maxphyaddr;
134 module_param(allow_smaller_maxphyaddr, bool, S_IRUGO);
136 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
137 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
138 #define KVM_VM_CR0_ALWAYS_ON \
139 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
141 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
142 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
143 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
145 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
147 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
148 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
149 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
150 RTIT_STATUS_BYTECNT))
153 * List of MSRs that can be directly passed to the guest.
154 * In addition to these x2apic and PT MSRs are handled specially.
156 static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = {
165 MSR_IA32_SYSENTER_CS,
166 MSR_IA32_SYSENTER_ESP,
167 MSR_IA32_SYSENTER_EIP,
169 MSR_CORE_C3_RESIDENCY,
170 MSR_CORE_C6_RESIDENCY,
171 MSR_CORE_C7_RESIDENCY,
175 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
176 * ple_gap: upper bound on the amount of time between two successive
177 * executions of PAUSE in a loop. Also indicate if ple enabled.
178 * According to test, this time is usually smaller than 128 cycles.
179 * ple_window: upper bound on the amount of time a guest is allowed to execute
180 * in a PAUSE loop. Tests indicate that most spinlocks are held for
181 * less than 2^12 cycles
182 * Time is measured based on a counter that runs at the same rate as the TSC,
183 * refer SDM volume 3b section 21.6.13 & 22.1.3.
185 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
186 module_param(ple_gap, uint, 0444);
188 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
189 module_param(ple_window, uint, 0444);
191 /* Default doubles per-vcpu window every exit. */
192 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
193 module_param(ple_window_grow, uint, 0444);
195 /* Default resets per-vcpu window every exit to ple_window. */
196 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
197 module_param(ple_window_shrink, uint, 0444);
199 /* Default is to compute the maximum so we can never overflow. */
200 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
201 module_param(ple_window_max, uint, 0444);
203 /* Default is SYSTEM mode, 1 for host-guest mode */
204 int __read_mostly pt_mode = PT_MODE_SYSTEM;
205 module_param(pt_mode, int, S_IRUGO);
207 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
208 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
209 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
211 /* Storage for pre module init parameter parsing */
212 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
214 static const struct {
217 } vmentry_l1d_param[] = {
218 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
219 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
220 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
221 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
222 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
223 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
226 #define L1D_CACHE_ORDER 4
227 static void *vmx_l1d_flush_pages;
229 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
234 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
235 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
240 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
244 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
247 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
248 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
249 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
254 /* If set to auto use the default l1tf mitigation method */
255 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
256 switch (l1tf_mitigation) {
257 case L1TF_MITIGATION_OFF:
258 l1tf = VMENTER_L1D_FLUSH_NEVER;
260 case L1TF_MITIGATION_FLUSH_NOWARN:
261 case L1TF_MITIGATION_FLUSH:
262 case L1TF_MITIGATION_FLUSH_NOSMT:
263 l1tf = VMENTER_L1D_FLUSH_COND;
265 case L1TF_MITIGATION_FULL:
266 case L1TF_MITIGATION_FULL_FORCE:
267 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
270 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
271 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
274 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
275 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
277 * This allocation for vmx_l1d_flush_pages is not tied to a VM
278 * lifetime and so should not be charged to a memcg.
280 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
283 vmx_l1d_flush_pages = page_address(page);
286 * Initialize each page with a different pattern in
287 * order to protect against KSM in the nested
288 * virtualization case.
290 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
291 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
296 l1tf_vmx_mitigation = l1tf;
298 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
299 static_branch_enable(&vmx_l1d_should_flush);
301 static_branch_disable(&vmx_l1d_should_flush);
303 if (l1tf == VMENTER_L1D_FLUSH_COND)
304 static_branch_enable(&vmx_l1d_flush_cond);
306 static_branch_disable(&vmx_l1d_flush_cond);
310 static int vmentry_l1d_flush_parse(const char *s)
315 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
316 if (vmentry_l1d_param[i].for_parse &&
317 sysfs_streq(s, vmentry_l1d_param[i].option))
324 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
328 l1tf = vmentry_l1d_flush_parse(s);
332 if (!boot_cpu_has(X86_BUG_L1TF))
336 * Has vmx_init() run already? If not then this is the pre init
337 * parameter parsing. In that case just store the value and let
338 * vmx_init() do the proper setup after enable_ept has been
341 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
342 vmentry_l1d_flush_param = l1tf;
346 mutex_lock(&vmx_l1d_flush_mutex);
347 ret = vmx_setup_l1d_flush(l1tf);
348 mutex_unlock(&vmx_l1d_flush_mutex);
352 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
354 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
355 return sprintf(s, "???\n");
357 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
360 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
361 .set = vmentry_l1d_flush_set,
362 .get = vmentry_l1d_flush_get,
364 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
366 static u32 vmx_segment_access_rights(struct kvm_segment *var);
368 void vmx_vmexit(void);
370 #define vmx_insn_failed(fmt...) \
373 pr_warn_ratelimited(fmt); \
376 asmlinkage void vmread_error(unsigned long field, bool fault)
379 kvm_spurious_fault();
381 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
384 noinline void vmwrite_error(unsigned long field, unsigned long value)
386 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
387 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
390 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
392 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
395 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
397 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
400 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
402 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
406 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
408 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
412 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
413 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
415 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
416 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
418 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
420 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
421 static DEFINE_SPINLOCK(vmx_vpid_lock);
423 struct vmcs_config vmcs_config;
424 struct vmx_capability vmx_capability;
426 #define VMX_SEGMENT_FIELD(seg) \
427 [VCPU_SREG_##seg] = { \
428 .selector = GUEST_##seg##_SELECTOR, \
429 .base = GUEST_##seg##_BASE, \
430 .limit = GUEST_##seg##_LIMIT, \
431 .ar_bytes = GUEST_##seg##_AR_BYTES, \
434 static const struct kvm_vmx_segment_field {
439 } kvm_vmx_segment_fields[] = {
440 VMX_SEGMENT_FIELD(CS),
441 VMX_SEGMENT_FIELD(DS),
442 VMX_SEGMENT_FIELD(ES),
443 VMX_SEGMENT_FIELD(FS),
444 VMX_SEGMENT_FIELD(GS),
445 VMX_SEGMENT_FIELD(SS),
446 VMX_SEGMENT_FIELD(TR),
447 VMX_SEGMENT_FIELD(LDTR),
450 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
452 vmx->segment_cache.bitmask = 0;
455 static unsigned long host_idt_base;
457 #if IS_ENABLED(CONFIG_HYPERV)
458 static bool __read_mostly enlightened_vmcs = true;
459 module_param(enlightened_vmcs, bool, 0444);
461 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
463 struct hv_enlightened_vmcs *evmcs;
464 struct hv_partition_assist_pg **p_hv_pa_pg =
465 &to_kvm_hv(vcpu->kvm)->hv_pa_pg;
467 * Synthetic VM-Exit is not enabled in current code and so All
468 * evmcs in singe VM shares same assist page.
471 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
476 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
478 evmcs->partition_assist_page =
480 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
481 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
486 #endif /* IS_ENABLED(CONFIG_HYPERV) */
489 * Comment's format: document - errata name - stepping - processor name.
491 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
493 static u32 vmx_preemption_cpu_tfms[] = {
494 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
496 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
497 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
498 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
500 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
502 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
503 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
505 * 320767.pdf - AAP86 - B1 -
506 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
509 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
511 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
513 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
515 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
516 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
517 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
519 /* Xeon E3-1220 V2 */
523 static inline bool cpu_has_broken_vmx_preemption_timer(void)
525 u32 eax = cpuid_eax(0x00000001), i;
527 /* Clear the reserved bits */
528 eax &= ~(0x3U << 14 | 0xfU << 28);
529 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
530 if (eax == vmx_preemption_cpu_tfms[i])
536 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
538 return flexpriority_enabled && lapic_in_kernel(vcpu);
541 static inline bool report_flexpriority(void)
543 return flexpriority_enabled;
546 static int possible_passthrough_msr_slot(u32 msr)
550 for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++)
551 if (vmx_possible_passthrough_msrs[i] == msr)
557 static bool is_valid_passthrough_msr(u32 msr)
562 case 0x800 ... 0x8ff:
563 /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */
565 case MSR_IA32_RTIT_STATUS:
566 case MSR_IA32_RTIT_OUTPUT_BASE:
567 case MSR_IA32_RTIT_OUTPUT_MASK:
568 case MSR_IA32_RTIT_CR3_MATCH:
569 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
570 /* PT MSRs. These are handled in pt_update_intercept_for_msr() */
573 case MSR_LBR_INFO_0 ... MSR_LBR_INFO_0 + 31:
574 case MSR_LBR_NHM_FROM ... MSR_LBR_NHM_FROM + 31:
575 case MSR_LBR_NHM_TO ... MSR_LBR_NHM_TO + 31:
576 case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8:
577 case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8:
578 /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */
582 r = possible_passthrough_msr_slot(msr) != -ENOENT;
584 WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr);
589 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
593 i = kvm_find_user_return_msr(msr);
595 return &vmx->guest_uret_msrs[i];
599 static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx,
600 struct vmx_uret_msr *msr, u64 data)
602 unsigned int slot = msr - vmx->guest_uret_msrs;
605 u64 old_msr_data = msr->data;
607 if (msr->load_into_hardware) {
609 ret = kvm_set_user_return_msr(slot, msr->data, msr->mask);
612 msr->data = old_msr_data;
617 #ifdef CONFIG_KEXEC_CORE
618 static void crash_vmclear_local_loaded_vmcss(void)
620 int cpu = raw_smp_processor_id();
621 struct loaded_vmcs *v;
623 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
624 loaded_vmcss_on_cpu_link)
627 #endif /* CONFIG_KEXEC_CORE */
629 static void __loaded_vmcs_clear(void *arg)
631 struct loaded_vmcs *loaded_vmcs = arg;
632 int cpu = raw_smp_processor_id();
634 if (loaded_vmcs->cpu != cpu)
635 return; /* vcpu migration can race with cpu offline */
636 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
637 per_cpu(current_vmcs, cpu) = NULL;
639 vmcs_clear(loaded_vmcs->vmcs);
640 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
641 vmcs_clear(loaded_vmcs->shadow_vmcs);
643 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
646 * Ensure all writes to loaded_vmcs, including deleting it from its
647 * current percpu list, complete before setting loaded_vmcs->vcpu to
648 * -1, otherwise a different cpu can see vcpu == -1 first and add
649 * loaded_vmcs to its percpu list before it's deleted from this cpu's
650 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
654 loaded_vmcs->cpu = -1;
655 loaded_vmcs->launched = 0;
658 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
660 int cpu = loaded_vmcs->cpu;
663 smp_call_function_single(cpu,
664 __loaded_vmcs_clear, loaded_vmcs, 1);
667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
671 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
673 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
674 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
675 vmx->segment_cache.bitmask = 0;
677 ret = vmx->segment_cache.bitmask & mask;
678 vmx->segment_cache.bitmask |= mask;
682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
684 u16 *p = &vmx->segment_cache.seg[seg].selector;
686 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
687 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
693 ulong *p = &vmx->segment_cache.seg[seg].base;
695 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
696 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
702 u32 *p = &vmx->segment_cache.seg[seg].limit;
704 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
705 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
711 u32 *p = &vmx->segment_cache.seg[seg].ar;
713 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
714 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
718 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu)
722 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
723 (1u << DB_VECTOR) | (1u << AC_VECTOR);
725 * Guest access to VMware backdoor ports could legitimately
726 * trigger #GP because of TSS I/O permission bitmap.
727 * We intercept those #GP and allow access to them anyway
730 if (enable_vmware_backdoor)
731 eb |= (1u << GP_VECTOR);
732 if ((vcpu->guest_debug &
733 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
734 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
735 eb |= 1u << BP_VECTOR;
736 if (to_vmx(vcpu)->rmode.vm86_active)
738 if (!vmx_need_pf_intercept(vcpu))
739 eb &= ~(1u << PF_VECTOR);
741 /* When we are running a nested L2 guest and L1 specified for it a
742 * certain exception bitmap, we must trap the same exceptions and pass
743 * them to L1. When running L2, we will only handle the exceptions
744 * specified above if L1 did not want them.
746 if (is_guest_mode(vcpu))
747 eb |= get_vmcs12(vcpu)->exception_bitmap;
749 int mask = 0, match = 0;
751 if (enable_ept && (eb & (1u << PF_VECTOR))) {
753 * If EPT is enabled, #PF is currently only intercepted
754 * if MAXPHYADDR is smaller on the guest than on the
755 * host. In that case we only care about present,
756 * non-reserved faults. For vmcs02, however, PFEC_MASK
757 * and PFEC_MATCH are set in prepare_vmcs02_rare.
759 mask = PFERR_PRESENT_MASK | PFERR_RSVD_MASK;
760 match = PFERR_PRESENT_MASK;
762 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
763 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, match);
766 vmcs_write32(EXCEPTION_BITMAP, eb);
770 * Check if MSR is intercepted for currently loaded MSR bitmap.
772 static bool msr_write_intercepted(struct vcpu_vmx *vmx, u32 msr)
774 if (!(exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS))
777 return vmx_test_msr_bitmap_write(vmx->loaded_vmcs->msr_bitmap,
781 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
782 unsigned long entry, unsigned long exit)
784 vm_entry_controls_clearbit(vmx, entry);
785 vm_exit_controls_clearbit(vmx, exit);
788 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr)
792 for (i = 0; i < m->nr; ++i) {
793 if (m->val[i].index == msr)
799 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
802 struct msr_autoload *m = &vmx->msr_autoload;
806 if (cpu_has_load_ia32_efer()) {
807 clear_atomic_switch_msr_special(vmx,
808 VM_ENTRY_LOAD_IA32_EFER,
809 VM_EXIT_LOAD_IA32_EFER);
813 case MSR_CORE_PERF_GLOBAL_CTRL:
814 if (cpu_has_load_perf_global_ctrl()) {
815 clear_atomic_switch_msr_special(vmx,
816 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
817 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
822 i = vmx_find_loadstore_msr_slot(&m->guest, msr);
826 m->guest.val[i] = m->guest.val[m->guest.nr];
827 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
830 i = vmx_find_loadstore_msr_slot(&m->host, msr);
835 m->host.val[i] = m->host.val[m->host.nr];
836 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
839 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
840 unsigned long entry, unsigned long exit,
841 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
842 u64 guest_val, u64 host_val)
844 vmcs_write64(guest_val_vmcs, guest_val);
845 if (host_val_vmcs != HOST_IA32_EFER)
846 vmcs_write64(host_val_vmcs, host_val);
847 vm_entry_controls_setbit(vmx, entry);
848 vm_exit_controls_setbit(vmx, exit);
851 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
852 u64 guest_val, u64 host_val, bool entry_only)
855 struct msr_autoload *m = &vmx->msr_autoload;
859 if (cpu_has_load_ia32_efer()) {
860 add_atomic_switch_msr_special(vmx,
861 VM_ENTRY_LOAD_IA32_EFER,
862 VM_EXIT_LOAD_IA32_EFER,
865 guest_val, host_val);
869 case MSR_CORE_PERF_GLOBAL_CTRL:
870 if (cpu_has_load_perf_global_ctrl()) {
871 add_atomic_switch_msr_special(vmx,
872 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
873 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
874 GUEST_IA32_PERF_GLOBAL_CTRL,
875 HOST_IA32_PERF_GLOBAL_CTRL,
876 guest_val, host_val);
880 case MSR_IA32_PEBS_ENABLE:
881 /* PEBS needs a quiescent period after being disabled (to write
882 * a record). Disabling PEBS through VMX MSR swapping doesn't
883 * provide that period, so a CPU could write host's record into
886 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
889 i = vmx_find_loadstore_msr_slot(&m->guest, msr);
891 j = vmx_find_loadstore_msr_slot(&m->host, msr);
893 if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) ||
894 (j < 0 && m->host.nr == MAX_NR_LOADSTORE_MSRS)) {
895 printk_once(KERN_WARNING "Not enough msr switch entries. "
896 "Can't add msr %x\n", msr);
901 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
903 m->guest.val[i].index = msr;
904 m->guest.val[i].value = guest_val;
911 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
913 m->host.val[j].index = msr;
914 m->host.val[j].value = host_val;
917 static bool update_transition_efer(struct vcpu_vmx *vmx)
919 u64 guest_efer = vmx->vcpu.arch.efer;
923 /* Shadow paging assumes NX to be available. */
925 guest_efer |= EFER_NX;
928 * LMA and LME handled by hardware; SCE meaningless outside long mode.
930 ignore_bits |= EFER_SCE;
932 ignore_bits |= EFER_LMA | EFER_LME;
933 /* SCE is meaningful only in long mode on Intel */
934 if (guest_efer & EFER_LMA)
935 ignore_bits &= ~(u64)EFER_SCE;
939 * On EPT, we can't emulate NX, so we must switch EFER atomically.
940 * On CPUs that support "load IA32_EFER", always switch EFER
941 * atomically, since it's faster than switching it manually.
943 if (cpu_has_load_ia32_efer() ||
944 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
945 if (!(guest_efer & EFER_LMA))
946 guest_efer &= ~EFER_LME;
947 if (guest_efer != host_efer)
948 add_atomic_switch_msr(vmx, MSR_EFER,
949 guest_efer, host_efer, false);
951 clear_atomic_switch_msr(vmx, MSR_EFER);
955 i = kvm_find_user_return_msr(MSR_EFER);
959 clear_atomic_switch_msr(vmx, MSR_EFER);
961 guest_efer &= ~ignore_bits;
962 guest_efer |= host_efer & ignore_bits;
964 vmx->guest_uret_msrs[i].data = guest_efer;
965 vmx->guest_uret_msrs[i].mask = ~ignore_bits;
972 * On 32-bit kernels, VM exits still load the FS and GS bases from the
973 * VMCS rather than the segment table. KVM uses this helper to figure
974 * out the current bases to poke them into the VMCS before entry.
976 static unsigned long segment_base(u16 selector)
978 struct desc_struct *table;
981 if (!(selector & ~SEGMENT_RPL_MASK))
984 table = get_current_gdt_ro();
986 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
987 u16 ldt_selector = kvm_read_ldt();
989 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
992 table = (struct desc_struct *)segment_base(ldt_selector);
994 v = get_desc_base(&table[selector >> 3]);
999 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1001 return vmx_pt_mode_is_host_guest() &&
1002 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1005 static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base)
1007 /* The base must be 128-byte aligned and a legal physical address. */
1008 return kvm_vcpu_is_legal_aligned_gpa(vcpu, base, 128);
1011 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1015 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1016 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1017 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1018 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1019 for (i = 0; i < addr_range; i++) {
1020 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1021 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1025 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1029 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1030 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1031 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1032 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1033 for (i = 0; i < addr_range; i++) {
1034 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1035 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1039 static void pt_guest_enter(struct vcpu_vmx *vmx)
1041 if (vmx_pt_mode_is_system())
1045 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1046 * Save host state before VM entry.
1048 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1049 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1050 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1051 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1052 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1056 static void pt_guest_exit(struct vcpu_vmx *vmx)
1058 if (vmx_pt_mode_is_system())
1061 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1062 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1063 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1067 * KVM requires VM_EXIT_CLEAR_IA32_RTIT_CTL to expose PT to the guest,
1068 * i.e. RTIT_CTL is always cleared on VM-Exit. Restore it if necessary.
1070 if (vmx->pt_desc.host.ctl)
1071 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1074 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1075 unsigned long fs_base, unsigned long gs_base)
1077 if (unlikely(fs_sel != host->fs_sel)) {
1079 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1081 vmcs_write16(HOST_FS_SELECTOR, 0);
1082 host->fs_sel = fs_sel;
1084 if (unlikely(gs_sel != host->gs_sel)) {
1086 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1088 vmcs_write16(HOST_GS_SELECTOR, 0);
1089 host->gs_sel = gs_sel;
1091 if (unlikely(fs_base != host->fs_base)) {
1092 vmcs_writel(HOST_FS_BASE, fs_base);
1093 host->fs_base = fs_base;
1095 if (unlikely(gs_base != host->gs_base)) {
1096 vmcs_writel(HOST_GS_BASE, gs_base);
1097 host->gs_base = gs_base;
1101 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1103 struct vcpu_vmx *vmx = to_vmx(vcpu);
1104 struct vmcs_host_state *host_state;
1105 #ifdef CONFIG_X86_64
1106 int cpu = raw_smp_processor_id();
1108 unsigned long fs_base, gs_base;
1112 vmx->req_immediate_exit = false;
1115 * Note that guest MSRs to be saved/restored can also be changed
1116 * when guest state is loaded. This happens when guest transitions
1117 * to/from long-mode by setting MSR_EFER.LMA.
1119 if (!vmx->guest_uret_msrs_loaded) {
1120 vmx->guest_uret_msrs_loaded = true;
1121 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
1122 if (!vmx->guest_uret_msrs[i].load_into_hardware)
1125 kvm_set_user_return_msr(i,
1126 vmx->guest_uret_msrs[i].data,
1127 vmx->guest_uret_msrs[i].mask);
1131 if (vmx->nested.need_vmcs12_to_shadow_sync)
1132 nested_sync_vmcs12_to_shadow(vcpu);
1134 if (vmx->guest_state_loaded)
1137 host_state = &vmx->loaded_vmcs->host_state;
1140 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1141 * allow segment selectors with cpl > 0 or ti == 1.
1143 host_state->ldt_sel = kvm_read_ldt();
1145 #ifdef CONFIG_X86_64
1146 savesegment(ds, host_state->ds_sel);
1147 savesegment(es, host_state->es_sel);
1149 gs_base = cpu_kernelmode_gs_base(cpu);
1150 if (likely(is_64bit_mm(current->mm))) {
1151 current_save_fsgs();
1152 fs_sel = current->thread.fsindex;
1153 gs_sel = current->thread.gsindex;
1154 fs_base = current->thread.fsbase;
1155 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1157 savesegment(fs, fs_sel);
1158 savesegment(gs, gs_sel);
1159 fs_base = read_msr(MSR_FS_BASE);
1160 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1163 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1165 savesegment(fs, fs_sel);
1166 savesegment(gs, gs_sel);
1167 fs_base = segment_base(fs_sel);
1168 gs_base = segment_base(gs_sel);
1171 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1172 vmx->guest_state_loaded = true;
1175 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1177 struct vmcs_host_state *host_state;
1179 if (!vmx->guest_state_loaded)
1182 host_state = &vmx->loaded_vmcs->host_state;
1184 ++vmx->vcpu.stat.host_state_reload;
1186 #ifdef CONFIG_X86_64
1187 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1189 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1190 kvm_load_ldt(host_state->ldt_sel);
1191 #ifdef CONFIG_X86_64
1192 load_gs_index(host_state->gs_sel);
1194 loadsegment(gs, host_state->gs_sel);
1197 if (host_state->fs_sel & 7)
1198 loadsegment(fs, host_state->fs_sel);
1199 #ifdef CONFIG_X86_64
1200 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1201 loadsegment(ds, host_state->ds_sel);
1202 loadsegment(es, host_state->es_sel);
1205 invalidate_tss_limit();
1206 #ifdef CONFIG_X86_64
1207 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1209 load_fixmap_gdt(raw_smp_processor_id());
1210 vmx->guest_state_loaded = false;
1211 vmx->guest_uret_msrs_loaded = false;
1214 #ifdef CONFIG_X86_64
1215 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1218 if (vmx->guest_state_loaded)
1219 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1221 return vmx->msr_guest_kernel_gs_base;
1224 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1227 if (vmx->guest_state_loaded)
1228 wrmsrl(MSR_KERNEL_GS_BASE, data);
1230 vmx->msr_guest_kernel_gs_base = data;
1234 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1235 struct loaded_vmcs *buddy)
1237 struct vcpu_vmx *vmx = to_vmx(vcpu);
1238 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1241 if (!already_loaded) {
1242 loaded_vmcs_clear(vmx->loaded_vmcs);
1243 local_irq_disable();
1246 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1247 * this cpu's percpu list, otherwise it may not yet be deleted
1248 * from its previous cpu's percpu list. Pairs with the
1249 * smb_wmb() in __loaded_vmcs_clear().
1253 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1254 &per_cpu(loaded_vmcss_on_cpu, cpu));
1258 prev = per_cpu(current_vmcs, cpu);
1259 if (prev != vmx->loaded_vmcs->vmcs) {
1260 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1261 vmcs_load(vmx->loaded_vmcs->vmcs);
1264 * No indirect branch prediction barrier needed when switching
1265 * the active VMCS within a guest, e.g. on nested VM-Enter.
1266 * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1268 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1269 indirect_branch_prediction_barrier();
1272 if (!already_loaded) {
1273 void *gdt = get_current_gdt_ro();
1274 unsigned long sysenter_esp;
1277 * Flush all EPTP/VPID contexts, the new pCPU may have stale
1278 * TLB entries from its previous association with the vCPU.
1280 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1283 * Linux uses per-cpu TSS and GDT, so set these when switching
1284 * processors. See 22.2.4.
1286 vmcs_writel(HOST_TR_BASE,
1287 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1288 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1290 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1291 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1293 vmx->loaded_vmcs->cpu = cpu;
1298 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1299 * vcpu mutex is already taken.
1301 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1303 struct vcpu_vmx *vmx = to_vmx(vcpu);
1305 vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1307 vmx_vcpu_pi_load(vcpu, cpu);
1309 vmx->host_debugctlmsr = get_debugctlmsr();
1312 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1314 vmx_vcpu_pi_put(vcpu);
1316 vmx_prepare_switch_to_host(to_vmx(vcpu));
1319 bool vmx_emulation_required(struct kvm_vcpu *vcpu)
1321 return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu);
1324 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1326 struct vcpu_vmx *vmx = to_vmx(vcpu);
1327 unsigned long rflags, save_rflags;
1329 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1330 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1331 rflags = vmcs_readl(GUEST_RFLAGS);
1332 if (vmx->rmode.vm86_active) {
1333 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1334 save_rflags = vmx->rmode.save_rflags;
1335 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1337 vmx->rflags = rflags;
1342 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1344 struct vcpu_vmx *vmx = to_vmx(vcpu);
1345 unsigned long old_rflags;
1347 if (is_unrestricted_guest(vcpu)) {
1348 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1349 vmx->rflags = rflags;
1350 vmcs_writel(GUEST_RFLAGS, rflags);
1354 old_rflags = vmx_get_rflags(vcpu);
1355 vmx->rflags = rflags;
1356 if (vmx->rmode.vm86_active) {
1357 vmx->rmode.save_rflags = rflags;
1358 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1360 vmcs_writel(GUEST_RFLAGS, rflags);
1362 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1363 vmx->emulation_required = vmx_emulation_required(vcpu);
1366 static bool vmx_get_if_flag(struct kvm_vcpu *vcpu)
1368 return vmx_get_rflags(vcpu) & X86_EFLAGS_IF;
1371 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1373 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1376 if (interruptibility & GUEST_INTR_STATE_STI)
1377 ret |= KVM_X86_SHADOW_INT_STI;
1378 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1379 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1384 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1386 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1387 u32 interruptibility = interruptibility_old;
1389 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1391 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1392 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1393 else if (mask & KVM_X86_SHADOW_INT_STI)
1394 interruptibility |= GUEST_INTR_STATE_STI;
1396 if ((interruptibility != interruptibility_old))
1397 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1400 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1402 struct vcpu_vmx *vmx = to_vmx(vcpu);
1403 unsigned long value;
1406 * Any MSR write that attempts to change bits marked reserved will
1409 if (data & vmx->pt_desc.ctl_bitmask)
1413 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1414 * result in a #GP unless the same write also clears TraceEn.
1416 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1417 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1421 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1422 * and FabricEn would cause #GP, if
1423 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1425 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1426 !(data & RTIT_CTL_FABRIC_EN) &&
1427 !intel_pt_validate_cap(vmx->pt_desc.caps,
1428 PT_CAP_single_range_output))
1432 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1433 * utilize encodings marked reserved will cause a #GP fault.
1435 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1436 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1437 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1438 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1440 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1441 PT_CAP_cycle_thresholds);
1442 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1443 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1444 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1446 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1447 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1448 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1449 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1453 * If ADDRx_CFG is reserved or the encodings is >2 will
1454 * cause a #GP fault.
1456 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1457 if ((value && (vmx->pt_desc.num_address_ranges < 1)) || (value > 2))
1459 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1460 if ((value && (vmx->pt_desc.num_address_ranges < 2)) || (value > 2))
1462 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1463 if ((value && (vmx->pt_desc.num_address_ranges < 3)) || (value > 2))
1465 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1466 if ((value && (vmx->pt_desc.num_address_ranges < 4)) || (value > 2))
1472 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
1475 * Emulation of instructions in SGX enclaves is impossible as RIP does
1476 * not point tthe failing instruction, and even if it did, the code
1477 * stream is inaccessible. Inject #UD instead of exiting to userspace
1478 * so that guest userspace can't DoS the guest simply by triggering
1479 * emulation (enclaves are CPL3 only).
1481 if (to_vmx(vcpu)->exit_reason.enclave_mode) {
1482 kvm_queue_exception(vcpu, UD_VECTOR);
1488 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1490 union vmx_exit_reason exit_reason = to_vmx(vcpu)->exit_reason;
1491 unsigned long rip, orig_rip;
1495 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1496 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1497 * set when EPT misconfig occurs. In practice, real hardware updates
1498 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1499 * (namely Hyper-V) don't set it due to it being undefined behavior,
1500 * i.e. we end up advancing IP with some random value.
1502 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1503 exit_reason.basic != EXIT_REASON_EPT_MISCONFIG) {
1504 instr_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1507 * Emulating an enclave's instructions isn't supported as KVM
1508 * cannot access the enclave's memory or its true RIP, e.g. the
1509 * vmcs.GUEST_RIP points at the exit point of the enclave, not
1510 * the RIP that actually triggered the VM-Exit. But, because
1511 * most instructions that cause VM-Exit will #UD in an enclave,
1512 * most instruction-based VM-Exits simply do not occur.
1514 * There are a few exceptions, notably the debug instructions
1515 * INT1ICEBRK and INT3, as they are allowed in debug enclaves
1516 * and generate #DB/#BP as expected, which KVM might intercept.
1517 * But again, the CPU does the dirty work and saves an instr
1518 * length of zero so VMMs don't shoot themselves in the foot.
1519 * WARN if KVM tries to skip a non-zero length instruction on
1520 * a VM-Exit from an enclave.
1525 WARN(exit_reason.enclave_mode,
1526 "KVM: skipping instruction after SGX enclave VM-Exit");
1528 orig_rip = kvm_rip_read(vcpu);
1529 rip = orig_rip + instr_len;
1530 #ifdef CONFIG_X86_64
1532 * We need to mask out the high 32 bits of RIP if not in 64-bit
1533 * mode, but just finding out that we are in 64-bit mode is
1534 * quite expensive. Only do it if there was a carry.
1536 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1539 kvm_rip_write(vcpu, rip);
1541 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1546 /* skipping an emulated instruction also counts */
1547 vmx_set_interrupt_shadow(vcpu, 0);
1553 * Recognizes a pending MTF VM-exit and records the nested state for later
1556 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1558 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1559 struct vcpu_vmx *vmx = to_vmx(vcpu);
1561 if (!is_guest_mode(vcpu))
1565 * Per the SDM, MTF takes priority over debug-trap exceptions besides
1566 * T-bit traps. As instruction emulation is completed (i.e. at the
1567 * instruction boundary), any #DB exception pending delivery must be a
1568 * debug-trap. Record the pending MTF state to be delivered in
1569 * vmx_check_nested_events().
1571 if (nested_cpu_has_mtf(vmcs12) &&
1572 (!vcpu->arch.exception.pending ||
1573 vcpu->arch.exception.nr == DB_VECTOR))
1574 vmx->nested.mtf_pending = true;
1576 vmx->nested.mtf_pending = false;
1579 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1581 vmx_update_emulated_instruction(vcpu);
1582 return skip_emulated_instruction(vcpu);
1585 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1588 * Ensure that we clear the HLT state in the VMCS. We don't need to
1589 * explicitly skip the instruction because if the HLT state is set,
1590 * then the instruction is already executing and RIP has already been
1593 if (kvm_hlt_in_guest(vcpu->kvm) &&
1594 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1595 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1598 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1600 struct vcpu_vmx *vmx = to_vmx(vcpu);
1601 unsigned nr = vcpu->arch.exception.nr;
1602 bool has_error_code = vcpu->arch.exception.has_error_code;
1603 u32 error_code = vcpu->arch.exception.error_code;
1604 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1606 kvm_deliver_exception_payload(vcpu);
1608 if (has_error_code) {
1609 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1610 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1613 if (vmx->rmode.vm86_active) {
1615 if (kvm_exception_is_soft(nr))
1616 inc_eip = vcpu->arch.event_exit_inst_len;
1617 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1621 WARN_ON_ONCE(vmx->emulation_required);
1623 if (kvm_exception_is_soft(nr)) {
1624 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1625 vmx->vcpu.arch.event_exit_inst_len);
1626 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1628 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1630 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1632 vmx_clear_hlt(vcpu);
1635 static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr,
1636 bool load_into_hardware)
1638 struct vmx_uret_msr *uret_msr;
1640 uret_msr = vmx_find_uret_msr(vmx, msr);
1644 uret_msr->load_into_hardware = load_into_hardware;
1648 * Configuring user return MSRs to automatically save, load, and restore MSRs
1649 * that need to be shoved into hardware when running the guest. Note, omitting
1650 * an MSR here does _NOT_ mean it's not emulated, only that it will not be
1651 * loaded into hardware when running the guest.
1653 static void vmx_setup_uret_msrs(struct vcpu_vmx *vmx)
1655 #ifdef CONFIG_X86_64
1656 bool load_syscall_msrs;
1659 * The SYSCALL MSRs are only needed on long mode guests, and only
1660 * when EFER.SCE is set.
1662 load_syscall_msrs = is_long_mode(&vmx->vcpu) &&
1663 (vmx->vcpu.arch.efer & EFER_SCE);
1665 vmx_setup_uret_msr(vmx, MSR_STAR, load_syscall_msrs);
1666 vmx_setup_uret_msr(vmx, MSR_LSTAR, load_syscall_msrs);
1667 vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK, load_syscall_msrs);
1669 vmx_setup_uret_msr(vmx, MSR_EFER, update_transition_efer(vmx));
1671 vmx_setup_uret_msr(vmx, MSR_TSC_AUX,
1672 guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP) ||
1673 guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDPID));
1676 * hle=0, rtm=0, tsx_ctrl=1 can be found with some combinations of new
1677 * kernel and old userspace. If those guests run on a tsx=off host, do
1678 * allow guests to use TSX_CTRL, but don't change the value in hardware
1679 * so that TSX remains always disabled.
1681 vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL, boot_cpu_has(X86_FEATURE_RTM));
1684 * The set of MSRs to load may have changed, reload MSRs before the
1687 vmx->guest_uret_msrs_loaded = false;
1690 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1692 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1694 if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING))
1695 return vmcs12->tsc_offset;
1700 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1702 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1704 if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING) &&
1705 nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
1706 return vmcs12->tsc_multiplier;
1708 return kvm_default_tsc_scaling_ratio;
1711 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1713 vmcs_write64(TSC_OFFSET, offset);
1716 static void vmx_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1718 vmcs_write64(TSC_MULTIPLIER, multiplier);
1722 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1723 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1724 * all guests if the "nested" module option is off, and can also be disabled
1725 * for a single guest by disabling its VMX cpuid bit.
1727 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1729 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1732 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1735 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1737 return !(val & ~valid_bits);
1740 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1742 switch (msr->index) {
1743 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1746 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1747 case MSR_IA32_PERF_CAPABILITIES:
1748 msr->data = vmx_get_perf_capabilities();
1751 return KVM_MSR_RET_INVALID;
1756 * Reads an msr value (of 'msr_index') into 'pdata'.
1757 * Returns 0 on success, non-0 otherwise.
1758 * Assumes vcpu_load() was already called.
1760 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1762 struct vcpu_vmx *vmx = to_vmx(vcpu);
1763 struct vmx_uret_msr *msr;
1766 switch (msr_info->index) {
1767 #ifdef CONFIG_X86_64
1769 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1772 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1774 case MSR_KERNEL_GS_BASE:
1775 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1779 return kvm_get_msr_common(vcpu, msr_info);
1780 case MSR_IA32_TSX_CTRL:
1781 if (!msr_info->host_initiated &&
1782 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1785 case MSR_IA32_UMWAIT_CONTROL:
1786 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1789 msr_info->data = vmx->msr_ia32_umwait_control;
1791 case MSR_IA32_SPEC_CTRL:
1792 if (!msr_info->host_initiated &&
1793 !guest_has_spec_ctrl_msr(vcpu))
1796 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1798 case MSR_IA32_SYSENTER_CS:
1799 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1801 case MSR_IA32_SYSENTER_EIP:
1802 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1804 case MSR_IA32_SYSENTER_ESP:
1805 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1807 case MSR_IA32_BNDCFGS:
1808 if (!kvm_mpx_supported() ||
1809 (!msr_info->host_initiated &&
1810 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1812 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1814 case MSR_IA32_MCG_EXT_CTL:
1815 if (!msr_info->host_initiated &&
1816 !(vmx->msr_ia32_feature_control &
1817 FEAT_CTL_LMCE_ENABLED))
1819 msr_info->data = vcpu->arch.mcg_ext_ctl;
1821 case MSR_IA32_FEAT_CTL:
1822 msr_info->data = vmx->msr_ia32_feature_control;
1824 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
1825 if (!msr_info->host_initiated &&
1826 !guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
1828 msr_info->data = to_vmx(vcpu)->msr_ia32_sgxlepubkeyhash
1829 [msr_info->index - MSR_IA32_SGXLEPUBKEYHASH0];
1831 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1832 if (!nested_vmx_allowed(vcpu))
1834 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1838 * Enlightened VMCS v1 doesn't have certain VMCS fields but
1839 * instead of just ignoring the features, different Hyper-V
1840 * versions are either trying to use them and fail or do some
1841 * sanity checking and refuse to boot. Filter all unsupported
1844 if (!msr_info->host_initiated &&
1845 vmx->nested.enlightened_vmcs_enabled)
1846 nested_evmcs_filter_control_msr(msr_info->index,
1849 case MSR_IA32_RTIT_CTL:
1850 if (!vmx_pt_mode_is_host_guest())
1852 msr_info->data = vmx->pt_desc.guest.ctl;
1854 case MSR_IA32_RTIT_STATUS:
1855 if (!vmx_pt_mode_is_host_guest())
1857 msr_info->data = vmx->pt_desc.guest.status;
1859 case MSR_IA32_RTIT_CR3_MATCH:
1860 if (!vmx_pt_mode_is_host_guest() ||
1861 !intel_pt_validate_cap(vmx->pt_desc.caps,
1862 PT_CAP_cr3_filtering))
1864 msr_info->data = vmx->pt_desc.guest.cr3_match;
1866 case MSR_IA32_RTIT_OUTPUT_BASE:
1867 if (!vmx_pt_mode_is_host_guest() ||
1868 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1869 PT_CAP_topa_output) &&
1870 !intel_pt_validate_cap(vmx->pt_desc.caps,
1871 PT_CAP_single_range_output)))
1873 msr_info->data = vmx->pt_desc.guest.output_base;
1875 case MSR_IA32_RTIT_OUTPUT_MASK:
1876 if (!vmx_pt_mode_is_host_guest() ||
1877 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1878 PT_CAP_topa_output) &&
1879 !intel_pt_validate_cap(vmx->pt_desc.caps,
1880 PT_CAP_single_range_output)))
1882 msr_info->data = vmx->pt_desc.guest.output_mask;
1884 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1885 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1886 if (!vmx_pt_mode_is_host_guest() ||
1887 (index >= 2 * vmx->pt_desc.num_address_ranges))
1890 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1892 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1894 case MSR_IA32_DEBUGCTLMSR:
1895 msr_info->data = vmcs_read64(GUEST_IA32_DEBUGCTL);
1899 msr = vmx_find_uret_msr(vmx, msr_info->index);
1901 msr_info->data = msr->data;
1904 return kvm_get_msr_common(vcpu, msr_info);
1910 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1913 #ifdef CONFIG_X86_64
1914 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1917 return (unsigned long)data;
1920 static u64 vcpu_supported_debugctl(struct kvm_vcpu *vcpu)
1922 u64 debugctl = vmx_supported_debugctl();
1924 if (!intel_pmu_lbr_is_enabled(vcpu))
1925 debugctl &= ~DEBUGCTLMSR_LBR_MASK;
1927 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1928 debugctl &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1934 * Writes msr value into the appropriate "register".
1935 * Returns 0 on success, non-0 otherwise.
1936 * Assumes vcpu_load() was already called.
1938 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1940 struct vcpu_vmx *vmx = to_vmx(vcpu);
1941 struct vmx_uret_msr *msr;
1943 u32 msr_index = msr_info->index;
1944 u64 data = msr_info->data;
1947 switch (msr_index) {
1949 ret = kvm_set_msr_common(vcpu, msr_info);
1951 #ifdef CONFIG_X86_64
1953 vmx_segment_cache_clear(vmx);
1954 vmcs_writel(GUEST_FS_BASE, data);
1957 vmx_segment_cache_clear(vmx);
1958 vmcs_writel(GUEST_GS_BASE, data);
1960 case MSR_KERNEL_GS_BASE:
1961 vmx_write_guest_kernel_gs_base(vmx, data);
1964 case MSR_IA32_SYSENTER_CS:
1965 if (is_guest_mode(vcpu))
1966 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1967 vmcs_write32(GUEST_SYSENTER_CS, data);
1969 case MSR_IA32_SYSENTER_EIP:
1970 if (is_guest_mode(vcpu)) {
1971 data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1972 get_vmcs12(vcpu)->guest_sysenter_eip = data;
1974 vmcs_writel(GUEST_SYSENTER_EIP, data);
1976 case MSR_IA32_SYSENTER_ESP:
1977 if (is_guest_mode(vcpu)) {
1978 data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1979 get_vmcs12(vcpu)->guest_sysenter_esp = data;
1981 vmcs_writel(GUEST_SYSENTER_ESP, data);
1983 case MSR_IA32_DEBUGCTLMSR: {
1984 u64 invalid = data & ~vcpu_supported_debugctl(vcpu);
1985 if (invalid & (DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR)) {
1986 if (report_ignored_msrs)
1987 vcpu_unimpl(vcpu, "%s: BTF|LBR in IA32_DEBUGCTLMSR 0x%llx, nop\n",
1989 data &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1990 invalid &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1996 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1997 VM_EXIT_SAVE_DEBUG_CONTROLS)
1998 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2000 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
2001 if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event &&
2002 (data & DEBUGCTLMSR_LBR))
2003 intel_pmu_create_guest_lbr_event(vcpu);
2006 case MSR_IA32_BNDCFGS:
2007 if (!kvm_mpx_supported() ||
2008 (!msr_info->host_initiated &&
2009 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2011 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2012 (data & MSR_IA32_BNDCFGS_RSVD))
2014 vmcs_write64(GUEST_BNDCFGS, data);
2016 case MSR_IA32_UMWAIT_CONTROL:
2017 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2020 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2021 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2024 vmx->msr_ia32_umwait_control = data;
2026 case MSR_IA32_SPEC_CTRL:
2027 if (!msr_info->host_initiated &&
2028 !guest_has_spec_ctrl_msr(vcpu))
2031 if (kvm_spec_ctrl_test_value(data))
2034 vmx->spec_ctrl = data;
2040 * When it's written (to non-zero) for the first time, pass
2044 * The handling of the MSR bitmap for L2 guests is done in
2045 * nested_vmx_prepare_msr_bitmap. We should not touch the
2046 * vmcs02.msr_bitmap here since it gets completely overwritten
2047 * in the merging. We update the vmcs01 here for L1 as well
2048 * since it will end up touching the MSR anyway now.
2050 vmx_disable_intercept_for_msr(vcpu,
2054 case MSR_IA32_TSX_CTRL:
2055 if (!msr_info->host_initiated &&
2056 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2058 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2061 case MSR_IA32_PRED_CMD:
2062 if (!msr_info->host_initiated &&
2063 !guest_has_pred_cmd_msr(vcpu))
2066 if (data & ~PRED_CMD_IBPB)
2068 if (!boot_cpu_has(X86_FEATURE_IBPB))
2073 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2077 * When it's written (to non-zero) for the first time, pass
2081 * The handling of the MSR bitmap for L2 guests is done in
2082 * nested_vmx_prepare_msr_bitmap. We should not touch the
2083 * vmcs02.msr_bitmap here since it gets completely overwritten
2086 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
2088 case MSR_IA32_CR_PAT:
2089 if (!kvm_pat_valid(data))
2092 if (is_guest_mode(vcpu) &&
2093 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2094 get_vmcs12(vcpu)->guest_ia32_pat = data;
2096 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2097 vmcs_write64(GUEST_IA32_PAT, data);
2098 vcpu->arch.pat = data;
2101 ret = kvm_set_msr_common(vcpu, msr_info);
2103 case MSR_IA32_TSC_ADJUST:
2104 ret = kvm_set_msr_common(vcpu, msr_info);
2106 case MSR_IA32_MCG_EXT_CTL:
2107 if ((!msr_info->host_initiated &&
2108 !(to_vmx(vcpu)->msr_ia32_feature_control &
2109 FEAT_CTL_LMCE_ENABLED)) ||
2110 (data & ~MCG_EXT_CTL_LMCE_EN))
2112 vcpu->arch.mcg_ext_ctl = data;
2114 case MSR_IA32_FEAT_CTL:
2115 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2116 (to_vmx(vcpu)->msr_ia32_feature_control &
2117 FEAT_CTL_LOCKED && !msr_info->host_initiated))
2119 vmx->msr_ia32_feature_control = data;
2120 if (msr_info->host_initiated && data == 0)
2121 vmx_leave_nested(vcpu);
2123 /* SGX may be enabled/disabled by guest's firmware */
2124 vmx_write_encls_bitmap(vcpu, NULL);
2126 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
2128 * On real hardware, the LE hash MSRs are writable before
2129 * the firmware sets bit 0 in MSR 0x7a ("activating" SGX),
2130 * at which point SGX related bits in IA32_FEATURE_CONTROL
2133 * KVM does not emulate SGX activation for simplicity, so
2134 * allow writes to the LE hash MSRs if IA32_FEATURE_CONTROL
2135 * is unlocked. This is technically not architectural
2136 * behavior, but it's close enough.
2138 if (!msr_info->host_initiated &&
2139 (!guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC) ||
2140 ((vmx->msr_ia32_feature_control & FEAT_CTL_LOCKED) &&
2141 !(vmx->msr_ia32_feature_control & FEAT_CTL_SGX_LC_ENABLED))))
2143 vmx->msr_ia32_sgxlepubkeyhash
2144 [msr_index - MSR_IA32_SGXLEPUBKEYHASH0] = data;
2146 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2147 if (!msr_info->host_initiated)
2148 return 1; /* they are read-only */
2149 if (!nested_vmx_allowed(vcpu))
2151 return vmx_set_vmx_msr(vcpu, msr_index, data);
2152 case MSR_IA32_RTIT_CTL:
2153 if (!vmx_pt_mode_is_host_guest() ||
2154 vmx_rtit_ctl_check(vcpu, data) ||
2157 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2158 vmx->pt_desc.guest.ctl = data;
2159 pt_update_intercept_for_msr(vcpu);
2161 case MSR_IA32_RTIT_STATUS:
2162 if (!pt_can_write_msr(vmx))
2164 if (data & MSR_IA32_RTIT_STATUS_MASK)
2166 vmx->pt_desc.guest.status = data;
2168 case MSR_IA32_RTIT_CR3_MATCH:
2169 if (!pt_can_write_msr(vmx))
2171 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2172 PT_CAP_cr3_filtering))
2174 vmx->pt_desc.guest.cr3_match = data;
2176 case MSR_IA32_RTIT_OUTPUT_BASE:
2177 if (!pt_can_write_msr(vmx))
2179 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2180 PT_CAP_topa_output) &&
2181 !intel_pt_validate_cap(vmx->pt_desc.caps,
2182 PT_CAP_single_range_output))
2184 if (!pt_output_base_valid(vcpu, data))
2186 vmx->pt_desc.guest.output_base = data;
2188 case MSR_IA32_RTIT_OUTPUT_MASK:
2189 if (!pt_can_write_msr(vmx))
2191 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2192 PT_CAP_topa_output) &&
2193 !intel_pt_validate_cap(vmx->pt_desc.caps,
2194 PT_CAP_single_range_output))
2196 vmx->pt_desc.guest.output_mask = data;
2198 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2199 if (!pt_can_write_msr(vmx))
2201 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2202 if (index >= 2 * vmx->pt_desc.num_address_ranges)
2204 if (is_noncanonical_address(data, vcpu))
2207 vmx->pt_desc.guest.addr_b[index / 2] = data;
2209 vmx->pt_desc.guest.addr_a[index / 2] = data;
2211 case MSR_IA32_PERF_CAPABILITIES:
2212 if (data && !vcpu_to_pmu(vcpu)->version)
2214 if (data & PMU_CAP_LBR_FMT) {
2215 if ((data & PMU_CAP_LBR_FMT) !=
2216 (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
2218 if (!intel_pmu_lbr_is_compatible(vcpu))
2221 ret = kvm_set_msr_common(vcpu, msr_info);
2226 msr = vmx_find_uret_msr(vmx, msr_index);
2228 ret = vmx_set_guest_uret_msr(vmx, msr, data);
2230 ret = kvm_set_msr_common(vcpu, msr_info);
2236 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2238 unsigned long guest_owned_bits;
2240 kvm_register_mark_available(vcpu, reg);
2244 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2247 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2249 case VCPU_EXREG_PDPTR:
2251 ept_save_pdptrs(vcpu);
2253 case VCPU_EXREG_CR0:
2254 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2256 vcpu->arch.cr0 &= ~guest_owned_bits;
2257 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2259 case VCPU_EXREG_CR3:
2261 * When intercepting CR3 loads, e.g. for shadowing paging, KVM's
2262 * CR3 is loaded into hardware, not the guest's CR3.
2264 if (!(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_CR3_LOAD_EXITING))
2265 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2267 case VCPU_EXREG_CR4:
2268 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2270 vcpu->arch.cr4 &= ~guest_owned_bits;
2271 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2274 KVM_BUG_ON(1, vcpu->kvm);
2279 static __init int cpu_has_kvm_support(void)
2281 return cpu_has_vmx();
2284 static __init int vmx_disabled_by_bios(void)
2286 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2287 !boot_cpu_has(X86_FEATURE_VMX);
2290 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2294 cr4_set_bits(X86_CR4_VMXE);
2296 asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2297 _ASM_EXTABLE(1b, %l[fault])
2298 : : [vmxon_pointer] "m"(vmxon_pointer)
2303 WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2304 rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2305 cr4_clear_bits(X86_CR4_VMXE);
2310 static int hardware_enable(void)
2312 int cpu = raw_smp_processor_id();
2313 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2316 if (cr4_read_shadow() & X86_CR4_VMXE)
2320 * This can happen if we hot-added a CPU but failed to allocate
2321 * VP assist page for it.
2323 if (static_branch_unlikely(&enable_evmcs) &&
2324 !hv_get_vp_assist_page(cpu))
2327 intel_pt_handle_vmx(1);
2329 r = kvm_cpu_vmxon(phys_addr);
2331 intel_pt_handle_vmx(0);
2341 static void vmclear_local_loaded_vmcss(void)
2343 int cpu = raw_smp_processor_id();
2344 struct loaded_vmcs *v, *n;
2346 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2347 loaded_vmcss_on_cpu_link)
2348 __loaded_vmcs_clear(v);
2351 static void hardware_disable(void)
2353 vmclear_local_loaded_vmcss();
2356 kvm_spurious_fault();
2358 intel_pt_handle_vmx(0);
2362 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2363 * directly instead of going through cpu_has(), to ensure KVM is trapping
2364 * ENCLS whenever it's supported in hardware. It does not matter whether
2365 * the host OS supports or has enabled SGX.
2367 static bool cpu_has_sgx(void)
2369 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2372 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2373 u32 msr, u32 *result)
2375 u32 vmx_msr_low, vmx_msr_high;
2376 u32 ctl = ctl_min | ctl_opt;
2378 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2380 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2381 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2383 /* Ensure minimum (required) set of control bits are supported. */
2391 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2392 struct vmx_capability *vmx_cap)
2394 u32 vmx_msr_low, vmx_msr_high;
2395 u32 min, opt, min2, opt2;
2396 u32 _pin_based_exec_control = 0;
2397 u32 _cpu_based_exec_control = 0;
2398 u32 _cpu_based_2nd_exec_control = 0;
2399 u32 _vmexit_control = 0;
2400 u32 _vmentry_control = 0;
2402 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2403 min = CPU_BASED_HLT_EXITING |
2404 #ifdef CONFIG_X86_64
2405 CPU_BASED_CR8_LOAD_EXITING |
2406 CPU_BASED_CR8_STORE_EXITING |
2408 CPU_BASED_CR3_LOAD_EXITING |
2409 CPU_BASED_CR3_STORE_EXITING |
2410 CPU_BASED_UNCOND_IO_EXITING |
2411 CPU_BASED_MOV_DR_EXITING |
2412 CPU_BASED_USE_TSC_OFFSETTING |
2413 CPU_BASED_MWAIT_EXITING |
2414 CPU_BASED_MONITOR_EXITING |
2415 CPU_BASED_INVLPG_EXITING |
2416 CPU_BASED_RDPMC_EXITING;
2418 opt = CPU_BASED_TPR_SHADOW |
2419 CPU_BASED_USE_MSR_BITMAPS |
2420 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2421 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2422 &_cpu_based_exec_control) < 0)
2424 #ifdef CONFIG_X86_64
2425 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2426 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2427 ~CPU_BASED_CR8_STORE_EXITING;
2429 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2431 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2432 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2433 SECONDARY_EXEC_WBINVD_EXITING |
2434 SECONDARY_EXEC_ENABLE_VPID |
2435 SECONDARY_EXEC_ENABLE_EPT |
2436 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2437 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2438 SECONDARY_EXEC_DESC |
2439 SECONDARY_EXEC_ENABLE_RDTSCP |
2440 SECONDARY_EXEC_ENABLE_INVPCID |
2441 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2442 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2443 SECONDARY_EXEC_SHADOW_VMCS |
2444 SECONDARY_EXEC_XSAVES |
2445 SECONDARY_EXEC_RDSEED_EXITING |
2446 SECONDARY_EXEC_RDRAND_EXITING |
2447 SECONDARY_EXEC_ENABLE_PML |
2448 SECONDARY_EXEC_TSC_SCALING |
2449 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2450 SECONDARY_EXEC_PT_USE_GPA |
2451 SECONDARY_EXEC_PT_CONCEAL_VMX |
2452 SECONDARY_EXEC_ENABLE_VMFUNC |
2453 SECONDARY_EXEC_BUS_LOCK_DETECTION;
2455 opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2456 if (adjust_vmx_controls(min2, opt2,
2457 MSR_IA32_VMX_PROCBASED_CTLS2,
2458 &_cpu_based_2nd_exec_control) < 0)
2461 #ifndef CONFIG_X86_64
2462 if (!(_cpu_based_2nd_exec_control &
2463 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2464 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2467 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2468 _cpu_based_2nd_exec_control &= ~(
2469 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2470 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2471 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2473 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2474 &vmx_cap->ept, &vmx_cap->vpid);
2476 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2477 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2479 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2480 CPU_BASED_CR3_STORE_EXITING |
2481 CPU_BASED_INVLPG_EXITING);
2482 } else if (vmx_cap->ept) {
2484 pr_warn_once("EPT CAP should not exist if not support "
2485 "1-setting enable EPT VM-execution control\n");
2487 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2490 pr_warn_once("VPID CAP should not exist if not support "
2491 "1-setting enable VPID VM-execution control\n");
2494 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2495 #ifdef CONFIG_X86_64
2496 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2498 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2499 VM_EXIT_LOAD_IA32_PAT |
2500 VM_EXIT_LOAD_IA32_EFER |
2501 VM_EXIT_CLEAR_BNDCFGS |
2502 VM_EXIT_PT_CONCEAL_PIP |
2503 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2504 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2505 &_vmexit_control) < 0)
2508 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2509 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2510 PIN_BASED_VMX_PREEMPTION_TIMER;
2511 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2512 &_pin_based_exec_control) < 0)
2515 if (cpu_has_broken_vmx_preemption_timer())
2516 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2517 if (!(_cpu_based_2nd_exec_control &
2518 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2519 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2521 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2522 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2523 VM_ENTRY_LOAD_IA32_PAT |
2524 VM_ENTRY_LOAD_IA32_EFER |
2525 VM_ENTRY_LOAD_BNDCFGS |
2526 VM_ENTRY_PT_CONCEAL_PIP |
2527 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2528 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2529 &_vmentry_control) < 0)
2533 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2534 * can't be used due to an errata where VM Exit may incorrectly clear
2535 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2536 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2538 if (boot_cpu_data.x86 == 0x6) {
2539 switch (boot_cpu_data.x86_model) {
2540 case 26: /* AAK155 */
2541 case 30: /* AAP115 */
2542 case 37: /* AAT100 */
2543 case 44: /* BC86,AAY89,BD102 */
2545 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2546 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2547 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2548 "does not work properly. Using workaround\n");
2556 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2558 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2559 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2562 #ifdef CONFIG_X86_64
2563 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2564 if (vmx_msr_high & (1u<<16))
2568 /* Require Write-Back (WB) memory type for VMCS accesses. */
2569 if (((vmx_msr_high >> 18) & 15) != 6)
2572 vmcs_conf->size = vmx_msr_high & 0x1fff;
2573 vmcs_conf->order = get_order(vmcs_conf->size);
2574 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2576 vmcs_conf->revision_id = vmx_msr_low;
2578 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2579 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2580 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2581 vmcs_conf->vmexit_ctrl = _vmexit_control;
2582 vmcs_conf->vmentry_ctrl = _vmentry_control;
2584 #if IS_ENABLED(CONFIG_HYPERV)
2585 if (enlightened_vmcs)
2586 evmcs_sanitize_exec_ctrls(vmcs_conf);
2592 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2594 int node = cpu_to_node(cpu);
2598 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2601 vmcs = page_address(pages);
2602 memset(vmcs, 0, vmcs_config.size);
2604 /* KVM supports Enlightened VMCS v1 only */
2605 if (static_branch_unlikely(&enable_evmcs))
2606 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2608 vmcs->hdr.revision_id = vmcs_config.revision_id;
2611 vmcs->hdr.shadow_vmcs = 1;
2615 void free_vmcs(struct vmcs *vmcs)
2617 free_pages((unsigned long)vmcs, vmcs_config.order);
2621 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2623 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2625 if (!loaded_vmcs->vmcs)
2627 loaded_vmcs_clear(loaded_vmcs);
2628 free_vmcs(loaded_vmcs->vmcs);
2629 loaded_vmcs->vmcs = NULL;
2630 if (loaded_vmcs->msr_bitmap)
2631 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2632 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2635 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2637 loaded_vmcs->vmcs = alloc_vmcs(false);
2638 if (!loaded_vmcs->vmcs)
2641 vmcs_clear(loaded_vmcs->vmcs);
2643 loaded_vmcs->shadow_vmcs = NULL;
2644 loaded_vmcs->hv_timer_soft_disabled = false;
2645 loaded_vmcs->cpu = -1;
2646 loaded_vmcs->launched = 0;
2648 if (cpu_has_vmx_msr_bitmap()) {
2649 loaded_vmcs->msr_bitmap = (unsigned long *)
2650 __get_free_page(GFP_KERNEL_ACCOUNT);
2651 if (!loaded_vmcs->msr_bitmap)
2653 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2656 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2657 memset(&loaded_vmcs->controls_shadow, 0,
2658 sizeof(struct vmcs_controls_shadow));
2663 free_loaded_vmcs(loaded_vmcs);
2667 static void free_kvm_area(void)
2671 for_each_possible_cpu(cpu) {
2672 free_vmcs(per_cpu(vmxarea, cpu));
2673 per_cpu(vmxarea, cpu) = NULL;
2677 static __init int alloc_kvm_area(void)
2681 for_each_possible_cpu(cpu) {
2684 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2691 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2692 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2693 * revision_id reported by MSR_IA32_VMX_BASIC.
2695 * However, even though not explicitly documented by
2696 * TLFS, VMXArea passed as VMXON argument should
2697 * still be marked with revision_id reported by
2700 if (static_branch_unlikely(&enable_evmcs))
2701 vmcs->hdr.revision_id = vmcs_config.revision_id;
2703 per_cpu(vmxarea, cpu) = vmcs;
2708 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2709 struct kvm_segment *save)
2711 if (!emulate_invalid_guest_state) {
2713 * CS and SS RPL should be equal during guest entry according
2714 * to VMX spec, but in reality it is not always so. Since vcpu
2715 * is in the middle of the transition from real mode to
2716 * protected mode it is safe to assume that RPL 0 is a good
2719 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2720 save->selector &= ~SEGMENT_RPL_MASK;
2721 save->dpl = save->selector & SEGMENT_RPL_MASK;
2724 __vmx_set_segment(vcpu, save, seg);
2727 static void enter_pmode(struct kvm_vcpu *vcpu)
2729 unsigned long flags;
2730 struct vcpu_vmx *vmx = to_vmx(vcpu);
2733 * Update real mode segment cache. It may be not up-to-date if segment
2734 * register was written while vcpu was in a guest mode.
2736 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2737 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2738 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2739 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2740 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2741 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2743 vmx->rmode.vm86_active = 0;
2745 __vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2747 flags = vmcs_readl(GUEST_RFLAGS);
2748 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2749 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2750 vmcs_writel(GUEST_RFLAGS, flags);
2752 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2753 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2755 vmx_update_exception_bitmap(vcpu);
2757 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2758 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2759 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2760 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2761 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2762 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2765 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2767 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2768 struct kvm_segment var = *save;
2771 if (seg == VCPU_SREG_CS)
2774 if (!emulate_invalid_guest_state) {
2775 var.selector = var.base >> 4;
2776 var.base = var.base & 0xffff0;
2786 if (save->base & 0xf)
2787 printk_once(KERN_WARNING "kvm: segment base is not "
2788 "paragraph aligned when entering "
2789 "protected mode (seg=%d)", seg);
2792 vmcs_write16(sf->selector, var.selector);
2793 vmcs_writel(sf->base, var.base);
2794 vmcs_write32(sf->limit, var.limit);
2795 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2798 static void enter_rmode(struct kvm_vcpu *vcpu)
2800 unsigned long flags;
2801 struct vcpu_vmx *vmx = to_vmx(vcpu);
2802 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2804 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2805 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2806 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2807 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2808 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2809 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2810 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2812 vmx->rmode.vm86_active = 1;
2815 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2816 * vcpu. Warn the user that an update is overdue.
2818 if (!kvm_vmx->tss_addr)
2819 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2820 "called before entering vcpu\n");
2822 vmx_segment_cache_clear(vmx);
2824 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2825 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2826 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2828 flags = vmcs_readl(GUEST_RFLAGS);
2829 vmx->rmode.save_rflags = flags;
2831 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2833 vmcs_writel(GUEST_RFLAGS, flags);
2834 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2835 vmx_update_exception_bitmap(vcpu);
2837 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2838 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2839 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2840 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2841 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2842 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2845 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2847 struct vcpu_vmx *vmx = to_vmx(vcpu);
2848 struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER);
2850 /* Nothing to do if hardware doesn't support EFER. */
2854 vcpu->arch.efer = efer;
2855 if (efer & EFER_LMA) {
2856 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2859 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2861 msr->data = efer & ~EFER_LME;
2863 vmx_setup_uret_msrs(vmx);
2867 #ifdef CONFIG_X86_64
2869 static void enter_lmode(struct kvm_vcpu *vcpu)
2873 vmx_segment_cache_clear(to_vmx(vcpu));
2875 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2876 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2877 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2879 vmcs_write32(GUEST_TR_AR_BYTES,
2880 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2881 | VMX_AR_TYPE_BUSY_64_TSS);
2883 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2886 static void exit_lmode(struct kvm_vcpu *vcpu)
2888 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2889 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2894 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2896 struct vcpu_vmx *vmx = to_vmx(vcpu);
2899 * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2900 * the CPU is not required to invalidate guest-physical mappings on
2901 * VM-Entry, even if VPID is disabled. Guest-physical mappings are
2902 * associated with the root EPT structure and not any particular VPID
2903 * (INVVPID also isn't required to invalidate guest-physical mappings).
2907 } else if (enable_vpid) {
2908 if (cpu_has_vmx_invvpid_global()) {
2909 vpid_sync_vcpu_global();
2911 vpid_sync_vcpu_single(vmx->vpid);
2912 vpid_sync_vcpu_single(vmx->nested.vpid02);
2917 static inline int vmx_get_current_vpid(struct kvm_vcpu *vcpu)
2919 if (is_guest_mode(vcpu))
2920 return nested_get_vpid02(vcpu);
2921 return to_vmx(vcpu)->vpid;
2924 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2926 struct kvm_mmu *mmu = vcpu->arch.mmu;
2927 u64 root_hpa = mmu->root_hpa;
2929 /* No flush required if the current context is invalid. */
2930 if (!VALID_PAGE(root_hpa))
2934 ept_sync_context(construct_eptp(vcpu, root_hpa,
2935 mmu->shadow_root_level));
2937 vpid_sync_context(vmx_get_current_vpid(vcpu));
2940 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2943 * vpid_sync_vcpu_addr() is a nop if vpid==0, see the comment in
2944 * vmx_flush_tlb_guest() for an explanation of why this is ok.
2946 vpid_sync_vcpu_addr(vmx_get_current_vpid(vcpu), addr);
2949 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2952 * vpid_sync_context() is a nop if vpid==0, e.g. if enable_vpid==0 or a
2953 * vpid couldn't be allocated for this vCPU. VM-Enter and VM-Exit are
2954 * required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2955 * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2956 * i.e. no explicit INVVPID is necessary.
2958 vpid_sync_context(vmx_get_current_vpid(vcpu));
2961 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2963 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2965 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2968 if (is_pae_paging(vcpu)) {
2969 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2970 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2971 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2972 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2976 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2978 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2980 if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2983 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2984 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2985 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2986 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2988 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2991 #define CR3_EXITING_BITS (CPU_BASED_CR3_LOAD_EXITING | \
2992 CPU_BASED_CR3_STORE_EXITING)
2994 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2996 struct vcpu_vmx *vmx = to_vmx(vcpu);
2997 unsigned long hw_cr0, old_cr0_pg;
3000 old_cr0_pg = kvm_read_cr0_bits(vcpu, X86_CR0_PG);
3002 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3003 if (is_unrestricted_guest(vcpu))
3004 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3006 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3008 hw_cr0 |= X86_CR0_WP;
3010 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3013 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3017 vmcs_writel(CR0_READ_SHADOW, cr0);
3018 vmcs_writel(GUEST_CR0, hw_cr0);
3019 vcpu->arch.cr0 = cr0;
3020 kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3022 #ifdef CONFIG_X86_64
3023 if (vcpu->arch.efer & EFER_LME) {
3024 if (!old_cr0_pg && (cr0 & X86_CR0_PG))
3026 else if (old_cr0_pg && !(cr0 & X86_CR0_PG))
3031 if (enable_ept && !is_unrestricted_guest(vcpu)) {
3033 * Ensure KVM has an up-to-date snapshot of the guest's CR3. If
3034 * the below code _enables_ CR3 exiting, vmx_cache_reg() will
3035 * (correctly) stop reading vmcs.GUEST_CR3 because it thinks
3036 * KVM's CR3 is installed.
3038 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
3039 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
3042 * When running with EPT but not unrestricted guest, KVM must
3043 * intercept CR3 accesses when paging is _disabled_. This is
3044 * necessary because restricted guests can't actually run with
3045 * paging disabled, and so KVM stuffs its own CR3 in order to
3046 * run the guest when identity mapped page tables.
3048 * Do _NOT_ check the old CR0.PG, e.g. to optimize away the
3049 * update, it may be stale with respect to CR3 interception,
3050 * e.g. after nested VM-Enter.
3052 * Lastly, honor L1's desires, i.e. intercept CR3 loads and/or
3053 * stores to forward them to L1, even if KVM does not need to
3054 * intercept them to preserve its identity mapped page tables.
3056 if (!(cr0 & X86_CR0_PG)) {
3057 exec_controls_setbit(vmx, CR3_EXITING_BITS);
3058 } else if (!is_guest_mode(vcpu)) {
3059 exec_controls_clearbit(vmx, CR3_EXITING_BITS);
3061 tmp = exec_controls_get(vmx);
3062 tmp &= ~CR3_EXITING_BITS;
3063 tmp |= get_vmcs12(vcpu)->cpu_based_vm_exec_control & CR3_EXITING_BITS;
3064 exec_controls_set(vmx, tmp);
3067 /* Note, vmx_set_cr4() consumes the new vcpu->arch.cr0. */
3068 if ((old_cr0_pg ^ cr0) & X86_CR0_PG)
3069 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3072 /* depends on vcpu->arch.cr0 to be set to a new value */
3073 vmx->emulation_required = vmx_emulation_required(vcpu);
3076 static int vmx_get_max_tdp_level(void)
3078 if (cpu_has_vmx_ept_5levels())
3083 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level)
3085 u64 eptp = VMX_EPTP_MT_WB;
3087 eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3089 if (enable_ept_ad_bits &&
3090 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3091 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3097 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3100 struct kvm *kvm = vcpu->kvm;
3101 bool update_guest_cr3 = true;
3102 unsigned long guest_cr3;
3106 eptp = construct_eptp(vcpu, root_hpa, root_level);
3107 vmcs_write64(EPT_POINTER, eptp);
3109 hv_track_root_tdp(vcpu, root_hpa);
3111 if (!enable_unrestricted_guest && !is_paging(vcpu))
3112 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3113 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3114 guest_cr3 = vcpu->arch.cr3;
3115 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3116 update_guest_cr3 = false;
3117 vmx_ept_load_pdptrs(vcpu);
3119 guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu);
3122 if (update_guest_cr3)
3123 vmcs_writel(GUEST_CR3, guest_cr3);
3126 static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3129 * We operate under the default treatment of SMM, so VMX cannot be
3130 * enabled under SMM. Note, whether or not VMXE is allowed at all is
3131 * handled by kvm_is_valid_cr4().
3133 if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu))
3136 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3142 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3144 unsigned long old_cr4 = vcpu->arch.cr4;
3145 struct vcpu_vmx *vmx = to_vmx(vcpu);
3147 * Pass through host's Machine Check Enable value to hw_cr4, which
3148 * is in force while we are in guest mode. Do not let guests control
3149 * this bit, even if host CR4.MCE == 0.
3151 unsigned long hw_cr4;
3153 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3154 if (is_unrestricted_guest(vcpu))
3155 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3156 else if (vmx->rmode.vm86_active)
3157 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3159 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3161 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3162 if (cr4 & X86_CR4_UMIP) {
3163 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3164 hw_cr4 &= ~X86_CR4_UMIP;
3165 } else if (!is_guest_mode(vcpu) ||
3166 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3167 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3171 vcpu->arch.cr4 = cr4;
3172 kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3174 if (!is_unrestricted_guest(vcpu)) {
3176 if (!is_paging(vcpu)) {
3177 hw_cr4 &= ~X86_CR4_PAE;
3178 hw_cr4 |= X86_CR4_PSE;
3179 } else if (!(cr4 & X86_CR4_PAE)) {
3180 hw_cr4 &= ~X86_CR4_PAE;
3185 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3186 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3187 * to be manually disabled when guest switches to non-paging
3190 * If !enable_unrestricted_guest, the CPU is always running
3191 * with CR0.PG=1 and CR4 needs to be modified.
3192 * If enable_unrestricted_guest, the CPU automatically
3193 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3195 if (!is_paging(vcpu))
3196 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3199 vmcs_writel(CR4_READ_SHADOW, cr4);
3200 vmcs_writel(GUEST_CR4, hw_cr4);
3202 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
3203 kvm_update_cpuid_runtime(vcpu);
3206 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3208 struct vcpu_vmx *vmx = to_vmx(vcpu);
3211 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3212 *var = vmx->rmode.segs[seg];
3213 if (seg == VCPU_SREG_TR
3214 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3216 var->base = vmx_read_guest_seg_base(vmx, seg);
3217 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3220 var->base = vmx_read_guest_seg_base(vmx, seg);
3221 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3222 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3223 ar = vmx_read_guest_seg_ar(vmx, seg);
3224 var->unusable = (ar >> 16) & 1;
3225 var->type = ar & 15;
3226 var->s = (ar >> 4) & 1;
3227 var->dpl = (ar >> 5) & 3;
3229 * Some userspaces do not preserve unusable property. Since usable
3230 * segment has to be present according to VMX spec we can use present
3231 * property to amend userspace bug by making unusable segment always
3232 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3233 * segment as unusable.
3235 var->present = !var->unusable;
3236 var->avl = (ar >> 12) & 1;
3237 var->l = (ar >> 13) & 1;
3238 var->db = (ar >> 14) & 1;
3239 var->g = (ar >> 15) & 1;
3242 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3244 struct kvm_segment s;
3246 if (to_vmx(vcpu)->rmode.vm86_active) {
3247 vmx_get_segment(vcpu, &s, seg);
3250 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3253 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3255 struct vcpu_vmx *vmx = to_vmx(vcpu);
3257 if (unlikely(vmx->rmode.vm86_active))
3260 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3261 return VMX_AR_DPL(ar);
3265 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3269 if (var->unusable || !var->present)
3272 ar = var->type & 15;
3273 ar |= (var->s & 1) << 4;
3274 ar |= (var->dpl & 3) << 5;
3275 ar |= (var->present & 1) << 7;
3276 ar |= (var->avl & 1) << 12;
3277 ar |= (var->l & 1) << 13;
3278 ar |= (var->db & 1) << 14;
3279 ar |= (var->g & 1) << 15;
3285 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3287 struct vcpu_vmx *vmx = to_vmx(vcpu);
3288 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3290 vmx_segment_cache_clear(vmx);
3292 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3293 vmx->rmode.segs[seg] = *var;
3294 if (seg == VCPU_SREG_TR)
3295 vmcs_write16(sf->selector, var->selector);
3297 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3301 vmcs_writel(sf->base, var->base);
3302 vmcs_write32(sf->limit, var->limit);
3303 vmcs_write16(sf->selector, var->selector);
3306 * Fix the "Accessed" bit in AR field of segment registers for older
3308 * IA32 arch specifies that at the time of processor reset the
3309 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3310 * is setting it to 0 in the userland code. This causes invalid guest
3311 * state vmexit when "unrestricted guest" mode is turned on.
3312 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3313 * tree. Newer qemu binaries with that qemu fix would not need this
3316 if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3317 var->type |= 0x1; /* Accessed */
3319 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3322 static void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3324 __vmx_set_segment(vcpu, var, seg);
3326 to_vmx(vcpu)->emulation_required = vmx_emulation_required(vcpu);
3329 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3331 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3333 *db = (ar >> 14) & 1;
3334 *l = (ar >> 13) & 1;
3337 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3339 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3340 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3343 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3345 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3346 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3349 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3351 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3352 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3355 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3357 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3358 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3361 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3363 struct kvm_segment var;
3366 vmx_get_segment(vcpu, &var, seg);
3368 if (seg == VCPU_SREG_CS)
3370 ar = vmx_segment_access_rights(&var);
3372 if (var.base != (var.selector << 4))
3374 if (var.limit != 0xffff)
3382 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3384 struct kvm_segment cs;
3385 unsigned int cs_rpl;
3387 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3388 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3392 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3396 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3397 if (cs.dpl > cs_rpl)
3400 if (cs.dpl != cs_rpl)
3406 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3410 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3412 struct kvm_segment ss;
3413 unsigned int ss_rpl;
3415 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3416 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3420 if (ss.type != 3 && ss.type != 7)
3424 if (ss.dpl != ss_rpl) /* DPL != RPL */
3432 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3434 struct kvm_segment var;
3437 vmx_get_segment(vcpu, &var, seg);
3438 rpl = var.selector & SEGMENT_RPL_MASK;
3446 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3447 if (var.dpl < rpl) /* DPL < RPL */
3451 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3457 static bool tr_valid(struct kvm_vcpu *vcpu)
3459 struct kvm_segment tr;
3461 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3465 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3467 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3475 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3477 struct kvm_segment ldtr;
3479 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3483 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3493 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3495 struct kvm_segment cs, ss;
3497 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3498 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3500 return ((cs.selector & SEGMENT_RPL_MASK) ==
3501 (ss.selector & SEGMENT_RPL_MASK));
3505 * Check if guest state is valid. Returns true if valid, false if
3507 * We assume that registers are always usable
3509 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu)
3511 /* real mode guest state checks */
3512 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3513 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3515 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3517 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3519 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3521 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3523 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3526 /* protected mode guest state checks */
3527 if (!cs_ss_rpl_check(vcpu))
3529 if (!code_segment_valid(vcpu))
3531 if (!stack_segment_valid(vcpu))
3533 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3535 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3537 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3539 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3541 if (!tr_valid(vcpu))
3543 if (!ldtr_valid(vcpu))
3547 * - Add checks on RIP
3548 * - Add checks on RFLAGS
3554 static int init_rmode_tss(struct kvm *kvm, void __user *ua)
3556 const void *zero_page = (const void *) __va(page_to_phys(ZERO_PAGE(0)));
3560 for (i = 0; i < 3; i++) {
3561 if (__copy_to_user(ua + PAGE_SIZE * i, zero_page, PAGE_SIZE))
3565 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3566 if (__copy_to_user(ua + TSS_IOPB_BASE_OFFSET, &data, sizeof(u16)))
3570 if (__copy_to_user(ua + RMODE_TSS_SIZE - 1, &data, sizeof(u8)))
3576 static int init_rmode_identity_map(struct kvm *kvm)
3578 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3583 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3584 mutex_lock(&kvm->slots_lock);
3586 if (likely(kvm_vmx->ept_identity_pagetable_done))
3589 if (!kvm_vmx->ept_identity_map_addr)
3590 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3592 uaddr = __x86_set_memory_region(kvm,
3593 IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3594 kvm_vmx->ept_identity_map_addr,
3596 if (IS_ERR(uaddr)) {
3601 /* Set up identity-mapping pagetable for EPT in real mode */
3602 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3603 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3604 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3605 if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) {
3610 kvm_vmx->ept_identity_pagetable_done = true;
3613 mutex_unlock(&kvm->slots_lock);
3617 static void seg_setup(int seg)
3619 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3622 vmcs_write16(sf->selector, 0);
3623 vmcs_writel(sf->base, 0);
3624 vmcs_write32(sf->limit, 0xffff);
3626 if (seg == VCPU_SREG_CS)
3627 ar |= 0x08; /* code segment */
3629 vmcs_write32(sf->ar_bytes, ar);
3632 static int alloc_apic_access_page(struct kvm *kvm)
3638 mutex_lock(&kvm->slots_lock);
3639 if (kvm->arch.apic_access_memslot_enabled)
3641 hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3642 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3648 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3649 if (is_error_page(page)) {
3655 * Do not pin the page in memory, so that memory hot-unplug
3656 * is able to migrate it.
3659 kvm->arch.apic_access_memslot_enabled = true;
3661 mutex_unlock(&kvm->slots_lock);
3665 int allocate_vpid(void)
3671 spin_lock(&vmx_vpid_lock);
3672 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3673 if (vpid < VMX_NR_VPIDS)
3674 __set_bit(vpid, vmx_vpid_bitmap);
3677 spin_unlock(&vmx_vpid_lock);
3681 void free_vpid(int vpid)
3683 if (!enable_vpid || vpid == 0)
3685 spin_lock(&vmx_vpid_lock);
3686 __clear_bit(vpid, vmx_vpid_bitmap);
3687 spin_unlock(&vmx_vpid_lock);
3690 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3692 struct vcpu_vmx *vmx = to_vmx(vcpu);
3693 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3695 if (!cpu_has_vmx_msr_bitmap())
3698 if (static_branch_unlikely(&enable_evmcs))
3699 evmcs_touch_msr_bitmap();
3702 * Mark the desired intercept state in shadow bitmap, this is needed
3703 * for resync when the MSR filters change.
3705 if (is_valid_passthrough_msr(msr)) {
3706 int idx = possible_passthrough_msr_slot(msr);
3708 if (idx != -ENOENT) {
3709 if (type & MSR_TYPE_R)
3710 clear_bit(idx, vmx->shadow_msr_intercept.read);
3711 if (type & MSR_TYPE_W)
3712 clear_bit(idx, vmx->shadow_msr_intercept.write);
3716 if ((type & MSR_TYPE_R) &&
3717 !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) {
3718 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3719 type &= ~MSR_TYPE_R;
3722 if ((type & MSR_TYPE_W) &&
3723 !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) {
3724 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3725 type &= ~MSR_TYPE_W;
3728 if (type & MSR_TYPE_R)
3729 vmx_clear_msr_bitmap_read(msr_bitmap, msr);
3731 if (type & MSR_TYPE_W)
3732 vmx_clear_msr_bitmap_write(msr_bitmap, msr);
3735 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3737 struct vcpu_vmx *vmx = to_vmx(vcpu);
3738 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3740 if (!cpu_has_vmx_msr_bitmap())
3743 if (static_branch_unlikely(&enable_evmcs))
3744 evmcs_touch_msr_bitmap();
3747 * Mark the desired intercept state in shadow bitmap, this is needed
3748 * for resync when the MSR filter changes.
3750 if (is_valid_passthrough_msr(msr)) {
3751 int idx = possible_passthrough_msr_slot(msr);
3753 if (idx != -ENOENT) {
3754 if (type & MSR_TYPE_R)
3755 set_bit(idx, vmx->shadow_msr_intercept.read);
3756 if (type & MSR_TYPE_W)
3757 set_bit(idx, vmx->shadow_msr_intercept.write);
3761 if (type & MSR_TYPE_R)
3762 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3764 if (type & MSR_TYPE_W)
3765 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3768 static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode)
3770 unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
3771 unsigned long read_intercept;
3774 read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3776 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3777 unsigned int read_idx = msr / BITS_PER_LONG;
3778 unsigned int write_idx = read_idx + (0x800 / sizeof(long));
3780 msr_bitmap[read_idx] = read_intercept;
3781 msr_bitmap[write_idx] = ~0ul;
3785 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
3787 struct vcpu_vmx *vmx = to_vmx(vcpu);
3790 if (!cpu_has_vmx_msr_bitmap())
3793 if (cpu_has_secondary_exec_ctrls() &&
3794 (secondary_exec_controls_get(vmx) &
3795 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3796 mode = MSR_BITMAP_MODE_X2APIC;
3797 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3798 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3803 if (mode == vmx->x2apic_msr_bitmap_mode)
3806 vmx->x2apic_msr_bitmap_mode = mode;
3808 vmx_reset_x2apic_msrs(vcpu, mode);
3811 * TPR reads and writes can be virtualized even if virtual interrupt
3812 * delivery is not in use.
3814 vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
3815 !(mode & MSR_BITMAP_MODE_X2APIC));
3817 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3818 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
3819 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3820 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3824 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu)
3826 struct vcpu_vmx *vmx = to_vmx(vcpu);
3827 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3830 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
3831 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
3832 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
3833 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
3834 for (i = 0; i < vmx->pt_desc.num_address_ranges; i++) {
3835 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3836 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3840 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3842 struct vcpu_vmx *vmx = to_vmx(vcpu);
3847 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3848 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3849 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3852 rvi = vmx_get_rvi();
3854 vapic_page = vmx->nested.virtual_apic_map.hva;
3855 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3857 return ((rvi & 0xf0) > (vppr & 0xf0));
3860 static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
3862 struct vcpu_vmx *vmx = to_vmx(vcpu);
3866 * Set intercept permissions for all potentially passed through MSRs
3867 * again. They will automatically get filtered through the MSR filter,
3868 * so we are back in sync after this.
3870 for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
3871 u32 msr = vmx_possible_passthrough_msrs[i];
3872 bool read = test_bit(i, vmx->shadow_msr_intercept.read);
3873 bool write = test_bit(i, vmx->shadow_msr_intercept.write);
3875 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
3876 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
3879 pt_update_intercept_for_msr(vcpu);
3882 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3886 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3888 if (vcpu->mode == IN_GUEST_MODE) {
3890 * The vector of interrupt to be delivered to vcpu had
3891 * been set in PIR before this function.
3893 * Following cases will be reached in this block, and
3894 * we always send a notification event in all cases as
3897 * Case 1: vcpu keeps in non-root mode. Sending a
3898 * notification event posts the interrupt to vcpu.
3900 * Case 2: vcpu exits to root mode and is still
3901 * runnable. PIR will be synced to vIRR before the
3902 * next vcpu entry. Sending a notification event in
3903 * this case has no effect, as vcpu is not in root
3906 * Case 3: vcpu exits to root mode and is blocked.
3907 * vcpu_block() has already synced PIR to vIRR and
3908 * never blocks vcpu if vIRR is not cleared. Therefore,
3909 * a blocked vcpu here does not wait for any requested
3910 * interrupts in PIR, and sending a notification event
3911 * which has no effect is safe here.
3914 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3921 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3924 struct vcpu_vmx *vmx = to_vmx(vcpu);
3926 if (is_guest_mode(vcpu) &&
3927 vector == vmx->nested.posted_intr_nv) {
3929 * If a posted intr is not recognized by hardware,
3930 * we will accomplish it in the next vmentry.
3932 vmx->nested.pi_pending = true;
3933 kvm_make_request(KVM_REQ_EVENT, vcpu);
3934 /* the PIR and ON have been set by L1. */
3935 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3936 kvm_vcpu_kick(vcpu);
3942 * Send interrupt to vcpu via posted interrupt way.
3943 * 1. If target vcpu is running(non-root mode), send posted interrupt
3944 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3945 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3946 * interrupt from PIR in next vmentry.
3948 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3950 struct vcpu_vmx *vmx = to_vmx(vcpu);
3953 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3957 if (!vcpu->arch.apicv_active)
3960 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3963 /* If a previous notification has sent the IPI, nothing to do. */
3964 if (pi_test_and_set_on(&vmx->pi_desc))
3967 if (vcpu != kvm_get_running_vcpu() &&
3968 !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3969 kvm_vcpu_kick(vcpu);
3975 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3976 * will not change in the lifetime of the guest.
3977 * Note that host-state that does change is set elsewhere. E.g., host-state
3978 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3980 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3984 unsigned long cr0, cr3, cr4;
3987 WARN_ON(cr0 & X86_CR0_TS);
3988 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3991 * Save the most likely value for this task's CR3 in the VMCS.
3992 * We can't use __get_current_cr3_fast() because we're not atomic.
3995 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
3996 vmx->loaded_vmcs->host_state.cr3 = cr3;
3998 /* Save the most likely value for this task's CR4 in the VMCS. */
3999 cr4 = cr4_read_shadow();
4000 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4001 vmx->loaded_vmcs->host_state.cr4 = cr4;
4003 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4004 #ifdef CONFIG_X86_64
4006 * Load null selectors, so we can avoid reloading them in
4007 * vmx_prepare_switch_to_host(), in case userspace uses
4008 * the null selectors too (the expected case).
4010 vmcs_write16(HOST_DS_SELECTOR, 0);
4011 vmcs_write16(HOST_ES_SELECTOR, 0);
4013 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4014 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4016 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4017 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4019 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
4021 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4023 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4024 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4025 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4026 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4028 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4029 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4030 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4033 if (cpu_has_load_ia32_efer())
4034 vmcs_write64(HOST_IA32_EFER, host_efer);
4037 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4039 struct kvm_vcpu *vcpu = &vmx->vcpu;
4041 vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
4042 ~vcpu->arch.cr4_guest_rsvd_bits;
4044 vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4045 if (is_guest_mode(&vmx->vcpu))
4046 vcpu->arch.cr4_guest_owned_bits &=
4047 ~get_vmcs12(vcpu)->cr4_guest_host_mask;
4048 vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits);
4051 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4053 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4055 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4056 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4059 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4061 if (!enable_preemption_timer)
4062 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4064 return pin_based_exec_ctrl;
4067 static u32 vmx_vmentry_ctrl(void)
4069 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
4071 if (vmx_pt_mode_is_system())
4072 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
4073 VM_ENTRY_LOAD_IA32_RTIT_CTL);
4074 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4075 return vmentry_ctrl &
4076 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
4079 static u32 vmx_vmexit_ctrl(void)
4081 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
4083 if (vmx_pt_mode_is_system())
4084 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
4085 VM_EXIT_CLEAR_IA32_RTIT_CTL);
4086 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4087 return vmexit_ctrl &
4088 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
4091 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4093 struct vcpu_vmx *vmx = to_vmx(vcpu);
4095 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4096 if (cpu_has_secondary_exec_ctrls()) {
4097 if (kvm_vcpu_apicv_active(vcpu))
4098 secondary_exec_controls_setbit(vmx,
4099 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4100 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4102 secondary_exec_controls_clearbit(vmx,
4103 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4104 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4107 vmx_update_msr_bitmap_x2apic(vcpu);
4110 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4112 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4114 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4115 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4117 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4118 exec_control &= ~CPU_BASED_TPR_SHADOW;
4119 #ifdef CONFIG_X86_64
4120 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4121 CPU_BASED_CR8_LOAD_EXITING;
4125 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4126 CPU_BASED_CR3_LOAD_EXITING |
4127 CPU_BASED_INVLPG_EXITING;
4128 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4129 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4130 CPU_BASED_MONITOR_EXITING);
4131 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4132 exec_control &= ~CPU_BASED_HLT_EXITING;
4133 return exec_control;
4137 * Adjust a single secondary execution control bit to intercept/allow an
4138 * instruction in the guest. This is usually done based on whether or not a
4139 * feature has been exposed to the guest in order to correctly emulate faults.
4142 vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control,
4143 u32 control, bool enabled, bool exiting)
4146 * If the control is for an opt-in feature, clear the control if the
4147 * feature is not exposed to the guest, i.e. not enabled. If the
4148 * control is opt-out, i.e. an exiting control, clear the control if
4149 * the feature _is_ exposed to the guest, i.e. exiting/interception is
4150 * disabled for the associated instruction. Note, the caller is
4151 * responsible presetting exec_control to set all supported bits.
4153 if (enabled == exiting)
4154 *exec_control &= ~control;
4157 * Update the nested MSR settings so that a nested VMM can/can't set
4158 * controls for features that are/aren't exposed to the guest.
4162 vmx->nested.msrs.secondary_ctls_high |= control;
4164 vmx->nested.msrs.secondary_ctls_high &= ~control;
4169 * Wrapper macro for the common case of adjusting a secondary execution control
4170 * based on a single guest CPUID bit, with a dedicated feature bit. This also
4171 * verifies that the control is actually supported by KVM and hardware.
4173 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \
4177 if (cpu_has_vmx_##name()) { \
4178 __enabled = guest_cpuid_has(&(vmx)->vcpu, \
4179 X86_FEATURE_##feat_name); \
4180 vmx_adjust_secondary_exec_control(vmx, exec_control, \
4181 SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \
4185 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */
4186 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \
4187 vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false)
4189 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \
4190 vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true)
4192 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4194 struct kvm_vcpu *vcpu = &vmx->vcpu;
4196 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4198 if (vmx_pt_mode_is_system())
4199 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4200 if (!cpu_need_virtualize_apic_accesses(vcpu))
4201 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4203 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4205 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4206 enable_unrestricted_guest = 0;
4208 if (!enable_unrestricted_guest)
4209 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4210 if (kvm_pause_in_guest(vmx->vcpu.kvm))
4211 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4212 if (!kvm_vcpu_apicv_active(vcpu))
4213 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4214 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4215 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4217 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4218 * in vmx_set_cr4. */
4219 exec_control &= ~SECONDARY_EXEC_DESC;
4221 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4223 We can NOT enable shadow_vmcs here because we don't have yet
4226 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4229 * PML is enabled/disabled when dirty logging of memsmlots changes, but
4230 * it needs to be set here when dirty logging is already active, e.g.
4231 * if this vCPU was created after dirty logging was enabled.
4233 if (!vcpu->kvm->arch.cpu_dirty_logging_count)
4234 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4236 if (cpu_has_vmx_xsaves()) {
4237 /* Exposing XSAVES only when XSAVE is exposed */
4238 bool xsaves_enabled =
4239 boot_cpu_has(X86_FEATURE_XSAVE) &&
4240 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4241 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4243 vcpu->arch.xsaves_enabled = xsaves_enabled;
4245 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4246 SECONDARY_EXEC_XSAVES,
4247 xsaves_enabled, false);
4251 * RDPID is also gated by ENABLE_RDTSCP, turn on the control if either
4252 * feature is exposed to the guest. This creates a virtualization hole
4253 * if both are supported in hardware but only one is exposed to the
4254 * guest, but letting the guest execute RDTSCP or RDPID when either one
4255 * is advertised is preferable to emulating the advertised instruction
4256 * in KVM on #UD, and obviously better than incorrectly injecting #UD.
4258 if (cpu_has_vmx_rdtscp()) {
4259 bool rdpid_or_rdtscp_enabled =
4260 guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) ||
4261 guest_cpuid_has(vcpu, X86_FEATURE_RDPID);
4263 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4264 SECONDARY_EXEC_ENABLE_RDTSCP,
4265 rdpid_or_rdtscp_enabled, false);
4267 vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID);
4269 vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND);
4270 vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED);
4272 vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG,
4273 ENABLE_USR_WAIT_PAUSE, false);
4275 if (!vcpu->kvm->arch.bus_lock_detection_enabled)
4276 exec_control &= ~SECONDARY_EXEC_BUS_LOCK_DETECTION;
4278 return exec_control;
4281 #define VMX_XSS_EXIT_BITMAP 0
4283 static void init_vmcs(struct vcpu_vmx *vmx)
4286 nested_vmx_set_vmcs_shadowing_bitmap();
4288 if (cpu_has_vmx_msr_bitmap())
4289 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4291 vmcs_write64(VMCS_LINK_POINTER, INVALID_GPA); /* 22.3.1.5 */
4294 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4296 exec_controls_set(vmx, vmx_exec_control(vmx));
4298 if (cpu_has_secondary_exec_ctrls())
4299 secondary_exec_controls_set(vmx, vmx_secondary_exec_control(vmx));
4301 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4302 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4303 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4304 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4305 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4307 vmcs_write16(GUEST_INTR_STATUS, 0);
4309 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4310 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4313 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4314 vmcs_write32(PLE_GAP, ple_gap);
4315 vmx->ple_window = ple_window;
4316 vmx->ple_window_dirty = true;
4319 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4320 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4321 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4323 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4324 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4325 vmx_set_constant_host_state(vmx);
4326 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4327 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4329 if (cpu_has_vmx_vmfunc())
4330 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4332 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4333 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4334 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4335 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4336 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4338 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4339 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4341 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4343 /* 22.2.1, 20.8.1 */
4344 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4346 vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4347 vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4349 set_cr4_guest_host_mask(vmx);
4352 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4354 if (cpu_has_vmx_xsaves())
4355 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4358 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4359 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4362 vmx_write_encls_bitmap(&vmx->vcpu, NULL);
4364 if (vmx_pt_mode_is_host_guest()) {
4365 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4366 /* Bit[6~0] are forced to 1, writes are ignored. */
4367 vmx->pt_desc.guest.output_mask = 0x7F;
4368 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4371 vmcs_write32(GUEST_SYSENTER_CS, 0);
4372 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4373 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4374 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4376 if (cpu_has_vmx_tpr_shadow()) {
4377 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4378 if (cpu_need_tpr_shadow(&vmx->vcpu))
4379 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4380 __pa(vmx->vcpu.arch.apic->regs));
4381 vmcs_write32(TPR_THRESHOLD, 0);
4384 vmx_setup_uret_msrs(vmx);
4387 static void __vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4389 struct vcpu_vmx *vmx = to_vmx(vcpu);
4394 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
4396 vcpu_setup_sgx_lepubkeyhash(vcpu);
4398 vmx->nested.posted_intr_nv = -1;
4399 vmx->nested.vmxon_ptr = INVALID_GPA;
4400 vmx->nested.current_vmptr = INVALID_GPA;
4401 vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
4403 vcpu->arch.microcode_version = 0x100000000ULL;
4404 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
4407 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
4408 * or POSTED_INTR_WAKEUP_VECTOR.
4410 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
4411 vmx->pi_desc.sn = 1;
4414 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4416 struct vcpu_vmx *vmx = to_vmx(vcpu);
4419 __vmx_vcpu_reset(vcpu);
4421 vmx->rmode.vm86_active = 0;
4424 vmx->msr_ia32_umwait_control = 0;
4426 vmx->hv_deadline_tsc = -1;
4427 kvm_set_cr8(vcpu, 0);
4429 vmx_segment_cache_clear(vmx);
4430 kvm_register_mark_available(vcpu, VCPU_EXREG_SEGMENTS);
4432 seg_setup(VCPU_SREG_CS);
4433 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4434 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4436 seg_setup(VCPU_SREG_DS);
4437 seg_setup(VCPU_SREG_ES);
4438 seg_setup(VCPU_SREG_FS);
4439 seg_setup(VCPU_SREG_GS);
4440 seg_setup(VCPU_SREG_SS);
4442 vmcs_write16(GUEST_TR_SELECTOR, 0);
4443 vmcs_writel(GUEST_TR_BASE, 0);
4444 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4445 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4447 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4448 vmcs_writel(GUEST_LDTR_BASE, 0);
4449 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4450 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4452 vmcs_writel(GUEST_GDTR_BASE, 0);
4453 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4455 vmcs_writel(GUEST_IDTR_BASE, 0);
4456 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4458 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4459 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4460 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4461 if (kvm_mpx_supported())
4462 vmcs_write64(GUEST_BNDCFGS, 0);
4464 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4466 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4468 vpid_sync_context(vmx->vpid);
4471 static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
4473 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4476 static void vmx_enable_nmi_window(struct kvm_vcpu *vcpu)
4479 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4480 vmx_enable_irq_window(vcpu);
4484 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4487 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4489 struct vcpu_vmx *vmx = to_vmx(vcpu);
4491 int irq = vcpu->arch.interrupt.nr;
4493 trace_kvm_inj_virq(irq);
4495 ++vcpu->stat.irq_injections;
4496 if (vmx->rmode.vm86_active) {
4498 if (vcpu->arch.interrupt.soft)
4499 inc_eip = vcpu->arch.event_exit_inst_len;
4500 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4503 intr = irq | INTR_INFO_VALID_MASK;
4504 if (vcpu->arch.interrupt.soft) {
4505 intr |= INTR_TYPE_SOFT_INTR;
4506 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4507 vmx->vcpu.arch.event_exit_inst_len);
4509 intr |= INTR_TYPE_EXT_INTR;
4510 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4512 vmx_clear_hlt(vcpu);
4515 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4517 struct vcpu_vmx *vmx = to_vmx(vcpu);
4521 * Tracking the NMI-blocked state in software is built upon
4522 * finding the next open IRQ window. This, in turn, depends on
4523 * well-behaving guests: They have to keep IRQs disabled at
4524 * least as long as the NMI handler runs. Otherwise we may
4525 * cause NMI nesting, maybe breaking the guest. But as this is
4526 * highly unlikely, we can live with the residual risk.
4528 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4529 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4532 ++vcpu->stat.nmi_injections;
4533 vmx->loaded_vmcs->nmi_known_unmasked = false;
4535 if (vmx->rmode.vm86_active) {
4536 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4540 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4541 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4543 vmx_clear_hlt(vcpu);
4546 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4548 struct vcpu_vmx *vmx = to_vmx(vcpu);
4552 return vmx->loaded_vmcs->soft_vnmi_blocked;
4553 if (vmx->loaded_vmcs->nmi_known_unmasked)
4555 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4556 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4560 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4562 struct vcpu_vmx *vmx = to_vmx(vcpu);
4565 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4566 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4567 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4570 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4572 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4573 GUEST_INTR_STATE_NMI);
4575 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4576 GUEST_INTR_STATE_NMI);
4580 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4582 if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4585 if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4588 return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4589 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4590 GUEST_INTR_STATE_NMI));
4593 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4595 if (to_vmx(vcpu)->nested.nested_run_pending)
4598 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
4599 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4602 return !vmx_nmi_blocked(vcpu);
4605 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4607 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4610 return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4611 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4612 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4615 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4617 if (to_vmx(vcpu)->nested.nested_run_pending)
4621 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4622 * e.g. if the IRQ arrived asynchronously after checking nested events.
4624 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4627 return !vmx_interrupt_blocked(vcpu);
4630 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4634 if (enable_unrestricted_guest)
4637 mutex_lock(&kvm->slots_lock);
4638 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4640 mutex_unlock(&kvm->slots_lock);
4643 return PTR_ERR(ret);
4645 to_kvm_vmx(kvm)->tss_addr = addr;
4647 return init_rmode_tss(kvm, ret);
4650 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4652 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4656 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4661 * Update instruction length as we may reinject the exception
4662 * from user space while in guest debugging mode.
4664 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4665 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4666 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4670 return !(vcpu->guest_debug &
4671 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4685 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4686 int vec, u32 err_code)
4689 * Instruction with address size override prefix opcode 0x67
4690 * Cause the #SS fault with 0 error code in VM86 mode.
4692 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4693 if (kvm_emulate_instruction(vcpu, 0)) {
4694 if (vcpu->arch.halt_request) {
4695 vcpu->arch.halt_request = 0;
4696 return kvm_vcpu_halt(vcpu);
4704 * Forward all other exceptions that are valid in real mode.
4705 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4706 * the required debugging infrastructure rework.
4708 kvm_queue_exception(vcpu, vec);
4712 static int handle_machine_check(struct kvm_vcpu *vcpu)
4714 /* handled by vmx_vcpu_run() */
4719 * If the host has split lock detection disabled, then #AC is
4720 * unconditionally injected into the guest, which is the pre split lock
4721 * detection behaviour.
4723 * If the host has split lock detection enabled then #AC is
4724 * only injected into the guest when:
4725 * - Guest CPL == 3 (user mode)
4726 * - Guest has #AC detection enabled in CR0
4727 * - Guest EFLAGS has AC bit set
4729 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu)
4731 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4734 return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4735 (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4738 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4740 struct vcpu_vmx *vmx = to_vmx(vcpu);
4741 struct kvm_run *kvm_run = vcpu->run;
4742 u32 intr_info, ex_no, error_code;
4743 unsigned long cr2, dr6;
4746 vect_info = vmx->idt_vectoring_info;
4747 intr_info = vmx_get_intr_info(vcpu);
4749 if (is_machine_check(intr_info) || is_nmi(intr_info))
4750 return 1; /* handled by handle_exception_nmi_irqoff() */
4752 if (is_invalid_opcode(intr_info))
4753 return handle_ud(vcpu);
4756 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4757 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4759 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4760 WARN_ON_ONCE(!enable_vmware_backdoor);
4763 * VMware backdoor emulation on #GP interception only handles
4764 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4765 * error code on #GP.
4768 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4771 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4775 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4776 * MMIO, it is better to report an internal error.
4777 * See the comments in vmx_handle_exit.
4779 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4780 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4781 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4782 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4783 vcpu->run->internal.ndata = 4;
4784 vcpu->run->internal.data[0] = vect_info;
4785 vcpu->run->internal.data[1] = intr_info;
4786 vcpu->run->internal.data[2] = error_code;
4787 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4791 if (is_page_fault(intr_info)) {
4792 cr2 = vmx_get_exit_qual(vcpu);
4793 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4795 * EPT will cause page fault only if we need to
4796 * detect illegal GPAs.
4798 WARN_ON_ONCE(!allow_smaller_maxphyaddr);
4799 kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4802 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4805 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4807 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4808 return handle_rmode_exception(vcpu, ex_no, error_code);
4812 dr6 = vmx_get_exit_qual(vcpu);
4813 if (!(vcpu->guest_debug &
4814 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4815 if (is_icebp(intr_info))
4816 WARN_ON(!skip_emulated_instruction(vcpu));
4818 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4821 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
4822 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4826 * Update instruction length as we may reinject #BP from
4827 * user space while in guest debugging mode. Reading it for
4828 * #DB as well causes no harm, it is not used in that case.
4830 vmx->vcpu.arch.event_exit_inst_len =
4831 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4832 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4833 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4834 kvm_run->debug.arch.exception = ex_no;
4837 if (vmx_guest_inject_ac(vcpu)) {
4838 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4843 * Handle split lock. Depending on detection mode this will
4844 * either warn and disable split lock detection for this
4845 * task or force SIGBUS on it.
4847 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4851 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4852 kvm_run->ex.exception = ex_no;
4853 kvm_run->ex.error_code = error_code;
4859 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4861 ++vcpu->stat.irq_exits;
4865 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4867 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4868 vcpu->mmio_needed = 0;
4872 static int handle_io(struct kvm_vcpu *vcpu)
4874 unsigned long exit_qualification;
4875 int size, in, string;
4878 exit_qualification = vmx_get_exit_qual(vcpu);
4879 string = (exit_qualification & 16) != 0;
4881 ++vcpu->stat.io_exits;
4884 return kvm_emulate_instruction(vcpu, 0);
4886 port = exit_qualification >> 16;
4887 size = (exit_qualification & 7) + 1;
4888 in = (exit_qualification & 8) != 0;
4890 return kvm_fast_pio(vcpu, size, port, in);
4894 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4897 * Patch in the VMCALL instruction:
4899 hypercall[0] = 0x0f;
4900 hypercall[1] = 0x01;
4901 hypercall[2] = 0xc1;
4904 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4905 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4907 if (is_guest_mode(vcpu)) {
4908 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4909 unsigned long orig_val = val;
4912 * We get here when L2 changed cr0 in a way that did not change
4913 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4914 * but did change L0 shadowed bits. So we first calculate the
4915 * effective cr0 value that L1 would like to write into the
4916 * hardware. It consists of the L2-owned bits from the new
4917 * value combined with the L1-owned bits from L1's guest_cr0.
4919 val = (val & ~vmcs12->cr0_guest_host_mask) |
4920 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4922 if (!nested_guest_cr0_valid(vcpu, val))
4925 if (kvm_set_cr0(vcpu, val))
4927 vmcs_writel(CR0_READ_SHADOW, orig_val);
4930 if (to_vmx(vcpu)->nested.vmxon &&
4931 !nested_host_cr0_valid(vcpu, val))
4934 return kvm_set_cr0(vcpu, val);
4938 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4940 if (is_guest_mode(vcpu)) {
4941 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4942 unsigned long orig_val = val;
4944 /* analogously to handle_set_cr0 */
4945 val = (val & ~vmcs12->cr4_guest_host_mask) |
4946 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4947 if (kvm_set_cr4(vcpu, val))
4949 vmcs_writel(CR4_READ_SHADOW, orig_val);
4952 return kvm_set_cr4(vcpu, val);
4955 static int handle_desc(struct kvm_vcpu *vcpu)
4957 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4958 return kvm_emulate_instruction(vcpu, 0);
4961 static int handle_cr(struct kvm_vcpu *vcpu)
4963 unsigned long exit_qualification, val;
4969 exit_qualification = vmx_get_exit_qual(vcpu);
4970 cr = exit_qualification & 15;
4971 reg = (exit_qualification >> 8) & 15;
4972 switch ((exit_qualification >> 4) & 3) {
4973 case 0: /* mov to cr */
4974 val = kvm_register_read(vcpu, reg);
4975 trace_kvm_cr_write(cr, val);
4978 err = handle_set_cr0(vcpu, val);
4979 return kvm_complete_insn_gp(vcpu, err);
4981 WARN_ON_ONCE(enable_unrestricted_guest);
4983 err = kvm_set_cr3(vcpu, val);
4984 return kvm_complete_insn_gp(vcpu, err);
4986 err = handle_set_cr4(vcpu, val);
4987 return kvm_complete_insn_gp(vcpu, err);
4989 u8 cr8_prev = kvm_get_cr8(vcpu);
4991 err = kvm_set_cr8(vcpu, cr8);
4992 ret = kvm_complete_insn_gp(vcpu, err);
4993 if (lapic_in_kernel(vcpu))
4995 if (cr8_prev <= cr8)
4998 * TODO: we might be squashing a
4999 * KVM_GUESTDBG_SINGLESTEP-triggered
5000 * KVM_EXIT_DEBUG here.
5002 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5008 KVM_BUG(1, vcpu->kvm, "Guest always owns CR0.TS");
5010 case 1: /*mov from cr*/
5013 WARN_ON_ONCE(enable_unrestricted_guest);
5015 val = kvm_read_cr3(vcpu);
5016 kvm_register_write(vcpu, reg, val);
5017 trace_kvm_cr_read(cr, val);
5018 return kvm_skip_emulated_instruction(vcpu);
5020 val = kvm_get_cr8(vcpu);
5021 kvm_register_write(vcpu, reg, val);
5022 trace_kvm_cr_read(cr, val);
5023 return kvm_skip_emulated_instruction(vcpu);
5027 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5028 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5029 kvm_lmsw(vcpu, val);
5031 return kvm_skip_emulated_instruction(vcpu);
5035 vcpu->run->exit_reason = 0;
5036 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5037 (int)(exit_qualification >> 4) & 3, cr);
5041 static int handle_dr(struct kvm_vcpu *vcpu)
5043 unsigned long exit_qualification;
5047 exit_qualification = vmx_get_exit_qual(vcpu);
5048 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5050 /* First, if DR does not exist, trigger UD */
5051 if (!kvm_require_dr(vcpu, dr))
5054 if (kvm_x86_ops.get_cpl(vcpu) > 0)
5057 dr7 = vmcs_readl(GUEST_DR7);
5060 * As the vm-exit takes precedence over the debug trap, we
5061 * need to emulate the latter, either for the host or the
5062 * guest debugging itself.
5064 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5065 vcpu->run->debug.arch.dr6 = DR6_BD | DR6_ACTIVE_LOW;
5066 vcpu->run->debug.arch.dr7 = dr7;
5067 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5068 vcpu->run->debug.arch.exception = DB_VECTOR;
5069 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5072 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5077 if (vcpu->guest_debug == 0) {
5078 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5081 * No more DR vmexits; force a reload of the debug registers
5082 * and reenter on this instruction. The next vmexit will
5083 * retrieve the full state of the debug registers.
5085 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5089 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5090 if (exit_qualification & TYPE_MOV_FROM_DR) {
5093 kvm_get_dr(vcpu, dr, &val);
5094 kvm_register_write(vcpu, reg, val);
5097 err = kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg));
5101 return kvm_complete_insn_gp(vcpu, err);
5104 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5106 get_debugreg(vcpu->arch.db[0], 0);
5107 get_debugreg(vcpu->arch.db[1], 1);
5108 get_debugreg(vcpu->arch.db[2], 2);
5109 get_debugreg(vcpu->arch.db[3], 3);
5110 get_debugreg(vcpu->arch.dr6, 6);
5111 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5113 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5114 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5117 * exc_debug expects dr6 to be cleared after it runs, avoid that it sees
5118 * a stale dr6 from the guest.
5120 set_debugreg(DR6_RESERVED, 6);
5123 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5125 vmcs_writel(GUEST_DR7, val);
5128 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5130 kvm_apic_update_ppr(vcpu);
5134 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5136 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5138 kvm_make_request(KVM_REQ_EVENT, vcpu);
5140 ++vcpu->stat.irq_window_exits;
5144 static int handle_invlpg(struct kvm_vcpu *vcpu)
5146 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5148 kvm_mmu_invlpg(vcpu, exit_qualification);
5149 return kvm_skip_emulated_instruction(vcpu);
5152 static int handle_apic_access(struct kvm_vcpu *vcpu)
5154 if (likely(fasteoi)) {
5155 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5156 int access_type, offset;
5158 access_type = exit_qualification & APIC_ACCESS_TYPE;
5159 offset = exit_qualification & APIC_ACCESS_OFFSET;
5161 * Sane guest uses MOV to write EOI, with written value
5162 * not cared. So make a short-circuit here by avoiding
5163 * heavy instruction emulation.
5165 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5166 (offset == APIC_EOI)) {
5167 kvm_lapic_set_eoi(vcpu);
5168 return kvm_skip_emulated_instruction(vcpu);
5171 return kvm_emulate_instruction(vcpu, 0);
5174 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5176 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5177 int vector = exit_qualification & 0xff;
5179 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5180 kvm_apic_set_eoi_accelerated(vcpu, vector);
5184 static int handle_apic_write(struct kvm_vcpu *vcpu)
5186 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5187 u32 offset = exit_qualification & 0xfff;
5189 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5190 kvm_apic_write_nodecode(vcpu, offset);
5194 static int handle_task_switch(struct kvm_vcpu *vcpu)
5196 struct vcpu_vmx *vmx = to_vmx(vcpu);
5197 unsigned long exit_qualification;
5198 bool has_error_code = false;
5201 int reason, type, idt_v, idt_index;
5203 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5204 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5205 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5207 exit_qualification = vmx_get_exit_qual(vcpu);
5209 reason = (u32)exit_qualification >> 30;
5210 if (reason == TASK_SWITCH_GATE && idt_v) {
5212 case INTR_TYPE_NMI_INTR:
5213 vcpu->arch.nmi_injected = false;
5214 vmx_set_nmi_mask(vcpu, true);
5216 case INTR_TYPE_EXT_INTR:
5217 case INTR_TYPE_SOFT_INTR:
5218 kvm_clear_interrupt_queue(vcpu);
5220 case INTR_TYPE_HARD_EXCEPTION:
5221 if (vmx->idt_vectoring_info &
5222 VECTORING_INFO_DELIVER_CODE_MASK) {
5223 has_error_code = true;
5225 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5228 case INTR_TYPE_SOFT_EXCEPTION:
5229 kvm_clear_exception_queue(vcpu);
5235 tss_selector = exit_qualification;
5237 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5238 type != INTR_TYPE_EXT_INTR &&
5239 type != INTR_TYPE_NMI_INTR))
5240 WARN_ON(!skip_emulated_instruction(vcpu));
5243 * TODO: What about debug traps on tss switch?
5244 * Are we supposed to inject them and update dr6?
5246 return kvm_task_switch(vcpu, tss_selector,
5247 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5248 reason, has_error_code, error_code);
5251 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5253 unsigned long exit_qualification;
5257 exit_qualification = vmx_get_exit_qual(vcpu);
5260 * EPT violation happened while executing iret from NMI,
5261 * "blocked by NMI" bit has to be set before next VM entry.
5262 * There are errata that may cause this bit to not be set:
5265 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5267 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5268 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5270 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5271 trace_kvm_page_fault(gpa, exit_qualification);
5273 /* Is it a read fault? */
5274 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5275 ? PFERR_USER_MASK : 0;
5276 /* Is it a write fault? */
5277 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5278 ? PFERR_WRITE_MASK : 0;
5279 /* Is it a fetch fault? */
5280 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5281 ? PFERR_FETCH_MASK : 0;
5282 /* ept page table entry is present? */
5283 error_code |= (exit_qualification &
5284 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5285 EPT_VIOLATION_EXECUTABLE))
5286 ? PFERR_PRESENT_MASK : 0;
5288 error_code |= (exit_qualification & EPT_VIOLATION_GVA_TRANSLATED) != 0 ?
5289 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5291 vcpu->arch.exit_qualification = exit_qualification;
5294 * Check that the GPA doesn't exceed physical memory limits, as that is
5295 * a guest page fault. We have to emulate the instruction here, because
5296 * if the illegal address is that of a paging structure, then
5297 * EPT_VIOLATION_ACC_WRITE bit is set. Alternatively, if supported we
5298 * would also use advanced VM-exit information for EPT violations to
5299 * reconstruct the page fault error code.
5301 if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa)))
5302 return kvm_emulate_instruction(vcpu, 0);
5304 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5307 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5311 if (!vmx_can_emulate_instruction(vcpu, NULL, 0))
5315 * A nested guest cannot optimize MMIO vmexits, because we have an
5316 * nGPA here instead of the required GPA.
5318 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5319 if (!is_guest_mode(vcpu) &&
5320 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5321 trace_kvm_fast_mmio(gpa);
5322 return kvm_skip_emulated_instruction(vcpu);
5325 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5328 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5330 if (KVM_BUG_ON(!enable_vnmi, vcpu->kvm))
5333 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5334 ++vcpu->stat.nmi_window_exits;
5335 kvm_make_request(KVM_REQ_EVENT, vcpu);
5340 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5342 struct vcpu_vmx *vmx = to_vmx(vcpu);
5343 bool intr_window_requested;
5344 unsigned count = 130;
5346 intr_window_requested = exec_controls_get(vmx) &
5347 CPU_BASED_INTR_WINDOW_EXITING;
5349 while (vmx->emulation_required && count-- != 0) {
5350 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5351 return handle_interrupt_window(&vmx->vcpu);
5353 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5356 if (!kvm_emulate_instruction(vcpu, 0))
5359 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5360 vcpu->arch.exception.pending) {
5361 kvm_prepare_emulation_failure_exit(vcpu);
5365 if (vcpu->arch.halt_request) {
5366 vcpu->arch.halt_request = 0;
5367 return kvm_vcpu_halt(vcpu);
5371 * Note, return 1 and not 0, vcpu_run() will invoke
5372 * xfer_to_guest_mode() which will create a proper return
5375 if (__xfer_to_guest_mode_work_pending())
5382 static void grow_ple_window(struct kvm_vcpu *vcpu)
5384 struct vcpu_vmx *vmx = to_vmx(vcpu);
5385 unsigned int old = vmx->ple_window;
5387 vmx->ple_window = __grow_ple_window(old, ple_window,
5391 if (vmx->ple_window != old) {
5392 vmx->ple_window_dirty = true;
5393 trace_kvm_ple_window_update(vcpu->vcpu_id,
5394 vmx->ple_window, old);
5398 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5400 struct vcpu_vmx *vmx = to_vmx(vcpu);
5401 unsigned int old = vmx->ple_window;
5403 vmx->ple_window = __shrink_ple_window(old, ple_window,
5407 if (vmx->ple_window != old) {
5408 vmx->ple_window_dirty = true;
5409 trace_kvm_ple_window_update(vcpu->vcpu_id,
5410 vmx->ple_window, old);
5415 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5416 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5418 static int handle_pause(struct kvm_vcpu *vcpu)
5420 if (!kvm_pause_in_guest(vcpu->kvm))
5421 grow_ple_window(vcpu);
5424 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5425 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5426 * never set PAUSE_EXITING and just set PLE if supported,
5427 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5429 kvm_vcpu_on_spin(vcpu, true);
5430 return kvm_skip_emulated_instruction(vcpu);
5433 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5438 static int handle_invpcid(struct kvm_vcpu *vcpu)
5440 u32 vmx_instruction_info;
5449 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5450 kvm_queue_exception(vcpu, UD_VECTOR);
5454 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5455 gpr_index = vmx_get_instr_info_reg2(vmx_instruction_info);
5456 type = kvm_register_read(vcpu, gpr_index);
5458 /* According to the Intel instruction reference, the memory operand
5459 * is read even if it isn't needed (e.g., for type==all)
5461 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5462 vmx_instruction_info, false,
5463 sizeof(operand), &gva))
5466 return kvm_handle_invpcid(vcpu, type, gva);
5469 static int handle_pml_full(struct kvm_vcpu *vcpu)
5471 unsigned long exit_qualification;
5473 trace_kvm_pml_full(vcpu->vcpu_id);
5475 exit_qualification = vmx_get_exit_qual(vcpu);
5478 * PML buffer FULL happened while executing iret from NMI,
5479 * "blocked by NMI" bit has to be set before next VM entry.
5481 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5483 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5484 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5485 GUEST_INTR_STATE_NMI);
5488 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5489 * here.., and there's no userspace involvement needed for PML.
5494 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5496 struct vcpu_vmx *vmx = to_vmx(vcpu);
5498 if (!vmx->req_immediate_exit &&
5499 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5500 kvm_lapic_expired_hv_timer(vcpu);
5501 return EXIT_FASTPATH_REENTER_GUEST;
5504 return EXIT_FASTPATH_NONE;
5507 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5509 handle_fastpath_preemption_timer(vcpu);
5514 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5515 * are overwritten by nested_vmx_setup() when nested=1.
5517 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5519 kvm_queue_exception(vcpu, UD_VECTOR);
5523 #ifndef CONFIG_X86_SGX_KVM
5524 static int handle_encls(struct kvm_vcpu *vcpu)
5527 * SGX virtualization is disabled. There is no software enable bit for
5528 * SGX, so KVM intercepts all ENCLS leafs and injects a #UD to prevent
5529 * the guest from executing ENCLS (when SGX is supported by hardware).
5531 kvm_queue_exception(vcpu, UD_VECTOR);
5534 #endif /* CONFIG_X86_SGX_KVM */
5536 static int handle_bus_lock_vmexit(struct kvm_vcpu *vcpu)
5539 * Hardware may or may not set the BUS_LOCK_DETECTED flag on BUS_LOCK
5540 * VM-Exits. Unconditionally set the flag here and leave the handling to
5541 * vmx_handle_exit().
5543 to_vmx(vcpu)->exit_reason.bus_lock_detected = true;
5548 * The exit handlers return 1 if the exit was handled fully and guest execution
5549 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5550 * to be done to userspace and return 0.
5552 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5553 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5554 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5555 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5556 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5557 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5558 [EXIT_REASON_CR_ACCESS] = handle_cr,
5559 [EXIT_REASON_DR_ACCESS] = handle_dr,
5560 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5561 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5562 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
5563 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
5564 [EXIT_REASON_HLT] = kvm_emulate_halt,
5565 [EXIT_REASON_INVD] = kvm_emulate_invd,
5566 [EXIT_REASON_INVLPG] = handle_invlpg,
5567 [EXIT_REASON_RDPMC] = kvm_emulate_rdpmc,
5568 [EXIT_REASON_VMCALL] = kvm_emulate_hypercall,
5569 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5570 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5571 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5572 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5573 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5574 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5575 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5576 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5577 [EXIT_REASON_VMON] = handle_vmx_instruction,
5578 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5579 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5580 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5581 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5582 [EXIT_REASON_WBINVD] = kvm_emulate_wbinvd,
5583 [EXIT_REASON_XSETBV] = kvm_emulate_xsetbv,
5584 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5585 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5586 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5587 [EXIT_REASON_LDTR_TR] = handle_desc,
5588 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5589 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5590 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5591 [EXIT_REASON_MWAIT_INSTRUCTION] = kvm_emulate_mwait,
5592 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5593 [EXIT_REASON_MONITOR_INSTRUCTION] = kvm_emulate_monitor,
5594 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5595 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5596 [EXIT_REASON_RDRAND] = kvm_handle_invalid_op,
5597 [EXIT_REASON_RDSEED] = kvm_handle_invalid_op,
5598 [EXIT_REASON_PML_FULL] = handle_pml_full,
5599 [EXIT_REASON_INVPCID] = handle_invpcid,
5600 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5601 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5602 [EXIT_REASON_ENCLS] = handle_encls,
5603 [EXIT_REASON_BUS_LOCK] = handle_bus_lock_vmexit,
5606 static const int kvm_vmx_max_exit_handlers =
5607 ARRAY_SIZE(kvm_vmx_exit_handlers);
5609 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
5610 u64 *info1, u64 *info2,
5611 u32 *intr_info, u32 *error_code)
5613 struct vcpu_vmx *vmx = to_vmx(vcpu);
5615 *reason = vmx->exit_reason.full;
5616 *info1 = vmx_get_exit_qual(vcpu);
5617 if (!(vmx->exit_reason.failed_vmentry)) {
5618 *info2 = vmx->idt_vectoring_info;
5619 *intr_info = vmx_get_intr_info(vcpu);
5620 if (is_exception_with_error_code(*intr_info))
5621 *error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5631 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5634 __free_page(vmx->pml_pg);
5639 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5641 struct vcpu_vmx *vmx = to_vmx(vcpu);
5645 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5647 /* Do nothing if PML buffer is empty */
5648 if (pml_idx == (PML_ENTITY_NUM - 1))
5651 /* PML index always points to next available PML buffer entity */
5652 if (pml_idx >= PML_ENTITY_NUM)
5657 pml_buf = page_address(vmx->pml_pg);
5658 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5661 gpa = pml_buf[pml_idx];
5662 WARN_ON(gpa & (PAGE_SIZE - 1));
5663 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5666 /* reset PML index */
5667 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5670 static void vmx_dump_sel(char *name, uint32_t sel)
5672 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5673 name, vmcs_read16(sel),
5674 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5675 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5676 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5679 static void vmx_dump_dtsel(char *name, uint32_t limit)
5681 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5682 name, vmcs_read32(limit),
5683 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5686 static void vmx_dump_msrs(char *name, struct vmx_msrs *m)
5689 struct vmx_msr_entry *e;
5691 pr_err("MSR %s:\n", name);
5692 for (i = 0, e = m->val; i < m->nr; ++i, ++e)
5693 pr_err(" %2d: msr=0x%08x value=0x%016llx\n", i, e->index, e->value);
5696 void dump_vmcs(struct kvm_vcpu *vcpu)
5698 struct vcpu_vmx *vmx = to_vmx(vcpu);
5699 u32 vmentry_ctl, vmexit_ctl;
5700 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5704 if (!dump_invalid_vmcs) {
5705 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5709 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5710 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5711 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5712 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5713 cr4 = vmcs_readl(GUEST_CR4);
5714 secondary_exec_control = 0;
5715 if (cpu_has_secondary_exec_ctrls())
5716 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5718 pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
5719 vmx->loaded_vmcs->vmcs, vcpu->arch.last_vmentry_cpu);
5720 pr_err("*** Guest State ***\n");
5721 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5722 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5723 vmcs_readl(CR0_GUEST_HOST_MASK));
5724 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5725 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5726 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5727 if (cpu_has_vmx_ept()) {
5728 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5729 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5730 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5731 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5733 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5734 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5735 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5736 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5737 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5738 vmcs_readl(GUEST_SYSENTER_ESP),
5739 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5740 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5741 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5742 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5743 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5744 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5745 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5746 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5747 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5748 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5749 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5750 efer_slot = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, MSR_EFER);
5751 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_EFER)
5752 pr_err("EFER= 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER));
5753 else if (efer_slot >= 0)
5754 pr_err("EFER= 0x%016llx (autoload)\n",
5755 vmx->msr_autoload.guest.val[efer_slot].value);
5756 else if (vmentry_ctl & VM_ENTRY_IA32E_MODE)
5757 pr_err("EFER= 0x%016llx (effective)\n",
5758 vcpu->arch.efer | (EFER_LMA | EFER_LME));
5760 pr_err("EFER= 0x%016llx (effective)\n",
5761 vcpu->arch.efer & ~(EFER_LMA | EFER_LME));
5762 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PAT)
5763 pr_err("PAT = 0x%016llx\n", vmcs_read64(GUEST_IA32_PAT));
5764 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5765 vmcs_read64(GUEST_IA32_DEBUGCTL),
5766 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5767 if (cpu_has_load_perf_global_ctrl() &&
5768 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5769 pr_err("PerfGlobCtl = 0x%016llx\n",
5770 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5771 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5772 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5773 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5774 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5775 vmcs_read32(GUEST_ACTIVITY_STATE));
5776 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5777 pr_err("InterruptStatus = %04x\n",
5778 vmcs_read16(GUEST_INTR_STATUS));
5779 if (vmcs_read32(VM_ENTRY_MSR_LOAD_COUNT) > 0)
5780 vmx_dump_msrs("guest autoload", &vmx->msr_autoload.guest);
5781 if (vmcs_read32(VM_EXIT_MSR_STORE_COUNT) > 0)
5782 vmx_dump_msrs("guest autostore", &vmx->msr_autostore.guest);
5784 pr_err("*** Host State ***\n");
5785 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5786 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5787 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5788 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5789 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5790 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5791 vmcs_read16(HOST_TR_SELECTOR));
5792 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5793 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5794 vmcs_readl(HOST_TR_BASE));
5795 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5796 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5797 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5798 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5799 vmcs_readl(HOST_CR4));
5800 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5801 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5802 vmcs_read32(HOST_IA32_SYSENTER_CS),
5803 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5804 if (vmexit_ctl & VM_EXIT_LOAD_IA32_EFER)
5805 pr_err("EFER= 0x%016llx\n", vmcs_read64(HOST_IA32_EFER));
5806 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PAT)
5807 pr_err("PAT = 0x%016llx\n", vmcs_read64(HOST_IA32_PAT));
5808 if (cpu_has_load_perf_global_ctrl() &&
5809 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5810 pr_err("PerfGlobCtl = 0x%016llx\n",
5811 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5812 if (vmcs_read32(VM_EXIT_MSR_LOAD_COUNT) > 0)
5813 vmx_dump_msrs("host autoload", &vmx->msr_autoload.host);
5815 pr_err("*** Control State ***\n");
5816 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5817 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5818 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5819 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5820 vmcs_read32(EXCEPTION_BITMAP),
5821 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5822 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5823 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5824 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5825 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5826 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5827 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5828 vmcs_read32(VM_EXIT_INTR_INFO),
5829 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5830 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5831 pr_err(" reason=%08x qualification=%016lx\n",
5832 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5833 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5834 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5835 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5836 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5837 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5838 pr_err("TSC Multiplier = 0x%016llx\n",
5839 vmcs_read64(TSC_MULTIPLIER));
5840 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5841 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5842 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5843 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5845 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5846 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5847 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5848 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5850 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5851 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5852 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5853 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5854 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5855 pr_err("PLE Gap=%08x Window=%08x\n",
5856 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5857 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5858 pr_err("Virtual processor ID = 0x%04x\n",
5859 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5863 * The guest has exited. See if we can fix it or if we need userspace
5866 static int __vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5868 struct vcpu_vmx *vmx = to_vmx(vcpu);
5869 union vmx_exit_reason exit_reason = vmx->exit_reason;
5870 u32 vectoring_info = vmx->idt_vectoring_info;
5871 u16 exit_handler_index;
5874 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5875 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5876 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5877 * mode as if vcpus is in root mode, the PML buffer must has been
5878 * flushed already. Note, PML is never enabled in hardware while
5881 if (enable_pml && !is_guest_mode(vcpu))
5882 vmx_flush_pml_buffer(vcpu);
5885 * KVM should never reach this point with a pending nested VM-Enter.
5886 * More specifically, short-circuiting VM-Entry to emulate L2 due to
5887 * invalid guest state should never happen as that means KVM knowingly
5888 * allowed a nested VM-Enter with an invalid vmcs12. More below.
5890 if (KVM_BUG_ON(vmx->nested.nested_run_pending, vcpu->kvm))
5893 if (is_guest_mode(vcpu)) {
5895 * PML is never enabled when running L2, bail immediately if a
5896 * PML full exit occurs as something is horribly wrong.
5898 if (exit_reason.basic == EXIT_REASON_PML_FULL)
5899 goto unexpected_vmexit;
5902 * The host physical addresses of some pages of guest memory
5903 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5904 * Page). The CPU may write to these pages via their host
5905 * physical address while L2 is running, bypassing any
5906 * address-translation-based dirty tracking (e.g. EPT write
5909 * Mark them dirty on every exit from L2 to prevent them from
5910 * getting out of sync with dirty tracking.
5912 nested_mark_vmcs12_pages_dirty(vcpu);
5915 * Synthesize a triple fault if L2 state is invalid. In normal
5916 * operation, nested VM-Enter rejects any attempt to enter L2
5917 * with invalid state. However, those checks are skipped if
5918 * state is being stuffed via RSM or KVM_SET_NESTED_STATE. If
5919 * L2 state is invalid, it means either L1 modified SMRAM state
5920 * or userspace provided bad state. Synthesize TRIPLE_FAULT as
5921 * doing so is architecturally allowed in the RSM case, and is
5922 * the least awful solution for the userspace case without
5923 * risking false positives.
5925 if (vmx->emulation_required) {
5926 nested_vmx_vmexit(vcpu, EXIT_REASON_TRIPLE_FAULT, 0, 0);
5930 if (nested_vmx_reflect_vmexit(vcpu))
5934 /* If guest state is invalid, start emulating. L2 is handled above. */
5935 if (vmx->emulation_required)
5936 return handle_invalid_guest_state(vcpu);
5938 if (exit_reason.failed_vmentry) {
5940 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5941 vcpu->run->fail_entry.hardware_entry_failure_reason
5943 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5947 if (unlikely(vmx->fail)) {
5949 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5950 vcpu->run->fail_entry.hardware_entry_failure_reason
5951 = vmcs_read32(VM_INSTRUCTION_ERROR);
5952 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5958 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5959 * delivery event since it indicates guest is accessing MMIO.
5960 * The vm-exit can be triggered again after return to guest that
5961 * will cause infinite loop.
5963 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5964 (exit_reason.basic != EXIT_REASON_EXCEPTION_NMI &&
5965 exit_reason.basic != EXIT_REASON_EPT_VIOLATION &&
5966 exit_reason.basic != EXIT_REASON_PML_FULL &&
5967 exit_reason.basic != EXIT_REASON_APIC_ACCESS &&
5968 exit_reason.basic != EXIT_REASON_TASK_SWITCH)) {
5971 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5972 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5973 vcpu->run->internal.data[0] = vectoring_info;
5974 vcpu->run->internal.data[1] = exit_reason.full;
5975 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5976 if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG) {
5977 vcpu->run->internal.data[ndata++] =
5978 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5980 vcpu->run->internal.data[ndata++] = vcpu->arch.last_vmentry_cpu;
5981 vcpu->run->internal.ndata = ndata;
5985 if (unlikely(!enable_vnmi &&
5986 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5987 if (!vmx_interrupt_blocked(vcpu)) {
5988 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5989 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5990 vcpu->arch.nmi_pending) {
5992 * This CPU don't support us in finding the end of an
5993 * NMI-blocked window if the guest runs with IRQs
5994 * disabled. So we pull the trigger after 1 s of
5995 * futile waiting, but inform the user about this.
5997 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5998 "state on VCPU %d after 1 s timeout\n",
5999 __func__, vcpu->vcpu_id);
6000 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6004 if (exit_fastpath != EXIT_FASTPATH_NONE)
6007 if (exit_reason.basic >= kvm_vmx_max_exit_handlers)
6008 goto unexpected_vmexit;
6009 #ifdef CONFIG_RETPOLINE
6010 if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
6011 return kvm_emulate_wrmsr(vcpu);
6012 else if (exit_reason.basic == EXIT_REASON_PREEMPTION_TIMER)
6013 return handle_preemption_timer(vcpu);
6014 else if (exit_reason.basic == EXIT_REASON_INTERRUPT_WINDOW)
6015 return handle_interrupt_window(vcpu);
6016 else if (exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6017 return handle_external_interrupt(vcpu);
6018 else if (exit_reason.basic == EXIT_REASON_HLT)
6019 return kvm_emulate_halt(vcpu);
6020 else if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG)
6021 return handle_ept_misconfig(vcpu);
6024 exit_handler_index = array_index_nospec((u16)exit_reason.basic,
6025 kvm_vmx_max_exit_handlers);
6026 if (!kvm_vmx_exit_handlers[exit_handler_index])
6027 goto unexpected_vmexit;
6029 return kvm_vmx_exit_handlers[exit_handler_index](vcpu);
6032 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
6035 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6036 vcpu->run->internal.suberror =
6037 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6038 vcpu->run->internal.ndata = 2;
6039 vcpu->run->internal.data[0] = exit_reason.full;
6040 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6044 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6046 int ret = __vmx_handle_exit(vcpu, exit_fastpath);
6049 * Exit to user space when bus lock detected to inform that there is
6050 * a bus lock in guest.
6052 if (to_vmx(vcpu)->exit_reason.bus_lock_detected) {
6054 vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
6056 vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
6063 * Software based L1D cache flush which is used when microcode providing
6064 * the cache control MSR is not loaded.
6066 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6067 * flush it is required to read in 64 KiB because the replacement algorithm
6068 * is not exactly LRU. This could be sized at runtime via topology
6069 * information but as all relevant affected CPUs have 32KiB L1D cache size
6070 * there is no point in doing so.
6072 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6074 int size = PAGE_SIZE << L1D_CACHE_ORDER;
6077 * This code is only executed when the the flush mode is 'cond' or
6080 if (static_branch_likely(&vmx_l1d_flush_cond)) {
6084 * Clear the per-vcpu flush bit, it gets set again
6085 * either from vcpu_run() or from one of the unsafe
6088 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6089 vcpu->arch.l1tf_flush_l1d = false;
6092 * Clear the per-cpu flush bit, it gets set again from
6093 * the interrupt handlers.
6095 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6096 kvm_clear_cpu_l1tf_flush_l1d();
6102 vcpu->stat.l1d_flush++;
6104 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6105 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6110 /* First ensure the pages are in the TLB */
6111 "xorl %%eax, %%eax\n"
6112 ".Lpopulate_tlb:\n\t"
6113 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6114 "addl $4096, %%eax\n\t"
6115 "cmpl %%eax, %[size]\n\t"
6116 "jne .Lpopulate_tlb\n\t"
6117 "xorl %%eax, %%eax\n\t"
6119 /* Now fill the cache */
6120 "xorl %%eax, %%eax\n"
6122 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6123 "addl $64, %%eax\n\t"
6124 "cmpl %%eax, %[size]\n\t"
6125 "jne .Lfill_cache\n\t"
6127 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6129 : "eax", "ebx", "ecx", "edx");
6132 static void vmx_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6134 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6137 if (is_guest_mode(vcpu) &&
6138 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6141 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6142 if (is_guest_mode(vcpu))
6143 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6145 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6148 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6150 struct vcpu_vmx *vmx = to_vmx(vcpu);
6151 u32 sec_exec_control;
6153 if (!lapic_in_kernel(vcpu))
6156 if (!flexpriority_enabled &&
6157 !cpu_has_vmx_virtualize_x2apic_mode())
6160 /* Postpone execution until vmcs01 is the current VMCS. */
6161 if (is_guest_mode(vcpu)) {
6162 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6166 sec_exec_control = secondary_exec_controls_get(vmx);
6167 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6168 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6170 switch (kvm_get_apic_mode(vcpu)) {
6171 case LAPIC_MODE_INVALID:
6172 WARN_ONCE(true, "Invalid local APIC state");
6174 case LAPIC_MODE_DISABLED:
6176 case LAPIC_MODE_XAPIC:
6177 if (flexpriority_enabled) {
6179 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6180 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6183 * Flush the TLB, reloading the APIC access page will
6184 * only do so if its physical address has changed, but
6185 * the guest may have inserted a non-APIC mapping into
6186 * the TLB while the APIC access page was disabled.
6188 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6191 case LAPIC_MODE_X2APIC:
6192 if (cpu_has_vmx_virtualize_x2apic_mode())
6194 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6197 secondary_exec_controls_set(vmx, sec_exec_control);
6199 vmx_update_msr_bitmap_x2apic(vcpu);
6202 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6206 /* Defer reload until vmcs01 is the current VMCS. */
6207 if (is_guest_mode(vcpu)) {
6208 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6212 if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6213 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6216 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6217 if (is_error_page(page))
6220 vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6221 vmx_flush_tlb_current(vcpu);
6224 * Do not pin apic access page in memory, the MMU notifier
6225 * will call us again if it is migrated or swapped out.
6230 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6238 status = vmcs_read16(GUEST_INTR_STATUS);
6240 if (max_isr != old) {
6242 status |= max_isr << 8;
6243 vmcs_write16(GUEST_INTR_STATUS, status);
6247 static void vmx_set_rvi(int vector)
6255 status = vmcs_read16(GUEST_INTR_STATUS);
6256 old = (u8)status & 0xff;
6257 if ((u8)vector != old) {
6259 status |= (u8)vector;
6260 vmcs_write16(GUEST_INTR_STATUS, status);
6264 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6267 * When running L2, updating RVI is only relevant when
6268 * vmcs12 virtual-interrupt-delivery enabled.
6269 * However, it can be enabled only when L1 also
6270 * intercepts external-interrupts and in that case
6271 * we should not update vmcs02 RVI but instead intercept
6272 * interrupt. Therefore, do nothing when running L2.
6274 if (!is_guest_mode(vcpu))
6275 vmx_set_rvi(max_irr);
6278 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6280 struct vcpu_vmx *vmx = to_vmx(vcpu);
6282 bool got_posted_interrupt;
6284 if (KVM_BUG_ON(!enable_apicv, vcpu->kvm))
6287 if (pi_test_on(&vmx->pi_desc)) {
6288 pi_clear_on(&vmx->pi_desc);
6290 * IOMMU can write to PID.ON, so the barrier matters even on UP.
6291 * But on x86 this is just a compiler barrier anyway.
6293 smp_mb__after_atomic();
6294 got_posted_interrupt =
6295 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6297 max_irr = kvm_lapic_find_highest_irr(vcpu);
6298 got_posted_interrupt = false;
6302 * Newly recognized interrupts are injected via either virtual interrupt
6303 * delivery (RVI) or KVM_REQ_EVENT. Virtual interrupt delivery is
6304 * disabled in two cases:
6306 * 1) If L2 is running and the vCPU has a new pending interrupt. If L1
6307 * wants to exit on interrupts, KVM_REQ_EVENT is needed to synthesize a
6308 * VM-Exit to L1. If L1 doesn't want to exit, the interrupt is injected
6309 * into L2, but KVM doesn't use virtual interrupt delivery to inject
6310 * interrupts into L2, and so KVM_REQ_EVENT is again needed.
6312 * 2) If APICv is disabled for this vCPU, assigned devices may still
6313 * attempt to post interrupts. The posted interrupt vector will cause
6314 * a VM-Exit and the subsequent entry will call sync_pir_to_irr.
6316 if (!is_guest_mode(vcpu) && kvm_vcpu_apicv_active(vcpu))
6317 vmx_set_rvi(max_irr);
6318 else if (got_posted_interrupt)
6319 kvm_make_request(KVM_REQ_EVENT, vcpu);
6324 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6326 if (!kvm_vcpu_apicv_active(vcpu))
6329 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6330 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6331 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6332 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6335 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6337 struct vcpu_vmx *vmx = to_vmx(vcpu);
6339 pi_clear_on(&vmx->pi_desc);
6340 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6343 void vmx_do_interrupt_nmi_irqoff(unsigned long entry);
6345 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu,
6346 unsigned long entry)
6348 kvm_before_interrupt(vcpu);
6349 vmx_do_interrupt_nmi_irqoff(entry);
6350 kvm_after_interrupt(vcpu);
6353 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6355 const unsigned long nmi_entry = (unsigned long)asm_exc_nmi_noist;
6356 u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6358 /* if exit due to PF check for async PF */
6359 if (is_page_fault(intr_info))
6360 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6361 /* Handle machine checks before interrupts are enabled */
6362 else if (is_machine_check(intr_info))
6363 kvm_machine_check();
6364 /* We need to handle NMIs before interrupts are enabled */
6365 else if (is_nmi(intr_info))
6366 handle_interrupt_nmi_irqoff(&vmx->vcpu, nmi_entry);
6369 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6371 u32 intr_info = vmx_get_intr_info(vcpu);
6372 unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK;
6373 gate_desc *desc = (gate_desc *)host_idt_base + vector;
6375 if (KVM_BUG(!is_external_intr(intr_info), vcpu->kvm,
6376 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6379 handle_interrupt_nmi_irqoff(vcpu, gate_offset(desc));
6382 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6384 struct vcpu_vmx *vmx = to_vmx(vcpu);
6386 if (vmx->emulation_required)
6389 if (vmx->exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6390 handle_external_interrupt_irqoff(vcpu);
6391 else if (vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI)
6392 handle_exception_nmi_irqoff(vmx);
6396 * The kvm parameter can be NULL (module initialization, or invocation before
6397 * VM creation). Be sure to check the kvm parameter before using it.
6399 static bool vmx_has_emulated_msr(struct kvm *kvm, u32 index)
6402 case MSR_IA32_SMBASE:
6404 * We cannot do SMM unless we can run the guest in big
6407 return enable_unrestricted_guest || emulate_invalid_guest_state;
6408 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6410 case MSR_AMD64_VIRT_SPEC_CTRL:
6411 case MSR_AMD64_TSC_RATIO:
6412 /* This is AMD only. */
6419 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6424 bool idtv_info_valid;
6426 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6429 if (vmx->loaded_vmcs->nmi_known_unmasked)
6432 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6433 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6434 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6436 * SDM 3: 27.7.1.2 (September 2008)
6437 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6438 * a guest IRET fault.
6439 * SDM 3: 23.2.2 (September 2008)
6440 * Bit 12 is undefined in any of the following cases:
6441 * If the VM exit sets the valid bit in the IDT-vectoring
6442 * information field.
6443 * If the VM exit is due to a double fault.
6445 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6446 vector != DF_VECTOR && !idtv_info_valid)
6447 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6448 GUEST_INTR_STATE_NMI);
6450 vmx->loaded_vmcs->nmi_known_unmasked =
6451 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6452 & GUEST_INTR_STATE_NMI);
6453 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6454 vmx->loaded_vmcs->vnmi_blocked_time +=
6455 ktime_to_ns(ktime_sub(ktime_get(),
6456 vmx->loaded_vmcs->entry_time));
6459 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6460 u32 idt_vectoring_info,
6461 int instr_len_field,
6462 int error_code_field)
6466 bool idtv_info_valid;
6468 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6470 vcpu->arch.nmi_injected = false;
6471 kvm_clear_exception_queue(vcpu);
6472 kvm_clear_interrupt_queue(vcpu);
6474 if (!idtv_info_valid)
6477 kvm_make_request(KVM_REQ_EVENT, vcpu);
6479 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6480 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6483 case INTR_TYPE_NMI_INTR:
6484 vcpu->arch.nmi_injected = true;
6486 * SDM 3: 27.7.1.2 (September 2008)
6487 * Clear bit "block by NMI" before VM entry if a NMI
6490 vmx_set_nmi_mask(vcpu, false);
6492 case INTR_TYPE_SOFT_EXCEPTION:
6493 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6495 case INTR_TYPE_HARD_EXCEPTION:
6496 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6497 u32 err = vmcs_read32(error_code_field);
6498 kvm_requeue_exception_e(vcpu, vector, err);
6500 kvm_requeue_exception(vcpu, vector);
6502 case INTR_TYPE_SOFT_INTR:
6503 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6505 case INTR_TYPE_EXT_INTR:
6506 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6513 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6515 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6516 VM_EXIT_INSTRUCTION_LEN,
6517 IDT_VECTORING_ERROR_CODE);
6520 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6522 __vmx_complete_interrupts(vcpu,
6523 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6524 VM_ENTRY_INSTRUCTION_LEN,
6525 VM_ENTRY_EXCEPTION_ERROR_CODE);
6527 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6530 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6533 struct perf_guest_switch_msr *msrs;
6535 /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
6536 msrs = perf_guest_get_msrs(&nr_msrs);
6540 for (i = 0; i < nr_msrs; i++)
6541 if (msrs[i].host == msrs[i].guest)
6542 clear_atomic_switch_msr(vmx, msrs[i].msr);
6544 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6545 msrs[i].host, false);
6548 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6550 struct vcpu_vmx *vmx = to_vmx(vcpu);
6554 if (vmx->req_immediate_exit) {
6555 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6556 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6557 } else if (vmx->hv_deadline_tsc != -1) {
6559 if (vmx->hv_deadline_tsc > tscl)
6560 /* set_hv_timer ensures the delta fits in 32-bits */
6561 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6562 cpu_preemption_timer_multi);
6566 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6567 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6568 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6569 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6570 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6574 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6576 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6577 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6578 vmcs_writel(HOST_RSP, host_rsp);
6582 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6584 switch (to_vmx(vcpu)->exit_reason.basic) {
6585 case EXIT_REASON_MSR_WRITE:
6586 return handle_fastpath_set_msr_irqoff(vcpu);
6587 case EXIT_REASON_PREEMPTION_TIMER:
6588 return handle_fastpath_preemption_timer(vcpu);
6590 return EXIT_FASTPATH_NONE;
6594 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6595 struct vcpu_vmx *vmx)
6597 kvm_guest_enter_irqoff();
6599 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6600 if (static_branch_unlikely(&vmx_l1d_should_flush))
6601 vmx_l1d_flush(vcpu);
6602 else if (static_branch_unlikely(&mds_user_clear))
6603 mds_clear_cpu_buffers();
6605 if (vcpu->arch.cr2 != native_read_cr2())
6606 native_write_cr2(vcpu->arch.cr2);
6608 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6609 vmx->loaded_vmcs->launched);
6611 vcpu->arch.cr2 = native_read_cr2();
6613 kvm_guest_exit_irqoff();
6616 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6618 struct vcpu_vmx *vmx = to_vmx(vcpu);
6619 unsigned long cr3, cr4;
6621 /* Record the guest's net vcpu time for enforced NMI injections. */
6622 if (unlikely(!enable_vnmi &&
6623 vmx->loaded_vmcs->soft_vnmi_blocked))
6624 vmx->loaded_vmcs->entry_time = ktime_get();
6627 * Don't enter VMX if guest state is invalid, let the exit handler
6628 * start emulation until we arrive back to a valid state. Synthesize a
6629 * consistency check VM-Exit due to invalid guest state and bail.
6631 if (unlikely(vmx->emulation_required)) {
6634 vmx->exit_reason.full = EXIT_REASON_INVALID_STATE;
6635 vmx->exit_reason.failed_vmentry = 1;
6636 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
6637 vmx->exit_qualification = ENTRY_FAIL_DEFAULT;
6638 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
6639 vmx->exit_intr_info = 0;
6640 return EXIT_FASTPATH_NONE;
6643 trace_kvm_entry(vcpu);
6645 if (vmx->ple_window_dirty) {
6646 vmx->ple_window_dirty = false;
6647 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6651 * We did this in prepare_switch_to_guest, because it needs to
6652 * be within srcu_read_lock.
6654 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6656 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6657 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6658 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6659 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6661 cr3 = __get_current_cr3_fast();
6662 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6663 vmcs_writel(HOST_CR3, cr3);
6664 vmx->loaded_vmcs->host_state.cr3 = cr3;
6667 cr4 = cr4_read_shadow();
6668 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6669 vmcs_writel(HOST_CR4, cr4);
6670 vmx->loaded_vmcs->host_state.cr4 = cr4;
6673 /* When KVM_DEBUGREG_WONT_EXIT, dr6 is accessible in guest. */
6674 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
6675 set_debugreg(vcpu->arch.dr6, 6);
6677 /* When single-stepping over STI and MOV SS, we must clear the
6678 * corresponding interruptibility bits in the guest state. Otherwise
6679 * vmentry fails as it then expects bit 14 (BS) in pending debug
6680 * exceptions being set, but that's not correct for the guest debugging
6682 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6683 vmx_set_interrupt_shadow(vcpu, 0);
6685 kvm_load_guest_xsave_state(vcpu);
6687 pt_guest_enter(vmx);
6689 atomic_switch_perf_msrs(vmx);
6690 if (intel_pmu_lbr_is_enabled(vcpu))
6691 vmx_passthrough_lbr_msrs(vcpu);
6693 if (enable_preemption_timer)
6694 vmx_update_hv_timer(vcpu);
6696 kvm_wait_lapic_expire(vcpu);
6699 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6700 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6701 * is no need to worry about the conditional branch over the wrmsr
6702 * being speculatively taken.
6704 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6706 /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6707 vmx_vcpu_enter_exit(vcpu, vmx);
6710 * We do not use IBRS in the kernel. If this vCPU has used the
6711 * SPEC_CTRL MSR it may have left it on; save the value and
6712 * turn it off. This is much more efficient than blindly adding
6713 * it to the atomic save/restore list. Especially as the former
6714 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6716 * For non-nested case:
6717 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6721 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6724 if (unlikely(!msr_write_intercepted(vmx, MSR_IA32_SPEC_CTRL)))
6725 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6727 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6729 /* All fields are clean at this point */
6730 if (static_branch_unlikely(&enable_evmcs)) {
6731 current_evmcs->hv_clean_fields |=
6732 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6734 current_evmcs->hv_vp_id = kvm_hv_get_vpindex(vcpu);
6737 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6738 if (vmx->host_debugctlmsr)
6739 update_debugctlmsr(vmx->host_debugctlmsr);
6741 #ifndef CONFIG_X86_64
6743 * The sysexit path does not restore ds/es, so we must set them to
6744 * a reasonable value ourselves.
6746 * We can't defer this to vmx_prepare_switch_to_host() since that
6747 * function may be executed in interrupt context, which saves and
6748 * restore segments around it, nullifying its effect.
6750 loadsegment(ds, __USER_DS);
6751 loadsegment(es, __USER_DS);
6754 vmx_register_cache_reset(vcpu);
6758 kvm_load_host_xsave_state(vcpu);
6760 if (is_guest_mode(vcpu)) {
6762 * Track VMLAUNCH/VMRESUME that have made past guest state
6765 if (vmx->nested.nested_run_pending &&
6766 !vmx->exit_reason.failed_vmentry)
6767 ++vcpu->stat.nested_run;
6769 vmx->nested.nested_run_pending = 0;
6772 vmx->idt_vectoring_info = 0;
6774 if (unlikely(vmx->fail)) {
6775 vmx->exit_reason.full = 0xdead;
6776 return EXIT_FASTPATH_NONE;
6779 vmx->exit_reason.full = vmcs_read32(VM_EXIT_REASON);
6780 if (unlikely((u16)vmx->exit_reason.basic == EXIT_REASON_MCE_DURING_VMENTRY))
6781 kvm_machine_check();
6783 if (likely(!vmx->exit_reason.failed_vmentry))
6784 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6786 trace_kvm_exit(vcpu, KVM_ISA_VMX);
6788 if (unlikely(vmx->exit_reason.failed_vmentry))
6789 return EXIT_FASTPATH_NONE;
6791 vmx->loaded_vmcs->launched = 1;
6793 vmx_recover_nmi_blocking(vmx);
6794 vmx_complete_interrupts(vmx);
6796 if (is_guest_mode(vcpu))
6797 return EXIT_FASTPATH_NONE;
6799 return vmx_exit_handlers_fastpath(vcpu);
6802 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6804 struct vcpu_vmx *vmx = to_vmx(vcpu);
6807 vmx_destroy_pml_buffer(vmx);
6808 free_vpid(vmx->vpid);
6809 nested_vmx_free_vcpu(vcpu);
6810 free_loaded_vmcs(vmx->loaded_vmcs);
6813 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6815 struct vmx_uret_msr *tsx_ctrl;
6816 struct vcpu_vmx *vmx;
6819 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6824 vmx->vpid = allocate_vpid();
6827 * If PML is turned on, failure on enabling PML just results in failure
6828 * of creating the vcpu, therefore we can simplify PML logic (by
6829 * avoiding dealing with cases, such as enabling PML partially on vcpus
6830 * for the guest), etc.
6833 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6838 for (i = 0; i < kvm_nr_uret_msrs; ++i)
6839 vmx->guest_uret_msrs[i].mask = -1ull;
6840 if (boot_cpu_has(X86_FEATURE_RTM)) {
6842 * TSX_CTRL_CPUID_CLEAR is handled in the CPUID interception.
6843 * Keep the host value unchanged to avoid changing CPUID bits
6844 * under the host kernel's feet.
6846 tsx_ctrl = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
6848 tsx_ctrl->mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6851 err = alloc_loaded_vmcs(&vmx->vmcs01);
6856 * Use Hyper-V 'Enlightened MSR Bitmap' feature when KVM runs as a
6857 * nested (L1) hypervisor and Hyper-V in L0 supports it. Enable the
6858 * feature only for vmcs01, KVM currently isn't equipped to realize any
6859 * performance benefits from enabling it for vmcs02.
6861 if (IS_ENABLED(CONFIG_HYPERV) && static_branch_unlikely(&enable_evmcs) &&
6862 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
6863 struct hv_enlightened_vmcs *evmcs = (void *)vmx->vmcs01.vmcs;
6865 evmcs->hv_enlightenments_control.msr_bitmap = 1;
6868 /* The MSR bitmap starts with all ones */
6869 bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6870 bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6872 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
6873 #ifdef CONFIG_X86_64
6874 vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
6875 vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
6876 vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6878 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6879 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6880 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6881 if (kvm_cstate_in_guest(vcpu->kvm)) {
6882 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
6883 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6884 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6885 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6888 vmx->loaded_vmcs = &vmx->vmcs01;
6890 if (cpu_need_virtualize_apic_accesses(vcpu)) {
6891 err = alloc_apic_access_page(vcpu->kvm);
6896 if (enable_ept && !enable_unrestricted_guest) {
6897 err = init_rmode_identity_map(vcpu->kvm);
6905 free_loaded_vmcs(vmx->loaded_vmcs);
6907 vmx_destroy_pml_buffer(vmx);
6909 free_vpid(vmx->vpid);
6913 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6914 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6916 static int vmx_vm_init(struct kvm *kvm)
6919 kvm->arch.pause_in_guest = true;
6921 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6922 switch (l1tf_mitigation) {
6923 case L1TF_MITIGATION_OFF:
6924 case L1TF_MITIGATION_FLUSH_NOWARN:
6925 /* 'I explicitly don't care' is set */
6927 case L1TF_MITIGATION_FLUSH:
6928 case L1TF_MITIGATION_FLUSH_NOSMT:
6929 case L1TF_MITIGATION_FULL:
6931 * Warn upon starting the first VM in a potentially
6932 * insecure environment.
6934 if (sched_smt_active())
6935 pr_warn_once(L1TF_MSG_SMT);
6936 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6937 pr_warn_once(L1TF_MSG_L1D);
6939 case L1TF_MITIGATION_FULL_FORCE:
6940 /* Flush is enforced */
6947 static int __init vmx_check_processor_compat(void)
6949 struct vmcs_config vmcs_conf;
6950 struct vmx_capability vmx_cap;
6952 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6953 !this_cpu_has(X86_FEATURE_VMX)) {
6954 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6958 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6961 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6962 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6963 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6964 smp_processor_id());
6970 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6975 /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6976 * memory aliases with conflicting memory types and sometimes MCEs.
6977 * We have to be careful as to what are honored and when.
6979 * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to
6980 * UC. The effective memory type is UC or WC depending on guest PAT.
6981 * This was historically the source of MCEs and we want to be
6984 * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6985 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The
6986 * EPT memory type is set to WB. The effective memory type is forced
6989 * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The
6990 * EPT memory type is used to emulate guest CD/MTRR.
6994 cache = MTRR_TYPE_UNCACHABLE;
6998 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6999 ipat = VMX_EPT_IPAT_BIT;
7000 cache = MTRR_TYPE_WRBACK;
7004 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
7005 ipat = VMX_EPT_IPAT_BIT;
7006 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
7007 cache = MTRR_TYPE_WRBACK;
7009 cache = MTRR_TYPE_UNCACHABLE;
7013 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
7016 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
7019 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx, u32 new_ctl)
7022 * These bits in the secondary execution controls field
7023 * are dynamic, the others are mostly based on the hypervisor
7024 * architecture and the guest's CPUID. Do not touch the
7028 SECONDARY_EXEC_SHADOW_VMCS |
7029 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7030 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7031 SECONDARY_EXEC_DESC;
7033 u32 cur_ctl = secondary_exec_controls_get(vmx);
7035 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7039 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7040 * (indicating "allowed-1") if they are supported in the guest's CPUID.
7042 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7044 struct vcpu_vmx *vmx = to_vmx(vcpu);
7045 struct kvm_cpuid_entry2 *entry;
7047 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7048 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7050 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
7051 if (entry && (entry->_reg & (_cpuid_mask))) \
7052 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
7055 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7056 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME));
7057 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME));
7058 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC));
7059 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE));
7060 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE));
7061 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE));
7062 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE));
7063 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE));
7064 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR));
7065 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7066 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX));
7067 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX));
7068 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID));
7069 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE));
7071 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7072 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE));
7073 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP));
7074 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP));
7075 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU));
7076 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP));
7077 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57));
7079 #undef cr4_fixed1_update
7082 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7084 struct vcpu_vmx *vmx = to_vmx(vcpu);
7086 if (kvm_mpx_supported()) {
7087 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7090 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7091 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7093 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7094 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7099 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7101 struct vcpu_vmx *vmx = to_vmx(vcpu);
7102 struct kvm_cpuid_entry2 *best = NULL;
7105 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7106 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7109 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7110 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7111 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7112 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7115 /* Get the number of configurable Address Ranges for filtering */
7116 vmx->pt_desc.num_address_ranges = intel_pt_validate_cap(vmx->pt_desc.caps,
7117 PT_CAP_num_address_ranges);
7119 /* Initialize and clear the no dependency bits */
7120 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7121 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC |
7122 RTIT_CTL_BRANCH_EN);
7125 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7126 * will inject an #GP
7128 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7129 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7132 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7133 * PSBFreq can be set
7135 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7136 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7137 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7140 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn and MTCFreq can be set
7142 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7143 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7144 RTIT_CTL_MTC_RANGE);
7146 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7147 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7148 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7151 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7152 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7153 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7155 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7156 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7157 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7159 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabricEn can be set */
7160 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7161 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7163 /* unmask address range configure area */
7164 for (i = 0; i < vmx->pt_desc.num_address_ranges; i++)
7165 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7168 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7170 struct vcpu_vmx *vmx = to_vmx(vcpu);
7172 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7173 vcpu->arch.xsaves_enabled = false;
7175 vmx_setup_uret_msrs(vmx);
7177 if (cpu_has_secondary_exec_ctrls())
7178 vmcs_set_secondary_exec_control(vmx,
7179 vmx_secondary_exec_control(vmx));
7181 if (nested_vmx_allowed(vcpu))
7182 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7183 FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7184 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7186 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7187 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7188 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7190 if (nested_vmx_allowed(vcpu)) {
7191 nested_vmx_cr_fixed1_bits_update(vcpu);
7192 nested_vmx_entry_exit_ctls_update(vcpu);
7195 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7196 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7197 update_intel_pt_cfg(vcpu);
7199 if (boot_cpu_has(X86_FEATURE_RTM)) {
7200 struct vmx_uret_msr *msr;
7201 msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
7203 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7204 vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7208 set_cr4_guest_host_mask(vmx);
7210 vmx_write_encls_bitmap(vcpu, NULL);
7211 if (guest_cpuid_has(vcpu, X86_FEATURE_SGX))
7212 vmx->msr_ia32_feature_control_valid_bits |= FEAT_CTL_SGX_ENABLED;
7214 vmx->msr_ia32_feature_control_valid_bits &= ~FEAT_CTL_SGX_ENABLED;
7216 if (guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
7217 vmx->msr_ia32_feature_control_valid_bits |=
7218 FEAT_CTL_SGX_LC_ENABLED;
7220 vmx->msr_ia32_feature_control_valid_bits &=
7221 ~FEAT_CTL_SGX_LC_ENABLED;
7223 /* Refresh #PF interception to account for MAXPHYADDR changes. */
7224 vmx_update_exception_bitmap(vcpu);
7227 static __init void vmx_set_cpu_caps(void)
7233 kvm_cpu_cap_set(X86_FEATURE_VMX);
7236 if (kvm_mpx_supported())
7237 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7238 if (!cpu_has_vmx_invpcid())
7239 kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
7240 if (vmx_pt_mode_is_host_guest())
7241 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7244 kvm_cpu_cap_clear(X86_FEATURE_SGX);
7245 kvm_cpu_cap_clear(X86_FEATURE_SGX_LC);
7246 kvm_cpu_cap_clear(X86_FEATURE_SGX1);
7247 kvm_cpu_cap_clear(X86_FEATURE_SGX2);
7250 if (vmx_umip_emulated())
7251 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7255 if (!cpu_has_vmx_xsaves())
7256 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7258 /* CPUID 0x80000001 and 0x7 (RDPID) */
7259 if (!cpu_has_vmx_rdtscp()) {
7260 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7261 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
7264 if (cpu_has_vmx_waitpkg())
7265 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7268 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7270 to_vmx(vcpu)->req_immediate_exit = true;
7273 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7274 struct x86_instruction_info *info)
7276 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7277 unsigned short port;
7281 if (info->intercept == x86_intercept_in ||
7282 info->intercept == x86_intercept_ins) {
7283 port = info->src_val;
7284 size = info->dst_bytes;
7286 port = info->dst_val;
7287 size = info->src_bytes;
7291 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7292 * VM-exits depend on the 'unconditional IO exiting' VM-execution
7295 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7297 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7298 intercept = nested_cpu_has(vmcs12,
7299 CPU_BASED_UNCOND_IO_EXITING);
7301 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7303 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7304 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7307 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7308 struct x86_instruction_info *info,
7309 enum x86_intercept_stage stage,
7310 struct x86_exception *exception)
7312 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7314 switch (info->intercept) {
7316 * RDPID causes #UD if disabled through secondary execution controls.
7317 * Because it is marked as EmulateOnUD, we need to intercept it here.
7318 * Note, RDPID is hidden behind ENABLE_RDTSCP.
7320 case x86_intercept_rdpid:
7321 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) {
7322 exception->vector = UD_VECTOR;
7323 exception->error_code_valid = false;
7324 return X86EMUL_PROPAGATE_FAULT;
7328 case x86_intercept_in:
7329 case x86_intercept_ins:
7330 case x86_intercept_out:
7331 case x86_intercept_outs:
7332 return vmx_check_intercept_io(vcpu, info);
7334 case x86_intercept_lgdt:
7335 case x86_intercept_lidt:
7336 case x86_intercept_lldt:
7337 case x86_intercept_ltr:
7338 case x86_intercept_sgdt:
7339 case x86_intercept_sidt:
7340 case x86_intercept_sldt:
7341 case x86_intercept_str:
7342 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7343 return X86EMUL_CONTINUE;
7345 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7348 /* TODO: check more intercepts... */
7353 return X86EMUL_UNHANDLEABLE;
7356 #ifdef CONFIG_X86_64
7357 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7358 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7359 u64 divisor, u64 *result)
7361 u64 low = a << shift, high = a >> (64 - shift);
7363 /* To avoid the overflow on divq */
7364 if (high >= divisor)
7367 /* Low hold the result, high hold rem which is discarded */
7368 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7369 "rm" (divisor), "0" (low), "1" (high));
7375 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7378 struct vcpu_vmx *vmx;
7379 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7380 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7384 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7385 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7386 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7387 ktimer->timer_advance_ns);
7389 if (delta_tsc > lapic_timer_advance_cycles)
7390 delta_tsc -= lapic_timer_advance_cycles;
7394 /* Convert to host delta tsc if tsc scaling is enabled */
7395 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7396 delta_tsc && u64_shl_div_u64(delta_tsc,
7397 kvm_tsc_scaling_ratio_frac_bits,
7398 vcpu->arch.l1_tsc_scaling_ratio, &delta_tsc))
7402 * If the delta tsc can't fit in the 32 bit after the multi shift,
7403 * we can't use the preemption timer.
7404 * It's possible that it fits on later vmentries, but checking
7405 * on every vmentry is costly so we just use an hrtimer.
7407 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7410 vmx->hv_deadline_tsc = tscl + delta_tsc;
7411 *expired = !delta_tsc;
7415 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7417 to_vmx(vcpu)->hv_deadline_tsc = -1;
7421 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7423 if (!kvm_pause_in_guest(vcpu->kvm))
7424 shrink_ple_window(vcpu);
7427 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu)
7429 struct vcpu_vmx *vmx = to_vmx(vcpu);
7431 if (is_guest_mode(vcpu)) {
7432 vmx->nested.update_vmcs01_cpu_dirty_logging = true;
7437 * Note, cpu_dirty_logging_count can be changed concurrent with this
7438 * code, but in that case another update request will be made and so
7439 * the guest will never run with a stale PML value.
7441 if (vcpu->kvm->arch.cpu_dirty_logging_count)
7442 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7444 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7447 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7449 if (pi_pre_block(vcpu))
7452 if (kvm_lapic_hv_timer_in_use(vcpu))
7453 kvm_lapic_switch_to_sw_timer(vcpu);
7458 static void vmx_post_block(struct kvm_vcpu *vcpu)
7460 if (kvm_x86_ops.set_hv_timer)
7461 kvm_lapic_switch_to_hv_timer(vcpu);
7463 pi_post_block(vcpu);
7466 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7468 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7469 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7470 FEAT_CTL_LMCE_ENABLED;
7472 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7473 ~FEAT_CTL_LMCE_ENABLED;
7476 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7478 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7479 if (to_vmx(vcpu)->nested.nested_run_pending)
7481 return !is_smm(vcpu);
7484 static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7486 struct vcpu_vmx *vmx = to_vmx(vcpu);
7488 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7489 if (vmx->nested.smm.guest_mode)
7490 nested_vmx_vmexit(vcpu, -1, 0, 0);
7492 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7493 vmx->nested.vmxon = false;
7494 vmx_clear_hlt(vcpu);
7498 static int vmx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7500 struct vcpu_vmx *vmx = to_vmx(vcpu);
7503 if (vmx->nested.smm.vmxon) {
7504 vmx->nested.vmxon = true;
7505 vmx->nested.smm.vmxon = false;
7508 if (vmx->nested.smm.guest_mode) {
7509 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7513 vmx->nested.smm.guest_mode = false;
7518 static void vmx_enable_smi_window(struct kvm_vcpu *vcpu)
7520 /* RSM will cause a vmexit anyway. */
7523 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7525 return to_vmx(vcpu)->nested.vmxon && !is_guest_mode(vcpu);
7528 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7530 if (is_guest_mode(vcpu)) {
7531 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7533 if (hrtimer_try_to_cancel(timer) == 1)
7534 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7538 static void hardware_unsetup(void)
7540 kvm_set_posted_intr_wakeup_handler(NULL);
7543 nested_vmx_hardware_unsetup();
7548 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7550 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7551 BIT(APICV_INHIBIT_REASON_ABSENT) |
7552 BIT(APICV_INHIBIT_REASON_HYPERV) |
7553 BIT(APICV_INHIBIT_REASON_BLOCKIRQ);
7555 return supported & BIT(bit);
7558 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7559 .name = "kvm_intel",
7561 .hardware_unsetup = hardware_unsetup,
7563 .hardware_enable = hardware_enable,
7564 .hardware_disable = hardware_disable,
7565 .cpu_has_accelerated_tpr = report_flexpriority,
7566 .has_emulated_msr = vmx_has_emulated_msr,
7568 .vm_size = sizeof(struct kvm_vmx),
7569 .vm_init = vmx_vm_init,
7571 .vcpu_create = vmx_create_vcpu,
7572 .vcpu_free = vmx_free_vcpu,
7573 .vcpu_reset = vmx_vcpu_reset,
7575 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7576 .vcpu_load = vmx_vcpu_load,
7577 .vcpu_put = vmx_vcpu_put,
7579 .update_exception_bitmap = vmx_update_exception_bitmap,
7580 .get_msr_feature = vmx_get_msr_feature,
7581 .get_msr = vmx_get_msr,
7582 .set_msr = vmx_set_msr,
7583 .get_segment_base = vmx_get_segment_base,
7584 .get_segment = vmx_get_segment,
7585 .set_segment = vmx_set_segment,
7586 .get_cpl = vmx_get_cpl,
7587 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7588 .set_cr0 = vmx_set_cr0,
7589 .is_valid_cr4 = vmx_is_valid_cr4,
7590 .set_cr4 = vmx_set_cr4,
7591 .set_efer = vmx_set_efer,
7592 .get_idt = vmx_get_idt,
7593 .set_idt = vmx_set_idt,
7594 .get_gdt = vmx_get_gdt,
7595 .set_gdt = vmx_set_gdt,
7596 .set_dr7 = vmx_set_dr7,
7597 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7598 .cache_reg = vmx_cache_reg,
7599 .get_rflags = vmx_get_rflags,
7600 .set_rflags = vmx_set_rflags,
7601 .get_if_flag = vmx_get_if_flag,
7603 .tlb_flush_all = vmx_flush_tlb_all,
7604 .tlb_flush_current = vmx_flush_tlb_current,
7605 .tlb_flush_gva = vmx_flush_tlb_gva,
7606 .tlb_flush_guest = vmx_flush_tlb_guest,
7608 .run = vmx_vcpu_run,
7609 .handle_exit = vmx_handle_exit,
7610 .skip_emulated_instruction = vmx_skip_emulated_instruction,
7611 .update_emulated_instruction = vmx_update_emulated_instruction,
7612 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7613 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7614 .patch_hypercall = vmx_patch_hypercall,
7615 .set_irq = vmx_inject_irq,
7616 .set_nmi = vmx_inject_nmi,
7617 .queue_exception = vmx_queue_exception,
7618 .cancel_injection = vmx_cancel_injection,
7619 .interrupt_allowed = vmx_interrupt_allowed,
7620 .nmi_allowed = vmx_nmi_allowed,
7621 .get_nmi_mask = vmx_get_nmi_mask,
7622 .set_nmi_mask = vmx_set_nmi_mask,
7623 .enable_nmi_window = vmx_enable_nmi_window,
7624 .enable_irq_window = vmx_enable_irq_window,
7625 .update_cr8_intercept = vmx_update_cr8_intercept,
7626 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7627 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7628 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7629 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7630 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7631 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7632 .hwapic_irr_update = vmx_hwapic_irr_update,
7633 .hwapic_isr_update = vmx_hwapic_isr_update,
7634 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7635 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7636 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7637 .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
7639 .set_tss_addr = vmx_set_tss_addr,
7640 .set_identity_map_addr = vmx_set_identity_map_addr,
7641 .get_mt_mask = vmx_get_mt_mask,
7643 .get_exit_info = vmx_get_exit_info,
7645 .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7647 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7649 .get_l2_tsc_offset = vmx_get_l2_tsc_offset,
7650 .get_l2_tsc_multiplier = vmx_get_l2_tsc_multiplier,
7651 .write_tsc_offset = vmx_write_tsc_offset,
7652 .write_tsc_multiplier = vmx_write_tsc_multiplier,
7654 .load_mmu_pgd = vmx_load_mmu_pgd,
7656 .check_intercept = vmx_check_intercept,
7657 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7659 .request_immediate_exit = vmx_request_immediate_exit,
7661 .sched_in = vmx_sched_in,
7663 .cpu_dirty_log_size = PML_ENTITY_NUM,
7664 .update_cpu_dirty_logging = vmx_update_cpu_dirty_logging,
7666 .pre_block = vmx_pre_block,
7667 .post_block = vmx_post_block,
7669 .pmu_ops = &intel_pmu_ops,
7670 .nested_ops = &vmx_nested_ops,
7672 .update_pi_irte = pi_update_irte,
7673 .start_assignment = vmx_pi_start_assignment,
7675 #ifdef CONFIG_X86_64
7676 .set_hv_timer = vmx_set_hv_timer,
7677 .cancel_hv_timer = vmx_cancel_hv_timer,
7680 .setup_mce = vmx_setup_mce,
7682 .smi_allowed = vmx_smi_allowed,
7683 .enter_smm = vmx_enter_smm,
7684 .leave_smm = vmx_leave_smm,
7685 .enable_smi_window = vmx_enable_smi_window,
7687 .can_emulate_instruction = vmx_can_emulate_instruction,
7688 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7689 .migrate_timers = vmx_migrate_timers,
7691 .msr_filter_changed = vmx_msr_filter_changed,
7692 .complete_emulated_msr = kvm_complete_insn_gp,
7694 .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector,
7697 static __init void vmx_setup_user_return_msrs(void)
7701 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
7702 * will emulate SYSCALL in legacy mode if the vendor string in guest
7703 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
7704 * support this emulation, MSR_STAR is included in the list for i386,
7705 * but is never loaded into hardware. MSR_CSTAR is also never loaded
7706 * into hardware and is here purely for emulation purposes.
7708 const u32 vmx_uret_msrs_list[] = {
7709 #ifdef CONFIG_X86_64
7710 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
7712 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
7717 BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
7719 for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
7720 kvm_add_user_return_msr(vmx_uret_msrs_list[i]);
7723 static __init int hardware_setup(void)
7725 unsigned long host_bndcfgs;
7727 int r, ept_lpage_level;
7730 host_idt_base = dt.address;
7732 vmx_setup_user_return_msrs();
7734 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7737 if (boot_cpu_has(X86_FEATURE_NX))
7738 kvm_enable_efer_bits(EFER_NX);
7740 if (boot_cpu_has(X86_FEATURE_MPX)) {
7741 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7742 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7745 if (!cpu_has_vmx_mpx())
7746 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7747 XFEATURE_MASK_BNDCSR);
7749 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7750 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7753 if (!cpu_has_vmx_ept() ||
7754 !cpu_has_vmx_ept_4levels() ||
7755 !cpu_has_vmx_ept_mt_wb() ||
7756 !cpu_has_vmx_invept_global())
7759 /* NX support is required for shadow paging. */
7760 if (!enable_ept && !boot_cpu_has(X86_FEATURE_NX)) {
7761 pr_err_ratelimited("kvm: NX (Execute Disable) not supported\n");
7765 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7766 enable_ept_ad_bits = 0;
7768 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7769 enable_unrestricted_guest = 0;
7771 if (!cpu_has_vmx_flexpriority())
7772 flexpriority_enabled = 0;
7774 if (!cpu_has_virtual_nmis())
7778 * set_apic_access_page_addr() is used to reload apic access
7779 * page upon invalidation. No need to do anything if not
7780 * using the APIC_ACCESS_ADDR VMCS field.
7782 if (!flexpriority_enabled)
7783 vmx_x86_ops.set_apic_access_page_addr = NULL;
7785 if (!cpu_has_vmx_tpr_shadow())
7786 vmx_x86_ops.update_cr8_intercept = NULL;
7788 #if IS_ENABLED(CONFIG_HYPERV)
7789 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7791 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7792 vmx_x86_ops.tlb_remote_flush_with_range =
7793 hv_remote_flush_tlb_with_range;
7797 if (!cpu_has_vmx_ple()) {
7800 ple_window_grow = 0;
7802 ple_window_shrink = 0;
7805 if (!cpu_has_vmx_apicv())
7808 vmx_x86_ops.sync_pir_to_irr = NULL;
7810 if (cpu_has_vmx_tsc_scaling()) {
7811 kvm_has_tsc_control = true;
7812 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7813 kvm_tsc_scaling_ratio_frac_bits = 48;
7816 kvm_has_bus_lock_exit = cpu_has_vmx_bus_lock_detection();
7818 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7821 kvm_mmu_set_ept_masks(enable_ept_ad_bits,
7822 cpu_has_vmx_ept_execute_only());
7825 ept_lpage_level = 0;
7826 else if (cpu_has_vmx_ept_1g_page())
7827 ept_lpage_level = PG_LEVEL_1G;
7828 else if (cpu_has_vmx_ept_2m_page())
7829 ept_lpage_level = PG_LEVEL_2M;
7831 ept_lpage_level = PG_LEVEL_4K;
7832 kvm_configure_mmu(enable_ept, 0, vmx_get_max_tdp_level(),
7836 * Only enable PML when hardware supports PML feature, and both EPT
7837 * and EPT A/D bit features are enabled -- PML depends on them to work.
7839 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7843 vmx_x86_ops.cpu_dirty_log_size = 0;
7845 if (!cpu_has_vmx_preemption_timer())
7846 enable_preemption_timer = false;
7848 if (enable_preemption_timer) {
7849 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7852 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7853 cpu_preemption_timer_multi =
7854 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7857 use_timer_freq = (u64)tsc_khz * 1000;
7858 use_timer_freq >>= cpu_preemption_timer_multi;
7861 * KVM "disables" the preemption timer by setting it to its max
7862 * value. Don't use the timer if it might cause spurious exits
7863 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7865 if (use_timer_freq > 0xffffffffu / 10)
7866 enable_preemption_timer = false;
7869 if (!enable_preemption_timer) {
7870 vmx_x86_ops.set_hv_timer = NULL;
7871 vmx_x86_ops.cancel_hv_timer = NULL;
7872 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
7875 kvm_mce_cap_supported |= MCG_LMCE_P;
7877 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7879 if (!enable_ept || !cpu_has_vmx_intel_pt())
7880 pt_mode = PT_MODE_SYSTEM;
7882 setup_default_sgx_lepubkeyhash();
7885 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7886 vmx_capability.ept);
7888 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7895 r = alloc_kvm_area();
7897 nested_vmx_hardware_unsetup();
7899 kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler);
7904 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
7905 .cpu_has_kvm_support = cpu_has_kvm_support,
7906 .disabled_by_bios = vmx_disabled_by_bios,
7907 .check_processor_compatibility = vmx_check_processor_compat,
7908 .hardware_setup = hardware_setup,
7910 .runtime_ops = &vmx_x86_ops,
7913 static void vmx_cleanup_l1d_flush(void)
7915 if (vmx_l1d_flush_pages) {
7916 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7917 vmx_l1d_flush_pages = NULL;
7919 /* Restore state so sysfs ignores VMX */
7920 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7923 static void vmx_exit(void)
7925 #ifdef CONFIG_KEXEC_CORE
7926 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7932 #if IS_ENABLED(CONFIG_HYPERV)
7933 if (static_branch_unlikely(&enable_evmcs)) {
7935 struct hv_vp_assist_page *vp_ap;
7937 * Reset everything to support using non-enlightened VMCS
7938 * access later (e.g. when we reload the module with
7939 * enlightened_vmcs=0)
7941 for_each_online_cpu(cpu) {
7942 vp_ap = hv_get_vp_assist_page(cpu);
7947 vp_ap->nested_control.features.directhypercall = 0;
7948 vp_ap->current_nested_vmcs = 0;
7949 vp_ap->enlighten_vmentry = 0;
7952 static_branch_disable(&enable_evmcs);
7955 vmx_cleanup_l1d_flush();
7957 allow_smaller_maxphyaddr = false;
7959 module_exit(vmx_exit);
7961 static int __init vmx_init(void)
7965 #if IS_ENABLED(CONFIG_HYPERV)
7967 * Enlightened VMCS usage should be recommended and the host needs
7968 * to support eVMCS v1 or above. We can also disable eVMCS support
7969 * with module parameter.
7971 if (enlightened_vmcs &&
7972 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7973 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7974 KVM_EVMCS_VERSION) {
7977 /* Check that we have assist pages on all online CPUs */
7978 for_each_online_cpu(cpu) {
7979 if (!hv_get_vp_assist_page(cpu)) {
7980 enlightened_vmcs = false;
7985 if (enlightened_vmcs) {
7986 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7987 static_branch_enable(&enable_evmcs);
7990 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7991 vmx_x86_ops.enable_direct_tlbflush
7992 = hv_enable_direct_tlbflush;
7995 enlightened_vmcs = false;
7999 r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
8000 __alignof__(struct vcpu_vmx), THIS_MODULE);
8005 * Must be called after kvm_init() so enable_ept is properly set
8006 * up. Hand the parameter mitigation value in which was stored in
8007 * the pre module init parser. If no parameter was given, it will
8008 * contain 'auto' which will be turned into the default 'cond'
8011 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8017 for_each_possible_cpu(cpu) {
8018 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8023 #ifdef CONFIG_KEXEC_CORE
8024 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8025 crash_vmclear_local_loaded_vmcss);
8027 vmx_check_vmcs12_offsets();
8030 * Shadow paging doesn't have a (further) performance penalty
8031 * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it
8035 allow_smaller_maxphyaddr = true;
8039 module_init(vmx_init);