1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/highmem.h>
17 #include <linux/hrtimer.h>
18 #include <linux/kernel.h>
19 #include <linux/kvm_host.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/mod_devicetable.h>
24 #include <linux/objtool.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
30 #include <linux/entry-kvm.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/debugreg.h>
38 #include <asm/fpu/api.h>
39 #include <asm/idtentry.h>
41 #include <asm/irq_remapping.h>
42 #include <asm/kexec.h>
43 #include <asm/perf_event.h>
44 #include <asm/mmu_context.h>
45 #include <asm/mshyperv.h>
46 #include <asm/mwait.h>
47 #include <asm/spec-ctrl.h>
48 #include <asm/virtext.h>
51 #include "capabilities.h"
55 #include "kvm_onhyperv.h"
57 #include "kvm_cache_regs.h"
69 MODULE_AUTHOR("Qumranet");
70 MODULE_LICENSE("GPL");
73 static const struct x86_cpu_id vmx_cpu_id[] = {
74 X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
77 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
80 bool __read_mostly enable_vpid = 1;
81 module_param_named(vpid, enable_vpid, bool, 0444);
83 static bool __read_mostly enable_vnmi = 1;
84 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
86 bool __read_mostly flexpriority_enabled = 1;
87 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
89 bool __read_mostly enable_ept = 1;
90 module_param_named(ept, enable_ept, bool, S_IRUGO);
92 bool __read_mostly enable_unrestricted_guest = 1;
93 module_param_named(unrestricted_guest,
94 enable_unrestricted_guest, bool, S_IRUGO);
96 bool __read_mostly enable_ept_ad_bits = 1;
97 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
99 static bool __read_mostly emulate_invalid_guest_state = true;
100 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
102 static bool __read_mostly fasteoi = 1;
103 module_param(fasteoi, bool, S_IRUGO);
105 module_param(enable_apicv, bool, S_IRUGO);
108 * If nested=1, nested virtualization is supported, i.e., guests may use
109 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
110 * use VMX instructions.
112 static bool __read_mostly nested = 1;
113 module_param(nested, bool, S_IRUGO);
115 bool __read_mostly enable_pml = 1;
116 module_param_named(pml, enable_pml, bool, S_IRUGO);
118 static bool __read_mostly dump_invalid_vmcs = 0;
119 module_param(dump_invalid_vmcs, bool, 0644);
121 #define MSR_BITMAP_MODE_X2APIC 1
122 #define MSR_BITMAP_MODE_X2APIC_APICV 2
124 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
126 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
127 static int __read_mostly cpu_preemption_timer_multi;
128 static bool __read_mostly enable_preemption_timer = 1;
130 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
133 extern bool __read_mostly allow_smaller_maxphyaddr;
134 module_param(allow_smaller_maxphyaddr, bool, S_IRUGO);
136 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
137 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
138 #define KVM_VM_CR0_ALWAYS_ON \
139 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
141 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
142 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
143 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
145 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
147 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
148 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
149 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
150 RTIT_STATUS_BYTECNT))
153 * List of MSRs that can be directly passed to the guest.
154 * In addition to these x2apic and PT MSRs are handled specially.
156 static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = {
165 MSR_IA32_SYSENTER_CS,
166 MSR_IA32_SYSENTER_ESP,
167 MSR_IA32_SYSENTER_EIP,
169 MSR_CORE_C3_RESIDENCY,
170 MSR_CORE_C6_RESIDENCY,
171 MSR_CORE_C7_RESIDENCY,
175 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
176 * ple_gap: upper bound on the amount of time between two successive
177 * executions of PAUSE in a loop. Also indicate if ple enabled.
178 * According to test, this time is usually smaller than 128 cycles.
179 * ple_window: upper bound on the amount of time a guest is allowed to execute
180 * in a PAUSE loop. Tests indicate that most spinlocks are held for
181 * less than 2^12 cycles
182 * Time is measured based on a counter that runs at the same rate as the TSC,
183 * refer SDM volume 3b section 21.6.13 & 22.1.3.
185 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
186 module_param(ple_gap, uint, 0444);
188 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
189 module_param(ple_window, uint, 0444);
191 /* Default doubles per-vcpu window every exit. */
192 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
193 module_param(ple_window_grow, uint, 0444);
195 /* Default resets per-vcpu window every exit to ple_window. */
196 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
197 module_param(ple_window_shrink, uint, 0444);
199 /* Default is to compute the maximum so we can never overflow. */
200 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
201 module_param(ple_window_max, uint, 0444);
203 /* Default is SYSTEM mode, 1 for host-guest mode */
204 int __read_mostly pt_mode = PT_MODE_SYSTEM;
205 module_param(pt_mode, int, S_IRUGO);
207 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
208 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
209 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
211 /* Storage for pre module init parameter parsing */
212 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
214 static const struct {
217 } vmentry_l1d_param[] = {
218 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
219 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
220 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
221 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
222 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
223 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
226 #define L1D_CACHE_ORDER 4
227 static void *vmx_l1d_flush_pages;
229 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
234 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
235 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
240 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
244 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
247 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
248 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
249 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
254 /* If set to auto use the default l1tf mitigation method */
255 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
256 switch (l1tf_mitigation) {
257 case L1TF_MITIGATION_OFF:
258 l1tf = VMENTER_L1D_FLUSH_NEVER;
260 case L1TF_MITIGATION_FLUSH_NOWARN:
261 case L1TF_MITIGATION_FLUSH:
262 case L1TF_MITIGATION_FLUSH_NOSMT:
263 l1tf = VMENTER_L1D_FLUSH_COND;
265 case L1TF_MITIGATION_FULL:
266 case L1TF_MITIGATION_FULL_FORCE:
267 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
270 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
271 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
274 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
275 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
277 * This allocation for vmx_l1d_flush_pages is not tied to a VM
278 * lifetime and so should not be charged to a memcg.
280 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
283 vmx_l1d_flush_pages = page_address(page);
286 * Initialize each page with a different pattern in
287 * order to protect against KSM in the nested
288 * virtualization case.
290 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
291 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
296 l1tf_vmx_mitigation = l1tf;
298 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
299 static_branch_enable(&vmx_l1d_should_flush);
301 static_branch_disable(&vmx_l1d_should_flush);
303 if (l1tf == VMENTER_L1D_FLUSH_COND)
304 static_branch_enable(&vmx_l1d_flush_cond);
306 static_branch_disable(&vmx_l1d_flush_cond);
310 static int vmentry_l1d_flush_parse(const char *s)
315 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
316 if (vmentry_l1d_param[i].for_parse &&
317 sysfs_streq(s, vmentry_l1d_param[i].option))
324 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
328 l1tf = vmentry_l1d_flush_parse(s);
332 if (!boot_cpu_has(X86_BUG_L1TF))
336 * Has vmx_init() run already? If not then this is the pre init
337 * parameter parsing. In that case just store the value and let
338 * vmx_init() do the proper setup after enable_ept has been
341 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
342 vmentry_l1d_flush_param = l1tf;
346 mutex_lock(&vmx_l1d_flush_mutex);
347 ret = vmx_setup_l1d_flush(l1tf);
348 mutex_unlock(&vmx_l1d_flush_mutex);
352 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
354 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
355 return sprintf(s, "???\n");
357 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
360 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
361 .set = vmentry_l1d_flush_set,
362 .get = vmentry_l1d_flush_get,
364 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
366 static u32 vmx_segment_access_rights(struct kvm_segment *var);
368 void vmx_vmexit(void);
370 #define vmx_insn_failed(fmt...) \
373 pr_warn_ratelimited(fmt); \
376 asmlinkage void vmread_error(unsigned long field, bool fault)
379 kvm_spurious_fault();
381 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
384 noinline void vmwrite_error(unsigned long field, unsigned long value)
386 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
387 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
390 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
392 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
395 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
397 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
400 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
402 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
406 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
408 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
412 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
413 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
415 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
416 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
418 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
420 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
421 static DEFINE_SPINLOCK(vmx_vpid_lock);
423 struct vmcs_config vmcs_config;
424 struct vmx_capability vmx_capability;
426 #define VMX_SEGMENT_FIELD(seg) \
427 [VCPU_SREG_##seg] = { \
428 .selector = GUEST_##seg##_SELECTOR, \
429 .base = GUEST_##seg##_BASE, \
430 .limit = GUEST_##seg##_LIMIT, \
431 .ar_bytes = GUEST_##seg##_AR_BYTES, \
434 static const struct kvm_vmx_segment_field {
439 } kvm_vmx_segment_fields[] = {
440 VMX_SEGMENT_FIELD(CS),
441 VMX_SEGMENT_FIELD(DS),
442 VMX_SEGMENT_FIELD(ES),
443 VMX_SEGMENT_FIELD(FS),
444 VMX_SEGMENT_FIELD(GS),
445 VMX_SEGMENT_FIELD(SS),
446 VMX_SEGMENT_FIELD(TR),
447 VMX_SEGMENT_FIELD(LDTR),
450 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
452 vmx->segment_cache.bitmask = 0;
455 static unsigned long host_idt_base;
457 #if IS_ENABLED(CONFIG_HYPERV)
458 static bool __read_mostly enlightened_vmcs = true;
459 module_param(enlightened_vmcs, bool, 0444);
461 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
463 struct hv_enlightened_vmcs *evmcs;
464 struct hv_partition_assist_pg **p_hv_pa_pg =
465 &to_kvm_hv(vcpu->kvm)->hv_pa_pg;
467 * Synthetic VM-Exit is not enabled in current code and so All
468 * evmcs in singe VM shares same assist page.
471 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
476 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
478 evmcs->partition_assist_page =
480 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
481 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
486 #endif /* IS_ENABLED(CONFIG_HYPERV) */
489 * Comment's format: document - errata name - stepping - processor name.
491 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
493 static u32 vmx_preemption_cpu_tfms[] = {
494 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
496 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
497 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
498 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
500 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
502 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
503 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
505 * 320767.pdf - AAP86 - B1 -
506 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
509 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
511 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
513 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
515 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
516 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
517 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
519 /* Xeon E3-1220 V2 */
523 static inline bool cpu_has_broken_vmx_preemption_timer(void)
525 u32 eax = cpuid_eax(0x00000001), i;
527 /* Clear the reserved bits */
528 eax &= ~(0x3U << 14 | 0xfU << 28);
529 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
530 if (eax == vmx_preemption_cpu_tfms[i])
536 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
538 return flexpriority_enabled && lapic_in_kernel(vcpu);
541 static inline bool report_flexpriority(void)
543 return flexpriority_enabled;
546 static int possible_passthrough_msr_slot(u32 msr)
550 for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++)
551 if (vmx_possible_passthrough_msrs[i] == msr)
557 static bool is_valid_passthrough_msr(u32 msr)
562 case 0x800 ... 0x8ff:
563 /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */
565 case MSR_IA32_RTIT_STATUS:
566 case MSR_IA32_RTIT_OUTPUT_BASE:
567 case MSR_IA32_RTIT_OUTPUT_MASK:
568 case MSR_IA32_RTIT_CR3_MATCH:
569 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
570 /* PT MSRs. These are handled in pt_update_intercept_for_msr() */
573 case MSR_LBR_INFO_0 ... MSR_LBR_INFO_0 + 31:
574 case MSR_LBR_NHM_FROM ... MSR_LBR_NHM_FROM + 31:
575 case MSR_LBR_NHM_TO ... MSR_LBR_NHM_TO + 31:
576 case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8:
577 case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8:
578 /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */
582 r = possible_passthrough_msr_slot(msr) != -ENOENT;
584 WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr);
589 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
593 i = kvm_find_user_return_msr(msr);
595 return &vmx->guest_uret_msrs[i];
599 static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx,
600 struct vmx_uret_msr *msr, u64 data)
602 unsigned int slot = msr - vmx->guest_uret_msrs;
605 u64 old_msr_data = msr->data;
607 if (msr->load_into_hardware) {
609 ret = kvm_set_user_return_msr(slot, msr->data, msr->mask);
612 msr->data = old_msr_data;
617 #ifdef CONFIG_KEXEC_CORE
618 static void crash_vmclear_local_loaded_vmcss(void)
620 int cpu = raw_smp_processor_id();
621 struct loaded_vmcs *v;
623 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
624 loaded_vmcss_on_cpu_link)
627 #endif /* CONFIG_KEXEC_CORE */
629 static void __loaded_vmcs_clear(void *arg)
631 struct loaded_vmcs *loaded_vmcs = arg;
632 int cpu = raw_smp_processor_id();
634 if (loaded_vmcs->cpu != cpu)
635 return; /* vcpu migration can race with cpu offline */
636 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
637 per_cpu(current_vmcs, cpu) = NULL;
639 vmcs_clear(loaded_vmcs->vmcs);
640 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
641 vmcs_clear(loaded_vmcs->shadow_vmcs);
643 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
646 * Ensure all writes to loaded_vmcs, including deleting it from its
647 * current percpu list, complete before setting loaded_vmcs->vcpu to
648 * -1, otherwise a different cpu can see vcpu == -1 first and add
649 * loaded_vmcs to its percpu list before it's deleted from this cpu's
650 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
654 loaded_vmcs->cpu = -1;
655 loaded_vmcs->launched = 0;
658 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
660 int cpu = loaded_vmcs->cpu;
663 smp_call_function_single(cpu,
664 __loaded_vmcs_clear, loaded_vmcs, 1);
667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
671 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
673 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
674 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
675 vmx->segment_cache.bitmask = 0;
677 ret = vmx->segment_cache.bitmask & mask;
678 vmx->segment_cache.bitmask |= mask;
682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
684 u16 *p = &vmx->segment_cache.seg[seg].selector;
686 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
687 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
693 ulong *p = &vmx->segment_cache.seg[seg].base;
695 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
696 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
702 u32 *p = &vmx->segment_cache.seg[seg].limit;
704 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
705 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
711 u32 *p = &vmx->segment_cache.seg[seg].ar;
713 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
714 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
718 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu)
722 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
723 (1u << DB_VECTOR) | (1u << AC_VECTOR);
725 * Guest access to VMware backdoor ports could legitimately
726 * trigger #GP because of TSS I/O permission bitmap.
727 * We intercept those #GP and allow access to them anyway
730 if (enable_vmware_backdoor)
731 eb |= (1u << GP_VECTOR);
732 if ((vcpu->guest_debug &
733 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
734 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
735 eb |= 1u << BP_VECTOR;
736 if (to_vmx(vcpu)->rmode.vm86_active)
738 if (!vmx_need_pf_intercept(vcpu))
739 eb &= ~(1u << PF_VECTOR);
741 /* When we are running a nested L2 guest and L1 specified for it a
742 * certain exception bitmap, we must trap the same exceptions and pass
743 * them to L1. When running L2, we will only handle the exceptions
744 * specified above if L1 did not want them.
746 if (is_guest_mode(vcpu))
747 eb |= get_vmcs12(vcpu)->exception_bitmap;
749 int mask = 0, match = 0;
751 if (enable_ept && (eb & (1u << PF_VECTOR))) {
753 * If EPT is enabled, #PF is currently only intercepted
754 * if MAXPHYADDR is smaller on the guest than on the
755 * host. In that case we only care about present,
756 * non-reserved faults. For vmcs02, however, PFEC_MASK
757 * and PFEC_MATCH are set in prepare_vmcs02_rare.
759 mask = PFERR_PRESENT_MASK | PFERR_RSVD_MASK;
760 match = PFERR_PRESENT_MASK;
762 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
763 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, match);
766 vmcs_write32(EXCEPTION_BITMAP, eb);
770 * Check if MSR is intercepted for currently loaded MSR bitmap.
772 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
774 unsigned long *msr_bitmap;
775 int f = sizeof(unsigned long);
777 if (!cpu_has_vmx_msr_bitmap())
780 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
783 return !!test_bit(msr, msr_bitmap + 0x800 / f);
784 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
786 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
792 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
793 unsigned long entry, unsigned long exit)
795 vm_entry_controls_clearbit(vmx, entry);
796 vm_exit_controls_clearbit(vmx, exit);
799 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr)
803 for (i = 0; i < m->nr; ++i) {
804 if (m->val[i].index == msr)
810 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
813 struct msr_autoload *m = &vmx->msr_autoload;
817 if (cpu_has_load_ia32_efer()) {
818 clear_atomic_switch_msr_special(vmx,
819 VM_ENTRY_LOAD_IA32_EFER,
820 VM_EXIT_LOAD_IA32_EFER);
824 case MSR_CORE_PERF_GLOBAL_CTRL:
825 if (cpu_has_load_perf_global_ctrl()) {
826 clear_atomic_switch_msr_special(vmx,
827 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
828 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
833 i = vmx_find_loadstore_msr_slot(&m->guest, msr);
837 m->guest.val[i] = m->guest.val[m->guest.nr];
838 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
841 i = vmx_find_loadstore_msr_slot(&m->host, msr);
846 m->host.val[i] = m->host.val[m->host.nr];
847 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
850 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
851 unsigned long entry, unsigned long exit,
852 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
853 u64 guest_val, u64 host_val)
855 vmcs_write64(guest_val_vmcs, guest_val);
856 if (host_val_vmcs != HOST_IA32_EFER)
857 vmcs_write64(host_val_vmcs, host_val);
858 vm_entry_controls_setbit(vmx, entry);
859 vm_exit_controls_setbit(vmx, exit);
862 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
863 u64 guest_val, u64 host_val, bool entry_only)
866 struct msr_autoload *m = &vmx->msr_autoload;
870 if (cpu_has_load_ia32_efer()) {
871 add_atomic_switch_msr_special(vmx,
872 VM_ENTRY_LOAD_IA32_EFER,
873 VM_EXIT_LOAD_IA32_EFER,
876 guest_val, host_val);
880 case MSR_CORE_PERF_GLOBAL_CTRL:
881 if (cpu_has_load_perf_global_ctrl()) {
882 add_atomic_switch_msr_special(vmx,
883 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
884 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
885 GUEST_IA32_PERF_GLOBAL_CTRL,
886 HOST_IA32_PERF_GLOBAL_CTRL,
887 guest_val, host_val);
891 case MSR_IA32_PEBS_ENABLE:
892 /* PEBS needs a quiescent period after being disabled (to write
893 * a record). Disabling PEBS through VMX MSR swapping doesn't
894 * provide that period, so a CPU could write host's record into
897 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
900 i = vmx_find_loadstore_msr_slot(&m->guest, msr);
902 j = vmx_find_loadstore_msr_slot(&m->host, msr);
904 if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) ||
905 (j < 0 && m->host.nr == MAX_NR_LOADSTORE_MSRS)) {
906 printk_once(KERN_WARNING "Not enough msr switch entries. "
907 "Can't add msr %x\n", msr);
912 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
914 m->guest.val[i].index = msr;
915 m->guest.val[i].value = guest_val;
922 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
924 m->host.val[j].index = msr;
925 m->host.val[j].value = host_val;
928 static bool update_transition_efer(struct vcpu_vmx *vmx)
930 u64 guest_efer = vmx->vcpu.arch.efer;
934 /* Shadow paging assumes NX to be available. */
936 guest_efer |= EFER_NX;
939 * LMA and LME handled by hardware; SCE meaningless outside long mode.
941 ignore_bits |= EFER_SCE;
943 ignore_bits |= EFER_LMA | EFER_LME;
944 /* SCE is meaningful only in long mode on Intel */
945 if (guest_efer & EFER_LMA)
946 ignore_bits &= ~(u64)EFER_SCE;
950 * On EPT, we can't emulate NX, so we must switch EFER atomically.
951 * On CPUs that support "load IA32_EFER", always switch EFER
952 * atomically, since it's faster than switching it manually.
954 if (cpu_has_load_ia32_efer() ||
955 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
956 if (!(guest_efer & EFER_LMA))
957 guest_efer &= ~EFER_LME;
958 if (guest_efer != host_efer)
959 add_atomic_switch_msr(vmx, MSR_EFER,
960 guest_efer, host_efer, false);
962 clear_atomic_switch_msr(vmx, MSR_EFER);
966 i = kvm_find_user_return_msr(MSR_EFER);
970 clear_atomic_switch_msr(vmx, MSR_EFER);
972 guest_efer &= ~ignore_bits;
973 guest_efer |= host_efer & ignore_bits;
975 vmx->guest_uret_msrs[i].data = guest_efer;
976 vmx->guest_uret_msrs[i].mask = ~ignore_bits;
983 * On 32-bit kernels, VM exits still load the FS and GS bases from the
984 * VMCS rather than the segment table. KVM uses this helper to figure
985 * out the current bases to poke them into the VMCS before entry.
987 static unsigned long segment_base(u16 selector)
989 struct desc_struct *table;
992 if (!(selector & ~SEGMENT_RPL_MASK))
995 table = get_current_gdt_ro();
997 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
998 u16 ldt_selector = kvm_read_ldt();
1000 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1003 table = (struct desc_struct *)segment_base(ldt_selector);
1005 v = get_desc_base(&table[selector >> 3]);
1010 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1012 return vmx_pt_mode_is_host_guest() &&
1013 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1016 static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base)
1018 /* The base must be 128-byte aligned and a legal physical address. */
1019 return kvm_vcpu_is_legal_aligned_gpa(vcpu, base, 128);
1022 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1026 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1027 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1028 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1029 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1030 for (i = 0; i < addr_range; i++) {
1031 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1032 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1036 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1040 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1041 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1042 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1043 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1044 for (i = 0; i < addr_range; i++) {
1045 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1046 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1050 static void pt_guest_enter(struct vcpu_vmx *vmx)
1052 if (vmx_pt_mode_is_system())
1056 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1057 * Save host state before VM entry.
1059 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1060 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1061 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1062 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1063 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1067 static void pt_guest_exit(struct vcpu_vmx *vmx)
1069 if (vmx_pt_mode_is_system())
1072 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1073 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1074 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1078 * KVM requires VM_EXIT_CLEAR_IA32_RTIT_CTL to expose PT to the guest,
1079 * i.e. RTIT_CTL is always cleared on VM-Exit. Restore it if necessary.
1081 if (vmx->pt_desc.host.ctl)
1082 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1085 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1086 unsigned long fs_base, unsigned long gs_base)
1088 if (unlikely(fs_sel != host->fs_sel)) {
1090 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1092 vmcs_write16(HOST_FS_SELECTOR, 0);
1093 host->fs_sel = fs_sel;
1095 if (unlikely(gs_sel != host->gs_sel)) {
1097 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1099 vmcs_write16(HOST_GS_SELECTOR, 0);
1100 host->gs_sel = gs_sel;
1102 if (unlikely(fs_base != host->fs_base)) {
1103 vmcs_writel(HOST_FS_BASE, fs_base);
1104 host->fs_base = fs_base;
1106 if (unlikely(gs_base != host->gs_base)) {
1107 vmcs_writel(HOST_GS_BASE, gs_base);
1108 host->gs_base = gs_base;
1112 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1114 struct vcpu_vmx *vmx = to_vmx(vcpu);
1115 struct vmcs_host_state *host_state;
1116 #ifdef CONFIG_X86_64
1117 int cpu = raw_smp_processor_id();
1119 unsigned long fs_base, gs_base;
1123 vmx->req_immediate_exit = false;
1126 * Note that guest MSRs to be saved/restored can also be changed
1127 * when guest state is loaded. This happens when guest transitions
1128 * to/from long-mode by setting MSR_EFER.LMA.
1130 if (!vmx->guest_uret_msrs_loaded) {
1131 vmx->guest_uret_msrs_loaded = true;
1132 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
1133 if (!vmx->guest_uret_msrs[i].load_into_hardware)
1136 kvm_set_user_return_msr(i,
1137 vmx->guest_uret_msrs[i].data,
1138 vmx->guest_uret_msrs[i].mask);
1142 if (vmx->nested.need_vmcs12_to_shadow_sync)
1143 nested_sync_vmcs12_to_shadow(vcpu);
1145 if (vmx->guest_state_loaded)
1148 host_state = &vmx->loaded_vmcs->host_state;
1151 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1152 * allow segment selectors with cpl > 0 or ti == 1.
1154 host_state->ldt_sel = kvm_read_ldt();
1156 #ifdef CONFIG_X86_64
1157 savesegment(ds, host_state->ds_sel);
1158 savesegment(es, host_state->es_sel);
1160 gs_base = cpu_kernelmode_gs_base(cpu);
1161 if (likely(is_64bit_mm(current->mm))) {
1162 current_save_fsgs();
1163 fs_sel = current->thread.fsindex;
1164 gs_sel = current->thread.gsindex;
1165 fs_base = current->thread.fsbase;
1166 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1168 savesegment(fs, fs_sel);
1169 savesegment(gs, gs_sel);
1170 fs_base = read_msr(MSR_FS_BASE);
1171 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1174 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1176 savesegment(fs, fs_sel);
1177 savesegment(gs, gs_sel);
1178 fs_base = segment_base(fs_sel);
1179 gs_base = segment_base(gs_sel);
1182 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1183 vmx->guest_state_loaded = true;
1186 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1188 struct vmcs_host_state *host_state;
1190 if (!vmx->guest_state_loaded)
1193 host_state = &vmx->loaded_vmcs->host_state;
1195 ++vmx->vcpu.stat.host_state_reload;
1197 #ifdef CONFIG_X86_64
1198 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1200 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1201 kvm_load_ldt(host_state->ldt_sel);
1202 #ifdef CONFIG_X86_64
1203 load_gs_index(host_state->gs_sel);
1205 loadsegment(gs, host_state->gs_sel);
1208 if (host_state->fs_sel & 7)
1209 loadsegment(fs, host_state->fs_sel);
1210 #ifdef CONFIG_X86_64
1211 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1212 loadsegment(ds, host_state->ds_sel);
1213 loadsegment(es, host_state->es_sel);
1216 invalidate_tss_limit();
1217 #ifdef CONFIG_X86_64
1218 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1220 load_fixmap_gdt(raw_smp_processor_id());
1221 vmx->guest_state_loaded = false;
1222 vmx->guest_uret_msrs_loaded = false;
1225 #ifdef CONFIG_X86_64
1226 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1229 if (vmx->guest_state_loaded)
1230 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1232 return vmx->msr_guest_kernel_gs_base;
1235 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1238 if (vmx->guest_state_loaded)
1239 wrmsrl(MSR_KERNEL_GS_BASE, data);
1241 vmx->msr_guest_kernel_gs_base = data;
1245 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1246 struct loaded_vmcs *buddy)
1248 struct vcpu_vmx *vmx = to_vmx(vcpu);
1249 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1252 if (!already_loaded) {
1253 loaded_vmcs_clear(vmx->loaded_vmcs);
1254 local_irq_disable();
1257 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1258 * this cpu's percpu list, otherwise it may not yet be deleted
1259 * from its previous cpu's percpu list. Pairs with the
1260 * smb_wmb() in __loaded_vmcs_clear().
1264 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1265 &per_cpu(loaded_vmcss_on_cpu, cpu));
1269 prev = per_cpu(current_vmcs, cpu);
1270 if (prev != vmx->loaded_vmcs->vmcs) {
1271 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1272 vmcs_load(vmx->loaded_vmcs->vmcs);
1275 * No indirect branch prediction barrier needed when switching
1276 * the active VMCS within a guest, e.g. on nested VM-Enter.
1277 * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1279 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1280 indirect_branch_prediction_barrier();
1283 if (!already_loaded) {
1284 void *gdt = get_current_gdt_ro();
1285 unsigned long sysenter_esp;
1288 * Flush all EPTP/VPID contexts, the new pCPU may have stale
1289 * TLB entries from its previous association with the vCPU.
1291 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1294 * Linux uses per-cpu TSS and GDT, so set these when switching
1295 * processors. See 22.2.4.
1297 vmcs_writel(HOST_TR_BASE,
1298 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1299 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1301 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1302 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1304 vmx->loaded_vmcs->cpu = cpu;
1309 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1310 * vcpu mutex is already taken.
1312 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1314 struct vcpu_vmx *vmx = to_vmx(vcpu);
1316 vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1318 vmx_vcpu_pi_load(vcpu, cpu);
1320 vmx->host_debugctlmsr = get_debugctlmsr();
1323 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1325 vmx_vcpu_pi_put(vcpu);
1327 vmx_prepare_switch_to_host(to_vmx(vcpu));
1330 bool vmx_emulation_required(struct kvm_vcpu *vcpu)
1332 return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu);
1335 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1337 struct vcpu_vmx *vmx = to_vmx(vcpu);
1338 unsigned long rflags, save_rflags;
1340 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1341 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1342 rflags = vmcs_readl(GUEST_RFLAGS);
1343 if (vmx->rmode.vm86_active) {
1344 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1345 save_rflags = vmx->rmode.save_rflags;
1346 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1348 vmx->rflags = rflags;
1353 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1355 struct vcpu_vmx *vmx = to_vmx(vcpu);
1356 unsigned long old_rflags;
1358 if (is_unrestricted_guest(vcpu)) {
1359 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1360 vmx->rflags = rflags;
1361 vmcs_writel(GUEST_RFLAGS, rflags);
1365 old_rflags = vmx_get_rflags(vcpu);
1366 vmx->rflags = rflags;
1367 if (vmx->rmode.vm86_active) {
1368 vmx->rmode.save_rflags = rflags;
1369 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1371 vmcs_writel(GUEST_RFLAGS, rflags);
1373 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1374 vmx->emulation_required = vmx_emulation_required(vcpu);
1377 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1379 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1382 if (interruptibility & GUEST_INTR_STATE_STI)
1383 ret |= KVM_X86_SHADOW_INT_STI;
1384 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1385 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1390 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1392 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1393 u32 interruptibility = interruptibility_old;
1395 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1397 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1398 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1399 else if (mask & KVM_X86_SHADOW_INT_STI)
1400 interruptibility |= GUEST_INTR_STATE_STI;
1402 if ((interruptibility != interruptibility_old))
1403 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1406 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1408 struct vcpu_vmx *vmx = to_vmx(vcpu);
1409 unsigned long value;
1412 * Any MSR write that attempts to change bits marked reserved will
1415 if (data & vmx->pt_desc.ctl_bitmask)
1419 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1420 * result in a #GP unless the same write also clears TraceEn.
1422 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1423 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1427 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1428 * and FabricEn would cause #GP, if
1429 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1431 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1432 !(data & RTIT_CTL_FABRIC_EN) &&
1433 !intel_pt_validate_cap(vmx->pt_desc.caps,
1434 PT_CAP_single_range_output))
1438 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1439 * utilize encodings marked reserved will cause a #GP fault.
1441 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1442 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1443 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1444 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1446 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1447 PT_CAP_cycle_thresholds);
1448 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1449 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1450 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1452 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1453 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1454 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1455 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1459 * If ADDRx_CFG is reserved or the encodings is >2 will
1460 * cause a #GP fault.
1462 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1463 if ((value && (vmx->pt_desc.num_address_ranges < 1)) || (value > 2))
1465 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1466 if ((value && (vmx->pt_desc.num_address_ranges < 2)) || (value > 2))
1468 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1469 if ((value && (vmx->pt_desc.num_address_ranges < 3)) || (value > 2))
1471 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1472 if ((value && (vmx->pt_desc.num_address_ranges < 4)) || (value > 2))
1478 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
1481 * Emulation of instructions in SGX enclaves is impossible as RIP does
1482 * not point tthe failing instruction, and even if it did, the code
1483 * stream is inaccessible. Inject #UD instead of exiting to userspace
1484 * so that guest userspace can't DoS the guest simply by triggering
1485 * emulation (enclaves are CPL3 only).
1487 if (to_vmx(vcpu)->exit_reason.enclave_mode) {
1488 kvm_queue_exception(vcpu, UD_VECTOR);
1494 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1496 union vmx_exit_reason exit_reason = to_vmx(vcpu)->exit_reason;
1497 unsigned long rip, orig_rip;
1501 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1502 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1503 * set when EPT misconfig occurs. In practice, real hardware updates
1504 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1505 * (namely Hyper-V) don't set it due to it being undefined behavior,
1506 * i.e. we end up advancing IP with some random value.
1508 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1509 exit_reason.basic != EXIT_REASON_EPT_MISCONFIG) {
1510 instr_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1513 * Emulating an enclave's instructions isn't supported as KVM
1514 * cannot access the enclave's memory or its true RIP, e.g. the
1515 * vmcs.GUEST_RIP points at the exit point of the enclave, not
1516 * the RIP that actually triggered the VM-Exit. But, because
1517 * most instructions that cause VM-Exit will #UD in an enclave,
1518 * most instruction-based VM-Exits simply do not occur.
1520 * There are a few exceptions, notably the debug instructions
1521 * INT1ICEBRK and INT3, as they are allowed in debug enclaves
1522 * and generate #DB/#BP as expected, which KVM might intercept.
1523 * But again, the CPU does the dirty work and saves an instr
1524 * length of zero so VMMs don't shoot themselves in the foot.
1525 * WARN if KVM tries to skip a non-zero length instruction on
1526 * a VM-Exit from an enclave.
1531 WARN(exit_reason.enclave_mode,
1532 "KVM: skipping instruction after SGX enclave VM-Exit");
1534 orig_rip = kvm_rip_read(vcpu);
1535 rip = orig_rip + instr_len;
1536 #ifdef CONFIG_X86_64
1538 * We need to mask out the high 32 bits of RIP if not in 64-bit
1539 * mode, but just finding out that we are in 64-bit mode is
1540 * quite expensive. Only do it if there was a carry.
1542 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1545 kvm_rip_write(vcpu, rip);
1547 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1552 /* skipping an emulated instruction also counts */
1553 vmx_set_interrupt_shadow(vcpu, 0);
1559 * Recognizes a pending MTF VM-exit and records the nested state for later
1562 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1564 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1565 struct vcpu_vmx *vmx = to_vmx(vcpu);
1567 if (!is_guest_mode(vcpu))
1571 * Per the SDM, MTF takes priority over debug-trap exceptions besides
1572 * T-bit traps. As instruction emulation is completed (i.e. at the
1573 * instruction boundary), any #DB exception pending delivery must be a
1574 * debug-trap. Record the pending MTF state to be delivered in
1575 * vmx_check_nested_events().
1577 if (nested_cpu_has_mtf(vmcs12) &&
1578 (!vcpu->arch.exception.pending ||
1579 vcpu->arch.exception.nr == DB_VECTOR))
1580 vmx->nested.mtf_pending = true;
1582 vmx->nested.mtf_pending = false;
1585 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1587 vmx_update_emulated_instruction(vcpu);
1588 return skip_emulated_instruction(vcpu);
1591 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1594 * Ensure that we clear the HLT state in the VMCS. We don't need to
1595 * explicitly skip the instruction because if the HLT state is set,
1596 * then the instruction is already executing and RIP has already been
1599 if (kvm_hlt_in_guest(vcpu->kvm) &&
1600 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1601 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1604 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1606 struct vcpu_vmx *vmx = to_vmx(vcpu);
1607 unsigned nr = vcpu->arch.exception.nr;
1608 bool has_error_code = vcpu->arch.exception.has_error_code;
1609 u32 error_code = vcpu->arch.exception.error_code;
1610 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1612 kvm_deliver_exception_payload(vcpu);
1614 if (has_error_code) {
1615 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1616 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1619 if (vmx->rmode.vm86_active) {
1621 if (kvm_exception_is_soft(nr))
1622 inc_eip = vcpu->arch.event_exit_inst_len;
1623 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1627 WARN_ON_ONCE(vmx->emulation_required);
1629 if (kvm_exception_is_soft(nr)) {
1630 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1631 vmx->vcpu.arch.event_exit_inst_len);
1632 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1634 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1636 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1638 vmx_clear_hlt(vcpu);
1641 static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr,
1642 bool load_into_hardware)
1644 struct vmx_uret_msr *uret_msr;
1646 uret_msr = vmx_find_uret_msr(vmx, msr);
1650 uret_msr->load_into_hardware = load_into_hardware;
1654 * Configuring user return MSRs to automatically save, load, and restore MSRs
1655 * that need to be shoved into hardware when running the guest. Note, omitting
1656 * an MSR here does _NOT_ mean it's not emulated, only that it will not be
1657 * loaded into hardware when running the guest.
1659 static void vmx_setup_uret_msrs(struct vcpu_vmx *vmx)
1661 #ifdef CONFIG_X86_64
1662 bool load_syscall_msrs;
1665 * The SYSCALL MSRs are only needed on long mode guests, and only
1666 * when EFER.SCE is set.
1668 load_syscall_msrs = is_long_mode(&vmx->vcpu) &&
1669 (vmx->vcpu.arch.efer & EFER_SCE);
1671 vmx_setup_uret_msr(vmx, MSR_STAR, load_syscall_msrs);
1672 vmx_setup_uret_msr(vmx, MSR_LSTAR, load_syscall_msrs);
1673 vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK, load_syscall_msrs);
1675 vmx_setup_uret_msr(vmx, MSR_EFER, update_transition_efer(vmx));
1677 vmx_setup_uret_msr(vmx, MSR_TSC_AUX,
1678 guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP) ||
1679 guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDPID));
1682 * hle=0, rtm=0, tsx_ctrl=1 can be found with some combinations of new
1683 * kernel and old userspace. If those guests run on a tsx=off host, do
1684 * allow guests to use TSX_CTRL, but don't change the value in hardware
1685 * so that TSX remains always disabled.
1687 vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL, boot_cpu_has(X86_FEATURE_RTM));
1690 * The set of MSRs to load may have changed, reload MSRs before the
1693 vmx->guest_uret_msrs_loaded = false;
1696 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1698 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1700 if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING))
1701 return vmcs12->tsc_offset;
1706 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1708 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1710 if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING) &&
1711 nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
1712 return vmcs12->tsc_multiplier;
1714 return kvm_default_tsc_scaling_ratio;
1717 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1719 vmcs_write64(TSC_OFFSET, offset);
1722 static void vmx_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1724 vmcs_write64(TSC_MULTIPLIER, multiplier);
1728 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1729 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1730 * all guests if the "nested" module option is off, and can also be disabled
1731 * for a single guest by disabling its VMX cpuid bit.
1733 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1735 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1738 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1741 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1743 return !(val & ~valid_bits);
1746 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1748 switch (msr->index) {
1749 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1752 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1753 case MSR_IA32_PERF_CAPABILITIES:
1754 msr->data = vmx_get_perf_capabilities();
1757 return KVM_MSR_RET_INVALID;
1762 * Reads an msr value (of 'msr_index') into 'pdata'.
1763 * Returns 0 on success, non-0 otherwise.
1764 * Assumes vcpu_load() was already called.
1766 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1768 struct vcpu_vmx *vmx = to_vmx(vcpu);
1769 struct vmx_uret_msr *msr;
1772 switch (msr_info->index) {
1773 #ifdef CONFIG_X86_64
1775 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1778 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1780 case MSR_KERNEL_GS_BASE:
1781 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1785 return kvm_get_msr_common(vcpu, msr_info);
1786 case MSR_IA32_TSX_CTRL:
1787 if (!msr_info->host_initiated &&
1788 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1791 case MSR_IA32_UMWAIT_CONTROL:
1792 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1795 msr_info->data = vmx->msr_ia32_umwait_control;
1797 case MSR_IA32_SPEC_CTRL:
1798 if (!msr_info->host_initiated &&
1799 !guest_has_spec_ctrl_msr(vcpu))
1802 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1804 case MSR_IA32_SYSENTER_CS:
1805 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1807 case MSR_IA32_SYSENTER_EIP:
1808 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1810 case MSR_IA32_SYSENTER_ESP:
1811 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1813 case MSR_IA32_BNDCFGS:
1814 if (!kvm_mpx_supported() ||
1815 (!msr_info->host_initiated &&
1816 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1818 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1820 case MSR_IA32_MCG_EXT_CTL:
1821 if (!msr_info->host_initiated &&
1822 !(vmx->msr_ia32_feature_control &
1823 FEAT_CTL_LMCE_ENABLED))
1825 msr_info->data = vcpu->arch.mcg_ext_ctl;
1827 case MSR_IA32_FEAT_CTL:
1828 msr_info->data = vmx->msr_ia32_feature_control;
1830 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
1831 if (!msr_info->host_initiated &&
1832 !guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
1834 msr_info->data = to_vmx(vcpu)->msr_ia32_sgxlepubkeyhash
1835 [msr_info->index - MSR_IA32_SGXLEPUBKEYHASH0];
1837 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1838 if (!nested_vmx_allowed(vcpu))
1840 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1844 * Enlightened VMCS v1 doesn't have certain VMCS fields but
1845 * instead of just ignoring the features, different Hyper-V
1846 * versions are either trying to use them and fail or do some
1847 * sanity checking and refuse to boot. Filter all unsupported
1850 if (!msr_info->host_initiated &&
1851 vmx->nested.enlightened_vmcs_enabled)
1852 nested_evmcs_filter_control_msr(msr_info->index,
1855 case MSR_IA32_RTIT_CTL:
1856 if (!vmx_pt_mode_is_host_guest())
1858 msr_info->data = vmx->pt_desc.guest.ctl;
1860 case MSR_IA32_RTIT_STATUS:
1861 if (!vmx_pt_mode_is_host_guest())
1863 msr_info->data = vmx->pt_desc.guest.status;
1865 case MSR_IA32_RTIT_CR3_MATCH:
1866 if (!vmx_pt_mode_is_host_guest() ||
1867 !intel_pt_validate_cap(vmx->pt_desc.caps,
1868 PT_CAP_cr3_filtering))
1870 msr_info->data = vmx->pt_desc.guest.cr3_match;
1872 case MSR_IA32_RTIT_OUTPUT_BASE:
1873 if (!vmx_pt_mode_is_host_guest() ||
1874 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1875 PT_CAP_topa_output) &&
1876 !intel_pt_validate_cap(vmx->pt_desc.caps,
1877 PT_CAP_single_range_output)))
1879 msr_info->data = vmx->pt_desc.guest.output_base;
1881 case MSR_IA32_RTIT_OUTPUT_MASK:
1882 if (!vmx_pt_mode_is_host_guest() ||
1883 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1884 PT_CAP_topa_output) &&
1885 !intel_pt_validate_cap(vmx->pt_desc.caps,
1886 PT_CAP_single_range_output)))
1888 msr_info->data = vmx->pt_desc.guest.output_mask;
1890 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1891 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1892 if (!vmx_pt_mode_is_host_guest() ||
1893 (index >= 2 * vmx->pt_desc.num_address_ranges))
1896 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1898 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1900 case MSR_IA32_DEBUGCTLMSR:
1901 msr_info->data = vmcs_read64(GUEST_IA32_DEBUGCTL);
1905 msr = vmx_find_uret_msr(vmx, msr_info->index);
1907 msr_info->data = msr->data;
1910 return kvm_get_msr_common(vcpu, msr_info);
1916 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1919 #ifdef CONFIG_X86_64
1920 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1923 return (unsigned long)data;
1926 static u64 vcpu_supported_debugctl(struct kvm_vcpu *vcpu)
1928 u64 debugctl = vmx_supported_debugctl();
1930 if (!intel_pmu_lbr_is_enabled(vcpu))
1931 debugctl &= ~DEBUGCTLMSR_LBR_MASK;
1933 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1934 debugctl &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1940 * Writes msr value into the appropriate "register".
1941 * Returns 0 on success, non-0 otherwise.
1942 * Assumes vcpu_load() was already called.
1944 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1946 struct vcpu_vmx *vmx = to_vmx(vcpu);
1947 struct vmx_uret_msr *msr;
1949 u32 msr_index = msr_info->index;
1950 u64 data = msr_info->data;
1953 switch (msr_index) {
1955 ret = kvm_set_msr_common(vcpu, msr_info);
1957 #ifdef CONFIG_X86_64
1959 vmx_segment_cache_clear(vmx);
1960 vmcs_writel(GUEST_FS_BASE, data);
1963 vmx_segment_cache_clear(vmx);
1964 vmcs_writel(GUEST_GS_BASE, data);
1966 case MSR_KERNEL_GS_BASE:
1967 vmx_write_guest_kernel_gs_base(vmx, data);
1970 case MSR_IA32_SYSENTER_CS:
1971 if (is_guest_mode(vcpu))
1972 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1973 vmcs_write32(GUEST_SYSENTER_CS, data);
1975 case MSR_IA32_SYSENTER_EIP:
1976 if (is_guest_mode(vcpu)) {
1977 data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1978 get_vmcs12(vcpu)->guest_sysenter_eip = data;
1980 vmcs_writel(GUEST_SYSENTER_EIP, data);
1982 case MSR_IA32_SYSENTER_ESP:
1983 if (is_guest_mode(vcpu)) {
1984 data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1985 get_vmcs12(vcpu)->guest_sysenter_esp = data;
1987 vmcs_writel(GUEST_SYSENTER_ESP, data);
1989 case MSR_IA32_DEBUGCTLMSR: {
1990 u64 invalid = data & ~vcpu_supported_debugctl(vcpu);
1991 if (invalid & (DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR)) {
1992 if (report_ignored_msrs)
1993 vcpu_unimpl(vcpu, "%s: BTF|LBR in IA32_DEBUGCTLMSR 0x%llx, nop\n",
1995 data &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1996 invalid &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
2002 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
2003 VM_EXIT_SAVE_DEBUG_CONTROLS)
2004 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2006 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
2007 if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event &&
2008 (data & DEBUGCTLMSR_LBR))
2009 intel_pmu_create_guest_lbr_event(vcpu);
2012 case MSR_IA32_BNDCFGS:
2013 if (!kvm_mpx_supported() ||
2014 (!msr_info->host_initiated &&
2015 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2017 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2018 (data & MSR_IA32_BNDCFGS_RSVD))
2020 vmcs_write64(GUEST_BNDCFGS, data);
2022 case MSR_IA32_UMWAIT_CONTROL:
2023 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2026 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2027 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2030 vmx->msr_ia32_umwait_control = data;
2032 case MSR_IA32_SPEC_CTRL:
2033 if (!msr_info->host_initiated &&
2034 !guest_has_spec_ctrl_msr(vcpu))
2037 if (kvm_spec_ctrl_test_value(data))
2040 vmx->spec_ctrl = data;
2046 * When it's written (to non-zero) for the first time, pass
2050 * The handling of the MSR bitmap for L2 guests is done in
2051 * nested_vmx_prepare_msr_bitmap. We should not touch the
2052 * vmcs02.msr_bitmap here since it gets completely overwritten
2053 * in the merging. We update the vmcs01 here for L1 as well
2054 * since it will end up touching the MSR anyway now.
2056 vmx_disable_intercept_for_msr(vcpu,
2060 case MSR_IA32_TSX_CTRL:
2061 if (!msr_info->host_initiated &&
2062 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2064 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2067 case MSR_IA32_PRED_CMD:
2068 if (!msr_info->host_initiated &&
2069 !guest_has_pred_cmd_msr(vcpu))
2072 if (data & ~PRED_CMD_IBPB)
2074 if (!boot_cpu_has(X86_FEATURE_IBPB))
2079 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2083 * When it's written (to non-zero) for the first time, pass
2087 * The handling of the MSR bitmap for L2 guests is done in
2088 * nested_vmx_prepare_msr_bitmap. We should not touch the
2089 * vmcs02.msr_bitmap here since it gets completely overwritten
2092 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
2094 case MSR_IA32_CR_PAT:
2095 if (!kvm_pat_valid(data))
2098 if (is_guest_mode(vcpu) &&
2099 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2100 get_vmcs12(vcpu)->guest_ia32_pat = data;
2102 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2103 vmcs_write64(GUEST_IA32_PAT, data);
2104 vcpu->arch.pat = data;
2107 ret = kvm_set_msr_common(vcpu, msr_info);
2109 case MSR_IA32_TSC_ADJUST:
2110 ret = kvm_set_msr_common(vcpu, msr_info);
2112 case MSR_IA32_MCG_EXT_CTL:
2113 if ((!msr_info->host_initiated &&
2114 !(to_vmx(vcpu)->msr_ia32_feature_control &
2115 FEAT_CTL_LMCE_ENABLED)) ||
2116 (data & ~MCG_EXT_CTL_LMCE_EN))
2118 vcpu->arch.mcg_ext_ctl = data;
2120 case MSR_IA32_FEAT_CTL:
2121 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2122 (to_vmx(vcpu)->msr_ia32_feature_control &
2123 FEAT_CTL_LOCKED && !msr_info->host_initiated))
2125 vmx->msr_ia32_feature_control = data;
2126 if (msr_info->host_initiated && data == 0)
2127 vmx_leave_nested(vcpu);
2129 /* SGX may be enabled/disabled by guest's firmware */
2130 vmx_write_encls_bitmap(vcpu, NULL);
2132 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
2134 * On real hardware, the LE hash MSRs are writable before
2135 * the firmware sets bit 0 in MSR 0x7a ("activating" SGX),
2136 * at which point SGX related bits in IA32_FEATURE_CONTROL
2139 * KVM does not emulate SGX activation for simplicity, so
2140 * allow writes to the LE hash MSRs if IA32_FEATURE_CONTROL
2141 * is unlocked. This is technically not architectural
2142 * behavior, but it's close enough.
2144 if (!msr_info->host_initiated &&
2145 (!guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC) ||
2146 ((vmx->msr_ia32_feature_control & FEAT_CTL_LOCKED) &&
2147 !(vmx->msr_ia32_feature_control & FEAT_CTL_SGX_LC_ENABLED))))
2149 vmx->msr_ia32_sgxlepubkeyhash
2150 [msr_index - MSR_IA32_SGXLEPUBKEYHASH0] = data;
2152 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2153 if (!msr_info->host_initiated)
2154 return 1; /* they are read-only */
2155 if (!nested_vmx_allowed(vcpu))
2157 return vmx_set_vmx_msr(vcpu, msr_index, data);
2158 case MSR_IA32_RTIT_CTL:
2159 if (!vmx_pt_mode_is_host_guest() ||
2160 vmx_rtit_ctl_check(vcpu, data) ||
2163 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2164 vmx->pt_desc.guest.ctl = data;
2165 pt_update_intercept_for_msr(vcpu);
2167 case MSR_IA32_RTIT_STATUS:
2168 if (!pt_can_write_msr(vmx))
2170 if (data & MSR_IA32_RTIT_STATUS_MASK)
2172 vmx->pt_desc.guest.status = data;
2174 case MSR_IA32_RTIT_CR3_MATCH:
2175 if (!pt_can_write_msr(vmx))
2177 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2178 PT_CAP_cr3_filtering))
2180 vmx->pt_desc.guest.cr3_match = data;
2182 case MSR_IA32_RTIT_OUTPUT_BASE:
2183 if (!pt_can_write_msr(vmx))
2185 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2186 PT_CAP_topa_output) &&
2187 !intel_pt_validate_cap(vmx->pt_desc.caps,
2188 PT_CAP_single_range_output))
2190 if (!pt_output_base_valid(vcpu, data))
2192 vmx->pt_desc.guest.output_base = data;
2194 case MSR_IA32_RTIT_OUTPUT_MASK:
2195 if (!pt_can_write_msr(vmx))
2197 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2198 PT_CAP_topa_output) &&
2199 !intel_pt_validate_cap(vmx->pt_desc.caps,
2200 PT_CAP_single_range_output))
2202 vmx->pt_desc.guest.output_mask = data;
2204 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2205 if (!pt_can_write_msr(vmx))
2207 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2208 if (index >= 2 * vmx->pt_desc.num_address_ranges)
2210 if (is_noncanonical_address(data, vcpu))
2213 vmx->pt_desc.guest.addr_b[index / 2] = data;
2215 vmx->pt_desc.guest.addr_a[index / 2] = data;
2217 case MSR_IA32_PERF_CAPABILITIES:
2218 if (data && !vcpu_to_pmu(vcpu)->version)
2220 if (data & PMU_CAP_LBR_FMT) {
2221 if ((data & PMU_CAP_LBR_FMT) !=
2222 (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
2224 if (!intel_pmu_lbr_is_compatible(vcpu))
2227 ret = kvm_set_msr_common(vcpu, msr_info);
2232 msr = vmx_find_uret_msr(vmx, msr_index);
2234 ret = vmx_set_guest_uret_msr(vmx, msr, data);
2236 ret = kvm_set_msr_common(vcpu, msr_info);
2242 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2244 unsigned long guest_owned_bits;
2246 kvm_register_mark_available(vcpu, reg);
2250 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2253 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2255 case VCPU_EXREG_PDPTR:
2257 ept_save_pdptrs(vcpu);
2259 case VCPU_EXREG_CR0:
2260 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2262 vcpu->arch.cr0 &= ~guest_owned_bits;
2263 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2265 case VCPU_EXREG_CR3:
2267 * When intercepting CR3 loads, e.g. for shadowing paging, KVM's
2268 * CR3 is loaded into hardware, not the guest's CR3.
2270 if (!(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_CR3_LOAD_EXITING))
2271 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2273 case VCPU_EXREG_CR4:
2274 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2276 vcpu->arch.cr4 &= ~guest_owned_bits;
2277 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2280 KVM_BUG_ON(1, vcpu->kvm);
2285 static __init int cpu_has_kvm_support(void)
2287 return cpu_has_vmx();
2290 static __init int vmx_disabled_by_bios(void)
2292 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2293 !boot_cpu_has(X86_FEATURE_VMX);
2296 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2300 cr4_set_bits(X86_CR4_VMXE);
2302 asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2303 _ASM_EXTABLE(1b, %l[fault])
2304 : : [vmxon_pointer] "m"(vmxon_pointer)
2309 WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2310 rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2311 cr4_clear_bits(X86_CR4_VMXE);
2316 static int hardware_enable(void)
2318 int cpu = raw_smp_processor_id();
2319 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2322 if (cr4_read_shadow() & X86_CR4_VMXE)
2326 * This can happen if we hot-added a CPU but failed to allocate
2327 * VP assist page for it.
2329 if (static_branch_unlikely(&enable_evmcs) &&
2330 !hv_get_vp_assist_page(cpu))
2333 intel_pt_handle_vmx(1);
2335 r = kvm_cpu_vmxon(phys_addr);
2337 intel_pt_handle_vmx(0);
2347 static void vmclear_local_loaded_vmcss(void)
2349 int cpu = raw_smp_processor_id();
2350 struct loaded_vmcs *v, *n;
2352 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2353 loaded_vmcss_on_cpu_link)
2354 __loaded_vmcs_clear(v);
2357 static void hardware_disable(void)
2359 vmclear_local_loaded_vmcss();
2362 kvm_spurious_fault();
2364 intel_pt_handle_vmx(0);
2368 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2369 * directly instead of going through cpu_has(), to ensure KVM is trapping
2370 * ENCLS whenever it's supported in hardware. It does not matter whether
2371 * the host OS supports or has enabled SGX.
2373 static bool cpu_has_sgx(void)
2375 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2378 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2379 u32 msr, u32 *result)
2381 u32 vmx_msr_low, vmx_msr_high;
2382 u32 ctl = ctl_min | ctl_opt;
2384 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2386 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2387 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2389 /* Ensure minimum (required) set of control bits are supported. */
2397 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2398 struct vmx_capability *vmx_cap)
2400 u32 vmx_msr_low, vmx_msr_high;
2401 u32 min, opt, min2, opt2;
2402 u32 _pin_based_exec_control = 0;
2403 u32 _cpu_based_exec_control = 0;
2404 u32 _cpu_based_2nd_exec_control = 0;
2405 u32 _vmexit_control = 0;
2406 u32 _vmentry_control = 0;
2408 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2409 min = CPU_BASED_HLT_EXITING |
2410 #ifdef CONFIG_X86_64
2411 CPU_BASED_CR8_LOAD_EXITING |
2412 CPU_BASED_CR8_STORE_EXITING |
2414 CPU_BASED_CR3_LOAD_EXITING |
2415 CPU_BASED_CR3_STORE_EXITING |
2416 CPU_BASED_UNCOND_IO_EXITING |
2417 CPU_BASED_MOV_DR_EXITING |
2418 CPU_BASED_USE_TSC_OFFSETTING |
2419 CPU_BASED_MWAIT_EXITING |
2420 CPU_BASED_MONITOR_EXITING |
2421 CPU_BASED_INVLPG_EXITING |
2422 CPU_BASED_RDPMC_EXITING;
2424 opt = CPU_BASED_TPR_SHADOW |
2425 CPU_BASED_USE_MSR_BITMAPS |
2426 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2427 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2428 &_cpu_based_exec_control) < 0)
2430 #ifdef CONFIG_X86_64
2431 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2432 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2433 ~CPU_BASED_CR8_STORE_EXITING;
2435 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2437 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2438 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2439 SECONDARY_EXEC_WBINVD_EXITING |
2440 SECONDARY_EXEC_ENABLE_VPID |
2441 SECONDARY_EXEC_ENABLE_EPT |
2442 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2443 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2444 SECONDARY_EXEC_DESC |
2445 SECONDARY_EXEC_ENABLE_RDTSCP |
2446 SECONDARY_EXEC_ENABLE_INVPCID |
2447 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2448 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2449 SECONDARY_EXEC_SHADOW_VMCS |
2450 SECONDARY_EXEC_XSAVES |
2451 SECONDARY_EXEC_RDSEED_EXITING |
2452 SECONDARY_EXEC_RDRAND_EXITING |
2453 SECONDARY_EXEC_ENABLE_PML |
2454 SECONDARY_EXEC_TSC_SCALING |
2455 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2456 SECONDARY_EXEC_PT_USE_GPA |
2457 SECONDARY_EXEC_PT_CONCEAL_VMX |
2458 SECONDARY_EXEC_ENABLE_VMFUNC |
2459 SECONDARY_EXEC_BUS_LOCK_DETECTION;
2461 opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2462 if (adjust_vmx_controls(min2, opt2,
2463 MSR_IA32_VMX_PROCBASED_CTLS2,
2464 &_cpu_based_2nd_exec_control) < 0)
2467 #ifndef CONFIG_X86_64
2468 if (!(_cpu_based_2nd_exec_control &
2469 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2470 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2473 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2474 _cpu_based_2nd_exec_control &= ~(
2475 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2476 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2477 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2479 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2480 &vmx_cap->ept, &vmx_cap->vpid);
2482 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2483 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2485 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2486 CPU_BASED_CR3_STORE_EXITING |
2487 CPU_BASED_INVLPG_EXITING);
2488 } else if (vmx_cap->ept) {
2490 pr_warn_once("EPT CAP should not exist if not support "
2491 "1-setting enable EPT VM-execution control\n");
2493 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2496 pr_warn_once("VPID CAP should not exist if not support "
2497 "1-setting enable VPID VM-execution control\n");
2500 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2501 #ifdef CONFIG_X86_64
2502 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2504 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2505 VM_EXIT_LOAD_IA32_PAT |
2506 VM_EXIT_LOAD_IA32_EFER |
2507 VM_EXIT_CLEAR_BNDCFGS |
2508 VM_EXIT_PT_CONCEAL_PIP |
2509 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2510 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2511 &_vmexit_control) < 0)
2514 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2515 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2516 PIN_BASED_VMX_PREEMPTION_TIMER;
2517 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2518 &_pin_based_exec_control) < 0)
2521 if (cpu_has_broken_vmx_preemption_timer())
2522 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2523 if (!(_cpu_based_2nd_exec_control &
2524 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2525 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2527 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2528 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2529 VM_ENTRY_LOAD_IA32_PAT |
2530 VM_ENTRY_LOAD_IA32_EFER |
2531 VM_ENTRY_LOAD_BNDCFGS |
2532 VM_ENTRY_PT_CONCEAL_PIP |
2533 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2534 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2535 &_vmentry_control) < 0)
2539 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2540 * can't be used due to an errata where VM Exit may incorrectly clear
2541 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2542 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2544 if (boot_cpu_data.x86 == 0x6) {
2545 switch (boot_cpu_data.x86_model) {
2546 case 26: /* AAK155 */
2547 case 30: /* AAP115 */
2548 case 37: /* AAT100 */
2549 case 44: /* BC86,AAY89,BD102 */
2551 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2552 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2553 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2554 "does not work properly. Using workaround\n");
2562 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2564 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2565 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2568 #ifdef CONFIG_X86_64
2569 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2570 if (vmx_msr_high & (1u<<16))
2574 /* Require Write-Back (WB) memory type for VMCS accesses. */
2575 if (((vmx_msr_high >> 18) & 15) != 6)
2578 vmcs_conf->size = vmx_msr_high & 0x1fff;
2579 vmcs_conf->order = get_order(vmcs_conf->size);
2580 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2582 vmcs_conf->revision_id = vmx_msr_low;
2584 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2585 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2586 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2587 vmcs_conf->vmexit_ctrl = _vmexit_control;
2588 vmcs_conf->vmentry_ctrl = _vmentry_control;
2590 #if IS_ENABLED(CONFIG_HYPERV)
2591 if (enlightened_vmcs)
2592 evmcs_sanitize_exec_ctrls(vmcs_conf);
2598 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2600 int node = cpu_to_node(cpu);
2604 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2607 vmcs = page_address(pages);
2608 memset(vmcs, 0, vmcs_config.size);
2610 /* KVM supports Enlightened VMCS v1 only */
2611 if (static_branch_unlikely(&enable_evmcs))
2612 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2614 vmcs->hdr.revision_id = vmcs_config.revision_id;
2617 vmcs->hdr.shadow_vmcs = 1;
2621 void free_vmcs(struct vmcs *vmcs)
2623 free_pages((unsigned long)vmcs, vmcs_config.order);
2627 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2629 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2631 if (!loaded_vmcs->vmcs)
2633 loaded_vmcs_clear(loaded_vmcs);
2634 free_vmcs(loaded_vmcs->vmcs);
2635 loaded_vmcs->vmcs = NULL;
2636 if (loaded_vmcs->msr_bitmap)
2637 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2638 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2641 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2643 loaded_vmcs->vmcs = alloc_vmcs(false);
2644 if (!loaded_vmcs->vmcs)
2647 vmcs_clear(loaded_vmcs->vmcs);
2649 loaded_vmcs->shadow_vmcs = NULL;
2650 loaded_vmcs->hv_timer_soft_disabled = false;
2651 loaded_vmcs->cpu = -1;
2652 loaded_vmcs->launched = 0;
2654 if (cpu_has_vmx_msr_bitmap()) {
2655 loaded_vmcs->msr_bitmap = (unsigned long *)
2656 __get_free_page(GFP_KERNEL_ACCOUNT);
2657 if (!loaded_vmcs->msr_bitmap)
2659 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2661 if (IS_ENABLED(CONFIG_HYPERV) &&
2662 static_branch_unlikely(&enable_evmcs) &&
2663 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2664 struct hv_enlightened_vmcs *evmcs =
2665 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2667 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2671 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2672 memset(&loaded_vmcs->controls_shadow, 0,
2673 sizeof(struct vmcs_controls_shadow));
2678 free_loaded_vmcs(loaded_vmcs);
2682 static void free_kvm_area(void)
2686 for_each_possible_cpu(cpu) {
2687 free_vmcs(per_cpu(vmxarea, cpu));
2688 per_cpu(vmxarea, cpu) = NULL;
2692 static __init int alloc_kvm_area(void)
2696 for_each_possible_cpu(cpu) {
2699 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2706 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2707 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2708 * revision_id reported by MSR_IA32_VMX_BASIC.
2710 * However, even though not explicitly documented by
2711 * TLFS, VMXArea passed as VMXON argument should
2712 * still be marked with revision_id reported by
2715 if (static_branch_unlikely(&enable_evmcs))
2716 vmcs->hdr.revision_id = vmcs_config.revision_id;
2718 per_cpu(vmxarea, cpu) = vmcs;
2723 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2724 struct kvm_segment *save)
2726 if (!emulate_invalid_guest_state) {
2728 * CS and SS RPL should be equal during guest entry according
2729 * to VMX spec, but in reality it is not always so. Since vcpu
2730 * is in the middle of the transition from real mode to
2731 * protected mode it is safe to assume that RPL 0 is a good
2734 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2735 save->selector &= ~SEGMENT_RPL_MASK;
2736 save->dpl = save->selector & SEGMENT_RPL_MASK;
2739 __vmx_set_segment(vcpu, save, seg);
2742 static void enter_pmode(struct kvm_vcpu *vcpu)
2744 unsigned long flags;
2745 struct vcpu_vmx *vmx = to_vmx(vcpu);
2748 * Update real mode segment cache. It may be not up-to-date if segment
2749 * register was written while vcpu was in a guest mode.
2751 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2752 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2753 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2754 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2755 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2756 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2758 vmx->rmode.vm86_active = 0;
2760 __vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2762 flags = vmcs_readl(GUEST_RFLAGS);
2763 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2764 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2765 vmcs_writel(GUEST_RFLAGS, flags);
2767 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2768 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2770 vmx_update_exception_bitmap(vcpu);
2772 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2773 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2774 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2775 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2776 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2777 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2780 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2782 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2783 struct kvm_segment var = *save;
2786 if (seg == VCPU_SREG_CS)
2789 if (!emulate_invalid_guest_state) {
2790 var.selector = var.base >> 4;
2791 var.base = var.base & 0xffff0;
2801 if (save->base & 0xf)
2802 printk_once(KERN_WARNING "kvm: segment base is not "
2803 "paragraph aligned when entering "
2804 "protected mode (seg=%d)", seg);
2807 vmcs_write16(sf->selector, var.selector);
2808 vmcs_writel(sf->base, var.base);
2809 vmcs_write32(sf->limit, var.limit);
2810 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2813 static void enter_rmode(struct kvm_vcpu *vcpu)
2815 unsigned long flags;
2816 struct vcpu_vmx *vmx = to_vmx(vcpu);
2817 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2819 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2820 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2821 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2822 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2823 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2824 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2825 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2827 vmx->rmode.vm86_active = 1;
2830 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2831 * vcpu. Warn the user that an update is overdue.
2833 if (!kvm_vmx->tss_addr)
2834 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2835 "called before entering vcpu\n");
2837 vmx_segment_cache_clear(vmx);
2839 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2840 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2841 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2843 flags = vmcs_readl(GUEST_RFLAGS);
2844 vmx->rmode.save_rflags = flags;
2846 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2848 vmcs_writel(GUEST_RFLAGS, flags);
2849 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2850 vmx_update_exception_bitmap(vcpu);
2852 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2853 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2854 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2855 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2856 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2857 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2860 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2862 struct vcpu_vmx *vmx = to_vmx(vcpu);
2863 struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER);
2865 /* Nothing to do if hardware doesn't support EFER. */
2869 vcpu->arch.efer = efer;
2870 if (efer & EFER_LMA) {
2871 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2874 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2876 msr->data = efer & ~EFER_LME;
2878 vmx_setup_uret_msrs(vmx);
2882 #ifdef CONFIG_X86_64
2884 static void enter_lmode(struct kvm_vcpu *vcpu)
2888 vmx_segment_cache_clear(to_vmx(vcpu));
2890 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2891 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2892 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2894 vmcs_write32(GUEST_TR_AR_BYTES,
2895 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2896 | VMX_AR_TYPE_BUSY_64_TSS);
2898 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2901 static void exit_lmode(struct kvm_vcpu *vcpu)
2903 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2904 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2909 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2911 struct vcpu_vmx *vmx = to_vmx(vcpu);
2914 * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2915 * the CPU is not required to invalidate guest-physical mappings on
2916 * VM-Entry, even if VPID is disabled. Guest-physical mappings are
2917 * associated with the root EPT structure and not any particular VPID
2918 * (INVVPID also isn't required to invalidate guest-physical mappings).
2922 } else if (enable_vpid) {
2923 if (cpu_has_vmx_invvpid_global()) {
2924 vpid_sync_vcpu_global();
2926 vpid_sync_vcpu_single(vmx->vpid);
2927 vpid_sync_vcpu_single(vmx->nested.vpid02);
2932 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2934 struct kvm_mmu *mmu = vcpu->arch.mmu;
2935 u64 root_hpa = mmu->root_hpa;
2937 /* No flush required if the current context is invalid. */
2938 if (!VALID_PAGE(root_hpa))
2942 ept_sync_context(construct_eptp(vcpu, root_hpa,
2943 mmu->shadow_root_level));
2944 else if (!is_guest_mode(vcpu))
2945 vpid_sync_context(to_vmx(vcpu)->vpid);
2947 vpid_sync_context(nested_get_vpid02(vcpu));
2950 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2953 * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2954 * vmx_flush_tlb_guest() for an explanation of why this is ok.
2956 vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2959 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2962 * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2963 * or a vpid couldn't be allocated for this vCPU. VM-Enter and VM-Exit
2964 * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2965 * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2966 * i.e. no explicit INVVPID is necessary.
2968 vpid_sync_context(to_vmx(vcpu)->vpid);
2971 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2973 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2975 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2978 if (is_pae_paging(vcpu)) {
2979 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2980 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2981 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2982 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2986 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2988 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2990 if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2993 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2994 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2995 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2996 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2998 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
3001 #define CR3_EXITING_BITS (CPU_BASED_CR3_LOAD_EXITING | \
3002 CPU_BASED_CR3_STORE_EXITING)
3004 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3006 struct vcpu_vmx *vmx = to_vmx(vcpu);
3007 unsigned long hw_cr0, old_cr0_pg;
3010 old_cr0_pg = kvm_read_cr0_bits(vcpu, X86_CR0_PG);
3012 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3013 if (is_unrestricted_guest(vcpu))
3014 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3016 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3018 hw_cr0 |= X86_CR0_WP;
3020 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3023 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3027 vmcs_writel(CR0_READ_SHADOW, cr0);
3028 vmcs_writel(GUEST_CR0, hw_cr0);
3029 vcpu->arch.cr0 = cr0;
3030 kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3032 #ifdef CONFIG_X86_64
3033 if (vcpu->arch.efer & EFER_LME) {
3034 if (!old_cr0_pg && (cr0 & X86_CR0_PG))
3036 else if (old_cr0_pg && !(cr0 & X86_CR0_PG))
3041 if (enable_ept && !is_unrestricted_guest(vcpu)) {
3043 * Ensure KVM has an up-to-date snapshot of the guest's CR3. If
3044 * the below code _enables_ CR3 exiting, vmx_cache_reg() will
3045 * (correctly) stop reading vmcs.GUEST_CR3 because it thinks
3046 * KVM's CR3 is installed.
3048 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
3049 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
3052 * When running with EPT but not unrestricted guest, KVM must
3053 * intercept CR3 accesses when paging is _disabled_. This is
3054 * necessary because restricted guests can't actually run with
3055 * paging disabled, and so KVM stuffs its own CR3 in order to
3056 * run the guest when identity mapped page tables.
3058 * Do _NOT_ check the old CR0.PG, e.g. to optimize away the
3059 * update, it may be stale with respect to CR3 interception,
3060 * e.g. after nested VM-Enter.
3062 * Lastly, honor L1's desires, i.e. intercept CR3 loads and/or
3063 * stores to forward them to L1, even if KVM does not need to
3064 * intercept them to preserve its identity mapped page tables.
3066 if (!(cr0 & X86_CR0_PG)) {
3067 exec_controls_setbit(vmx, CR3_EXITING_BITS);
3068 } else if (!is_guest_mode(vcpu)) {
3069 exec_controls_clearbit(vmx, CR3_EXITING_BITS);
3071 tmp = exec_controls_get(vmx);
3072 tmp &= ~CR3_EXITING_BITS;
3073 tmp |= get_vmcs12(vcpu)->cpu_based_vm_exec_control & CR3_EXITING_BITS;
3074 exec_controls_set(vmx, tmp);
3077 /* Note, vmx_set_cr4() consumes the new vcpu->arch.cr0. */
3078 if ((old_cr0_pg ^ cr0) & X86_CR0_PG)
3079 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3082 /* depends on vcpu->arch.cr0 to be set to a new value */
3083 vmx->emulation_required = vmx_emulation_required(vcpu);
3086 static int vmx_get_max_tdp_level(void)
3088 if (cpu_has_vmx_ept_5levels())
3093 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level)
3095 u64 eptp = VMX_EPTP_MT_WB;
3097 eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3099 if (enable_ept_ad_bits &&
3100 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3101 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3107 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3110 struct kvm *kvm = vcpu->kvm;
3111 bool update_guest_cr3 = true;
3112 unsigned long guest_cr3;
3116 eptp = construct_eptp(vcpu, root_hpa, root_level);
3117 vmcs_write64(EPT_POINTER, eptp);
3119 hv_track_root_tdp(vcpu, root_hpa);
3121 if (!enable_unrestricted_guest && !is_paging(vcpu))
3122 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3123 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3124 guest_cr3 = vcpu->arch.cr3;
3125 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3126 update_guest_cr3 = false;
3127 vmx_ept_load_pdptrs(vcpu);
3129 guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu);
3132 if (update_guest_cr3)
3133 vmcs_writel(GUEST_CR3, guest_cr3);
3136 static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3139 * We operate under the default treatment of SMM, so VMX cannot be
3140 * enabled under SMM. Note, whether or not VMXE is allowed at all is
3141 * handled by kvm_is_valid_cr4().
3143 if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu))
3146 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3152 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3154 unsigned long old_cr4 = vcpu->arch.cr4;
3155 struct vcpu_vmx *vmx = to_vmx(vcpu);
3157 * Pass through host's Machine Check Enable value to hw_cr4, which
3158 * is in force while we are in guest mode. Do not let guests control
3159 * this bit, even if host CR4.MCE == 0.
3161 unsigned long hw_cr4;
3163 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3164 if (is_unrestricted_guest(vcpu))
3165 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3166 else if (vmx->rmode.vm86_active)
3167 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3169 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3171 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3172 if (cr4 & X86_CR4_UMIP) {
3173 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3174 hw_cr4 &= ~X86_CR4_UMIP;
3175 } else if (!is_guest_mode(vcpu) ||
3176 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3177 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3181 vcpu->arch.cr4 = cr4;
3182 kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3184 if (!is_unrestricted_guest(vcpu)) {
3186 if (!is_paging(vcpu)) {
3187 hw_cr4 &= ~X86_CR4_PAE;
3188 hw_cr4 |= X86_CR4_PSE;
3189 } else if (!(cr4 & X86_CR4_PAE)) {
3190 hw_cr4 &= ~X86_CR4_PAE;
3195 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3196 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3197 * to be manually disabled when guest switches to non-paging
3200 * If !enable_unrestricted_guest, the CPU is always running
3201 * with CR0.PG=1 and CR4 needs to be modified.
3202 * If enable_unrestricted_guest, the CPU automatically
3203 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3205 if (!is_paging(vcpu))
3206 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3209 vmcs_writel(CR4_READ_SHADOW, cr4);
3210 vmcs_writel(GUEST_CR4, hw_cr4);
3212 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
3213 kvm_update_cpuid_runtime(vcpu);
3216 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3218 struct vcpu_vmx *vmx = to_vmx(vcpu);
3221 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3222 *var = vmx->rmode.segs[seg];
3223 if (seg == VCPU_SREG_TR
3224 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3226 var->base = vmx_read_guest_seg_base(vmx, seg);
3227 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3230 var->base = vmx_read_guest_seg_base(vmx, seg);
3231 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3232 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3233 ar = vmx_read_guest_seg_ar(vmx, seg);
3234 var->unusable = (ar >> 16) & 1;
3235 var->type = ar & 15;
3236 var->s = (ar >> 4) & 1;
3237 var->dpl = (ar >> 5) & 3;
3239 * Some userspaces do not preserve unusable property. Since usable
3240 * segment has to be present according to VMX spec we can use present
3241 * property to amend userspace bug by making unusable segment always
3242 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3243 * segment as unusable.
3245 var->present = !var->unusable;
3246 var->avl = (ar >> 12) & 1;
3247 var->l = (ar >> 13) & 1;
3248 var->db = (ar >> 14) & 1;
3249 var->g = (ar >> 15) & 1;
3252 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3254 struct kvm_segment s;
3256 if (to_vmx(vcpu)->rmode.vm86_active) {
3257 vmx_get_segment(vcpu, &s, seg);
3260 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3263 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3265 struct vcpu_vmx *vmx = to_vmx(vcpu);
3267 if (unlikely(vmx->rmode.vm86_active))
3270 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3271 return VMX_AR_DPL(ar);
3275 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3279 if (var->unusable || !var->present)
3282 ar = var->type & 15;
3283 ar |= (var->s & 1) << 4;
3284 ar |= (var->dpl & 3) << 5;
3285 ar |= (var->present & 1) << 7;
3286 ar |= (var->avl & 1) << 12;
3287 ar |= (var->l & 1) << 13;
3288 ar |= (var->db & 1) << 14;
3289 ar |= (var->g & 1) << 15;
3295 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3297 struct vcpu_vmx *vmx = to_vmx(vcpu);
3298 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3300 vmx_segment_cache_clear(vmx);
3302 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3303 vmx->rmode.segs[seg] = *var;
3304 if (seg == VCPU_SREG_TR)
3305 vmcs_write16(sf->selector, var->selector);
3307 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3311 vmcs_writel(sf->base, var->base);
3312 vmcs_write32(sf->limit, var->limit);
3313 vmcs_write16(sf->selector, var->selector);
3316 * Fix the "Accessed" bit in AR field of segment registers for older
3318 * IA32 arch specifies that at the time of processor reset the
3319 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3320 * is setting it to 0 in the userland code. This causes invalid guest
3321 * state vmexit when "unrestricted guest" mode is turned on.
3322 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3323 * tree. Newer qemu binaries with that qemu fix would not need this
3326 if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3327 var->type |= 0x1; /* Accessed */
3329 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3332 static void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3334 __vmx_set_segment(vcpu, var, seg);
3336 to_vmx(vcpu)->emulation_required = vmx_emulation_required(vcpu);
3339 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3341 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3343 *db = (ar >> 14) & 1;
3344 *l = (ar >> 13) & 1;
3347 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3349 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3350 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3353 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3355 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3356 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3359 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3361 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3362 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3365 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3367 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3368 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3371 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3373 struct kvm_segment var;
3376 vmx_get_segment(vcpu, &var, seg);
3378 if (seg == VCPU_SREG_CS)
3380 ar = vmx_segment_access_rights(&var);
3382 if (var.base != (var.selector << 4))
3384 if (var.limit != 0xffff)
3392 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3394 struct kvm_segment cs;
3395 unsigned int cs_rpl;
3397 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3398 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3402 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3406 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3407 if (cs.dpl > cs_rpl)
3410 if (cs.dpl != cs_rpl)
3416 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3420 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3422 struct kvm_segment ss;
3423 unsigned int ss_rpl;
3425 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3426 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3430 if (ss.type != 3 && ss.type != 7)
3434 if (ss.dpl != ss_rpl) /* DPL != RPL */
3442 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3444 struct kvm_segment var;
3447 vmx_get_segment(vcpu, &var, seg);
3448 rpl = var.selector & SEGMENT_RPL_MASK;
3456 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3457 if (var.dpl < rpl) /* DPL < RPL */
3461 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3467 static bool tr_valid(struct kvm_vcpu *vcpu)
3469 struct kvm_segment tr;
3471 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3475 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3477 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3485 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3487 struct kvm_segment ldtr;
3489 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3493 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3503 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3505 struct kvm_segment cs, ss;
3507 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3508 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3510 return ((cs.selector & SEGMENT_RPL_MASK) ==
3511 (ss.selector & SEGMENT_RPL_MASK));
3515 * Check if guest state is valid. Returns true if valid, false if
3517 * We assume that registers are always usable
3519 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu)
3521 /* real mode guest state checks */
3522 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3523 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3525 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3527 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3529 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3531 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3533 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3536 /* protected mode guest state checks */
3537 if (!cs_ss_rpl_check(vcpu))
3539 if (!code_segment_valid(vcpu))
3541 if (!stack_segment_valid(vcpu))
3543 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3545 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3547 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3549 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3551 if (!tr_valid(vcpu))
3553 if (!ldtr_valid(vcpu))
3557 * - Add checks on RIP
3558 * - Add checks on RFLAGS
3564 static int init_rmode_tss(struct kvm *kvm, void __user *ua)
3566 const void *zero_page = (const void *) __va(page_to_phys(ZERO_PAGE(0)));
3570 for (i = 0; i < 3; i++) {
3571 if (__copy_to_user(ua + PAGE_SIZE * i, zero_page, PAGE_SIZE))
3575 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3576 if (__copy_to_user(ua + TSS_IOPB_BASE_OFFSET, &data, sizeof(u16)))
3580 if (__copy_to_user(ua + RMODE_TSS_SIZE - 1, &data, sizeof(u8)))
3586 static int init_rmode_identity_map(struct kvm *kvm)
3588 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3593 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3594 mutex_lock(&kvm->slots_lock);
3596 if (likely(kvm_vmx->ept_identity_pagetable_done))
3599 if (!kvm_vmx->ept_identity_map_addr)
3600 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3602 uaddr = __x86_set_memory_region(kvm,
3603 IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3604 kvm_vmx->ept_identity_map_addr,
3606 if (IS_ERR(uaddr)) {
3611 /* Set up identity-mapping pagetable for EPT in real mode */
3612 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3613 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3614 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3615 if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) {
3620 kvm_vmx->ept_identity_pagetable_done = true;
3623 mutex_unlock(&kvm->slots_lock);
3627 static void seg_setup(int seg)
3629 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3632 vmcs_write16(sf->selector, 0);
3633 vmcs_writel(sf->base, 0);
3634 vmcs_write32(sf->limit, 0xffff);
3636 if (seg == VCPU_SREG_CS)
3637 ar |= 0x08; /* code segment */
3639 vmcs_write32(sf->ar_bytes, ar);
3642 static int alloc_apic_access_page(struct kvm *kvm)
3648 mutex_lock(&kvm->slots_lock);
3649 if (kvm->arch.apic_access_memslot_enabled)
3651 hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3652 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3658 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3659 if (is_error_page(page)) {
3665 * Do not pin the page in memory, so that memory hot-unplug
3666 * is able to migrate it.
3669 kvm->arch.apic_access_memslot_enabled = true;
3671 mutex_unlock(&kvm->slots_lock);
3675 int allocate_vpid(void)
3681 spin_lock(&vmx_vpid_lock);
3682 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3683 if (vpid < VMX_NR_VPIDS)
3684 __set_bit(vpid, vmx_vpid_bitmap);
3687 spin_unlock(&vmx_vpid_lock);
3691 void free_vpid(int vpid)
3693 if (!enable_vpid || vpid == 0)
3695 spin_lock(&vmx_vpid_lock);
3696 __clear_bit(vpid, vmx_vpid_bitmap);
3697 spin_unlock(&vmx_vpid_lock);
3700 static void vmx_clear_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3702 int f = sizeof(unsigned long);
3705 __clear_bit(msr, msr_bitmap + 0x000 / f);
3706 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3707 __clear_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3710 static void vmx_clear_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3712 int f = sizeof(unsigned long);
3715 __clear_bit(msr, msr_bitmap + 0x800 / f);
3716 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3717 __clear_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3720 static void vmx_set_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3722 int f = sizeof(unsigned long);
3725 __set_bit(msr, msr_bitmap + 0x000 / f);
3726 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3727 __set_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3730 static void vmx_set_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3732 int f = sizeof(unsigned long);
3735 __set_bit(msr, msr_bitmap + 0x800 / f);
3736 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3737 __set_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3740 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3742 struct vcpu_vmx *vmx = to_vmx(vcpu);
3743 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3745 if (!cpu_has_vmx_msr_bitmap())
3748 if (static_branch_unlikely(&enable_evmcs))
3749 evmcs_touch_msr_bitmap();
3752 * Mark the desired intercept state in shadow bitmap, this is needed
3753 * for resync when the MSR filters change.
3755 if (is_valid_passthrough_msr(msr)) {
3756 int idx = possible_passthrough_msr_slot(msr);
3758 if (idx != -ENOENT) {
3759 if (type & MSR_TYPE_R)
3760 clear_bit(idx, vmx->shadow_msr_intercept.read);
3761 if (type & MSR_TYPE_W)
3762 clear_bit(idx, vmx->shadow_msr_intercept.write);
3766 if ((type & MSR_TYPE_R) &&
3767 !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) {
3768 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3769 type &= ~MSR_TYPE_R;
3772 if ((type & MSR_TYPE_W) &&
3773 !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) {
3774 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3775 type &= ~MSR_TYPE_W;
3778 if (type & MSR_TYPE_R)
3779 vmx_clear_msr_bitmap_read(msr_bitmap, msr);
3781 if (type & MSR_TYPE_W)
3782 vmx_clear_msr_bitmap_write(msr_bitmap, msr);
3785 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3787 struct vcpu_vmx *vmx = to_vmx(vcpu);
3788 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3790 if (!cpu_has_vmx_msr_bitmap())
3793 if (static_branch_unlikely(&enable_evmcs))
3794 evmcs_touch_msr_bitmap();
3797 * Mark the desired intercept state in shadow bitmap, this is needed
3798 * for resync when the MSR filter changes.
3800 if (is_valid_passthrough_msr(msr)) {
3801 int idx = possible_passthrough_msr_slot(msr);
3803 if (idx != -ENOENT) {
3804 if (type & MSR_TYPE_R)
3805 set_bit(idx, vmx->shadow_msr_intercept.read);
3806 if (type & MSR_TYPE_W)
3807 set_bit(idx, vmx->shadow_msr_intercept.write);
3811 if (type & MSR_TYPE_R)
3812 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3814 if (type & MSR_TYPE_W)
3815 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3818 static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode)
3820 unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
3821 unsigned long read_intercept;
3824 read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3826 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3827 unsigned int read_idx = msr / BITS_PER_LONG;
3828 unsigned int write_idx = read_idx + (0x800 / sizeof(long));
3830 msr_bitmap[read_idx] = read_intercept;
3831 msr_bitmap[write_idx] = ~0ul;
3835 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
3837 struct vcpu_vmx *vmx = to_vmx(vcpu);
3840 if (!cpu_has_vmx_msr_bitmap())
3843 if (cpu_has_secondary_exec_ctrls() &&
3844 (secondary_exec_controls_get(vmx) &
3845 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3846 mode = MSR_BITMAP_MODE_X2APIC;
3847 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3848 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3853 if (mode == vmx->x2apic_msr_bitmap_mode)
3856 vmx->x2apic_msr_bitmap_mode = mode;
3858 vmx_reset_x2apic_msrs(vcpu, mode);
3861 * TPR reads and writes can be virtualized even if virtual interrupt
3862 * delivery is not in use.
3864 vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
3865 !(mode & MSR_BITMAP_MODE_X2APIC));
3867 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3868 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
3869 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3870 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3874 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu)
3876 struct vcpu_vmx *vmx = to_vmx(vcpu);
3877 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3880 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
3881 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
3882 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
3883 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
3884 for (i = 0; i < vmx->pt_desc.num_address_ranges; i++) {
3885 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3886 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3890 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3892 struct vcpu_vmx *vmx = to_vmx(vcpu);
3897 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3898 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3899 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3902 rvi = vmx_get_rvi();
3904 vapic_page = vmx->nested.virtual_apic_map.hva;
3905 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3907 return ((rvi & 0xf0) > (vppr & 0xf0));
3910 static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
3912 struct vcpu_vmx *vmx = to_vmx(vcpu);
3916 * Set intercept permissions for all potentially passed through MSRs
3917 * again. They will automatically get filtered through the MSR filter,
3918 * so we are back in sync after this.
3920 for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
3921 u32 msr = vmx_possible_passthrough_msrs[i];
3922 bool read = test_bit(i, vmx->shadow_msr_intercept.read);
3923 bool write = test_bit(i, vmx->shadow_msr_intercept.write);
3925 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
3926 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
3929 pt_update_intercept_for_msr(vcpu);
3932 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3936 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3938 if (vcpu->mode == IN_GUEST_MODE) {
3940 * The vector of interrupt to be delivered to vcpu had
3941 * been set in PIR before this function.
3943 * Following cases will be reached in this block, and
3944 * we always send a notification event in all cases as
3947 * Case 1: vcpu keeps in non-root mode. Sending a
3948 * notification event posts the interrupt to vcpu.
3950 * Case 2: vcpu exits to root mode and is still
3951 * runnable. PIR will be synced to vIRR before the
3952 * next vcpu entry. Sending a notification event in
3953 * this case has no effect, as vcpu is not in root
3956 * Case 3: vcpu exits to root mode and is blocked.
3957 * vcpu_block() has already synced PIR to vIRR and
3958 * never blocks vcpu if vIRR is not cleared. Therefore,
3959 * a blocked vcpu here does not wait for any requested
3960 * interrupts in PIR, and sending a notification event
3961 * which has no effect is safe here.
3964 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3971 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3974 struct vcpu_vmx *vmx = to_vmx(vcpu);
3976 if (is_guest_mode(vcpu) &&
3977 vector == vmx->nested.posted_intr_nv) {
3979 * If a posted intr is not recognized by hardware,
3980 * we will accomplish it in the next vmentry.
3982 vmx->nested.pi_pending = true;
3983 kvm_make_request(KVM_REQ_EVENT, vcpu);
3984 /* the PIR and ON have been set by L1. */
3985 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3986 kvm_vcpu_kick(vcpu);
3992 * Send interrupt to vcpu via posted interrupt way.
3993 * 1. If target vcpu is running(non-root mode), send posted interrupt
3994 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3995 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3996 * interrupt from PIR in next vmentry.
3998 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4000 struct vcpu_vmx *vmx = to_vmx(vcpu);
4003 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4007 if (!vcpu->arch.apicv_active)
4010 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4013 /* If a previous notification has sent the IPI, nothing to do. */
4014 if (pi_test_and_set_on(&vmx->pi_desc))
4017 if (vcpu != kvm_get_running_vcpu() &&
4018 !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
4019 kvm_vcpu_kick(vcpu);
4025 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4026 * will not change in the lifetime of the guest.
4027 * Note that host-state that does change is set elsewhere. E.g., host-state
4028 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4030 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4034 unsigned long cr0, cr3, cr4;
4037 WARN_ON(cr0 & X86_CR0_TS);
4038 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
4041 * Save the most likely value for this task's CR3 in the VMCS.
4042 * We can't use __get_current_cr3_fast() because we're not atomic.
4045 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
4046 vmx->loaded_vmcs->host_state.cr3 = cr3;
4048 /* Save the most likely value for this task's CR4 in the VMCS. */
4049 cr4 = cr4_read_shadow();
4050 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4051 vmx->loaded_vmcs->host_state.cr4 = cr4;
4053 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4054 #ifdef CONFIG_X86_64
4056 * Load null selectors, so we can avoid reloading them in
4057 * vmx_prepare_switch_to_host(), in case userspace uses
4058 * the null selectors too (the expected case).
4060 vmcs_write16(HOST_DS_SELECTOR, 0);
4061 vmcs_write16(HOST_ES_SELECTOR, 0);
4063 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4064 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4066 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4067 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4069 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
4071 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4073 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4074 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4075 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4076 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4078 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4079 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4080 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4083 if (cpu_has_load_ia32_efer())
4084 vmcs_write64(HOST_IA32_EFER, host_efer);
4087 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4089 struct kvm_vcpu *vcpu = &vmx->vcpu;
4091 vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
4092 ~vcpu->arch.cr4_guest_rsvd_bits;
4094 vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4095 if (is_guest_mode(&vmx->vcpu))
4096 vcpu->arch.cr4_guest_owned_bits &=
4097 ~get_vmcs12(vcpu)->cr4_guest_host_mask;
4098 vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits);
4101 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4103 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4105 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4106 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4109 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4111 if (!enable_preemption_timer)
4112 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4114 return pin_based_exec_ctrl;
4117 static u32 vmx_vmentry_ctrl(void)
4119 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
4121 if (vmx_pt_mode_is_system())
4122 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
4123 VM_ENTRY_LOAD_IA32_RTIT_CTL);
4124 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4125 return vmentry_ctrl &
4126 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
4129 static u32 vmx_vmexit_ctrl(void)
4131 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
4133 if (vmx_pt_mode_is_system())
4134 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
4135 VM_EXIT_CLEAR_IA32_RTIT_CTL);
4136 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4137 return vmexit_ctrl &
4138 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
4141 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4143 struct vcpu_vmx *vmx = to_vmx(vcpu);
4145 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4146 if (cpu_has_secondary_exec_ctrls()) {
4147 if (kvm_vcpu_apicv_active(vcpu))
4148 secondary_exec_controls_setbit(vmx,
4149 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4150 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4152 secondary_exec_controls_clearbit(vmx,
4153 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4154 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4157 vmx_update_msr_bitmap_x2apic(vcpu);
4160 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4162 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4164 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4165 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4167 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4168 exec_control &= ~CPU_BASED_TPR_SHADOW;
4169 #ifdef CONFIG_X86_64
4170 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4171 CPU_BASED_CR8_LOAD_EXITING;
4175 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4176 CPU_BASED_CR3_LOAD_EXITING |
4177 CPU_BASED_INVLPG_EXITING;
4178 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4179 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4180 CPU_BASED_MONITOR_EXITING);
4181 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4182 exec_control &= ~CPU_BASED_HLT_EXITING;
4183 return exec_control;
4187 * Adjust a single secondary execution control bit to intercept/allow an
4188 * instruction in the guest. This is usually done based on whether or not a
4189 * feature has been exposed to the guest in order to correctly emulate faults.
4192 vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control,
4193 u32 control, bool enabled, bool exiting)
4196 * If the control is for an opt-in feature, clear the control if the
4197 * feature is not exposed to the guest, i.e. not enabled. If the
4198 * control is opt-out, i.e. an exiting control, clear the control if
4199 * the feature _is_ exposed to the guest, i.e. exiting/interception is
4200 * disabled for the associated instruction. Note, the caller is
4201 * responsible presetting exec_control to set all supported bits.
4203 if (enabled == exiting)
4204 *exec_control &= ~control;
4207 * Update the nested MSR settings so that a nested VMM can/can't set
4208 * controls for features that are/aren't exposed to the guest.
4212 vmx->nested.msrs.secondary_ctls_high |= control;
4214 vmx->nested.msrs.secondary_ctls_high &= ~control;
4219 * Wrapper macro for the common case of adjusting a secondary execution control
4220 * based on a single guest CPUID bit, with a dedicated feature bit. This also
4221 * verifies that the control is actually supported by KVM and hardware.
4223 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \
4227 if (cpu_has_vmx_##name()) { \
4228 __enabled = guest_cpuid_has(&(vmx)->vcpu, \
4229 X86_FEATURE_##feat_name); \
4230 vmx_adjust_secondary_exec_control(vmx, exec_control, \
4231 SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \
4235 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */
4236 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \
4237 vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false)
4239 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \
4240 vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true)
4242 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4244 struct kvm_vcpu *vcpu = &vmx->vcpu;
4246 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4248 if (vmx_pt_mode_is_system())
4249 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4250 if (!cpu_need_virtualize_apic_accesses(vcpu))
4251 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4253 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4255 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4256 enable_unrestricted_guest = 0;
4258 if (!enable_unrestricted_guest)
4259 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4260 if (kvm_pause_in_guest(vmx->vcpu.kvm))
4261 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4262 if (!kvm_vcpu_apicv_active(vcpu))
4263 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4264 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4265 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4267 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4268 * in vmx_set_cr4. */
4269 exec_control &= ~SECONDARY_EXEC_DESC;
4271 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4273 We can NOT enable shadow_vmcs here because we don't have yet
4276 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4279 * PML is enabled/disabled when dirty logging of memsmlots changes, but
4280 * it needs to be set here when dirty logging is already active, e.g.
4281 * if this vCPU was created after dirty logging was enabled.
4283 if (!vcpu->kvm->arch.cpu_dirty_logging_count)
4284 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4286 if (cpu_has_vmx_xsaves()) {
4287 /* Exposing XSAVES only when XSAVE is exposed */
4288 bool xsaves_enabled =
4289 boot_cpu_has(X86_FEATURE_XSAVE) &&
4290 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4291 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4293 vcpu->arch.xsaves_enabled = xsaves_enabled;
4295 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4296 SECONDARY_EXEC_XSAVES,
4297 xsaves_enabled, false);
4301 * RDPID is also gated by ENABLE_RDTSCP, turn on the control if either
4302 * feature is exposed to the guest. This creates a virtualization hole
4303 * if both are supported in hardware but only one is exposed to the
4304 * guest, but letting the guest execute RDTSCP or RDPID when either one
4305 * is advertised is preferable to emulating the advertised instruction
4306 * in KVM on #UD, and obviously better than incorrectly injecting #UD.
4308 if (cpu_has_vmx_rdtscp()) {
4309 bool rdpid_or_rdtscp_enabled =
4310 guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) ||
4311 guest_cpuid_has(vcpu, X86_FEATURE_RDPID);
4313 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4314 SECONDARY_EXEC_ENABLE_RDTSCP,
4315 rdpid_or_rdtscp_enabled, false);
4317 vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID);
4319 vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND);
4320 vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED);
4322 vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG,
4323 ENABLE_USR_WAIT_PAUSE, false);
4325 if (!vcpu->kvm->arch.bus_lock_detection_enabled)
4326 exec_control &= ~SECONDARY_EXEC_BUS_LOCK_DETECTION;
4328 return exec_control;
4331 #define VMX_XSS_EXIT_BITMAP 0
4333 static void init_vmcs(struct vcpu_vmx *vmx)
4336 nested_vmx_set_vmcs_shadowing_bitmap();
4338 if (cpu_has_vmx_msr_bitmap())
4339 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4341 vmcs_write64(VMCS_LINK_POINTER, INVALID_GPA); /* 22.3.1.5 */
4344 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4346 exec_controls_set(vmx, vmx_exec_control(vmx));
4348 if (cpu_has_secondary_exec_ctrls())
4349 secondary_exec_controls_set(vmx, vmx_secondary_exec_control(vmx));
4351 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4352 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4353 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4354 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4355 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4357 vmcs_write16(GUEST_INTR_STATUS, 0);
4359 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4360 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4363 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4364 vmcs_write32(PLE_GAP, ple_gap);
4365 vmx->ple_window = ple_window;
4366 vmx->ple_window_dirty = true;
4369 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4370 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4371 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4373 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4374 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4375 vmx_set_constant_host_state(vmx);
4376 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4377 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4379 if (cpu_has_vmx_vmfunc())
4380 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4382 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4383 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4384 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4385 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4386 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4388 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4389 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4391 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4393 /* 22.2.1, 20.8.1 */
4394 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4396 vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4397 vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4399 set_cr4_guest_host_mask(vmx);
4402 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4404 if (cpu_has_vmx_xsaves())
4405 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4408 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4409 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4412 vmx_write_encls_bitmap(&vmx->vcpu, NULL);
4414 if (vmx_pt_mode_is_host_guest()) {
4415 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4416 /* Bit[6~0] are forced to 1, writes are ignored. */
4417 vmx->pt_desc.guest.output_mask = 0x7F;
4418 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4421 vmcs_write32(GUEST_SYSENTER_CS, 0);
4422 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4423 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4424 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4426 if (cpu_has_vmx_tpr_shadow()) {
4427 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4428 if (cpu_need_tpr_shadow(&vmx->vcpu))
4429 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4430 __pa(vmx->vcpu.arch.apic->regs));
4431 vmcs_write32(TPR_THRESHOLD, 0);
4434 vmx_setup_uret_msrs(vmx);
4437 static void __vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4439 struct vcpu_vmx *vmx = to_vmx(vcpu);
4444 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
4446 vcpu_setup_sgx_lepubkeyhash(vcpu);
4448 vmx->nested.posted_intr_nv = -1;
4449 vmx->nested.vmxon_ptr = INVALID_GPA;
4450 vmx->nested.current_vmptr = INVALID_GPA;
4451 vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
4453 vcpu->arch.microcode_version = 0x100000000ULL;
4454 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
4457 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
4458 * or POSTED_INTR_WAKEUP_VECTOR.
4460 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
4461 vmx->pi_desc.sn = 1;
4464 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4466 struct vcpu_vmx *vmx = to_vmx(vcpu);
4469 __vmx_vcpu_reset(vcpu);
4471 vmx->rmode.vm86_active = 0;
4474 vmx->msr_ia32_umwait_control = 0;
4476 vmx->hv_deadline_tsc = -1;
4477 kvm_set_cr8(vcpu, 0);
4479 vmx_segment_cache_clear(vmx);
4480 kvm_register_mark_available(vcpu, VCPU_EXREG_SEGMENTS);
4482 seg_setup(VCPU_SREG_CS);
4483 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4484 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4486 seg_setup(VCPU_SREG_DS);
4487 seg_setup(VCPU_SREG_ES);
4488 seg_setup(VCPU_SREG_FS);
4489 seg_setup(VCPU_SREG_GS);
4490 seg_setup(VCPU_SREG_SS);
4492 vmcs_write16(GUEST_TR_SELECTOR, 0);
4493 vmcs_writel(GUEST_TR_BASE, 0);
4494 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4495 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4497 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4498 vmcs_writel(GUEST_LDTR_BASE, 0);
4499 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4500 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4502 vmcs_writel(GUEST_GDTR_BASE, 0);
4503 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4505 vmcs_writel(GUEST_IDTR_BASE, 0);
4506 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4508 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4509 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4510 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4511 if (kvm_mpx_supported())
4512 vmcs_write64(GUEST_BNDCFGS, 0);
4514 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4516 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4518 vpid_sync_context(vmx->vpid);
4521 static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
4523 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4526 static void vmx_enable_nmi_window(struct kvm_vcpu *vcpu)
4529 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4530 vmx_enable_irq_window(vcpu);
4534 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4537 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4539 struct vcpu_vmx *vmx = to_vmx(vcpu);
4541 int irq = vcpu->arch.interrupt.nr;
4543 trace_kvm_inj_virq(irq);
4545 ++vcpu->stat.irq_injections;
4546 if (vmx->rmode.vm86_active) {
4548 if (vcpu->arch.interrupt.soft)
4549 inc_eip = vcpu->arch.event_exit_inst_len;
4550 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4553 intr = irq | INTR_INFO_VALID_MASK;
4554 if (vcpu->arch.interrupt.soft) {
4555 intr |= INTR_TYPE_SOFT_INTR;
4556 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4557 vmx->vcpu.arch.event_exit_inst_len);
4559 intr |= INTR_TYPE_EXT_INTR;
4560 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4562 vmx_clear_hlt(vcpu);
4565 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4567 struct vcpu_vmx *vmx = to_vmx(vcpu);
4571 * Tracking the NMI-blocked state in software is built upon
4572 * finding the next open IRQ window. This, in turn, depends on
4573 * well-behaving guests: They have to keep IRQs disabled at
4574 * least as long as the NMI handler runs. Otherwise we may
4575 * cause NMI nesting, maybe breaking the guest. But as this is
4576 * highly unlikely, we can live with the residual risk.
4578 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4579 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4582 ++vcpu->stat.nmi_injections;
4583 vmx->loaded_vmcs->nmi_known_unmasked = false;
4585 if (vmx->rmode.vm86_active) {
4586 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4590 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4591 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4593 vmx_clear_hlt(vcpu);
4596 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4598 struct vcpu_vmx *vmx = to_vmx(vcpu);
4602 return vmx->loaded_vmcs->soft_vnmi_blocked;
4603 if (vmx->loaded_vmcs->nmi_known_unmasked)
4605 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4606 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4610 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4612 struct vcpu_vmx *vmx = to_vmx(vcpu);
4615 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4616 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4617 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4620 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4622 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4623 GUEST_INTR_STATE_NMI);
4625 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4626 GUEST_INTR_STATE_NMI);
4630 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4632 if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4635 if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4638 return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4639 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4640 GUEST_INTR_STATE_NMI));
4643 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4645 if (to_vmx(vcpu)->nested.nested_run_pending)
4648 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
4649 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4652 return !vmx_nmi_blocked(vcpu);
4655 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4657 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4660 return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4661 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4662 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4665 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4667 if (to_vmx(vcpu)->nested.nested_run_pending)
4671 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4672 * e.g. if the IRQ arrived asynchronously after checking nested events.
4674 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4677 return !vmx_interrupt_blocked(vcpu);
4680 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4684 if (enable_unrestricted_guest)
4687 mutex_lock(&kvm->slots_lock);
4688 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4690 mutex_unlock(&kvm->slots_lock);
4693 return PTR_ERR(ret);
4695 to_kvm_vmx(kvm)->tss_addr = addr;
4697 return init_rmode_tss(kvm, ret);
4700 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4702 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4706 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4711 * Update instruction length as we may reinject the exception
4712 * from user space while in guest debugging mode.
4714 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4715 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4716 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4720 return !(vcpu->guest_debug &
4721 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4735 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4736 int vec, u32 err_code)
4739 * Instruction with address size override prefix opcode 0x67
4740 * Cause the #SS fault with 0 error code in VM86 mode.
4742 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4743 if (kvm_emulate_instruction(vcpu, 0)) {
4744 if (vcpu->arch.halt_request) {
4745 vcpu->arch.halt_request = 0;
4746 return kvm_vcpu_halt(vcpu);
4754 * Forward all other exceptions that are valid in real mode.
4755 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4756 * the required debugging infrastructure rework.
4758 kvm_queue_exception(vcpu, vec);
4762 static int handle_machine_check(struct kvm_vcpu *vcpu)
4764 /* handled by vmx_vcpu_run() */
4769 * If the host has split lock detection disabled, then #AC is
4770 * unconditionally injected into the guest, which is the pre split lock
4771 * detection behaviour.
4773 * If the host has split lock detection enabled then #AC is
4774 * only injected into the guest when:
4775 * - Guest CPL == 3 (user mode)
4776 * - Guest has #AC detection enabled in CR0
4777 * - Guest EFLAGS has AC bit set
4779 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu)
4781 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4784 return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4785 (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4788 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4790 struct vcpu_vmx *vmx = to_vmx(vcpu);
4791 struct kvm_run *kvm_run = vcpu->run;
4792 u32 intr_info, ex_no, error_code;
4793 unsigned long cr2, dr6;
4796 vect_info = vmx->idt_vectoring_info;
4797 intr_info = vmx_get_intr_info(vcpu);
4799 if (is_machine_check(intr_info) || is_nmi(intr_info))
4800 return 1; /* handled by handle_exception_nmi_irqoff() */
4802 if (is_invalid_opcode(intr_info))
4803 return handle_ud(vcpu);
4806 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4807 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4809 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4810 WARN_ON_ONCE(!enable_vmware_backdoor);
4813 * VMware backdoor emulation on #GP interception only handles
4814 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4815 * error code on #GP.
4818 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4821 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4825 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4826 * MMIO, it is better to report an internal error.
4827 * See the comments in vmx_handle_exit.
4829 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4830 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4831 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4832 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4833 vcpu->run->internal.ndata = 4;
4834 vcpu->run->internal.data[0] = vect_info;
4835 vcpu->run->internal.data[1] = intr_info;
4836 vcpu->run->internal.data[2] = error_code;
4837 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4841 if (is_page_fault(intr_info)) {
4842 cr2 = vmx_get_exit_qual(vcpu);
4843 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4845 * EPT will cause page fault only if we need to
4846 * detect illegal GPAs.
4848 WARN_ON_ONCE(!allow_smaller_maxphyaddr);
4849 kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4852 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4855 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4857 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4858 return handle_rmode_exception(vcpu, ex_no, error_code);
4862 dr6 = vmx_get_exit_qual(vcpu);
4863 if (!(vcpu->guest_debug &
4864 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4865 if (is_icebp(intr_info))
4866 WARN_ON(!skip_emulated_instruction(vcpu));
4868 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4871 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
4872 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4876 * Update instruction length as we may reinject #BP from
4877 * user space while in guest debugging mode. Reading it for
4878 * #DB as well causes no harm, it is not used in that case.
4880 vmx->vcpu.arch.event_exit_inst_len =
4881 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4882 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4883 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4884 kvm_run->debug.arch.exception = ex_no;
4887 if (vmx_guest_inject_ac(vcpu)) {
4888 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4893 * Handle split lock. Depending on detection mode this will
4894 * either warn and disable split lock detection for this
4895 * task or force SIGBUS on it.
4897 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4901 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4902 kvm_run->ex.exception = ex_no;
4903 kvm_run->ex.error_code = error_code;
4909 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4911 ++vcpu->stat.irq_exits;
4915 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4917 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4918 vcpu->mmio_needed = 0;
4922 static int handle_io(struct kvm_vcpu *vcpu)
4924 unsigned long exit_qualification;
4925 int size, in, string;
4928 exit_qualification = vmx_get_exit_qual(vcpu);
4929 string = (exit_qualification & 16) != 0;
4931 ++vcpu->stat.io_exits;
4934 return kvm_emulate_instruction(vcpu, 0);
4936 port = exit_qualification >> 16;
4937 size = (exit_qualification & 7) + 1;
4938 in = (exit_qualification & 8) != 0;
4940 return kvm_fast_pio(vcpu, size, port, in);
4944 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4947 * Patch in the VMCALL instruction:
4949 hypercall[0] = 0x0f;
4950 hypercall[1] = 0x01;
4951 hypercall[2] = 0xc1;
4954 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4955 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4957 if (is_guest_mode(vcpu)) {
4958 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4959 unsigned long orig_val = val;
4962 * We get here when L2 changed cr0 in a way that did not change
4963 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4964 * but did change L0 shadowed bits. So we first calculate the
4965 * effective cr0 value that L1 would like to write into the
4966 * hardware. It consists of the L2-owned bits from the new
4967 * value combined with the L1-owned bits from L1's guest_cr0.
4969 val = (val & ~vmcs12->cr0_guest_host_mask) |
4970 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4972 if (!nested_guest_cr0_valid(vcpu, val))
4975 if (kvm_set_cr0(vcpu, val))
4977 vmcs_writel(CR0_READ_SHADOW, orig_val);
4980 if (to_vmx(vcpu)->nested.vmxon &&
4981 !nested_host_cr0_valid(vcpu, val))
4984 return kvm_set_cr0(vcpu, val);
4988 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4990 if (is_guest_mode(vcpu)) {
4991 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4992 unsigned long orig_val = val;
4994 /* analogously to handle_set_cr0 */
4995 val = (val & ~vmcs12->cr4_guest_host_mask) |
4996 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4997 if (kvm_set_cr4(vcpu, val))
4999 vmcs_writel(CR4_READ_SHADOW, orig_val);
5002 return kvm_set_cr4(vcpu, val);
5005 static int handle_desc(struct kvm_vcpu *vcpu)
5007 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
5008 return kvm_emulate_instruction(vcpu, 0);
5011 static int handle_cr(struct kvm_vcpu *vcpu)
5013 unsigned long exit_qualification, val;
5019 exit_qualification = vmx_get_exit_qual(vcpu);
5020 cr = exit_qualification & 15;
5021 reg = (exit_qualification >> 8) & 15;
5022 switch ((exit_qualification >> 4) & 3) {
5023 case 0: /* mov to cr */
5024 val = kvm_register_read(vcpu, reg);
5025 trace_kvm_cr_write(cr, val);
5028 err = handle_set_cr0(vcpu, val);
5029 return kvm_complete_insn_gp(vcpu, err);
5031 WARN_ON_ONCE(enable_unrestricted_guest);
5033 err = kvm_set_cr3(vcpu, val);
5034 return kvm_complete_insn_gp(vcpu, err);
5036 err = handle_set_cr4(vcpu, val);
5037 return kvm_complete_insn_gp(vcpu, err);
5039 u8 cr8_prev = kvm_get_cr8(vcpu);
5041 err = kvm_set_cr8(vcpu, cr8);
5042 ret = kvm_complete_insn_gp(vcpu, err);
5043 if (lapic_in_kernel(vcpu))
5045 if (cr8_prev <= cr8)
5048 * TODO: we might be squashing a
5049 * KVM_GUESTDBG_SINGLESTEP-triggered
5050 * KVM_EXIT_DEBUG here.
5052 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5058 KVM_BUG(1, vcpu->kvm, "Guest always owns CR0.TS");
5060 case 1: /*mov from cr*/
5063 WARN_ON_ONCE(enable_unrestricted_guest);
5065 val = kvm_read_cr3(vcpu);
5066 kvm_register_write(vcpu, reg, val);
5067 trace_kvm_cr_read(cr, val);
5068 return kvm_skip_emulated_instruction(vcpu);
5070 val = kvm_get_cr8(vcpu);
5071 kvm_register_write(vcpu, reg, val);
5072 trace_kvm_cr_read(cr, val);
5073 return kvm_skip_emulated_instruction(vcpu);
5077 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5078 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5079 kvm_lmsw(vcpu, val);
5081 return kvm_skip_emulated_instruction(vcpu);
5085 vcpu->run->exit_reason = 0;
5086 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5087 (int)(exit_qualification >> 4) & 3, cr);
5091 static int handle_dr(struct kvm_vcpu *vcpu)
5093 unsigned long exit_qualification;
5097 exit_qualification = vmx_get_exit_qual(vcpu);
5098 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5100 /* First, if DR does not exist, trigger UD */
5101 if (!kvm_require_dr(vcpu, dr))
5104 if (kvm_x86_ops.get_cpl(vcpu) > 0)
5107 dr7 = vmcs_readl(GUEST_DR7);
5110 * As the vm-exit takes precedence over the debug trap, we
5111 * need to emulate the latter, either for the host or the
5112 * guest debugging itself.
5114 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5115 vcpu->run->debug.arch.dr6 = DR6_BD | DR6_ACTIVE_LOW;
5116 vcpu->run->debug.arch.dr7 = dr7;
5117 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5118 vcpu->run->debug.arch.exception = DB_VECTOR;
5119 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5122 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5127 if (vcpu->guest_debug == 0) {
5128 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5131 * No more DR vmexits; force a reload of the debug registers
5132 * and reenter on this instruction. The next vmexit will
5133 * retrieve the full state of the debug registers.
5135 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5139 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5140 if (exit_qualification & TYPE_MOV_FROM_DR) {
5143 kvm_get_dr(vcpu, dr, &val);
5144 kvm_register_write(vcpu, reg, val);
5147 err = kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg));
5151 return kvm_complete_insn_gp(vcpu, err);
5154 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5156 get_debugreg(vcpu->arch.db[0], 0);
5157 get_debugreg(vcpu->arch.db[1], 1);
5158 get_debugreg(vcpu->arch.db[2], 2);
5159 get_debugreg(vcpu->arch.db[3], 3);
5160 get_debugreg(vcpu->arch.dr6, 6);
5161 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5163 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5164 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5167 * exc_debug expects dr6 to be cleared after it runs, avoid that it sees
5168 * a stale dr6 from the guest.
5170 set_debugreg(DR6_RESERVED, 6);
5173 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5175 vmcs_writel(GUEST_DR7, val);
5178 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5180 kvm_apic_update_ppr(vcpu);
5184 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5186 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5188 kvm_make_request(KVM_REQ_EVENT, vcpu);
5190 ++vcpu->stat.irq_window_exits;
5194 static int handle_invlpg(struct kvm_vcpu *vcpu)
5196 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5198 kvm_mmu_invlpg(vcpu, exit_qualification);
5199 return kvm_skip_emulated_instruction(vcpu);
5202 static int handle_apic_access(struct kvm_vcpu *vcpu)
5204 if (likely(fasteoi)) {
5205 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5206 int access_type, offset;
5208 access_type = exit_qualification & APIC_ACCESS_TYPE;
5209 offset = exit_qualification & APIC_ACCESS_OFFSET;
5211 * Sane guest uses MOV to write EOI, with written value
5212 * not cared. So make a short-circuit here by avoiding
5213 * heavy instruction emulation.
5215 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5216 (offset == APIC_EOI)) {
5217 kvm_lapic_set_eoi(vcpu);
5218 return kvm_skip_emulated_instruction(vcpu);
5221 return kvm_emulate_instruction(vcpu, 0);
5224 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5226 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5227 int vector = exit_qualification & 0xff;
5229 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5230 kvm_apic_set_eoi_accelerated(vcpu, vector);
5234 static int handle_apic_write(struct kvm_vcpu *vcpu)
5236 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5237 u32 offset = exit_qualification & 0xfff;
5239 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5240 kvm_apic_write_nodecode(vcpu, offset);
5244 static int handle_task_switch(struct kvm_vcpu *vcpu)
5246 struct vcpu_vmx *vmx = to_vmx(vcpu);
5247 unsigned long exit_qualification;
5248 bool has_error_code = false;
5251 int reason, type, idt_v, idt_index;
5253 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5254 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5255 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5257 exit_qualification = vmx_get_exit_qual(vcpu);
5259 reason = (u32)exit_qualification >> 30;
5260 if (reason == TASK_SWITCH_GATE && idt_v) {
5262 case INTR_TYPE_NMI_INTR:
5263 vcpu->arch.nmi_injected = false;
5264 vmx_set_nmi_mask(vcpu, true);
5266 case INTR_TYPE_EXT_INTR:
5267 case INTR_TYPE_SOFT_INTR:
5268 kvm_clear_interrupt_queue(vcpu);
5270 case INTR_TYPE_HARD_EXCEPTION:
5271 if (vmx->idt_vectoring_info &
5272 VECTORING_INFO_DELIVER_CODE_MASK) {
5273 has_error_code = true;
5275 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5278 case INTR_TYPE_SOFT_EXCEPTION:
5279 kvm_clear_exception_queue(vcpu);
5285 tss_selector = exit_qualification;
5287 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5288 type != INTR_TYPE_EXT_INTR &&
5289 type != INTR_TYPE_NMI_INTR))
5290 WARN_ON(!skip_emulated_instruction(vcpu));
5293 * TODO: What about debug traps on tss switch?
5294 * Are we supposed to inject them and update dr6?
5296 return kvm_task_switch(vcpu, tss_selector,
5297 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5298 reason, has_error_code, error_code);
5301 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5303 unsigned long exit_qualification;
5307 exit_qualification = vmx_get_exit_qual(vcpu);
5310 * EPT violation happened while executing iret from NMI,
5311 * "blocked by NMI" bit has to be set before next VM entry.
5312 * There are errata that may cause this bit to not be set:
5315 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5317 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5318 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5320 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5321 trace_kvm_page_fault(gpa, exit_qualification);
5323 /* Is it a read fault? */
5324 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5325 ? PFERR_USER_MASK : 0;
5326 /* Is it a write fault? */
5327 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5328 ? PFERR_WRITE_MASK : 0;
5329 /* Is it a fetch fault? */
5330 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5331 ? PFERR_FETCH_MASK : 0;
5332 /* ept page table entry is present? */
5333 error_code |= (exit_qualification &
5334 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5335 EPT_VIOLATION_EXECUTABLE))
5336 ? PFERR_PRESENT_MASK : 0;
5338 error_code |= (exit_qualification & EPT_VIOLATION_GVA_TRANSLATED) != 0 ?
5339 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5341 vcpu->arch.exit_qualification = exit_qualification;
5344 * Check that the GPA doesn't exceed physical memory limits, as that is
5345 * a guest page fault. We have to emulate the instruction here, because
5346 * if the illegal address is that of a paging structure, then
5347 * EPT_VIOLATION_ACC_WRITE bit is set. Alternatively, if supported we
5348 * would also use advanced VM-exit information for EPT violations to
5349 * reconstruct the page fault error code.
5351 if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa)))
5352 return kvm_emulate_instruction(vcpu, 0);
5354 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5357 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5361 if (!vmx_can_emulate_instruction(vcpu, NULL, 0))
5365 * A nested guest cannot optimize MMIO vmexits, because we have an
5366 * nGPA here instead of the required GPA.
5368 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5369 if (!is_guest_mode(vcpu) &&
5370 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5371 trace_kvm_fast_mmio(gpa);
5372 return kvm_skip_emulated_instruction(vcpu);
5375 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5378 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5380 if (KVM_BUG_ON(!enable_vnmi, vcpu->kvm))
5383 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5384 ++vcpu->stat.nmi_window_exits;
5385 kvm_make_request(KVM_REQ_EVENT, vcpu);
5390 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5392 struct vcpu_vmx *vmx = to_vmx(vcpu);
5393 bool intr_window_requested;
5394 unsigned count = 130;
5396 intr_window_requested = exec_controls_get(vmx) &
5397 CPU_BASED_INTR_WINDOW_EXITING;
5399 while (vmx->emulation_required && count-- != 0) {
5400 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5401 return handle_interrupt_window(&vmx->vcpu);
5403 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5406 if (!kvm_emulate_instruction(vcpu, 0))
5409 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5410 vcpu->arch.exception.pending) {
5411 kvm_prepare_emulation_failure_exit(vcpu);
5415 if (vcpu->arch.halt_request) {
5416 vcpu->arch.halt_request = 0;
5417 return kvm_vcpu_halt(vcpu);
5421 * Note, return 1 and not 0, vcpu_run() will invoke
5422 * xfer_to_guest_mode() which will create a proper return
5425 if (__xfer_to_guest_mode_work_pending())
5432 static void grow_ple_window(struct kvm_vcpu *vcpu)
5434 struct vcpu_vmx *vmx = to_vmx(vcpu);
5435 unsigned int old = vmx->ple_window;
5437 vmx->ple_window = __grow_ple_window(old, ple_window,
5441 if (vmx->ple_window != old) {
5442 vmx->ple_window_dirty = true;
5443 trace_kvm_ple_window_update(vcpu->vcpu_id,
5444 vmx->ple_window, old);
5448 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5450 struct vcpu_vmx *vmx = to_vmx(vcpu);
5451 unsigned int old = vmx->ple_window;
5453 vmx->ple_window = __shrink_ple_window(old, ple_window,
5457 if (vmx->ple_window != old) {
5458 vmx->ple_window_dirty = true;
5459 trace_kvm_ple_window_update(vcpu->vcpu_id,
5460 vmx->ple_window, old);
5465 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5466 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5468 static int handle_pause(struct kvm_vcpu *vcpu)
5470 if (!kvm_pause_in_guest(vcpu->kvm))
5471 grow_ple_window(vcpu);
5474 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5475 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5476 * never set PAUSE_EXITING and just set PLE if supported,
5477 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5479 kvm_vcpu_on_spin(vcpu, true);
5480 return kvm_skip_emulated_instruction(vcpu);
5483 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5488 static int handle_invpcid(struct kvm_vcpu *vcpu)
5490 u32 vmx_instruction_info;
5498 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5499 kvm_queue_exception(vcpu, UD_VECTOR);
5503 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5504 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
5507 kvm_inject_gp(vcpu, 0);
5511 /* According to the Intel instruction reference, the memory operand
5512 * is read even if it isn't needed (e.g., for type==all)
5514 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5515 vmx_instruction_info, false,
5516 sizeof(operand), &gva))
5519 return kvm_handle_invpcid(vcpu, type, gva);
5522 static int handle_pml_full(struct kvm_vcpu *vcpu)
5524 unsigned long exit_qualification;
5526 trace_kvm_pml_full(vcpu->vcpu_id);
5528 exit_qualification = vmx_get_exit_qual(vcpu);
5531 * PML buffer FULL happened while executing iret from NMI,
5532 * "blocked by NMI" bit has to be set before next VM entry.
5534 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5536 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5537 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5538 GUEST_INTR_STATE_NMI);
5541 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5542 * here.., and there's no userspace involvement needed for PML.
5547 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5549 struct vcpu_vmx *vmx = to_vmx(vcpu);
5551 if (!vmx->req_immediate_exit &&
5552 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5553 kvm_lapic_expired_hv_timer(vcpu);
5554 return EXIT_FASTPATH_REENTER_GUEST;
5557 return EXIT_FASTPATH_NONE;
5560 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5562 handle_fastpath_preemption_timer(vcpu);
5567 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5568 * are overwritten by nested_vmx_setup() when nested=1.
5570 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5572 kvm_queue_exception(vcpu, UD_VECTOR);
5576 #ifndef CONFIG_X86_SGX_KVM
5577 static int handle_encls(struct kvm_vcpu *vcpu)
5580 * SGX virtualization is disabled. There is no software enable bit for
5581 * SGX, so KVM intercepts all ENCLS leafs and injects a #UD to prevent
5582 * the guest from executing ENCLS (when SGX is supported by hardware).
5584 kvm_queue_exception(vcpu, UD_VECTOR);
5587 #endif /* CONFIG_X86_SGX_KVM */
5589 static int handle_bus_lock_vmexit(struct kvm_vcpu *vcpu)
5592 * Hardware may or may not set the BUS_LOCK_DETECTED flag on BUS_LOCK
5593 * VM-Exits. Unconditionally set the flag here and leave the handling to
5594 * vmx_handle_exit().
5596 to_vmx(vcpu)->exit_reason.bus_lock_detected = true;
5601 * The exit handlers return 1 if the exit was handled fully and guest execution
5602 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5603 * to be done to userspace and return 0.
5605 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5606 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5607 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5608 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5609 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5610 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5611 [EXIT_REASON_CR_ACCESS] = handle_cr,
5612 [EXIT_REASON_DR_ACCESS] = handle_dr,
5613 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5614 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5615 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
5616 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
5617 [EXIT_REASON_HLT] = kvm_emulate_halt,
5618 [EXIT_REASON_INVD] = kvm_emulate_invd,
5619 [EXIT_REASON_INVLPG] = handle_invlpg,
5620 [EXIT_REASON_RDPMC] = kvm_emulate_rdpmc,
5621 [EXIT_REASON_VMCALL] = kvm_emulate_hypercall,
5622 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5623 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5624 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5625 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5626 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5627 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5628 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5629 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5630 [EXIT_REASON_VMON] = handle_vmx_instruction,
5631 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5632 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5633 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5634 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5635 [EXIT_REASON_WBINVD] = kvm_emulate_wbinvd,
5636 [EXIT_REASON_XSETBV] = kvm_emulate_xsetbv,
5637 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5638 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5639 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5640 [EXIT_REASON_LDTR_TR] = handle_desc,
5641 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5642 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5643 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5644 [EXIT_REASON_MWAIT_INSTRUCTION] = kvm_emulate_mwait,
5645 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5646 [EXIT_REASON_MONITOR_INSTRUCTION] = kvm_emulate_monitor,
5647 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5648 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5649 [EXIT_REASON_RDRAND] = kvm_handle_invalid_op,
5650 [EXIT_REASON_RDSEED] = kvm_handle_invalid_op,
5651 [EXIT_REASON_PML_FULL] = handle_pml_full,
5652 [EXIT_REASON_INVPCID] = handle_invpcid,
5653 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5654 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5655 [EXIT_REASON_ENCLS] = handle_encls,
5656 [EXIT_REASON_BUS_LOCK] = handle_bus_lock_vmexit,
5659 static const int kvm_vmx_max_exit_handlers =
5660 ARRAY_SIZE(kvm_vmx_exit_handlers);
5662 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
5663 u64 *info1, u64 *info2,
5664 u32 *intr_info, u32 *error_code)
5666 struct vcpu_vmx *vmx = to_vmx(vcpu);
5668 *reason = vmx->exit_reason.full;
5669 *info1 = vmx_get_exit_qual(vcpu);
5670 if (!(vmx->exit_reason.failed_vmentry)) {
5671 *info2 = vmx->idt_vectoring_info;
5672 *intr_info = vmx_get_intr_info(vcpu);
5673 if (is_exception_with_error_code(*intr_info))
5674 *error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5684 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5687 __free_page(vmx->pml_pg);
5692 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5694 struct vcpu_vmx *vmx = to_vmx(vcpu);
5698 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5700 /* Do nothing if PML buffer is empty */
5701 if (pml_idx == (PML_ENTITY_NUM - 1))
5704 /* PML index always points to next available PML buffer entity */
5705 if (pml_idx >= PML_ENTITY_NUM)
5710 pml_buf = page_address(vmx->pml_pg);
5711 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5714 gpa = pml_buf[pml_idx];
5715 WARN_ON(gpa & (PAGE_SIZE - 1));
5716 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5719 /* reset PML index */
5720 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5723 static void vmx_dump_sel(char *name, uint32_t sel)
5725 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5726 name, vmcs_read16(sel),
5727 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5728 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5729 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5732 static void vmx_dump_dtsel(char *name, uint32_t limit)
5734 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5735 name, vmcs_read32(limit),
5736 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5739 static void vmx_dump_msrs(char *name, struct vmx_msrs *m)
5742 struct vmx_msr_entry *e;
5744 pr_err("MSR %s:\n", name);
5745 for (i = 0, e = m->val; i < m->nr; ++i, ++e)
5746 pr_err(" %2d: msr=0x%08x value=0x%016llx\n", i, e->index, e->value);
5749 void dump_vmcs(struct kvm_vcpu *vcpu)
5751 struct vcpu_vmx *vmx = to_vmx(vcpu);
5752 u32 vmentry_ctl, vmexit_ctl;
5753 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5757 if (!dump_invalid_vmcs) {
5758 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5762 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5763 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5764 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5765 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5766 cr4 = vmcs_readl(GUEST_CR4);
5767 secondary_exec_control = 0;
5768 if (cpu_has_secondary_exec_ctrls())
5769 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5771 pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
5772 vmx->loaded_vmcs->vmcs, vcpu->arch.last_vmentry_cpu);
5773 pr_err("*** Guest State ***\n");
5774 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5775 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5776 vmcs_readl(CR0_GUEST_HOST_MASK));
5777 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5778 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5779 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5780 if (cpu_has_vmx_ept()) {
5781 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5782 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5783 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5784 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5786 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5787 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5788 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5789 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5790 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5791 vmcs_readl(GUEST_SYSENTER_ESP),
5792 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5793 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5794 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5795 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5796 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5797 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5798 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5799 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5800 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5801 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5802 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5803 efer_slot = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, MSR_EFER);
5804 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_EFER)
5805 pr_err("EFER= 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER));
5806 else if (efer_slot >= 0)
5807 pr_err("EFER= 0x%016llx (autoload)\n",
5808 vmx->msr_autoload.guest.val[efer_slot].value);
5809 else if (vmentry_ctl & VM_ENTRY_IA32E_MODE)
5810 pr_err("EFER= 0x%016llx (effective)\n",
5811 vcpu->arch.efer | (EFER_LMA | EFER_LME));
5813 pr_err("EFER= 0x%016llx (effective)\n",
5814 vcpu->arch.efer & ~(EFER_LMA | EFER_LME));
5815 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PAT)
5816 pr_err("PAT = 0x%016llx\n", vmcs_read64(GUEST_IA32_PAT));
5817 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5818 vmcs_read64(GUEST_IA32_DEBUGCTL),
5819 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5820 if (cpu_has_load_perf_global_ctrl() &&
5821 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5822 pr_err("PerfGlobCtl = 0x%016llx\n",
5823 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5824 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5825 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5826 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5827 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5828 vmcs_read32(GUEST_ACTIVITY_STATE));
5829 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5830 pr_err("InterruptStatus = %04x\n",
5831 vmcs_read16(GUEST_INTR_STATUS));
5832 if (vmcs_read32(VM_ENTRY_MSR_LOAD_COUNT) > 0)
5833 vmx_dump_msrs("guest autoload", &vmx->msr_autoload.guest);
5834 if (vmcs_read32(VM_EXIT_MSR_STORE_COUNT) > 0)
5835 vmx_dump_msrs("guest autostore", &vmx->msr_autostore.guest);
5837 pr_err("*** Host State ***\n");
5838 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5839 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5840 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5841 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5842 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5843 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5844 vmcs_read16(HOST_TR_SELECTOR));
5845 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5846 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5847 vmcs_readl(HOST_TR_BASE));
5848 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5849 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5850 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5851 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5852 vmcs_readl(HOST_CR4));
5853 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5854 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5855 vmcs_read32(HOST_IA32_SYSENTER_CS),
5856 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5857 if (vmexit_ctl & VM_EXIT_LOAD_IA32_EFER)
5858 pr_err("EFER= 0x%016llx\n", vmcs_read64(HOST_IA32_EFER));
5859 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PAT)
5860 pr_err("PAT = 0x%016llx\n", vmcs_read64(HOST_IA32_PAT));
5861 if (cpu_has_load_perf_global_ctrl() &&
5862 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5863 pr_err("PerfGlobCtl = 0x%016llx\n",
5864 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5865 if (vmcs_read32(VM_EXIT_MSR_LOAD_COUNT) > 0)
5866 vmx_dump_msrs("host autoload", &vmx->msr_autoload.host);
5868 pr_err("*** Control State ***\n");
5869 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5870 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5871 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5872 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5873 vmcs_read32(EXCEPTION_BITMAP),
5874 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5875 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5876 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5877 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5878 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5879 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5880 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5881 vmcs_read32(VM_EXIT_INTR_INFO),
5882 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5883 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5884 pr_err(" reason=%08x qualification=%016lx\n",
5885 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5886 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5887 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5888 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5889 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5890 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5891 pr_err("TSC Multiplier = 0x%016llx\n",
5892 vmcs_read64(TSC_MULTIPLIER));
5893 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5894 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5895 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5896 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5898 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5899 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5900 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5901 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5903 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5904 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5905 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5906 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5907 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5908 pr_err("PLE Gap=%08x Window=%08x\n",
5909 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5910 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5911 pr_err("Virtual processor ID = 0x%04x\n",
5912 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5916 * The guest has exited. See if we can fix it or if we need userspace
5919 static int __vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5921 struct vcpu_vmx *vmx = to_vmx(vcpu);
5922 union vmx_exit_reason exit_reason = vmx->exit_reason;
5923 u32 vectoring_info = vmx->idt_vectoring_info;
5924 u16 exit_handler_index;
5927 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5928 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5929 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5930 * mode as if vcpus is in root mode, the PML buffer must has been
5931 * flushed already. Note, PML is never enabled in hardware while
5934 if (enable_pml && !is_guest_mode(vcpu))
5935 vmx_flush_pml_buffer(vcpu);
5938 * We should never reach this point with a pending nested VM-Enter, and
5939 * more specifically emulation of L2 due to invalid guest state (see
5940 * below) should never happen as that means we incorrectly allowed a
5941 * nested VM-Enter with an invalid vmcs12.
5943 if (KVM_BUG_ON(vmx->nested.nested_run_pending, vcpu->kvm))
5946 /* If guest state is invalid, start emulating */
5947 if (vmx->emulation_required)
5948 return handle_invalid_guest_state(vcpu);
5950 if (is_guest_mode(vcpu)) {
5952 * PML is never enabled when running L2, bail immediately if a
5953 * PML full exit occurs as something is horribly wrong.
5955 if (exit_reason.basic == EXIT_REASON_PML_FULL)
5956 goto unexpected_vmexit;
5959 * The host physical addresses of some pages of guest memory
5960 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5961 * Page). The CPU may write to these pages via their host
5962 * physical address while L2 is running, bypassing any
5963 * address-translation-based dirty tracking (e.g. EPT write
5966 * Mark them dirty on every exit from L2 to prevent them from
5967 * getting out of sync with dirty tracking.
5969 nested_mark_vmcs12_pages_dirty(vcpu);
5971 if (nested_vmx_reflect_vmexit(vcpu))
5975 if (exit_reason.failed_vmentry) {
5977 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5978 vcpu->run->fail_entry.hardware_entry_failure_reason
5980 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5984 if (unlikely(vmx->fail)) {
5986 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5987 vcpu->run->fail_entry.hardware_entry_failure_reason
5988 = vmcs_read32(VM_INSTRUCTION_ERROR);
5989 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5995 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5996 * delivery event since it indicates guest is accessing MMIO.
5997 * The vm-exit can be triggered again after return to guest that
5998 * will cause infinite loop.
6000 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6001 (exit_reason.basic != EXIT_REASON_EXCEPTION_NMI &&
6002 exit_reason.basic != EXIT_REASON_EPT_VIOLATION &&
6003 exit_reason.basic != EXIT_REASON_PML_FULL &&
6004 exit_reason.basic != EXIT_REASON_APIC_ACCESS &&
6005 exit_reason.basic != EXIT_REASON_TASK_SWITCH)) {
6008 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6009 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6010 vcpu->run->internal.data[0] = vectoring_info;
6011 vcpu->run->internal.data[1] = exit_reason.full;
6012 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
6013 if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG) {
6014 vcpu->run->internal.data[ndata++] =
6015 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6017 vcpu->run->internal.data[ndata++] = vcpu->arch.last_vmentry_cpu;
6018 vcpu->run->internal.ndata = ndata;
6022 if (unlikely(!enable_vnmi &&
6023 vmx->loaded_vmcs->soft_vnmi_blocked)) {
6024 if (!vmx_interrupt_blocked(vcpu)) {
6025 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6026 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
6027 vcpu->arch.nmi_pending) {
6029 * This CPU don't support us in finding the end of an
6030 * NMI-blocked window if the guest runs with IRQs
6031 * disabled. So we pull the trigger after 1 s of
6032 * futile waiting, but inform the user about this.
6034 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6035 "state on VCPU %d after 1 s timeout\n",
6036 __func__, vcpu->vcpu_id);
6037 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6041 if (exit_fastpath != EXIT_FASTPATH_NONE)
6044 if (exit_reason.basic >= kvm_vmx_max_exit_handlers)
6045 goto unexpected_vmexit;
6046 #ifdef CONFIG_RETPOLINE
6047 if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
6048 return kvm_emulate_wrmsr(vcpu);
6049 else if (exit_reason.basic == EXIT_REASON_PREEMPTION_TIMER)
6050 return handle_preemption_timer(vcpu);
6051 else if (exit_reason.basic == EXIT_REASON_INTERRUPT_WINDOW)
6052 return handle_interrupt_window(vcpu);
6053 else if (exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6054 return handle_external_interrupt(vcpu);
6055 else if (exit_reason.basic == EXIT_REASON_HLT)
6056 return kvm_emulate_halt(vcpu);
6057 else if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG)
6058 return handle_ept_misconfig(vcpu);
6061 exit_handler_index = array_index_nospec((u16)exit_reason.basic,
6062 kvm_vmx_max_exit_handlers);
6063 if (!kvm_vmx_exit_handlers[exit_handler_index])
6064 goto unexpected_vmexit;
6066 return kvm_vmx_exit_handlers[exit_handler_index](vcpu);
6069 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
6072 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6073 vcpu->run->internal.suberror =
6074 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6075 vcpu->run->internal.ndata = 2;
6076 vcpu->run->internal.data[0] = exit_reason.full;
6077 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6081 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6083 int ret = __vmx_handle_exit(vcpu, exit_fastpath);
6086 * Exit to user space when bus lock detected to inform that there is
6087 * a bus lock in guest.
6089 if (to_vmx(vcpu)->exit_reason.bus_lock_detected) {
6091 vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
6093 vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
6100 * Software based L1D cache flush which is used when microcode providing
6101 * the cache control MSR is not loaded.
6103 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6104 * flush it is required to read in 64 KiB because the replacement algorithm
6105 * is not exactly LRU. This could be sized at runtime via topology
6106 * information but as all relevant affected CPUs have 32KiB L1D cache size
6107 * there is no point in doing so.
6109 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6111 int size = PAGE_SIZE << L1D_CACHE_ORDER;
6114 * This code is only executed when the the flush mode is 'cond' or
6117 if (static_branch_likely(&vmx_l1d_flush_cond)) {
6121 * Clear the per-vcpu flush bit, it gets set again
6122 * either from vcpu_run() or from one of the unsafe
6125 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6126 vcpu->arch.l1tf_flush_l1d = false;
6129 * Clear the per-cpu flush bit, it gets set again from
6130 * the interrupt handlers.
6132 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6133 kvm_clear_cpu_l1tf_flush_l1d();
6139 vcpu->stat.l1d_flush++;
6141 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6142 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6147 /* First ensure the pages are in the TLB */
6148 "xorl %%eax, %%eax\n"
6149 ".Lpopulate_tlb:\n\t"
6150 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6151 "addl $4096, %%eax\n\t"
6152 "cmpl %%eax, %[size]\n\t"
6153 "jne .Lpopulate_tlb\n\t"
6154 "xorl %%eax, %%eax\n\t"
6156 /* Now fill the cache */
6157 "xorl %%eax, %%eax\n"
6159 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6160 "addl $64, %%eax\n\t"
6161 "cmpl %%eax, %[size]\n\t"
6162 "jne .Lfill_cache\n\t"
6164 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6166 : "eax", "ebx", "ecx", "edx");
6169 static void vmx_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6171 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6174 if (is_guest_mode(vcpu) &&
6175 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6178 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6179 if (is_guest_mode(vcpu))
6180 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6182 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6185 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6187 struct vcpu_vmx *vmx = to_vmx(vcpu);
6188 u32 sec_exec_control;
6190 if (!lapic_in_kernel(vcpu))
6193 if (!flexpriority_enabled &&
6194 !cpu_has_vmx_virtualize_x2apic_mode())
6197 /* Postpone execution until vmcs01 is the current VMCS. */
6198 if (is_guest_mode(vcpu)) {
6199 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6203 sec_exec_control = secondary_exec_controls_get(vmx);
6204 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6205 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6207 switch (kvm_get_apic_mode(vcpu)) {
6208 case LAPIC_MODE_INVALID:
6209 WARN_ONCE(true, "Invalid local APIC state");
6211 case LAPIC_MODE_DISABLED:
6213 case LAPIC_MODE_XAPIC:
6214 if (flexpriority_enabled) {
6216 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6217 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6220 * Flush the TLB, reloading the APIC access page will
6221 * only do so if its physical address has changed, but
6222 * the guest may have inserted a non-APIC mapping into
6223 * the TLB while the APIC access page was disabled.
6225 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6228 case LAPIC_MODE_X2APIC:
6229 if (cpu_has_vmx_virtualize_x2apic_mode())
6231 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6234 secondary_exec_controls_set(vmx, sec_exec_control);
6236 vmx_update_msr_bitmap_x2apic(vcpu);
6239 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6243 /* Defer reload until vmcs01 is the current VMCS. */
6244 if (is_guest_mode(vcpu)) {
6245 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6249 if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6250 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6253 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6254 if (is_error_page(page))
6257 vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6258 vmx_flush_tlb_current(vcpu);
6261 * Do not pin apic access page in memory, the MMU notifier
6262 * will call us again if it is migrated or swapped out.
6267 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6275 status = vmcs_read16(GUEST_INTR_STATUS);
6277 if (max_isr != old) {
6279 status |= max_isr << 8;
6280 vmcs_write16(GUEST_INTR_STATUS, status);
6284 static void vmx_set_rvi(int vector)
6292 status = vmcs_read16(GUEST_INTR_STATUS);
6293 old = (u8)status & 0xff;
6294 if ((u8)vector != old) {
6296 status |= (u8)vector;
6297 vmcs_write16(GUEST_INTR_STATUS, status);
6301 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6304 * When running L2, updating RVI is only relevant when
6305 * vmcs12 virtual-interrupt-delivery enabled.
6306 * However, it can be enabled only when L1 also
6307 * intercepts external-interrupts and in that case
6308 * we should not update vmcs02 RVI but instead intercept
6309 * interrupt. Therefore, do nothing when running L2.
6311 if (!is_guest_mode(vcpu))
6312 vmx_set_rvi(max_irr);
6315 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6317 struct vcpu_vmx *vmx = to_vmx(vcpu);
6319 bool max_irr_updated;
6321 if (KVM_BUG_ON(!vcpu->arch.apicv_active, vcpu->kvm))
6324 if (pi_test_on(&vmx->pi_desc)) {
6325 pi_clear_on(&vmx->pi_desc);
6327 * IOMMU can write to PID.ON, so the barrier matters even on UP.
6328 * But on x86 this is just a compiler barrier anyway.
6330 smp_mb__after_atomic();
6332 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6335 * If we are running L2 and L1 has a new pending interrupt
6336 * which can be injected, this may cause a vmexit or it may
6337 * be injected into L2. Either way, this interrupt will be
6338 * processed via KVM_REQ_EVENT, not RVI, because we do not use
6339 * virtual interrupt delivery to inject L1 interrupts into L2.
6341 if (is_guest_mode(vcpu) && max_irr_updated)
6342 kvm_make_request(KVM_REQ_EVENT, vcpu);
6344 max_irr = kvm_lapic_find_highest_irr(vcpu);
6346 vmx_hwapic_irr_update(vcpu, max_irr);
6350 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6352 if (!kvm_vcpu_apicv_active(vcpu))
6355 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6356 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6357 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6358 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6361 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6363 struct vcpu_vmx *vmx = to_vmx(vcpu);
6365 pi_clear_on(&vmx->pi_desc);
6366 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6369 void vmx_do_interrupt_nmi_irqoff(unsigned long entry);
6371 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu,
6372 unsigned long entry)
6374 kvm_before_interrupt(vcpu);
6375 vmx_do_interrupt_nmi_irqoff(entry);
6376 kvm_after_interrupt(vcpu);
6379 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6381 const unsigned long nmi_entry = (unsigned long)asm_exc_nmi_noist;
6382 u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6384 /* if exit due to PF check for async PF */
6385 if (is_page_fault(intr_info))
6386 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6387 /* Handle machine checks before interrupts are enabled */
6388 else if (is_machine_check(intr_info))
6389 kvm_machine_check();
6390 /* We need to handle NMIs before interrupts are enabled */
6391 else if (is_nmi(intr_info))
6392 handle_interrupt_nmi_irqoff(&vmx->vcpu, nmi_entry);
6395 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6397 u32 intr_info = vmx_get_intr_info(vcpu);
6398 unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK;
6399 gate_desc *desc = (gate_desc *)host_idt_base + vector;
6401 if (KVM_BUG(!is_external_intr(intr_info), vcpu->kvm,
6402 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6405 handle_interrupt_nmi_irqoff(vcpu, gate_offset(desc));
6408 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6410 struct vcpu_vmx *vmx = to_vmx(vcpu);
6412 if (vmx->emulation_required)
6415 if (vmx->exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6416 handle_external_interrupt_irqoff(vcpu);
6417 else if (vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI)
6418 handle_exception_nmi_irqoff(vmx);
6422 * The kvm parameter can be NULL (module initialization, or invocation before
6423 * VM creation). Be sure to check the kvm parameter before using it.
6425 static bool vmx_has_emulated_msr(struct kvm *kvm, u32 index)
6428 case MSR_IA32_SMBASE:
6430 * We cannot do SMM unless we can run the guest in big
6433 return enable_unrestricted_guest || emulate_invalid_guest_state;
6434 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6436 case MSR_AMD64_VIRT_SPEC_CTRL:
6437 case MSR_AMD64_TSC_RATIO:
6438 /* This is AMD only. */
6445 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6450 bool idtv_info_valid;
6452 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6455 if (vmx->loaded_vmcs->nmi_known_unmasked)
6458 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6459 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6460 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6462 * SDM 3: 27.7.1.2 (September 2008)
6463 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6464 * a guest IRET fault.
6465 * SDM 3: 23.2.2 (September 2008)
6466 * Bit 12 is undefined in any of the following cases:
6467 * If the VM exit sets the valid bit in the IDT-vectoring
6468 * information field.
6469 * If the VM exit is due to a double fault.
6471 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6472 vector != DF_VECTOR && !idtv_info_valid)
6473 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6474 GUEST_INTR_STATE_NMI);
6476 vmx->loaded_vmcs->nmi_known_unmasked =
6477 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6478 & GUEST_INTR_STATE_NMI);
6479 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6480 vmx->loaded_vmcs->vnmi_blocked_time +=
6481 ktime_to_ns(ktime_sub(ktime_get(),
6482 vmx->loaded_vmcs->entry_time));
6485 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6486 u32 idt_vectoring_info,
6487 int instr_len_field,
6488 int error_code_field)
6492 bool idtv_info_valid;
6494 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6496 vcpu->arch.nmi_injected = false;
6497 kvm_clear_exception_queue(vcpu);
6498 kvm_clear_interrupt_queue(vcpu);
6500 if (!idtv_info_valid)
6503 kvm_make_request(KVM_REQ_EVENT, vcpu);
6505 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6506 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6509 case INTR_TYPE_NMI_INTR:
6510 vcpu->arch.nmi_injected = true;
6512 * SDM 3: 27.7.1.2 (September 2008)
6513 * Clear bit "block by NMI" before VM entry if a NMI
6516 vmx_set_nmi_mask(vcpu, false);
6518 case INTR_TYPE_SOFT_EXCEPTION:
6519 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6521 case INTR_TYPE_HARD_EXCEPTION:
6522 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6523 u32 err = vmcs_read32(error_code_field);
6524 kvm_requeue_exception_e(vcpu, vector, err);
6526 kvm_requeue_exception(vcpu, vector);
6528 case INTR_TYPE_SOFT_INTR:
6529 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6531 case INTR_TYPE_EXT_INTR:
6532 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6539 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6541 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6542 VM_EXIT_INSTRUCTION_LEN,
6543 IDT_VECTORING_ERROR_CODE);
6546 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6548 __vmx_complete_interrupts(vcpu,
6549 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6550 VM_ENTRY_INSTRUCTION_LEN,
6551 VM_ENTRY_EXCEPTION_ERROR_CODE);
6553 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6556 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6559 struct perf_guest_switch_msr *msrs;
6561 /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
6562 msrs = perf_guest_get_msrs(&nr_msrs);
6566 for (i = 0; i < nr_msrs; i++)
6567 if (msrs[i].host == msrs[i].guest)
6568 clear_atomic_switch_msr(vmx, msrs[i].msr);
6570 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6571 msrs[i].host, false);
6574 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6576 struct vcpu_vmx *vmx = to_vmx(vcpu);
6580 if (vmx->req_immediate_exit) {
6581 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6582 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6583 } else if (vmx->hv_deadline_tsc != -1) {
6585 if (vmx->hv_deadline_tsc > tscl)
6586 /* set_hv_timer ensures the delta fits in 32-bits */
6587 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6588 cpu_preemption_timer_multi);
6592 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6593 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6594 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6595 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6596 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6600 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6602 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6603 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6604 vmcs_writel(HOST_RSP, host_rsp);
6608 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6610 switch (to_vmx(vcpu)->exit_reason.basic) {
6611 case EXIT_REASON_MSR_WRITE:
6612 return handle_fastpath_set_msr_irqoff(vcpu);
6613 case EXIT_REASON_PREEMPTION_TIMER:
6614 return handle_fastpath_preemption_timer(vcpu);
6616 return EXIT_FASTPATH_NONE;
6620 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6621 struct vcpu_vmx *vmx)
6623 kvm_guest_enter_irqoff();
6625 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6626 if (static_branch_unlikely(&vmx_l1d_should_flush))
6627 vmx_l1d_flush(vcpu);
6628 else if (static_branch_unlikely(&mds_user_clear))
6629 mds_clear_cpu_buffers();
6631 if (vcpu->arch.cr2 != native_read_cr2())
6632 native_write_cr2(vcpu->arch.cr2);
6634 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6635 vmx->loaded_vmcs->launched);
6637 vcpu->arch.cr2 = native_read_cr2();
6639 kvm_guest_exit_irqoff();
6642 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6644 struct vcpu_vmx *vmx = to_vmx(vcpu);
6645 unsigned long cr3, cr4;
6647 /* Record the guest's net vcpu time for enforced NMI injections. */
6648 if (unlikely(!enable_vnmi &&
6649 vmx->loaded_vmcs->soft_vnmi_blocked))
6650 vmx->loaded_vmcs->entry_time = ktime_get();
6653 * Don't enter VMX if guest state is invalid, let the exit handler
6654 * start emulation until we arrive back to a valid state. Synthesize a
6655 * consistency check VM-Exit due to invalid guest state and bail.
6657 if (unlikely(vmx->emulation_required)) {
6659 /* We don't emulate invalid state of a nested guest */
6660 vmx->fail = is_guest_mode(vcpu);
6662 vmx->exit_reason.full = EXIT_REASON_INVALID_STATE;
6663 vmx->exit_reason.failed_vmentry = 1;
6664 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
6665 vmx->exit_qualification = ENTRY_FAIL_DEFAULT;
6666 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
6667 vmx->exit_intr_info = 0;
6668 return EXIT_FASTPATH_NONE;
6671 trace_kvm_entry(vcpu);
6673 if (vmx->ple_window_dirty) {
6674 vmx->ple_window_dirty = false;
6675 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6679 * We did this in prepare_switch_to_guest, because it needs to
6680 * be within srcu_read_lock.
6682 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6684 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6685 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6686 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6687 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6689 cr3 = __get_current_cr3_fast();
6690 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6691 vmcs_writel(HOST_CR3, cr3);
6692 vmx->loaded_vmcs->host_state.cr3 = cr3;
6695 cr4 = cr4_read_shadow();
6696 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6697 vmcs_writel(HOST_CR4, cr4);
6698 vmx->loaded_vmcs->host_state.cr4 = cr4;
6701 /* When KVM_DEBUGREG_WONT_EXIT, dr6 is accessible in guest. */
6702 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
6703 set_debugreg(vcpu->arch.dr6, 6);
6705 /* When single-stepping over STI and MOV SS, we must clear the
6706 * corresponding interruptibility bits in the guest state. Otherwise
6707 * vmentry fails as it then expects bit 14 (BS) in pending debug
6708 * exceptions being set, but that's not correct for the guest debugging
6710 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6711 vmx_set_interrupt_shadow(vcpu, 0);
6713 kvm_load_guest_xsave_state(vcpu);
6715 pt_guest_enter(vmx);
6717 atomic_switch_perf_msrs(vmx);
6718 if (intel_pmu_lbr_is_enabled(vcpu))
6719 vmx_passthrough_lbr_msrs(vcpu);
6721 if (enable_preemption_timer)
6722 vmx_update_hv_timer(vcpu);
6724 kvm_wait_lapic_expire(vcpu);
6727 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6728 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6729 * is no need to worry about the conditional branch over the wrmsr
6730 * being speculatively taken.
6732 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6734 /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6735 vmx_vcpu_enter_exit(vcpu, vmx);
6738 * We do not use IBRS in the kernel. If this vCPU has used the
6739 * SPEC_CTRL MSR it may have left it on; save the value and
6740 * turn it off. This is much more efficient than blindly adding
6741 * it to the atomic save/restore list. Especially as the former
6742 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6744 * For non-nested case:
6745 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6749 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6752 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6753 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6755 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6757 /* All fields are clean at this point */
6758 if (static_branch_unlikely(&enable_evmcs)) {
6759 current_evmcs->hv_clean_fields |=
6760 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6762 current_evmcs->hv_vp_id = kvm_hv_get_vpindex(vcpu);
6765 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6766 if (vmx->host_debugctlmsr)
6767 update_debugctlmsr(vmx->host_debugctlmsr);
6769 #ifndef CONFIG_X86_64
6771 * The sysexit path does not restore ds/es, so we must set them to
6772 * a reasonable value ourselves.
6774 * We can't defer this to vmx_prepare_switch_to_host() since that
6775 * function may be executed in interrupt context, which saves and
6776 * restore segments around it, nullifying its effect.
6778 loadsegment(ds, __USER_DS);
6779 loadsegment(es, __USER_DS);
6782 vmx_register_cache_reset(vcpu);
6786 kvm_load_host_xsave_state(vcpu);
6788 if (is_guest_mode(vcpu)) {
6790 * Track VMLAUNCH/VMRESUME that have made past guest state
6793 if (vmx->nested.nested_run_pending &&
6794 !vmx->exit_reason.failed_vmentry)
6795 ++vcpu->stat.nested_run;
6797 vmx->nested.nested_run_pending = 0;
6800 vmx->idt_vectoring_info = 0;
6802 if (unlikely(vmx->fail)) {
6803 vmx->exit_reason.full = 0xdead;
6804 return EXIT_FASTPATH_NONE;
6807 vmx->exit_reason.full = vmcs_read32(VM_EXIT_REASON);
6808 if (unlikely((u16)vmx->exit_reason.basic == EXIT_REASON_MCE_DURING_VMENTRY))
6809 kvm_machine_check();
6811 if (likely(!vmx->exit_reason.failed_vmentry))
6812 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6814 trace_kvm_exit(vcpu, KVM_ISA_VMX);
6816 if (unlikely(vmx->exit_reason.failed_vmentry))
6817 return EXIT_FASTPATH_NONE;
6819 vmx->loaded_vmcs->launched = 1;
6821 vmx_recover_nmi_blocking(vmx);
6822 vmx_complete_interrupts(vmx);
6824 if (is_guest_mode(vcpu))
6825 return EXIT_FASTPATH_NONE;
6827 return vmx_exit_handlers_fastpath(vcpu);
6830 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6832 struct vcpu_vmx *vmx = to_vmx(vcpu);
6835 vmx_destroy_pml_buffer(vmx);
6836 free_vpid(vmx->vpid);
6837 nested_vmx_free_vcpu(vcpu);
6838 free_loaded_vmcs(vmx->loaded_vmcs);
6841 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6843 struct vmx_uret_msr *tsx_ctrl;
6844 struct vcpu_vmx *vmx;
6847 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6852 vmx->vpid = allocate_vpid();
6855 * If PML is turned on, failure on enabling PML just results in failure
6856 * of creating the vcpu, therefore we can simplify PML logic (by
6857 * avoiding dealing with cases, such as enabling PML partially on vcpus
6858 * for the guest), etc.
6861 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6866 for (i = 0; i < kvm_nr_uret_msrs; ++i)
6867 vmx->guest_uret_msrs[i].mask = -1ull;
6868 if (boot_cpu_has(X86_FEATURE_RTM)) {
6870 * TSX_CTRL_CPUID_CLEAR is handled in the CPUID interception.
6871 * Keep the host value unchanged to avoid changing CPUID bits
6872 * under the host kernel's feet.
6874 tsx_ctrl = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
6876 tsx_ctrl->mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6879 err = alloc_loaded_vmcs(&vmx->vmcs01);
6883 /* The MSR bitmap starts with all ones */
6884 bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6885 bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6887 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
6888 #ifdef CONFIG_X86_64
6889 vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
6890 vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
6891 vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6893 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6894 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6895 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6896 if (kvm_cstate_in_guest(vcpu->kvm)) {
6897 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
6898 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6899 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6900 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6903 vmx->loaded_vmcs = &vmx->vmcs01;
6905 if (cpu_need_virtualize_apic_accesses(vcpu)) {
6906 err = alloc_apic_access_page(vcpu->kvm);
6911 if (enable_ept && !enable_unrestricted_guest) {
6912 err = init_rmode_identity_map(vcpu->kvm);
6920 free_loaded_vmcs(vmx->loaded_vmcs);
6922 vmx_destroy_pml_buffer(vmx);
6924 free_vpid(vmx->vpid);
6928 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6929 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6931 static int vmx_vm_init(struct kvm *kvm)
6934 kvm->arch.pause_in_guest = true;
6936 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6937 switch (l1tf_mitigation) {
6938 case L1TF_MITIGATION_OFF:
6939 case L1TF_MITIGATION_FLUSH_NOWARN:
6940 /* 'I explicitly don't care' is set */
6942 case L1TF_MITIGATION_FLUSH:
6943 case L1TF_MITIGATION_FLUSH_NOSMT:
6944 case L1TF_MITIGATION_FULL:
6946 * Warn upon starting the first VM in a potentially
6947 * insecure environment.
6949 if (sched_smt_active())
6950 pr_warn_once(L1TF_MSG_SMT);
6951 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6952 pr_warn_once(L1TF_MSG_L1D);
6954 case L1TF_MITIGATION_FULL_FORCE:
6955 /* Flush is enforced */
6962 static int __init vmx_check_processor_compat(void)
6964 struct vmcs_config vmcs_conf;
6965 struct vmx_capability vmx_cap;
6967 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6968 !this_cpu_has(X86_FEATURE_VMX)) {
6969 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6973 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6976 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6977 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6978 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6979 smp_processor_id());
6985 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6990 /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6991 * memory aliases with conflicting memory types and sometimes MCEs.
6992 * We have to be careful as to what are honored and when.
6994 * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to
6995 * UC. The effective memory type is UC or WC depending on guest PAT.
6996 * This was historically the source of MCEs and we want to be
6999 * When there is no need to deal with noncoherent DMA (e.g., no VT-d
7000 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The
7001 * EPT memory type is set to WB. The effective memory type is forced
7004 * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The
7005 * EPT memory type is used to emulate guest CD/MTRR.
7009 cache = MTRR_TYPE_UNCACHABLE;
7013 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
7014 ipat = VMX_EPT_IPAT_BIT;
7015 cache = MTRR_TYPE_WRBACK;
7019 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
7020 ipat = VMX_EPT_IPAT_BIT;
7021 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
7022 cache = MTRR_TYPE_WRBACK;
7024 cache = MTRR_TYPE_UNCACHABLE;
7028 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
7031 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
7034 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx, u32 new_ctl)
7037 * These bits in the secondary execution controls field
7038 * are dynamic, the others are mostly based on the hypervisor
7039 * architecture and the guest's CPUID. Do not touch the
7043 SECONDARY_EXEC_SHADOW_VMCS |
7044 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7045 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7046 SECONDARY_EXEC_DESC;
7048 u32 cur_ctl = secondary_exec_controls_get(vmx);
7050 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7054 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7055 * (indicating "allowed-1") if they are supported in the guest's CPUID.
7057 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7059 struct vcpu_vmx *vmx = to_vmx(vcpu);
7060 struct kvm_cpuid_entry2 *entry;
7062 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7063 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7065 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
7066 if (entry && (entry->_reg & (_cpuid_mask))) \
7067 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
7070 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7071 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME));
7072 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME));
7073 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC));
7074 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE));
7075 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE));
7076 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE));
7077 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE));
7078 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE));
7079 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR));
7080 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7081 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX));
7082 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX));
7083 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID));
7084 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE));
7086 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7087 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE));
7088 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP));
7089 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP));
7090 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU));
7091 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP));
7092 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57));
7094 #undef cr4_fixed1_update
7097 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7099 struct vcpu_vmx *vmx = to_vmx(vcpu);
7101 if (kvm_mpx_supported()) {
7102 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7105 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7106 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7108 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7109 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7114 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7116 struct vcpu_vmx *vmx = to_vmx(vcpu);
7117 struct kvm_cpuid_entry2 *best = NULL;
7120 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7121 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7124 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7125 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7126 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7127 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7130 /* Get the number of configurable Address Ranges for filtering */
7131 vmx->pt_desc.num_address_ranges = intel_pt_validate_cap(vmx->pt_desc.caps,
7132 PT_CAP_num_address_ranges);
7134 /* Initialize and clear the no dependency bits */
7135 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7136 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC |
7137 RTIT_CTL_BRANCH_EN);
7140 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7141 * will inject an #GP
7143 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7144 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7147 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7148 * PSBFreq can be set
7150 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7151 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7152 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7155 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn and MTCFreq can be set
7157 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7158 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7159 RTIT_CTL_MTC_RANGE);
7161 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7162 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7163 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7166 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7167 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7168 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7170 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7171 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7172 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7174 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabricEn can be set */
7175 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7176 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7178 /* unmask address range configure area */
7179 for (i = 0; i < vmx->pt_desc.num_address_ranges; i++)
7180 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7183 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7185 struct vcpu_vmx *vmx = to_vmx(vcpu);
7187 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7188 vcpu->arch.xsaves_enabled = false;
7190 vmx_setup_uret_msrs(vmx);
7192 if (cpu_has_secondary_exec_ctrls())
7193 vmcs_set_secondary_exec_control(vmx,
7194 vmx_secondary_exec_control(vmx));
7196 if (nested_vmx_allowed(vcpu))
7197 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7198 FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7199 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7201 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7202 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7203 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7205 if (nested_vmx_allowed(vcpu)) {
7206 nested_vmx_cr_fixed1_bits_update(vcpu);
7207 nested_vmx_entry_exit_ctls_update(vcpu);
7210 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7211 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7212 update_intel_pt_cfg(vcpu);
7214 if (boot_cpu_has(X86_FEATURE_RTM)) {
7215 struct vmx_uret_msr *msr;
7216 msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
7218 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7219 vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7223 set_cr4_guest_host_mask(vmx);
7225 vmx_write_encls_bitmap(vcpu, NULL);
7226 if (guest_cpuid_has(vcpu, X86_FEATURE_SGX))
7227 vmx->msr_ia32_feature_control_valid_bits |= FEAT_CTL_SGX_ENABLED;
7229 vmx->msr_ia32_feature_control_valid_bits &= ~FEAT_CTL_SGX_ENABLED;
7231 if (guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
7232 vmx->msr_ia32_feature_control_valid_bits |=
7233 FEAT_CTL_SGX_LC_ENABLED;
7235 vmx->msr_ia32_feature_control_valid_bits &=
7236 ~FEAT_CTL_SGX_LC_ENABLED;
7238 /* Refresh #PF interception to account for MAXPHYADDR changes. */
7239 vmx_update_exception_bitmap(vcpu);
7242 static __init void vmx_set_cpu_caps(void)
7248 kvm_cpu_cap_set(X86_FEATURE_VMX);
7251 if (kvm_mpx_supported())
7252 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7253 if (!cpu_has_vmx_invpcid())
7254 kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
7255 if (vmx_pt_mode_is_host_guest())
7256 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7259 kvm_cpu_cap_clear(X86_FEATURE_SGX);
7260 kvm_cpu_cap_clear(X86_FEATURE_SGX_LC);
7261 kvm_cpu_cap_clear(X86_FEATURE_SGX1);
7262 kvm_cpu_cap_clear(X86_FEATURE_SGX2);
7265 if (vmx_umip_emulated())
7266 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7270 if (!cpu_has_vmx_xsaves())
7271 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7273 /* CPUID 0x80000001 and 0x7 (RDPID) */
7274 if (!cpu_has_vmx_rdtscp()) {
7275 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7276 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
7279 if (cpu_has_vmx_waitpkg())
7280 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7283 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7285 to_vmx(vcpu)->req_immediate_exit = true;
7288 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7289 struct x86_instruction_info *info)
7291 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7292 unsigned short port;
7296 if (info->intercept == x86_intercept_in ||
7297 info->intercept == x86_intercept_ins) {
7298 port = info->src_val;
7299 size = info->dst_bytes;
7301 port = info->dst_val;
7302 size = info->src_bytes;
7306 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7307 * VM-exits depend on the 'unconditional IO exiting' VM-execution
7310 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7312 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7313 intercept = nested_cpu_has(vmcs12,
7314 CPU_BASED_UNCOND_IO_EXITING);
7316 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7318 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7319 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7322 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7323 struct x86_instruction_info *info,
7324 enum x86_intercept_stage stage,
7325 struct x86_exception *exception)
7327 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7329 switch (info->intercept) {
7331 * RDPID causes #UD if disabled through secondary execution controls.
7332 * Because it is marked as EmulateOnUD, we need to intercept it here.
7333 * Note, RDPID is hidden behind ENABLE_RDTSCP.
7335 case x86_intercept_rdpid:
7336 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) {
7337 exception->vector = UD_VECTOR;
7338 exception->error_code_valid = false;
7339 return X86EMUL_PROPAGATE_FAULT;
7343 case x86_intercept_in:
7344 case x86_intercept_ins:
7345 case x86_intercept_out:
7346 case x86_intercept_outs:
7347 return vmx_check_intercept_io(vcpu, info);
7349 case x86_intercept_lgdt:
7350 case x86_intercept_lidt:
7351 case x86_intercept_lldt:
7352 case x86_intercept_ltr:
7353 case x86_intercept_sgdt:
7354 case x86_intercept_sidt:
7355 case x86_intercept_sldt:
7356 case x86_intercept_str:
7357 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7358 return X86EMUL_CONTINUE;
7360 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7363 /* TODO: check more intercepts... */
7368 return X86EMUL_UNHANDLEABLE;
7371 #ifdef CONFIG_X86_64
7372 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7373 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7374 u64 divisor, u64 *result)
7376 u64 low = a << shift, high = a >> (64 - shift);
7378 /* To avoid the overflow on divq */
7379 if (high >= divisor)
7382 /* Low hold the result, high hold rem which is discarded */
7383 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7384 "rm" (divisor), "0" (low), "1" (high));
7390 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7393 struct vcpu_vmx *vmx;
7394 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7395 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7399 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7400 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7401 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7402 ktimer->timer_advance_ns);
7404 if (delta_tsc > lapic_timer_advance_cycles)
7405 delta_tsc -= lapic_timer_advance_cycles;
7409 /* Convert to host delta tsc if tsc scaling is enabled */
7410 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7411 delta_tsc && u64_shl_div_u64(delta_tsc,
7412 kvm_tsc_scaling_ratio_frac_bits,
7413 vcpu->arch.l1_tsc_scaling_ratio, &delta_tsc))
7417 * If the delta tsc can't fit in the 32 bit after the multi shift,
7418 * we can't use the preemption timer.
7419 * It's possible that it fits on later vmentries, but checking
7420 * on every vmentry is costly so we just use an hrtimer.
7422 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7425 vmx->hv_deadline_tsc = tscl + delta_tsc;
7426 *expired = !delta_tsc;
7430 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7432 to_vmx(vcpu)->hv_deadline_tsc = -1;
7436 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7438 if (!kvm_pause_in_guest(vcpu->kvm))
7439 shrink_ple_window(vcpu);
7442 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu)
7444 struct vcpu_vmx *vmx = to_vmx(vcpu);
7446 if (is_guest_mode(vcpu)) {
7447 vmx->nested.update_vmcs01_cpu_dirty_logging = true;
7452 * Note, cpu_dirty_logging_count can be changed concurrent with this
7453 * code, but in that case another update request will be made and so
7454 * the guest will never run with a stale PML value.
7456 if (vcpu->kvm->arch.cpu_dirty_logging_count)
7457 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7459 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7462 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7464 if (pi_pre_block(vcpu))
7467 if (kvm_lapic_hv_timer_in_use(vcpu))
7468 kvm_lapic_switch_to_sw_timer(vcpu);
7473 static void vmx_post_block(struct kvm_vcpu *vcpu)
7475 if (kvm_x86_ops.set_hv_timer)
7476 kvm_lapic_switch_to_hv_timer(vcpu);
7478 pi_post_block(vcpu);
7481 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7483 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7484 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7485 FEAT_CTL_LMCE_ENABLED;
7487 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7488 ~FEAT_CTL_LMCE_ENABLED;
7491 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7493 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7494 if (to_vmx(vcpu)->nested.nested_run_pending)
7496 return !is_smm(vcpu);
7499 static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7501 struct vcpu_vmx *vmx = to_vmx(vcpu);
7503 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7504 if (vmx->nested.smm.guest_mode)
7505 nested_vmx_vmexit(vcpu, -1, 0, 0);
7507 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7508 vmx->nested.vmxon = false;
7509 vmx_clear_hlt(vcpu);
7513 static int vmx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7515 struct vcpu_vmx *vmx = to_vmx(vcpu);
7518 if (vmx->nested.smm.vmxon) {
7519 vmx->nested.vmxon = true;
7520 vmx->nested.smm.vmxon = false;
7523 if (vmx->nested.smm.guest_mode) {
7524 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7528 vmx->nested.smm.guest_mode = false;
7533 static void vmx_enable_smi_window(struct kvm_vcpu *vcpu)
7535 /* RSM will cause a vmexit anyway. */
7538 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7540 return to_vmx(vcpu)->nested.vmxon && !is_guest_mode(vcpu);
7543 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7545 if (is_guest_mode(vcpu)) {
7546 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7548 if (hrtimer_try_to_cancel(timer) == 1)
7549 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7553 static void hardware_unsetup(void)
7555 kvm_set_posted_intr_wakeup_handler(NULL);
7558 nested_vmx_hardware_unsetup();
7563 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7565 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7566 BIT(APICV_INHIBIT_REASON_HYPERV);
7568 return supported & BIT(bit);
7571 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7572 .name = "kvm_intel",
7574 .hardware_unsetup = hardware_unsetup,
7576 .hardware_enable = hardware_enable,
7577 .hardware_disable = hardware_disable,
7578 .cpu_has_accelerated_tpr = report_flexpriority,
7579 .has_emulated_msr = vmx_has_emulated_msr,
7581 .vm_size = sizeof(struct kvm_vmx),
7582 .vm_init = vmx_vm_init,
7584 .vcpu_create = vmx_create_vcpu,
7585 .vcpu_free = vmx_free_vcpu,
7586 .vcpu_reset = vmx_vcpu_reset,
7588 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7589 .vcpu_load = vmx_vcpu_load,
7590 .vcpu_put = vmx_vcpu_put,
7592 .update_exception_bitmap = vmx_update_exception_bitmap,
7593 .get_msr_feature = vmx_get_msr_feature,
7594 .get_msr = vmx_get_msr,
7595 .set_msr = vmx_set_msr,
7596 .get_segment_base = vmx_get_segment_base,
7597 .get_segment = vmx_get_segment,
7598 .set_segment = vmx_set_segment,
7599 .get_cpl = vmx_get_cpl,
7600 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7601 .set_cr0 = vmx_set_cr0,
7602 .is_valid_cr4 = vmx_is_valid_cr4,
7603 .set_cr4 = vmx_set_cr4,
7604 .set_efer = vmx_set_efer,
7605 .get_idt = vmx_get_idt,
7606 .set_idt = vmx_set_idt,
7607 .get_gdt = vmx_get_gdt,
7608 .set_gdt = vmx_set_gdt,
7609 .set_dr7 = vmx_set_dr7,
7610 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7611 .cache_reg = vmx_cache_reg,
7612 .get_rflags = vmx_get_rflags,
7613 .set_rflags = vmx_set_rflags,
7615 .tlb_flush_all = vmx_flush_tlb_all,
7616 .tlb_flush_current = vmx_flush_tlb_current,
7617 .tlb_flush_gva = vmx_flush_tlb_gva,
7618 .tlb_flush_guest = vmx_flush_tlb_guest,
7620 .run = vmx_vcpu_run,
7621 .handle_exit = vmx_handle_exit,
7622 .skip_emulated_instruction = vmx_skip_emulated_instruction,
7623 .update_emulated_instruction = vmx_update_emulated_instruction,
7624 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7625 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7626 .patch_hypercall = vmx_patch_hypercall,
7627 .set_irq = vmx_inject_irq,
7628 .set_nmi = vmx_inject_nmi,
7629 .queue_exception = vmx_queue_exception,
7630 .cancel_injection = vmx_cancel_injection,
7631 .interrupt_allowed = vmx_interrupt_allowed,
7632 .nmi_allowed = vmx_nmi_allowed,
7633 .get_nmi_mask = vmx_get_nmi_mask,
7634 .set_nmi_mask = vmx_set_nmi_mask,
7635 .enable_nmi_window = vmx_enable_nmi_window,
7636 .enable_irq_window = vmx_enable_irq_window,
7637 .update_cr8_intercept = vmx_update_cr8_intercept,
7638 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7639 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7640 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7641 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7642 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7643 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7644 .hwapic_irr_update = vmx_hwapic_irr_update,
7645 .hwapic_isr_update = vmx_hwapic_isr_update,
7646 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7647 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7648 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7649 .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
7651 .set_tss_addr = vmx_set_tss_addr,
7652 .set_identity_map_addr = vmx_set_identity_map_addr,
7653 .get_mt_mask = vmx_get_mt_mask,
7655 .get_exit_info = vmx_get_exit_info,
7657 .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7659 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7661 .get_l2_tsc_offset = vmx_get_l2_tsc_offset,
7662 .get_l2_tsc_multiplier = vmx_get_l2_tsc_multiplier,
7663 .write_tsc_offset = vmx_write_tsc_offset,
7664 .write_tsc_multiplier = vmx_write_tsc_multiplier,
7666 .load_mmu_pgd = vmx_load_mmu_pgd,
7668 .check_intercept = vmx_check_intercept,
7669 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7671 .request_immediate_exit = vmx_request_immediate_exit,
7673 .sched_in = vmx_sched_in,
7675 .cpu_dirty_log_size = PML_ENTITY_NUM,
7676 .update_cpu_dirty_logging = vmx_update_cpu_dirty_logging,
7678 .pre_block = vmx_pre_block,
7679 .post_block = vmx_post_block,
7681 .pmu_ops = &intel_pmu_ops,
7682 .nested_ops = &vmx_nested_ops,
7684 .update_pi_irte = pi_update_irte,
7685 .start_assignment = vmx_pi_start_assignment,
7687 #ifdef CONFIG_X86_64
7688 .set_hv_timer = vmx_set_hv_timer,
7689 .cancel_hv_timer = vmx_cancel_hv_timer,
7692 .setup_mce = vmx_setup_mce,
7694 .smi_allowed = vmx_smi_allowed,
7695 .enter_smm = vmx_enter_smm,
7696 .leave_smm = vmx_leave_smm,
7697 .enable_smi_window = vmx_enable_smi_window,
7699 .can_emulate_instruction = vmx_can_emulate_instruction,
7700 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7701 .migrate_timers = vmx_migrate_timers,
7703 .msr_filter_changed = vmx_msr_filter_changed,
7704 .complete_emulated_msr = kvm_complete_insn_gp,
7706 .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector,
7709 static __init void vmx_setup_user_return_msrs(void)
7713 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
7714 * will emulate SYSCALL in legacy mode if the vendor string in guest
7715 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
7716 * support this emulation, MSR_STAR is included in the list for i386,
7717 * but is never loaded into hardware. MSR_CSTAR is also never loaded
7718 * into hardware and is here purely for emulation purposes.
7720 const u32 vmx_uret_msrs_list[] = {
7721 #ifdef CONFIG_X86_64
7722 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
7724 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
7729 BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
7731 for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
7732 kvm_add_user_return_msr(vmx_uret_msrs_list[i]);
7735 static __init int hardware_setup(void)
7737 unsigned long host_bndcfgs;
7739 int r, ept_lpage_level;
7742 host_idt_base = dt.address;
7744 vmx_setup_user_return_msrs();
7746 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7749 if (boot_cpu_has(X86_FEATURE_NX))
7750 kvm_enable_efer_bits(EFER_NX);
7752 if (boot_cpu_has(X86_FEATURE_MPX)) {
7753 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7754 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7757 if (!cpu_has_vmx_mpx())
7758 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7759 XFEATURE_MASK_BNDCSR);
7761 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7762 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7765 if (!cpu_has_vmx_ept() ||
7766 !cpu_has_vmx_ept_4levels() ||
7767 !cpu_has_vmx_ept_mt_wb() ||
7768 !cpu_has_vmx_invept_global())
7771 /* NX support is required for shadow paging. */
7772 if (!enable_ept && !boot_cpu_has(X86_FEATURE_NX)) {
7773 pr_err_ratelimited("kvm: NX (Execute Disable) not supported\n");
7777 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7778 enable_ept_ad_bits = 0;
7780 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7781 enable_unrestricted_guest = 0;
7783 if (!cpu_has_vmx_flexpriority())
7784 flexpriority_enabled = 0;
7786 if (!cpu_has_virtual_nmis())
7790 * set_apic_access_page_addr() is used to reload apic access
7791 * page upon invalidation. No need to do anything if not
7792 * using the APIC_ACCESS_ADDR VMCS field.
7794 if (!flexpriority_enabled)
7795 vmx_x86_ops.set_apic_access_page_addr = NULL;
7797 if (!cpu_has_vmx_tpr_shadow())
7798 vmx_x86_ops.update_cr8_intercept = NULL;
7800 #if IS_ENABLED(CONFIG_HYPERV)
7801 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7803 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7804 vmx_x86_ops.tlb_remote_flush_with_range =
7805 hv_remote_flush_tlb_with_range;
7809 if (!cpu_has_vmx_ple()) {
7812 ple_window_grow = 0;
7814 ple_window_shrink = 0;
7817 if (!cpu_has_vmx_apicv()) {
7819 vmx_x86_ops.sync_pir_to_irr = NULL;
7822 if (cpu_has_vmx_tsc_scaling()) {
7823 kvm_has_tsc_control = true;
7824 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7825 kvm_tsc_scaling_ratio_frac_bits = 48;
7828 kvm_has_bus_lock_exit = cpu_has_vmx_bus_lock_detection();
7830 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7833 kvm_mmu_set_ept_masks(enable_ept_ad_bits,
7834 cpu_has_vmx_ept_execute_only());
7837 ept_lpage_level = 0;
7838 else if (cpu_has_vmx_ept_1g_page())
7839 ept_lpage_level = PG_LEVEL_1G;
7840 else if (cpu_has_vmx_ept_2m_page())
7841 ept_lpage_level = PG_LEVEL_2M;
7843 ept_lpage_level = PG_LEVEL_4K;
7844 kvm_configure_mmu(enable_ept, 0, vmx_get_max_tdp_level(),
7848 * Only enable PML when hardware supports PML feature, and both EPT
7849 * and EPT A/D bit features are enabled -- PML depends on them to work.
7851 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7855 vmx_x86_ops.cpu_dirty_log_size = 0;
7857 if (!cpu_has_vmx_preemption_timer())
7858 enable_preemption_timer = false;
7860 if (enable_preemption_timer) {
7861 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7864 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7865 cpu_preemption_timer_multi =
7866 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7869 use_timer_freq = (u64)tsc_khz * 1000;
7870 use_timer_freq >>= cpu_preemption_timer_multi;
7873 * KVM "disables" the preemption timer by setting it to its max
7874 * value. Don't use the timer if it might cause spurious exits
7875 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7877 if (use_timer_freq > 0xffffffffu / 10)
7878 enable_preemption_timer = false;
7881 if (!enable_preemption_timer) {
7882 vmx_x86_ops.set_hv_timer = NULL;
7883 vmx_x86_ops.cancel_hv_timer = NULL;
7884 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
7887 kvm_mce_cap_supported |= MCG_LMCE_P;
7889 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7891 if (!enable_ept || !cpu_has_vmx_intel_pt())
7892 pt_mode = PT_MODE_SYSTEM;
7894 setup_default_sgx_lepubkeyhash();
7897 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7898 vmx_capability.ept);
7900 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7907 r = alloc_kvm_area();
7909 nested_vmx_hardware_unsetup();
7911 kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler);
7916 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
7917 .cpu_has_kvm_support = cpu_has_kvm_support,
7918 .disabled_by_bios = vmx_disabled_by_bios,
7919 .check_processor_compatibility = vmx_check_processor_compat,
7920 .hardware_setup = hardware_setup,
7922 .runtime_ops = &vmx_x86_ops,
7925 static void vmx_cleanup_l1d_flush(void)
7927 if (vmx_l1d_flush_pages) {
7928 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7929 vmx_l1d_flush_pages = NULL;
7931 /* Restore state so sysfs ignores VMX */
7932 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7935 static void vmx_exit(void)
7937 #ifdef CONFIG_KEXEC_CORE
7938 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7944 #if IS_ENABLED(CONFIG_HYPERV)
7945 if (static_branch_unlikely(&enable_evmcs)) {
7947 struct hv_vp_assist_page *vp_ap;
7949 * Reset everything to support using non-enlightened VMCS
7950 * access later (e.g. when we reload the module with
7951 * enlightened_vmcs=0)
7953 for_each_online_cpu(cpu) {
7954 vp_ap = hv_get_vp_assist_page(cpu);
7959 vp_ap->nested_control.features.directhypercall = 0;
7960 vp_ap->current_nested_vmcs = 0;
7961 vp_ap->enlighten_vmentry = 0;
7964 static_branch_disable(&enable_evmcs);
7967 vmx_cleanup_l1d_flush();
7969 allow_smaller_maxphyaddr = false;
7971 module_exit(vmx_exit);
7973 static int __init vmx_init(void)
7977 #if IS_ENABLED(CONFIG_HYPERV)
7979 * Enlightened VMCS usage should be recommended and the host needs
7980 * to support eVMCS v1 or above. We can also disable eVMCS support
7981 * with module parameter.
7983 if (enlightened_vmcs &&
7984 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7985 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7986 KVM_EVMCS_VERSION) {
7989 /* Check that we have assist pages on all online CPUs */
7990 for_each_online_cpu(cpu) {
7991 if (!hv_get_vp_assist_page(cpu)) {
7992 enlightened_vmcs = false;
7997 if (enlightened_vmcs) {
7998 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7999 static_branch_enable(&enable_evmcs);
8002 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8003 vmx_x86_ops.enable_direct_tlbflush
8004 = hv_enable_direct_tlbflush;
8007 enlightened_vmcs = false;
8011 r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
8012 __alignof__(struct vcpu_vmx), THIS_MODULE);
8017 * Must be called after kvm_init() so enable_ept is properly set
8018 * up. Hand the parameter mitigation value in which was stored in
8019 * the pre module init parser. If no parameter was given, it will
8020 * contain 'auto' which will be turned into the default 'cond'
8023 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8029 for_each_possible_cpu(cpu) {
8030 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8035 #ifdef CONFIG_KEXEC_CORE
8036 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8037 crash_vmclear_local_loaded_vmcss);
8039 vmx_check_vmcs12_offsets();
8042 * Shadow paging doesn't have a (further) performance penalty
8043 * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it
8047 allow_smaller_maxphyaddr = true;
8051 module_init(vmx_init);