1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/frame.h>
17 #include <linux/highmem.h>
18 #include <linux/hrtimer.h>
19 #include <linux/kernel.h>
20 #include <linux/kvm_host.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/mod_devicetable.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
34 #include <asm/debugreg.h>
36 #include <asm/fpu/internal.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/kexec.h>
40 #include <asm/perf_event.h>
42 #include <asm/mmu_context.h>
43 #include <asm/mshyperv.h>
44 #include <asm/spec-ctrl.h>
45 #include <asm/virtext.h>
48 #include "capabilities.h"
52 #include "kvm_cache_regs.h"
64 MODULE_AUTHOR("Qumranet");
65 MODULE_LICENSE("GPL");
67 static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
73 bool __read_mostly enable_vpid = 1;
74 module_param_named(vpid, enable_vpid, bool, 0444);
76 static bool __read_mostly enable_vnmi = 1;
77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
79 bool __read_mostly flexpriority_enabled = 1;
80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
82 bool __read_mostly enable_ept = 1;
83 module_param_named(ept, enable_ept, bool, S_IRUGO);
85 bool __read_mostly enable_unrestricted_guest = 1;
86 module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
89 bool __read_mostly enable_ept_ad_bits = 1;
90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
92 static bool __read_mostly emulate_invalid_guest_state = true;
93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
95 static bool __read_mostly fasteoi = 1;
96 module_param(fasteoi, bool, S_IRUGO);
98 bool __read_mostly enable_apicv = 1;
99 module_param(enable_apicv, bool, S_IRUGO);
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
106 static bool __read_mostly nested = 1;
107 module_param(nested, bool, S_IRUGO);
109 bool __read_mostly enable_pml = 1;
110 module_param_named(pml, enable_pml, bool, S_IRUGO);
112 static bool __read_mostly dump_invalid_vmcs = 0;
113 module_param(dump_invalid_vmcs, bool, 0644);
115 #define MSR_BITMAP_MODE_X2APIC 1
116 #define MSR_BITMAP_MODE_X2APIC_APICV 2
118 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
120 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
121 static int __read_mostly cpu_preemption_timer_multi;
122 static bool __read_mostly enable_preemption_timer = 1;
124 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
127 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
128 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
129 #define KVM_VM_CR0_ALWAYS_ON \
130 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
131 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
132 #define KVM_CR4_GUEST_OWNED_BITS \
133 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
134 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
136 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
137 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
138 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
140 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
142 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
143 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
144 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
145 RTIT_STATUS_BYTECNT))
147 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
148 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
151 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
152 * ple_gap: upper bound on the amount of time between two successive
153 * executions of PAUSE in a loop. Also indicate if ple enabled.
154 * According to test, this time is usually smaller than 128 cycles.
155 * ple_window: upper bound on the amount of time a guest is allowed to execute
156 * in a PAUSE loop. Tests indicate that most spinlocks are held for
157 * less than 2^12 cycles
158 * Time is measured based on a counter that runs at the same rate as the TSC,
159 * refer SDM volume 3b section 21.6.13 & 22.1.3.
161 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
162 module_param(ple_gap, uint, 0444);
164 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
165 module_param(ple_window, uint, 0444);
167 /* Default doubles per-vcpu window every exit. */
168 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
169 module_param(ple_window_grow, uint, 0444);
171 /* Default resets per-vcpu window every exit to ple_window. */
172 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
173 module_param(ple_window_shrink, uint, 0444);
175 /* Default is to compute the maximum so we can never overflow. */
176 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
177 module_param(ple_window_max, uint, 0444);
179 /* Default is SYSTEM mode, 1 for host-guest mode */
180 int __read_mostly pt_mode = PT_MODE_SYSTEM;
181 module_param(pt_mode, int, S_IRUGO);
183 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
184 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
185 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
187 /* Storage for pre module init parameter parsing */
188 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
190 static const struct {
193 } vmentry_l1d_param[] = {
194 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
195 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
196 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
197 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
198 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
199 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
202 #define L1D_CACHE_ORDER 4
203 static void *vmx_l1d_flush_pages;
205 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
210 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
211 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
216 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
220 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
223 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
224 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
225 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
230 /* If set to auto use the default l1tf mitigation method */
231 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
232 switch (l1tf_mitigation) {
233 case L1TF_MITIGATION_OFF:
234 l1tf = VMENTER_L1D_FLUSH_NEVER;
236 case L1TF_MITIGATION_FLUSH_NOWARN:
237 case L1TF_MITIGATION_FLUSH:
238 case L1TF_MITIGATION_FLUSH_NOSMT:
239 l1tf = VMENTER_L1D_FLUSH_COND;
241 case L1TF_MITIGATION_FULL:
242 case L1TF_MITIGATION_FULL_FORCE:
243 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
246 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
247 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
250 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
251 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
253 * This allocation for vmx_l1d_flush_pages is not tied to a VM
254 * lifetime and so should not be charged to a memcg.
256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
259 vmx_l1d_flush_pages = page_address(page);
262 * Initialize each page with a different pattern in
263 * order to protect against KSM in the nested
264 * virtualization case.
266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
272 l1tf_vmx_mitigation = l1tf;
274 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
275 static_branch_enable(&vmx_l1d_should_flush);
277 static_branch_disable(&vmx_l1d_should_flush);
279 if (l1tf == VMENTER_L1D_FLUSH_COND)
280 static_branch_enable(&vmx_l1d_flush_cond);
282 static_branch_disable(&vmx_l1d_flush_cond);
286 static int vmentry_l1d_flush_parse(const char *s)
291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
292 if (vmentry_l1d_param[i].for_parse &&
293 sysfs_streq(s, vmentry_l1d_param[i].option))
300 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
304 l1tf = vmentry_l1d_flush_parse(s);
308 if (!boot_cpu_has(X86_BUG_L1TF))
312 * Has vmx_init() run already? If not then this is the pre init
313 * parameter parsing. In that case just store the value and let
314 * vmx_init() do the proper setup after enable_ept has been
317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
318 vmentry_l1d_flush_param = l1tf;
322 mutex_lock(&vmx_l1d_flush_mutex);
323 ret = vmx_setup_l1d_flush(l1tf);
324 mutex_unlock(&vmx_l1d_flush_mutex);
328 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
331 return sprintf(s, "???\n");
333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
336 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
337 .set = vmentry_l1d_flush_set,
338 .get = vmentry_l1d_flush_get,
340 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
342 static bool guest_state_valid(struct kvm_vcpu *vcpu);
343 static u32 vmx_segment_access_rights(struct kvm_segment *var);
344 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
347 void vmx_vmexit(void);
349 #define vmx_insn_failed(fmt...) \
352 pr_warn_ratelimited(fmt); \
355 asmlinkage void vmread_error(unsigned long field, bool fault)
358 kvm_spurious_fault();
360 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
363 noinline void vmwrite_error(unsigned long field, unsigned long value)
365 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
366 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
369 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
371 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
374 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
376 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
379 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
381 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
385 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
387 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
391 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
392 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
394 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
395 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
397 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
400 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
401 * can find which vCPU should be waken up.
403 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
404 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
406 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
407 static DEFINE_SPINLOCK(vmx_vpid_lock);
409 struct vmcs_config vmcs_config;
410 struct vmx_capability vmx_capability;
412 #define VMX_SEGMENT_FIELD(seg) \
413 [VCPU_SREG_##seg] = { \
414 .selector = GUEST_##seg##_SELECTOR, \
415 .base = GUEST_##seg##_BASE, \
416 .limit = GUEST_##seg##_LIMIT, \
417 .ar_bytes = GUEST_##seg##_AR_BYTES, \
420 static const struct kvm_vmx_segment_field {
425 } kvm_vmx_segment_fields[] = {
426 VMX_SEGMENT_FIELD(CS),
427 VMX_SEGMENT_FIELD(DS),
428 VMX_SEGMENT_FIELD(ES),
429 VMX_SEGMENT_FIELD(FS),
430 VMX_SEGMENT_FIELD(GS),
431 VMX_SEGMENT_FIELD(SS),
432 VMX_SEGMENT_FIELD(TR),
433 VMX_SEGMENT_FIELD(LDTR),
437 static unsigned long host_idt_base;
440 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
441 * will emulate SYSCALL in legacy mode if the vendor string in guest
442 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
443 * support this emulation, IA32_STAR must always be included in
444 * vmx_msr_index[], even in i386 builds.
446 const u32 vmx_msr_index[] = {
448 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
450 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
454 #if IS_ENABLED(CONFIG_HYPERV)
455 static bool __read_mostly enlightened_vmcs = true;
456 module_param(enlightened_vmcs, bool, 0444);
458 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
459 static void check_ept_pointer_match(struct kvm *kvm)
461 struct kvm_vcpu *vcpu;
462 u64 tmp_eptp = INVALID_PAGE;
465 kvm_for_each_vcpu(i, vcpu, kvm) {
466 if (!VALID_PAGE(tmp_eptp)) {
467 tmp_eptp = to_vmx(vcpu)->ept_pointer;
468 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
469 to_kvm_vmx(kvm)->ept_pointers_match
470 = EPT_POINTERS_MISMATCH;
475 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
478 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
481 struct kvm_tlb_range *range = data;
483 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
487 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
488 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
490 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
493 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
494 * of the base of EPT PML4 table, strip off EPT configuration
498 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
499 kvm_fill_hv_flush_list_func, (void *)range);
501 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
504 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
505 struct kvm_tlb_range *range)
507 struct kvm_vcpu *vcpu;
510 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
512 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
513 check_ept_pointer_match(kvm);
515 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
516 kvm_for_each_vcpu(i, vcpu, kvm) {
517 /* If ept_pointer is invalid pointer, bypass flush request. */
518 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
519 ret |= __hv_remote_flush_tlb_with_range(
523 ret = __hv_remote_flush_tlb_with_range(kvm,
524 kvm_get_vcpu(kvm, 0), range);
527 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
530 static int hv_remote_flush_tlb(struct kvm *kvm)
532 return hv_remote_flush_tlb_with_range(kvm, NULL);
535 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
537 struct hv_enlightened_vmcs *evmcs;
538 struct hv_partition_assist_pg **p_hv_pa_pg =
539 &vcpu->kvm->arch.hyperv.hv_pa_pg;
541 * Synthetic VM-Exit is not enabled in current code and so All
542 * evmcs in singe VM shares same assist page.
545 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
550 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
552 evmcs->partition_assist_page =
554 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
555 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
560 #endif /* IS_ENABLED(CONFIG_HYPERV) */
563 * Comment's format: document - errata name - stepping - processor name.
565 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
567 static u32 vmx_preemption_cpu_tfms[] = {
568 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
570 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
571 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
572 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
574 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
576 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
577 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
579 * 320767.pdf - AAP86 - B1 -
580 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
583 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
585 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
587 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
589 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
590 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
591 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
593 /* Xeon E3-1220 V2 */
597 static inline bool cpu_has_broken_vmx_preemption_timer(void)
599 u32 eax = cpuid_eax(0x00000001), i;
601 /* Clear the reserved bits */
602 eax &= ~(0x3U << 14 | 0xfU << 28);
603 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
604 if (eax == vmx_preemption_cpu_tfms[i])
610 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
612 return flexpriority_enabled && lapic_in_kernel(vcpu);
615 static inline bool report_flexpriority(void)
617 return flexpriority_enabled;
620 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
624 for (i = 0; i < vmx->nmsrs; ++i)
625 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
630 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
634 i = __find_msr_index(vmx, msr);
636 return &vmx->guest_msrs[i];
640 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
644 u64 old_msr_data = msr->data;
646 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
648 ret = kvm_set_shared_msr(msr->index, msr->data,
652 msr->data = old_msr_data;
657 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
659 vmcs_clear(loaded_vmcs->vmcs);
660 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
661 vmcs_clear(loaded_vmcs->shadow_vmcs);
662 loaded_vmcs->cpu = -1;
663 loaded_vmcs->launched = 0;
666 #ifdef CONFIG_KEXEC_CORE
668 * This bitmap is used to indicate whether the vmclear
669 * operation is enabled on all cpus. All disabled by
672 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
674 static inline void crash_enable_local_vmclear(int cpu)
676 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
679 static inline void crash_disable_local_vmclear(int cpu)
681 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
684 static inline int crash_local_vmclear_enabled(int cpu)
686 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
689 static void crash_vmclear_local_loaded_vmcss(void)
691 int cpu = raw_smp_processor_id();
692 struct loaded_vmcs *v;
694 if (!crash_local_vmclear_enabled(cpu))
697 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
698 loaded_vmcss_on_cpu_link)
702 static inline void crash_enable_local_vmclear(int cpu) { }
703 static inline void crash_disable_local_vmclear(int cpu) { }
704 #endif /* CONFIG_KEXEC_CORE */
706 static void __loaded_vmcs_clear(void *arg)
708 struct loaded_vmcs *loaded_vmcs = arg;
709 int cpu = raw_smp_processor_id();
711 if (loaded_vmcs->cpu != cpu)
712 return; /* vcpu migration can race with cpu offline */
713 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
714 per_cpu(current_vmcs, cpu) = NULL;
715 crash_disable_local_vmclear(cpu);
716 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
719 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
720 * is before setting loaded_vmcs->vcpu to -1 which is done in
721 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
722 * then adds the vmcs into percpu list before it is deleted.
726 loaded_vmcs_init(loaded_vmcs);
727 crash_enable_local_vmclear(cpu);
730 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
732 int cpu = loaded_vmcs->cpu;
735 smp_call_function_single(cpu,
736 __loaded_vmcs_clear, loaded_vmcs, 1);
739 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
743 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
745 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
746 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
747 vmx->segment_cache.bitmask = 0;
749 ret = vmx->segment_cache.bitmask & mask;
750 vmx->segment_cache.bitmask |= mask;
754 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
756 u16 *p = &vmx->segment_cache.seg[seg].selector;
758 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
759 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
763 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
765 ulong *p = &vmx->segment_cache.seg[seg].base;
767 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
768 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
772 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
774 u32 *p = &vmx->segment_cache.seg[seg].limit;
776 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
777 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
781 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
783 u32 *p = &vmx->segment_cache.seg[seg].ar;
785 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
786 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
790 void update_exception_bitmap(struct kvm_vcpu *vcpu)
794 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
795 (1u << DB_VECTOR) | (1u << AC_VECTOR);
797 * Guest access to VMware backdoor ports could legitimately
798 * trigger #GP because of TSS I/O permission bitmap.
799 * We intercept those #GP and allow access to them anyway
802 if (enable_vmware_backdoor)
803 eb |= (1u << GP_VECTOR);
804 if ((vcpu->guest_debug &
805 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
806 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
807 eb |= 1u << BP_VECTOR;
808 if (to_vmx(vcpu)->rmode.vm86_active)
811 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
813 /* When we are running a nested L2 guest and L1 specified for it a
814 * certain exception bitmap, we must trap the same exceptions and pass
815 * them to L1. When running L2, we will only handle the exceptions
816 * specified above if L1 did not want them.
818 if (is_guest_mode(vcpu))
819 eb |= get_vmcs12(vcpu)->exception_bitmap;
821 vmcs_write32(EXCEPTION_BITMAP, eb);
825 * Check if MSR is intercepted for currently loaded MSR bitmap.
827 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
829 unsigned long *msr_bitmap;
830 int f = sizeof(unsigned long);
832 if (!cpu_has_vmx_msr_bitmap())
835 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
838 return !!test_bit(msr, msr_bitmap + 0x800 / f);
839 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
841 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
847 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
848 unsigned long entry, unsigned long exit)
850 vm_entry_controls_clearbit(vmx, entry);
851 vm_exit_controls_clearbit(vmx, exit);
854 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
858 for (i = 0; i < m->nr; ++i) {
859 if (m->val[i].index == msr)
865 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
868 struct msr_autoload *m = &vmx->msr_autoload;
872 if (cpu_has_load_ia32_efer()) {
873 clear_atomic_switch_msr_special(vmx,
874 VM_ENTRY_LOAD_IA32_EFER,
875 VM_EXIT_LOAD_IA32_EFER);
879 case MSR_CORE_PERF_GLOBAL_CTRL:
880 if (cpu_has_load_perf_global_ctrl()) {
881 clear_atomic_switch_msr_special(vmx,
882 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
883 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
888 i = vmx_find_msr_index(&m->guest, msr);
892 m->guest.val[i] = m->guest.val[m->guest.nr];
893 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
896 i = vmx_find_msr_index(&m->host, msr);
901 m->host.val[i] = m->host.val[m->host.nr];
902 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
905 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
906 unsigned long entry, unsigned long exit,
907 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
908 u64 guest_val, u64 host_val)
910 vmcs_write64(guest_val_vmcs, guest_val);
911 if (host_val_vmcs != HOST_IA32_EFER)
912 vmcs_write64(host_val_vmcs, host_val);
913 vm_entry_controls_setbit(vmx, entry);
914 vm_exit_controls_setbit(vmx, exit);
917 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
918 u64 guest_val, u64 host_val, bool entry_only)
921 struct msr_autoload *m = &vmx->msr_autoload;
925 if (cpu_has_load_ia32_efer()) {
926 add_atomic_switch_msr_special(vmx,
927 VM_ENTRY_LOAD_IA32_EFER,
928 VM_EXIT_LOAD_IA32_EFER,
931 guest_val, host_val);
935 case MSR_CORE_PERF_GLOBAL_CTRL:
936 if (cpu_has_load_perf_global_ctrl()) {
937 add_atomic_switch_msr_special(vmx,
938 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
939 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
940 GUEST_IA32_PERF_GLOBAL_CTRL,
941 HOST_IA32_PERF_GLOBAL_CTRL,
942 guest_val, host_val);
946 case MSR_IA32_PEBS_ENABLE:
947 /* PEBS needs a quiescent period after being disabled (to write
948 * a record). Disabling PEBS through VMX MSR swapping doesn't
949 * provide that period, so a CPU could write host's record into
952 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
955 i = vmx_find_msr_index(&m->guest, msr);
957 j = vmx_find_msr_index(&m->host, msr);
959 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
960 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) {
961 printk_once(KERN_WARNING "Not enough msr switch entries. "
962 "Can't add msr %x\n", msr);
967 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
969 m->guest.val[i].index = msr;
970 m->guest.val[i].value = guest_val;
977 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
979 m->host.val[j].index = msr;
980 m->host.val[j].value = host_val;
983 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
985 u64 guest_efer = vmx->vcpu.arch.efer;
988 /* Shadow paging assumes NX to be available. */
990 guest_efer |= EFER_NX;
993 * LMA and LME handled by hardware; SCE meaningless outside long mode.
995 ignore_bits |= EFER_SCE;
997 ignore_bits |= EFER_LMA | EFER_LME;
998 /* SCE is meaningful only in long mode on Intel */
999 if (guest_efer & EFER_LMA)
1000 ignore_bits &= ~(u64)EFER_SCE;
1004 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1005 * On CPUs that support "load IA32_EFER", always switch EFER
1006 * atomically, since it's faster than switching it manually.
1008 if (cpu_has_load_ia32_efer() ||
1009 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1010 if (!(guest_efer & EFER_LMA))
1011 guest_efer &= ~EFER_LME;
1012 if (guest_efer != host_efer)
1013 add_atomic_switch_msr(vmx, MSR_EFER,
1014 guest_efer, host_efer, false);
1016 clear_atomic_switch_msr(vmx, MSR_EFER);
1019 clear_atomic_switch_msr(vmx, MSR_EFER);
1021 guest_efer &= ~ignore_bits;
1022 guest_efer |= host_efer & ignore_bits;
1024 vmx->guest_msrs[efer_offset].data = guest_efer;
1025 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1031 #ifdef CONFIG_X86_32
1033 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1034 * VMCS rather than the segment table. KVM uses this helper to figure
1035 * out the current bases to poke them into the VMCS before entry.
1037 static unsigned long segment_base(u16 selector)
1039 struct desc_struct *table;
1042 if (!(selector & ~SEGMENT_RPL_MASK))
1045 table = get_current_gdt_ro();
1047 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1048 u16 ldt_selector = kvm_read_ldt();
1050 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1053 table = (struct desc_struct *)segment_base(ldt_selector);
1055 v = get_desc_base(&table[selector >> 3]);
1060 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1062 return (pt_mode == PT_MODE_HOST_GUEST) &&
1063 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1066 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1070 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1071 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1072 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1073 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1074 for (i = 0; i < addr_range; i++) {
1075 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1076 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1080 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1084 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1085 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1086 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1087 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1088 for (i = 0; i < addr_range; i++) {
1089 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1090 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1094 static void pt_guest_enter(struct vcpu_vmx *vmx)
1096 if (pt_mode == PT_MODE_SYSTEM)
1100 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1101 * Save host state before VM entry.
1103 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1104 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1105 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1106 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1107 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1111 static void pt_guest_exit(struct vcpu_vmx *vmx)
1113 if (pt_mode == PT_MODE_SYSTEM)
1116 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1117 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1118 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1121 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1122 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1125 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1126 unsigned long fs_base, unsigned long gs_base)
1128 if (unlikely(fs_sel != host->fs_sel)) {
1130 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1132 vmcs_write16(HOST_FS_SELECTOR, 0);
1133 host->fs_sel = fs_sel;
1135 if (unlikely(gs_sel != host->gs_sel)) {
1137 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1139 vmcs_write16(HOST_GS_SELECTOR, 0);
1140 host->gs_sel = gs_sel;
1142 if (unlikely(fs_base != host->fs_base)) {
1143 vmcs_writel(HOST_FS_BASE, fs_base);
1144 host->fs_base = fs_base;
1146 if (unlikely(gs_base != host->gs_base)) {
1147 vmcs_writel(HOST_GS_BASE, gs_base);
1148 host->gs_base = gs_base;
1152 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1154 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155 struct vmcs_host_state *host_state;
1156 #ifdef CONFIG_X86_64
1157 int cpu = raw_smp_processor_id();
1159 unsigned long fs_base, gs_base;
1163 vmx->req_immediate_exit = false;
1166 * Note that guest MSRs to be saved/restored can also be changed
1167 * when guest state is loaded. This happens when guest transitions
1168 * to/from long-mode by setting MSR_EFER.LMA.
1170 if (!vmx->guest_msrs_ready) {
1171 vmx->guest_msrs_ready = true;
1172 for (i = 0; i < vmx->save_nmsrs; ++i)
1173 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1174 vmx->guest_msrs[i].data,
1175 vmx->guest_msrs[i].mask);
1179 if (vmx->nested.need_vmcs12_to_shadow_sync)
1180 nested_sync_vmcs12_to_shadow(vcpu);
1182 if (vmx->guest_state_loaded)
1185 host_state = &vmx->loaded_vmcs->host_state;
1188 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1189 * allow segment selectors with cpl > 0 or ti == 1.
1191 host_state->ldt_sel = kvm_read_ldt();
1193 #ifdef CONFIG_X86_64
1194 savesegment(ds, host_state->ds_sel);
1195 savesegment(es, host_state->es_sel);
1197 gs_base = cpu_kernelmode_gs_base(cpu);
1198 if (likely(is_64bit_mm(current->mm))) {
1199 save_fsgs_for_kvm();
1200 fs_sel = current->thread.fsindex;
1201 gs_sel = current->thread.gsindex;
1202 fs_base = current->thread.fsbase;
1203 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1205 savesegment(fs, fs_sel);
1206 savesegment(gs, gs_sel);
1207 fs_base = read_msr(MSR_FS_BASE);
1208 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1211 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1213 savesegment(fs, fs_sel);
1214 savesegment(gs, gs_sel);
1215 fs_base = segment_base(fs_sel);
1216 gs_base = segment_base(gs_sel);
1219 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1220 vmx->guest_state_loaded = true;
1223 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1225 struct vmcs_host_state *host_state;
1227 if (!vmx->guest_state_loaded)
1230 host_state = &vmx->loaded_vmcs->host_state;
1232 ++vmx->vcpu.stat.host_state_reload;
1234 #ifdef CONFIG_X86_64
1235 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1237 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1238 kvm_load_ldt(host_state->ldt_sel);
1239 #ifdef CONFIG_X86_64
1240 load_gs_index(host_state->gs_sel);
1242 loadsegment(gs, host_state->gs_sel);
1245 if (host_state->fs_sel & 7)
1246 loadsegment(fs, host_state->fs_sel);
1247 #ifdef CONFIG_X86_64
1248 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1249 loadsegment(ds, host_state->ds_sel);
1250 loadsegment(es, host_state->es_sel);
1253 invalidate_tss_limit();
1254 #ifdef CONFIG_X86_64
1255 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1257 load_fixmap_gdt(raw_smp_processor_id());
1258 vmx->guest_state_loaded = false;
1259 vmx->guest_msrs_ready = false;
1262 #ifdef CONFIG_X86_64
1263 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1266 if (vmx->guest_state_loaded)
1267 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1269 return vmx->msr_guest_kernel_gs_base;
1272 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1275 if (vmx->guest_state_loaded)
1276 wrmsrl(MSR_KERNEL_GS_BASE, data);
1278 vmx->msr_guest_kernel_gs_base = data;
1282 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1284 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1285 struct pi_desc old, new;
1289 * In case of hot-plug or hot-unplug, we may have to undo
1290 * vmx_vcpu_pi_put even if there is no assigned device. And we
1291 * always keep PI.NDST up to date for simplicity: it makes the
1292 * code easier, and CPU migration is not a fast path.
1294 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1298 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1299 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1300 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1301 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1304 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1305 pi_clear_sn(pi_desc);
1306 goto after_clear_sn;
1309 /* The full case. */
1311 old.control = new.control = pi_desc->control;
1313 dest = cpu_physical_id(cpu);
1315 if (x2apic_enabled())
1318 new.ndst = (dest << 8) & 0xFF00;
1321 } while (cmpxchg64(&pi_desc->control, old.control,
1322 new.control) != old.control);
1327 * Clear SN before reading the bitmap. The VT-d firmware
1328 * writes the bitmap and reads SN atomically (5.2.3 in the
1329 * spec), so it doesn't really have a memory barrier that
1330 * pairs with this, but we cannot do that and we need one.
1332 smp_mb__after_atomic();
1334 if (!pi_is_pir_empty(pi_desc))
1338 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1340 struct vcpu_vmx *vmx = to_vmx(vcpu);
1341 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1343 if (!already_loaded) {
1344 loaded_vmcs_clear(vmx->loaded_vmcs);
1345 local_irq_disable();
1346 crash_disable_local_vmclear(cpu);
1349 * Read loaded_vmcs->cpu should be before fetching
1350 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1351 * See the comments in __loaded_vmcs_clear().
1355 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1356 &per_cpu(loaded_vmcss_on_cpu, cpu));
1357 crash_enable_local_vmclear(cpu);
1361 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1362 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1363 vmcs_load(vmx->loaded_vmcs->vmcs);
1364 indirect_branch_prediction_barrier();
1367 if (!already_loaded) {
1368 void *gdt = get_current_gdt_ro();
1369 unsigned long sysenter_esp;
1371 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1374 * Linux uses per-cpu TSS and GDT, so set these when switching
1375 * processors. See 22.2.4.
1377 vmcs_writel(HOST_TR_BASE,
1378 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1379 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1381 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1382 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1384 vmx->loaded_vmcs->cpu = cpu;
1387 /* Setup TSC multiplier */
1388 if (kvm_has_tsc_control &&
1389 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1390 decache_tsc_multiplier(vmx);
1394 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1395 * vcpu mutex is already taken.
1397 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1399 struct vcpu_vmx *vmx = to_vmx(vcpu);
1401 vmx_vcpu_load_vmcs(vcpu, cpu);
1403 vmx_vcpu_pi_load(vcpu, cpu);
1405 vmx->host_pkru = read_pkru();
1406 vmx->host_debugctlmsr = get_debugctlmsr();
1409 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1411 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1413 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1414 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1415 !kvm_vcpu_apicv_active(vcpu))
1418 /* Set SN when the vCPU is preempted */
1419 if (vcpu->preempted)
1423 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1425 vmx_vcpu_pi_put(vcpu);
1427 vmx_prepare_switch_to_host(to_vmx(vcpu));
1430 static bool emulation_required(struct kvm_vcpu *vcpu)
1432 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1435 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1437 struct vcpu_vmx *vmx = to_vmx(vcpu);
1438 unsigned long rflags, save_rflags;
1440 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1441 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1442 rflags = vmcs_readl(GUEST_RFLAGS);
1443 if (vmx->rmode.vm86_active) {
1444 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1445 save_rflags = vmx->rmode.save_rflags;
1446 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1448 vmx->rflags = rflags;
1453 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1455 struct vcpu_vmx *vmx = to_vmx(vcpu);
1456 unsigned long old_rflags;
1458 if (enable_unrestricted_guest) {
1459 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1460 vmx->rflags = rflags;
1461 vmcs_writel(GUEST_RFLAGS, rflags);
1465 old_rflags = vmx_get_rflags(vcpu);
1466 vmx->rflags = rflags;
1467 if (vmx->rmode.vm86_active) {
1468 vmx->rmode.save_rflags = rflags;
1469 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1471 vmcs_writel(GUEST_RFLAGS, rflags);
1473 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1474 vmx->emulation_required = emulation_required(vcpu);
1477 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1479 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1482 if (interruptibility & GUEST_INTR_STATE_STI)
1483 ret |= KVM_X86_SHADOW_INT_STI;
1484 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1485 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1490 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1492 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1493 u32 interruptibility = interruptibility_old;
1495 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1497 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1498 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1499 else if (mask & KVM_X86_SHADOW_INT_STI)
1500 interruptibility |= GUEST_INTR_STATE_STI;
1502 if ((interruptibility != interruptibility_old))
1503 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1506 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1508 struct vcpu_vmx *vmx = to_vmx(vcpu);
1509 unsigned long value;
1512 * Any MSR write that attempts to change bits marked reserved will
1515 if (data & vmx->pt_desc.ctl_bitmask)
1519 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1520 * result in a #GP unless the same write also clears TraceEn.
1522 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1523 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1527 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1528 * and FabricEn would cause #GP, if
1529 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1531 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1532 !(data & RTIT_CTL_FABRIC_EN) &&
1533 !intel_pt_validate_cap(vmx->pt_desc.caps,
1534 PT_CAP_single_range_output))
1538 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1539 * utilize encodings marked reserved will casue a #GP fault.
1541 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1542 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1543 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1544 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1546 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1547 PT_CAP_cycle_thresholds);
1548 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1549 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1550 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1552 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1553 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1554 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1555 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1559 * If ADDRx_CFG is reserved or the encodings is >2 will
1560 * cause a #GP fault.
1562 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1563 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1565 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1566 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1568 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1569 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1571 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1572 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1578 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1583 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1584 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1585 * set when EPT misconfig occurs. In practice, real hardware updates
1586 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1587 * (namely Hyper-V) don't set it due to it being undefined behavior,
1588 * i.e. we end up advancing IP with some random value.
1590 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1591 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1592 rip = kvm_rip_read(vcpu);
1593 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1594 kvm_rip_write(vcpu, rip);
1596 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1600 /* skipping an emulated instruction also counts */
1601 vmx_set_interrupt_shadow(vcpu, 0);
1608 * Recognizes a pending MTF VM-exit and records the nested state for later
1611 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1613 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1614 struct vcpu_vmx *vmx = to_vmx(vcpu);
1616 if (!is_guest_mode(vcpu))
1620 * Per the SDM, MTF takes priority over debug-trap exceptions besides
1621 * T-bit traps. As instruction emulation is completed (i.e. at the
1622 * instruction boundary), any #DB exception pending delivery must be a
1623 * debug-trap. Record the pending MTF state to be delivered in
1624 * vmx_check_nested_events().
1626 if (nested_cpu_has_mtf(vmcs12) &&
1627 (!vcpu->arch.exception.pending ||
1628 vcpu->arch.exception.nr == DB_VECTOR))
1629 vmx->nested.mtf_pending = true;
1631 vmx->nested.mtf_pending = false;
1634 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1636 vmx_update_emulated_instruction(vcpu);
1637 return skip_emulated_instruction(vcpu);
1640 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1643 * Ensure that we clear the HLT state in the VMCS. We don't need to
1644 * explicitly skip the instruction because if the HLT state is set,
1645 * then the instruction is already executing and RIP has already been
1648 if (kvm_hlt_in_guest(vcpu->kvm) &&
1649 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1650 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1653 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1655 struct vcpu_vmx *vmx = to_vmx(vcpu);
1656 unsigned nr = vcpu->arch.exception.nr;
1657 bool has_error_code = vcpu->arch.exception.has_error_code;
1658 u32 error_code = vcpu->arch.exception.error_code;
1659 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1661 kvm_deliver_exception_payload(vcpu);
1663 if (has_error_code) {
1664 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1665 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1668 if (vmx->rmode.vm86_active) {
1670 if (kvm_exception_is_soft(nr))
1671 inc_eip = vcpu->arch.event_exit_inst_len;
1672 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1676 WARN_ON_ONCE(vmx->emulation_required);
1678 if (kvm_exception_is_soft(nr)) {
1679 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1680 vmx->vcpu.arch.event_exit_inst_len);
1681 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1683 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1685 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1687 vmx_clear_hlt(vcpu);
1690 static bool vmx_rdtscp_supported(void)
1692 return cpu_has_vmx_rdtscp();
1695 static bool vmx_invpcid_supported(void)
1697 return cpu_has_vmx_invpcid();
1701 * Swap MSR entry in host/guest MSR entry array.
1703 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1705 struct shared_msr_entry tmp;
1707 tmp = vmx->guest_msrs[to];
1708 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1709 vmx->guest_msrs[from] = tmp;
1713 * Set up the vmcs to automatically save and restore system
1714 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1715 * mode, as fiddling with msrs is very expensive.
1717 static void setup_msrs(struct vcpu_vmx *vmx)
1719 int save_nmsrs, index;
1722 #ifdef CONFIG_X86_64
1724 * The SYSCALL MSRs are only needed on long mode guests, and only
1725 * when EFER.SCE is set.
1727 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1728 index = __find_msr_index(vmx, MSR_STAR);
1730 move_msr_up(vmx, index, save_nmsrs++);
1731 index = __find_msr_index(vmx, MSR_LSTAR);
1733 move_msr_up(vmx, index, save_nmsrs++);
1734 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1736 move_msr_up(vmx, index, save_nmsrs++);
1739 index = __find_msr_index(vmx, MSR_EFER);
1740 if (index >= 0 && update_transition_efer(vmx, index))
1741 move_msr_up(vmx, index, save_nmsrs++);
1742 index = __find_msr_index(vmx, MSR_TSC_AUX);
1743 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1744 move_msr_up(vmx, index, save_nmsrs++);
1745 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1747 move_msr_up(vmx, index, save_nmsrs++);
1749 vmx->save_nmsrs = save_nmsrs;
1750 vmx->guest_msrs_ready = false;
1752 if (cpu_has_vmx_msr_bitmap())
1753 vmx_update_msr_bitmap(&vmx->vcpu);
1756 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1758 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1760 if (is_guest_mode(vcpu) &&
1761 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1762 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1764 return vcpu->arch.tsc_offset;
1767 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1769 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1770 u64 g_tsc_offset = 0;
1773 * We're here if L1 chose not to trap WRMSR to TSC. According
1774 * to the spec, this should set L1's TSC; The offset that L1
1775 * set for L2 remains unchanged, and still needs to be added
1776 * to the newly set TSC to get L2's TSC.
1778 if (is_guest_mode(vcpu) &&
1779 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1780 g_tsc_offset = vmcs12->tsc_offset;
1782 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1783 vcpu->arch.tsc_offset - g_tsc_offset,
1785 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1786 return offset + g_tsc_offset;
1790 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1791 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1792 * all guests if the "nested" module option is off, and can also be disabled
1793 * for a single guest by disabling its VMX cpuid bit.
1795 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1797 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1800 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1803 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1805 return !(val & ~valid_bits);
1808 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1810 switch (msr->index) {
1811 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1814 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1821 * Reads an msr value (of 'msr_index') into 'pdata'.
1822 * Returns 0 on success, non-0 otherwise.
1823 * Assumes vcpu_load() was already called.
1825 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1827 struct vcpu_vmx *vmx = to_vmx(vcpu);
1828 struct shared_msr_entry *msr;
1831 switch (msr_info->index) {
1832 #ifdef CONFIG_X86_64
1834 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1837 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1839 case MSR_KERNEL_GS_BASE:
1840 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1844 return kvm_get_msr_common(vcpu, msr_info);
1845 case MSR_IA32_TSX_CTRL:
1846 if (!msr_info->host_initiated &&
1847 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1849 goto find_shared_msr;
1850 case MSR_IA32_UMWAIT_CONTROL:
1851 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1854 msr_info->data = vmx->msr_ia32_umwait_control;
1856 case MSR_IA32_SPEC_CTRL:
1857 if (!msr_info->host_initiated &&
1858 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1861 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1863 case MSR_IA32_SYSENTER_CS:
1864 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1866 case MSR_IA32_SYSENTER_EIP:
1867 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1869 case MSR_IA32_SYSENTER_ESP:
1870 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1872 case MSR_IA32_BNDCFGS:
1873 if (!kvm_mpx_supported() ||
1874 (!msr_info->host_initiated &&
1875 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1877 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1879 case MSR_IA32_MCG_EXT_CTL:
1880 if (!msr_info->host_initiated &&
1881 !(vmx->msr_ia32_feature_control &
1882 FEAT_CTL_LMCE_ENABLED))
1884 msr_info->data = vcpu->arch.mcg_ext_ctl;
1886 case MSR_IA32_FEAT_CTL:
1887 msr_info->data = vmx->msr_ia32_feature_control;
1889 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1890 if (!nested_vmx_allowed(vcpu))
1892 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1896 * Enlightened VMCS v1 doesn't have certain fields, but buggy
1897 * Hyper-V versions are still trying to use corresponding
1898 * features when they are exposed. Filter out the essential
1901 if (!msr_info->host_initiated &&
1902 vmx->nested.enlightened_vmcs_enabled)
1903 nested_evmcs_filter_control_msr(msr_info->index,
1906 case MSR_IA32_RTIT_CTL:
1907 if (pt_mode != PT_MODE_HOST_GUEST)
1909 msr_info->data = vmx->pt_desc.guest.ctl;
1911 case MSR_IA32_RTIT_STATUS:
1912 if (pt_mode != PT_MODE_HOST_GUEST)
1914 msr_info->data = vmx->pt_desc.guest.status;
1916 case MSR_IA32_RTIT_CR3_MATCH:
1917 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1918 !intel_pt_validate_cap(vmx->pt_desc.caps,
1919 PT_CAP_cr3_filtering))
1921 msr_info->data = vmx->pt_desc.guest.cr3_match;
1923 case MSR_IA32_RTIT_OUTPUT_BASE:
1924 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1925 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1926 PT_CAP_topa_output) &&
1927 !intel_pt_validate_cap(vmx->pt_desc.caps,
1928 PT_CAP_single_range_output)))
1930 msr_info->data = vmx->pt_desc.guest.output_base;
1932 case MSR_IA32_RTIT_OUTPUT_MASK:
1933 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1934 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1935 PT_CAP_topa_output) &&
1936 !intel_pt_validate_cap(vmx->pt_desc.caps,
1937 PT_CAP_single_range_output)))
1939 msr_info->data = vmx->pt_desc.guest.output_mask;
1941 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1942 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1943 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1944 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1945 PT_CAP_num_address_ranges)))
1948 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1950 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1953 if (!msr_info->host_initiated &&
1954 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1956 goto find_shared_msr;
1959 msr = find_msr_entry(vmx, msr_info->index);
1961 msr_info->data = msr->data;
1964 return kvm_get_msr_common(vcpu, msr_info);
1971 * Writes msr value into the appropriate "register".
1972 * Returns 0 on success, non-0 otherwise.
1973 * Assumes vcpu_load() was already called.
1975 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1977 struct vcpu_vmx *vmx = to_vmx(vcpu);
1978 struct shared_msr_entry *msr;
1980 u32 msr_index = msr_info->index;
1981 u64 data = msr_info->data;
1984 switch (msr_index) {
1986 ret = kvm_set_msr_common(vcpu, msr_info);
1988 #ifdef CONFIG_X86_64
1990 vmx_segment_cache_clear(vmx);
1991 vmcs_writel(GUEST_FS_BASE, data);
1994 vmx_segment_cache_clear(vmx);
1995 vmcs_writel(GUEST_GS_BASE, data);
1997 case MSR_KERNEL_GS_BASE:
1998 vmx_write_guest_kernel_gs_base(vmx, data);
2001 case MSR_IA32_SYSENTER_CS:
2002 if (is_guest_mode(vcpu))
2003 get_vmcs12(vcpu)->guest_sysenter_cs = data;
2004 vmcs_write32(GUEST_SYSENTER_CS, data);
2006 case MSR_IA32_SYSENTER_EIP:
2007 if (is_guest_mode(vcpu))
2008 get_vmcs12(vcpu)->guest_sysenter_eip = data;
2009 vmcs_writel(GUEST_SYSENTER_EIP, data);
2011 case MSR_IA32_SYSENTER_ESP:
2012 if (is_guest_mode(vcpu))
2013 get_vmcs12(vcpu)->guest_sysenter_esp = data;
2014 vmcs_writel(GUEST_SYSENTER_ESP, data);
2016 case MSR_IA32_DEBUGCTLMSR:
2017 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
2018 VM_EXIT_SAVE_DEBUG_CONTROLS)
2019 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2021 ret = kvm_set_msr_common(vcpu, msr_info);
2024 case MSR_IA32_BNDCFGS:
2025 if (!kvm_mpx_supported() ||
2026 (!msr_info->host_initiated &&
2027 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2029 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2030 (data & MSR_IA32_BNDCFGS_RSVD))
2032 vmcs_write64(GUEST_BNDCFGS, data);
2034 case MSR_IA32_UMWAIT_CONTROL:
2035 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2038 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2039 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2042 vmx->msr_ia32_umwait_control = data;
2044 case MSR_IA32_SPEC_CTRL:
2045 if (!msr_info->host_initiated &&
2046 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2049 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
2052 vmx->spec_ctrl = data;
2058 * When it's written (to non-zero) for the first time, pass
2062 * The handling of the MSR bitmap for L2 guests is done in
2063 * nested_vmx_prepare_msr_bitmap. We should not touch the
2064 * vmcs02.msr_bitmap here since it gets completely overwritten
2065 * in the merging. We update the vmcs01 here for L1 as well
2066 * since it will end up touching the MSR anyway now.
2068 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2072 case MSR_IA32_TSX_CTRL:
2073 if (!msr_info->host_initiated &&
2074 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2076 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2078 goto find_shared_msr;
2079 case MSR_IA32_PRED_CMD:
2080 if (!msr_info->host_initiated &&
2081 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2084 if (data & ~PRED_CMD_IBPB)
2086 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2091 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2095 * When it's written (to non-zero) for the first time, pass
2099 * The handling of the MSR bitmap for L2 guests is done in
2100 * nested_vmx_prepare_msr_bitmap. We should not touch the
2101 * vmcs02.msr_bitmap here since it gets completely overwritten
2104 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2107 case MSR_IA32_CR_PAT:
2108 if (!kvm_pat_valid(data))
2111 if (is_guest_mode(vcpu) &&
2112 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2113 get_vmcs12(vcpu)->guest_ia32_pat = data;
2115 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2116 vmcs_write64(GUEST_IA32_PAT, data);
2117 vcpu->arch.pat = data;
2120 ret = kvm_set_msr_common(vcpu, msr_info);
2122 case MSR_IA32_TSC_ADJUST:
2123 ret = kvm_set_msr_common(vcpu, msr_info);
2125 case MSR_IA32_MCG_EXT_CTL:
2126 if ((!msr_info->host_initiated &&
2127 !(to_vmx(vcpu)->msr_ia32_feature_control &
2128 FEAT_CTL_LMCE_ENABLED)) ||
2129 (data & ~MCG_EXT_CTL_LMCE_EN))
2131 vcpu->arch.mcg_ext_ctl = data;
2133 case MSR_IA32_FEAT_CTL:
2134 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2135 (to_vmx(vcpu)->msr_ia32_feature_control &
2136 FEAT_CTL_LOCKED && !msr_info->host_initiated))
2138 vmx->msr_ia32_feature_control = data;
2139 if (msr_info->host_initiated && data == 0)
2140 vmx_leave_nested(vcpu);
2142 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2143 if (!msr_info->host_initiated)
2144 return 1; /* they are read-only */
2145 if (!nested_vmx_allowed(vcpu))
2147 return vmx_set_vmx_msr(vcpu, msr_index, data);
2148 case MSR_IA32_RTIT_CTL:
2149 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2150 vmx_rtit_ctl_check(vcpu, data) ||
2153 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2154 vmx->pt_desc.guest.ctl = data;
2155 pt_update_intercept_for_msr(vmx);
2157 case MSR_IA32_RTIT_STATUS:
2158 if (!pt_can_write_msr(vmx))
2160 if (data & MSR_IA32_RTIT_STATUS_MASK)
2162 vmx->pt_desc.guest.status = data;
2164 case MSR_IA32_RTIT_CR3_MATCH:
2165 if (!pt_can_write_msr(vmx))
2167 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2168 PT_CAP_cr3_filtering))
2170 vmx->pt_desc.guest.cr3_match = data;
2172 case MSR_IA32_RTIT_OUTPUT_BASE:
2173 if (!pt_can_write_msr(vmx))
2175 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2176 PT_CAP_topa_output) &&
2177 !intel_pt_validate_cap(vmx->pt_desc.caps,
2178 PT_CAP_single_range_output))
2180 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
2182 vmx->pt_desc.guest.output_base = data;
2184 case MSR_IA32_RTIT_OUTPUT_MASK:
2185 if (!pt_can_write_msr(vmx))
2187 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2188 PT_CAP_topa_output) &&
2189 !intel_pt_validate_cap(vmx->pt_desc.caps,
2190 PT_CAP_single_range_output))
2192 vmx->pt_desc.guest.output_mask = data;
2194 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2195 if (!pt_can_write_msr(vmx))
2197 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2198 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2199 PT_CAP_num_address_ranges))
2201 if (is_noncanonical_address(data, vcpu))
2204 vmx->pt_desc.guest.addr_b[index / 2] = data;
2206 vmx->pt_desc.guest.addr_a[index / 2] = data;
2209 if (!msr_info->host_initiated &&
2210 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2212 /* Check reserved bit, higher 32 bits should be zero */
2213 if ((data >> 32) != 0)
2215 goto find_shared_msr;
2219 msr = find_msr_entry(vmx, msr_index);
2221 ret = vmx_set_guest_msr(vmx, msr, data);
2223 ret = kvm_set_msr_common(vcpu, msr_info);
2229 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2231 kvm_register_mark_available(vcpu, reg);
2235 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2238 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2240 case VCPU_EXREG_PDPTR:
2242 ept_save_pdptrs(vcpu);
2244 case VCPU_EXREG_CR3:
2245 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2246 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2254 static __init int cpu_has_kvm_support(void)
2256 return cpu_has_vmx();
2259 static __init int vmx_disabled_by_bios(void)
2261 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2262 !boot_cpu_has(X86_FEATURE_VMX);
2265 static void kvm_cpu_vmxon(u64 addr)
2267 cr4_set_bits(X86_CR4_VMXE);
2268 intel_pt_handle_vmx(1);
2270 asm volatile ("vmxon %0" : : "m"(addr));
2273 static int hardware_enable(void)
2275 int cpu = raw_smp_processor_id();
2276 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2278 if (cr4_read_shadow() & X86_CR4_VMXE)
2282 * This can happen if we hot-added a CPU but failed to allocate
2283 * VP assist page for it.
2285 if (static_branch_unlikely(&enable_evmcs) &&
2286 !hv_get_vp_assist_page(cpu))
2289 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2290 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2291 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2294 * Now we can enable the vmclear operation in kdump
2295 * since the loaded_vmcss_on_cpu list on this cpu
2296 * has been initialized.
2298 * Though the cpu is not in VMX operation now, there
2299 * is no problem to enable the vmclear operation
2300 * for the loaded_vmcss_on_cpu list is empty!
2302 crash_enable_local_vmclear(cpu);
2304 kvm_cpu_vmxon(phys_addr);
2311 static void vmclear_local_loaded_vmcss(void)
2313 int cpu = raw_smp_processor_id();
2314 struct loaded_vmcs *v, *n;
2316 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2317 loaded_vmcss_on_cpu_link)
2318 __loaded_vmcs_clear(v);
2322 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2325 static void kvm_cpu_vmxoff(void)
2327 asm volatile (__ex("vmxoff"));
2329 intel_pt_handle_vmx(0);
2330 cr4_clear_bits(X86_CR4_VMXE);
2333 static void hardware_disable(void)
2335 vmclear_local_loaded_vmcss();
2339 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2340 u32 msr, u32 *result)
2342 u32 vmx_msr_low, vmx_msr_high;
2343 u32 ctl = ctl_min | ctl_opt;
2345 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2347 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2348 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2350 /* Ensure minimum (required) set of control bits are supported. */
2358 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2359 struct vmx_capability *vmx_cap)
2361 u32 vmx_msr_low, vmx_msr_high;
2362 u32 min, opt, min2, opt2;
2363 u32 _pin_based_exec_control = 0;
2364 u32 _cpu_based_exec_control = 0;
2365 u32 _cpu_based_2nd_exec_control = 0;
2366 u32 _vmexit_control = 0;
2367 u32 _vmentry_control = 0;
2369 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2370 min = CPU_BASED_HLT_EXITING |
2371 #ifdef CONFIG_X86_64
2372 CPU_BASED_CR8_LOAD_EXITING |
2373 CPU_BASED_CR8_STORE_EXITING |
2375 CPU_BASED_CR3_LOAD_EXITING |
2376 CPU_BASED_CR3_STORE_EXITING |
2377 CPU_BASED_UNCOND_IO_EXITING |
2378 CPU_BASED_MOV_DR_EXITING |
2379 CPU_BASED_USE_TSC_OFFSETTING |
2380 CPU_BASED_MWAIT_EXITING |
2381 CPU_BASED_MONITOR_EXITING |
2382 CPU_BASED_INVLPG_EXITING |
2383 CPU_BASED_RDPMC_EXITING;
2385 opt = CPU_BASED_TPR_SHADOW |
2386 CPU_BASED_USE_MSR_BITMAPS |
2387 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2388 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2389 &_cpu_based_exec_control) < 0)
2391 #ifdef CONFIG_X86_64
2392 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2393 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2394 ~CPU_BASED_CR8_STORE_EXITING;
2396 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2398 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2399 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2400 SECONDARY_EXEC_WBINVD_EXITING |
2401 SECONDARY_EXEC_ENABLE_VPID |
2402 SECONDARY_EXEC_ENABLE_EPT |
2403 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2404 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2405 SECONDARY_EXEC_DESC |
2406 SECONDARY_EXEC_RDTSCP |
2407 SECONDARY_EXEC_ENABLE_INVPCID |
2408 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2409 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2410 SECONDARY_EXEC_SHADOW_VMCS |
2411 SECONDARY_EXEC_XSAVES |
2412 SECONDARY_EXEC_RDSEED_EXITING |
2413 SECONDARY_EXEC_RDRAND_EXITING |
2414 SECONDARY_EXEC_ENABLE_PML |
2415 SECONDARY_EXEC_TSC_SCALING |
2416 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2417 SECONDARY_EXEC_PT_USE_GPA |
2418 SECONDARY_EXEC_PT_CONCEAL_VMX |
2419 SECONDARY_EXEC_ENABLE_VMFUNC |
2420 SECONDARY_EXEC_ENCLS_EXITING;
2421 if (adjust_vmx_controls(min2, opt2,
2422 MSR_IA32_VMX_PROCBASED_CTLS2,
2423 &_cpu_based_2nd_exec_control) < 0)
2426 #ifndef CONFIG_X86_64
2427 if (!(_cpu_based_2nd_exec_control &
2428 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2429 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2432 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2433 _cpu_based_2nd_exec_control &= ~(
2434 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2435 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2436 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2438 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2439 &vmx_cap->ept, &vmx_cap->vpid);
2441 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2442 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2444 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2445 CPU_BASED_CR3_STORE_EXITING |
2446 CPU_BASED_INVLPG_EXITING);
2447 } else if (vmx_cap->ept) {
2449 pr_warn_once("EPT CAP should not exist if not support "
2450 "1-setting enable EPT VM-execution control\n");
2452 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2455 pr_warn_once("VPID CAP should not exist if not support "
2456 "1-setting enable VPID VM-execution control\n");
2459 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2460 #ifdef CONFIG_X86_64
2461 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2463 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2464 VM_EXIT_LOAD_IA32_PAT |
2465 VM_EXIT_LOAD_IA32_EFER |
2466 VM_EXIT_CLEAR_BNDCFGS |
2467 VM_EXIT_PT_CONCEAL_PIP |
2468 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2469 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2470 &_vmexit_control) < 0)
2473 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2474 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2475 PIN_BASED_VMX_PREEMPTION_TIMER;
2476 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2477 &_pin_based_exec_control) < 0)
2480 if (cpu_has_broken_vmx_preemption_timer())
2481 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2482 if (!(_cpu_based_2nd_exec_control &
2483 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2484 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2486 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2487 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2488 VM_ENTRY_LOAD_IA32_PAT |
2489 VM_ENTRY_LOAD_IA32_EFER |
2490 VM_ENTRY_LOAD_BNDCFGS |
2491 VM_ENTRY_PT_CONCEAL_PIP |
2492 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2493 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2494 &_vmentry_control) < 0)
2498 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2499 * can't be used due to an errata where VM Exit may incorrectly clear
2500 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2501 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2503 if (boot_cpu_data.x86 == 0x6) {
2504 switch (boot_cpu_data.x86_model) {
2505 case 26: /* AAK155 */
2506 case 30: /* AAP115 */
2507 case 37: /* AAT100 */
2508 case 44: /* BC86,AAY89,BD102 */
2510 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2511 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2512 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2513 "does not work properly. Using workaround\n");
2521 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2523 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2524 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2527 #ifdef CONFIG_X86_64
2528 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2529 if (vmx_msr_high & (1u<<16))
2533 /* Require Write-Back (WB) memory type for VMCS accesses. */
2534 if (((vmx_msr_high >> 18) & 15) != 6)
2537 vmcs_conf->size = vmx_msr_high & 0x1fff;
2538 vmcs_conf->order = get_order(vmcs_conf->size);
2539 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2541 vmcs_conf->revision_id = vmx_msr_low;
2543 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2544 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2545 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2546 vmcs_conf->vmexit_ctrl = _vmexit_control;
2547 vmcs_conf->vmentry_ctrl = _vmentry_control;
2549 if (static_branch_unlikely(&enable_evmcs))
2550 evmcs_sanitize_exec_ctrls(vmcs_conf);
2555 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2557 int node = cpu_to_node(cpu);
2561 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2564 vmcs = page_address(pages);
2565 memset(vmcs, 0, vmcs_config.size);
2567 /* KVM supports Enlightened VMCS v1 only */
2568 if (static_branch_unlikely(&enable_evmcs))
2569 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2571 vmcs->hdr.revision_id = vmcs_config.revision_id;
2574 vmcs->hdr.shadow_vmcs = 1;
2578 void free_vmcs(struct vmcs *vmcs)
2580 free_pages((unsigned long)vmcs, vmcs_config.order);
2584 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2586 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2588 if (!loaded_vmcs->vmcs)
2590 loaded_vmcs_clear(loaded_vmcs);
2591 free_vmcs(loaded_vmcs->vmcs);
2592 loaded_vmcs->vmcs = NULL;
2593 if (loaded_vmcs->msr_bitmap)
2594 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2595 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2598 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2600 loaded_vmcs->vmcs = alloc_vmcs(false);
2601 if (!loaded_vmcs->vmcs)
2604 loaded_vmcs->shadow_vmcs = NULL;
2605 loaded_vmcs->hv_timer_soft_disabled = false;
2606 loaded_vmcs_init(loaded_vmcs);
2608 if (cpu_has_vmx_msr_bitmap()) {
2609 loaded_vmcs->msr_bitmap = (unsigned long *)
2610 __get_free_page(GFP_KERNEL_ACCOUNT);
2611 if (!loaded_vmcs->msr_bitmap)
2613 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2615 if (IS_ENABLED(CONFIG_HYPERV) &&
2616 static_branch_unlikely(&enable_evmcs) &&
2617 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2618 struct hv_enlightened_vmcs *evmcs =
2619 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2621 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2625 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2626 memset(&loaded_vmcs->controls_shadow, 0,
2627 sizeof(struct vmcs_controls_shadow));
2632 free_loaded_vmcs(loaded_vmcs);
2636 static void free_kvm_area(void)
2640 for_each_possible_cpu(cpu) {
2641 free_vmcs(per_cpu(vmxarea, cpu));
2642 per_cpu(vmxarea, cpu) = NULL;
2646 static __init int alloc_kvm_area(void)
2650 for_each_possible_cpu(cpu) {
2653 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2660 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2661 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2662 * revision_id reported by MSR_IA32_VMX_BASIC.
2664 * However, even though not explicitly documented by
2665 * TLFS, VMXArea passed as VMXON argument should
2666 * still be marked with revision_id reported by
2669 if (static_branch_unlikely(&enable_evmcs))
2670 vmcs->hdr.revision_id = vmcs_config.revision_id;
2672 per_cpu(vmxarea, cpu) = vmcs;
2677 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2678 struct kvm_segment *save)
2680 if (!emulate_invalid_guest_state) {
2682 * CS and SS RPL should be equal during guest entry according
2683 * to VMX spec, but in reality it is not always so. Since vcpu
2684 * is in the middle of the transition from real mode to
2685 * protected mode it is safe to assume that RPL 0 is a good
2688 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2689 save->selector &= ~SEGMENT_RPL_MASK;
2690 save->dpl = save->selector & SEGMENT_RPL_MASK;
2693 vmx_set_segment(vcpu, save, seg);
2696 static void enter_pmode(struct kvm_vcpu *vcpu)
2698 unsigned long flags;
2699 struct vcpu_vmx *vmx = to_vmx(vcpu);
2702 * Update real mode segment cache. It may be not up-to-date if sement
2703 * register was written while vcpu was in a guest mode.
2705 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2706 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2707 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2708 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2709 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2710 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2712 vmx->rmode.vm86_active = 0;
2714 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2716 flags = vmcs_readl(GUEST_RFLAGS);
2717 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2718 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2719 vmcs_writel(GUEST_RFLAGS, flags);
2721 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2722 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2724 update_exception_bitmap(vcpu);
2726 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2727 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2728 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2729 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2730 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2731 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2734 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2736 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2737 struct kvm_segment var = *save;
2740 if (seg == VCPU_SREG_CS)
2743 if (!emulate_invalid_guest_state) {
2744 var.selector = var.base >> 4;
2745 var.base = var.base & 0xffff0;
2755 if (save->base & 0xf)
2756 printk_once(KERN_WARNING "kvm: segment base is not "
2757 "paragraph aligned when entering "
2758 "protected mode (seg=%d)", seg);
2761 vmcs_write16(sf->selector, var.selector);
2762 vmcs_writel(sf->base, var.base);
2763 vmcs_write32(sf->limit, var.limit);
2764 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2767 static void enter_rmode(struct kvm_vcpu *vcpu)
2769 unsigned long flags;
2770 struct vcpu_vmx *vmx = to_vmx(vcpu);
2771 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2773 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2774 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2775 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2776 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2777 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2778 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2779 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2781 vmx->rmode.vm86_active = 1;
2784 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2785 * vcpu. Warn the user that an update is overdue.
2787 if (!kvm_vmx->tss_addr)
2788 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2789 "called before entering vcpu\n");
2791 vmx_segment_cache_clear(vmx);
2793 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2794 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2795 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2797 flags = vmcs_readl(GUEST_RFLAGS);
2798 vmx->rmode.save_rflags = flags;
2800 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2802 vmcs_writel(GUEST_RFLAGS, flags);
2803 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2804 update_exception_bitmap(vcpu);
2806 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2807 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2808 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2809 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2810 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2811 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2813 kvm_mmu_reset_context(vcpu);
2816 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2818 struct vcpu_vmx *vmx = to_vmx(vcpu);
2819 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2824 vcpu->arch.efer = efer;
2825 if (efer & EFER_LMA) {
2826 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2829 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2831 msr->data = efer & ~EFER_LME;
2836 #ifdef CONFIG_X86_64
2838 static void enter_lmode(struct kvm_vcpu *vcpu)
2842 vmx_segment_cache_clear(to_vmx(vcpu));
2844 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2845 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2846 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2848 vmcs_write32(GUEST_TR_AR_BYTES,
2849 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2850 | VMX_AR_TYPE_BUSY_64_TSS);
2852 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2855 static void exit_lmode(struct kvm_vcpu *vcpu)
2857 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2858 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2863 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2865 int vpid = to_vmx(vcpu)->vpid;
2867 if (!vpid_sync_vcpu_addr(vpid, addr))
2868 vpid_sync_context(vpid);
2871 * If VPIDs are not supported or enabled, then the above is a no-op.
2872 * But we don't really need a TLB flush in that case anyway, because
2873 * each VM entry/exit includes an implicit flush when VPID is 0.
2877 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2879 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2881 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2882 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2885 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2887 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2889 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2890 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2893 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2895 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2897 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2900 if (is_pae_paging(vcpu)) {
2901 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2902 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2903 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2904 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2908 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2910 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2912 if (is_pae_paging(vcpu)) {
2913 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2914 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2915 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2916 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2919 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2922 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2924 struct kvm_vcpu *vcpu)
2926 struct vcpu_vmx *vmx = to_vmx(vcpu);
2928 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2929 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2930 if (!(cr0 & X86_CR0_PG)) {
2931 /* From paging/starting to nonpaging */
2932 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2933 CPU_BASED_CR3_STORE_EXITING);
2934 vcpu->arch.cr0 = cr0;
2935 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2936 } else if (!is_paging(vcpu)) {
2937 /* From nonpaging to paging */
2938 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2939 CPU_BASED_CR3_STORE_EXITING);
2940 vcpu->arch.cr0 = cr0;
2941 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2944 if (!(cr0 & X86_CR0_WP))
2945 *hw_cr0 &= ~X86_CR0_WP;
2948 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2950 struct vcpu_vmx *vmx = to_vmx(vcpu);
2951 unsigned long hw_cr0;
2953 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2954 if (enable_unrestricted_guest)
2955 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2957 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2959 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2962 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2966 #ifdef CONFIG_X86_64
2967 if (vcpu->arch.efer & EFER_LME) {
2968 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2970 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2975 if (enable_ept && !enable_unrestricted_guest)
2976 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2978 vmcs_writel(CR0_READ_SHADOW, cr0);
2979 vmcs_writel(GUEST_CR0, hw_cr0);
2980 vcpu->arch.cr0 = cr0;
2982 /* depends on vcpu->arch.cr0 to be set to a new value */
2983 vmx->emulation_required = emulation_required(vcpu);
2986 static int get_ept_level(struct kvm_vcpu *vcpu)
2988 /* Nested EPT currently only supports 4-level walks. */
2989 if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu)))
2991 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2996 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2998 u64 eptp = VMX_EPTP_MT_WB;
3000 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3002 if (enable_ept_ad_bits &&
3003 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3004 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3005 eptp |= (root_hpa & PAGE_MASK);
3010 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3012 struct kvm *kvm = vcpu->kvm;
3013 bool update_guest_cr3 = true;
3014 unsigned long guest_cr3;
3019 eptp = construct_eptp(vcpu, cr3);
3020 vmcs_write64(EPT_POINTER, eptp);
3022 if (kvm_x86_ops->tlb_remote_flush) {
3023 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3024 to_vmx(vcpu)->ept_pointer = eptp;
3025 to_kvm_vmx(kvm)->ept_pointers_match
3026 = EPT_POINTERS_CHECK;
3027 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3030 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3031 if (is_guest_mode(vcpu))
3032 update_guest_cr3 = false;
3033 else if (!enable_unrestricted_guest && !is_paging(vcpu))
3034 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3035 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3036 guest_cr3 = vcpu->arch.cr3;
3037 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3038 update_guest_cr3 = false;
3039 ept_load_pdptrs(vcpu);
3042 if (update_guest_cr3)
3043 vmcs_writel(GUEST_CR3, guest_cr3);
3046 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3048 struct vcpu_vmx *vmx = to_vmx(vcpu);
3050 * Pass through host's Machine Check Enable value to hw_cr4, which
3051 * is in force while we are in guest mode. Do not let guests control
3052 * this bit, even if host CR4.MCE == 0.
3054 unsigned long hw_cr4;
3056 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3057 if (enable_unrestricted_guest)
3058 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3059 else if (vmx->rmode.vm86_active)
3060 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3062 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3064 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3065 if (cr4 & X86_CR4_UMIP) {
3066 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3067 hw_cr4 &= ~X86_CR4_UMIP;
3068 } else if (!is_guest_mode(vcpu) ||
3069 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3070 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3074 if (cr4 & X86_CR4_VMXE) {
3076 * To use VMXON (and later other VMX instructions), a guest
3077 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3078 * So basically the check on whether to allow nested VMX
3079 * is here. We operate under the default treatment of SMM,
3080 * so VMX cannot be enabled under SMM.
3082 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3086 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3089 vcpu->arch.cr4 = cr4;
3091 if (!enable_unrestricted_guest) {
3093 if (!is_paging(vcpu)) {
3094 hw_cr4 &= ~X86_CR4_PAE;
3095 hw_cr4 |= X86_CR4_PSE;
3096 } else if (!(cr4 & X86_CR4_PAE)) {
3097 hw_cr4 &= ~X86_CR4_PAE;
3102 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3103 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3104 * to be manually disabled when guest switches to non-paging
3107 * If !enable_unrestricted_guest, the CPU is always running
3108 * with CR0.PG=1 and CR4 needs to be modified.
3109 * If enable_unrestricted_guest, the CPU automatically
3110 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3112 if (!is_paging(vcpu))
3113 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3116 vmcs_writel(CR4_READ_SHADOW, cr4);
3117 vmcs_writel(GUEST_CR4, hw_cr4);
3121 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3123 struct vcpu_vmx *vmx = to_vmx(vcpu);
3126 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3127 *var = vmx->rmode.segs[seg];
3128 if (seg == VCPU_SREG_TR
3129 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3131 var->base = vmx_read_guest_seg_base(vmx, seg);
3132 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3135 var->base = vmx_read_guest_seg_base(vmx, seg);
3136 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3137 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3138 ar = vmx_read_guest_seg_ar(vmx, seg);
3139 var->unusable = (ar >> 16) & 1;
3140 var->type = ar & 15;
3141 var->s = (ar >> 4) & 1;
3142 var->dpl = (ar >> 5) & 3;
3144 * Some userspaces do not preserve unusable property. Since usable
3145 * segment has to be present according to VMX spec we can use present
3146 * property to amend userspace bug by making unusable segment always
3147 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3148 * segment as unusable.
3150 var->present = !var->unusable;
3151 var->avl = (ar >> 12) & 1;
3152 var->l = (ar >> 13) & 1;
3153 var->db = (ar >> 14) & 1;
3154 var->g = (ar >> 15) & 1;
3157 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3159 struct kvm_segment s;
3161 if (to_vmx(vcpu)->rmode.vm86_active) {
3162 vmx_get_segment(vcpu, &s, seg);
3165 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3168 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3170 struct vcpu_vmx *vmx = to_vmx(vcpu);
3172 if (unlikely(vmx->rmode.vm86_active))
3175 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3176 return VMX_AR_DPL(ar);
3180 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3184 if (var->unusable || !var->present)
3187 ar = var->type & 15;
3188 ar |= (var->s & 1) << 4;
3189 ar |= (var->dpl & 3) << 5;
3190 ar |= (var->present & 1) << 7;
3191 ar |= (var->avl & 1) << 12;
3192 ar |= (var->l & 1) << 13;
3193 ar |= (var->db & 1) << 14;
3194 ar |= (var->g & 1) << 15;
3200 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3202 struct vcpu_vmx *vmx = to_vmx(vcpu);
3203 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3205 vmx_segment_cache_clear(vmx);
3207 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3208 vmx->rmode.segs[seg] = *var;
3209 if (seg == VCPU_SREG_TR)
3210 vmcs_write16(sf->selector, var->selector);
3212 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3216 vmcs_writel(sf->base, var->base);
3217 vmcs_write32(sf->limit, var->limit);
3218 vmcs_write16(sf->selector, var->selector);
3221 * Fix the "Accessed" bit in AR field of segment registers for older
3223 * IA32 arch specifies that at the time of processor reset the
3224 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3225 * is setting it to 0 in the userland code. This causes invalid guest
3226 * state vmexit when "unrestricted guest" mode is turned on.
3227 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3228 * tree. Newer qemu binaries with that qemu fix would not need this
3231 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3232 var->type |= 0x1; /* Accessed */
3234 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3237 vmx->emulation_required = emulation_required(vcpu);
3240 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3242 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3244 *db = (ar >> 14) & 1;
3245 *l = (ar >> 13) & 1;
3248 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3250 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3251 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3254 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3256 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3257 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3260 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3262 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3263 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3266 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3268 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3269 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3272 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3274 struct kvm_segment var;
3277 vmx_get_segment(vcpu, &var, seg);
3279 if (seg == VCPU_SREG_CS)
3281 ar = vmx_segment_access_rights(&var);
3283 if (var.base != (var.selector << 4))
3285 if (var.limit != 0xffff)
3293 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3295 struct kvm_segment cs;
3296 unsigned int cs_rpl;
3298 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3299 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3303 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3307 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3308 if (cs.dpl > cs_rpl)
3311 if (cs.dpl != cs_rpl)
3317 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3321 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3323 struct kvm_segment ss;
3324 unsigned int ss_rpl;
3326 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3327 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3331 if (ss.type != 3 && ss.type != 7)
3335 if (ss.dpl != ss_rpl) /* DPL != RPL */
3343 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3345 struct kvm_segment var;
3348 vmx_get_segment(vcpu, &var, seg);
3349 rpl = var.selector & SEGMENT_RPL_MASK;
3357 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3358 if (var.dpl < rpl) /* DPL < RPL */
3362 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3368 static bool tr_valid(struct kvm_vcpu *vcpu)
3370 struct kvm_segment tr;
3372 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3376 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3378 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3386 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3388 struct kvm_segment ldtr;
3390 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3394 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3404 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3406 struct kvm_segment cs, ss;
3408 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3409 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3411 return ((cs.selector & SEGMENT_RPL_MASK) ==
3412 (ss.selector & SEGMENT_RPL_MASK));
3416 * Check if guest state is valid. Returns true if valid, false if
3418 * We assume that registers are always usable
3420 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3422 if (enable_unrestricted_guest)
3425 /* real mode guest state checks */
3426 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3427 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3429 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3431 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3433 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3435 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3437 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3440 /* protected mode guest state checks */
3441 if (!cs_ss_rpl_check(vcpu))
3443 if (!code_segment_valid(vcpu))
3445 if (!stack_segment_valid(vcpu))
3447 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3449 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3451 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3453 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3455 if (!tr_valid(vcpu))
3457 if (!ldtr_valid(vcpu))
3461 * - Add checks on RIP
3462 * - Add checks on RFLAGS
3468 static int init_rmode_tss(struct kvm *kvm)
3474 idx = srcu_read_lock(&kvm->srcu);
3475 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3476 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3479 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3480 r = kvm_write_guest_page(kvm, fn++, &data,
3481 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3484 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3487 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3491 r = kvm_write_guest_page(kvm, fn, &data,
3492 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3495 srcu_read_unlock(&kvm->srcu, idx);
3499 static int init_rmode_identity_map(struct kvm *kvm)
3501 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3503 kvm_pfn_t identity_map_pfn;
3506 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3507 mutex_lock(&kvm->slots_lock);
3509 if (likely(kvm_vmx->ept_identity_pagetable_done))
3512 if (!kvm_vmx->ept_identity_map_addr)
3513 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3514 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3516 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3517 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3521 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3524 /* Set up identity-mapping pagetable for EPT in real mode */
3525 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3526 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3527 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3528 r = kvm_write_guest_page(kvm, identity_map_pfn,
3529 &tmp, i * sizeof(tmp), sizeof(tmp));
3533 kvm_vmx->ept_identity_pagetable_done = true;
3536 mutex_unlock(&kvm->slots_lock);
3540 static void seg_setup(int seg)
3542 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3545 vmcs_write16(sf->selector, 0);
3546 vmcs_writel(sf->base, 0);
3547 vmcs_write32(sf->limit, 0xffff);
3549 if (seg == VCPU_SREG_CS)
3550 ar |= 0x08; /* code segment */
3552 vmcs_write32(sf->ar_bytes, ar);
3555 static int alloc_apic_access_page(struct kvm *kvm)
3560 mutex_lock(&kvm->slots_lock);
3561 if (kvm->arch.apic_access_page_done)
3563 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3564 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3568 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3569 if (is_error_page(page)) {
3575 * Do not pin the page in memory, so that memory hot-unplug
3576 * is able to migrate it.
3579 kvm->arch.apic_access_page_done = true;
3581 mutex_unlock(&kvm->slots_lock);
3585 int allocate_vpid(void)
3591 spin_lock(&vmx_vpid_lock);
3592 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3593 if (vpid < VMX_NR_VPIDS)
3594 __set_bit(vpid, vmx_vpid_bitmap);
3597 spin_unlock(&vmx_vpid_lock);
3601 void free_vpid(int vpid)
3603 if (!enable_vpid || vpid == 0)
3605 spin_lock(&vmx_vpid_lock);
3606 __clear_bit(vpid, vmx_vpid_bitmap);
3607 spin_unlock(&vmx_vpid_lock);
3610 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3613 int f = sizeof(unsigned long);
3615 if (!cpu_has_vmx_msr_bitmap())
3618 if (static_branch_unlikely(&enable_evmcs))
3619 evmcs_touch_msr_bitmap();
3622 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3623 * have the write-low and read-high bitmap offsets the wrong way round.
3624 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3626 if (msr <= 0x1fff) {
3627 if (type & MSR_TYPE_R)
3629 __clear_bit(msr, msr_bitmap + 0x000 / f);
3631 if (type & MSR_TYPE_W)
3633 __clear_bit(msr, msr_bitmap + 0x800 / f);
3635 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3637 if (type & MSR_TYPE_R)
3639 __clear_bit(msr, msr_bitmap + 0x400 / f);
3641 if (type & MSR_TYPE_W)
3643 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3648 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3651 int f = sizeof(unsigned long);
3653 if (!cpu_has_vmx_msr_bitmap())
3656 if (static_branch_unlikely(&enable_evmcs))
3657 evmcs_touch_msr_bitmap();
3660 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3661 * have the write-low and read-high bitmap offsets the wrong way round.
3662 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3664 if (msr <= 0x1fff) {
3665 if (type & MSR_TYPE_R)
3667 __set_bit(msr, msr_bitmap + 0x000 / f);
3669 if (type & MSR_TYPE_W)
3671 __set_bit(msr, msr_bitmap + 0x800 / f);
3673 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3675 if (type & MSR_TYPE_R)
3677 __set_bit(msr, msr_bitmap + 0x400 / f);
3679 if (type & MSR_TYPE_W)
3681 __set_bit(msr, msr_bitmap + 0xc00 / f);
3686 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3687 u32 msr, int type, bool value)
3690 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3692 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3695 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3699 if (cpu_has_secondary_exec_ctrls() &&
3700 (secondary_exec_controls_get(to_vmx(vcpu)) &
3701 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3702 mode |= MSR_BITMAP_MODE_X2APIC;
3703 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3704 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3710 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3715 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3716 unsigned word = msr / BITS_PER_LONG;
3717 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3718 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3721 if (mode & MSR_BITMAP_MODE_X2APIC) {
3723 * TPR reads and writes can be virtualized even if virtual interrupt
3724 * delivery is not in use.
3726 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3727 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3728 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3729 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3730 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3735 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3737 struct vcpu_vmx *vmx = to_vmx(vcpu);
3738 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3739 u8 mode = vmx_msr_bitmap_mode(vcpu);
3740 u8 changed = mode ^ vmx->msr_bitmap_mode;
3745 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3746 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3748 vmx->msr_bitmap_mode = mode;
3751 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3753 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3754 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3757 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3759 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3761 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3763 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3765 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3766 vmx_set_intercept_for_msr(msr_bitmap,
3767 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3768 vmx_set_intercept_for_msr(msr_bitmap,
3769 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3773 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3775 struct vcpu_vmx *vmx = to_vmx(vcpu);
3780 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3781 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3782 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3785 rvi = vmx_get_rvi();
3787 vapic_page = vmx->nested.virtual_apic_map.hva;
3788 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3790 return ((rvi & 0xf0) > (vppr & 0xf0));
3793 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3797 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3799 if (vcpu->mode == IN_GUEST_MODE) {
3801 * The vector of interrupt to be delivered to vcpu had
3802 * been set in PIR before this function.
3804 * Following cases will be reached in this block, and
3805 * we always send a notification event in all cases as
3808 * Case 1: vcpu keeps in non-root mode. Sending a
3809 * notification event posts the interrupt to vcpu.
3811 * Case 2: vcpu exits to root mode and is still
3812 * runnable. PIR will be synced to vIRR before the
3813 * next vcpu entry. Sending a notification event in
3814 * this case has no effect, as vcpu is not in root
3817 * Case 3: vcpu exits to root mode and is blocked.
3818 * vcpu_block() has already synced PIR to vIRR and
3819 * never blocks vcpu if vIRR is not cleared. Therefore,
3820 * a blocked vcpu here does not wait for any requested
3821 * interrupts in PIR, and sending a notification event
3822 * which has no effect is safe here.
3825 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3832 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3835 struct vcpu_vmx *vmx = to_vmx(vcpu);
3837 if (is_guest_mode(vcpu) &&
3838 vector == vmx->nested.posted_intr_nv) {
3840 * If a posted intr is not recognized by hardware,
3841 * we will accomplish it in the next vmentry.
3843 vmx->nested.pi_pending = true;
3844 kvm_make_request(KVM_REQ_EVENT, vcpu);
3845 /* the PIR and ON have been set by L1. */
3846 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3847 kvm_vcpu_kick(vcpu);
3853 * Send interrupt to vcpu via posted interrupt way.
3854 * 1. If target vcpu is running(non-root mode), send posted interrupt
3855 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3856 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3857 * interrupt from PIR in next vmentry.
3859 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3861 struct vcpu_vmx *vmx = to_vmx(vcpu);
3864 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3868 if (!vcpu->arch.apicv_active)
3871 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3874 /* If a previous notification has sent the IPI, nothing to do. */
3875 if (pi_test_and_set_on(&vmx->pi_desc))
3878 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3879 kvm_vcpu_kick(vcpu);
3885 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3886 * will not change in the lifetime of the guest.
3887 * Note that host-state that does change is set elsewhere. E.g., host-state
3888 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3890 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3894 unsigned long cr0, cr3, cr4;
3897 WARN_ON(cr0 & X86_CR0_TS);
3898 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3901 * Save the most likely value for this task's CR3 in the VMCS.
3902 * We can't use __get_current_cr3_fast() because we're not atomic.
3905 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
3906 vmx->loaded_vmcs->host_state.cr3 = cr3;
3908 /* Save the most likely value for this task's CR4 in the VMCS. */
3909 cr4 = cr4_read_shadow();
3910 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
3911 vmx->loaded_vmcs->host_state.cr4 = cr4;
3913 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3914 #ifdef CONFIG_X86_64
3916 * Load null selectors, so we can avoid reloading them in
3917 * vmx_prepare_switch_to_host(), in case userspace uses
3918 * the null selectors too (the expected case).
3920 vmcs_write16(HOST_DS_SELECTOR, 0);
3921 vmcs_write16(HOST_ES_SELECTOR, 0);
3923 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3924 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3926 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3927 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3929 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
3931 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3933 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3934 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3935 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3936 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3938 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3939 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3940 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3943 if (cpu_has_load_ia32_efer())
3944 vmcs_write64(HOST_IA32_EFER, host_efer);
3947 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3949 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3951 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3952 if (is_guest_mode(&vmx->vcpu))
3953 vmx->vcpu.arch.cr4_guest_owned_bits &=
3954 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3955 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3958 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3960 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3962 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3963 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3966 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3968 if (!enable_preemption_timer)
3969 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3971 return pin_based_exec_ctrl;
3974 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3976 struct vcpu_vmx *vmx = to_vmx(vcpu);
3978 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3979 if (cpu_has_secondary_exec_ctrls()) {
3980 if (kvm_vcpu_apicv_active(vcpu))
3981 secondary_exec_controls_setbit(vmx,
3982 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3983 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3985 secondary_exec_controls_clearbit(vmx,
3986 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3987 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3990 if (cpu_has_vmx_msr_bitmap())
3991 vmx_update_msr_bitmap(vcpu);
3994 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3996 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3998 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3999 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4001 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4002 exec_control &= ~CPU_BASED_TPR_SHADOW;
4003 #ifdef CONFIG_X86_64
4004 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4005 CPU_BASED_CR8_LOAD_EXITING;
4009 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4010 CPU_BASED_CR3_LOAD_EXITING |
4011 CPU_BASED_INVLPG_EXITING;
4012 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4013 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4014 CPU_BASED_MONITOR_EXITING);
4015 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4016 exec_control &= ~CPU_BASED_HLT_EXITING;
4017 return exec_control;
4021 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4023 struct kvm_vcpu *vcpu = &vmx->vcpu;
4025 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4027 if (pt_mode == PT_MODE_SYSTEM)
4028 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4029 if (!cpu_need_virtualize_apic_accesses(vcpu))
4030 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4032 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4034 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4035 enable_unrestricted_guest = 0;
4037 if (!enable_unrestricted_guest)
4038 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4039 if (kvm_pause_in_guest(vmx->vcpu.kvm))
4040 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4041 if (!kvm_vcpu_apicv_active(vcpu))
4042 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4043 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4044 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4046 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4047 * in vmx_set_cr4. */
4048 exec_control &= ~SECONDARY_EXEC_DESC;
4050 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4052 We can NOT enable shadow_vmcs here because we don't have yet
4055 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4058 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4060 if (vmx_xsaves_supported()) {
4061 /* Exposing XSAVES only when XSAVE is exposed */
4062 bool xsaves_enabled =
4063 boot_cpu_has(X86_FEATURE_XSAVE) &&
4064 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4065 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4067 vcpu->arch.xsaves_enabled = xsaves_enabled;
4069 if (!xsaves_enabled)
4070 exec_control &= ~SECONDARY_EXEC_XSAVES;
4074 vmx->nested.msrs.secondary_ctls_high |=
4075 SECONDARY_EXEC_XSAVES;
4077 vmx->nested.msrs.secondary_ctls_high &=
4078 ~SECONDARY_EXEC_XSAVES;
4082 if (vmx_rdtscp_supported()) {
4083 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4084 if (!rdtscp_enabled)
4085 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4089 vmx->nested.msrs.secondary_ctls_high |=
4090 SECONDARY_EXEC_RDTSCP;
4092 vmx->nested.msrs.secondary_ctls_high &=
4093 ~SECONDARY_EXEC_RDTSCP;
4097 if (vmx_invpcid_supported()) {
4098 /* Exposing INVPCID only when PCID is exposed */
4099 bool invpcid_enabled =
4100 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4101 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4103 if (!invpcid_enabled) {
4104 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4105 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4109 if (invpcid_enabled)
4110 vmx->nested.msrs.secondary_ctls_high |=
4111 SECONDARY_EXEC_ENABLE_INVPCID;
4113 vmx->nested.msrs.secondary_ctls_high &=
4114 ~SECONDARY_EXEC_ENABLE_INVPCID;
4118 if (vmx_rdrand_supported()) {
4119 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4121 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4125 vmx->nested.msrs.secondary_ctls_high |=
4126 SECONDARY_EXEC_RDRAND_EXITING;
4128 vmx->nested.msrs.secondary_ctls_high &=
4129 ~SECONDARY_EXEC_RDRAND_EXITING;
4133 if (vmx_rdseed_supported()) {
4134 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4136 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4140 vmx->nested.msrs.secondary_ctls_high |=
4141 SECONDARY_EXEC_RDSEED_EXITING;
4143 vmx->nested.msrs.secondary_ctls_high &=
4144 ~SECONDARY_EXEC_RDSEED_EXITING;
4148 if (vmx_waitpkg_supported()) {
4149 bool waitpkg_enabled =
4150 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4152 if (!waitpkg_enabled)
4153 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4156 if (waitpkg_enabled)
4157 vmx->nested.msrs.secondary_ctls_high |=
4158 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4160 vmx->nested.msrs.secondary_ctls_high &=
4161 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4165 vmx->secondary_exec_control = exec_control;
4168 static void ept_set_mmio_spte_mask(void)
4171 * EPT Misconfigurations can be generated if the value of bits 2:0
4172 * of an EPT paging-structure entry is 110b (write/execute).
4174 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4175 VMX_EPT_MISCONFIG_WX_VALUE, 0);
4178 #define VMX_XSS_EXIT_BITMAP 0
4181 * Noting that the initialization of Guest-state Area of VMCS is in
4184 static void init_vmcs(struct vcpu_vmx *vmx)
4187 nested_vmx_set_vmcs_shadowing_bitmap();
4189 if (cpu_has_vmx_msr_bitmap())
4190 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4192 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4195 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4197 exec_controls_set(vmx, vmx_exec_control(vmx));
4199 if (cpu_has_secondary_exec_ctrls()) {
4200 vmx_compute_secondary_exec_control(vmx);
4201 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4204 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4205 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4206 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4207 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4208 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4210 vmcs_write16(GUEST_INTR_STATUS, 0);
4212 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4213 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4216 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4217 vmcs_write32(PLE_GAP, ple_gap);
4218 vmx->ple_window = ple_window;
4219 vmx->ple_window_dirty = true;
4222 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4223 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4224 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4226 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4227 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4228 vmx_set_constant_host_state(vmx);
4229 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4230 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4232 if (cpu_has_vmx_vmfunc())
4233 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4235 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4236 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4237 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4238 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4239 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4241 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4242 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4244 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4246 /* 22.2.1, 20.8.1 */
4247 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4249 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4250 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4252 set_cr4_guest_host_mask(vmx);
4255 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4257 if (vmx_xsaves_supported())
4258 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4261 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4262 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4265 if (cpu_has_vmx_encls_vmexit())
4266 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4268 if (pt_mode == PT_MODE_HOST_GUEST) {
4269 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4270 /* Bit[6~0] are forced to 1, writes are ignored. */
4271 vmx->pt_desc.guest.output_mask = 0x7F;
4272 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4276 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4278 struct vcpu_vmx *vmx = to_vmx(vcpu);
4279 struct msr_data apic_base_msr;
4282 vmx->rmode.vm86_active = 0;
4285 vmx->msr_ia32_umwait_control = 0;
4287 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4288 vmx->hv_deadline_tsc = -1;
4289 kvm_set_cr8(vcpu, 0);
4292 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4293 MSR_IA32_APICBASE_ENABLE;
4294 if (kvm_vcpu_is_reset_bsp(vcpu))
4295 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4296 apic_base_msr.host_initiated = true;
4297 kvm_set_apic_base(vcpu, &apic_base_msr);
4300 vmx_segment_cache_clear(vmx);
4302 seg_setup(VCPU_SREG_CS);
4303 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4304 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4306 seg_setup(VCPU_SREG_DS);
4307 seg_setup(VCPU_SREG_ES);
4308 seg_setup(VCPU_SREG_FS);
4309 seg_setup(VCPU_SREG_GS);
4310 seg_setup(VCPU_SREG_SS);
4312 vmcs_write16(GUEST_TR_SELECTOR, 0);
4313 vmcs_writel(GUEST_TR_BASE, 0);
4314 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4315 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4317 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4318 vmcs_writel(GUEST_LDTR_BASE, 0);
4319 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4320 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4323 vmcs_write32(GUEST_SYSENTER_CS, 0);
4324 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4325 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4326 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4329 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4330 kvm_rip_write(vcpu, 0xfff0);
4332 vmcs_writel(GUEST_GDTR_BASE, 0);
4333 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4335 vmcs_writel(GUEST_IDTR_BASE, 0);
4336 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4338 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4339 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4340 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4341 if (kvm_mpx_supported())
4342 vmcs_write64(GUEST_BNDCFGS, 0);
4346 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4348 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4349 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4350 if (cpu_need_tpr_shadow(vcpu))
4351 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4352 __pa(vcpu->arch.apic->regs));
4353 vmcs_write32(TPR_THRESHOLD, 0);
4356 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4358 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4359 vmx->vcpu.arch.cr0 = cr0;
4360 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4361 vmx_set_cr4(vcpu, 0);
4362 vmx_set_efer(vcpu, 0);
4364 update_exception_bitmap(vcpu);
4366 vpid_sync_context(vmx->vpid);
4368 vmx_clear_hlt(vcpu);
4371 static void enable_irq_window(struct kvm_vcpu *vcpu)
4373 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4376 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4379 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4380 enable_irq_window(vcpu);
4384 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4387 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4389 struct vcpu_vmx *vmx = to_vmx(vcpu);
4391 int irq = vcpu->arch.interrupt.nr;
4393 trace_kvm_inj_virq(irq);
4395 ++vcpu->stat.irq_injections;
4396 if (vmx->rmode.vm86_active) {
4398 if (vcpu->arch.interrupt.soft)
4399 inc_eip = vcpu->arch.event_exit_inst_len;
4400 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4403 intr = irq | INTR_INFO_VALID_MASK;
4404 if (vcpu->arch.interrupt.soft) {
4405 intr |= INTR_TYPE_SOFT_INTR;
4406 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4407 vmx->vcpu.arch.event_exit_inst_len);
4409 intr |= INTR_TYPE_EXT_INTR;
4410 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4412 vmx_clear_hlt(vcpu);
4415 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4417 struct vcpu_vmx *vmx = to_vmx(vcpu);
4421 * Tracking the NMI-blocked state in software is built upon
4422 * finding the next open IRQ window. This, in turn, depends on
4423 * well-behaving guests: They have to keep IRQs disabled at
4424 * least as long as the NMI handler runs. Otherwise we may
4425 * cause NMI nesting, maybe breaking the guest. But as this is
4426 * highly unlikely, we can live with the residual risk.
4428 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4429 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4432 ++vcpu->stat.nmi_injections;
4433 vmx->loaded_vmcs->nmi_known_unmasked = false;
4435 if (vmx->rmode.vm86_active) {
4436 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4440 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4441 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4443 vmx_clear_hlt(vcpu);
4446 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4448 struct vcpu_vmx *vmx = to_vmx(vcpu);
4452 return vmx->loaded_vmcs->soft_vnmi_blocked;
4453 if (vmx->loaded_vmcs->nmi_known_unmasked)
4455 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4456 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4460 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4462 struct vcpu_vmx *vmx = to_vmx(vcpu);
4465 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4466 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4467 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4470 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4472 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4473 GUEST_INTR_STATE_NMI);
4475 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4476 GUEST_INTR_STATE_NMI);
4480 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4482 if (to_vmx(vcpu)->nested.nested_run_pending)
4486 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4489 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4490 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4491 | GUEST_INTR_STATE_NMI));
4494 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4496 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4497 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4498 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4499 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4502 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4506 if (enable_unrestricted_guest)
4509 mutex_lock(&kvm->slots_lock);
4510 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4512 mutex_unlock(&kvm->slots_lock);
4516 to_kvm_vmx(kvm)->tss_addr = addr;
4517 return init_rmode_tss(kvm);
4520 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4522 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4526 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4531 * Update instruction length as we may reinject the exception
4532 * from user space while in guest debugging mode.
4534 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4535 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4536 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4540 if (vcpu->guest_debug &
4541 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4558 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4559 int vec, u32 err_code)
4562 * Instruction with address size override prefix opcode 0x67
4563 * Cause the #SS fault with 0 error code in VM86 mode.
4565 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4566 if (kvm_emulate_instruction(vcpu, 0)) {
4567 if (vcpu->arch.halt_request) {
4568 vcpu->arch.halt_request = 0;
4569 return kvm_vcpu_halt(vcpu);
4577 * Forward all other exceptions that are valid in real mode.
4578 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4579 * the required debugging infrastructure rework.
4581 kvm_queue_exception(vcpu, vec);
4586 * Trigger machine check on the host. We assume all the MSRs are already set up
4587 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4588 * We pass a fake environment to the machine check handler because we want
4589 * the guest to be always treated like user space, no matter what context
4590 * it used internally.
4592 static void kvm_machine_check(void)
4594 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4595 struct pt_regs regs = {
4596 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4597 .flags = X86_EFLAGS_IF,
4600 do_machine_check(®s, 0);
4604 static int handle_machine_check(struct kvm_vcpu *vcpu)
4606 /* handled by vmx_vcpu_run() */
4610 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4612 struct vcpu_vmx *vmx = to_vmx(vcpu);
4613 struct kvm_run *kvm_run = vcpu->run;
4614 u32 intr_info, ex_no, error_code;
4615 unsigned long cr2, rip, dr6;
4618 vect_info = vmx->idt_vectoring_info;
4619 intr_info = vmx->exit_intr_info;
4621 if (is_machine_check(intr_info) || is_nmi(intr_info))
4622 return 1; /* handled by handle_exception_nmi_irqoff() */
4624 if (is_invalid_opcode(intr_info))
4625 return handle_ud(vcpu);
4628 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4629 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4631 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4632 WARN_ON_ONCE(!enable_vmware_backdoor);
4635 * VMware backdoor emulation on #GP interception only handles
4636 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4637 * error code on #GP.
4640 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4643 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4647 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4648 * MMIO, it is better to report an internal error.
4649 * See the comments in vmx_handle_exit.
4651 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4652 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4653 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4654 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4655 vcpu->run->internal.ndata = 3;
4656 vcpu->run->internal.data[0] = vect_info;
4657 vcpu->run->internal.data[1] = intr_info;
4658 vcpu->run->internal.data[2] = error_code;
4662 if (is_page_fault(intr_info)) {
4663 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4664 /* EPT won't cause page fault directly */
4665 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4666 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4669 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4671 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4672 return handle_rmode_exception(vcpu, ex_no, error_code);
4676 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4679 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4680 if (!(vcpu->guest_debug &
4681 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4682 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4683 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4684 if (is_icebp(intr_info))
4685 WARN_ON(!skip_emulated_instruction(vcpu));
4687 kvm_queue_exception(vcpu, DB_VECTOR);
4690 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4691 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4695 * Update instruction length as we may reinject #BP from
4696 * user space while in guest debugging mode. Reading it for
4697 * #DB as well causes no harm, it is not used in that case.
4699 vmx->vcpu.arch.event_exit_inst_len =
4700 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4701 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4702 rip = kvm_rip_read(vcpu);
4703 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4704 kvm_run->debug.arch.exception = ex_no;
4707 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4708 kvm_run->ex.exception = ex_no;
4709 kvm_run->ex.error_code = error_code;
4715 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4717 ++vcpu->stat.irq_exits;
4721 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4723 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4724 vcpu->mmio_needed = 0;
4728 static int handle_io(struct kvm_vcpu *vcpu)
4730 unsigned long exit_qualification;
4731 int size, in, string;
4734 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4735 string = (exit_qualification & 16) != 0;
4737 ++vcpu->stat.io_exits;
4740 return kvm_emulate_instruction(vcpu, 0);
4742 port = exit_qualification >> 16;
4743 size = (exit_qualification & 7) + 1;
4744 in = (exit_qualification & 8) != 0;
4746 return kvm_fast_pio(vcpu, size, port, in);
4750 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4753 * Patch in the VMCALL instruction:
4755 hypercall[0] = 0x0f;
4756 hypercall[1] = 0x01;
4757 hypercall[2] = 0xc1;
4760 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4761 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4763 if (is_guest_mode(vcpu)) {
4764 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4765 unsigned long orig_val = val;
4768 * We get here when L2 changed cr0 in a way that did not change
4769 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4770 * but did change L0 shadowed bits. So we first calculate the
4771 * effective cr0 value that L1 would like to write into the
4772 * hardware. It consists of the L2-owned bits from the new
4773 * value combined with the L1-owned bits from L1's guest_cr0.
4775 val = (val & ~vmcs12->cr0_guest_host_mask) |
4776 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4778 if (!nested_guest_cr0_valid(vcpu, val))
4781 if (kvm_set_cr0(vcpu, val))
4783 vmcs_writel(CR0_READ_SHADOW, orig_val);
4786 if (to_vmx(vcpu)->nested.vmxon &&
4787 !nested_host_cr0_valid(vcpu, val))
4790 return kvm_set_cr0(vcpu, val);
4794 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4796 if (is_guest_mode(vcpu)) {
4797 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4798 unsigned long orig_val = val;
4800 /* analogously to handle_set_cr0 */
4801 val = (val & ~vmcs12->cr4_guest_host_mask) |
4802 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4803 if (kvm_set_cr4(vcpu, val))
4805 vmcs_writel(CR4_READ_SHADOW, orig_val);
4808 return kvm_set_cr4(vcpu, val);
4811 static int handle_desc(struct kvm_vcpu *vcpu)
4813 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4814 return kvm_emulate_instruction(vcpu, 0);
4817 static int handle_cr(struct kvm_vcpu *vcpu)
4819 unsigned long exit_qualification, val;
4825 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4826 cr = exit_qualification & 15;
4827 reg = (exit_qualification >> 8) & 15;
4828 switch ((exit_qualification >> 4) & 3) {
4829 case 0: /* mov to cr */
4830 val = kvm_register_readl(vcpu, reg);
4831 trace_kvm_cr_write(cr, val);
4834 err = handle_set_cr0(vcpu, val);
4835 return kvm_complete_insn_gp(vcpu, err);
4837 WARN_ON_ONCE(enable_unrestricted_guest);
4838 err = kvm_set_cr3(vcpu, val);
4839 return kvm_complete_insn_gp(vcpu, err);
4841 err = handle_set_cr4(vcpu, val);
4842 return kvm_complete_insn_gp(vcpu, err);
4844 u8 cr8_prev = kvm_get_cr8(vcpu);
4846 err = kvm_set_cr8(vcpu, cr8);
4847 ret = kvm_complete_insn_gp(vcpu, err);
4848 if (lapic_in_kernel(vcpu))
4850 if (cr8_prev <= cr8)
4853 * TODO: we might be squashing a
4854 * KVM_GUESTDBG_SINGLESTEP-triggered
4855 * KVM_EXIT_DEBUG here.
4857 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4863 WARN_ONCE(1, "Guest should always own CR0.TS");
4864 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4865 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4866 return kvm_skip_emulated_instruction(vcpu);
4867 case 1: /*mov from cr*/
4870 WARN_ON_ONCE(enable_unrestricted_guest);
4871 val = kvm_read_cr3(vcpu);
4872 kvm_register_write(vcpu, reg, val);
4873 trace_kvm_cr_read(cr, val);
4874 return kvm_skip_emulated_instruction(vcpu);
4876 val = kvm_get_cr8(vcpu);
4877 kvm_register_write(vcpu, reg, val);
4878 trace_kvm_cr_read(cr, val);
4879 return kvm_skip_emulated_instruction(vcpu);
4883 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4884 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4885 kvm_lmsw(vcpu, val);
4887 return kvm_skip_emulated_instruction(vcpu);
4891 vcpu->run->exit_reason = 0;
4892 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4893 (int)(exit_qualification >> 4) & 3, cr);
4897 static int handle_dr(struct kvm_vcpu *vcpu)
4899 unsigned long exit_qualification;
4902 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4903 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4905 /* First, if DR does not exist, trigger UD */
4906 if (!kvm_require_dr(vcpu, dr))
4909 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4910 if (!kvm_require_cpl(vcpu, 0))
4912 dr7 = vmcs_readl(GUEST_DR7);
4915 * As the vm-exit takes precedence over the debug trap, we
4916 * need to emulate the latter, either for the host or the
4917 * guest debugging itself.
4919 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4920 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4921 vcpu->run->debug.arch.dr7 = dr7;
4922 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4923 vcpu->run->debug.arch.exception = DB_VECTOR;
4924 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4927 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4928 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4929 kvm_queue_exception(vcpu, DB_VECTOR);
4934 if (vcpu->guest_debug == 0) {
4935 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4938 * No more DR vmexits; force a reload of the debug registers
4939 * and reenter on this instruction. The next vmexit will
4940 * retrieve the full state of the debug registers.
4942 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4946 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4947 if (exit_qualification & TYPE_MOV_FROM_DR) {
4950 if (kvm_get_dr(vcpu, dr, &val))
4952 kvm_register_write(vcpu, reg, val);
4954 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4957 return kvm_skip_emulated_instruction(vcpu);
4960 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4962 return vcpu->arch.dr6;
4965 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4969 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4971 get_debugreg(vcpu->arch.db[0], 0);
4972 get_debugreg(vcpu->arch.db[1], 1);
4973 get_debugreg(vcpu->arch.db[2], 2);
4974 get_debugreg(vcpu->arch.db[3], 3);
4975 get_debugreg(vcpu->arch.dr6, 6);
4976 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4978 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4979 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4982 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4984 vmcs_writel(GUEST_DR7, val);
4987 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4989 kvm_apic_update_ppr(vcpu);
4993 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4995 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4997 kvm_make_request(KVM_REQ_EVENT, vcpu);
4999 ++vcpu->stat.irq_window_exits;
5003 static int handle_vmcall(struct kvm_vcpu *vcpu)
5005 return kvm_emulate_hypercall(vcpu);
5008 static int handle_invd(struct kvm_vcpu *vcpu)
5010 return kvm_emulate_instruction(vcpu, 0);
5013 static int handle_invlpg(struct kvm_vcpu *vcpu)
5015 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5017 kvm_mmu_invlpg(vcpu, exit_qualification);
5018 return kvm_skip_emulated_instruction(vcpu);
5021 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5025 err = kvm_rdpmc(vcpu);
5026 return kvm_complete_insn_gp(vcpu, err);
5029 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5031 return kvm_emulate_wbinvd(vcpu);
5034 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5036 u64 new_bv = kvm_read_edx_eax(vcpu);
5037 u32 index = kvm_rcx_read(vcpu);
5039 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5040 return kvm_skip_emulated_instruction(vcpu);
5044 static int handle_apic_access(struct kvm_vcpu *vcpu)
5046 if (likely(fasteoi)) {
5047 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5048 int access_type, offset;
5050 access_type = exit_qualification & APIC_ACCESS_TYPE;
5051 offset = exit_qualification & APIC_ACCESS_OFFSET;
5053 * Sane guest uses MOV to write EOI, with written value
5054 * not cared. So make a short-circuit here by avoiding
5055 * heavy instruction emulation.
5057 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5058 (offset == APIC_EOI)) {
5059 kvm_lapic_set_eoi(vcpu);
5060 return kvm_skip_emulated_instruction(vcpu);
5063 return kvm_emulate_instruction(vcpu, 0);
5066 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5068 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5069 int vector = exit_qualification & 0xff;
5071 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5072 kvm_apic_set_eoi_accelerated(vcpu, vector);
5076 static int handle_apic_write(struct kvm_vcpu *vcpu)
5078 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5079 u32 offset = exit_qualification & 0xfff;
5081 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5082 kvm_apic_write_nodecode(vcpu, offset);
5086 static int handle_task_switch(struct kvm_vcpu *vcpu)
5088 struct vcpu_vmx *vmx = to_vmx(vcpu);
5089 unsigned long exit_qualification;
5090 bool has_error_code = false;
5093 int reason, type, idt_v, idt_index;
5095 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5096 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5097 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5099 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5101 reason = (u32)exit_qualification >> 30;
5102 if (reason == TASK_SWITCH_GATE && idt_v) {
5104 case INTR_TYPE_NMI_INTR:
5105 vcpu->arch.nmi_injected = false;
5106 vmx_set_nmi_mask(vcpu, true);
5108 case INTR_TYPE_EXT_INTR:
5109 case INTR_TYPE_SOFT_INTR:
5110 kvm_clear_interrupt_queue(vcpu);
5112 case INTR_TYPE_HARD_EXCEPTION:
5113 if (vmx->idt_vectoring_info &
5114 VECTORING_INFO_DELIVER_CODE_MASK) {
5115 has_error_code = true;
5117 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5120 case INTR_TYPE_SOFT_EXCEPTION:
5121 kvm_clear_exception_queue(vcpu);
5127 tss_selector = exit_qualification;
5129 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5130 type != INTR_TYPE_EXT_INTR &&
5131 type != INTR_TYPE_NMI_INTR))
5132 WARN_ON(!skip_emulated_instruction(vcpu));
5135 * TODO: What about debug traps on tss switch?
5136 * Are we supposed to inject them and update dr6?
5138 return kvm_task_switch(vcpu, tss_selector,
5139 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5140 reason, has_error_code, error_code);
5143 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5145 unsigned long exit_qualification;
5149 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5152 * EPT violation happened while executing iret from NMI,
5153 * "blocked by NMI" bit has to be set before next VM entry.
5154 * There are errata that may cause this bit to not be set:
5157 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5159 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5160 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5162 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5163 trace_kvm_page_fault(gpa, exit_qualification);
5165 /* Is it a read fault? */
5166 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5167 ? PFERR_USER_MASK : 0;
5168 /* Is it a write fault? */
5169 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5170 ? PFERR_WRITE_MASK : 0;
5171 /* Is it a fetch fault? */
5172 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5173 ? PFERR_FETCH_MASK : 0;
5174 /* ept page table entry is present? */
5175 error_code |= (exit_qualification &
5176 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5177 EPT_VIOLATION_EXECUTABLE))
5178 ? PFERR_PRESENT_MASK : 0;
5180 error_code |= (exit_qualification & 0x100) != 0 ?
5181 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5183 vcpu->arch.exit_qualification = exit_qualification;
5184 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5187 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5192 * A nested guest cannot optimize MMIO vmexits, because we have an
5193 * nGPA here instead of the required GPA.
5195 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5196 if (!is_guest_mode(vcpu) &&
5197 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5198 trace_kvm_fast_mmio(gpa);
5199 return kvm_skip_emulated_instruction(vcpu);
5202 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5205 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5207 WARN_ON_ONCE(!enable_vnmi);
5208 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5209 ++vcpu->stat.nmi_window_exits;
5210 kvm_make_request(KVM_REQ_EVENT, vcpu);
5215 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5217 struct vcpu_vmx *vmx = to_vmx(vcpu);
5218 bool intr_window_requested;
5219 unsigned count = 130;
5222 * We should never reach the point where we are emulating L2
5223 * due to invalid guest state as that means we incorrectly
5224 * allowed a nested VMEntry with an invalid vmcs12.
5226 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5228 intr_window_requested = exec_controls_get(vmx) &
5229 CPU_BASED_INTR_WINDOW_EXITING;
5231 while (vmx->emulation_required && count-- != 0) {
5232 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5233 return handle_interrupt_window(&vmx->vcpu);
5235 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5238 if (!kvm_emulate_instruction(vcpu, 0))
5241 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5242 vcpu->arch.exception.pending) {
5243 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5244 vcpu->run->internal.suberror =
5245 KVM_INTERNAL_ERROR_EMULATION;
5246 vcpu->run->internal.ndata = 0;
5250 if (vcpu->arch.halt_request) {
5251 vcpu->arch.halt_request = 0;
5252 return kvm_vcpu_halt(vcpu);
5256 * Note, return 1 and not 0, vcpu_run() is responsible for
5257 * morphing the pending signal into the proper return code.
5259 if (signal_pending(current))
5269 static void grow_ple_window(struct kvm_vcpu *vcpu)
5271 struct vcpu_vmx *vmx = to_vmx(vcpu);
5272 unsigned int old = vmx->ple_window;
5274 vmx->ple_window = __grow_ple_window(old, ple_window,
5278 if (vmx->ple_window != old) {
5279 vmx->ple_window_dirty = true;
5280 trace_kvm_ple_window_update(vcpu->vcpu_id,
5281 vmx->ple_window, old);
5285 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5287 struct vcpu_vmx *vmx = to_vmx(vcpu);
5288 unsigned int old = vmx->ple_window;
5290 vmx->ple_window = __shrink_ple_window(old, ple_window,
5294 if (vmx->ple_window != old) {
5295 vmx->ple_window_dirty = true;
5296 trace_kvm_ple_window_update(vcpu->vcpu_id,
5297 vmx->ple_window, old);
5302 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5304 static void wakeup_handler(void)
5306 struct kvm_vcpu *vcpu;
5307 int cpu = smp_processor_id();
5309 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5310 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5311 blocked_vcpu_list) {
5312 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5314 if (pi_test_on(pi_desc) == 1)
5315 kvm_vcpu_kick(vcpu);
5317 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5320 static void vmx_enable_tdp(void)
5322 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5323 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5324 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5325 0ull, VMX_EPT_EXECUTABLE_MASK,
5326 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5327 VMX_EPT_RWX_MASK, 0ull);
5329 ept_set_mmio_spte_mask();
5334 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5335 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5337 static int handle_pause(struct kvm_vcpu *vcpu)
5339 if (!kvm_pause_in_guest(vcpu->kvm))
5340 grow_ple_window(vcpu);
5343 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5344 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5345 * never set PAUSE_EXITING and just set PLE if supported,
5346 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5348 kvm_vcpu_on_spin(vcpu, true);
5349 return kvm_skip_emulated_instruction(vcpu);
5352 static int handle_nop(struct kvm_vcpu *vcpu)
5354 return kvm_skip_emulated_instruction(vcpu);
5357 static int handle_mwait(struct kvm_vcpu *vcpu)
5359 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5360 return handle_nop(vcpu);
5363 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5365 kvm_queue_exception(vcpu, UD_VECTOR);
5369 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5374 static int handle_monitor(struct kvm_vcpu *vcpu)
5376 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5377 return handle_nop(vcpu);
5380 static int handle_invpcid(struct kvm_vcpu *vcpu)
5382 u32 vmx_instruction_info;
5386 struct x86_exception e;
5388 unsigned long roots_to_free = 0;
5394 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5395 kvm_queue_exception(vcpu, UD_VECTOR);
5399 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5400 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5403 kvm_inject_gp(vcpu, 0);
5407 /* According to the Intel instruction reference, the memory operand
5408 * is read even if it isn't needed (e.g., for type==all)
5410 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5411 vmx_instruction_info, false,
5412 sizeof(operand), &gva))
5415 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5416 kvm_inject_page_fault(vcpu, &e);
5420 if (operand.pcid >> 12 != 0) {
5421 kvm_inject_gp(vcpu, 0);
5425 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5428 case INVPCID_TYPE_INDIV_ADDR:
5429 if ((!pcid_enabled && (operand.pcid != 0)) ||
5430 is_noncanonical_address(operand.gla, vcpu)) {
5431 kvm_inject_gp(vcpu, 0);
5434 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5435 return kvm_skip_emulated_instruction(vcpu);
5437 case INVPCID_TYPE_SINGLE_CTXT:
5438 if (!pcid_enabled && (operand.pcid != 0)) {
5439 kvm_inject_gp(vcpu, 0);
5443 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5444 kvm_mmu_sync_roots(vcpu);
5445 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5448 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5449 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5451 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5453 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5455 * If neither the current cr3 nor any of the prev_roots use the
5456 * given PCID, then nothing needs to be done here because a
5457 * resync will happen anyway before switching to any other CR3.
5460 return kvm_skip_emulated_instruction(vcpu);
5462 case INVPCID_TYPE_ALL_NON_GLOBAL:
5464 * Currently, KVM doesn't mark global entries in the shadow
5465 * page tables, so a non-global flush just degenerates to a
5466 * global flush. If needed, we could optimize this later by
5467 * keeping track of global entries in shadow page tables.
5471 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5472 kvm_mmu_unload(vcpu);
5473 return kvm_skip_emulated_instruction(vcpu);
5476 BUG(); /* We have already checked above that type <= 3 */
5480 static int handle_pml_full(struct kvm_vcpu *vcpu)
5482 unsigned long exit_qualification;
5484 trace_kvm_pml_full(vcpu->vcpu_id);
5486 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5489 * PML buffer FULL happened while executing iret from NMI,
5490 * "blocked by NMI" bit has to be set before next VM entry.
5492 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5494 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5495 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5496 GUEST_INTR_STATE_NMI);
5499 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5500 * here.., and there's no userspace involvement needed for PML.
5505 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5507 struct vcpu_vmx *vmx = to_vmx(vcpu);
5509 if (!vmx->req_immediate_exit &&
5510 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5511 kvm_lapic_expired_hv_timer(vcpu);
5517 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5518 * are overwritten by nested_vmx_setup() when nested=1.
5520 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5522 kvm_queue_exception(vcpu, UD_VECTOR);
5526 static int handle_encls(struct kvm_vcpu *vcpu)
5529 * SGX virtualization is not yet supported. There is no software
5530 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5531 * to prevent the guest from executing ENCLS.
5533 kvm_queue_exception(vcpu, UD_VECTOR);
5538 * The exit handlers return 1 if the exit was handled fully and guest execution
5539 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5540 * to be done to userspace and return 0.
5542 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5543 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5544 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5545 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5546 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5547 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5548 [EXIT_REASON_CR_ACCESS] = handle_cr,
5549 [EXIT_REASON_DR_ACCESS] = handle_dr,
5550 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5551 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5552 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
5553 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
5554 [EXIT_REASON_HLT] = kvm_emulate_halt,
5555 [EXIT_REASON_INVD] = handle_invd,
5556 [EXIT_REASON_INVLPG] = handle_invlpg,
5557 [EXIT_REASON_RDPMC] = handle_rdpmc,
5558 [EXIT_REASON_VMCALL] = handle_vmcall,
5559 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5560 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5561 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5562 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5563 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5564 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5565 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5566 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5567 [EXIT_REASON_VMON] = handle_vmx_instruction,
5568 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5569 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5570 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5571 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5572 [EXIT_REASON_WBINVD] = handle_wbinvd,
5573 [EXIT_REASON_XSETBV] = handle_xsetbv,
5574 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5575 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5576 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5577 [EXIT_REASON_LDTR_TR] = handle_desc,
5578 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5579 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5580 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5581 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5582 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5583 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5584 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5585 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5586 [EXIT_REASON_RDRAND] = handle_invalid_op,
5587 [EXIT_REASON_RDSEED] = handle_invalid_op,
5588 [EXIT_REASON_PML_FULL] = handle_pml_full,
5589 [EXIT_REASON_INVPCID] = handle_invpcid,
5590 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5591 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5592 [EXIT_REASON_ENCLS] = handle_encls,
5595 static const int kvm_vmx_max_exit_handlers =
5596 ARRAY_SIZE(kvm_vmx_exit_handlers);
5598 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5600 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5601 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5604 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5607 __free_page(vmx->pml_pg);
5612 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5614 struct vcpu_vmx *vmx = to_vmx(vcpu);
5618 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5620 /* Do nothing if PML buffer is empty */
5621 if (pml_idx == (PML_ENTITY_NUM - 1))
5624 /* PML index always points to next available PML buffer entity */
5625 if (pml_idx >= PML_ENTITY_NUM)
5630 pml_buf = page_address(vmx->pml_pg);
5631 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5634 gpa = pml_buf[pml_idx];
5635 WARN_ON(gpa & (PAGE_SIZE - 1));
5636 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5639 /* reset PML index */
5640 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5644 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5645 * Called before reporting dirty_bitmap to userspace.
5647 static void kvm_flush_pml_buffers(struct kvm *kvm)
5650 struct kvm_vcpu *vcpu;
5652 * We only need to kick vcpu out of guest mode here, as PML buffer
5653 * is flushed at beginning of all VMEXITs, and it's obvious that only
5654 * vcpus running in guest are possible to have unflushed GPAs in PML
5657 kvm_for_each_vcpu(i, vcpu, kvm)
5658 kvm_vcpu_kick(vcpu);
5661 static void vmx_dump_sel(char *name, uint32_t sel)
5663 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5664 name, vmcs_read16(sel),
5665 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5666 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5667 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5670 static void vmx_dump_dtsel(char *name, uint32_t limit)
5672 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5673 name, vmcs_read32(limit),
5674 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5677 void dump_vmcs(void)
5679 u32 vmentry_ctl, vmexit_ctl;
5680 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5685 if (!dump_invalid_vmcs) {
5686 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5690 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5691 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5692 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5693 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5694 cr4 = vmcs_readl(GUEST_CR4);
5695 efer = vmcs_read64(GUEST_IA32_EFER);
5696 secondary_exec_control = 0;
5697 if (cpu_has_secondary_exec_ctrls())
5698 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5700 pr_err("*** Guest State ***\n");
5701 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5702 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5703 vmcs_readl(CR0_GUEST_HOST_MASK));
5704 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5705 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5706 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5707 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5708 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5710 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5711 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5712 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5713 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5715 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5716 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5717 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5718 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5719 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5720 vmcs_readl(GUEST_SYSENTER_ESP),
5721 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5722 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5723 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5724 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5725 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5726 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5727 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5728 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5729 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5730 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5731 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5732 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5733 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5734 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5735 efer, vmcs_read64(GUEST_IA32_PAT));
5736 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5737 vmcs_read64(GUEST_IA32_DEBUGCTL),
5738 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5739 if (cpu_has_load_perf_global_ctrl() &&
5740 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5741 pr_err("PerfGlobCtl = 0x%016llx\n",
5742 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5743 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5744 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5745 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5746 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5747 vmcs_read32(GUEST_ACTIVITY_STATE));
5748 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5749 pr_err("InterruptStatus = %04x\n",
5750 vmcs_read16(GUEST_INTR_STATUS));
5752 pr_err("*** Host State ***\n");
5753 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5754 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5755 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5756 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5757 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5758 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5759 vmcs_read16(HOST_TR_SELECTOR));
5760 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5761 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5762 vmcs_readl(HOST_TR_BASE));
5763 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5764 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5765 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5766 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5767 vmcs_readl(HOST_CR4));
5768 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5769 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5770 vmcs_read32(HOST_IA32_SYSENTER_CS),
5771 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5772 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5773 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5774 vmcs_read64(HOST_IA32_EFER),
5775 vmcs_read64(HOST_IA32_PAT));
5776 if (cpu_has_load_perf_global_ctrl() &&
5777 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5778 pr_err("PerfGlobCtl = 0x%016llx\n",
5779 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5781 pr_err("*** Control State ***\n");
5782 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5783 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5784 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5785 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5786 vmcs_read32(EXCEPTION_BITMAP),
5787 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5788 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5789 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5790 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5791 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5792 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5793 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5794 vmcs_read32(VM_EXIT_INTR_INFO),
5795 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5796 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5797 pr_err(" reason=%08x qualification=%016lx\n",
5798 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5799 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5800 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5801 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5802 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5803 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5804 pr_err("TSC Multiplier = 0x%016llx\n",
5805 vmcs_read64(TSC_MULTIPLIER));
5806 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5807 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5808 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5809 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5811 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5812 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5813 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5814 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5816 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5817 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5818 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5819 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5820 n = vmcs_read32(CR3_TARGET_COUNT);
5821 for (i = 0; i + 1 < n; i += 4)
5822 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5823 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5824 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5826 pr_err("CR3 target%u=%016lx\n",
5827 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5828 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5829 pr_err("PLE Gap=%08x Window=%08x\n",
5830 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5831 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5832 pr_err("Virtual processor ID = 0x%04x\n",
5833 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5837 * The guest has exited. See if we can fix it or if we need userspace
5840 static int vmx_handle_exit(struct kvm_vcpu *vcpu,
5841 enum exit_fastpath_completion exit_fastpath)
5843 struct vcpu_vmx *vmx = to_vmx(vcpu);
5844 u32 exit_reason = vmx->exit_reason;
5845 u32 vectoring_info = vmx->idt_vectoring_info;
5847 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5850 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5851 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5852 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5853 * mode as if vcpus is in root mode, the PML buffer must has been
5857 vmx_flush_pml_buffer(vcpu);
5859 /* If guest state is invalid, start emulating */
5860 if (vmx->emulation_required)
5861 return handle_invalid_guest_state(vcpu);
5863 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5864 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5866 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5868 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5869 vcpu->run->fail_entry.hardware_entry_failure_reason
5874 if (unlikely(vmx->fail)) {
5876 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5877 vcpu->run->fail_entry.hardware_entry_failure_reason
5878 = vmcs_read32(VM_INSTRUCTION_ERROR);
5884 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5885 * delivery event since it indicates guest is accessing MMIO.
5886 * The vm-exit can be triggered again after return to guest that
5887 * will cause infinite loop.
5889 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5890 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5891 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5892 exit_reason != EXIT_REASON_PML_FULL &&
5893 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5894 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5895 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5896 vcpu->run->internal.ndata = 3;
5897 vcpu->run->internal.data[0] = vectoring_info;
5898 vcpu->run->internal.data[1] = exit_reason;
5899 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5900 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5901 vcpu->run->internal.ndata++;
5902 vcpu->run->internal.data[3] =
5903 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5908 if (unlikely(!enable_vnmi &&
5909 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5910 if (vmx_interrupt_allowed(vcpu)) {
5911 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5912 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5913 vcpu->arch.nmi_pending) {
5915 * This CPU don't support us in finding the end of an
5916 * NMI-blocked window if the guest runs with IRQs
5917 * disabled. So we pull the trigger after 1 s of
5918 * futile waiting, but inform the user about this.
5920 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5921 "state on VCPU %d after 1 s timeout\n",
5922 __func__, vcpu->vcpu_id);
5923 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5927 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5928 kvm_skip_emulated_instruction(vcpu);
5932 if (exit_reason >= kvm_vmx_max_exit_handlers)
5933 goto unexpected_vmexit;
5934 #ifdef CONFIG_RETPOLINE
5935 if (exit_reason == EXIT_REASON_MSR_WRITE)
5936 return kvm_emulate_wrmsr(vcpu);
5937 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5938 return handle_preemption_timer(vcpu);
5939 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
5940 return handle_interrupt_window(vcpu);
5941 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5942 return handle_external_interrupt(vcpu);
5943 else if (exit_reason == EXIT_REASON_HLT)
5944 return kvm_emulate_halt(vcpu);
5945 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5946 return handle_ept_misconfig(vcpu);
5949 exit_reason = array_index_nospec(exit_reason,
5950 kvm_vmx_max_exit_handlers);
5951 if (!kvm_vmx_exit_handlers[exit_reason])
5952 goto unexpected_vmexit;
5954 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5957 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
5959 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5960 vcpu->run->internal.suberror =
5961 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5962 vcpu->run->internal.ndata = 1;
5963 vcpu->run->internal.data[0] = exit_reason;
5968 * Software based L1D cache flush which is used when microcode providing
5969 * the cache control MSR is not loaded.
5971 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5972 * flush it is required to read in 64 KiB because the replacement algorithm
5973 * is not exactly LRU. This could be sized at runtime via topology
5974 * information but as all relevant affected CPUs have 32KiB L1D cache size
5975 * there is no point in doing so.
5977 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5979 int size = PAGE_SIZE << L1D_CACHE_ORDER;
5982 * This code is only executed when the the flush mode is 'cond' or
5985 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5989 * Clear the per-vcpu flush bit, it gets set again
5990 * either from vcpu_run() or from one of the unsafe
5993 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5994 vcpu->arch.l1tf_flush_l1d = false;
5997 * Clear the per-cpu flush bit, it gets set again from
5998 * the interrupt handlers.
6000 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6001 kvm_clear_cpu_l1tf_flush_l1d();
6007 vcpu->stat.l1d_flush++;
6009 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6010 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6015 /* First ensure the pages are in the TLB */
6016 "xorl %%eax, %%eax\n"
6017 ".Lpopulate_tlb:\n\t"
6018 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6019 "addl $4096, %%eax\n\t"
6020 "cmpl %%eax, %[size]\n\t"
6021 "jne .Lpopulate_tlb\n\t"
6022 "xorl %%eax, %%eax\n\t"
6024 /* Now fill the cache */
6025 "xorl %%eax, %%eax\n"
6027 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6028 "addl $64, %%eax\n\t"
6029 "cmpl %%eax, %[size]\n\t"
6030 "jne .Lfill_cache\n\t"
6032 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6034 : "eax", "ebx", "ecx", "edx");
6037 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6039 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6042 if (is_guest_mode(vcpu) &&
6043 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6046 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6047 if (is_guest_mode(vcpu))
6048 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6050 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6053 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6055 struct vcpu_vmx *vmx = to_vmx(vcpu);
6056 u32 sec_exec_control;
6058 if (!lapic_in_kernel(vcpu))
6061 if (!flexpriority_enabled &&
6062 !cpu_has_vmx_virtualize_x2apic_mode())
6065 /* Postpone execution until vmcs01 is the current VMCS. */
6066 if (is_guest_mode(vcpu)) {
6067 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6071 sec_exec_control = secondary_exec_controls_get(vmx);
6072 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6073 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6075 switch (kvm_get_apic_mode(vcpu)) {
6076 case LAPIC_MODE_INVALID:
6077 WARN_ONCE(true, "Invalid local APIC state");
6078 case LAPIC_MODE_DISABLED:
6080 case LAPIC_MODE_XAPIC:
6081 if (flexpriority_enabled) {
6083 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6084 vmx_flush_tlb(vcpu, true);
6087 case LAPIC_MODE_X2APIC:
6088 if (cpu_has_vmx_virtualize_x2apic_mode())
6090 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6093 secondary_exec_controls_set(vmx, sec_exec_control);
6095 vmx_update_msr_bitmap(vcpu);
6098 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6100 if (!is_guest_mode(vcpu)) {
6101 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6102 vmx_flush_tlb(vcpu, true);
6106 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6114 status = vmcs_read16(GUEST_INTR_STATUS);
6116 if (max_isr != old) {
6118 status |= max_isr << 8;
6119 vmcs_write16(GUEST_INTR_STATUS, status);
6123 static void vmx_set_rvi(int vector)
6131 status = vmcs_read16(GUEST_INTR_STATUS);
6132 old = (u8)status & 0xff;
6133 if ((u8)vector != old) {
6135 status |= (u8)vector;
6136 vmcs_write16(GUEST_INTR_STATUS, status);
6140 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6143 * When running L2, updating RVI is only relevant when
6144 * vmcs12 virtual-interrupt-delivery enabled.
6145 * However, it can be enabled only when L1 also
6146 * intercepts external-interrupts and in that case
6147 * we should not update vmcs02 RVI but instead intercept
6148 * interrupt. Therefore, do nothing when running L2.
6150 if (!is_guest_mode(vcpu))
6151 vmx_set_rvi(max_irr);
6154 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6156 struct vcpu_vmx *vmx = to_vmx(vcpu);
6158 bool max_irr_updated;
6160 WARN_ON(!vcpu->arch.apicv_active);
6161 if (pi_test_on(&vmx->pi_desc)) {
6162 pi_clear_on(&vmx->pi_desc);
6164 * IOMMU can write to PID.ON, so the barrier matters even on UP.
6165 * But on x86 this is just a compiler barrier anyway.
6167 smp_mb__after_atomic();
6169 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6172 * If we are running L2 and L1 has a new pending interrupt
6173 * which can be injected, we should re-evaluate
6174 * what should be done with this new L1 interrupt.
6175 * If L1 intercepts external-interrupts, we should
6176 * exit from L2 to L1. Otherwise, interrupt should be
6177 * delivered directly to L2.
6179 if (is_guest_mode(vcpu) && max_irr_updated) {
6180 if (nested_exit_on_intr(vcpu))
6181 kvm_vcpu_exiting_guest_mode(vcpu);
6183 kvm_make_request(KVM_REQ_EVENT, vcpu);
6186 max_irr = kvm_lapic_find_highest_irr(vcpu);
6188 vmx_hwapic_irr_update(vcpu, max_irr);
6192 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6194 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6196 return pi_test_on(pi_desc) ||
6197 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6200 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6202 if (!kvm_vcpu_apicv_active(vcpu))
6205 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6206 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6207 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6208 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6211 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6213 struct vcpu_vmx *vmx = to_vmx(vcpu);
6215 pi_clear_on(&vmx->pi_desc);
6216 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6219 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6221 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6223 /* if exit due to PF check for async PF */
6224 if (is_page_fault(vmx->exit_intr_info))
6225 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6227 /* Handle machine checks before interrupts are enabled */
6228 if (is_machine_check(vmx->exit_intr_info))
6229 kvm_machine_check();
6231 /* We need to handle NMIs before interrupts are enabled */
6232 if (is_nmi(vmx->exit_intr_info)) {
6233 kvm_before_interrupt(&vmx->vcpu);
6235 kvm_after_interrupt(&vmx->vcpu);
6239 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6241 unsigned int vector;
6242 unsigned long entry;
6243 #ifdef CONFIG_X86_64
6249 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6250 if (WARN_ONCE(!is_external_intr(intr_info),
6251 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6254 vector = intr_info & INTR_INFO_VECTOR_MASK;
6255 desc = (gate_desc *)host_idt_base + vector;
6256 entry = gate_offset(desc);
6258 kvm_before_interrupt(vcpu);
6261 #ifdef CONFIG_X86_64
6262 "mov %%" _ASM_SP ", %[sp]\n\t"
6263 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6268 __ASM_SIZE(push) " $%c[cs]\n\t"
6271 #ifdef CONFIG_X86_64
6276 THUNK_TARGET(entry),
6277 [ss]"i"(__KERNEL_DS),
6278 [cs]"i"(__KERNEL_CS)
6281 kvm_after_interrupt(vcpu);
6283 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6285 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6286 enum exit_fastpath_completion *exit_fastpath)
6288 struct vcpu_vmx *vmx = to_vmx(vcpu);
6290 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6291 handle_external_interrupt_irqoff(vcpu);
6292 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6293 handle_exception_nmi_irqoff(vmx);
6294 else if (!is_guest_mode(vcpu) &&
6295 vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6296 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
6299 static bool vmx_has_emulated_msr(int index)
6302 case MSR_IA32_SMBASE:
6304 * We cannot do SMM unless we can run the guest in big
6307 return enable_unrestricted_guest || emulate_invalid_guest_state;
6308 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6310 case MSR_AMD64_VIRT_SPEC_CTRL:
6311 /* This is AMD only. */
6318 static bool vmx_pt_supported(void)
6320 return pt_mode == PT_MODE_HOST_GUEST;
6323 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6328 bool idtv_info_valid;
6330 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6333 if (vmx->loaded_vmcs->nmi_known_unmasked)
6336 * Can't use vmx->exit_intr_info since we're not sure what
6337 * the exit reason is.
6339 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6340 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6341 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6343 * SDM 3: 27.7.1.2 (September 2008)
6344 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6345 * a guest IRET fault.
6346 * SDM 3: 23.2.2 (September 2008)
6347 * Bit 12 is undefined in any of the following cases:
6348 * If the VM exit sets the valid bit in the IDT-vectoring
6349 * information field.
6350 * If the VM exit is due to a double fault.
6352 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6353 vector != DF_VECTOR && !idtv_info_valid)
6354 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6355 GUEST_INTR_STATE_NMI);
6357 vmx->loaded_vmcs->nmi_known_unmasked =
6358 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6359 & GUEST_INTR_STATE_NMI);
6360 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6361 vmx->loaded_vmcs->vnmi_blocked_time +=
6362 ktime_to_ns(ktime_sub(ktime_get(),
6363 vmx->loaded_vmcs->entry_time));
6366 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6367 u32 idt_vectoring_info,
6368 int instr_len_field,
6369 int error_code_field)
6373 bool idtv_info_valid;
6375 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6377 vcpu->arch.nmi_injected = false;
6378 kvm_clear_exception_queue(vcpu);
6379 kvm_clear_interrupt_queue(vcpu);
6381 if (!idtv_info_valid)
6384 kvm_make_request(KVM_REQ_EVENT, vcpu);
6386 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6387 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6390 case INTR_TYPE_NMI_INTR:
6391 vcpu->arch.nmi_injected = true;
6393 * SDM 3: 27.7.1.2 (September 2008)
6394 * Clear bit "block by NMI" before VM entry if a NMI
6397 vmx_set_nmi_mask(vcpu, false);
6399 case INTR_TYPE_SOFT_EXCEPTION:
6400 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6402 case INTR_TYPE_HARD_EXCEPTION:
6403 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6404 u32 err = vmcs_read32(error_code_field);
6405 kvm_requeue_exception_e(vcpu, vector, err);
6407 kvm_requeue_exception(vcpu, vector);
6409 case INTR_TYPE_SOFT_INTR:
6410 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6412 case INTR_TYPE_EXT_INTR:
6413 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6420 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6422 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6423 VM_EXIT_INSTRUCTION_LEN,
6424 IDT_VECTORING_ERROR_CODE);
6427 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6429 __vmx_complete_interrupts(vcpu,
6430 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6431 VM_ENTRY_INSTRUCTION_LEN,
6432 VM_ENTRY_EXCEPTION_ERROR_CODE);
6434 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6437 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6440 struct perf_guest_switch_msr *msrs;
6442 msrs = perf_guest_get_msrs(&nr_msrs);
6447 for (i = 0; i < nr_msrs; i++)
6448 if (msrs[i].host == msrs[i].guest)
6449 clear_atomic_switch_msr(vmx, msrs[i].msr);
6451 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6452 msrs[i].host, false);
6455 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6457 u32 host_umwait_control;
6459 if (!vmx_has_waitpkg(vmx))
6462 host_umwait_control = get_umwait_control_msr();
6464 if (vmx->msr_ia32_umwait_control != host_umwait_control)
6465 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6466 vmx->msr_ia32_umwait_control,
6467 host_umwait_control, false);
6469 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6472 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6474 struct vcpu_vmx *vmx = to_vmx(vcpu);
6478 if (vmx->req_immediate_exit) {
6479 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6480 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6481 } else if (vmx->hv_deadline_tsc != -1) {
6483 if (vmx->hv_deadline_tsc > tscl)
6484 /* set_hv_timer ensures the delta fits in 32-bits */
6485 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6486 cpu_preemption_timer_multi);
6490 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6491 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6492 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6493 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6494 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6498 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6500 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6501 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6502 vmcs_writel(HOST_RSP, host_rsp);
6506 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6508 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6510 struct vcpu_vmx *vmx = to_vmx(vcpu);
6511 unsigned long cr3, cr4;
6513 /* Record the guest's net vcpu time for enforced NMI injections. */
6514 if (unlikely(!enable_vnmi &&
6515 vmx->loaded_vmcs->soft_vnmi_blocked))
6516 vmx->loaded_vmcs->entry_time = ktime_get();
6518 /* Don't enter VMX if guest state is invalid, let the exit handler
6519 start emulation until we arrive back to a valid state */
6520 if (vmx->emulation_required)
6523 if (vmx->ple_window_dirty) {
6524 vmx->ple_window_dirty = false;
6525 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6529 * We did this in prepare_switch_to_guest, because it needs to
6530 * be within srcu_read_lock.
6532 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6534 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6535 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6536 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6537 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6539 cr3 = __get_current_cr3_fast();
6540 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6541 vmcs_writel(HOST_CR3, cr3);
6542 vmx->loaded_vmcs->host_state.cr3 = cr3;
6545 cr4 = cr4_read_shadow();
6546 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6547 vmcs_writel(HOST_CR4, cr4);
6548 vmx->loaded_vmcs->host_state.cr4 = cr4;
6551 /* When single-stepping over STI and MOV SS, we must clear the
6552 * corresponding interruptibility bits in the guest state. Otherwise
6553 * vmentry fails as it then expects bit 14 (BS) in pending debug
6554 * exceptions being set, but that's not correct for the guest debugging
6556 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6557 vmx_set_interrupt_shadow(vcpu, 0);
6559 kvm_load_guest_xsave_state(vcpu);
6561 if (static_cpu_has(X86_FEATURE_PKU) &&
6562 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6563 vcpu->arch.pkru != vmx->host_pkru)
6564 __write_pkru(vcpu->arch.pkru);
6566 pt_guest_enter(vmx);
6568 atomic_switch_perf_msrs(vmx);
6569 atomic_switch_umwait_control_msr(vmx);
6571 if (enable_preemption_timer)
6572 vmx_update_hv_timer(vcpu);
6574 if (lapic_in_kernel(vcpu) &&
6575 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6576 kvm_wait_lapic_expire(vcpu);
6579 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6580 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6581 * is no need to worry about the conditional branch over the wrmsr
6582 * being speculatively taken.
6584 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6586 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6587 if (static_branch_unlikely(&vmx_l1d_should_flush))
6588 vmx_l1d_flush(vcpu);
6589 else if (static_branch_unlikely(&mds_user_clear))
6590 mds_clear_cpu_buffers();
6592 if (vcpu->arch.cr2 != read_cr2())
6593 write_cr2(vcpu->arch.cr2);
6595 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6596 vmx->loaded_vmcs->launched);
6598 vcpu->arch.cr2 = read_cr2();
6601 * We do not use IBRS in the kernel. If this vCPU has used the
6602 * SPEC_CTRL MSR it may have left it on; save the value and
6603 * turn it off. This is much more efficient than blindly adding
6604 * it to the atomic save/restore list. Especially as the former
6605 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6607 * For non-nested case:
6608 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6612 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6615 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6616 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6618 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6620 /* All fields are clean at this point */
6621 if (static_branch_unlikely(&enable_evmcs))
6622 current_evmcs->hv_clean_fields |=
6623 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6625 if (static_branch_unlikely(&enable_evmcs))
6626 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6628 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6629 if (vmx->host_debugctlmsr)
6630 update_debugctlmsr(vmx->host_debugctlmsr);
6632 #ifndef CONFIG_X86_64
6634 * The sysexit path does not restore ds/es, so we must set them to
6635 * a reasonable value ourselves.
6637 * We can't defer this to vmx_prepare_switch_to_host() since that
6638 * function may be executed in interrupt context, which saves and
6639 * restore segments around it, nullifying its effect.
6641 loadsegment(ds, __USER_DS);
6642 loadsegment(es, __USER_DS);
6645 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6646 | (1 << VCPU_EXREG_RFLAGS)
6647 | (1 << VCPU_EXREG_PDPTR)
6648 | (1 << VCPU_EXREG_SEGMENTS)
6649 | (1 << VCPU_EXREG_CR3));
6650 vcpu->arch.regs_dirty = 0;
6655 * eager fpu is enabled if PKEY is supported and CR4 is switched
6656 * back on host, so it is safe to read guest PKRU from current
6659 if (static_cpu_has(X86_FEATURE_PKU) &&
6660 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6661 vcpu->arch.pkru = rdpkru();
6662 if (vcpu->arch.pkru != vmx->host_pkru)
6663 __write_pkru(vmx->host_pkru);
6666 kvm_load_host_xsave_state(vcpu);
6668 vmx->nested.nested_run_pending = 0;
6669 vmx->idt_vectoring_info = 0;
6671 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6672 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6673 kvm_machine_check();
6675 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6678 vmx->loaded_vmcs->launched = 1;
6679 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6681 vmx_recover_nmi_blocking(vmx);
6682 vmx_complete_interrupts(vmx);
6685 static struct kvm *vmx_vm_alloc(void)
6687 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6688 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6690 return &kvm_vmx->kvm;
6693 static void vmx_vm_free(struct kvm *kvm)
6695 kfree(kvm->arch.hyperv.hv_pa_pg);
6696 vfree(to_kvm_vmx(kvm));
6699 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6701 struct vcpu_vmx *vmx = to_vmx(vcpu);
6704 vmx_destroy_pml_buffer(vmx);
6705 free_vpid(vmx->vpid);
6706 nested_vmx_free_vcpu(vcpu);
6707 free_loaded_vmcs(vmx->loaded_vmcs);
6710 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6712 struct vcpu_vmx *vmx;
6713 unsigned long *msr_bitmap;
6716 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6721 vmx->vpid = allocate_vpid();
6724 * If PML is turned on, failure on enabling PML just results in failure
6725 * of creating the vcpu, therefore we can simplify PML logic (by
6726 * avoiding dealing with cases, such as enabling PML partially on vcpus
6727 * for the guest), etc.
6730 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6735 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
6737 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6738 u32 index = vmx_msr_index[i];
6739 u32 data_low, data_high;
6742 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6744 if (wrmsr_safe(index, data_low, data_high) < 0)
6747 vmx->guest_msrs[j].index = i;
6748 vmx->guest_msrs[j].data = 0;
6750 case MSR_IA32_TSX_CTRL:
6752 * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6753 * let's avoid changing CPUID bits under the host
6756 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6759 vmx->guest_msrs[j].mask = -1ull;
6765 err = alloc_loaded_vmcs(&vmx->vmcs01);
6769 msr_bitmap = vmx->vmcs01.msr_bitmap;
6770 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6771 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6772 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6773 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6774 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6775 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6776 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6777 if (kvm_cstate_in_guest(vcpu->kvm)) {
6778 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6779 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6780 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6781 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6783 vmx->msr_bitmap_mode = 0;
6785 vmx->loaded_vmcs = &vmx->vmcs01;
6787 vmx_vcpu_load(vcpu, cpu);
6792 if (cpu_need_virtualize_apic_accesses(vcpu)) {
6793 err = alloc_apic_access_page(vcpu->kvm);
6798 if (enable_ept && !enable_unrestricted_guest) {
6799 err = init_rmode_identity_map(vcpu->kvm);
6805 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6806 vmx_capability.ept);
6808 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6810 vmx->nested.posted_intr_nv = -1;
6811 vmx->nested.current_vmptr = -1ull;
6813 vcpu->arch.microcode_version = 0x100000000ULL;
6814 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6817 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6818 * or POSTED_INTR_WAKEUP_VECTOR.
6820 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6821 vmx->pi_desc.sn = 1;
6823 vmx->ept_pointer = INVALID_PAGE;
6828 free_loaded_vmcs(vmx->loaded_vmcs);
6830 vmx_destroy_pml_buffer(vmx);
6832 free_vpid(vmx->vpid);
6836 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6837 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6839 static int vmx_vm_init(struct kvm *kvm)
6841 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6844 kvm->arch.pause_in_guest = true;
6846 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6847 switch (l1tf_mitigation) {
6848 case L1TF_MITIGATION_OFF:
6849 case L1TF_MITIGATION_FLUSH_NOWARN:
6850 /* 'I explicitly don't care' is set */
6852 case L1TF_MITIGATION_FLUSH:
6853 case L1TF_MITIGATION_FLUSH_NOSMT:
6854 case L1TF_MITIGATION_FULL:
6856 * Warn upon starting the first VM in a potentially
6857 * insecure environment.
6859 if (sched_smt_active())
6860 pr_warn_once(L1TF_MSG_SMT);
6861 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6862 pr_warn_once(L1TF_MSG_L1D);
6864 case L1TF_MITIGATION_FULL_FORCE:
6865 /* Flush is enforced */
6869 kvm_apicv_init(kvm, enable_apicv);
6873 static int __init vmx_check_processor_compat(void)
6875 struct vmcs_config vmcs_conf;
6876 struct vmx_capability vmx_cap;
6878 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6879 !this_cpu_has(X86_FEATURE_VMX)) {
6880 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6884 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6887 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6888 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6889 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6890 smp_processor_id());
6896 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6901 /* For VT-d and EPT combination
6902 * 1. MMIO: always map as UC
6904 * a. VT-d without snooping control feature: can't guarantee the
6905 * result, try to trust guest.
6906 * b. VT-d with snooping control feature: snooping control feature of
6907 * VT-d engine can guarantee the cache correctness. Just set it
6908 * to WB to keep consistent with host. So the same as item 3.
6909 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6910 * consistent with host MTRR
6913 cache = MTRR_TYPE_UNCACHABLE;
6917 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6918 ipat = VMX_EPT_IPAT_BIT;
6919 cache = MTRR_TYPE_WRBACK;
6923 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6924 ipat = VMX_EPT_IPAT_BIT;
6925 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6926 cache = MTRR_TYPE_WRBACK;
6928 cache = MTRR_TYPE_UNCACHABLE;
6932 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6935 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6938 static int vmx_get_lpage_level(void)
6940 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6941 return PT_DIRECTORY_LEVEL;
6943 /* For shadow and EPT supported 1GB page */
6944 return PT_PDPE_LEVEL;
6947 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6950 * These bits in the secondary execution controls field
6951 * are dynamic, the others are mostly based on the hypervisor
6952 * architecture and the guest's CPUID. Do not touch the
6956 SECONDARY_EXEC_SHADOW_VMCS |
6957 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6958 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6959 SECONDARY_EXEC_DESC;
6961 u32 new_ctl = vmx->secondary_exec_control;
6962 u32 cur_ctl = secondary_exec_controls_get(vmx);
6964 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6968 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6969 * (indicating "allowed-1") if they are supported in the guest's CPUID.
6971 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6973 struct vcpu_vmx *vmx = to_vmx(vcpu);
6974 struct kvm_cpuid_entry2 *entry;
6976 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6977 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6979 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6980 if (entry && (entry->_reg & (_cpuid_mask))) \
6981 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6984 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6985 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME));
6986 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME));
6987 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC));
6988 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE));
6989 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE));
6990 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE));
6991 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE));
6992 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE));
6993 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR));
6994 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
6995 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX));
6996 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX));
6997 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID));
6998 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE));
7000 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7001 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE));
7002 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP));
7003 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP));
7004 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU));
7005 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP));
7006 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57));
7008 #undef cr4_fixed1_update
7011 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7013 struct vcpu_vmx *vmx = to_vmx(vcpu);
7015 if (kvm_mpx_supported()) {
7016 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7019 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7020 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7022 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7023 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7028 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7030 struct vcpu_vmx *vmx = to_vmx(vcpu);
7031 struct kvm_cpuid_entry2 *best = NULL;
7034 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7035 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7038 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7039 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7040 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7041 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7044 /* Get the number of configurable Address Ranges for filtering */
7045 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7046 PT_CAP_num_address_ranges);
7048 /* Initialize and clear the no dependency bits */
7049 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7050 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7053 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7054 * will inject an #GP
7056 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7057 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7060 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7061 * PSBFreq can be set
7063 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7064 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7065 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7068 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7069 * MTCFreq can be set
7071 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7072 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7073 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7075 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7076 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7077 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7080 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7081 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7082 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7084 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7085 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7086 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7088 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7089 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7090 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7092 /* unmask address range configure area */
7093 for (i = 0; i < vmx->pt_desc.addr_range; i++)
7094 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7097 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7099 struct vcpu_vmx *vmx = to_vmx(vcpu);
7101 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7102 vcpu->arch.xsaves_enabled = false;
7104 if (cpu_has_secondary_exec_ctrls()) {
7105 vmx_compute_secondary_exec_control(vmx);
7106 vmcs_set_secondary_exec_control(vmx);
7109 if (nested_vmx_allowed(vcpu))
7110 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7111 FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7112 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7114 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7115 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7116 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7118 if (nested_vmx_allowed(vcpu)) {
7119 nested_vmx_cr_fixed1_bits_update(vcpu);
7120 nested_vmx_entry_exit_ctls_update(vcpu);
7123 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7124 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7125 update_intel_pt_cfg(vcpu);
7127 if (boot_cpu_has(X86_FEATURE_RTM)) {
7128 struct shared_msr_entry *msr;
7129 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7131 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7132 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7137 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7139 if (func == 1 && nested)
7140 entry->ecx |= feature_bit(VMX);
7143 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7145 to_vmx(vcpu)->req_immediate_exit = true;
7148 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7149 struct x86_instruction_info *info)
7151 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7152 unsigned short port;
7156 if (info->intercept == x86_intercept_in ||
7157 info->intercept == x86_intercept_ins) {
7158 port = info->src_val;
7159 size = info->dst_bytes;
7161 port = info->dst_val;
7162 size = info->src_bytes;
7166 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7167 * VM-exits depend on the 'unconditional IO exiting' VM-execution
7170 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7172 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7173 intercept = nested_cpu_has(vmcs12,
7174 CPU_BASED_UNCOND_IO_EXITING);
7176 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7178 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7181 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7182 struct x86_instruction_info *info,
7183 enum x86_intercept_stage stage)
7185 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7186 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7188 switch (info->intercept) {
7190 * RDPID causes #UD if disabled through secondary execution controls.
7191 * Because it is marked as EmulateOnUD, we need to intercept it here.
7193 case x86_intercept_rdtscp:
7194 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7195 ctxt->exception.vector = UD_VECTOR;
7196 ctxt->exception.error_code_valid = false;
7197 return X86EMUL_PROPAGATE_FAULT;
7201 case x86_intercept_in:
7202 case x86_intercept_ins:
7203 case x86_intercept_out:
7204 case x86_intercept_outs:
7205 return vmx_check_intercept_io(vcpu, info);
7207 /* TODO: check more intercepts... */
7212 return X86EMUL_UNHANDLEABLE;
7215 #ifdef CONFIG_X86_64
7216 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7217 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7218 u64 divisor, u64 *result)
7220 u64 low = a << shift, high = a >> (64 - shift);
7222 /* To avoid the overflow on divq */
7223 if (high >= divisor)
7226 /* Low hold the result, high hold rem which is discarded */
7227 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7228 "rm" (divisor), "0" (low), "1" (high));
7234 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7237 struct vcpu_vmx *vmx;
7238 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7239 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7241 if (kvm_mwait_in_guest(vcpu->kvm) ||
7242 kvm_can_post_timer_interrupt(vcpu))
7247 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7248 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7249 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7250 ktimer->timer_advance_ns);
7252 if (delta_tsc > lapic_timer_advance_cycles)
7253 delta_tsc -= lapic_timer_advance_cycles;
7257 /* Convert to host delta tsc if tsc scaling is enabled */
7258 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7259 delta_tsc && u64_shl_div_u64(delta_tsc,
7260 kvm_tsc_scaling_ratio_frac_bits,
7261 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7265 * If the delta tsc can't fit in the 32 bit after the multi shift,
7266 * we can't use the preemption timer.
7267 * It's possible that it fits on later vmentries, but checking
7268 * on every vmentry is costly so we just use an hrtimer.
7270 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7273 vmx->hv_deadline_tsc = tscl + delta_tsc;
7274 *expired = !delta_tsc;
7278 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7280 to_vmx(vcpu)->hv_deadline_tsc = -1;
7284 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7286 if (!kvm_pause_in_guest(vcpu->kvm))
7287 shrink_ple_window(vcpu);
7290 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7291 struct kvm_memory_slot *slot)
7293 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7294 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7297 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7298 struct kvm_memory_slot *slot)
7300 kvm_mmu_slot_set_dirty(kvm, slot);
7303 static void vmx_flush_log_dirty(struct kvm *kvm)
7305 kvm_flush_pml_buffers(kvm);
7308 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7310 struct vmcs12 *vmcs12;
7311 struct vcpu_vmx *vmx = to_vmx(vcpu);
7314 if (is_guest_mode(vcpu)) {
7315 WARN_ON_ONCE(vmx->nested.pml_full);
7318 * Check if PML is enabled for the nested guest.
7319 * Whether eptp bit 6 is set is already checked
7320 * as part of A/D emulation.
7322 vmcs12 = get_vmcs12(vcpu);
7323 if (!nested_cpu_has_pml(vmcs12))
7326 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7327 vmx->nested.pml_full = true;
7331 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7332 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7334 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7335 offset_in_page(dst), sizeof(gpa)))
7338 vmcs12->guest_pml_index--;
7344 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7345 struct kvm_memory_slot *memslot,
7346 gfn_t offset, unsigned long mask)
7348 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7351 static void __pi_post_block(struct kvm_vcpu *vcpu)
7353 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7354 struct pi_desc old, new;
7358 old.control = new.control = pi_desc->control;
7359 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7360 "Wakeup handler not enabled while the VCPU is blocked\n");
7362 dest = cpu_physical_id(vcpu->cpu);
7364 if (x2apic_enabled())
7367 new.ndst = (dest << 8) & 0xFF00;
7369 /* set 'NV' to 'notification vector' */
7370 new.nv = POSTED_INTR_VECTOR;
7371 } while (cmpxchg64(&pi_desc->control, old.control,
7372 new.control) != old.control);
7374 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7375 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7376 list_del(&vcpu->blocked_vcpu_list);
7377 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7378 vcpu->pre_pcpu = -1;
7383 * This routine does the following things for vCPU which is going
7384 * to be blocked if VT-d PI is enabled.
7385 * - Store the vCPU to the wakeup list, so when interrupts happen
7386 * we can find the right vCPU to wake up.
7387 * - Change the Posted-interrupt descriptor as below:
7388 * 'NDST' <-- vcpu->pre_pcpu
7389 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7390 * - If 'ON' is set during this process, which means at least one
7391 * interrupt is posted for this vCPU, we cannot block it, in
7392 * this case, return 1, otherwise, return 0.
7395 static int pi_pre_block(struct kvm_vcpu *vcpu)
7398 struct pi_desc old, new;
7399 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7401 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7402 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7403 !kvm_vcpu_apicv_active(vcpu))
7406 WARN_ON(irqs_disabled());
7407 local_irq_disable();
7408 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7409 vcpu->pre_pcpu = vcpu->cpu;
7410 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7411 list_add_tail(&vcpu->blocked_vcpu_list,
7412 &per_cpu(blocked_vcpu_on_cpu,
7414 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7418 old.control = new.control = pi_desc->control;
7420 WARN((pi_desc->sn == 1),
7421 "Warning: SN field of posted-interrupts "
7422 "is set before blocking\n");
7425 * Since vCPU can be preempted during this process,
7426 * vcpu->cpu could be different with pre_pcpu, we
7427 * need to set pre_pcpu as the destination of wakeup
7428 * notification event, then we can find the right vCPU
7429 * to wakeup in wakeup handler if interrupts happen
7430 * when the vCPU is in blocked state.
7432 dest = cpu_physical_id(vcpu->pre_pcpu);
7434 if (x2apic_enabled())
7437 new.ndst = (dest << 8) & 0xFF00;
7439 /* set 'NV' to 'wakeup vector' */
7440 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7441 } while (cmpxchg64(&pi_desc->control, old.control,
7442 new.control) != old.control);
7444 /* We should not block the vCPU if an interrupt is posted for it. */
7445 if (pi_test_on(pi_desc) == 1)
7446 __pi_post_block(vcpu);
7449 return (vcpu->pre_pcpu == -1);
7452 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7454 if (pi_pre_block(vcpu))
7457 if (kvm_lapic_hv_timer_in_use(vcpu))
7458 kvm_lapic_switch_to_sw_timer(vcpu);
7463 static void pi_post_block(struct kvm_vcpu *vcpu)
7465 if (vcpu->pre_pcpu == -1)
7468 WARN_ON(irqs_disabled());
7469 local_irq_disable();
7470 __pi_post_block(vcpu);
7474 static void vmx_post_block(struct kvm_vcpu *vcpu)
7476 if (kvm_x86_ops->set_hv_timer)
7477 kvm_lapic_switch_to_hv_timer(vcpu);
7479 pi_post_block(vcpu);
7483 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7486 * @host_irq: host irq of the interrupt
7487 * @guest_irq: gsi of the interrupt
7488 * @set: set or unset PI
7489 * returns 0 on success, < 0 on failure
7491 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7492 uint32_t guest_irq, bool set)
7494 struct kvm_kernel_irq_routing_entry *e;
7495 struct kvm_irq_routing_table *irq_rt;
7496 struct kvm_lapic_irq irq;
7497 struct kvm_vcpu *vcpu;
7498 struct vcpu_data vcpu_info;
7501 if (!kvm_arch_has_assigned_device(kvm) ||
7502 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7503 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7506 idx = srcu_read_lock(&kvm->irq_srcu);
7507 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7508 if (guest_irq >= irq_rt->nr_rt_entries ||
7509 hlist_empty(&irq_rt->map[guest_irq])) {
7510 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7511 guest_irq, irq_rt->nr_rt_entries);
7515 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7516 if (e->type != KVM_IRQ_ROUTING_MSI)
7519 * VT-d PI cannot support posting multicast/broadcast
7520 * interrupts to a vCPU, we still use interrupt remapping
7521 * for these kind of interrupts.
7523 * For lowest-priority interrupts, we only support
7524 * those with single CPU as the destination, e.g. user
7525 * configures the interrupts via /proc/irq or uses
7526 * irqbalance to make the interrupts single-CPU.
7528 * We will support full lowest-priority interrupt later.
7530 * In addition, we can only inject generic interrupts using
7531 * the PI mechanism, refuse to route others through it.
7534 kvm_set_msi_irq(kvm, e, &irq);
7535 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7536 !kvm_irq_is_postable(&irq)) {
7538 * Make sure the IRTE is in remapped mode if
7539 * we don't handle it in posted mode.
7541 ret = irq_set_vcpu_affinity(host_irq, NULL);
7544 "failed to back to remapped mode, irq: %u\n",
7552 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7553 vcpu_info.vector = irq.vector;
7555 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7556 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7559 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7561 ret = irq_set_vcpu_affinity(host_irq, NULL);
7564 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7572 srcu_read_unlock(&kvm->irq_srcu, idx);
7576 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7578 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7579 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7580 FEAT_CTL_LMCE_ENABLED;
7582 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7583 ~FEAT_CTL_LMCE_ENABLED;
7586 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7588 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7589 if (to_vmx(vcpu)->nested.nested_run_pending)
7594 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7596 struct vcpu_vmx *vmx = to_vmx(vcpu);
7598 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7599 if (vmx->nested.smm.guest_mode)
7600 nested_vmx_vmexit(vcpu, -1, 0, 0);
7602 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7603 vmx->nested.vmxon = false;
7604 vmx_clear_hlt(vcpu);
7608 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7610 struct vcpu_vmx *vmx = to_vmx(vcpu);
7613 if (vmx->nested.smm.vmxon) {
7614 vmx->nested.vmxon = true;
7615 vmx->nested.smm.vmxon = false;
7618 if (vmx->nested.smm.guest_mode) {
7619 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7623 vmx->nested.smm.guest_mode = false;
7628 static int enable_smi_window(struct kvm_vcpu *vcpu)
7633 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7638 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7640 return to_vmx(vcpu)->nested.vmxon;
7643 static __init int hardware_setup(void)
7645 unsigned long host_bndcfgs;
7649 rdmsrl_safe(MSR_EFER, &host_efer);
7652 host_idt_base = dt.address;
7654 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7655 kvm_define_shared_msr(i, vmx_msr_index[i]);
7657 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7660 if (boot_cpu_has(X86_FEATURE_NX))
7661 kvm_enable_efer_bits(EFER_NX);
7663 if (boot_cpu_has(X86_FEATURE_MPX)) {
7664 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7665 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7668 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7669 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7672 if (!cpu_has_vmx_ept() ||
7673 !cpu_has_vmx_ept_4levels() ||
7674 !cpu_has_vmx_ept_mt_wb() ||
7675 !cpu_has_vmx_invept_global())
7678 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7679 enable_ept_ad_bits = 0;
7681 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7682 enable_unrestricted_guest = 0;
7684 if (!cpu_has_vmx_flexpriority())
7685 flexpriority_enabled = 0;
7687 if (!cpu_has_virtual_nmis())
7691 * set_apic_access_page_addr() is used to reload apic access
7692 * page upon invalidation. No need to do anything if not
7693 * using the APIC_ACCESS_ADDR VMCS field.
7695 if (!flexpriority_enabled)
7696 kvm_x86_ops->set_apic_access_page_addr = NULL;
7698 if (!cpu_has_vmx_tpr_shadow())
7699 kvm_x86_ops->update_cr8_intercept = NULL;
7701 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7702 kvm_disable_largepages();
7704 #if IS_ENABLED(CONFIG_HYPERV)
7705 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7707 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7708 kvm_x86_ops->tlb_remote_flush_with_range =
7709 hv_remote_flush_tlb_with_range;
7713 if (!cpu_has_vmx_ple()) {
7716 ple_window_grow = 0;
7718 ple_window_shrink = 0;
7721 if (!cpu_has_vmx_apicv()) {
7723 kvm_x86_ops->sync_pir_to_irr = NULL;
7726 if (cpu_has_vmx_tsc_scaling()) {
7727 kvm_has_tsc_control = true;
7728 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7729 kvm_tsc_scaling_ratio_frac_bits = 48;
7732 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7740 * Only enable PML when hardware supports PML feature, and both EPT
7741 * and EPT A/D bit features are enabled -- PML depends on them to work.
7743 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7747 kvm_x86_ops->slot_enable_log_dirty = NULL;
7748 kvm_x86_ops->slot_disable_log_dirty = NULL;
7749 kvm_x86_ops->flush_log_dirty = NULL;
7750 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7753 if (!cpu_has_vmx_preemption_timer())
7754 enable_preemption_timer = false;
7756 if (enable_preemption_timer) {
7757 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7760 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7761 cpu_preemption_timer_multi =
7762 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7765 use_timer_freq = (u64)tsc_khz * 1000;
7766 use_timer_freq >>= cpu_preemption_timer_multi;
7769 * KVM "disables" the preemption timer by setting it to its max
7770 * value. Don't use the timer if it might cause spurious exits
7771 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7773 if (use_timer_freq > 0xffffffffu / 10)
7774 enable_preemption_timer = false;
7777 if (!enable_preemption_timer) {
7778 kvm_x86_ops->set_hv_timer = NULL;
7779 kvm_x86_ops->cancel_hv_timer = NULL;
7780 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7783 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7785 kvm_mce_cap_supported |= MCG_LMCE_P;
7787 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7789 if (!enable_ept || !cpu_has_vmx_intel_pt())
7790 pt_mode = PT_MODE_SYSTEM;
7793 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7794 vmx_capability.ept);
7796 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7801 r = alloc_kvm_area();
7803 nested_vmx_hardware_unsetup();
7807 static __exit void hardware_unsetup(void)
7810 nested_vmx_hardware_unsetup();
7815 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7817 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7818 BIT(APICV_INHIBIT_REASON_HYPERV);
7820 return supported & BIT(bit);
7823 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7824 .cpu_has_kvm_support = cpu_has_kvm_support,
7825 .disabled_by_bios = vmx_disabled_by_bios,
7826 .hardware_setup = hardware_setup,
7827 .hardware_unsetup = hardware_unsetup,
7828 .check_processor_compatibility = vmx_check_processor_compat,
7829 .hardware_enable = hardware_enable,
7830 .hardware_disable = hardware_disable,
7831 .cpu_has_accelerated_tpr = report_flexpriority,
7832 .has_emulated_msr = vmx_has_emulated_msr,
7834 .vm_init = vmx_vm_init,
7835 .vm_alloc = vmx_vm_alloc,
7836 .vm_free = vmx_vm_free,
7838 .vcpu_create = vmx_create_vcpu,
7839 .vcpu_free = vmx_free_vcpu,
7840 .vcpu_reset = vmx_vcpu_reset,
7842 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7843 .vcpu_load = vmx_vcpu_load,
7844 .vcpu_put = vmx_vcpu_put,
7846 .update_bp_intercept = update_exception_bitmap,
7847 .get_msr_feature = vmx_get_msr_feature,
7848 .get_msr = vmx_get_msr,
7849 .set_msr = vmx_set_msr,
7850 .get_segment_base = vmx_get_segment_base,
7851 .get_segment = vmx_get_segment,
7852 .set_segment = vmx_set_segment,
7853 .get_cpl = vmx_get_cpl,
7854 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7855 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7856 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7857 .set_cr0 = vmx_set_cr0,
7858 .set_cr3 = vmx_set_cr3,
7859 .set_cr4 = vmx_set_cr4,
7860 .set_efer = vmx_set_efer,
7861 .get_idt = vmx_get_idt,
7862 .set_idt = vmx_set_idt,
7863 .get_gdt = vmx_get_gdt,
7864 .set_gdt = vmx_set_gdt,
7865 .get_dr6 = vmx_get_dr6,
7866 .set_dr6 = vmx_set_dr6,
7867 .set_dr7 = vmx_set_dr7,
7868 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7869 .cache_reg = vmx_cache_reg,
7870 .get_rflags = vmx_get_rflags,
7871 .set_rflags = vmx_set_rflags,
7873 .tlb_flush = vmx_flush_tlb,
7874 .tlb_flush_gva = vmx_flush_tlb_gva,
7876 .run = vmx_vcpu_run,
7877 .handle_exit = vmx_handle_exit,
7878 .skip_emulated_instruction = vmx_skip_emulated_instruction,
7879 .update_emulated_instruction = vmx_update_emulated_instruction,
7880 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7881 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7882 .patch_hypercall = vmx_patch_hypercall,
7883 .set_irq = vmx_inject_irq,
7884 .set_nmi = vmx_inject_nmi,
7885 .queue_exception = vmx_queue_exception,
7886 .cancel_injection = vmx_cancel_injection,
7887 .interrupt_allowed = vmx_interrupt_allowed,
7888 .nmi_allowed = vmx_nmi_allowed,
7889 .get_nmi_mask = vmx_get_nmi_mask,
7890 .set_nmi_mask = vmx_set_nmi_mask,
7891 .enable_nmi_window = enable_nmi_window,
7892 .enable_irq_window = enable_irq_window,
7893 .update_cr8_intercept = update_cr8_intercept,
7894 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7895 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7896 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7897 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7898 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7899 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7900 .hwapic_irr_update = vmx_hwapic_irr_update,
7901 .hwapic_isr_update = vmx_hwapic_isr_update,
7902 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7903 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7904 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7905 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7907 .set_tss_addr = vmx_set_tss_addr,
7908 .set_identity_map_addr = vmx_set_identity_map_addr,
7909 .get_tdp_level = get_ept_level,
7910 .get_mt_mask = vmx_get_mt_mask,
7912 .get_exit_info = vmx_get_exit_info,
7914 .get_lpage_level = vmx_get_lpage_level,
7916 .cpuid_update = vmx_cpuid_update,
7918 .rdtscp_supported = vmx_rdtscp_supported,
7919 .invpcid_supported = vmx_invpcid_supported,
7921 .set_supported_cpuid = vmx_set_supported_cpuid,
7923 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7925 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7926 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7928 .set_tdp_cr3 = vmx_set_cr3,
7930 .check_intercept = vmx_check_intercept,
7931 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7932 .mpx_supported = vmx_mpx_supported,
7933 .xsaves_supported = vmx_xsaves_supported,
7934 .umip_emulated = vmx_umip_emulated,
7935 .pt_supported = vmx_pt_supported,
7936 .pku_supported = vmx_pku_supported,
7938 .request_immediate_exit = vmx_request_immediate_exit,
7940 .sched_in = vmx_sched_in,
7942 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7943 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7944 .flush_log_dirty = vmx_flush_log_dirty,
7945 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7946 .write_log_dirty = vmx_write_pml_buffer,
7948 .pre_block = vmx_pre_block,
7949 .post_block = vmx_post_block,
7951 .pmu_ops = &intel_pmu_ops,
7953 .update_pi_irte = vmx_update_pi_irte,
7955 #ifdef CONFIG_X86_64
7956 .set_hv_timer = vmx_set_hv_timer,
7957 .cancel_hv_timer = vmx_cancel_hv_timer,
7960 .setup_mce = vmx_setup_mce,
7962 .smi_allowed = vmx_smi_allowed,
7963 .pre_enter_smm = vmx_pre_enter_smm,
7964 .pre_leave_smm = vmx_pre_leave_smm,
7965 .enable_smi_window = enable_smi_window,
7967 .check_nested_events = NULL,
7968 .get_nested_state = NULL,
7969 .set_nested_state = NULL,
7970 .get_vmcs12_pages = NULL,
7971 .nested_enable_evmcs = NULL,
7972 .nested_get_evmcs_version = NULL,
7973 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7974 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7977 static void vmx_cleanup_l1d_flush(void)
7979 if (vmx_l1d_flush_pages) {
7980 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7981 vmx_l1d_flush_pages = NULL;
7983 /* Restore state so sysfs ignores VMX */
7984 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7987 static void vmx_exit(void)
7989 #ifdef CONFIG_KEXEC_CORE
7990 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7996 #if IS_ENABLED(CONFIG_HYPERV)
7997 if (static_branch_unlikely(&enable_evmcs)) {
7999 struct hv_vp_assist_page *vp_ap;
8001 * Reset everything to support using non-enlightened VMCS
8002 * access later (e.g. when we reload the module with
8003 * enlightened_vmcs=0)
8005 for_each_online_cpu(cpu) {
8006 vp_ap = hv_get_vp_assist_page(cpu);
8011 vp_ap->nested_control.features.directhypercall = 0;
8012 vp_ap->current_nested_vmcs = 0;
8013 vp_ap->enlighten_vmentry = 0;
8016 static_branch_disable(&enable_evmcs);
8019 vmx_cleanup_l1d_flush();
8021 module_exit(vmx_exit);
8023 static int __init vmx_init(void)
8027 #if IS_ENABLED(CONFIG_HYPERV)
8029 * Enlightened VMCS usage should be recommended and the host needs
8030 * to support eVMCS v1 or above. We can also disable eVMCS support
8031 * with module parameter.
8033 if (enlightened_vmcs &&
8034 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8035 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8036 KVM_EVMCS_VERSION) {
8039 /* Check that we have assist pages on all online CPUs */
8040 for_each_online_cpu(cpu) {
8041 if (!hv_get_vp_assist_page(cpu)) {
8042 enlightened_vmcs = false;
8047 if (enlightened_vmcs) {
8048 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8049 static_branch_enable(&enable_evmcs);
8052 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8053 vmx_x86_ops.enable_direct_tlbflush
8054 = hv_enable_direct_tlbflush;
8057 enlightened_vmcs = false;
8061 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8062 __alignof__(struct vcpu_vmx), THIS_MODULE);
8067 * Must be called after kvm_init() so enable_ept is properly set
8068 * up. Hand the parameter mitigation value in which was stored in
8069 * the pre module init parser. If no parameter was given, it will
8070 * contain 'auto' which will be turned into the default 'cond'
8073 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8079 #ifdef CONFIG_KEXEC_CORE
8080 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8081 crash_vmclear_local_loaded_vmcss);
8083 vmx_check_vmcs12_offsets();
8087 module_init(vmx_init);