1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/frame.h>
17 #include <linux/highmem.h>
18 #include <linux/hrtimer.h>
19 #include <linux/kernel.h>
20 #include <linux/kvm_host.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/mod_devicetable.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
30 #include <linux/entry-kvm.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/debugreg.h>
38 #include <asm/fpu/internal.h>
40 #include <asm/irq_remapping.h>
41 #include <asm/kexec.h>
42 #include <asm/perf_event.h>
44 #include <asm/mmu_context.h>
45 #include <asm/mshyperv.h>
46 #include <asm/mwait.h>
47 #include <asm/spec-ctrl.h>
48 #include <asm/virtext.h>
51 #include "capabilities.h"
55 #include "kvm_cache_regs.h"
67 MODULE_AUTHOR("Qumranet");
68 MODULE_LICENSE("GPL");
71 static const struct x86_cpu_id vmx_cpu_id[] = {
72 X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
75 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
78 bool __read_mostly enable_vpid = 1;
79 module_param_named(vpid, enable_vpid, bool, 0444);
81 static bool __read_mostly enable_vnmi = 1;
82 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
84 bool __read_mostly flexpriority_enabled = 1;
85 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
87 bool __read_mostly enable_ept = 1;
88 module_param_named(ept, enable_ept, bool, S_IRUGO);
90 bool __read_mostly enable_unrestricted_guest = 1;
91 module_param_named(unrestricted_guest,
92 enable_unrestricted_guest, bool, S_IRUGO);
94 bool __read_mostly enable_ept_ad_bits = 1;
95 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
97 static bool __read_mostly emulate_invalid_guest_state = true;
98 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
100 static bool __read_mostly fasteoi = 1;
101 module_param(fasteoi, bool, S_IRUGO);
103 bool __read_mostly enable_apicv = 1;
104 module_param(enable_apicv, bool, S_IRUGO);
107 * If nested=1, nested virtualization is supported, i.e., guests may use
108 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
109 * use VMX instructions.
111 static bool __read_mostly nested = 1;
112 module_param(nested, bool, S_IRUGO);
114 bool __read_mostly enable_pml = 1;
115 module_param_named(pml, enable_pml, bool, S_IRUGO);
117 static bool __read_mostly dump_invalid_vmcs = 0;
118 module_param(dump_invalid_vmcs, bool, 0644);
120 #define MSR_BITMAP_MODE_X2APIC 1
121 #define MSR_BITMAP_MODE_X2APIC_APICV 2
123 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
125 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
126 static int __read_mostly cpu_preemption_timer_multi;
127 static bool __read_mostly enable_preemption_timer = 1;
129 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
132 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
133 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
134 #define KVM_VM_CR0_ALWAYS_ON \
135 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
136 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
147 RTIT_STATUS_BYTECNT))
149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
153 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
154 * ple_gap: upper bound on the amount of time between two successive
155 * executions of PAUSE in a loop. Also indicate if ple enabled.
156 * According to test, this time is usually smaller than 128 cycles.
157 * ple_window: upper bound on the amount of time a guest is allowed to execute
158 * in a PAUSE loop. Tests indicate that most spinlocks are held for
159 * less than 2^12 cycles
160 * Time is measured based on a counter that runs at the same rate as the TSC,
161 * refer SDM volume 3b section 21.6.13 & 22.1.3.
163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
164 module_param(ple_gap, uint, 0444);
166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167 module_param(ple_window, uint, 0444);
169 /* Default doubles per-vcpu window every exit. */
170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
171 module_param(ple_window_grow, uint, 0444);
173 /* Default resets per-vcpu window every exit to ple_window. */
174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
175 module_param(ple_window_shrink, uint, 0444);
177 /* Default is to compute the maximum so we can never overflow. */
178 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179 module_param(ple_window_max, uint, 0444);
181 /* Default is SYSTEM mode, 1 for host-guest mode */
182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
183 module_param(pt_mode, int, S_IRUGO);
185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
189 /* Storage for pre module init parameter parsing */
190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
192 static const struct {
195 } vmentry_l1d_param[] = {
196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
198 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
204 #define L1D_CACHE_ORDER 4
205 static void *vmx_l1d_flush_pages;
207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
212 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
218 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
222 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
225 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
226 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
227 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
232 /* If set to auto use the default l1tf mitigation method */
233 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
234 switch (l1tf_mitigation) {
235 case L1TF_MITIGATION_OFF:
236 l1tf = VMENTER_L1D_FLUSH_NEVER;
238 case L1TF_MITIGATION_FLUSH_NOWARN:
239 case L1TF_MITIGATION_FLUSH:
240 case L1TF_MITIGATION_FLUSH_NOSMT:
241 l1tf = VMENTER_L1D_FLUSH_COND;
243 case L1TF_MITIGATION_FULL:
244 case L1TF_MITIGATION_FULL_FORCE:
245 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
248 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
249 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
252 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
253 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
255 * This allocation for vmx_l1d_flush_pages is not tied to a VM
256 * lifetime and so should not be charged to a memcg.
258 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
261 vmx_l1d_flush_pages = page_address(page);
264 * Initialize each page with a different pattern in
265 * order to protect against KSM in the nested
266 * virtualization case.
268 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
269 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
274 l1tf_vmx_mitigation = l1tf;
276 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
277 static_branch_enable(&vmx_l1d_should_flush);
279 static_branch_disable(&vmx_l1d_should_flush);
281 if (l1tf == VMENTER_L1D_FLUSH_COND)
282 static_branch_enable(&vmx_l1d_flush_cond);
284 static_branch_disable(&vmx_l1d_flush_cond);
288 static int vmentry_l1d_flush_parse(const char *s)
293 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
294 if (vmentry_l1d_param[i].for_parse &&
295 sysfs_streq(s, vmentry_l1d_param[i].option))
302 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
306 l1tf = vmentry_l1d_flush_parse(s);
310 if (!boot_cpu_has(X86_BUG_L1TF))
314 * Has vmx_init() run already? If not then this is the pre init
315 * parameter parsing. In that case just store the value and let
316 * vmx_init() do the proper setup after enable_ept has been
319 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
320 vmentry_l1d_flush_param = l1tf;
324 mutex_lock(&vmx_l1d_flush_mutex);
325 ret = vmx_setup_l1d_flush(l1tf);
326 mutex_unlock(&vmx_l1d_flush_mutex);
330 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
332 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
333 return sprintf(s, "???\n");
335 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
338 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
339 .set = vmentry_l1d_flush_set,
340 .get = vmentry_l1d_flush_get,
342 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
344 static bool guest_state_valid(struct kvm_vcpu *vcpu);
345 static u32 vmx_segment_access_rights(struct kvm_segment *var);
346 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
349 void vmx_vmexit(void);
351 #define vmx_insn_failed(fmt...) \
354 pr_warn_ratelimited(fmt); \
357 asmlinkage void vmread_error(unsigned long field, bool fault)
360 kvm_spurious_fault();
362 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
365 noinline void vmwrite_error(unsigned long field, unsigned long value)
367 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
368 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
371 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
373 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
376 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
378 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
381 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
383 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
387 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
389 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
393 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
394 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
396 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
397 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
399 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
402 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
403 * can find which vCPU should be waken up.
405 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
406 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
408 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
409 static DEFINE_SPINLOCK(vmx_vpid_lock);
411 struct vmcs_config vmcs_config;
412 struct vmx_capability vmx_capability;
414 #define VMX_SEGMENT_FIELD(seg) \
415 [VCPU_SREG_##seg] = { \
416 .selector = GUEST_##seg##_SELECTOR, \
417 .base = GUEST_##seg##_BASE, \
418 .limit = GUEST_##seg##_LIMIT, \
419 .ar_bytes = GUEST_##seg##_AR_BYTES, \
422 static const struct kvm_vmx_segment_field {
427 } kvm_vmx_segment_fields[] = {
428 VMX_SEGMENT_FIELD(CS),
429 VMX_SEGMENT_FIELD(DS),
430 VMX_SEGMENT_FIELD(ES),
431 VMX_SEGMENT_FIELD(FS),
432 VMX_SEGMENT_FIELD(GS),
433 VMX_SEGMENT_FIELD(SS),
434 VMX_SEGMENT_FIELD(TR),
435 VMX_SEGMENT_FIELD(LDTR),
438 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
440 vmx->segment_cache.bitmask = 0;
443 static unsigned long host_idt_base;
446 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
447 * will emulate SYSCALL in legacy mode if the vendor string in guest
448 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
449 * support this emulation, IA32_STAR must always be included in
450 * vmx_msr_index[], even in i386 builds.
452 const u32 vmx_msr_index[] = {
454 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
456 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
460 #if IS_ENABLED(CONFIG_HYPERV)
461 static bool __read_mostly enlightened_vmcs = true;
462 module_param(enlightened_vmcs, bool, 0444);
464 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
465 static void check_ept_pointer_match(struct kvm *kvm)
467 struct kvm_vcpu *vcpu;
468 u64 tmp_eptp = INVALID_PAGE;
471 kvm_for_each_vcpu(i, vcpu, kvm) {
472 if (!VALID_PAGE(tmp_eptp)) {
473 tmp_eptp = to_vmx(vcpu)->ept_pointer;
474 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
475 to_kvm_vmx(kvm)->ept_pointers_match
476 = EPT_POINTERS_MISMATCH;
481 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
484 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
487 struct kvm_tlb_range *range = data;
489 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
493 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
494 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
496 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
499 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
500 * of the base of EPT PML4 table, strip off EPT configuration
504 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
505 kvm_fill_hv_flush_list_func, (void *)range);
507 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
510 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
511 struct kvm_tlb_range *range)
513 struct kvm_vcpu *vcpu;
516 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
518 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
519 check_ept_pointer_match(kvm);
521 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
522 kvm_for_each_vcpu(i, vcpu, kvm) {
523 /* If ept_pointer is invalid pointer, bypass flush request. */
524 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
525 ret |= __hv_remote_flush_tlb_with_range(
529 ret = __hv_remote_flush_tlb_with_range(kvm,
530 kvm_get_vcpu(kvm, 0), range);
533 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
536 static int hv_remote_flush_tlb(struct kvm *kvm)
538 return hv_remote_flush_tlb_with_range(kvm, NULL);
541 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
543 struct hv_enlightened_vmcs *evmcs;
544 struct hv_partition_assist_pg **p_hv_pa_pg =
545 &vcpu->kvm->arch.hyperv.hv_pa_pg;
547 * Synthetic VM-Exit is not enabled in current code and so All
548 * evmcs in singe VM shares same assist page.
551 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
556 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
558 evmcs->partition_assist_page =
560 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
561 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
566 #endif /* IS_ENABLED(CONFIG_HYPERV) */
569 * Comment's format: document - errata name - stepping - processor name.
571 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
573 static u32 vmx_preemption_cpu_tfms[] = {
574 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
576 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
577 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
578 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
580 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
582 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
583 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
585 * 320767.pdf - AAP86 - B1 -
586 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
589 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
591 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
593 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
595 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
596 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
597 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
599 /* Xeon E3-1220 V2 */
603 static inline bool cpu_has_broken_vmx_preemption_timer(void)
605 u32 eax = cpuid_eax(0x00000001), i;
607 /* Clear the reserved bits */
608 eax &= ~(0x3U << 14 | 0xfU << 28);
609 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
610 if (eax == vmx_preemption_cpu_tfms[i])
616 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
618 return flexpriority_enabled && lapic_in_kernel(vcpu);
621 static inline bool report_flexpriority(void)
623 return flexpriority_enabled;
626 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
630 for (i = 0; i < vmx->nmsrs; ++i)
631 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
636 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
640 i = __find_msr_index(vmx, msr);
642 return &vmx->guest_msrs[i];
646 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
650 u64 old_msr_data = msr->data;
652 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
654 ret = kvm_set_shared_msr(msr->index, msr->data,
658 msr->data = old_msr_data;
663 #ifdef CONFIG_KEXEC_CORE
664 static void crash_vmclear_local_loaded_vmcss(void)
666 int cpu = raw_smp_processor_id();
667 struct loaded_vmcs *v;
669 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
670 loaded_vmcss_on_cpu_link)
673 #endif /* CONFIG_KEXEC_CORE */
675 static void __loaded_vmcs_clear(void *arg)
677 struct loaded_vmcs *loaded_vmcs = arg;
678 int cpu = raw_smp_processor_id();
680 if (loaded_vmcs->cpu != cpu)
681 return; /* vcpu migration can race with cpu offline */
682 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
683 per_cpu(current_vmcs, cpu) = NULL;
685 vmcs_clear(loaded_vmcs->vmcs);
686 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
687 vmcs_clear(loaded_vmcs->shadow_vmcs);
689 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
692 * Ensure all writes to loaded_vmcs, including deleting it from its
693 * current percpu list, complete before setting loaded_vmcs->vcpu to
694 * -1, otherwise a different cpu can see vcpu == -1 first and add
695 * loaded_vmcs to its percpu list before it's deleted from this cpu's
696 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
700 loaded_vmcs->cpu = -1;
701 loaded_vmcs->launched = 0;
704 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
706 int cpu = loaded_vmcs->cpu;
709 smp_call_function_single(cpu,
710 __loaded_vmcs_clear, loaded_vmcs, 1);
713 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
717 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
719 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
720 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
721 vmx->segment_cache.bitmask = 0;
723 ret = vmx->segment_cache.bitmask & mask;
724 vmx->segment_cache.bitmask |= mask;
728 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
730 u16 *p = &vmx->segment_cache.seg[seg].selector;
732 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
733 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
737 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
739 ulong *p = &vmx->segment_cache.seg[seg].base;
741 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
742 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
746 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
748 u32 *p = &vmx->segment_cache.seg[seg].limit;
750 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
751 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
755 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
757 u32 *p = &vmx->segment_cache.seg[seg].ar;
759 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
760 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
764 void update_exception_bitmap(struct kvm_vcpu *vcpu)
768 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
769 (1u << DB_VECTOR) | (1u << AC_VECTOR);
771 * Guest access to VMware backdoor ports could legitimately
772 * trigger #GP because of TSS I/O permission bitmap.
773 * We intercept those #GP and allow access to them anyway
776 if (enable_vmware_backdoor)
777 eb |= (1u << GP_VECTOR);
778 if ((vcpu->guest_debug &
779 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
780 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
781 eb |= 1u << BP_VECTOR;
782 if (to_vmx(vcpu)->rmode.vm86_active)
784 if (!vmx_need_pf_intercept(vcpu))
785 eb &= ~(1u << PF_VECTOR);
787 /* When we are running a nested L2 guest and L1 specified for it a
788 * certain exception bitmap, we must trap the same exceptions and pass
789 * them to L1. When running L2, we will only handle the exceptions
790 * specified above if L1 did not want them.
792 if (is_guest_mode(vcpu))
793 eb |= get_vmcs12(vcpu)->exception_bitmap;
795 vmcs_write32(EXCEPTION_BITMAP, eb);
799 * Check if MSR is intercepted for currently loaded MSR bitmap.
801 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
803 unsigned long *msr_bitmap;
804 int f = sizeof(unsigned long);
806 if (!cpu_has_vmx_msr_bitmap())
809 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
812 return !!test_bit(msr, msr_bitmap + 0x800 / f);
813 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
815 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
821 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
822 unsigned long entry, unsigned long exit)
824 vm_entry_controls_clearbit(vmx, entry);
825 vm_exit_controls_clearbit(vmx, exit);
828 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
832 for (i = 0; i < m->nr; ++i) {
833 if (m->val[i].index == msr)
839 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
842 struct msr_autoload *m = &vmx->msr_autoload;
846 if (cpu_has_load_ia32_efer()) {
847 clear_atomic_switch_msr_special(vmx,
848 VM_ENTRY_LOAD_IA32_EFER,
849 VM_EXIT_LOAD_IA32_EFER);
853 case MSR_CORE_PERF_GLOBAL_CTRL:
854 if (cpu_has_load_perf_global_ctrl()) {
855 clear_atomic_switch_msr_special(vmx,
856 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
857 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
862 i = vmx_find_msr_index(&m->guest, msr);
866 m->guest.val[i] = m->guest.val[m->guest.nr];
867 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
870 i = vmx_find_msr_index(&m->host, msr);
875 m->host.val[i] = m->host.val[m->host.nr];
876 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
879 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
880 unsigned long entry, unsigned long exit,
881 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
882 u64 guest_val, u64 host_val)
884 vmcs_write64(guest_val_vmcs, guest_val);
885 if (host_val_vmcs != HOST_IA32_EFER)
886 vmcs_write64(host_val_vmcs, host_val);
887 vm_entry_controls_setbit(vmx, entry);
888 vm_exit_controls_setbit(vmx, exit);
891 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
892 u64 guest_val, u64 host_val, bool entry_only)
895 struct msr_autoload *m = &vmx->msr_autoload;
899 if (cpu_has_load_ia32_efer()) {
900 add_atomic_switch_msr_special(vmx,
901 VM_ENTRY_LOAD_IA32_EFER,
902 VM_EXIT_LOAD_IA32_EFER,
905 guest_val, host_val);
909 case MSR_CORE_PERF_GLOBAL_CTRL:
910 if (cpu_has_load_perf_global_ctrl()) {
911 add_atomic_switch_msr_special(vmx,
912 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
913 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
914 GUEST_IA32_PERF_GLOBAL_CTRL,
915 HOST_IA32_PERF_GLOBAL_CTRL,
916 guest_val, host_val);
920 case MSR_IA32_PEBS_ENABLE:
921 /* PEBS needs a quiescent period after being disabled (to write
922 * a record). Disabling PEBS through VMX MSR swapping doesn't
923 * provide that period, so a CPU could write host's record into
926 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
929 i = vmx_find_msr_index(&m->guest, msr);
931 j = vmx_find_msr_index(&m->host, msr);
933 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
934 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) {
935 printk_once(KERN_WARNING "Not enough msr switch entries. "
936 "Can't add msr %x\n", msr);
941 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
943 m->guest.val[i].index = msr;
944 m->guest.val[i].value = guest_val;
951 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
953 m->host.val[j].index = msr;
954 m->host.val[j].value = host_val;
957 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
959 u64 guest_efer = vmx->vcpu.arch.efer;
962 /* Shadow paging assumes NX to be available. */
964 guest_efer |= EFER_NX;
967 * LMA and LME handled by hardware; SCE meaningless outside long mode.
969 ignore_bits |= EFER_SCE;
971 ignore_bits |= EFER_LMA | EFER_LME;
972 /* SCE is meaningful only in long mode on Intel */
973 if (guest_efer & EFER_LMA)
974 ignore_bits &= ~(u64)EFER_SCE;
978 * On EPT, we can't emulate NX, so we must switch EFER atomically.
979 * On CPUs that support "load IA32_EFER", always switch EFER
980 * atomically, since it's faster than switching it manually.
982 if (cpu_has_load_ia32_efer() ||
983 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
984 if (!(guest_efer & EFER_LMA))
985 guest_efer &= ~EFER_LME;
986 if (guest_efer != host_efer)
987 add_atomic_switch_msr(vmx, MSR_EFER,
988 guest_efer, host_efer, false);
990 clear_atomic_switch_msr(vmx, MSR_EFER);
993 clear_atomic_switch_msr(vmx, MSR_EFER);
995 guest_efer &= ~ignore_bits;
996 guest_efer |= host_efer & ignore_bits;
998 vmx->guest_msrs[efer_offset].data = guest_efer;
999 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1005 #ifdef CONFIG_X86_32
1007 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1008 * VMCS rather than the segment table. KVM uses this helper to figure
1009 * out the current bases to poke them into the VMCS before entry.
1011 static unsigned long segment_base(u16 selector)
1013 struct desc_struct *table;
1016 if (!(selector & ~SEGMENT_RPL_MASK))
1019 table = get_current_gdt_ro();
1021 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1022 u16 ldt_selector = kvm_read_ldt();
1024 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1027 table = (struct desc_struct *)segment_base(ldt_selector);
1029 v = get_desc_base(&table[selector >> 3]);
1034 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1036 return vmx_pt_mode_is_host_guest() &&
1037 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1040 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1044 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1045 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1046 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1047 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1048 for (i = 0; i < addr_range; i++) {
1049 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1050 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1054 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1058 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1059 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1060 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1061 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1062 for (i = 0; i < addr_range; i++) {
1063 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1064 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1068 static void pt_guest_enter(struct vcpu_vmx *vmx)
1070 if (vmx_pt_mode_is_system())
1074 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1075 * Save host state before VM entry.
1077 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1078 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1079 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1080 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1081 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1085 static void pt_guest_exit(struct vcpu_vmx *vmx)
1087 if (vmx_pt_mode_is_system())
1090 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1091 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1092 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1095 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1096 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1099 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1100 unsigned long fs_base, unsigned long gs_base)
1102 if (unlikely(fs_sel != host->fs_sel)) {
1104 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1106 vmcs_write16(HOST_FS_SELECTOR, 0);
1107 host->fs_sel = fs_sel;
1109 if (unlikely(gs_sel != host->gs_sel)) {
1111 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1113 vmcs_write16(HOST_GS_SELECTOR, 0);
1114 host->gs_sel = gs_sel;
1116 if (unlikely(fs_base != host->fs_base)) {
1117 vmcs_writel(HOST_FS_BASE, fs_base);
1118 host->fs_base = fs_base;
1120 if (unlikely(gs_base != host->gs_base)) {
1121 vmcs_writel(HOST_GS_BASE, gs_base);
1122 host->gs_base = gs_base;
1126 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1128 struct vcpu_vmx *vmx = to_vmx(vcpu);
1129 struct vmcs_host_state *host_state;
1130 #ifdef CONFIG_X86_64
1131 int cpu = raw_smp_processor_id();
1133 unsigned long fs_base, gs_base;
1137 vmx->req_immediate_exit = false;
1140 * Note that guest MSRs to be saved/restored can also be changed
1141 * when guest state is loaded. This happens when guest transitions
1142 * to/from long-mode by setting MSR_EFER.LMA.
1144 if (!vmx->guest_msrs_ready) {
1145 vmx->guest_msrs_ready = true;
1146 for (i = 0; i < vmx->save_nmsrs; ++i)
1147 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1148 vmx->guest_msrs[i].data,
1149 vmx->guest_msrs[i].mask);
1153 if (vmx->nested.need_vmcs12_to_shadow_sync)
1154 nested_sync_vmcs12_to_shadow(vcpu);
1156 if (vmx->guest_state_loaded)
1159 host_state = &vmx->loaded_vmcs->host_state;
1162 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1163 * allow segment selectors with cpl > 0 or ti == 1.
1165 host_state->ldt_sel = kvm_read_ldt();
1167 #ifdef CONFIG_X86_64
1168 savesegment(ds, host_state->ds_sel);
1169 savesegment(es, host_state->es_sel);
1171 gs_base = cpu_kernelmode_gs_base(cpu);
1172 if (likely(is_64bit_mm(current->mm))) {
1173 current_save_fsgs();
1174 fs_sel = current->thread.fsindex;
1175 gs_sel = current->thread.gsindex;
1176 fs_base = current->thread.fsbase;
1177 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1179 savesegment(fs, fs_sel);
1180 savesegment(gs, gs_sel);
1181 fs_base = read_msr(MSR_FS_BASE);
1182 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1185 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1187 savesegment(fs, fs_sel);
1188 savesegment(gs, gs_sel);
1189 fs_base = segment_base(fs_sel);
1190 gs_base = segment_base(gs_sel);
1193 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1194 vmx->guest_state_loaded = true;
1197 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1199 struct vmcs_host_state *host_state;
1201 if (!vmx->guest_state_loaded)
1204 host_state = &vmx->loaded_vmcs->host_state;
1206 ++vmx->vcpu.stat.host_state_reload;
1208 #ifdef CONFIG_X86_64
1209 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1211 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1212 kvm_load_ldt(host_state->ldt_sel);
1213 #ifdef CONFIG_X86_64
1214 load_gs_index(host_state->gs_sel);
1216 loadsegment(gs, host_state->gs_sel);
1219 if (host_state->fs_sel & 7)
1220 loadsegment(fs, host_state->fs_sel);
1221 #ifdef CONFIG_X86_64
1222 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1223 loadsegment(ds, host_state->ds_sel);
1224 loadsegment(es, host_state->es_sel);
1227 invalidate_tss_limit();
1228 #ifdef CONFIG_X86_64
1229 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1231 load_fixmap_gdt(raw_smp_processor_id());
1232 vmx->guest_state_loaded = false;
1233 vmx->guest_msrs_ready = false;
1236 #ifdef CONFIG_X86_64
1237 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1240 if (vmx->guest_state_loaded)
1241 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1243 return vmx->msr_guest_kernel_gs_base;
1246 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1249 if (vmx->guest_state_loaded)
1250 wrmsrl(MSR_KERNEL_GS_BASE, data);
1252 vmx->msr_guest_kernel_gs_base = data;
1256 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1258 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1259 struct pi_desc old, new;
1263 * In case of hot-plug or hot-unplug, we may have to undo
1264 * vmx_vcpu_pi_put even if there is no assigned device. And we
1265 * always keep PI.NDST up to date for simplicity: it makes the
1266 * code easier, and CPU migration is not a fast path.
1268 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1272 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1273 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1274 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1275 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1278 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1279 pi_clear_sn(pi_desc);
1280 goto after_clear_sn;
1283 /* The full case. */
1285 old.control = new.control = pi_desc->control;
1287 dest = cpu_physical_id(cpu);
1289 if (x2apic_enabled())
1292 new.ndst = (dest << 8) & 0xFF00;
1295 } while (cmpxchg64(&pi_desc->control, old.control,
1296 new.control) != old.control);
1301 * Clear SN before reading the bitmap. The VT-d firmware
1302 * writes the bitmap and reads SN atomically (5.2.3 in the
1303 * spec), so it doesn't really have a memory barrier that
1304 * pairs with this, but we cannot do that and we need one.
1306 smp_mb__after_atomic();
1308 if (!pi_is_pir_empty(pi_desc))
1312 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1313 struct loaded_vmcs *buddy)
1315 struct vcpu_vmx *vmx = to_vmx(vcpu);
1316 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1319 if (!already_loaded) {
1320 loaded_vmcs_clear(vmx->loaded_vmcs);
1321 local_irq_disable();
1324 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1325 * this cpu's percpu list, otherwise it may not yet be deleted
1326 * from its previous cpu's percpu list. Pairs with the
1327 * smb_wmb() in __loaded_vmcs_clear().
1331 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1332 &per_cpu(loaded_vmcss_on_cpu, cpu));
1336 prev = per_cpu(current_vmcs, cpu);
1337 if (prev != vmx->loaded_vmcs->vmcs) {
1338 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1339 vmcs_load(vmx->loaded_vmcs->vmcs);
1342 * No indirect branch prediction barrier needed when switching
1343 * the active VMCS within a guest, e.g. on nested VM-Enter.
1344 * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1346 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1347 indirect_branch_prediction_barrier();
1350 if (!already_loaded) {
1351 void *gdt = get_current_gdt_ro();
1352 unsigned long sysenter_esp;
1355 * Flush all EPTP/VPID contexts, the new pCPU may have stale
1356 * TLB entries from its previous association with the vCPU.
1358 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1361 * Linux uses per-cpu TSS and GDT, so set these when switching
1362 * processors. See 22.2.4.
1364 vmcs_writel(HOST_TR_BASE,
1365 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1366 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1368 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1369 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1371 vmx->loaded_vmcs->cpu = cpu;
1374 /* Setup TSC multiplier */
1375 if (kvm_has_tsc_control &&
1376 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1377 decache_tsc_multiplier(vmx);
1381 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1382 * vcpu mutex is already taken.
1384 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1386 struct vcpu_vmx *vmx = to_vmx(vcpu);
1388 vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1390 vmx_vcpu_pi_load(vcpu, cpu);
1392 vmx->host_debugctlmsr = get_debugctlmsr();
1395 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1397 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1399 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1400 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1401 !kvm_vcpu_apicv_active(vcpu))
1404 /* Set SN when the vCPU is preempted */
1405 if (vcpu->preempted)
1409 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1411 vmx_vcpu_pi_put(vcpu);
1413 vmx_prepare_switch_to_host(to_vmx(vcpu));
1416 static bool emulation_required(struct kvm_vcpu *vcpu)
1418 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1421 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1423 struct vcpu_vmx *vmx = to_vmx(vcpu);
1424 unsigned long rflags, save_rflags;
1426 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1427 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1428 rflags = vmcs_readl(GUEST_RFLAGS);
1429 if (vmx->rmode.vm86_active) {
1430 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1431 save_rflags = vmx->rmode.save_rflags;
1432 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1434 vmx->rflags = rflags;
1439 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1441 struct vcpu_vmx *vmx = to_vmx(vcpu);
1442 unsigned long old_rflags;
1444 if (is_unrestricted_guest(vcpu)) {
1445 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1446 vmx->rflags = rflags;
1447 vmcs_writel(GUEST_RFLAGS, rflags);
1451 old_rflags = vmx_get_rflags(vcpu);
1452 vmx->rflags = rflags;
1453 if (vmx->rmode.vm86_active) {
1454 vmx->rmode.save_rflags = rflags;
1455 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1457 vmcs_writel(GUEST_RFLAGS, rflags);
1459 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1460 vmx->emulation_required = emulation_required(vcpu);
1463 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1465 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1468 if (interruptibility & GUEST_INTR_STATE_STI)
1469 ret |= KVM_X86_SHADOW_INT_STI;
1470 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1471 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1476 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1478 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1479 u32 interruptibility = interruptibility_old;
1481 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1483 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1484 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1485 else if (mask & KVM_X86_SHADOW_INT_STI)
1486 interruptibility |= GUEST_INTR_STATE_STI;
1488 if ((interruptibility != interruptibility_old))
1489 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1492 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1494 struct vcpu_vmx *vmx = to_vmx(vcpu);
1495 unsigned long value;
1498 * Any MSR write that attempts to change bits marked reserved will
1501 if (data & vmx->pt_desc.ctl_bitmask)
1505 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1506 * result in a #GP unless the same write also clears TraceEn.
1508 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1509 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1513 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1514 * and FabricEn would cause #GP, if
1515 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1517 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1518 !(data & RTIT_CTL_FABRIC_EN) &&
1519 !intel_pt_validate_cap(vmx->pt_desc.caps,
1520 PT_CAP_single_range_output))
1524 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1525 * utilize encodings marked reserved will casue a #GP fault.
1527 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1528 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1529 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1530 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1532 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1533 PT_CAP_cycle_thresholds);
1534 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1535 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1536 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1538 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1539 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1540 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1541 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1545 * If ADDRx_CFG is reserved or the encodings is >2 will
1546 * cause a #GP fault.
1548 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1549 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1551 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1552 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1554 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1555 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1557 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1558 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1564 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1566 unsigned long rip, orig_rip;
1569 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1570 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1571 * set when EPT misconfig occurs. In practice, real hardware updates
1572 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1573 * (namely Hyper-V) don't set it due to it being undefined behavior,
1574 * i.e. we end up advancing IP with some random value.
1576 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1577 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1578 orig_rip = kvm_rip_read(vcpu);
1579 rip = orig_rip + vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1580 #ifdef CONFIG_X86_64
1582 * We need to mask out the high 32 bits of RIP if not in 64-bit
1583 * mode, but just finding out that we are in 64-bit mode is
1584 * quite expensive. Only do it if there was a carry.
1586 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1589 kvm_rip_write(vcpu, rip);
1591 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1595 /* skipping an emulated instruction also counts */
1596 vmx_set_interrupt_shadow(vcpu, 0);
1602 * Recognizes a pending MTF VM-exit and records the nested state for later
1605 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1607 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1608 struct vcpu_vmx *vmx = to_vmx(vcpu);
1610 if (!is_guest_mode(vcpu))
1614 * Per the SDM, MTF takes priority over debug-trap exceptions besides
1615 * T-bit traps. As instruction emulation is completed (i.e. at the
1616 * instruction boundary), any #DB exception pending delivery must be a
1617 * debug-trap. Record the pending MTF state to be delivered in
1618 * vmx_check_nested_events().
1620 if (nested_cpu_has_mtf(vmcs12) &&
1621 (!vcpu->arch.exception.pending ||
1622 vcpu->arch.exception.nr == DB_VECTOR))
1623 vmx->nested.mtf_pending = true;
1625 vmx->nested.mtf_pending = false;
1628 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1630 vmx_update_emulated_instruction(vcpu);
1631 return skip_emulated_instruction(vcpu);
1634 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1637 * Ensure that we clear the HLT state in the VMCS. We don't need to
1638 * explicitly skip the instruction because if the HLT state is set,
1639 * then the instruction is already executing and RIP has already been
1642 if (kvm_hlt_in_guest(vcpu->kvm) &&
1643 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1644 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1647 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1649 struct vcpu_vmx *vmx = to_vmx(vcpu);
1650 unsigned nr = vcpu->arch.exception.nr;
1651 bool has_error_code = vcpu->arch.exception.has_error_code;
1652 u32 error_code = vcpu->arch.exception.error_code;
1653 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1655 kvm_deliver_exception_payload(vcpu);
1657 if (has_error_code) {
1658 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1659 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1662 if (vmx->rmode.vm86_active) {
1664 if (kvm_exception_is_soft(nr))
1665 inc_eip = vcpu->arch.event_exit_inst_len;
1666 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1670 WARN_ON_ONCE(vmx->emulation_required);
1672 if (kvm_exception_is_soft(nr)) {
1673 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1674 vmx->vcpu.arch.event_exit_inst_len);
1675 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1677 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1679 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1681 vmx_clear_hlt(vcpu);
1685 * Swap MSR entry in host/guest MSR entry array.
1687 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1689 struct shared_msr_entry tmp;
1691 tmp = vmx->guest_msrs[to];
1692 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1693 vmx->guest_msrs[from] = tmp;
1697 * Set up the vmcs to automatically save and restore system
1698 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1699 * mode, as fiddling with msrs is very expensive.
1701 static void setup_msrs(struct vcpu_vmx *vmx)
1703 int save_nmsrs, index;
1706 #ifdef CONFIG_X86_64
1708 * The SYSCALL MSRs are only needed on long mode guests, and only
1709 * when EFER.SCE is set.
1711 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1712 index = __find_msr_index(vmx, MSR_STAR);
1714 move_msr_up(vmx, index, save_nmsrs++);
1715 index = __find_msr_index(vmx, MSR_LSTAR);
1717 move_msr_up(vmx, index, save_nmsrs++);
1718 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1720 move_msr_up(vmx, index, save_nmsrs++);
1723 index = __find_msr_index(vmx, MSR_EFER);
1724 if (index >= 0 && update_transition_efer(vmx, index))
1725 move_msr_up(vmx, index, save_nmsrs++);
1726 index = __find_msr_index(vmx, MSR_TSC_AUX);
1727 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1728 move_msr_up(vmx, index, save_nmsrs++);
1729 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1731 move_msr_up(vmx, index, save_nmsrs++);
1733 vmx->save_nmsrs = save_nmsrs;
1734 vmx->guest_msrs_ready = false;
1736 if (cpu_has_vmx_msr_bitmap())
1737 vmx_update_msr_bitmap(&vmx->vcpu);
1740 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1742 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1743 u64 g_tsc_offset = 0;
1746 * We're here if L1 chose not to trap WRMSR to TSC. According
1747 * to the spec, this should set L1's TSC; The offset that L1
1748 * set for L2 remains unchanged, and still needs to be added
1749 * to the newly set TSC to get L2's TSC.
1751 if (is_guest_mode(vcpu) &&
1752 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1753 g_tsc_offset = vmcs12->tsc_offset;
1755 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1756 vcpu->arch.tsc_offset - g_tsc_offset,
1758 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1759 return offset + g_tsc_offset;
1763 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1764 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1765 * all guests if the "nested" module option is off, and can also be disabled
1766 * for a single guest by disabling its VMX cpuid bit.
1768 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1770 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1773 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1776 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1778 return !(val & ~valid_bits);
1781 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1783 switch (msr->index) {
1784 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1787 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1788 case MSR_IA32_PERF_CAPABILITIES:
1789 msr->data = vmx_get_perf_capabilities();
1792 return KVM_MSR_RET_INVALID;
1797 * Reads an msr value (of 'msr_index') into 'pdata'.
1798 * Returns 0 on success, non-0 otherwise.
1799 * Assumes vcpu_load() was already called.
1801 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1803 struct vcpu_vmx *vmx = to_vmx(vcpu);
1804 struct shared_msr_entry *msr;
1807 switch (msr_info->index) {
1808 #ifdef CONFIG_X86_64
1810 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1813 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1815 case MSR_KERNEL_GS_BASE:
1816 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1820 return kvm_get_msr_common(vcpu, msr_info);
1821 case MSR_IA32_TSX_CTRL:
1822 if (!msr_info->host_initiated &&
1823 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1825 goto find_shared_msr;
1826 case MSR_IA32_UMWAIT_CONTROL:
1827 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1830 msr_info->data = vmx->msr_ia32_umwait_control;
1832 case MSR_IA32_SPEC_CTRL:
1833 if (!msr_info->host_initiated &&
1834 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1837 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1839 case MSR_IA32_SYSENTER_CS:
1840 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1842 case MSR_IA32_SYSENTER_EIP:
1843 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1845 case MSR_IA32_SYSENTER_ESP:
1846 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1848 case MSR_IA32_BNDCFGS:
1849 if (!kvm_mpx_supported() ||
1850 (!msr_info->host_initiated &&
1851 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1853 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1855 case MSR_IA32_MCG_EXT_CTL:
1856 if (!msr_info->host_initiated &&
1857 !(vmx->msr_ia32_feature_control &
1858 FEAT_CTL_LMCE_ENABLED))
1860 msr_info->data = vcpu->arch.mcg_ext_ctl;
1862 case MSR_IA32_FEAT_CTL:
1863 msr_info->data = vmx->msr_ia32_feature_control;
1865 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1866 if (!nested_vmx_allowed(vcpu))
1868 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1872 * Enlightened VMCS v1 doesn't have certain fields, but buggy
1873 * Hyper-V versions are still trying to use corresponding
1874 * features when they are exposed. Filter out the essential
1877 if (!msr_info->host_initiated &&
1878 vmx->nested.enlightened_vmcs_enabled)
1879 nested_evmcs_filter_control_msr(msr_info->index,
1882 case MSR_IA32_RTIT_CTL:
1883 if (!vmx_pt_mode_is_host_guest())
1885 msr_info->data = vmx->pt_desc.guest.ctl;
1887 case MSR_IA32_RTIT_STATUS:
1888 if (!vmx_pt_mode_is_host_guest())
1890 msr_info->data = vmx->pt_desc.guest.status;
1892 case MSR_IA32_RTIT_CR3_MATCH:
1893 if (!vmx_pt_mode_is_host_guest() ||
1894 !intel_pt_validate_cap(vmx->pt_desc.caps,
1895 PT_CAP_cr3_filtering))
1897 msr_info->data = vmx->pt_desc.guest.cr3_match;
1899 case MSR_IA32_RTIT_OUTPUT_BASE:
1900 if (!vmx_pt_mode_is_host_guest() ||
1901 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1902 PT_CAP_topa_output) &&
1903 !intel_pt_validate_cap(vmx->pt_desc.caps,
1904 PT_CAP_single_range_output)))
1906 msr_info->data = vmx->pt_desc.guest.output_base;
1908 case MSR_IA32_RTIT_OUTPUT_MASK:
1909 if (!vmx_pt_mode_is_host_guest() ||
1910 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1911 PT_CAP_topa_output) &&
1912 !intel_pt_validate_cap(vmx->pt_desc.caps,
1913 PT_CAP_single_range_output)))
1915 msr_info->data = vmx->pt_desc.guest.output_mask;
1917 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1918 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1919 if (!vmx_pt_mode_is_host_guest() ||
1920 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1921 PT_CAP_num_address_ranges)))
1924 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1926 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1929 if (!msr_info->host_initiated &&
1930 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1932 goto find_shared_msr;
1935 msr = find_msr_entry(vmx, msr_info->index);
1937 msr_info->data = msr->data;
1940 return kvm_get_msr_common(vcpu, msr_info);
1946 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1949 #ifdef CONFIG_X86_64
1950 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1953 return (unsigned long)data;
1957 * Writes msr value into the appropriate "register".
1958 * Returns 0 on success, non-0 otherwise.
1959 * Assumes vcpu_load() was already called.
1961 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1963 struct vcpu_vmx *vmx = to_vmx(vcpu);
1964 struct shared_msr_entry *msr;
1966 u32 msr_index = msr_info->index;
1967 u64 data = msr_info->data;
1970 switch (msr_index) {
1972 ret = kvm_set_msr_common(vcpu, msr_info);
1974 #ifdef CONFIG_X86_64
1976 vmx_segment_cache_clear(vmx);
1977 vmcs_writel(GUEST_FS_BASE, data);
1980 vmx_segment_cache_clear(vmx);
1981 vmcs_writel(GUEST_GS_BASE, data);
1983 case MSR_KERNEL_GS_BASE:
1984 vmx_write_guest_kernel_gs_base(vmx, data);
1987 case MSR_IA32_SYSENTER_CS:
1988 if (is_guest_mode(vcpu))
1989 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1990 vmcs_write32(GUEST_SYSENTER_CS, data);
1992 case MSR_IA32_SYSENTER_EIP:
1993 if (is_guest_mode(vcpu)) {
1994 data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1995 get_vmcs12(vcpu)->guest_sysenter_eip = data;
1997 vmcs_writel(GUEST_SYSENTER_EIP, data);
1999 case MSR_IA32_SYSENTER_ESP:
2000 if (is_guest_mode(vcpu)) {
2001 data = nested_vmx_truncate_sysenter_addr(vcpu, data);
2002 get_vmcs12(vcpu)->guest_sysenter_esp = data;
2004 vmcs_writel(GUEST_SYSENTER_ESP, data);
2006 case MSR_IA32_DEBUGCTLMSR:
2007 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
2008 VM_EXIT_SAVE_DEBUG_CONTROLS)
2009 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2011 ret = kvm_set_msr_common(vcpu, msr_info);
2014 case MSR_IA32_BNDCFGS:
2015 if (!kvm_mpx_supported() ||
2016 (!msr_info->host_initiated &&
2017 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2019 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2020 (data & MSR_IA32_BNDCFGS_RSVD))
2022 vmcs_write64(GUEST_BNDCFGS, data);
2024 case MSR_IA32_UMWAIT_CONTROL:
2025 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2028 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2029 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2032 vmx->msr_ia32_umwait_control = data;
2034 case MSR_IA32_SPEC_CTRL:
2035 if (!msr_info->host_initiated &&
2036 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2039 if (kvm_spec_ctrl_test_value(data))
2042 vmx->spec_ctrl = data;
2048 * When it's written (to non-zero) for the first time, pass
2052 * The handling of the MSR bitmap for L2 guests is done in
2053 * nested_vmx_prepare_msr_bitmap. We should not touch the
2054 * vmcs02.msr_bitmap here since it gets completely overwritten
2055 * in the merging. We update the vmcs01 here for L1 as well
2056 * since it will end up touching the MSR anyway now.
2058 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2062 case MSR_IA32_TSX_CTRL:
2063 if (!msr_info->host_initiated &&
2064 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2066 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2068 goto find_shared_msr;
2069 case MSR_IA32_PRED_CMD:
2070 if (!msr_info->host_initiated &&
2071 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2074 if (data & ~PRED_CMD_IBPB)
2076 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2081 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2085 * When it's written (to non-zero) for the first time, pass
2089 * The handling of the MSR bitmap for L2 guests is done in
2090 * nested_vmx_prepare_msr_bitmap. We should not touch the
2091 * vmcs02.msr_bitmap here since it gets completely overwritten
2094 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2097 case MSR_IA32_CR_PAT:
2098 if (!kvm_pat_valid(data))
2101 if (is_guest_mode(vcpu) &&
2102 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2103 get_vmcs12(vcpu)->guest_ia32_pat = data;
2105 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2106 vmcs_write64(GUEST_IA32_PAT, data);
2107 vcpu->arch.pat = data;
2110 ret = kvm_set_msr_common(vcpu, msr_info);
2112 case MSR_IA32_TSC_ADJUST:
2113 ret = kvm_set_msr_common(vcpu, msr_info);
2115 case MSR_IA32_MCG_EXT_CTL:
2116 if ((!msr_info->host_initiated &&
2117 !(to_vmx(vcpu)->msr_ia32_feature_control &
2118 FEAT_CTL_LMCE_ENABLED)) ||
2119 (data & ~MCG_EXT_CTL_LMCE_EN))
2121 vcpu->arch.mcg_ext_ctl = data;
2123 case MSR_IA32_FEAT_CTL:
2124 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2125 (to_vmx(vcpu)->msr_ia32_feature_control &
2126 FEAT_CTL_LOCKED && !msr_info->host_initiated))
2128 vmx->msr_ia32_feature_control = data;
2129 if (msr_info->host_initiated && data == 0)
2130 vmx_leave_nested(vcpu);
2132 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2133 if (!msr_info->host_initiated)
2134 return 1; /* they are read-only */
2135 if (!nested_vmx_allowed(vcpu))
2137 return vmx_set_vmx_msr(vcpu, msr_index, data);
2138 case MSR_IA32_RTIT_CTL:
2139 if (!vmx_pt_mode_is_host_guest() ||
2140 vmx_rtit_ctl_check(vcpu, data) ||
2143 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2144 vmx->pt_desc.guest.ctl = data;
2145 pt_update_intercept_for_msr(vmx);
2147 case MSR_IA32_RTIT_STATUS:
2148 if (!pt_can_write_msr(vmx))
2150 if (data & MSR_IA32_RTIT_STATUS_MASK)
2152 vmx->pt_desc.guest.status = data;
2154 case MSR_IA32_RTIT_CR3_MATCH:
2155 if (!pt_can_write_msr(vmx))
2157 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2158 PT_CAP_cr3_filtering))
2160 vmx->pt_desc.guest.cr3_match = data;
2162 case MSR_IA32_RTIT_OUTPUT_BASE:
2163 if (!pt_can_write_msr(vmx))
2165 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2166 PT_CAP_topa_output) &&
2167 !intel_pt_validate_cap(vmx->pt_desc.caps,
2168 PT_CAP_single_range_output))
2170 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
2172 vmx->pt_desc.guest.output_base = data;
2174 case MSR_IA32_RTIT_OUTPUT_MASK:
2175 if (!pt_can_write_msr(vmx))
2177 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2178 PT_CAP_topa_output) &&
2179 !intel_pt_validate_cap(vmx->pt_desc.caps,
2180 PT_CAP_single_range_output))
2182 vmx->pt_desc.guest.output_mask = data;
2184 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2185 if (!pt_can_write_msr(vmx))
2187 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2188 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2189 PT_CAP_num_address_ranges))
2191 if (is_noncanonical_address(data, vcpu))
2194 vmx->pt_desc.guest.addr_b[index / 2] = data;
2196 vmx->pt_desc.guest.addr_a[index / 2] = data;
2199 if (!msr_info->host_initiated &&
2200 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2202 /* Check reserved bit, higher 32 bits should be zero */
2203 if ((data >> 32) != 0)
2205 goto find_shared_msr;
2209 msr = find_msr_entry(vmx, msr_index);
2211 ret = vmx_set_guest_msr(vmx, msr, data);
2213 ret = kvm_set_msr_common(vcpu, msr_info);
2219 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2221 unsigned long guest_owned_bits;
2223 kvm_register_mark_available(vcpu, reg);
2227 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2230 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2232 case VCPU_EXREG_PDPTR:
2234 ept_save_pdptrs(vcpu);
2236 case VCPU_EXREG_CR0:
2237 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2239 vcpu->arch.cr0 &= ~guest_owned_bits;
2240 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2242 case VCPU_EXREG_CR3:
2243 if (is_unrestricted_guest(vcpu) ||
2244 (enable_ept && is_paging(vcpu)))
2245 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2247 case VCPU_EXREG_CR4:
2248 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2250 vcpu->arch.cr4 &= ~guest_owned_bits;
2251 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2259 static __init int cpu_has_kvm_support(void)
2261 return cpu_has_vmx();
2264 static __init int vmx_disabled_by_bios(void)
2266 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2267 !boot_cpu_has(X86_FEATURE_VMX);
2270 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2274 cr4_set_bits(X86_CR4_VMXE);
2275 intel_pt_handle_vmx(1);
2277 asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2278 _ASM_EXTABLE(1b, %l[fault])
2279 : : [vmxon_pointer] "m"(vmxon_pointer)
2284 WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2285 rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2286 intel_pt_handle_vmx(0);
2287 cr4_clear_bits(X86_CR4_VMXE);
2292 static int hardware_enable(void)
2294 int cpu = raw_smp_processor_id();
2295 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2298 if (cr4_read_shadow() & X86_CR4_VMXE)
2302 * This can happen if we hot-added a CPU but failed to allocate
2303 * VP assist page for it.
2305 if (static_branch_unlikely(&enable_evmcs) &&
2306 !hv_get_vp_assist_page(cpu))
2309 r = kvm_cpu_vmxon(phys_addr);
2319 static void vmclear_local_loaded_vmcss(void)
2321 int cpu = raw_smp_processor_id();
2322 struct loaded_vmcs *v, *n;
2324 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2325 loaded_vmcss_on_cpu_link)
2326 __loaded_vmcs_clear(v);
2330 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2333 static void kvm_cpu_vmxoff(void)
2335 asm volatile (__ex("vmxoff"));
2337 intel_pt_handle_vmx(0);
2338 cr4_clear_bits(X86_CR4_VMXE);
2341 static void hardware_disable(void)
2343 vmclear_local_loaded_vmcss();
2348 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2349 * directly instead of going through cpu_has(), to ensure KVM is trapping
2350 * ENCLS whenever it's supported in hardware. It does not matter whether
2351 * the host OS supports or has enabled SGX.
2353 static bool cpu_has_sgx(void)
2355 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2358 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2359 u32 msr, u32 *result)
2361 u32 vmx_msr_low, vmx_msr_high;
2362 u32 ctl = ctl_min | ctl_opt;
2364 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2366 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2367 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2369 /* Ensure minimum (required) set of control bits are supported. */
2377 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2378 struct vmx_capability *vmx_cap)
2380 u32 vmx_msr_low, vmx_msr_high;
2381 u32 min, opt, min2, opt2;
2382 u32 _pin_based_exec_control = 0;
2383 u32 _cpu_based_exec_control = 0;
2384 u32 _cpu_based_2nd_exec_control = 0;
2385 u32 _vmexit_control = 0;
2386 u32 _vmentry_control = 0;
2388 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2389 min = CPU_BASED_HLT_EXITING |
2390 #ifdef CONFIG_X86_64
2391 CPU_BASED_CR8_LOAD_EXITING |
2392 CPU_BASED_CR8_STORE_EXITING |
2394 CPU_BASED_CR3_LOAD_EXITING |
2395 CPU_BASED_CR3_STORE_EXITING |
2396 CPU_BASED_UNCOND_IO_EXITING |
2397 CPU_BASED_MOV_DR_EXITING |
2398 CPU_BASED_USE_TSC_OFFSETTING |
2399 CPU_BASED_MWAIT_EXITING |
2400 CPU_BASED_MONITOR_EXITING |
2401 CPU_BASED_INVLPG_EXITING |
2402 CPU_BASED_RDPMC_EXITING;
2404 opt = CPU_BASED_TPR_SHADOW |
2405 CPU_BASED_USE_MSR_BITMAPS |
2406 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2407 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2408 &_cpu_based_exec_control) < 0)
2410 #ifdef CONFIG_X86_64
2411 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2412 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2413 ~CPU_BASED_CR8_STORE_EXITING;
2415 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2417 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2418 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2419 SECONDARY_EXEC_WBINVD_EXITING |
2420 SECONDARY_EXEC_ENABLE_VPID |
2421 SECONDARY_EXEC_ENABLE_EPT |
2422 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2423 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2424 SECONDARY_EXEC_DESC |
2425 SECONDARY_EXEC_RDTSCP |
2426 SECONDARY_EXEC_ENABLE_INVPCID |
2427 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2428 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2429 SECONDARY_EXEC_SHADOW_VMCS |
2430 SECONDARY_EXEC_XSAVES |
2431 SECONDARY_EXEC_RDSEED_EXITING |
2432 SECONDARY_EXEC_RDRAND_EXITING |
2433 SECONDARY_EXEC_ENABLE_PML |
2434 SECONDARY_EXEC_TSC_SCALING |
2435 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2436 SECONDARY_EXEC_PT_USE_GPA |
2437 SECONDARY_EXEC_PT_CONCEAL_VMX |
2438 SECONDARY_EXEC_ENABLE_VMFUNC;
2440 opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2441 if (adjust_vmx_controls(min2, opt2,
2442 MSR_IA32_VMX_PROCBASED_CTLS2,
2443 &_cpu_based_2nd_exec_control) < 0)
2446 #ifndef CONFIG_X86_64
2447 if (!(_cpu_based_2nd_exec_control &
2448 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2449 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2452 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2453 _cpu_based_2nd_exec_control &= ~(
2454 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2455 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2456 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2458 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2459 &vmx_cap->ept, &vmx_cap->vpid);
2461 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2462 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2464 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2465 CPU_BASED_CR3_STORE_EXITING |
2466 CPU_BASED_INVLPG_EXITING);
2467 } else if (vmx_cap->ept) {
2469 pr_warn_once("EPT CAP should not exist if not support "
2470 "1-setting enable EPT VM-execution control\n");
2472 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2475 pr_warn_once("VPID CAP should not exist if not support "
2476 "1-setting enable VPID VM-execution control\n");
2479 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2480 #ifdef CONFIG_X86_64
2481 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2483 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2484 VM_EXIT_LOAD_IA32_PAT |
2485 VM_EXIT_LOAD_IA32_EFER |
2486 VM_EXIT_CLEAR_BNDCFGS |
2487 VM_EXIT_PT_CONCEAL_PIP |
2488 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2489 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2490 &_vmexit_control) < 0)
2493 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2494 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2495 PIN_BASED_VMX_PREEMPTION_TIMER;
2496 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2497 &_pin_based_exec_control) < 0)
2500 if (cpu_has_broken_vmx_preemption_timer())
2501 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2502 if (!(_cpu_based_2nd_exec_control &
2503 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2504 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2506 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2507 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2508 VM_ENTRY_LOAD_IA32_PAT |
2509 VM_ENTRY_LOAD_IA32_EFER |
2510 VM_ENTRY_LOAD_BNDCFGS |
2511 VM_ENTRY_PT_CONCEAL_PIP |
2512 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2513 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2514 &_vmentry_control) < 0)
2518 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2519 * can't be used due to an errata where VM Exit may incorrectly clear
2520 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2521 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2523 if (boot_cpu_data.x86 == 0x6) {
2524 switch (boot_cpu_data.x86_model) {
2525 case 26: /* AAK155 */
2526 case 30: /* AAP115 */
2527 case 37: /* AAT100 */
2528 case 44: /* BC86,AAY89,BD102 */
2530 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2531 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2532 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2533 "does not work properly. Using workaround\n");
2541 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2543 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2544 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2547 #ifdef CONFIG_X86_64
2548 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2549 if (vmx_msr_high & (1u<<16))
2553 /* Require Write-Back (WB) memory type for VMCS accesses. */
2554 if (((vmx_msr_high >> 18) & 15) != 6)
2557 vmcs_conf->size = vmx_msr_high & 0x1fff;
2558 vmcs_conf->order = get_order(vmcs_conf->size);
2559 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2561 vmcs_conf->revision_id = vmx_msr_low;
2563 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2564 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2565 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2566 vmcs_conf->vmexit_ctrl = _vmexit_control;
2567 vmcs_conf->vmentry_ctrl = _vmentry_control;
2569 if (static_branch_unlikely(&enable_evmcs))
2570 evmcs_sanitize_exec_ctrls(vmcs_conf);
2575 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2577 int node = cpu_to_node(cpu);
2581 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2584 vmcs = page_address(pages);
2585 memset(vmcs, 0, vmcs_config.size);
2587 /* KVM supports Enlightened VMCS v1 only */
2588 if (static_branch_unlikely(&enable_evmcs))
2589 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2591 vmcs->hdr.revision_id = vmcs_config.revision_id;
2594 vmcs->hdr.shadow_vmcs = 1;
2598 void free_vmcs(struct vmcs *vmcs)
2600 free_pages((unsigned long)vmcs, vmcs_config.order);
2604 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2606 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2608 if (!loaded_vmcs->vmcs)
2610 loaded_vmcs_clear(loaded_vmcs);
2611 free_vmcs(loaded_vmcs->vmcs);
2612 loaded_vmcs->vmcs = NULL;
2613 if (loaded_vmcs->msr_bitmap)
2614 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2615 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2618 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2620 loaded_vmcs->vmcs = alloc_vmcs(false);
2621 if (!loaded_vmcs->vmcs)
2624 vmcs_clear(loaded_vmcs->vmcs);
2626 loaded_vmcs->shadow_vmcs = NULL;
2627 loaded_vmcs->hv_timer_soft_disabled = false;
2628 loaded_vmcs->cpu = -1;
2629 loaded_vmcs->launched = 0;
2631 if (cpu_has_vmx_msr_bitmap()) {
2632 loaded_vmcs->msr_bitmap = (unsigned long *)
2633 __get_free_page(GFP_KERNEL_ACCOUNT);
2634 if (!loaded_vmcs->msr_bitmap)
2636 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2638 if (IS_ENABLED(CONFIG_HYPERV) &&
2639 static_branch_unlikely(&enable_evmcs) &&
2640 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2641 struct hv_enlightened_vmcs *evmcs =
2642 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2644 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2648 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2649 memset(&loaded_vmcs->controls_shadow, 0,
2650 sizeof(struct vmcs_controls_shadow));
2655 free_loaded_vmcs(loaded_vmcs);
2659 static void free_kvm_area(void)
2663 for_each_possible_cpu(cpu) {
2664 free_vmcs(per_cpu(vmxarea, cpu));
2665 per_cpu(vmxarea, cpu) = NULL;
2669 static __init int alloc_kvm_area(void)
2673 for_each_possible_cpu(cpu) {
2676 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2683 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2684 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2685 * revision_id reported by MSR_IA32_VMX_BASIC.
2687 * However, even though not explicitly documented by
2688 * TLFS, VMXArea passed as VMXON argument should
2689 * still be marked with revision_id reported by
2692 if (static_branch_unlikely(&enable_evmcs))
2693 vmcs->hdr.revision_id = vmcs_config.revision_id;
2695 per_cpu(vmxarea, cpu) = vmcs;
2700 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2701 struct kvm_segment *save)
2703 if (!emulate_invalid_guest_state) {
2705 * CS and SS RPL should be equal during guest entry according
2706 * to VMX spec, but in reality it is not always so. Since vcpu
2707 * is in the middle of the transition from real mode to
2708 * protected mode it is safe to assume that RPL 0 is a good
2711 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2712 save->selector &= ~SEGMENT_RPL_MASK;
2713 save->dpl = save->selector & SEGMENT_RPL_MASK;
2716 vmx_set_segment(vcpu, save, seg);
2719 static void enter_pmode(struct kvm_vcpu *vcpu)
2721 unsigned long flags;
2722 struct vcpu_vmx *vmx = to_vmx(vcpu);
2725 * Update real mode segment cache. It may be not up-to-date if sement
2726 * register was written while vcpu was in a guest mode.
2728 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2729 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2730 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2731 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2732 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2733 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2735 vmx->rmode.vm86_active = 0;
2737 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2739 flags = vmcs_readl(GUEST_RFLAGS);
2740 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2741 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2742 vmcs_writel(GUEST_RFLAGS, flags);
2744 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2745 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2747 update_exception_bitmap(vcpu);
2749 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2750 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2751 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2752 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2753 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2754 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2757 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2759 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2760 struct kvm_segment var = *save;
2763 if (seg == VCPU_SREG_CS)
2766 if (!emulate_invalid_guest_state) {
2767 var.selector = var.base >> 4;
2768 var.base = var.base & 0xffff0;
2778 if (save->base & 0xf)
2779 printk_once(KERN_WARNING "kvm: segment base is not "
2780 "paragraph aligned when entering "
2781 "protected mode (seg=%d)", seg);
2784 vmcs_write16(sf->selector, var.selector);
2785 vmcs_writel(sf->base, var.base);
2786 vmcs_write32(sf->limit, var.limit);
2787 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2790 static void enter_rmode(struct kvm_vcpu *vcpu)
2792 unsigned long flags;
2793 struct vcpu_vmx *vmx = to_vmx(vcpu);
2794 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2796 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2797 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2798 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2799 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2800 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2801 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2802 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2804 vmx->rmode.vm86_active = 1;
2807 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2808 * vcpu. Warn the user that an update is overdue.
2810 if (!kvm_vmx->tss_addr)
2811 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2812 "called before entering vcpu\n");
2814 vmx_segment_cache_clear(vmx);
2816 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2817 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2818 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2820 flags = vmcs_readl(GUEST_RFLAGS);
2821 vmx->rmode.save_rflags = flags;
2823 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2825 vmcs_writel(GUEST_RFLAGS, flags);
2826 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2827 update_exception_bitmap(vcpu);
2829 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2830 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2831 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2832 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2833 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2834 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2836 kvm_mmu_reset_context(vcpu);
2839 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2841 struct vcpu_vmx *vmx = to_vmx(vcpu);
2842 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2847 vcpu->arch.efer = efer;
2848 if (efer & EFER_LMA) {
2849 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2852 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2854 msr->data = efer & ~EFER_LME;
2859 #ifdef CONFIG_X86_64
2861 static void enter_lmode(struct kvm_vcpu *vcpu)
2865 vmx_segment_cache_clear(to_vmx(vcpu));
2867 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2868 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2869 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2871 vmcs_write32(GUEST_TR_AR_BYTES,
2872 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2873 | VMX_AR_TYPE_BUSY_64_TSS);
2875 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2878 static void exit_lmode(struct kvm_vcpu *vcpu)
2880 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2881 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2886 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2888 struct vcpu_vmx *vmx = to_vmx(vcpu);
2891 * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2892 * the CPU is not required to invalidate guest-physical mappings on
2893 * VM-Entry, even if VPID is disabled. Guest-physical mappings are
2894 * associated with the root EPT structure and not any particular VPID
2895 * (INVVPID also isn't required to invalidate guest-physical mappings).
2899 } else if (enable_vpid) {
2900 if (cpu_has_vmx_invvpid_global()) {
2901 vpid_sync_vcpu_global();
2903 vpid_sync_vcpu_single(vmx->vpid);
2904 vpid_sync_vcpu_single(vmx->nested.vpid02);
2909 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2911 struct kvm_mmu *mmu = vcpu->arch.mmu;
2912 u64 root_hpa = mmu->root_hpa;
2914 /* No flush required if the current context is invalid. */
2915 if (!VALID_PAGE(root_hpa))
2919 ept_sync_context(construct_eptp(vcpu, root_hpa,
2920 mmu->shadow_root_level));
2921 else if (!is_guest_mode(vcpu))
2922 vpid_sync_context(to_vmx(vcpu)->vpid);
2924 vpid_sync_context(nested_get_vpid02(vcpu));
2927 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2930 * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2931 * vmx_flush_tlb_guest() for an explanation of why this is ok.
2933 vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2936 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2939 * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2940 * or a vpid couldn't be allocated for this vCPU. VM-Enter and VM-Exit
2941 * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2942 * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2943 * i.e. no explicit INVVPID is necessary.
2945 vpid_sync_context(to_vmx(vcpu)->vpid);
2948 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2950 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2952 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2955 if (is_pae_paging(vcpu)) {
2956 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2957 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2958 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2959 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2963 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2965 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2967 if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2970 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2971 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2972 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2973 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2975 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2978 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2980 struct kvm_vcpu *vcpu)
2982 struct vcpu_vmx *vmx = to_vmx(vcpu);
2984 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2985 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2986 if (!(cr0 & X86_CR0_PG)) {
2987 /* From paging/starting to nonpaging */
2988 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2989 CPU_BASED_CR3_STORE_EXITING);
2990 vcpu->arch.cr0 = cr0;
2991 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2992 } else if (!is_paging(vcpu)) {
2993 /* From nonpaging to paging */
2994 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2995 CPU_BASED_CR3_STORE_EXITING);
2996 vcpu->arch.cr0 = cr0;
2997 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3000 if (!(cr0 & X86_CR0_WP))
3001 *hw_cr0 &= ~X86_CR0_WP;
3004 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3006 struct vcpu_vmx *vmx = to_vmx(vcpu);
3007 unsigned long hw_cr0;
3009 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3010 if (is_unrestricted_guest(vcpu))
3011 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3013 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3015 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3018 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3022 #ifdef CONFIG_X86_64
3023 if (vcpu->arch.efer & EFER_LME) {
3024 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3026 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3031 if (enable_ept && !is_unrestricted_guest(vcpu))
3032 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3034 vmcs_writel(CR0_READ_SHADOW, cr0);
3035 vmcs_writel(GUEST_CR0, hw_cr0);
3036 vcpu->arch.cr0 = cr0;
3037 kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3039 /* depends on vcpu->arch.cr0 to be set to a new value */
3040 vmx->emulation_required = emulation_required(vcpu);
3043 static int vmx_get_max_tdp_level(void)
3045 if (cpu_has_vmx_ept_5levels())
3050 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa,
3053 u64 eptp = VMX_EPTP_MT_WB;
3055 eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3057 if (enable_ept_ad_bits &&
3058 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3059 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3060 eptp |= (root_hpa & PAGE_MASK);
3065 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long pgd,
3068 struct kvm *kvm = vcpu->kvm;
3069 bool update_guest_cr3 = true;
3070 unsigned long guest_cr3;
3074 eptp = construct_eptp(vcpu, pgd, pgd_level);
3075 vmcs_write64(EPT_POINTER, eptp);
3077 if (kvm_x86_ops.tlb_remote_flush) {
3078 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3079 to_vmx(vcpu)->ept_pointer = eptp;
3080 to_kvm_vmx(kvm)->ept_pointers_match
3081 = EPT_POINTERS_CHECK;
3082 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3085 if (!enable_unrestricted_guest && !is_paging(vcpu))
3086 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3087 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3088 guest_cr3 = vcpu->arch.cr3;
3089 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3090 update_guest_cr3 = false;
3091 vmx_ept_load_pdptrs(vcpu);
3096 if (update_guest_cr3)
3097 vmcs_writel(GUEST_CR3, guest_cr3);
3100 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3102 struct vcpu_vmx *vmx = to_vmx(vcpu);
3104 * Pass through host's Machine Check Enable value to hw_cr4, which
3105 * is in force while we are in guest mode. Do not let guests control
3106 * this bit, even if host CR4.MCE == 0.
3108 unsigned long hw_cr4;
3110 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3111 if (is_unrestricted_guest(vcpu))
3112 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3113 else if (vmx->rmode.vm86_active)
3114 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3116 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3118 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3119 if (cr4 & X86_CR4_UMIP) {
3120 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3121 hw_cr4 &= ~X86_CR4_UMIP;
3122 } else if (!is_guest_mode(vcpu) ||
3123 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3124 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3128 if (cr4 & X86_CR4_VMXE) {
3130 * To use VMXON (and later other VMX instructions), a guest
3131 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3132 * So basically the check on whether to allow nested VMX
3133 * is here. We operate under the default treatment of SMM,
3134 * so VMX cannot be enabled under SMM.
3136 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3140 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3143 vcpu->arch.cr4 = cr4;
3144 kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3146 if (!is_unrestricted_guest(vcpu)) {
3148 if (!is_paging(vcpu)) {
3149 hw_cr4 &= ~X86_CR4_PAE;
3150 hw_cr4 |= X86_CR4_PSE;
3151 } else if (!(cr4 & X86_CR4_PAE)) {
3152 hw_cr4 &= ~X86_CR4_PAE;
3157 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3158 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3159 * to be manually disabled when guest switches to non-paging
3162 * If !enable_unrestricted_guest, the CPU is always running
3163 * with CR0.PG=1 and CR4 needs to be modified.
3164 * If enable_unrestricted_guest, the CPU automatically
3165 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3167 if (!is_paging(vcpu))
3168 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3171 vmcs_writel(CR4_READ_SHADOW, cr4);
3172 vmcs_writel(GUEST_CR4, hw_cr4);
3176 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3178 struct vcpu_vmx *vmx = to_vmx(vcpu);
3181 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3182 *var = vmx->rmode.segs[seg];
3183 if (seg == VCPU_SREG_TR
3184 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3186 var->base = vmx_read_guest_seg_base(vmx, seg);
3187 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3190 var->base = vmx_read_guest_seg_base(vmx, seg);
3191 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3192 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3193 ar = vmx_read_guest_seg_ar(vmx, seg);
3194 var->unusable = (ar >> 16) & 1;
3195 var->type = ar & 15;
3196 var->s = (ar >> 4) & 1;
3197 var->dpl = (ar >> 5) & 3;
3199 * Some userspaces do not preserve unusable property. Since usable
3200 * segment has to be present according to VMX spec we can use present
3201 * property to amend userspace bug by making unusable segment always
3202 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3203 * segment as unusable.
3205 var->present = !var->unusable;
3206 var->avl = (ar >> 12) & 1;
3207 var->l = (ar >> 13) & 1;
3208 var->db = (ar >> 14) & 1;
3209 var->g = (ar >> 15) & 1;
3212 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3214 struct kvm_segment s;
3216 if (to_vmx(vcpu)->rmode.vm86_active) {
3217 vmx_get_segment(vcpu, &s, seg);
3220 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3223 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3225 struct vcpu_vmx *vmx = to_vmx(vcpu);
3227 if (unlikely(vmx->rmode.vm86_active))
3230 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3231 return VMX_AR_DPL(ar);
3235 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3239 if (var->unusable || !var->present)
3242 ar = var->type & 15;
3243 ar |= (var->s & 1) << 4;
3244 ar |= (var->dpl & 3) << 5;
3245 ar |= (var->present & 1) << 7;
3246 ar |= (var->avl & 1) << 12;
3247 ar |= (var->l & 1) << 13;
3248 ar |= (var->db & 1) << 14;
3249 ar |= (var->g & 1) << 15;
3255 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3257 struct vcpu_vmx *vmx = to_vmx(vcpu);
3258 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3260 vmx_segment_cache_clear(vmx);
3262 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3263 vmx->rmode.segs[seg] = *var;
3264 if (seg == VCPU_SREG_TR)
3265 vmcs_write16(sf->selector, var->selector);
3267 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3271 vmcs_writel(sf->base, var->base);
3272 vmcs_write32(sf->limit, var->limit);
3273 vmcs_write16(sf->selector, var->selector);
3276 * Fix the "Accessed" bit in AR field of segment registers for older
3278 * IA32 arch specifies that at the time of processor reset the
3279 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3280 * is setting it to 0 in the userland code. This causes invalid guest
3281 * state vmexit when "unrestricted guest" mode is turned on.
3282 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3283 * tree. Newer qemu binaries with that qemu fix would not need this
3286 if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3287 var->type |= 0x1; /* Accessed */
3289 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3292 vmx->emulation_required = emulation_required(vcpu);
3295 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3297 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3299 *db = (ar >> 14) & 1;
3300 *l = (ar >> 13) & 1;
3303 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3305 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3306 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3309 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3311 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3312 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3315 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3317 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3318 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3321 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3323 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3324 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3327 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3329 struct kvm_segment var;
3332 vmx_get_segment(vcpu, &var, seg);
3334 if (seg == VCPU_SREG_CS)
3336 ar = vmx_segment_access_rights(&var);
3338 if (var.base != (var.selector << 4))
3340 if (var.limit != 0xffff)
3348 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3350 struct kvm_segment cs;
3351 unsigned int cs_rpl;
3353 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3354 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3358 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3362 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3363 if (cs.dpl > cs_rpl)
3366 if (cs.dpl != cs_rpl)
3372 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3376 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3378 struct kvm_segment ss;
3379 unsigned int ss_rpl;
3381 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3382 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3386 if (ss.type != 3 && ss.type != 7)
3390 if (ss.dpl != ss_rpl) /* DPL != RPL */
3398 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3400 struct kvm_segment var;
3403 vmx_get_segment(vcpu, &var, seg);
3404 rpl = var.selector & SEGMENT_RPL_MASK;
3412 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3413 if (var.dpl < rpl) /* DPL < RPL */
3417 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3423 static bool tr_valid(struct kvm_vcpu *vcpu)
3425 struct kvm_segment tr;
3427 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3431 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3433 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3441 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3443 struct kvm_segment ldtr;
3445 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3449 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3459 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3461 struct kvm_segment cs, ss;
3463 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3464 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3466 return ((cs.selector & SEGMENT_RPL_MASK) ==
3467 (ss.selector & SEGMENT_RPL_MASK));
3471 * Check if guest state is valid. Returns true if valid, false if
3473 * We assume that registers are always usable
3475 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3477 if (is_unrestricted_guest(vcpu))
3480 /* real mode guest state checks */
3481 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3482 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3484 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3486 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3488 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3490 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3492 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3495 /* protected mode guest state checks */
3496 if (!cs_ss_rpl_check(vcpu))
3498 if (!code_segment_valid(vcpu))
3500 if (!stack_segment_valid(vcpu))
3502 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3504 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3506 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3508 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3510 if (!tr_valid(vcpu))
3512 if (!ldtr_valid(vcpu))
3516 * - Add checks on RIP
3517 * - Add checks on RFLAGS
3523 static int init_rmode_tss(struct kvm *kvm)
3529 idx = srcu_read_lock(&kvm->srcu);
3530 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3531 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3534 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3535 r = kvm_write_guest_page(kvm, fn++, &data,
3536 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3539 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3542 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3546 r = kvm_write_guest_page(kvm, fn, &data,
3547 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3550 srcu_read_unlock(&kvm->srcu, idx);
3554 static int init_rmode_identity_map(struct kvm *kvm)
3556 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3558 kvm_pfn_t identity_map_pfn;
3561 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3562 mutex_lock(&kvm->slots_lock);
3564 if (likely(kvm_vmx->ept_identity_pagetable_done))
3567 if (!kvm_vmx->ept_identity_map_addr)
3568 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3569 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3571 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3572 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3576 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3579 /* Set up identity-mapping pagetable for EPT in real mode */
3580 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3581 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3582 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3583 r = kvm_write_guest_page(kvm, identity_map_pfn,
3584 &tmp, i * sizeof(tmp), sizeof(tmp));
3588 kvm_vmx->ept_identity_pagetable_done = true;
3591 mutex_unlock(&kvm->slots_lock);
3595 static void seg_setup(int seg)
3597 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3600 vmcs_write16(sf->selector, 0);
3601 vmcs_writel(sf->base, 0);
3602 vmcs_write32(sf->limit, 0xffff);
3604 if (seg == VCPU_SREG_CS)
3605 ar |= 0x08; /* code segment */
3607 vmcs_write32(sf->ar_bytes, ar);
3610 static int alloc_apic_access_page(struct kvm *kvm)
3615 mutex_lock(&kvm->slots_lock);
3616 if (kvm->arch.apic_access_page_done)
3618 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3619 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3623 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3624 if (is_error_page(page)) {
3630 * Do not pin the page in memory, so that memory hot-unplug
3631 * is able to migrate it.
3634 kvm->arch.apic_access_page_done = true;
3636 mutex_unlock(&kvm->slots_lock);
3640 int allocate_vpid(void)
3646 spin_lock(&vmx_vpid_lock);
3647 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3648 if (vpid < VMX_NR_VPIDS)
3649 __set_bit(vpid, vmx_vpid_bitmap);
3652 spin_unlock(&vmx_vpid_lock);
3656 void free_vpid(int vpid)
3658 if (!enable_vpid || vpid == 0)
3660 spin_lock(&vmx_vpid_lock);
3661 __clear_bit(vpid, vmx_vpid_bitmap);
3662 spin_unlock(&vmx_vpid_lock);
3665 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3668 int f = sizeof(unsigned long);
3670 if (!cpu_has_vmx_msr_bitmap())
3673 if (static_branch_unlikely(&enable_evmcs))
3674 evmcs_touch_msr_bitmap();
3677 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3678 * have the write-low and read-high bitmap offsets the wrong way round.
3679 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3681 if (msr <= 0x1fff) {
3682 if (type & MSR_TYPE_R)
3684 __clear_bit(msr, msr_bitmap + 0x000 / f);
3686 if (type & MSR_TYPE_W)
3688 __clear_bit(msr, msr_bitmap + 0x800 / f);
3690 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3692 if (type & MSR_TYPE_R)
3694 __clear_bit(msr, msr_bitmap + 0x400 / f);
3696 if (type & MSR_TYPE_W)
3698 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3703 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3706 int f = sizeof(unsigned long);
3708 if (!cpu_has_vmx_msr_bitmap())
3711 if (static_branch_unlikely(&enable_evmcs))
3712 evmcs_touch_msr_bitmap();
3715 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3716 * have the write-low and read-high bitmap offsets the wrong way round.
3717 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3719 if (msr <= 0x1fff) {
3720 if (type & MSR_TYPE_R)
3722 __set_bit(msr, msr_bitmap + 0x000 / f);
3724 if (type & MSR_TYPE_W)
3726 __set_bit(msr, msr_bitmap + 0x800 / f);
3728 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3730 if (type & MSR_TYPE_R)
3732 __set_bit(msr, msr_bitmap + 0x400 / f);
3734 if (type & MSR_TYPE_W)
3736 __set_bit(msr, msr_bitmap + 0xc00 / f);
3741 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3742 u32 msr, int type, bool value)
3745 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3747 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3750 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3754 if (cpu_has_secondary_exec_ctrls() &&
3755 (secondary_exec_controls_get(to_vmx(vcpu)) &
3756 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3757 mode |= MSR_BITMAP_MODE_X2APIC;
3758 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3759 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3765 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3770 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3771 unsigned word = msr / BITS_PER_LONG;
3772 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3773 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3776 if (mode & MSR_BITMAP_MODE_X2APIC) {
3778 * TPR reads and writes can be virtualized even if virtual interrupt
3779 * delivery is not in use.
3781 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3782 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3783 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3784 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3785 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3790 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3792 struct vcpu_vmx *vmx = to_vmx(vcpu);
3793 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3794 u8 mode = vmx_msr_bitmap_mode(vcpu);
3795 u8 changed = mode ^ vmx->msr_bitmap_mode;
3800 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3801 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3803 vmx->msr_bitmap_mode = mode;
3806 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3808 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3809 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3812 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3814 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3816 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3818 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3820 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3821 vmx_set_intercept_for_msr(msr_bitmap,
3822 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3823 vmx_set_intercept_for_msr(msr_bitmap,
3824 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3828 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3830 struct vcpu_vmx *vmx = to_vmx(vcpu);
3835 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3836 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3837 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3840 rvi = vmx_get_rvi();
3842 vapic_page = vmx->nested.virtual_apic_map.hva;
3843 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3845 return ((rvi & 0xf0) > (vppr & 0xf0));
3848 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3852 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3854 if (vcpu->mode == IN_GUEST_MODE) {
3856 * The vector of interrupt to be delivered to vcpu had
3857 * been set in PIR before this function.
3859 * Following cases will be reached in this block, and
3860 * we always send a notification event in all cases as
3863 * Case 1: vcpu keeps in non-root mode. Sending a
3864 * notification event posts the interrupt to vcpu.
3866 * Case 2: vcpu exits to root mode and is still
3867 * runnable. PIR will be synced to vIRR before the
3868 * next vcpu entry. Sending a notification event in
3869 * this case has no effect, as vcpu is not in root
3872 * Case 3: vcpu exits to root mode and is blocked.
3873 * vcpu_block() has already synced PIR to vIRR and
3874 * never blocks vcpu if vIRR is not cleared. Therefore,
3875 * a blocked vcpu here does not wait for any requested
3876 * interrupts in PIR, and sending a notification event
3877 * which has no effect is safe here.
3880 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3887 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3890 struct vcpu_vmx *vmx = to_vmx(vcpu);
3892 if (is_guest_mode(vcpu) &&
3893 vector == vmx->nested.posted_intr_nv) {
3895 * If a posted intr is not recognized by hardware,
3896 * we will accomplish it in the next vmentry.
3898 vmx->nested.pi_pending = true;
3899 kvm_make_request(KVM_REQ_EVENT, vcpu);
3900 /* the PIR and ON have been set by L1. */
3901 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3902 kvm_vcpu_kick(vcpu);
3908 * Send interrupt to vcpu via posted interrupt way.
3909 * 1. If target vcpu is running(non-root mode), send posted interrupt
3910 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3911 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3912 * interrupt from PIR in next vmentry.
3914 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3916 struct vcpu_vmx *vmx = to_vmx(vcpu);
3919 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3923 if (!vcpu->arch.apicv_active)
3926 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3929 /* If a previous notification has sent the IPI, nothing to do. */
3930 if (pi_test_and_set_on(&vmx->pi_desc))
3933 if (vcpu != kvm_get_running_vcpu() &&
3934 !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3935 kvm_vcpu_kick(vcpu);
3941 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3942 * will not change in the lifetime of the guest.
3943 * Note that host-state that does change is set elsewhere. E.g., host-state
3944 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3946 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3950 unsigned long cr0, cr3, cr4;
3953 WARN_ON(cr0 & X86_CR0_TS);
3954 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3957 * Save the most likely value for this task's CR3 in the VMCS.
3958 * We can't use __get_current_cr3_fast() because we're not atomic.
3961 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
3962 vmx->loaded_vmcs->host_state.cr3 = cr3;
3964 /* Save the most likely value for this task's CR4 in the VMCS. */
3965 cr4 = cr4_read_shadow();
3966 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
3967 vmx->loaded_vmcs->host_state.cr4 = cr4;
3969 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3970 #ifdef CONFIG_X86_64
3972 * Load null selectors, so we can avoid reloading them in
3973 * vmx_prepare_switch_to_host(), in case userspace uses
3974 * the null selectors too (the expected case).
3976 vmcs_write16(HOST_DS_SELECTOR, 0);
3977 vmcs_write16(HOST_ES_SELECTOR, 0);
3979 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3980 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3982 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3983 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3985 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
3987 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3989 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3990 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3991 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3992 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3994 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3995 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3996 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3999 if (cpu_has_load_ia32_efer())
4000 vmcs_write64(HOST_IA32_EFER, host_efer);
4003 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4005 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS;
4007 vmx->vcpu.arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4008 if (is_guest_mode(&vmx->vcpu))
4009 vmx->vcpu.arch.cr4_guest_owned_bits &=
4010 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4011 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4014 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4016 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4018 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4019 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4022 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4024 if (!enable_preemption_timer)
4025 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4027 return pin_based_exec_ctrl;
4030 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4032 struct vcpu_vmx *vmx = to_vmx(vcpu);
4034 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4035 if (cpu_has_secondary_exec_ctrls()) {
4036 if (kvm_vcpu_apicv_active(vcpu))
4037 secondary_exec_controls_setbit(vmx,
4038 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4039 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4041 secondary_exec_controls_clearbit(vmx,
4042 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4043 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4046 if (cpu_has_vmx_msr_bitmap())
4047 vmx_update_msr_bitmap(vcpu);
4050 u32 vmx_exec_control(struct vcpu_vmx *vmx)
4052 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4054 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4055 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4057 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4058 exec_control &= ~CPU_BASED_TPR_SHADOW;
4059 #ifdef CONFIG_X86_64
4060 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4061 CPU_BASED_CR8_LOAD_EXITING;
4065 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4066 CPU_BASED_CR3_LOAD_EXITING |
4067 CPU_BASED_INVLPG_EXITING;
4068 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4069 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4070 CPU_BASED_MONITOR_EXITING);
4071 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4072 exec_control &= ~CPU_BASED_HLT_EXITING;
4073 return exec_control;
4077 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4079 struct kvm_vcpu *vcpu = &vmx->vcpu;
4081 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4083 if (vmx_pt_mode_is_system())
4084 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4085 if (!cpu_need_virtualize_apic_accesses(vcpu))
4086 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4088 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4090 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4091 enable_unrestricted_guest = 0;
4093 if (!enable_unrestricted_guest)
4094 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4095 if (kvm_pause_in_guest(vmx->vcpu.kvm))
4096 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4097 if (!kvm_vcpu_apicv_active(vcpu))
4098 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4099 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4100 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4102 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4103 * in vmx_set_cr4. */
4104 exec_control &= ~SECONDARY_EXEC_DESC;
4106 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4108 We can NOT enable shadow_vmcs here because we don't have yet
4111 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4114 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4116 if (vmx_xsaves_supported()) {
4117 /* Exposing XSAVES only when XSAVE is exposed */
4118 bool xsaves_enabled =
4119 boot_cpu_has(X86_FEATURE_XSAVE) &&
4120 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4121 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4123 vcpu->arch.xsaves_enabled = xsaves_enabled;
4125 if (!xsaves_enabled)
4126 exec_control &= ~SECONDARY_EXEC_XSAVES;
4130 vmx->nested.msrs.secondary_ctls_high |=
4131 SECONDARY_EXEC_XSAVES;
4133 vmx->nested.msrs.secondary_ctls_high &=
4134 ~SECONDARY_EXEC_XSAVES;
4138 if (cpu_has_vmx_rdtscp()) {
4139 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4140 if (!rdtscp_enabled)
4141 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4145 vmx->nested.msrs.secondary_ctls_high |=
4146 SECONDARY_EXEC_RDTSCP;
4148 vmx->nested.msrs.secondary_ctls_high &=
4149 ~SECONDARY_EXEC_RDTSCP;
4153 if (cpu_has_vmx_invpcid()) {
4154 /* Exposing INVPCID only when PCID is exposed */
4155 bool invpcid_enabled =
4156 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4157 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4159 if (!invpcid_enabled) {
4160 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4161 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4165 if (invpcid_enabled)
4166 vmx->nested.msrs.secondary_ctls_high |=
4167 SECONDARY_EXEC_ENABLE_INVPCID;
4169 vmx->nested.msrs.secondary_ctls_high &=
4170 ~SECONDARY_EXEC_ENABLE_INVPCID;
4174 if (vmx_rdrand_supported()) {
4175 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4177 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4181 vmx->nested.msrs.secondary_ctls_high |=
4182 SECONDARY_EXEC_RDRAND_EXITING;
4184 vmx->nested.msrs.secondary_ctls_high &=
4185 ~SECONDARY_EXEC_RDRAND_EXITING;
4189 if (vmx_rdseed_supported()) {
4190 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4192 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4196 vmx->nested.msrs.secondary_ctls_high |=
4197 SECONDARY_EXEC_RDSEED_EXITING;
4199 vmx->nested.msrs.secondary_ctls_high &=
4200 ~SECONDARY_EXEC_RDSEED_EXITING;
4204 if (vmx_waitpkg_supported()) {
4205 bool waitpkg_enabled =
4206 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4208 if (!waitpkg_enabled)
4209 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4212 if (waitpkg_enabled)
4213 vmx->nested.msrs.secondary_ctls_high |=
4214 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4216 vmx->nested.msrs.secondary_ctls_high &=
4217 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4221 vmx->secondary_exec_control = exec_control;
4224 static void ept_set_mmio_spte_mask(void)
4227 * EPT Misconfigurations can be generated if the value of bits 2:0
4228 * of an EPT paging-structure entry is 110b (write/execute).
4230 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE, 0);
4233 #define VMX_XSS_EXIT_BITMAP 0
4236 * Noting that the initialization of Guest-state Area of VMCS is in
4239 static void init_vmcs(struct vcpu_vmx *vmx)
4242 nested_vmx_set_vmcs_shadowing_bitmap();
4244 if (cpu_has_vmx_msr_bitmap())
4245 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4247 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4250 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4252 exec_controls_set(vmx, vmx_exec_control(vmx));
4254 if (cpu_has_secondary_exec_ctrls()) {
4255 vmx_compute_secondary_exec_control(vmx);
4256 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4259 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4260 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4261 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4262 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4263 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4265 vmcs_write16(GUEST_INTR_STATUS, 0);
4267 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4268 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4271 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4272 vmcs_write32(PLE_GAP, ple_gap);
4273 vmx->ple_window = ple_window;
4274 vmx->ple_window_dirty = true;
4277 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4278 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4279 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4281 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4282 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4283 vmx_set_constant_host_state(vmx);
4284 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4285 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4287 if (cpu_has_vmx_vmfunc())
4288 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4290 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4291 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4292 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4293 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4294 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4296 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4297 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4299 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4301 /* 22.2.1, 20.8.1 */
4302 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4304 vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4305 vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4307 set_cr4_guest_host_mask(vmx);
4310 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4312 if (vmx_xsaves_supported())
4313 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4316 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4317 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4320 if (cpu_has_vmx_encls_vmexit())
4321 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4323 if (vmx_pt_mode_is_host_guest()) {
4324 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4325 /* Bit[6~0] are forced to 1, writes are ignored. */
4326 vmx->pt_desc.guest.output_mask = 0x7F;
4327 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4331 * If EPT is enabled, #PF is only trapped if MAXPHYADDR is mismatched
4332 * between guest and host. In that case we only care about present
4336 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, PFERR_PRESENT_MASK);
4337 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, PFERR_PRESENT_MASK);
4341 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4343 struct vcpu_vmx *vmx = to_vmx(vcpu);
4344 struct msr_data apic_base_msr;
4347 vmx->rmode.vm86_active = 0;
4350 vmx->msr_ia32_umwait_control = 0;
4352 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4353 vmx->hv_deadline_tsc = -1;
4354 kvm_set_cr8(vcpu, 0);
4357 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4358 MSR_IA32_APICBASE_ENABLE;
4359 if (kvm_vcpu_is_reset_bsp(vcpu))
4360 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4361 apic_base_msr.host_initiated = true;
4362 kvm_set_apic_base(vcpu, &apic_base_msr);
4365 vmx_segment_cache_clear(vmx);
4367 seg_setup(VCPU_SREG_CS);
4368 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4369 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4371 seg_setup(VCPU_SREG_DS);
4372 seg_setup(VCPU_SREG_ES);
4373 seg_setup(VCPU_SREG_FS);
4374 seg_setup(VCPU_SREG_GS);
4375 seg_setup(VCPU_SREG_SS);
4377 vmcs_write16(GUEST_TR_SELECTOR, 0);
4378 vmcs_writel(GUEST_TR_BASE, 0);
4379 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4380 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4382 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4383 vmcs_writel(GUEST_LDTR_BASE, 0);
4384 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4385 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4388 vmcs_write32(GUEST_SYSENTER_CS, 0);
4389 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4390 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4391 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4394 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4395 kvm_rip_write(vcpu, 0xfff0);
4397 vmcs_writel(GUEST_GDTR_BASE, 0);
4398 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4400 vmcs_writel(GUEST_IDTR_BASE, 0);
4401 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4403 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4404 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4405 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4406 if (kvm_mpx_supported())
4407 vmcs_write64(GUEST_BNDCFGS, 0);
4411 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4413 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4414 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4415 if (cpu_need_tpr_shadow(vcpu))
4416 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4417 __pa(vcpu->arch.apic->regs));
4418 vmcs_write32(TPR_THRESHOLD, 0);
4421 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4423 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4424 vmx->vcpu.arch.cr0 = cr0;
4425 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4426 vmx_set_cr4(vcpu, 0);
4427 vmx_set_efer(vcpu, 0);
4429 update_exception_bitmap(vcpu);
4431 vpid_sync_context(vmx->vpid);
4433 vmx_clear_hlt(vcpu);
4436 static void enable_irq_window(struct kvm_vcpu *vcpu)
4438 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4441 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4444 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4445 enable_irq_window(vcpu);
4449 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4452 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4454 struct vcpu_vmx *vmx = to_vmx(vcpu);
4456 int irq = vcpu->arch.interrupt.nr;
4458 trace_kvm_inj_virq(irq);
4460 ++vcpu->stat.irq_injections;
4461 if (vmx->rmode.vm86_active) {
4463 if (vcpu->arch.interrupt.soft)
4464 inc_eip = vcpu->arch.event_exit_inst_len;
4465 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4468 intr = irq | INTR_INFO_VALID_MASK;
4469 if (vcpu->arch.interrupt.soft) {
4470 intr |= INTR_TYPE_SOFT_INTR;
4471 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4472 vmx->vcpu.arch.event_exit_inst_len);
4474 intr |= INTR_TYPE_EXT_INTR;
4475 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4477 vmx_clear_hlt(vcpu);
4480 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4482 struct vcpu_vmx *vmx = to_vmx(vcpu);
4486 * Tracking the NMI-blocked state in software is built upon
4487 * finding the next open IRQ window. This, in turn, depends on
4488 * well-behaving guests: They have to keep IRQs disabled at
4489 * least as long as the NMI handler runs. Otherwise we may
4490 * cause NMI nesting, maybe breaking the guest. But as this is
4491 * highly unlikely, we can live with the residual risk.
4493 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4494 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4497 ++vcpu->stat.nmi_injections;
4498 vmx->loaded_vmcs->nmi_known_unmasked = false;
4500 if (vmx->rmode.vm86_active) {
4501 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4505 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4506 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4508 vmx_clear_hlt(vcpu);
4511 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4513 struct vcpu_vmx *vmx = to_vmx(vcpu);
4517 return vmx->loaded_vmcs->soft_vnmi_blocked;
4518 if (vmx->loaded_vmcs->nmi_known_unmasked)
4520 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4521 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4525 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4527 struct vcpu_vmx *vmx = to_vmx(vcpu);
4530 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4531 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4532 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4535 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4537 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4538 GUEST_INTR_STATE_NMI);
4540 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4541 GUEST_INTR_STATE_NMI);
4545 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4547 if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4550 if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4553 return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4554 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4555 GUEST_INTR_STATE_NMI));
4558 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4560 if (to_vmx(vcpu)->nested.nested_run_pending)
4563 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
4564 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4567 return !vmx_nmi_blocked(vcpu);
4570 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4572 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4575 return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4576 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4577 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4580 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4582 if (to_vmx(vcpu)->nested.nested_run_pending)
4586 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4587 * e.g. if the IRQ arrived asynchronously after checking nested events.
4589 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4592 return !vmx_interrupt_blocked(vcpu);
4595 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4599 if (enable_unrestricted_guest)
4602 mutex_lock(&kvm->slots_lock);
4603 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4605 mutex_unlock(&kvm->slots_lock);
4609 to_kvm_vmx(kvm)->tss_addr = addr;
4610 return init_rmode_tss(kvm);
4613 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4615 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4619 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4624 * Update instruction length as we may reinject the exception
4625 * from user space while in guest debugging mode.
4627 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4628 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4629 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4633 return !(vcpu->guest_debug &
4634 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4648 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4649 int vec, u32 err_code)
4652 * Instruction with address size override prefix opcode 0x67
4653 * Cause the #SS fault with 0 error code in VM86 mode.
4655 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4656 if (kvm_emulate_instruction(vcpu, 0)) {
4657 if (vcpu->arch.halt_request) {
4658 vcpu->arch.halt_request = 0;
4659 return kvm_vcpu_halt(vcpu);
4667 * Forward all other exceptions that are valid in real mode.
4668 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4669 * the required debugging infrastructure rework.
4671 kvm_queue_exception(vcpu, vec);
4676 * Trigger machine check on the host. We assume all the MSRs are already set up
4677 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4678 * We pass a fake environment to the machine check handler because we want
4679 * the guest to be always treated like user space, no matter what context
4680 * it used internally.
4682 static void kvm_machine_check(void)
4684 #if defined(CONFIG_X86_MCE)
4685 struct pt_regs regs = {
4686 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4687 .flags = X86_EFLAGS_IF,
4690 do_machine_check(®s);
4694 static int handle_machine_check(struct kvm_vcpu *vcpu)
4696 /* handled by vmx_vcpu_run() */
4701 * If the host has split lock detection disabled, then #AC is
4702 * unconditionally injected into the guest, which is the pre split lock
4703 * detection behaviour.
4705 * If the host has split lock detection enabled then #AC is
4706 * only injected into the guest when:
4707 * - Guest CPL == 3 (user mode)
4708 * - Guest has #AC detection enabled in CR0
4709 * - Guest EFLAGS has AC bit set
4711 static inline bool guest_inject_ac(struct kvm_vcpu *vcpu)
4713 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4716 return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4717 (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4720 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4722 struct vcpu_vmx *vmx = to_vmx(vcpu);
4723 struct kvm_run *kvm_run = vcpu->run;
4724 u32 intr_info, ex_no, error_code;
4725 unsigned long cr2, rip, dr6;
4728 vect_info = vmx->idt_vectoring_info;
4729 intr_info = vmx_get_intr_info(vcpu);
4731 if (is_machine_check(intr_info) || is_nmi(intr_info))
4732 return 1; /* handled by handle_exception_nmi_irqoff() */
4734 if (is_invalid_opcode(intr_info))
4735 return handle_ud(vcpu);
4738 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4739 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4741 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4742 WARN_ON_ONCE(!enable_vmware_backdoor);
4745 * VMware backdoor emulation on #GP interception only handles
4746 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4747 * error code on #GP.
4750 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4753 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4757 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4758 * MMIO, it is better to report an internal error.
4759 * See the comments in vmx_handle_exit.
4761 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4762 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4763 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4764 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4765 vcpu->run->internal.ndata = 4;
4766 vcpu->run->internal.data[0] = vect_info;
4767 vcpu->run->internal.data[1] = intr_info;
4768 vcpu->run->internal.data[2] = error_code;
4769 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4773 if (is_page_fault(intr_info)) {
4774 cr2 = vmx_get_exit_qual(vcpu);
4775 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4777 * EPT will cause page fault only if we need to
4778 * detect illegal GPAs.
4780 kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4783 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4786 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4788 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4789 return handle_rmode_exception(vcpu, ex_no, error_code);
4793 dr6 = vmx_get_exit_qual(vcpu);
4794 if (!(vcpu->guest_debug &
4795 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4796 if (is_icebp(intr_info))
4797 WARN_ON(!skip_emulated_instruction(vcpu));
4799 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4802 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4803 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4807 * Update instruction length as we may reinject #BP from
4808 * user space while in guest debugging mode. Reading it for
4809 * #DB as well causes no harm, it is not used in that case.
4811 vmx->vcpu.arch.event_exit_inst_len =
4812 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4813 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4814 rip = kvm_rip_read(vcpu);
4815 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4816 kvm_run->debug.arch.exception = ex_no;
4819 if (guest_inject_ac(vcpu)) {
4820 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4825 * Handle split lock. Depending on detection mode this will
4826 * either warn and disable split lock detection for this
4827 * task or force SIGBUS on it.
4829 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4833 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4834 kvm_run->ex.exception = ex_no;
4835 kvm_run->ex.error_code = error_code;
4841 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4843 ++vcpu->stat.irq_exits;
4847 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4849 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4850 vcpu->mmio_needed = 0;
4854 static int handle_io(struct kvm_vcpu *vcpu)
4856 unsigned long exit_qualification;
4857 int size, in, string;
4860 exit_qualification = vmx_get_exit_qual(vcpu);
4861 string = (exit_qualification & 16) != 0;
4863 ++vcpu->stat.io_exits;
4866 return kvm_emulate_instruction(vcpu, 0);
4868 port = exit_qualification >> 16;
4869 size = (exit_qualification & 7) + 1;
4870 in = (exit_qualification & 8) != 0;
4872 return kvm_fast_pio(vcpu, size, port, in);
4876 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4879 * Patch in the VMCALL instruction:
4881 hypercall[0] = 0x0f;
4882 hypercall[1] = 0x01;
4883 hypercall[2] = 0xc1;
4886 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4887 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4889 if (is_guest_mode(vcpu)) {
4890 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4891 unsigned long orig_val = val;
4894 * We get here when L2 changed cr0 in a way that did not change
4895 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4896 * but did change L0 shadowed bits. So we first calculate the
4897 * effective cr0 value that L1 would like to write into the
4898 * hardware. It consists of the L2-owned bits from the new
4899 * value combined with the L1-owned bits from L1's guest_cr0.
4901 val = (val & ~vmcs12->cr0_guest_host_mask) |
4902 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4904 if (!nested_guest_cr0_valid(vcpu, val))
4907 if (kvm_set_cr0(vcpu, val))
4909 vmcs_writel(CR0_READ_SHADOW, orig_val);
4912 if (to_vmx(vcpu)->nested.vmxon &&
4913 !nested_host_cr0_valid(vcpu, val))
4916 return kvm_set_cr0(vcpu, val);
4920 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4922 if (is_guest_mode(vcpu)) {
4923 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4924 unsigned long orig_val = val;
4926 /* analogously to handle_set_cr0 */
4927 val = (val & ~vmcs12->cr4_guest_host_mask) |
4928 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4929 if (kvm_set_cr4(vcpu, val))
4931 vmcs_writel(CR4_READ_SHADOW, orig_val);
4934 return kvm_set_cr4(vcpu, val);
4937 static int handle_desc(struct kvm_vcpu *vcpu)
4939 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4940 return kvm_emulate_instruction(vcpu, 0);
4943 static int handle_cr(struct kvm_vcpu *vcpu)
4945 unsigned long exit_qualification, val;
4951 exit_qualification = vmx_get_exit_qual(vcpu);
4952 cr = exit_qualification & 15;
4953 reg = (exit_qualification >> 8) & 15;
4954 switch ((exit_qualification >> 4) & 3) {
4955 case 0: /* mov to cr */
4956 val = kvm_register_readl(vcpu, reg);
4957 trace_kvm_cr_write(cr, val);
4960 err = handle_set_cr0(vcpu, val);
4961 return kvm_complete_insn_gp(vcpu, err);
4963 WARN_ON_ONCE(enable_unrestricted_guest);
4964 err = kvm_set_cr3(vcpu, val);
4965 return kvm_complete_insn_gp(vcpu, err);
4967 err = handle_set_cr4(vcpu, val);
4968 return kvm_complete_insn_gp(vcpu, err);
4970 u8 cr8_prev = kvm_get_cr8(vcpu);
4972 err = kvm_set_cr8(vcpu, cr8);
4973 ret = kvm_complete_insn_gp(vcpu, err);
4974 if (lapic_in_kernel(vcpu))
4976 if (cr8_prev <= cr8)
4979 * TODO: we might be squashing a
4980 * KVM_GUESTDBG_SINGLESTEP-triggered
4981 * KVM_EXIT_DEBUG here.
4983 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4989 WARN_ONCE(1, "Guest should always own CR0.TS");
4990 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4991 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4992 return kvm_skip_emulated_instruction(vcpu);
4993 case 1: /*mov from cr*/
4996 WARN_ON_ONCE(enable_unrestricted_guest);
4997 val = kvm_read_cr3(vcpu);
4998 kvm_register_write(vcpu, reg, val);
4999 trace_kvm_cr_read(cr, val);
5000 return kvm_skip_emulated_instruction(vcpu);
5002 val = kvm_get_cr8(vcpu);
5003 kvm_register_write(vcpu, reg, val);
5004 trace_kvm_cr_read(cr, val);
5005 return kvm_skip_emulated_instruction(vcpu);
5009 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5010 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5011 kvm_lmsw(vcpu, val);
5013 return kvm_skip_emulated_instruction(vcpu);
5017 vcpu->run->exit_reason = 0;
5018 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5019 (int)(exit_qualification >> 4) & 3, cr);
5023 static int handle_dr(struct kvm_vcpu *vcpu)
5025 unsigned long exit_qualification;
5028 exit_qualification = vmx_get_exit_qual(vcpu);
5029 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5031 /* First, if DR does not exist, trigger UD */
5032 if (!kvm_require_dr(vcpu, dr))
5035 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5036 if (!kvm_require_cpl(vcpu, 0))
5038 dr7 = vmcs_readl(GUEST_DR7);
5041 * As the vm-exit takes precedence over the debug trap, we
5042 * need to emulate the latter, either for the host or the
5043 * guest debugging itself.
5045 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5046 vcpu->run->debug.arch.dr6 = DR6_BD | DR6_RTM | DR6_FIXED_1;
5047 vcpu->run->debug.arch.dr7 = dr7;
5048 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5049 vcpu->run->debug.arch.exception = DB_VECTOR;
5050 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5053 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5058 if (vcpu->guest_debug == 0) {
5059 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5062 * No more DR vmexits; force a reload of the debug registers
5063 * and reenter on this instruction. The next vmexit will
5064 * retrieve the full state of the debug registers.
5066 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5070 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5071 if (exit_qualification & TYPE_MOV_FROM_DR) {
5074 if (kvm_get_dr(vcpu, dr, &val))
5076 kvm_register_write(vcpu, reg, val);
5078 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5081 return kvm_skip_emulated_instruction(vcpu);
5084 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5086 get_debugreg(vcpu->arch.db[0], 0);
5087 get_debugreg(vcpu->arch.db[1], 1);
5088 get_debugreg(vcpu->arch.db[2], 2);
5089 get_debugreg(vcpu->arch.db[3], 3);
5090 get_debugreg(vcpu->arch.dr6, 6);
5091 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5093 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5094 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5097 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5099 vmcs_writel(GUEST_DR7, val);
5102 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5104 kvm_apic_update_ppr(vcpu);
5108 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5110 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5112 kvm_make_request(KVM_REQ_EVENT, vcpu);
5114 ++vcpu->stat.irq_window_exits;
5118 static int handle_vmcall(struct kvm_vcpu *vcpu)
5120 return kvm_emulate_hypercall(vcpu);
5123 static int handle_invd(struct kvm_vcpu *vcpu)
5125 return kvm_emulate_instruction(vcpu, 0);
5128 static int handle_invlpg(struct kvm_vcpu *vcpu)
5130 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5132 kvm_mmu_invlpg(vcpu, exit_qualification);
5133 return kvm_skip_emulated_instruction(vcpu);
5136 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5140 err = kvm_rdpmc(vcpu);
5141 return kvm_complete_insn_gp(vcpu, err);
5144 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5146 return kvm_emulate_wbinvd(vcpu);
5149 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5151 u64 new_bv = kvm_read_edx_eax(vcpu);
5152 u32 index = kvm_rcx_read(vcpu);
5154 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5155 return kvm_skip_emulated_instruction(vcpu);
5159 static int handle_apic_access(struct kvm_vcpu *vcpu)
5161 if (likely(fasteoi)) {
5162 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5163 int access_type, offset;
5165 access_type = exit_qualification & APIC_ACCESS_TYPE;
5166 offset = exit_qualification & APIC_ACCESS_OFFSET;
5168 * Sane guest uses MOV to write EOI, with written value
5169 * not cared. So make a short-circuit here by avoiding
5170 * heavy instruction emulation.
5172 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5173 (offset == APIC_EOI)) {
5174 kvm_lapic_set_eoi(vcpu);
5175 return kvm_skip_emulated_instruction(vcpu);
5178 return kvm_emulate_instruction(vcpu, 0);
5181 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5183 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5184 int vector = exit_qualification & 0xff;
5186 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5187 kvm_apic_set_eoi_accelerated(vcpu, vector);
5191 static int handle_apic_write(struct kvm_vcpu *vcpu)
5193 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5194 u32 offset = exit_qualification & 0xfff;
5196 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5197 kvm_apic_write_nodecode(vcpu, offset);
5201 static int handle_task_switch(struct kvm_vcpu *vcpu)
5203 struct vcpu_vmx *vmx = to_vmx(vcpu);
5204 unsigned long exit_qualification;
5205 bool has_error_code = false;
5208 int reason, type, idt_v, idt_index;
5210 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5211 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5212 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5214 exit_qualification = vmx_get_exit_qual(vcpu);
5216 reason = (u32)exit_qualification >> 30;
5217 if (reason == TASK_SWITCH_GATE && idt_v) {
5219 case INTR_TYPE_NMI_INTR:
5220 vcpu->arch.nmi_injected = false;
5221 vmx_set_nmi_mask(vcpu, true);
5223 case INTR_TYPE_EXT_INTR:
5224 case INTR_TYPE_SOFT_INTR:
5225 kvm_clear_interrupt_queue(vcpu);
5227 case INTR_TYPE_HARD_EXCEPTION:
5228 if (vmx->idt_vectoring_info &
5229 VECTORING_INFO_DELIVER_CODE_MASK) {
5230 has_error_code = true;
5232 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5235 case INTR_TYPE_SOFT_EXCEPTION:
5236 kvm_clear_exception_queue(vcpu);
5242 tss_selector = exit_qualification;
5244 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5245 type != INTR_TYPE_EXT_INTR &&
5246 type != INTR_TYPE_NMI_INTR))
5247 WARN_ON(!skip_emulated_instruction(vcpu));
5250 * TODO: What about debug traps on tss switch?
5251 * Are we supposed to inject them and update dr6?
5253 return kvm_task_switch(vcpu, tss_selector,
5254 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5255 reason, has_error_code, error_code);
5258 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5260 unsigned long exit_qualification;
5264 exit_qualification = vmx_get_exit_qual(vcpu);
5267 * EPT violation happened while executing iret from NMI,
5268 * "blocked by NMI" bit has to be set before next VM entry.
5269 * There are errata that may cause this bit to not be set:
5272 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5274 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5275 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5277 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5278 trace_kvm_page_fault(gpa, exit_qualification);
5280 /* Is it a read fault? */
5281 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5282 ? PFERR_USER_MASK : 0;
5283 /* Is it a write fault? */
5284 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5285 ? PFERR_WRITE_MASK : 0;
5286 /* Is it a fetch fault? */
5287 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5288 ? PFERR_FETCH_MASK : 0;
5289 /* ept page table entry is present? */
5290 error_code |= (exit_qualification &
5291 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5292 EPT_VIOLATION_EXECUTABLE))
5293 ? PFERR_PRESENT_MASK : 0;
5295 error_code |= (exit_qualification & 0x100) != 0 ?
5296 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5298 vcpu->arch.exit_qualification = exit_qualification;
5301 * Check that the GPA doesn't exceed physical memory limits, as that is
5302 * a guest page fault. We have to emulate the instruction here, because
5303 * if the illegal address is that of a paging structure, then
5304 * EPT_VIOLATION_ACC_WRITE bit is set. Alternatively, if supported we
5305 * would also use advanced VM-exit information for EPT violations to
5306 * reconstruct the page fault error code.
5308 if (unlikely(kvm_mmu_is_illegal_gpa(vcpu, gpa)))
5309 return kvm_emulate_instruction(vcpu, 0);
5311 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5314 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5319 * A nested guest cannot optimize MMIO vmexits, because we have an
5320 * nGPA here instead of the required GPA.
5322 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5323 if (!is_guest_mode(vcpu) &&
5324 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5325 trace_kvm_fast_mmio(gpa);
5326 return kvm_skip_emulated_instruction(vcpu);
5329 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5332 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5334 WARN_ON_ONCE(!enable_vnmi);
5335 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5336 ++vcpu->stat.nmi_window_exits;
5337 kvm_make_request(KVM_REQ_EVENT, vcpu);
5342 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5344 struct vcpu_vmx *vmx = to_vmx(vcpu);
5345 bool intr_window_requested;
5346 unsigned count = 130;
5348 intr_window_requested = exec_controls_get(vmx) &
5349 CPU_BASED_INTR_WINDOW_EXITING;
5351 while (vmx->emulation_required && count-- != 0) {
5352 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5353 return handle_interrupt_window(&vmx->vcpu);
5355 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5358 if (!kvm_emulate_instruction(vcpu, 0))
5361 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5362 vcpu->arch.exception.pending) {
5363 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5364 vcpu->run->internal.suberror =
5365 KVM_INTERNAL_ERROR_EMULATION;
5366 vcpu->run->internal.ndata = 0;
5370 if (vcpu->arch.halt_request) {
5371 vcpu->arch.halt_request = 0;
5372 return kvm_vcpu_halt(vcpu);
5376 * Note, return 1 and not 0, vcpu_run() will invoke
5377 * xfer_to_guest_mode() which will create a proper return
5380 if (__xfer_to_guest_mode_work_pending())
5387 static void grow_ple_window(struct kvm_vcpu *vcpu)
5389 struct vcpu_vmx *vmx = to_vmx(vcpu);
5390 unsigned int old = vmx->ple_window;
5392 vmx->ple_window = __grow_ple_window(old, ple_window,
5396 if (vmx->ple_window != old) {
5397 vmx->ple_window_dirty = true;
5398 trace_kvm_ple_window_update(vcpu->vcpu_id,
5399 vmx->ple_window, old);
5403 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5405 struct vcpu_vmx *vmx = to_vmx(vcpu);
5406 unsigned int old = vmx->ple_window;
5408 vmx->ple_window = __shrink_ple_window(old, ple_window,
5412 if (vmx->ple_window != old) {
5413 vmx->ple_window_dirty = true;
5414 trace_kvm_ple_window_update(vcpu->vcpu_id,
5415 vmx->ple_window, old);
5420 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5422 static void wakeup_handler(void)
5424 struct kvm_vcpu *vcpu;
5425 int cpu = smp_processor_id();
5427 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5428 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5429 blocked_vcpu_list) {
5430 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5432 if (pi_test_on(pi_desc) == 1)
5433 kvm_vcpu_kick(vcpu);
5435 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5438 static void vmx_enable_tdp(void)
5440 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5441 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5442 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5443 0ull, VMX_EPT_EXECUTABLE_MASK,
5444 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5445 VMX_EPT_RWX_MASK, 0ull);
5447 ept_set_mmio_spte_mask();
5451 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5452 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5454 static int handle_pause(struct kvm_vcpu *vcpu)
5456 if (!kvm_pause_in_guest(vcpu->kvm))
5457 grow_ple_window(vcpu);
5460 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5461 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5462 * never set PAUSE_EXITING and just set PLE if supported,
5463 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5465 kvm_vcpu_on_spin(vcpu, true);
5466 return kvm_skip_emulated_instruction(vcpu);
5469 static int handle_nop(struct kvm_vcpu *vcpu)
5471 return kvm_skip_emulated_instruction(vcpu);
5474 static int handle_mwait(struct kvm_vcpu *vcpu)
5476 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5477 return handle_nop(vcpu);
5480 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5482 kvm_queue_exception(vcpu, UD_VECTOR);
5486 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5491 static int handle_monitor(struct kvm_vcpu *vcpu)
5493 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5494 return handle_nop(vcpu);
5497 static int handle_invpcid(struct kvm_vcpu *vcpu)
5499 u32 vmx_instruction_info;
5507 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5508 kvm_queue_exception(vcpu, UD_VECTOR);
5512 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5513 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5516 kvm_inject_gp(vcpu, 0);
5520 /* According to the Intel instruction reference, the memory operand
5521 * is read even if it isn't needed (e.g., for type==all)
5523 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5524 vmx_instruction_info, false,
5525 sizeof(operand), &gva))
5528 return kvm_handle_invpcid(vcpu, type, gva);
5531 static int handle_pml_full(struct kvm_vcpu *vcpu)
5533 unsigned long exit_qualification;
5535 trace_kvm_pml_full(vcpu->vcpu_id);
5537 exit_qualification = vmx_get_exit_qual(vcpu);
5540 * PML buffer FULL happened while executing iret from NMI,
5541 * "blocked by NMI" bit has to be set before next VM entry.
5543 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5545 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5546 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5547 GUEST_INTR_STATE_NMI);
5550 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5551 * here.., and there's no userspace involvement needed for PML.
5556 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5558 struct vcpu_vmx *vmx = to_vmx(vcpu);
5560 if (!vmx->req_immediate_exit &&
5561 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5562 kvm_lapic_expired_hv_timer(vcpu);
5563 return EXIT_FASTPATH_REENTER_GUEST;
5566 return EXIT_FASTPATH_NONE;
5569 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5571 handle_fastpath_preemption_timer(vcpu);
5576 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5577 * are overwritten by nested_vmx_setup() when nested=1.
5579 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5581 kvm_queue_exception(vcpu, UD_VECTOR);
5585 static int handle_encls(struct kvm_vcpu *vcpu)
5588 * SGX virtualization is not yet supported. There is no software
5589 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5590 * to prevent the guest from executing ENCLS.
5592 kvm_queue_exception(vcpu, UD_VECTOR);
5597 * The exit handlers return 1 if the exit was handled fully and guest execution
5598 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5599 * to be done to userspace and return 0.
5601 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5602 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5603 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5604 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5605 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5606 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5607 [EXIT_REASON_CR_ACCESS] = handle_cr,
5608 [EXIT_REASON_DR_ACCESS] = handle_dr,
5609 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5610 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5611 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
5612 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
5613 [EXIT_REASON_HLT] = kvm_emulate_halt,
5614 [EXIT_REASON_INVD] = handle_invd,
5615 [EXIT_REASON_INVLPG] = handle_invlpg,
5616 [EXIT_REASON_RDPMC] = handle_rdpmc,
5617 [EXIT_REASON_VMCALL] = handle_vmcall,
5618 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5619 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5620 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5621 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5622 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5623 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5624 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5625 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5626 [EXIT_REASON_VMON] = handle_vmx_instruction,
5627 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5628 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5629 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5630 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5631 [EXIT_REASON_WBINVD] = handle_wbinvd,
5632 [EXIT_REASON_XSETBV] = handle_xsetbv,
5633 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5634 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5635 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5636 [EXIT_REASON_LDTR_TR] = handle_desc,
5637 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5638 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5639 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5640 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5641 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5642 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5643 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5644 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5645 [EXIT_REASON_RDRAND] = handle_invalid_op,
5646 [EXIT_REASON_RDSEED] = handle_invalid_op,
5647 [EXIT_REASON_PML_FULL] = handle_pml_full,
5648 [EXIT_REASON_INVPCID] = handle_invpcid,
5649 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5650 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5651 [EXIT_REASON_ENCLS] = handle_encls,
5654 static const int kvm_vmx_max_exit_handlers =
5655 ARRAY_SIZE(kvm_vmx_exit_handlers);
5657 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5659 *info1 = vmx_get_exit_qual(vcpu);
5660 *info2 = vmx_get_intr_info(vcpu);
5663 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5666 __free_page(vmx->pml_pg);
5671 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5673 struct vcpu_vmx *vmx = to_vmx(vcpu);
5677 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5679 /* Do nothing if PML buffer is empty */
5680 if (pml_idx == (PML_ENTITY_NUM - 1))
5683 /* PML index always points to next available PML buffer entity */
5684 if (pml_idx >= PML_ENTITY_NUM)
5689 pml_buf = page_address(vmx->pml_pg);
5690 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5693 gpa = pml_buf[pml_idx];
5694 WARN_ON(gpa & (PAGE_SIZE - 1));
5695 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5698 /* reset PML index */
5699 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5703 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5704 * Called before reporting dirty_bitmap to userspace.
5706 static void kvm_flush_pml_buffers(struct kvm *kvm)
5709 struct kvm_vcpu *vcpu;
5711 * We only need to kick vcpu out of guest mode here, as PML buffer
5712 * is flushed at beginning of all VMEXITs, and it's obvious that only
5713 * vcpus running in guest are possible to have unflushed GPAs in PML
5716 kvm_for_each_vcpu(i, vcpu, kvm)
5717 kvm_vcpu_kick(vcpu);
5720 static void vmx_dump_sel(char *name, uint32_t sel)
5722 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5723 name, vmcs_read16(sel),
5724 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5725 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5726 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5729 static void vmx_dump_dtsel(char *name, uint32_t limit)
5731 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5732 name, vmcs_read32(limit),
5733 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5736 void dump_vmcs(void)
5738 u32 vmentry_ctl, vmexit_ctl;
5739 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5743 if (!dump_invalid_vmcs) {
5744 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5748 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5749 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5750 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5751 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5752 cr4 = vmcs_readl(GUEST_CR4);
5753 efer = vmcs_read64(GUEST_IA32_EFER);
5754 secondary_exec_control = 0;
5755 if (cpu_has_secondary_exec_ctrls())
5756 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5758 pr_err("*** Guest State ***\n");
5759 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5760 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5761 vmcs_readl(CR0_GUEST_HOST_MASK));
5762 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5763 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5764 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5765 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5766 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5768 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5769 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5770 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5771 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5773 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5774 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5775 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5776 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5777 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5778 vmcs_readl(GUEST_SYSENTER_ESP),
5779 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5780 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5781 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5782 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5783 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5784 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5785 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5786 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5787 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5788 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5789 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5790 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5791 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5792 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5793 efer, vmcs_read64(GUEST_IA32_PAT));
5794 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5795 vmcs_read64(GUEST_IA32_DEBUGCTL),
5796 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5797 if (cpu_has_load_perf_global_ctrl() &&
5798 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5799 pr_err("PerfGlobCtl = 0x%016llx\n",
5800 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5801 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5802 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5803 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5804 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5805 vmcs_read32(GUEST_ACTIVITY_STATE));
5806 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5807 pr_err("InterruptStatus = %04x\n",
5808 vmcs_read16(GUEST_INTR_STATUS));
5810 pr_err("*** Host State ***\n");
5811 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5812 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5813 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5814 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5815 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5816 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5817 vmcs_read16(HOST_TR_SELECTOR));
5818 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5819 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5820 vmcs_readl(HOST_TR_BASE));
5821 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5822 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5823 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5824 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5825 vmcs_readl(HOST_CR4));
5826 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5827 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5828 vmcs_read32(HOST_IA32_SYSENTER_CS),
5829 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5830 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5831 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5832 vmcs_read64(HOST_IA32_EFER),
5833 vmcs_read64(HOST_IA32_PAT));
5834 if (cpu_has_load_perf_global_ctrl() &&
5835 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5836 pr_err("PerfGlobCtl = 0x%016llx\n",
5837 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5839 pr_err("*** Control State ***\n");
5840 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5841 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5842 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5843 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5844 vmcs_read32(EXCEPTION_BITMAP),
5845 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5846 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5847 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5848 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5849 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5850 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5851 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5852 vmcs_read32(VM_EXIT_INTR_INFO),
5853 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5854 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5855 pr_err(" reason=%08x qualification=%016lx\n",
5856 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5857 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5858 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5859 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5860 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5861 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5862 pr_err("TSC Multiplier = 0x%016llx\n",
5863 vmcs_read64(TSC_MULTIPLIER));
5864 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5865 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5866 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5867 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5869 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5870 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5871 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5872 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5874 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5875 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5876 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5877 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5878 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5879 pr_err("PLE Gap=%08x Window=%08x\n",
5880 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5881 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5882 pr_err("Virtual processor ID = 0x%04x\n",
5883 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5887 * The guest has exited. See if we can fix it or if we need userspace
5890 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5892 struct vcpu_vmx *vmx = to_vmx(vcpu);
5893 u32 exit_reason = vmx->exit_reason;
5894 u32 vectoring_info = vmx->idt_vectoring_info;
5897 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5898 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5899 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5900 * mode as if vcpus is in root mode, the PML buffer must has been
5904 vmx_flush_pml_buffer(vcpu);
5907 * We should never reach this point with a pending nested VM-Enter, and
5908 * more specifically emulation of L2 due to invalid guest state (see
5909 * below) should never happen as that means we incorrectly allowed a
5910 * nested VM-Enter with an invalid vmcs12.
5912 WARN_ON_ONCE(vmx->nested.nested_run_pending);
5914 /* If guest state is invalid, start emulating */
5915 if (vmx->emulation_required)
5916 return handle_invalid_guest_state(vcpu);
5918 if (is_guest_mode(vcpu)) {
5920 * The host physical addresses of some pages of guest memory
5921 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5922 * Page). The CPU may write to these pages via their host
5923 * physical address while L2 is running, bypassing any
5924 * address-translation-based dirty tracking (e.g. EPT write
5927 * Mark them dirty on every exit from L2 to prevent them from
5928 * getting out of sync with dirty tracking.
5930 nested_mark_vmcs12_pages_dirty(vcpu);
5932 if (nested_vmx_reflect_vmexit(vcpu))
5936 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5938 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5939 vcpu->run->fail_entry.hardware_entry_failure_reason
5941 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5945 if (unlikely(vmx->fail)) {
5947 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5948 vcpu->run->fail_entry.hardware_entry_failure_reason
5949 = vmcs_read32(VM_INSTRUCTION_ERROR);
5950 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5956 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5957 * delivery event since it indicates guest is accessing MMIO.
5958 * The vm-exit can be triggered again after return to guest that
5959 * will cause infinite loop.
5961 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5962 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5963 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5964 exit_reason != EXIT_REASON_PML_FULL &&
5965 exit_reason != EXIT_REASON_APIC_ACCESS &&
5966 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5967 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5968 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5969 vcpu->run->internal.ndata = 3;
5970 vcpu->run->internal.data[0] = vectoring_info;
5971 vcpu->run->internal.data[1] = exit_reason;
5972 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5973 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5974 vcpu->run->internal.ndata++;
5975 vcpu->run->internal.data[3] =
5976 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5978 vcpu->run->internal.data[vcpu->run->internal.ndata++] =
5979 vcpu->arch.last_vmentry_cpu;
5983 if (unlikely(!enable_vnmi &&
5984 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5985 if (!vmx_interrupt_blocked(vcpu)) {
5986 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5987 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5988 vcpu->arch.nmi_pending) {
5990 * This CPU don't support us in finding the end of an
5991 * NMI-blocked window if the guest runs with IRQs
5992 * disabled. So we pull the trigger after 1 s of
5993 * futile waiting, but inform the user about this.
5995 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5996 "state on VCPU %d after 1 s timeout\n",
5997 __func__, vcpu->vcpu_id);
5998 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6002 if (exit_fastpath != EXIT_FASTPATH_NONE)
6005 if (exit_reason >= kvm_vmx_max_exit_handlers)
6006 goto unexpected_vmexit;
6007 #ifdef CONFIG_RETPOLINE
6008 if (exit_reason == EXIT_REASON_MSR_WRITE)
6009 return kvm_emulate_wrmsr(vcpu);
6010 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
6011 return handle_preemption_timer(vcpu);
6012 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
6013 return handle_interrupt_window(vcpu);
6014 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6015 return handle_external_interrupt(vcpu);
6016 else if (exit_reason == EXIT_REASON_HLT)
6017 return kvm_emulate_halt(vcpu);
6018 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
6019 return handle_ept_misconfig(vcpu);
6022 exit_reason = array_index_nospec(exit_reason,
6023 kvm_vmx_max_exit_handlers);
6024 if (!kvm_vmx_exit_handlers[exit_reason])
6025 goto unexpected_vmexit;
6027 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6030 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
6032 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6033 vcpu->run->internal.suberror =
6034 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6035 vcpu->run->internal.ndata = 2;
6036 vcpu->run->internal.data[0] = exit_reason;
6037 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6042 * Software based L1D cache flush which is used when microcode providing
6043 * the cache control MSR is not loaded.
6045 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6046 * flush it is required to read in 64 KiB because the replacement algorithm
6047 * is not exactly LRU. This could be sized at runtime via topology
6048 * information but as all relevant affected CPUs have 32KiB L1D cache size
6049 * there is no point in doing so.
6051 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6053 int size = PAGE_SIZE << L1D_CACHE_ORDER;
6056 * This code is only executed when the the flush mode is 'cond' or
6059 if (static_branch_likely(&vmx_l1d_flush_cond)) {
6063 * Clear the per-vcpu flush bit, it gets set again
6064 * either from vcpu_run() or from one of the unsafe
6067 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6068 vcpu->arch.l1tf_flush_l1d = false;
6071 * Clear the per-cpu flush bit, it gets set again from
6072 * the interrupt handlers.
6074 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6075 kvm_clear_cpu_l1tf_flush_l1d();
6081 vcpu->stat.l1d_flush++;
6083 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6084 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6089 /* First ensure the pages are in the TLB */
6090 "xorl %%eax, %%eax\n"
6091 ".Lpopulate_tlb:\n\t"
6092 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6093 "addl $4096, %%eax\n\t"
6094 "cmpl %%eax, %[size]\n\t"
6095 "jne .Lpopulate_tlb\n\t"
6096 "xorl %%eax, %%eax\n\t"
6098 /* Now fill the cache */
6099 "xorl %%eax, %%eax\n"
6101 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6102 "addl $64, %%eax\n\t"
6103 "cmpl %%eax, %[size]\n\t"
6104 "jne .Lfill_cache\n\t"
6106 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6108 : "eax", "ebx", "ecx", "edx");
6111 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6113 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6116 if (is_guest_mode(vcpu) &&
6117 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6120 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6121 if (is_guest_mode(vcpu))
6122 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6124 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6127 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6129 struct vcpu_vmx *vmx = to_vmx(vcpu);
6130 u32 sec_exec_control;
6132 if (!lapic_in_kernel(vcpu))
6135 if (!flexpriority_enabled &&
6136 !cpu_has_vmx_virtualize_x2apic_mode())
6139 /* Postpone execution until vmcs01 is the current VMCS. */
6140 if (is_guest_mode(vcpu)) {
6141 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6145 sec_exec_control = secondary_exec_controls_get(vmx);
6146 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6147 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6149 switch (kvm_get_apic_mode(vcpu)) {
6150 case LAPIC_MODE_INVALID:
6151 WARN_ONCE(true, "Invalid local APIC state");
6152 case LAPIC_MODE_DISABLED:
6154 case LAPIC_MODE_XAPIC:
6155 if (flexpriority_enabled) {
6157 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6158 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6161 * Flush the TLB, reloading the APIC access page will
6162 * only do so if its physical address has changed, but
6163 * the guest may have inserted a non-APIC mapping into
6164 * the TLB while the APIC access page was disabled.
6166 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6169 case LAPIC_MODE_X2APIC:
6170 if (cpu_has_vmx_virtualize_x2apic_mode())
6172 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6175 secondary_exec_controls_set(vmx, sec_exec_control);
6177 vmx_update_msr_bitmap(vcpu);
6180 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6184 /* Defer reload until vmcs01 is the current VMCS. */
6185 if (is_guest_mode(vcpu)) {
6186 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6190 if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6191 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6194 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6195 if (is_error_page(page))
6198 vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6199 vmx_flush_tlb_current(vcpu);
6202 * Do not pin apic access page in memory, the MMU notifier
6203 * will call us again if it is migrated or swapped out.
6208 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6216 status = vmcs_read16(GUEST_INTR_STATUS);
6218 if (max_isr != old) {
6220 status |= max_isr << 8;
6221 vmcs_write16(GUEST_INTR_STATUS, status);
6225 static void vmx_set_rvi(int vector)
6233 status = vmcs_read16(GUEST_INTR_STATUS);
6234 old = (u8)status & 0xff;
6235 if ((u8)vector != old) {
6237 status |= (u8)vector;
6238 vmcs_write16(GUEST_INTR_STATUS, status);
6242 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6245 * When running L2, updating RVI is only relevant when
6246 * vmcs12 virtual-interrupt-delivery enabled.
6247 * However, it can be enabled only when L1 also
6248 * intercepts external-interrupts and in that case
6249 * we should not update vmcs02 RVI but instead intercept
6250 * interrupt. Therefore, do nothing when running L2.
6252 if (!is_guest_mode(vcpu))
6253 vmx_set_rvi(max_irr);
6256 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6258 struct vcpu_vmx *vmx = to_vmx(vcpu);
6260 bool max_irr_updated;
6262 WARN_ON(!vcpu->arch.apicv_active);
6263 if (pi_test_on(&vmx->pi_desc)) {
6264 pi_clear_on(&vmx->pi_desc);
6266 * IOMMU can write to PID.ON, so the barrier matters even on UP.
6267 * But on x86 this is just a compiler barrier anyway.
6269 smp_mb__after_atomic();
6271 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6274 * If we are running L2 and L1 has a new pending interrupt
6275 * which can be injected, we should re-evaluate
6276 * what should be done with this new L1 interrupt.
6277 * If L1 intercepts external-interrupts, we should
6278 * exit from L2 to L1. Otherwise, interrupt should be
6279 * delivered directly to L2.
6281 if (is_guest_mode(vcpu) && max_irr_updated) {
6282 if (nested_exit_on_intr(vcpu))
6283 kvm_vcpu_exiting_guest_mode(vcpu);
6285 kvm_make_request(KVM_REQ_EVENT, vcpu);
6288 max_irr = kvm_lapic_find_highest_irr(vcpu);
6290 vmx_hwapic_irr_update(vcpu, max_irr);
6294 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6296 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6298 return pi_test_on(pi_desc) ||
6299 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6302 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6304 if (!kvm_vcpu_apicv_active(vcpu))
6307 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6308 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6309 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6310 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6313 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6315 struct vcpu_vmx *vmx = to_vmx(vcpu);
6317 pi_clear_on(&vmx->pi_desc);
6318 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6321 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6323 u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6325 /* if exit due to PF check for async PF */
6326 if (is_page_fault(intr_info)) {
6327 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6328 /* Handle machine checks before interrupts are enabled */
6329 } else if (is_machine_check(intr_info)) {
6330 kvm_machine_check();
6331 /* We need to handle NMIs before interrupts are enabled */
6332 } else if (is_nmi(intr_info)) {
6333 kvm_before_interrupt(&vmx->vcpu);
6335 kvm_after_interrupt(&vmx->vcpu);
6339 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6341 unsigned int vector;
6342 unsigned long entry;
6343 #ifdef CONFIG_X86_64
6347 u32 intr_info = vmx_get_intr_info(vcpu);
6349 if (WARN_ONCE(!is_external_intr(intr_info),
6350 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6353 vector = intr_info & INTR_INFO_VECTOR_MASK;
6354 desc = (gate_desc *)host_idt_base + vector;
6355 entry = gate_offset(desc);
6357 kvm_before_interrupt(vcpu);
6360 #ifdef CONFIG_X86_64
6361 "mov %%rsp, %[sp]\n\t"
6362 "and $-16, %%rsp\n\t"
6370 #ifdef CONFIG_X86_64
6375 [thunk_target]"r"(entry),
6376 #ifdef CONFIG_X86_64
6377 [ss]"i"(__KERNEL_DS),
6379 [cs]"i"(__KERNEL_CS)
6382 kvm_after_interrupt(vcpu);
6384 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6386 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6388 struct vcpu_vmx *vmx = to_vmx(vcpu);
6390 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6391 handle_external_interrupt_irqoff(vcpu);
6392 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6393 handle_exception_nmi_irqoff(vmx);
6396 static bool vmx_has_emulated_msr(u32 index)
6399 case MSR_IA32_SMBASE:
6401 * We cannot do SMM unless we can run the guest in big
6404 return enable_unrestricted_guest || emulate_invalid_guest_state;
6405 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6407 case MSR_AMD64_VIRT_SPEC_CTRL:
6408 /* This is AMD only. */
6415 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6420 bool idtv_info_valid;
6422 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6425 if (vmx->loaded_vmcs->nmi_known_unmasked)
6428 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6429 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6430 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6432 * SDM 3: 27.7.1.2 (September 2008)
6433 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6434 * a guest IRET fault.
6435 * SDM 3: 23.2.2 (September 2008)
6436 * Bit 12 is undefined in any of the following cases:
6437 * If the VM exit sets the valid bit in the IDT-vectoring
6438 * information field.
6439 * If the VM exit is due to a double fault.
6441 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6442 vector != DF_VECTOR && !idtv_info_valid)
6443 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6444 GUEST_INTR_STATE_NMI);
6446 vmx->loaded_vmcs->nmi_known_unmasked =
6447 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6448 & GUEST_INTR_STATE_NMI);
6449 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6450 vmx->loaded_vmcs->vnmi_blocked_time +=
6451 ktime_to_ns(ktime_sub(ktime_get(),
6452 vmx->loaded_vmcs->entry_time));
6455 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6456 u32 idt_vectoring_info,
6457 int instr_len_field,
6458 int error_code_field)
6462 bool idtv_info_valid;
6464 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6466 vcpu->arch.nmi_injected = false;
6467 kvm_clear_exception_queue(vcpu);
6468 kvm_clear_interrupt_queue(vcpu);
6470 if (!idtv_info_valid)
6473 kvm_make_request(KVM_REQ_EVENT, vcpu);
6475 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6476 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6479 case INTR_TYPE_NMI_INTR:
6480 vcpu->arch.nmi_injected = true;
6482 * SDM 3: 27.7.1.2 (September 2008)
6483 * Clear bit "block by NMI" before VM entry if a NMI
6486 vmx_set_nmi_mask(vcpu, false);
6488 case INTR_TYPE_SOFT_EXCEPTION:
6489 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6491 case INTR_TYPE_HARD_EXCEPTION:
6492 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6493 u32 err = vmcs_read32(error_code_field);
6494 kvm_requeue_exception_e(vcpu, vector, err);
6496 kvm_requeue_exception(vcpu, vector);
6498 case INTR_TYPE_SOFT_INTR:
6499 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6501 case INTR_TYPE_EXT_INTR:
6502 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6509 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6511 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6512 VM_EXIT_INSTRUCTION_LEN,
6513 IDT_VECTORING_ERROR_CODE);
6516 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6518 __vmx_complete_interrupts(vcpu,
6519 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6520 VM_ENTRY_INSTRUCTION_LEN,
6521 VM_ENTRY_EXCEPTION_ERROR_CODE);
6523 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6526 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6529 struct perf_guest_switch_msr *msrs;
6531 msrs = perf_guest_get_msrs(&nr_msrs);
6536 for (i = 0; i < nr_msrs; i++)
6537 if (msrs[i].host == msrs[i].guest)
6538 clear_atomic_switch_msr(vmx, msrs[i].msr);
6540 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6541 msrs[i].host, false);
6544 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6546 struct vcpu_vmx *vmx = to_vmx(vcpu);
6550 if (vmx->req_immediate_exit) {
6551 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6552 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6553 } else if (vmx->hv_deadline_tsc != -1) {
6555 if (vmx->hv_deadline_tsc > tscl)
6556 /* set_hv_timer ensures the delta fits in 32-bits */
6557 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6558 cpu_preemption_timer_multi);
6562 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6563 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6564 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6565 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6566 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6570 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6572 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6573 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6574 vmcs_writel(HOST_RSP, host_rsp);
6578 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6580 switch (to_vmx(vcpu)->exit_reason) {
6581 case EXIT_REASON_MSR_WRITE:
6582 return handle_fastpath_set_msr_irqoff(vcpu);
6583 case EXIT_REASON_PREEMPTION_TIMER:
6584 return handle_fastpath_preemption_timer(vcpu);
6586 return EXIT_FASTPATH_NONE;
6590 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6592 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6593 struct vcpu_vmx *vmx)
6596 * VMENTER enables interrupts (host state), but the kernel state is
6597 * interrupts disabled when this is invoked. Also tell RCU about
6598 * it. This is the same logic as for exit_to_user_mode().
6600 * This ensures that e.g. latency analysis on the host observes
6601 * guest mode as interrupt enabled.
6603 * guest_enter_irqoff() informs context tracking about the
6604 * transition to guest mode and if enabled adjusts RCU state
6607 instrumentation_begin();
6608 trace_hardirqs_on_prepare();
6609 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
6610 instrumentation_end();
6612 guest_enter_irqoff();
6613 lockdep_hardirqs_on(CALLER_ADDR0);
6615 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6616 if (static_branch_unlikely(&vmx_l1d_should_flush))
6617 vmx_l1d_flush(vcpu);
6618 else if (static_branch_unlikely(&mds_user_clear))
6619 mds_clear_cpu_buffers();
6621 if (vcpu->arch.cr2 != native_read_cr2())
6622 native_write_cr2(vcpu->arch.cr2);
6624 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6625 vmx->loaded_vmcs->launched);
6627 vcpu->arch.cr2 = native_read_cr2();
6630 * VMEXIT disables interrupts (host state), but tracing and lockdep
6631 * have them in state 'on' as recorded before entering guest mode.
6632 * Same as enter_from_user_mode().
6634 * guest_exit_irqoff() restores host context and reinstates RCU if
6635 * enabled and required.
6637 * This needs to be done before the below as native_read_msr()
6638 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
6639 * into world and some more.
6641 lockdep_hardirqs_off(CALLER_ADDR0);
6642 guest_exit_irqoff();
6644 instrumentation_begin();
6645 trace_hardirqs_off_finish();
6646 instrumentation_end();
6649 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6651 fastpath_t exit_fastpath;
6652 struct vcpu_vmx *vmx = to_vmx(vcpu);
6653 unsigned long cr3, cr4;
6656 /* Record the guest's net vcpu time for enforced NMI injections. */
6657 if (unlikely(!enable_vnmi &&
6658 vmx->loaded_vmcs->soft_vnmi_blocked))
6659 vmx->loaded_vmcs->entry_time = ktime_get();
6661 /* Don't enter VMX if guest state is invalid, let the exit handler
6662 start emulation until we arrive back to a valid state */
6663 if (vmx->emulation_required)
6664 return EXIT_FASTPATH_NONE;
6666 if (vmx->ple_window_dirty) {
6667 vmx->ple_window_dirty = false;
6668 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6672 * We did this in prepare_switch_to_guest, because it needs to
6673 * be within srcu_read_lock.
6675 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6677 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6678 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6679 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6680 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6682 cr3 = __get_current_cr3_fast();
6683 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6684 vmcs_writel(HOST_CR3, cr3);
6685 vmx->loaded_vmcs->host_state.cr3 = cr3;
6688 cr4 = cr4_read_shadow();
6689 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6690 vmcs_writel(HOST_CR4, cr4);
6691 vmx->loaded_vmcs->host_state.cr4 = cr4;
6694 /* When single-stepping over STI and MOV SS, we must clear the
6695 * corresponding interruptibility bits in the guest state. Otherwise
6696 * vmentry fails as it then expects bit 14 (BS) in pending debug
6697 * exceptions being set, but that's not correct for the guest debugging
6699 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6700 vmx_set_interrupt_shadow(vcpu, 0);
6702 kvm_load_guest_xsave_state(vcpu);
6704 pt_guest_enter(vmx);
6706 atomic_switch_perf_msrs(vmx);
6708 if (enable_preemption_timer)
6709 vmx_update_hv_timer(vcpu);
6711 kvm_wait_lapic_expire(vcpu);
6714 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6715 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6716 * is no need to worry about the conditional branch over the wrmsr
6717 * being speculatively taken.
6719 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6721 /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6722 vmx_vcpu_enter_exit(vcpu, vmx);
6725 * We do not use IBRS in the kernel. If this vCPU has used the
6726 * SPEC_CTRL MSR it may have left it on; save the value and
6727 * turn it off. This is much more efficient than blindly adding
6728 * it to the atomic save/restore list. Especially as the former
6729 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6731 * For non-nested case:
6732 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6736 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6739 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6740 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6742 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6744 /* All fields are clean at this point */
6745 if (static_branch_unlikely(&enable_evmcs))
6746 current_evmcs->hv_clean_fields |=
6747 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6749 if (static_branch_unlikely(&enable_evmcs))
6750 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6752 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6753 if (vmx->host_debugctlmsr)
6754 update_debugctlmsr(vmx->host_debugctlmsr);
6756 #ifndef CONFIG_X86_64
6758 * The sysexit path does not restore ds/es, so we must set them to
6759 * a reasonable value ourselves.
6761 * We can't defer this to vmx_prepare_switch_to_host() since that
6762 * function may be executed in interrupt context, which saves and
6763 * restore segments around it, nullifying its effect.
6765 loadsegment(ds, __USER_DS);
6766 loadsegment(es, __USER_DS);
6769 vmx_register_cache_reset(vcpu);
6773 kvm_load_host_xsave_state(vcpu);
6775 vmx->nested.nested_run_pending = 0;
6776 vmx->idt_vectoring_info = 0;
6778 if (unlikely(vmx->fail)) {
6779 vmx->exit_reason = 0xdead;
6780 return EXIT_FASTPATH_NONE;
6783 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6784 if (unlikely((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY))
6785 kvm_machine_check();
6787 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6789 if (unlikely(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6790 return EXIT_FASTPATH_NONE;
6792 vmx->loaded_vmcs->launched = 1;
6793 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6795 vmx_recover_nmi_blocking(vmx);
6796 vmx_complete_interrupts(vmx);
6798 if (is_guest_mode(vcpu))
6799 return EXIT_FASTPATH_NONE;
6801 exit_fastpath = vmx_exit_handlers_fastpath(vcpu);
6802 if (exit_fastpath == EXIT_FASTPATH_REENTER_GUEST) {
6803 if (!kvm_vcpu_exit_request(vcpu)) {
6805 * FIXME: this goto should be a loop in vcpu_enter_guest,
6806 * but it would incur the cost of a retpoline for now.
6807 * Revisit once static calls are available.
6809 if (vcpu->arch.apicv_active)
6810 vmx_sync_pir_to_irr(vcpu);
6813 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
6816 return exit_fastpath;
6819 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6821 struct vcpu_vmx *vmx = to_vmx(vcpu);
6824 vmx_destroy_pml_buffer(vmx);
6825 free_vpid(vmx->vpid);
6826 nested_vmx_free_vcpu(vcpu);
6827 free_loaded_vmcs(vmx->loaded_vmcs);
6830 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6832 struct vcpu_vmx *vmx;
6833 unsigned long *msr_bitmap;
6836 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6841 vmx->vpid = allocate_vpid();
6844 * If PML is turned on, failure on enabling PML just results in failure
6845 * of creating the vcpu, therefore we can simplify PML logic (by
6846 * avoiding dealing with cases, such as enabling PML partially on vcpus
6847 * for the guest), etc.
6850 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6855 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
6857 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6858 u32 index = vmx_msr_index[i];
6859 u32 data_low, data_high;
6862 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6864 if (wrmsr_safe(index, data_low, data_high) < 0)
6867 vmx->guest_msrs[j].index = i;
6868 vmx->guest_msrs[j].data = 0;
6870 case MSR_IA32_TSX_CTRL:
6872 * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6873 * let's avoid changing CPUID bits under the host
6876 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6879 vmx->guest_msrs[j].mask = -1ull;
6885 err = alloc_loaded_vmcs(&vmx->vmcs01);
6889 msr_bitmap = vmx->vmcs01.msr_bitmap;
6890 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6891 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6892 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6893 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6894 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6895 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6896 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6897 if (kvm_cstate_in_guest(vcpu->kvm)) {
6898 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6899 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6900 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6901 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6903 vmx->msr_bitmap_mode = 0;
6905 vmx->loaded_vmcs = &vmx->vmcs01;
6907 vmx_vcpu_load(vcpu, cpu);
6912 if (cpu_need_virtualize_apic_accesses(vcpu)) {
6913 err = alloc_apic_access_page(vcpu->kvm);
6918 if (enable_ept && !enable_unrestricted_guest) {
6919 err = init_rmode_identity_map(vcpu->kvm);
6925 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
6927 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6929 vmx->nested.posted_intr_nv = -1;
6930 vmx->nested.current_vmptr = -1ull;
6932 vcpu->arch.microcode_version = 0x100000000ULL;
6933 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6936 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6937 * or POSTED_INTR_WAKEUP_VECTOR.
6939 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6940 vmx->pi_desc.sn = 1;
6942 vmx->ept_pointer = INVALID_PAGE;
6947 free_loaded_vmcs(vmx->loaded_vmcs);
6949 vmx_destroy_pml_buffer(vmx);
6951 free_vpid(vmx->vpid);
6955 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6956 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6958 static int vmx_vm_init(struct kvm *kvm)
6960 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6963 kvm->arch.pause_in_guest = true;
6965 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6966 switch (l1tf_mitigation) {
6967 case L1TF_MITIGATION_OFF:
6968 case L1TF_MITIGATION_FLUSH_NOWARN:
6969 /* 'I explicitly don't care' is set */
6971 case L1TF_MITIGATION_FLUSH:
6972 case L1TF_MITIGATION_FLUSH_NOSMT:
6973 case L1TF_MITIGATION_FULL:
6975 * Warn upon starting the first VM in a potentially
6976 * insecure environment.
6978 if (sched_smt_active())
6979 pr_warn_once(L1TF_MSG_SMT);
6980 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6981 pr_warn_once(L1TF_MSG_L1D);
6983 case L1TF_MITIGATION_FULL_FORCE:
6984 /* Flush is enforced */
6988 kvm_apicv_init(kvm, enable_apicv);
6992 static int __init vmx_check_processor_compat(void)
6994 struct vmcs_config vmcs_conf;
6995 struct vmx_capability vmx_cap;
6997 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6998 !this_cpu_has(X86_FEATURE_VMX)) {
6999 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
7003 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
7006 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
7007 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7008 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7009 smp_processor_id());
7015 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7020 /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
7021 * memory aliases with conflicting memory types and sometimes MCEs.
7022 * We have to be careful as to what are honored and when.
7024 * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to
7025 * UC. The effective memory type is UC or WC depending on guest PAT.
7026 * This was historically the source of MCEs and we want to be
7029 * When there is no need to deal with noncoherent DMA (e.g., no VT-d
7030 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The
7031 * EPT memory type is set to WB. The effective memory type is forced
7034 * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The
7035 * EPT memory type is used to emulate guest CD/MTRR.
7039 cache = MTRR_TYPE_UNCACHABLE;
7043 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
7044 ipat = VMX_EPT_IPAT_BIT;
7045 cache = MTRR_TYPE_WRBACK;
7049 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
7050 ipat = VMX_EPT_IPAT_BIT;
7051 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
7052 cache = MTRR_TYPE_WRBACK;
7054 cache = MTRR_TYPE_UNCACHABLE;
7058 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
7061 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
7064 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
7067 * These bits in the secondary execution controls field
7068 * are dynamic, the others are mostly based on the hypervisor
7069 * architecture and the guest's CPUID. Do not touch the
7073 SECONDARY_EXEC_SHADOW_VMCS |
7074 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7075 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7076 SECONDARY_EXEC_DESC;
7078 u32 new_ctl = vmx->secondary_exec_control;
7079 u32 cur_ctl = secondary_exec_controls_get(vmx);
7081 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7085 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7086 * (indicating "allowed-1") if they are supported in the guest's CPUID.
7088 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7090 struct vcpu_vmx *vmx = to_vmx(vcpu);
7091 struct kvm_cpuid_entry2 *entry;
7093 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7094 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7096 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
7097 if (entry && (entry->_reg & (_cpuid_mask))) \
7098 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
7101 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7102 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME));
7103 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME));
7104 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC));
7105 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE));
7106 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE));
7107 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE));
7108 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE));
7109 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE));
7110 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR));
7111 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7112 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX));
7113 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX));
7114 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID));
7115 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE));
7117 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7118 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE));
7119 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP));
7120 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP));
7121 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU));
7122 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP));
7123 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57));
7125 #undef cr4_fixed1_update
7128 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7130 struct vcpu_vmx *vmx = to_vmx(vcpu);
7132 if (kvm_mpx_supported()) {
7133 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7136 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7137 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7139 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7140 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7145 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7147 struct vcpu_vmx *vmx = to_vmx(vcpu);
7148 struct kvm_cpuid_entry2 *best = NULL;
7151 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7152 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7155 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7156 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7157 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7158 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7161 /* Get the number of configurable Address Ranges for filtering */
7162 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7163 PT_CAP_num_address_ranges);
7165 /* Initialize and clear the no dependency bits */
7166 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7167 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7170 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7171 * will inject an #GP
7173 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7174 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7177 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7178 * PSBFreq can be set
7180 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7181 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7182 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7185 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7186 * MTCFreq can be set
7188 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7189 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7190 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7192 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7193 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7194 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7197 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7198 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7199 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7201 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7202 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7203 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7205 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7206 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7207 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7209 /* unmask address range configure area */
7210 for (i = 0; i < vmx->pt_desc.addr_range; i++)
7211 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7214 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7216 struct vcpu_vmx *vmx = to_vmx(vcpu);
7218 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7219 vcpu->arch.xsaves_enabled = false;
7221 if (cpu_has_secondary_exec_ctrls()) {
7222 vmx_compute_secondary_exec_control(vmx);
7223 vmcs_set_secondary_exec_control(vmx);
7226 if (nested_vmx_allowed(vcpu))
7227 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7228 FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7229 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7231 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7232 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7233 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7235 if (nested_vmx_allowed(vcpu)) {
7236 nested_vmx_cr_fixed1_bits_update(vcpu);
7237 nested_vmx_entry_exit_ctls_update(vcpu);
7240 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7241 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7242 update_intel_pt_cfg(vcpu);
7244 if (boot_cpu_has(X86_FEATURE_RTM)) {
7245 struct shared_msr_entry *msr;
7246 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7248 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7249 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7254 static __init void vmx_set_cpu_caps(void)
7260 kvm_cpu_cap_set(X86_FEATURE_VMX);
7263 if (kvm_mpx_supported())
7264 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7265 if (cpu_has_vmx_invpcid())
7266 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
7267 if (vmx_pt_mode_is_host_guest())
7268 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7270 if (vmx_umip_emulated())
7271 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7275 if (!vmx_xsaves_supported())
7276 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7278 /* CPUID 0x80000001 */
7279 if (!cpu_has_vmx_rdtscp())
7280 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7282 if (vmx_waitpkg_supported())
7283 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7286 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7288 to_vmx(vcpu)->req_immediate_exit = true;
7291 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7292 struct x86_instruction_info *info)
7294 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7295 unsigned short port;
7299 if (info->intercept == x86_intercept_in ||
7300 info->intercept == x86_intercept_ins) {
7301 port = info->src_val;
7302 size = info->dst_bytes;
7304 port = info->dst_val;
7305 size = info->src_bytes;
7309 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7310 * VM-exits depend on the 'unconditional IO exiting' VM-execution
7313 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7315 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7316 intercept = nested_cpu_has(vmcs12,
7317 CPU_BASED_UNCOND_IO_EXITING);
7319 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7321 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7322 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7325 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7326 struct x86_instruction_info *info,
7327 enum x86_intercept_stage stage,
7328 struct x86_exception *exception)
7330 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7332 switch (info->intercept) {
7334 * RDPID causes #UD if disabled through secondary execution controls.
7335 * Because it is marked as EmulateOnUD, we need to intercept it here.
7337 case x86_intercept_rdtscp:
7338 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7339 exception->vector = UD_VECTOR;
7340 exception->error_code_valid = false;
7341 return X86EMUL_PROPAGATE_FAULT;
7345 case x86_intercept_in:
7346 case x86_intercept_ins:
7347 case x86_intercept_out:
7348 case x86_intercept_outs:
7349 return vmx_check_intercept_io(vcpu, info);
7351 case x86_intercept_lgdt:
7352 case x86_intercept_lidt:
7353 case x86_intercept_lldt:
7354 case x86_intercept_ltr:
7355 case x86_intercept_sgdt:
7356 case x86_intercept_sidt:
7357 case x86_intercept_sldt:
7358 case x86_intercept_str:
7359 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7360 return X86EMUL_CONTINUE;
7362 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7365 /* TODO: check more intercepts... */
7370 return X86EMUL_UNHANDLEABLE;
7373 #ifdef CONFIG_X86_64
7374 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7375 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7376 u64 divisor, u64 *result)
7378 u64 low = a << shift, high = a >> (64 - shift);
7380 /* To avoid the overflow on divq */
7381 if (high >= divisor)
7384 /* Low hold the result, high hold rem which is discarded */
7385 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7386 "rm" (divisor), "0" (low), "1" (high));
7392 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7395 struct vcpu_vmx *vmx;
7396 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7397 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7401 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7402 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7403 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7404 ktimer->timer_advance_ns);
7406 if (delta_tsc > lapic_timer_advance_cycles)
7407 delta_tsc -= lapic_timer_advance_cycles;
7411 /* Convert to host delta tsc if tsc scaling is enabled */
7412 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7413 delta_tsc && u64_shl_div_u64(delta_tsc,
7414 kvm_tsc_scaling_ratio_frac_bits,
7415 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7419 * If the delta tsc can't fit in the 32 bit after the multi shift,
7420 * we can't use the preemption timer.
7421 * It's possible that it fits on later vmentries, but checking
7422 * on every vmentry is costly so we just use an hrtimer.
7424 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7427 vmx->hv_deadline_tsc = tscl + delta_tsc;
7428 *expired = !delta_tsc;
7432 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7434 to_vmx(vcpu)->hv_deadline_tsc = -1;
7438 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7440 if (!kvm_pause_in_guest(vcpu->kvm))
7441 shrink_ple_window(vcpu);
7444 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7445 struct kvm_memory_slot *slot)
7447 if (!kvm_dirty_log_manual_protect_and_init_set(kvm))
7448 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7449 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7452 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7453 struct kvm_memory_slot *slot)
7455 kvm_mmu_slot_set_dirty(kvm, slot);
7458 static void vmx_flush_log_dirty(struct kvm *kvm)
7460 kvm_flush_pml_buffers(kvm);
7463 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7464 struct kvm_memory_slot *memslot,
7465 gfn_t offset, unsigned long mask)
7467 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7470 static void __pi_post_block(struct kvm_vcpu *vcpu)
7472 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7473 struct pi_desc old, new;
7477 old.control = new.control = pi_desc->control;
7478 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7479 "Wakeup handler not enabled while the VCPU is blocked\n");
7481 dest = cpu_physical_id(vcpu->cpu);
7483 if (x2apic_enabled())
7486 new.ndst = (dest << 8) & 0xFF00;
7488 /* set 'NV' to 'notification vector' */
7489 new.nv = POSTED_INTR_VECTOR;
7490 } while (cmpxchg64(&pi_desc->control, old.control,
7491 new.control) != old.control);
7493 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7494 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7495 list_del(&vcpu->blocked_vcpu_list);
7496 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7497 vcpu->pre_pcpu = -1;
7502 * This routine does the following things for vCPU which is going
7503 * to be blocked if VT-d PI is enabled.
7504 * - Store the vCPU to the wakeup list, so when interrupts happen
7505 * we can find the right vCPU to wake up.
7506 * - Change the Posted-interrupt descriptor as below:
7507 * 'NDST' <-- vcpu->pre_pcpu
7508 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7509 * - If 'ON' is set during this process, which means at least one
7510 * interrupt is posted for this vCPU, we cannot block it, in
7511 * this case, return 1, otherwise, return 0.
7514 static int pi_pre_block(struct kvm_vcpu *vcpu)
7517 struct pi_desc old, new;
7518 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7520 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7521 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7522 !kvm_vcpu_apicv_active(vcpu))
7525 WARN_ON(irqs_disabled());
7526 local_irq_disable();
7527 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7528 vcpu->pre_pcpu = vcpu->cpu;
7529 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7530 list_add_tail(&vcpu->blocked_vcpu_list,
7531 &per_cpu(blocked_vcpu_on_cpu,
7533 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7537 old.control = new.control = pi_desc->control;
7539 WARN((pi_desc->sn == 1),
7540 "Warning: SN field of posted-interrupts "
7541 "is set before blocking\n");
7544 * Since vCPU can be preempted during this process,
7545 * vcpu->cpu could be different with pre_pcpu, we
7546 * need to set pre_pcpu as the destination of wakeup
7547 * notification event, then we can find the right vCPU
7548 * to wakeup in wakeup handler if interrupts happen
7549 * when the vCPU is in blocked state.
7551 dest = cpu_physical_id(vcpu->pre_pcpu);
7553 if (x2apic_enabled())
7556 new.ndst = (dest << 8) & 0xFF00;
7558 /* set 'NV' to 'wakeup vector' */
7559 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7560 } while (cmpxchg64(&pi_desc->control, old.control,
7561 new.control) != old.control);
7563 /* We should not block the vCPU if an interrupt is posted for it. */
7564 if (pi_test_on(pi_desc) == 1)
7565 __pi_post_block(vcpu);
7568 return (vcpu->pre_pcpu == -1);
7571 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7573 if (pi_pre_block(vcpu))
7576 if (kvm_lapic_hv_timer_in_use(vcpu))
7577 kvm_lapic_switch_to_sw_timer(vcpu);
7582 static void pi_post_block(struct kvm_vcpu *vcpu)
7584 if (vcpu->pre_pcpu == -1)
7587 WARN_ON(irqs_disabled());
7588 local_irq_disable();
7589 __pi_post_block(vcpu);
7593 static void vmx_post_block(struct kvm_vcpu *vcpu)
7595 if (kvm_x86_ops.set_hv_timer)
7596 kvm_lapic_switch_to_hv_timer(vcpu);
7598 pi_post_block(vcpu);
7602 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7605 * @host_irq: host irq of the interrupt
7606 * @guest_irq: gsi of the interrupt
7607 * @set: set or unset PI
7608 * returns 0 on success, < 0 on failure
7610 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7611 uint32_t guest_irq, bool set)
7613 struct kvm_kernel_irq_routing_entry *e;
7614 struct kvm_irq_routing_table *irq_rt;
7615 struct kvm_lapic_irq irq;
7616 struct kvm_vcpu *vcpu;
7617 struct vcpu_data vcpu_info;
7620 if (!kvm_arch_has_assigned_device(kvm) ||
7621 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7622 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7625 idx = srcu_read_lock(&kvm->irq_srcu);
7626 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7627 if (guest_irq >= irq_rt->nr_rt_entries ||
7628 hlist_empty(&irq_rt->map[guest_irq])) {
7629 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7630 guest_irq, irq_rt->nr_rt_entries);
7634 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7635 if (e->type != KVM_IRQ_ROUTING_MSI)
7638 * VT-d PI cannot support posting multicast/broadcast
7639 * interrupts to a vCPU, we still use interrupt remapping
7640 * for these kind of interrupts.
7642 * For lowest-priority interrupts, we only support
7643 * those with single CPU as the destination, e.g. user
7644 * configures the interrupts via /proc/irq or uses
7645 * irqbalance to make the interrupts single-CPU.
7647 * We will support full lowest-priority interrupt later.
7649 * In addition, we can only inject generic interrupts using
7650 * the PI mechanism, refuse to route others through it.
7653 kvm_set_msi_irq(kvm, e, &irq);
7654 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7655 !kvm_irq_is_postable(&irq)) {
7657 * Make sure the IRTE is in remapped mode if
7658 * we don't handle it in posted mode.
7660 ret = irq_set_vcpu_affinity(host_irq, NULL);
7663 "failed to back to remapped mode, irq: %u\n",
7671 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7672 vcpu_info.vector = irq.vector;
7674 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7675 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7678 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7680 ret = irq_set_vcpu_affinity(host_irq, NULL);
7683 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7691 srcu_read_unlock(&kvm->irq_srcu, idx);
7695 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7697 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7698 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7699 FEAT_CTL_LMCE_ENABLED;
7701 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7702 ~FEAT_CTL_LMCE_ENABLED;
7705 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7707 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7708 if (to_vmx(vcpu)->nested.nested_run_pending)
7710 return !is_smm(vcpu);
7713 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7715 struct vcpu_vmx *vmx = to_vmx(vcpu);
7717 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7718 if (vmx->nested.smm.guest_mode)
7719 nested_vmx_vmexit(vcpu, -1, 0, 0);
7721 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7722 vmx->nested.vmxon = false;
7723 vmx_clear_hlt(vcpu);
7727 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7729 struct vcpu_vmx *vmx = to_vmx(vcpu);
7732 if (vmx->nested.smm.vmxon) {
7733 vmx->nested.vmxon = true;
7734 vmx->nested.smm.vmxon = false;
7737 if (vmx->nested.smm.guest_mode) {
7738 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7742 vmx->nested.smm.guest_mode = false;
7747 static void enable_smi_window(struct kvm_vcpu *vcpu)
7749 /* RSM will cause a vmexit anyway. */
7752 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7757 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7759 return to_vmx(vcpu)->nested.vmxon;
7762 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7764 if (is_guest_mode(vcpu)) {
7765 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7767 if (hrtimer_try_to_cancel(timer) == 1)
7768 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7772 static void hardware_unsetup(void)
7775 nested_vmx_hardware_unsetup();
7780 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7782 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7783 BIT(APICV_INHIBIT_REASON_HYPERV);
7785 return supported & BIT(bit);
7788 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7789 .hardware_unsetup = hardware_unsetup,
7791 .hardware_enable = hardware_enable,
7792 .hardware_disable = hardware_disable,
7793 .cpu_has_accelerated_tpr = report_flexpriority,
7794 .has_emulated_msr = vmx_has_emulated_msr,
7796 .vm_size = sizeof(struct kvm_vmx),
7797 .vm_init = vmx_vm_init,
7799 .vcpu_create = vmx_create_vcpu,
7800 .vcpu_free = vmx_free_vcpu,
7801 .vcpu_reset = vmx_vcpu_reset,
7803 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7804 .vcpu_load = vmx_vcpu_load,
7805 .vcpu_put = vmx_vcpu_put,
7807 .update_exception_bitmap = update_exception_bitmap,
7808 .get_msr_feature = vmx_get_msr_feature,
7809 .get_msr = vmx_get_msr,
7810 .set_msr = vmx_set_msr,
7811 .get_segment_base = vmx_get_segment_base,
7812 .get_segment = vmx_get_segment,
7813 .set_segment = vmx_set_segment,
7814 .get_cpl = vmx_get_cpl,
7815 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7816 .set_cr0 = vmx_set_cr0,
7817 .set_cr4 = vmx_set_cr4,
7818 .set_efer = vmx_set_efer,
7819 .get_idt = vmx_get_idt,
7820 .set_idt = vmx_set_idt,
7821 .get_gdt = vmx_get_gdt,
7822 .set_gdt = vmx_set_gdt,
7823 .set_dr7 = vmx_set_dr7,
7824 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7825 .cache_reg = vmx_cache_reg,
7826 .get_rflags = vmx_get_rflags,
7827 .set_rflags = vmx_set_rflags,
7829 .tlb_flush_all = vmx_flush_tlb_all,
7830 .tlb_flush_current = vmx_flush_tlb_current,
7831 .tlb_flush_gva = vmx_flush_tlb_gva,
7832 .tlb_flush_guest = vmx_flush_tlb_guest,
7834 .run = vmx_vcpu_run,
7835 .handle_exit = vmx_handle_exit,
7836 .skip_emulated_instruction = vmx_skip_emulated_instruction,
7837 .update_emulated_instruction = vmx_update_emulated_instruction,
7838 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7839 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7840 .patch_hypercall = vmx_patch_hypercall,
7841 .set_irq = vmx_inject_irq,
7842 .set_nmi = vmx_inject_nmi,
7843 .queue_exception = vmx_queue_exception,
7844 .cancel_injection = vmx_cancel_injection,
7845 .interrupt_allowed = vmx_interrupt_allowed,
7846 .nmi_allowed = vmx_nmi_allowed,
7847 .get_nmi_mask = vmx_get_nmi_mask,
7848 .set_nmi_mask = vmx_set_nmi_mask,
7849 .enable_nmi_window = enable_nmi_window,
7850 .enable_irq_window = enable_irq_window,
7851 .update_cr8_intercept = update_cr8_intercept,
7852 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7853 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7854 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7855 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7856 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7857 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7858 .hwapic_irr_update = vmx_hwapic_irr_update,
7859 .hwapic_isr_update = vmx_hwapic_isr_update,
7860 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7861 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7862 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7863 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7865 .set_tss_addr = vmx_set_tss_addr,
7866 .set_identity_map_addr = vmx_set_identity_map_addr,
7867 .get_mt_mask = vmx_get_mt_mask,
7869 .get_exit_info = vmx_get_exit_info,
7871 .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7873 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7875 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7877 .load_mmu_pgd = vmx_load_mmu_pgd,
7879 .check_intercept = vmx_check_intercept,
7880 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7882 .request_immediate_exit = vmx_request_immediate_exit,
7884 .sched_in = vmx_sched_in,
7886 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7887 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7888 .flush_log_dirty = vmx_flush_log_dirty,
7889 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7891 .pre_block = vmx_pre_block,
7892 .post_block = vmx_post_block,
7894 .pmu_ops = &intel_pmu_ops,
7895 .nested_ops = &vmx_nested_ops,
7897 .update_pi_irte = vmx_update_pi_irte,
7899 #ifdef CONFIG_X86_64
7900 .set_hv_timer = vmx_set_hv_timer,
7901 .cancel_hv_timer = vmx_cancel_hv_timer,
7904 .setup_mce = vmx_setup_mce,
7906 .smi_allowed = vmx_smi_allowed,
7907 .pre_enter_smm = vmx_pre_enter_smm,
7908 .pre_leave_smm = vmx_pre_leave_smm,
7909 .enable_smi_window = enable_smi_window,
7911 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7912 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7913 .migrate_timers = vmx_migrate_timers,
7916 static __init int hardware_setup(void)
7918 unsigned long host_bndcfgs;
7920 int r, i, ept_lpage_level;
7923 host_idt_base = dt.address;
7925 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7926 kvm_define_shared_msr(i, vmx_msr_index[i]);
7928 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7931 if (boot_cpu_has(X86_FEATURE_NX))
7932 kvm_enable_efer_bits(EFER_NX);
7934 if (boot_cpu_has(X86_FEATURE_MPX)) {
7935 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7936 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7939 if (!cpu_has_vmx_mpx())
7940 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7941 XFEATURE_MASK_BNDCSR);
7943 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7944 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7947 if (!cpu_has_vmx_ept() ||
7948 !cpu_has_vmx_ept_4levels() ||
7949 !cpu_has_vmx_ept_mt_wb() ||
7950 !cpu_has_vmx_invept_global())
7953 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7954 enable_ept_ad_bits = 0;
7956 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7957 enable_unrestricted_guest = 0;
7959 if (!cpu_has_vmx_flexpriority())
7960 flexpriority_enabled = 0;
7962 if (!cpu_has_virtual_nmis())
7966 * set_apic_access_page_addr() is used to reload apic access
7967 * page upon invalidation. No need to do anything if not
7968 * using the APIC_ACCESS_ADDR VMCS field.
7970 if (!flexpriority_enabled)
7971 vmx_x86_ops.set_apic_access_page_addr = NULL;
7973 if (!cpu_has_vmx_tpr_shadow())
7974 vmx_x86_ops.update_cr8_intercept = NULL;
7976 #if IS_ENABLED(CONFIG_HYPERV)
7977 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7979 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7980 vmx_x86_ops.tlb_remote_flush_with_range =
7981 hv_remote_flush_tlb_with_range;
7985 if (!cpu_has_vmx_ple()) {
7988 ple_window_grow = 0;
7990 ple_window_shrink = 0;
7993 if (!cpu_has_vmx_apicv()) {
7995 vmx_x86_ops.sync_pir_to_irr = NULL;
7998 if (cpu_has_vmx_tsc_scaling()) {
7999 kvm_has_tsc_control = true;
8000 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
8001 kvm_tsc_scaling_ratio_frac_bits = 48;
8004 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8010 ept_lpage_level = 0;
8011 else if (cpu_has_vmx_ept_1g_page())
8012 ept_lpage_level = PG_LEVEL_1G;
8013 else if (cpu_has_vmx_ept_2m_page())
8014 ept_lpage_level = PG_LEVEL_2M;
8016 ept_lpage_level = PG_LEVEL_4K;
8017 kvm_configure_mmu(enable_ept, vmx_get_max_tdp_level(), ept_lpage_level);
8020 * Only enable PML when hardware supports PML feature, and both EPT
8021 * and EPT A/D bit features are enabled -- PML depends on them to work.
8023 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
8027 vmx_x86_ops.slot_enable_log_dirty = NULL;
8028 vmx_x86_ops.slot_disable_log_dirty = NULL;
8029 vmx_x86_ops.flush_log_dirty = NULL;
8030 vmx_x86_ops.enable_log_dirty_pt_masked = NULL;
8033 if (!cpu_has_vmx_preemption_timer())
8034 enable_preemption_timer = false;
8036 if (enable_preemption_timer) {
8037 u64 use_timer_freq = 5000ULL * 1000 * 1000;
8040 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
8041 cpu_preemption_timer_multi =
8042 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
8045 use_timer_freq = (u64)tsc_khz * 1000;
8046 use_timer_freq >>= cpu_preemption_timer_multi;
8049 * KVM "disables" the preemption timer by setting it to its max
8050 * value. Don't use the timer if it might cause spurious exits
8051 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
8053 if (use_timer_freq > 0xffffffffu / 10)
8054 enable_preemption_timer = false;
8057 if (!enable_preemption_timer) {
8058 vmx_x86_ops.set_hv_timer = NULL;
8059 vmx_x86_ops.cancel_hv_timer = NULL;
8060 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
8063 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
8065 kvm_mce_cap_supported |= MCG_LMCE_P;
8067 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
8069 if (!enable_ept || !cpu_has_vmx_intel_pt())
8070 pt_mode = PT_MODE_SYSTEM;
8073 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
8074 vmx_capability.ept);
8076 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
8083 r = alloc_kvm_area();
8085 nested_vmx_hardware_unsetup();
8089 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
8090 .cpu_has_kvm_support = cpu_has_kvm_support,
8091 .disabled_by_bios = vmx_disabled_by_bios,
8092 .check_processor_compatibility = vmx_check_processor_compat,
8093 .hardware_setup = hardware_setup,
8095 .runtime_ops = &vmx_x86_ops,
8098 static void vmx_cleanup_l1d_flush(void)
8100 if (vmx_l1d_flush_pages) {
8101 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
8102 vmx_l1d_flush_pages = NULL;
8104 /* Restore state so sysfs ignores VMX */
8105 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
8108 static void vmx_exit(void)
8110 #ifdef CONFIG_KEXEC_CORE
8111 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8117 #if IS_ENABLED(CONFIG_HYPERV)
8118 if (static_branch_unlikely(&enable_evmcs)) {
8120 struct hv_vp_assist_page *vp_ap;
8122 * Reset everything to support using non-enlightened VMCS
8123 * access later (e.g. when we reload the module with
8124 * enlightened_vmcs=0)
8126 for_each_online_cpu(cpu) {
8127 vp_ap = hv_get_vp_assist_page(cpu);
8132 vp_ap->nested_control.features.directhypercall = 0;
8133 vp_ap->current_nested_vmcs = 0;
8134 vp_ap->enlighten_vmentry = 0;
8137 static_branch_disable(&enable_evmcs);
8140 vmx_cleanup_l1d_flush();
8142 module_exit(vmx_exit);
8144 static int __init vmx_init(void)
8148 #if IS_ENABLED(CONFIG_HYPERV)
8150 * Enlightened VMCS usage should be recommended and the host needs
8151 * to support eVMCS v1 or above. We can also disable eVMCS support
8152 * with module parameter.
8154 if (enlightened_vmcs &&
8155 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8156 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8157 KVM_EVMCS_VERSION) {
8160 /* Check that we have assist pages on all online CPUs */
8161 for_each_online_cpu(cpu) {
8162 if (!hv_get_vp_assist_page(cpu)) {
8163 enlightened_vmcs = false;
8168 if (enlightened_vmcs) {
8169 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8170 static_branch_enable(&enable_evmcs);
8173 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8174 vmx_x86_ops.enable_direct_tlbflush
8175 = hv_enable_direct_tlbflush;
8178 enlightened_vmcs = false;
8182 r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
8183 __alignof__(struct vcpu_vmx), THIS_MODULE);
8188 * Must be called after kvm_init() so enable_ept is properly set
8189 * up. Hand the parameter mitigation value in which was stored in
8190 * the pre module init parser. If no parameter was given, it will
8191 * contain 'auto' which will be turned into the default 'cond'
8194 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8200 for_each_possible_cpu(cpu) {
8201 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8202 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
8203 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8206 #ifdef CONFIG_KEXEC_CORE
8207 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8208 crash_vmclear_local_loaded_vmcss);
8210 vmx_check_vmcs12_offsets();
8213 * Intel processors don't have problems with
8214 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable
8215 * it for VMX by default
8217 allow_smaller_maxphyaddr = true;
8221 module_init(vmx_init);