1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/frame.h>
17 #include <linux/highmem.h>
18 #include <linux/hrtimer.h>
19 #include <linux/kernel.h>
20 #include <linux/kvm_host.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/mod_devicetable.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
34 #include <asm/debugreg.h>
36 #include <asm/fpu/internal.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/kexec.h>
40 #include <asm/perf_event.h>
42 #include <asm/mmu_context.h>
43 #include <asm/mshyperv.h>
44 #include <asm/spec-ctrl.h>
45 #include <asm/virtext.h>
48 #include "capabilities.h"
52 #include "kvm_cache_regs.h"
64 MODULE_AUTHOR("Qumranet");
65 MODULE_LICENSE("GPL");
67 static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
73 bool __read_mostly enable_vpid = 1;
74 module_param_named(vpid, enable_vpid, bool, 0444);
76 static bool __read_mostly enable_vnmi = 1;
77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
79 bool __read_mostly flexpriority_enabled = 1;
80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
82 bool __read_mostly enable_ept = 1;
83 module_param_named(ept, enable_ept, bool, S_IRUGO);
85 bool __read_mostly enable_unrestricted_guest = 1;
86 module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
89 bool __read_mostly enable_ept_ad_bits = 1;
90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
92 static bool __read_mostly emulate_invalid_guest_state = true;
93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
95 static bool __read_mostly fasteoi = 1;
96 module_param(fasteoi, bool, S_IRUGO);
98 static bool __read_mostly enable_apicv = 1;
99 module_param(enable_apicv, bool, S_IRUGO);
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
106 static bool __read_mostly nested = 1;
107 module_param(nested, bool, S_IRUGO);
109 bool __read_mostly enable_pml = 1;
110 module_param_named(pml, enable_pml, bool, S_IRUGO);
112 static bool __read_mostly dump_invalid_vmcs = 0;
113 module_param(dump_invalid_vmcs, bool, 0644);
115 #define MSR_BITMAP_MODE_X2APIC 1
116 #define MSR_BITMAP_MODE_X2APIC_APICV 2
118 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
120 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
121 static int __read_mostly cpu_preemption_timer_multi;
122 static bool __read_mostly enable_preemption_timer = 1;
124 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
127 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
128 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
129 #define KVM_VM_CR0_ALWAYS_ON \
130 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
131 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
132 #define KVM_CR4_GUEST_OWNED_BITS \
133 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
134 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
136 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
137 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
138 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
140 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
142 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
143 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
144 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
145 RTIT_STATUS_BYTECNT))
147 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
148 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
151 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
152 * ple_gap: upper bound on the amount of time between two successive
153 * executions of PAUSE in a loop. Also indicate if ple enabled.
154 * According to test, this time is usually smaller than 128 cycles.
155 * ple_window: upper bound on the amount of time a guest is allowed to execute
156 * in a PAUSE loop. Tests indicate that most spinlocks are held for
157 * less than 2^12 cycles
158 * Time is measured based on a counter that runs at the same rate as the TSC,
159 * refer SDM volume 3b section 21.6.13 & 22.1.3.
161 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
162 module_param(ple_gap, uint, 0444);
164 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
165 module_param(ple_window, uint, 0444);
167 /* Default doubles per-vcpu window every exit. */
168 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
169 module_param(ple_window_grow, uint, 0444);
171 /* Default resets per-vcpu window every exit to ple_window. */
172 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
173 module_param(ple_window_shrink, uint, 0444);
175 /* Default is to compute the maximum so we can never overflow. */
176 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
177 module_param(ple_window_max, uint, 0444);
179 /* Default is SYSTEM mode, 1 for host-guest mode */
180 int __read_mostly pt_mode = PT_MODE_SYSTEM;
181 module_param(pt_mode, int, S_IRUGO);
183 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
184 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
185 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
187 /* Storage for pre module init parameter parsing */
188 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
190 static const struct {
193 } vmentry_l1d_param[] = {
194 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
195 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
196 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
197 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
198 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
199 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
202 #define L1D_CACHE_ORDER 4
203 static void *vmx_l1d_flush_pages;
205 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
210 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
211 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
216 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
220 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
223 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
224 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
225 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
230 /* If set to auto use the default l1tf mitigation method */
231 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
232 switch (l1tf_mitigation) {
233 case L1TF_MITIGATION_OFF:
234 l1tf = VMENTER_L1D_FLUSH_NEVER;
236 case L1TF_MITIGATION_FLUSH_NOWARN:
237 case L1TF_MITIGATION_FLUSH:
238 case L1TF_MITIGATION_FLUSH_NOSMT:
239 l1tf = VMENTER_L1D_FLUSH_COND;
241 case L1TF_MITIGATION_FULL:
242 case L1TF_MITIGATION_FULL_FORCE:
243 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
246 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
247 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
250 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
251 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
253 * This allocation for vmx_l1d_flush_pages is not tied to a VM
254 * lifetime and so should not be charged to a memcg.
256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
259 vmx_l1d_flush_pages = page_address(page);
262 * Initialize each page with a different pattern in
263 * order to protect against KSM in the nested
264 * virtualization case.
266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
272 l1tf_vmx_mitigation = l1tf;
274 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
275 static_branch_enable(&vmx_l1d_should_flush);
277 static_branch_disable(&vmx_l1d_should_flush);
279 if (l1tf == VMENTER_L1D_FLUSH_COND)
280 static_branch_enable(&vmx_l1d_flush_cond);
282 static_branch_disable(&vmx_l1d_flush_cond);
286 static int vmentry_l1d_flush_parse(const char *s)
291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
292 if (vmentry_l1d_param[i].for_parse &&
293 sysfs_streq(s, vmentry_l1d_param[i].option))
300 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
304 l1tf = vmentry_l1d_flush_parse(s);
308 if (!boot_cpu_has(X86_BUG_L1TF))
312 * Has vmx_init() run already? If not then this is the pre init
313 * parameter parsing. In that case just store the value and let
314 * vmx_init() do the proper setup after enable_ept has been
317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
318 vmentry_l1d_flush_param = l1tf;
322 mutex_lock(&vmx_l1d_flush_mutex);
323 ret = vmx_setup_l1d_flush(l1tf);
324 mutex_unlock(&vmx_l1d_flush_mutex);
328 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
331 return sprintf(s, "???\n");
333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
336 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
337 .set = vmentry_l1d_flush_set,
338 .get = vmentry_l1d_flush_get,
340 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
342 static bool guest_state_valid(struct kvm_vcpu *vcpu);
343 static u32 vmx_segment_access_rights(struct kvm_segment *var);
344 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
347 void vmx_vmexit(void);
349 #define vmx_insn_failed(fmt...) \
352 pr_warn_ratelimited(fmt); \
355 asmlinkage void vmread_error(unsigned long field, bool fault)
358 kvm_spurious_fault();
360 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
363 noinline void vmwrite_error(unsigned long field, unsigned long value)
365 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
366 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
369 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
371 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
374 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
376 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
379 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
381 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
385 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
387 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
391 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
392 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
394 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
395 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
397 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
400 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
401 * can find which vCPU should be waken up.
403 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
404 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
406 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
407 static DEFINE_SPINLOCK(vmx_vpid_lock);
409 struct vmcs_config vmcs_config;
410 struct vmx_capability vmx_capability;
412 #define VMX_SEGMENT_FIELD(seg) \
413 [VCPU_SREG_##seg] = { \
414 .selector = GUEST_##seg##_SELECTOR, \
415 .base = GUEST_##seg##_BASE, \
416 .limit = GUEST_##seg##_LIMIT, \
417 .ar_bytes = GUEST_##seg##_AR_BYTES, \
420 static const struct kvm_vmx_segment_field {
425 } kvm_vmx_segment_fields[] = {
426 VMX_SEGMENT_FIELD(CS),
427 VMX_SEGMENT_FIELD(DS),
428 VMX_SEGMENT_FIELD(ES),
429 VMX_SEGMENT_FIELD(FS),
430 VMX_SEGMENT_FIELD(GS),
431 VMX_SEGMENT_FIELD(SS),
432 VMX_SEGMENT_FIELD(TR),
433 VMX_SEGMENT_FIELD(LDTR),
437 static unsigned long host_idt_base;
440 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
441 * will emulate SYSCALL in legacy mode if the vendor string in guest
442 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
443 * support this emulation, IA32_STAR must always be included in
444 * vmx_msr_index[], even in i386 builds.
446 const u32 vmx_msr_index[] = {
448 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
450 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
454 #if IS_ENABLED(CONFIG_HYPERV)
455 static bool __read_mostly enlightened_vmcs = true;
456 module_param(enlightened_vmcs, bool, 0444);
458 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
459 static void check_ept_pointer_match(struct kvm *kvm)
461 struct kvm_vcpu *vcpu;
462 u64 tmp_eptp = INVALID_PAGE;
465 kvm_for_each_vcpu(i, vcpu, kvm) {
466 if (!VALID_PAGE(tmp_eptp)) {
467 tmp_eptp = to_vmx(vcpu)->ept_pointer;
468 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
469 to_kvm_vmx(kvm)->ept_pointers_match
470 = EPT_POINTERS_MISMATCH;
475 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
478 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
481 struct kvm_tlb_range *range = data;
483 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
487 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
488 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
490 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
493 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
494 * of the base of EPT PML4 table, strip off EPT configuration
498 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
499 kvm_fill_hv_flush_list_func, (void *)range);
501 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
504 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
505 struct kvm_tlb_range *range)
507 struct kvm_vcpu *vcpu;
510 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
512 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
513 check_ept_pointer_match(kvm);
515 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
516 kvm_for_each_vcpu(i, vcpu, kvm) {
517 /* If ept_pointer is invalid pointer, bypass flush request. */
518 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
519 ret |= __hv_remote_flush_tlb_with_range(
523 ret = __hv_remote_flush_tlb_with_range(kvm,
524 kvm_get_vcpu(kvm, 0), range);
527 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
530 static int hv_remote_flush_tlb(struct kvm *kvm)
532 return hv_remote_flush_tlb_with_range(kvm, NULL);
535 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
537 struct hv_enlightened_vmcs *evmcs;
538 struct hv_partition_assist_pg **p_hv_pa_pg =
539 &vcpu->kvm->arch.hyperv.hv_pa_pg;
541 * Synthetic VM-Exit is not enabled in current code and so All
542 * evmcs in singe VM shares same assist page.
545 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
550 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
552 evmcs->partition_assist_page =
554 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
555 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
560 #endif /* IS_ENABLED(CONFIG_HYPERV) */
563 * Comment's format: document - errata name - stepping - processor name.
565 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
567 static u32 vmx_preemption_cpu_tfms[] = {
568 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
570 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
571 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
572 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
574 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
576 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
577 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
579 * 320767.pdf - AAP86 - B1 -
580 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
583 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
585 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
587 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
589 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
590 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
591 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
593 /* Xeon E3-1220 V2 */
597 static inline bool cpu_has_broken_vmx_preemption_timer(void)
599 u32 eax = cpuid_eax(0x00000001), i;
601 /* Clear the reserved bits */
602 eax &= ~(0x3U << 14 | 0xfU << 28);
603 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
604 if (eax == vmx_preemption_cpu_tfms[i])
610 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
612 return flexpriority_enabled && lapic_in_kernel(vcpu);
615 static inline bool report_flexpriority(void)
617 return flexpriority_enabled;
620 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
624 for (i = 0; i < vmx->nmsrs; ++i)
625 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
630 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
634 i = __find_msr_index(vmx, msr);
636 return &vmx->guest_msrs[i];
640 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
644 u64 old_msr_data = msr->data;
646 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
648 ret = kvm_set_shared_msr(msr->index, msr->data,
652 msr->data = old_msr_data;
657 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
659 vmcs_clear(loaded_vmcs->vmcs);
660 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
661 vmcs_clear(loaded_vmcs->shadow_vmcs);
662 loaded_vmcs->cpu = -1;
663 loaded_vmcs->launched = 0;
666 #ifdef CONFIG_KEXEC_CORE
668 * This bitmap is used to indicate whether the vmclear
669 * operation is enabled on all cpus. All disabled by
672 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
674 static inline void crash_enable_local_vmclear(int cpu)
676 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
679 static inline void crash_disable_local_vmclear(int cpu)
681 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
684 static inline int crash_local_vmclear_enabled(int cpu)
686 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
689 static void crash_vmclear_local_loaded_vmcss(void)
691 int cpu = raw_smp_processor_id();
692 struct loaded_vmcs *v;
694 if (!crash_local_vmclear_enabled(cpu))
697 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
698 loaded_vmcss_on_cpu_link)
702 static inline void crash_enable_local_vmclear(int cpu) { }
703 static inline void crash_disable_local_vmclear(int cpu) { }
704 #endif /* CONFIG_KEXEC_CORE */
706 static void __loaded_vmcs_clear(void *arg)
708 struct loaded_vmcs *loaded_vmcs = arg;
709 int cpu = raw_smp_processor_id();
711 if (loaded_vmcs->cpu != cpu)
712 return; /* vcpu migration can race with cpu offline */
713 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
714 per_cpu(current_vmcs, cpu) = NULL;
715 crash_disable_local_vmclear(cpu);
716 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
719 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
720 * is before setting loaded_vmcs->vcpu to -1 which is done in
721 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
722 * then adds the vmcs into percpu list before it is deleted.
726 loaded_vmcs_init(loaded_vmcs);
727 crash_enable_local_vmclear(cpu);
730 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
732 int cpu = loaded_vmcs->cpu;
735 smp_call_function_single(cpu,
736 __loaded_vmcs_clear, loaded_vmcs, 1);
739 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
743 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
745 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
746 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
747 vmx->segment_cache.bitmask = 0;
749 ret = vmx->segment_cache.bitmask & mask;
750 vmx->segment_cache.bitmask |= mask;
754 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
756 u16 *p = &vmx->segment_cache.seg[seg].selector;
758 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
759 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
763 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
765 ulong *p = &vmx->segment_cache.seg[seg].base;
767 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
768 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
772 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
774 u32 *p = &vmx->segment_cache.seg[seg].limit;
776 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
777 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
781 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
783 u32 *p = &vmx->segment_cache.seg[seg].ar;
785 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
786 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
790 void update_exception_bitmap(struct kvm_vcpu *vcpu)
794 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
795 (1u << DB_VECTOR) | (1u << AC_VECTOR);
797 * Guest access to VMware backdoor ports could legitimately
798 * trigger #GP because of TSS I/O permission bitmap.
799 * We intercept those #GP and allow access to them anyway
802 if (enable_vmware_backdoor)
803 eb |= (1u << GP_VECTOR);
804 if ((vcpu->guest_debug &
805 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
806 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
807 eb |= 1u << BP_VECTOR;
808 if (to_vmx(vcpu)->rmode.vm86_active)
811 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
813 /* When we are running a nested L2 guest and L1 specified for it a
814 * certain exception bitmap, we must trap the same exceptions and pass
815 * them to L1. When running L2, we will only handle the exceptions
816 * specified above if L1 did not want them.
818 if (is_guest_mode(vcpu))
819 eb |= get_vmcs12(vcpu)->exception_bitmap;
821 vmcs_write32(EXCEPTION_BITMAP, eb);
825 * Check if MSR is intercepted for currently loaded MSR bitmap.
827 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
829 unsigned long *msr_bitmap;
830 int f = sizeof(unsigned long);
832 if (!cpu_has_vmx_msr_bitmap())
835 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
838 return !!test_bit(msr, msr_bitmap + 0x800 / f);
839 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
841 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
847 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
848 unsigned long entry, unsigned long exit)
850 vm_entry_controls_clearbit(vmx, entry);
851 vm_exit_controls_clearbit(vmx, exit);
854 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
858 for (i = 0; i < m->nr; ++i) {
859 if (m->val[i].index == msr)
865 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
868 struct msr_autoload *m = &vmx->msr_autoload;
872 if (cpu_has_load_ia32_efer()) {
873 clear_atomic_switch_msr_special(vmx,
874 VM_ENTRY_LOAD_IA32_EFER,
875 VM_EXIT_LOAD_IA32_EFER);
879 case MSR_CORE_PERF_GLOBAL_CTRL:
880 if (cpu_has_load_perf_global_ctrl()) {
881 clear_atomic_switch_msr_special(vmx,
882 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
883 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
888 i = vmx_find_msr_index(&m->guest, msr);
892 m->guest.val[i] = m->guest.val[m->guest.nr];
893 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
896 i = vmx_find_msr_index(&m->host, msr);
901 m->host.val[i] = m->host.val[m->host.nr];
902 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
905 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
906 unsigned long entry, unsigned long exit,
907 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
908 u64 guest_val, u64 host_val)
910 vmcs_write64(guest_val_vmcs, guest_val);
911 if (host_val_vmcs != HOST_IA32_EFER)
912 vmcs_write64(host_val_vmcs, host_val);
913 vm_entry_controls_setbit(vmx, entry);
914 vm_exit_controls_setbit(vmx, exit);
917 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
918 u64 guest_val, u64 host_val, bool entry_only)
921 struct msr_autoload *m = &vmx->msr_autoload;
925 if (cpu_has_load_ia32_efer()) {
926 add_atomic_switch_msr_special(vmx,
927 VM_ENTRY_LOAD_IA32_EFER,
928 VM_EXIT_LOAD_IA32_EFER,
931 guest_val, host_val);
935 case MSR_CORE_PERF_GLOBAL_CTRL:
936 if (cpu_has_load_perf_global_ctrl()) {
937 add_atomic_switch_msr_special(vmx,
938 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
939 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
940 GUEST_IA32_PERF_GLOBAL_CTRL,
941 HOST_IA32_PERF_GLOBAL_CTRL,
942 guest_val, host_val);
946 case MSR_IA32_PEBS_ENABLE:
947 /* PEBS needs a quiescent period after being disabled (to write
948 * a record). Disabling PEBS through VMX MSR swapping doesn't
949 * provide that period, so a CPU could write host's record into
952 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
955 i = vmx_find_msr_index(&m->guest, msr);
957 j = vmx_find_msr_index(&m->host, msr);
959 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
960 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) {
961 printk_once(KERN_WARNING "Not enough msr switch entries. "
962 "Can't add msr %x\n", msr);
967 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
969 m->guest.val[i].index = msr;
970 m->guest.val[i].value = guest_val;
977 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
979 m->host.val[j].index = msr;
980 m->host.val[j].value = host_val;
983 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
985 u64 guest_efer = vmx->vcpu.arch.efer;
988 /* Shadow paging assumes NX to be available. */
990 guest_efer |= EFER_NX;
993 * LMA and LME handled by hardware; SCE meaningless outside long mode.
995 ignore_bits |= EFER_SCE;
997 ignore_bits |= EFER_LMA | EFER_LME;
998 /* SCE is meaningful only in long mode on Intel */
999 if (guest_efer & EFER_LMA)
1000 ignore_bits &= ~(u64)EFER_SCE;
1004 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1005 * On CPUs that support "load IA32_EFER", always switch EFER
1006 * atomically, since it's faster than switching it manually.
1008 if (cpu_has_load_ia32_efer() ||
1009 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1010 if (!(guest_efer & EFER_LMA))
1011 guest_efer &= ~EFER_LME;
1012 if (guest_efer != host_efer)
1013 add_atomic_switch_msr(vmx, MSR_EFER,
1014 guest_efer, host_efer, false);
1016 clear_atomic_switch_msr(vmx, MSR_EFER);
1019 clear_atomic_switch_msr(vmx, MSR_EFER);
1021 guest_efer &= ~ignore_bits;
1022 guest_efer |= host_efer & ignore_bits;
1024 vmx->guest_msrs[efer_offset].data = guest_efer;
1025 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1031 #ifdef CONFIG_X86_32
1033 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1034 * VMCS rather than the segment table. KVM uses this helper to figure
1035 * out the current bases to poke them into the VMCS before entry.
1037 static unsigned long segment_base(u16 selector)
1039 struct desc_struct *table;
1042 if (!(selector & ~SEGMENT_RPL_MASK))
1045 table = get_current_gdt_ro();
1047 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1048 u16 ldt_selector = kvm_read_ldt();
1050 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1053 table = (struct desc_struct *)segment_base(ldt_selector);
1055 v = get_desc_base(&table[selector >> 3]);
1060 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1064 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1065 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1066 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1067 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1068 for (i = 0; i < addr_range; i++) {
1069 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1070 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1074 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1078 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1079 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1080 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1081 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1082 for (i = 0; i < addr_range; i++) {
1083 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1084 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1088 static void pt_guest_enter(struct vcpu_vmx *vmx)
1090 if (pt_mode == PT_MODE_SYSTEM)
1094 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1095 * Save host state before VM entry.
1097 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1098 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1099 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1100 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1101 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1105 static void pt_guest_exit(struct vcpu_vmx *vmx)
1107 if (pt_mode == PT_MODE_SYSTEM)
1110 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1111 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1112 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1115 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1116 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1119 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1120 unsigned long fs_base, unsigned long gs_base)
1122 if (unlikely(fs_sel != host->fs_sel)) {
1124 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1126 vmcs_write16(HOST_FS_SELECTOR, 0);
1127 host->fs_sel = fs_sel;
1129 if (unlikely(gs_sel != host->gs_sel)) {
1131 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1133 vmcs_write16(HOST_GS_SELECTOR, 0);
1134 host->gs_sel = gs_sel;
1136 if (unlikely(fs_base != host->fs_base)) {
1137 vmcs_writel(HOST_FS_BASE, fs_base);
1138 host->fs_base = fs_base;
1140 if (unlikely(gs_base != host->gs_base)) {
1141 vmcs_writel(HOST_GS_BASE, gs_base);
1142 host->gs_base = gs_base;
1146 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1148 struct vcpu_vmx *vmx = to_vmx(vcpu);
1149 struct vmcs_host_state *host_state;
1150 #ifdef CONFIG_X86_64
1151 int cpu = raw_smp_processor_id();
1153 unsigned long fs_base, gs_base;
1157 vmx->req_immediate_exit = false;
1160 * Note that guest MSRs to be saved/restored can also be changed
1161 * when guest state is loaded. This happens when guest transitions
1162 * to/from long-mode by setting MSR_EFER.LMA.
1164 if (!vmx->guest_msrs_ready) {
1165 vmx->guest_msrs_ready = true;
1166 for (i = 0; i < vmx->save_nmsrs; ++i)
1167 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1168 vmx->guest_msrs[i].data,
1169 vmx->guest_msrs[i].mask);
1172 if (vmx->guest_state_loaded)
1175 host_state = &vmx->loaded_vmcs->host_state;
1178 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1179 * allow segment selectors with cpl > 0 or ti == 1.
1181 host_state->ldt_sel = kvm_read_ldt();
1183 #ifdef CONFIG_X86_64
1184 savesegment(ds, host_state->ds_sel);
1185 savesegment(es, host_state->es_sel);
1187 gs_base = cpu_kernelmode_gs_base(cpu);
1188 if (likely(is_64bit_mm(current->mm))) {
1189 save_fsgs_for_kvm();
1190 fs_sel = current->thread.fsindex;
1191 gs_sel = current->thread.gsindex;
1192 fs_base = current->thread.fsbase;
1193 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1195 savesegment(fs, fs_sel);
1196 savesegment(gs, gs_sel);
1197 fs_base = read_msr(MSR_FS_BASE);
1198 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1201 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1203 savesegment(fs, fs_sel);
1204 savesegment(gs, gs_sel);
1205 fs_base = segment_base(fs_sel);
1206 gs_base = segment_base(gs_sel);
1209 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1210 vmx->guest_state_loaded = true;
1213 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1215 struct vmcs_host_state *host_state;
1217 if (!vmx->guest_state_loaded)
1220 host_state = &vmx->loaded_vmcs->host_state;
1222 ++vmx->vcpu.stat.host_state_reload;
1224 #ifdef CONFIG_X86_64
1225 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1227 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1228 kvm_load_ldt(host_state->ldt_sel);
1229 #ifdef CONFIG_X86_64
1230 load_gs_index(host_state->gs_sel);
1232 loadsegment(gs, host_state->gs_sel);
1235 if (host_state->fs_sel & 7)
1236 loadsegment(fs, host_state->fs_sel);
1237 #ifdef CONFIG_X86_64
1238 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1239 loadsegment(ds, host_state->ds_sel);
1240 loadsegment(es, host_state->es_sel);
1243 invalidate_tss_limit();
1244 #ifdef CONFIG_X86_64
1245 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1247 load_fixmap_gdt(raw_smp_processor_id());
1248 vmx->guest_state_loaded = false;
1249 vmx->guest_msrs_ready = false;
1252 #ifdef CONFIG_X86_64
1253 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1256 if (vmx->guest_state_loaded)
1257 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1259 return vmx->msr_guest_kernel_gs_base;
1262 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1265 if (vmx->guest_state_loaded)
1266 wrmsrl(MSR_KERNEL_GS_BASE, data);
1268 vmx->msr_guest_kernel_gs_base = data;
1272 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1274 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1275 struct pi_desc old, new;
1279 * In case of hot-plug or hot-unplug, we may have to undo
1280 * vmx_vcpu_pi_put even if there is no assigned device. And we
1281 * always keep PI.NDST up to date for simplicity: it makes the
1282 * code easier, and CPU migration is not a fast path.
1284 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1288 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1289 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1290 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1291 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1294 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1295 pi_clear_sn(pi_desc);
1296 goto after_clear_sn;
1299 /* The full case. */
1301 old.control = new.control = pi_desc->control;
1303 dest = cpu_physical_id(cpu);
1305 if (x2apic_enabled())
1308 new.ndst = (dest << 8) & 0xFF00;
1311 } while (cmpxchg64(&pi_desc->control, old.control,
1312 new.control) != old.control);
1317 * Clear SN before reading the bitmap. The VT-d firmware
1318 * writes the bitmap and reads SN atomically (5.2.3 in the
1319 * spec), so it doesn't really have a memory barrier that
1320 * pairs with this, but we cannot do that and we need one.
1322 smp_mb__after_atomic();
1324 if (!pi_is_pir_empty(pi_desc))
1328 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1330 struct vcpu_vmx *vmx = to_vmx(vcpu);
1331 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1333 if (!already_loaded) {
1334 loaded_vmcs_clear(vmx->loaded_vmcs);
1335 local_irq_disable();
1336 crash_disable_local_vmclear(cpu);
1339 * Read loaded_vmcs->cpu should be before fetching
1340 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1341 * See the comments in __loaded_vmcs_clear().
1345 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1346 &per_cpu(loaded_vmcss_on_cpu, cpu));
1347 crash_enable_local_vmclear(cpu);
1351 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1352 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1353 vmcs_load(vmx->loaded_vmcs->vmcs);
1354 indirect_branch_prediction_barrier();
1357 if (!already_loaded) {
1358 void *gdt = get_current_gdt_ro();
1359 unsigned long sysenter_esp;
1361 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1364 * Linux uses per-cpu TSS and GDT, so set these when switching
1365 * processors. See 22.2.4.
1367 vmcs_writel(HOST_TR_BASE,
1368 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1369 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1371 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1372 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1374 vmx->loaded_vmcs->cpu = cpu;
1377 /* Setup TSC multiplier */
1378 if (kvm_has_tsc_control &&
1379 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1380 decache_tsc_multiplier(vmx);
1384 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1385 * vcpu mutex is already taken.
1387 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1389 struct vcpu_vmx *vmx = to_vmx(vcpu);
1391 vmx_vcpu_load_vmcs(vcpu, cpu);
1393 vmx_vcpu_pi_load(vcpu, cpu);
1395 vmx->host_pkru = read_pkru();
1396 vmx->host_debugctlmsr = get_debugctlmsr();
1399 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1401 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1403 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1404 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1405 !kvm_vcpu_apicv_active(vcpu))
1408 /* Set SN when the vCPU is preempted */
1409 if (vcpu->preempted)
1413 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1415 vmx_vcpu_pi_put(vcpu);
1417 vmx_prepare_switch_to_host(to_vmx(vcpu));
1420 static bool emulation_required(struct kvm_vcpu *vcpu)
1422 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1425 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1427 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1429 struct vcpu_vmx *vmx = to_vmx(vcpu);
1430 unsigned long rflags, save_rflags;
1432 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1433 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1434 rflags = vmcs_readl(GUEST_RFLAGS);
1435 if (vmx->rmode.vm86_active) {
1436 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1437 save_rflags = vmx->rmode.save_rflags;
1438 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1440 vmx->rflags = rflags;
1445 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1447 struct vcpu_vmx *vmx = to_vmx(vcpu);
1448 unsigned long old_rflags;
1450 if (enable_unrestricted_guest) {
1451 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1452 vmx->rflags = rflags;
1453 vmcs_writel(GUEST_RFLAGS, rflags);
1457 old_rflags = vmx_get_rflags(vcpu);
1458 vmx->rflags = rflags;
1459 if (vmx->rmode.vm86_active) {
1460 vmx->rmode.save_rflags = rflags;
1461 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1463 vmcs_writel(GUEST_RFLAGS, rflags);
1465 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1466 vmx->emulation_required = emulation_required(vcpu);
1469 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1471 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1474 if (interruptibility & GUEST_INTR_STATE_STI)
1475 ret |= KVM_X86_SHADOW_INT_STI;
1476 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1477 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1482 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1484 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1485 u32 interruptibility = interruptibility_old;
1487 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1489 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1490 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1491 else if (mask & KVM_X86_SHADOW_INT_STI)
1492 interruptibility |= GUEST_INTR_STATE_STI;
1494 if ((interruptibility != interruptibility_old))
1495 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1498 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1500 struct vcpu_vmx *vmx = to_vmx(vcpu);
1501 unsigned long value;
1504 * Any MSR write that attempts to change bits marked reserved will
1507 if (data & vmx->pt_desc.ctl_bitmask)
1511 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1512 * result in a #GP unless the same write also clears TraceEn.
1514 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1515 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1519 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1520 * and FabricEn would cause #GP, if
1521 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1523 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1524 !(data & RTIT_CTL_FABRIC_EN) &&
1525 !intel_pt_validate_cap(vmx->pt_desc.caps,
1526 PT_CAP_single_range_output))
1530 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1531 * utilize encodings marked reserved will casue a #GP fault.
1533 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1534 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1535 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1536 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1538 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1539 PT_CAP_cycle_thresholds);
1540 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1541 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1542 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1544 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1545 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1546 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1547 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1551 * If ADDRx_CFG is reserved or the encodings is >2 will
1552 * cause a #GP fault.
1554 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1555 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1557 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1558 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1560 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1561 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1563 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1564 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1570 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1575 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1576 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1577 * set when EPT misconfig occurs. In practice, real hardware updates
1578 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1579 * (namely Hyper-V) don't set it due to it being undefined behavior,
1580 * i.e. we end up advancing IP with some random value.
1582 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1583 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1584 rip = kvm_rip_read(vcpu);
1585 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1586 kvm_rip_write(vcpu, rip);
1588 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1592 /* skipping an emulated instruction also counts */
1593 vmx_set_interrupt_shadow(vcpu, 0);
1598 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1601 * Ensure that we clear the HLT state in the VMCS. We don't need to
1602 * explicitly skip the instruction because if the HLT state is set,
1603 * then the instruction is already executing and RIP has already been
1606 if (kvm_hlt_in_guest(vcpu->kvm) &&
1607 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1608 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1611 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1613 struct vcpu_vmx *vmx = to_vmx(vcpu);
1614 unsigned nr = vcpu->arch.exception.nr;
1615 bool has_error_code = vcpu->arch.exception.has_error_code;
1616 u32 error_code = vcpu->arch.exception.error_code;
1617 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1619 kvm_deliver_exception_payload(vcpu);
1621 if (has_error_code) {
1622 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1623 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1626 if (vmx->rmode.vm86_active) {
1628 if (kvm_exception_is_soft(nr))
1629 inc_eip = vcpu->arch.event_exit_inst_len;
1630 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1634 WARN_ON_ONCE(vmx->emulation_required);
1636 if (kvm_exception_is_soft(nr)) {
1637 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1638 vmx->vcpu.arch.event_exit_inst_len);
1639 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1641 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1643 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1645 vmx_clear_hlt(vcpu);
1648 static bool vmx_rdtscp_supported(void)
1650 return cpu_has_vmx_rdtscp();
1653 static bool vmx_invpcid_supported(void)
1655 return cpu_has_vmx_invpcid();
1659 * Swap MSR entry in host/guest MSR entry array.
1661 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1663 struct shared_msr_entry tmp;
1665 tmp = vmx->guest_msrs[to];
1666 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1667 vmx->guest_msrs[from] = tmp;
1671 * Set up the vmcs to automatically save and restore system
1672 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1673 * mode, as fiddling with msrs is very expensive.
1675 static void setup_msrs(struct vcpu_vmx *vmx)
1677 int save_nmsrs, index;
1680 #ifdef CONFIG_X86_64
1682 * The SYSCALL MSRs are only needed on long mode guests, and only
1683 * when EFER.SCE is set.
1685 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1686 index = __find_msr_index(vmx, MSR_STAR);
1688 move_msr_up(vmx, index, save_nmsrs++);
1689 index = __find_msr_index(vmx, MSR_LSTAR);
1691 move_msr_up(vmx, index, save_nmsrs++);
1692 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1694 move_msr_up(vmx, index, save_nmsrs++);
1697 index = __find_msr_index(vmx, MSR_EFER);
1698 if (index >= 0 && update_transition_efer(vmx, index))
1699 move_msr_up(vmx, index, save_nmsrs++);
1700 index = __find_msr_index(vmx, MSR_TSC_AUX);
1701 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1702 move_msr_up(vmx, index, save_nmsrs++);
1703 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1705 move_msr_up(vmx, index, save_nmsrs++);
1707 vmx->save_nmsrs = save_nmsrs;
1708 vmx->guest_msrs_ready = false;
1710 if (cpu_has_vmx_msr_bitmap())
1711 vmx_update_msr_bitmap(&vmx->vcpu);
1714 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1716 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1718 if (is_guest_mode(vcpu) &&
1719 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1720 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1722 return vcpu->arch.tsc_offset;
1725 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1727 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1728 u64 g_tsc_offset = 0;
1731 * We're here if L1 chose not to trap WRMSR to TSC. According
1732 * to the spec, this should set L1's TSC; The offset that L1
1733 * set for L2 remains unchanged, and still needs to be added
1734 * to the newly set TSC to get L2's TSC.
1736 if (is_guest_mode(vcpu) &&
1737 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1738 g_tsc_offset = vmcs12->tsc_offset;
1740 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1741 vcpu->arch.tsc_offset - g_tsc_offset,
1743 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1744 return offset + g_tsc_offset;
1748 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1749 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1750 * all guests if the "nested" module option is off, and can also be disabled
1751 * for a single guest by disabling its VMX cpuid bit.
1753 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1755 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1758 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1761 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1763 return !(val & ~valid_bits);
1766 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1768 switch (msr->index) {
1769 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1772 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1781 * Reads an msr value (of 'msr_index') into 'pdata'.
1782 * Returns 0 on success, non-0 otherwise.
1783 * Assumes vcpu_load() was already called.
1785 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1787 struct vcpu_vmx *vmx = to_vmx(vcpu);
1788 struct shared_msr_entry *msr;
1791 switch (msr_info->index) {
1792 #ifdef CONFIG_X86_64
1794 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1797 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1799 case MSR_KERNEL_GS_BASE:
1800 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1804 return kvm_get_msr_common(vcpu, msr_info);
1805 case MSR_IA32_TSX_CTRL:
1806 if (!msr_info->host_initiated &&
1807 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1809 goto find_shared_msr;
1810 case MSR_IA32_UMWAIT_CONTROL:
1811 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1814 msr_info->data = vmx->msr_ia32_umwait_control;
1816 case MSR_IA32_SPEC_CTRL:
1817 if (!msr_info->host_initiated &&
1818 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1821 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1823 case MSR_IA32_SYSENTER_CS:
1824 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1826 case MSR_IA32_SYSENTER_EIP:
1827 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1829 case MSR_IA32_SYSENTER_ESP:
1830 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1832 case MSR_IA32_BNDCFGS:
1833 if (!kvm_mpx_supported() ||
1834 (!msr_info->host_initiated &&
1835 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1837 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1839 case MSR_IA32_MCG_EXT_CTL:
1840 if (!msr_info->host_initiated &&
1841 !(vmx->msr_ia32_feature_control &
1842 FEATURE_CONTROL_LMCE))
1844 msr_info->data = vcpu->arch.mcg_ext_ctl;
1846 case MSR_IA32_FEATURE_CONTROL:
1847 msr_info->data = vmx->msr_ia32_feature_control;
1849 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1850 if (!nested_vmx_allowed(vcpu))
1852 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1854 case MSR_IA32_RTIT_CTL:
1855 if (pt_mode != PT_MODE_HOST_GUEST)
1857 msr_info->data = vmx->pt_desc.guest.ctl;
1859 case MSR_IA32_RTIT_STATUS:
1860 if (pt_mode != PT_MODE_HOST_GUEST)
1862 msr_info->data = vmx->pt_desc.guest.status;
1864 case MSR_IA32_RTIT_CR3_MATCH:
1865 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1866 !intel_pt_validate_cap(vmx->pt_desc.caps,
1867 PT_CAP_cr3_filtering))
1869 msr_info->data = vmx->pt_desc.guest.cr3_match;
1871 case MSR_IA32_RTIT_OUTPUT_BASE:
1872 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1873 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1874 PT_CAP_topa_output) &&
1875 !intel_pt_validate_cap(vmx->pt_desc.caps,
1876 PT_CAP_single_range_output)))
1878 msr_info->data = vmx->pt_desc.guest.output_base;
1880 case MSR_IA32_RTIT_OUTPUT_MASK:
1881 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1882 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1883 PT_CAP_topa_output) &&
1884 !intel_pt_validate_cap(vmx->pt_desc.caps,
1885 PT_CAP_single_range_output)))
1887 msr_info->data = vmx->pt_desc.guest.output_mask;
1889 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1890 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1891 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1892 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1893 PT_CAP_num_address_ranges)))
1896 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1898 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1901 if (!msr_info->host_initiated &&
1902 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1904 goto find_shared_msr;
1907 msr = find_msr_entry(vmx, msr_info->index);
1909 msr_info->data = msr->data;
1912 return kvm_get_msr_common(vcpu, msr_info);
1919 * Writes msr value into into the appropriate "register".
1920 * Returns 0 on success, non-0 otherwise.
1921 * Assumes vcpu_load() was already called.
1923 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1925 struct vcpu_vmx *vmx = to_vmx(vcpu);
1926 struct shared_msr_entry *msr;
1928 u32 msr_index = msr_info->index;
1929 u64 data = msr_info->data;
1932 switch (msr_index) {
1934 ret = kvm_set_msr_common(vcpu, msr_info);
1936 #ifdef CONFIG_X86_64
1938 vmx_segment_cache_clear(vmx);
1939 vmcs_writel(GUEST_FS_BASE, data);
1942 vmx_segment_cache_clear(vmx);
1943 vmcs_writel(GUEST_GS_BASE, data);
1945 case MSR_KERNEL_GS_BASE:
1946 vmx_write_guest_kernel_gs_base(vmx, data);
1949 case MSR_IA32_SYSENTER_CS:
1950 if (is_guest_mode(vcpu))
1951 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1952 vmcs_write32(GUEST_SYSENTER_CS, data);
1954 case MSR_IA32_SYSENTER_EIP:
1955 if (is_guest_mode(vcpu))
1956 get_vmcs12(vcpu)->guest_sysenter_eip = data;
1957 vmcs_writel(GUEST_SYSENTER_EIP, data);
1959 case MSR_IA32_SYSENTER_ESP:
1960 if (is_guest_mode(vcpu))
1961 get_vmcs12(vcpu)->guest_sysenter_esp = data;
1962 vmcs_writel(GUEST_SYSENTER_ESP, data);
1964 case MSR_IA32_DEBUGCTLMSR:
1965 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1966 VM_EXIT_SAVE_DEBUG_CONTROLS)
1967 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1969 ret = kvm_set_msr_common(vcpu, msr_info);
1972 case MSR_IA32_BNDCFGS:
1973 if (!kvm_mpx_supported() ||
1974 (!msr_info->host_initiated &&
1975 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1977 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1978 (data & MSR_IA32_BNDCFGS_RSVD))
1980 vmcs_write64(GUEST_BNDCFGS, data);
1982 case MSR_IA32_UMWAIT_CONTROL:
1983 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1986 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
1987 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
1990 vmx->msr_ia32_umwait_control = data;
1992 case MSR_IA32_SPEC_CTRL:
1993 if (!msr_info->host_initiated &&
1994 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1997 /* The STIBP bit doesn't fault even if it's not advertised */
1998 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
2001 vmx->spec_ctrl = data;
2008 * When it's written (to non-zero) for the first time, pass
2012 * The handling of the MSR bitmap for L2 guests is done in
2013 * nested_vmx_merge_msr_bitmap. We should not touch the
2014 * vmcs02.msr_bitmap here since it gets completely overwritten
2015 * in the merging. We update the vmcs01 here for L1 as well
2016 * since it will end up touching the MSR anyway now.
2018 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2022 case MSR_IA32_TSX_CTRL:
2023 if (!msr_info->host_initiated &&
2024 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2026 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2028 goto find_shared_msr;
2029 case MSR_IA32_PRED_CMD:
2030 if (!msr_info->host_initiated &&
2031 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2034 if (data & ~PRED_CMD_IBPB)
2040 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2044 * When it's written (to non-zero) for the first time, pass
2048 * The handling of the MSR bitmap for L2 guests is done in
2049 * nested_vmx_merge_msr_bitmap. We should not touch the
2050 * vmcs02.msr_bitmap here since it gets completely overwritten
2053 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2056 case MSR_IA32_CR_PAT:
2057 if (!kvm_pat_valid(data))
2060 if (is_guest_mode(vcpu) &&
2061 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2062 get_vmcs12(vcpu)->guest_ia32_pat = data;
2064 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2065 vmcs_write64(GUEST_IA32_PAT, data);
2066 vcpu->arch.pat = data;
2069 ret = kvm_set_msr_common(vcpu, msr_info);
2071 case MSR_IA32_TSC_ADJUST:
2072 ret = kvm_set_msr_common(vcpu, msr_info);
2074 case MSR_IA32_MCG_EXT_CTL:
2075 if ((!msr_info->host_initiated &&
2076 !(to_vmx(vcpu)->msr_ia32_feature_control &
2077 FEATURE_CONTROL_LMCE)) ||
2078 (data & ~MCG_EXT_CTL_LMCE_EN))
2080 vcpu->arch.mcg_ext_ctl = data;
2082 case MSR_IA32_FEATURE_CONTROL:
2083 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2084 (to_vmx(vcpu)->msr_ia32_feature_control &
2085 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2087 vmx->msr_ia32_feature_control = data;
2088 if (msr_info->host_initiated && data == 0)
2089 vmx_leave_nested(vcpu);
2091 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2092 if (!msr_info->host_initiated)
2093 return 1; /* they are read-only */
2094 if (!nested_vmx_allowed(vcpu))
2096 return vmx_set_vmx_msr(vcpu, msr_index, data);
2097 case MSR_IA32_RTIT_CTL:
2098 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2099 vmx_rtit_ctl_check(vcpu, data) ||
2102 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2103 vmx->pt_desc.guest.ctl = data;
2104 pt_update_intercept_for_msr(vmx);
2106 case MSR_IA32_RTIT_STATUS:
2107 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2108 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2109 (data & MSR_IA32_RTIT_STATUS_MASK))
2111 vmx->pt_desc.guest.status = data;
2113 case MSR_IA32_RTIT_CR3_MATCH:
2114 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2115 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2116 !intel_pt_validate_cap(vmx->pt_desc.caps,
2117 PT_CAP_cr3_filtering))
2119 vmx->pt_desc.guest.cr3_match = data;
2121 case MSR_IA32_RTIT_OUTPUT_BASE:
2122 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2123 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2124 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2125 PT_CAP_topa_output) &&
2126 !intel_pt_validate_cap(vmx->pt_desc.caps,
2127 PT_CAP_single_range_output)) ||
2128 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2130 vmx->pt_desc.guest.output_base = data;
2132 case MSR_IA32_RTIT_OUTPUT_MASK:
2133 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2134 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2135 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2136 PT_CAP_topa_output) &&
2137 !intel_pt_validate_cap(vmx->pt_desc.caps,
2138 PT_CAP_single_range_output)))
2140 vmx->pt_desc.guest.output_mask = data;
2142 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2143 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2144 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2145 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2146 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2147 PT_CAP_num_address_ranges)))
2150 vmx->pt_desc.guest.addr_b[index / 2] = data;
2152 vmx->pt_desc.guest.addr_a[index / 2] = data;
2155 if (!msr_info->host_initiated &&
2156 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2158 /* Check reserved bit, higher 32 bits should be zero */
2159 if ((data >> 32) != 0)
2161 goto find_shared_msr;
2165 msr = find_msr_entry(vmx, msr_index);
2167 ret = vmx_set_guest_msr(vmx, msr, data);
2169 ret = kvm_set_msr_common(vcpu, msr_info);
2175 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2177 kvm_register_mark_available(vcpu, reg);
2181 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2184 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2186 case VCPU_EXREG_PDPTR:
2188 ept_save_pdptrs(vcpu);
2190 case VCPU_EXREG_CR3:
2191 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2192 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2200 static __init int cpu_has_kvm_support(void)
2202 return cpu_has_vmx();
2205 static __init int vmx_disabled_by_bios(void)
2209 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2210 if (msr & FEATURE_CONTROL_LOCKED) {
2211 /* launched w/ TXT and VMX disabled */
2212 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2215 /* launched w/o TXT and VMX only enabled w/ TXT */
2216 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2217 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2218 && !tboot_enabled()) {
2219 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2220 "activate TXT before enabling KVM\n");
2223 /* launched w/o TXT and VMX disabled */
2224 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2225 && !tboot_enabled())
2232 static void kvm_cpu_vmxon(u64 addr)
2234 cr4_set_bits(X86_CR4_VMXE);
2235 intel_pt_handle_vmx(1);
2237 asm volatile ("vmxon %0" : : "m"(addr));
2240 static int hardware_enable(void)
2242 int cpu = raw_smp_processor_id();
2243 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2246 if (cr4_read_shadow() & X86_CR4_VMXE)
2250 * This can happen if we hot-added a CPU but failed to allocate
2251 * VP assist page for it.
2253 if (static_branch_unlikely(&enable_evmcs) &&
2254 !hv_get_vp_assist_page(cpu))
2257 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2258 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2259 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2262 * Now we can enable the vmclear operation in kdump
2263 * since the loaded_vmcss_on_cpu list on this cpu
2264 * has been initialized.
2266 * Though the cpu is not in VMX operation now, there
2267 * is no problem to enable the vmclear operation
2268 * for the loaded_vmcss_on_cpu list is empty!
2270 crash_enable_local_vmclear(cpu);
2272 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2274 test_bits = FEATURE_CONTROL_LOCKED;
2275 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2276 if (tboot_enabled())
2277 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2279 if ((old & test_bits) != test_bits) {
2280 /* enable and lock */
2281 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2283 kvm_cpu_vmxon(phys_addr);
2290 static void vmclear_local_loaded_vmcss(void)
2292 int cpu = raw_smp_processor_id();
2293 struct loaded_vmcs *v, *n;
2295 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2296 loaded_vmcss_on_cpu_link)
2297 __loaded_vmcs_clear(v);
2301 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2304 static void kvm_cpu_vmxoff(void)
2306 asm volatile (__ex("vmxoff"));
2308 intel_pt_handle_vmx(0);
2309 cr4_clear_bits(X86_CR4_VMXE);
2312 static void hardware_disable(void)
2314 vmclear_local_loaded_vmcss();
2318 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2319 u32 msr, u32 *result)
2321 u32 vmx_msr_low, vmx_msr_high;
2322 u32 ctl = ctl_min | ctl_opt;
2324 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2326 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2327 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2329 /* Ensure minimum (required) set of control bits are supported. */
2337 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2338 struct vmx_capability *vmx_cap)
2340 u32 vmx_msr_low, vmx_msr_high;
2341 u32 min, opt, min2, opt2;
2342 u32 _pin_based_exec_control = 0;
2343 u32 _cpu_based_exec_control = 0;
2344 u32 _cpu_based_2nd_exec_control = 0;
2345 u32 _vmexit_control = 0;
2346 u32 _vmentry_control = 0;
2348 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2349 min = CPU_BASED_HLT_EXITING |
2350 #ifdef CONFIG_X86_64
2351 CPU_BASED_CR8_LOAD_EXITING |
2352 CPU_BASED_CR8_STORE_EXITING |
2354 CPU_BASED_CR3_LOAD_EXITING |
2355 CPU_BASED_CR3_STORE_EXITING |
2356 CPU_BASED_UNCOND_IO_EXITING |
2357 CPU_BASED_MOV_DR_EXITING |
2358 CPU_BASED_USE_TSC_OFFSETING |
2359 CPU_BASED_MWAIT_EXITING |
2360 CPU_BASED_MONITOR_EXITING |
2361 CPU_BASED_INVLPG_EXITING |
2362 CPU_BASED_RDPMC_EXITING;
2364 opt = CPU_BASED_TPR_SHADOW |
2365 CPU_BASED_USE_MSR_BITMAPS |
2366 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2367 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2368 &_cpu_based_exec_control) < 0)
2370 #ifdef CONFIG_X86_64
2371 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2372 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2373 ~CPU_BASED_CR8_STORE_EXITING;
2375 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2377 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2378 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2379 SECONDARY_EXEC_WBINVD_EXITING |
2380 SECONDARY_EXEC_ENABLE_VPID |
2381 SECONDARY_EXEC_ENABLE_EPT |
2382 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2383 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2384 SECONDARY_EXEC_DESC |
2385 SECONDARY_EXEC_RDTSCP |
2386 SECONDARY_EXEC_ENABLE_INVPCID |
2387 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2388 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2389 SECONDARY_EXEC_SHADOW_VMCS |
2390 SECONDARY_EXEC_XSAVES |
2391 SECONDARY_EXEC_RDSEED_EXITING |
2392 SECONDARY_EXEC_RDRAND_EXITING |
2393 SECONDARY_EXEC_ENABLE_PML |
2394 SECONDARY_EXEC_TSC_SCALING |
2395 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2396 SECONDARY_EXEC_PT_USE_GPA |
2397 SECONDARY_EXEC_PT_CONCEAL_VMX |
2398 SECONDARY_EXEC_ENABLE_VMFUNC |
2399 SECONDARY_EXEC_ENCLS_EXITING;
2400 if (adjust_vmx_controls(min2, opt2,
2401 MSR_IA32_VMX_PROCBASED_CTLS2,
2402 &_cpu_based_2nd_exec_control) < 0)
2405 #ifndef CONFIG_X86_64
2406 if (!(_cpu_based_2nd_exec_control &
2407 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2408 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2411 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2412 _cpu_based_2nd_exec_control &= ~(
2413 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2414 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2415 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2417 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2418 &vmx_cap->ept, &vmx_cap->vpid);
2420 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2421 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2423 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2424 CPU_BASED_CR3_STORE_EXITING |
2425 CPU_BASED_INVLPG_EXITING);
2426 } else if (vmx_cap->ept) {
2428 pr_warn_once("EPT CAP should not exist if not support "
2429 "1-setting enable EPT VM-execution control\n");
2431 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2434 pr_warn_once("VPID CAP should not exist if not support "
2435 "1-setting enable VPID VM-execution control\n");
2438 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2439 #ifdef CONFIG_X86_64
2440 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2442 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2443 VM_EXIT_LOAD_IA32_PAT |
2444 VM_EXIT_LOAD_IA32_EFER |
2445 VM_EXIT_CLEAR_BNDCFGS |
2446 VM_EXIT_PT_CONCEAL_PIP |
2447 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2448 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2449 &_vmexit_control) < 0)
2452 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2453 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2454 PIN_BASED_VMX_PREEMPTION_TIMER;
2455 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2456 &_pin_based_exec_control) < 0)
2459 if (cpu_has_broken_vmx_preemption_timer())
2460 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2461 if (!(_cpu_based_2nd_exec_control &
2462 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2463 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2465 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2466 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2467 VM_ENTRY_LOAD_IA32_PAT |
2468 VM_ENTRY_LOAD_IA32_EFER |
2469 VM_ENTRY_LOAD_BNDCFGS |
2470 VM_ENTRY_PT_CONCEAL_PIP |
2471 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2472 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2473 &_vmentry_control) < 0)
2477 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2478 * can't be used due to an errata where VM Exit may incorrectly clear
2479 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2480 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2482 if (boot_cpu_data.x86 == 0x6) {
2483 switch (boot_cpu_data.x86_model) {
2484 case 26: /* AAK155 */
2485 case 30: /* AAP115 */
2486 case 37: /* AAT100 */
2487 case 44: /* BC86,AAY89,BD102 */
2489 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2490 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2491 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2492 "does not work properly. Using workaround\n");
2500 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2502 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2503 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2506 #ifdef CONFIG_X86_64
2507 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2508 if (vmx_msr_high & (1u<<16))
2512 /* Require Write-Back (WB) memory type for VMCS accesses. */
2513 if (((vmx_msr_high >> 18) & 15) != 6)
2516 vmcs_conf->size = vmx_msr_high & 0x1fff;
2517 vmcs_conf->order = get_order(vmcs_conf->size);
2518 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2520 vmcs_conf->revision_id = vmx_msr_low;
2522 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2523 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2524 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2525 vmcs_conf->vmexit_ctrl = _vmexit_control;
2526 vmcs_conf->vmentry_ctrl = _vmentry_control;
2528 if (static_branch_unlikely(&enable_evmcs))
2529 evmcs_sanitize_exec_ctrls(vmcs_conf);
2534 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2536 int node = cpu_to_node(cpu);
2540 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2543 vmcs = page_address(pages);
2544 memset(vmcs, 0, vmcs_config.size);
2546 /* KVM supports Enlightened VMCS v1 only */
2547 if (static_branch_unlikely(&enable_evmcs))
2548 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2550 vmcs->hdr.revision_id = vmcs_config.revision_id;
2553 vmcs->hdr.shadow_vmcs = 1;
2557 void free_vmcs(struct vmcs *vmcs)
2559 free_pages((unsigned long)vmcs, vmcs_config.order);
2563 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2565 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2567 if (!loaded_vmcs->vmcs)
2569 loaded_vmcs_clear(loaded_vmcs);
2570 free_vmcs(loaded_vmcs->vmcs);
2571 loaded_vmcs->vmcs = NULL;
2572 if (loaded_vmcs->msr_bitmap)
2573 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2574 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2577 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2579 loaded_vmcs->vmcs = alloc_vmcs(false);
2580 if (!loaded_vmcs->vmcs)
2583 loaded_vmcs->shadow_vmcs = NULL;
2584 loaded_vmcs->hv_timer_soft_disabled = false;
2585 loaded_vmcs_init(loaded_vmcs);
2587 if (cpu_has_vmx_msr_bitmap()) {
2588 loaded_vmcs->msr_bitmap = (unsigned long *)
2589 __get_free_page(GFP_KERNEL_ACCOUNT);
2590 if (!loaded_vmcs->msr_bitmap)
2592 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2594 if (IS_ENABLED(CONFIG_HYPERV) &&
2595 static_branch_unlikely(&enable_evmcs) &&
2596 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2597 struct hv_enlightened_vmcs *evmcs =
2598 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2600 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2604 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2605 memset(&loaded_vmcs->controls_shadow, 0,
2606 sizeof(struct vmcs_controls_shadow));
2611 free_loaded_vmcs(loaded_vmcs);
2615 static void free_kvm_area(void)
2619 for_each_possible_cpu(cpu) {
2620 free_vmcs(per_cpu(vmxarea, cpu));
2621 per_cpu(vmxarea, cpu) = NULL;
2625 static __init int alloc_kvm_area(void)
2629 for_each_possible_cpu(cpu) {
2632 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2639 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2640 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2641 * revision_id reported by MSR_IA32_VMX_BASIC.
2643 * However, even though not explicitly documented by
2644 * TLFS, VMXArea passed as VMXON argument should
2645 * still be marked with revision_id reported by
2648 if (static_branch_unlikely(&enable_evmcs))
2649 vmcs->hdr.revision_id = vmcs_config.revision_id;
2651 per_cpu(vmxarea, cpu) = vmcs;
2656 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2657 struct kvm_segment *save)
2659 if (!emulate_invalid_guest_state) {
2661 * CS and SS RPL should be equal during guest entry according
2662 * to VMX spec, but in reality it is not always so. Since vcpu
2663 * is in the middle of the transition from real mode to
2664 * protected mode it is safe to assume that RPL 0 is a good
2667 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2668 save->selector &= ~SEGMENT_RPL_MASK;
2669 save->dpl = save->selector & SEGMENT_RPL_MASK;
2672 vmx_set_segment(vcpu, save, seg);
2675 static void enter_pmode(struct kvm_vcpu *vcpu)
2677 unsigned long flags;
2678 struct vcpu_vmx *vmx = to_vmx(vcpu);
2681 * Update real mode segment cache. It may be not up-to-date if sement
2682 * register was written while vcpu was in a guest mode.
2684 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2685 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2686 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2687 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2688 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2689 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2691 vmx->rmode.vm86_active = 0;
2693 vmx_segment_cache_clear(vmx);
2695 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2697 flags = vmcs_readl(GUEST_RFLAGS);
2698 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2699 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2700 vmcs_writel(GUEST_RFLAGS, flags);
2702 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2703 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2705 update_exception_bitmap(vcpu);
2707 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2708 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2709 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2710 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2711 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2712 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2715 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2717 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2718 struct kvm_segment var = *save;
2721 if (seg == VCPU_SREG_CS)
2724 if (!emulate_invalid_guest_state) {
2725 var.selector = var.base >> 4;
2726 var.base = var.base & 0xffff0;
2736 if (save->base & 0xf)
2737 printk_once(KERN_WARNING "kvm: segment base is not "
2738 "paragraph aligned when entering "
2739 "protected mode (seg=%d)", seg);
2742 vmcs_write16(sf->selector, var.selector);
2743 vmcs_writel(sf->base, var.base);
2744 vmcs_write32(sf->limit, var.limit);
2745 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2748 static void enter_rmode(struct kvm_vcpu *vcpu)
2750 unsigned long flags;
2751 struct vcpu_vmx *vmx = to_vmx(vcpu);
2752 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2754 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2755 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2756 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2757 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2758 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2759 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2760 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2762 vmx->rmode.vm86_active = 1;
2765 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2766 * vcpu. Warn the user that an update is overdue.
2768 if (!kvm_vmx->tss_addr)
2769 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2770 "called before entering vcpu\n");
2772 vmx_segment_cache_clear(vmx);
2774 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2775 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2776 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2778 flags = vmcs_readl(GUEST_RFLAGS);
2779 vmx->rmode.save_rflags = flags;
2781 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2783 vmcs_writel(GUEST_RFLAGS, flags);
2784 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2785 update_exception_bitmap(vcpu);
2787 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2788 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2789 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2790 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2791 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2792 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2794 kvm_mmu_reset_context(vcpu);
2797 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2799 struct vcpu_vmx *vmx = to_vmx(vcpu);
2800 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2805 vcpu->arch.efer = efer;
2806 if (efer & EFER_LMA) {
2807 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2810 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2812 msr->data = efer & ~EFER_LME;
2817 #ifdef CONFIG_X86_64
2819 static void enter_lmode(struct kvm_vcpu *vcpu)
2823 vmx_segment_cache_clear(to_vmx(vcpu));
2825 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2826 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2827 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2829 vmcs_write32(GUEST_TR_AR_BYTES,
2830 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2831 | VMX_AR_TYPE_BUSY_64_TSS);
2833 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2836 static void exit_lmode(struct kvm_vcpu *vcpu)
2838 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2839 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2844 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2846 int vpid = to_vmx(vcpu)->vpid;
2848 if (!vpid_sync_vcpu_addr(vpid, addr))
2849 vpid_sync_context(vpid);
2852 * If VPIDs are not supported or enabled, then the above is a no-op.
2853 * But we don't really need a TLB flush in that case anyway, because
2854 * each VM entry/exit includes an implicit flush when VPID is 0.
2858 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2860 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2862 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2863 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2866 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2868 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2870 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2871 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2874 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2876 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2878 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2881 if (is_pae_paging(vcpu)) {
2882 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2883 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2884 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2885 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2889 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2891 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2893 if (is_pae_paging(vcpu)) {
2894 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2895 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2896 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2897 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2900 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2903 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2905 struct kvm_vcpu *vcpu)
2907 struct vcpu_vmx *vmx = to_vmx(vcpu);
2909 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2910 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2911 if (!(cr0 & X86_CR0_PG)) {
2912 /* From paging/starting to nonpaging */
2913 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2914 CPU_BASED_CR3_STORE_EXITING);
2915 vcpu->arch.cr0 = cr0;
2916 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2917 } else if (!is_paging(vcpu)) {
2918 /* From nonpaging to paging */
2919 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2920 CPU_BASED_CR3_STORE_EXITING);
2921 vcpu->arch.cr0 = cr0;
2922 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2925 if (!(cr0 & X86_CR0_WP))
2926 *hw_cr0 &= ~X86_CR0_WP;
2929 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2931 struct vcpu_vmx *vmx = to_vmx(vcpu);
2932 unsigned long hw_cr0;
2934 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2935 if (enable_unrestricted_guest)
2936 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2938 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2940 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2943 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2947 #ifdef CONFIG_X86_64
2948 if (vcpu->arch.efer & EFER_LME) {
2949 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2951 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2956 if (enable_ept && !enable_unrestricted_guest)
2957 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2959 vmcs_writel(CR0_READ_SHADOW, cr0);
2960 vmcs_writel(GUEST_CR0, hw_cr0);
2961 vcpu->arch.cr0 = cr0;
2963 /* depends on vcpu->arch.cr0 to be set to a new value */
2964 vmx->emulation_required = emulation_required(vcpu);
2967 static int get_ept_level(struct kvm_vcpu *vcpu)
2969 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2974 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2976 u64 eptp = VMX_EPTP_MT_WB;
2978 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2980 if (enable_ept_ad_bits &&
2981 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2982 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2983 eptp |= (root_hpa & PAGE_MASK);
2988 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2990 struct kvm *kvm = vcpu->kvm;
2991 bool update_guest_cr3 = true;
2992 unsigned long guest_cr3;
2997 eptp = construct_eptp(vcpu, cr3);
2998 vmcs_write64(EPT_POINTER, eptp);
3000 if (kvm_x86_ops->tlb_remote_flush) {
3001 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3002 to_vmx(vcpu)->ept_pointer = eptp;
3003 to_kvm_vmx(kvm)->ept_pointers_match
3004 = EPT_POINTERS_CHECK;
3005 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3008 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3009 if (is_guest_mode(vcpu))
3010 update_guest_cr3 = false;
3011 else if (!enable_unrestricted_guest && !is_paging(vcpu))
3012 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3013 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3014 guest_cr3 = vcpu->arch.cr3;
3015 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3016 update_guest_cr3 = false;
3017 ept_load_pdptrs(vcpu);
3020 if (update_guest_cr3)
3021 vmcs_writel(GUEST_CR3, guest_cr3);
3024 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3026 struct vcpu_vmx *vmx = to_vmx(vcpu);
3028 * Pass through host's Machine Check Enable value to hw_cr4, which
3029 * is in force while we are in guest mode. Do not let guests control
3030 * this bit, even if host CR4.MCE == 0.
3032 unsigned long hw_cr4;
3034 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3035 if (enable_unrestricted_guest)
3036 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3037 else if (vmx->rmode.vm86_active)
3038 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3040 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3042 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3043 if (cr4 & X86_CR4_UMIP) {
3044 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3045 hw_cr4 &= ~X86_CR4_UMIP;
3046 } else if (!is_guest_mode(vcpu) ||
3047 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3048 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3052 if (cr4 & X86_CR4_VMXE) {
3054 * To use VMXON (and later other VMX instructions), a guest
3055 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3056 * So basically the check on whether to allow nested VMX
3057 * is here. We operate under the default treatment of SMM,
3058 * so VMX cannot be enabled under SMM.
3060 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3064 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3067 vcpu->arch.cr4 = cr4;
3069 if (!enable_unrestricted_guest) {
3071 if (!is_paging(vcpu)) {
3072 hw_cr4 &= ~X86_CR4_PAE;
3073 hw_cr4 |= X86_CR4_PSE;
3074 } else if (!(cr4 & X86_CR4_PAE)) {
3075 hw_cr4 &= ~X86_CR4_PAE;
3080 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3081 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3082 * to be manually disabled when guest switches to non-paging
3085 * If !enable_unrestricted_guest, the CPU is always running
3086 * with CR0.PG=1 and CR4 needs to be modified.
3087 * If enable_unrestricted_guest, the CPU automatically
3088 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3090 if (!is_paging(vcpu))
3091 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3094 vmcs_writel(CR4_READ_SHADOW, cr4);
3095 vmcs_writel(GUEST_CR4, hw_cr4);
3099 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3101 struct vcpu_vmx *vmx = to_vmx(vcpu);
3104 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3105 *var = vmx->rmode.segs[seg];
3106 if (seg == VCPU_SREG_TR
3107 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3109 var->base = vmx_read_guest_seg_base(vmx, seg);
3110 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3113 var->base = vmx_read_guest_seg_base(vmx, seg);
3114 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3115 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3116 ar = vmx_read_guest_seg_ar(vmx, seg);
3117 var->unusable = (ar >> 16) & 1;
3118 var->type = ar & 15;
3119 var->s = (ar >> 4) & 1;
3120 var->dpl = (ar >> 5) & 3;
3122 * Some userspaces do not preserve unusable property. Since usable
3123 * segment has to be present according to VMX spec we can use present
3124 * property to amend userspace bug by making unusable segment always
3125 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3126 * segment as unusable.
3128 var->present = !var->unusable;
3129 var->avl = (ar >> 12) & 1;
3130 var->l = (ar >> 13) & 1;
3131 var->db = (ar >> 14) & 1;
3132 var->g = (ar >> 15) & 1;
3135 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3137 struct kvm_segment s;
3139 if (to_vmx(vcpu)->rmode.vm86_active) {
3140 vmx_get_segment(vcpu, &s, seg);
3143 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3146 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3148 struct vcpu_vmx *vmx = to_vmx(vcpu);
3150 if (unlikely(vmx->rmode.vm86_active))
3153 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3154 return VMX_AR_DPL(ar);
3158 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3162 if (var->unusable || !var->present)
3165 ar = var->type & 15;
3166 ar |= (var->s & 1) << 4;
3167 ar |= (var->dpl & 3) << 5;
3168 ar |= (var->present & 1) << 7;
3169 ar |= (var->avl & 1) << 12;
3170 ar |= (var->l & 1) << 13;
3171 ar |= (var->db & 1) << 14;
3172 ar |= (var->g & 1) << 15;
3178 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3180 struct vcpu_vmx *vmx = to_vmx(vcpu);
3181 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3183 vmx_segment_cache_clear(vmx);
3185 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3186 vmx->rmode.segs[seg] = *var;
3187 if (seg == VCPU_SREG_TR)
3188 vmcs_write16(sf->selector, var->selector);
3190 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3194 vmcs_writel(sf->base, var->base);
3195 vmcs_write32(sf->limit, var->limit);
3196 vmcs_write16(sf->selector, var->selector);
3199 * Fix the "Accessed" bit in AR field of segment registers for older
3201 * IA32 arch specifies that at the time of processor reset the
3202 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3203 * is setting it to 0 in the userland code. This causes invalid guest
3204 * state vmexit when "unrestricted guest" mode is turned on.
3205 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3206 * tree. Newer qemu binaries with that qemu fix would not need this
3209 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3210 var->type |= 0x1; /* Accessed */
3212 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3215 vmx->emulation_required = emulation_required(vcpu);
3218 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3220 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3222 *db = (ar >> 14) & 1;
3223 *l = (ar >> 13) & 1;
3226 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3228 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3229 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3232 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3234 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3235 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3238 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3240 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3241 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3244 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3246 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3247 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3250 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3252 struct kvm_segment var;
3255 vmx_get_segment(vcpu, &var, seg);
3257 if (seg == VCPU_SREG_CS)
3259 ar = vmx_segment_access_rights(&var);
3261 if (var.base != (var.selector << 4))
3263 if (var.limit != 0xffff)
3271 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3273 struct kvm_segment cs;
3274 unsigned int cs_rpl;
3276 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3277 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3281 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3285 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3286 if (cs.dpl > cs_rpl)
3289 if (cs.dpl != cs_rpl)
3295 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3299 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3301 struct kvm_segment ss;
3302 unsigned int ss_rpl;
3304 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3305 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3309 if (ss.type != 3 && ss.type != 7)
3313 if (ss.dpl != ss_rpl) /* DPL != RPL */
3321 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3323 struct kvm_segment var;
3326 vmx_get_segment(vcpu, &var, seg);
3327 rpl = var.selector & SEGMENT_RPL_MASK;
3335 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3336 if (var.dpl < rpl) /* DPL < RPL */
3340 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3346 static bool tr_valid(struct kvm_vcpu *vcpu)
3348 struct kvm_segment tr;
3350 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3354 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3356 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3364 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3366 struct kvm_segment ldtr;
3368 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3372 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3382 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3384 struct kvm_segment cs, ss;
3386 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3387 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3389 return ((cs.selector & SEGMENT_RPL_MASK) ==
3390 (ss.selector & SEGMENT_RPL_MASK));
3394 * Check if guest state is valid. Returns true if valid, false if
3396 * We assume that registers are always usable
3398 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3400 if (enable_unrestricted_guest)
3403 /* real mode guest state checks */
3404 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3405 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3407 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3409 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3411 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3413 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3415 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3418 /* protected mode guest state checks */
3419 if (!cs_ss_rpl_check(vcpu))
3421 if (!code_segment_valid(vcpu))
3423 if (!stack_segment_valid(vcpu))
3425 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3427 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3429 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3431 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3433 if (!tr_valid(vcpu))
3435 if (!ldtr_valid(vcpu))
3439 * - Add checks on RIP
3440 * - Add checks on RFLAGS
3446 static int init_rmode_tss(struct kvm *kvm)
3452 idx = srcu_read_lock(&kvm->srcu);
3453 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3454 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3457 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3458 r = kvm_write_guest_page(kvm, fn++, &data,
3459 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3462 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3465 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3469 r = kvm_write_guest_page(kvm, fn, &data,
3470 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3473 srcu_read_unlock(&kvm->srcu, idx);
3477 static int init_rmode_identity_map(struct kvm *kvm)
3479 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3481 kvm_pfn_t identity_map_pfn;
3484 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3485 mutex_lock(&kvm->slots_lock);
3487 if (likely(kvm_vmx->ept_identity_pagetable_done))
3490 if (!kvm_vmx->ept_identity_map_addr)
3491 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3492 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3494 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3495 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3499 idx = srcu_read_lock(&kvm->srcu);
3500 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3503 /* Set up identity-mapping pagetable for EPT in real mode */
3504 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3505 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3506 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3507 r = kvm_write_guest_page(kvm, identity_map_pfn,
3508 &tmp, i * sizeof(tmp), sizeof(tmp));
3512 kvm_vmx->ept_identity_pagetable_done = true;
3515 srcu_read_unlock(&kvm->srcu, idx);
3518 mutex_unlock(&kvm->slots_lock);
3522 static void seg_setup(int seg)
3524 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3527 vmcs_write16(sf->selector, 0);
3528 vmcs_writel(sf->base, 0);
3529 vmcs_write32(sf->limit, 0xffff);
3531 if (seg == VCPU_SREG_CS)
3532 ar |= 0x08; /* code segment */
3534 vmcs_write32(sf->ar_bytes, ar);
3537 static int alloc_apic_access_page(struct kvm *kvm)
3542 mutex_lock(&kvm->slots_lock);
3543 if (kvm->arch.apic_access_page_done)
3545 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3546 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3550 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3551 if (is_error_page(page)) {
3557 * Do not pin the page in memory, so that memory hot-unplug
3558 * is able to migrate it.
3561 kvm->arch.apic_access_page_done = true;
3563 mutex_unlock(&kvm->slots_lock);
3567 int allocate_vpid(void)
3573 spin_lock(&vmx_vpid_lock);
3574 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3575 if (vpid < VMX_NR_VPIDS)
3576 __set_bit(vpid, vmx_vpid_bitmap);
3579 spin_unlock(&vmx_vpid_lock);
3583 void free_vpid(int vpid)
3585 if (!enable_vpid || vpid == 0)
3587 spin_lock(&vmx_vpid_lock);
3588 __clear_bit(vpid, vmx_vpid_bitmap);
3589 spin_unlock(&vmx_vpid_lock);
3592 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3595 int f = sizeof(unsigned long);
3597 if (!cpu_has_vmx_msr_bitmap())
3600 if (static_branch_unlikely(&enable_evmcs))
3601 evmcs_touch_msr_bitmap();
3604 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3605 * have the write-low and read-high bitmap offsets the wrong way round.
3606 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3608 if (msr <= 0x1fff) {
3609 if (type & MSR_TYPE_R)
3611 __clear_bit(msr, msr_bitmap + 0x000 / f);
3613 if (type & MSR_TYPE_W)
3615 __clear_bit(msr, msr_bitmap + 0x800 / f);
3617 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3619 if (type & MSR_TYPE_R)
3621 __clear_bit(msr, msr_bitmap + 0x400 / f);
3623 if (type & MSR_TYPE_W)
3625 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3630 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3633 int f = sizeof(unsigned long);
3635 if (!cpu_has_vmx_msr_bitmap())
3638 if (static_branch_unlikely(&enable_evmcs))
3639 evmcs_touch_msr_bitmap();
3642 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3643 * have the write-low and read-high bitmap offsets the wrong way round.
3644 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3646 if (msr <= 0x1fff) {
3647 if (type & MSR_TYPE_R)
3649 __set_bit(msr, msr_bitmap + 0x000 / f);
3651 if (type & MSR_TYPE_W)
3653 __set_bit(msr, msr_bitmap + 0x800 / f);
3655 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3657 if (type & MSR_TYPE_R)
3659 __set_bit(msr, msr_bitmap + 0x400 / f);
3661 if (type & MSR_TYPE_W)
3663 __set_bit(msr, msr_bitmap + 0xc00 / f);
3668 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3669 u32 msr, int type, bool value)
3672 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3674 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3677 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3681 if (cpu_has_secondary_exec_ctrls() &&
3682 (secondary_exec_controls_get(to_vmx(vcpu)) &
3683 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3684 mode |= MSR_BITMAP_MODE_X2APIC;
3685 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3686 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3692 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3697 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3698 unsigned word = msr / BITS_PER_LONG;
3699 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3700 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3703 if (mode & MSR_BITMAP_MODE_X2APIC) {
3705 * TPR reads and writes can be virtualized even if virtual interrupt
3706 * delivery is not in use.
3708 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3709 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3710 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3711 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3712 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3717 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3719 struct vcpu_vmx *vmx = to_vmx(vcpu);
3720 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3721 u8 mode = vmx_msr_bitmap_mode(vcpu);
3722 u8 changed = mode ^ vmx->msr_bitmap_mode;
3727 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3728 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3730 vmx->msr_bitmap_mode = mode;
3733 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3735 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3736 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3739 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3741 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3743 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3745 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3747 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3748 vmx_set_intercept_for_msr(msr_bitmap,
3749 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3750 vmx_set_intercept_for_msr(msr_bitmap,
3751 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3755 static bool vmx_get_enable_apicv(struct kvm *kvm)
3757 return enable_apicv;
3760 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3762 struct vcpu_vmx *vmx = to_vmx(vcpu);
3767 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3768 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3769 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3772 rvi = vmx_get_rvi();
3774 vapic_page = vmx->nested.virtual_apic_map.hva;
3775 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3777 return ((rvi & 0xf0) > (vppr & 0xf0));
3780 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3784 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3786 if (vcpu->mode == IN_GUEST_MODE) {
3788 * The vector of interrupt to be delivered to vcpu had
3789 * been set in PIR before this function.
3791 * Following cases will be reached in this block, and
3792 * we always send a notification event in all cases as
3795 * Case 1: vcpu keeps in non-root mode. Sending a
3796 * notification event posts the interrupt to vcpu.
3798 * Case 2: vcpu exits to root mode and is still
3799 * runnable. PIR will be synced to vIRR before the
3800 * next vcpu entry. Sending a notification event in
3801 * this case has no effect, as vcpu is not in root
3804 * Case 3: vcpu exits to root mode and is blocked.
3805 * vcpu_block() has already synced PIR to vIRR and
3806 * never blocks vcpu if vIRR is not cleared. Therefore,
3807 * a blocked vcpu here does not wait for any requested
3808 * interrupts in PIR, and sending a notification event
3809 * which has no effect is safe here.
3812 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3819 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3822 struct vcpu_vmx *vmx = to_vmx(vcpu);
3824 if (is_guest_mode(vcpu) &&
3825 vector == vmx->nested.posted_intr_nv) {
3827 * If a posted intr is not recognized by hardware,
3828 * we will accomplish it in the next vmentry.
3830 vmx->nested.pi_pending = true;
3831 kvm_make_request(KVM_REQ_EVENT, vcpu);
3832 /* the PIR and ON have been set by L1. */
3833 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3834 kvm_vcpu_kick(vcpu);
3840 * Send interrupt to vcpu via posted interrupt way.
3841 * 1. If target vcpu is running(non-root mode), send posted interrupt
3842 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3843 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3844 * interrupt from PIR in next vmentry.
3846 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3848 struct vcpu_vmx *vmx = to_vmx(vcpu);
3851 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3855 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3858 /* If a previous notification has sent the IPI, nothing to do. */
3859 if (pi_test_and_set_on(&vmx->pi_desc))
3862 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3863 kvm_vcpu_kick(vcpu);
3867 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3868 * will not change in the lifetime of the guest.
3869 * Note that host-state that does change is set elsewhere. E.g., host-state
3870 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3872 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3876 unsigned long cr0, cr3, cr4;
3879 WARN_ON(cr0 & X86_CR0_TS);
3880 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3883 * Save the most likely value for this task's CR3 in the VMCS.
3884 * We can't use __get_current_cr3_fast() because we're not atomic.
3887 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
3888 vmx->loaded_vmcs->host_state.cr3 = cr3;
3890 /* Save the most likely value for this task's CR4 in the VMCS. */
3891 cr4 = cr4_read_shadow();
3892 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
3893 vmx->loaded_vmcs->host_state.cr4 = cr4;
3895 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3896 #ifdef CONFIG_X86_64
3898 * Load null selectors, so we can avoid reloading them in
3899 * vmx_prepare_switch_to_host(), in case userspace uses
3900 * the null selectors too (the expected case).
3902 vmcs_write16(HOST_DS_SELECTOR, 0);
3903 vmcs_write16(HOST_ES_SELECTOR, 0);
3905 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3906 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3908 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3909 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3911 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
3913 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3915 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3916 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3917 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3918 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3920 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3921 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3922 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3925 if (cpu_has_load_ia32_efer())
3926 vmcs_write64(HOST_IA32_EFER, host_efer);
3929 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3931 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3933 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3934 if (is_guest_mode(&vmx->vcpu))
3935 vmx->vcpu.arch.cr4_guest_owned_bits &=
3936 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3937 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3940 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3942 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3944 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3945 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3948 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3950 if (!enable_preemption_timer)
3951 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3953 return pin_based_exec_ctrl;
3956 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3958 struct vcpu_vmx *vmx = to_vmx(vcpu);
3960 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3961 if (cpu_has_secondary_exec_ctrls()) {
3962 if (kvm_vcpu_apicv_active(vcpu))
3963 secondary_exec_controls_setbit(vmx,
3964 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3965 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3967 secondary_exec_controls_clearbit(vmx,
3968 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3969 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3972 if (cpu_has_vmx_msr_bitmap())
3973 vmx_update_msr_bitmap(vcpu);
3976 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3978 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3980 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3981 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3983 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3984 exec_control &= ~CPU_BASED_TPR_SHADOW;
3985 #ifdef CONFIG_X86_64
3986 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3987 CPU_BASED_CR8_LOAD_EXITING;
3991 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3992 CPU_BASED_CR3_LOAD_EXITING |
3993 CPU_BASED_INVLPG_EXITING;
3994 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3995 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3996 CPU_BASED_MONITOR_EXITING);
3997 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3998 exec_control &= ~CPU_BASED_HLT_EXITING;
3999 return exec_control;
4003 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4005 struct kvm_vcpu *vcpu = &vmx->vcpu;
4007 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4009 if (pt_mode == PT_MODE_SYSTEM)
4010 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4011 if (!cpu_need_virtualize_apic_accesses(vcpu))
4012 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4014 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4016 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4017 enable_unrestricted_guest = 0;
4019 if (!enable_unrestricted_guest)
4020 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4021 if (kvm_pause_in_guest(vmx->vcpu.kvm))
4022 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4023 if (!kvm_vcpu_apicv_active(vcpu))
4024 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4025 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4026 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4028 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4029 * in vmx_set_cr4. */
4030 exec_control &= ~SECONDARY_EXEC_DESC;
4032 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4034 We can NOT enable shadow_vmcs here because we don't have yet
4037 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4040 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4042 if (vmx_xsaves_supported()) {
4043 /* Exposing XSAVES only when XSAVE is exposed */
4044 bool xsaves_enabled =
4045 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4046 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4048 vcpu->arch.xsaves_enabled = xsaves_enabled;
4050 if (!xsaves_enabled)
4051 exec_control &= ~SECONDARY_EXEC_XSAVES;
4055 vmx->nested.msrs.secondary_ctls_high |=
4056 SECONDARY_EXEC_XSAVES;
4058 vmx->nested.msrs.secondary_ctls_high &=
4059 ~SECONDARY_EXEC_XSAVES;
4063 if (vmx_rdtscp_supported()) {
4064 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4065 if (!rdtscp_enabled)
4066 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4070 vmx->nested.msrs.secondary_ctls_high |=
4071 SECONDARY_EXEC_RDTSCP;
4073 vmx->nested.msrs.secondary_ctls_high &=
4074 ~SECONDARY_EXEC_RDTSCP;
4078 if (vmx_invpcid_supported()) {
4079 /* Exposing INVPCID only when PCID is exposed */
4080 bool invpcid_enabled =
4081 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4082 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4084 if (!invpcid_enabled) {
4085 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4086 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4090 if (invpcid_enabled)
4091 vmx->nested.msrs.secondary_ctls_high |=
4092 SECONDARY_EXEC_ENABLE_INVPCID;
4094 vmx->nested.msrs.secondary_ctls_high &=
4095 ~SECONDARY_EXEC_ENABLE_INVPCID;
4099 if (vmx_rdrand_supported()) {
4100 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4102 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4106 vmx->nested.msrs.secondary_ctls_high |=
4107 SECONDARY_EXEC_RDRAND_EXITING;
4109 vmx->nested.msrs.secondary_ctls_high &=
4110 ~SECONDARY_EXEC_RDRAND_EXITING;
4114 if (vmx_rdseed_supported()) {
4115 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4117 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4121 vmx->nested.msrs.secondary_ctls_high |=
4122 SECONDARY_EXEC_RDSEED_EXITING;
4124 vmx->nested.msrs.secondary_ctls_high &=
4125 ~SECONDARY_EXEC_RDSEED_EXITING;
4129 if (vmx_waitpkg_supported()) {
4130 bool waitpkg_enabled =
4131 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4133 if (!waitpkg_enabled)
4134 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4137 if (waitpkg_enabled)
4138 vmx->nested.msrs.secondary_ctls_high |=
4139 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4141 vmx->nested.msrs.secondary_ctls_high &=
4142 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4146 vmx->secondary_exec_control = exec_control;
4149 static void ept_set_mmio_spte_mask(void)
4152 * EPT Misconfigurations can be generated if the value of bits 2:0
4153 * of an EPT paging-structure entry is 110b (write/execute).
4155 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4156 VMX_EPT_MISCONFIG_WX_VALUE, 0);
4159 #define VMX_XSS_EXIT_BITMAP 0
4162 * Noting that the initialization of Guest-state Area of VMCS is in
4165 static void init_vmcs(struct vcpu_vmx *vmx)
4168 nested_vmx_set_vmcs_shadowing_bitmap();
4170 if (cpu_has_vmx_msr_bitmap())
4171 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4173 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4176 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4178 exec_controls_set(vmx, vmx_exec_control(vmx));
4180 if (cpu_has_secondary_exec_ctrls()) {
4181 vmx_compute_secondary_exec_control(vmx);
4182 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4185 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4186 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4187 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4188 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4189 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4191 vmcs_write16(GUEST_INTR_STATUS, 0);
4193 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4194 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4197 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4198 vmcs_write32(PLE_GAP, ple_gap);
4199 vmx->ple_window = ple_window;
4200 vmx->ple_window_dirty = true;
4203 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4204 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4205 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4207 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4208 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4209 vmx_set_constant_host_state(vmx);
4210 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4211 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4213 if (cpu_has_vmx_vmfunc())
4214 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4216 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4217 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4218 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4219 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4220 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4222 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4223 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4225 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4227 /* 22.2.1, 20.8.1 */
4228 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4230 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4231 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4233 set_cr4_guest_host_mask(vmx);
4236 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4238 if (vmx_xsaves_supported())
4239 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4242 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4243 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4246 if (cpu_has_vmx_encls_vmexit())
4247 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4249 if (pt_mode == PT_MODE_HOST_GUEST) {
4250 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4251 /* Bit[6~0] are forced to 1, writes are ignored. */
4252 vmx->pt_desc.guest.output_mask = 0x7F;
4253 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4257 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4259 struct vcpu_vmx *vmx = to_vmx(vcpu);
4260 struct msr_data apic_base_msr;
4263 vmx->rmode.vm86_active = 0;
4266 vmx->msr_ia32_umwait_control = 0;
4268 vcpu->arch.microcode_version = 0x100000000ULL;
4269 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4270 vmx->hv_deadline_tsc = -1;
4271 kvm_set_cr8(vcpu, 0);
4274 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4275 MSR_IA32_APICBASE_ENABLE;
4276 if (kvm_vcpu_is_reset_bsp(vcpu))
4277 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4278 apic_base_msr.host_initiated = true;
4279 kvm_set_apic_base(vcpu, &apic_base_msr);
4282 vmx_segment_cache_clear(vmx);
4284 seg_setup(VCPU_SREG_CS);
4285 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4286 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4288 seg_setup(VCPU_SREG_DS);
4289 seg_setup(VCPU_SREG_ES);
4290 seg_setup(VCPU_SREG_FS);
4291 seg_setup(VCPU_SREG_GS);
4292 seg_setup(VCPU_SREG_SS);
4294 vmcs_write16(GUEST_TR_SELECTOR, 0);
4295 vmcs_writel(GUEST_TR_BASE, 0);
4296 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4297 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4299 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4300 vmcs_writel(GUEST_LDTR_BASE, 0);
4301 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4302 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4305 vmcs_write32(GUEST_SYSENTER_CS, 0);
4306 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4307 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4308 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4311 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4312 kvm_rip_write(vcpu, 0xfff0);
4314 vmcs_writel(GUEST_GDTR_BASE, 0);
4315 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4317 vmcs_writel(GUEST_IDTR_BASE, 0);
4318 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4320 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4321 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4322 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4323 if (kvm_mpx_supported())
4324 vmcs_write64(GUEST_BNDCFGS, 0);
4328 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4330 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4331 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4332 if (cpu_need_tpr_shadow(vcpu))
4333 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4334 __pa(vcpu->arch.apic->regs));
4335 vmcs_write32(TPR_THRESHOLD, 0);
4338 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4340 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4341 vmx->vcpu.arch.cr0 = cr0;
4342 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4343 vmx_set_cr4(vcpu, 0);
4344 vmx_set_efer(vcpu, 0);
4346 update_exception_bitmap(vcpu);
4348 vpid_sync_context(vmx->vpid);
4350 vmx_clear_hlt(vcpu);
4353 static void enable_irq_window(struct kvm_vcpu *vcpu)
4355 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4358 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4361 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4362 enable_irq_window(vcpu);
4366 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
4369 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4371 struct vcpu_vmx *vmx = to_vmx(vcpu);
4373 int irq = vcpu->arch.interrupt.nr;
4375 trace_kvm_inj_virq(irq);
4377 ++vcpu->stat.irq_injections;
4378 if (vmx->rmode.vm86_active) {
4380 if (vcpu->arch.interrupt.soft)
4381 inc_eip = vcpu->arch.event_exit_inst_len;
4382 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4385 intr = irq | INTR_INFO_VALID_MASK;
4386 if (vcpu->arch.interrupt.soft) {
4387 intr |= INTR_TYPE_SOFT_INTR;
4388 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4389 vmx->vcpu.arch.event_exit_inst_len);
4391 intr |= INTR_TYPE_EXT_INTR;
4392 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4394 vmx_clear_hlt(vcpu);
4397 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4399 struct vcpu_vmx *vmx = to_vmx(vcpu);
4403 * Tracking the NMI-blocked state in software is built upon
4404 * finding the next open IRQ window. This, in turn, depends on
4405 * well-behaving guests: They have to keep IRQs disabled at
4406 * least as long as the NMI handler runs. Otherwise we may
4407 * cause NMI nesting, maybe breaking the guest. But as this is
4408 * highly unlikely, we can live with the residual risk.
4410 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4411 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4414 ++vcpu->stat.nmi_injections;
4415 vmx->loaded_vmcs->nmi_known_unmasked = false;
4417 if (vmx->rmode.vm86_active) {
4418 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4422 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4423 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4425 vmx_clear_hlt(vcpu);
4428 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4430 struct vcpu_vmx *vmx = to_vmx(vcpu);
4434 return vmx->loaded_vmcs->soft_vnmi_blocked;
4435 if (vmx->loaded_vmcs->nmi_known_unmasked)
4437 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4438 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4442 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4444 struct vcpu_vmx *vmx = to_vmx(vcpu);
4447 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4448 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4449 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4452 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4454 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4455 GUEST_INTR_STATE_NMI);
4457 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4458 GUEST_INTR_STATE_NMI);
4462 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4464 if (to_vmx(vcpu)->nested.nested_run_pending)
4468 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4471 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4472 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4473 | GUEST_INTR_STATE_NMI));
4476 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4478 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4479 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4480 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4481 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4484 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4488 if (enable_unrestricted_guest)
4491 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4495 to_kvm_vmx(kvm)->tss_addr = addr;
4496 return init_rmode_tss(kvm);
4499 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4501 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4505 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4510 * Update instruction length as we may reinject the exception
4511 * from user space while in guest debugging mode.
4513 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4514 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4515 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4519 if (vcpu->guest_debug &
4520 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4537 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4538 int vec, u32 err_code)
4541 * Instruction with address size override prefix opcode 0x67
4542 * Cause the #SS fault with 0 error code in VM86 mode.
4544 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4545 if (kvm_emulate_instruction(vcpu, 0)) {
4546 if (vcpu->arch.halt_request) {
4547 vcpu->arch.halt_request = 0;
4548 return kvm_vcpu_halt(vcpu);
4556 * Forward all other exceptions that are valid in real mode.
4557 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4558 * the required debugging infrastructure rework.
4560 kvm_queue_exception(vcpu, vec);
4565 * Trigger machine check on the host. We assume all the MSRs are already set up
4566 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4567 * We pass a fake environment to the machine check handler because we want
4568 * the guest to be always treated like user space, no matter what context
4569 * it used internally.
4571 static void kvm_machine_check(void)
4573 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4574 struct pt_regs regs = {
4575 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4576 .flags = X86_EFLAGS_IF,
4579 do_machine_check(®s, 0);
4583 static int handle_machine_check(struct kvm_vcpu *vcpu)
4585 /* handled by vmx_vcpu_run() */
4589 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4591 struct vcpu_vmx *vmx = to_vmx(vcpu);
4592 struct kvm_run *kvm_run = vcpu->run;
4593 u32 intr_info, ex_no, error_code;
4594 unsigned long cr2, rip, dr6;
4597 vect_info = vmx->idt_vectoring_info;
4598 intr_info = vmx->exit_intr_info;
4600 if (is_machine_check(intr_info) || is_nmi(intr_info))
4601 return 1; /* handled by handle_exception_nmi_irqoff() */
4603 if (is_invalid_opcode(intr_info))
4604 return handle_ud(vcpu);
4607 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4608 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4610 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4611 WARN_ON_ONCE(!enable_vmware_backdoor);
4614 * VMware backdoor emulation on #GP interception only handles
4615 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4616 * error code on #GP.
4619 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4622 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4626 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4627 * MMIO, it is better to report an internal error.
4628 * See the comments in vmx_handle_exit.
4630 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4631 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4632 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4633 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4634 vcpu->run->internal.ndata = 3;
4635 vcpu->run->internal.data[0] = vect_info;
4636 vcpu->run->internal.data[1] = intr_info;
4637 vcpu->run->internal.data[2] = error_code;
4641 if (is_page_fault(intr_info)) {
4642 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4643 /* EPT won't cause page fault directly */
4644 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4645 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4648 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4650 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4651 return handle_rmode_exception(vcpu, ex_no, error_code);
4655 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4658 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4659 if (!(vcpu->guest_debug &
4660 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4661 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4662 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4663 if (is_icebp(intr_info))
4664 WARN_ON(!skip_emulated_instruction(vcpu));
4666 kvm_queue_exception(vcpu, DB_VECTOR);
4669 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4670 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4674 * Update instruction length as we may reinject #BP from
4675 * user space while in guest debugging mode. Reading it for
4676 * #DB as well causes no harm, it is not used in that case.
4678 vmx->vcpu.arch.event_exit_inst_len =
4679 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4680 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4681 rip = kvm_rip_read(vcpu);
4682 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4683 kvm_run->debug.arch.exception = ex_no;
4686 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4687 kvm_run->ex.exception = ex_no;
4688 kvm_run->ex.error_code = error_code;
4694 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4696 ++vcpu->stat.irq_exits;
4700 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4702 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4703 vcpu->mmio_needed = 0;
4707 static int handle_io(struct kvm_vcpu *vcpu)
4709 unsigned long exit_qualification;
4710 int size, in, string;
4713 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4714 string = (exit_qualification & 16) != 0;
4716 ++vcpu->stat.io_exits;
4719 return kvm_emulate_instruction(vcpu, 0);
4721 port = exit_qualification >> 16;
4722 size = (exit_qualification & 7) + 1;
4723 in = (exit_qualification & 8) != 0;
4725 return kvm_fast_pio(vcpu, size, port, in);
4729 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4732 * Patch in the VMCALL instruction:
4734 hypercall[0] = 0x0f;
4735 hypercall[1] = 0x01;
4736 hypercall[2] = 0xc1;
4739 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4740 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4742 if (is_guest_mode(vcpu)) {
4743 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4744 unsigned long orig_val = val;
4747 * We get here when L2 changed cr0 in a way that did not change
4748 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4749 * but did change L0 shadowed bits. So we first calculate the
4750 * effective cr0 value that L1 would like to write into the
4751 * hardware. It consists of the L2-owned bits from the new
4752 * value combined with the L1-owned bits from L1's guest_cr0.
4754 val = (val & ~vmcs12->cr0_guest_host_mask) |
4755 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4757 if (!nested_guest_cr0_valid(vcpu, val))
4760 if (kvm_set_cr0(vcpu, val))
4762 vmcs_writel(CR0_READ_SHADOW, orig_val);
4765 if (to_vmx(vcpu)->nested.vmxon &&
4766 !nested_host_cr0_valid(vcpu, val))
4769 return kvm_set_cr0(vcpu, val);
4773 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4775 if (is_guest_mode(vcpu)) {
4776 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4777 unsigned long orig_val = val;
4779 /* analogously to handle_set_cr0 */
4780 val = (val & ~vmcs12->cr4_guest_host_mask) |
4781 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4782 if (kvm_set_cr4(vcpu, val))
4784 vmcs_writel(CR4_READ_SHADOW, orig_val);
4787 return kvm_set_cr4(vcpu, val);
4790 static int handle_desc(struct kvm_vcpu *vcpu)
4792 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4793 return kvm_emulate_instruction(vcpu, 0);
4796 static int handle_cr(struct kvm_vcpu *vcpu)
4798 unsigned long exit_qualification, val;
4804 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4805 cr = exit_qualification & 15;
4806 reg = (exit_qualification >> 8) & 15;
4807 switch ((exit_qualification >> 4) & 3) {
4808 case 0: /* mov to cr */
4809 val = kvm_register_readl(vcpu, reg);
4810 trace_kvm_cr_write(cr, val);
4813 err = handle_set_cr0(vcpu, val);
4814 return kvm_complete_insn_gp(vcpu, err);
4816 WARN_ON_ONCE(enable_unrestricted_guest);
4817 err = kvm_set_cr3(vcpu, val);
4818 return kvm_complete_insn_gp(vcpu, err);
4820 err = handle_set_cr4(vcpu, val);
4821 return kvm_complete_insn_gp(vcpu, err);
4823 u8 cr8_prev = kvm_get_cr8(vcpu);
4825 err = kvm_set_cr8(vcpu, cr8);
4826 ret = kvm_complete_insn_gp(vcpu, err);
4827 if (lapic_in_kernel(vcpu))
4829 if (cr8_prev <= cr8)
4832 * TODO: we might be squashing a
4833 * KVM_GUESTDBG_SINGLESTEP-triggered
4834 * KVM_EXIT_DEBUG here.
4836 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4842 WARN_ONCE(1, "Guest should always own CR0.TS");
4843 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4844 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4845 return kvm_skip_emulated_instruction(vcpu);
4846 case 1: /*mov from cr*/
4849 WARN_ON_ONCE(enable_unrestricted_guest);
4850 val = kvm_read_cr3(vcpu);
4851 kvm_register_write(vcpu, reg, val);
4852 trace_kvm_cr_read(cr, val);
4853 return kvm_skip_emulated_instruction(vcpu);
4855 val = kvm_get_cr8(vcpu);
4856 kvm_register_write(vcpu, reg, val);
4857 trace_kvm_cr_read(cr, val);
4858 return kvm_skip_emulated_instruction(vcpu);
4862 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4863 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4864 kvm_lmsw(vcpu, val);
4866 return kvm_skip_emulated_instruction(vcpu);
4870 vcpu->run->exit_reason = 0;
4871 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4872 (int)(exit_qualification >> 4) & 3, cr);
4876 static int handle_dr(struct kvm_vcpu *vcpu)
4878 unsigned long exit_qualification;
4881 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4882 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4884 /* First, if DR does not exist, trigger UD */
4885 if (!kvm_require_dr(vcpu, dr))
4888 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4889 if (!kvm_require_cpl(vcpu, 0))
4891 dr7 = vmcs_readl(GUEST_DR7);
4894 * As the vm-exit takes precedence over the debug trap, we
4895 * need to emulate the latter, either for the host or the
4896 * guest debugging itself.
4898 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4899 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4900 vcpu->run->debug.arch.dr7 = dr7;
4901 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4902 vcpu->run->debug.arch.exception = DB_VECTOR;
4903 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4906 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4907 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4908 kvm_queue_exception(vcpu, DB_VECTOR);
4913 if (vcpu->guest_debug == 0) {
4914 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4917 * No more DR vmexits; force a reload of the debug registers
4918 * and reenter on this instruction. The next vmexit will
4919 * retrieve the full state of the debug registers.
4921 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4925 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4926 if (exit_qualification & TYPE_MOV_FROM_DR) {
4929 if (kvm_get_dr(vcpu, dr, &val))
4931 kvm_register_write(vcpu, reg, val);
4933 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4936 return kvm_skip_emulated_instruction(vcpu);
4939 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4941 return vcpu->arch.dr6;
4944 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4948 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4950 get_debugreg(vcpu->arch.db[0], 0);
4951 get_debugreg(vcpu->arch.db[1], 1);
4952 get_debugreg(vcpu->arch.db[2], 2);
4953 get_debugreg(vcpu->arch.db[3], 3);
4954 get_debugreg(vcpu->arch.dr6, 6);
4955 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4957 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4958 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4961 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4963 vmcs_writel(GUEST_DR7, val);
4966 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4968 kvm_apic_update_ppr(vcpu);
4972 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4974 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4976 kvm_make_request(KVM_REQ_EVENT, vcpu);
4978 ++vcpu->stat.irq_window_exits;
4982 static int handle_vmcall(struct kvm_vcpu *vcpu)
4984 return kvm_emulate_hypercall(vcpu);
4987 static int handle_invd(struct kvm_vcpu *vcpu)
4989 return kvm_emulate_instruction(vcpu, 0);
4992 static int handle_invlpg(struct kvm_vcpu *vcpu)
4994 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4996 kvm_mmu_invlpg(vcpu, exit_qualification);
4997 return kvm_skip_emulated_instruction(vcpu);
5000 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5004 err = kvm_rdpmc(vcpu);
5005 return kvm_complete_insn_gp(vcpu, err);
5008 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5010 return kvm_emulate_wbinvd(vcpu);
5013 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5015 u64 new_bv = kvm_read_edx_eax(vcpu);
5016 u32 index = kvm_rcx_read(vcpu);
5018 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5019 return kvm_skip_emulated_instruction(vcpu);
5023 static int handle_apic_access(struct kvm_vcpu *vcpu)
5025 if (likely(fasteoi)) {
5026 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5027 int access_type, offset;
5029 access_type = exit_qualification & APIC_ACCESS_TYPE;
5030 offset = exit_qualification & APIC_ACCESS_OFFSET;
5032 * Sane guest uses MOV to write EOI, with written value
5033 * not cared. So make a short-circuit here by avoiding
5034 * heavy instruction emulation.
5036 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5037 (offset == APIC_EOI)) {
5038 kvm_lapic_set_eoi(vcpu);
5039 return kvm_skip_emulated_instruction(vcpu);
5042 return kvm_emulate_instruction(vcpu, 0);
5045 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5047 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5048 int vector = exit_qualification & 0xff;
5050 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5051 kvm_apic_set_eoi_accelerated(vcpu, vector);
5055 static int handle_apic_write(struct kvm_vcpu *vcpu)
5057 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5058 u32 offset = exit_qualification & 0xfff;
5060 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5061 kvm_apic_write_nodecode(vcpu, offset);
5065 static int handle_task_switch(struct kvm_vcpu *vcpu)
5067 struct vcpu_vmx *vmx = to_vmx(vcpu);
5068 unsigned long exit_qualification;
5069 bool has_error_code = false;
5072 int reason, type, idt_v, idt_index;
5074 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5075 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5076 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5078 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5080 reason = (u32)exit_qualification >> 30;
5081 if (reason == TASK_SWITCH_GATE && idt_v) {
5083 case INTR_TYPE_NMI_INTR:
5084 vcpu->arch.nmi_injected = false;
5085 vmx_set_nmi_mask(vcpu, true);
5087 case INTR_TYPE_EXT_INTR:
5088 case INTR_TYPE_SOFT_INTR:
5089 kvm_clear_interrupt_queue(vcpu);
5091 case INTR_TYPE_HARD_EXCEPTION:
5092 if (vmx->idt_vectoring_info &
5093 VECTORING_INFO_DELIVER_CODE_MASK) {
5094 has_error_code = true;
5096 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5099 case INTR_TYPE_SOFT_EXCEPTION:
5100 kvm_clear_exception_queue(vcpu);
5106 tss_selector = exit_qualification;
5108 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5109 type != INTR_TYPE_EXT_INTR &&
5110 type != INTR_TYPE_NMI_INTR))
5111 WARN_ON(!skip_emulated_instruction(vcpu));
5114 * TODO: What about debug traps on tss switch?
5115 * Are we supposed to inject them and update dr6?
5117 return kvm_task_switch(vcpu, tss_selector,
5118 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5119 reason, has_error_code, error_code);
5122 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5124 unsigned long exit_qualification;
5128 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5131 * EPT violation happened while executing iret from NMI,
5132 * "blocked by NMI" bit has to be set before next VM entry.
5133 * There are errata that may cause this bit to not be set:
5136 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5138 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5139 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5141 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5142 trace_kvm_page_fault(gpa, exit_qualification);
5144 /* Is it a read fault? */
5145 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5146 ? PFERR_USER_MASK : 0;
5147 /* Is it a write fault? */
5148 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5149 ? PFERR_WRITE_MASK : 0;
5150 /* Is it a fetch fault? */
5151 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5152 ? PFERR_FETCH_MASK : 0;
5153 /* ept page table entry is present? */
5154 error_code |= (exit_qualification &
5155 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5156 EPT_VIOLATION_EXECUTABLE))
5157 ? PFERR_PRESENT_MASK : 0;
5159 error_code |= (exit_qualification & 0x100) != 0 ?
5160 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5162 vcpu->arch.exit_qualification = exit_qualification;
5163 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5166 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5171 * A nested guest cannot optimize MMIO vmexits, because we have an
5172 * nGPA here instead of the required GPA.
5174 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5175 if (!is_guest_mode(vcpu) &&
5176 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5177 trace_kvm_fast_mmio(gpa);
5178 return kvm_skip_emulated_instruction(vcpu);
5181 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5184 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5186 WARN_ON_ONCE(!enable_vnmi);
5187 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
5188 ++vcpu->stat.nmi_window_exits;
5189 kvm_make_request(KVM_REQ_EVENT, vcpu);
5194 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5196 struct vcpu_vmx *vmx = to_vmx(vcpu);
5197 bool intr_window_requested;
5198 unsigned count = 130;
5201 * We should never reach the point where we are emulating L2
5202 * due to invalid guest state as that means we incorrectly
5203 * allowed a nested VMEntry with an invalid vmcs12.
5205 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5207 intr_window_requested = exec_controls_get(vmx) &
5208 CPU_BASED_VIRTUAL_INTR_PENDING;
5210 while (vmx->emulation_required && count-- != 0) {
5211 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5212 return handle_interrupt_window(&vmx->vcpu);
5214 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5217 if (!kvm_emulate_instruction(vcpu, 0))
5220 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5221 vcpu->arch.exception.pending) {
5222 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5223 vcpu->run->internal.suberror =
5224 KVM_INTERNAL_ERROR_EMULATION;
5225 vcpu->run->internal.ndata = 0;
5229 if (vcpu->arch.halt_request) {
5230 vcpu->arch.halt_request = 0;
5231 return kvm_vcpu_halt(vcpu);
5235 * Note, return 1 and not 0, vcpu_run() is responsible for
5236 * morphing the pending signal into the proper return code.
5238 if (signal_pending(current))
5248 static void grow_ple_window(struct kvm_vcpu *vcpu)
5250 struct vcpu_vmx *vmx = to_vmx(vcpu);
5251 unsigned int old = vmx->ple_window;
5253 vmx->ple_window = __grow_ple_window(old, ple_window,
5257 if (vmx->ple_window != old) {
5258 vmx->ple_window_dirty = true;
5259 trace_kvm_ple_window_update(vcpu->vcpu_id,
5260 vmx->ple_window, old);
5264 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5266 struct vcpu_vmx *vmx = to_vmx(vcpu);
5267 unsigned int old = vmx->ple_window;
5269 vmx->ple_window = __shrink_ple_window(old, ple_window,
5273 if (vmx->ple_window != old) {
5274 vmx->ple_window_dirty = true;
5275 trace_kvm_ple_window_update(vcpu->vcpu_id,
5276 vmx->ple_window, old);
5281 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5283 static void wakeup_handler(void)
5285 struct kvm_vcpu *vcpu;
5286 int cpu = smp_processor_id();
5288 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5289 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5290 blocked_vcpu_list) {
5291 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5293 if (pi_test_on(pi_desc) == 1)
5294 kvm_vcpu_kick(vcpu);
5296 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5299 static void vmx_enable_tdp(void)
5301 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5302 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5303 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5304 0ull, VMX_EPT_EXECUTABLE_MASK,
5305 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5306 VMX_EPT_RWX_MASK, 0ull);
5308 ept_set_mmio_spte_mask();
5313 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5314 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5316 static int handle_pause(struct kvm_vcpu *vcpu)
5318 if (!kvm_pause_in_guest(vcpu->kvm))
5319 grow_ple_window(vcpu);
5322 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5323 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5324 * never set PAUSE_EXITING and just set PLE if supported,
5325 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5327 kvm_vcpu_on_spin(vcpu, true);
5328 return kvm_skip_emulated_instruction(vcpu);
5331 static int handle_nop(struct kvm_vcpu *vcpu)
5333 return kvm_skip_emulated_instruction(vcpu);
5336 static int handle_mwait(struct kvm_vcpu *vcpu)
5338 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5339 return handle_nop(vcpu);
5342 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5344 kvm_queue_exception(vcpu, UD_VECTOR);
5348 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5353 static int handle_monitor(struct kvm_vcpu *vcpu)
5355 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5356 return handle_nop(vcpu);
5359 static int handle_invpcid(struct kvm_vcpu *vcpu)
5361 u32 vmx_instruction_info;
5365 struct x86_exception e;
5367 unsigned long roots_to_free = 0;
5373 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5374 kvm_queue_exception(vcpu, UD_VECTOR);
5378 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5379 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5382 kvm_inject_gp(vcpu, 0);
5386 /* According to the Intel instruction reference, the memory operand
5387 * is read even if it isn't needed (e.g., for type==all)
5389 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5390 vmx_instruction_info, false,
5391 sizeof(operand), &gva))
5394 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5395 kvm_inject_page_fault(vcpu, &e);
5399 if (operand.pcid >> 12 != 0) {
5400 kvm_inject_gp(vcpu, 0);
5404 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5407 case INVPCID_TYPE_INDIV_ADDR:
5408 if ((!pcid_enabled && (operand.pcid != 0)) ||
5409 is_noncanonical_address(operand.gla, vcpu)) {
5410 kvm_inject_gp(vcpu, 0);
5413 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5414 return kvm_skip_emulated_instruction(vcpu);
5416 case INVPCID_TYPE_SINGLE_CTXT:
5417 if (!pcid_enabled && (operand.pcid != 0)) {
5418 kvm_inject_gp(vcpu, 0);
5422 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5423 kvm_mmu_sync_roots(vcpu);
5424 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5427 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5428 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5430 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5432 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5434 * If neither the current cr3 nor any of the prev_roots use the
5435 * given PCID, then nothing needs to be done here because a
5436 * resync will happen anyway before switching to any other CR3.
5439 return kvm_skip_emulated_instruction(vcpu);
5441 case INVPCID_TYPE_ALL_NON_GLOBAL:
5443 * Currently, KVM doesn't mark global entries in the shadow
5444 * page tables, so a non-global flush just degenerates to a
5445 * global flush. If needed, we could optimize this later by
5446 * keeping track of global entries in shadow page tables.
5450 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5451 kvm_mmu_unload(vcpu);
5452 return kvm_skip_emulated_instruction(vcpu);
5455 BUG(); /* We have already checked above that type <= 3 */
5459 static int handle_pml_full(struct kvm_vcpu *vcpu)
5461 unsigned long exit_qualification;
5463 trace_kvm_pml_full(vcpu->vcpu_id);
5465 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5468 * PML buffer FULL happened while executing iret from NMI,
5469 * "blocked by NMI" bit has to be set before next VM entry.
5471 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5473 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5474 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5475 GUEST_INTR_STATE_NMI);
5478 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5479 * here.., and there's no userspace involvement needed for PML.
5484 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5486 struct vcpu_vmx *vmx = to_vmx(vcpu);
5488 if (!vmx->req_immediate_exit &&
5489 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5490 kvm_lapic_expired_hv_timer(vcpu);
5496 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5497 * are overwritten by nested_vmx_setup() when nested=1.
5499 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5501 kvm_queue_exception(vcpu, UD_VECTOR);
5505 static int handle_encls(struct kvm_vcpu *vcpu)
5508 * SGX virtualization is not yet supported. There is no software
5509 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5510 * to prevent the guest from executing ENCLS.
5512 kvm_queue_exception(vcpu, UD_VECTOR);
5517 * The exit handlers return 1 if the exit was handled fully and guest execution
5518 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5519 * to be done to userspace and return 0.
5521 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5522 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5523 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5524 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5525 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5526 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5527 [EXIT_REASON_CR_ACCESS] = handle_cr,
5528 [EXIT_REASON_DR_ACCESS] = handle_dr,
5529 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5530 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5531 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
5532 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5533 [EXIT_REASON_HLT] = kvm_emulate_halt,
5534 [EXIT_REASON_INVD] = handle_invd,
5535 [EXIT_REASON_INVLPG] = handle_invlpg,
5536 [EXIT_REASON_RDPMC] = handle_rdpmc,
5537 [EXIT_REASON_VMCALL] = handle_vmcall,
5538 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5539 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5540 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5541 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5542 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5543 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5544 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5545 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5546 [EXIT_REASON_VMON] = handle_vmx_instruction,
5547 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5548 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5549 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5550 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5551 [EXIT_REASON_WBINVD] = handle_wbinvd,
5552 [EXIT_REASON_XSETBV] = handle_xsetbv,
5553 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5554 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5555 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5556 [EXIT_REASON_LDTR_TR] = handle_desc,
5557 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5558 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5559 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5560 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5561 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5562 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5563 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5564 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5565 [EXIT_REASON_RDRAND] = handle_invalid_op,
5566 [EXIT_REASON_RDSEED] = handle_invalid_op,
5567 [EXIT_REASON_PML_FULL] = handle_pml_full,
5568 [EXIT_REASON_INVPCID] = handle_invpcid,
5569 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5570 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5571 [EXIT_REASON_ENCLS] = handle_encls,
5574 static const int kvm_vmx_max_exit_handlers =
5575 ARRAY_SIZE(kvm_vmx_exit_handlers);
5577 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5579 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5580 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5583 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5586 __free_page(vmx->pml_pg);
5591 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5593 struct vcpu_vmx *vmx = to_vmx(vcpu);
5597 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5599 /* Do nothing if PML buffer is empty */
5600 if (pml_idx == (PML_ENTITY_NUM - 1))
5603 /* PML index always points to next available PML buffer entity */
5604 if (pml_idx >= PML_ENTITY_NUM)
5609 pml_buf = page_address(vmx->pml_pg);
5610 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5613 gpa = pml_buf[pml_idx];
5614 WARN_ON(gpa & (PAGE_SIZE - 1));
5615 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5618 /* reset PML index */
5619 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5623 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5624 * Called before reporting dirty_bitmap to userspace.
5626 static void kvm_flush_pml_buffers(struct kvm *kvm)
5629 struct kvm_vcpu *vcpu;
5631 * We only need to kick vcpu out of guest mode here, as PML buffer
5632 * is flushed at beginning of all VMEXITs, and it's obvious that only
5633 * vcpus running in guest are possible to have unflushed GPAs in PML
5636 kvm_for_each_vcpu(i, vcpu, kvm)
5637 kvm_vcpu_kick(vcpu);
5640 static void vmx_dump_sel(char *name, uint32_t sel)
5642 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5643 name, vmcs_read16(sel),
5644 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5645 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5646 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5649 static void vmx_dump_dtsel(char *name, uint32_t limit)
5651 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5652 name, vmcs_read32(limit),
5653 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5656 void dump_vmcs(void)
5658 u32 vmentry_ctl, vmexit_ctl;
5659 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5664 if (!dump_invalid_vmcs) {
5665 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5669 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5670 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5671 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5672 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5673 cr4 = vmcs_readl(GUEST_CR4);
5674 efer = vmcs_read64(GUEST_IA32_EFER);
5675 secondary_exec_control = 0;
5676 if (cpu_has_secondary_exec_ctrls())
5677 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5679 pr_err("*** Guest State ***\n");
5680 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5681 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5682 vmcs_readl(CR0_GUEST_HOST_MASK));
5683 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5684 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5685 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5686 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5687 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5689 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5690 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5691 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5692 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5694 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5695 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5696 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5697 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5698 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5699 vmcs_readl(GUEST_SYSENTER_ESP),
5700 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5701 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5702 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5703 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5704 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5705 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5706 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5707 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5708 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5709 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5710 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5711 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5712 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5713 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5714 efer, vmcs_read64(GUEST_IA32_PAT));
5715 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5716 vmcs_read64(GUEST_IA32_DEBUGCTL),
5717 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5718 if (cpu_has_load_perf_global_ctrl() &&
5719 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5720 pr_err("PerfGlobCtl = 0x%016llx\n",
5721 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5722 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5723 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5724 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5725 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5726 vmcs_read32(GUEST_ACTIVITY_STATE));
5727 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5728 pr_err("InterruptStatus = %04x\n",
5729 vmcs_read16(GUEST_INTR_STATUS));
5731 pr_err("*** Host State ***\n");
5732 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5733 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5734 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5735 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5736 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5737 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5738 vmcs_read16(HOST_TR_SELECTOR));
5739 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5740 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5741 vmcs_readl(HOST_TR_BASE));
5742 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5743 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5744 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5745 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5746 vmcs_readl(HOST_CR4));
5747 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5748 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5749 vmcs_read32(HOST_IA32_SYSENTER_CS),
5750 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5751 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5752 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5753 vmcs_read64(HOST_IA32_EFER),
5754 vmcs_read64(HOST_IA32_PAT));
5755 if (cpu_has_load_perf_global_ctrl() &&
5756 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5757 pr_err("PerfGlobCtl = 0x%016llx\n",
5758 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5760 pr_err("*** Control State ***\n");
5761 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5762 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5763 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5764 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5765 vmcs_read32(EXCEPTION_BITMAP),
5766 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5767 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5768 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5769 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5770 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5771 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5772 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5773 vmcs_read32(VM_EXIT_INTR_INFO),
5774 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5775 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5776 pr_err(" reason=%08x qualification=%016lx\n",
5777 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5778 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5779 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5780 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5781 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5782 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5783 pr_err("TSC Multiplier = 0x%016llx\n",
5784 vmcs_read64(TSC_MULTIPLIER));
5785 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5786 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5787 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5788 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5790 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5791 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5792 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5793 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5795 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5796 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5797 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5798 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5799 n = vmcs_read32(CR3_TARGET_COUNT);
5800 for (i = 0; i + 1 < n; i += 4)
5801 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5802 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5803 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5805 pr_err("CR3 target%u=%016lx\n",
5806 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5807 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5808 pr_err("PLE Gap=%08x Window=%08x\n",
5809 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5810 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5811 pr_err("Virtual processor ID = 0x%04x\n",
5812 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5816 * The guest has exited. See if we can fix it or if we need userspace
5819 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5821 struct vcpu_vmx *vmx = to_vmx(vcpu);
5822 u32 exit_reason = vmx->exit_reason;
5823 u32 vectoring_info = vmx->idt_vectoring_info;
5825 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5828 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5829 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5830 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5831 * mode as if vcpus is in root mode, the PML buffer must has been
5835 vmx_flush_pml_buffer(vcpu);
5837 /* If guest state is invalid, start emulating */
5838 if (vmx->emulation_required)
5839 return handle_invalid_guest_state(vcpu);
5841 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5842 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5844 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5846 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5847 vcpu->run->fail_entry.hardware_entry_failure_reason
5852 if (unlikely(vmx->fail)) {
5854 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5855 vcpu->run->fail_entry.hardware_entry_failure_reason
5856 = vmcs_read32(VM_INSTRUCTION_ERROR);
5862 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5863 * delivery event since it indicates guest is accessing MMIO.
5864 * The vm-exit can be triggered again after return to guest that
5865 * will cause infinite loop.
5867 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5868 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5869 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5870 exit_reason != EXIT_REASON_PML_FULL &&
5871 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5872 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5873 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5874 vcpu->run->internal.ndata = 3;
5875 vcpu->run->internal.data[0] = vectoring_info;
5876 vcpu->run->internal.data[1] = exit_reason;
5877 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5878 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5879 vcpu->run->internal.ndata++;
5880 vcpu->run->internal.data[3] =
5881 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5886 if (unlikely(!enable_vnmi &&
5887 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5888 if (vmx_interrupt_allowed(vcpu)) {
5889 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5890 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5891 vcpu->arch.nmi_pending) {
5893 * This CPU don't support us in finding the end of an
5894 * NMI-blocked window if the guest runs with IRQs
5895 * disabled. So we pull the trigger after 1 s of
5896 * futile waiting, but inform the user about this.
5898 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5899 "state on VCPU %d after 1 s timeout\n",
5900 __func__, vcpu->vcpu_id);
5901 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5905 if (exit_reason < kvm_vmx_max_exit_handlers
5906 && kvm_vmx_exit_handlers[exit_reason]) {
5907 #ifdef CONFIG_RETPOLINE
5908 if (exit_reason == EXIT_REASON_MSR_WRITE)
5909 return kvm_emulate_wrmsr(vcpu);
5910 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5911 return handle_preemption_timer(vcpu);
5912 else if (exit_reason == EXIT_REASON_PENDING_INTERRUPT)
5913 return handle_interrupt_window(vcpu);
5914 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5915 return handle_external_interrupt(vcpu);
5916 else if (exit_reason == EXIT_REASON_HLT)
5917 return kvm_emulate_halt(vcpu);
5918 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5919 return handle_ept_misconfig(vcpu);
5921 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5923 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5926 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5927 vcpu->run->internal.suberror =
5928 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5929 vcpu->run->internal.ndata = 1;
5930 vcpu->run->internal.data[0] = exit_reason;
5936 * Software based L1D cache flush which is used when microcode providing
5937 * the cache control MSR is not loaded.
5939 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5940 * flush it is required to read in 64 KiB because the replacement algorithm
5941 * is not exactly LRU. This could be sized at runtime via topology
5942 * information but as all relevant affected CPUs have 32KiB L1D cache size
5943 * there is no point in doing so.
5945 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5947 int size = PAGE_SIZE << L1D_CACHE_ORDER;
5950 * This code is only executed when the the flush mode is 'cond' or
5953 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5957 * Clear the per-vcpu flush bit, it gets set again
5958 * either from vcpu_run() or from one of the unsafe
5961 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5962 vcpu->arch.l1tf_flush_l1d = false;
5965 * Clear the per-cpu flush bit, it gets set again from
5966 * the interrupt handlers.
5968 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5969 kvm_clear_cpu_l1tf_flush_l1d();
5975 vcpu->stat.l1d_flush++;
5977 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5978 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5983 /* First ensure the pages are in the TLB */
5984 "xorl %%eax, %%eax\n"
5985 ".Lpopulate_tlb:\n\t"
5986 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5987 "addl $4096, %%eax\n\t"
5988 "cmpl %%eax, %[size]\n\t"
5989 "jne .Lpopulate_tlb\n\t"
5990 "xorl %%eax, %%eax\n\t"
5992 /* Now fill the cache */
5993 "xorl %%eax, %%eax\n"
5995 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5996 "addl $64, %%eax\n\t"
5997 "cmpl %%eax, %[size]\n\t"
5998 "jne .Lfill_cache\n\t"
6000 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6002 : "eax", "ebx", "ecx", "edx");
6005 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6007 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6010 if (is_guest_mode(vcpu) &&
6011 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6014 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6015 if (is_guest_mode(vcpu))
6016 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6018 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6021 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6023 struct vcpu_vmx *vmx = to_vmx(vcpu);
6024 u32 sec_exec_control;
6026 if (!lapic_in_kernel(vcpu))
6029 if (!flexpriority_enabled &&
6030 !cpu_has_vmx_virtualize_x2apic_mode())
6033 /* Postpone execution until vmcs01 is the current VMCS. */
6034 if (is_guest_mode(vcpu)) {
6035 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6039 sec_exec_control = secondary_exec_controls_get(vmx);
6040 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6041 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6043 switch (kvm_get_apic_mode(vcpu)) {
6044 case LAPIC_MODE_INVALID:
6045 WARN_ONCE(true, "Invalid local APIC state");
6046 case LAPIC_MODE_DISABLED:
6048 case LAPIC_MODE_XAPIC:
6049 if (flexpriority_enabled) {
6051 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6052 vmx_flush_tlb(vcpu, true);
6055 case LAPIC_MODE_X2APIC:
6056 if (cpu_has_vmx_virtualize_x2apic_mode())
6058 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6061 secondary_exec_controls_set(vmx, sec_exec_control);
6063 vmx_update_msr_bitmap(vcpu);
6066 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6068 if (!is_guest_mode(vcpu)) {
6069 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6070 vmx_flush_tlb(vcpu, true);
6074 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6082 status = vmcs_read16(GUEST_INTR_STATUS);
6084 if (max_isr != old) {
6086 status |= max_isr << 8;
6087 vmcs_write16(GUEST_INTR_STATUS, status);
6091 static void vmx_set_rvi(int vector)
6099 status = vmcs_read16(GUEST_INTR_STATUS);
6100 old = (u8)status & 0xff;
6101 if ((u8)vector != old) {
6103 status |= (u8)vector;
6104 vmcs_write16(GUEST_INTR_STATUS, status);
6108 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6111 * When running L2, updating RVI is only relevant when
6112 * vmcs12 virtual-interrupt-delivery enabled.
6113 * However, it can be enabled only when L1 also
6114 * intercepts external-interrupts and in that case
6115 * we should not update vmcs02 RVI but instead intercept
6116 * interrupt. Therefore, do nothing when running L2.
6118 if (!is_guest_mode(vcpu))
6119 vmx_set_rvi(max_irr);
6122 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6124 struct vcpu_vmx *vmx = to_vmx(vcpu);
6126 bool max_irr_updated;
6128 WARN_ON(!vcpu->arch.apicv_active);
6129 if (pi_test_on(&vmx->pi_desc)) {
6130 pi_clear_on(&vmx->pi_desc);
6132 * IOMMU can write to PID.ON, so the barrier matters even on UP.
6133 * But on x86 this is just a compiler barrier anyway.
6135 smp_mb__after_atomic();
6137 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6140 * If we are running L2 and L1 has a new pending interrupt
6141 * which can be injected, we should re-evaluate
6142 * what should be done with this new L1 interrupt.
6143 * If L1 intercepts external-interrupts, we should
6144 * exit from L2 to L1. Otherwise, interrupt should be
6145 * delivered directly to L2.
6147 if (is_guest_mode(vcpu) && max_irr_updated) {
6148 if (nested_exit_on_intr(vcpu))
6149 kvm_vcpu_exiting_guest_mode(vcpu);
6151 kvm_make_request(KVM_REQ_EVENT, vcpu);
6154 max_irr = kvm_lapic_find_highest_irr(vcpu);
6156 vmx_hwapic_irr_update(vcpu, max_irr);
6160 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6162 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6164 return pi_test_on(pi_desc) ||
6165 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6168 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6170 if (!kvm_vcpu_apicv_active(vcpu))
6173 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6174 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6175 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6176 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6179 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6181 struct vcpu_vmx *vmx = to_vmx(vcpu);
6183 pi_clear_on(&vmx->pi_desc);
6184 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6187 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6189 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6191 /* if exit due to PF check for async PF */
6192 if (is_page_fault(vmx->exit_intr_info))
6193 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6195 /* Handle machine checks before interrupts are enabled */
6196 if (is_machine_check(vmx->exit_intr_info))
6197 kvm_machine_check();
6199 /* We need to handle NMIs before interrupts are enabled */
6200 if (is_nmi(vmx->exit_intr_info)) {
6201 kvm_before_interrupt(&vmx->vcpu);
6203 kvm_after_interrupt(&vmx->vcpu);
6207 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6209 unsigned int vector;
6210 unsigned long entry;
6211 #ifdef CONFIG_X86_64
6217 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6218 if (WARN_ONCE(!is_external_intr(intr_info),
6219 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6222 vector = intr_info & INTR_INFO_VECTOR_MASK;
6223 desc = (gate_desc *)host_idt_base + vector;
6224 entry = gate_offset(desc);
6226 kvm_before_interrupt(vcpu);
6229 #ifdef CONFIG_X86_64
6230 "mov %%" _ASM_SP ", %[sp]\n\t"
6231 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6236 __ASM_SIZE(push) " $%c[cs]\n\t"
6239 #ifdef CONFIG_X86_64
6244 THUNK_TARGET(entry),
6245 [ss]"i"(__KERNEL_DS),
6246 [cs]"i"(__KERNEL_CS)
6249 kvm_after_interrupt(vcpu);
6251 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6253 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6255 struct vcpu_vmx *vmx = to_vmx(vcpu);
6257 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6258 handle_external_interrupt_irqoff(vcpu);
6259 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6260 handle_exception_nmi_irqoff(vmx);
6263 static bool vmx_has_emulated_msr(int index)
6266 case MSR_IA32_SMBASE:
6268 * We cannot do SMM unless we can run the guest in big
6271 return enable_unrestricted_guest || emulate_invalid_guest_state;
6272 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6274 case MSR_AMD64_VIRT_SPEC_CTRL:
6275 /* This is AMD only. */
6282 static bool vmx_pt_supported(void)
6284 return pt_mode == PT_MODE_HOST_GUEST;
6287 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6292 bool idtv_info_valid;
6294 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6297 if (vmx->loaded_vmcs->nmi_known_unmasked)
6300 * Can't use vmx->exit_intr_info since we're not sure what
6301 * the exit reason is.
6303 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6304 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6305 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6307 * SDM 3: 27.7.1.2 (September 2008)
6308 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6309 * a guest IRET fault.
6310 * SDM 3: 23.2.2 (September 2008)
6311 * Bit 12 is undefined in any of the following cases:
6312 * If the VM exit sets the valid bit in the IDT-vectoring
6313 * information field.
6314 * If the VM exit is due to a double fault.
6316 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6317 vector != DF_VECTOR && !idtv_info_valid)
6318 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6319 GUEST_INTR_STATE_NMI);
6321 vmx->loaded_vmcs->nmi_known_unmasked =
6322 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6323 & GUEST_INTR_STATE_NMI);
6324 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6325 vmx->loaded_vmcs->vnmi_blocked_time +=
6326 ktime_to_ns(ktime_sub(ktime_get(),
6327 vmx->loaded_vmcs->entry_time));
6330 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6331 u32 idt_vectoring_info,
6332 int instr_len_field,
6333 int error_code_field)
6337 bool idtv_info_valid;
6339 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6341 vcpu->arch.nmi_injected = false;
6342 kvm_clear_exception_queue(vcpu);
6343 kvm_clear_interrupt_queue(vcpu);
6345 if (!idtv_info_valid)
6348 kvm_make_request(KVM_REQ_EVENT, vcpu);
6350 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6351 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6354 case INTR_TYPE_NMI_INTR:
6355 vcpu->arch.nmi_injected = true;
6357 * SDM 3: 27.7.1.2 (September 2008)
6358 * Clear bit "block by NMI" before VM entry if a NMI
6361 vmx_set_nmi_mask(vcpu, false);
6363 case INTR_TYPE_SOFT_EXCEPTION:
6364 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6366 case INTR_TYPE_HARD_EXCEPTION:
6367 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6368 u32 err = vmcs_read32(error_code_field);
6369 kvm_requeue_exception_e(vcpu, vector, err);
6371 kvm_requeue_exception(vcpu, vector);
6373 case INTR_TYPE_SOFT_INTR:
6374 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6376 case INTR_TYPE_EXT_INTR:
6377 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6384 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6386 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6387 VM_EXIT_INSTRUCTION_LEN,
6388 IDT_VECTORING_ERROR_CODE);
6391 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6393 __vmx_complete_interrupts(vcpu,
6394 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6395 VM_ENTRY_INSTRUCTION_LEN,
6396 VM_ENTRY_EXCEPTION_ERROR_CODE);
6398 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6401 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6404 struct perf_guest_switch_msr *msrs;
6406 msrs = perf_guest_get_msrs(&nr_msrs);
6411 for (i = 0; i < nr_msrs; i++)
6412 if (msrs[i].host == msrs[i].guest)
6413 clear_atomic_switch_msr(vmx, msrs[i].msr);
6415 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6416 msrs[i].host, false);
6419 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6421 u32 host_umwait_control;
6423 if (!vmx_has_waitpkg(vmx))
6426 host_umwait_control = get_umwait_control_msr();
6428 if (vmx->msr_ia32_umwait_control != host_umwait_control)
6429 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6430 vmx->msr_ia32_umwait_control,
6431 host_umwait_control, false);
6433 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6436 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6438 struct vcpu_vmx *vmx = to_vmx(vcpu);
6442 if (vmx->req_immediate_exit) {
6443 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6444 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6445 } else if (vmx->hv_deadline_tsc != -1) {
6447 if (vmx->hv_deadline_tsc > tscl)
6448 /* set_hv_timer ensures the delta fits in 32-bits */
6449 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6450 cpu_preemption_timer_multi);
6454 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6455 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6456 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6457 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6458 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6462 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6464 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6465 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6466 vmcs_writel(HOST_RSP, host_rsp);
6470 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6472 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6474 struct vcpu_vmx *vmx = to_vmx(vcpu);
6475 unsigned long cr3, cr4;
6477 /* Record the guest's net vcpu time for enforced NMI injections. */
6478 if (unlikely(!enable_vnmi &&
6479 vmx->loaded_vmcs->soft_vnmi_blocked))
6480 vmx->loaded_vmcs->entry_time = ktime_get();
6482 /* Don't enter VMX if guest state is invalid, let the exit handler
6483 start emulation until we arrive back to a valid state */
6484 if (vmx->emulation_required)
6487 if (vmx->ple_window_dirty) {
6488 vmx->ple_window_dirty = false;
6489 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6492 if (vmx->nested.need_vmcs12_to_shadow_sync)
6493 nested_sync_vmcs12_to_shadow(vcpu);
6495 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6496 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6497 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6498 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6500 cr3 = __get_current_cr3_fast();
6501 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6502 vmcs_writel(HOST_CR3, cr3);
6503 vmx->loaded_vmcs->host_state.cr3 = cr3;
6506 cr4 = cr4_read_shadow();
6507 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6508 vmcs_writel(HOST_CR4, cr4);
6509 vmx->loaded_vmcs->host_state.cr4 = cr4;
6512 /* When single-stepping over STI and MOV SS, we must clear the
6513 * corresponding interruptibility bits in the guest state. Otherwise
6514 * vmentry fails as it then expects bit 14 (BS) in pending debug
6515 * exceptions being set, but that's not correct for the guest debugging
6517 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6518 vmx_set_interrupt_shadow(vcpu, 0);
6520 kvm_load_guest_xsave_state(vcpu);
6522 if (static_cpu_has(X86_FEATURE_PKU) &&
6523 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6524 vcpu->arch.pkru != vmx->host_pkru)
6525 __write_pkru(vcpu->arch.pkru);
6527 pt_guest_enter(vmx);
6529 atomic_switch_perf_msrs(vmx);
6530 atomic_switch_umwait_control_msr(vmx);
6532 if (enable_preemption_timer)
6533 vmx_update_hv_timer(vcpu);
6535 if (lapic_in_kernel(vcpu) &&
6536 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6537 kvm_wait_lapic_expire(vcpu);
6540 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6541 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6542 * is no need to worry about the conditional branch over the wrmsr
6543 * being speculatively taken.
6545 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6547 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6548 if (static_branch_unlikely(&vmx_l1d_should_flush))
6549 vmx_l1d_flush(vcpu);
6550 else if (static_branch_unlikely(&mds_user_clear))
6551 mds_clear_cpu_buffers();
6553 if (vcpu->arch.cr2 != read_cr2())
6554 write_cr2(vcpu->arch.cr2);
6556 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6557 vmx->loaded_vmcs->launched);
6559 vcpu->arch.cr2 = read_cr2();
6562 * We do not use IBRS in the kernel. If this vCPU has used the
6563 * SPEC_CTRL MSR it may have left it on; save the value and
6564 * turn it off. This is much more efficient than blindly adding
6565 * it to the atomic save/restore list. Especially as the former
6566 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6568 * For non-nested case:
6569 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6573 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6576 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6577 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6579 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6581 /* All fields are clean at this point */
6582 if (static_branch_unlikely(&enable_evmcs))
6583 current_evmcs->hv_clean_fields |=
6584 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6586 if (static_branch_unlikely(&enable_evmcs))
6587 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6589 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6590 if (vmx->host_debugctlmsr)
6591 update_debugctlmsr(vmx->host_debugctlmsr);
6593 #ifndef CONFIG_X86_64
6595 * The sysexit path does not restore ds/es, so we must set them to
6596 * a reasonable value ourselves.
6598 * We can't defer this to vmx_prepare_switch_to_host() since that
6599 * function may be executed in interrupt context, which saves and
6600 * restore segments around it, nullifying its effect.
6602 loadsegment(ds, __USER_DS);
6603 loadsegment(es, __USER_DS);
6606 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6607 | (1 << VCPU_EXREG_RFLAGS)
6608 | (1 << VCPU_EXREG_PDPTR)
6609 | (1 << VCPU_EXREG_SEGMENTS)
6610 | (1 << VCPU_EXREG_CR3));
6611 vcpu->arch.regs_dirty = 0;
6616 * eager fpu is enabled if PKEY is supported and CR4 is switched
6617 * back on host, so it is safe to read guest PKRU from current
6620 if (static_cpu_has(X86_FEATURE_PKU) &&
6621 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6622 vcpu->arch.pkru = rdpkru();
6623 if (vcpu->arch.pkru != vmx->host_pkru)
6624 __write_pkru(vmx->host_pkru);
6627 kvm_load_host_xsave_state(vcpu);
6629 vmx->nested.nested_run_pending = 0;
6630 vmx->idt_vectoring_info = 0;
6632 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6633 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6634 kvm_machine_check();
6636 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6639 vmx->loaded_vmcs->launched = 1;
6640 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6642 vmx_recover_nmi_blocking(vmx);
6643 vmx_complete_interrupts(vmx);
6646 static struct kvm *vmx_vm_alloc(void)
6648 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6649 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6651 return &kvm_vmx->kvm;
6654 static void vmx_vm_free(struct kvm *kvm)
6656 kfree(kvm->arch.hyperv.hv_pa_pg);
6657 vfree(to_kvm_vmx(kvm));
6660 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6662 struct vcpu_vmx *vmx = to_vmx(vcpu);
6665 vmx_destroy_pml_buffer(vmx);
6666 free_vpid(vmx->vpid);
6667 nested_vmx_free_vcpu(vcpu);
6668 free_loaded_vmcs(vmx->loaded_vmcs);
6669 kfree(vmx->guest_msrs);
6670 kvm_vcpu_uninit(vcpu);
6671 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6672 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6673 kmem_cache_free(kvm_vcpu_cache, vmx);
6676 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6679 struct vcpu_vmx *vmx;
6680 unsigned long *msr_bitmap;
6683 BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
6684 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
6686 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
6688 return ERR_PTR(-ENOMEM);
6690 vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6691 GFP_KERNEL_ACCOUNT);
6692 if (!vmx->vcpu.arch.user_fpu) {
6693 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6695 goto free_partial_vcpu;
6698 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6699 GFP_KERNEL_ACCOUNT);
6700 if (!vmx->vcpu.arch.guest_fpu) {
6701 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6706 vmx->vpid = allocate_vpid();
6708 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6715 * If PML is turned on, failure on enabling PML just results in failure
6716 * of creating the vcpu, therefore we can simplify PML logic (by
6717 * avoiding dealing with cases, such as enabling PML partially on vcpus
6718 * for the guest, etc.
6721 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6726 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
6727 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6730 if (!vmx->guest_msrs)
6733 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6734 u32 index = vmx_msr_index[i];
6735 u32 data_low, data_high;
6738 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6740 if (wrmsr_safe(index, data_low, data_high) < 0)
6743 vmx->guest_msrs[j].index = i;
6744 vmx->guest_msrs[j].data = 0;
6746 case MSR_IA32_TSX_CTRL:
6748 * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6749 * let's avoid changing CPUID bits under the host
6752 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6755 vmx->guest_msrs[j].mask = -1ull;
6761 err = alloc_loaded_vmcs(&vmx->vmcs01);
6765 msr_bitmap = vmx->vmcs01.msr_bitmap;
6766 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6767 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6768 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6769 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6770 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6771 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6772 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6773 if (kvm_cstate_in_guest(kvm)) {
6774 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6775 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6776 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6777 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6779 vmx->msr_bitmap_mode = 0;
6781 vmx->loaded_vmcs = &vmx->vmcs01;
6783 vmx_vcpu_load(&vmx->vcpu, cpu);
6784 vmx->vcpu.cpu = cpu;
6786 vmx_vcpu_put(&vmx->vcpu);
6788 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6789 err = alloc_apic_access_page(kvm);
6794 if (enable_ept && !enable_unrestricted_guest) {
6795 err = init_rmode_identity_map(kvm);
6801 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6803 kvm_vcpu_apicv_active(&vmx->vcpu));
6805 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6807 vmx->nested.posted_intr_nv = -1;
6808 vmx->nested.current_vmptr = -1ull;
6810 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
6813 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6814 * or POSTED_INTR_WAKEUP_VECTOR.
6816 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6817 vmx->pi_desc.sn = 1;
6819 vmx->ept_pointer = INVALID_PAGE;
6824 free_loaded_vmcs(vmx->loaded_vmcs);
6826 kfree(vmx->guest_msrs);
6828 vmx_destroy_pml_buffer(vmx);
6830 kvm_vcpu_uninit(&vmx->vcpu);
6832 free_vpid(vmx->vpid);
6833 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6835 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6837 kmem_cache_free(kvm_vcpu_cache, vmx);
6838 return ERR_PTR(err);
6841 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6842 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6844 static int vmx_vm_init(struct kvm *kvm)
6846 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6849 kvm->arch.pause_in_guest = true;
6851 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6852 switch (l1tf_mitigation) {
6853 case L1TF_MITIGATION_OFF:
6854 case L1TF_MITIGATION_FLUSH_NOWARN:
6855 /* 'I explicitly don't care' is set */
6857 case L1TF_MITIGATION_FLUSH:
6858 case L1TF_MITIGATION_FLUSH_NOSMT:
6859 case L1TF_MITIGATION_FULL:
6861 * Warn upon starting the first VM in a potentially
6862 * insecure environment.
6864 if (sched_smt_active())
6865 pr_warn_once(L1TF_MSG_SMT);
6866 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6867 pr_warn_once(L1TF_MSG_L1D);
6869 case L1TF_MITIGATION_FULL_FORCE:
6870 /* Flush is enforced */
6877 static int __init vmx_check_processor_compat(void)
6879 struct vmcs_config vmcs_conf;
6880 struct vmx_capability vmx_cap;
6882 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6885 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6887 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6888 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6889 smp_processor_id());
6895 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6900 /* For VT-d and EPT combination
6901 * 1. MMIO: always map as UC
6903 * a. VT-d without snooping control feature: can't guarantee the
6904 * result, try to trust guest.
6905 * b. VT-d with snooping control feature: snooping control feature of
6906 * VT-d engine can guarantee the cache correctness. Just set it
6907 * to WB to keep consistent with host. So the same as item 3.
6908 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6909 * consistent with host MTRR
6912 cache = MTRR_TYPE_UNCACHABLE;
6916 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6917 ipat = VMX_EPT_IPAT_BIT;
6918 cache = MTRR_TYPE_WRBACK;
6922 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6923 ipat = VMX_EPT_IPAT_BIT;
6924 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6925 cache = MTRR_TYPE_WRBACK;
6927 cache = MTRR_TYPE_UNCACHABLE;
6931 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6934 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6937 static int vmx_get_lpage_level(void)
6939 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6940 return PT_DIRECTORY_LEVEL;
6942 /* For shadow and EPT supported 1GB page */
6943 return PT_PDPE_LEVEL;
6946 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6949 * These bits in the secondary execution controls field
6950 * are dynamic, the others are mostly based on the hypervisor
6951 * architecture and the guest's CPUID. Do not touch the
6955 SECONDARY_EXEC_SHADOW_VMCS |
6956 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6957 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6958 SECONDARY_EXEC_DESC;
6960 u32 new_ctl = vmx->secondary_exec_control;
6961 u32 cur_ctl = secondary_exec_controls_get(vmx);
6963 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6967 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6968 * (indicating "allowed-1") if they are supported in the guest's CPUID.
6970 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6972 struct vcpu_vmx *vmx = to_vmx(vcpu);
6973 struct kvm_cpuid_entry2 *entry;
6975 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6976 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6978 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6979 if (entry && (entry->_reg & (_cpuid_mask))) \
6980 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6983 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6984 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6985 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6986 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6987 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6988 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6989 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6990 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6991 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6992 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6993 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6994 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6995 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6996 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6997 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
6999 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7000 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
7001 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
7002 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
7003 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
7004 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
7005 cr4_fixed1_update(X86_CR4_LA57, ecx, bit(X86_FEATURE_LA57));
7007 #undef cr4_fixed1_update
7010 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7012 struct vcpu_vmx *vmx = to_vmx(vcpu);
7014 if (kvm_mpx_supported()) {
7015 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7018 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7019 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7021 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7022 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7027 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7029 struct vcpu_vmx *vmx = to_vmx(vcpu);
7030 struct kvm_cpuid_entry2 *best = NULL;
7033 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7034 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7037 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7038 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7039 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7040 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7043 /* Get the number of configurable Address Ranges for filtering */
7044 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7045 PT_CAP_num_address_ranges);
7047 /* Initialize and clear the no dependency bits */
7048 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7049 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7052 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7053 * will inject an #GP
7055 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7056 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7059 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7060 * PSBFreq can be set
7062 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7063 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7064 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7067 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7068 * MTCFreq can be set
7070 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7071 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7072 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7074 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7075 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7076 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7079 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7080 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7081 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7083 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7084 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7085 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7087 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7088 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7089 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7091 /* unmask address range configure area */
7092 for (i = 0; i < vmx->pt_desc.addr_range; i++)
7093 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7096 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7098 struct vcpu_vmx *vmx = to_vmx(vcpu);
7100 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7101 vcpu->arch.xsaves_enabled = false;
7103 if (cpu_has_secondary_exec_ctrls()) {
7104 vmx_compute_secondary_exec_control(vmx);
7105 vmcs_set_secondary_exec_control(vmx);
7108 if (nested_vmx_allowed(vcpu))
7109 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7110 FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX |
7111 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7113 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7114 ~(FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX |
7115 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX);
7117 if (nested_vmx_allowed(vcpu)) {
7118 nested_vmx_cr_fixed1_bits_update(vcpu);
7119 nested_vmx_entry_exit_ctls_update(vcpu);
7122 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7123 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7124 update_intel_pt_cfg(vcpu);
7126 if (boot_cpu_has(X86_FEATURE_RTM)) {
7127 struct shared_msr_entry *msr;
7128 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7130 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7131 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7136 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7138 if (func == 1 && nested)
7139 entry->ecx |= bit(X86_FEATURE_VMX);
7142 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7144 to_vmx(vcpu)->req_immediate_exit = true;
7147 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7148 struct x86_instruction_info *info,
7149 enum x86_intercept_stage stage)
7151 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7152 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7155 * RDPID causes #UD if disabled through secondary execution controls.
7156 * Because it is marked as EmulateOnUD, we need to intercept it here.
7158 if (info->intercept == x86_intercept_rdtscp &&
7159 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7160 ctxt->exception.vector = UD_VECTOR;
7161 ctxt->exception.error_code_valid = false;
7162 return X86EMUL_PROPAGATE_FAULT;
7165 /* TODO: check more intercepts... */
7166 return X86EMUL_CONTINUE;
7169 #ifdef CONFIG_X86_64
7170 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7171 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7172 u64 divisor, u64 *result)
7174 u64 low = a << shift, high = a >> (64 - shift);
7176 /* To avoid the overflow on divq */
7177 if (high >= divisor)
7180 /* Low hold the result, high hold rem which is discarded */
7181 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7182 "rm" (divisor), "0" (low), "1" (high));
7188 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7191 struct vcpu_vmx *vmx;
7192 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7193 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7195 if (kvm_mwait_in_guest(vcpu->kvm) ||
7196 kvm_can_post_timer_interrupt(vcpu))
7201 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7202 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7203 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7204 ktimer->timer_advance_ns);
7206 if (delta_tsc > lapic_timer_advance_cycles)
7207 delta_tsc -= lapic_timer_advance_cycles;
7211 /* Convert to host delta tsc if tsc scaling is enabled */
7212 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7213 delta_tsc && u64_shl_div_u64(delta_tsc,
7214 kvm_tsc_scaling_ratio_frac_bits,
7215 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7219 * If the delta tsc can't fit in the 32 bit after the multi shift,
7220 * we can't use the preemption timer.
7221 * It's possible that it fits on later vmentries, but checking
7222 * on every vmentry is costly so we just use an hrtimer.
7224 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7227 vmx->hv_deadline_tsc = tscl + delta_tsc;
7228 *expired = !delta_tsc;
7232 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7234 to_vmx(vcpu)->hv_deadline_tsc = -1;
7238 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7240 if (!kvm_pause_in_guest(vcpu->kvm))
7241 shrink_ple_window(vcpu);
7244 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7245 struct kvm_memory_slot *slot)
7247 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7248 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7251 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7252 struct kvm_memory_slot *slot)
7254 kvm_mmu_slot_set_dirty(kvm, slot);
7257 static void vmx_flush_log_dirty(struct kvm *kvm)
7259 kvm_flush_pml_buffers(kvm);
7262 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7264 struct vmcs12 *vmcs12;
7265 struct vcpu_vmx *vmx = to_vmx(vcpu);
7268 if (is_guest_mode(vcpu)) {
7269 WARN_ON_ONCE(vmx->nested.pml_full);
7272 * Check if PML is enabled for the nested guest.
7273 * Whether eptp bit 6 is set is already checked
7274 * as part of A/D emulation.
7276 vmcs12 = get_vmcs12(vcpu);
7277 if (!nested_cpu_has_pml(vmcs12))
7280 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7281 vmx->nested.pml_full = true;
7285 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7286 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7288 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7289 offset_in_page(dst), sizeof(gpa)))
7292 vmcs12->guest_pml_index--;
7298 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7299 struct kvm_memory_slot *memslot,
7300 gfn_t offset, unsigned long mask)
7302 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7305 static void __pi_post_block(struct kvm_vcpu *vcpu)
7307 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7308 struct pi_desc old, new;
7312 old.control = new.control = pi_desc->control;
7313 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7314 "Wakeup handler not enabled while the VCPU is blocked\n");
7316 dest = cpu_physical_id(vcpu->cpu);
7318 if (x2apic_enabled())
7321 new.ndst = (dest << 8) & 0xFF00;
7323 /* set 'NV' to 'notification vector' */
7324 new.nv = POSTED_INTR_VECTOR;
7325 } while (cmpxchg64(&pi_desc->control, old.control,
7326 new.control) != old.control);
7328 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7329 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7330 list_del(&vcpu->blocked_vcpu_list);
7331 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7332 vcpu->pre_pcpu = -1;
7337 * This routine does the following things for vCPU which is going
7338 * to be blocked if VT-d PI is enabled.
7339 * - Store the vCPU to the wakeup list, so when interrupts happen
7340 * we can find the right vCPU to wake up.
7341 * - Change the Posted-interrupt descriptor as below:
7342 * 'NDST' <-- vcpu->pre_pcpu
7343 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7344 * - If 'ON' is set during this process, which means at least one
7345 * interrupt is posted for this vCPU, we cannot block it, in
7346 * this case, return 1, otherwise, return 0.
7349 static int pi_pre_block(struct kvm_vcpu *vcpu)
7352 struct pi_desc old, new;
7353 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7355 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7356 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7357 !kvm_vcpu_apicv_active(vcpu))
7360 WARN_ON(irqs_disabled());
7361 local_irq_disable();
7362 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7363 vcpu->pre_pcpu = vcpu->cpu;
7364 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7365 list_add_tail(&vcpu->blocked_vcpu_list,
7366 &per_cpu(blocked_vcpu_on_cpu,
7368 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7372 old.control = new.control = pi_desc->control;
7374 WARN((pi_desc->sn == 1),
7375 "Warning: SN field of posted-interrupts "
7376 "is set before blocking\n");
7379 * Since vCPU can be preempted during this process,
7380 * vcpu->cpu could be different with pre_pcpu, we
7381 * need to set pre_pcpu as the destination of wakeup
7382 * notification event, then we can find the right vCPU
7383 * to wakeup in wakeup handler if interrupts happen
7384 * when the vCPU is in blocked state.
7386 dest = cpu_physical_id(vcpu->pre_pcpu);
7388 if (x2apic_enabled())
7391 new.ndst = (dest << 8) & 0xFF00;
7393 /* set 'NV' to 'wakeup vector' */
7394 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7395 } while (cmpxchg64(&pi_desc->control, old.control,
7396 new.control) != old.control);
7398 /* We should not block the vCPU if an interrupt is posted for it. */
7399 if (pi_test_on(pi_desc) == 1)
7400 __pi_post_block(vcpu);
7403 return (vcpu->pre_pcpu == -1);
7406 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7408 if (pi_pre_block(vcpu))
7411 if (kvm_lapic_hv_timer_in_use(vcpu))
7412 kvm_lapic_switch_to_sw_timer(vcpu);
7417 static void pi_post_block(struct kvm_vcpu *vcpu)
7419 if (vcpu->pre_pcpu == -1)
7422 WARN_ON(irqs_disabled());
7423 local_irq_disable();
7424 __pi_post_block(vcpu);
7428 static void vmx_post_block(struct kvm_vcpu *vcpu)
7430 if (kvm_x86_ops->set_hv_timer)
7431 kvm_lapic_switch_to_hv_timer(vcpu);
7433 pi_post_block(vcpu);
7437 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7440 * @host_irq: host irq of the interrupt
7441 * @guest_irq: gsi of the interrupt
7442 * @set: set or unset PI
7443 * returns 0 on success, < 0 on failure
7445 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7446 uint32_t guest_irq, bool set)
7448 struct kvm_kernel_irq_routing_entry *e;
7449 struct kvm_irq_routing_table *irq_rt;
7450 struct kvm_lapic_irq irq;
7451 struct kvm_vcpu *vcpu;
7452 struct vcpu_data vcpu_info;
7455 if (!kvm_arch_has_assigned_device(kvm) ||
7456 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7457 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7460 idx = srcu_read_lock(&kvm->irq_srcu);
7461 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7462 if (guest_irq >= irq_rt->nr_rt_entries ||
7463 hlist_empty(&irq_rt->map[guest_irq])) {
7464 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7465 guest_irq, irq_rt->nr_rt_entries);
7469 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7470 if (e->type != KVM_IRQ_ROUTING_MSI)
7473 * VT-d PI cannot support posting multicast/broadcast
7474 * interrupts to a vCPU, we still use interrupt remapping
7475 * for these kind of interrupts.
7477 * For lowest-priority interrupts, we only support
7478 * those with single CPU as the destination, e.g. user
7479 * configures the interrupts via /proc/irq or uses
7480 * irqbalance to make the interrupts single-CPU.
7482 * We will support full lowest-priority interrupt later.
7484 * In addition, we can only inject generic interrupts using
7485 * the PI mechanism, refuse to route others through it.
7488 kvm_set_msi_irq(kvm, e, &irq);
7489 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7490 !kvm_irq_is_postable(&irq)) {
7492 * Make sure the IRTE is in remapped mode if
7493 * we don't handle it in posted mode.
7495 ret = irq_set_vcpu_affinity(host_irq, NULL);
7498 "failed to back to remapped mode, irq: %u\n",
7506 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7507 vcpu_info.vector = irq.vector;
7509 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7510 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7513 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7515 ret = irq_set_vcpu_affinity(host_irq, NULL);
7518 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7526 srcu_read_unlock(&kvm->irq_srcu, idx);
7530 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7532 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7533 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7534 FEATURE_CONTROL_LMCE;
7536 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7537 ~FEATURE_CONTROL_LMCE;
7540 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7542 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7543 if (to_vmx(vcpu)->nested.nested_run_pending)
7548 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7550 struct vcpu_vmx *vmx = to_vmx(vcpu);
7552 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7553 if (vmx->nested.smm.guest_mode)
7554 nested_vmx_vmexit(vcpu, -1, 0, 0);
7556 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7557 vmx->nested.vmxon = false;
7558 vmx_clear_hlt(vcpu);
7562 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7564 struct vcpu_vmx *vmx = to_vmx(vcpu);
7567 if (vmx->nested.smm.vmxon) {
7568 vmx->nested.vmxon = true;
7569 vmx->nested.smm.vmxon = false;
7572 if (vmx->nested.smm.guest_mode) {
7573 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7577 vmx->nested.smm.guest_mode = false;
7582 static int enable_smi_window(struct kvm_vcpu *vcpu)
7587 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7592 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7594 return to_vmx(vcpu)->nested.vmxon;
7597 static __init int hardware_setup(void)
7599 unsigned long host_bndcfgs;
7603 rdmsrl_safe(MSR_EFER, &host_efer);
7606 host_idt_base = dt.address;
7608 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7609 kvm_define_shared_msr(i, vmx_msr_index[i]);
7611 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7614 if (boot_cpu_has(X86_FEATURE_NX))
7615 kvm_enable_efer_bits(EFER_NX);
7617 if (boot_cpu_has(X86_FEATURE_MPX)) {
7618 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7619 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7622 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7623 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7626 if (!cpu_has_vmx_ept() ||
7627 !cpu_has_vmx_ept_4levels() ||
7628 !cpu_has_vmx_ept_mt_wb() ||
7629 !cpu_has_vmx_invept_global())
7632 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7633 enable_ept_ad_bits = 0;
7635 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7636 enable_unrestricted_guest = 0;
7638 if (!cpu_has_vmx_flexpriority())
7639 flexpriority_enabled = 0;
7641 if (!cpu_has_virtual_nmis())
7645 * set_apic_access_page_addr() is used to reload apic access
7646 * page upon invalidation. No need to do anything if not
7647 * using the APIC_ACCESS_ADDR VMCS field.
7649 if (!flexpriority_enabled)
7650 kvm_x86_ops->set_apic_access_page_addr = NULL;
7652 if (!cpu_has_vmx_tpr_shadow())
7653 kvm_x86_ops->update_cr8_intercept = NULL;
7655 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7656 kvm_disable_largepages();
7658 #if IS_ENABLED(CONFIG_HYPERV)
7659 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7661 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7662 kvm_x86_ops->tlb_remote_flush_with_range =
7663 hv_remote_flush_tlb_with_range;
7667 if (!cpu_has_vmx_ple()) {
7670 ple_window_grow = 0;
7672 ple_window_shrink = 0;
7675 if (!cpu_has_vmx_apicv()) {
7677 kvm_x86_ops->sync_pir_to_irr = NULL;
7680 if (cpu_has_vmx_tsc_scaling()) {
7681 kvm_has_tsc_control = true;
7682 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7683 kvm_tsc_scaling_ratio_frac_bits = 48;
7686 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7694 * Only enable PML when hardware supports PML feature, and both EPT
7695 * and EPT A/D bit features are enabled -- PML depends on them to work.
7697 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7701 kvm_x86_ops->slot_enable_log_dirty = NULL;
7702 kvm_x86_ops->slot_disable_log_dirty = NULL;
7703 kvm_x86_ops->flush_log_dirty = NULL;
7704 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7707 if (!cpu_has_vmx_preemption_timer())
7708 enable_preemption_timer = false;
7710 if (enable_preemption_timer) {
7711 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7714 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7715 cpu_preemption_timer_multi =
7716 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7719 use_timer_freq = (u64)tsc_khz * 1000;
7720 use_timer_freq >>= cpu_preemption_timer_multi;
7723 * KVM "disables" the preemption timer by setting it to its max
7724 * value. Don't use the timer if it might cause spurious exits
7725 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7727 if (use_timer_freq > 0xffffffffu / 10)
7728 enable_preemption_timer = false;
7731 if (!enable_preemption_timer) {
7732 kvm_x86_ops->set_hv_timer = NULL;
7733 kvm_x86_ops->cancel_hv_timer = NULL;
7734 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7737 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7739 kvm_mce_cap_supported |= MCG_LMCE_P;
7741 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7743 if (!enable_ept || !cpu_has_vmx_intel_pt())
7744 pt_mode = PT_MODE_SYSTEM;
7747 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7748 vmx_capability.ept, enable_apicv);
7750 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7755 r = alloc_kvm_area();
7757 nested_vmx_hardware_unsetup();
7761 static __exit void hardware_unsetup(void)
7764 nested_vmx_hardware_unsetup();
7769 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7770 .cpu_has_kvm_support = cpu_has_kvm_support,
7771 .disabled_by_bios = vmx_disabled_by_bios,
7772 .hardware_setup = hardware_setup,
7773 .hardware_unsetup = hardware_unsetup,
7774 .check_processor_compatibility = vmx_check_processor_compat,
7775 .hardware_enable = hardware_enable,
7776 .hardware_disable = hardware_disable,
7777 .cpu_has_accelerated_tpr = report_flexpriority,
7778 .has_emulated_msr = vmx_has_emulated_msr,
7780 .vm_init = vmx_vm_init,
7781 .vm_alloc = vmx_vm_alloc,
7782 .vm_free = vmx_vm_free,
7784 .vcpu_create = vmx_create_vcpu,
7785 .vcpu_free = vmx_free_vcpu,
7786 .vcpu_reset = vmx_vcpu_reset,
7788 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7789 .vcpu_load = vmx_vcpu_load,
7790 .vcpu_put = vmx_vcpu_put,
7792 .update_bp_intercept = update_exception_bitmap,
7793 .get_msr_feature = vmx_get_msr_feature,
7794 .get_msr = vmx_get_msr,
7795 .set_msr = vmx_set_msr,
7796 .get_segment_base = vmx_get_segment_base,
7797 .get_segment = vmx_get_segment,
7798 .set_segment = vmx_set_segment,
7799 .get_cpl = vmx_get_cpl,
7800 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7801 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7802 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7803 .set_cr0 = vmx_set_cr0,
7804 .set_cr3 = vmx_set_cr3,
7805 .set_cr4 = vmx_set_cr4,
7806 .set_efer = vmx_set_efer,
7807 .get_idt = vmx_get_idt,
7808 .set_idt = vmx_set_idt,
7809 .get_gdt = vmx_get_gdt,
7810 .set_gdt = vmx_set_gdt,
7811 .get_dr6 = vmx_get_dr6,
7812 .set_dr6 = vmx_set_dr6,
7813 .set_dr7 = vmx_set_dr7,
7814 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7815 .cache_reg = vmx_cache_reg,
7816 .get_rflags = vmx_get_rflags,
7817 .set_rflags = vmx_set_rflags,
7819 .tlb_flush = vmx_flush_tlb,
7820 .tlb_flush_gva = vmx_flush_tlb_gva,
7822 .run = vmx_vcpu_run,
7823 .handle_exit = vmx_handle_exit,
7824 .skip_emulated_instruction = skip_emulated_instruction,
7825 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7826 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7827 .patch_hypercall = vmx_patch_hypercall,
7828 .set_irq = vmx_inject_irq,
7829 .set_nmi = vmx_inject_nmi,
7830 .queue_exception = vmx_queue_exception,
7831 .cancel_injection = vmx_cancel_injection,
7832 .interrupt_allowed = vmx_interrupt_allowed,
7833 .nmi_allowed = vmx_nmi_allowed,
7834 .get_nmi_mask = vmx_get_nmi_mask,
7835 .set_nmi_mask = vmx_set_nmi_mask,
7836 .enable_nmi_window = enable_nmi_window,
7837 .enable_irq_window = enable_irq_window,
7838 .update_cr8_intercept = update_cr8_intercept,
7839 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7840 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7841 .get_enable_apicv = vmx_get_enable_apicv,
7842 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7843 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7844 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7845 .hwapic_irr_update = vmx_hwapic_irr_update,
7846 .hwapic_isr_update = vmx_hwapic_isr_update,
7847 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7848 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7849 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7850 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7852 .set_tss_addr = vmx_set_tss_addr,
7853 .set_identity_map_addr = vmx_set_identity_map_addr,
7854 .get_tdp_level = get_ept_level,
7855 .get_mt_mask = vmx_get_mt_mask,
7857 .get_exit_info = vmx_get_exit_info,
7859 .get_lpage_level = vmx_get_lpage_level,
7861 .cpuid_update = vmx_cpuid_update,
7863 .rdtscp_supported = vmx_rdtscp_supported,
7864 .invpcid_supported = vmx_invpcid_supported,
7866 .set_supported_cpuid = vmx_set_supported_cpuid,
7868 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7870 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7871 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7873 .set_tdp_cr3 = vmx_set_cr3,
7875 .check_intercept = vmx_check_intercept,
7876 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7877 .mpx_supported = vmx_mpx_supported,
7878 .xsaves_supported = vmx_xsaves_supported,
7879 .umip_emulated = vmx_umip_emulated,
7880 .pt_supported = vmx_pt_supported,
7882 .request_immediate_exit = vmx_request_immediate_exit,
7884 .sched_in = vmx_sched_in,
7886 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7887 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7888 .flush_log_dirty = vmx_flush_log_dirty,
7889 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7890 .write_log_dirty = vmx_write_pml_buffer,
7892 .pre_block = vmx_pre_block,
7893 .post_block = vmx_post_block,
7895 .pmu_ops = &intel_pmu_ops,
7897 .update_pi_irte = vmx_update_pi_irte,
7899 #ifdef CONFIG_X86_64
7900 .set_hv_timer = vmx_set_hv_timer,
7901 .cancel_hv_timer = vmx_cancel_hv_timer,
7904 .setup_mce = vmx_setup_mce,
7906 .smi_allowed = vmx_smi_allowed,
7907 .pre_enter_smm = vmx_pre_enter_smm,
7908 .pre_leave_smm = vmx_pre_leave_smm,
7909 .enable_smi_window = enable_smi_window,
7911 .check_nested_events = NULL,
7912 .get_nested_state = NULL,
7913 .set_nested_state = NULL,
7914 .get_vmcs12_pages = NULL,
7915 .nested_enable_evmcs = NULL,
7916 .nested_get_evmcs_version = NULL,
7917 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7918 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7921 static void vmx_cleanup_l1d_flush(void)
7923 if (vmx_l1d_flush_pages) {
7924 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7925 vmx_l1d_flush_pages = NULL;
7927 /* Restore state so sysfs ignores VMX */
7928 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7931 static void vmx_exit(void)
7933 #ifdef CONFIG_KEXEC_CORE
7934 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7940 #if IS_ENABLED(CONFIG_HYPERV)
7941 if (static_branch_unlikely(&enable_evmcs)) {
7943 struct hv_vp_assist_page *vp_ap;
7945 * Reset everything to support using non-enlightened VMCS
7946 * access later (e.g. when we reload the module with
7947 * enlightened_vmcs=0)
7949 for_each_online_cpu(cpu) {
7950 vp_ap = hv_get_vp_assist_page(cpu);
7955 vp_ap->nested_control.features.directhypercall = 0;
7956 vp_ap->current_nested_vmcs = 0;
7957 vp_ap->enlighten_vmentry = 0;
7960 static_branch_disable(&enable_evmcs);
7963 vmx_cleanup_l1d_flush();
7965 module_exit(vmx_exit);
7967 static int __init vmx_init(void)
7971 #if IS_ENABLED(CONFIG_HYPERV)
7973 * Enlightened VMCS usage should be recommended and the host needs
7974 * to support eVMCS v1 or above. We can also disable eVMCS support
7975 * with module parameter.
7977 if (enlightened_vmcs &&
7978 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7979 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7980 KVM_EVMCS_VERSION) {
7983 /* Check that we have assist pages on all online CPUs */
7984 for_each_online_cpu(cpu) {
7985 if (!hv_get_vp_assist_page(cpu)) {
7986 enlightened_vmcs = false;
7991 if (enlightened_vmcs) {
7992 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7993 static_branch_enable(&enable_evmcs);
7996 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7997 vmx_x86_ops.enable_direct_tlbflush
7998 = hv_enable_direct_tlbflush;
8001 enlightened_vmcs = false;
8005 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8006 __alignof__(struct vcpu_vmx), THIS_MODULE);
8011 * Must be called after kvm_init() so enable_ept is properly set
8012 * up. Hand the parameter mitigation value in which was stored in
8013 * the pre module init parser. If no parameter was given, it will
8014 * contain 'auto' which will be turned into the default 'cond'
8017 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8023 #ifdef CONFIG_KEXEC_CORE
8024 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8025 crash_vmclear_local_loaded_vmcss);
8027 vmx_check_vmcs12_offsets();
8031 module_init(vmx_init);