arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/highmem.h>
  17 #include <linux/hrtimer.h>
  18 #include <linux/kernel.h>
  19 #include <linux/kvm_host.h>
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/mod_devicetable.h>
  23 #include <linux/mm.h>
  24 #include <linux/objtool.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30 #include <linux/entry-kvm.h>
  31
  32 #include <asm/apic.h>
  33 #include <asm/asm.h>
  34 #include <asm/cpu.h>
  35 #include <asm/cpu_device_id.h>
  36 #include <asm/debugreg.h>
  37 #include <asm/desc.h>
  38 #include <asm/fpu/api.h>
  39 #include <asm/idtentry.h>
  40 #include <asm/io.h>
  41 #include <asm/irq_remapping.h>
  42 #include <asm/kexec.h>
  43 #include <asm/perf_event.h>
  44 #include <asm/mmu_context.h>
  45 #include <asm/mshyperv.h>
  46 #include <asm/mwait.h>
  47 #include <asm/spec-ctrl.h>
  48 #include <asm/virtext.h>
  49 #include <asm/vmx.h>
  50
  51 #include "capabilities.h"
  52 #include "cpuid.h"
  53 #include "evmcs.h"
  54 #include "hyperv.h"
  55 #include "kvm_onhyperv.h"
  56 #include "irq.h"
  57 #include "kvm_cache_regs.h"
  58 #include "lapic.h"
  59 #include "mmu.h"
  60 #include "nested.h"
  61 #include "pmu.h"
  62 #include "sgx.h"
  63 #include "trace.h"
  64 #include "vmcs.h"
  65 #include "vmcs12.h"
  66 #include "vmx.h"
  67 #include "x86.h"
  68
  69 MODULE_AUTHOR("Qumranet");
  70 MODULE_LICENSE("GPL");
  71
  72 #ifdef MODULE
  73 static const struct x86_cpu_id vmx_cpu_id[] = {
  74         X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
  75         {}
  76 };
  77 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  78 #endif
  79
  80 bool __read_mostly enable_vpid = 1;
  81 module_param_named(vpid, enable_vpid, bool, 0444);
  82
  83 static bool __read_mostly enable_vnmi = 1;
  84 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  85
  86 bool __read_mostly flexpriority_enabled = 1;
  87 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_ept = 1;
  90 module_param_named(ept, enable_ept, bool, S_IRUGO);
  91
  92 bool __read_mostly enable_unrestricted_guest = 1;
  93 module_param_named(unrestricted_guest,
  94                         enable_unrestricted_guest, bool, S_IRUGO);
  95
  96 bool __read_mostly enable_ept_ad_bits = 1;
  97 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  98
  99 static bool __read_mostly emulate_invalid_guest_state = true;
 100 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
 101
 102 static bool __read_mostly fasteoi = 1;
 103 module_param(fasteoi, bool, S_IRUGO);
 104
 105 module_param(enable_apicv, bool, S_IRUGO);
 106
 107 /*
 108  * If nested=1, nested virtualization is supported, i.e., guests may use
 109  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 110  * use VMX instructions.
 111  */
 112 static bool __read_mostly nested = 1;
 113 module_param(nested, bool, S_IRUGO);
 114
 115 bool __read_mostly enable_pml = 1;
 116 module_param_named(pml, enable_pml, bool, S_IRUGO);
 117
 118 static bool __read_mostly dump_invalid_vmcs = 0;
 119 module_param(dump_invalid_vmcs, bool, 0644);
 120
 121 #define MSR_BITMAP_MODE_X2APIC          1
 122 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 123
 124 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 125
 126 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 127 static int __read_mostly cpu_preemption_timer_multi;
 128 static bool __read_mostly enable_preemption_timer = 1;
 129 #ifdef CONFIG_X86_64
 130 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 131 #endif
 132
 133 extern bool __read_mostly allow_smaller_maxphyaddr;
 134 module_param(allow_smaller_maxphyaddr, bool, S_IRUGO);
 135
 136 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 137 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 138 #define KVM_VM_CR0_ALWAYS_ON                            \
 139         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 140
 141 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 142 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 143 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 144
 145 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 146
 147 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 148         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 149         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 150         RTIT_STATUS_BYTECNT))
 151
 152 /*
 153  * List of MSRs that can be directly passed to the guest.
 154  * In addition to these x2apic and PT MSRs are handled specially.
 155  */
 156 static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = {
 157         MSR_IA32_SPEC_CTRL,
 158         MSR_IA32_PRED_CMD,
 159         MSR_IA32_TSC,
 160 #ifdef CONFIG_X86_64
 161         MSR_FS_BASE,
 162         MSR_GS_BASE,
 163         MSR_KERNEL_GS_BASE,
 164 #endif
 165         MSR_IA32_SYSENTER_CS,
 166         MSR_IA32_SYSENTER_ESP,
 167         MSR_IA32_SYSENTER_EIP,
 168         MSR_CORE_C1_RES,
 169         MSR_CORE_C3_RESIDENCY,
 170         MSR_CORE_C6_RESIDENCY,
 171         MSR_CORE_C7_RESIDENCY,
 172 };
 173
 174 /*
 175  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 176  * ple_gap:    upper bound on the amount of time between two successive
 177  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 178  *             According to test, this time is usually smaller than 128 cycles.
 179  * ple_window: upper bound on the amount of time a guest is allowed to execute
 180  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 181  *             less than 2^12 cycles
 182  * Time is measured based on a counter that runs at the same rate as the TSC,
 183  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 184  */
 185 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 186 module_param(ple_gap, uint, 0444);
 187
 188 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 189 module_param(ple_window, uint, 0444);
 190
 191 /* Default doubles per-vcpu window every exit. */
 192 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 193 module_param(ple_window_grow, uint, 0444);
 194
 195 /* Default resets per-vcpu window every exit to ple_window. */
 196 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 197 module_param(ple_window_shrink, uint, 0444);
 198
 199 /* Default is to compute the maximum so we can never overflow. */
 200 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 201 module_param(ple_window_max, uint, 0444);
 202
 203 /* Default is SYSTEM mode, 1 for host-guest mode */
 204 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 205 module_param(pt_mode, int, S_IRUGO);
 206
 207 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 208 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 209 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 210
 211 /* Storage for pre module init parameter parsing */
 212 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 213
 214 static const struct {
 215         const char *option;
 216         bool for_parse;
 217 } vmentry_l1d_param[] = {
 218         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 219         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 220         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 221         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 222         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 223         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 224 };
 225
 226 #define L1D_CACHE_ORDER 4
 227 static void *vmx_l1d_flush_pages;
 228
 229 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 230 {
 231         struct page *page;
 232         unsigned int i;
 233
 234         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 235                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 236                 return 0;
 237         }
 238
 239         if (!enable_ept) {
 240                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 241                 return 0;
 242         }
 243
 244         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 245                 u64 msr;
 246
 247                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 248                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 249                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 250                         return 0;
 251                 }
 252         }
 253
 254         /* If set to auto use the default l1tf mitigation method */
 255         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 256                 switch (l1tf_mitigation) {
 257                 case L1TF_MITIGATION_OFF:
 258                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 259                         break;
 260                 case L1TF_MITIGATION_FLUSH_NOWARN:
 261                 case L1TF_MITIGATION_FLUSH:
 262                 case L1TF_MITIGATION_FLUSH_NOSMT:
 263                         l1tf = VMENTER_L1D_FLUSH_COND;
 264                         break;
 265                 case L1TF_MITIGATION_FULL:
 266                 case L1TF_MITIGATION_FULL_FORCE:
 267                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 268                         break;
 269                 }
 270         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 271                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 272         }
 273
 274         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 275             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 276                 /*
 277                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 278                  * lifetime and so should not be charged to a memcg.
 279                  */
 280                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 281                 if (!page)
 282                         return -ENOMEM;
 283                 vmx_l1d_flush_pages = page_address(page);
 284
 285                 /*
 286                  * Initialize each page with a different pattern in
 287                  * order to protect against KSM in the nested
 288                  * virtualization case.
 289                  */
 290                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 291                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 292                                PAGE_SIZE);
 293                 }
 294         }
 295
 296         l1tf_vmx_mitigation = l1tf;
 297
 298         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 299                 static_branch_enable(&vmx_l1d_should_flush);
 300         else
 301                 static_branch_disable(&vmx_l1d_should_flush);
 302
 303         if (l1tf == VMENTER_L1D_FLUSH_COND)
 304                 static_branch_enable(&vmx_l1d_flush_cond);
 305         else
 306                 static_branch_disable(&vmx_l1d_flush_cond);
 307         return 0;
 308 }
 309
 310 static int vmentry_l1d_flush_parse(const char *s)
 311 {
 312         unsigned int i;
 313
 314         if (s) {
 315                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 316                         if (vmentry_l1d_param[i].for_parse &&
 317                             sysfs_streq(s, vmentry_l1d_param[i].option))
 318                                 return i;
 319                 }
 320         }
 321         return -EINVAL;
 322 }
 323
 324 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 325 {
 326         int l1tf, ret;
 327
 328         l1tf = vmentry_l1d_flush_parse(s);
 329         if (l1tf < 0)
 330                 return l1tf;
 331
 332         if (!boot_cpu_has(X86_BUG_L1TF))
 333                 return 0;
 334
 335         /*
 336          * Has vmx_init() run already? If not then this is the pre init
 337          * parameter parsing. In that case just store the value and let
 338          * vmx_init() do the proper setup after enable_ept has been
 339          * established.
 340          */
 341         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 342                 vmentry_l1d_flush_param = l1tf;
 343                 return 0;
 344         }
 345
 346         mutex_lock(&vmx_l1d_flush_mutex);
 347         ret = vmx_setup_l1d_flush(l1tf);
 348         mutex_unlock(&vmx_l1d_flush_mutex);
 349         return ret;
 350 }
 351
 352 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 353 {
 354         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 355                 return sprintf(s, "???\n");
 356
 357         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 358 }
 359
 360 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 361         .set = vmentry_l1d_flush_set,
 362         .get = vmentry_l1d_flush_get,
 363 };
 364 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 365
 366 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 367
 368 void vmx_vmexit(void);
 369
 370 #define vmx_insn_failed(fmt...)         \
 371 do {                                    \
 372         WARN_ONCE(1, fmt);              \
 373         pr_warn_ratelimited(fmt);       \
 374 } while (0)
 375
 376 asmlinkage void vmread_error(unsigned long field, bool fault)
 377 {
 378         if (fault)
 379                 kvm_spurious_fault();
 380         else
 381                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 382 }
 383
 384 noinline void vmwrite_error(unsigned long field, unsigned long value)
 385 {
 386         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 387                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 388 }
 389
 390 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 391 {
 392         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 393 }
 394
 395 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 396 {
 397         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 398 }
 399
 400 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 401 {
 402         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 403                         ext, vpid, gva);
 404 }
 405
 406 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 407 {
 408         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 409                         ext, eptp, gpa);
 410 }
 411
 412 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 413 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 414 /*
 415  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 416  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 417  */
 418 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 419
 420 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 421 static DEFINE_SPINLOCK(vmx_vpid_lock);
 422
 423 struct vmcs_config vmcs_config;
 424 struct vmx_capability vmx_capability;
 425
 426 #define VMX_SEGMENT_FIELD(seg)                                  \
 427         [VCPU_SREG_##seg] = {                                   \
 428                 .selector = GUEST_##seg##_SELECTOR,             \
 429                 .base = GUEST_##seg##_BASE,                     \
 430                 .limit = GUEST_##seg##_LIMIT,                   \
 431                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 432         }
 433
 434 static const struct kvm_vmx_segment_field {
 435         unsigned selector;
 436         unsigned base;
 437         unsigned limit;
 438         unsigned ar_bytes;
 439 } kvm_vmx_segment_fields[] = {
 440         VMX_SEGMENT_FIELD(CS),
 441         VMX_SEGMENT_FIELD(DS),
 442         VMX_SEGMENT_FIELD(ES),
 443         VMX_SEGMENT_FIELD(FS),
 444         VMX_SEGMENT_FIELD(GS),
 445         VMX_SEGMENT_FIELD(SS),
 446         VMX_SEGMENT_FIELD(TR),
 447         VMX_SEGMENT_FIELD(LDTR),
 448 };
 449
 450 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
 451 {
 452         vmx->segment_cache.bitmask = 0;
 453 }
 454
 455 static unsigned long host_idt_base;
 456
 457 #if IS_ENABLED(CONFIG_HYPERV)
 458 static bool __read_mostly enlightened_vmcs = true;
 459 module_param(enlightened_vmcs, bool, 0444);
 460
 461 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 462 {
 463         struct hv_enlightened_vmcs *evmcs;
 464         struct hv_partition_assist_pg **p_hv_pa_pg =
 465                         &to_kvm_hv(vcpu->kvm)->hv_pa_pg;
 466         /*
 467          * Synthetic VM-Exit is not enabled in current code and so All
 468          * evmcs in singe VM shares same assist page.
 469          */
 470         if (!*p_hv_pa_pg)
 471                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
 472
 473         if (!*p_hv_pa_pg)
 474                 return -ENOMEM;
 475
 476         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 477
 478         evmcs->partition_assist_page =
 479                 __pa(*p_hv_pa_pg);
 480         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 481         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 482
 483         return 0;
 484 }
 485
 486 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 487
 488 /*
 489  * Comment's format: document - errata name - stepping - processor name.
 490  * Refer from
 491  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 492  */
 493 static u32 vmx_preemption_cpu_tfms[] = {
 494 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 495 0x000206E6,
 496 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 497 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 498 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 499 0x00020652,
 500 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 501 0x00020655,
 502 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 503 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 504 /*
 505  * 320767.pdf - AAP86  - B1 -
 506  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 507  */
 508 0x000106E5,
 509 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 510 0x000106A0,
 511 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 512 0x000106A1,
 513 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 514 0x000106A4,
 515  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 516  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 517  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 518 0x000106A5,
 519  /* Xeon E3-1220 V2 */
 520 0x000306A8,
 521 };
 522
 523 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 524 {
 525         u32 eax = cpuid_eax(0x00000001), i;
 526
 527         /* Clear the reserved bits */
 528         eax &= ~(0x3U << 14 | 0xfU << 28);
 529         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 530                 if (eax == vmx_preemption_cpu_tfms[i])
 531                         return true;
 532
 533         return false;
 534 }
 535
 536 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 537 {
 538         return flexpriority_enabled && lapic_in_kernel(vcpu);
 539 }
 540
 541 static inline bool report_flexpriority(void)
 542 {
 543         return flexpriority_enabled;
 544 }
 545
 546 static int possible_passthrough_msr_slot(u32 msr)
 547 {
 548         u32 i;
 549
 550         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++)
 551                 if (vmx_possible_passthrough_msrs[i] == msr)
 552                         return i;
 553
 554         return -ENOENT;
 555 }
 556
 557 static bool is_valid_passthrough_msr(u32 msr)
 558 {
 559         bool r;
 560
 561         switch (msr) {
 562         case 0x800 ... 0x8ff:
 563                 /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */
 564                 return true;
 565         case MSR_IA32_RTIT_STATUS:
 566         case MSR_IA32_RTIT_OUTPUT_BASE:
 567         case MSR_IA32_RTIT_OUTPUT_MASK:
 568         case MSR_IA32_RTIT_CR3_MATCH:
 569         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
 570                 /* PT MSRs. These are handled in pt_update_intercept_for_msr() */
 571         case MSR_LBR_SELECT:
 572         case MSR_LBR_TOS:
 573         case MSR_LBR_INFO_0 ... MSR_LBR_INFO_0 + 31:
 574         case MSR_LBR_NHM_FROM ... MSR_LBR_NHM_FROM + 31:
 575         case MSR_LBR_NHM_TO ... MSR_LBR_NHM_TO + 31:
 576         case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8:
 577         case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8:
 578                 /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */
 579                 return true;
 580         }
 581
 582         r = possible_passthrough_msr_slot(msr) != -ENOENT;
 583
 584         WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr);
 585
 586         return r;
 587 }
 588
 589 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
 590 {
 591         int i;
 592
 593         i = kvm_find_user_return_msr(msr);
 594         if (i >= 0)
 595                 return &vmx->guest_uret_msrs[i];
 596         return NULL;
 597 }
 598
 599 static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx,
 600                                   struct vmx_uret_msr *msr, u64 data)
 601 {
 602         unsigned int slot = msr - vmx->guest_uret_msrs;
 603         int ret = 0;
 604
 605         u64 old_msr_data = msr->data;
 606         msr->data = data;
 607         if (msr->load_into_hardware) {
 608                 preempt_disable();
 609                 ret = kvm_set_user_return_msr(slot, msr->data, msr->mask);
 610                 preempt_enable();
 611                 if (ret)
 612                         msr->data = old_msr_data;
 613         }
 614         return ret;
 615 }
 616
 617 #ifdef CONFIG_KEXEC_CORE
 618 static void crash_vmclear_local_loaded_vmcss(void)
 619 {
 620         int cpu = raw_smp_processor_id();
 621         struct loaded_vmcs *v;
 622
 623         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 624                             loaded_vmcss_on_cpu_link)
 625                 vmcs_clear(v->vmcs);
 626 }
 627 #endif /* CONFIG_KEXEC_CORE */
 628
 629 static void __loaded_vmcs_clear(void *arg)
 630 {
 631         struct loaded_vmcs *loaded_vmcs = arg;
 632         int cpu = raw_smp_processor_id();
 633
 634         if (loaded_vmcs->cpu != cpu)
 635                 return; /* vcpu migration can race with cpu offline */
 636         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 637                 per_cpu(current_vmcs, cpu) = NULL;
 638
 639         vmcs_clear(loaded_vmcs->vmcs);
 640         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 641                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 642
 643         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 644
 645         /*
 646          * Ensure all writes to loaded_vmcs, including deleting it from its
 647          * current percpu list, complete before setting loaded_vmcs->vcpu to
 648          * -1, otherwise a different cpu can see vcpu == -1 first and add
 649          * loaded_vmcs to its percpu list before it's deleted from this cpu's
 650          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
 651          */
 652         smp_wmb();
 653
 654         loaded_vmcs->cpu = -1;
 655         loaded_vmcs->launched = 0;
 656 }
 657
 658 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 659 {
 660         int cpu = loaded_vmcs->cpu;
 661
 662         if (cpu != -1)
 663                 smp_call_function_single(cpu,
 664                          __loaded_vmcs_clear, loaded_vmcs, 1);
 665 }
 666
 667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 668                                        unsigned field)
 669 {
 670         bool ret;
 671         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 672
 673         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
 674                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
 675                 vmx->segment_cache.bitmask = 0;
 676         }
 677         ret = vmx->segment_cache.bitmask & mask;
 678         vmx->segment_cache.bitmask |= mask;
 679         return ret;
 680 }
 681
 682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 683 {
 684         u16 *p = &vmx->segment_cache.seg[seg].selector;
 685
 686         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 687                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 688         return *p;
 689 }
 690
 691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 692 {
 693         ulong *p = &vmx->segment_cache.seg[seg].base;
 694
 695         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 696                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 697         return *p;
 698 }
 699
 700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 701 {
 702         u32 *p = &vmx->segment_cache.seg[seg].limit;
 703
 704         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 705                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 706         return *p;
 707 }
 708
 709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 710 {
 711         u32 *p = &vmx->segment_cache.seg[seg].ar;
 712
 713         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 714                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 715         return *p;
 716 }
 717
 718 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu)
 719 {
 720         u32 eb;
 721
 722         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 723              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 724         /*
 725          * Guest access to VMware backdoor ports could legitimately
 726          * trigger #GP because of TSS I/O permission bitmap.
 727          * We intercept those #GP and allow access to them anyway
 728          * as VMware does.
 729          */
 730         if (enable_vmware_backdoor)
 731                 eb |= (1u << GP_VECTOR);
 732         if ((vcpu->guest_debug &
 733              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 734             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 735                 eb |= 1u << BP_VECTOR;
 736         if (to_vmx(vcpu)->rmode.vm86_active)
 737                 eb = ~0;
 738         if (!vmx_need_pf_intercept(vcpu))
 739                 eb &= ~(1u << PF_VECTOR);
 740
 741         /* When we are running a nested L2 guest and L1 specified for it a
 742          * certain exception bitmap, we must trap the same exceptions and pass
 743          * them to L1. When running L2, we will only handle the exceptions
 744          * specified above if L1 did not want them.
 745          */
 746         if (is_guest_mode(vcpu))
 747                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 748         else {
 749                 int mask = 0, match = 0;
 750
 751                 if (enable_ept && (eb & (1u << PF_VECTOR))) {
 752                         /*
 753                          * If EPT is enabled, #PF is currently only intercepted
 754                          * if MAXPHYADDR is smaller on the guest than on the
 755                          * host.  In that case we only care about present,
 756                          * non-reserved faults.  For vmcs02, however, PFEC_MASK
 757                          * and PFEC_MATCH are set in prepare_vmcs02_rare.
 758                          */
 759                         mask = PFERR_PRESENT_MASK | PFERR_RSVD_MASK;
 760                         match = PFERR_PRESENT_MASK;
 761                 }
 762                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
 763                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, match);
 764         }
 765
 766         vmcs_write32(EXCEPTION_BITMAP, eb);
 767 }
 768
 769 /*
 770  * Check if MSR is intercepted for currently loaded MSR bitmap.
 771  */
 772 static bool msr_write_intercepted(struct vcpu_vmx *vmx, u32 msr)
 773 {
 774         if (!(exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS))
 775                 return true;
 776
 777         return vmx_test_msr_bitmap_write(vmx->loaded_vmcs->msr_bitmap,
 778                                          MSR_IA32_SPEC_CTRL);
 779 }
 780
 781 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 782                 unsigned long entry, unsigned long exit)
 783 {
 784         vm_entry_controls_clearbit(vmx, entry);
 785         vm_exit_controls_clearbit(vmx, exit);
 786 }
 787
 788 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr)
 789 {
 790         unsigned int i;
 791
 792         for (i = 0; i < m->nr; ++i) {
 793                 if (m->val[i].index == msr)
 794                         return i;
 795         }
 796         return -ENOENT;
 797 }
 798
 799 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 800 {
 801         int i;
 802         struct msr_autoload *m = &vmx->msr_autoload;
 803
 804         switch (msr) {
 805         case MSR_EFER:
 806                 if (cpu_has_load_ia32_efer()) {
 807                         clear_atomic_switch_msr_special(vmx,
 808                                         VM_ENTRY_LOAD_IA32_EFER,
 809                                         VM_EXIT_LOAD_IA32_EFER);
 810                         return;
 811                 }
 812                 break;
 813         case MSR_CORE_PERF_GLOBAL_CTRL:
 814                 if (cpu_has_load_perf_global_ctrl()) {
 815                         clear_atomic_switch_msr_special(vmx,
 816                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 817                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 818                         return;
 819                 }
 820                 break;
 821         }
 822         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
 823         if (i < 0)
 824                 goto skip_guest;
 825         --m->guest.nr;
 826         m->guest.val[i] = m->guest.val[m->guest.nr];
 827         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 828
 829 skip_guest:
 830         i = vmx_find_loadstore_msr_slot(&m->host, msr);
 831         if (i < 0)
 832                 return;
 833
 834         --m->host.nr;
 835         m->host.val[i] = m->host.val[m->host.nr];
 836         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 837 }
 838
 839 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 840                 unsigned long entry, unsigned long exit,
 841                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 842                 u64 guest_val, u64 host_val)
 843 {
 844         vmcs_write64(guest_val_vmcs, guest_val);
 845         if (host_val_vmcs != HOST_IA32_EFER)
 846                 vmcs_write64(host_val_vmcs, host_val);
 847         vm_entry_controls_setbit(vmx, entry);
 848         vm_exit_controls_setbit(vmx, exit);
 849 }
 850
 851 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 852                                   u64 guest_val, u64 host_val, bool entry_only)
 853 {
 854         int i, j = 0;
 855         struct msr_autoload *m = &vmx->msr_autoload;
 856
 857         switch (msr) {
 858         case MSR_EFER:
 859                 if (cpu_has_load_ia32_efer()) {
 860                         add_atomic_switch_msr_special(vmx,
 861                                         VM_ENTRY_LOAD_IA32_EFER,
 862                                         VM_EXIT_LOAD_IA32_EFER,
 863                                         GUEST_IA32_EFER,
 864                                         HOST_IA32_EFER,
 865                                         guest_val, host_val);
 866                         return;
 867                 }
 868                 break;
 869         case MSR_CORE_PERF_GLOBAL_CTRL:
 870                 if (cpu_has_load_perf_global_ctrl()) {
 871                         add_atomic_switch_msr_special(vmx,
 872                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 873                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 874                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 875                                         HOST_IA32_PERF_GLOBAL_CTRL,
 876                                         guest_val, host_val);
 877                         return;
 878                 }
 879                 break;
 880         case MSR_IA32_PEBS_ENABLE:
 881                 /* PEBS needs a quiescent period after being disabled (to write
 882                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 883                  * provide that period, so a CPU could write host's record into
 884                  * guest's memory.
 885                  */
 886                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 887         }
 888
 889         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
 890         if (!entry_only)
 891                 j = vmx_find_loadstore_msr_slot(&m->host, msr);
 892
 893         if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) ||
 894             (j < 0 &&  m->host.nr == MAX_NR_LOADSTORE_MSRS)) {
 895                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 896                                 "Can't add msr %x\n", msr);
 897                 return;
 898         }
 899         if (i < 0) {
 900                 i = m->guest.nr++;
 901                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 902         }
 903         m->guest.val[i].index = msr;
 904         m->guest.val[i].value = guest_val;
 905
 906         if (entry_only)
 907                 return;
 908
 909         if (j < 0) {
 910                 j = m->host.nr++;
 911                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 912         }
 913         m->host.val[j].index = msr;
 914         m->host.val[j].value = host_val;
 915 }
 916
 917 static bool update_transition_efer(struct vcpu_vmx *vmx)
 918 {
 919         u64 guest_efer = vmx->vcpu.arch.efer;
 920         u64 ignore_bits = 0;
 921         int i;
 922
 923         /* Shadow paging assumes NX to be available.  */
 924         if (!enable_ept)
 925                 guest_efer |= EFER_NX;
 926
 927         /*
 928          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 929          */
 930         ignore_bits |= EFER_SCE;
 931 #ifdef CONFIG_X86_64
 932         ignore_bits |= EFER_LMA | EFER_LME;
 933         /* SCE is meaningful only in long mode on Intel */
 934         if (guest_efer & EFER_LMA)
 935                 ignore_bits &= ~(u64)EFER_SCE;
 936 #endif
 937
 938         /*
 939          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 940          * On CPUs that support "load IA32_EFER", always switch EFER
 941          * atomically, since it's faster than switching it manually.
 942          */
 943         if (cpu_has_load_ia32_efer() ||
 944             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 945                 if (!(guest_efer & EFER_LMA))
 946                         guest_efer &= ~EFER_LME;
 947                 if (guest_efer != host_efer)
 948                         add_atomic_switch_msr(vmx, MSR_EFER,
 949                                               guest_efer, host_efer, false);
 950                 else
 951                         clear_atomic_switch_msr(vmx, MSR_EFER);
 952                 return false;
 953         }
 954
 955         i = kvm_find_user_return_msr(MSR_EFER);
 956         if (i < 0)
 957                 return false;
 958
 959         clear_atomic_switch_msr(vmx, MSR_EFER);
 960
 961         guest_efer &= ~ignore_bits;
 962         guest_efer |= host_efer & ignore_bits;
 963
 964         vmx->guest_uret_msrs[i].data = guest_efer;
 965         vmx->guest_uret_msrs[i].mask = ~ignore_bits;
 966
 967         return true;
 968 }
 969
 970 #ifdef CONFIG_X86_32
 971 /*
 972  * On 32-bit kernels, VM exits still load the FS and GS bases from the
 973  * VMCS rather than the segment table.  KVM uses this helper to figure
 974  * out the current bases to poke them into the VMCS before entry.
 975  */
 976 static unsigned long segment_base(u16 selector)
 977 {
 978         struct desc_struct *table;
 979         unsigned long v;
 980
 981         if (!(selector & ~SEGMENT_RPL_MASK))
 982                 return 0;
 983
 984         table = get_current_gdt_ro();
 985
 986         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
 987                 u16 ldt_selector = kvm_read_ldt();
 988
 989                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
 990                         return 0;
 991
 992                 table = (struct desc_struct *)segment_base(ldt_selector);
 993         }
 994         v = get_desc_base(&table[selector >> 3]);
 995         return v;
 996 }
 997 #endif
 998
 999 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1000 {
1001         return vmx_pt_mode_is_host_guest() &&
1002                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1003 }
1004
1005 static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base)
1006 {
1007         /* The base must be 128-byte aligned and a legal physical address. */
1008         return kvm_vcpu_is_legal_aligned_gpa(vcpu, base, 128);
1009 }
1010
1011 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1012 {
1013         u32 i;
1014
1015         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1016         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1017         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1018         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1019         for (i = 0; i < addr_range; i++) {
1020                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1021                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1022         }
1023 }
1024
1025 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1026 {
1027         u32 i;
1028
1029         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1030         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1031         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1032         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1033         for (i = 0; i < addr_range; i++) {
1034                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1035                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1036         }
1037 }
1038
1039 static void pt_guest_enter(struct vcpu_vmx *vmx)
1040 {
1041         if (vmx_pt_mode_is_system())
1042                 return;
1043
1044         /*
1045          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1046          * Save host state before VM entry.
1047          */
1048         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1049         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1050                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1051                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1052                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1053         }
1054 }
1055
1056 static void pt_guest_exit(struct vcpu_vmx *vmx)
1057 {
1058         if (vmx_pt_mode_is_system())
1059                 return;
1060
1061         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1062                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1063                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1064         }
1065
1066         /*
1067          * KVM requires VM_EXIT_CLEAR_IA32_RTIT_CTL to expose PT to the guest,
1068          * i.e. RTIT_CTL is always cleared on VM-Exit.  Restore it if necessary.
1069          */
1070         if (vmx->pt_desc.host.ctl)
1071                 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1072 }
1073
1074 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1075                         unsigned long fs_base, unsigned long gs_base)
1076 {
1077         if (unlikely(fs_sel != host->fs_sel)) {
1078                 if (!(fs_sel & 7))
1079                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1080                 else
1081                         vmcs_write16(HOST_FS_SELECTOR, 0);
1082                 host->fs_sel = fs_sel;
1083         }
1084         if (unlikely(gs_sel != host->gs_sel)) {
1085                 if (!(gs_sel & 7))
1086                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1087                 else
1088                         vmcs_write16(HOST_GS_SELECTOR, 0);
1089                 host->gs_sel = gs_sel;
1090         }
1091         if (unlikely(fs_base != host->fs_base)) {
1092                 vmcs_writel(HOST_FS_BASE, fs_base);
1093                 host->fs_base = fs_base;
1094         }
1095         if (unlikely(gs_base != host->gs_base)) {
1096                 vmcs_writel(HOST_GS_BASE, gs_base);
1097                 host->gs_base = gs_base;
1098         }
1099 }
1100
1101 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1102 {
1103         struct vcpu_vmx *vmx = to_vmx(vcpu);
1104         struct vmcs_host_state *host_state;
1105 #ifdef CONFIG_X86_64
1106         int cpu = raw_smp_processor_id();
1107 #endif
1108         unsigned long fs_base, gs_base;
1109         u16 fs_sel, gs_sel;
1110         int i;
1111
1112         vmx->req_immediate_exit = false;
1113
1114         /*
1115          * Note that guest MSRs to be saved/restored can also be changed
1116          * when guest state is loaded. This happens when guest transitions
1117          * to/from long-mode by setting MSR_EFER.LMA.
1118          */
1119         if (!vmx->guest_uret_msrs_loaded) {
1120                 vmx->guest_uret_msrs_loaded = true;
1121                 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
1122                         if (!vmx->guest_uret_msrs[i].load_into_hardware)
1123                                 continue;
1124
1125                         kvm_set_user_return_msr(i,
1126                                                 vmx->guest_uret_msrs[i].data,
1127                                                 vmx->guest_uret_msrs[i].mask);
1128                 }
1129         }
1130
1131         if (vmx->nested.need_vmcs12_to_shadow_sync)
1132                 nested_sync_vmcs12_to_shadow(vcpu);
1133
1134         if (vmx->guest_state_loaded)
1135                 return;
1136
1137         host_state = &vmx->loaded_vmcs->host_state;
1138
1139         /*
1140          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1141          * allow segment selectors with cpl > 0 or ti == 1.
1142          */
1143         host_state->ldt_sel = kvm_read_ldt();
1144
1145 #ifdef CONFIG_X86_64
1146         savesegment(ds, host_state->ds_sel);
1147         savesegment(es, host_state->es_sel);
1148
1149         gs_base = cpu_kernelmode_gs_base(cpu);
1150         if (likely(is_64bit_mm(current->mm))) {
1151                 current_save_fsgs();
1152                 fs_sel = current->thread.fsindex;
1153                 gs_sel = current->thread.gsindex;
1154                 fs_base = current->thread.fsbase;
1155                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1156         } else {
1157                 savesegment(fs, fs_sel);
1158                 savesegment(gs, gs_sel);
1159                 fs_base = read_msr(MSR_FS_BASE);
1160                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1161         }
1162
1163         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1164 #else
1165         savesegment(fs, fs_sel);
1166         savesegment(gs, gs_sel);
1167         fs_base = segment_base(fs_sel);
1168         gs_base = segment_base(gs_sel);
1169 #endif
1170
1171         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1172         vmx->guest_state_loaded = true;
1173 }
1174
1175 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1176 {
1177         struct vmcs_host_state *host_state;
1178
1179         if (!vmx->guest_state_loaded)
1180                 return;
1181
1182         host_state = &vmx->loaded_vmcs->host_state;
1183
1184         ++vmx->vcpu.stat.host_state_reload;
1185
1186 #ifdef CONFIG_X86_64
1187         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1188 #endif
1189         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1190                 kvm_load_ldt(host_state->ldt_sel);
1191 #ifdef CONFIG_X86_64
1192                 load_gs_index(host_state->gs_sel);
1193 #else
1194                 loadsegment(gs, host_state->gs_sel);
1195 #endif
1196         }
1197         if (host_state->fs_sel & 7)
1198                 loadsegment(fs, host_state->fs_sel);
1199 #ifdef CONFIG_X86_64
1200         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1201                 loadsegment(ds, host_state->ds_sel);
1202                 loadsegment(es, host_state->es_sel);
1203         }
1204 #endif
1205         invalidate_tss_limit();
1206 #ifdef CONFIG_X86_64
1207         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1208 #endif
1209         load_fixmap_gdt(raw_smp_processor_id());
1210         vmx->guest_state_loaded = false;
1211         vmx->guest_uret_msrs_loaded = false;
1212 }
1213
1214 #ifdef CONFIG_X86_64
1215 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1216 {
1217         preempt_disable();
1218         if (vmx->guest_state_loaded)
1219                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1220         preempt_enable();
1221         return vmx->msr_guest_kernel_gs_base;
1222 }
1223
1224 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1225 {
1226         preempt_disable();
1227         if (vmx->guest_state_loaded)
1228                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1229         preempt_enable();
1230         vmx->msr_guest_kernel_gs_base = data;
1231 }
1232 #endif
1233
1234 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1235                         struct loaded_vmcs *buddy)
1236 {
1237         struct vcpu_vmx *vmx = to_vmx(vcpu);
1238         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1239         struct vmcs *prev;
1240
1241         if (!already_loaded) {
1242                 loaded_vmcs_clear(vmx->loaded_vmcs);
1243                 local_irq_disable();
1244
1245                 /*
1246                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1247                  * this cpu's percpu list, otherwise it may not yet be deleted
1248                  * from its previous cpu's percpu list.  Pairs with the
1249                  * smb_wmb() in __loaded_vmcs_clear().
1250                  */
1251                 smp_rmb();
1252
1253                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1254                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1255                 local_irq_enable();
1256         }
1257
1258         prev = per_cpu(current_vmcs, cpu);
1259         if (prev != vmx->loaded_vmcs->vmcs) {
1260                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1261                 vmcs_load(vmx->loaded_vmcs->vmcs);
1262
1263                 /*
1264                  * No indirect branch prediction barrier needed when switching
1265                  * the active VMCS within a guest, e.g. on nested VM-Enter.
1266                  * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1267                  */
1268                 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1269                         indirect_branch_prediction_barrier();
1270         }
1271
1272         if (!already_loaded) {
1273                 void *gdt = get_current_gdt_ro();
1274                 unsigned long sysenter_esp;
1275
1276                 /*
1277                  * Flush all EPTP/VPID contexts, the new pCPU may have stale
1278                  * TLB entries from its previous association with the vCPU.
1279                  */
1280                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1281
1282                 /*
1283                  * Linux uses per-cpu TSS and GDT, so set these when switching
1284                  * processors.  See 22.2.4.
1285                  */
1286                 vmcs_writel(HOST_TR_BASE,
1287                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1288                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1289
1290                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1291                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1292
1293                 vmx->loaded_vmcs->cpu = cpu;
1294         }
1295 }
1296
1297 /*
1298  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1299  * vcpu mutex is already taken.
1300  */
1301 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1302 {
1303         struct vcpu_vmx *vmx = to_vmx(vcpu);
1304
1305         vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1306
1307         vmx_vcpu_pi_load(vcpu, cpu);
1308
1309         vmx->host_debugctlmsr = get_debugctlmsr();
1310 }
1311
1312 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1313 {
1314         vmx_vcpu_pi_put(vcpu);
1315
1316         vmx_prepare_switch_to_host(to_vmx(vcpu));
1317 }
1318
1319 bool vmx_emulation_required(struct kvm_vcpu *vcpu)
1320 {
1321         return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu);
1322 }
1323
1324 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1325 {
1326         struct vcpu_vmx *vmx = to_vmx(vcpu);
1327         unsigned long rflags, save_rflags;
1328
1329         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1330                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1331                 rflags = vmcs_readl(GUEST_RFLAGS);
1332                 if (vmx->rmode.vm86_active) {
1333                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1334                         save_rflags = vmx->rmode.save_rflags;
1335                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1336                 }
1337                 vmx->rflags = rflags;
1338         }
1339         return vmx->rflags;
1340 }
1341
1342 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1343 {
1344         struct vcpu_vmx *vmx = to_vmx(vcpu);
1345         unsigned long old_rflags;
1346
1347         if (is_unrestricted_guest(vcpu)) {
1348                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1349                 vmx->rflags = rflags;
1350                 vmcs_writel(GUEST_RFLAGS, rflags);
1351                 return;
1352         }
1353
1354         old_rflags = vmx_get_rflags(vcpu);
1355         vmx->rflags = rflags;
1356         if (vmx->rmode.vm86_active) {
1357                 vmx->rmode.save_rflags = rflags;
1358                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1359         }
1360         vmcs_writel(GUEST_RFLAGS, rflags);
1361
1362         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1363                 vmx->emulation_required = vmx_emulation_required(vcpu);
1364 }
1365
1366 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1367 {
1368         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1369         int ret = 0;
1370
1371         if (interruptibility & GUEST_INTR_STATE_STI)
1372                 ret |= KVM_X86_SHADOW_INT_STI;
1373         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1374                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1375
1376         return ret;
1377 }
1378
1379 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1380 {
1381         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1382         u32 interruptibility = interruptibility_old;
1383
1384         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1385
1386         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1387                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1388         else if (mask & KVM_X86_SHADOW_INT_STI)
1389                 interruptibility |= GUEST_INTR_STATE_STI;
1390
1391         if ((interruptibility != interruptibility_old))
1392                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1393 }
1394
1395 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1396 {
1397         struct vcpu_vmx *vmx = to_vmx(vcpu);
1398         unsigned long value;
1399
1400         /*
1401          * Any MSR write that attempts to change bits marked reserved will
1402          * case a #GP fault.
1403          */
1404         if (data & vmx->pt_desc.ctl_bitmask)
1405                 return 1;
1406
1407         /*
1408          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1409          * result in a #GP unless the same write also clears TraceEn.
1410          */
1411         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1412                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1413                 return 1;
1414
1415         /*
1416          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1417          * and FabricEn would cause #GP, if
1418          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1419          */
1420         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1421                 !(data & RTIT_CTL_FABRIC_EN) &&
1422                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1423                                         PT_CAP_single_range_output))
1424                 return 1;
1425
1426         /*
1427          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1428          * utilize encodings marked reserved will cause a #GP fault.
1429          */
1430         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1431         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1432                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1433                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1434                 return 1;
1435         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1436                                                 PT_CAP_cycle_thresholds);
1437         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1438                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1439                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1440                 return 1;
1441         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1442         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1443                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1444                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1445                 return 1;
1446
1447         /*
1448          * If ADDRx_CFG is reserved or the encodings is >2 will
1449          * cause a #GP fault.
1450          */
1451         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1452         if ((value && (vmx->pt_desc.num_address_ranges < 1)) || (value > 2))
1453                 return 1;
1454         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1455         if ((value && (vmx->pt_desc.num_address_ranges < 2)) || (value > 2))
1456                 return 1;
1457         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1458         if ((value && (vmx->pt_desc.num_address_ranges < 3)) || (value > 2))
1459                 return 1;
1460         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1461         if ((value && (vmx->pt_desc.num_address_ranges < 4)) || (value > 2))
1462                 return 1;
1463
1464         return 0;
1465 }
1466
1467 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
1468 {
1469         /*
1470          * Emulation of instructions in SGX enclaves is impossible as RIP does
1471          * not point  tthe failing instruction, and even if it did, the code
1472          * stream is inaccessible.  Inject #UD instead of exiting to userspace
1473          * so that guest userspace can't DoS the guest simply by triggering
1474          * emulation (enclaves are CPL3 only).
1475          */
1476         if (to_vmx(vcpu)->exit_reason.enclave_mode) {
1477                 kvm_queue_exception(vcpu, UD_VECTOR);
1478                 return false;
1479         }
1480         return true;
1481 }
1482
1483 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1484 {
1485         union vmx_exit_reason exit_reason = to_vmx(vcpu)->exit_reason;
1486         unsigned long rip, orig_rip;
1487         u32 instr_len;
1488
1489         /*
1490          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1491          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1492          * set when EPT misconfig occurs.  In practice, real hardware updates
1493          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1494          * (namely Hyper-V) don't set it due to it being undefined behavior,
1495          * i.e. we end up advancing IP with some random value.
1496          */
1497         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1498             exit_reason.basic != EXIT_REASON_EPT_MISCONFIG) {
1499                 instr_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1500
1501                 /*
1502                  * Emulating an enclave's instructions isn't supported as KVM
1503                  * cannot access the enclave's memory or its true RIP, e.g. the
1504                  * vmcs.GUEST_RIP points at the exit point of the enclave, not
1505                  * the RIP that actually triggered the VM-Exit.  But, because
1506                  * most instructions that cause VM-Exit will #UD in an enclave,
1507                  * most instruction-based VM-Exits simply do not occur.
1508                  *
1509                  * There are a few exceptions, notably the debug instructions
1510                  * INT1ICEBRK and INT3, as they are allowed in debug enclaves
1511                  * and generate #DB/#BP as expected, which KVM might intercept.
1512                  * But again, the CPU does the dirty work and saves an instr
1513                  * length of zero so VMMs don't shoot themselves in the foot.
1514                  * WARN if KVM tries to skip a non-zero length instruction on
1515                  * a VM-Exit from an enclave.
1516                  */
1517                 if (!instr_len)
1518                         goto rip_updated;
1519
1520                 WARN(exit_reason.enclave_mode,
1521                      "KVM: skipping instruction after SGX enclave VM-Exit");
1522
1523                 orig_rip = kvm_rip_read(vcpu);
1524                 rip = orig_rip + instr_len;
1525 #ifdef CONFIG_X86_64
1526                 /*
1527                  * We need to mask out the high 32 bits of RIP if not in 64-bit
1528                  * mode, but just finding out that we are in 64-bit mode is
1529                  * quite expensive.  Only do it if there was a carry.
1530                  */
1531                 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1532                         rip = (u32)rip;
1533 #endif
1534                 kvm_rip_write(vcpu, rip);
1535         } else {
1536                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1537                         return 0;
1538         }
1539
1540 rip_updated:
1541         /* skipping an emulated instruction also counts */
1542         vmx_set_interrupt_shadow(vcpu, 0);
1543
1544         return 1;
1545 }
1546
1547 /*
1548  * Recognizes a pending MTF VM-exit and records the nested state for later
1549  * delivery.
1550  */
1551 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1552 {
1553         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1554         struct vcpu_vmx *vmx = to_vmx(vcpu);
1555
1556         if (!is_guest_mode(vcpu))
1557                 return;
1558
1559         /*
1560          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1561          * T-bit traps. As instruction emulation is completed (i.e. at the
1562          * instruction boundary), any #DB exception pending delivery must be a
1563          * debug-trap. Record the pending MTF state to be delivered in
1564          * vmx_check_nested_events().
1565          */
1566         if (nested_cpu_has_mtf(vmcs12) &&
1567             (!vcpu->arch.exception.pending ||
1568              vcpu->arch.exception.nr == DB_VECTOR))
1569                 vmx->nested.mtf_pending = true;
1570         else
1571                 vmx->nested.mtf_pending = false;
1572 }
1573
1574 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1575 {
1576         vmx_update_emulated_instruction(vcpu);
1577         return skip_emulated_instruction(vcpu);
1578 }
1579
1580 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1581 {
1582         /*
1583          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1584          * explicitly skip the instruction because if the HLT state is set,
1585          * then the instruction is already executing and RIP has already been
1586          * advanced.
1587          */
1588         if (kvm_hlt_in_guest(vcpu->kvm) &&
1589                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1590                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1591 }
1592
1593 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1594 {
1595         struct vcpu_vmx *vmx = to_vmx(vcpu);
1596         unsigned nr = vcpu->arch.exception.nr;
1597         bool has_error_code = vcpu->arch.exception.has_error_code;
1598         u32 error_code = vcpu->arch.exception.error_code;
1599         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1600
1601         kvm_deliver_exception_payload(vcpu);
1602
1603         if (has_error_code) {
1604                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1605                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1606         }
1607
1608         if (vmx->rmode.vm86_active) {
1609                 int inc_eip = 0;
1610                 if (kvm_exception_is_soft(nr))
1611                         inc_eip = vcpu->arch.event_exit_inst_len;
1612                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1613                 return;
1614         }
1615
1616         WARN_ON_ONCE(vmx->emulation_required);
1617
1618         if (kvm_exception_is_soft(nr)) {
1619                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1620                              vmx->vcpu.arch.event_exit_inst_len);
1621                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1622         } else
1623                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1624
1625         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1626
1627         vmx_clear_hlt(vcpu);
1628 }
1629
1630 static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr,
1631                                bool load_into_hardware)
1632 {
1633         struct vmx_uret_msr *uret_msr;
1634
1635         uret_msr = vmx_find_uret_msr(vmx, msr);
1636         if (!uret_msr)
1637                 return;
1638
1639         uret_msr->load_into_hardware = load_into_hardware;
1640 }
1641
1642 /*
1643  * Configuring user return MSRs to automatically save, load, and restore MSRs
1644  * that need to be shoved into hardware when running the guest.  Note, omitting
1645  * an MSR here does _NOT_ mean it's not emulated, only that it will not be
1646  * loaded into hardware when running the guest.
1647  */
1648 static void vmx_setup_uret_msrs(struct vcpu_vmx *vmx)
1649 {
1650 #ifdef CONFIG_X86_64
1651         bool load_syscall_msrs;
1652
1653         /*
1654          * The SYSCALL MSRs are only needed on long mode guests, and only
1655          * when EFER.SCE is set.
1656          */
1657         load_syscall_msrs = is_long_mode(&vmx->vcpu) &&
1658                             (vmx->vcpu.arch.efer & EFER_SCE);
1659
1660         vmx_setup_uret_msr(vmx, MSR_STAR, load_syscall_msrs);
1661         vmx_setup_uret_msr(vmx, MSR_LSTAR, load_syscall_msrs);
1662         vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK, load_syscall_msrs);
1663 #endif
1664         vmx_setup_uret_msr(vmx, MSR_EFER, update_transition_efer(vmx));
1665
1666         vmx_setup_uret_msr(vmx, MSR_TSC_AUX,
1667                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP) ||
1668                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDPID));
1669
1670         /*
1671          * hle=0, rtm=0, tsx_ctrl=1 can be found with some combinations of new
1672          * kernel and old userspace.  If those guests run on a tsx=off host, do
1673          * allow guests to use TSX_CTRL, but don't change the value in hardware
1674          * so that TSX remains always disabled.
1675          */
1676         vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL, boot_cpu_has(X86_FEATURE_RTM));
1677
1678         /*
1679          * The set of MSRs to load may have changed, reload MSRs before the
1680          * next VM-Enter.
1681          */
1682         vmx->guest_uret_msrs_loaded = false;
1683 }
1684
1685 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1686 {
1687         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1688
1689         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING))
1690                 return vmcs12->tsc_offset;
1691
1692         return 0;
1693 }
1694
1695 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1696 {
1697         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1698
1699         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING) &&
1700             nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
1701                 return vmcs12->tsc_multiplier;
1702
1703         return kvm_default_tsc_scaling_ratio;
1704 }
1705
1706 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1707 {
1708         vmcs_write64(TSC_OFFSET, offset);
1709 }
1710
1711 static void vmx_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1712 {
1713         vmcs_write64(TSC_MULTIPLIER, multiplier);
1714 }
1715
1716 /*
1717  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1718  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1719  * all guests if the "nested" module option is off, and can also be disabled
1720  * for a single guest by disabling its VMX cpuid bit.
1721  */
1722 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1723 {
1724         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1725 }
1726
1727 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1728                                                  uint64_t val)
1729 {
1730         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1731
1732         return !(val & ~valid_bits);
1733 }
1734
1735 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1736 {
1737         switch (msr->index) {
1738         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1739                 if (!nested)
1740                         return 1;
1741                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1742         case MSR_IA32_PERF_CAPABILITIES:
1743                 msr->data = vmx_get_perf_capabilities();
1744                 return 0;
1745         default:
1746                 return KVM_MSR_RET_INVALID;
1747         }
1748 }
1749
1750 /*
1751  * Reads an msr value (of 'msr_index') into 'pdata'.
1752  * Returns 0 on success, non-0 otherwise.
1753  * Assumes vcpu_load() was already called.
1754  */
1755 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1756 {
1757         struct vcpu_vmx *vmx = to_vmx(vcpu);
1758         struct vmx_uret_msr *msr;
1759         u32 index;
1760
1761         switch (msr_info->index) {
1762 #ifdef CONFIG_X86_64
1763         case MSR_FS_BASE:
1764                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1765                 break;
1766         case MSR_GS_BASE:
1767                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1768                 break;
1769         case MSR_KERNEL_GS_BASE:
1770                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1771                 break;
1772 #endif
1773         case MSR_EFER:
1774                 return kvm_get_msr_common(vcpu, msr_info);
1775         case MSR_IA32_TSX_CTRL:
1776                 if (!msr_info->host_initiated &&
1777                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1778                         return 1;
1779                 goto find_uret_msr;
1780         case MSR_IA32_UMWAIT_CONTROL:
1781                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1782                         return 1;
1783
1784                 msr_info->data = vmx->msr_ia32_umwait_control;
1785                 break;
1786         case MSR_IA32_SPEC_CTRL:
1787                 if (!msr_info->host_initiated &&
1788                     !guest_has_spec_ctrl_msr(vcpu))
1789                         return 1;
1790
1791                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1792                 break;
1793         case MSR_IA32_SYSENTER_CS:
1794                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1795                 break;
1796         case MSR_IA32_SYSENTER_EIP:
1797                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1798                 break;
1799         case MSR_IA32_SYSENTER_ESP:
1800                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1801                 break;
1802         case MSR_IA32_BNDCFGS:
1803                 if (!kvm_mpx_supported() ||
1804                     (!msr_info->host_initiated &&
1805                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1806                         return 1;
1807                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1808                 break;
1809         case MSR_IA32_MCG_EXT_CTL:
1810                 if (!msr_info->host_initiated &&
1811                     !(vmx->msr_ia32_feature_control &
1812                       FEAT_CTL_LMCE_ENABLED))
1813                         return 1;
1814                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1815                 break;
1816         case MSR_IA32_FEAT_CTL:
1817                 msr_info->data = vmx->msr_ia32_feature_control;
1818                 break;
1819         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
1820                 if (!msr_info->host_initiated &&
1821                     !guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
1822                         return 1;
1823                 msr_info->data = to_vmx(vcpu)->msr_ia32_sgxlepubkeyhash
1824                         [msr_info->index - MSR_IA32_SGXLEPUBKEYHASH0];
1825                 break;
1826         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1827                 if (!nested_vmx_allowed(vcpu))
1828                         return 1;
1829                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1830                                     &msr_info->data))
1831                         return 1;
1832                 /*
1833                  * Enlightened VMCS v1 doesn't have certain VMCS fields but
1834                  * instead of just ignoring the features, different Hyper-V
1835                  * versions are either trying to use them and fail or do some
1836                  * sanity checking and refuse to boot. Filter all unsupported
1837                  * features out.
1838                  */
1839                 if (!msr_info->host_initiated &&
1840                     vmx->nested.enlightened_vmcs_enabled)
1841                         nested_evmcs_filter_control_msr(msr_info->index,
1842                                                         &msr_info->data);
1843                 break;
1844         case MSR_IA32_RTIT_CTL:
1845                 if (!vmx_pt_mode_is_host_guest())
1846                         return 1;
1847                 msr_info->data = vmx->pt_desc.guest.ctl;
1848                 break;
1849         case MSR_IA32_RTIT_STATUS:
1850                 if (!vmx_pt_mode_is_host_guest())
1851                         return 1;
1852                 msr_info->data = vmx->pt_desc.guest.status;
1853                 break;
1854         case MSR_IA32_RTIT_CR3_MATCH:
1855                 if (!vmx_pt_mode_is_host_guest() ||
1856                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1857                                                 PT_CAP_cr3_filtering))
1858                         return 1;
1859                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1860                 break;
1861         case MSR_IA32_RTIT_OUTPUT_BASE:
1862                 if (!vmx_pt_mode_is_host_guest() ||
1863                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1864                                         PT_CAP_topa_output) &&
1865                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1866                                         PT_CAP_single_range_output)))
1867                         return 1;
1868                 msr_info->data = vmx->pt_desc.guest.output_base;
1869                 break;
1870         case MSR_IA32_RTIT_OUTPUT_MASK:
1871                 if (!vmx_pt_mode_is_host_guest() ||
1872                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1873                                         PT_CAP_topa_output) &&
1874                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1875                                         PT_CAP_single_range_output)))
1876                         return 1;
1877                 msr_info->data = vmx->pt_desc.guest.output_mask;
1878                 break;
1879         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1880                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1881                 if (!vmx_pt_mode_is_host_guest() ||
1882                     (index >= 2 * vmx->pt_desc.num_address_ranges))
1883                         return 1;
1884                 if (index % 2)
1885                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1886                 else
1887                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1888                 break;
1889         case MSR_IA32_DEBUGCTLMSR:
1890                 msr_info->data = vmcs_read64(GUEST_IA32_DEBUGCTL);
1891                 break;
1892         default:
1893         find_uret_msr:
1894                 msr = vmx_find_uret_msr(vmx, msr_info->index);
1895                 if (msr) {
1896                         msr_info->data = msr->data;
1897                         break;
1898                 }
1899                 return kvm_get_msr_common(vcpu, msr_info);
1900         }
1901
1902         return 0;
1903 }
1904
1905 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1906                                                     u64 data)
1907 {
1908 #ifdef CONFIG_X86_64
1909         if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1910                 return (u32)data;
1911 #endif
1912         return (unsigned long)data;
1913 }
1914
1915 static u64 vcpu_supported_debugctl(struct kvm_vcpu *vcpu)
1916 {
1917         u64 debugctl = vmx_supported_debugctl();
1918
1919         if (!intel_pmu_lbr_is_enabled(vcpu))
1920                 debugctl &= ~DEBUGCTLMSR_LBR_MASK;
1921
1922         if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1923                 debugctl &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1924
1925         return debugctl;
1926 }
1927
1928 /*
1929  * Writes msr value into the appropriate "register".
1930  * Returns 0 on success, non-0 otherwise.
1931  * Assumes vcpu_load() was already called.
1932  */
1933 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1934 {
1935         struct vcpu_vmx *vmx = to_vmx(vcpu);
1936         struct vmx_uret_msr *msr;
1937         int ret = 0;
1938         u32 msr_index = msr_info->index;
1939         u64 data = msr_info->data;
1940         u32 index;
1941
1942         switch (msr_index) {
1943         case MSR_EFER:
1944                 ret = kvm_set_msr_common(vcpu, msr_info);
1945                 break;
1946 #ifdef CONFIG_X86_64
1947         case MSR_FS_BASE:
1948                 vmx_segment_cache_clear(vmx);
1949                 vmcs_writel(GUEST_FS_BASE, data);
1950                 break;
1951         case MSR_GS_BASE:
1952                 vmx_segment_cache_clear(vmx);
1953                 vmcs_writel(GUEST_GS_BASE, data);
1954                 break;
1955         case MSR_KERNEL_GS_BASE:
1956                 vmx_write_guest_kernel_gs_base(vmx, data);
1957                 break;
1958 #endif
1959         case MSR_IA32_SYSENTER_CS:
1960                 if (is_guest_mode(vcpu))
1961                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1962                 vmcs_write32(GUEST_SYSENTER_CS, data);
1963                 break;
1964         case MSR_IA32_SYSENTER_EIP:
1965                 if (is_guest_mode(vcpu)) {
1966                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1967                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1968                 }
1969                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1970                 break;
1971         case MSR_IA32_SYSENTER_ESP:
1972                 if (is_guest_mode(vcpu)) {
1973                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1974                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1975                 }
1976                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1977                 break;
1978         case MSR_IA32_DEBUGCTLMSR: {
1979                 u64 invalid = data & ~vcpu_supported_debugctl(vcpu);
1980                 if (invalid & (DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR)) {
1981                         if (report_ignored_msrs)
1982                                 vcpu_unimpl(vcpu, "%s: BTF|LBR in IA32_DEBUGCTLMSR 0x%llx, nop\n",
1983                                             __func__, data);
1984                         data &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1985                         invalid &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1986                 }
1987
1988                 if (invalid)
1989                         return 1;
1990
1991                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1992                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
1993                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1994
1995                 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
1996                 if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event &&
1997                     (data & DEBUGCTLMSR_LBR))
1998                         intel_pmu_create_guest_lbr_event(vcpu);
1999                 return 0;
2000         }
2001         case MSR_IA32_BNDCFGS:
2002                 if (!kvm_mpx_supported() ||
2003                     (!msr_info->host_initiated &&
2004                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2005                         return 1;
2006                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2007                     (data & MSR_IA32_BNDCFGS_RSVD))
2008                         return 1;
2009                 vmcs_write64(GUEST_BNDCFGS, data);
2010                 break;
2011         case MSR_IA32_UMWAIT_CONTROL:
2012                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2013                         return 1;
2014
2015                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2016                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2017                         return 1;
2018
2019                 vmx->msr_ia32_umwait_control = data;
2020                 break;
2021         case MSR_IA32_SPEC_CTRL:
2022                 if (!msr_info->host_initiated &&
2023                     !guest_has_spec_ctrl_msr(vcpu))
2024                         return 1;
2025
2026                 if (kvm_spec_ctrl_test_value(data))
2027                         return 1;
2028
2029                 vmx->spec_ctrl = data;
2030                 if (!data)
2031                         break;
2032
2033                 /*
2034                  * For non-nested:
2035                  * When it's written (to non-zero) for the first time, pass
2036                  * it through.
2037                  *
2038                  * For nested:
2039                  * The handling of the MSR bitmap for L2 guests is done in
2040                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2041                  * vmcs02.msr_bitmap here since it gets completely overwritten
2042                  * in the merging. We update the vmcs01 here for L1 as well
2043                  * since it will end up touching the MSR anyway now.
2044                  */
2045                 vmx_disable_intercept_for_msr(vcpu,
2046                                               MSR_IA32_SPEC_CTRL,
2047                                               MSR_TYPE_RW);
2048                 break;
2049         case MSR_IA32_TSX_CTRL:
2050                 if (!msr_info->host_initiated &&
2051                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2052                         return 1;
2053                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2054                         return 1;
2055                 goto find_uret_msr;
2056         case MSR_IA32_PRED_CMD:
2057                 if (!msr_info->host_initiated &&
2058                     !guest_has_pred_cmd_msr(vcpu))
2059                         return 1;
2060
2061                 if (data & ~PRED_CMD_IBPB)
2062                         return 1;
2063                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2064                         return 1;
2065                 if (!data)
2066                         break;
2067
2068                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2069
2070                 /*
2071                  * For non-nested:
2072                  * When it's written (to non-zero) for the first time, pass
2073                  * it through.
2074                  *
2075                  * For nested:
2076                  * The handling of the MSR bitmap for L2 guests is done in
2077                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2078                  * vmcs02.msr_bitmap here since it gets completely overwritten
2079                  * in the merging.
2080                  */
2081                 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
2082                 break;
2083         case MSR_IA32_CR_PAT:
2084                 if (!kvm_pat_valid(data))
2085                         return 1;
2086
2087                 if (is_guest_mode(vcpu) &&
2088                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2089                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2090
2091                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2092                         vmcs_write64(GUEST_IA32_PAT, data);
2093                         vcpu->arch.pat = data;
2094                         break;
2095                 }
2096                 ret = kvm_set_msr_common(vcpu, msr_info);
2097                 break;
2098         case MSR_IA32_TSC_ADJUST:
2099                 ret = kvm_set_msr_common(vcpu, msr_info);
2100                 break;
2101         case MSR_IA32_MCG_EXT_CTL:
2102                 if ((!msr_info->host_initiated &&
2103                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2104                        FEAT_CTL_LMCE_ENABLED)) ||
2105                     (data & ~MCG_EXT_CTL_LMCE_EN))
2106                         return 1;
2107                 vcpu->arch.mcg_ext_ctl = data;
2108                 break;
2109         case MSR_IA32_FEAT_CTL:
2110                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2111                     (to_vmx(vcpu)->msr_ia32_feature_control &
2112                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2113                         return 1;
2114                 vmx->msr_ia32_feature_control = data;
2115                 if (msr_info->host_initiated && data == 0)
2116                         vmx_leave_nested(vcpu);
2117
2118                 /* SGX may be enabled/disabled by guest's firmware */
2119                 vmx_write_encls_bitmap(vcpu, NULL);
2120                 break;
2121         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
2122                 /*
2123                  * On real hardware, the LE hash MSRs are writable before
2124                  * the firmware sets bit 0 in MSR 0x7a ("activating" SGX),
2125                  * at which point SGX related bits in IA32_FEATURE_CONTROL
2126                  * become writable.
2127                  *
2128                  * KVM does not emulate SGX activation for simplicity, so
2129                  * allow writes to the LE hash MSRs if IA32_FEATURE_CONTROL
2130                  * is unlocked.  This is technically not architectural
2131                  * behavior, but it's close enough.
2132                  */
2133                 if (!msr_info->host_initiated &&
2134                     (!guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC) ||
2135                     ((vmx->msr_ia32_feature_control & FEAT_CTL_LOCKED) &&
2136                     !(vmx->msr_ia32_feature_control & FEAT_CTL_SGX_LC_ENABLED))))
2137                         return 1;
2138                 vmx->msr_ia32_sgxlepubkeyhash
2139                         [msr_index - MSR_IA32_SGXLEPUBKEYHASH0] = data;
2140                 break;
2141         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2142                 if (!msr_info->host_initiated)
2143                         return 1; /* they are read-only */
2144                 if (!nested_vmx_allowed(vcpu))
2145                         return 1;
2146                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2147         case MSR_IA32_RTIT_CTL:
2148                 if (!vmx_pt_mode_is_host_guest() ||
2149                         vmx_rtit_ctl_check(vcpu, data) ||
2150                         vmx->nested.vmxon)
2151                         return 1;
2152                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2153                 vmx->pt_desc.guest.ctl = data;
2154                 pt_update_intercept_for_msr(vcpu);
2155                 break;
2156         case MSR_IA32_RTIT_STATUS:
2157                 if (!pt_can_write_msr(vmx))
2158                         return 1;
2159                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2160                         return 1;
2161                 vmx->pt_desc.guest.status = data;
2162                 break;
2163         case MSR_IA32_RTIT_CR3_MATCH:
2164                 if (!pt_can_write_msr(vmx))
2165                         return 1;
2166                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2167                                            PT_CAP_cr3_filtering))
2168                         return 1;
2169                 vmx->pt_desc.guest.cr3_match = data;
2170                 break;
2171         case MSR_IA32_RTIT_OUTPUT_BASE:
2172                 if (!pt_can_write_msr(vmx))
2173                         return 1;
2174                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2175                                            PT_CAP_topa_output) &&
2176                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2177                                            PT_CAP_single_range_output))
2178                         return 1;
2179                 if (!pt_output_base_valid(vcpu, data))
2180                         return 1;
2181                 vmx->pt_desc.guest.output_base = data;
2182                 break;
2183         case MSR_IA32_RTIT_OUTPUT_MASK:
2184                 if (!pt_can_write_msr(vmx))
2185                         return 1;
2186                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2187                                            PT_CAP_topa_output) &&
2188                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2189                                            PT_CAP_single_range_output))
2190                         return 1;
2191                 vmx->pt_desc.guest.output_mask = data;
2192                 break;
2193         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2194                 if (!pt_can_write_msr(vmx))
2195                         return 1;
2196                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2197                 if (index >= 2 * vmx->pt_desc.num_address_ranges)
2198                         return 1;
2199                 if (is_noncanonical_address(data, vcpu))
2200                         return 1;
2201                 if (index % 2)
2202                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2203                 else
2204                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2205                 break;
2206         case MSR_IA32_PERF_CAPABILITIES:
2207                 if (data && !vcpu_to_pmu(vcpu)->version)
2208                         return 1;
2209                 if (data & PMU_CAP_LBR_FMT) {
2210                         if ((data & PMU_CAP_LBR_FMT) !=
2211                             (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
2212                                 return 1;
2213                         if (!intel_pmu_lbr_is_compatible(vcpu))
2214                                 return 1;
2215                 }
2216                 ret = kvm_set_msr_common(vcpu, msr_info);
2217                 break;
2218
2219         default:
2220         find_uret_msr:
2221                 msr = vmx_find_uret_msr(vmx, msr_index);
2222                 if (msr)
2223                         ret = vmx_set_guest_uret_msr(vmx, msr, data);
2224                 else
2225                         ret = kvm_set_msr_common(vcpu, msr_info);
2226         }
2227
2228         return ret;
2229 }
2230
2231 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2232 {
2233         unsigned long guest_owned_bits;
2234
2235         kvm_register_mark_available(vcpu, reg);
2236
2237         switch (reg) {
2238         case VCPU_REGS_RSP:
2239                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2240                 break;
2241         case VCPU_REGS_RIP:
2242                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2243                 break;
2244         case VCPU_EXREG_PDPTR:
2245                 if (enable_ept)
2246                         ept_save_pdptrs(vcpu);
2247                 break;
2248         case VCPU_EXREG_CR0:
2249                 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2250
2251                 vcpu->arch.cr0 &= ~guest_owned_bits;
2252                 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2253                 break;
2254         case VCPU_EXREG_CR3:
2255                 /*
2256                  * When intercepting CR3 loads, e.g. for shadowing paging, KVM's
2257                  * CR3 is loaded into hardware, not the guest's CR3.
2258                  */
2259                 if (!(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_CR3_LOAD_EXITING))
2260                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2261                 break;
2262         case VCPU_EXREG_CR4:
2263                 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2264
2265                 vcpu->arch.cr4 &= ~guest_owned_bits;
2266                 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2267                 break;
2268         default:
2269                 KVM_BUG_ON(1, vcpu->kvm);
2270                 break;
2271         }
2272 }
2273
2274 static __init int cpu_has_kvm_support(void)
2275 {
2276         return cpu_has_vmx();
2277 }
2278
2279 static __init int vmx_disabled_by_bios(void)
2280 {
2281         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2282                !boot_cpu_has(X86_FEATURE_VMX);
2283 }
2284
2285 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2286 {
2287         u64 msr;
2288
2289         cr4_set_bits(X86_CR4_VMXE);
2290
2291         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2292                           _ASM_EXTABLE(1b, %l[fault])
2293                           : : [vmxon_pointer] "m"(vmxon_pointer)
2294                           : : fault);
2295         return 0;
2296
2297 fault:
2298         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2299                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2300         cr4_clear_bits(X86_CR4_VMXE);
2301
2302         return -EFAULT;
2303 }
2304
2305 static int hardware_enable(void)
2306 {
2307         int cpu = raw_smp_processor_id();
2308         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2309         int r;
2310
2311         if (cr4_read_shadow() & X86_CR4_VMXE)
2312                 return -EBUSY;
2313
2314         /*
2315          * This can happen if we hot-added a CPU but failed to allocate
2316          * VP assist page for it.
2317          */
2318         if (static_branch_unlikely(&enable_evmcs) &&
2319             !hv_get_vp_assist_page(cpu))
2320                 return -EFAULT;
2321
2322         intel_pt_handle_vmx(1);
2323
2324         r = kvm_cpu_vmxon(phys_addr);
2325         if (r) {
2326                 intel_pt_handle_vmx(0);
2327                 return r;
2328         }
2329
2330         if (enable_ept)
2331                 ept_sync_global();
2332
2333         return 0;
2334 }
2335
2336 static void vmclear_local_loaded_vmcss(void)
2337 {
2338         int cpu = raw_smp_processor_id();
2339         struct loaded_vmcs *v, *n;
2340
2341         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2342                                  loaded_vmcss_on_cpu_link)
2343                 __loaded_vmcs_clear(v);
2344 }
2345
2346 static void hardware_disable(void)
2347 {
2348         vmclear_local_loaded_vmcss();
2349
2350         if (cpu_vmxoff())
2351                 kvm_spurious_fault();
2352
2353         intel_pt_handle_vmx(0);
2354 }
2355
2356 /*
2357  * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2358  * directly instead of going through cpu_has(), to ensure KVM is trapping
2359  * ENCLS whenever it's supported in hardware.  It does not matter whether
2360  * the host OS supports or has enabled SGX.
2361  */
2362 static bool cpu_has_sgx(void)
2363 {
2364         return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2365 }
2366
2367 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2368                                       u32 msr, u32 *result)
2369 {
2370         u32 vmx_msr_low, vmx_msr_high;
2371         u32 ctl = ctl_min | ctl_opt;
2372
2373         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2374
2375         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2376         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2377
2378         /* Ensure minimum (required) set of control bits are supported. */
2379         if (ctl_min & ~ctl)
2380                 return -EIO;
2381
2382         *result = ctl;
2383         return 0;
2384 }
2385
2386 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2387                                     struct vmx_capability *vmx_cap)
2388 {
2389         u32 vmx_msr_low, vmx_msr_high;
2390         u32 min, opt, min2, opt2;
2391         u32 _pin_based_exec_control = 0;
2392         u32 _cpu_based_exec_control = 0;
2393         u32 _cpu_based_2nd_exec_control = 0;
2394         u32 _vmexit_control = 0;
2395         u32 _vmentry_control = 0;
2396
2397         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2398         min = CPU_BASED_HLT_EXITING |
2399 #ifdef CONFIG_X86_64
2400               CPU_BASED_CR8_LOAD_EXITING |
2401               CPU_BASED_CR8_STORE_EXITING |
2402 #endif
2403               CPU_BASED_CR3_LOAD_EXITING |
2404               CPU_BASED_CR3_STORE_EXITING |
2405               CPU_BASED_UNCOND_IO_EXITING |
2406               CPU_BASED_MOV_DR_EXITING |
2407               CPU_BASED_USE_TSC_OFFSETTING |
2408               CPU_BASED_MWAIT_EXITING |
2409               CPU_BASED_MONITOR_EXITING |
2410               CPU_BASED_INVLPG_EXITING |
2411               CPU_BASED_RDPMC_EXITING;
2412
2413         opt = CPU_BASED_TPR_SHADOW |
2414               CPU_BASED_USE_MSR_BITMAPS |
2415               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2416         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2417                                 &_cpu_based_exec_control) < 0)
2418                 return -EIO;
2419 #ifdef CONFIG_X86_64
2420         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2421                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2422                                            ~CPU_BASED_CR8_STORE_EXITING;
2423 #endif
2424         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2425                 min2 = 0;
2426                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2427                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2428                         SECONDARY_EXEC_WBINVD_EXITING |
2429                         SECONDARY_EXEC_ENABLE_VPID |
2430                         SECONDARY_EXEC_ENABLE_EPT |
2431                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2432                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2433                         SECONDARY_EXEC_DESC |
2434                         SECONDARY_EXEC_ENABLE_RDTSCP |
2435                         SECONDARY_EXEC_ENABLE_INVPCID |
2436                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2437                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2438                         SECONDARY_EXEC_SHADOW_VMCS |
2439                         SECONDARY_EXEC_XSAVES |
2440                         SECONDARY_EXEC_RDSEED_EXITING |
2441                         SECONDARY_EXEC_RDRAND_EXITING |
2442                         SECONDARY_EXEC_ENABLE_PML |
2443                         SECONDARY_EXEC_TSC_SCALING |
2444                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2445                         SECONDARY_EXEC_PT_USE_GPA |
2446                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2447                         SECONDARY_EXEC_ENABLE_VMFUNC |
2448                         SECONDARY_EXEC_BUS_LOCK_DETECTION;
2449                 if (cpu_has_sgx())
2450                         opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2451                 if (adjust_vmx_controls(min2, opt2,
2452                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2453                                         &_cpu_based_2nd_exec_control) < 0)
2454                         return -EIO;
2455         }
2456 #ifndef CONFIG_X86_64
2457         if (!(_cpu_based_2nd_exec_control &
2458                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2459                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2460 #endif
2461
2462         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2463                 _cpu_based_2nd_exec_control &= ~(
2464                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2465                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2466                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2467
2468         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2469                 &vmx_cap->ept, &vmx_cap->vpid);
2470
2471         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2472                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2473                    enabled */
2474                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2475                                              CPU_BASED_CR3_STORE_EXITING |
2476                                              CPU_BASED_INVLPG_EXITING);
2477         } else if (vmx_cap->ept) {
2478                 vmx_cap->ept = 0;
2479                 pr_warn_once("EPT CAP should not exist if not support "
2480                                 "1-setting enable EPT VM-execution control\n");
2481         }
2482         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2483                 vmx_cap->vpid) {
2484                 vmx_cap->vpid = 0;
2485                 pr_warn_once("VPID CAP should not exist if not support "
2486                                 "1-setting enable VPID VM-execution control\n");
2487         }
2488
2489         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2490 #ifdef CONFIG_X86_64
2491         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2492 #endif
2493         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2494               VM_EXIT_LOAD_IA32_PAT |
2495               VM_EXIT_LOAD_IA32_EFER |
2496               VM_EXIT_CLEAR_BNDCFGS |
2497               VM_EXIT_PT_CONCEAL_PIP |
2498               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2499         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2500                                 &_vmexit_control) < 0)
2501                 return -EIO;
2502
2503         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2504         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2505                  PIN_BASED_VMX_PREEMPTION_TIMER;
2506         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2507                                 &_pin_based_exec_control) < 0)
2508                 return -EIO;
2509
2510         if (cpu_has_broken_vmx_preemption_timer())
2511                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2512         if (!(_cpu_based_2nd_exec_control &
2513                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2514                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2515
2516         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2517         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2518               VM_ENTRY_LOAD_IA32_PAT |
2519               VM_ENTRY_LOAD_IA32_EFER |
2520               VM_ENTRY_LOAD_BNDCFGS |
2521               VM_ENTRY_PT_CONCEAL_PIP |
2522               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2523         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2524                                 &_vmentry_control) < 0)
2525                 return -EIO;
2526
2527         /*
2528          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2529          * can't be used due to an errata where VM Exit may incorrectly clear
2530          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2531          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2532          */
2533         if (boot_cpu_data.x86 == 0x6) {
2534                 switch (boot_cpu_data.x86_model) {
2535                 case 26: /* AAK155 */
2536                 case 30: /* AAP115 */
2537                 case 37: /* AAT100 */
2538                 case 44: /* BC86,AAY89,BD102 */
2539                 case 46: /* BA97 */
2540                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2541                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2542                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2543                                         "does not work properly. Using workaround\n");
2544                         break;
2545                 default:
2546                         break;
2547                 }
2548         }
2549
2550
2551         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2552
2553         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2554         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2555                 return -EIO;
2556
2557 #ifdef CONFIG_X86_64
2558         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2559         if (vmx_msr_high & (1u<<16))
2560                 return -EIO;
2561 #endif
2562
2563         /* Require Write-Back (WB) memory type for VMCS accesses. */
2564         if (((vmx_msr_high >> 18) & 15) != 6)
2565                 return -EIO;
2566
2567         vmcs_conf->size = vmx_msr_high & 0x1fff;
2568         vmcs_conf->order = get_order(vmcs_conf->size);
2569         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2570
2571         vmcs_conf->revision_id = vmx_msr_low;
2572
2573         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2574         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2575         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2576         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2577         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2578
2579 #if IS_ENABLED(CONFIG_HYPERV)
2580         if (enlightened_vmcs)
2581                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2582 #endif
2583
2584         return 0;
2585 }
2586
2587 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2588 {
2589         int node = cpu_to_node(cpu);
2590         struct page *pages;
2591         struct vmcs *vmcs;
2592
2593         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2594         if (!pages)
2595                 return NULL;
2596         vmcs = page_address(pages);
2597         memset(vmcs, 0, vmcs_config.size);
2598
2599         /* KVM supports Enlightened VMCS v1 only */
2600         if (static_branch_unlikely(&enable_evmcs))
2601                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2602         else
2603                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2604
2605         if (shadow)
2606                 vmcs->hdr.shadow_vmcs = 1;
2607         return vmcs;
2608 }
2609
2610 void free_vmcs(struct vmcs *vmcs)
2611 {
2612         free_pages((unsigned long)vmcs, vmcs_config.order);
2613 }
2614
2615 /*
2616  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2617  */
2618 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2619 {
2620         if (!loaded_vmcs->vmcs)
2621                 return;
2622         loaded_vmcs_clear(loaded_vmcs);
2623         free_vmcs(loaded_vmcs->vmcs);
2624         loaded_vmcs->vmcs = NULL;
2625         if (loaded_vmcs->msr_bitmap)
2626                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2627         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2628 }
2629
2630 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2631 {
2632         loaded_vmcs->vmcs = alloc_vmcs(false);
2633         if (!loaded_vmcs->vmcs)
2634                 return -ENOMEM;
2635
2636         vmcs_clear(loaded_vmcs->vmcs);
2637
2638         loaded_vmcs->shadow_vmcs = NULL;
2639         loaded_vmcs->hv_timer_soft_disabled = false;
2640         loaded_vmcs->cpu = -1;
2641         loaded_vmcs->launched = 0;
2642
2643         if (cpu_has_vmx_msr_bitmap()) {
2644                 loaded_vmcs->msr_bitmap = (unsigned long *)
2645                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2646                 if (!loaded_vmcs->msr_bitmap)
2647                         goto out_vmcs;
2648                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2649
2650                 if (IS_ENABLED(CONFIG_HYPERV) &&
2651                     static_branch_unlikely(&enable_evmcs) &&
2652                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2653                         struct hv_enlightened_vmcs *evmcs =
2654                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2655
2656                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2657                 }
2658         }
2659
2660         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2661         memset(&loaded_vmcs->controls_shadow, 0,
2662                 sizeof(struct vmcs_controls_shadow));
2663
2664         return 0;
2665
2666 out_vmcs:
2667         free_loaded_vmcs(loaded_vmcs);
2668         return -ENOMEM;
2669 }
2670
2671 static void free_kvm_area(void)
2672 {
2673         int cpu;
2674
2675         for_each_possible_cpu(cpu) {
2676                 free_vmcs(per_cpu(vmxarea, cpu));
2677                 per_cpu(vmxarea, cpu) = NULL;
2678         }
2679 }
2680
2681 static __init int alloc_kvm_area(void)
2682 {
2683         int cpu;
2684
2685         for_each_possible_cpu(cpu) {
2686                 struct vmcs *vmcs;
2687
2688                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2689                 if (!vmcs) {
2690                         free_kvm_area();
2691                         return -ENOMEM;
2692                 }
2693
2694                 /*
2695                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2696                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2697                  * revision_id reported by MSR_IA32_VMX_BASIC.
2698                  *
2699                  * However, even though not explicitly documented by
2700                  * TLFS, VMXArea passed as VMXON argument should
2701                  * still be marked with revision_id reported by
2702                  * physical CPU.
2703                  */
2704                 if (static_branch_unlikely(&enable_evmcs))
2705                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2706
2707                 per_cpu(vmxarea, cpu) = vmcs;
2708         }
2709         return 0;
2710 }
2711
2712 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2713                 struct kvm_segment *save)
2714 {
2715         if (!emulate_invalid_guest_state) {
2716                 /*
2717                  * CS and SS RPL should be equal during guest entry according
2718                  * to VMX spec, but in reality it is not always so. Since vcpu
2719                  * is in the middle of the transition from real mode to
2720                  * protected mode it is safe to assume that RPL 0 is a good
2721                  * default value.
2722                  */
2723                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2724                         save->selector &= ~SEGMENT_RPL_MASK;
2725                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2726                 save->s = 1;
2727         }
2728         __vmx_set_segment(vcpu, save, seg);
2729 }
2730
2731 static void enter_pmode(struct kvm_vcpu *vcpu)
2732 {
2733         unsigned long flags;
2734         struct vcpu_vmx *vmx = to_vmx(vcpu);
2735
2736         /*
2737          * Update real mode segment cache. It may be not up-to-date if segment
2738          * register was written while vcpu was in a guest mode.
2739          */
2740         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2741         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2742         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2743         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2744         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2745         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2746
2747         vmx->rmode.vm86_active = 0;
2748
2749         __vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2750
2751         flags = vmcs_readl(GUEST_RFLAGS);
2752         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2753         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2754         vmcs_writel(GUEST_RFLAGS, flags);
2755
2756         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2757                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2758
2759         vmx_update_exception_bitmap(vcpu);
2760
2761         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2762         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2763         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2764         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2765         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2766         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2767 }
2768
2769 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2770 {
2771         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2772         struct kvm_segment var = *save;
2773
2774         var.dpl = 0x3;
2775         if (seg == VCPU_SREG_CS)
2776                 var.type = 0x3;
2777
2778         if (!emulate_invalid_guest_state) {
2779                 var.selector = var.base >> 4;
2780                 var.base = var.base & 0xffff0;
2781                 var.limit = 0xffff;
2782                 var.g = 0;
2783                 var.db = 0;
2784                 var.present = 1;
2785                 var.s = 1;
2786                 var.l = 0;
2787                 var.unusable = 0;
2788                 var.type = 0x3;
2789                 var.avl = 0;
2790                 if (save->base & 0xf)
2791                         printk_once(KERN_WARNING "kvm: segment base is not "
2792                                         "paragraph aligned when entering "
2793                                         "protected mode (seg=%d)", seg);
2794         }
2795
2796         vmcs_write16(sf->selector, var.selector);
2797         vmcs_writel(sf->base, var.base);
2798         vmcs_write32(sf->limit, var.limit);
2799         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2800 }
2801
2802 static void enter_rmode(struct kvm_vcpu *vcpu)
2803 {
2804         unsigned long flags;
2805         struct vcpu_vmx *vmx = to_vmx(vcpu);
2806         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2807
2808         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2809         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2810         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2811         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2812         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2813         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2814         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2815
2816         vmx->rmode.vm86_active = 1;
2817
2818         /*
2819          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2820          * vcpu. Warn the user that an update is overdue.
2821          */
2822         if (!kvm_vmx->tss_addr)
2823                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2824                              "called before entering vcpu\n");
2825
2826         vmx_segment_cache_clear(vmx);
2827
2828         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2829         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2830         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2831
2832         flags = vmcs_readl(GUEST_RFLAGS);
2833         vmx->rmode.save_rflags = flags;
2834
2835         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2836
2837         vmcs_writel(GUEST_RFLAGS, flags);
2838         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2839         vmx_update_exception_bitmap(vcpu);
2840
2841         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2842         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2843         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2844         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2845         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2846         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2847 }
2848
2849 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2850 {
2851         struct vcpu_vmx *vmx = to_vmx(vcpu);
2852         struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER);
2853
2854         /* Nothing to do if hardware doesn't support EFER. */
2855         if (!msr)
2856                 return 0;
2857
2858         vcpu->arch.efer = efer;
2859         if (efer & EFER_LMA) {
2860                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2861                 msr->data = efer;
2862         } else {
2863                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2864
2865                 msr->data = efer & ~EFER_LME;
2866         }
2867         vmx_setup_uret_msrs(vmx);
2868         return 0;
2869 }
2870
2871 #ifdef CONFIG_X86_64
2872
2873 static void enter_lmode(struct kvm_vcpu *vcpu)
2874 {
2875         u32 guest_tr_ar;
2876
2877         vmx_segment_cache_clear(to_vmx(vcpu));
2878
2879         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2880         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2881                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2882                                      __func__);
2883                 vmcs_write32(GUEST_TR_AR_BYTES,
2884                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2885                              | VMX_AR_TYPE_BUSY_64_TSS);
2886         }
2887         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2888 }
2889
2890 static void exit_lmode(struct kvm_vcpu *vcpu)
2891 {
2892         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2893         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2894 }
2895
2896 #endif
2897
2898 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2899 {
2900         struct vcpu_vmx *vmx = to_vmx(vcpu);
2901
2902         /*
2903          * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2904          * the CPU is not required to invalidate guest-physical mappings on
2905          * VM-Entry, even if VPID is disabled.  Guest-physical mappings are
2906          * associated with the root EPT structure and not any particular VPID
2907          * (INVVPID also isn't required to invalidate guest-physical mappings).
2908          */
2909         if (enable_ept) {
2910                 ept_sync_global();
2911         } else if (enable_vpid) {
2912                 if (cpu_has_vmx_invvpid_global()) {
2913                         vpid_sync_vcpu_global();
2914                 } else {
2915                         vpid_sync_vcpu_single(vmx->vpid);
2916                         vpid_sync_vcpu_single(vmx->nested.vpid02);
2917                 }
2918         }
2919 }
2920
2921 static inline int vmx_get_current_vpid(struct kvm_vcpu *vcpu)
2922 {
2923         if (is_guest_mode(vcpu))
2924                 return nested_get_vpid02(vcpu);
2925         return to_vmx(vcpu)->vpid;
2926 }
2927
2928 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2929 {
2930         struct kvm_mmu *mmu = vcpu->arch.mmu;
2931         u64 root_hpa = mmu->root_hpa;
2932
2933         /* No flush required if the current context is invalid. */
2934         if (!VALID_PAGE(root_hpa))
2935                 return;
2936
2937         if (enable_ept)
2938                 ept_sync_context(construct_eptp(vcpu, root_hpa,
2939                                                 mmu->shadow_root_level));
2940         else
2941                 vpid_sync_context(vmx_get_current_vpid(vcpu));
2942 }
2943
2944 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2945 {
2946         /*
2947          * vpid_sync_vcpu_addr() is a nop if vpid==0, see the comment in
2948          * vmx_flush_tlb_guest() for an explanation of why this is ok.
2949          */
2950         vpid_sync_vcpu_addr(vmx_get_current_vpid(vcpu), addr);
2951 }
2952
2953 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2954 {
2955         /*
2956          * vpid_sync_context() is a nop if vpid==0, e.g. if enable_vpid==0 or a
2957          * vpid couldn't be allocated for this vCPU.  VM-Enter and VM-Exit are
2958          * required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2959          * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2960          * i.e. no explicit INVVPID is necessary.
2961          */
2962         vpid_sync_context(vmx_get_current_vpid(vcpu));
2963 }
2964
2965 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2966 {
2967         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2968
2969         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2970                 return;
2971
2972         if (is_pae_paging(vcpu)) {
2973                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2974                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2975                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2976                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2977         }
2978 }
2979
2980 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2981 {
2982         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2983
2984         if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2985                 return;
2986
2987         mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2988         mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2989         mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2990         mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2991
2992         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2993 }
2994
2995 #define CR3_EXITING_BITS (CPU_BASED_CR3_LOAD_EXITING | \
2996                           CPU_BASED_CR3_STORE_EXITING)
2997
2998 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2999 {
3000         struct vcpu_vmx *vmx = to_vmx(vcpu);
3001         unsigned long hw_cr0, old_cr0_pg;
3002         u32 tmp;
3003
3004         old_cr0_pg = kvm_read_cr0_bits(vcpu, X86_CR0_PG);
3005
3006         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3007         if (is_unrestricted_guest(vcpu))
3008                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3009         else {
3010                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3011                 if (!enable_ept)
3012                         hw_cr0 |= X86_CR0_WP;
3013
3014                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3015                         enter_pmode(vcpu);
3016
3017                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3018                         enter_rmode(vcpu);
3019         }
3020
3021         vmcs_writel(CR0_READ_SHADOW, cr0);
3022         vmcs_writel(GUEST_CR0, hw_cr0);
3023         vcpu->arch.cr0 = cr0;
3024         kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3025
3026 #ifdef CONFIG_X86_64
3027         if (vcpu->arch.efer & EFER_LME) {
3028                 if (!old_cr0_pg && (cr0 & X86_CR0_PG))
3029                         enter_lmode(vcpu);
3030                 else if (old_cr0_pg && !(cr0 & X86_CR0_PG))
3031                         exit_lmode(vcpu);
3032         }
3033 #endif
3034
3035         if (enable_ept && !is_unrestricted_guest(vcpu)) {
3036                 /*
3037                  * Ensure KVM has an up-to-date snapshot of the guest's CR3.  If
3038                  * the below code _enables_ CR3 exiting, vmx_cache_reg() will
3039                  * (correctly) stop reading vmcs.GUEST_CR3 because it thinks
3040                  * KVM's CR3 is installed.
3041                  */
3042                 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
3043                         vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
3044
3045                 /*
3046                  * When running with EPT but not unrestricted guest, KVM must
3047                  * intercept CR3 accesses when paging is _disabled_.  This is
3048                  * necessary because restricted guests can't actually run with
3049                  * paging disabled, and so KVM stuffs its own CR3 in order to
3050                  * run the guest when identity mapped page tables.
3051                  *
3052                  * Do _NOT_ check the old CR0.PG, e.g. to optimize away the
3053                  * update, it may be stale with respect to CR3 interception,
3054                  * e.g. after nested VM-Enter.
3055                  *
3056                  * Lastly, honor L1's desires, i.e. intercept CR3 loads and/or
3057                  * stores to forward them to L1, even if KVM does not need to
3058                  * intercept them to preserve its identity mapped page tables.
3059                  */
3060                 if (!(cr0 & X86_CR0_PG)) {
3061                         exec_controls_setbit(vmx, CR3_EXITING_BITS);
3062                 } else if (!is_guest_mode(vcpu)) {
3063                         exec_controls_clearbit(vmx, CR3_EXITING_BITS);
3064                 } else {
3065                         tmp = exec_controls_get(vmx);
3066                         tmp &= ~CR3_EXITING_BITS;
3067                         tmp |= get_vmcs12(vcpu)->cpu_based_vm_exec_control & CR3_EXITING_BITS;
3068                         exec_controls_set(vmx, tmp);
3069                 }
3070
3071                 /* Note, vmx_set_cr4() consumes the new vcpu->arch.cr0. */
3072                 if ((old_cr0_pg ^ cr0) & X86_CR0_PG)
3073                         vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3074         }
3075
3076         /* depends on vcpu->arch.cr0 to be set to a new value */
3077         vmx->emulation_required = vmx_emulation_required(vcpu);
3078 }
3079
3080 static int vmx_get_max_tdp_level(void)
3081 {
3082         if (cpu_has_vmx_ept_5levels())
3083                 return 5;
3084         return 4;
3085 }
3086
3087 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level)
3088 {
3089         u64 eptp = VMX_EPTP_MT_WB;
3090
3091         eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3092
3093         if (enable_ept_ad_bits &&
3094             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3095                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3096         eptp |= root_hpa;
3097
3098         return eptp;
3099 }
3100
3101 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3102                              int root_level)
3103 {
3104         struct kvm *kvm = vcpu->kvm;
3105         bool update_guest_cr3 = true;
3106         unsigned long guest_cr3;
3107         u64 eptp;
3108
3109         if (enable_ept) {
3110                 eptp = construct_eptp(vcpu, root_hpa, root_level);
3111                 vmcs_write64(EPT_POINTER, eptp);
3112
3113                 hv_track_root_tdp(vcpu, root_hpa);
3114
3115                 if (!enable_unrestricted_guest && !is_paging(vcpu))
3116                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3117                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3118                         guest_cr3 = vcpu->arch.cr3;
3119                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3120                         update_guest_cr3 = false;
3121                 vmx_ept_load_pdptrs(vcpu);
3122         } else {
3123                 guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu);
3124         }
3125
3126         if (update_guest_cr3)
3127                 vmcs_writel(GUEST_CR3, guest_cr3);
3128 }
3129
3130 static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3131 {
3132         /*
3133          * We operate under the default treatment of SMM, so VMX cannot be
3134          * enabled under SMM.  Note, whether or not VMXE is allowed at all is
3135          * handled by kvm_is_valid_cr4().
3136          */
3137         if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu))
3138                 return false;
3139
3140         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3141                 return false;
3142
3143         return true;
3144 }
3145
3146 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3147 {
3148         unsigned long old_cr4 = vcpu->arch.cr4;
3149         struct vcpu_vmx *vmx = to_vmx(vcpu);
3150         /*
3151          * Pass through host's Machine Check Enable value to hw_cr4, which
3152          * is in force while we are in guest mode.  Do not let guests control
3153          * this bit, even if host CR4.MCE == 0.
3154          */
3155         unsigned long hw_cr4;
3156
3157         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3158         if (is_unrestricted_guest(vcpu))
3159                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3160         else if (vmx->rmode.vm86_active)
3161                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3162         else
3163                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3164
3165         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3166                 if (cr4 & X86_CR4_UMIP) {
3167                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3168                         hw_cr4 &= ~X86_CR4_UMIP;
3169                 } else if (!is_guest_mode(vcpu) ||
3170                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3171                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3172                 }
3173         }
3174
3175         vcpu->arch.cr4 = cr4;
3176         kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3177
3178         if (!is_unrestricted_guest(vcpu)) {
3179                 if (enable_ept) {
3180                         if (!is_paging(vcpu)) {
3181                                 hw_cr4 &= ~X86_CR4_PAE;
3182                                 hw_cr4 |= X86_CR4_PSE;
3183                         } else if (!(cr4 & X86_CR4_PAE)) {
3184                                 hw_cr4 &= ~X86_CR4_PAE;
3185                         }
3186                 }
3187
3188                 /*
3189                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3190                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3191                  * to be manually disabled when guest switches to non-paging
3192                  * mode.
3193                  *
3194                  * If !enable_unrestricted_guest, the CPU is always running
3195                  * with CR0.PG=1 and CR4 needs to be modified.
3196                  * If enable_unrestricted_guest, the CPU automatically
3197                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3198                  */
3199                 if (!is_paging(vcpu))
3200                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3201         }
3202
3203         vmcs_writel(CR4_READ_SHADOW, cr4);
3204         vmcs_writel(GUEST_CR4, hw_cr4);
3205
3206         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
3207                 kvm_update_cpuid_runtime(vcpu);
3208 }
3209
3210 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3211 {
3212         struct vcpu_vmx *vmx = to_vmx(vcpu);
3213         u32 ar;
3214
3215         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3216                 *var = vmx->rmode.segs[seg];
3217                 if (seg == VCPU_SREG_TR
3218                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3219                         return;
3220                 var->base = vmx_read_guest_seg_base(vmx, seg);
3221                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3222                 return;
3223         }
3224         var->base = vmx_read_guest_seg_base(vmx, seg);
3225         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3226         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3227         ar = vmx_read_guest_seg_ar(vmx, seg);
3228         var->unusable = (ar >> 16) & 1;
3229         var->type = ar & 15;
3230         var->s = (ar >> 4) & 1;
3231         var->dpl = (ar >> 5) & 3;
3232         /*
3233          * Some userspaces do not preserve unusable property. Since usable
3234          * segment has to be present according to VMX spec we can use present
3235          * property to amend userspace bug by making unusable segment always
3236          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3237          * segment as unusable.
3238          */
3239         var->present = !var->unusable;
3240         var->avl = (ar >> 12) & 1;
3241         var->l = (ar >> 13) & 1;
3242         var->db = (ar >> 14) & 1;
3243         var->g = (ar >> 15) & 1;
3244 }
3245
3246 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3247 {
3248         struct kvm_segment s;
3249
3250         if (to_vmx(vcpu)->rmode.vm86_active) {
3251                 vmx_get_segment(vcpu, &s, seg);
3252                 return s.base;
3253         }
3254         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3255 }
3256
3257 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3258 {
3259         struct vcpu_vmx *vmx = to_vmx(vcpu);
3260
3261         if (unlikely(vmx->rmode.vm86_active))
3262                 return 0;
3263         else {
3264                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3265                 return VMX_AR_DPL(ar);
3266         }
3267 }
3268
3269 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3270 {
3271         u32 ar;
3272
3273         if (var->unusable || !var->present)
3274                 ar = 1 << 16;
3275         else {
3276                 ar = var->type & 15;
3277                 ar |= (var->s & 1) << 4;
3278                 ar |= (var->dpl & 3) << 5;
3279                 ar |= (var->present & 1) << 7;
3280                 ar |= (var->avl & 1) << 12;
3281                 ar |= (var->l & 1) << 13;
3282                 ar |= (var->db & 1) << 14;
3283                 ar |= (var->g & 1) << 15;
3284         }
3285
3286         return ar;
3287 }
3288
3289 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3290 {
3291         struct vcpu_vmx *vmx = to_vmx(vcpu);
3292         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3293
3294         vmx_segment_cache_clear(vmx);
3295
3296         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3297                 vmx->rmode.segs[seg] = *var;
3298                 if (seg == VCPU_SREG_TR)
3299                         vmcs_write16(sf->selector, var->selector);
3300                 else if (var->s)
3301                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3302                 return;
3303         }
3304
3305         vmcs_writel(sf->base, var->base);
3306         vmcs_write32(sf->limit, var->limit);
3307         vmcs_write16(sf->selector, var->selector);
3308
3309         /*
3310          *   Fix the "Accessed" bit in AR field of segment registers for older
3311          * qemu binaries.
3312          *   IA32 arch specifies that at the time of processor reset the
3313          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3314          * is setting it to 0 in the userland code. This causes invalid guest
3315          * state vmexit when "unrestricted guest" mode is turned on.
3316          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3317          * tree. Newer qemu binaries with that qemu fix would not need this
3318          * kvm hack.
3319          */
3320         if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3321                 var->type |= 0x1; /* Accessed */
3322
3323         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3324 }
3325
3326 static void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3327 {
3328         __vmx_set_segment(vcpu, var, seg);
3329
3330         to_vmx(vcpu)->emulation_required = vmx_emulation_required(vcpu);
3331 }
3332
3333 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3334 {
3335         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3336
3337         *db = (ar >> 14) & 1;
3338         *l = (ar >> 13) & 1;
3339 }
3340
3341 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3342 {
3343         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3344         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3345 }
3346
3347 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3348 {
3349         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3350         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3351 }
3352
3353 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3354 {
3355         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3356         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3357 }
3358
3359 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3360 {
3361         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3362         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3363 }
3364
3365 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3366 {
3367         struct kvm_segment var;
3368         u32 ar;
3369
3370         vmx_get_segment(vcpu, &var, seg);
3371         var.dpl = 0x3;
3372         if (seg == VCPU_SREG_CS)
3373                 var.type = 0x3;
3374         ar = vmx_segment_access_rights(&var);
3375
3376         if (var.base != (var.selector << 4))
3377                 return false;
3378         if (var.limit != 0xffff)
3379                 return false;
3380         if (ar != 0xf3)
3381                 return false;
3382
3383         return true;
3384 }
3385
3386 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3387 {
3388         struct kvm_segment cs;
3389         unsigned int cs_rpl;
3390
3391         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3392         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3393
3394         if (cs.unusable)
3395                 return false;
3396         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3397                 return false;
3398         if (!cs.s)
3399                 return false;
3400         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3401                 if (cs.dpl > cs_rpl)
3402                         return false;
3403         } else {
3404                 if (cs.dpl != cs_rpl)
3405                         return false;
3406         }
3407         if (!cs.present)
3408                 return false;
3409
3410         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3411         return true;
3412 }
3413
3414 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3415 {
3416         struct kvm_segment ss;
3417         unsigned int ss_rpl;
3418
3419         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3420         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3421
3422         if (ss.unusable)
3423                 return true;
3424         if (ss.type != 3 && ss.type != 7)
3425                 return false;
3426         if (!ss.s)
3427                 return false;
3428         if (ss.dpl != ss_rpl) /* DPL != RPL */
3429                 return false;
3430         if (!ss.present)
3431                 return false;
3432
3433         return true;
3434 }
3435
3436 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3437 {
3438         struct kvm_segment var;
3439         unsigned int rpl;
3440
3441         vmx_get_segment(vcpu, &var, seg);
3442         rpl = var.selector & SEGMENT_RPL_MASK;
3443
3444         if (var.unusable)
3445                 return true;
3446         if (!var.s)
3447                 return false;
3448         if (!var.present)
3449                 return false;
3450         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3451                 if (var.dpl < rpl) /* DPL < RPL */
3452                         return false;
3453         }
3454
3455         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3456          * rights flags
3457          */
3458         return true;
3459 }
3460
3461 static bool tr_valid(struct kvm_vcpu *vcpu)
3462 {
3463         struct kvm_segment tr;
3464
3465         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3466
3467         if (tr.unusable)
3468                 return false;
3469         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3470                 return false;
3471         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3472                 return false;
3473         if (!tr.present)
3474                 return false;
3475
3476         return true;
3477 }
3478
3479 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3480 {
3481         struct kvm_segment ldtr;
3482
3483         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3484
3485         if (ldtr.unusable)
3486                 return true;
3487         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3488                 return false;
3489         if (ldtr.type != 2)
3490                 return false;
3491         if (!ldtr.present)
3492                 return false;
3493
3494         return true;
3495 }
3496
3497 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3498 {
3499         struct kvm_segment cs, ss;
3500
3501         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3502         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3503
3504         return ((cs.selector & SEGMENT_RPL_MASK) ==
3505                  (ss.selector & SEGMENT_RPL_MASK));
3506 }
3507
3508 /*
3509  * Check if guest state is valid. Returns true if valid, false if
3510  * not.
3511  * We assume that registers are always usable
3512  */
3513 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu)
3514 {
3515         /* real mode guest state checks */
3516         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3517                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3518                         return false;
3519                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3520                         return false;
3521                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3522                         return false;
3523                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3524                         return false;
3525                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3526                         return false;
3527                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3528                         return false;
3529         } else {
3530         /* protected mode guest state checks */
3531                 if (!cs_ss_rpl_check(vcpu))
3532                         return false;
3533                 if (!code_segment_valid(vcpu))
3534                         return false;
3535                 if (!stack_segment_valid(vcpu))
3536                         return false;
3537                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3538                         return false;
3539                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3540                         return false;
3541                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3542                         return false;
3543                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3544                         return false;
3545                 if (!tr_valid(vcpu))
3546                         return false;
3547                 if (!ldtr_valid(vcpu))
3548                         return false;
3549         }
3550         /* TODO:
3551          * - Add checks on RIP
3552          * - Add checks on RFLAGS
3553          */
3554
3555         return true;
3556 }
3557
3558 static int init_rmode_tss(struct kvm *kvm, void __user *ua)
3559 {
3560         const void *zero_page = (const void *) __va(page_to_phys(ZERO_PAGE(0)));
3561         u16 data;
3562         int i;
3563
3564         for (i = 0; i < 3; i++) {
3565                 if (__copy_to_user(ua + PAGE_SIZE * i, zero_page, PAGE_SIZE))
3566                         return -EFAULT;
3567         }
3568
3569         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3570         if (__copy_to_user(ua + TSS_IOPB_BASE_OFFSET, &data, sizeof(u16)))
3571                 return -EFAULT;
3572
3573         data = ~0;
3574         if (__copy_to_user(ua + RMODE_TSS_SIZE - 1, &data, sizeof(u8)))
3575                 return -EFAULT;
3576
3577         return 0;
3578 }
3579
3580 static int init_rmode_identity_map(struct kvm *kvm)
3581 {
3582         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3583         int i, r = 0;
3584         void __user *uaddr;
3585         u32 tmp;
3586
3587         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3588         mutex_lock(&kvm->slots_lock);
3589
3590         if (likely(kvm_vmx->ept_identity_pagetable_done))
3591                 goto out;
3592
3593         if (!kvm_vmx->ept_identity_map_addr)
3594                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3595
3596         uaddr = __x86_set_memory_region(kvm,
3597                                         IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3598                                         kvm_vmx->ept_identity_map_addr,
3599                                         PAGE_SIZE);
3600         if (IS_ERR(uaddr)) {
3601                 r = PTR_ERR(uaddr);
3602                 goto out;
3603         }
3604
3605         /* Set up identity-mapping pagetable for EPT in real mode */
3606         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3607                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3608                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3609                 if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) {
3610                         r = -EFAULT;
3611                         goto out;
3612                 }
3613         }
3614         kvm_vmx->ept_identity_pagetable_done = true;
3615
3616 out:
3617         mutex_unlock(&kvm->slots_lock);
3618         return r;
3619 }
3620
3621 static void seg_setup(int seg)
3622 {
3623         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3624         unsigned int ar;
3625
3626         vmcs_write16(sf->selector, 0);
3627         vmcs_writel(sf->base, 0);
3628         vmcs_write32(sf->limit, 0xffff);
3629         ar = 0x93;
3630         if (seg == VCPU_SREG_CS)
3631                 ar |= 0x08; /* code segment */
3632
3633         vmcs_write32(sf->ar_bytes, ar);
3634 }
3635
3636 static int alloc_apic_access_page(struct kvm *kvm)
3637 {
3638         struct page *page;
3639         void __user *hva;
3640         int ret = 0;
3641
3642         mutex_lock(&kvm->slots_lock);
3643         if (kvm->arch.apic_access_memslot_enabled)
3644                 goto out;
3645         hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3646                                       APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3647         if (IS_ERR(hva)) {
3648                 ret = PTR_ERR(hva);
3649                 goto out;
3650         }
3651
3652         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3653         if (is_error_page(page)) {
3654                 ret = -EFAULT;
3655                 goto out;
3656         }
3657
3658         /*
3659          * Do not pin the page in memory, so that memory hot-unplug
3660          * is able to migrate it.
3661          */
3662         put_page(page);
3663         kvm->arch.apic_access_memslot_enabled = true;
3664 out:
3665         mutex_unlock(&kvm->slots_lock);
3666         return ret;
3667 }
3668
3669 int allocate_vpid(void)
3670 {
3671         int vpid;
3672
3673         if (!enable_vpid)
3674                 return 0;
3675         spin_lock(&vmx_vpid_lock);
3676         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3677         if (vpid < VMX_NR_VPIDS)
3678                 __set_bit(vpid, vmx_vpid_bitmap);
3679         else
3680                 vpid = 0;
3681         spin_unlock(&vmx_vpid_lock);
3682         return vpid;
3683 }
3684
3685 void free_vpid(int vpid)
3686 {
3687         if (!enable_vpid || vpid == 0)
3688                 return;
3689         spin_lock(&vmx_vpid_lock);
3690         __clear_bit(vpid, vmx_vpid_bitmap);
3691         spin_unlock(&vmx_vpid_lock);
3692 }
3693
3694 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3695 {
3696         struct vcpu_vmx *vmx = to_vmx(vcpu);
3697         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3698
3699         if (!cpu_has_vmx_msr_bitmap())
3700                 return;
3701
3702         if (static_branch_unlikely(&enable_evmcs))
3703                 evmcs_touch_msr_bitmap();
3704
3705         /*
3706          * Mark the desired intercept state in shadow bitmap, this is needed
3707          * for resync when the MSR filters change.
3708         */
3709         if (is_valid_passthrough_msr(msr)) {
3710                 int idx = possible_passthrough_msr_slot(msr);
3711
3712                 if (idx != -ENOENT) {
3713                         if (type & MSR_TYPE_R)
3714                                 clear_bit(idx, vmx->shadow_msr_intercept.read);
3715                         if (type & MSR_TYPE_W)
3716                                 clear_bit(idx, vmx->shadow_msr_intercept.write);
3717                 }
3718         }
3719
3720         if ((type & MSR_TYPE_R) &&
3721             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) {
3722                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3723                 type &= ~MSR_TYPE_R;
3724         }
3725
3726         if ((type & MSR_TYPE_W) &&
3727             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) {
3728                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3729                 type &= ~MSR_TYPE_W;
3730         }
3731
3732         if (type & MSR_TYPE_R)
3733                 vmx_clear_msr_bitmap_read(msr_bitmap, msr);
3734
3735         if (type & MSR_TYPE_W)
3736                 vmx_clear_msr_bitmap_write(msr_bitmap, msr);
3737 }
3738
3739 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3740 {
3741         struct vcpu_vmx *vmx = to_vmx(vcpu);
3742         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3743
3744         if (!cpu_has_vmx_msr_bitmap())
3745                 return;
3746
3747         if (static_branch_unlikely(&enable_evmcs))
3748                 evmcs_touch_msr_bitmap();
3749
3750         /*
3751          * Mark the desired intercept state in shadow bitmap, this is needed
3752          * for resync when the MSR filter changes.
3753         */
3754         if (is_valid_passthrough_msr(msr)) {
3755                 int idx = possible_passthrough_msr_slot(msr);
3756
3757                 if (idx != -ENOENT) {
3758                         if (type & MSR_TYPE_R)
3759                                 set_bit(idx, vmx->shadow_msr_intercept.read);
3760                         if (type & MSR_TYPE_W)
3761                                 set_bit(idx, vmx->shadow_msr_intercept.write);
3762                 }
3763         }
3764
3765         if (type & MSR_TYPE_R)
3766                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3767
3768         if (type & MSR_TYPE_W)
3769                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3770 }
3771
3772 static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode)
3773 {
3774         unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
3775         unsigned long read_intercept;
3776         int msr;
3777
3778         read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3779
3780         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3781                 unsigned int read_idx = msr / BITS_PER_LONG;
3782                 unsigned int write_idx = read_idx + (0x800 / sizeof(long));
3783
3784                 msr_bitmap[read_idx] = read_intercept;
3785                 msr_bitmap[write_idx] = ~0ul;
3786         }
3787 }
3788
3789 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
3790 {
3791         struct vcpu_vmx *vmx = to_vmx(vcpu);
3792         u8 mode;
3793
3794         if (!cpu_has_vmx_msr_bitmap())
3795                 return;
3796
3797         if (cpu_has_secondary_exec_ctrls() &&
3798             (secondary_exec_controls_get(vmx) &
3799              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3800                 mode = MSR_BITMAP_MODE_X2APIC;
3801                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3802                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3803         } else {
3804                 mode = 0;
3805         }
3806
3807         if (mode == vmx->x2apic_msr_bitmap_mode)
3808                 return;
3809
3810         vmx->x2apic_msr_bitmap_mode = mode;
3811
3812         vmx_reset_x2apic_msrs(vcpu, mode);
3813
3814         /*
3815          * TPR reads and writes can be virtualized even if virtual interrupt
3816          * delivery is not in use.
3817          */
3818         vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
3819                                   !(mode & MSR_BITMAP_MODE_X2APIC));
3820
3821         if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3822                 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
3823                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3824                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3825         }
3826 }
3827
3828 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu)
3829 {
3830         struct vcpu_vmx *vmx = to_vmx(vcpu);
3831         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3832         u32 i;
3833
3834         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
3835         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
3836         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
3837         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
3838         for (i = 0; i < vmx->pt_desc.num_address_ranges; i++) {
3839                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3840                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3841         }
3842 }
3843
3844 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3845 {
3846         struct vcpu_vmx *vmx = to_vmx(vcpu);
3847         void *vapic_page;
3848         u32 vppr;
3849         int rvi;
3850
3851         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3852                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3853                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3854                 return false;
3855
3856         rvi = vmx_get_rvi();
3857
3858         vapic_page = vmx->nested.virtual_apic_map.hva;
3859         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3860
3861         return ((rvi & 0xf0) > (vppr & 0xf0));
3862 }
3863
3864 static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
3865 {
3866         struct vcpu_vmx *vmx = to_vmx(vcpu);
3867         u32 i;
3868
3869         /*
3870          * Set intercept permissions for all potentially passed through MSRs
3871          * again. They will automatically get filtered through the MSR filter,
3872          * so we are back in sync after this.
3873          */
3874         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
3875                 u32 msr = vmx_possible_passthrough_msrs[i];
3876                 bool read = test_bit(i, vmx->shadow_msr_intercept.read);
3877                 bool write = test_bit(i, vmx->shadow_msr_intercept.write);
3878
3879                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
3880                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
3881         }
3882
3883         pt_update_intercept_for_msr(vcpu);
3884 }
3885
3886 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3887                                                      bool nested)
3888 {
3889 #ifdef CONFIG_SMP
3890         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3891
3892         if (vcpu->mode == IN_GUEST_MODE) {
3893                 /*
3894                  * The vector of interrupt to be delivered to vcpu had
3895                  * been set in PIR before this function.
3896                  *
3897                  * Following cases will be reached in this block, and
3898                  * we always send a notification event in all cases as
3899                  * explained below.
3900                  *
3901                  * Case 1: vcpu keeps in non-root mode. Sending a
3902                  * notification event posts the interrupt to vcpu.
3903                  *
3904                  * Case 2: vcpu exits to root mode and is still
3905                  * runnable. PIR will be synced to vIRR before the
3906                  * next vcpu entry. Sending a notification event in
3907                  * this case has no effect, as vcpu is not in root
3908                  * mode.
3909                  *
3910                  * Case 3: vcpu exits to root mode and is blocked.
3911                  * vcpu_block() has already synced PIR to vIRR and
3912                  * never blocks vcpu if vIRR is not cleared. Therefore,
3913                  * a blocked vcpu here does not wait for any requested
3914                  * interrupts in PIR, and sending a notification event
3915                  * which has no effect is safe here.
3916                  */
3917
3918                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3919                 return true;
3920         }
3921 #endif
3922         return false;
3923 }
3924
3925 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3926                                                 int vector)
3927 {
3928         struct vcpu_vmx *vmx = to_vmx(vcpu);
3929
3930         if (is_guest_mode(vcpu) &&
3931             vector == vmx->nested.posted_intr_nv) {
3932                 /*
3933                  * If a posted intr is not recognized by hardware,
3934                  * we will accomplish it in the next vmentry.
3935                  */
3936                 vmx->nested.pi_pending = true;
3937                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3938                 /* the PIR and ON have been set by L1. */
3939                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3940                         kvm_vcpu_kick(vcpu);
3941                 return 0;
3942         }
3943         return -1;
3944 }
3945 /*
3946  * Send interrupt to vcpu via posted interrupt way.
3947  * 1. If target vcpu is running(non-root mode), send posted interrupt
3948  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3949  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3950  * interrupt from PIR in next vmentry.
3951  */
3952 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3953 {
3954         struct vcpu_vmx *vmx = to_vmx(vcpu);
3955         int r;
3956
3957         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3958         if (!r)
3959                 return 0;
3960
3961         if (!vcpu->arch.apicv_active)
3962                 return -1;
3963
3964         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3965                 return 0;
3966
3967         /* If a previous notification has sent the IPI, nothing to do.  */
3968         if (pi_test_and_set_on(&vmx->pi_desc))
3969                 return 0;
3970
3971         if (vcpu != kvm_get_running_vcpu() &&
3972             !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3973                 kvm_vcpu_kick(vcpu);
3974
3975         return 0;
3976 }
3977
3978 /*
3979  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3980  * will not change in the lifetime of the guest.
3981  * Note that host-state that does change is set elsewhere. E.g., host-state
3982  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3983  */
3984 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3985 {
3986         u32 low32, high32;
3987         unsigned long tmpl;
3988         unsigned long cr0, cr3, cr4;
3989
3990         cr0 = read_cr0();
3991         WARN_ON(cr0 & X86_CR0_TS);
3992         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3993
3994         /*
3995          * Save the most likely value for this task's CR3 in the VMCS.
3996          * We can't use __get_current_cr3_fast() because we're not atomic.
3997          */
3998         cr3 = __read_cr3();
3999         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
4000         vmx->loaded_vmcs->host_state.cr3 = cr3;
4001
4002         /* Save the most likely value for this task's CR4 in the VMCS. */
4003         cr4 = cr4_read_shadow();
4004         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4005         vmx->loaded_vmcs->host_state.cr4 = cr4;
4006
4007         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4008 #ifdef CONFIG_X86_64
4009         /*
4010          * Load null selectors, so we can avoid reloading them in
4011          * vmx_prepare_switch_to_host(), in case userspace uses
4012          * the null selectors too (the expected case).
4013          */
4014         vmcs_write16(HOST_DS_SELECTOR, 0);
4015         vmcs_write16(HOST_ES_SELECTOR, 0);
4016 #else
4017         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4018         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4019 #endif
4020         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4021         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4022
4023         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
4024
4025         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4026
4027         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4028         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4029         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4030         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4031
4032         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4033                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4034                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4035         }
4036
4037         if (cpu_has_load_ia32_efer())
4038                 vmcs_write64(HOST_IA32_EFER, host_efer);
4039 }
4040
4041 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4042 {
4043         struct kvm_vcpu *vcpu = &vmx->vcpu;
4044
4045         vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
4046                                           ~vcpu->arch.cr4_guest_rsvd_bits;
4047         if (!enable_ept)
4048                 vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4049         if (is_guest_mode(&vmx->vcpu))
4050                 vcpu->arch.cr4_guest_owned_bits &=
4051                         ~get_vmcs12(vcpu)->cr4_guest_host_mask;
4052         vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits);
4053 }
4054
4055 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4056 {
4057         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4058
4059         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4060                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4061
4062         if (!enable_vnmi)
4063                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4064
4065         if (!enable_preemption_timer)
4066                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4067
4068         return pin_based_exec_ctrl;
4069 }
4070
4071 static u32 vmx_vmentry_ctrl(void)
4072 {
4073         u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
4074
4075         if (vmx_pt_mode_is_system())
4076                 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
4077                                   VM_ENTRY_LOAD_IA32_RTIT_CTL);
4078         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4079         return vmentry_ctrl &
4080                 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
4081 }
4082
4083 static u32 vmx_vmexit_ctrl(void)
4084 {
4085         u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
4086
4087         if (vmx_pt_mode_is_system())
4088                 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
4089                                  VM_EXIT_CLEAR_IA32_RTIT_CTL);
4090         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4091         return vmexit_ctrl &
4092                 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
4093 }
4094
4095 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4096 {
4097         struct vcpu_vmx *vmx = to_vmx(vcpu);
4098
4099         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4100         if (cpu_has_secondary_exec_ctrls()) {
4101                 if (kvm_vcpu_apicv_active(vcpu))
4102                         secondary_exec_controls_setbit(vmx,
4103                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4104                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4105                 else
4106                         secondary_exec_controls_clearbit(vmx,
4107                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4108                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4109         }
4110
4111         vmx_update_msr_bitmap_x2apic(vcpu);
4112 }
4113
4114 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4115 {
4116         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4117
4118         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4119                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4120
4121         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4122                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4123 #ifdef CONFIG_X86_64
4124                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4125                                 CPU_BASED_CR8_LOAD_EXITING;
4126 #endif
4127         }
4128         if (!enable_ept)
4129                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4130                                 CPU_BASED_CR3_LOAD_EXITING  |
4131                                 CPU_BASED_INVLPG_EXITING;
4132         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4133                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4134                                 CPU_BASED_MONITOR_EXITING);
4135         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4136                 exec_control &= ~CPU_BASED_HLT_EXITING;
4137         return exec_control;
4138 }
4139
4140 /*
4141  * Adjust a single secondary execution control bit to intercept/allow an
4142  * instruction in the guest.  This is usually done based on whether or not a
4143  * feature has been exposed to the guest in order to correctly emulate faults.
4144  */
4145 static inline void
4146 vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control,
4147                                   u32 control, bool enabled, bool exiting)
4148 {
4149         /*
4150          * If the control is for an opt-in feature, clear the control if the
4151          * feature is not exposed to the guest, i.e. not enabled.  If the
4152          * control is opt-out, i.e. an exiting control, clear the control if
4153          * the feature _is_ exposed to the guest, i.e. exiting/interception is
4154          * disabled for the associated instruction.  Note, the caller is
4155          * responsible presetting exec_control to set all supported bits.
4156          */
4157         if (enabled == exiting)
4158                 *exec_control &= ~control;
4159
4160         /*
4161          * Update the nested MSR settings so that a nested VMM can/can't set
4162          * controls for features that are/aren't exposed to the guest.
4163          */
4164         if (nested) {
4165                 if (enabled)
4166                         vmx->nested.msrs.secondary_ctls_high |= control;
4167                 else
4168                         vmx->nested.msrs.secondary_ctls_high &= ~control;
4169         }
4170 }
4171
4172 /*
4173  * Wrapper macro for the common case of adjusting a secondary execution control
4174  * based on a single guest CPUID bit, with a dedicated feature bit.  This also
4175  * verifies that the control is actually supported by KVM and hardware.
4176  */
4177 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \
4178 ({                                                                       \
4179         bool __enabled;                                                  \
4180                                                                          \
4181         if (cpu_has_vmx_##name()) {                                      \
4182                 __enabled = guest_cpuid_has(&(vmx)->vcpu,                \
4183                                             X86_FEATURE_##feat_name);    \
4184                 vmx_adjust_secondary_exec_control(vmx, exec_control,     \
4185                         SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \
4186         }                                                                \
4187 })
4188
4189 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */
4190 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \
4191         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false)
4192
4193 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \
4194         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true)
4195
4196 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4197 {
4198         struct kvm_vcpu *vcpu = &vmx->vcpu;
4199
4200         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4201
4202         if (vmx_pt_mode_is_system())
4203                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4204         if (!cpu_need_virtualize_apic_accesses(vcpu))
4205                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4206         if (vmx->vpid == 0)
4207                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4208         if (!enable_ept) {
4209                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4210                 enable_unrestricted_guest = 0;
4211         }
4212         if (!enable_unrestricted_guest)
4213                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4214         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4215                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4216         if (!kvm_vcpu_apicv_active(vcpu))
4217                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4218                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4219         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4220
4221         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4222          * in vmx_set_cr4.  */
4223         exec_control &= ~SECONDARY_EXEC_DESC;
4224
4225         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4226            (handle_vmptrld).
4227            We can NOT enable shadow_vmcs here because we don't have yet
4228            a current VMCS12
4229         */
4230         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4231
4232         /*
4233          * PML is enabled/disabled when dirty logging of memsmlots changes, but
4234          * it needs to be set here when dirty logging is already active, e.g.
4235          * if this vCPU was created after dirty logging was enabled.
4236          */
4237         if (!vcpu->kvm->arch.cpu_dirty_logging_count)
4238                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4239
4240         if (cpu_has_vmx_xsaves()) {
4241                 /* Exposing XSAVES only when XSAVE is exposed */
4242                 bool xsaves_enabled =
4243                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4244                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4245                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4246
4247                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4248
4249                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4250                                                   SECONDARY_EXEC_XSAVES,
4251                                                   xsaves_enabled, false);
4252         }
4253
4254         /*
4255          * RDPID is also gated by ENABLE_RDTSCP, turn on the control if either
4256          * feature is exposed to the guest.  This creates a virtualization hole
4257          * if both are supported in hardware but only one is exposed to the
4258          * guest, but letting the guest execute RDTSCP or RDPID when either one
4259          * is advertised is preferable to emulating the advertised instruction
4260          * in KVM on #UD, and obviously better than incorrectly injecting #UD.
4261          */
4262         if (cpu_has_vmx_rdtscp()) {
4263                 bool rdpid_or_rdtscp_enabled =
4264                         guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) ||
4265                         guest_cpuid_has(vcpu, X86_FEATURE_RDPID);
4266
4267                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4268                                                   SECONDARY_EXEC_ENABLE_RDTSCP,
4269                                                   rdpid_or_rdtscp_enabled, false);
4270         }
4271         vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID);
4272
4273         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND);
4274         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED);
4275
4276         vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG,
4277                                     ENABLE_USR_WAIT_PAUSE, false);
4278
4279         if (!vcpu->kvm->arch.bus_lock_detection_enabled)
4280                 exec_control &= ~SECONDARY_EXEC_BUS_LOCK_DETECTION;
4281
4282         return exec_control;
4283 }
4284
4285 #define VMX_XSS_EXIT_BITMAP 0
4286
4287 static void init_vmcs(struct vcpu_vmx *vmx)
4288 {
4289         if (nested)
4290                 nested_vmx_set_vmcs_shadowing_bitmap();
4291
4292         if (cpu_has_vmx_msr_bitmap())
4293                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4294
4295         vmcs_write64(VMCS_LINK_POINTER, INVALID_GPA); /* 22.3.1.5 */
4296
4297         /* Control */
4298         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4299
4300         exec_controls_set(vmx, vmx_exec_control(vmx));
4301
4302         if (cpu_has_secondary_exec_ctrls())
4303                 secondary_exec_controls_set(vmx, vmx_secondary_exec_control(vmx));
4304
4305         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4306                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4307                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4308                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4309                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4310
4311                 vmcs_write16(GUEST_INTR_STATUS, 0);
4312
4313                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4314                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4315         }
4316
4317         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4318                 vmcs_write32(PLE_GAP, ple_gap);
4319                 vmx->ple_window = ple_window;
4320                 vmx->ple_window_dirty = true;
4321         }
4322
4323         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4324         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4325         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4326
4327         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4328         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4329         vmx_set_constant_host_state(vmx);
4330         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4331         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4332
4333         if (cpu_has_vmx_vmfunc())
4334                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4335
4336         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4337         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4338         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4339         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4340         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4341
4342         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4343                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4344
4345         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4346
4347         /* 22.2.1, 20.8.1 */
4348         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4349
4350         vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4351         vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4352
4353         set_cr4_guest_host_mask(vmx);
4354
4355         if (vmx->vpid != 0)
4356                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4357
4358         if (cpu_has_vmx_xsaves())
4359                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4360
4361         if (enable_pml) {
4362                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4363                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4364         }
4365
4366         vmx_write_encls_bitmap(&vmx->vcpu, NULL);
4367
4368         if (vmx_pt_mode_is_host_guest()) {
4369                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4370                 /* Bit[6~0] are forced to 1, writes are ignored. */
4371                 vmx->pt_desc.guest.output_mask = 0x7F;
4372                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4373         }
4374
4375         vmcs_write32(GUEST_SYSENTER_CS, 0);
4376         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4377         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4378         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4379
4380         if (cpu_has_vmx_tpr_shadow()) {
4381                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4382                 if (cpu_need_tpr_shadow(&vmx->vcpu))
4383                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4384                                      __pa(vmx->vcpu.arch.apic->regs));
4385                 vmcs_write32(TPR_THRESHOLD, 0);
4386         }
4387
4388         vmx_setup_uret_msrs(vmx);
4389 }
4390
4391 static void __vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4392 {
4393         struct vcpu_vmx *vmx = to_vmx(vcpu);
4394
4395         init_vmcs(vmx);
4396
4397         if (nested)
4398                 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
4399
4400         vcpu_setup_sgx_lepubkeyhash(vcpu);
4401
4402         vmx->nested.posted_intr_nv = -1;
4403         vmx->nested.vmxon_ptr = INVALID_GPA;
4404         vmx->nested.current_vmptr = INVALID_GPA;
4405         vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
4406
4407         vcpu->arch.microcode_version = 0x100000000ULL;
4408         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
4409
4410         /*
4411          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
4412          * or POSTED_INTR_WAKEUP_VECTOR.
4413          */
4414         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
4415         vmx->pi_desc.sn = 1;
4416 }
4417
4418 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4419 {
4420         struct vcpu_vmx *vmx = to_vmx(vcpu);
4421
4422         if (!init_event)
4423                 __vmx_vcpu_reset(vcpu);
4424
4425         vmx->rmode.vm86_active = 0;
4426         vmx->spec_ctrl = 0;
4427
4428         vmx->msr_ia32_umwait_control = 0;
4429
4430         vmx->hv_deadline_tsc = -1;
4431         kvm_set_cr8(vcpu, 0);
4432
4433         vmx_segment_cache_clear(vmx);
4434         kvm_register_mark_available(vcpu, VCPU_EXREG_SEGMENTS);
4435
4436         seg_setup(VCPU_SREG_CS);
4437         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4438         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4439
4440         seg_setup(VCPU_SREG_DS);
4441         seg_setup(VCPU_SREG_ES);
4442         seg_setup(VCPU_SREG_FS);
4443         seg_setup(VCPU_SREG_GS);
4444         seg_setup(VCPU_SREG_SS);
4445
4446         vmcs_write16(GUEST_TR_SELECTOR, 0);
4447         vmcs_writel(GUEST_TR_BASE, 0);
4448         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4449         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4450
4451         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4452         vmcs_writel(GUEST_LDTR_BASE, 0);
4453         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4454         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4455
4456         vmcs_writel(GUEST_GDTR_BASE, 0);
4457         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4458
4459         vmcs_writel(GUEST_IDTR_BASE, 0);
4460         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4461
4462         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4463         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4464         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4465         if (kvm_mpx_supported())
4466                 vmcs_write64(GUEST_BNDCFGS, 0);
4467
4468         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4469
4470         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4471
4472         vpid_sync_context(vmx->vpid);
4473 }
4474
4475 static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
4476 {
4477         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4478 }
4479
4480 static void vmx_enable_nmi_window(struct kvm_vcpu *vcpu)
4481 {
4482         if (!enable_vnmi ||
4483             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4484                 vmx_enable_irq_window(vcpu);
4485                 return;
4486         }
4487
4488         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4489 }
4490
4491 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4492 {
4493         struct vcpu_vmx *vmx = to_vmx(vcpu);
4494         uint32_t intr;
4495         int irq = vcpu->arch.interrupt.nr;
4496
4497         trace_kvm_inj_virq(irq);
4498
4499         ++vcpu->stat.irq_injections;
4500         if (vmx->rmode.vm86_active) {
4501                 int inc_eip = 0;
4502                 if (vcpu->arch.interrupt.soft)
4503                         inc_eip = vcpu->arch.event_exit_inst_len;
4504                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4505                 return;
4506         }
4507         intr = irq | INTR_INFO_VALID_MASK;
4508         if (vcpu->arch.interrupt.soft) {
4509                 intr |= INTR_TYPE_SOFT_INTR;
4510                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4511                              vmx->vcpu.arch.event_exit_inst_len);
4512         } else
4513                 intr |= INTR_TYPE_EXT_INTR;
4514         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4515
4516         vmx_clear_hlt(vcpu);
4517 }
4518
4519 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4520 {
4521         struct vcpu_vmx *vmx = to_vmx(vcpu);
4522
4523         if (!enable_vnmi) {
4524                 /*
4525                  * Tracking the NMI-blocked state in software is built upon
4526                  * finding the next open IRQ window. This, in turn, depends on
4527                  * well-behaving guests: They have to keep IRQs disabled at
4528                  * least as long as the NMI handler runs. Otherwise we may
4529                  * cause NMI nesting, maybe breaking the guest. But as this is
4530                  * highly unlikely, we can live with the residual risk.
4531                  */
4532                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4533                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4534         }
4535
4536         ++vcpu->stat.nmi_injections;
4537         vmx->loaded_vmcs->nmi_known_unmasked = false;
4538
4539         if (vmx->rmode.vm86_active) {
4540                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4541                 return;
4542         }
4543
4544         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4545                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4546
4547         vmx_clear_hlt(vcpu);
4548 }
4549
4550 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4551 {
4552         struct vcpu_vmx *vmx = to_vmx(vcpu);
4553         bool masked;
4554
4555         if (!enable_vnmi)
4556                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4557         if (vmx->loaded_vmcs->nmi_known_unmasked)
4558                 return false;
4559         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4560         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4561         return masked;
4562 }
4563
4564 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4565 {
4566         struct vcpu_vmx *vmx = to_vmx(vcpu);
4567
4568         if (!enable_vnmi) {
4569                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4570                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4571                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4572                 }
4573         } else {
4574                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4575                 if (masked)
4576                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4577                                       GUEST_INTR_STATE_NMI);
4578                 else
4579                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4580                                         GUEST_INTR_STATE_NMI);
4581         }
4582 }
4583
4584 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4585 {
4586         if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4587                 return false;
4588
4589         if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4590                 return true;
4591
4592         return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4593                 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4594                  GUEST_INTR_STATE_NMI));
4595 }
4596
4597 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4598 {
4599         if (to_vmx(vcpu)->nested.nested_run_pending)
4600                 return -EBUSY;
4601
4602         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
4603         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4604                 return -EBUSY;
4605
4606         return !vmx_nmi_blocked(vcpu);
4607 }
4608
4609 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4610 {
4611         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4612                 return false;
4613
4614         return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4615                (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4616                 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4617 }
4618
4619 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4620 {
4621         if (to_vmx(vcpu)->nested.nested_run_pending)
4622                 return -EBUSY;
4623
4624        /*
4625         * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4626         * e.g. if the IRQ arrived asynchronously after checking nested events.
4627         */
4628         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4629                 return -EBUSY;
4630
4631         return !vmx_interrupt_blocked(vcpu);
4632 }
4633
4634 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4635 {
4636         void __user *ret;
4637
4638         if (enable_unrestricted_guest)
4639                 return 0;
4640
4641         mutex_lock(&kvm->slots_lock);
4642         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4643                                       PAGE_SIZE * 3);
4644         mutex_unlock(&kvm->slots_lock);
4645
4646         if (IS_ERR(ret))
4647                 return PTR_ERR(ret);
4648
4649         to_kvm_vmx(kvm)->tss_addr = addr;
4650
4651         return init_rmode_tss(kvm, ret);
4652 }
4653
4654 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4655 {
4656         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4657         return 0;
4658 }
4659
4660 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4661 {
4662         switch (vec) {
4663         case BP_VECTOR:
4664                 /*
4665                  * Update instruction length as we may reinject the exception
4666                  * from user space while in guest debugging mode.
4667                  */
4668                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4669                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4670                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4671                         return false;
4672                 fallthrough;
4673         case DB_VECTOR:
4674                 return !(vcpu->guest_debug &
4675                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4676         case DE_VECTOR:
4677         case OF_VECTOR:
4678         case BR_VECTOR:
4679         case UD_VECTOR:
4680         case DF_VECTOR:
4681         case SS_VECTOR:
4682         case GP_VECTOR:
4683         case MF_VECTOR:
4684                 return true;
4685         }
4686         return false;
4687 }
4688
4689 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4690                                   int vec, u32 err_code)
4691 {
4692         /*
4693          * Instruction with address size override prefix opcode 0x67
4694          * Cause the #SS fault with 0 error code in VM86 mode.
4695          */
4696         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4697                 if (kvm_emulate_instruction(vcpu, 0)) {
4698                         if (vcpu->arch.halt_request) {
4699                                 vcpu->arch.halt_request = 0;
4700                                 return kvm_vcpu_halt(vcpu);
4701                         }
4702                         return 1;
4703                 }
4704                 return 0;
4705         }
4706
4707         /*
4708          * Forward all other exceptions that are valid in real mode.
4709          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4710          *        the required debugging infrastructure rework.
4711          */
4712         kvm_queue_exception(vcpu, vec);
4713         return 1;
4714 }
4715
4716 static int handle_machine_check(struct kvm_vcpu *vcpu)
4717 {
4718         /* handled by vmx_vcpu_run() */
4719         return 1;
4720 }
4721
4722 /*
4723  * If the host has split lock detection disabled, then #AC is
4724  * unconditionally injected into the guest, which is the pre split lock
4725  * detection behaviour.
4726  *
4727  * If the host has split lock detection enabled then #AC is
4728  * only injected into the guest when:
4729  *  - Guest CPL == 3 (user mode)
4730  *  - Guest has #AC detection enabled in CR0
4731  *  - Guest EFLAGS has AC bit set
4732  */
4733 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu)
4734 {
4735         if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4736                 return true;
4737
4738         return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4739                (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4740 }
4741
4742 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4743 {
4744         struct vcpu_vmx *vmx = to_vmx(vcpu);
4745         struct kvm_run *kvm_run = vcpu->run;
4746         u32 intr_info, ex_no, error_code;
4747         unsigned long cr2, dr6;
4748         u32 vect_info;
4749
4750         vect_info = vmx->idt_vectoring_info;
4751         intr_info = vmx_get_intr_info(vcpu);
4752
4753         if (is_machine_check(intr_info) || is_nmi(intr_info))
4754                 return 1; /* handled by handle_exception_nmi_irqoff() */
4755
4756         if (is_invalid_opcode(intr_info))
4757                 return handle_ud(vcpu);
4758
4759         error_code = 0;
4760         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4761                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4762
4763         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4764                 WARN_ON_ONCE(!enable_vmware_backdoor);
4765
4766                 /*
4767                  * VMware backdoor emulation on #GP interception only handles
4768                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4769                  * error code on #GP.
4770                  */
4771                 if (error_code) {
4772                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4773                         return 1;
4774                 }
4775                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4776         }
4777
4778         /*
4779          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4780          * MMIO, it is better to report an internal error.
4781          * See the comments in vmx_handle_exit.
4782          */
4783         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4784             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4785                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4786                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4787                 vcpu->run->internal.ndata = 4;
4788                 vcpu->run->internal.data[0] = vect_info;
4789                 vcpu->run->internal.data[1] = intr_info;
4790                 vcpu->run->internal.data[2] = error_code;
4791                 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4792                 return 0;
4793         }
4794
4795         if (is_page_fault(intr_info)) {
4796                 cr2 = vmx_get_exit_qual(vcpu);
4797                 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4798                         /*
4799                          * EPT will cause page fault only if we need to
4800                          * detect illegal GPAs.
4801                          */
4802                         WARN_ON_ONCE(!allow_smaller_maxphyaddr);
4803                         kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4804                         return 1;
4805                 } else
4806                         return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4807         }
4808
4809         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4810
4811         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4812                 return handle_rmode_exception(vcpu, ex_no, error_code);
4813
4814         switch (ex_no) {
4815         case DB_VECTOR:
4816                 dr6 = vmx_get_exit_qual(vcpu);
4817                 if (!(vcpu->guest_debug &
4818                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4819                         if (is_icebp(intr_info))
4820                                 WARN_ON(!skip_emulated_instruction(vcpu));
4821
4822                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4823                         return 1;
4824                 }
4825                 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
4826                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4827                 fallthrough;
4828         case BP_VECTOR:
4829                 /*
4830                  * Update instruction length as we may reinject #BP from
4831                  * user space while in guest debugging mode. Reading it for
4832                  * #DB as well causes no harm, it is not used in that case.
4833                  */
4834                 vmx->vcpu.arch.event_exit_inst_len =
4835                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4836                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4837                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4838                 kvm_run->debug.arch.exception = ex_no;
4839                 break;
4840         case AC_VECTOR:
4841                 if (vmx_guest_inject_ac(vcpu)) {
4842                         kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4843                         return 1;
4844                 }
4845
4846                 /*
4847                  * Handle split lock. Depending on detection mode this will
4848                  * either warn and disable split lock detection for this
4849                  * task or force SIGBUS on it.
4850                  */
4851                 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4852                         return 1;
4853                 fallthrough;
4854         default:
4855                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4856                 kvm_run->ex.exception = ex_no;
4857                 kvm_run->ex.error_code = error_code;
4858                 break;
4859         }
4860         return 0;
4861 }
4862
4863 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4864 {
4865         ++vcpu->stat.irq_exits;
4866         return 1;
4867 }
4868
4869 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4870 {
4871         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4872         vcpu->mmio_needed = 0;
4873         return 0;
4874 }
4875
4876 static int handle_io(struct kvm_vcpu *vcpu)
4877 {
4878         unsigned long exit_qualification;
4879         int size, in, string;
4880         unsigned port;
4881
4882         exit_qualification = vmx_get_exit_qual(vcpu);
4883         string = (exit_qualification & 16) != 0;
4884
4885         ++vcpu->stat.io_exits;
4886
4887         if (string)
4888                 return kvm_emulate_instruction(vcpu, 0);
4889
4890         port = exit_qualification >> 16;
4891         size = (exit_qualification & 7) + 1;
4892         in = (exit_qualification & 8) != 0;
4893
4894         return kvm_fast_pio(vcpu, size, port, in);
4895 }
4896
4897 static void
4898 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4899 {
4900         /*
4901          * Patch in the VMCALL instruction:
4902          */
4903         hypercall[0] = 0x0f;
4904         hypercall[1] = 0x01;
4905         hypercall[2] = 0xc1;
4906 }
4907
4908 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4909 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4910 {
4911         if (is_guest_mode(vcpu)) {
4912                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4913                 unsigned long orig_val = val;
4914
4915                 /*
4916                  * We get here when L2 changed cr0 in a way that did not change
4917                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4918                  * but did change L0 shadowed bits. So we first calculate the
4919                  * effective cr0 value that L1 would like to write into the
4920                  * hardware. It consists of the L2-owned bits from the new
4921                  * value combined with the L1-owned bits from L1's guest_cr0.
4922                  */
4923                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4924                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4925
4926                 if (!nested_guest_cr0_valid(vcpu, val))
4927                         return 1;
4928
4929                 if (kvm_set_cr0(vcpu, val))
4930                         return 1;
4931                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4932                 return 0;
4933         } else {
4934                 if (to_vmx(vcpu)->nested.vmxon &&
4935                     !nested_host_cr0_valid(vcpu, val))
4936                         return 1;
4937
4938                 return kvm_set_cr0(vcpu, val);
4939         }
4940 }
4941
4942 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4943 {
4944         if (is_guest_mode(vcpu)) {
4945                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4946                 unsigned long orig_val = val;
4947
4948                 /* analogously to handle_set_cr0 */
4949                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4950                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4951                 if (kvm_set_cr4(vcpu, val))
4952                         return 1;
4953                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4954                 return 0;
4955         } else
4956                 return kvm_set_cr4(vcpu, val);
4957 }
4958
4959 static int handle_desc(struct kvm_vcpu *vcpu)
4960 {
4961         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4962         return kvm_emulate_instruction(vcpu, 0);
4963 }
4964
4965 static int handle_cr(struct kvm_vcpu *vcpu)
4966 {
4967         unsigned long exit_qualification, val;
4968         int cr;
4969         int reg;
4970         int err;
4971         int ret;
4972
4973         exit_qualification = vmx_get_exit_qual(vcpu);
4974         cr = exit_qualification & 15;
4975         reg = (exit_qualification >> 8) & 15;
4976         switch ((exit_qualification >> 4) & 3) {
4977         case 0: /* mov to cr */
4978                 val = kvm_register_read(vcpu, reg);
4979                 trace_kvm_cr_write(cr, val);
4980                 switch (cr) {
4981                 case 0:
4982                         err = handle_set_cr0(vcpu, val);
4983                         return kvm_complete_insn_gp(vcpu, err);
4984                 case 3:
4985                         WARN_ON_ONCE(enable_unrestricted_guest);
4986
4987                         err = kvm_set_cr3(vcpu, val);
4988                         return kvm_complete_insn_gp(vcpu, err);
4989                 case 4:
4990                         err = handle_set_cr4(vcpu, val);
4991                         return kvm_complete_insn_gp(vcpu, err);
4992                 case 8: {
4993                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4994                                 u8 cr8 = (u8)val;
4995                                 err = kvm_set_cr8(vcpu, cr8);
4996                                 ret = kvm_complete_insn_gp(vcpu, err);
4997                                 if (lapic_in_kernel(vcpu))
4998                                         return ret;
4999                                 if (cr8_prev <= cr8)
5000                                         return ret;
5001                                 /*
5002                                  * TODO: we might be squashing a
5003                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5004                                  * KVM_EXIT_DEBUG here.
5005                                  */
5006                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5007                                 return 0;
5008                         }
5009                 }
5010                 break;
5011         case 2: /* clts */
5012                 KVM_BUG(1, vcpu->kvm, "Guest always owns CR0.TS");
5013                 return -EIO;
5014         case 1: /*mov from cr*/
5015                 switch (cr) {
5016                 case 3:
5017                         WARN_ON_ONCE(enable_unrestricted_guest);
5018
5019                         val = kvm_read_cr3(vcpu);
5020                         kvm_register_write(vcpu, reg, val);
5021                         trace_kvm_cr_read(cr, val);
5022                         return kvm_skip_emulated_instruction(vcpu);
5023                 case 8:
5024                         val = kvm_get_cr8(vcpu);
5025                         kvm_register_write(vcpu, reg, val);
5026                         trace_kvm_cr_read(cr, val);
5027                         return kvm_skip_emulated_instruction(vcpu);
5028                 }
5029                 break;
5030         case 3: /* lmsw */
5031                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5032                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5033                 kvm_lmsw(vcpu, val);
5034
5035                 return kvm_skip_emulated_instruction(vcpu);
5036         default:
5037                 break;
5038         }
5039         vcpu->run->exit_reason = 0;
5040         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5041                (int)(exit_qualification >> 4) & 3, cr);
5042         return 0;
5043 }
5044
5045 static int handle_dr(struct kvm_vcpu *vcpu)
5046 {
5047         unsigned long exit_qualification;
5048         int dr, dr7, reg;
5049         int err = 1;
5050
5051         exit_qualification = vmx_get_exit_qual(vcpu);
5052         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5053
5054         /* First, if DR does not exist, trigger UD */
5055         if (!kvm_require_dr(vcpu, dr))
5056                 return 1;
5057
5058         if (kvm_x86_ops.get_cpl(vcpu) > 0)
5059                 goto out;
5060
5061         dr7 = vmcs_readl(GUEST_DR7);
5062         if (dr7 & DR7_GD) {
5063                 /*
5064                  * As the vm-exit takes precedence over the debug trap, we
5065                  * need to emulate the latter, either for the host or the
5066                  * guest debugging itself.
5067                  */
5068                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5069                         vcpu->run->debug.arch.dr6 = DR6_BD | DR6_ACTIVE_LOW;
5070                         vcpu->run->debug.arch.dr7 = dr7;
5071                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5072                         vcpu->run->debug.arch.exception = DB_VECTOR;
5073                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5074                         return 0;
5075                 } else {
5076                         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5077                         return 1;
5078                 }
5079         }
5080
5081         if (vcpu->guest_debug == 0) {
5082                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5083
5084                 /*
5085                  * No more DR vmexits; force a reload of the debug registers
5086                  * and reenter on this instruction.  The next vmexit will
5087                  * retrieve the full state of the debug registers.
5088                  */
5089                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5090                 return 1;
5091         }
5092
5093         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5094         if (exit_qualification & TYPE_MOV_FROM_DR) {
5095                 unsigned long val;
5096
5097                 kvm_get_dr(vcpu, dr, &val);
5098                 kvm_register_write(vcpu, reg, val);
5099                 err = 0;
5100         } else {
5101                 err = kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg));
5102         }
5103
5104 out:
5105         return kvm_complete_insn_gp(vcpu, err);
5106 }
5107
5108 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5109 {
5110         get_debugreg(vcpu->arch.db[0], 0);
5111         get_debugreg(vcpu->arch.db[1], 1);
5112         get_debugreg(vcpu->arch.db[2], 2);
5113         get_debugreg(vcpu->arch.db[3], 3);
5114         get_debugreg(vcpu->arch.dr6, 6);
5115         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5116
5117         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5118         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5119
5120         /*
5121          * exc_debug expects dr6 to be cleared after it runs, avoid that it sees
5122          * a stale dr6 from the guest.
5123          */
5124         set_debugreg(DR6_RESERVED, 6);
5125 }
5126
5127 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5128 {
5129         vmcs_writel(GUEST_DR7, val);
5130 }
5131
5132 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5133 {
5134         kvm_apic_update_ppr(vcpu);
5135         return 1;
5136 }
5137
5138 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5139 {
5140         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5141
5142         kvm_make_request(KVM_REQ_EVENT, vcpu);
5143
5144         ++vcpu->stat.irq_window_exits;
5145         return 1;
5146 }
5147
5148 static int handle_invlpg(struct kvm_vcpu *vcpu)
5149 {
5150         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5151
5152         kvm_mmu_invlpg(vcpu, exit_qualification);
5153         return kvm_skip_emulated_instruction(vcpu);
5154 }
5155
5156 static int handle_apic_access(struct kvm_vcpu *vcpu)
5157 {
5158         if (likely(fasteoi)) {
5159                 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5160                 int access_type, offset;
5161
5162                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5163                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5164                 /*
5165                  * Sane guest uses MOV to write EOI, with written value
5166                  * not cared. So make a short-circuit here by avoiding
5167                  * heavy instruction emulation.
5168                  */
5169                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5170                     (offset == APIC_EOI)) {
5171                         kvm_lapic_set_eoi(vcpu);
5172                         return kvm_skip_emulated_instruction(vcpu);
5173                 }
5174         }
5175         return kvm_emulate_instruction(vcpu, 0);
5176 }
5177
5178 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5179 {
5180         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5181         int vector = exit_qualification & 0xff;
5182
5183         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5184         kvm_apic_set_eoi_accelerated(vcpu, vector);
5185         return 1;
5186 }
5187
5188 static int handle_apic_write(struct kvm_vcpu *vcpu)
5189 {
5190         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5191         u32 offset = exit_qualification & 0xfff;
5192
5193         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5194         kvm_apic_write_nodecode(vcpu, offset);
5195         return 1;
5196 }
5197
5198 static int handle_task_switch(struct kvm_vcpu *vcpu)
5199 {
5200         struct vcpu_vmx *vmx = to_vmx(vcpu);
5201         unsigned long exit_qualification;
5202         bool has_error_code = false;
5203         u32 error_code = 0;
5204         u16 tss_selector;
5205         int reason, type, idt_v, idt_index;
5206
5207         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5208         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5209         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5210
5211         exit_qualification = vmx_get_exit_qual(vcpu);
5212
5213         reason = (u32)exit_qualification >> 30;
5214         if (reason == TASK_SWITCH_GATE && idt_v) {
5215                 switch (type) {
5216                 case INTR_TYPE_NMI_INTR:
5217                         vcpu->arch.nmi_injected = false;
5218                         vmx_set_nmi_mask(vcpu, true);
5219                         break;
5220                 case INTR_TYPE_EXT_INTR:
5221                 case INTR_TYPE_SOFT_INTR:
5222                         kvm_clear_interrupt_queue(vcpu);
5223                         break;
5224                 case INTR_TYPE_HARD_EXCEPTION:
5225                         if (vmx->idt_vectoring_info &
5226                             VECTORING_INFO_DELIVER_CODE_MASK) {
5227                                 has_error_code = true;
5228                                 error_code =
5229                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5230                         }
5231                         fallthrough;
5232                 case INTR_TYPE_SOFT_EXCEPTION:
5233                         kvm_clear_exception_queue(vcpu);
5234                         break;
5235                 default:
5236                         break;
5237                 }
5238         }
5239         tss_selector = exit_qualification;
5240
5241         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5242                        type != INTR_TYPE_EXT_INTR &&
5243                        type != INTR_TYPE_NMI_INTR))
5244                 WARN_ON(!skip_emulated_instruction(vcpu));
5245
5246         /*
5247          * TODO: What about debug traps on tss switch?
5248          *       Are we supposed to inject them and update dr6?
5249          */
5250         return kvm_task_switch(vcpu, tss_selector,
5251                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5252                                reason, has_error_code, error_code);
5253 }
5254
5255 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5256 {
5257         unsigned long exit_qualification;
5258         gpa_t gpa;
5259         u64 error_code;
5260
5261         exit_qualification = vmx_get_exit_qual(vcpu);
5262
5263         /*
5264          * EPT violation happened while executing iret from NMI,
5265          * "blocked by NMI" bit has to be set before next VM entry.
5266          * There are errata that may cause this bit to not be set:
5267          * AAK134, BY25.
5268          */
5269         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5270                         enable_vnmi &&
5271                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5272                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5273
5274         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5275         trace_kvm_page_fault(gpa, exit_qualification);
5276
5277         /* Is it a read fault? */
5278         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5279                      ? PFERR_USER_MASK : 0;
5280         /* Is it a write fault? */
5281         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5282                       ? PFERR_WRITE_MASK : 0;
5283         /* Is it a fetch fault? */
5284         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5285                       ? PFERR_FETCH_MASK : 0;
5286         /* ept page table entry is present? */
5287         error_code |= (exit_qualification &
5288                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5289                         EPT_VIOLATION_EXECUTABLE))
5290                       ? PFERR_PRESENT_MASK : 0;
5291
5292         error_code |= (exit_qualification & EPT_VIOLATION_GVA_TRANSLATED) != 0 ?
5293                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5294
5295         vcpu->arch.exit_qualification = exit_qualification;
5296
5297         /*
5298          * Check that the GPA doesn't exceed physical memory limits, as that is
5299          * a guest page fault.  We have to emulate the instruction here, because
5300          * if the illegal address is that of a paging structure, then
5301          * EPT_VIOLATION_ACC_WRITE bit is set.  Alternatively, if supported we
5302          * would also use advanced VM-exit information for EPT violations to
5303          * reconstruct the page fault error code.
5304          */
5305         if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa)))
5306                 return kvm_emulate_instruction(vcpu, 0);
5307
5308         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5309 }
5310
5311 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5312 {
5313         gpa_t gpa;
5314
5315         if (!vmx_can_emulate_instruction(vcpu, NULL, 0))
5316                 return 1;
5317
5318         /*
5319          * A nested guest cannot optimize MMIO vmexits, because we have an
5320          * nGPA here instead of the required GPA.
5321          */
5322         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5323         if (!is_guest_mode(vcpu) &&
5324             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5325                 trace_kvm_fast_mmio(gpa);
5326                 return kvm_skip_emulated_instruction(vcpu);
5327         }
5328
5329         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5330 }
5331
5332 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5333 {
5334         if (KVM_BUG_ON(!enable_vnmi, vcpu->kvm))
5335                 return -EIO;
5336
5337         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5338         ++vcpu->stat.nmi_window_exits;
5339         kvm_make_request(KVM_REQ_EVENT, vcpu);
5340
5341         return 1;
5342 }
5343
5344 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5345 {
5346         struct vcpu_vmx *vmx = to_vmx(vcpu);
5347         bool intr_window_requested;
5348         unsigned count = 130;
5349
5350         intr_window_requested = exec_controls_get(vmx) &
5351                                 CPU_BASED_INTR_WINDOW_EXITING;
5352
5353         while (vmx->emulation_required && count-- != 0) {
5354                 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5355                         return handle_interrupt_window(&vmx->vcpu);
5356
5357                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5358                         return 1;
5359
5360                 if (!kvm_emulate_instruction(vcpu, 0))
5361                         return 0;
5362
5363                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5364                     vcpu->arch.exception.pending) {
5365                         kvm_prepare_emulation_failure_exit(vcpu);
5366                         return 0;
5367                 }
5368
5369                 if (vcpu->arch.halt_request) {
5370                         vcpu->arch.halt_request = 0;
5371                         return kvm_vcpu_halt(vcpu);
5372                 }
5373
5374                 /*
5375                  * Note, return 1 and not 0, vcpu_run() will invoke
5376                  * xfer_to_guest_mode() which will create a proper return
5377                  * code.
5378                  */
5379                 if (__xfer_to_guest_mode_work_pending())
5380                         return 1;
5381         }
5382
5383         return 1;
5384 }
5385
5386 static void grow_ple_window(struct kvm_vcpu *vcpu)
5387 {
5388         struct vcpu_vmx *vmx = to_vmx(vcpu);
5389         unsigned int old = vmx->ple_window;
5390
5391         vmx->ple_window = __grow_ple_window(old, ple_window,
5392                                             ple_window_grow,
5393                                             ple_window_max);
5394
5395         if (vmx->ple_window != old) {
5396                 vmx->ple_window_dirty = true;
5397                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5398                                             vmx->ple_window, old);
5399         }
5400 }
5401
5402 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5403 {
5404         struct vcpu_vmx *vmx = to_vmx(vcpu);
5405         unsigned int old = vmx->ple_window;
5406
5407         vmx->ple_window = __shrink_ple_window(old, ple_window,
5408                                               ple_window_shrink,
5409                                               ple_window);
5410
5411         if (vmx->ple_window != old) {
5412                 vmx->ple_window_dirty = true;
5413                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5414                                             vmx->ple_window, old);
5415         }
5416 }
5417
5418 /*
5419  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5420  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5421  */
5422 static int handle_pause(struct kvm_vcpu *vcpu)
5423 {
5424         if (!kvm_pause_in_guest(vcpu->kvm))
5425                 grow_ple_window(vcpu);
5426
5427         /*
5428          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5429          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5430          * never set PAUSE_EXITING and just set PLE if supported,
5431          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5432          */
5433         kvm_vcpu_on_spin(vcpu, true);
5434         return kvm_skip_emulated_instruction(vcpu);
5435 }
5436
5437 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5438 {
5439         return 1;
5440 }
5441
5442 static int handle_invpcid(struct kvm_vcpu *vcpu)
5443 {
5444         u32 vmx_instruction_info;
5445         unsigned long type;
5446         gva_t gva;
5447         struct {
5448                 u64 pcid;
5449                 u64 gla;
5450         } operand;
5451         int gpr_index;
5452
5453         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5454                 kvm_queue_exception(vcpu, UD_VECTOR);
5455                 return 1;
5456         }
5457
5458         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5459         gpr_index = vmx_get_instr_info_reg2(vmx_instruction_info);
5460         type = kvm_register_read(vcpu, gpr_index);
5461
5462         /* According to the Intel instruction reference, the memory operand
5463          * is read even if it isn't needed (e.g., for type==all)
5464          */
5465         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5466                                 vmx_instruction_info, false,
5467                                 sizeof(operand), &gva))
5468                 return 1;
5469
5470         return kvm_handle_invpcid(vcpu, type, gva);
5471 }
5472
5473 static int handle_pml_full(struct kvm_vcpu *vcpu)
5474 {
5475         unsigned long exit_qualification;
5476
5477         trace_kvm_pml_full(vcpu->vcpu_id);
5478
5479         exit_qualification = vmx_get_exit_qual(vcpu);
5480
5481         /*
5482          * PML buffer FULL happened while executing iret from NMI,
5483          * "blocked by NMI" bit has to be set before next VM entry.
5484          */
5485         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5486                         enable_vnmi &&
5487                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5488                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5489                                 GUEST_INTR_STATE_NMI);
5490
5491         /*
5492          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5493          * here.., and there's no userspace involvement needed for PML.
5494          */
5495         return 1;
5496 }
5497
5498 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5499 {
5500         struct vcpu_vmx *vmx = to_vmx(vcpu);
5501
5502         if (!vmx->req_immediate_exit &&
5503             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5504                 kvm_lapic_expired_hv_timer(vcpu);
5505                 return EXIT_FASTPATH_REENTER_GUEST;
5506         }
5507
5508         return EXIT_FASTPATH_NONE;
5509 }
5510
5511 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5512 {
5513         handle_fastpath_preemption_timer(vcpu);
5514         return 1;
5515 }
5516
5517 /*
5518  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5519  * are overwritten by nested_vmx_setup() when nested=1.
5520  */
5521 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5522 {
5523         kvm_queue_exception(vcpu, UD_VECTOR);
5524         return 1;
5525 }
5526
5527 #ifndef CONFIG_X86_SGX_KVM
5528 static int handle_encls(struct kvm_vcpu *vcpu)
5529 {
5530         /*
5531          * SGX virtualization is disabled.  There is no software enable bit for
5532          * SGX, so KVM intercepts all ENCLS leafs and injects a #UD to prevent
5533          * the guest from executing ENCLS (when SGX is supported by hardware).
5534          */
5535         kvm_queue_exception(vcpu, UD_VECTOR);
5536         return 1;
5537 }
5538 #endif /* CONFIG_X86_SGX_KVM */
5539
5540 static int handle_bus_lock_vmexit(struct kvm_vcpu *vcpu)
5541 {
5542         /*
5543          * Hardware may or may not set the BUS_LOCK_DETECTED flag on BUS_LOCK
5544          * VM-Exits. Unconditionally set the flag here and leave the handling to
5545          * vmx_handle_exit().
5546          */
5547         to_vmx(vcpu)->exit_reason.bus_lock_detected = true;
5548         return 1;
5549 }
5550
5551 /*
5552  * The exit handlers return 1 if the exit was handled fully and guest execution
5553  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5554  * to be done to userspace and return 0.
5555  */
5556 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5557         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5558         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5559         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5560         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5561         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5562         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5563         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5564         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5565         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5566         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5567         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5568         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5569         [EXIT_REASON_INVD]                    = kvm_emulate_invd,
5570         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5571         [EXIT_REASON_RDPMC]                   = kvm_emulate_rdpmc,
5572         [EXIT_REASON_VMCALL]                  = kvm_emulate_hypercall,
5573         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5574         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5575         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5576         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5577         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5578         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5579         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5580         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5581         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5582         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5583         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5584         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5585         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5586         [EXIT_REASON_WBINVD]                  = kvm_emulate_wbinvd,
5587         [EXIT_REASON_XSETBV]                  = kvm_emulate_xsetbv,
5588         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5589         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5590         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5591         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5592         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5593         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5594         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5595         [EXIT_REASON_MWAIT_INSTRUCTION]       = kvm_emulate_mwait,
5596         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5597         [EXIT_REASON_MONITOR_INSTRUCTION]     = kvm_emulate_monitor,
5598         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5599         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5600         [EXIT_REASON_RDRAND]                  = kvm_handle_invalid_op,
5601         [EXIT_REASON_RDSEED]                  = kvm_handle_invalid_op,
5602         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5603         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5604         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5605         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5606         [EXIT_REASON_ENCLS]                   = handle_encls,
5607         [EXIT_REASON_BUS_LOCK]                = handle_bus_lock_vmexit,
5608 };
5609
5610 static const int kvm_vmx_max_exit_handlers =
5611         ARRAY_SIZE(kvm_vmx_exit_handlers);
5612
5613 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
5614                               u64 *info1, u64 *info2,
5615                               u32 *intr_info, u32 *error_code)
5616 {
5617         struct vcpu_vmx *vmx = to_vmx(vcpu);
5618
5619         *reason = vmx->exit_reason.full;
5620         *info1 = vmx_get_exit_qual(vcpu);
5621         if (!(vmx->exit_reason.failed_vmentry)) {
5622                 *info2 = vmx->idt_vectoring_info;
5623                 *intr_info = vmx_get_intr_info(vcpu);
5624                 if (is_exception_with_error_code(*intr_info))
5625                         *error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5626                 else
5627                         *error_code = 0;
5628         } else {
5629                 *info2 = 0;
5630                 *intr_info = 0;
5631                 *error_code = 0;
5632         }
5633 }
5634
5635 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5636 {
5637         if (vmx->pml_pg) {
5638                 __free_page(vmx->pml_pg);
5639                 vmx->pml_pg = NULL;
5640         }
5641 }
5642
5643 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5644 {
5645         struct vcpu_vmx *vmx = to_vmx(vcpu);
5646         u64 *pml_buf;
5647         u16 pml_idx;
5648
5649         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5650
5651         /* Do nothing if PML buffer is empty */
5652         if (pml_idx == (PML_ENTITY_NUM - 1))
5653                 return;
5654
5655         /* PML index always points to next available PML buffer entity */
5656         if (pml_idx >= PML_ENTITY_NUM)
5657                 pml_idx = 0;
5658         else
5659                 pml_idx++;
5660
5661         pml_buf = page_address(vmx->pml_pg);
5662         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5663                 u64 gpa;
5664
5665                 gpa = pml_buf[pml_idx];
5666                 WARN_ON(gpa & (PAGE_SIZE - 1));
5667                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5668         }
5669
5670         /* reset PML index */
5671         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5672 }
5673
5674 static void vmx_dump_sel(char *name, uint32_t sel)
5675 {
5676         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5677                name, vmcs_read16(sel),
5678                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5679                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5680                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5681 }
5682
5683 static void vmx_dump_dtsel(char *name, uint32_t limit)
5684 {
5685         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5686                name, vmcs_read32(limit),
5687                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5688 }
5689
5690 static void vmx_dump_msrs(char *name, struct vmx_msrs *m)
5691 {
5692         unsigned int i;
5693         struct vmx_msr_entry *e;
5694
5695         pr_err("MSR %s:\n", name);
5696         for (i = 0, e = m->val; i < m->nr; ++i, ++e)
5697                 pr_err("  %2d: msr=0x%08x value=0x%016llx\n", i, e->index, e->value);
5698 }
5699
5700 void dump_vmcs(struct kvm_vcpu *vcpu)
5701 {
5702         struct vcpu_vmx *vmx = to_vmx(vcpu);
5703         u32 vmentry_ctl, vmexit_ctl;
5704         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5705         unsigned long cr4;
5706         int efer_slot;
5707
5708         if (!dump_invalid_vmcs) {
5709                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5710                 return;
5711         }
5712
5713         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5714         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5715         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5716         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5717         cr4 = vmcs_readl(GUEST_CR4);
5718         secondary_exec_control = 0;
5719         if (cpu_has_secondary_exec_ctrls())
5720                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5721
5722         pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
5723                vmx->loaded_vmcs->vmcs, vcpu->arch.last_vmentry_cpu);
5724         pr_err("*** Guest State ***\n");
5725         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5726                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5727                vmcs_readl(CR0_GUEST_HOST_MASK));
5728         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5729                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5730         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5731         if (cpu_has_vmx_ept()) {
5732                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5733                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5734                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5735                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5736         }
5737         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5738                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5739         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5740                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5741         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5742                vmcs_readl(GUEST_SYSENTER_ESP),
5743                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5744         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5745         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5746         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5747         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5748         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5749         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5750         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5751         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5752         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5753         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5754         efer_slot = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, MSR_EFER);
5755         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_EFER)
5756                 pr_err("EFER= 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER));
5757         else if (efer_slot >= 0)
5758                 pr_err("EFER= 0x%016llx (autoload)\n",
5759                        vmx->msr_autoload.guest.val[efer_slot].value);
5760         else if (vmentry_ctl & VM_ENTRY_IA32E_MODE)
5761                 pr_err("EFER= 0x%016llx (effective)\n",
5762                        vcpu->arch.efer | (EFER_LMA | EFER_LME));
5763         else
5764                 pr_err("EFER= 0x%016llx (effective)\n",
5765                        vcpu->arch.efer & ~(EFER_LMA | EFER_LME));
5766         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PAT)
5767                 pr_err("PAT = 0x%016llx\n", vmcs_read64(GUEST_IA32_PAT));
5768         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5769                vmcs_read64(GUEST_IA32_DEBUGCTL),
5770                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5771         if (cpu_has_load_perf_global_ctrl() &&
5772             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5773                 pr_err("PerfGlobCtl = 0x%016llx\n",
5774                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5775         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5776                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5777         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5778                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5779                vmcs_read32(GUEST_ACTIVITY_STATE));
5780         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5781                 pr_err("InterruptStatus = %04x\n",
5782                        vmcs_read16(GUEST_INTR_STATUS));
5783         if (vmcs_read32(VM_ENTRY_MSR_LOAD_COUNT) > 0)
5784                 vmx_dump_msrs("guest autoload", &vmx->msr_autoload.guest);
5785         if (vmcs_read32(VM_EXIT_MSR_STORE_COUNT) > 0)
5786                 vmx_dump_msrs("guest autostore", &vmx->msr_autostore.guest);
5787
5788         pr_err("*** Host State ***\n");
5789         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5790                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5791         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5792                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5793                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5794                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5795                vmcs_read16(HOST_TR_SELECTOR));
5796         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5797                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5798                vmcs_readl(HOST_TR_BASE));
5799         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5800                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5801         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5802                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5803                vmcs_readl(HOST_CR4));
5804         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5805                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5806                vmcs_read32(HOST_IA32_SYSENTER_CS),
5807                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5808         if (vmexit_ctl & VM_EXIT_LOAD_IA32_EFER)
5809                 pr_err("EFER= 0x%016llx\n", vmcs_read64(HOST_IA32_EFER));
5810         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PAT)
5811                 pr_err("PAT = 0x%016llx\n", vmcs_read64(HOST_IA32_PAT));
5812         if (cpu_has_load_perf_global_ctrl() &&
5813             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5814                 pr_err("PerfGlobCtl = 0x%016llx\n",
5815                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5816         if (vmcs_read32(VM_EXIT_MSR_LOAD_COUNT) > 0)
5817                 vmx_dump_msrs("host autoload", &vmx->msr_autoload.host);
5818
5819         pr_err("*** Control State ***\n");
5820         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5821                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5822         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5823         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5824                vmcs_read32(EXCEPTION_BITMAP),
5825                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5826                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5827         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5828                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5829                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5830                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5831         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5832                vmcs_read32(VM_EXIT_INTR_INFO),
5833                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5834                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5835         pr_err("        reason=%08x qualification=%016lx\n",
5836                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5837         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5838                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5839                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5840         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5841         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5842                 pr_err("TSC Multiplier = 0x%016llx\n",
5843                        vmcs_read64(TSC_MULTIPLIER));
5844         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5845                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5846                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5847                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5848                 }
5849                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5850                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5851                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5852                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5853         }
5854         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5855                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5856         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5857                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5858         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5859                 pr_err("PLE Gap=%08x Window=%08x\n",
5860                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5861         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5862                 pr_err("Virtual processor ID = 0x%04x\n",
5863                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5864 }
5865
5866 /*
5867  * The guest has exited.  See if we can fix it or if we need userspace
5868  * assistance.
5869  */
5870 static int __vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5871 {
5872         struct vcpu_vmx *vmx = to_vmx(vcpu);
5873         union vmx_exit_reason exit_reason = vmx->exit_reason;
5874         u32 vectoring_info = vmx->idt_vectoring_info;
5875         u16 exit_handler_index;
5876
5877         /*
5878          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5879          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5880          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5881          * mode as if vcpus is in root mode, the PML buffer must has been
5882          * flushed already.  Note, PML is never enabled in hardware while
5883          * running L2.
5884          */
5885         if (enable_pml && !is_guest_mode(vcpu))
5886                 vmx_flush_pml_buffer(vcpu);
5887
5888         /*
5889          * We should never reach this point with a pending nested VM-Enter, and
5890          * more specifically emulation of L2 due to invalid guest state (see
5891          * below) should never happen as that means we incorrectly allowed a
5892          * nested VM-Enter with an invalid vmcs12.
5893          */
5894         if (KVM_BUG_ON(vmx->nested.nested_run_pending, vcpu->kvm))
5895                 return -EIO;
5896
5897         /* If guest state is invalid, start emulating */
5898         if (vmx->emulation_required)
5899                 return handle_invalid_guest_state(vcpu);
5900
5901         if (is_guest_mode(vcpu)) {
5902                 /*
5903                  * PML is never enabled when running L2, bail immediately if a
5904                  * PML full exit occurs as something is horribly wrong.
5905                  */
5906                 if (exit_reason.basic == EXIT_REASON_PML_FULL)
5907                         goto unexpected_vmexit;
5908
5909                 /*
5910                  * The host physical addresses of some pages of guest memory
5911                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5912                  * Page). The CPU may write to these pages via their host
5913                  * physical address while L2 is running, bypassing any
5914                  * address-translation-based dirty tracking (e.g. EPT write
5915                  * protection).
5916                  *
5917                  * Mark them dirty on every exit from L2 to prevent them from
5918                  * getting out of sync with dirty tracking.
5919                  */
5920                 nested_mark_vmcs12_pages_dirty(vcpu);
5921
5922                 if (nested_vmx_reflect_vmexit(vcpu))
5923                         return 1;
5924         }
5925
5926         if (exit_reason.failed_vmentry) {
5927                 dump_vmcs(vcpu);
5928                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5929                 vcpu->run->fail_entry.hardware_entry_failure_reason
5930                         = exit_reason.full;
5931                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5932                 return 0;
5933         }
5934
5935         if (unlikely(vmx->fail)) {
5936                 dump_vmcs(vcpu);
5937                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5938                 vcpu->run->fail_entry.hardware_entry_failure_reason
5939                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5940                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5941                 return 0;
5942         }
5943
5944         /*
5945          * Note:
5946          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5947          * delivery event since it indicates guest is accessing MMIO.
5948          * The vm-exit can be triggered again after return to guest that
5949          * will cause infinite loop.
5950          */
5951         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5952             (exit_reason.basic != EXIT_REASON_EXCEPTION_NMI &&
5953              exit_reason.basic != EXIT_REASON_EPT_VIOLATION &&
5954              exit_reason.basic != EXIT_REASON_PML_FULL &&
5955              exit_reason.basic != EXIT_REASON_APIC_ACCESS &&
5956              exit_reason.basic != EXIT_REASON_TASK_SWITCH)) {
5957                 int ndata = 3;
5958
5959                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5960                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5961                 vcpu->run->internal.data[0] = vectoring_info;
5962                 vcpu->run->internal.data[1] = exit_reason.full;
5963                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5964                 if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG) {
5965                         vcpu->run->internal.data[ndata++] =
5966                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5967                 }
5968                 vcpu->run->internal.data[ndata++] = vcpu->arch.last_vmentry_cpu;
5969                 vcpu->run->internal.ndata = ndata;
5970                 return 0;
5971         }
5972
5973         if (unlikely(!enable_vnmi &&
5974                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5975                 if (!vmx_interrupt_blocked(vcpu)) {
5976                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5977                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5978                            vcpu->arch.nmi_pending) {
5979                         /*
5980                          * This CPU don't support us in finding the end of an
5981                          * NMI-blocked window if the guest runs with IRQs
5982                          * disabled. So we pull the trigger after 1 s of
5983                          * futile waiting, but inform the user about this.
5984                          */
5985                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5986                                "state on VCPU %d after 1 s timeout\n",
5987                                __func__, vcpu->vcpu_id);
5988                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5989                 }
5990         }
5991
5992         if (exit_fastpath != EXIT_FASTPATH_NONE)
5993                 return 1;
5994
5995         if (exit_reason.basic >= kvm_vmx_max_exit_handlers)
5996                 goto unexpected_vmexit;
5997 #ifdef CONFIG_RETPOLINE
5998         if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
5999                 return kvm_emulate_wrmsr(vcpu);
6000         else if (exit_reason.basic == EXIT_REASON_PREEMPTION_TIMER)
6001                 return handle_preemption_timer(vcpu);
6002         else if (exit_reason.basic == EXIT_REASON_INTERRUPT_WINDOW)
6003                 return handle_interrupt_window(vcpu);
6004         else if (exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6005                 return handle_external_interrupt(vcpu);
6006         else if (exit_reason.basic == EXIT_REASON_HLT)
6007                 return kvm_emulate_halt(vcpu);
6008         else if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG)
6009                 return handle_ept_misconfig(vcpu);
6010 #endif
6011
6012         exit_handler_index = array_index_nospec((u16)exit_reason.basic,
6013                                                 kvm_vmx_max_exit_handlers);
6014         if (!kvm_vmx_exit_handlers[exit_handler_index])
6015                 goto unexpected_vmexit;
6016
6017         return kvm_vmx_exit_handlers[exit_handler_index](vcpu);
6018
6019 unexpected_vmexit:
6020         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
6021                     exit_reason.full);
6022         dump_vmcs(vcpu);
6023         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6024         vcpu->run->internal.suberror =
6025                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6026         vcpu->run->internal.ndata = 2;
6027         vcpu->run->internal.data[0] = exit_reason.full;
6028         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6029         return 0;
6030 }
6031
6032 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6033 {
6034         int ret = __vmx_handle_exit(vcpu, exit_fastpath);
6035
6036         /*
6037          * Exit to user space when bus lock detected to inform that there is
6038          * a bus lock in guest.
6039          */
6040         if (to_vmx(vcpu)->exit_reason.bus_lock_detected) {
6041                 if (ret > 0)
6042                         vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
6043
6044                 vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
6045                 return 0;
6046         }
6047         return ret;
6048 }
6049
6050 /*
6051  * Software based L1D cache flush which is used when microcode providing
6052  * the cache control MSR is not loaded.
6053  *
6054  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6055  * flush it is required to read in 64 KiB because the replacement algorithm
6056  * is not exactly LRU. This could be sized at runtime via topology
6057  * information but as all relevant affected CPUs have 32KiB L1D cache size
6058  * there is no point in doing so.
6059  */
6060 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6061 {
6062         int size = PAGE_SIZE << L1D_CACHE_ORDER;
6063
6064         /*
6065          * This code is only executed when the the flush mode is 'cond' or
6066          * 'always'
6067          */
6068         if (static_branch_likely(&vmx_l1d_flush_cond)) {
6069                 bool flush_l1d;
6070
6071                 /*
6072                  * Clear the per-vcpu flush bit, it gets set again
6073                  * either from vcpu_run() or from one of the unsafe
6074                  * VMEXIT handlers.
6075                  */
6076                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6077                 vcpu->arch.l1tf_flush_l1d = false;
6078
6079                 /*
6080                  * Clear the per-cpu flush bit, it gets set again from
6081                  * the interrupt handlers.
6082                  */
6083                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6084                 kvm_clear_cpu_l1tf_flush_l1d();
6085
6086                 if (!flush_l1d)
6087                         return;
6088         }
6089
6090         vcpu->stat.l1d_flush++;
6091
6092         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6093                 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6094                 return;
6095         }
6096
6097         asm volatile(
6098                 /* First ensure the pages are in the TLB */
6099                 "xorl   %%eax, %%eax\n"
6100                 ".Lpopulate_tlb:\n\t"
6101                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6102                 "addl   $4096, %%eax\n\t"
6103                 "cmpl   %%eax, %[size]\n\t"
6104                 "jne    .Lpopulate_tlb\n\t"
6105                 "xorl   %%eax, %%eax\n\t"
6106                 "cpuid\n\t"
6107                 /* Now fill the cache */
6108                 "xorl   %%eax, %%eax\n"
6109                 ".Lfill_cache:\n"
6110                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6111                 "addl   $64, %%eax\n\t"
6112                 "cmpl   %%eax, %[size]\n\t"
6113                 "jne    .Lfill_cache\n\t"
6114                 "lfence\n"
6115                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6116                     [size] "r" (size)
6117                 : "eax", "ebx", "ecx", "edx");
6118 }
6119
6120 static void vmx_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6121 {
6122         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6123         int tpr_threshold;
6124
6125         if (is_guest_mode(vcpu) &&
6126                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6127                 return;
6128
6129         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6130         if (is_guest_mode(vcpu))
6131                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6132         else
6133                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6134 }
6135
6136 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6137 {
6138         struct vcpu_vmx *vmx = to_vmx(vcpu);
6139         u32 sec_exec_control;
6140
6141         if (!lapic_in_kernel(vcpu))
6142                 return;
6143
6144         if (!flexpriority_enabled &&
6145             !cpu_has_vmx_virtualize_x2apic_mode())
6146                 return;
6147
6148         /* Postpone execution until vmcs01 is the current VMCS. */
6149         if (is_guest_mode(vcpu)) {
6150                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6151                 return;
6152         }
6153
6154         sec_exec_control = secondary_exec_controls_get(vmx);
6155         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6156                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6157
6158         switch (kvm_get_apic_mode(vcpu)) {
6159         case LAPIC_MODE_INVALID:
6160                 WARN_ONCE(true, "Invalid local APIC state");
6161                 break;
6162         case LAPIC_MODE_DISABLED:
6163                 break;
6164         case LAPIC_MODE_XAPIC:
6165                 if (flexpriority_enabled) {
6166                         sec_exec_control |=
6167                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6168                         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6169
6170                         /*
6171                          * Flush the TLB, reloading the APIC access page will
6172                          * only do so if its physical address has changed, but
6173                          * the guest may have inserted a non-APIC mapping into
6174                          * the TLB while the APIC access page was disabled.
6175                          */
6176                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6177                 }
6178                 break;
6179         case LAPIC_MODE_X2APIC:
6180                 if (cpu_has_vmx_virtualize_x2apic_mode())
6181                         sec_exec_control |=
6182                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6183                 break;
6184         }
6185         secondary_exec_controls_set(vmx, sec_exec_control);
6186
6187         vmx_update_msr_bitmap_x2apic(vcpu);
6188 }
6189
6190 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6191 {
6192         struct page *page;
6193
6194         /* Defer reload until vmcs01 is the current VMCS. */
6195         if (is_guest_mode(vcpu)) {
6196                 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6197                 return;
6198         }
6199
6200         if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6201             SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6202                 return;
6203
6204         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6205         if (is_error_page(page))
6206                 return;
6207
6208         vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6209         vmx_flush_tlb_current(vcpu);
6210
6211         /*
6212          * Do not pin apic access page in memory, the MMU notifier
6213          * will call us again if it is migrated or swapped out.
6214          */
6215         put_page(page);
6216 }
6217
6218 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6219 {
6220         u16 status;
6221         u8 old;
6222
6223         if (max_isr == -1)
6224                 max_isr = 0;
6225
6226         status = vmcs_read16(GUEST_INTR_STATUS);
6227         old = status >> 8;
6228         if (max_isr != old) {
6229                 status &= 0xff;
6230                 status |= max_isr << 8;
6231                 vmcs_write16(GUEST_INTR_STATUS, status);
6232         }
6233 }
6234
6235 static void vmx_set_rvi(int vector)
6236 {
6237         u16 status;
6238         u8 old;
6239
6240         if (vector == -1)
6241                 vector = 0;
6242
6243         status = vmcs_read16(GUEST_INTR_STATUS);
6244         old = (u8)status & 0xff;
6245         if ((u8)vector != old) {
6246                 status &= ~0xff;
6247                 status |= (u8)vector;
6248                 vmcs_write16(GUEST_INTR_STATUS, status);
6249         }
6250 }
6251
6252 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6253 {
6254         /*
6255          * When running L2, updating RVI is only relevant when
6256          * vmcs12 virtual-interrupt-delivery enabled.
6257          * However, it can be enabled only when L1 also
6258          * intercepts external-interrupts and in that case
6259          * we should not update vmcs02 RVI but instead intercept
6260          * interrupt. Therefore, do nothing when running L2.
6261          */
6262         if (!is_guest_mode(vcpu))
6263                 vmx_set_rvi(max_irr);
6264 }
6265
6266 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6267 {
6268         struct vcpu_vmx *vmx = to_vmx(vcpu);
6269         int max_irr;
6270         bool got_posted_interrupt;
6271
6272         if (KVM_BUG_ON(!enable_apicv, vcpu->kvm))
6273                 return -EIO;
6274
6275         if (pi_test_on(&vmx->pi_desc)) {
6276                 pi_clear_on(&vmx->pi_desc);
6277                 /*
6278                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6279                  * But on x86 this is just a compiler barrier anyway.
6280                  */
6281                 smp_mb__after_atomic();
6282                 got_posted_interrupt =
6283                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6284         } else {
6285                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6286                 got_posted_interrupt = false;
6287         }
6288
6289         /*
6290          * Newly recognized interrupts are injected via either virtual interrupt
6291          * delivery (RVI) or KVM_REQ_EVENT.  Virtual interrupt delivery is
6292          * disabled in two cases:
6293          *
6294          * 1) If L2 is running and the vCPU has a new pending interrupt.  If L1
6295          * wants to exit on interrupts, KVM_REQ_EVENT is needed to synthesize a
6296          * VM-Exit to L1.  If L1 doesn't want to exit, the interrupt is injected
6297          * into L2, but KVM doesn't use virtual interrupt delivery to inject
6298          * interrupts into L2, and so KVM_REQ_EVENT is again needed.
6299          *
6300          * 2) If APICv is disabled for this vCPU, assigned devices may still
6301          * attempt to post interrupts.  The posted interrupt vector will cause
6302          * a VM-Exit and the subsequent entry will call sync_pir_to_irr.
6303          */
6304         if (!is_guest_mode(vcpu) && kvm_vcpu_apicv_active(vcpu))
6305                 vmx_set_rvi(max_irr);
6306         else if (got_posted_interrupt)
6307                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6308
6309         return max_irr;
6310 }
6311
6312 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6313 {
6314         if (!kvm_vcpu_apicv_active(vcpu))
6315                 return;
6316
6317         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6318         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6319         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6320         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6321 }
6322
6323 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6324 {
6325         struct vcpu_vmx *vmx = to_vmx(vcpu);
6326
6327         pi_clear_on(&vmx->pi_desc);
6328         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6329 }
6330
6331 void vmx_do_interrupt_nmi_irqoff(unsigned long entry);
6332
6333 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu,
6334                                         unsigned long entry)
6335 {
6336         kvm_before_interrupt(vcpu);
6337         vmx_do_interrupt_nmi_irqoff(entry);
6338         kvm_after_interrupt(vcpu);
6339 }
6340
6341 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6342 {
6343         const unsigned long nmi_entry = (unsigned long)asm_exc_nmi_noist;
6344         u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6345
6346         /* if exit due to PF check for async PF */
6347         if (is_page_fault(intr_info))
6348                 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6349         /* Handle machine checks before interrupts are enabled */
6350         else if (is_machine_check(intr_info))
6351                 kvm_machine_check();
6352         /* We need to handle NMIs before interrupts are enabled */
6353         else if (is_nmi(intr_info))
6354                 handle_interrupt_nmi_irqoff(&vmx->vcpu, nmi_entry);
6355 }
6356
6357 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6358 {
6359         u32 intr_info = vmx_get_intr_info(vcpu);
6360         unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK;
6361         gate_desc *desc = (gate_desc *)host_idt_base + vector;
6362
6363         if (KVM_BUG(!is_external_intr(intr_info), vcpu->kvm,
6364             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6365                 return;
6366
6367         handle_interrupt_nmi_irqoff(vcpu, gate_offset(desc));
6368 }
6369
6370 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6371 {
6372         struct vcpu_vmx *vmx = to_vmx(vcpu);
6373
6374         if (vmx->emulation_required)
6375                 return;
6376
6377         if (vmx->exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6378                 handle_external_interrupt_irqoff(vcpu);
6379         else if (vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI)
6380                 handle_exception_nmi_irqoff(vmx);
6381 }
6382
6383 /*
6384  * The kvm parameter can be NULL (module initialization, or invocation before
6385  * VM creation). Be sure to check the kvm parameter before using it.
6386  */
6387 static bool vmx_has_emulated_msr(struct kvm *kvm, u32 index)
6388 {
6389         switch (index) {
6390         case MSR_IA32_SMBASE:
6391                 /*
6392                  * We cannot do SMM unless we can run the guest in big
6393                  * real mode.
6394                  */
6395                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6396         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6397                 return nested;
6398         case MSR_AMD64_VIRT_SPEC_CTRL:
6399         case MSR_AMD64_TSC_RATIO:
6400                 /* This is AMD only.  */
6401                 return false;
6402         default:
6403                 return true;
6404         }
6405 }
6406
6407 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6408 {
6409         u32 exit_intr_info;
6410         bool unblock_nmi;
6411         u8 vector;
6412         bool idtv_info_valid;
6413
6414         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6415
6416         if (enable_vnmi) {
6417                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6418                         return;
6419
6420                 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6421                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6422                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6423                 /*
6424                  * SDM 3: 27.7.1.2 (September 2008)
6425                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6426                  * a guest IRET fault.
6427                  * SDM 3: 23.2.2 (September 2008)
6428                  * Bit 12 is undefined in any of the following cases:
6429                  *  If the VM exit sets the valid bit in the IDT-vectoring
6430                  *   information field.
6431                  *  If the VM exit is due to a double fault.
6432                  */
6433                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6434                     vector != DF_VECTOR && !idtv_info_valid)
6435                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6436                                       GUEST_INTR_STATE_NMI);
6437                 else
6438                         vmx->loaded_vmcs->nmi_known_unmasked =
6439                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6440                                   & GUEST_INTR_STATE_NMI);
6441         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6442                 vmx->loaded_vmcs->vnmi_blocked_time +=
6443                         ktime_to_ns(ktime_sub(ktime_get(),
6444                                               vmx->loaded_vmcs->entry_time));
6445 }
6446
6447 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6448                                       u32 idt_vectoring_info,
6449                                       int instr_len_field,
6450                                       int error_code_field)
6451 {
6452         u8 vector;
6453         int type;
6454         bool idtv_info_valid;
6455
6456         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6457
6458         vcpu->arch.nmi_injected = false;
6459         kvm_clear_exception_queue(vcpu);
6460         kvm_clear_interrupt_queue(vcpu);
6461
6462         if (!idtv_info_valid)
6463                 return;
6464
6465         kvm_make_request(KVM_REQ_EVENT, vcpu);
6466
6467         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6468         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6469
6470         switch (type) {
6471         case INTR_TYPE_NMI_INTR:
6472                 vcpu->arch.nmi_injected = true;
6473                 /*
6474                  * SDM 3: 27.7.1.2 (September 2008)
6475                  * Clear bit "block by NMI" before VM entry if a NMI
6476                  * delivery faulted.
6477                  */
6478                 vmx_set_nmi_mask(vcpu, false);
6479                 break;
6480         case INTR_TYPE_SOFT_EXCEPTION:
6481                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6482                 fallthrough;
6483         case INTR_TYPE_HARD_EXCEPTION:
6484                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6485                         u32 err = vmcs_read32(error_code_field);
6486                         kvm_requeue_exception_e(vcpu, vector, err);
6487                 } else
6488                         kvm_requeue_exception(vcpu, vector);
6489                 break;
6490         case INTR_TYPE_SOFT_INTR:
6491                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6492                 fallthrough;
6493         case INTR_TYPE_EXT_INTR:
6494                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6495                 break;
6496         default:
6497                 break;
6498         }
6499 }
6500
6501 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6502 {
6503         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6504                                   VM_EXIT_INSTRUCTION_LEN,
6505                                   IDT_VECTORING_ERROR_CODE);
6506 }
6507
6508 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6509 {
6510         __vmx_complete_interrupts(vcpu,
6511                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6512                                   VM_ENTRY_INSTRUCTION_LEN,
6513                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6514
6515         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6516 }
6517
6518 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6519 {
6520         int i, nr_msrs;
6521         struct perf_guest_switch_msr *msrs;
6522
6523         /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
6524         msrs = perf_guest_get_msrs(&nr_msrs);
6525         if (!msrs)
6526                 return;
6527
6528         for (i = 0; i < nr_msrs; i++)
6529                 if (msrs[i].host == msrs[i].guest)
6530                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6531                 else
6532                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6533                                         msrs[i].host, false);
6534 }
6535
6536 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6537 {
6538         struct vcpu_vmx *vmx = to_vmx(vcpu);
6539         u64 tscl;
6540         u32 delta_tsc;
6541
6542         if (vmx->req_immediate_exit) {
6543                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6544                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6545         } else if (vmx->hv_deadline_tsc != -1) {
6546                 tscl = rdtsc();
6547                 if (vmx->hv_deadline_tsc > tscl)
6548                         /* set_hv_timer ensures the delta fits in 32-bits */
6549                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6550                                 cpu_preemption_timer_multi);
6551                 else
6552                         delta_tsc = 0;
6553
6554                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6555                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6556         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6557                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6558                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6559         }
6560 }
6561
6562 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6563 {
6564         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6565                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6566                 vmcs_writel(HOST_RSP, host_rsp);
6567         }
6568 }
6569
6570 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6571 {
6572         switch (to_vmx(vcpu)->exit_reason.basic) {
6573         case EXIT_REASON_MSR_WRITE:
6574                 return handle_fastpath_set_msr_irqoff(vcpu);
6575         case EXIT_REASON_PREEMPTION_TIMER:
6576                 return handle_fastpath_preemption_timer(vcpu);
6577         default:
6578                 return EXIT_FASTPATH_NONE;
6579         }
6580 }
6581
6582 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6583                                         struct vcpu_vmx *vmx)
6584 {
6585         kvm_guest_enter_irqoff();
6586
6587         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6588         if (static_branch_unlikely(&vmx_l1d_should_flush))
6589                 vmx_l1d_flush(vcpu);
6590         else if (static_branch_unlikely(&mds_user_clear))
6591                 mds_clear_cpu_buffers();
6592
6593         if (vcpu->arch.cr2 != native_read_cr2())
6594                 native_write_cr2(vcpu->arch.cr2);
6595
6596         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6597                                    vmx->loaded_vmcs->launched);
6598
6599         vcpu->arch.cr2 = native_read_cr2();
6600
6601         kvm_guest_exit_irqoff();
6602 }
6603
6604 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6605 {
6606         struct vcpu_vmx *vmx = to_vmx(vcpu);
6607         unsigned long cr3, cr4;
6608
6609         /* Record the guest's net vcpu time for enforced NMI injections. */
6610         if (unlikely(!enable_vnmi &&
6611                      vmx->loaded_vmcs->soft_vnmi_blocked))
6612                 vmx->loaded_vmcs->entry_time = ktime_get();
6613
6614         /*
6615          * Don't enter VMX if guest state is invalid, let the exit handler
6616          * start emulation until we arrive back to a valid state.  Synthesize a
6617          * consistency check VM-Exit due to invalid guest state and bail.
6618          */
6619         if (unlikely(vmx->emulation_required)) {
6620
6621                 /* We don't emulate invalid state of a nested guest */
6622                 vmx->fail = is_guest_mode(vcpu);
6623
6624                 vmx->exit_reason.full = EXIT_REASON_INVALID_STATE;
6625                 vmx->exit_reason.failed_vmentry = 1;
6626                 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
6627                 vmx->exit_qualification = ENTRY_FAIL_DEFAULT;
6628                 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
6629                 vmx->exit_intr_info = 0;
6630                 return EXIT_FASTPATH_NONE;
6631         }
6632
6633         trace_kvm_entry(vcpu);
6634
6635         if (vmx->ple_window_dirty) {
6636                 vmx->ple_window_dirty = false;
6637                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6638         }
6639
6640         /*
6641          * We did this in prepare_switch_to_guest, because it needs to
6642          * be within srcu_read_lock.
6643          */
6644         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6645
6646         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6647                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6648         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6649                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6650
6651         cr3 = __get_current_cr3_fast();
6652         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6653                 vmcs_writel(HOST_CR3, cr3);
6654                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6655         }
6656
6657         cr4 = cr4_read_shadow();
6658         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6659                 vmcs_writel(HOST_CR4, cr4);
6660                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6661         }
6662
6663         /* When KVM_DEBUGREG_WONT_EXIT, dr6 is accessible in guest. */
6664         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
6665                 set_debugreg(vcpu->arch.dr6, 6);
6666
6667         /* When single-stepping over STI and MOV SS, we must clear the
6668          * corresponding interruptibility bits in the guest state. Otherwise
6669          * vmentry fails as it then expects bit 14 (BS) in pending debug
6670          * exceptions being set, but that's not correct for the guest debugging
6671          * case. */
6672         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6673                 vmx_set_interrupt_shadow(vcpu, 0);
6674
6675         kvm_load_guest_xsave_state(vcpu);
6676
6677         pt_guest_enter(vmx);
6678
6679         atomic_switch_perf_msrs(vmx);
6680         if (intel_pmu_lbr_is_enabled(vcpu))
6681                 vmx_passthrough_lbr_msrs(vcpu);
6682
6683         if (enable_preemption_timer)
6684                 vmx_update_hv_timer(vcpu);
6685
6686         kvm_wait_lapic_expire(vcpu);
6687
6688         /*
6689          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6690          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6691          * is no need to worry about the conditional branch over the wrmsr
6692          * being speculatively taken.
6693          */
6694         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6695
6696         /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6697         vmx_vcpu_enter_exit(vcpu, vmx);
6698
6699         /*
6700          * We do not use IBRS in the kernel. If this vCPU has used the
6701          * SPEC_CTRL MSR it may have left it on; save the value and
6702          * turn it off. This is much more efficient than blindly adding
6703          * it to the atomic save/restore list. Especially as the former
6704          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6705          *
6706          * For non-nested case:
6707          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6708          * save it.
6709          *
6710          * For nested case:
6711          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6712          * save it.
6713          */
6714         if (unlikely(!msr_write_intercepted(vmx, MSR_IA32_SPEC_CTRL)))
6715                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6716
6717         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6718
6719         /* All fields are clean at this point */
6720         if (static_branch_unlikely(&enable_evmcs)) {
6721                 current_evmcs->hv_clean_fields |=
6722                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6723
6724                 current_evmcs->hv_vp_id = kvm_hv_get_vpindex(vcpu);
6725         }
6726
6727         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6728         if (vmx->host_debugctlmsr)
6729                 update_debugctlmsr(vmx->host_debugctlmsr);
6730
6731 #ifndef CONFIG_X86_64
6732         /*
6733          * The sysexit path does not restore ds/es, so we must set them to
6734          * a reasonable value ourselves.
6735          *
6736          * We can't defer this to vmx_prepare_switch_to_host() since that
6737          * function may be executed in interrupt context, which saves and
6738          * restore segments around it, nullifying its effect.
6739          */
6740         loadsegment(ds, __USER_DS);
6741         loadsegment(es, __USER_DS);
6742 #endif
6743
6744         vmx_register_cache_reset(vcpu);
6745
6746         pt_guest_exit(vmx);
6747
6748         kvm_load_host_xsave_state(vcpu);
6749
6750         if (is_guest_mode(vcpu)) {
6751                 /*
6752                  * Track VMLAUNCH/VMRESUME that have made past guest state
6753                  * checking.
6754                  */
6755                 if (vmx->nested.nested_run_pending &&
6756                     !vmx->exit_reason.failed_vmentry)
6757                         ++vcpu->stat.nested_run;
6758
6759                 vmx->nested.nested_run_pending = 0;
6760         }
6761
6762         vmx->idt_vectoring_info = 0;
6763
6764         if (unlikely(vmx->fail)) {
6765                 vmx->exit_reason.full = 0xdead;
6766                 return EXIT_FASTPATH_NONE;
6767         }
6768
6769         vmx->exit_reason.full = vmcs_read32(VM_EXIT_REASON);
6770         if (unlikely((u16)vmx->exit_reason.basic == EXIT_REASON_MCE_DURING_VMENTRY))
6771                 kvm_machine_check();
6772
6773         if (likely(!vmx->exit_reason.failed_vmentry))
6774                 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6775
6776         trace_kvm_exit(vcpu, KVM_ISA_VMX);
6777
6778         if (unlikely(vmx->exit_reason.failed_vmentry))
6779                 return EXIT_FASTPATH_NONE;
6780
6781         vmx->loaded_vmcs->launched = 1;
6782
6783         vmx_recover_nmi_blocking(vmx);
6784         vmx_complete_interrupts(vmx);
6785
6786         if (is_guest_mode(vcpu))
6787                 return EXIT_FASTPATH_NONE;
6788
6789         return vmx_exit_handlers_fastpath(vcpu);
6790 }
6791
6792 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6793 {
6794         struct vcpu_vmx *vmx = to_vmx(vcpu);
6795
6796         if (enable_pml)
6797                 vmx_destroy_pml_buffer(vmx);
6798         free_vpid(vmx->vpid);
6799         nested_vmx_free_vcpu(vcpu);
6800         free_loaded_vmcs(vmx->loaded_vmcs);
6801 }
6802
6803 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6804 {
6805         struct vmx_uret_msr *tsx_ctrl;
6806         struct vcpu_vmx *vmx;
6807         int i, err;
6808
6809         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6810         vmx = to_vmx(vcpu);
6811
6812         err = -ENOMEM;
6813
6814         vmx->vpid = allocate_vpid();
6815
6816         /*
6817          * If PML is turned on, failure on enabling PML just results in failure
6818          * of creating the vcpu, therefore we can simplify PML logic (by
6819          * avoiding dealing with cases, such as enabling PML partially on vcpus
6820          * for the guest), etc.
6821          */
6822         if (enable_pml) {
6823                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6824                 if (!vmx->pml_pg)
6825                         goto free_vpid;
6826         }
6827
6828         for (i = 0; i < kvm_nr_uret_msrs; ++i)
6829                 vmx->guest_uret_msrs[i].mask = -1ull;
6830         if (boot_cpu_has(X86_FEATURE_RTM)) {
6831                 /*
6832                  * TSX_CTRL_CPUID_CLEAR is handled in the CPUID interception.
6833                  * Keep the host value unchanged to avoid changing CPUID bits
6834                  * under the host kernel's feet.
6835                  */
6836                 tsx_ctrl = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
6837                 if (tsx_ctrl)
6838                         tsx_ctrl->mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6839         }
6840
6841         err = alloc_loaded_vmcs(&vmx->vmcs01);
6842         if (err < 0)
6843                 goto free_pml;
6844
6845         /* The MSR bitmap starts with all ones */
6846         bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6847         bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6848
6849         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
6850 #ifdef CONFIG_X86_64
6851         vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
6852         vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
6853         vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6854 #endif
6855         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6856         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6857         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6858         if (kvm_cstate_in_guest(vcpu->kvm)) {
6859                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
6860                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6861                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6862                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6863         }
6864
6865         vmx->loaded_vmcs = &vmx->vmcs01;
6866
6867         if (cpu_need_virtualize_apic_accesses(vcpu)) {
6868                 err = alloc_apic_access_page(vcpu->kvm);
6869                 if (err)
6870                         goto free_vmcs;
6871         }
6872
6873         if (enable_ept && !enable_unrestricted_guest) {
6874                 err = init_rmode_identity_map(vcpu->kvm);
6875                 if (err)
6876                         goto free_vmcs;
6877         }
6878
6879         return 0;
6880
6881 free_vmcs:
6882         free_loaded_vmcs(vmx->loaded_vmcs);
6883 free_pml:
6884         vmx_destroy_pml_buffer(vmx);
6885 free_vpid:
6886         free_vpid(vmx->vpid);
6887         return err;
6888 }
6889
6890 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6891 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6892
6893 static int vmx_vm_init(struct kvm *kvm)
6894 {
6895         if (!ple_gap)
6896                 kvm->arch.pause_in_guest = true;
6897
6898         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6899                 switch (l1tf_mitigation) {
6900                 case L1TF_MITIGATION_OFF:
6901                 case L1TF_MITIGATION_FLUSH_NOWARN:
6902                         /* 'I explicitly don't care' is set */
6903                         break;
6904                 case L1TF_MITIGATION_FLUSH:
6905                 case L1TF_MITIGATION_FLUSH_NOSMT:
6906                 case L1TF_MITIGATION_FULL:
6907                         /*
6908                          * Warn upon starting the first VM in a potentially
6909                          * insecure environment.
6910                          */
6911                         if (sched_smt_active())
6912                                 pr_warn_once(L1TF_MSG_SMT);
6913                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6914                                 pr_warn_once(L1TF_MSG_L1D);
6915                         break;
6916                 case L1TF_MITIGATION_FULL_FORCE:
6917                         /* Flush is enforced */
6918                         break;
6919                 }
6920         }
6921         return 0;
6922 }
6923
6924 static int __init vmx_check_processor_compat(void)
6925 {
6926         struct vmcs_config vmcs_conf;
6927         struct vmx_capability vmx_cap;
6928
6929         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6930             !this_cpu_has(X86_FEATURE_VMX)) {
6931                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6932                 return -EIO;
6933         }
6934
6935         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6936                 return -EIO;
6937         if (nested)
6938                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6939         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6940                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6941                                 smp_processor_id());
6942                 return -EIO;
6943         }
6944         return 0;
6945 }
6946
6947 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6948 {
6949         u8 cache;
6950         u64 ipat = 0;
6951
6952         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6953          * memory aliases with conflicting memory types and sometimes MCEs.
6954          * We have to be careful as to what are honored and when.
6955          *
6956          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
6957          * UC.  The effective memory type is UC or WC depending on guest PAT.
6958          * This was historically the source of MCEs and we want to be
6959          * conservative.
6960          *
6961          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6962          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
6963          * EPT memory type is set to WB.  The effective memory type is forced
6964          * WB.
6965          *
6966          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
6967          * EPT memory type is used to emulate guest CD/MTRR.
6968          */
6969
6970         if (is_mmio) {
6971                 cache = MTRR_TYPE_UNCACHABLE;
6972                 goto exit;
6973         }
6974
6975         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6976                 ipat = VMX_EPT_IPAT_BIT;
6977                 cache = MTRR_TYPE_WRBACK;
6978                 goto exit;
6979         }
6980
6981         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6982                 ipat = VMX_EPT_IPAT_BIT;
6983                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6984                         cache = MTRR_TYPE_WRBACK;
6985                 else
6986                         cache = MTRR_TYPE_UNCACHABLE;
6987                 goto exit;
6988         }
6989
6990         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6991
6992 exit:
6993         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6994 }
6995
6996 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx, u32 new_ctl)
6997 {
6998         /*
6999          * These bits in the secondary execution controls field
7000          * are dynamic, the others are mostly based on the hypervisor
7001          * architecture and the guest's CPUID.  Do not touch the
7002          * dynamic bits.
7003          */
7004         u32 mask =
7005                 SECONDARY_EXEC_SHADOW_VMCS |
7006                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7007                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7008                 SECONDARY_EXEC_DESC;
7009
7010         u32 cur_ctl = secondary_exec_controls_get(vmx);
7011
7012         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7013 }
7014
7015 /*
7016  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7017  * (indicating "allowed-1") if they are supported in the guest's CPUID.
7018  */
7019 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7020 {
7021         struct vcpu_vmx *vmx = to_vmx(vcpu);
7022         struct kvm_cpuid_entry2 *entry;
7023
7024         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7025         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7026
7027 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
7028         if (entry && (entry->_reg & (_cpuid_mask)))                     \
7029                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
7030 } while (0)
7031
7032         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7033         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
7034         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
7035         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
7036         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
7037         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
7038         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
7039         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
7040         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
7041         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
7042         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7043         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
7044         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
7045         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
7046         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
7047
7048         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7049         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
7050         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
7051         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
7052         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
7053         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
7054         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
7055
7056 #undef cr4_fixed1_update
7057 }
7058
7059 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7060 {
7061         struct vcpu_vmx *vmx = to_vmx(vcpu);
7062
7063         if (kvm_mpx_supported()) {
7064                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7065
7066                 if (mpx_enabled) {
7067                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7068                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7069                 } else {
7070                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7071                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7072                 }
7073         }
7074 }
7075
7076 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7077 {
7078         struct vcpu_vmx *vmx = to_vmx(vcpu);
7079         struct kvm_cpuid_entry2 *best = NULL;
7080         int i;
7081
7082         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7083                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7084                 if (!best)
7085                         return;
7086                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7087                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7088                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7089                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7090         }
7091
7092         /* Get the number of configurable Address Ranges for filtering */
7093         vmx->pt_desc.num_address_ranges = intel_pt_validate_cap(vmx->pt_desc.caps,
7094                                                 PT_CAP_num_address_ranges);
7095
7096         /* Initialize and clear the no dependency bits */
7097         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7098                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC |
7099                         RTIT_CTL_BRANCH_EN);
7100
7101         /*
7102          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7103          * will inject an #GP
7104          */
7105         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7106                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7107
7108         /*
7109          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7110          * PSBFreq can be set
7111          */
7112         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7113                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7114                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7115
7116         /*
7117          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn and MTCFreq can be set
7118          */
7119         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7120                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7121                                               RTIT_CTL_MTC_RANGE);
7122
7123         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7124         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7125                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7126                                                         RTIT_CTL_PTW_EN);
7127
7128         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7129         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7130                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7131
7132         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7133         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7134                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7135
7136         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabricEn can be set */
7137         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7138                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7139
7140         /* unmask address range configure area */
7141         for (i = 0; i < vmx->pt_desc.num_address_ranges; i++)
7142                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7143 }
7144
7145 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7146 {
7147         struct vcpu_vmx *vmx = to_vmx(vcpu);
7148
7149         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7150         vcpu->arch.xsaves_enabled = false;
7151
7152         vmx_setup_uret_msrs(vmx);
7153
7154         if (cpu_has_secondary_exec_ctrls())
7155                 vmcs_set_secondary_exec_control(vmx,
7156                                                 vmx_secondary_exec_control(vmx));
7157
7158         if (nested_vmx_allowed(vcpu))
7159                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7160                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7161                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7162         else
7163                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7164                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7165                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7166
7167         if (nested_vmx_allowed(vcpu)) {
7168                 nested_vmx_cr_fixed1_bits_update(vcpu);
7169                 nested_vmx_entry_exit_ctls_update(vcpu);
7170         }
7171
7172         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7173                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7174                 update_intel_pt_cfg(vcpu);
7175
7176         if (boot_cpu_has(X86_FEATURE_RTM)) {
7177                 struct vmx_uret_msr *msr;
7178                 msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
7179                 if (msr) {
7180                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7181                         vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7182                 }
7183         }
7184
7185         set_cr4_guest_host_mask(vmx);
7186
7187         vmx_write_encls_bitmap(vcpu, NULL);
7188         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX))
7189                 vmx->msr_ia32_feature_control_valid_bits |= FEAT_CTL_SGX_ENABLED;
7190         else
7191                 vmx->msr_ia32_feature_control_valid_bits &= ~FEAT_CTL_SGX_ENABLED;
7192
7193         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
7194                 vmx->msr_ia32_feature_control_valid_bits |=
7195                         FEAT_CTL_SGX_LC_ENABLED;
7196         else
7197                 vmx->msr_ia32_feature_control_valid_bits &=
7198                         ~FEAT_CTL_SGX_LC_ENABLED;
7199
7200         /* Refresh #PF interception to account for MAXPHYADDR changes. */
7201         vmx_update_exception_bitmap(vcpu);
7202 }
7203
7204 static __init void vmx_set_cpu_caps(void)
7205 {
7206         kvm_set_cpu_caps();
7207
7208         /* CPUID 0x1 */
7209         if (nested)
7210                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7211
7212         /* CPUID 0x7 */
7213         if (kvm_mpx_supported())
7214                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7215         if (!cpu_has_vmx_invpcid())
7216                 kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
7217         if (vmx_pt_mode_is_host_guest())
7218                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7219
7220         if (!enable_sgx) {
7221                 kvm_cpu_cap_clear(X86_FEATURE_SGX);
7222                 kvm_cpu_cap_clear(X86_FEATURE_SGX_LC);
7223                 kvm_cpu_cap_clear(X86_FEATURE_SGX1);
7224                 kvm_cpu_cap_clear(X86_FEATURE_SGX2);
7225         }
7226
7227         if (vmx_umip_emulated())
7228                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7229
7230         /* CPUID 0xD.1 */
7231         supported_xss = 0;
7232         if (!cpu_has_vmx_xsaves())
7233                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7234
7235         /* CPUID 0x80000001 and 0x7 (RDPID) */
7236         if (!cpu_has_vmx_rdtscp()) {
7237                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7238                 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
7239         }
7240
7241         if (cpu_has_vmx_waitpkg())
7242                 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7243 }
7244
7245 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7246 {
7247         to_vmx(vcpu)->req_immediate_exit = true;
7248 }
7249
7250 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7251                                   struct x86_instruction_info *info)
7252 {
7253         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7254         unsigned short port;
7255         bool intercept;
7256         int size;
7257
7258         if (info->intercept == x86_intercept_in ||
7259             info->intercept == x86_intercept_ins) {
7260                 port = info->src_val;
7261                 size = info->dst_bytes;
7262         } else {
7263                 port = info->dst_val;
7264                 size = info->src_bytes;
7265         }
7266
7267         /*
7268          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7269          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7270          * control.
7271          *
7272          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7273          */
7274         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7275                 intercept = nested_cpu_has(vmcs12,
7276                                            CPU_BASED_UNCOND_IO_EXITING);
7277         else
7278                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7279
7280         /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7281         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7282 }
7283
7284 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7285                                struct x86_instruction_info *info,
7286                                enum x86_intercept_stage stage,
7287                                struct x86_exception *exception)
7288 {
7289         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7290
7291         switch (info->intercept) {
7292         /*
7293          * RDPID causes #UD if disabled through secondary execution controls.
7294          * Because it is marked as EmulateOnUD, we need to intercept it here.
7295          * Note, RDPID is hidden behind ENABLE_RDTSCP.
7296          */
7297         case x86_intercept_rdpid:
7298                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) {
7299                         exception->vector = UD_VECTOR;
7300                         exception->error_code_valid = false;
7301                         return X86EMUL_PROPAGATE_FAULT;
7302                 }
7303                 break;
7304
7305         case x86_intercept_in:
7306         case x86_intercept_ins:
7307         case x86_intercept_out:
7308         case x86_intercept_outs:
7309                 return vmx_check_intercept_io(vcpu, info);
7310
7311         case x86_intercept_lgdt:
7312         case x86_intercept_lidt:
7313         case x86_intercept_lldt:
7314         case x86_intercept_ltr:
7315         case x86_intercept_sgdt:
7316         case x86_intercept_sidt:
7317         case x86_intercept_sldt:
7318         case x86_intercept_str:
7319                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7320                         return X86EMUL_CONTINUE;
7321
7322                 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7323                 break;
7324
7325         /* TODO: check more intercepts... */
7326         default:
7327                 break;
7328         }
7329
7330         return X86EMUL_UNHANDLEABLE;
7331 }
7332
7333 #ifdef CONFIG_X86_64
7334 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7335 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7336                                   u64 divisor, u64 *result)
7337 {
7338         u64 low = a << shift, high = a >> (64 - shift);
7339
7340         /* To avoid the overflow on divq */
7341         if (high >= divisor)
7342                 return 1;
7343
7344         /* Low hold the result, high hold rem which is discarded */
7345         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7346             "rm" (divisor), "0" (low), "1" (high));
7347         *result = low;
7348
7349         return 0;
7350 }
7351
7352 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7353                             bool *expired)
7354 {
7355         struct vcpu_vmx *vmx;
7356         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7357         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7358
7359         vmx = to_vmx(vcpu);
7360         tscl = rdtsc();
7361         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7362         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7363         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7364                                                     ktimer->timer_advance_ns);
7365
7366         if (delta_tsc > lapic_timer_advance_cycles)
7367                 delta_tsc -= lapic_timer_advance_cycles;
7368         else
7369                 delta_tsc = 0;
7370
7371         /* Convert to host delta tsc if tsc scaling is enabled */
7372         if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7373             delta_tsc && u64_shl_div_u64(delta_tsc,
7374                                 kvm_tsc_scaling_ratio_frac_bits,
7375                                 vcpu->arch.l1_tsc_scaling_ratio, &delta_tsc))
7376                 return -ERANGE;
7377
7378         /*
7379          * If the delta tsc can't fit in the 32 bit after the multi shift,
7380          * we can't use the preemption timer.
7381          * It's possible that it fits on later vmentries, but checking
7382          * on every vmentry is costly so we just use an hrtimer.
7383          */
7384         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7385                 return -ERANGE;
7386
7387         vmx->hv_deadline_tsc = tscl + delta_tsc;
7388         *expired = !delta_tsc;
7389         return 0;
7390 }
7391
7392 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7393 {
7394         to_vmx(vcpu)->hv_deadline_tsc = -1;
7395 }
7396 #endif
7397
7398 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7399 {
7400         if (!kvm_pause_in_guest(vcpu->kvm))
7401                 shrink_ple_window(vcpu);
7402 }
7403
7404 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu)
7405 {
7406         struct vcpu_vmx *vmx = to_vmx(vcpu);
7407
7408         if (is_guest_mode(vcpu)) {
7409                 vmx->nested.update_vmcs01_cpu_dirty_logging = true;
7410                 return;
7411         }
7412
7413         /*
7414          * Note, cpu_dirty_logging_count can be changed concurrent with this
7415          * code, but in that case another update request will be made and so
7416          * the guest will never run with a stale PML value.
7417          */
7418         if (vcpu->kvm->arch.cpu_dirty_logging_count)
7419                 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7420         else
7421                 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7422 }
7423
7424 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7425 {
7426         if (pi_pre_block(vcpu))
7427                 return 1;
7428
7429         if (kvm_lapic_hv_timer_in_use(vcpu))
7430                 kvm_lapic_switch_to_sw_timer(vcpu);
7431
7432         return 0;
7433 }
7434
7435 static void vmx_post_block(struct kvm_vcpu *vcpu)
7436 {
7437         if (kvm_x86_ops.set_hv_timer)
7438                 kvm_lapic_switch_to_hv_timer(vcpu);
7439
7440         pi_post_block(vcpu);
7441 }
7442
7443 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7444 {
7445         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7446                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7447                         FEAT_CTL_LMCE_ENABLED;
7448         else
7449                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7450                         ~FEAT_CTL_LMCE_ENABLED;
7451 }
7452
7453 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7454 {
7455         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7456         if (to_vmx(vcpu)->nested.nested_run_pending)
7457                 return -EBUSY;
7458         return !is_smm(vcpu);
7459 }
7460
7461 static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7462 {
7463         struct vcpu_vmx *vmx = to_vmx(vcpu);
7464
7465         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7466         if (vmx->nested.smm.guest_mode)
7467                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7468
7469         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7470         vmx->nested.vmxon = false;
7471         vmx_clear_hlt(vcpu);
7472         return 0;
7473 }
7474
7475 static int vmx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7476 {
7477         struct vcpu_vmx *vmx = to_vmx(vcpu);
7478         int ret;
7479
7480         if (vmx->nested.smm.vmxon) {
7481                 vmx->nested.vmxon = true;
7482                 vmx->nested.smm.vmxon = false;
7483         }
7484
7485         if (vmx->nested.smm.guest_mode) {
7486                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7487                 if (ret)
7488                         return ret;
7489
7490                 vmx->nested.smm.guest_mode = false;
7491         }
7492         return 0;
7493 }
7494
7495 static void vmx_enable_smi_window(struct kvm_vcpu *vcpu)
7496 {
7497         /* RSM will cause a vmexit anyway.  */
7498 }
7499
7500 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7501 {
7502         return to_vmx(vcpu)->nested.vmxon && !is_guest_mode(vcpu);
7503 }
7504
7505 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7506 {
7507         if (is_guest_mode(vcpu)) {
7508                 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7509
7510                 if (hrtimer_try_to_cancel(timer) == 1)
7511                         hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7512         }
7513 }
7514
7515 static void hardware_unsetup(void)
7516 {
7517         kvm_set_posted_intr_wakeup_handler(NULL);
7518
7519         if (nested)
7520                 nested_vmx_hardware_unsetup();
7521
7522         free_kvm_area();
7523 }
7524
7525 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7526 {
7527         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7528                           BIT(APICV_INHIBIT_REASON_HYPERV) |
7529                           BIT(APICV_INHIBIT_REASON_BLOCKIRQ);
7530
7531         return supported & BIT(bit);
7532 }
7533
7534 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7535         .name = "kvm_intel",
7536
7537         .hardware_unsetup = hardware_unsetup,
7538
7539         .hardware_enable = hardware_enable,
7540         .hardware_disable = hardware_disable,
7541         .cpu_has_accelerated_tpr = report_flexpriority,
7542         .has_emulated_msr = vmx_has_emulated_msr,
7543
7544         .vm_size = sizeof(struct kvm_vmx),
7545         .vm_init = vmx_vm_init,
7546
7547         .vcpu_create = vmx_create_vcpu,
7548         .vcpu_free = vmx_free_vcpu,
7549         .vcpu_reset = vmx_vcpu_reset,
7550
7551         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7552         .vcpu_load = vmx_vcpu_load,
7553         .vcpu_put = vmx_vcpu_put,
7554
7555         .update_exception_bitmap = vmx_update_exception_bitmap,
7556         .get_msr_feature = vmx_get_msr_feature,
7557         .get_msr = vmx_get_msr,
7558         .set_msr = vmx_set_msr,
7559         .get_segment_base = vmx_get_segment_base,
7560         .get_segment = vmx_get_segment,
7561         .set_segment = vmx_set_segment,
7562         .get_cpl = vmx_get_cpl,
7563         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7564         .set_cr0 = vmx_set_cr0,
7565         .is_valid_cr4 = vmx_is_valid_cr4,
7566         .set_cr4 = vmx_set_cr4,
7567         .set_efer = vmx_set_efer,
7568         .get_idt = vmx_get_idt,
7569         .set_idt = vmx_set_idt,
7570         .get_gdt = vmx_get_gdt,
7571         .set_gdt = vmx_set_gdt,
7572         .set_dr7 = vmx_set_dr7,
7573         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7574         .cache_reg = vmx_cache_reg,
7575         .get_rflags = vmx_get_rflags,
7576         .set_rflags = vmx_set_rflags,
7577
7578         .tlb_flush_all = vmx_flush_tlb_all,
7579         .tlb_flush_current = vmx_flush_tlb_current,
7580         .tlb_flush_gva = vmx_flush_tlb_gva,
7581         .tlb_flush_guest = vmx_flush_tlb_guest,
7582
7583         .run = vmx_vcpu_run,
7584         .handle_exit = vmx_handle_exit,
7585         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7586         .update_emulated_instruction = vmx_update_emulated_instruction,
7587         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7588         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7589         .patch_hypercall = vmx_patch_hypercall,
7590         .set_irq = vmx_inject_irq,
7591         .set_nmi = vmx_inject_nmi,
7592         .queue_exception = vmx_queue_exception,
7593         .cancel_injection = vmx_cancel_injection,
7594         .interrupt_allowed = vmx_interrupt_allowed,
7595         .nmi_allowed = vmx_nmi_allowed,
7596         .get_nmi_mask = vmx_get_nmi_mask,
7597         .set_nmi_mask = vmx_set_nmi_mask,
7598         .enable_nmi_window = vmx_enable_nmi_window,
7599         .enable_irq_window = vmx_enable_irq_window,
7600         .update_cr8_intercept = vmx_update_cr8_intercept,
7601         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7602         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7603         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7604         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7605         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7606         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7607         .hwapic_irr_update = vmx_hwapic_irr_update,
7608         .hwapic_isr_update = vmx_hwapic_isr_update,
7609         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7610         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7611         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7612         .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
7613
7614         .set_tss_addr = vmx_set_tss_addr,
7615         .set_identity_map_addr = vmx_set_identity_map_addr,
7616         .get_mt_mask = vmx_get_mt_mask,
7617
7618         .get_exit_info = vmx_get_exit_info,
7619
7620         .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7621
7622         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7623
7624         .get_l2_tsc_offset = vmx_get_l2_tsc_offset,
7625         .get_l2_tsc_multiplier = vmx_get_l2_tsc_multiplier,
7626         .write_tsc_offset = vmx_write_tsc_offset,
7627         .write_tsc_multiplier = vmx_write_tsc_multiplier,
7628
7629         .load_mmu_pgd = vmx_load_mmu_pgd,
7630
7631         .check_intercept = vmx_check_intercept,
7632         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7633
7634         .request_immediate_exit = vmx_request_immediate_exit,
7635
7636         .sched_in = vmx_sched_in,
7637
7638         .cpu_dirty_log_size = PML_ENTITY_NUM,
7639         .update_cpu_dirty_logging = vmx_update_cpu_dirty_logging,
7640
7641         .pre_block = vmx_pre_block,
7642         .post_block = vmx_post_block,
7643
7644         .pmu_ops = &intel_pmu_ops,
7645         .nested_ops = &vmx_nested_ops,
7646
7647         .update_pi_irte = pi_update_irte,
7648         .start_assignment = vmx_pi_start_assignment,
7649
7650 #ifdef CONFIG_X86_64
7651         .set_hv_timer = vmx_set_hv_timer,
7652         .cancel_hv_timer = vmx_cancel_hv_timer,
7653 #endif
7654
7655         .setup_mce = vmx_setup_mce,
7656
7657         .smi_allowed = vmx_smi_allowed,
7658         .enter_smm = vmx_enter_smm,
7659         .leave_smm = vmx_leave_smm,
7660         .enable_smi_window = vmx_enable_smi_window,
7661
7662         .can_emulate_instruction = vmx_can_emulate_instruction,
7663         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7664         .migrate_timers = vmx_migrate_timers,
7665
7666         .msr_filter_changed = vmx_msr_filter_changed,
7667         .complete_emulated_msr = kvm_complete_insn_gp,
7668
7669         .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector,
7670 };
7671
7672 static __init void vmx_setup_user_return_msrs(void)
7673 {
7674
7675         /*
7676          * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
7677          * will emulate SYSCALL in legacy mode if the vendor string in guest
7678          * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
7679          * support this emulation, MSR_STAR is included in the list for i386,
7680          * but is never loaded into hardware.  MSR_CSTAR is also never loaded
7681          * into hardware and is here purely for emulation purposes.
7682          */
7683         const u32 vmx_uret_msrs_list[] = {
7684         #ifdef CONFIG_X86_64
7685                 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
7686         #endif
7687                 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
7688                 MSR_IA32_TSX_CTRL,
7689         };
7690         int i;
7691
7692         BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
7693
7694         for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
7695                 kvm_add_user_return_msr(vmx_uret_msrs_list[i]);
7696 }
7697
7698 static __init int hardware_setup(void)
7699 {
7700         unsigned long host_bndcfgs;
7701         struct desc_ptr dt;
7702         int r, ept_lpage_level;
7703
7704         store_idt(&dt);
7705         host_idt_base = dt.address;
7706
7707         vmx_setup_user_return_msrs();
7708
7709         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7710                 return -EIO;
7711
7712         if (boot_cpu_has(X86_FEATURE_NX))
7713                 kvm_enable_efer_bits(EFER_NX);
7714
7715         if (boot_cpu_has(X86_FEATURE_MPX)) {
7716                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7717                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7718         }
7719
7720         if (!cpu_has_vmx_mpx())
7721                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7722                                     XFEATURE_MASK_BNDCSR);
7723
7724         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7725             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7726                 enable_vpid = 0;
7727
7728         if (!cpu_has_vmx_ept() ||
7729             !cpu_has_vmx_ept_4levels() ||
7730             !cpu_has_vmx_ept_mt_wb() ||
7731             !cpu_has_vmx_invept_global())
7732                 enable_ept = 0;
7733
7734         /* NX support is required for shadow paging. */
7735         if (!enable_ept && !boot_cpu_has(X86_FEATURE_NX)) {
7736                 pr_err_ratelimited("kvm: NX (Execute Disable) not supported\n");
7737                 return -EOPNOTSUPP;
7738         }
7739
7740         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7741                 enable_ept_ad_bits = 0;
7742
7743         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7744                 enable_unrestricted_guest = 0;
7745
7746         if (!cpu_has_vmx_flexpriority())
7747                 flexpriority_enabled = 0;
7748
7749         if (!cpu_has_virtual_nmis())
7750                 enable_vnmi = 0;
7751
7752         /*
7753          * set_apic_access_page_addr() is used to reload apic access
7754          * page upon invalidation.  No need to do anything if not
7755          * using the APIC_ACCESS_ADDR VMCS field.
7756          */
7757         if (!flexpriority_enabled)
7758                 vmx_x86_ops.set_apic_access_page_addr = NULL;
7759
7760         if (!cpu_has_vmx_tpr_shadow())
7761                 vmx_x86_ops.update_cr8_intercept = NULL;
7762
7763 #if IS_ENABLED(CONFIG_HYPERV)
7764         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7765             && enable_ept) {
7766                 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7767                 vmx_x86_ops.tlb_remote_flush_with_range =
7768                                 hv_remote_flush_tlb_with_range;
7769         }
7770 #endif
7771
7772         if (!cpu_has_vmx_ple()) {
7773                 ple_gap = 0;
7774                 ple_window = 0;
7775                 ple_window_grow = 0;
7776                 ple_window_max = 0;
7777                 ple_window_shrink = 0;
7778         }
7779
7780         if (!cpu_has_vmx_apicv())
7781                 enable_apicv = 0;
7782         if (!enable_apicv)
7783                 vmx_x86_ops.sync_pir_to_irr = NULL;
7784
7785         if (cpu_has_vmx_tsc_scaling()) {
7786                 kvm_has_tsc_control = true;
7787                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7788                 kvm_tsc_scaling_ratio_frac_bits = 48;
7789         }
7790
7791         kvm_has_bus_lock_exit = cpu_has_vmx_bus_lock_detection();
7792
7793         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7794
7795         if (enable_ept)
7796                 kvm_mmu_set_ept_masks(enable_ept_ad_bits,
7797                                       cpu_has_vmx_ept_execute_only());
7798
7799         if (!enable_ept)
7800                 ept_lpage_level = 0;
7801         else if (cpu_has_vmx_ept_1g_page())
7802                 ept_lpage_level = PG_LEVEL_1G;
7803         else if (cpu_has_vmx_ept_2m_page())
7804                 ept_lpage_level = PG_LEVEL_2M;
7805         else
7806                 ept_lpage_level = PG_LEVEL_4K;
7807         kvm_configure_mmu(enable_ept, 0, vmx_get_max_tdp_level(),
7808                           ept_lpage_level);
7809
7810         /*
7811          * Only enable PML when hardware supports PML feature, and both EPT
7812          * and EPT A/D bit features are enabled -- PML depends on them to work.
7813          */
7814         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7815                 enable_pml = 0;
7816
7817         if (!enable_pml)
7818                 vmx_x86_ops.cpu_dirty_log_size = 0;
7819
7820         if (!cpu_has_vmx_preemption_timer())
7821                 enable_preemption_timer = false;
7822
7823         if (enable_preemption_timer) {
7824                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7825                 u64 vmx_msr;
7826
7827                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7828                 cpu_preemption_timer_multi =
7829                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7830
7831                 if (tsc_khz)
7832                         use_timer_freq = (u64)tsc_khz * 1000;
7833                 use_timer_freq >>= cpu_preemption_timer_multi;
7834
7835                 /*
7836                  * KVM "disables" the preemption timer by setting it to its max
7837                  * value.  Don't use the timer if it might cause spurious exits
7838                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7839                  */
7840                 if (use_timer_freq > 0xffffffffu / 10)
7841                         enable_preemption_timer = false;
7842         }
7843
7844         if (!enable_preemption_timer) {
7845                 vmx_x86_ops.set_hv_timer = NULL;
7846                 vmx_x86_ops.cancel_hv_timer = NULL;
7847                 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
7848         }
7849
7850         kvm_mce_cap_supported |= MCG_LMCE_P;
7851
7852         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7853                 return -EINVAL;
7854         if (!enable_ept || !cpu_has_vmx_intel_pt())
7855                 pt_mode = PT_MODE_SYSTEM;
7856
7857         setup_default_sgx_lepubkeyhash();
7858
7859         if (nested) {
7860                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7861                                            vmx_capability.ept);
7862
7863                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7864                 if (r)
7865                         return r;
7866         }
7867
7868         vmx_set_cpu_caps();
7869
7870         r = alloc_kvm_area();
7871         if (r)
7872                 nested_vmx_hardware_unsetup();
7873
7874         kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler);
7875
7876         return r;
7877 }
7878
7879 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
7880         .cpu_has_kvm_support = cpu_has_kvm_support,
7881         .disabled_by_bios = vmx_disabled_by_bios,
7882         .check_processor_compatibility = vmx_check_processor_compat,
7883         .hardware_setup = hardware_setup,
7884
7885         .runtime_ops = &vmx_x86_ops,
7886 };
7887
7888 static void vmx_cleanup_l1d_flush(void)
7889 {
7890         if (vmx_l1d_flush_pages) {
7891                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7892                 vmx_l1d_flush_pages = NULL;
7893         }
7894         /* Restore state so sysfs ignores VMX */
7895         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7896 }
7897
7898 static void vmx_exit(void)
7899 {
7900 #ifdef CONFIG_KEXEC_CORE
7901         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7902         synchronize_rcu();
7903 #endif
7904
7905         kvm_exit();
7906
7907 #if IS_ENABLED(CONFIG_HYPERV)
7908         if (static_branch_unlikely(&enable_evmcs)) {
7909                 int cpu;
7910                 struct hv_vp_assist_page *vp_ap;
7911                 /*
7912                  * Reset everything to support using non-enlightened VMCS
7913                  * access later (e.g. when we reload the module with
7914                  * enlightened_vmcs=0)
7915                  */
7916                 for_each_online_cpu(cpu) {
7917                         vp_ap = hv_get_vp_assist_page(cpu);
7918
7919                         if (!vp_ap)
7920                                 continue;
7921
7922                         vp_ap->nested_control.features.directhypercall = 0;
7923                         vp_ap->current_nested_vmcs = 0;
7924                         vp_ap->enlighten_vmentry = 0;
7925                 }
7926
7927                 static_branch_disable(&enable_evmcs);
7928         }
7929 #endif
7930         vmx_cleanup_l1d_flush();
7931
7932         allow_smaller_maxphyaddr = false;
7933 }
7934 module_exit(vmx_exit);
7935
7936 static int __init vmx_init(void)
7937 {
7938         int r, cpu;
7939
7940 #if IS_ENABLED(CONFIG_HYPERV)
7941         /*
7942          * Enlightened VMCS usage should be recommended and the host needs
7943          * to support eVMCS v1 or above. We can also disable eVMCS support
7944          * with module parameter.
7945          */
7946         if (enlightened_vmcs &&
7947             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7948             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7949             KVM_EVMCS_VERSION) {
7950                 int cpu;
7951
7952                 /* Check that we have assist pages on all online CPUs */
7953                 for_each_online_cpu(cpu) {
7954                         if (!hv_get_vp_assist_page(cpu)) {
7955                                 enlightened_vmcs = false;
7956                                 break;
7957                         }
7958                 }
7959
7960                 if (enlightened_vmcs) {
7961                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7962                         static_branch_enable(&enable_evmcs);
7963                 }
7964
7965                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7966                         vmx_x86_ops.enable_direct_tlbflush
7967                                 = hv_enable_direct_tlbflush;
7968
7969         } else {
7970                 enlightened_vmcs = false;
7971         }
7972 #endif
7973
7974         r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
7975                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7976         if (r)
7977                 return r;
7978
7979         /*
7980          * Must be called after kvm_init() so enable_ept is properly set
7981          * up. Hand the parameter mitigation value in which was stored in
7982          * the pre module init parser. If no parameter was given, it will
7983          * contain 'auto' which will be turned into the default 'cond'
7984          * mitigation mode.
7985          */
7986         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7987         if (r) {
7988                 vmx_exit();
7989                 return r;
7990         }
7991
7992         for_each_possible_cpu(cpu) {
7993                 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
7994
7995                 pi_init_cpu(cpu);
7996         }
7997
7998 #ifdef CONFIG_KEXEC_CORE
7999         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8000                            crash_vmclear_local_loaded_vmcss);
8001 #endif
8002         vmx_check_vmcs12_offsets();
8003
8004         /*
8005          * Shadow paging doesn't have a (further) performance penalty
8006          * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it
8007          * by default
8008          */
8009         if (!enable_ept)
8010                 allow_smaller_maxphyaddr = true;
8011
8012         return 0;
8013 }
8014 module_init(vmx_init);