arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/highmem.h>
  17 #include <linux/hrtimer.h>
  18 #include <linux/kernel.h>
  19 #include <linux/kvm_host.h>
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/mod_devicetable.h>
  23 #include <linux/mm.h>
  24 #include <linux/objtool.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30 #include <linux/entry-kvm.h>
  31
  32 #include <asm/apic.h>
  33 #include <asm/asm.h>
  34 #include <asm/cpu.h>
  35 #include <asm/cpu_device_id.h>
  36 #include <asm/debugreg.h>
  37 #include <asm/desc.h>
  38 #include <asm/fpu/internal.h>
  39 #include <asm/idtentry.h>
  40 #include <asm/io.h>
  41 #include <asm/irq_remapping.h>
  42 #include <asm/kexec.h>
  43 #include <asm/perf_event.h>
  44 #include <asm/mmu_context.h>
  45 #include <asm/mshyperv.h>
  46 #include <asm/mwait.h>
  47 #include <asm/spec-ctrl.h>
  48 #include <asm/virtext.h>
  49 #include <asm/vmx.h>
  50
  51 #include "capabilities.h"
  52 #include "cpuid.h"
  53 #include "evmcs.h"
  54 #include "hyperv.h"
  55 #include "kvm_onhyperv.h"
  56 #include "irq.h"
  57 #include "kvm_cache_regs.h"
  58 #include "lapic.h"
  59 #include "mmu.h"
  60 #include "nested.h"
  61 #include "pmu.h"
  62 #include "sgx.h"
  63 #include "trace.h"
  64 #include "vmcs.h"
  65 #include "vmcs12.h"
  66 #include "vmx.h"
  67 #include "x86.h"
  68
  69 MODULE_AUTHOR("Qumranet");
  70 MODULE_LICENSE("GPL");
  71
  72 #ifdef MODULE
  73 static const struct x86_cpu_id vmx_cpu_id[] = {
  74         X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
  75         {}
  76 };
  77 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  78 #endif
  79
  80 bool __read_mostly enable_vpid = 1;
  81 module_param_named(vpid, enable_vpid, bool, 0444);
  82
  83 static bool __read_mostly enable_vnmi = 1;
  84 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  85
  86 bool __read_mostly flexpriority_enabled = 1;
  87 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_ept = 1;
  90 module_param_named(ept, enable_ept, bool, S_IRUGO);
  91
  92 bool __read_mostly enable_unrestricted_guest = 1;
  93 module_param_named(unrestricted_guest,
  94                         enable_unrestricted_guest, bool, S_IRUGO);
  95
  96 bool __read_mostly enable_ept_ad_bits = 1;
  97 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  98
  99 static bool __read_mostly emulate_invalid_guest_state = true;
 100 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
 101
 102 static bool __read_mostly fasteoi = 1;
 103 module_param(fasteoi, bool, S_IRUGO);
 104
 105 module_param(enable_apicv, bool, S_IRUGO);
 106
 107 /*
 108  * If nested=1, nested virtualization is supported, i.e., guests may use
 109  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 110  * use VMX instructions.
 111  */
 112 static bool __read_mostly nested = 1;
 113 module_param(nested, bool, S_IRUGO);
 114
 115 bool __read_mostly enable_pml = 1;
 116 module_param_named(pml, enable_pml, bool, S_IRUGO);
 117
 118 static bool __read_mostly dump_invalid_vmcs = 0;
 119 module_param(dump_invalid_vmcs, bool, 0644);
 120
 121 #define MSR_BITMAP_MODE_X2APIC          1
 122 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 123
 124 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 125
 126 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 127 static int __read_mostly cpu_preemption_timer_multi;
 128 static bool __read_mostly enable_preemption_timer = 1;
 129 #ifdef CONFIG_X86_64
 130 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 131 #endif
 132
 133 extern bool __read_mostly allow_smaller_maxphyaddr;
 134 module_param(allow_smaller_maxphyaddr, bool, S_IRUGO);
 135
 136 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 137 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 138 #define KVM_VM_CR0_ALWAYS_ON                            \
 139         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 140
 141 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 142 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 143 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 144
 145 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 146
 147 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 148         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 149         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 150         RTIT_STATUS_BYTECNT))
 151
 152 /*
 153  * List of MSRs that can be directly passed to the guest.
 154  * In addition to these x2apic and PT MSRs are handled specially.
 155  */
 156 static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = {
 157         MSR_IA32_SPEC_CTRL,
 158         MSR_IA32_PRED_CMD,
 159         MSR_IA32_TSC,
 160 #ifdef CONFIG_X86_64
 161         MSR_FS_BASE,
 162         MSR_GS_BASE,
 163         MSR_KERNEL_GS_BASE,
 164 #endif
 165         MSR_IA32_SYSENTER_CS,
 166         MSR_IA32_SYSENTER_ESP,
 167         MSR_IA32_SYSENTER_EIP,
 168         MSR_CORE_C1_RES,
 169         MSR_CORE_C3_RESIDENCY,
 170         MSR_CORE_C6_RESIDENCY,
 171         MSR_CORE_C7_RESIDENCY,
 172 };
 173
 174 /*
 175  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 176  * ple_gap:    upper bound on the amount of time between two successive
 177  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 178  *             According to test, this time is usually smaller than 128 cycles.
 179  * ple_window: upper bound on the amount of time a guest is allowed to execute
 180  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 181  *             less than 2^12 cycles
 182  * Time is measured based on a counter that runs at the same rate as the TSC,
 183  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 184  */
 185 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 186 module_param(ple_gap, uint, 0444);
 187
 188 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 189 module_param(ple_window, uint, 0444);
 190
 191 /* Default doubles per-vcpu window every exit. */
 192 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 193 module_param(ple_window_grow, uint, 0444);
 194
 195 /* Default resets per-vcpu window every exit to ple_window. */
 196 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 197 module_param(ple_window_shrink, uint, 0444);
 198
 199 /* Default is to compute the maximum so we can never overflow. */
 200 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 201 module_param(ple_window_max, uint, 0444);
 202
 203 /* Default is SYSTEM mode, 1 for host-guest mode */
 204 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 205 module_param(pt_mode, int, S_IRUGO);
 206
 207 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 208 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 209 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 210
 211 /* Storage for pre module init parameter parsing */
 212 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 213
 214 static const struct {
 215         const char *option;
 216         bool for_parse;
 217 } vmentry_l1d_param[] = {
 218         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 219         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 220         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 221         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 222         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 223         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 224 };
 225
 226 #define L1D_CACHE_ORDER 4
 227 static void *vmx_l1d_flush_pages;
 228
 229 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 230 {
 231         struct page *page;
 232         unsigned int i;
 233
 234         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 235                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 236                 return 0;
 237         }
 238
 239         if (!enable_ept) {
 240                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 241                 return 0;
 242         }
 243
 244         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 245                 u64 msr;
 246
 247                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 248                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 249                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 250                         return 0;
 251                 }
 252         }
 253
 254         /* If set to auto use the default l1tf mitigation method */
 255         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 256                 switch (l1tf_mitigation) {
 257                 case L1TF_MITIGATION_OFF:
 258                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 259                         break;
 260                 case L1TF_MITIGATION_FLUSH_NOWARN:
 261                 case L1TF_MITIGATION_FLUSH:
 262                 case L1TF_MITIGATION_FLUSH_NOSMT:
 263                         l1tf = VMENTER_L1D_FLUSH_COND;
 264                         break;
 265                 case L1TF_MITIGATION_FULL:
 266                 case L1TF_MITIGATION_FULL_FORCE:
 267                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 268                         break;
 269                 }
 270         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 271                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 272         }
 273
 274         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 275             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 276                 /*
 277                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 278                  * lifetime and so should not be charged to a memcg.
 279                  */
 280                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 281                 if (!page)
 282                         return -ENOMEM;
 283                 vmx_l1d_flush_pages = page_address(page);
 284
 285                 /*
 286                  * Initialize each page with a different pattern in
 287                  * order to protect against KSM in the nested
 288                  * virtualization case.
 289                  */
 290                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 291                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 292                                PAGE_SIZE);
 293                 }
 294         }
 295
 296         l1tf_vmx_mitigation = l1tf;
 297
 298         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 299                 static_branch_enable(&vmx_l1d_should_flush);
 300         else
 301                 static_branch_disable(&vmx_l1d_should_flush);
 302
 303         if (l1tf == VMENTER_L1D_FLUSH_COND)
 304                 static_branch_enable(&vmx_l1d_flush_cond);
 305         else
 306                 static_branch_disable(&vmx_l1d_flush_cond);
 307         return 0;
 308 }
 309
 310 static int vmentry_l1d_flush_parse(const char *s)
 311 {
 312         unsigned int i;
 313
 314         if (s) {
 315                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 316                         if (vmentry_l1d_param[i].for_parse &&
 317                             sysfs_streq(s, vmentry_l1d_param[i].option))
 318                                 return i;
 319                 }
 320         }
 321         return -EINVAL;
 322 }
 323
 324 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 325 {
 326         int l1tf, ret;
 327
 328         l1tf = vmentry_l1d_flush_parse(s);
 329         if (l1tf < 0)
 330                 return l1tf;
 331
 332         if (!boot_cpu_has(X86_BUG_L1TF))
 333                 return 0;
 334
 335         /*
 336          * Has vmx_init() run already? If not then this is the pre init
 337          * parameter parsing. In that case just store the value and let
 338          * vmx_init() do the proper setup after enable_ept has been
 339          * established.
 340          */
 341         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 342                 vmentry_l1d_flush_param = l1tf;
 343                 return 0;
 344         }
 345
 346         mutex_lock(&vmx_l1d_flush_mutex);
 347         ret = vmx_setup_l1d_flush(l1tf);
 348         mutex_unlock(&vmx_l1d_flush_mutex);
 349         return ret;
 350 }
 351
 352 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 353 {
 354         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 355                 return sprintf(s, "???\n");
 356
 357         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 358 }
 359
 360 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 361         .set = vmentry_l1d_flush_set,
 362         .get = vmentry_l1d_flush_get,
 363 };
 364 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 365
 366 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 367
 368 void vmx_vmexit(void);
 369
 370 #define vmx_insn_failed(fmt...)         \
 371 do {                                    \
 372         WARN_ONCE(1, fmt);              \
 373         pr_warn_ratelimited(fmt);       \
 374 } while (0)
 375
 376 asmlinkage void vmread_error(unsigned long field, bool fault)
 377 {
 378         if (fault)
 379                 kvm_spurious_fault();
 380         else
 381                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 382 }
 383
 384 noinline void vmwrite_error(unsigned long field, unsigned long value)
 385 {
 386         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 387                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 388 }
 389
 390 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 391 {
 392         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 393 }
 394
 395 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 396 {
 397         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 398 }
 399
 400 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 401 {
 402         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 403                         ext, vpid, gva);
 404 }
 405
 406 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 407 {
 408         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 409                         ext, eptp, gpa);
 410 }
 411
 412 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 413 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 414 /*
 415  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 416  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 417  */
 418 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 419
 420 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 421 static DEFINE_SPINLOCK(vmx_vpid_lock);
 422
 423 struct vmcs_config vmcs_config;
 424 struct vmx_capability vmx_capability;
 425
 426 #define VMX_SEGMENT_FIELD(seg)                                  \
 427         [VCPU_SREG_##seg] = {                                   \
 428                 .selector = GUEST_##seg##_SELECTOR,             \
 429                 .base = GUEST_##seg##_BASE,                     \
 430                 .limit = GUEST_##seg##_LIMIT,                   \
 431                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 432         }
 433
 434 static const struct kvm_vmx_segment_field {
 435         unsigned selector;
 436         unsigned base;
 437         unsigned limit;
 438         unsigned ar_bytes;
 439 } kvm_vmx_segment_fields[] = {
 440         VMX_SEGMENT_FIELD(CS),
 441         VMX_SEGMENT_FIELD(DS),
 442         VMX_SEGMENT_FIELD(ES),
 443         VMX_SEGMENT_FIELD(FS),
 444         VMX_SEGMENT_FIELD(GS),
 445         VMX_SEGMENT_FIELD(SS),
 446         VMX_SEGMENT_FIELD(TR),
 447         VMX_SEGMENT_FIELD(LDTR),
 448 };
 449
 450 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
 451 {
 452         vmx->segment_cache.bitmask = 0;
 453 }
 454
 455 static unsigned long host_idt_base;
 456
 457 #if IS_ENABLED(CONFIG_HYPERV)
 458 static bool __read_mostly enlightened_vmcs = true;
 459 module_param(enlightened_vmcs, bool, 0444);
 460
 461 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 462 {
 463         struct hv_enlightened_vmcs *evmcs;
 464         struct hv_partition_assist_pg **p_hv_pa_pg =
 465                         &to_kvm_hv(vcpu->kvm)->hv_pa_pg;
 466         /*
 467          * Synthetic VM-Exit is not enabled in current code and so All
 468          * evmcs in singe VM shares same assist page.
 469          */
 470         if (!*p_hv_pa_pg)
 471                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
 472
 473         if (!*p_hv_pa_pg)
 474                 return -ENOMEM;
 475
 476         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 477
 478         evmcs->partition_assist_page =
 479                 __pa(*p_hv_pa_pg);
 480         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 481         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 482
 483         return 0;
 484 }
 485
 486 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 487
 488 /*
 489  * Comment's format: document - errata name - stepping - processor name.
 490  * Refer from
 491  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 492  */
 493 static u32 vmx_preemption_cpu_tfms[] = {
 494 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 495 0x000206E6,
 496 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 497 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 498 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 499 0x00020652,
 500 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 501 0x00020655,
 502 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 503 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 504 /*
 505  * 320767.pdf - AAP86  - B1 -
 506  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 507  */
 508 0x000106E5,
 509 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 510 0x000106A0,
 511 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 512 0x000106A1,
 513 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 514 0x000106A4,
 515  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 516  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 517  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 518 0x000106A5,
 519  /* Xeon E3-1220 V2 */
 520 0x000306A8,
 521 };
 522
 523 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 524 {
 525         u32 eax = cpuid_eax(0x00000001), i;
 526
 527         /* Clear the reserved bits */
 528         eax &= ~(0x3U << 14 | 0xfU << 28);
 529         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 530                 if (eax == vmx_preemption_cpu_tfms[i])
 531                         return true;
 532
 533         return false;
 534 }
 535
 536 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 537 {
 538         return flexpriority_enabled && lapic_in_kernel(vcpu);
 539 }
 540
 541 static inline bool report_flexpriority(void)
 542 {
 543         return flexpriority_enabled;
 544 }
 545
 546 static int possible_passthrough_msr_slot(u32 msr)
 547 {
 548         u32 i;
 549
 550         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++)
 551                 if (vmx_possible_passthrough_msrs[i] == msr)
 552                         return i;
 553
 554         return -ENOENT;
 555 }
 556
 557 static bool is_valid_passthrough_msr(u32 msr)
 558 {
 559         bool r;
 560
 561         switch (msr) {
 562         case 0x800 ... 0x8ff:
 563                 /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */
 564                 return true;
 565         case MSR_IA32_RTIT_STATUS:
 566         case MSR_IA32_RTIT_OUTPUT_BASE:
 567         case MSR_IA32_RTIT_OUTPUT_MASK:
 568         case MSR_IA32_RTIT_CR3_MATCH:
 569         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
 570                 /* PT MSRs. These are handled in pt_update_intercept_for_msr() */
 571         case MSR_LBR_SELECT:
 572         case MSR_LBR_TOS:
 573         case MSR_LBR_INFO_0 ... MSR_LBR_INFO_0 + 31:
 574         case MSR_LBR_NHM_FROM ... MSR_LBR_NHM_FROM + 31:
 575         case MSR_LBR_NHM_TO ... MSR_LBR_NHM_TO + 31:
 576         case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8:
 577         case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8:
 578                 /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */
 579                 return true;
 580         }
 581
 582         r = possible_passthrough_msr_slot(msr) != -ENOENT;
 583
 584         WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr);
 585
 586         return r;
 587 }
 588
 589 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
 590 {
 591         int i;
 592
 593         i = kvm_find_user_return_msr(msr);
 594         if (i >= 0)
 595                 return &vmx->guest_uret_msrs[i];
 596         return NULL;
 597 }
 598
 599 static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx,
 600                                   struct vmx_uret_msr *msr, u64 data)
 601 {
 602         unsigned int slot = msr - vmx->guest_uret_msrs;
 603         int ret = 0;
 604
 605         u64 old_msr_data = msr->data;
 606         msr->data = data;
 607         if (msr->load_into_hardware) {
 608                 preempt_disable();
 609                 ret = kvm_set_user_return_msr(slot, msr->data, msr->mask);
 610                 preempt_enable();
 611                 if (ret)
 612                         msr->data = old_msr_data;
 613         }
 614         return ret;
 615 }
 616
 617 #ifdef CONFIG_KEXEC_CORE
 618 static void crash_vmclear_local_loaded_vmcss(void)
 619 {
 620         int cpu = raw_smp_processor_id();
 621         struct loaded_vmcs *v;
 622
 623         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 624                             loaded_vmcss_on_cpu_link)
 625                 vmcs_clear(v->vmcs);
 626 }
 627 #endif /* CONFIG_KEXEC_CORE */
 628
 629 static void __loaded_vmcs_clear(void *arg)
 630 {
 631         struct loaded_vmcs *loaded_vmcs = arg;
 632         int cpu = raw_smp_processor_id();
 633
 634         if (loaded_vmcs->cpu != cpu)
 635                 return; /* vcpu migration can race with cpu offline */
 636         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 637                 per_cpu(current_vmcs, cpu) = NULL;
 638
 639         vmcs_clear(loaded_vmcs->vmcs);
 640         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 641                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 642
 643         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 644
 645         /*
 646          * Ensure all writes to loaded_vmcs, including deleting it from its
 647          * current percpu list, complete before setting loaded_vmcs->vcpu to
 648          * -1, otherwise a different cpu can see vcpu == -1 first and add
 649          * loaded_vmcs to its percpu list before it's deleted from this cpu's
 650          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
 651          */
 652         smp_wmb();
 653
 654         loaded_vmcs->cpu = -1;
 655         loaded_vmcs->launched = 0;
 656 }
 657
 658 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 659 {
 660         int cpu = loaded_vmcs->cpu;
 661
 662         if (cpu != -1)
 663                 smp_call_function_single(cpu,
 664                          __loaded_vmcs_clear, loaded_vmcs, 1);
 665 }
 666
 667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 668                                        unsigned field)
 669 {
 670         bool ret;
 671         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 672
 673         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
 674                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
 675                 vmx->segment_cache.bitmask = 0;
 676         }
 677         ret = vmx->segment_cache.bitmask & mask;
 678         vmx->segment_cache.bitmask |= mask;
 679         return ret;
 680 }
 681
 682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 683 {
 684         u16 *p = &vmx->segment_cache.seg[seg].selector;
 685
 686         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 687                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 688         return *p;
 689 }
 690
 691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 692 {
 693         ulong *p = &vmx->segment_cache.seg[seg].base;
 694
 695         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 696                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 697         return *p;
 698 }
 699
 700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 701 {
 702         u32 *p = &vmx->segment_cache.seg[seg].limit;
 703
 704         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 705                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 706         return *p;
 707 }
 708
 709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 710 {
 711         u32 *p = &vmx->segment_cache.seg[seg].ar;
 712
 713         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 714                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 715         return *p;
 716 }
 717
 718 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu)
 719 {
 720         u32 eb;
 721
 722         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 723              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 724         /*
 725          * Guest access to VMware backdoor ports could legitimately
 726          * trigger #GP because of TSS I/O permission bitmap.
 727          * We intercept those #GP and allow access to them anyway
 728          * as VMware does.
 729          */
 730         if (enable_vmware_backdoor)
 731                 eb |= (1u << GP_VECTOR);
 732         if ((vcpu->guest_debug &
 733              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 734             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 735                 eb |= 1u << BP_VECTOR;
 736         if (to_vmx(vcpu)->rmode.vm86_active)
 737                 eb = ~0;
 738         if (!vmx_need_pf_intercept(vcpu))
 739                 eb &= ~(1u << PF_VECTOR);
 740
 741         /* When we are running a nested L2 guest and L1 specified for it a
 742          * certain exception bitmap, we must trap the same exceptions and pass
 743          * them to L1. When running L2, we will only handle the exceptions
 744          * specified above if L1 did not want them.
 745          */
 746         if (is_guest_mode(vcpu))
 747                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 748         else {
 749                 int mask = 0, match = 0;
 750
 751                 if (enable_ept && (eb & (1u << PF_VECTOR))) {
 752                         /*
 753                          * If EPT is enabled, #PF is currently only intercepted
 754                          * if MAXPHYADDR is smaller on the guest than on the
 755                          * host.  In that case we only care about present,
 756                          * non-reserved faults.  For vmcs02, however, PFEC_MASK
 757                          * and PFEC_MATCH are set in prepare_vmcs02_rare.
 758                          */
 759                         mask = PFERR_PRESENT_MASK | PFERR_RSVD_MASK;
 760                         match = PFERR_PRESENT_MASK;
 761                 }
 762                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
 763                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, match);
 764         }
 765
 766         vmcs_write32(EXCEPTION_BITMAP, eb);
 767 }
 768
 769 /*
 770  * Check if MSR is intercepted for currently loaded MSR bitmap.
 771  */
 772 static bool msr_write_intercepted(struct vcpu_vmx *vmx, u32 msr)
 773 {
 774         unsigned long *msr_bitmap;
 775         int f = sizeof(unsigned long);
 776
 777         if (!(exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS))
 778                 return true;
 779
 780         msr_bitmap = vmx->loaded_vmcs->msr_bitmap;
 781
 782         if (msr <= 0x1fff) {
 783                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 784         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 785                 msr &= 0x1fff;
 786                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 787         }
 788
 789         return true;
 790 }
 791
 792 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 793                 unsigned long entry, unsigned long exit)
 794 {
 795         vm_entry_controls_clearbit(vmx, entry);
 796         vm_exit_controls_clearbit(vmx, exit);
 797 }
 798
 799 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr)
 800 {
 801         unsigned int i;
 802
 803         for (i = 0; i < m->nr; ++i) {
 804                 if (m->val[i].index == msr)
 805                         return i;
 806         }
 807         return -ENOENT;
 808 }
 809
 810 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 811 {
 812         int i;
 813         struct msr_autoload *m = &vmx->msr_autoload;
 814
 815         switch (msr) {
 816         case MSR_EFER:
 817                 if (cpu_has_load_ia32_efer()) {
 818                         clear_atomic_switch_msr_special(vmx,
 819                                         VM_ENTRY_LOAD_IA32_EFER,
 820                                         VM_EXIT_LOAD_IA32_EFER);
 821                         return;
 822                 }
 823                 break;
 824         case MSR_CORE_PERF_GLOBAL_CTRL:
 825                 if (cpu_has_load_perf_global_ctrl()) {
 826                         clear_atomic_switch_msr_special(vmx,
 827                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 828                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 829                         return;
 830                 }
 831                 break;
 832         }
 833         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
 834         if (i < 0)
 835                 goto skip_guest;
 836         --m->guest.nr;
 837         m->guest.val[i] = m->guest.val[m->guest.nr];
 838         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 839
 840 skip_guest:
 841         i = vmx_find_loadstore_msr_slot(&m->host, msr);
 842         if (i < 0)
 843                 return;
 844
 845         --m->host.nr;
 846         m->host.val[i] = m->host.val[m->host.nr];
 847         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 848 }
 849
 850 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 851                 unsigned long entry, unsigned long exit,
 852                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 853                 u64 guest_val, u64 host_val)
 854 {
 855         vmcs_write64(guest_val_vmcs, guest_val);
 856         if (host_val_vmcs != HOST_IA32_EFER)
 857                 vmcs_write64(host_val_vmcs, host_val);
 858         vm_entry_controls_setbit(vmx, entry);
 859         vm_exit_controls_setbit(vmx, exit);
 860 }
 861
 862 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 863                                   u64 guest_val, u64 host_val, bool entry_only)
 864 {
 865         int i, j = 0;
 866         struct msr_autoload *m = &vmx->msr_autoload;
 867
 868         switch (msr) {
 869         case MSR_EFER:
 870                 if (cpu_has_load_ia32_efer()) {
 871                         add_atomic_switch_msr_special(vmx,
 872                                         VM_ENTRY_LOAD_IA32_EFER,
 873                                         VM_EXIT_LOAD_IA32_EFER,
 874                                         GUEST_IA32_EFER,
 875                                         HOST_IA32_EFER,
 876                                         guest_val, host_val);
 877                         return;
 878                 }
 879                 break;
 880         case MSR_CORE_PERF_GLOBAL_CTRL:
 881                 if (cpu_has_load_perf_global_ctrl()) {
 882                         add_atomic_switch_msr_special(vmx,
 883                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 884                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 885                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 886                                         HOST_IA32_PERF_GLOBAL_CTRL,
 887                                         guest_val, host_val);
 888                         return;
 889                 }
 890                 break;
 891         case MSR_IA32_PEBS_ENABLE:
 892                 /* PEBS needs a quiescent period after being disabled (to write
 893                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 894                  * provide that period, so a CPU could write host's record into
 895                  * guest's memory.
 896                  */
 897                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 898         }
 899
 900         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
 901         if (!entry_only)
 902                 j = vmx_find_loadstore_msr_slot(&m->host, msr);
 903
 904         if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) ||
 905             (j < 0 &&  m->host.nr == MAX_NR_LOADSTORE_MSRS)) {
 906                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 907                                 "Can't add msr %x\n", msr);
 908                 return;
 909         }
 910         if (i < 0) {
 911                 i = m->guest.nr++;
 912                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 913         }
 914         m->guest.val[i].index = msr;
 915         m->guest.val[i].value = guest_val;
 916
 917         if (entry_only)
 918                 return;
 919
 920         if (j < 0) {
 921                 j = m->host.nr++;
 922                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 923         }
 924         m->host.val[j].index = msr;
 925         m->host.val[j].value = host_val;
 926 }
 927
 928 static bool update_transition_efer(struct vcpu_vmx *vmx)
 929 {
 930         u64 guest_efer = vmx->vcpu.arch.efer;
 931         u64 ignore_bits = 0;
 932         int i;
 933
 934         /* Shadow paging assumes NX to be available.  */
 935         if (!enable_ept)
 936                 guest_efer |= EFER_NX;
 937
 938         /*
 939          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 940          */
 941         ignore_bits |= EFER_SCE;
 942 #ifdef CONFIG_X86_64
 943         ignore_bits |= EFER_LMA | EFER_LME;
 944         /* SCE is meaningful only in long mode on Intel */
 945         if (guest_efer & EFER_LMA)
 946                 ignore_bits &= ~(u64)EFER_SCE;
 947 #endif
 948
 949         /*
 950          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 951          * On CPUs that support "load IA32_EFER", always switch EFER
 952          * atomically, since it's faster than switching it manually.
 953          */
 954         if (cpu_has_load_ia32_efer() ||
 955             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 956                 if (!(guest_efer & EFER_LMA))
 957                         guest_efer &= ~EFER_LME;
 958                 if (guest_efer != host_efer)
 959                         add_atomic_switch_msr(vmx, MSR_EFER,
 960                                               guest_efer, host_efer, false);
 961                 else
 962                         clear_atomic_switch_msr(vmx, MSR_EFER);
 963                 return false;
 964         }
 965
 966         i = kvm_find_user_return_msr(MSR_EFER);
 967         if (i < 0)
 968                 return false;
 969
 970         clear_atomic_switch_msr(vmx, MSR_EFER);
 971
 972         guest_efer &= ~ignore_bits;
 973         guest_efer |= host_efer & ignore_bits;
 974
 975         vmx->guest_uret_msrs[i].data = guest_efer;
 976         vmx->guest_uret_msrs[i].mask = ~ignore_bits;
 977
 978         return true;
 979 }
 980
 981 #ifdef CONFIG_X86_32
 982 /*
 983  * On 32-bit kernels, VM exits still load the FS and GS bases from the
 984  * VMCS rather than the segment table.  KVM uses this helper to figure
 985  * out the current bases to poke them into the VMCS before entry.
 986  */
 987 static unsigned long segment_base(u16 selector)
 988 {
 989         struct desc_struct *table;
 990         unsigned long v;
 991
 992         if (!(selector & ~SEGMENT_RPL_MASK))
 993                 return 0;
 994
 995         table = get_current_gdt_ro();
 996
 997         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
 998                 u16 ldt_selector = kvm_read_ldt();
 999
1000                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1001                         return 0;
1002
1003                 table = (struct desc_struct *)segment_base(ldt_selector);
1004         }
1005         v = get_desc_base(&table[selector >> 3]);
1006         return v;
1007 }
1008 #endif
1009
1010 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1011 {
1012         return vmx_pt_mode_is_host_guest() &&
1013                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1014 }
1015
1016 static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base)
1017 {
1018         /* The base must be 128-byte aligned and a legal physical address. */
1019         return kvm_vcpu_is_legal_aligned_gpa(vcpu, base, 128);
1020 }
1021
1022 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1023 {
1024         u32 i;
1025
1026         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1027         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1028         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1029         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1030         for (i = 0; i < addr_range; i++) {
1031                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1032                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1033         }
1034 }
1035
1036 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1037 {
1038         u32 i;
1039
1040         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1041         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1042         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1043         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1044         for (i = 0; i < addr_range; i++) {
1045                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1046                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1047         }
1048 }
1049
1050 static void pt_guest_enter(struct vcpu_vmx *vmx)
1051 {
1052         if (vmx_pt_mode_is_system())
1053                 return;
1054
1055         /*
1056          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1057          * Save host state before VM entry.
1058          */
1059         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1060         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1061                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1062                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1063                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1064         }
1065 }
1066
1067 static void pt_guest_exit(struct vcpu_vmx *vmx)
1068 {
1069         if (vmx_pt_mode_is_system())
1070                 return;
1071
1072         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1073                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1074                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1075         }
1076
1077         /*
1078          * KVM requires VM_EXIT_CLEAR_IA32_RTIT_CTL to expose PT to the guest,
1079          * i.e. RTIT_CTL is always cleared on VM-Exit.  Restore it if necessary.
1080          */
1081         if (vmx->pt_desc.host.ctl)
1082                 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1083 }
1084
1085 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1086                         unsigned long fs_base, unsigned long gs_base)
1087 {
1088         if (unlikely(fs_sel != host->fs_sel)) {
1089                 if (!(fs_sel & 7))
1090                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1091                 else
1092                         vmcs_write16(HOST_FS_SELECTOR, 0);
1093                 host->fs_sel = fs_sel;
1094         }
1095         if (unlikely(gs_sel != host->gs_sel)) {
1096                 if (!(gs_sel & 7))
1097                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1098                 else
1099                         vmcs_write16(HOST_GS_SELECTOR, 0);
1100                 host->gs_sel = gs_sel;
1101         }
1102         if (unlikely(fs_base != host->fs_base)) {
1103                 vmcs_writel(HOST_FS_BASE, fs_base);
1104                 host->fs_base = fs_base;
1105         }
1106         if (unlikely(gs_base != host->gs_base)) {
1107                 vmcs_writel(HOST_GS_BASE, gs_base);
1108                 host->gs_base = gs_base;
1109         }
1110 }
1111
1112 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1113 {
1114         struct vcpu_vmx *vmx = to_vmx(vcpu);
1115         struct vmcs_host_state *host_state;
1116 #ifdef CONFIG_X86_64
1117         int cpu = raw_smp_processor_id();
1118 #endif
1119         unsigned long fs_base, gs_base;
1120         u16 fs_sel, gs_sel;
1121         int i;
1122
1123         vmx->req_immediate_exit = false;
1124
1125         /*
1126          * Note that guest MSRs to be saved/restored can also be changed
1127          * when guest state is loaded. This happens when guest transitions
1128          * to/from long-mode by setting MSR_EFER.LMA.
1129          */
1130         if (!vmx->guest_uret_msrs_loaded) {
1131                 vmx->guest_uret_msrs_loaded = true;
1132                 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
1133                         if (!vmx->guest_uret_msrs[i].load_into_hardware)
1134                                 continue;
1135
1136                         kvm_set_user_return_msr(i,
1137                                                 vmx->guest_uret_msrs[i].data,
1138                                                 vmx->guest_uret_msrs[i].mask);
1139                 }
1140         }
1141
1142         if (vmx->nested.need_vmcs12_to_shadow_sync)
1143                 nested_sync_vmcs12_to_shadow(vcpu);
1144
1145         if (vmx->guest_state_loaded)
1146                 return;
1147
1148         host_state = &vmx->loaded_vmcs->host_state;
1149
1150         /*
1151          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1152          * allow segment selectors with cpl > 0 or ti == 1.
1153          */
1154         host_state->ldt_sel = kvm_read_ldt();
1155
1156 #ifdef CONFIG_X86_64
1157         savesegment(ds, host_state->ds_sel);
1158         savesegment(es, host_state->es_sel);
1159
1160         gs_base = cpu_kernelmode_gs_base(cpu);
1161         if (likely(is_64bit_mm(current->mm))) {
1162                 current_save_fsgs();
1163                 fs_sel = current->thread.fsindex;
1164                 gs_sel = current->thread.gsindex;
1165                 fs_base = current->thread.fsbase;
1166                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1167         } else {
1168                 savesegment(fs, fs_sel);
1169                 savesegment(gs, gs_sel);
1170                 fs_base = read_msr(MSR_FS_BASE);
1171                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1172         }
1173
1174         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1175 #else
1176         savesegment(fs, fs_sel);
1177         savesegment(gs, gs_sel);
1178         fs_base = segment_base(fs_sel);
1179         gs_base = segment_base(gs_sel);
1180 #endif
1181
1182         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1183         vmx->guest_state_loaded = true;
1184 }
1185
1186 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1187 {
1188         struct vmcs_host_state *host_state;
1189
1190         if (!vmx->guest_state_loaded)
1191                 return;
1192
1193         host_state = &vmx->loaded_vmcs->host_state;
1194
1195         ++vmx->vcpu.stat.host_state_reload;
1196
1197 #ifdef CONFIG_X86_64
1198         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1199 #endif
1200         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1201                 kvm_load_ldt(host_state->ldt_sel);
1202 #ifdef CONFIG_X86_64
1203                 load_gs_index(host_state->gs_sel);
1204 #else
1205                 loadsegment(gs, host_state->gs_sel);
1206 #endif
1207         }
1208         if (host_state->fs_sel & 7)
1209                 loadsegment(fs, host_state->fs_sel);
1210 #ifdef CONFIG_X86_64
1211         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1212                 loadsegment(ds, host_state->ds_sel);
1213                 loadsegment(es, host_state->es_sel);
1214         }
1215 #endif
1216         invalidate_tss_limit();
1217 #ifdef CONFIG_X86_64
1218         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1219 #endif
1220         load_fixmap_gdt(raw_smp_processor_id());
1221         vmx->guest_state_loaded = false;
1222         vmx->guest_uret_msrs_loaded = false;
1223 }
1224
1225 #ifdef CONFIG_X86_64
1226 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1227 {
1228         preempt_disable();
1229         if (vmx->guest_state_loaded)
1230                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1231         preempt_enable();
1232         return vmx->msr_guest_kernel_gs_base;
1233 }
1234
1235 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1236 {
1237         preempt_disable();
1238         if (vmx->guest_state_loaded)
1239                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1240         preempt_enable();
1241         vmx->msr_guest_kernel_gs_base = data;
1242 }
1243 #endif
1244
1245 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1246                         struct loaded_vmcs *buddy)
1247 {
1248         struct vcpu_vmx *vmx = to_vmx(vcpu);
1249         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1250         struct vmcs *prev;
1251
1252         if (!already_loaded) {
1253                 loaded_vmcs_clear(vmx->loaded_vmcs);
1254                 local_irq_disable();
1255
1256                 /*
1257                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1258                  * this cpu's percpu list, otherwise it may not yet be deleted
1259                  * from its previous cpu's percpu list.  Pairs with the
1260                  * smb_wmb() in __loaded_vmcs_clear().
1261                  */
1262                 smp_rmb();
1263
1264                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1265                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1266                 local_irq_enable();
1267         }
1268
1269         prev = per_cpu(current_vmcs, cpu);
1270         if (prev != vmx->loaded_vmcs->vmcs) {
1271                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1272                 vmcs_load(vmx->loaded_vmcs->vmcs);
1273
1274                 /*
1275                  * No indirect branch prediction barrier needed when switching
1276                  * the active VMCS within a guest, e.g. on nested VM-Enter.
1277                  * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1278                  */
1279                 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1280                         indirect_branch_prediction_barrier();
1281         }
1282
1283         if (!already_loaded) {
1284                 void *gdt = get_current_gdt_ro();
1285                 unsigned long sysenter_esp;
1286
1287                 /*
1288                  * Flush all EPTP/VPID contexts, the new pCPU may have stale
1289                  * TLB entries from its previous association with the vCPU.
1290                  */
1291                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1292
1293                 /*
1294                  * Linux uses per-cpu TSS and GDT, so set these when switching
1295                  * processors.  See 22.2.4.
1296                  */
1297                 vmcs_writel(HOST_TR_BASE,
1298                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1299                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1300
1301                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1302                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1303
1304                 vmx->loaded_vmcs->cpu = cpu;
1305         }
1306 }
1307
1308 /*
1309  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1310  * vcpu mutex is already taken.
1311  */
1312 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1313 {
1314         struct vcpu_vmx *vmx = to_vmx(vcpu);
1315
1316         vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1317
1318         vmx_vcpu_pi_load(vcpu, cpu);
1319
1320         vmx->host_debugctlmsr = get_debugctlmsr();
1321 }
1322
1323 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1324 {
1325         vmx_vcpu_pi_put(vcpu);
1326
1327         vmx_prepare_switch_to_host(to_vmx(vcpu));
1328 }
1329
1330 bool vmx_emulation_required(struct kvm_vcpu *vcpu)
1331 {
1332         return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu);
1333 }
1334
1335 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1336 {
1337         struct vcpu_vmx *vmx = to_vmx(vcpu);
1338         unsigned long rflags, save_rflags;
1339
1340         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1341                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1342                 rflags = vmcs_readl(GUEST_RFLAGS);
1343                 if (vmx->rmode.vm86_active) {
1344                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1345                         save_rflags = vmx->rmode.save_rflags;
1346                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1347                 }
1348                 vmx->rflags = rflags;
1349         }
1350         return vmx->rflags;
1351 }
1352
1353 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1354 {
1355         struct vcpu_vmx *vmx = to_vmx(vcpu);
1356         unsigned long old_rflags;
1357
1358         if (is_unrestricted_guest(vcpu)) {
1359                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1360                 vmx->rflags = rflags;
1361                 vmcs_writel(GUEST_RFLAGS, rflags);
1362                 return;
1363         }
1364
1365         old_rflags = vmx_get_rflags(vcpu);
1366         vmx->rflags = rflags;
1367         if (vmx->rmode.vm86_active) {
1368                 vmx->rmode.save_rflags = rflags;
1369                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1370         }
1371         vmcs_writel(GUEST_RFLAGS, rflags);
1372
1373         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1374                 vmx->emulation_required = vmx_emulation_required(vcpu);
1375 }
1376
1377 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1378 {
1379         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1380         int ret = 0;
1381
1382         if (interruptibility & GUEST_INTR_STATE_STI)
1383                 ret |= KVM_X86_SHADOW_INT_STI;
1384         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1385                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1386
1387         return ret;
1388 }
1389
1390 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1391 {
1392         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1393         u32 interruptibility = interruptibility_old;
1394
1395         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1396
1397         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1398                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1399         else if (mask & KVM_X86_SHADOW_INT_STI)
1400                 interruptibility |= GUEST_INTR_STATE_STI;
1401
1402         if ((interruptibility != interruptibility_old))
1403                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1404 }
1405
1406 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1407 {
1408         struct vcpu_vmx *vmx = to_vmx(vcpu);
1409         unsigned long value;
1410
1411         /*
1412          * Any MSR write that attempts to change bits marked reserved will
1413          * case a #GP fault.
1414          */
1415         if (data & vmx->pt_desc.ctl_bitmask)
1416                 return 1;
1417
1418         /*
1419          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1420          * result in a #GP unless the same write also clears TraceEn.
1421          */
1422         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1423                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1424                 return 1;
1425
1426         /*
1427          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1428          * and FabricEn would cause #GP, if
1429          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1430          */
1431         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1432                 !(data & RTIT_CTL_FABRIC_EN) &&
1433                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1434                                         PT_CAP_single_range_output))
1435                 return 1;
1436
1437         /*
1438          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1439          * utilize encodings marked reserved will cause a #GP fault.
1440          */
1441         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1442         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1443                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1444                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1445                 return 1;
1446         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1447                                                 PT_CAP_cycle_thresholds);
1448         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1449                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1450                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1451                 return 1;
1452         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1453         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1454                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1455                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1456                 return 1;
1457
1458         /*
1459          * If ADDRx_CFG is reserved or the encodings is >2 will
1460          * cause a #GP fault.
1461          */
1462         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1463         if ((value && (vmx->pt_desc.num_address_ranges < 1)) || (value > 2))
1464                 return 1;
1465         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1466         if ((value && (vmx->pt_desc.num_address_ranges < 2)) || (value > 2))
1467                 return 1;
1468         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1469         if ((value && (vmx->pt_desc.num_address_ranges < 3)) || (value > 2))
1470                 return 1;
1471         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1472         if ((value && (vmx->pt_desc.num_address_ranges < 4)) || (value > 2))
1473                 return 1;
1474
1475         return 0;
1476 }
1477
1478 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
1479 {
1480         /*
1481          * Emulation of instructions in SGX enclaves is impossible as RIP does
1482          * not point  tthe failing instruction, and even if it did, the code
1483          * stream is inaccessible.  Inject #UD instead of exiting to userspace
1484          * so that guest userspace can't DoS the guest simply by triggering
1485          * emulation (enclaves are CPL3 only).
1486          */
1487         if (to_vmx(vcpu)->exit_reason.enclave_mode) {
1488                 kvm_queue_exception(vcpu, UD_VECTOR);
1489                 return false;
1490         }
1491         return true;
1492 }
1493
1494 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1495 {
1496         union vmx_exit_reason exit_reason = to_vmx(vcpu)->exit_reason;
1497         unsigned long rip, orig_rip;
1498         u32 instr_len;
1499
1500         /*
1501          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1502          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1503          * set when EPT misconfig occurs.  In practice, real hardware updates
1504          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1505          * (namely Hyper-V) don't set it due to it being undefined behavior,
1506          * i.e. we end up advancing IP with some random value.
1507          */
1508         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1509             exit_reason.basic != EXIT_REASON_EPT_MISCONFIG) {
1510                 instr_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1511
1512                 /*
1513                  * Emulating an enclave's instructions isn't supported as KVM
1514                  * cannot access the enclave's memory or its true RIP, e.g. the
1515                  * vmcs.GUEST_RIP points at the exit point of the enclave, not
1516                  * the RIP that actually triggered the VM-Exit.  But, because
1517                  * most instructions that cause VM-Exit will #UD in an enclave,
1518                  * most instruction-based VM-Exits simply do not occur.
1519                  *
1520                  * There are a few exceptions, notably the debug instructions
1521                  * INT1ICEBRK and INT3, as they are allowed in debug enclaves
1522                  * and generate #DB/#BP as expected, which KVM might intercept.
1523                  * But again, the CPU does the dirty work and saves an instr
1524                  * length of zero so VMMs don't shoot themselves in the foot.
1525                  * WARN if KVM tries to skip a non-zero length instruction on
1526                  * a VM-Exit from an enclave.
1527                  */
1528                 if (!instr_len)
1529                         goto rip_updated;
1530
1531                 WARN(exit_reason.enclave_mode,
1532                      "KVM: skipping instruction after SGX enclave VM-Exit");
1533
1534                 orig_rip = kvm_rip_read(vcpu);
1535                 rip = orig_rip + instr_len;
1536 #ifdef CONFIG_X86_64
1537                 /*
1538                  * We need to mask out the high 32 bits of RIP if not in 64-bit
1539                  * mode, but just finding out that we are in 64-bit mode is
1540                  * quite expensive.  Only do it if there was a carry.
1541                  */
1542                 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1543                         rip = (u32)rip;
1544 #endif
1545                 kvm_rip_write(vcpu, rip);
1546         } else {
1547                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1548                         return 0;
1549         }
1550
1551 rip_updated:
1552         /* skipping an emulated instruction also counts */
1553         vmx_set_interrupt_shadow(vcpu, 0);
1554
1555         return 1;
1556 }
1557
1558 /*
1559  * Recognizes a pending MTF VM-exit and records the nested state for later
1560  * delivery.
1561  */
1562 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1563 {
1564         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1565         struct vcpu_vmx *vmx = to_vmx(vcpu);
1566
1567         if (!is_guest_mode(vcpu))
1568                 return;
1569
1570         /*
1571          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1572          * T-bit traps. As instruction emulation is completed (i.e. at the
1573          * instruction boundary), any #DB exception pending delivery must be a
1574          * debug-trap. Record the pending MTF state to be delivered in
1575          * vmx_check_nested_events().
1576          */
1577         if (nested_cpu_has_mtf(vmcs12) &&
1578             (!vcpu->arch.exception.pending ||
1579              vcpu->arch.exception.nr == DB_VECTOR))
1580                 vmx->nested.mtf_pending = true;
1581         else
1582                 vmx->nested.mtf_pending = false;
1583 }
1584
1585 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1586 {
1587         vmx_update_emulated_instruction(vcpu);
1588         return skip_emulated_instruction(vcpu);
1589 }
1590
1591 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1592 {
1593         /*
1594          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1595          * explicitly skip the instruction because if the HLT state is set,
1596          * then the instruction is already executing and RIP has already been
1597          * advanced.
1598          */
1599         if (kvm_hlt_in_guest(vcpu->kvm) &&
1600                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1601                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1602 }
1603
1604 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1605 {
1606         struct vcpu_vmx *vmx = to_vmx(vcpu);
1607         unsigned nr = vcpu->arch.exception.nr;
1608         bool has_error_code = vcpu->arch.exception.has_error_code;
1609         u32 error_code = vcpu->arch.exception.error_code;
1610         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1611
1612         kvm_deliver_exception_payload(vcpu);
1613
1614         if (has_error_code) {
1615                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1616                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1617         }
1618
1619         if (vmx->rmode.vm86_active) {
1620                 int inc_eip = 0;
1621                 if (kvm_exception_is_soft(nr))
1622                         inc_eip = vcpu->arch.event_exit_inst_len;
1623                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1624                 return;
1625         }
1626
1627         WARN_ON_ONCE(vmx->emulation_required);
1628
1629         if (kvm_exception_is_soft(nr)) {
1630                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1631                              vmx->vcpu.arch.event_exit_inst_len);
1632                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1633         } else
1634                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1635
1636         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1637
1638         vmx_clear_hlt(vcpu);
1639 }
1640
1641 static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr,
1642                                bool load_into_hardware)
1643 {
1644         struct vmx_uret_msr *uret_msr;
1645
1646         uret_msr = vmx_find_uret_msr(vmx, msr);
1647         if (!uret_msr)
1648                 return;
1649
1650         uret_msr->load_into_hardware = load_into_hardware;
1651 }
1652
1653 /*
1654  * Configuring user return MSRs to automatically save, load, and restore MSRs
1655  * that need to be shoved into hardware when running the guest.  Note, omitting
1656  * an MSR here does _NOT_ mean it's not emulated, only that it will not be
1657  * loaded into hardware when running the guest.
1658  */
1659 static void vmx_setup_uret_msrs(struct vcpu_vmx *vmx)
1660 {
1661 #ifdef CONFIG_X86_64
1662         bool load_syscall_msrs;
1663
1664         /*
1665          * The SYSCALL MSRs are only needed on long mode guests, and only
1666          * when EFER.SCE is set.
1667          */
1668         load_syscall_msrs = is_long_mode(&vmx->vcpu) &&
1669                             (vmx->vcpu.arch.efer & EFER_SCE);
1670
1671         vmx_setup_uret_msr(vmx, MSR_STAR, load_syscall_msrs);
1672         vmx_setup_uret_msr(vmx, MSR_LSTAR, load_syscall_msrs);
1673         vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK, load_syscall_msrs);
1674 #endif
1675         vmx_setup_uret_msr(vmx, MSR_EFER, update_transition_efer(vmx));
1676
1677         vmx_setup_uret_msr(vmx, MSR_TSC_AUX,
1678                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP) ||
1679                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDPID));
1680
1681         /*
1682          * hle=0, rtm=0, tsx_ctrl=1 can be found with some combinations of new
1683          * kernel and old userspace.  If those guests run on a tsx=off host, do
1684          * allow guests to use TSX_CTRL, but don't change the value in hardware
1685          * so that TSX remains always disabled.
1686          */
1687         vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL, boot_cpu_has(X86_FEATURE_RTM));
1688
1689         /*
1690          * The set of MSRs to load may have changed, reload MSRs before the
1691          * next VM-Enter.
1692          */
1693         vmx->guest_uret_msrs_loaded = false;
1694 }
1695
1696 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1697 {
1698         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1699
1700         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING))
1701                 return vmcs12->tsc_offset;
1702
1703         return 0;
1704 }
1705
1706 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1707 {
1708         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1709
1710         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING) &&
1711             nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
1712                 return vmcs12->tsc_multiplier;
1713
1714         return kvm_default_tsc_scaling_ratio;
1715 }
1716
1717 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1718 {
1719         vmcs_write64(TSC_OFFSET, offset);
1720 }
1721
1722 static void vmx_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1723 {
1724         vmcs_write64(TSC_MULTIPLIER, multiplier);
1725 }
1726
1727 /*
1728  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1729  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1730  * all guests if the "nested" module option is off, and can also be disabled
1731  * for a single guest by disabling its VMX cpuid bit.
1732  */
1733 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1734 {
1735         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1736 }
1737
1738 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1739                                                  uint64_t val)
1740 {
1741         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1742
1743         return !(val & ~valid_bits);
1744 }
1745
1746 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1747 {
1748         switch (msr->index) {
1749         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1750                 if (!nested)
1751                         return 1;
1752                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1753         case MSR_IA32_PERF_CAPABILITIES:
1754                 msr->data = vmx_get_perf_capabilities();
1755                 return 0;
1756         default:
1757                 return KVM_MSR_RET_INVALID;
1758         }
1759 }
1760
1761 /*
1762  * Reads an msr value (of 'msr_index') into 'pdata'.
1763  * Returns 0 on success, non-0 otherwise.
1764  * Assumes vcpu_load() was already called.
1765  */
1766 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1767 {
1768         struct vcpu_vmx *vmx = to_vmx(vcpu);
1769         struct vmx_uret_msr *msr;
1770         u32 index;
1771
1772         switch (msr_info->index) {
1773 #ifdef CONFIG_X86_64
1774         case MSR_FS_BASE:
1775                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1776                 break;
1777         case MSR_GS_BASE:
1778                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1779                 break;
1780         case MSR_KERNEL_GS_BASE:
1781                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1782                 break;
1783 #endif
1784         case MSR_EFER:
1785                 return kvm_get_msr_common(vcpu, msr_info);
1786         case MSR_IA32_TSX_CTRL:
1787                 if (!msr_info->host_initiated &&
1788                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1789                         return 1;
1790                 goto find_uret_msr;
1791         case MSR_IA32_UMWAIT_CONTROL:
1792                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1793                         return 1;
1794
1795                 msr_info->data = vmx->msr_ia32_umwait_control;
1796                 break;
1797         case MSR_IA32_SPEC_CTRL:
1798                 if (!msr_info->host_initiated &&
1799                     !guest_has_spec_ctrl_msr(vcpu))
1800                         return 1;
1801
1802                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1803                 break;
1804         case MSR_IA32_SYSENTER_CS:
1805                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1806                 break;
1807         case MSR_IA32_SYSENTER_EIP:
1808                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1809                 break;
1810         case MSR_IA32_SYSENTER_ESP:
1811                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1812                 break;
1813         case MSR_IA32_BNDCFGS:
1814                 if (!kvm_mpx_supported() ||
1815                     (!msr_info->host_initiated &&
1816                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1817                         return 1;
1818                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1819                 break;
1820         case MSR_IA32_MCG_EXT_CTL:
1821                 if (!msr_info->host_initiated &&
1822                     !(vmx->msr_ia32_feature_control &
1823                       FEAT_CTL_LMCE_ENABLED))
1824                         return 1;
1825                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1826                 break;
1827         case MSR_IA32_FEAT_CTL:
1828                 msr_info->data = vmx->msr_ia32_feature_control;
1829                 break;
1830         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
1831                 if (!msr_info->host_initiated &&
1832                     !guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
1833                         return 1;
1834                 msr_info->data = to_vmx(vcpu)->msr_ia32_sgxlepubkeyhash
1835                         [msr_info->index - MSR_IA32_SGXLEPUBKEYHASH0];
1836                 break;
1837         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1838                 if (!nested_vmx_allowed(vcpu))
1839                         return 1;
1840                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1841                                     &msr_info->data))
1842                         return 1;
1843                 /*
1844                  * Enlightened VMCS v1 doesn't have certain VMCS fields but
1845                  * instead of just ignoring the features, different Hyper-V
1846                  * versions are either trying to use them and fail or do some
1847                  * sanity checking and refuse to boot. Filter all unsupported
1848                  * features out.
1849                  */
1850                 if (!msr_info->host_initiated &&
1851                     vmx->nested.enlightened_vmcs_enabled)
1852                         nested_evmcs_filter_control_msr(msr_info->index,
1853                                                         &msr_info->data);
1854                 break;
1855         case MSR_IA32_RTIT_CTL:
1856                 if (!vmx_pt_mode_is_host_guest())
1857                         return 1;
1858                 msr_info->data = vmx->pt_desc.guest.ctl;
1859                 break;
1860         case MSR_IA32_RTIT_STATUS:
1861                 if (!vmx_pt_mode_is_host_guest())
1862                         return 1;
1863                 msr_info->data = vmx->pt_desc.guest.status;
1864                 break;
1865         case MSR_IA32_RTIT_CR3_MATCH:
1866                 if (!vmx_pt_mode_is_host_guest() ||
1867                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1868                                                 PT_CAP_cr3_filtering))
1869                         return 1;
1870                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1871                 break;
1872         case MSR_IA32_RTIT_OUTPUT_BASE:
1873                 if (!vmx_pt_mode_is_host_guest() ||
1874                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1875                                         PT_CAP_topa_output) &&
1876                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1877                                         PT_CAP_single_range_output)))
1878                         return 1;
1879                 msr_info->data = vmx->pt_desc.guest.output_base;
1880                 break;
1881         case MSR_IA32_RTIT_OUTPUT_MASK:
1882                 if (!vmx_pt_mode_is_host_guest() ||
1883                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1884                                         PT_CAP_topa_output) &&
1885                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1886                                         PT_CAP_single_range_output)))
1887                         return 1;
1888                 msr_info->data = vmx->pt_desc.guest.output_mask;
1889                 break;
1890         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1891                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1892                 if (!vmx_pt_mode_is_host_guest() ||
1893                     (index >= 2 * vmx->pt_desc.num_address_ranges))
1894                         return 1;
1895                 if (index % 2)
1896                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1897                 else
1898                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1899                 break;
1900         case MSR_IA32_DEBUGCTLMSR:
1901                 msr_info->data = vmcs_read64(GUEST_IA32_DEBUGCTL);
1902                 break;
1903         default:
1904         find_uret_msr:
1905                 msr = vmx_find_uret_msr(vmx, msr_info->index);
1906                 if (msr) {
1907                         msr_info->data = msr->data;
1908                         break;
1909                 }
1910                 return kvm_get_msr_common(vcpu, msr_info);
1911         }
1912
1913         return 0;
1914 }
1915
1916 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1917                                                     u64 data)
1918 {
1919 #ifdef CONFIG_X86_64
1920         if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1921                 return (u32)data;
1922 #endif
1923         return (unsigned long)data;
1924 }
1925
1926 static u64 vcpu_supported_debugctl(struct kvm_vcpu *vcpu)
1927 {
1928         u64 debugctl = vmx_supported_debugctl();
1929
1930         if (!intel_pmu_lbr_is_enabled(vcpu))
1931                 debugctl &= ~DEBUGCTLMSR_LBR_MASK;
1932
1933         if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1934                 debugctl &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1935
1936         return debugctl;
1937 }
1938
1939 /*
1940  * Writes msr value into the appropriate "register".
1941  * Returns 0 on success, non-0 otherwise.
1942  * Assumes vcpu_load() was already called.
1943  */
1944 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1945 {
1946         struct vcpu_vmx *vmx = to_vmx(vcpu);
1947         struct vmx_uret_msr *msr;
1948         int ret = 0;
1949         u32 msr_index = msr_info->index;
1950         u64 data = msr_info->data;
1951         u32 index;
1952
1953         switch (msr_index) {
1954         case MSR_EFER:
1955                 ret = kvm_set_msr_common(vcpu, msr_info);
1956                 break;
1957 #ifdef CONFIG_X86_64
1958         case MSR_FS_BASE:
1959                 vmx_segment_cache_clear(vmx);
1960                 vmcs_writel(GUEST_FS_BASE, data);
1961                 break;
1962         case MSR_GS_BASE:
1963                 vmx_segment_cache_clear(vmx);
1964                 vmcs_writel(GUEST_GS_BASE, data);
1965                 break;
1966         case MSR_KERNEL_GS_BASE:
1967                 vmx_write_guest_kernel_gs_base(vmx, data);
1968                 break;
1969 #endif
1970         case MSR_IA32_SYSENTER_CS:
1971                 if (is_guest_mode(vcpu))
1972                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1973                 vmcs_write32(GUEST_SYSENTER_CS, data);
1974                 break;
1975         case MSR_IA32_SYSENTER_EIP:
1976                 if (is_guest_mode(vcpu)) {
1977                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1978                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1979                 }
1980                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1981                 break;
1982         case MSR_IA32_SYSENTER_ESP:
1983                 if (is_guest_mode(vcpu)) {
1984                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1985                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1986                 }
1987                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1988                 break;
1989         case MSR_IA32_DEBUGCTLMSR: {
1990                 u64 invalid = data & ~vcpu_supported_debugctl(vcpu);
1991                 if (invalid & (DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR)) {
1992                         if (report_ignored_msrs)
1993                                 vcpu_unimpl(vcpu, "%s: BTF|LBR in IA32_DEBUGCTLMSR 0x%llx, nop\n",
1994                                             __func__, data);
1995                         data &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1996                         invalid &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1997                 }
1998
1999                 if (invalid)
2000                         return 1;
2001
2002                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
2003                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
2004                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2005
2006                 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
2007                 if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event &&
2008                     (data & DEBUGCTLMSR_LBR))
2009                         intel_pmu_create_guest_lbr_event(vcpu);
2010                 return 0;
2011         }
2012         case MSR_IA32_BNDCFGS:
2013                 if (!kvm_mpx_supported() ||
2014                     (!msr_info->host_initiated &&
2015                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2016                         return 1;
2017                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2018                     (data & MSR_IA32_BNDCFGS_RSVD))
2019                         return 1;
2020                 vmcs_write64(GUEST_BNDCFGS, data);
2021                 break;
2022         case MSR_IA32_UMWAIT_CONTROL:
2023                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2024                         return 1;
2025
2026                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2027                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2028                         return 1;
2029
2030                 vmx->msr_ia32_umwait_control = data;
2031                 break;
2032         case MSR_IA32_SPEC_CTRL:
2033                 if (!msr_info->host_initiated &&
2034                     !guest_has_spec_ctrl_msr(vcpu))
2035                         return 1;
2036
2037                 if (kvm_spec_ctrl_test_value(data))
2038                         return 1;
2039
2040                 vmx->spec_ctrl = data;
2041                 if (!data)
2042                         break;
2043
2044                 /*
2045                  * For non-nested:
2046                  * When it's written (to non-zero) for the first time, pass
2047                  * it through.
2048                  *
2049                  * For nested:
2050                  * The handling of the MSR bitmap for L2 guests is done in
2051                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2052                  * vmcs02.msr_bitmap here since it gets completely overwritten
2053                  * in the merging. We update the vmcs01 here for L1 as well
2054                  * since it will end up touching the MSR anyway now.
2055                  */
2056                 vmx_disable_intercept_for_msr(vcpu,
2057                                               MSR_IA32_SPEC_CTRL,
2058                                               MSR_TYPE_RW);
2059                 break;
2060         case MSR_IA32_TSX_CTRL:
2061                 if (!msr_info->host_initiated &&
2062                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2063                         return 1;
2064                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2065                         return 1;
2066                 goto find_uret_msr;
2067         case MSR_IA32_PRED_CMD:
2068                 if (!msr_info->host_initiated &&
2069                     !guest_has_pred_cmd_msr(vcpu))
2070                         return 1;
2071
2072                 if (data & ~PRED_CMD_IBPB)
2073                         return 1;
2074                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2075                         return 1;
2076                 if (!data)
2077                         break;
2078
2079                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2080
2081                 /*
2082                  * For non-nested:
2083                  * When it's written (to non-zero) for the first time, pass
2084                  * it through.
2085                  *
2086                  * For nested:
2087                  * The handling of the MSR bitmap for L2 guests is done in
2088                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2089                  * vmcs02.msr_bitmap here since it gets completely overwritten
2090                  * in the merging.
2091                  */
2092                 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
2093                 break;
2094         case MSR_IA32_CR_PAT:
2095                 if (!kvm_pat_valid(data))
2096                         return 1;
2097
2098                 if (is_guest_mode(vcpu) &&
2099                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2100                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2101
2102                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2103                         vmcs_write64(GUEST_IA32_PAT, data);
2104                         vcpu->arch.pat = data;
2105                         break;
2106                 }
2107                 ret = kvm_set_msr_common(vcpu, msr_info);
2108                 break;
2109         case MSR_IA32_TSC_ADJUST:
2110                 ret = kvm_set_msr_common(vcpu, msr_info);
2111                 break;
2112         case MSR_IA32_MCG_EXT_CTL:
2113                 if ((!msr_info->host_initiated &&
2114                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2115                        FEAT_CTL_LMCE_ENABLED)) ||
2116                     (data & ~MCG_EXT_CTL_LMCE_EN))
2117                         return 1;
2118                 vcpu->arch.mcg_ext_ctl = data;
2119                 break;
2120         case MSR_IA32_FEAT_CTL:
2121                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2122                     (to_vmx(vcpu)->msr_ia32_feature_control &
2123                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2124                         return 1;
2125                 vmx->msr_ia32_feature_control = data;
2126                 if (msr_info->host_initiated && data == 0)
2127                         vmx_leave_nested(vcpu);
2128
2129                 /* SGX may be enabled/disabled by guest's firmware */
2130                 vmx_write_encls_bitmap(vcpu, NULL);
2131                 break;
2132         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
2133                 /*
2134                  * On real hardware, the LE hash MSRs are writable before
2135                  * the firmware sets bit 0 in MSR 0x7a ("activating" SGX),
2136                  * at which point SGX related bits in IA32_FEATURE_CONTROL
2137                  * become writable.
2138                  *
2139                  * KVM does not emulate SGX activation for simplicity, so
2140                  * allow writes to the LE hash MSRs if IA32_FEATURE_CONTROL
2141                  * is unlocked.  This is technically not architectural
2142                  * behavior, but it's close enough.
2143                  */
2144                 if (!msr_info->host_initiated &&
2145                     (!guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC) ||
2146                     ((vmx->msr_ia32_feature_control & FEAT_CTL_LOCKED) &&
2147                     !(vmx->msr_ia32_feature_control & FEAT_CTL_SGX_LC_ENABLED))))
2148                         return 1;
2149                 vmx->msr_ia32_sgxlepubkeyhash
2150                         [msr_index - MSR_IA32_SGXLEPUBKEYHASH0] = data;
2151                 break;
2152         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2153                 if (!msr_info->host_initiated)
2154                         return 1; /* they are read-only */
2155                 if (!nested_vmx_allowed(vcpu))
2156                         return 1;
2157                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2158         case MSR_IA32_RTIT_CTL:
2159                 if (!vmx_pt_mode_is_host_guest() ||
2160                         vmx_rtit_ctl_check(vcpu, data) ||
2161                         vmx->nested.vmxon)
2162                         return 1;
2163                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2164                 vmx->pt_desc.guest.ctl = data;
2165                 pt_update_intercept_for_msr(vcpu);
2166                 break;
2167         case MSR_IA32_RTIT_STATUS:
2168                 if (!pt_can_write_msr(vmx))
2169                         return 1;
2170                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2171                         return 1;
2172                 vmx->pt_desc.guest.status = data;
2173                 break;
2174         case MSR_IA32_RTIT_CR3_MATCH:
2175                 if (!pt_can_write_msr(vmx))
2176                         return 1;
2177                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2178                                            PT_CAP_cr3_filtering))
2179                         return 1;
2180                 vmx->pt_desc.guest.cr3_match = data;
2181                 break;
2182         case MSR_IA32_RTIT_OUTPUT_BASE:
2183                 if (!pt_can_write_msr(vmx))
2184                         return 1;
2185                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2186                                            PT_CAP_topa_output) &&
2187                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2188                                            PT_CAP_single_range_output))
2189                         return 1;
2190                 if (!pt_output_base_valid(vcpu, data))
2191                         return 1;
2192                 vmx->pt_desc.guest.output_base = data;
2193                 break;
2194         case MSR_IA32_RTIT_OUTPUT_MASK:
2195                 if (!pt_can_write_msr(vmx))
2196                         return 1;
2197                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2198                                            PT_CAP_topa_output) &&
2199                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2200                                            PT_CAP_single_range_output))
2201                         return 1;
2202                 vmx->pt_desc.guest.output_mask = data;
2203                 break;
2204         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2205                 if (!pt_can_write_msr(vmx))
2206                         return 1;
2207                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2208                 if (index >= 2 * vmx->pt_desc.num_address_ranges)
2209                         return 1;
2210                 if (is_noncanonical_address(data, vcpu))
2211                         return 1;
2212                 if (index % 2)
2213                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2214                 else
2215                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2216                 break;
2217         case MSR_IA32_PERF_CAPABILITIES:
2218                 if (data && !vcpu_to_pmu(vcpu)->version)
2219                         return 1;
2220                 if (data & PMU_CAP_LBR_FMT) {
2221                         if ((data & PMU_CAP_LBR_FMT) !=
2222                             (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
2223                                 return 1;
2224                         if (!intel_pmu_lbr_is_compatible(vcpu))
2225                                 return 1;
2226                 }
2227                 ret = kvm_set_msr_common(vcpu, msr_info);
2228                 break;
2229
2230         default:
2231         find_uret_msr:
2232                 msr = vmx_find_uret_msr(vmx, msr_index);
2233                 if (msr)
2234                         ret = vmx_set_guest_uret_msr(vmx, msr, data);
2235                 else
2236                         ret = kvm_set_msr_common(vcpu, msr_info);
2237         }
2238
2239         return ret;
2240 }
2241
2242 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2243 {
2244         unsigned long guest_owned_bits;
2245
2246         kvm_register_mark_available(vcpu, reg);
2247
2248         switch (reg) {
2249         case VCPU_REGS_RSP:
2250                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2251                 break;
2252         case VCPU_REGS_RIP:
2253                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2254                 break;
2255         case VCPU_EXREG_PDPTR:
2256                 if (enable_ept)
2257                         ept_save_pdptrs(vcpu);
2258                 break;
2259         case VCPU_EXREG_CR0:
2260                 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2261
2262                 vcpu->arch.cr0 &= ~guest_owned_bits;
2263                 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2264                 break;
2265         case VCPU_EXREG_CR3:
2266                 /*
2267                  * When intercepting CR3 loads, e.g. for shadowing paging, KVM's
2268                  * CR3 is loaded into hardware, not the guest's CR3.
2269                  */
2270                 if (!(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_CR3_LOAD_EXITING))
2271                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2272                 break;
2273         case VCPU_EXREG_CR4:
2274                 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2275
2276                 vcpu->arch.cr4 &= ~guest_owned_bits;
2277                 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2278                 break;
2279         default:
2280                 KVM_BUG_ON(1, vcpu->kvm);
2281                 break;
2282         }
2283 }
2284
2285 static __init int cpu_has_kvm_support(void)
2286 {
2287         return cpu_has_vmx();
2288 }
2289
2290 static __init int vmx_disabled_by_bios(void)
2291 {
2292         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2293                !boot_cpu_has(X86_FEATURE_VMX);
2294 }
2295
2296 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2297 {
2298         u64 msr;
2299
2300         cr4_set_bits(X86_CR4_VMXE);
2301
2302         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2303                           _ASM_EXTABLE(1b, %l[fault])
2304                           : : [vmxon_pointer] "m"(vmxon_pointer)
2305                           : : fault);
2306         return 0;
2307
2308 fault:
2309         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2310                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2311         cr4_clear_bits(X86_CR4_VMXE);
2312
2313         return -EFAULT;
2314 }
2315
2316 static int hardware_enable(void)
2317 {
2318         int cpu = raw_smp_processor_id();
2319         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2320         int r;
2321
2322         if (cr4_read_shadow() & X86_CR4_VMXE)
2323                 return -EBUSY;
2324
2325         /*
2326          * This can happen if we hot-added a CPU but failed to allocate
2327          * VP assist page for it.
2328          */
2329         if (static_branch_unlikely(&enable_evmcs) &&
2330             !hv_get_vp_assist_page(cpu))
2331                 return -EFAULT;
2332
2333         intel_pt_handle_vmx(1);
2334
2335         r = kvm_cpu_vmxon(phys_addr);
2336         if (r) {
2337                 intel_pt_handle_vmx(0);
2338                 return r;
2339         }
2340
2341         if (enable_ept)
2342                 ept_sync_global();
2343
2344         return 0;
2345 }
2346
2347 static void vmclear_local_loaded_vmcss(void)
2348 {
2349         int cpu = raw_smp_processor_id();
2350         struct loaded_vmcs *v, *n;
2351
2352         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2353                                  loaded_vmcss_on_cpu_link)
2354                 __loaded_vmcs_clear(v);
2355 }
2356
2357 static void hardware_disable(void)
2358 {
2359         vmclear_local_loaded_vmcss();
2360
2361         if (cpu_vmxoff())
2362                 kvm_spurious_fault();
2363
2364         intel_pt_handle_vmx(0);
2365 }
2366
2367 /*
2368  * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2369  * directly instead of going through cpu_has(), to ensure KVM is trapping
2370  * ENCLS whenever it's supported in hardware.  It does not matter whether
2371  * the host OS supports or has enabled SGX.
2372  */
2373 static bool cpu_has_sgx(void)
2374 {
2375         return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2376 }
2377
2378 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2379                                       u32 msr, u32 *result)
2380 {
2381         u32 vmx_msr_low, vmx_msr_high;
2382         u32 ctl = ctl_min | ctl_opt;
2383
2384         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2385
2386         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2387         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2388
2389         /* Ensure minimum (required) set of control bits are supported. */
2390         if (ctl_min & ~ctl)
2391                 return -EIO;
2392
2393         *result = ctl;
2394         return 0;
2395 }
2396
2397 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2398                                     struct vmx_capability *vmx_cap)
2399 {
2400         u32 vmx_msr_low, vmx_msr_high;
2401         u32 min, opt, min2, opt2;
2402         u32 _pin_based_exec_control = 0;
2403         u32 _cpu_based_exec_control = 0;
2404         u32 _cpu_based_2nd_exec_control = 0;
2405         u32 _vmexit_control = 0;
2406         u32 _vmentry_control = 0;
2407
2408         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2409         min = CPU_BASED_HLT_EXITING |
2410 #ifdef CONFIG_X86_64
2411               CPU_BASED_CR8_LOAD_EXITING |
2412               CPU_BASED_CR8_STORE_EXITING |
2413 #endif
2414               CPU_BASED_CR3_LOAD_EXITING |
2415               CPU_BASED_CR3_STORE_EXITING |
2416               CPU_BASED_UNCOND_IO_EXITING |
2417               CPU_BASED_MOV_DR_EXITING |
2418               CPU_BASED_USE_TSC_OFFSETTING |
2419               CPU_BASED_MWAIT_EXITING |
2420               CPU_BASED_MONITOR_EXITING |
2421               CPU_BASED_INVLPG_EXITING |
2422               CPU_BASED_RDPMC_EXITING;
2423
2424         opt = CPU_BASED_TPR_SHADOW |
2425               CPU_BASED_USE_MSR_BITMAPS |
2426               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2427         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2428                                 &_cpu_based_exec_control) < 0)
2429                 return -EIO;
2430 #ifdef CONFIG_X86_64
2431         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2432                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2433                                            ~CPU_BASED_CR8_STORE_EXITING;
2434 #endif
2435         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2436                 min2 = 0;
2437                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2438                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2439                         SECONDARY_EXEC_WBINVD_EXITING |
2440                         SECONDARY_EXEC_ENABLE_VPID |
2441                         SECONDARY_EXEC_ENABLE_EPT |
2442                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2443                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2444                         SECONDARY_EXEC_DESC |
2445                         SECONDARY_EXEC_ENABLE_RDTSCP |
2446                         SECONDARY_EXEC_ENABLE_INVPCID |
2447                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2448                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2449                         SECONDARY_EXEC_SHADOW_VMCS |
2450                         SECONDARY_EXEC_XSAVES |
2451                         SECONDARY_EXEC_RDSEED_EXITING |
2452                         SECONDARY_EXEC_RDRAND_EXITING |
2453                         SECONDARY_EXEC_ENABLE_PML |
2454                         SECONDARY_EXEC_TSC_SCALING |
2455                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2456                         SECONDARY_EXEC_PT_USE_GPA |
2457                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2458                         SECONDARY_EXEC_ENABLE_VMFUNC |
2459                         SECONDARY_EXEC_BUS_LOCK_DETECTION;
2460                 if (cpu_has_sgx())
2461                         opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2462                 if (adjust_vmx_controls(min2, opt2,
2463                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2464                                         &_cpu_based_2nd_exec_control) < 0)
2465                         return -EIO;
2466         }
2467 #ifndef CONFIG_X86_64
2468         if (!(_cpu_based_2nd_exec_control &
2469                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2470                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2471 #endif
2472
2473         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2474                 _cpu_based_2nd_exec_control &= ~(
2475                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2476                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2477                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2478
2479         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2480                 &vmx_cap->ept, &vmx_cap->vpid);
2481
2482         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2483                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2484                    enabled */
2485                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2486                                              CPU_BASED_CR3_STORE_EXITING |
2487                                              CPU_BASED_INVLPG_EXITING);
2488         } else if (vmx_cap->ept) {
2489                 vmx_cap->ept = 0;
2490                 pr_warn_once("EPT CAP should not exist if not support "
2491                                 "1-setting enable EPT VM-execution control\n");
2492         }
2493         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2494                 vmx_cap->vpid) {
2495                 vmx_cap->vpid = 0;
2496                 pr_warn_once("VPID CAP should not exist if not support "
2497                                 "1-setting enable VPID VM-execution control\n");
2498         }
2499
2500         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2501 #ifdef CONFIG_X86_64
2502         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2503 #endif
2504         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2505               VM_EXIT_LOAD_IA32_PAT |
2506               VM_EXIT_LOAD_IA32_EFER |
2507               VM_EXIT_CLEAR_BNDCFGS |
2508               VM_EXIT_PT_CONCEAL_PIP |
2509               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2510         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2511                                 &_vmexit_control) < 0)
2512                 return -EIO;
2513
2514         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2515         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2516                  PIN_BASED_VMX_PREEMPTION_TIMER;
2517         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2518                                 &_pin_based_exec_control) < 0)
2519                 return -EIO;
2520
2521         if (cpu_has_broken_vmx_preemption_timer())
2522                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2523         if (!(_cpu_based_2nd_exec_control &
2524                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2525                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2526
2527         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2528         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2529               VM_ENTRY_LOAD_IA32_PAT |
2530               VM_ENTRY_LOAD_IA32_EFER |
2531               VM_ENTRY_LOAD_BNDCFGS |
2532               VM_ENTRY_PT_CONCEAL_PIP |
2533               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2534         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2535                                 &_vmentry_control) < 0)
2536                 return -EIO;
2537
2538         /*
2539          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2540          * can't be used due to an errata where VM Exit may incorrectly clear
2541          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2542          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2543          */
2544         if (boot_cpu_data.x86 == 0x6) {
2545                 switch (boot_cpu_data.x86_model) {
2546                 case 26: /* AAK155 */
2547                 case 30: /* AAP115 */
2548                 case 37: /* AAT100 */
2549                 case 44: /* BC86,AAY89,BD102 */
2550                 case 46: /* BA97 */
2551                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2552                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2553                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2554                                         "does not work properly. Using workaround\n");
2555                         break;
2556                 default:
2557                         break;
2558                 }
2559         }
2560
2561
2562         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2563
2564         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2565         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2566                 return -EIO;
2567
2568 #ifdef CONFIG_X86_64
2569         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2570         if (vmx_msr_high & (1u<<16))
2571                 return -EIO;
2572 #endif
2573
2574         /* Require Write-Back (WB) memory type for VMCS accesses. */
2575         if (((vmx_msr_high >> 18) & 15) != 6)
2576                 return -EIO;
2577
2578         vmcs_conf->size = vmx_msr_high & 0x1fff;
2579         vmcs_conf->order = get_order(vmcs_conf->size);
2580         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2581
2582         vmcs_conf->revision_id = vmx_msr_low;
2583
2584         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2585         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2586         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2587         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2588         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2589
2590 #if IS_ENABLED(CONFIG_HYPERV)
2591         if (enlightened_vmcs)
2592                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2593 #endif
2594
2595         return 0;
2596 }
2597
2598 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2599 {
2600         int node = cpu_to_node(cpu);
2601         struct page *pages;
2602         struct vmcs *vmcs;
2603
2604         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2605         if (!pages)
2606                 return NULL;
2607         vmcs = page_address(pages);
2608         memset(vmcs, 0, vmcs_config.size);
2609
2610         /* KVM supports Enlightened VMCS v1 only */
2611         if (static_branch_unlikely(&enable_evmcs))
2612                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2613         else
2614                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2615
2616         if (shadow)
2617                 vmcs->hdr.shadow_vmcs = 1;
2618         return vmcs;
2619 }
2620
2621 void free_vmcs(struct vmcs *vmcs)
2622 {
2623         free_pages((unsigned long)vmcs, vmcs_config.order);
2624 }
2625
2626 /*
2627  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2628  */
2629 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2630 {
2631         if (!loaded_vmcs->vmcs)
2632                 return;
2633         loaded_vmcs_clear(loaded_vmcs);
2634         free_vmcs(loaded_vmcs->vmcs);
2635         loaded_vmcs->vmcs = NULL;
2636         if (loaded_vmcs->msr_bitmap)
2637                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2638         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2639 }
2640
2641 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2642 {
2643         loaded_vmcs->vmcs = alloc_vmcs(false);
2644         if (!loaded_vmcs->vmcs)
2645                 return -ENOMEM;
2646
2647         vmcs_clear(loaded_vmcs->vmcs);
2648
2649         loaded_vmcs->shadow_vmcs = NULL;
2650         loaded_vmcs->hv_timer_soft_disabled = false;
2651         loaded_vmcs->cpu = -1;
2652         loaded_vmcs->launched = 0;
2653
2654         if (cpu_has_vmx_msr_bitmap()) {
2655                 loaded_vmcs->msr_bitmap = (unsigned long *)
2656                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2657                 if (!loaded_vmcs->msr_bitmap)
2658                         goto out_vmcs;
2659                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2660
2661                 if (IS_ENABLED(CONFIG_HYPERV) &&
2662                     static_branch_unlikely(&enable_evmcs) &&
2663                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2664                         struct hv_enlightened_vmcs *evmcs =
2665                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2666
2667                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2668                 }
2669         }
2670
2671         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2672         memset(&loaded_vmcs->controls_shadow, 0,
2673                 sizeof(struct vmcs_controls_shadow));
2674
2675         return 0;
2676
2677 out_vmcs:
2678         free_loaded_vmcs(loaded_vmcs);
2679         return -ENOMEM;
2680 }
2681
2682 static void free_kvm_area(void)
2683 {
2684         int cpu;
2685
2686         for_each_possible_cpu(cpu) {
2687                 free_vmcs(per_cpu(vmxarea, cpu));
2688                 per_cpu(vmxarea, cpu) = NULL;
2689         }
2690 }
2691
2692 static __init int alloc_kvm_area(void)
2693 {
2694         int cpu;
2695
2696         for_each_possible_cpu(cpu) {
2697                 struct vmcs *vmcs;
2698
2699                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2700                 if (!vmcs) {
2701                         free_kvm_area();
2702                         return -ENOMEM;
2703                 }
2704
2705                 /*
2706                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2707                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2708                  * revision_id reported by MSR_IA32_VMX_BASIC.
2709                  *
2710                  * However, even though not explicitly documented by
2711                  * TLFS, VMXArea passed as VMXON argument should
2712                  * still be marked with revision_id reported by
2713                  * physical CPU.
2714                  */
2715                 if (static_branch_unlikely(&enable_evmcs))
2716                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2717
2718                 per_cpu(vmxarea, cpu) = vmcs;
2719         }
2720         return 0;
2721 }
2722
2723 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2724                 struct kvm_segment *save)
2725 {
2726         if (!emulate_invalid_guest_state) {
2727                 /*
2728                  * CS and SS RPL should be equal during guest entry according
2729                  * to VMX spec, but in reality it is not always so. Since vcpu
2730                  * is in the middle of the transition from real mode to
2731                  * protected mode it is safe to assume that RPL 0 is a good
2732                  * default value.
2733                  */
2734                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2735                         save->selector &= ~SEGMENT_RPL_MASK;
2736                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2737                 save->s = 1;
2738         }
2739         __vmx_set_segment(vcpu, save, seg);
2740 }
2741
2742 static void enter_pmode(struct kvm_vcpu *vcpu)
2743 {
2744         unsigned long flags;
2745         struct vcpu_vmx *vmx = to_vmx(vcpu);
2746
2747         /*
2748          * Update real mode segment cache. It may be not up-to-date if segment
2749          * register was written while vcpu was in a guest mode.
2750          */
2751         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2752         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2753         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2754         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2755         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2756         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2757
2758         vmx->rmode.vm86_active = 0;
2759
2760         __vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2761
2762         flags = vmcs_readl(GUEST_RFLAGS);
2763         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2764         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2765         vmcs_writel(GUEST_RFLAGS, flags);
2766
2767         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2768                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2769
2770         vmx_update_exception_bitmap(vcpu);
2771
2772         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2773         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2774         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2775         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2776         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2777         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2778 }
2779
2780 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2781 {
2782         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2783         struct kvm_segment var = *save;
2784
2785         var.dpl = 0x3;
2786         if (seg == VCPU_SREG_CS)
2787                 var.type = 0x3;
2788
2789         if (!emulate_invalid_guest_state) {
2790                 var.selector = var.base >> 4;
2791                 var.base = var.base & 0xffff0;
2792                 var.limit = 0xffff;
2793                 var.g = 0;
2794                 var.db = 0;
2795                 var.present = 1;
2796                 var.s = 1;
2797                 var.l = 0;
2798                 var.unusable = 0;
2799                 var.type = 0x3;
2800                 var.avl = 0;
2801                 if (save->base & 0xf)
2802                         printk_once(KERN_WARNING "kvm: segment base is not "
2803                                         "paragraph aligned when entering "
2804                                         "protected mode (seg=%d)", seg);
2805         }
2806
2807         vmcs_write16(sf->selector, var.selector);
2808         vmcs_writel(sf->base, var.base);
2809         vmcs_write32(sf->limit, var.limit);
2810         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2811 }
2812
2813 static void enter_rmode(struct kvm_vcpu *vcpu)
2814 {
2815         unsigned long flags;
2816         struct vcpu_vmx *vmx = to_vmx(vcpu);
2817         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2818
2819         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2820         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2821         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2822         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2823         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2824         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2825         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2826
2827         vmx->rmode.vm86_active = 1;
2828
2829         /*
2830          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2831          * vcpu. Warn the user that an update is overdue.
2832          */
2833         if (!kvm_vmx->tss_addr)
2834                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2835                              "called before entering vcpu\n");
2836
2837         vmx_segment_cache_clear(vmx);
2838
2839         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2840         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2841         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2842
2843         flags = vmcs_readl(GUEST_RFLAGS);
2844         vmx->rmode.save_rflags = flags;
2845
2846         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2847
2848         vmcs_writel(GUEST_RFLAGS, flags);
2849         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2850         vmx_update_exception_bitmap(vcpu);
2851
2852         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2853         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2854         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2855         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2856         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2857         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2858 }
2859
2860 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2861 {
2862         struct vcpu_vmx *vmx = to_vmx(vcpu);
2863         struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER);
2864
2865         /* Nothing to do if hardware doesn't support EFER. */
2866         if (!msr)
2867                 return 0;
2868
2869         vcpu->arch.efer = efer;
2870         if (efer & EFER_LMA) {
2871                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2872                 msr->data = efer;
2873         } else {
2874                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2875
2876                 msr->data = efer & ~EFER_LME;
2877         }
2878         vmx_setup_uret_msrs(vmx);
2879         return 0;
2880 }
2881
2882 #ifdef CONFIG_X86_64
2883
2884 static void enter_lmode(struct kvm_vcpu *vcpu)
2885 {
2886         u32 guest_tr_ar;
2887
2888         vmx_segment_cache_clear(to_vmx(vcpu));
2889
2890         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2891         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2892                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2893                                      __func__);
2894                 vmcs_write32(GUEST_TR_AR_BYTES,
2895                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2896                              | VMX_AR_TYPE_BUSY_64_TSS);
2897         }
2898         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2899 }
2900
2901 static void exit_lmode(struct kvm_vcpu *vcpu)
2902 {
2903         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2904         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2905 }
2906
2907 #endif
2908
2909 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2910 {
2911         struct vcpu_vmx *vmx = to_vmx(vcpu);
2912
2913         /*
2914          * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2915          * the CPU is not required to invalidate guest-physical mappings on
2916          * VM-Entry, even if VPID is disabled.  Guest-physical mappings are
2917          * associated with the root EPT structure and not any particular VPID
2918          * (INVVPID also isn't required to invalidate guest-physical mappings).
2919          */
2920         if (enable_ept) {
2921                 ept_sync_global();
2922         } else if (enable_vpid) {
2923                 if (cpu_has_vmx_invvpid_global()) {
2924                         vpid_sync_vcpu_global();
2925                 } else {
2926                         vpid_sync_vcpu_single(vmx->vpid);
2927                         vpid_sync_vcpu_single(vmx->nested.vpid02);
2928                 }
2929         }
2930 }
2931
2932 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2933 {
2934         struct kvm_mmu *mmu = vcpu->arch.mmu;
2935         u64 root_hpa = mmu->root_hpa;
2936
2937         /* No flush required if the current context is invalid. */
2938         if (!VALID_PAGE(root_hpa))
2939                 return;
2940
2941         if (enable_ept)
2942                 ept_sync_context(construct_eptp(vcpu, root_hpa,
2943                                                 mmu->shadow_root_level));
2944         else if (!is_guest_mode(vcpu))
2945                 vpid_sync_context(to_vmx(vcpu)->vpid);
2946         else
2947                 vpid_sync_context(nested_get_vpid02(vcpu));
2948 }
2949
2950 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2951 {
2952         /*
2953          * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2954          * vmx_flush_tlb_guest() for an explanation of why this is ok.
2955          */
2956         vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2957 }
2958
2959 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2960 {
2961         /*
2962          * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2963          * or a vpid couldn't be allocated for this vCPU.  VM-Enter and VM-Exit
2964          * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2965          * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2966          * i.e. no explicit INVVPID is necessary.
2967          */
2968         vpid_sync_context(to_vmx(vcpu)->vpid);
2969 }
2970
2971 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2972 {
2973         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2974
2975         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2976                 return;
2977
2978         if (is_pae_paging(vcpu)) {
2979                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2980                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2981                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2982                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2983         }
2984 }
2985
2986 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2987 {
2988         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2989
2990         if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2991                 return;
2992
2993         mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2994         mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2995         mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2996         mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2997
2998         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2999 }
3000
3001 #define CR3_EXITING_BITS (CPU_BASED_CR3_LOAD_EXITING | \
3002                           CPU_BASED_CR3_STORE_EXITING)
3003
3004 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3005 {
3006         struct vcpu_vmx *vmx = to_vmx(vcpu);
3007         unsigned long hw_cr0, old_cr0_pg;
3008         u32 tmp;
3009
3010         old_cr0_pg = kvm_read_cr0_bits(vcpu, X86_CR0_PG);
3011
3012         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3013         if (is_unrestricted_guest(vcpu))
3014                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3015         else {
3016                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3017                 if (!enable_ept)
3018                         hw_cr0 |= X86_CR0_WP;
3019
3020                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3021                         enter_pmode(vcpu);
3022
3023                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3024                         enter_rmode(vcpu);
3025         }
3026
3027         vmcs_writel(CR0_READ_SHADOW, cr0);
3028         vmcs_writel(GUEST_CR0, hw_cr0);
3029         vcpu->arch.cr0 = cr0;
3030         kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3031
3032 #ifdef CONFIG_X86_64
3033         if (vcpu->arch.efer & EFER_LME) {
3034                 if (!old_cr0_pg && (cr0 & X86_CR0_PG))
3035                         enter_lmode(vcpu);
3036                 else if (old_cr0_pg && !(cr0 & X86_CR0_PG))
3037                         exit_lmode(vcpu);
3038         }
3039 #endif
3040
3041         if (enable_ept && !is_unrestricted_guest(vcpu)) {
3042                 /*
3043                  * Ensure KVM has an up-to-date snapshot of the guest's CR3.  If
3044                  * the below code _enables_ CR3 exiting, vmx_cache_reg() will
3045                  * (correctly) stop reading vmcs.GUEST_CR3 because it thinks
3046                  * KVM's CR3 is installed.
3047                  */
3048                 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
3049                         vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
3050
3051                 /*
3052                  * When running with EPT but not unrestricted guest, KVM must
3053                  * intercept CR3 accesses when paging is _disabled_.  This is
3054                  * necessary because restricted guests can't actually run with
3055                  * paging disabled, and so KVM stuffs its own CR3 in order to
3056                  * run the guest when identity mapped page tables.
3057                  *
3058                  * Do _NOT_ check the old CR0.PG, e.g. to optimize away the
3059                  * update, it may be stale with respect to CR3 interception,
3060                  * e.g. after nested VM-Enter.
3061                  *
3062                  * Lastly, honor L1's desires, i.e. intercept CR3 loads and/or
3063                  * stores to forward them to L1, even if KVM does not need to
3064                  * intercept them to preserve its identity mapped page tables.
3065                  */
3066                 if (!(cr0 & X86_CR0_PG)) {
3067                         exec_controls_setbit(vmx, CR3_EXITING_BITS);
3068                 } else if (!is_guest_mode(vcpu)) {
3069                         exec_controls_clearbit(vmx, CR3_EXITING_BITS);
3070                 } else {
3071                         tmp = exec_controls_get(vmx);
3072                         tmp &= ~CR3_EXITING_BITS;
3073                         tmp |= get_vmcs12(vcpu)->cpu_based_vm_exec_control & CR3_EXITING_BITS;
3074                         exec_controls_set(vmx, tmp);
3075                 }
3076
3077                 /* Note, vmx_set_cr4() consumes the new vcpu->arch.cr0. */
3078                 if ((old_cr0_pg ^ cr0) & X86_CR0_PG)
3079                         vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3080         }
3081
3082         /* depends on vcpu->arch.cr0 to be set to a new value */
3083         vmx->emulation_required = vmx_emulation_required(vcpu);
3084 }
3085
3086 static int vmx_get_max_tdp_level(void)
3087 {
3088         if (cpu_has_vmx_ept_5levels())
3089                 return 5;
3090         return 4;
3091 }
3092
3093 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level)
3094 {
3095         u64 eptp = VMX_EPTP_MT_WB;
3096
3097         eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3098
3099         if (enable_ept_ad_bits &&
3100             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3101                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3102         eptp |= root_hpa;
3103
3104         return eptp;
3105 }
3106
3107 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3108                              int root_level)
3109 {
3110         struct kvm *kvm = vcpu->kvm;
3111         bool update_guest_cr3 = true;
3112         unsigned long guest_cr3;
3113         u64 eptp;
3114
3115         if (enable_ept) {
3116                 eptp = construct_eptp(vcpu, root_hpa, root_level);
3117                 vmcs_write64(EPT_POINTER, eptp);
3118
3119                 hv_track_root_tdp(vcpu, root_hpa);
3120
3121                 if (!enable_unrestricted_guest && !is_paging(vcpu))
3122                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3123                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3124                         guest_cr3 = vcpu->arch.cr3;
3125                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3126                         update_guest_cr3 = false;
3127                 vmx_ept_load_pdptrs(vcpu);
3128         } else {
3129                 guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu);
3130         }
3131
3132         if (update_guest_cr3)
3133                 vmcs_writel(GUEST_CR3, guest_cr3);
3134 }
3135
3136 static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3137 {
3138         /*
3139          * We operate under the default treatment of SMM, so VMX cannot be
3140          * enabled under SMM.  Note, whether or not VMXE is allowed at all is
3141          * handled by kvm_is_valid_cr4().
3142          */
3143         if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu))
3144                 return false;
3145
3146         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3147                 return false;
3148
3149         return true;
3150 }
3151
3152 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3153 {
3154         unsigned long old_cr4 = vcpu->arch.cr4;
3155         struct vcpu_vmx *vmx = to_vmx(vcpu);
3156         /*
3157          * Pass through host's Machine Check Enable value to hw_cr4, which
3158          * is in force while we are in guest mode.  Do not let guests control
3159          * this bit, even if host CR4.MCE == 0.
3160          */
3161         unsigned long hw_cr4;
3162
3163         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3164         if (is_unrestricted_guest(vcpu))
3165                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3166         else if (vmx->rmode.vm86_active)
3167                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3168         else
3169                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3170
3171         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3172                 if (cr4 & X86_CR4_UMIP) {
3173                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3174                         hw_cr4 &= ~X86_CR4_UMIP;
3175                 } else if (!is_guest_mode(vcpu) ||
3176                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3177                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3178                 }
3179         }
3180
3181         vcpu->arch.cr4 = cr4;
3182         kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3183
3184         if (!is_unrestricted_guest(vcpu)) {
3185                 if (enable_ept) {
3186                         if (!is_paging(vcpu)) {
3187                                 hw_cr4 &= ~X86_CR4_PAE;
3188                                 hw_cr4 |= X86_CR4_PSE;
3189                         } else if (!(cr4 & X86_CR4_PAE)) {
3190                                 hw_cr4 &= ~X86_CR4_PAE;
3191                         }
3192                 }
3193
3194                 /*
3195                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3196                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3197                  * to be manually disabled when guest switches to non-paging
3198                  * mode.
3199                  *
3200                  * If !enable_unrestricted_guest, the CPU is always running
3201                  * with CR0.PG=1 and CR4 needs to be modified.
3202                  * If enable_unrestricted_guest, the CPU automatically
3203                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3204                  */
3205                 if (!is_paging(vcpu))
3206                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3207         }
3208
3209         vmcs_writel(CR4_READ_SHADOW, cr4);
3210         vmcs_writel(GUEST_CR4, hw_cr4);
3211
3212         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
3213                 kvm_update_cpuid_runtime(vcpu);
3214 }
3215
3216 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3217 {
3218         struct vcpu_vmx *vmx = to_vmx(vcpu);
3219         u32 ar;
3220
3221         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3222                 *var = vmx->rmode.segs[seg];
3223                 if (seg == VCPU_SREG_TR
3224                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3225                         return;
3226                 var->base = vmx_read_guest_seg_base(vmx, seg);
3227                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3228                 return;
3229         }
3230         var->base = vmx_read_guest_seg_base(vmx, seg);
3231         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3232         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3233         ar = vmx_read_guest_seg_ar(vmx, seg);
3234         var->unusable = (ar >> 16) & 1;
3235         var->type = ar & 15;
3236         var->s = (ar >> 4) & 1;
3237         var->dpl = (ar >> 5) & 3;
3238         /*
3239          * Some userspaces do not preserve unusable property. Since usable
3240          * segment has to be present according to VMX spec we can use present
3241          * property to amend userspace bug by making unusable segment always
3242          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3243          * segment as unusable.
3244          */
3245         var->present = !var->unusable;
3246         var->avl = (ar >> 12) & 1;
3247         var->l = (ar >> 13) & 1;
3248         var->db = (ar >> 14) & 1;
3249         var->g = (ar >> 15) & 1;
3250 }
3251
3252 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3253 {
3254         struct kvm_segment s;
3255
3256         if (to_vmx(vcpu)->rmode.vm86_active) {
3257                 vmx_get_segment(vcpu, &s, seg);
3258                 return s.base;
3259         }
3260         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3261 }
3262
3263 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3264 {
3265         struct vcpu_vmx *vmx = to_vmx(vcpu);
3266
3267         if (unlikely(vmx->rmode.vm86_active))
3268                 return 0;
3269         else {
3270                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3271                 return VMX_AR_DPL(ar);
3272         }
3273 }
3274
3275 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3276 {
3277         u32 ar;
3278
3279         if (var->unusable || !var->present)
3280                 ar = 1 << 16;
3281         else {
3282                 ar = var->type & 15;
3283                 ar |= (var->s & 1) << 4;
3284                 ar |= (var->dpl & 3) << 5;
3285                 ar |= (var->present & 1) << 7;
3286                 ar |= (var->avl & 1) << 12;
3287                 ar |= (var->l & 1) << 13;
3288                 ar |= (var->db & 1) << 14;
3289                 ar |= (var->g & 1) << 15;
3290         }
3291
3292         return ar;
3293 }
3294
3295 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3296 {
3297         struct vcpu_vmx *vmx = to_vmx(vcpu);
3298         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3299
3300         vmx_segment_cache_clear(vmx);
3301
3302         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3303                 vmx->rmode.segs[seg] = *var;
3304                 if (seg == VCPU_SREG_TR)
3305                         vmcs_write16(sf->selector, var->selector);
3306                 else if (var->s)
3307                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3308                 return;
3309         }
3310
3311         vmcs_writel(sf->base, var->base);
3312         vmcs_write32(sf->limit, var->limit);
3313         vmcs_write16(sf->selector, var->selector);
3314
3315         /*
3316          *   Fix the "Accessed" bit in AR field of segment registers for older
3317          * qemu binaries.
3318          *   IA32 arch specifies that at the time of processor reset the
3319          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3320          * is setting it to 0 in the userland code. This causes invalid guest
3321          * state vmexit when "unrestricted guest" mode is turned on.
3322          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3323          * tree. Newer qemu binaries with that qemu fix would not need this
3324          * kvm hack.
3325          */
3326         if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3327                 var->type |= 0x1; /* Accessed */
3328
3329         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3330 }
3331
3332 static void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3333 {
3334         __vmx_set_segment(vcpu, var, seg);
3335
3336         to_vmx(vcpu)->emulation_required = vmx_emulation_required(vcpu);
3337 }
3338
3339 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3340 {
3341         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3342
3343         *db = (ar >> 14) & 1;
3344         *l = (ar >> 13) & 1;
3345 }
3346
3347 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3348 {
3349         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3350         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3351 }
3352
3353 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3354 {
3355         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3356         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3357 }
3358
3359 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3360 {
3361         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3362         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3363 }
3364
3365 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3366 {
3367         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3368         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3369 }
3370
3371 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3372 {
3373         struct kvm_segment var;
3374         u32 ar;
3375
3376         vmx_get_segment(vcpu, &var, seg);
3377         var.dpl = 0x3;
3378         if (seg == VCPU_SREG_CS)
3379                 var.type = 0x3;
3380         ar = vmx_segment_access_rights(&var);
3381
3382         if (var.base != (var.selector << 4))
3383                 return false;
3384         if (var.limit != 0xffff)
3385                 return false;
3386         if (ar != 0xf3)
3387                 return false;
3388
3389         return true;
3390 }
3391
3392 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3393 {
3394         struct kvm_segment cs;
3395         unsigned int cs_rpl;
3396
3397         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3398         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3399
3400         if (cs.unusable)
3401                 return false;
3402         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3403                 return false;
3404         if (!cs.s)
3405                 return false;
3406         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3407                 if (cs.dpl > cs_rpl)
3408                         return false;
3409         } else {
3410                 if (cs.dpl != cs_rpl)
3411                         return false;
3412         }
3413         if (!cs.present)
3414                 return false;
3415
3416         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3417         return true;
3418 }
3419
3420 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3421 {
3422         struct kvm_segment ss;
3423         unsigned int ss_rpl;
3424
3425         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3426         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3427
3428         if (ss.unusable)
3429                 return true;
3430         if (ss.type != 3 && ss.type != 7)
3431                 return false;
3432         if (!ss.s)
3433                 return false;
3434         if (ss.dpl != ss_rpl) /* DPL != RPL */
3435                 return false;
3436         if (!ss.present)
3437                 return false;
3438
3439         return true;
3440 }
3441
3442 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3443 {
3444         struct kvm_segment var;
3445         unsigned int rpl;
3446
3447         vmx_get_segment(vcpu, &var, seg);
3448         rpl = var.selector & SEGMENT_RPL_MASK;
3449
3450         if (var.unusable)
3451                 return true;
3452         if (!var.s)
3453                 return false;
3454         if (!var.present)
3455                 return false;
3456         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3457                 if (var.dpl < rpl) /* DPL < RPL */
3458                         return false;
3459         }
3460
3461         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3462          * rights flags
3463          */
3464         return true;
3465 }
3466
3467 static bool tr_valid(struct kvm_vcpu *vcpu)
3468 {
3469         struct kvm_segment tr;
3470
3471         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3472
3473         if (tr.unusable)
3474                 return false;
3475         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3476                 return false;
3477         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3478                 return false;
3479         if (!tr.present)
3480                 return false;
3481
3482         return true;
3483 }
3484
3485 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3486 {
3487         struct kvm_segment ldtr;
3488
3489         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3490
3491         if (ldtr.unusable)
3492                 return true;
3493         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3494                 return false;
3495         if (ldtr.type != 2)
3496                 return false;
3497         if (!ldtr.present)
3498                 return false;
3499
3500         return true;
3501 }
3502
3503 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3504 {
3505         struct kvm_segment cs, ss;
3506
3507         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3508         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3509
3510         return ((cs.selector & SEGMENT_RPL_MASK) ==
3511                  (ss.selector & SEGMENT_RPL_MASK));
3512 }
3513
3514 /*
3515  * Check if guest state is valid. Returns true if valid, false if
3516  * not.
3517  * We assume that registers are always usable
3518  */
3519 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu)
3520 {
3521         /* real mode guest state checks */
3522         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3523                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3524                         return false;
3525                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3526                         return false;
3527                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3528                         return false;
3529                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3530                         return false;
3531                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3532                         return false;
3533                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3534                         return false;
3535         } else {
3536         /* protected mode guest state checks */
3537                 if (!cs_ss_rpl_check(vcpu))
3538                         return false;
3539                 if (!code_segment_valid(vcpu))
3540                         return false;
3541                 if (!stack_segment_valid(vcpu))
3542                         return false;
3543                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3544                         return false;
3545                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3546                         return false;
3547                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3548                         return false;
3549                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3550                         return false;
3551                 if (!tr_valid(vcpu))
3552                         return false;
3553                 if (!ldtr_valid(vcpu))
3554                         return false;
3555         }
3556         /* TODO:
3557          * - Add checks on RIP
3558          * - Add checks on RFLAGS
3559          */
3560
3561         return true;
3562 }
3563
3564 static int init_rmode_tss(struct kvm *kvm, void __user *ua)
3565 {
3566         const void *zero_page = (const void *) __va(page_to_phys(ZERO_PAGE(0)));
3567         u16 data;
3568         int i;
3569
3570         for (i = 0; i < 3; i++) {
3571                 if (__copy_to_user(ua + PAGE_SIZE * i, zero_page, PAGE_SIZE))
3572                         return -EFAULT;
3573         }
3574
3575         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3576         if (__copy_to_user(ua + TSS_IOPB_BASE_OFFSET, &data, sizeof(u16)))
3577                 return -EFAULT;
3578
3579         data = ~0;
3580         if (__copy_to_user(ua + RMODE_TSS_SIZE - 1, &data, sizeof(u8)))
3581                 return -EFAULT;
3582
3583         return 0;
3584 }
3585
3586 static int init_rmode_identity_map(struct kvm *kvm)
3587 {
3588         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3589         int i, r = 0;
3590         void __user *uaddr;
3591         u32 tmp;
3592
3593         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3594         mutex_lock(&kvm->slots_lock);
3595
3596         if (likely(kvm_vmx->ept_identity_pagetable_done))
3597                 goto out;
3598
3599         if (!kvm_vmx->ept_identity_map_addr)
3600                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3601
3602         uaddr = __x86_set_memory_region(kvm,
3603                                         IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3604                                         kvm_vmx->ept_identity_map_addr,
3605                                         PAGE_SIZE);
3606         if (IS_ERR(uaddr)) {
3607                 r = PTR_ERR(uaddr);
3608                 goto out;
3609         }
3610
3611         /* Set up identity-mapping pagetable for EPT in real mode */
3612         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3613                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3614                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3615                 if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) {
3616                         r = -EFAULT;
3617                         goto out;
3618                 }
3619         }
3620         kvm_vmx->ept_identity_pagetable_done = true;
3621
3622 out:
3623         mutex_unlock(&kvm->slots_lock);
3624         return r;
3625 }
3626
3627 static void seg_setup(int seg)
3628 {
3629         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3630         unsigned int ar;
3631
3632         vmcs_write16(sf->selector, 0);
3633         vmcs_writel(sf->base, 0);
3634         vmcs_write32(sf->limit, 0xffff);
3635         ar = 0x93;
3636         if (seg == VCPU_SREG_CS)
3637                 ar |= 0x08; /* code segment */
3638
3639         vmcs_write32(sf->ar_bytes, ar);
3640 }
3641
3642 static int alloc_apic_access_page(struct kvm *kvm)
3643 {
3644         struct page *page;
3645         void __user *hva;
3646         int ret = 0;
3647
3648         mutex_lock(&kvm->slots_lock);
3649         if (kvm->arch.apic_access_memslot_enabled)
3650                 goto out;
3651         hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3652                                       APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3653         if (IS_ERR(hva)) {
3654                 ret = PTR_ERR(hva);
3655                 goto out;
3656         }
3657
3658         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3659         if (is_error_page(page)) {
3660                 ret = -EFAULT;
3661                 goto out;
3662         }
3663
3664         /*
3665          * Do not pin the page in memory, so that memory hot-unplug
3666          * is able to migrate it.
3667          */
3668         put_page(page);
3669         kvm->arch.apic_access_memslot_enabled = true;
3670 out:
3671         mutex_unlock(&kvm->slots_lock);
3672         return ret;
3673 }
3674
3675 int allocate_vpid(void)
3676 {
3677         int vpid;
3678
3679         if (!enable_vpid)
3680                 return 0;
3681         spin_lock(&vmx_vpid_lock);
3682         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3683         if (vpid < VMX_NR_VPIDS)
3684                 __set_bit(vpid, vmx_vpid_bitmap);
3685         else
3686                 vpid = 0;
3687         spin_unlock(&vmx_vpid_lock);
3688         return vpid;
3689 }
3690
3691 void free_vpid(int vpid)
3692 {
3693         if (!enable_vpid || vpid == 0)
3694                 return;
3695         spin_lock(&vmx_vpid_lock);
3696         __clear_bit(vpid, vmx_vpid_bitmap);
3697         spin_unlock(&vmx_vpid_lock);
3698 }
3699
3700 static void vmx_clear_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3701 {
3702         int f = sizeof(unsigned long);
3703
3704         if (msr <= 0x1fff)
3705                 __clear_bit(msr, msr_bitmap + 0x000 / f);
3706         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3707                 __clear_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3708 }
3709
3710 static void vmx_clear_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3711 {
3712         int f = sizeof(unsigned long);
3713
3714         if (msr <= 0x1fff)
3715                 __clear_bit(msr, msr_bitmap + 0x800 / f);
3716         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3717                 __clear_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3718 }
3719
3720 static void vmx_set_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3721 {
3722         int f = sizeof(unsigned long);
3723
3724         if (msr <= 0x1fff)
3725                 __set_bit(msr, msr_bitmap + 0x000 / f);
3726         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3727                 __set_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3728 }
3729
3730 static void vmx_set_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3731 {
3732         int f = sizeof(unsigned long);
3733
3734         if (msr <= 0x1fff)
3735                 __set_bit(msr, msr_bitmap + 0x800 / f);
3736         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3737                 __set_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3738 }
3739
3740 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3741 {
3742         struct vcpu_vmx *vmx = to_vmx(vcpu);
3743         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3744
3745         if (!cpu_has_vmx_msr_bitmap())
3746                 return;
3747
3748         if (static_branch_unlikely(&enable_evmcs))
3749                 evmcs_touch_msr_bitmap();
3750
3751         /*
3752          * Mark the desired intercept state in shadow bitmap, this is needed
3753          * for resync when the MSR filters change.
3754         */
3755         if (is_valid_passthrough_msr(msr)) {
3756                 int idx = possible_passthrough_msr_slot(msr);
3757
3758                 if (idx != -ENOENT) {
3759                         if (type & MSR_TYPE_R)
3760                                 clear_bit(idx, vmx->shadow_msr_intercept.read);
3761                         if (type & MSR_TYPE_W)
3762                                 clear_bit(idx, vmx->shadow_msr_intercept.write);
3763                 }
3764         }
3765
3766         if ((type & MSR_TYPE_R) &&
3767             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) {
3768                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3769                 type &= ~MSR_TYPE_R;
3770         }
3771
3772         if ((type & MSR_TYPE_W) &&
3773             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) {
3774                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3775                 type &= ~MSR_TYPE_W;
3776         }
3777
3778         if (type & MSR_TYPE_R)
3779                 vmx_clear_msr_bitmap_read(msr_bitmap, msr);
3780
3781         if (type & MSR_TYPE_W)
3782                 vmx_clear_msr_bitmap_write(msr_bitmap, msr);
3783 }
3784
3785 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3786 {
3787         struct vcpu_vmx *vmx = to_vmx(vcpu);
3788         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3789
3790         if (!cpu_has_vmx_msr_bitmap())
3791                 return;
3792
3793         if (static_branch_unlikely(&enable_evmcs))
3794                 evmcs_touch_msr_bitmap();
3795
3796         /*
3797          * Mark the desired intercept state in shadow bitmap, this is needed
3798          * for resync when the MSR filter changes.
3799         */
3800         if (is_valid_passthrough_msr(msr)) {
3801                 int idx = possible_passthrough_msr_slot(msr);
3802
3803                 if (idx != -ENOENT) {
3804                         if (type & MSR_TYPE_R)
3805                                 set_bit(idx, vmx->shadow_msr_intercept.read);
3806                         if (type & MSR_TYPE_W)
3807                                 set_bit(idx, vmx->shadow_msr_intercept.write);
3808                 }
3809         }
3810
3811         if (type & MSR_TYPE_R)
3812                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3813
3814         if (type & MSR_TYPE_W)
3815                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3816 }
3817
3818 static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode)
3819 {
3820         unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
3821         unsigned long read_intercept;
3822         int msr;
3823
3824         read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3825
3826         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3827                 unsigned int read_idx = msr / BITS_PER_LONG;
3828                 unsigned int write_idx = read_idx + (0x800 / sizeof(long));
3829
3830                 msr_bitmap[read_idx] = read_intercept;
3831                 msr_bitmap[write_idx] = ~0ul;
3832         }
3833 }
3834
3835 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
3836 {
3837         struct vcpu_vmx *vmx = to_vmx(vcpu);
3838         u8 mode;
3839
3840         if (!cpu_has_vmx_msr_bitmap())
3841                 return;
3842
3843         if (cpu_has_secondary_exec_ctrls() &&
3844             (secondary_exec_controls_get(vmx) &
3845              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3846                 mode = MSR_BITMAP_MODE_X2APIC;
3847                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3848                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3849         } else {
3850                 mode = 0;
3851         }
3852
3853         if (mode == vmx->x2apic_msr_bitmap_mode)
3854                 return;
3855
3856         vmx->x2apic_msr_bitmap_mode = mode;
3857
3858         vmx_reset_x2apic_msrs(vcpu, mode);
3859
3860         /*
3861          * TPR reads and writes can be virtualized even if virtual interrupt
3862          * delivery is not in use.
3863          */
3864         vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
3865                                   !(mode & MSR_BITMAP_MODE_X2APIC));
3866
3867         if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3868                 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
3869                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3870                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3871         }
3872 }
3873
3874 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu)
3875 {
3876         struct vcpu_vmx *vmx = to_vmx(vcpu);
3877         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3878         u32 i;
3879
3880         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
3881         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
3882         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
3883         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
3884         for (i = 0; i < vmx->pt_desc.num_address_ranges; i++) {
3885                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3886                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3887         }
3888 }
3889
3890 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3891 {
3892         struct vcpu_vmx *vmx = to_vmx(vcpu);
3893         void *vapic_page;
3894         u32 vppr;
3895         int rvi;
3896
3897         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3898                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3899                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3900                 return false;
3901
3902         rvi = vmx_get_rvi();
3903
3904         vapic_page = vmx->nested.virtual_apic_map.hva;
3905         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3906
3907         return ((rvi & 0xf0) > (vppr & 0xf0));
3908 }
3909
3910 static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
3911 {
3912         struct vcpu_vmx *vmx = to_vmx(vcpu);
3913         u32 i;
3914
3915         /*
3916          * Set intercept permissions for all potentially passed through MSRs
3917          * again. They will automatically get filtered through the MSR filter,
3918          * so we are back in sync after this.
3919          */
3920         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
3921                 u32 msr = vmx_possible_passthrough_msrs[i];
3922                 bool read = test_bit(i, vmx->shadow_msr_intercept.read);
3923                 bool write = test_bit(i, vmx->shadow_msr_intercept.write);
3924
3925                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
3926                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
3927         }
3928
3929         pt_update_intercept_for_msr(vcpu);
3930 }
3931
3932 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3933                                                      bool nested)
3934 {
3935 #ifdef CONFIG_SMP
3936         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3937
3938         if (vcpu->mode == IN_GUEST_MODE) {
3939                 /*
3940                  * The vector of interrupt to be delivered to vcpu had
3941                  * been set in PIR before this function.
3942                  *
3943                  * Following cases will be reached in this block, and
3944                  * we always send a notification event in all cases as
3945                  * explained below.
3946                  *
3947                  * Case 1: vcpu keeps in non-root mode. Sending a
3948                  * notification event posts the interrupt to vcpu.
3949                  *
3950                  * Case 2: vcpu exits to root mode and is still
3951                  * runnable. PIR will be synced to vIRR before the
3952                  * next vcpu entry. Sending a notification event in
3953                  * this case has no effect, as vcpu is not in root
3954                  * mode.
3955                  *
3956                  * Case 3: vcpu exits to root mode and is blocked.
3957                  * vcpu_block() has already synced PIR to vIRR and
3958                  * never blocks vcpu if vIRR is not cleared. Therefore,
3959                  * a blocked vcpu here does not wait for any requested
3960                  * interrupts in PIR, and sending a notification event
3961                  * which has no effect is safe here.
3962                  */
3963
3964                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3965                 return true;
3966         }
3967 #endif
3968         return false;
3969 }
3970
3971 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3972                                                 int vector)
3973 {
3974         struct vcpu_vmx *vmx = to_vmx(vcpu);
3975
3976         if (is_guest_mode(vcpu) &&
3977             vector == vmx->nested.posted_intr_nv) {
3978                 /*
3979                  * If a posted intr is not recognized by hardware,
3980                  * we will accomplish it in the next vmentry.
3981                  */
3982                 vmx->nested.pi_pending = true;
3983                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3984                 /* the PIR and ON have been set by L1. */
3985                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3986                         kvm_vcpu_kick(vcpu);
3987                 return 0;
3988         }
3989         return -1;
3990 }
3991 /*
3992  * Send interrupt to vcpu via posted interrupt way.
3993  * 1. If target vcpu is running(non-root mode), send posted interrupt
3994  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3995  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3996  * interrupt from PIR in next vmentry.
3997  */
3998 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3999 {
4000         struct vcpu_vmx *vmx = to_vmx(vcpu);
4001         int r;
4002
4003         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4004         if (!r)
4005                 return 0;
4006
4007         if (!vcpu->arch.apicv_active)
4008                 return -1;
4009
4010         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4011                 return 0;
4012
4013         /* If a previous notification has sent the IPI, nothing to do.  */
4014         if (pi_test_and_set_on(&vmx->pi_desc))
4015                 return 0;
4016
4017         if (vcpu != kvm_get_running_vcpu() &&
4018             !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
4019                 kvm_vcpu_kick(vcpu);
4020
4021         return 0;
4022 }
4023
4024 /*
4025  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4026  * will not change in the lifetime of the guest.
4027  * Note that host-state that does change is set elsewhere. E.g., host-state
4028  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4029  */
4030 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4031 {
4032         u32 low32, high32;
4033         unsigned long tmpl;
4034         unsigned long cr0, cr3, cr4;
4035
4036         cr0 = read_cr0();
4037         WARN_ON(cr0 & X86_CR0_TS);
4038         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
4039
4040         /*
4041          * Save the most likely value for this task's CR3 in the VMCS.
4042          * We can't use __get_current_cr3_fast() because we're not atomic.
4043          */
4044         cr3 = __read_cr3();
4045         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
4046         vmx->loaded_vmcs->host_state.cr3 = cr3;
4047
4048         /* Save the most likely value for this task's CR4 in the VMCS. */
4049         cr4 = cr4_read_shadow();
4050         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4051         vmx->loaded_vmcs->host_state.cr4 = cr4;
4052
4053         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4054 #ifdef CONFIG_X86_64
4055         /*
4056          * Load null selectors, so we can avoid reloading them in
4057          * vmx_prepare_switch_to_host(), in case userspace uses
4058          * the null selectors too (the expected case).
4059          */
4060         vmcs_write16(HOST_DS_SELECTOR, 0);
4061         vmcs_write16(HOST_ES_SELECTOR, 0);
4062 #else
4063         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4064         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4065 #endif
4066         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4067         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4068
4069         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
4070
4071         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4072
4073         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4074         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4075         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4076         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4077
4078         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4079                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4080                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4081         }
4082
4083         if (cpu_has_load_ia32_efer())
4084                 vmcs_write64(HOST_IA32_EFER, host_efer);
4085 }
4086
4087 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4088 {
4089         struct kvm_vcpu *vcpu = &vmx->vcpu;
4090
4091         vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
4092                                           ~vcpu->arch.cr4_guest_rsvd_bits;
4093         if (!enable_ept)
4094                 vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4095         if (is_guest_mode(&vmx->vcpu))
4096                 vcpu->arch.cr4_guest_owned_bits &=
4097                         ~get_vmcs12(vcpu)->cr4_guest_host_mask;
4098         vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits);
4099 }
4100
4101 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4102 {
4103         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4104
4105         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4106                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4107
4108         if (!enable_vnmi)
4109                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4110
4111         if (!enable_preemption_timer)
4112                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4113
4114         return pin_based_exec_ctrl;
4115 }
4116
4117 static u32 vmx_vmentry_ctrl(void)
4118 {
4119         u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
4120
4121         if (vmx_pt_mode_is_system())
4122                 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
4123                                   VM_ENTRY_LOAD_IA32_RTIT_CTL);
4124         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4125         return vmentry_ctrl &
4126                 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
4127 }
4128
4129 static u32 vmx_vmexit_ctrl(void)
4130 {
4131         u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
4132
4133         if (vmx_pt_mode_is_system())
4134                 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
4135                                  VM_EXIT_CLEAR_IA32_RTIT_CTL);
4136         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4137         return vmexit_ctrl &
4138                 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
4139 }
4140
4141 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4142 {
4143         struct vcpu_vmx *vmx = to_vmx(vcpu);
4144
4145         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4146         if (cpu_has_secondary_exec_ctrls()) {
4147                 if (kvm_vcpu_apicv_active(vcpu))
4148                         secondary_exec_controls_setbit(vmx,
4149                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4150                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4151                 else
4152                         secondary_exec_controls_clearbit(vmx,
4153                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4154                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4155         }
4156
4157         vmx_update_msr_bitmap_x2apic(vcpu);
4158 }
4159
4160 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4161 {
4162         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4163
4164         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4165                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4166
4167         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4168                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4169 #ifdef CONFIG_X86_64
4170                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4171                                 CPU_BASED_CR8_LOAD_EXITING;
4172 #endif
4173         }
4174         if (!enable_ept)
4175                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4176                                 CPU_BASED_CR3_LOAD_EXITING  |
4177                                 CPU_BASED_INVLPG_EXITING;
4178         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4179                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4180                                 CPU_BASED_MONITOR_EXITING);
4181         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4182                 exec_control &= ~CPU_BASED_HLT_EXITING;
4183         return exec_control;
4184 }
4185
4186 /*
4187  * Adjust a single secondary execution control bit to intercept/allow an
4188  * instruction in the guest.  This is usually done based on whether or not a
4189  * feature has been exposed to the guest in order to correctly emulate faults.
4190  */
4191 static inline void
4192 vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control,
4193                                   u32 control, bool enabled, bool exiting)
4194 {
4195         /*
4196          * If the control is for an opt-in feature, clear the control if the
4197          * feature is not exposed to the guest, i.e. not enabled.  If the
4198          * control is opt-out, i.e. an exiting control, clear the control if
4199          * the feature _is_ exposed to the guest, i.e. exiting/interception is
4200          * disabled for the associated instruction.  Note, the caller is
4201          * responsible presetting exec_control to set all supported bits.
4202          */
4203         if (enabled == exiting)
4204                 *exec_control &= ~control;
4205
4206         /*
4207          * Update the nested MSR settings so that a nested VMM can/can't set
4208          * controls for features that are/aren't exposed to the guest.
4209          */
4210         if (nested) {
4211                 if (enabled)
4212                         vmx->nested.msrs.secondary_ctls_high |= control;
4213                 else
4214                         vmx->nested.msrs.secondary_ctls_high &= ~control;
4215         }
4216 }
4217
4218 /*
4219  * Wrapper macro for the common case of adjusting a secondary execution control
4220  * based on a single guest CPUID bit, with a dedicated feature bit.  This also
4221  * verifies that the control is actually supported by KVM and hardware.
4222  */
4223 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \
4224 ({                                                                       \
4225         bool __enabled;                                                  \
4226                                                                          \
4227         if (cpu_has_vmx_##name()) {                                      \
4228                 __enabled = guest_cpuid_has(&(vmx)->vcpu,                \
4229                                             X86_FEATURE_##feat_name);    \
4230                 vmx_adjust_secondary_exec_control(vmx, exec_control,     \
4231                         SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \
4232         }                                                                \
4233 })
4234
4235 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */
4236 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \
4237         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false)
4238
4239 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \
4240         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true)
4241
4242 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4243 {
4244         struct kvm_vcpu *vcpu = &vmx->vcpu;
4245
4246         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4247
4248         if (vmx_pt_mode_is_system())
4249                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4250         if (!cpu_need_virtualize_apic_accesses(vcpu))
4251                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4252         if (vmx->vpid == 0)
4253                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4254         if (!enable_ept) {
4255                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4256                 enable_unrestricted_guest = 0;
4257         }
4258         if (!enable_unrestricted_guest)
4259                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4260         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4261                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4262         if (!kvm_vcpu_apicv_active(vcpu))
4263                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4264                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4265         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4266
4267         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4268          * in vmx_set_cr4.  */
4269         exec_control &= ~SECONDARY_EXEC_DESC;
4270
4271         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4272            (handle_vmptrld).
4273            We can NOT enable shadow_vmcs here because we don't have yet
4274            a current VMCS12
4275         */
4276         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4277
4278         /*
4279          * PML is enabled/disabled when dirty logging of memsmlots changes, but
4280          * it needs to be set here when dirty logging is already active, e.g.
4281          * if this vCPU was created after dirty logging was enabled.
4282          */
4283         if (!vcpu->kvm->arch.cpu_dirty_logging_count)
4284                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4285
4286         if (cpu_has_vmx_xsaves()) {
4287                 /* Exposing XSAVES only when XSAVE is exposed */
4288                 bool xsaves_enabled =
4289                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4290                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4291                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4292
4293                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4294
4295                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4296                                                   SECONDARY_EXEC_XSAVES,
4297                                                   xsaves_enabled, false);
4298         }
4299
4300         /*
4301          * RDPID is also gated by ENABLE_RDTSCP, turn on the control if either
4302          * feature is exposed to the guest.  This creates a virtualization hole
4303          * if both are supported in hardware but only one is exposed to the
4304          * guest, but letting the guest execute RDTSCP or RDPID when either one
4305          * is advertised is preferable to emulating the advertised instruction
4306          * in KVM on #UD, and obviously better than incorrectly injecting #UD.
4307          */
4308         if (cpu_has_vmx_rdtscp()) {
4309                 bool rdpid_or_rdtscp_enabled =
4310                         guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) ||
4311                         guest_cpuid_has(vcpu, X86_FEATURE_RDPID);
4312
4313                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4314                                                   SECONDARY_EXEC_ENABLE_RDTSCP,
4315                                                   rdpid_or_rdtscp_enabled, false);
4316         }
4317         vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID);
4318
4319         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND);
4320         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED);
4321
4322         vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG,
4323                                     ENABLE_USR_WAIT_PAUSE, false);
4324
4325         if (!vcpu->kvm->arch.bus_lock_detection_enabled)
4326                 exec_control &= ~SECONDARY_EXEC_BUS_LOCK_DETECTION;
4327
4328         return exec_control;
4329 }
4330
4331 #define VMX_XSS_EXIT_BITMAP 0
4332
4333 static void init_vmcs(struct vcpu_vmx *vmx)
4334 {
4335         if (nested)
4336                 nested_vmx_set_vmcs_shadowing_bitmap();
4337
4338         if (cpu_has_vmx_msr_bitmap())
4339                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4340
4341         vmcs_write64(VMCS_LINK_POINTER, INVALID_GPA); /* 22.3.1.5 */
4342
4343         /* Control */
4344         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4345
4346         exec_controls_set(vmx, vmx_exec_control(vmx));
4347
4348         if (cpu_has_secondary_exec_ctrls())
4349                 secondary_exec_controls_set(vmx, vmx_secondary_exec_control(vmx));
4350
4351         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4352                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4353                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4354                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4355                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4356
4357                 vmcs_write16(GUEST_INTR_STATUS, 0);
4358
4359                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4360                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4361         }
4362
4363         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4364                 vmcs_write32(PLE_GAP, ple_gap);
4365                 vmx->ple_window = ple_window;
4366                 vmx->ple_window_dirty = true;
4367         }
4368
4369         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4370         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4371         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4372
4373         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4374         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4375         vmx_set_constant_host_state(vmx);
4376         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4377         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4378
4379         if (cpu_has_vmx_vmfunc())
4380                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4381
4382         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4383         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4384         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4385         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4386         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4387
4388         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4389                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4390
4391         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4392
4393         /* 22.2.1, 20.8.1 */
4394         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4395
4396         vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4397         vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4398
4399         set_cr4_guest_host_mask(vmx);
4400
4401         if (vmx->vpid != 0)
4402                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4403
4404         if (cpu_has_vmx_xsaves())
4405                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4406
4407         if (enable_pml) {
4408                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4409                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4410         }
4411
4412         vmx_write_encls_bitmap(&vmx->vcpu, NULL);
4413
4414         if (vmx_pt_mode_is_host_guest()) {
4415                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4416                 /* Bit[6~0] are forced to 1, writes are ignored. */
4417                 vmx->pt_desc.guest.output_mask = 0x7F;
4418                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4419         }
4420
4421         vmcs_write32(GUEST_SYSENTER_CS, 0);
4422         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4423         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4424         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4425
4426         if (cpu_has_vmx_tpr_shadow()) {
4427                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4428                 if (cpu_need_tpr_shadow(&vmx->vcpu))
4429                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4430                                      __pa(vmx->vcpu.arch.apic->regs));
4431                 vmcs_write32(TPR_THRESHOLD, 0);
4432         }
4433
4434         vmx_setup_uret_msrs(vmx);
4435 }
4436
4437 static void __vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4438 {
4439         struct vcpu_vmx *vmx = to_vmx(vcpu);
4440
4441         init_vmcs(vmx);
4442
4443         if (nested)
4444                 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
4445
4446         vcpu_setup_sgx_lepubkeyhash(vcpu);
4447
4448         vmx->nested.posted_intr_nv = -1;
4449         vmx->nested.vmxon_ptr = INVALID_GPA;
4450         vmx->nested.current_vmptr = INVALID_GPA;
4451         vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
4452
4453         vcpu->arch.microcode_version = 0x100000000ULL;
4454         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
4455
4456         /*
4457          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
4458          * or POSTED_INTR_WAKEUP_VECTOR.
4459          */
4460         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
4461         vmx->pi_desc.sn = 1;
4462 }
4463
4464 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4465 {
4466         struct vcpu_vmx *vmx = to_vmx(vcpu);
4467
4468         if (!init_event)
4469                 __vmx_vcpu_reset(vcpu);
4470
4471         vmx->rmode.vm86_active = 0;
4472         vmx->spec_ctrl = 0;
4473
4474         vmx->msr_ia32_umwait_control = 0;
4475
4476         vmx->hv_deadline_tsc = -1;
4477         kvm_set_cr8(vcpu, 0);
4478
4479         vmx_segment_cache_clear(vmx);
4480         kvm_register_mark_available(vcpu, VCPU_EXREG_SEGMENTS);
4481
4482         seg_setup(VCPU_SREG_CS);
4483         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4484         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4485
4486         seg_setup(VCPU_SREG_DS);
4487         seg_setup(VCPU_SREG_ES);
4488         seg_setup(VCPU_SREG_FS);
4489         seg_setup(VCPU_SREG_GS);
4490         seg_setup(VCPU_SREG_SS);
4491
4492         vmcs_write16(GUEST_TR_SELECTOR, 0);
4493         vmcs_writel(GUEST_TR_BASE, 0);
4494         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4495         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4496
4497         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4498         vmcs_writel(GUEST_LDTR_BASE, 0);
4499         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4500         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4501
4502         vmcs_writel(GUEST_GDTR_BASE, 0);
4503         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4504
4505         vmcs_writel(GUEST_IDTR_BASE, 0);
4506         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4507
4508         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4509         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4510         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4511         if (kvm_mpx_supported())
4512                 vmcs_write64(GUEST_BNDCFGS, 0);
4513
4514         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4515
4516         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4517
4518         vpid_sync_context(vmx->vpid);
4519 }
4520
4521 static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
4522 {
4523         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4524 }
4525
4526 static void vmx_enable_nmi_window(struct kvm_vcpu *vcpu)
4527 {
4528         if (!enable_vnmi ||
4529             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4530                 vmx_enable_irq_window(vcpu);
4531                 return;
4532         }
4533
4534         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4535 }
4536
4537 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4538 {
4539         struct vcpu_vmx *vmx = to_vmx(vcpu);
4540         uint32_t intr;
4541         int irq = vcpu->arch.interrupt.nr;
4542
4543         trace_kvm_inj_virq(irq);
4544
4545         ++vcpu->stat.irq_injections;
4546         if (vmx->rmode.vm86_active) {
4547                 int inc_eip = 0;
4548                 if (vcpu->arch.interrupt.soft)
4549                         inc_eip = vcpu->arch.event_exit_inst_len;
4550                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4551                 return;
4552         }
4553         intr = irq | INTR_INFO_VALID_MASK;
4554         if (vcpu->arch.interrupt.soft) {
4555                 intr |= INTR_TYPE_SOFT_INTR;
4556                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4557                              vmx->vcpu.arch.event_exit_inst_len);
4558         } else
4559                 intr |= INTR_TYPE_EXT_INTR;
4560         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4561
4562         vmx_clear_hlt(vcpu);
4563 }
4564
4565 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4566 {
4567         struct vcpu_vmx *vmx = to_vmx(vcpu);
4568
4569         if (!enable_vnmi) {
4570                 /*
4571                  * Tracking the NMI-blocked state in software is built upon
4572                  * finding the next open IRQ window. This, in turn, depends on
4573                  * well-behaving guests: They have to keep IRQs disabled at
4574                  * least as long as the NMI handler runs. Otherwise we may
4575                  * cause NMI nesting, maybe breaking the guest. But as this is
4576                  * highly unlikely, we can live with the residual risk.
4577                  */
4578                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4579                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4580         }
4581
4582         ++vcpu->stat.nmi_injections;
4583         vmx->loaded_vmcs->nmi_known_unmasked = false;
4584
4585         if (vmx->rmode.vm86_active) {
4586                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4587                 return;
4588         }
4589
4590         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4591                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4592
4593         vmx_clear_hlt(vcpu);
4594 }
4595
4596 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4597 {
4598         struct vcpu_vmx *vmx = to_vmx(vcpu);
4599         bool masked;
4600
4601         if (!enable_vnmi)
4602                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4603         if (vmx->loaded_vmcs->nmi_known_unmasked)
4604                 return false;
4605         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4606         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4607         return masked;
4608 }
4609
4610 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4611 {
4612         struct vcpu_vmx *vmx = to_vmx(vcpu);
4613
4614         if (!enable_vnmi) {
4615                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4616                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4617                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4618                 }
4619         } else {
4620                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4621                 if (masked)
4622                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4623                                       GUEST_INTR_STATE_NMI);
4624                 else
4625                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4626                                         GUEST_INTR_STATE_NMI);
4627         }
4628 }
4629
4630 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4631 {
4632         if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4633                 return false;
4634
4635         if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4636                 return true;
4637
4638         return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4639                 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4640                  GUEST_INTR_STATE_NMI));
4641 }
4642
4643 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4644 {
4645         if (to_vmx(vcpu)->nested.nested_run_pending)
4646                 return -EBUSY;
4647
4648         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
4649         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4650                 return -EBUSY;
4651
4652         return !vmx_nmi_blocked(vcpu);
4653 }
4654
4655 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4656 {
4657         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4658                 return false;
4659
4660         return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4661                (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4662                 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4663 }
4664
4665 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4666 {
4667         if (to_vmx(vcpu)->nested.nested_run_pending)
4668                 return -EBUSY;
4669
4670        /*
4671         * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4672         * e.g. if the IRQ arrived asynchronously after checking nested events.
4673         */
4674         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4675                 return -EBUSY;
4676
4677         return !vmx_interrupt_blocked(vcpu);
4678 }
4679
4680 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4681 {
4682         void __user *ret;
4683
4684         if (enable_unrestricted_guest)
4685                 return 0;
4686
4687         mutex_lock(&kvm->slots_lock);
4688         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4689                                       PAGE_SIZE * 3);
4690         mutex_unlock(&kvm->slots_lock);
4691
4692         if (IS_ERR(ret))
4693                 return PTR_ERR(ret);
4694
4695         to_kvm_vmx(kvm)->tss_addr = addr;
4696
4697         return init_rmode_tss(kvm, ret);
4698 }
4699
4700 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4701 {
4702         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4703         return 0;
4704 }
4705
4706 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4707 {
4708         switch (vec) {
4709         case BP_VECTOR:
4710                 /*
4711                  * Update instruction length as we may reinject the exception
4712                  * from user space while in guest debugging mode.
4713                  */
4714                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4715                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4716                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4717                         return false;
4718                 fallthrough;
4719         case DB_VECTOR:
4720                 return !(vcpu->guest_debug &
4721                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4722         case DE_VECTOR:
4723         case OF_VECTOR:
4724         case BR_VECTOR:
4725         case UD_VECTOR:
4726         case DF_VECTOR:
4727         case SS_VECTOR:
4728         case GP_VECTOR:
4729         case MF_VECTOR:
4730                 return true;
4731         }
4732         return false;
4733 }
4734
4735 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4736                                   int vec, u32 err_code)
4737 {
4738         /*
4739          * Instruction with address size override prefix opcode 0x67
4740          * Cause the #SS fault with 0 error code in VM86 mode.
4741          */
4742         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4743                 if (kvm_emulate_instruction(vcpu, 0)) {
4744                         if (vcpu->arch.halt_request) {
4745                                 vcpu->arch.halt_request = 0;
4746                                 return kvm_vcpu_halt(vcpu);
4747                         }
4748                         return 1;
4749                 }
4750                 return 0;
4751         }
4752
4753         /*
4754          * Forward all other exceptions that are valid in real mode.
4755          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4756          *        the required debugging infrastructure rework.
4757          */
4758         kvm_queue_exception(vcpu, vec);
4759         return 1;
4760 }
4761
4762 static int handle_machine_check(struct kvm_vcpu *vcpu)
4763 {
4764         /* handled by vmx_vcpu_run() */
4765         return 1;
4766 }
4767
4768 /*
4769  * If the host has split lock detection disabled, then #AC is
4770  * unconditionally injected into the guest, which is the pre split lock
4771  * detection behaviour.
4772  *
4773  * If the host has split lock detection enabled then #AC is
4774  * only injected into the guest when:
4775  *  - Guest CPL == 3 (user mode)
4776  *  - Guest has #AC detection enabled in CR0
4777  *  - Guest EFLAGS has AC bit set
4778  */
4779 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu)
4780 {
4781         if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4782                 return true;
4783
4784         return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4785                (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4786 }
4787
4788 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4789 {
4790         struct vcpu_vmx *vmx = to_vmx(vcpu);
4791         struct kvm_run *kvm_run = vcpu->run;
4792         u32 intr_info, ex_no, error_code;
4793         unsigned long cr2, dr6;
4794         u32 vect_info;
4795
4796         vect_info = vmx->idt_vectoring_info;
4797         intr_info = vmx_get_intr_info(vcpu);
4798
4799         if (is_machine_check(intr_info) || is_nmi(intr_info))
4800                 return 1; /* handled by handle_exception_nmi_irqoff() */
4801
4802         if (is_invalid_opcode(intr_info))
4803                 return handle_ud(vcpu);
4804
4805         error_code = 0;
4806         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4807                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4808
4809         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4810                 WARN_ON_ONCE(!enable_vmware_backdoor);
4811
4812                 /*
4813                  * VMware backdoor emulation on #GP interception only handles
4814                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4815                  * error code on #GP.
4816                  */
4817                 if (error_code) {
4818                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4819                         return 1;
4820                 }
4821                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4822         }
4823
4824         /*
4825          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4826          * MMIO, it is better to report an internal error.
4827          * See the comments in vmx_handle_exit.
4828          */
4829         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4830             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4831                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4832                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4833                 vcpu->run->internal.ndata = 4;
4834                 vcpu->run->internal.data[0] = vect_info;
4835                 vcpu->run->internal.data[1] = intr_info;
4836                 vcpu->run->internal.data[2] = error_code;
4837                 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4838                 return 0;
4839         }
4840
4841         if (is_page_fault(intr_info)) {
4842                 cr2 = vmx_get_exit_qual(vcpu);
4843                 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4844                         /*
4845                          * EPT will cause page fault only if we need to
4846                          * detect illegal GPAs.
4847                          */
4848                         WARN_ON_ONCE(!allow_smaller_maxphyaddr);
4849                         kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4850                         return 1;
4851                 } else
4852                         return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4853         }
4854
4855         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4856
4857         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4858                 return handle_rmode_exception(vcpu, ex_no, error_code);
4859
4860         switch (ex_no) {
4861         case DB_VECTOR:
4862                 dr6 = vmx_get_exit_qual(vcpu);
4863                 if (!(vcpu->guest_debug &
4864                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4865                         if (is_icebp(intr_info))
4866                                 WARN_ON(!skip_emulated_instruction(vcpu));
4867
4868                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4869                         return 1;
4870                 }
4871                 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
4872                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4873                 fallthrough;
4874         case BP_VECTOR:
4875                 /*
4876                  * Update instruction length as we may reinject #BP from
4877                  * user space while in guest debugging mode. Reading it for
4878                  * #DB as well causes no harm, it is not used in that case.
4879                  */
4880                 vmx->vcpu.arch.event_exit_inst_len =
4881                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4882                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4883                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4884                 kvm_run->debug.arch.exception = ex_no;
4885                 break;
4886         case AC_VECTOR:
4887                 if (vmx_guest_inject_ac(vcpu)) {
4888                         kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4889                         return 1;
4890                 }
4891
4892                 /*
4893                  * Handle split lock. Depending on detection mode this will
4894                  * either warn and disable split lock detection for this
4895                  * task or force SIGBUS on it.
4896                  */
4897                 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4898                         return 1;
4899                 fallthrough;
4900         default:
4901                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4902                 kvm_run->ex.exception = ex_no;
4903                 kvm_run->ex.error_code = error_code;
4904                 break;
4905         }
4906         return 0;
4907 }
4908
4909 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4910 {
4911         ++vcpu->stat.irq_exits;
4912         return 1;
4913 }
4914
4915 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4916 {
4917         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4918         vcpu->mmio_needed = 0;
4919         return 0;
4920 }
4921
4922 static int handle_io(struct kvm_vcpu *vcpu)
4923 {
4924         unsigned long exit_qualification;
4925         int size, in, string;
4926         unsigned port;
4927
4928         exit_qualification = vmx_get_exit_qual(vcpu);
4929         string = (exit_qualification & 16) != 0;
4930
4931         ++vcpu->stat.io_exits;
4932
4933         if (string)
4934                 return kvm_emulate_instruction(vcpu, 0);
4935
4936         port = exit_qualification >> 16;
4937         size = (exit_qualification & 7) + 1;
4938         in = (exit_qualification & 8) != 0;
4939
4940         return kvm_fast_pio(vcpu, size, port, in);
4941 }
4942
4943 static void
4944 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4945 {
4946         /*
4947          * Patch in the VMCALL instruction:
4948          */
4949         hypercall[0] = 0x0f;
4950         hypercall[1] = 0x01;
4951         hypercall[2] = 0xc1;
4952 }
4953
4954 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4955 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4956 {
4957         if (is_guest_mode(vcpu)) {
4958                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4959                 unsigned long orig_val = val;
4960
4961                 /*
4962                  * We get here when L2 changed cr0 in a way that did not change
4963                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4964                  * but did change L0 shadowed bits. So we first calculate the
4965                  * effective cr0 value that L1 would like to write into the
4966                  * hardware. It consists of the L2-owned bits from the new
4967                  * value combined with the L1-owned bits from L1's guest_cr0.
4968                  */
4969                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4970                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4971
4972                 if (!nested_guest_cr0_valid(vcpu, val))
4973                         return 1;
4974
4975                 if (kvm_set_cr0(vcpu, val))
4976                         return 1;
4977                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4978                 return 0;
4979         } else {
4980                 if (to_vmx(vcpu)->nested.vmxon &&
4981                     !nested_host_cr0_valid(vcpu, val))
4982                         return 1;
4983
4984                 return kvm_set_cr0(vcpu, val);
4985         }
4986 }
4987
4988 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4989 {
4990         if (is_guest_mode(vcpu)) {
4991                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4992                 unsigned long orig_val = val;
4993
4994                 /* analogously to handle_set_cr0 */
4995                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4996                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4997                 if (kvm_set_cr4(vcpu, val))
4998                         return 1;
4999                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5000                 return 0;
5001         } else
5002                 return kvm_set_cr4(vcpu, val);
5003 }
5004
5005 static int handle_desc(struct kvm_vcpu *vcpu)
5006 {
5007         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
5008         return kvm_emulate_instruction(vcpu, 0);
5009 }
5010
5011 static int handle_cr(struct kvm_vcpu *vcpu)
5012 {
5013         unsigned long exit_qualification, val;
5014         int cr;
5015         int reg;
5016         int err;
5017         int ret;
5018
5019         exit_qualification = vmx_get_exit_qual(vcpu);
5020         cr = exit_qualification & 15;
5021         reg = (exit_qualification >> 8) & 15;
5022         switch ((exit_qualification >> 4) & 3) {
5023         case 0: /* mov to cr */
5024                 val = kvm_register_read(vcpu, reg);
5025                 trace_kvm_cr_write(cr, val);
5026                 switch (cr) {
5027                 case 0:
5028                         err = handle_set_cr0(vcpu, val);
5029                         return kvm_complete_insn_gp(vcpu, err);
5030                 case 3:
5031                         WARN_ON_ONCE(enable_unrestricted_guest);
5032
5033                         err = kvm_set_cr3(vcpu, val);
5034                         return kvm_complete_insn_gp(vcpu, err);
5035                 case 4:
5036                         err = handle_set_cr4(vcpu, val);
5037                         return kvm_complete_insn_gp(vcpu, err);
5038                 case 8: {
5039                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5040                                 u8 cr8 = (u8)val;
5041                                 err = kvm_set_cr8(vcpu, cr8);
5042                                 ret = kvm_complete_insn_gp(vcpu, err);
5043                                 if (lapic_in_kernel(vcpu))
5044                                         return ret;
5045                                 if (cr8_prev <= cr8)
5046                                         return ret;
5047                                 /*
5048                                  * TODO: we might be squashing a
5049                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5050                                  * KVM_EXIT_DEBUG here.
5051                                  */
5052                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5053                                 return 0;
5054                         }
5055                 }
5056                 break;
5057         case 2: /* clts */
5058                 KVM_BUG(1, vcpu->kvm, "Guest always owns CR0.TS");
5059                 return -EIO;
5060         case 1: /*mov from cr*/
5061                 switch (cr) {
5062                 case 3:
5063                         WARN_ON_ONCE(enable_unrestricted_guest);
5064
5065                         val = kvm_read_cr3(vcpu);
5066                         kvm_register_write(vcpu, reg, val);
5067                         trace_kvm_cr_read(cr, val);
5068                         return kvm_skip_emulated_instruction(vcpu);
5069                 case 8:
5070                         val = kvm_get_cr8(vcpu);
5071                         kvm_register_write(vcpu, reg, val);
5072                         trace_kvm_cr_read(cr, val);
5073                         return kvm_skip_emulated_instruction(vcpu);
5074                 }
5075                 break;
5076         case 3: /* lmsw */
5077                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5078                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5079                 kvm_lmsw(vcpu, val);
5080
5081                 return kvm_skip_emulated_instruction(vcpu);
5082         default:
5083                 break;
5084         }
5085         vcpu->run->exit_reason = 0;
5086         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5087                (int)(exit_qualification >> 4) & 3, cr);
5088         return 0;
5089 }
5090
5091 static int handle_dr(struct kvm_vcpu *vcpu)
5092 {
5093         unsigned long exit_qualification;
5094         int dr, dr7, reg;
5095         int err = 1;
5096
5097         exit_qualification = vmx_get_exit_qual(vcpu);
5098         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5099
5100         /* First, if DR does not exist, trigger UD */
5101         if (!kvm_require_dr(vcpu, dr))
5102                 return 1;
5103
5104         if (kvm_x86_ops.get_cpl(vcpu) > 0)
5105                 goto out;
5106
5107         dr7 = vmcs_readl(GUEST_DR7);
5108         if (dr7 & DR7_GD) {
5109                 /*
5110                  * As the vm-exit takes precedence over the debug trap, we
5111                  * need to emulate the latter, either for the host or the
5112                  * guest debugging itself.
5113                  */
5114                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5115                         vcpu->run->debug.arch.dr6 = DR6_BD | DR6_ACTIVE_LOW;
5116                         vcpu->run->debug.arch.dr7 = dr7;
5117                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5118                         vcpu->run->debug.arch.exception = DB_VECTOR;
5119                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5120                         return 0;
5121                 } else {
5122                         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5123                         return 1;
5124                 }
5125         }
5126
5127         if (vcpu->guest_debug == 0) {
5128                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5129
5130                 /*
5131                  * No more DR vmexits; force a reload of the debug registers
5132                  * and reenter on this instruction.  The next vmexit will
5133                  * retrieve the full state of the debug registers.
5134                  */
5135                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5136                 return 1;
5137         }
5138
5139         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5140         if (exit_qualification & TYPE_MOV_FROM_DR) {
5141                 unsigned long val;
5142
5143                 kvm_get_dr(vcpu, dr, &val);
5144                 kvm_register_write(vcpu, reg, val);
5145                 err = 0;
5146         } else {
5147                 err = kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg));
5148         }
5149
5150 out:
5151         return kvm_complete_insn_gp(vcpu, err);
5152 }
5153
5154 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5155 {
5156         get_debugreg(vcpu->arch.db[0], 0);
5157         get_debugreg(vcpu->arch.db[1], 1);
5158         get_debugreg(vcpu->arch.db[2], 2);
5159         get_debugreg(vcpu->arch.db[3], 3);
5160         get_debugreg(vcpu->arch.dr6, 6);
5161         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5162
5163         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5164         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5165
5166         /*
5167          * exc_debug expects dr6 to be cleared after it runs, avoid that it sees
5168          * a stale dr6 from the guest.
5169          */
5170         set_debugreg(DR6_RESERVED, 6);
5171 }
5172
5173 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5174 {
5175         vmcs_writel(GUEST_DR7, val);
5176 }
5177
5178 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5179 {
5180         kvm_apic_update_ppr(vcpu);
5181         return 1;
5182 }
5183
5184 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5185 {
5186         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5187
5188         kvm_make_request(KVM_REQ_EVENT, vcpu);
5189
5190         ++vcpu->stat.irq_window_exits;
5191         return 1;
5192 }
5193
5194 static int handle_invlpg(struct kvm_vcpu *vcpu)
5195 {
5196         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5197
5198         kvm_mmu_invlpg(vcpu, exit_qualification);
5199         return kvm_skip_emulated_instruction(vcpu);
5200 }
5201
5202 static int handle_apic_access(struct kvm_vcpu *vcpu)
5203 {
5204         if (likely(fasteoi)) {
5205                 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5206                 int access_type, offset;
5207
5208                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5209                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5210                 /*
5211                  * Sane guest uses MOV to write EOI, with written value
5212                  * not cared. So make a short-circuit here by avoiding
5213                  * heavy instruction emulation.
5214                  */
5215                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5216                     (offset == APIC_EOI)) {
5217                         kvm_lapic_set_eoi(vcpu);
5218                         return kvm_skip_emulated_instruction(vcpu);
5219                 }
5220         }
5221         return kvm_emulate_instruction(vcpu, 0);
5222 }
5223
5224 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5225 {
5226         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5227         int vector = exit_qualification & 0xff;
5228
5229         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5230         kvm_apic_set_eoi_accelerated(vcpu, vector);
5231         return 1;
5232 }
5233
5234 static int handle_apic_write(struct kvm_vcpu *vcpu)
5235 {
5236         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5237         u32 offset = exit_qualification & 0xfff;
5238
5239         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5240         kvm_apic_write_nodecode(vcpu, offset);
5241         return 1;
5242 }
5243
5244 static int handle_task_switch(struct kvm_vcpu *vcpu)
5245 {
5246         struct vcpu_vmx *vmx = to_vmx(vcpu);
5247         unsigned long exit_qualification;
5248         bool has_error_code = false;
5249         u32 error_code = 0;
5250         u16 tss_selector;
5251         int reason, type, idt_v, idt_index;
5252
5253         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5254         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5255         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5256
5257         exit_qualification = vmx_get_exit_qual(vcpu);
5258
5259         reason = (u32)exit_qualification >> 30;
5260         if (reason == TASK_SWITCH_GATE && idt_v) {
5261                 switch (type) {
5262                 case INTR_TYPE_NMI_INTR:
5263                         vcpu->arch.nmi_injected = false;
5264                         vmx_set_nmi_mask(vcpu, true);
5265                         break;
5266                 case INTR_TYPE_EXT_INTR:
5267                 case INTR_TYPE_SOFT_INTR:
5268                         kvm_clear_interrupt_queue(vcpu);
5269                         break;
5270                 case INTR_TYPE_HARD_EXCEPTION:
5271                         if (vmx->idt_vectoring_info &
5272                             VECTORING_INFO_DELIVER_CODE_MASK) {
5273                                 has_error_code = true;
5274                                 error_code =
5275                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5276                         }
5277                         fallthrough;
5278                 case INTR_TYPE_SOFT_EXCEPTION:
5279                         kvm_clear_exception_queue(vcpu);
5280                         break;
5281                 default:
5282                         break;
5283                 }
5284         }
5285         tss_selector = exit_qualification;
5286
5287         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5288                        type != INTR_TYPE_EXT_INTR &&
5289                        type != INTR_TYPE_NMI_INTR))
5290                 WARN_ON(!skip_emulated_instruction(vcpu));
5291
5292         /*
5293          * TODO: What about debug traps on tss switch?
5294          *       Are we supposed to inject them and update dr6?
5295          */
5296         return kvm_task_switch(vcpu, tss_selector,
5297                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5298                                reason, has_error_code, error_code);
5299 }
5300
5301 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5302 {
5303         unsigned long exit_qualification;
5304         gpa_t gpa;
5305         u64 error_code;
5306
5307         exit_qualification = vmx_get_exit_qual(vcpu);
5308
5309         /*
5310          * EPT violation happened while executing iret from NMI,
5311          * "blocked by NMI" bit has to be set before next VM entry.
5312          * There are errata that may cause this bit to not be set:
5313          * AAK134, BY25.
5314          */
5315         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5316                         enable_vnmi &&
5317                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5318                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5319
5320         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5321         trace_kvm_page_fault(gpa, exit_qualification);
5322
5323         /* Is it a read fault? */
5324         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5325                      ? PFERR_USER_MASK : 0;
5326         /* Is it a write fault? */
5327         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5328                       ? PFERR_WRITE_MASK : 0;
5329         /* Is it a fetch fault? */
5330         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5331                       ? PFERR_FETCH_MASK : 0;
5332         /* ept page table entry is present? */
5333         error_code |= (exit_qualification &
5334                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5335                         EPT_VIOLATION_EXECUTABLE))
5336                       ? PFERR_PRESENT_MASK : 0;
5337
5338         error_code |= (exit_qualification & EPT_VIOLATION_GVA_TRANSLATED) != 0 ?
5339                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5340
5341         vcpu->arch.exit_qualification = exit_qualification;
5342
5343         /*
5344          * Check that the GPA doesn't exceed physical memory limits, as that is
5345          * a guest page fault.  We have to emulate the instruction here, because
5346          * if the illegal address is that of a paging structure, then
5347          * EPT_VIOLATION_ACC_WRITE bit is set.  Alternatively, if supported we
5348          * would also use advanced VM-exit information for EPT violations to
5349          * reconstruct the page fault error code.
5350          */
5351         if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa)))
5352                 return kvm_emulate_instruction(vcpu, 0);
5353
5354         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5355 }
5356
5357 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5358 {
5359         gpa_t gpa;
5360
5361         if (!vmx_can_emulate_instruction(vcpu, NULL, 0))
5362                 return 1;
5363
5364         /*
5365          * A nested guest cannot optimize MMIO vmexits, because we have an
5366          * nGPA here instead of the required GPA.
5367          */
5368         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5369         if (!is_guest_mode(vcpu) &&
5370             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5371                 trace_kvm_fast_mmio(gpa);
5372                 return kvm_skip_emulated_instruction(vcpu);
5373         }
5374
5375         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5376 }
5377
5378 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5379 {
5380         if (KVM_BUG_ON(!enable_vnmi, vcpu->kvm))
5381                 return -EIO;
5382
5383         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5384         ++vcpu->stat.nmi_window_exits;
5385         kvm_make_request(KVM_REQ_EVENT, vcpu);
5386
5387         return 1;
5388 }
5389
5390 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5391 {
5392         struct vcpu_vmx *vmx = to_vmx(vcpu);
5393         bool intr_window_requested;
5394         unsigned count = 130;
5395
5396         intr_window_requested = exec_controls_get(vmx) &
5397                                 CPU_BASED_INTR_WINDOW_EXITING;
5398
5399         while (vmx->emulation_required && count-- != 0) {
5400                 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5401                         return handle_interrupt_window(&vmx->vcpu);
5402
5403                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5404                         return 1;
5405
5406                 if (!kvm_emulate_instruction(vcpu, 0))
5407                         return 0;
5408
5409                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5410                     vcpu->arch.exception.pending) {
5411                         kvm_prepare_emulation_failure_exit(vcpu);
5412                         return 0;
5413                 }
5414
5415                 if (vcpu->arch.halt_request) {
5416                         vcpu->arch.halt_request = 0;
5417                         return kvm_vcpu_halt(vcpu);
5418                 }
5419
5420                 /*
5421                  * Note, return 1 and not 0, vcpu_run() will invoke
5422                  * xfer_to_guest_mode() which will create a proper return
5423                  * code.
5424                  */
5425                 if (__xfer_to_guest_mode_work_pending())
5426                         return 1;
5427         }
5428
5429         return 1;
5430 }
5431
5432 static void grow_ple_window(struct kvm_vcpu *vcpu)
5433 {
5434         struct vcpu_vmx *vmx = to_vmx(vcpu);
5435         unsigned int old = vmx->ple_window;
5436
5437         vmx->ple_window = __grow_ple_window(old, ple_window,
5438                                             ple_window_grow,
5439                                             ple_window_max);
5440
5441         if (vmx->ple_window != old) {
5442                 vmx->ple_window_dirty = true;
5443                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5444                                             vmx->ple_window, old);
5445         }
5446 }
5447
5448 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5449 {
5450         struct vcpu_vmx *vmx = to_vmx(vcpu);
5451         unsigned int old = vmx->ple_window;
5452
5453         vmx->ple_window = __shrink_ple_window(old, ple_window,
5454                                               ple_window_shrink,
5455                                               ple_window);
5456
5457         if (vmx->ple_window != old) {
5458                 vmx->ple_window_dirty = true;
5459                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5460                                             vmx->ple_window, old);
5461         }
5462 }
5463
5464 /*
5465  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5466  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5467  */
5468 static int handle_pause(struct kvm_vcpu *vcpu)
5469 {
5470         if (!kvm_pause_in_guest(vcpu->kvm))
5471                 grow_ple_window(vcpu);
5472
5473         /*
5474          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5475          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5476          * never set PAUSE_EXITING and just set PLE if supported,
5477          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5478          */
5479         kvm_vcpu_on_spin(vcpu, true);
5480         return kvm_skip_emulated_instruction(vcpu);
5481 }
5482
5483 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5484 {
5485         return 1;
5486 }
5487
5488 static int handle_invpcid(struct kvm_vcpu *vcpu)
5489 {
5490         u32 vmx_instruction_info;
5491         unsigned long type;
5492         gva_t gva;
5493         struct {
5494                 u64 pcid;
5495                 u64 gla;
5496         } operand;
5497
5498         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5499                 kvm_queue_exception(vcpu, UD_VECTOR);
5500                 return 1;
5501         }
5502
5503         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5504         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
5505
5506         if (type > 3) {
5507                 kvm_inject_gp(vcpu, 0);
5508                 return 1;
5509         }
5510
5511         /* According to the Intel instruction reference, the memory operand
5512          * is read even if it isn't needed (e.g., for type==all)
5513          */
5514         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5515                                 vmx_instruction_info, false,
5516                                 sizeof(operand), &gva))
5517                 return 1;
5518
5519         return kvm_handle_invpcid(vcpu, type, gva);
5520 }
5521
5522 static int handle_pml_full(struct kvm_vcpu *vcpu)
5523 {
5524         unsigned long exit_qualification;
5525
5526         trace_kvm_pml_full(vcpu->vcpu_id);
5527
5528         exit_qualification = vmx_get_exit_qual(vcpu);
5529
5530         /*
5531          * PML buffer FULL happened while executing iret from NMI,
5532          * "blocked by NMI" bit has to be set before next VM entry.
5533          */
5534         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5535                         enable_vnmi &&
5536                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5537                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5538                                 GUEST_INTR_STATE_NMI);
5539
5540         /*
5541          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5542          * here.., and there's no userspace involvement needed for PML.
5543          */
5544         return 1;
5545 }
5546
5547 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5548 {
5549         struct vcpu_vmx *vmx = to_vmx(vcpu);
5550
5551         if (!vmx->req_immediate_exit &&
5552             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5553                 kvm_lapic_expired_hv_timer(vcpu);
5554                 return EXIT_FASTPATH_REENTER_GUEST;
5555         }
5556
5557         return EXIT_FASTPATH_NONE;
5558 }
5559
5560 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5561 {
5562         handle_fastpath_preemption_timer(vcpu);
5563         return 1;
5564 }
5565
5566 /*
5567  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5568  * are overwritten by nested_vmx_setup() when nested=1.
5569  */
5570 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5571 {
5572         kvm_queue_exception(vcpu, UD_VECTOR);
5573         return 1;
5574 }
5575
5576 #ifndef CONFIG_X86_SGX_KVM
5577 static int handle_encls(struct kvm_vcpu *vcpu)
5578 {
5579         /*
5580          * SGX virtualization is disabled.  There is no software enable bit for
5581          * SGX, so KVM intercepts all ENCLS leafs and injects a #UD to prevent
5582          * the guest from executing ENCLS (when SGX is supported by hardware).
5583          */
5584         kvm_queue_exception(vcpu, UD_VECTOR);
5585         return 1;
5586 }
5587 #endif /* CONFIG_X86_SGX_KVM */
5588
5589 static int handle_bus_lock_vmexit(struct kvm_vcpu *vcpu)
5590 {
5591         vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
5592         vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
5593         return 0;
5594 }
5595
5596 /*
5597  * The exit handlers return 1 if the exit was handled fully and guest execution
5598  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5599  * to be done to userspace and return 0.
5600  */
5601 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5602         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5603         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5604         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5605         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5606         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5607         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5608         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5609         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5610         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5611         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5612         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5613         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5614         [EXIT_REASON_INVD]                    = kvm_emulate_invd,
5615         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5616         [EXIT_REASON_RDPMC]                   = kvm_emulate_rdpmc,
5617         [EXIT_REASON_VMCALL]                  = kvm_emulate_hypercall,
5618         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5619         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5620         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5621         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5622         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5623         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5624         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5625         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5626         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5627         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5628         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5629         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5630         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5631         [EXIT_REASON_WBINVD]                  = kvm_emulate_wbinvd,
5632         [EXIT_REASON_XSETBV]                  = kvm_emulate_xsetbv,
5633         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5634         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5635         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5636         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5637         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5638         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5639         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5640         [EXIT_REASON_MWAIT_INSTRUCTION]       = kvm_emulate_mwait,
5641         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5642         [EXIT_REASON_MONITOR_INSTRUCTION]     = kvm_emulate_monitor,
5643         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5644         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5645         [EXIT_REASON_RDRAND]                  = kvm_handle_invalid_op,
5646         [EXIT_REASON_RDSEED]                  = kvm_handle_invalid_op,
5647         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5648         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5649         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5650         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5651         [EXIT_REASON_ENCLS]                   = handle_encls,
5652         [EXIT_REASON_BUS_LOCK]                = handle_bus_lock_vmexit,
5653 };
5654
5655 static const int kvm_vmx_max_exit_handlers =
5656         ARRAY_SIZE(kvm_vmx_exit_handlers);
5657
5658 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
5659                               u64 *info1, u64 *info2,
5660                               u32 *intr_info, u32 *error_code)
5661 {
5662         struct vcpu_vmx *vmx = to_vmx(vcpu);
5663
5664         *reason = vmx->exit_reason.full;
5665         *info1 = vmx_get_exit_qual(vcpu);
5666         if (!(vmx->exit_reason.failed_vmentry)) {
5667                 *info2 = vmx->idt_vectoring_info;
5668                 *intr_info = vmx_get_intr_info(vcpu);
5669                 if (is_exception_with_error_code(*intr_info))
5670                         *error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5671                 else
5672                         *error_code = 0;
5673         } else {
5674                 *info2 = 0;
5675                 *intr_info = 0;
5676                 *error_code = 0;
5677         }
5678 }
5679
5680 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5681 {
5682         if (vmx->pml_pg) {
5683                 __free_page(vmx->pml_pg);
5684                 vmx->pml_pg = NULL;
5685         }
5686 }
5687
5688 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5689 {
5690         struct vcpu_vmx *vmx = to_vmx(vcpu);
5691         u64 *pml_buf;
5692         u16 pml_idx;
5693
5694         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5695
5696         /* Do nothing if PML buffer is empty */
5697         if (pml_idx == (PML_ENTITY_NUM - 1))
5698                 return;
5699
5700         /* PML index always points to next available PML buffer entity */
5701         if (pml_idx >= PML_ENTITY_NUM)
5702                 pml_idx = 0;
5703         else
5704                 pml_idx++;
5705
5706         pml_buf = page_address(vmx->pml_pg);
5707         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5708                 u64 gpa;
5709
5710                 gpa = pml_buf[pml_idx];
5711                 WARN_ON(gpa & (PAGE_SIZE - 1));
5712                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5713         }
5714
5715         /* reset PML index */
5716         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5717 }
5718
5719 static void vmx_dump_sel(char *name, uint32_t sel)
5720 {
5721         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5722                name, vmcs_read16(sel),
5723                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5724                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5725                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5726 }
5727
5728 static void vmx_dump_dtsel(char *name, uint32_t limit)
5729 {
5730         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5731                name, vmcs_read32(limit),
5732                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5733 }
5734
5735 static void vmx_dump_msrs(char *name, struct vmx_msrs *m)
5736 {
5737         unsigned int i;
5738         struct vmx_msr_entry *e;
5739
5740         pr_err("MSR %s:\n", name);
5741         for (i = 0, e = m->val; i < m->nr; ++i, ++e)
5742                 pr_err("  %2d: msr=0x%08x value=0x%016llx\n", i, e->index, e->value);
5743 }
5744
5745 void dump_vmcs(struct kvm_vcpu *vcpu)
5746 {
5747         struct vcpu_vmx *vmx = to_vmx(vcpu);
5748         u32 vmentry_ctl, vmexit_ctl;
5749         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5750         unsigned long cr4;
5751         int efer_slot;
5752
5753         if (!dump_invalid_vmcs) {
5754                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5755                 return;
5756         }
5757
5758         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5759         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5760         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5761         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5762         cr4 = vmcs_readl(GUEST_CR4);
5763         secondary_exec_control = 0;
5764         if (cpu_has_secondary_exec_ctrls())
5765                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5766
5767         pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
5768                vmx->loaded_vmcs->vmcs, vcpu->arch.last_vmentry_cpu);
5769         pr_err("*** Guest State ***\n");
5770         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5771                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5772                vmcs_readl(CR0_GUEST_HOST_MASK));
5773         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5774                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5775         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5776         if (cpu_has_vmx_ept()) {
5777                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5778                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5779                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5780                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5781         }
5782         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5783                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5784         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5785                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5786         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5787                vmcs_readl(GUEST_SYSENTER_ESP),
5788                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5789         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5790         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5791         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5792         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5793         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5794         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5795         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5796         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5797         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5798         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5799         efer_slot = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, MSR_EFER);
5800         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_EFER)
5801                 pr_err("EFER= 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER));
5802         else if (efer_slot >= 0)
5803                 pr_err("EFER= 0x%016llx (autoload)\n",
5804                        vmx->msr_autoload.guest.val[efer_slot].value);
5805         else if (vmentry_ctl & VM_ENTRY_IA32E_MODE)
5806                 pr_err("EFER= 0x%016llx (effective)\n",
5807                        vcpu->arch.efer | (EFER_LMA | EFER_LME));
5808         else
5809                 pr_err("EFER= 0x%016llx (effective)\n",
5810                        vcpu->arch.efer & ~(EFER_LMA | EFER_LME));
5811         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PAT)
5812                 pr_err("PAT = 0x%016llx\n", vmcs_read64(GUEST_IA32_PAT));
5813         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5814                vmcs_read64(GUEST_IA32_DEBUGCTL),
5815                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5816         if (cpu_has_load_perf_global_ctrl() &&
5817             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5818                 pr_err("PerfGlobCtl = 0x%016llx\n",
5819                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5820         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5821                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5822         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5823                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5824                vmcs_read32(GUEST_ACTIVITY_STATE));
5825         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5826                 pr_err("InterruptStatus = %04x\n",
5827                        vmcs_read16(GUEST_INTR_STATUS));
5828         if (vmcs_read32(VM_ENTRY_MSR_LOAD_COUNT) > 0)
5829                 vmx_dump_msrs("guest autoload", &vmx->msr_autoload.guest);
5830         if (vmcs_read32(VM_EXIT_MSR_STORE_COUNT) > 0)
5831                 vmx_dump_msrs("guest autostore", &vmx->msr_autostore.guest);
5832
5833         pr_err("*** Host State ***\n");
5834         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5835                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5836         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5837                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5838                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5839                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5840                vmcs_read16(HOST_TR_SELECTOR));
5841         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5842                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5843                vmcs_readl(HOST_TR_BASE));
5844         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5845                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5846         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5847                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5848                vmcs_readl(HOST_CR4));
5849         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5850                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5851                vmcs_read32(HOST_IA32_SYSENTER_CS),
5852                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5853         if (vmexit_ctl & VM_EXIT_LOAD_IA32_EFER)
5854                 pr_err("EFER= 0x%016llx\n", vmcs_read64(HOST_IA32_EFER));
5855         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PAT)
5856                 pr_err("PAT = 0x%016llx\n", vmcs_read64(HOST_IA32_PAT));
5857         if (cpu_has_load_perf_global_ctrl() &&
5858             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5859                 pr_err("PerfGlobCtl = 0x%016llx\n",
5860                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5861         if (vmcs_read32(VM_EXIT_MSR_LOAD_COUNT) > 0)
5862                 vmx_dump_msrs("host autoload", &vmx->msr_autoload.host);
5863
5864         pr_err("*** Control State ***\n");
5865         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5866                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5867         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5868         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5869                vmcs_read32(EXCEPTION_BITMAP),
5870                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5871                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5872         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5873                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5874                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5875                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5876         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5877                vmcs_read32(VM_EXIT_INTR_INFO),
5878                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5879                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5880         pr_err("        reason=%08x qualification=%016lx\n",
5881                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5882         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5883                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5884                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5885         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5886         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5887                 pr_err("TSC Multiplier = 0x%016llx\n",
5888                        vmcs_read64(TSC_MULTIPLIER));
5889         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5890                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5891                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5892                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5893                 }
5894                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5895                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5896                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5897                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5898         }
5899         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5900                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5901         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5902                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5903         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5904                 pr_err("PLE Gap=%08x Window=%08x\n",
5905                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5906         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5907                 pr_err("Virtual processor ID = 0x%04x\n",
5908                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5909 }
5910
5911 /*
5912  * The guest has exited.  See if we can fix it or if we need userspace
5913  * assistance.
5914  */
5915 static int __vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5916 {
5917         struct vcpu_vmx *vmx = to_vmx(vcpu);
5918         union vmx_exit_reason exit_reason = vmx->exit_reason;
5919         u32 vectoring_info = vmx->idt_vectoring_info;
5920         u16 exit_handler_index;
5921
5922         /*
5923          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5924          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5925          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5926          * mode as if vcpus is in root mode, the PML buffer must has been
5927          * flushed already.  Note, PML is never enabled in hardware while
5928          * running L2.
5929          */
5930         if (enable_pml && !is_guest_mode(vcpu))
5931                 vmx_flush_pml_buffer(vcpu);
5932
5933         /*
5934          * We should never reach this point with a pending nested VM-Enter, and
5935          * more specifically emulation of L2 due to invalid guest state (see
5936          * below) should never happen as that means we incorrectly allowed a
5937          * nested VM-Enter with an invalid vmcs12.
5938          */
5939         if (KVM_BUG_ON(vmx->nested.nested_run_pending, vcpu->kvm))
5940                 return -EIO;
5941
5942         /* If guest state is invalid, start emulating */
5943         if (vmx->emulation_required)
5944                 return handle_invalid_guest_state(vcpu);
5945
5946         if (is_guest_mode(vcpu)) {
5947                 /*
5948                  * PML is never enabled when running L2, bail immediately if a
5949                  * PML full exit occurs as something is horribly wrong.
5950                  */
5951                 if (exit_reason.basic == EXIT_REASON_PML_FULL)
5952                         goto unexpected_vmexit;
5953
5954                 /*
5955                  * The host physical addresses of some pages of guest memory
5956                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5957                  * Page). The CPU may write to these pages via their host
5958                  * physical address while L2 is running, bypassing any
5959                  * address-translation-based dirty tracking (e.g. EPT write
5960                  * protection).
5961                  *
5962                  * Mark them dirty on every exit from L2 to prevent them from
5963                  * getting out of sync with dirty tracking.
5964                  */
5965                 nested_mark_vmcs12_pages_dirty(vcpu);
5966
5967                 if (nested_vmx_reflect_vmexit(vcpu))
5968                         return 1;
5969         }
5970
5971         if (exit_reason.failed_vmentry) {
5972                 dump_vmcs(vcpu);
5973                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5974                 vcpu->run->fail_entry.hardware_entry_failure_reason
5975                         = exit_reason.full;
5976                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5977                 return 0;
5978         }
5979
5980         if (unlikely(vmx->fail)) {
5981                 dump_vmcs(vcpu);
5982                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5983                 vcpu->run->fail_entry.hardware_entry_failure_reason
5984                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5985                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5986                 return 0;
5987         }
5988
5989         /*
5990          * Note:
5991          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5992          * delivery event since it indicates guest is accessing MMIO.
5993          * The vm-exit can be triggered again after return to guest that
5994          * will cause infinite loop.
5995          */
5996         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5997             (exit_reason.basic != EXIT_REASON_EXCEPTION_NMI &&
5998              exit_reason.basic != EXIT_REASON_EPT_VIOLATION &&
5999              exit_reason.basic != EXIT_REASON_PML_FULL &&
6000              exit_reason.basic != EXIT_REASON_APIC_ACCESS &&
6001              exit_reason.basic != EXIT_REASON_TASK_SWITCH)) {
6002                 int ndata = 3;
6003
6004                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6005                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6006                 vcpu->run->internal.data[0] = vectoring_info;
6007                 vcpu->run->internal.data[1] = exit_reason.full;
6008                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
6009                 if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG) {
6010                         vcpu->run->internal.data[ndata++] =
6011                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6012                 }
6013                 vcpu->run->internal.data[ndata++] = vcpu->arch.last_vmentry_cpu;
6014                 vcpu->run->internal.ndata = ndata;
6015                 return 0;
6016         }
6017
6018         if (unlikely(!enable_vnmi &&
6019                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
6020                 if (!vmx_interrupt_blocked(vcpu)) {
6021                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6022                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
6023                            vcpu->arch.nmi_pending) {
6024                         /*
6025                          * This CPU don't support us in finding the end of an
6026                          * NMI-blocked window if the guest runs with IRQs
6027                          * disabled. So we pull the trigger after 1 s of
6028                          * futile waiting, but inform the user about this.
6029                          */
6030                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6031                                "state on VCPU %d after 1 s timeout\n",
6032                                __func__, vcpu->vcpu_id);
6033                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6034                 }
6035         }
6036
6037         if (exit_fastpath != EXIT_FASTPATH_NONE)
6038                 return 1;
6039
6040         if (exit_reason.basic >= kvm_vmx_max_exit_handlers)
6041                 goto unexpected_vmexit;
6042 #ifdef CONFIG_RETPOLINE
6043         if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
6044                 return kvm_emulate_wrmsr(vcpu);
6045         else if (exit_reason.basic == EXIT_REASON_PREEMPTION_TIMER)
6046                 return handle_preemption_timer(vcpu);
6047         else if (exit_reason.basic == EXIT_REASON_INTERRUPT_WINDOW)
6048                 return handle_interrupt_window(vcpu);
6049         else if (exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6050                 return handle_external_interrupt(vcpu);
6051         else if (exit_reason.basic == EXIT_REASON_HLT)
6052                 return kvm_emulate_halt(vcpu);
6053         else if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG)
6054                 return handle_ept_misconfig(vcpu);
6055 #endif
6056
6057         exit_handler_index = array_index_nospec((u16)exit_reason.basic,
6058                                                 kvm_vmx_max_exit_handlers);
6059         if (!kvm_vmx_exit_handlers[exit_handler_index])
6060                 goto unexpected_vmexit;
6061
6062         return kvm_vmx_exit_handlers[exit_handler_index](vcpu);
6063
6064 unexpected_vmexit:
6065         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
6066                     exit_reason.full);
6067         dump_vmcs(vcpu);
6068         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6069         vcpu->run->internal.suberror =
6070                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6071         vcpu->run->internal.ndata = 2;
6072         vcpu->run->internal.data[0] = exit_reason.full;
6073         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6074         return 0;
6075 }
6076
6077 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6078 {
6079         int ret = __vmx_handle_exit(vcpu, exit_fastpath);
6080
6081         /*
6082          * Even when current exit reason is handled by KVM internally, we
6083          * still need to exit to user space when bus lock detected to inform
6084          * that there is a bus lock in guest.
6085          */
6086         if (to_vmx(vcpu)->exit_reason.bus_lock_detected) {
6087                 if (ret > 0)
6088                         vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
6089
6090                 vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
6091                 return 0;
6092         }
6093         return ret;
6094 }
6095
6096 /*
6097  * Software based L1D cache flush which is used when microcode providing
6098  * the cache control MSR is not loaded.
6099  *
6100  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6101  * flush it is required to read in 64 KiB because the replacement algorithm
6102  * is not exactly LRU. This could be sized at runtime via topology
6103  * information but as all relevant affected CPUs have 32KiB L1D cache size
6104  * there is no point in doing so.
6105  */
6106 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6107 {
6108         int size = PAGE_SIZE << L1D_CACHE_ORDER;
6109
6110         /*
6111          * This code is only executed when the the flush mode is 'cond' or
6112          * 'always'
6113          */
6114         if (static_branch_likely(&vmx_l1d_flush_cond)) {
6115                 bool flush_l1d;
6116
6117                 /*
6118                  * Clear the per-vcpu flush bit, it gets set again
6119                  * either from vcpu_run() or from one of the unsafe
6120                  * VMEXIT handlers.
6121                  */
6122                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6123                 vcpu->arch.l1tf_flush_l1d = false;
6124
6125                 /*
6126                  * Clear the per-cpu flush bit, it gets set again from
6127                  * the interrupt handlers.
6128                  */
6129                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6130                 kvm_clear_cpu_l1tf_flush_l1d();
6131
6132                 if (!flush_l1d)
6133                         return;
6134         }
6135
6136         vcpu->stat.l1d_flush++;
6137
6138         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6139                 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6140                 return;
6141         }
6142
6143         asm volatile(
6144                 /* First ensure the pages are in the TLB */
6145                 "xorl   %%eax, %%eax\n"
6146                 ".Lpopulate_tlb:\n\t"
6147                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6148                 "addl   $4096, %%eax\n\t"
6149                 "cmpl   %%eax, %[size]\n\t"
6150                 "jne    .Lpopulate_tlb\n\t"
6151                 "xorl   %%eax, %%eax\n\t"
6152                 "cpuid\n\t"
6153                 /* Now fill the cache */
6154                 "xorl   %%eax, %%eax\n"
6155                 ".Lfill_cache:\n"
6156                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6157                 "addl   $64, %%eax\n\t"
6158                 "cmpl   %%eax, %[size]\n\t"
6159                 "jne    .Lfill_cache\n\t"
6160                 "lfence\n"
6161                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6162                     [size] "r" (size)
6163                 : "eax", "ebx", "ecx", "edx");
6164 }
6165
6166 static void vmx_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6167 {
6168         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6169         int tpr_threshold;
6170
6171         if (is_guest_mode(vcpu) &&
6172                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6173                 return;
6174
6175         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6176         if (is_guest_mode(vcpu))
6177                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6178         else
6179                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6180 }
6181
6182 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6183 {
6184         struct vcpu_vmx *vmx = to_vmx(vcpu);
6185         u32 sec_exec_control;
6186
6187         if (!lapic_in_kernel(vcpu))
6188                 return;
6189
6190         if (!flexpriority_enabled &&
6191             !cpu_has_vmx_virtualize_x2apic_mode())
6192                 return;
6193
6194         /* Postpone execution until vmcs01 is the current VMCS. */
6195         if (is_guest_mode(vcpu)) {
6196                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6197                 return;
6198         }
6199
6200         sec_exec_control = secondary_exec_controls_get(vmx);
6201         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6202                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6203
6204         switch (kvm_get_apic_mode(vcpu)) {
6205         case LAPIC_MODE_INVALID:
6206                 WARN_ONCE(true, "Invalid local APIC state");
6207                 break;
6208         case LAPIC_MODE_DISABLED:
6209                 break;
6210         case LAPIC_MODE_XAPIC:
6211                 if (flexpriority_enabled) {
6212                         sec_exec_control |=
6213                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6214                         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6215
6216                         /*
6217                          * Flush the TLB, reloading the APIC access page will
6218                          * only do so if its physical address has changed, but
6219                          * the guest may have inserted a non-APIC mapping into
6220                          * the TLB while the APIC access page was disabled.
6221                          */
6222                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6223                 }
6224                 break;
6225         case LAPIC_MODE_X2APIC:
6226                 if (cpu_has_vmx_virtualize_x2apic_mode())
6227                         sec_exec_control |=
6228                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6229                 break;
6230         }
6231         secondary_exec_controls_set(vmx, sec_exec_control);
6232
6233         vmx_update_msr_bitmap_x2apic(vcpu);
6234 }
6235
6236 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6237 {
6238         struct page *page;
6239
6240         /* Defer reload until vmcs01 is the current VMCS. */
6241         if (is_guest_mode(vcpu)) {
6242                 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6243                 return;
6244         }
6245
6246         if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6247             SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6248                 return;
6249
6250         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6251         if (is_error_page(page))
6252                 return;
6253
6254         vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6255         vmx_flush_tlb_current(vcpu);
6256
6257         /*
6258          * Do not pin apic access page in memory, the MMU notifier
6259          * will call us again if it is migrated or swapped out.
6260          */
6261         put_page(page);
6262 }
6263
6264 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6265 {
6266         u16 status;
6267         u8 old;
6268
6269         if (max_isr == -1)
6270                 max_isr = 0;
6271
6272         status = vmcs_read16(GUEST_INTR_STATUS);
6273         old = status >> 8;
6274         if (max_isr != old) {
6275                 status &= 0xff;
6276                 status |= max_isr << 8;
6277                 vmcs_write16(GUEST_INTR_STATUS, status);
6278         }
6279 }
6280
6281 static void vmx_set_rvi(int vector)
6282 {
6283         u16 status;
6284         u8 old;
6285
6286         if (vector == -1)
6287                 vector = 0;
6288
6289         status = vmcs_read16(GUEST_INTR_STATUS);
6290         old = (u8)status & 0xff;
6291         if ((u8)vector != old) {
6292                 status &= ~0xff;
6293                 status |= (u8)vector;
6294                 vmcs_write16(GUEST_INTR_STATUS, status);
6295         }
6296 }
6297
6298 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6299 {
6300         /*
6301          * When running L2, updating RVI is only relevant when
6302          * vmcs12 virtual-interrupt-delivery enabled.
6303          * However, it can be enabled only when L1 also
6304          * intercepts external-interrupts and in that case
6305          * we should not update vmcs02 RVI but instead intercept
6306          * interrupt. Therefore, do nothing when running L2.
6307          */
6308         if (!is_guest_mode(vcpu))
6309                 vmx_set_rvi(max_irr);
6310 }
6311
6312 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6313 {
6314         struct vcpu_vmx *vmx = to_vmx(vcpu);
6315         int max_irr;
6316         bool max_irr_updated;
6317
6318         if (KVM_BUG_ON(!vcpu->arch.apicv_active, vcpu->kvm))
6319                 return -EIO;
6320
6321         if (pi_test_on(&vmx->pi_desc)) {
6322                 pi_clear_on(&vmx->pi_desc);
6323                 /*
6324                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6325                  * But on x86 this is just a compiler barrier anyway.
6326                  */
6327                 smp_mb__after_atomic();
6328                 max_irr_updated =
6329                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6330
6331                 /*
6332                  * If we are running L2 and L1 has a new pending interrupt
6333                  * which can be injected, we should re-evaluate
6334                  * what should be done with this new L1 interrupt.
6335                  * If L1 intercepts external-interrupts, we should
6336                  * exit from L2 to L1. Otherwise, interrupt should be
6337                  * delivered directly to L2.
6338                  */
6339                 if (is_guest_mode(vcpu) && max_irr_updated) {
6340                         if (nested_exit_on_intr(vcpu))
6341                                 kvm_vcpu_exiting_guest_mode(vcpu);
6342                         else
6343                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6344                 }
6345         } else {
6346                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6347         }
6348         vmx_hwapic_irr_update(vcpu, max_irr);
6349         return max_irr;
6350 }
6351
6352 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6353 {
6354         if (!kvm_vcpu_apicv_active(vcpu))
6355                 return;
6356
6357         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6358         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6359         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6360         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6361 }
6362
6363 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6364 {
6365         struct vcpu_vmx *vmx = to_vmx(vcpu);
6366
6367         pi_clear_on(&vmx->pi_desc);
6368         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6369 }
6370
6371 void vmx_do_interrupt_nmi_irqoff(unsigned long entry);
6372
6373 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu,
6374                                         unsigned long entry)
6375 {
6376         kvm_before_interrupt(vcpu);
6377         vmx_do_interrupt_nmi_irqoff(entry);
6378         kvm_after_interrupt(vcpu);
6379 }
6380
6381 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6382 {
6383         const unsigned long nmi_entry = (unsigned long)asm_exc_nmi_noist;
6384         u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6385
6386         /* if exit due to PF check for async PF */
6387         if (is_page_fault(intr_info))
6388                 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6389         /* Handle machine checks before interrupts are enabled */
6390         else if (is_machine_check(intr_info))
6391                 kvm_machine_check();
6392         /* We need to handle NMIs before interrupts are enabled */
6393         else if (is_nmi(intr_info))
6394                 handle_interrupt_nmi_irqoff(&vmx->vcpu, nmi_entry);
6395 }
6396
6397 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6398 {
6399         u32 intr_info = vmx_get_intr_info(vcpu);
6400         unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK;
6401         gate_desc *desc = (gate_desc *)host_idt_base + vector;
6402
6403         if (KVM_BUG(!is_external_intr(intr_info), vcpu->kvm,
6404             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6405                 return;
6406
6407         handle_interrupt_nmi_irqoff(vcpu, gate_offset(desc));
6408 }
6409
6410 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6411 {
6412         struct vcpu_vmx *vmx = to_vmx(vcpu);
6413
6414         if (vmx->emulation_required)
6415                 return;
6416
6417         if (vmx->exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6418                 handle_external_interrupt_irqoff(vcpu);
6419         else if (vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI)
6420                 handle_exception_nmi_irqoff(vmx);
6421 }
6422
6423 /*
6424  * The kvm parameter can be NULL (module initialization, or invocation before
6425  * VM creation). Be sure to check the kvm parameter before using it.
6426  */
6427 static bool vmx_has_emulated_msr(struct kvm *kvm, u32 index)
6428 {
6429         switch (index) {
6430         case MSR_IA32_SMBASE:
6431                 /*
6432                  * We cannot do SMM unless we can run the guest in big
6433                  * real mode.
6434                  */
6435                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6436         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6437                 return nested;
6438         case MSR_AMD64_VIRT_SPEC_CTRL:
6439         case MSR_AMD64_TSC_RATIO:
6440                 /* This is AMD only.  */
6441                 return false;
6442         default:
6443                 return true;
6444         }
6445 }
6446
6447 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6448 {
6449         u32 exit_intr_info;
6450         bool unblock_nmi;
6451         u8 vector;
6452         bool idtv_info_valid;
6453
6454         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6455
6456         if (enable_vnmi) {
6457                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6458                         return;
6459
6460                 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6461                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6462                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6463                 /*
6464                  * SDM 3: 27.7.1.2 (September 2008)
6465                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6466                  * a guest IRET fault.
6467                  * SDM 3: 23.2.2 (September 2008)
6468                  * Bit 12 is undefined in any of the following cases:
6469                  *  If the VM exit sets the valid bit in the IDT-vectoring
6470                  *   information field.
6471                  *  If the VM exit is due to a double fault.
6472                  */
6473                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6474                     vector != DF_VECTOR && !idtv_info_valid)
6475                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6476                                       GUEST_INTR_STATE_NMI);
6477                 else
6478                         vmx->loaded_vmcs->nmi_known_unmasked =
6479                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6480                                   & GUEST_INTR_STATE_NMI);
6481         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6482                 vmx->loaded_vmcs->vnmi_blocked_time +=
6483                         ktime_to_ns(ktime_sub(ktime_get(),
6484                                               vmx->loaded_vmcs->entry_time));
6485 }
6486
6487 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6488                                       u32 idt_vectoring_info,
6489                                       int instr_len_field,
6490                                       int error_code_field)
6491 {
6492         u8 vector;
6493         int type;
6494         bool idtv_info_valid;
6495
6496         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6497
6498         vcpu->arch.nmi_injected = false;
6499         kvm_clear_exception_queue(vcpu);
6500         kvm_clear_interrupt_queue(vcpu);
6501
6502         if (!idtv_info_valid)
6503                 return;
6504
6505         kvm_make_request(KVM_REQ_EVENT, vcpu);
6506
6507         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6508         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6509
6510         switch (type) {
6511         case INTR_TYPE_NMI_INTR:
6512                 vcpu->arch.nmi_injected = true;
6513                 /*
6514                  * SDM 3: 27.7.1.2 (September 2008)
6515                  * Clear bit "block by NMI" before VM entry if a NMI
6516                  * delivery faulted.
6517                  */
6518                 vmx_set_nmi_mask(vcpu, false);
6519                 break;
6520         case INTR_TYPE_SOFT_EXCEPTION:
6521                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6522                 fallthrough;
6523         case INTR_TYPE_HARD_EXCEPTION:
6524                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6525                         u32 err = vmcs_read32(error_code_field);
6526                         kvm_requeue_exception_e(vcpu, vector, err);
6527                 } else
6528                         kvm_requeue_exception(vcpu, vector);
6529                 break;
6530         case INTR_TYPE_SOFT_INTR:
6531                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6532                 fallthrough;
6533         case INTR_TYPE_EXT_INTR:
6534                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6535                 break;
6536         default:
6537                 break;
6538         }
6539 }
6540
6541 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6542 {
6543         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6544                                   VM_EXIT_INSTRUCTION_LEN,
6545                                   IDT_VECTORING_ERROR_CODE);
6546 }
6547
6548 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6549 {
6550         __vmx_complete_interrupts(vcpu,
6551                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6552                                   VM_ENTRY_INSTRUCTION_LEN,
6553                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6554
6555         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6556 }
6557
6558 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6559 {
6560         int i, nr_msrs;
6561         struct perf_guest_switch_msr *msrs;
6562
6563         /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
6564         msrs = perf_guest_get_msrs(&nr_msrs);
6565         if (!msrs)
6566                 return;
6567
6568         for (i = 0; i < nr_msrs; i++)
6569                 if (msrs[i].host == msrs[i].guest)
6570                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6571                 else
6572                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6573                                         msrs[i].host, false);
6574 }
6575
6576 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6577 {
6578         struct vcpu_vmx *vmx = to_vmx(vcpu);
6579         u64 tscl;
6580         u32 delta_tsc;
6581
6582         if (vmx->req_immediate_exit) {
6583                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6584                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6585         } else if (vmx->hv_deadline_tsc != -1) {
6586                 tscl = rdtsc();
6587                 if (vmx->hv_deadline_tsc > tscl)
6588                         /* set_hv_timer ensures the delta fits in 32-bits */
6589                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6590                                 cpu_preemption_timer_multi);
6591                 else
6592                         delta_tsc = 0;
6593
6594                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6595                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6596         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6597                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6598                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6599         }
6600 }
6601
6602 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6603 {
6604         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6605                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6606                 vmcs_writel(HOST_RSP, host_rsp);
6607         }
6608 }
6609
6610 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6611 {
6612         switch (to_vmx(vcpu)->exit_reason.basic) {
6613         case EXIT_REASON_MSR_WRITE:
6614                 return handle_fastpath_set_msr_irqoff(vcpu);
6615         case EXIT_REASON_PREEMPTION_TIMER:
6616                 return handle_fastpath_preemption_timer(vcpu);
6617         default:
6618                 return EXIT_FASTPATH_NONE;
6619         }
6620 }
6621
6622 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6623                                         struct vcpu_vmx *vmx)
6624 {
6625         kvm_guest_enter_irqoff();
6626
6627         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6628         if (static_branch_unlikely(&vmx_l1d_should_flush))
6629                 vmx_l1d_flush(vcpu);
6630         else if (static_branch_unlikely(&mds_user_clear))
6631                 mds_clear_cpu_buffers();
6632
6633         if (vcpu->arch.cr2 != native_read_cr2())
6634                 native_write_cr2(vcpu->arch.cr2);
6635
6636         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6637                                    vmx->loaded_vmcs->launched);
6638
6639         vcpu->arch.cr2 = native_read_cr2();
6640
6641         kvm_guest_exit_irqoff();
6642 }
6643
6644 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6645 {
6646         struct vcpu_vmx *vmx = to_vmx(vcpu);
6647         unsigned long cr3, cr4;
6648
6649         /* Record the guest's net vcpu time for enforced NMI injections. */
6650         if (unlikely(!enable_vnmi &&
6651                      vmx->loaded_vmcs->soft_vnmi_blocked))
6652                 vmx->loaded_vmcs->entry_time = ktime_get();
6653
6654         /*
6655          * Don't enter VMX if guest state is invalid, let the exit handler
6656          * start emulation until we arrive back to a valid state.  Synthesize a
6657          * consistency check VM-Exit due to invalid guest state and bail.
6658          */
6659         if (unlikely(vmx->emulation_required)) {
6660
6661                 /* We don't emulate invalid state of a nested guest */
6662                 vmx->fail = is_guest_mode(vcpu);
6663
6664                 vmx->exit_reason.full = EXIT_REASON_INVALID_STATE;
6665                 vmx->exit_reason.failed_vmentry = 1;
6666                 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
6667                 vmx->exit_qualification = ENTRY_FAIL_DEFAULT;
6668                 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
6669                 vmx->exit_intr_info = 0;
6670                 return EXIT_FASTPATH_NONE;
6671         }
6672
6673         trace_kvm_entry(vcpu);
6674
6675         if (vmx->ple_window_dirty) {
6676                 vmx->ple_window_dirty = false;
6677                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6678         }
6679
6680         /*
6681          * We did this in prepare_switch_to_guest, because it needs to
6682          * be within srcu_read_lock.
6683          */
6684         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6685
6686         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6687                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6688         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6689                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6690
6691         cr3 = __get_current_cr3_fast();
6692         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6693                 vmcs_writel(HOST_CR3, cr3);
6694                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6695         }
6696
6697         cr4 = cr4_read_shadow();
6698         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6699                 vmcs_writel(HOST_CR4, cr4);
6700                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6701         }
6702
6703         /* When KVM_DEBUGREG_WONT_EXIT, dr6 is accessible in guest. */
6704         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
6705                 set_debugreg(vcpu->arch.dr6, 6);
6706
6707         /* When single-stepping over STI and MOV SS, we must clear the
6708          * corresponding interruptibility bits in the guest state. Otherwise
6709          * vmentry fails as it then expects bit 14 (BS) in pending debug
6710          * exceptions being set, but that's not correct for the guest debugging
6711          * case. */
6712         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6713                 vmx_set_interrupt_shadow(vcpu, 0);
6714
6715         kvm_load_guest_xsave_state(vcpu);
6716
6717         pt_guest_enter(vmx);
6718
6719         atomic_switch_perf_msrs(vmx);
6720         if (intel_pmu_lbr_is_enabled(vcpu))
6721                 vmx_passthrough_lbr_msrs(vcpu);
6722
6723         if (enable_preemption_timer)
6724                 vmx_update_hv_timer(vcpu);
6725
6726         kvm_wait_lapic_expire(vcpu);
6727
6728         /*
6729          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6730          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6731          * is no need to worry about the conditional branch over the wrmsr
6732          * being speculatively taken.
6733          */
6734         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6735
6736         /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6737         vmx_vcpu_enter_exit(vcpu, vmx);
6738
6739         /*
6740          * We do not use IBRS in the kernel. If this vCPU has used the
6741          * SPEC_CTRL MSR it may have left it on; save the value and
6742          * turn it off. This is much more efficient than blindly adding
6743          * it to the atomic save/restore list. Especially as the former
6744          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6745          *
6746          * For non-nested case:
6747          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6748          * save it.
6749          *
6750          * For nested case:
6751          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6752          * save it.
6753          */
6754         if (unlikely(!msr_write_intercepted(vmx, MSR_IA32_SPEC_CTRL)))
6755                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6756
6757         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6758
6759         /* All fields are clean at this point */
6760         if (static_branch_unlikely(&enable_evmcs)) {
6761                 current_evmcs->hv_clean_fields |=
6762                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6763
6764                 current_evmcs->hv_vp_id = kvm_hv_get_vpindex(vcpu);
6765         }
6766
6767         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6768         if (vmx->host_debugctlmsr)
6769                 update_debugctlmsr(vmx->host_debugctlmsr);
6770
6771 #ifndef CONFIG_X86_64
6772         /*
6773          * The sysexit path does not restore ds/es, so we must set them to
6774          * a reasonable value ourselves.
6775          *
6776          * We can't defer this to vmx_prepare_switch_to_host() since that
6777          * function may be executed in interrupt context, which saves and
6778          * restore segments around it, nullifying its effect.
6779          */
6780         loadsegment(ds, __USER_DS);
6781         loadsegment(es, __USER_DS);
6782 #endif
6783
6784         vmx_register_cache_reset(vcpu);
6785
6786         pt_guest_exit(vmx);
6787
6788         kvm_load_host_xsave_state(vcpu);
6789
6790         if (is_guest_mode(vcpu)) {
6791                 /*
6792                  * Track VMLAUNCH/VMRESUME that have made past guest state
6793                  * checking.
6794                  */
6795                 if (vmx->nested.nested_run_pending &&
6796                     !vmx->exit_reason.failed_vmentry)
6797                         ++vcpu->stat.nested_run;
6798
6799                 vmx->nested.nested_run_pending = 0;
6800         }
6801
6802         vmx->idt_vectoring_info = 0;
6803
6804         if (unlikely(vmx->fail)) {
6805                 vmx->exit_reason.full = 0xdead;
6806                 return EXIT_FASTPATH_NONE;
6807         }
6808
6809         vmx->exit_reason.full = vmcs_read32(VM_EXIT_REASON);
6810         if (unlikely((u16)vmx->exit_reason.basic == EXIT_REASON_MCE_DURING_VMENTRY))
6811                 kvm_machine_check();
6812
6813         if (likely(!vmx->exit_reason.failed_vmentry))
6814                 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6815
6816         trace_kvm_exit(vcpu, KVM_ISA_VMX);
6817
6818         if (unlikely(vmx->exit_reason.failed_vmentry))
6819                 return EXIT_FASTPATH_NONE;
6820
6821         vmx->loaded_vmcs->launched = 1;
6822
6823         vmx_recover_nmi_blocking(vmx);
6824         vmx_complete_interrupts(vmx);
6825
6826         if (is_guest_mode(vcpu))
6827                 return EXIT_FASTPATH_NONE;
6828
6829         return vmx_exit_handlers_fastpath(vcpu);
6830 }
6831
6832 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6833 {
6834         struct vcpu_vmx *vmx = to_vmx(vcpu);
6835
6836         if (enable_pml)
6837                 vmx_destroy_pml_buffer(vmx);
6838         free_vpid(vmx->vpid);
6839         nested_vmx_free_vcpu(vcpu);
6840         free_loaded_vmcs(vmx->loaded_vmcs);
6841 }
6842
6843 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6844 {
6845         struct vmx_uret_msr *tsx_ctrl;
6846         struct vcpu_vmx *vmx;
6847         int i, err;
6848
6849         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6850         vmx = to_vmx(vcpu);
6851
6852         err = -ENOMEM;
6853
6854         vmx->vpid = allocate_vpid();
6855
6856         /*
6857          * If PML is turned on, failure on enabling PML just results in failure
6858          * of creating the vcpu, therefore we can simplify PML logic (by
6859          * avoiding dealing with cases, such as enabling PML partially on vcpus
6860          * for the guest), etc.
6861          */
6862         if (enable_pml) {
6863                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6864                 if (!vmx->pml_pg)
6865                         goto free_vpid;
6866         }
6867
6868         for (i = 0; i < kvm_nr_uret_msrs; ++i)
6869                 vmx->guest_uret_msrs[i].mask = -1ull;
6870         if (boot_cpu_has(X86_FEATURE_RTM)) {
6871                 /*
6872                  * TSX_CTRL_CPUID_CLEAR is handled in the CPUID interception.
6873                  * Keep the host value unchanged to avoid changing CPUID bits
6874                  * under the host kernel's feet.
6875                  */
6876                 tsx_ctrl = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
6877                 if (tsx_ctrl)
6878                         tsx_ctrl->mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6879         }
6880
6881         err = alloc_loaded_vmcs(&vmx->vmcs01);
6882         if (err < 0)
6883                 goto free_pml;
6884
6885         /* The MSR bitmap starts with all ones */
6886         bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6887         bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6888
6889         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
6890 #ifdef CONFIG_X86_64
6891         vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
6892         vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
6893         vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6894 #endif
6895         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6896         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6897         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6898         if (kvm_cstate_in_guest(vcpu->kvm)) {
6899                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
6900                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6901                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6902                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6903         }
6904
6905         vmx->loaded_vmcs = &vmx->vmcs01;
6906
6907         if (cpu_need_virtualize_apic_accesses(vcpu)) {
6908                 err = alloc_apic_access_page(vcpu->kvm);
6909                 if (err)
6910                         goto free_vmcs;
6911         }
6912
6913         if (enable_ept && !enable_unrestricted_guest) {
6914                 err = init_rmode_identity_map(vcpu->kvm);
6915                 if (err)
6916                         goto free_vmcs;
6917         }
6918
6919         return 0;
6920
6921 free_vmcs:
6922         free_loaded_vmcs(vmx->loaded_vmcs);
6923 free_pml:
6924         vmx_destroy_pml_buffer(vmx);
6925 free_vpid:
6926         free_vpid(vmx->vpid);
6927         return err;
6928 }
6929
6930 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6931 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6932
6933 static int vmx_vm_init(struct kvm *kvm)
6934 {
6935         if (!ple_gap)
6936                 kvm->arch.pause_in_guest = true;
6937
6938         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6939                 switch (l1tf_mitigation) {
6940                 case L1TF_MITIGATION_OFF:
6941                 case L1TF_MITIGATION_FLUSH_NOWARN:
6942                         /* 'I explicitly don't care' is set */
6943                         break;
6944                 case L1TF_MITIGATION_FLUSH:
6945                 case L1TF_MITIGATION_FLUSH_NOSMT:
6946                 case L1TF_MITIGATION_FULL:
6947                         /*
6948                          * Warn upon starting the first VM in a potentially
6949                          * insecure environment.
6950                          */
6951                         if (sched_smt_active())
6952                                 pr_warn_once(L1TF_MSG_SMT);
6953                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6954                                 pr_warn_once(L1TF_MSG_L1D);
6955                         break;
6956                 case L1TF_MITIGATION_FULL_FORCE:
6957                         /* Flush is enforced */
6958                         break;
6959                 }
6960         }
6961         return 0;
6962 }
6963
6964 static int __init vmx_check_processor_compat(void)
6965 {
6966         struct vmcs_config vmcs_conf;
6967         struct vmx_capability vmx_cap;
6968
6969         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6970             !this_cpu_has(X86_FEATURE_VMX)) {
6971                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6972                 return -EIO;
6973         }
6974
6975         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6976                 return -EIO;
6977         if (nested)
6978                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6979         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6980                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6981                                 smp_processor_id());
6982                 return -EIO;
6983         }
6984         return 0;
6985 }
6986
6987 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6988 {
6989         u8 cache;
6990         u64 ipat = 0;
6991
6992         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6993          * memory aliases with conflicting memory types and sometimes MCEs.
6994          * We have to be careful as to what are honored and when.
6995          *
6996          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
6997          * UC.  The effective memory type is UC or WC depending on guest PAT.
6998          * This was historically the source of MCEs and we want to be
6999          * conservative.
7000          *
7001          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
7002          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
7003          * EPT memory type is set to WB.  The effective memory type is forced
7004          * WB.
7005          *
7006          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
7007          * EPT memory type is used to emulate guest CD/MTRR.
7008          */
7009
7010         if (is_mmio) {
7011                 cache = MTRR_TYPE_UNCACHABLE;
7012                 goto exit;
7013         }
7014
7015         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
7016                 ipat = VMX_EPT_IPAT_BIT;
7017                 cache = MTRR_TYPE_WRBACK;
7018                 goto exit;
7019         }
7020
7021         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
7022                 ipat = VMX_EPT_IPAT_BIT;
7023                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
7024                         cache = MTRR_TYPE_WRBACK;
7025                 else
7026                         cache = MTRR_TYPE_UNCACHABLE;
7027                 goto exit;
7028         }
7029
7030         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
7031
7032 exit:
7033         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
7034 }
7035
7036 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx, u32 new_ctl)
7037 {
7038         /*
7039          * These bits in the secondary execution controls field
7040          * are dynamic, the others are mostly based on the hypervisor
7041          * architecture and the guest's CPUID.  Do not touch the
7042          * dynamic bits.
7043          */
7044         u32 mask =
7045                 SECONDARY_EXEC_SHADOW_VMCS |
7046                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7047                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7048                 SECONDARY_EXEC_DESC;
7049
7050         u32 cur_ctl = secondary_exec_controls_get(vmx);
7051
7052         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7053 }
7054
7055 /*
7056  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7057  * (indicating "allowed-1") if they are supported in the guest's CPUID.
7058  */
7059 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7060 {
7061         struct vcpu_vmx *vmx = to_vmx(vcpu);
7062         struct kvm_cpuid_entry2 *entry;
7063
7064         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7065         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7066
7067 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
7068         if (entry && (entry->_reg & (_cpuid_mask)))                     \
7069                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
7070 } while (0)
7071
7072         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7073         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
7074         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
7075         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
7076         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
7077         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
7078         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
7079         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
7080         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
7081         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
7082         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7083         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
7084         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
7085         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
7086         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
7087
7088         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7089         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
7090         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
7091         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
7092         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
7093         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
7094         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
7095
7096 #undef cr4_fixed1_update
7097 }
7098
7099 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7100 {
7101         struct vcpu_vmx *vmx = to_vmx(vcpu);
7102
7103         if (kvm_mpx_supported()) {
7104                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7105
7106                 if (mpx_enabled) {
7107                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7108                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7109                 } else {
7110                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7111                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7112                 }
7113         }
7114 }
7115
7116 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7117 {
7118         struct vcpu_vmx *vmx = to_vmx(vcpu);
7119         struct kvm_cpuid_entry2 *best = NULL;
7120         int i;
7121
7122         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7123                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7124                 if (!best)
7125                         return;
7126                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7127                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7128                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7129                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7130         }
7131
7132         /* Get the number of configurable Address Ranges for filtering */
7133         vmx->pt_desc.num_address_ranges = intel_pt_validate_cap(vmx->pt_desc.caps,
7134                                                 PT_CAP_num_address_ranges);
7135
7136         /* Initialize and clear the no dependency bits */
7137         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7138                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC |
7139                         RTIT_CTL_BRANCH_EN);
7140
7141         /*
7142          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7143          * will inject an #GP
7144          */
7145         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7146                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7147
7148         /*
7149          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7150          * PSBFreq can be set
7151          */
7152         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7153                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7154                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7155
7156         /*
7157          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn and MTCFreq can be set
7158          */
7159         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7160                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7161                                               RTIT_CTL_MTC_RANGE);
7162
7163         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7164         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7165                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7166                                                         RTIT_CTL_PTW_EN);
7167
7168         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7169         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7170                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7171
7172         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7173         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7174                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7175
7176         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabricEn can be set */
7177         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7178                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7179
7180         /* unmask address range configure area */
7181         for (i = 0; i < vmx->pt_desc.num_address_ranges; i++)
7182                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7183 }
7184
7185 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7186 {
7187         struct vcpu_vmx *vmx = to_vmx(vcpu);
7188
7189         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7190         vcpu->arch.xsaves_enabled = false;
7191
7192         vmx_setup_uret_msrs(vmx);
7193
7194         if (cpu_has_secondary_exec_ctrls())
7195                 vmcs_set_secondary_exec_control(vmx,
7196                                                 vmx_secondary_exec_control(vmx));
7197
7198         if (nested_vmx_allowed(vcpu))
7199                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7200                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7201                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7202         else
7203                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7204                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7205                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7206
7207         if (nested_vmx_allowed(vcpu)) {
7208                 nested_vmx_cr_fixed1_bits_update(vcpu);
7209                 nested_vmx_entry_exit_ctls_update(vcpu);
7210         }
7211
7212         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7213                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7214                 update_intel_pt_cfg(vcpu);
7215
7216         if (boot_cpu_has(X86_FEATURE_RTM)) {
7217                 struct vmx_uret_msr *msr;
7218                 msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
7219                 if (msr) {
7220                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7221                         vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7222                 }
7223         }
7224
7225         set_cr4_guest_host_mask(vmx);
7226
7227         vmx_write_encls_bitmap(vcpu, NULL);
7228         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX))
7229                 vmx->msr_ia32_feature_control_valid_bits |= FEAT_CTL_SGX_ENABLED;
7230         else
7231                 vmx->msr_ia32_feature_control_valid_bits &= ~FEAT_CTL_SGX_ENABLED;
7232
7233         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
7234                 vmx->msr_ia32_feature_control_valid_bits |=
7235                         FEAT_CTL_SGX_LC_ENABLED;
7236         else
7237                 vmx->msr_ia32_feature_control_valid_bits &=
7238                         ~FEAT_CTL_SGX_LC_ENABLED;
7239
7240         /* Refresh #PF interception to account for MAXPHYADDR changes. */
7241         vmx_update_exception_bitmap(vcpu);
7242 }
7243
7244 static __init void vmx_set_cpu_caps(void)
7245 {
7246         kvm_set_cpu_caps();
7247
7248         /* CPUID 0x1 */
7249         if (nested)
7250                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7251
7252         /* CPUID 0x7 */
7253         if (kvm_mpx_supported())
7254                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7255         if (!cpu_has_vmx_invpcid())
7256                 kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
7257         if (vmx_pt_mode_is_host_guest())
7258                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7259
7260         if (!enable_sgx) {
7261                 kvm_cpu_cap_clear(X86_FEATURE_SGX);
7262                 kvm_cpu_cap_clear(X86_FEATURE_SGX_LC);
7263                 kvm_cpu_cap_clear(X86_FEATURE_SGX1);
7264                 kvm_cpu_cap_clear(X86_FEATURE_SGX2);
7265         }
7266
7267         if (vmx_umip_emulated())
7268                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7269
7270         /* CPUID 0xD.1 */
7271         supported_xss = 0;
7272         if (!cpu_has_vmx_xsaves())
7273                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7274
7275         /* CPUID 0x80000001 and 0x7 (RDPID) */
7276         if (!cpu_has_vmx_rdtscp()) {
7277                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7278                 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
7279         }
7280
7281         if (cpu_has_vmx_waitpkg())
7282                 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7283 }
7284
7285 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7286 {
7287         to_vmx(vcpu)->req_immediate_exit = true;
7288 }
7289
7290 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7291                                   struct x86_instruction_info *info)
7292 {
7293         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7294         unsigned short port;
7295         bool intercept;
7296         int size;
7297
7298         if (info->intercept == x86_intercept_in ||
7299             info->intercept == x86_intercept_ins) {
7300                 port = info->src_val;
7301                 size = info->dst_bytes;
7302         } else {
7303                 port = info->dst_val;
7304                 size = info->src_bytes;
7305         }
7306
7307         /*
7308          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7309          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7310          * control.
7311          *
7312          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7313          */
7314         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7315                 intercept = nested_cpu_has(vmcs12,
7316                                            CPU_BASED_UNCOND_IO_EXITING);
7317         else
7318                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7319
7320         /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7321         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7322 }
7323
7324 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7325                                struct x86_instruction_info *info,
7326                                enum x86_intercept_stage stage,
7327                                struct x86_exception *exception)
7328 {
7329         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7330
7331         switch (info->intercept) {
7332         /*
7333          * RDPID causes #UD if disabled through secondary execution controls.
7334          * Because it is marked as EmulateOnUD, we need to intercept it here.
7335          * Note, RDPID is hidden behind ENABLE_RDTSCP.
7336          */
7337         case x86_intercept_rdpid:
7338                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) {
7339                         exception->vector = UD_VECTOR;
7340                         exception->error_code_valid = false;
7341                         return X86EMUL_PROPAGATE_FAULT;
7342                 }
7343                 break;
7344
7345         case x86_intercept_in:
7346         case x86_intercept_ins:
7347         case x86_intercept_out:
7348         case x86_intercept_outs:
7349                 return vmx_check_intercept_io(vcpu, info);
7350
7351         case x86_intercept_lgdt:
7352         case x86_intercept_lidt:
7353         case x86_intercept_lldt:
7354         case x86_intercept_ltr:
7355         case x86_intercept_sgdt:
7356         case x86_intercept_sidt:
7357         case x86_intercept_sldt:
7358         case x86_intercept_str:
7359                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7360                         return X86EMUL_CONTINUE;
7361
7362                 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7363                 break;
7364
7365         /* TODO: check more intercepts... */
7366         default:
7367                 break;
7368         }
7369
7370         return X86EMUL_UNHANDLEABLE;
7371 }
7372
7373 #ifdef CONFIG_X86_64
7374 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7375 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7376                                   u64 divisor, u64 *result)
7377 {
7378         u64 low = a << shift, high = a >> (64 - shift);
7379
7380         /* To avoid the overflow on divq */
7381         if (high >= divisor)
7382                 return 1;
7383
7384         /* Low hold the result, high hold rem which is discarded */
7385         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7386             "rm" (divisor), "0" (low), "1" (high));
7387         *result = low;
7388
7389         return 0;
7390 }
7391
7392 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7393                             bool *expired)
7394 {
7395         struct vcpu_vmx *vmx;
7396         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7397         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7398
7399         vmx = to_vmx(vcpu);
7400         tscl = rdtsc();
7401         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7402         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7403         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7404                                                     ktimer->timer_advance_ns);
7405
7406         if (delta_tsc > lapic_timer_advance_cycles)
7407                 delta_tsc -= lapic_timer_advance_cycles;
7408         else
7409                 delta_tsc = 0;
7410
7411         /* Convert to host delta tsc if tsc scaling is enabled */
7412         if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7413             delta_tsc && u64_shl_div_u64(delta_tsc,
7414                                 kvm_tsc_scaling_ratio_frac_bits,
7415                                 vcpu->arch.l1_tsc_scaling_ratio, &delta_tsc))
7416                 return -ERANGE;
7417
7418         /*
7419          * If the delta tsc can't fit in the 32 bit after the multi shift,
7420          * we can't use the preemption timer.
7421          * It's possible that it fits on later vmentries, but checking
7422          * on every vmentry is costly so we just use an hrtimer.
7423          */
7424         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7425                 return -ERANGE;
7426
7427         vmx->hv_deadline_tsc = tscl + delta_tsc;
7428         *expired = !delta_tsc;
7429         return 0;
7430 }
7431
7432 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7433 {
7434         to_vmx(vcpu)->hv_deadline_tsc = -1;
7435 }
7436 #endif
7437
7438 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7439 {
7440         if (!kvm_pause_in_guest(vcpu->kvm))
7441                 shrink_ple_window(vcpu);
7442 }
7443
7444 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu)
7445 {
7446         struct vcpu_vmx *vmx = to_vmx(vcpu);
7447
7448         if (is_guest_mode(vcpu)) {
7449                 vmx->nested.update_vmcs01_cpu_dirty_logging = true;
7450                 return;
7451         }
7452
7453         /*
7454          * Note, cpu_dirty_logging_count can be changed concurrent with this
7455          * code, but in that case another update request will be made and so
7456          * the guest will never run with a stale PML value.
7457          */
7458         if (vcpu->kvm->arch.cpu_dirty_logging_count)
7459                 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7460         else
7461                 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7462 }
7463
7464 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7465 {
7466         if (pi_pre_block(vcpu))
7467                 return 1;
7468
7469         if (kvm_lapic_hv_timer_in_use(vcpu))
7470                 kvm_lapic_switch_to_sw_timer(vcpu);
7471
7472         return 0;
7473 }
7474
7475 static void vmx_post_block(struct kvm_vcpu *vcpu)
7476 {
7477         if (kvm_x86_ops.set_hv_timer)
7478                 kvm_lapic_switch_to_hv_timer(vcpu);
7479
7480         pi_post_block(vcpu);
7481 }
7482
7483 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7484 {
7485         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7486                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7487                         FEAT_CTL_LMCE_ENABLED;
7488         else
7489                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7490                         ~FEAT_CTL_LMCE_ENABLED;
7491 }
7492
7493 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7494 {
7495         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7496         if (to_vmx(vcpu)->nested.nested_run_pending)
7497                 return -EBUSY;
7498         return !is_smm(vcpu);
7499 }
7500
7501 static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7502 {
7503         struct vcpu_vmx *vmx = to_vmx(vcpu);
7504
7505         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7506         if (vmx->nested.smm.guest_mode)
7507                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7508
7509         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7510         vmx->nested.vmxon = false;
7511         vmx_clear_hlt(vcpu);
7512         return 0;
7513 }
7514
7515 static int vmx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7516 {
7517         struct vcpu_vmx *vmx = to_vmx(vcpu);
7518         int ret;
7519
7520         if (vmx->nested.smm.vmxon) {
7521                 vmx->nested.vmxon = true;
7522                 vmx->nested.smm.vmxon = false;
7523         }
7524
7525         if (vmx->nested.smm.guest_mode) {
7526                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7527                 if (ret)
7528                         return ret;
7529
7530                 vmx->nested.smm.guest_mode = false;
7531         }
7532         return 0;
7533 }
7534
7535 static void vmx_enable_smi_window(struct kvm_vcpu *vcpu)
7536 {
7537         /* RSM will cause a vmexit anyway.  */
7538 }
7539
7540 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7541 {
7542         return to_vmx(vcpu)->nested.vmxon && !is_guest_mode(vcpu);
7543 }
7544
7545 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7546 {
7547         if (is_guest_mode(vcpu)) {
7548                 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7549
7550                 if (hrtimer_try_to_cancel(timer) == 1)
7551                         hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7552         }
7553 }
7554
7555 static void hardware_unsetup(void)
7556 {
7557         kvm_set_posted_intr_wakeup_handler(NULL);
7558
7559         if (nested)
7560                 nested_vmx_hardware_unsetup();
7561
7562         free_kvm_area();
7563 }
7564
7565 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7566 {
7567         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7568                           BIT(APICV_INHIBIT_REASON_HYPERV) |
7569                           BIT(APICV_INHIBIT_REASON_BLOCKIRQ);
7570
7571         return supported & BIT(bit);
7572 }
7573
7574 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7575         .name = "kvm_intel",
7576
7577         .hardware_unsetup = hardware_unsetup,
7578
7579         .hardware_enable = hardware_enable,
7580         .hardware_disable = hardware_disable,
7581         .cpu_has_accelerated_tpr = report_flexpriority,
7582         .has_emulated_msr = vmx_has_emulated_msr,
7583
7584         .vm_size = sizeof(struct kvm_vmx),
7585         .vm_init = vmx_vm_init,
7586
7587         .vcpu_create = vmx_create_vcpu,
7588         .vcpu_free = vmx_free_vcpu,
7589         .vcpu_reset = vmx_vcpu_reset,
7590
7591         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7592         .vcpu_load = vmx_vcpu_load,
7593         .vcpu_put = vmx_vcpu_put,
7594
7595         .update_exception_bitmap = vmx_update_exception_bitmap,
7596         .get_msr_feature = vmx_get_msr_feature,
7597         .get_msr = vmx_get_msr,
7598         .set_msr = vmx_set_msr,
7599         .get_segment_base = vmx_get_segment_base,
7600         .get_segment = vmx_get_segment,
7601         .set_segment = vmx_set_segment,
7602         .get_cpl = vmx_get_cpl,
7603         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7604         .set_cr0 = vmx_set_cr0,
7605         .is_valid_cr4 = vmx_is_valid_cr4,
7606         .set_cr4 = vmx_set_cr4,
7607         .set_efer = vmx_set_efer,
7608         .get_idt = vmx_get_idt,
7609         .set_idt = vmx_set_idt,
7610         .get_gdt = vmx_get_gdt,
7611         .set_gdt = vmx_set_gdt,
7612         .set_dr7 = vmx_set_dr7,
7613         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7614         .cache_reg = vmx_cache_reg,
7615         .get_rflags = vmx_get_rflags,
7616         .set_rflags = vmx_set_rflags,
7617
7618         .tlb_flush_all = vmx_flush_tlb_all,
7619         .tlb_flush_current = vmx_flush_tlb_current,
7620         .tlb_flush_gva = vmx_flush_tlb_gva,
7621         .tlb_flush_guest = vmx_flush_tlb_guest,
7622
7623         .run = vmx_vcpu_run,
7624         .handle_exit = vmx_handle_exit,
7625         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7626         .update_emulated_instruction = vmx_update_emulated_instruction,
7627         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7628         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7629         .patch_hypercall = vmx_patch_hypercall,
7630         .set_irq = vmx_inject_irq,
7631         .set_nmi = vmx_inject_nmi,
7632         .queue_exception = vmx_queue_exception,
7633         .cancel_injection = vmx_cancel_injection,
7634         .interrupt_allowed = vmx_interrupt_allowed,
7635         .nmi_allowed = vmx_nmi_allowed,
7636         .get_nmi_mask = vmx_get_nmi_mask,
7637         .set_nmi_mask = vmx_set_nmi_mask,
7638         .enable_nmi_window = vmx_enable_nmi_window,
7639         .enable_irq_window = vmx_enable_irq_window,
7640         .update_cr8_intercept = vmx_update_cr8_intercept,
7641         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7642         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7643         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7644         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7645         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7646         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7647         .hwapic_irr_update = vmx_hwapic_irr_update,
7648         .hwapic_isr_update = vmx_hwapic_isr_update,
7649         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7650         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7651         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7652         .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
7653
7654         .set_tss_addr = vmx_set_tss_addr,
7655         .set_identity_map_addr = vmx_set_identity_map_addr,
7656         .get_mt_mask = vmx_get_mt_mask,
7657
7658         .get_exit_info = vmx_get_exit_info,
7659
7660         .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7661
7662         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7663
7664         .get_l2_tsc_offset = vmx_get_l2_tsc_offset,
7665         .get_l2_tsc_multiplier = vmx_get_l2_tsc_multiplier,
7666         .write_tsc_offset = vmx_write_tsc_offset,
7667         .write_tsc_multiplier = vmx_write_tsc_multiplier,
7668
7669         .load_mmu_pgd = vmx_load_mmu_pgd,
7670
7671         .check_intercept = vmx_check_intercept,
7672         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7673
7674         .request_immediate_exit = vmx_request_immediate_exit,
7675
7676         .sched_in = vmx_sched_in,
7677
7678         .cpu_dirty_log_size = PML_ENTITY_NUM,
7679         .update_cpu_dirty_logging = vmx_update_cpu_dirty_logging,
7680
7681         .pre_block = vmx_pre_block,
7682         .post_block = vmx_post_block,
7683
7684         .pmu_ops = &intel_pmu_ops,
7685         .nested_ops = &vmx_nested_ops,
7686
7687         .update_pi_irte = pi_update_irte,
7688         .start_assignment = vmx_pi_start_assignment,
7689
7690 #ifdef CONFIG_X86_64
7691         .set_hv_timer = vmx_set_hv_timer,
7692         .cancel_hv_timer = vmx_cancel_hv_timer,
7693 #endif
7694
7695         .setup_mce = vmx_setup_mce,
7696
7697         .smi_allowed = vmx_smi_allowed,
7698         .enter_smm = vmx_enter_smm,
7699         .leave_smm = vmx_leave_smm,
7700         .enable_smi_window = vmx_enable_smi_window,
7701
7702         .can_emulate_instruction = vmx_can_emulate_instruction,
7703         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7704         .migrate_timers = vmx_migrate_timers,
7705
7706         .msr_filter_changed = vmx_msr_filter_changed,
7707         .complete_emulated_msr = kvm_complete_insn_gp,
7708
7709         .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector,
7710 };
7711
7712 static __init void vmx_setup_user_return_msrs(void)
7713 {
7714
7715         /*
7716          * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
7717          * will emulate SYSCALL in legacy mode if the vendor string in guest
7718          * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
7719          * support this emulation, MSR_STAR is included in the list for i386,
7720          * but is never loaded into hardware.  MSR_CSTAR is also never loaded
7721          * into hardware and is here purely for emulation purposes.
7722          */
7723         const u32 vmx_uret_msrs_list[] = {
7724         #ifdef CONFIG_X86_64
7725                 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
7726         #endif
7727                 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
7728                 MSR_IA32_TSX_CTRL,
7729         };
7730         int i;
7731
7732         BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
7733
7734         for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
7735                 kvm_add_user_return_msr(vmx_uret_msrs_list[i]);
7736 }
7737
7738 static __init int hardware_setup(void)
7739 {
7740         unsigned long host_bndcfgs;
7741         struct desc_ptr dt;
7742         int r, ept_lpage_level;
7743
7744         store_idt(&dt);
7745         host_idt_base = dt.address;
7746
7747         vmx_setup_user_return_msrs();
7748
7749         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7750                 return -EIO;
7751
7752         if (boot_cpu_has(X86_FEATURE_NX))
7753                 kvm_enable_efer_bits(EFER_NX);
7754
7755         if (boot_cpu_has(X86_FEATURE_MPX)) {
7756                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7757                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7758         }
7759
7760         if (!cpu_has_vmx_mpx())
7761                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7762                                     XFEATURE_MASK_BNDCSR);
7763
7764         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7765             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7766                 enable_vpid = 0;
7767
7768         if (!cpu_has_vmx_ept() ||
7769             !cpu_has_vmx_ept_4levels() ||
7770             !cpu_has_vmx_ept_mt_wb() ||
7771             !cpu_has_vmx_invept_global())
7772                 enable_ept = 0;
7773
7774         /* NX support is required for shadow paging. */
7775         if (!enable_ept && !boot_cpu_has(X86_FEATURE_NX)) {
7776                 pr_err_ratelimited("kvm: NX (Execute Disable) not supported\n");
7777                 return -EOPNOTSUPP;
7778         }
7779
7780         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7781                 enable_ept_ad_bits = 0;
7782
7783         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7784                 enable_unrestricted_guest = 0;
7785
7786         if (!cpu_has_vmx_flexpriority())
7787                 flexpriority_enabled = 0;
7788
7789         if (!cpu_has_virtual_nmis())
7790                 enable_vnmi = 0;
7791
7792         /*
7793          * set_apic_access_page_addr() is used to reload apic access
7794          * page upon invalidation.  No need to do anything if not
7795          * using the APIC_ACCESS_ADDR VMCS field.
7796          */
7797         if (!flexpriority_enabled)
7798                 vmx_x86_ops.set_apic_access_page_addr = NULL;
7799
7800         if (!cpu_has_vmx_tpr_shadow())
7801                 vmx_x86_ops.update_cr8_intercept = NULL;
7802
7803 #if IS_ENABLED(CONFIG_HYPERV)
7804         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7805             && enable_ept) {
7806                 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7807                 vmx_x86_ops.tlb_remote_flush_with_range =
7808                                 hv_remote_flush_tlb_with_range;
7809         }
7810 #endif
7811
7812         if (!cpu_has_vmx_ple()) {
7813                 ple_gap = 0;
7814                 ple_window = 0;
7815                 ple_window_grow = 0;
7816                 ple_window_max = 0;
7817                 ple_window_shrink = 0;
7818         }
7819
7820         if (!cpu_has_vmx_apicv()) {
7821                 enable_apicv = 0;
7822                 vmx_x86_ops.sync_pir_to_irr = NULL;
7823         }
7824
7825         if (cpu_has_vmx_tsc_scaling()) {
7826                 kvm_has_tsc_control = true;
7827                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7828                 kvm_tsc_scaling_ratio_frac_bits = 48;
7829         }
7830
7831         kvm_has_bus_lock_exit = cpu_has_vmx_bus_lock_detection();
7832
7833         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7834
7835         if (enable_ept)
7836                 kvm_mmu_set_ept_masks(enable_ept_ad_bits,
7837                                       cpu_has_vmx_ept_execute_only());
7838
7839         if (!enable_ept)
7840                 ept_lpage_level = 0;
7841         else if (cpu_has_vmx_ept_1g_page())
7842                 ept_lpage_level = PG_LEVEL_1G;
7843         else if (cpu_has_vmx_ept_2m_page())
7844                 ept_lpage_level = PG_LEVEL_2M;
7845         else
7846                 ept_lpage_level = PG_LEVEL_4K;
7847         kvm_configure_mmu(enable_ept, 0, vmx_get_max_tdp_level(),
7848                           ept_lpage_level);
7849
7850         /*
7851          * Only enable PML when hardware supports PML feature, and both EPT
7852          * and EPT A/D bit features are enabled -- PML depends on them to work.
7853          */
7854         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7855                 enable_pml = 0;
7856
7857         if (!enable_pml)
7858                 vmx_x86_ops.cpu_dirty_log_size = 0;
7859
7860         if (!cpu_has_vmx_preemption_timer())
7861                 enable_preemption_timer = false;
7862
7863         if (enable_preemption_timer) {
7864                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7865                 u64 vmx_msr;
7866
7867                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7868                 cpu_preemption_timer_multi =
7869                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7870
7871                 if (tsc_khz)
7872                         use_timer_freq = (u64)tsc_khz * 1000;
7873                 use_timer_freq >>= cpu_preemption_timer_multi;
7874
7875                 /*
7876                  * KVM "disables" the preemption timer by setting it to its max
7877                  * value.  Don't use the timer if it might cause spurious exits
7878                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7879                  */
7880                 if (use_timer_freq > 0xffffffffu / 10)
7881                         enable_preemption_timer = false;
7882         }
7883
7884         if (!enable_preemption_timer) {
7885                 vmx_x86_ops.set_hv_timer = NULL;
7886                 vmx_x86_ops.cancel_hv_timer = NULL;
7887                 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
7888         }
7889
7890         kvm_mce_cap_supported |= MCG_LMCE_P;
7891
7892         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7893                 return -EINVAL;
7894         if (!enable_ept || !cpu_has_vmx_intel_pt())
7895                 pt_mode = PT_MODE_SYSTEM;
7896
7897         setup_default_sgx_lepubkeyhash();
7898
7899         if (nested) {
7900                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7901                                            vmx_capability.ept);
7902
7903                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7904                 if (r)
7905                         return r;
7906         }
7907
7908         vmx_set_cpu_caps();
7909
7910         r = alloc_kvm_area();
7911         if (r)
7912                 nested_vmx_hardware_unsetup();
7913
7914         kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler);
7915
7916         return r;
7917 }
7918
7919 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
7920         .cpu_has_kvm_support = cpu_has_kvm_support,
7921         .disabled_by_bios = vmx_disabled_by_bios,
7922         .check_processor_compatibility = vmx_check_processor_compat,
7923         .hardware_setup = hardware_setup,
7924
7925         .runtime_ops = &vmx_x86_ops,
7926 };
7927
7928 static void vmx_cleanup_l1d_flush(void)
7929 {
7930         if (vmx_l1d_flush_pages) {
7931                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7932                 vmx_l1d_flush_pages = NULL;
7933         }
7934         /* Restore state so sysfs ignores VMX */
7935         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7936 }
7937
7938 static void vmx_exit(void)
7939 {
7940 #ifdef CONFIG_KEXEC_CORE
7941         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7942         synchronize_rcu();
7943 #endif
7944
7945         kvm_exit();
7946
7947 #if IS_ENABLED(CONFIG_HYPERV)
7948         if (static_branch_unlikely(&enable_evmcs)) {
7949                 int cpu;
7950                 struct hv_vp_assist_page *vp_ap;
7951                 /*
7952                  * Reset everything to support using non-enlightened VMCS
7953                  * access later (e.g. when we reload the module with
7954                  * enlightened_vmcs=0)
7955                  */
7956                 for_each_online_cpu(cpu) {
7957                         vp_ap = hv_get_vp_assist_page(cpu);
7958
7959                         if (!vp_ap)
7960                                 continue;
7961
7962                         vp_ap->nested_control.features.directhypercall = 0;
7963                         vp_ap->current_nested_vmcs = 0;
7964                         vp_ap->enlighten_vmentry = 0;
7965                 }
7966
7967                 static_branch_disable(&enable_evmcs);
7968         }
7969 #endif
7970         vmx_cleanup_l1d_flush();
7971
7972         allow_smaller_maxphyaddr = false;
7973 }
7974 module_exit(vmx_exit);
7975
7976 static int __init vmx_init(void)
7977 {
7978         int r, cpu;
7979
7980 #if IS_ENABLED(CONFIG_HYPERV)
7981         /*
7982          * Enlightened VMCS usage should be recommended and the host needs
7983          * to support eVMCS v1 or above. We can also disable eVMCS support
7984          * with module parameter.
7985          */
7986         if (enlightened_vmcs &&
7987             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7988             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7989             KVM_EVMCS_VERSION) {
7990                 int cpu;
7991
7992                 /* Check that we have assist pages on all online CPUs */
7993                 for_each_online_cpu(cpu) {
7994                         if (!hv_get_vp_assist_page(cpu)) {
7995                                 enlightened_vmcs = false;
7996                                 break;
7997                         }
7998                 }
7999
8000                 if (enlightened_vmcs) {
8001                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8002                         static_branch_enable(&enable_evmcs);
8003                 }
8004
8005                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8006                         vmx_x86_ops.enable_direct_tlbflush
8007                                 = hv_enable_direct_tlbflush;
8008
8009         } else {
8010                 enlightened_vmcs = false;
8011         }
8012 #endif
8013
8014         r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
8015                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8016         if (r)
8017                 return r;
8018
8019         /*
8020          * Must be called after kvm_init() so enable_ept is properly set
8021          * up. Hand the parameter mitigation value in which was stored in
8022          * the pre module init parser. If no parameter was given, it will
8023          * contain 'auto' which will be turned into the default 'cond'
8024          * mitigation mode.
8025          */
8026         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8027         if (r) {
8028                 vmx_exit();
8029                 return r;
8030         }
8031
8032         for_each_possible_cpu(cpu) {
8033                 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8034
8035                 pi_init_cpu(cpu);
8036         }
8037
8038 #ifdef CONFIG_KEXEC_CORE
8039         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8040                            crash_vmclear_local_loaded_vmcss);
8041 #endif
8042         vmx_check_vmcs12_offsets();
8043
8044         /*
8045          * Shadow paging doesn't have a (further) performance penalty
8046          * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it
8047          * by default
8048          */
8049         if (!enable_ept)
8050                 allow_smaller_maxphyaddr = true;
8051
8052         return 0;
8053 }
8054 module_init(vmx_init);