1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/highmem.h>
17 #include <linux/hrtimer.h>
18 #include <linux/kernel.h>
19 #include <linux/kvm_host.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/mod_devicetable.h>
24 #include <linux/objtool.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
30 #include <linux/entry-kvm.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/debugreg.h>
38 #include <asm/fpu/api.h>
39 #include <asm/idtentry.h>
41 #include <asm/irq_remapping.h>
42 #include <asm/kexec.h>
43 #include <asm/perf_event.h>
44 #include <asm/mmu_context.h>
45 #include <asm/mshyperv.h>
46 #include <asm/mwait.h>
47 #include <asm/spec-ctrl.h>
48 #include <asm/virtext.h>
51 #include "capabilities.h"
55 #include "kvm_onhyperv.h"
57 #include "kvm_cache_regs.h"
69 MODULE_AUTHOR("Qumranet");
70 MODULE_LICENSE("GPL");
73 static const struct x86_cpu_id vmx_cpu_id[] = {
74 X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
77 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
80 bool __read_mostly enable_vpid = 1;
81 module_param_named(vpid, enable_vpid, bool, 0444);
83 static bool __read_mostly enable_vnmi = 1;
84 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
86 bool __read_mostly flexpriority_enabled = 1;
87 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
89 bool __read_mostly enable_ept = 1;
90 module_param_named(ept, enable_ept, bool, S_IRUGO);
92 bool __read_mostly enable_unrestricted_guest = 1;
93 module_param_named(unrestricted_guest,
94 enable_unrestricted_guest, bool, S_IRUGO);
96 bool __read_mostly enable_ept_ad_bits = 1;
97 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
99 static bool __read_mostly emulate_invalid_guest_state = true;
100 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
102 static bool __read_mostly fasteoi = 1;
103 module_param(fasteoi, bool, S_IRUGO);
105 module_param(enable_apicv, bool, S_IRUGO);
108 * If nested=1, nested virtualization is supported, i.e., guests may use
109 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
110 * use VMX instructions.
112 static bool __read_mostly nested = 1;
113 module_param(nested, bool, S_IRUGO);
115 bool __read_mostly enable_pml = 1;
116 module_param_named(pml, enable_pml, bool, S_IRUGO);
118 static bool __read_mostly dump_invalid_vmcs = 0;
119 module_param(dump_invalid_vmcs, bool, 0644);
121 #define MSR_BITMAP_MODE_X2APIC 1
122 #define MSR_BITMAP_MODE_X2APIC_APICV 2
124 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
126 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
127 static int __read_mostly cpu_preemption_timer_multi;
128 static bool __read_mostly enable_preemption_timer = 1;
130 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
133 extern bool __read_mostly allow_smaller_maxphyaddr;
134 module_param(allow_smaller_maxphyaddr, bool, S_IRUGO);
136 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
137 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
138 #define KVM_VM_CR0_ALWAYS_ON \
139 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
141 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
142 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
143 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
145 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
147 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
148 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
149 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
150 RTIT_STATUS_BYTECNT))
153 * List of MSRs that can be directly passed to the guest.
154 * In addition to these x2apic and PT MSRs are handled specially.
156 static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = {
165 MSR_IA32_SYSENTER_CS,
166 MSR_IA32_SYSENTER_ESP,
167 MSR_IA32_SYSENTER_EIP,
169 MSR_CORE_C3_RESIDENCY,
170 MSR_CORE_C6_RESIDENCY,
171 MSR_CORE_C7_RESIDENCY,
175 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
176 * ple_gap: upper bound on the amount of time between two successive
177 * executions of PAUSE in a loop. Also indicate if ple enabled.
178 * According to test, this time is usually smaller than 128 cycles.
179 * ple_window: upper bound on the amount of time a guest is allowed to execute
180 * in a PAUSE loop. Tests indicate that most spinlocks are held for
181 * less than 2^12 cycles
182 * Time is measured based on a counter that runs at the same rate as the TSC,
183 * refer SDM volume 3b section 21.6.13 & 22.1.3.
185 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
186 module_param(ple_gap, uint, 0444);
188 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
189 module_param(ple_window, uint, 0444);
191 /* Default doubles per-vcpu window every exit. */
192 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
193 module_param(ple_window_grow, uint, 0444);
195 /* Default resets per-vcpu window every exit to ple_window. */
196 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
197 module_param(ple_window_shrink, uint, 0444);
199 /* Default is to compute the maximum so we can never overflow. */
200 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
201 module_param(ple_window_max, uint, 0444);
203 /* Default is SYSTEM mode, 1 for host-guest mode */
204 int __read_mostly pt_mode = PT_MODE_SYSTEM;
205 module_param(pt_mode, int, S_IRUGO);
207 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
208 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
209 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
211 /* Storage for pre module init parameter parsing */
212 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
214 static const struct {
217 } vmentry_l1d_param[] = {
218 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
219 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
220 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
221 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
222 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
223 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
226 #define L1D_CACHE_ORDER 4
227 static void *vmx_l1d_flush_pages;
229 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
234 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
235 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
240 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
244 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
247 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
248 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
249 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
254 /* If set to auto use the default l1tf mitigation method */
255 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
256 switch (l1tf_mitigation) {
257 case L1TF_MITIGATION_OFF:
258 l1tf = VMENTER_L1D_FLUSH_NEVER;
260 case L1TF_MITIGATION_FLUSH_NOWARN:
261 case L1TF_MITIGATION_FLUSH:
262 case L1TF_MITIGATION_FLUSH_NOSMT:
263 l1tf = VMENTER_L1D_FLUSH_COND;
265 case L1TF_MITIGATION_FULL:
266 case L1TF_MITIGATION_FULL_FORCE:
267 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
270 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
271 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
274 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
275 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
277 * This allocation for vmx_l1d_flush_pages is not tied to a VM
278 * lifetime and so should not be charged to a memcg.
280 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
283 vmx_l1d_flush_pages = page_address(page);
286 * Initialize each page with a different pattern in
287 * order to protect against KSM in the nested
288 * virtualization case.
290 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
291 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
296 l1tf_vmx_mitigation = l1tf;
298 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
299 static_branch_enable(&vmx_l1d_should_flush);
301 static_branch_disable(&vmx_l1d_should_flush);
303 if (l1tf == VMENTER_L1D_FLUSH_COND)
304 static_branch_enable(&vmx_l1d_flush_cond);
306 static_branch_disable(&vmx_l1d_flush_cond);
310 static int vmentry_l1d_flush_parse(const char *s)
315 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
316 if (vmentry_l1d_param[i].for_parse &&
317 sysfs_streq(s, vmentry_l1d_param[i].option))
324 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
328 l1tf = vmentry_l1d_flush_parse(s);
332 if (!boot_cpu_has(X86_BUG_L1TF))
336 * Has vmx_init() run already? If not then this is the pre init
337 * parameter parsing. In that case just store the value and let
338 * vmx_init() do the proper setup after enable_ept has been
341 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
342 vmentry_l1d_flush_param = l1tf;
346 mutex_lock(&vmx_l1d_flush_mutex);
347 ret = vmx_setup_l1d_flush(l1tf);
348 mutex_unlock(&vmx_l1d_flush_mutex);
352 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
354 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
355 return sprintf(s, "???\n");
357 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
360 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
361 .set = vmentry_l1d_flush_set,
362 .get = vmentry_l1d_flush_get,
364 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
366 static u32 vmx_segment_access_rights(struct kvm_segment *var);
368 void vmx_vmexit(void);
370 #define vmx_insn_failed(fmt...) \
373 pr_warn_ratelimited(fmt); \
376 asmlinkage void vmread_error(unsigned long field, bool fault)
379 kvm_spurious_fault();
381 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
384 noinline void vmwrite_error(unsigned long field, unsigned long value)
386 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
387 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
390 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
392 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
395 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
397 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
400 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
402 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
406 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
408 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
412 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
413 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
415 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
416 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
418 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
420 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
421 static DEFINE_SPINLOCK(vmx_vpid_lock);
423 struct vmcs_config vmcs_config;
424 struct vmx_capability vmx_capability;
426 #define VMX_SEGMENT_FIELD(seg) \
427 [VCPU_SREG_##seg] = { \
428 .selector = GUEST_##seg##_SELECTOR, \
429 .base = GUEST_##seg##_BASE, \
430 .limit = GUEST_##seg##_LIMIT, \
431 .ar_bytes = GUEST_##seg##_AR_BYTES, \
434 static const struct kvm_vmx_segment_field {
439 } kvm_vmx_segment_fields[] = {
440 VMX_SEGMENT_FIELD(CS),
441 VMX_SEGMENT_FIELD(DS),
442 VMX_SEGMENT_FIELD(ES),
443 VMX_SEGMENT_FIELD(FS),
444 VMX_SEGMENT_FIELD(GS),
445 VMX_SEGMENT_FIELD(SS),
446 VMX_SEGMENT_FIELD(TR),
447 VMX_SEGMENT_FIELD(LDTR),
450 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
452 vmx->segment_cache.bitmask = 0;
455 static unsigned long host_idt_base;
457 #if IS_ENABLED(CONFIG_HYPERV)
458 static bool __read_mostly enlightened_vmcs = true;
459 module_param(enlightened_vmcs, bool, 0444);
461 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
463 struct hv_enlightened_vmcs *evmcs;
464 struct hv_partition_assist_pg **p_hv_pa_pg =
465 &to_kvm_hv(vcpu->kvm)->hv_pa_pg;
467 * Synthetic VM-Exit is not enabled in current code and so All
468 * evmcs in singe VM shares same assist page.
471 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
476 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
478 evmcs->partition_assist_page =
480 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
481 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
486 #endif /* IS_ENABLED(CONFIG_HYPERV) */
489 * Comment's format: document - errata name - stepping - processor name.
491 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
493 static u32 vmx_preemption_cpu_tfms[] = {
494 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
496 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
497 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
498 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
500 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
502 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
503 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
505 * 320767.pdf - AAP86 - B1 -
506 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
509 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
511 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
513 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
515 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
516 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
517 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
519 /* Xeon E3-1220 V2 */
523 static inline bool cpu_has_broken_vmx_preemption_timer(void)
525 u32 eax = cpuid_eax(0x00000001), i;
527 /* Clear the reserved bits */
528 eax &= ~(0x3U << 14 | 0xfU << 28);
529 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
530 if (eax == vmx_preemption_cpu_tfms[i])
536 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
538 return flexpriority_enabled && lapic_in_kernel(vcpu);
541 static inline bool report_flexpriority(void)
543 return flexpriority_enabled;
546 static int possible_passthrough_msr_slot(u32 msr)
550 for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++)
551 if (vmx_possible_passthrough_msrs[i] == msr)
557 static bool is_valid_passthrough_msr(u32 msr)
562 case 0x800 ... 0x8ff:
563 /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */
565 case MSR_IA32_RTIT_STATUS:
566 case MSR_IA32_RTIT_OUTPUT_BASE:
567 case MSR_IA32_RTIT_OUTPUT_MASK:
568 case MSR_IA32_RTIT_CR3_MATCH:
569 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
570 /* PT MSRs. These are handled in pt_update_intercept_for_msr() */
573 case MSR_LBR_INFO_0 ... MSR_LBR_INFO_0 + 31:
574 case MSR_LBR_NHM_FROM ... MSR_LBR_NHM_FROM + 31:
575 case MSR_LBR_NHM_TO ... MSR_LBR_NHM_TO + 31:
576 case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8:
577 case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8:
578 /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */
582 r = possible_passthrough_msr_slot(msr) != -ENOENT;
584 WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr);
589 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
593 i = kvm_find_user_return_msr(msr);
595 return &vmx->guest_uret_msrs[i];
599 static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx,
600 struct vmx_uret_msr *msr, u64 data)
602 unsigned int slot = msr - vmx->guest_uret_msrs;
605 if (msr->load_into_hardware) {
607 ret = kvm_set_user_return_msr(slot, data, msr->mask);
615 #ifdef CONFIG_KEXEC_CORE
616 static void crash_vmclear_local_loaded_vmcss(void)
618 int cpu = raw_smp_processor_id();
619 struct loaded_vmcs *v;
621 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
622 loaded_vmcss_on_cpu_link)
625 #endif /* CONFIG_KEXEC_CORE */
627 static void __loaded_vmcs_clear(void *arg)
629 struct loaded_vmcs *loaded_vmcs = arg;
630 int cpu = raw_smp_processor_id();
632 if (loaded_vmcs->cpu != cpu)
633 return; /* vcpu migration can race with cpu offline */
634 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
635 per_cpu(current_vmcs, cpu) = NULL;
637 vmcs_clear(loaded_vmcs->vmcs);
638 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
639 vmcs_clear(loaded_vmcs->shadow_vmcs);
641 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
644 * Ensure all writes to loaded_vmcs, including deleting it from its
645 * current percpu list, complete before setting loaded_vmcs->vcpu to
646 * -1, otherwise a different cpu can see vcpu == -1 first and add
647 * loaded_vmcs to its percpu list before it's deleted from this cpu's
648 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
652 loaded_vmcs->cpu = -1;
653 loaded_vmcs->launched = 0;
656 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
658 int cpu = loaded_vmcs->cpu;
661 smp_call_function_single(cpu,
662 __loaded_vmcs_clear, loaded_vmcs, 1);
665 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
669 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
671 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
672 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
673 vmx->segment_cache.bitmask = 0;
675 ret = vmx->segment_cache.bitmask & mask;
676 vmx->segment_cache.bitmask |= mask;
680 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
682 u16 *p = &vmx->segment_cache.seg[seg].selector;
684 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
685 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
689 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
691 ulong *p = &vmx->segment_cache.seg[seg].base;
693 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
694 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
698 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
700 u32 *p = &vmx->segment_cache.seg[seg].limit;
702 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
703 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
707 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
709 u32 *p = &vmx->segment_cache.seg[seg].ar;
711 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
712 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
716 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu)
720 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
721 (1u << DB_VECTOR) | (1u << AC_VECTOR);
723 * Guest access to VMware backdoor ports could legitimately
724 * trigger #GP because of TSS I/O permission bitmap.
725 * We intercept those #GP and allow access to them anyway
728 if (enable_vmware_backdoor)
729 eb |= (1u << GP_VECTOR);
730 if ((vcpu->guest_debug &
731 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
732 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
733 eb |= 1u << BP_VECTOR;
734 if (to_vmx(vcpu)->rmode.vm86_active)
736 if (!vmx_need_pf_intercept(vcpu))
737 eb &= ~(1u << PF_VECTOR);
739 /* When we are running a nested L2 guest and L1 specified for it a
740 * certain exception bitmap, we must trap the same exceptions and pass
741 * them to L1. When running L2, we will only handle the exceptions
742 * specified above if L1 did not want them.
744 if (is_guest_mode(vcpu))
745 eb |= get_vmcs12(vcpu)->exception_bitmap;
747 int mask = 0, match = 0;
749 if (enable_ept && (eb & (1u << PF_VECTOR))) {
751 * If EPT is enabled, #PF is currently only intercepted
752 * if MAXPHYADDR is smaller on the guest than on the
753 * host. In that case we only care about present,
754 * non-reserved faults. For vmcs02, however, PFEC_MASK
755 * and PFEC_MATCH are set in prepare_vmcs02_rare.
757 mask = PFERR_PRESENT_MASK | PFERR_RSVD_MASK;
758 match = PFERR_PRESENT_MASK;
760 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
761 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, match);
764 vmcs_write32(EXCEPTION_BITMAP, eb);
768 * Check if MSR is intercepted for currently loaded MSR bitmap.
770 static bool msr_write_intercepted(struct vcpu_vmx *vmx, u32 msr)
772 if (!(exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS))
775 return vmx_test_msr_bitmap_write(vmx->loaded_vmcs->msr_bitmap,
779 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
780 unsigned long entry, unsigned long exit)
782 vm_entry_controls_clearbit(vmx, entry);
783 vm_exit_controls_clearbit(vmx, exit);
786 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr)
790 for (i = 0; i < m->nr; ++i) {
791 if (m->val[i].index == msr)
797 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
800 struct msr_autoload *m = &vmx->msr_autoload;
804 if (cpu_has_load_ia32_efer()) {
805 clear_atomic_switch_msr_special(vmx,
806 VM_ENTRY_LOAD_IA32_EFER,
807 VM_EXIT_LOAD_IA32_EFER);
811 case MSR_CORE_PERF_GLOBAL_CTRL:
812 if (cpu_has_load_perf_global_ctrl()) {
813 clear_atomic_switch_msr_special(vmx,
814 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
815 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
820 i = vmx_find_loadstore_msr_slot(&m->guest, msr);
824 m->guest.val[i] = m->guest.val[m->guest.nr];
825 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
828 i = vmx_find_loadstore_msr_slot(&m->host, msr);
833 m->host.val[i] = m->host.val[m->host.nr];
834 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
837 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
838 unsigned long entry, unsigned long exit,
839 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
840 u64 guest_val, u64 host_val)
842 vmcs_write64(guest_val_vmcs, guest_val);
843 if (host_val_vmcs != HOST_IA32_EFER)
844 vmcs_write64(host_val_vmcs, host_val);
845 vm_entry_controls_setbit(vmx, entry);
846 vm_exit_controls_setbit(vmx, exit);
849 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
850 u64 guest_val, u64 host_val, bool entry_only)
853 struct msr_autoload *m = &vmx->msr_autoload;
857 if (cpu_has_load_ia32_efer()) {
858 add_atomic_switch_msr_special(vmx,
859 VM_ENTRY_LOAD_IA32_EFER,
860 VM_EXIT_LOAD_IA32_EFER,
863 guest_val, host_val);
867 case MSR_CORE_PERF_GLOBAL_CTRL:
868 if (cpu_has_load_perf_global_ctrl()) {
869 add_atomic_switch_msr_special(vmx,
870 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
871 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
872 GUEST_IA32_PERF_GLOBAL_CTRL,
873 HOST_IA32_PERF_GLOBAL_CTRL,
874 guest_val, host_val);
878 case MSR_IA32_PEBS_ENABLE:
879 /* PEBS needs a quiescent period after being disabled (to write
880 * a record). Disabling PEBS through VMX MSR swapping doesn't
881 * provide that period, so a CPU could write host's record into
884 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
887 i = vmx_find_loadstore_msr_slot(&m->guest, msr);
889 j = vmx_find_loadstore_msr_slot(&m->host, msr);
891 if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) ||
892 (j < 0 && m->host.nr == MAX_NR_LOADSTORE_MSRS)) {
893 printk_once(KERN_WARNING "Not enough msr switch entries. "
894 "Can't add msr %x\n", msr);
899 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
901 m->guest.val[i].index = msr;
902 m->guest.val[i].value = guest_val;
909 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
911 m->host.val[j].index = msr;
912 m->host.val[j].value = host_val;
915 static bool update_transition_efer(struct vcpu_vmx *vmx)
917 u64 guest_efer = vmx->vcpu.arch.efer;
921 /* Shadow paging assumes NX to be available. */
923 guest_efer |= EFER_NX;
926 * LMA and LME handled by hardware; SCE meaningless outside long mode.
928 ignore_bits |= EFER_SCE;
930 ignore_bits |= EFER_LMA | EFER_LME;
931 /* SCE is meaningful only in long mode on Intel */
932 if (guest_efer & EFER_LMA)
933 ignore_bits &= ~(u64)EFER_SCE;
937 * On EPT, we can't emulate NX, so we must switch EFER atomically.
938 * On CPUs that support "load IA32_EFER", always switch EFER
939 * atomically, since it's faster than switching it manually.
941 if (cpu_has_load_ia32_efer() ||
942 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
943 if (!(guest_efer & EFER_LMA))
944 guest_efer &= ~EFER_LME;
945 if (guest_efer != host_efer)
946 add_atomic_switch_msr(vmx, MSR_EFER,
947 guest_efer, host_efer, false);
949 clear_atomic_switch_msr(vmx, MSR_EFER);
953 i = kvm_find_user_return_msr(MSR_EFER);
957 clear_atomic_switch_msr(vmx, MSR_EFER);
959 guest_efer &= ~ignore_bits;
960 guest_efer |= host_efer & ignore_bits;
962 vmx->guest_uret_msrs[i].data = guest_efer;
963 vmx->guest_uret_msrs[i].mask = ~ignore_bits;
970 * On 32-bit kernels, VM exits still load the FS and GS bases from the
971 * VMCS rather than the segment table. KVM uses this helper to figure
972 * out the current bases to poke them into the VMCS before entry.
974 static unsigned long segment_base(u16 selector)
976 struct desc_struct *table;
979 if (!(selector & ~SEGMENT_RPL_MASK))
982 table = get_current_gdt_ro();
984 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
985 u16 ldt_selector = kvm_read_ldt();
987 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
990 table = (struct desc_struct *)segment_base(ldt_selector);
992 v = get_desc_base(&table[selector >> 3]);
997 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
999 return vmx_pt_mode_is_host_guest() &&
1000 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1003 static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base)
1005 /* The base must be 128-byte aligned and a legal physical address. */
1006 return kvm_vcpu_is_legal_aligned_gpa(vcpu, base, 128);
1009 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1013 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1014 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1015 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1016 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1017 for (i = 0; i < addr_range; i++) {
1018 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1019 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1023 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1027 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1028 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1029 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1030 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1031 for (i = 0; i < addr_range; i++) {
1032 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1033 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1037 static void pt_guest_enter(struct vcpu_vmx *vmx)
1039 if (vmx_pt_mode_is_system())
1043 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1044 * Save host state before VM entry.
1046 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1047 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1048 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1049 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1050 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1054 static void pt_guest_exit(struct vcpu_vmx *vmx)
1056 if (vmx_pt_mode_is_system())
1059 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1060 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges);
1061 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
1065 * KVM requires VM_EXIT_CLEAR_IA32_RTIT_CTL to expose PT to the guest,
1066 * i.e. RTIT_CTL is always cleared on VM-Exit. Restore it if necessary.
1068 if (vmx->pt_desc.host.ctl)
1069 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1072 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1073 unsigned long fs_base, unsigned long gs_base)
1075 if (unlikely(fs_sel != host->fs_sel)) {
1077 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1079 vmcs_write16(HOST_FS_SELECTOR, 0);
1080 host->fs_sel = fs_sel;
1082 if (unlikely(gs_sel != host->gs_sel)) {
1084 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1086 vmcs_write16(HOST_GS_SELECTOR, 0);
1087 host->gs_sel = gs_sel;
1089 if (unlikely(fs_base != host->fs_base)) {
1090 vmcs_writel(HOST_FS_BASE, fs_base);
1091 host->fs_base = fs_base;
1093 if (unlikely(gs_base != host->gs_base)) {
1094 vmcs_writel(HOST_GS_BASE, gs_base);
1095 host->gs_base = gs_base;
1099 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1101 struct vcpu_vmx *vmx = to_vmx(vcpu);
1102 struct vmcs_host_state *host_state;
1103 #ifdef CONFIG_X86_64
1104 int cpu = raw_smp_processor_id();
1107 unsigned long fs_base, gs_base;
1111 vmx->req_immediate_exit = false;
1114 * Note that guest MSRs to be saved/restored can also be changed
1115 * when guest state is loaded. This happens when guest transitions
1116 * to/from long-mode by setting MSR_EFER.LMA.
1118 if (!vmx->guest_uret_msrs_loaded) {
1119 vmx->guest_uret_msrs_loaded = true;
1120 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
1121 if (!vmx->guest_uret_msrs[i].load_into_hardware)
1124 kvm_set_user_return_msr(i,
1125 vmx->guest_uret_msrs[i].data,
1126 vmx->guest_uret_msrs[i].mask);
1130 if (vmx->nested.need_vmcs12_to_shadow_sync)
1131 nested_sync_vmcs12_to_shadow(vcpu);
1133 if (vmx->guest_state_loaded)
1136 host_state = &vmx->loaded_vmcs->host_state;
1139 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1140 * allow segment selectors with cpl > 0 or ti == 1.
1142 host_state->ldt_sel = kvm_read_ldt();
1144 #ifdef CONFIG_X86_64
1145 savesegment(ds, host_state->ds_sel);
1146 savesegment(es, host_state->es_sel);
1148 gs_base = cpu_kernelmode_gs_base(cpu);
1149 if (likely(is_64bit_mm(current->mm))) {
1150 current_save_fsgs();
1151 fs_sel = current->thread.fsindex;
1152 gs_sel = current->thread.gsindex;
1153 fs_base = current->thread.fsbase;
1154 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1156 savesegment(fs, fs_sel);
1157 savesegment(gs, gs_sel);
1158 fs_base = read_msr(MSR_FS_BASE);
1159 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1162 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1164 savesegment(fs, fs_sel);
1165 savesegment(gs, gs_sel);
1166 fs_base = segment_base(fs_sel);
1167 gs_base = segment_base(gs_sel);
1170 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1172 /* Host CR3 including its PCID is stable when guest state is loaded. */
1173 cr3 = __get_current_cr3_fast();
1174 if (unlikely(cr3 != host_state->cr3)) {
1175 vmcs_writel(HOST_CR3, cr3);
1176 host_state->cr3 = cr3;
1179 vmx->guest_state_loaded = true;
1182 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1184 struct vmcs_host_state *host_state;
1186 if (!vmx->guest_state_loaded)
1189 host_state = &vmx->loaded_vmcs->host_state;
1191 ++vmx->vcpu.stat.host_state_reload;
1193 #ifdef CONFIG_X86_64
1194 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1196 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1197 kvm_load_ldt(host_state->ldt_sel);
1198 #ifdef CONFIG_X86_64
1199 load_gs_index(host_state->gs_sel);
1201 loadsegment(gs, host_state->gs_sel);
1204 if (host_state->fs_sel & 7)
1205 loadsegment(fs, host_state->fs_sel);
1206 #ifdef CONFIG_X86_64
1207 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1208 loadsegment(ds, host_state->ds_sel);
1209 loadsegment(es, host_state->es_sel);
1212 invalidate_tss_limit();
1213 #ifdef CONFIG_X86_64
1214 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1216 load_fixmap_gdt(raw_smp_processor_id());
1217 vmx->guest_state_loaded = false;
1218 vmx->guest_uret_msrs_loaded = false;
1221 #ifdef CONFIG_X86_64
1222 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1225 if (vmx->guest_state_loaded)
1226 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1228 return vmx->msr_guest_kernel_gs_base;
1231 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1234 if (vmx->guest_state_loaded)
1235 wrmsrl(MSR_KERNEL_GS_BASE, data);
1237 vmx->msr_guest_kernel_gs_base = data;
1241 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1242 struct loaded_vmcs *buddy)
1244 struct vcpu_vmx *vmx = to_vmx(vcpu);
1245 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1248 if (!already_loaded) {
1249 loaded_vmcs_clear(vmx->loaded_vmcs);
1250 local_irq_disable();
1253 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1254 * this cpu's percpu list, otherwise it may not yet be deleted
1255 * from its previous cpu's percpu list. Pairs with the
1256 * smb_wmb() in __loaded_vmcs_clear().
1260 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1261 &per_cpu(loaded_vmcss_on_cpu, cpu));
1265 prev = per_cpu(current_vmcs, cpu);
1266 if (prev != vmx->loaded_vmcs->vmcs) {
1267 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1268 vmcs_load(vmx->loaded_vmcs->vmcs);
1271 * No indirect branch prediction barrier needed when switching
1272 * the active VMCS within a guest, e.g. on nested VM-Enter.
1273 * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1275 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1276 indirect_branch_prediction_barrier();
1279 if (!already_loaded) {
1280 void *gdt = get_current_gdt_ro();
1283 * Flush all EPTP/VPID contexts, the new pCPU may have stale
1284 * TLB entries from its previous association with the vCPU.
1286 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1289 * Linux uses per-cpu TSS and GDT, so set these when switching
1290 * processors. See 22.2.4.
1292 vmcs_writel(HOST_TR_BASE,
1293 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1294 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1296 if (IS_ENABLED(CONFIG_IA32_EMULATION) || IS_ENABLED(CONFIG_X86_32)) {
1298 vmcs_writel(HOST_IA32_SYSENTER_ESP,
1299 (unsigned long)(cpu_entry_stack(cpu) + 1));
1302 vmx->loaded_vmcs->cpu = cpu;
1307 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1308 * vcpu mutex is already taken.
1310 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1312 struct vcpu_vmx *vmx = to_vmx(vcpu);
1314 vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1316 vmx_vcpu_pi_load(vcpu, cpu);
1318 vmx->host_debugctlmsr = get_debugctlmsr();
1321 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1323 vmx_vcpu_pi_put(vcpu);
1325 vmx_prepare_switch_to_host(to_vmx(vcpu));
1328 bool vmx_emulation_required(struct kvm_vcpu *vcpu)
1330 return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu);
1333 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1335 struct vcpu_vmx *vmx = to_vmx(vcpu);
1336 unsigned long rflags, save_rflags;
1338 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1339 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1340 rflags = vmcs_readl(GUEST_RFLAGS);
1341 if (vmx->rmode.vm86_active) {
1342 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1343 save_rflags = vmx->rmode.save_rflags;
1344 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1346 vmx->rflags = rflags;
1351 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1353 struct vcpu_vmx *vmx = to_vmx(vcpu);
1354 unsigned long old_rflags;
1356 if (is_unrestricted_guest(vcpu)) {
1357 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1358 vmx->rflags = rflags;
1359 vmcs_writel(GUEST_RFLAGS, rflags);
1363 old_rflags = vmx_get_rflags(vcpu);
1364 vmx->rflags = rflags;
1365 if (vmx->rmode.vm86_active) {
1366 vmx->rmode.save_rflags = rflags;
1367 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1369 vmcs_writel(GUEST_RFLAGS, rflags);
1371 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1372 vmx->emulation_required = vmx_emulation_required(vcpu);
1375 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1377 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1380 if (interruptibility & GUEST_INTR_STATE_STI)
1381 ret |= KVM_X86_SHADOW_INT_STI;
1382 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1383 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1388 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1390 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1391 u32 interruptibility = interruptibility_old;
1393 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1395 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1396 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1397 else if (mask & KVM_X86_SHADOW_INT_STI)
1398 interruptibility |= GUEST_INTR_STATE_STI;
1400 if ((interruptibility != interruptibility_old))
1401 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1404 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1406 struct vcpu_vmx *vmx = to_vmx(vcpu);
1407 unsigned long value;
1410 * Any MSR write that attempts to change bits marked reserved will
1413 if (data & vmx->pt_desc.ctl_bitmask)
1417 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1418 * result in a #GP unless the same write also clears TraceEn.
1420 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1421 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1425 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1426 * and FabricEn would cause #GP, if
1427 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1429 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1430 !(data & RTIT_CTL_FABRIC_EN) &&
1431 !intel_pt_validate_cap(vmx->pt_desc.caps,
1432 PT_CAP_single_range_output))
1436 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1437 * utilize encodings marked reserved will cause a #GP fault.
1439 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1440 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1441 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1442 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1444 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1445 PT_CAP_cycle_thresholds);
1446 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1447 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1448 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1450 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1451 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1452 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1453 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1457 * If ADDRx_CFG is reserved or the encodings is >2 will
1458 * cause a #GP fault.
1460 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1461 if ((value && (vmx->pt_desc.num_address_ranges < 1)) || (value > 2))
1463 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1464 if ((value && (vmx->pt_desc.num_address_ranges < 2)) || (value > 2))
1466 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1467 if ((value && (vmx->pt_desc.num_address_ranges < 3)) || (value > 2))
1469 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1470 if ((value && (vmx->pt_desc.num_address_ranges < 4)) || (value > 2))
1476 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
1479 * Emulation of instructions in SGX enclaves is impossible as RIP does
1480 * not point tthe failing instruction, and even if it did, the code
1481 * stream is inaccessible. Inject #UD instead of exiting to userspace
1482 * so that guest userspace can't DoS the guest simply by triggering
1483 * emulation (enclaves are CPL3 only).
1485 if (to_vmx(vcpu)->exit_reason.enclave_mode) {
1486 kvm_queue_exception(vcpu, UD_VECTOR);
1492 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1494 union vmx_exit_reason exit_reason = to_vmx(vcpu)->exit_reason;
1495 unsigned long rip, orig_rip;
1499 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1500 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1501 * set when EPT misconfig occurs. In practice, real hardware updates
1502 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1503 * (namely Hyper-V) don't set it due to it being undefined behavior,
1504 * i.e. we end up advancing IP with some random value.
1506 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1507 exit_reason.basic != EXIT_REASON_EPT_MISCONFIG) {
1508 instr_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1511 * Emulating an enclave's instructions isn't supported as KVM
1512 * cannot access the enclave's memory or its true RIP, e.g. the
1513 * vmcs.GUEST_RIP points at the exit point of the enclave, not
1514 * the RIP that actually triggered the VM-Exit. But, because
1515 * most instructions that cause VM-Exit will #UD in an enclave,
1516 * most instruction-based VM-Exits simply do not occur.
1518 * There are a few exceptions, notably the debug instructions
1519 * INT1ICEBRK and INT3, as they are allowed in debug enclaves
1520 * and generate #DB/#BP as expected, which KVM might intercept.
1521 * But again, the CPU does the dirty work and saves an instr
1522 * length of zero so VMMs don't shoot themselves in the foot.
1523 * WARN if KVM tries to skip a non-zero length instruction on
1524 * a VM-Exit from an enclave.
1529 WARN(exit_reason.enclave_mode,
1530 "KVM: skipping instruction after SGX enclave VM-Exit");
1532 orig_rip = kvm_rip_read(vcpu);
1533 rip = orig_rip + instr_len;
1534 #ifdef CONFIG_X86_64
1536 * We need to mask out the high 32 bits of RIP if not in 64-bit
1537 * mode, but just finding out that we are in 64-bit mode is
1538 * quite expensive. Only do it if there was a carry.
1540 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1543 kvm_rip_write(vcpu, rip);
1545 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1550 /* skipping an emulated instruction also counts */
1551 vmx_set_interrupt_shadow(vcpu, 0);
1557 * Recognizes a pending MTF VM-exit and records the nested state for later
1560 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1562 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1563 struct vcpu_vmx *vmx = to_vmx(vcpu);
1565 if (!is_guest_mode(vcpu))
1569 * Per the SDM, MTF takes priority over debug-trap exceptions besides
1570 * T-bit traps. As instruction emulation is completed (i.e. at the
1571 * instruction boundary), any #DB exception pending delivery must be a
1572 * debug-trap. Record the pending MTF state to be delivered in
1573 * vmx_check_nested_events().
1575 if (nested_cpu_has_mtf(vmcs12) &&
1576 (!vcpu->arch.exception.pending ||
1577 vcpu->arch.exception.nr == DB_VECTOR))
1578 vmx->nested.mtf_pending = true;
1580 vmx->nested.mtf_pending = false;
1583 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1585 vmx_update_emulated_instruction(vcpu);
1586 return skip_emulated_instruction(vcpu);
1589 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1592 * Ensure that we clear the HLT state in the VMCS. We don't need to
1593 * explicitly skip the instruction because if the HLT state is set,
1594 * then the instruction is already executing and RIP has already been
1597 if (kvm_hlt_in_guest(vcpu->kvm) &&
1598 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1599 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1602 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1604 struct vcpu_vmx *vmx = to_vmx(vcpu);
1605 unsigned nr = vcpu->arch.exception.nr;
1606 bool has_error_code = vcpu->arch.exception.has_error_code;
1607 u32 error_code = vcpu->arch.exception.error_code;
1608 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1610 kvm_deliver_exception_payload(vcpu);
1612 if (has_error_code) {
1613 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1614 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1617 if (vmx->rmode.vm86_active) {
1619 if (kvm_exception_is_soft(nr))
1620 inc_eip = vcpu->arch.event_exit_inst_len;
1621 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1625 WARN_ON_ONCE(vmx->emulation_required);
1627 if (kvm_exception_is_soft(nr)) {
1628 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1629 vmx->vcpu.arch.event_exit_inst_len);
1630 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1632 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1634 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1636 vmx_clear_hlt(vcpu);
1639 static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr,
1640 bool load_into_hardware)
1642 struct vmx_uret_msr *uret_msr;
1644 uret_msr = vmx_find_uret_msr(vmx, msr);
1648 uret_msr->load_into_hardware = load_into_hardware;
1652 * Configuring user return MSRs to automatically save, load, and restore MSRs
1653 * that need to be shoved into hardware when running the guest. Note, omitting
1654 * an MSR here does _NOT_ mean it's not emulated, only that it will not be
1655 * loaded into hardware when running the guest.
1657 static void vmx_setup_uret_msrs(struct vcpu_vmx *vmx)
1659 #ifdef CONFIG_X86_64
1660 bool load_syscall_msrs;
1663 * The SYSCALL MSRs are only needed on long mode guests, and only
1664 * when EFER.SCE is set.
1666 load_syscall_msrs = is_long_mode(&vmx->vcpu) &&
1667 (vmx->vcpu.arch.efer & EFER_SCE);
1669 vmx_setup_uret_msr(vmx, MSR_STAR, load_syscall_msrs);
1670 vmx_setup_uret_msr(vmx, MSR_LSTAR, load_syscall_msrs);
1671 vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK, load_syscall_msrs);
1673 vmx_setup_uret_msr(vmx, MSR_EFER, update_transition_efer(vmx));
1675 vmx_setup_uret_msr(vmx, MSR_TSC_AUX,
1676 guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP) ||
1677 guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDPID));
1680 * hle=0, rtm=0, tsx_ctrl=1 can be found with some combinations of new
1681 * kernel and old userspace. If those guests run on a tsx=off host, do
1682 * allow guests to use TSX_CTRL, but don't change the value in hardware
1683 * so that TSX remains always disabled.
1685 vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL, boot_cpu_has(X86_FEATURE_RTM));
1688 * The set of MSRs to load may have changed, reload MSRs before the
1691 vmx->guest_uret_msrs_loaded = false;
1694 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1696 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1698 if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING))
1699 return vmcs12->tsc_offset;
1704 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1706 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1708 if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING) &&
1709 nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
1710 return vmcs12->tsc_multiplier;
1712 return kvm_default_tsc_scaling_ratio;
1715 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1717 vmcs_write64(TSC_OFFSET, offset);
1720 static void vmx_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1722 vmcs_write64(TSC_MULTIPLIER, multiplier);
1726 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1727 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1728 * all guests if the "nested" module option is off, and can also be disabled
1729 * for a single guest by disabling its VMX cpuid bit.
1731 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1733 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1736 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1739 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1741 return !(val & ~valid_bits);
1744 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1746 switch (msr->index) {
1747 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1750 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1751 case MSR_IA32_PERF_CAPABILITIES:
1752 msr->data = vmx_get_perf_capabilities();
1755 return KVM_MSR_RET_INVALID;
1760 * Reads an msr value (of 'msr_info->index') into 'msr_info->data'.
1761 * Returns 0 on success, non-0 otherwise.
1762 * Assumes vcpu_load() was already called.
1764 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1766 struct vcpu_vmx *vmx = to_vmx(vcpu);
1767 struct vmx_uret_msr *msr;
1770 switch (msr_info->index) {
1771 #ifdef CONFIG_X86_64
1773 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1776 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1778 case MSR_KERNEL_GS_BASE:
1779 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1783 return kvm_get_msr_common(vcpu, msr_info);
1784 case MSR_IA32_TSX_CTRL:
1785 if (!msr_info->host_initiated &&
1786 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1789 case MSR_IA32_UMWAIT_CONTROL:
1790 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1793 msr_info->data = vmx->msr_ia32_umwait_control;
1795 case MSR_IA32_SPEC_CTRL:
1796 if (!msr_info->host_initiated &&
1797 !guest_has_spec_ctrl_msr(vcpu))
1800 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1802 case MSR_IA32_SYSENTER_CS:
1803 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1805 case MSR_IA32_SYSENTER_EIP:
1806 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1808 case MSR_IA32_SYSENTER_ESP:
1809 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1811 case MSR_IA32_BNDCFGS:
1812 if (!kvm_mpx_supported() ||
1813 (!msr_info->host_initiated &&
1814 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1816 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1818 case MSR_IA32_MCG_EXT_CTL:
1819 if (!msr_info->host_initiated &&
1820 !(vmx->msr_ia32_feature_control &
1821 FEAT_CTL_LMCE_ENABLED))
1823 msr_info->data = vcpu->arch.mcg_ext_ctl;
1825 case MSR_IA32_FEAT_CTL:
1826 msr_info->data = vmx->msr_ia32_feature_control;
1828 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
1829 if (!msr_info->host_initiated &&
1830 !guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
1832 msr_info->data = to_vmx(vcpu)->msr_ia32_sgxlepubkeyhash
1833 [msr_info->index - MSR_IA32_SGXLEPUBKEYHASH0];
1835 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1836 if (!nested_vmx_allowed(vcpu))
1838 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1842 * Enlightened VMCS v1 doesn't have certain VMCS fields but
1843 * instead of just ignoring the features, different Hyper-V
1844 * versions are either trying to use them and fail or do some
1845 * sanity checking and refuse to boot. Filter all unsupported
1848 if (!msr_info->host_initiated &&
1849 vmx->nested.enlightened_vmcs_enabled)
1850 nested_evmcs_filter_control_msr(msr_info->index,
1853 case MSR_IA32_RTIT_CTL:
1854 if (!vmx_pt_mode_is_host_guest())
1856 msr_info->data = vmx->pt_desc.guest.ctl;
1858 case MSR_IA32_RTIT_STATUS:
1859 if (!vmx_pt_mode_is_host_guest())
1861 msr_info->data = vmx->pt_desc.guest.status;
1863 case MSR_IA32_RTIT_CR3_MATCH:
1864 if (!vmx_pt_mode_is_host_guest() ||
1865 !intel_pt_validate_cap(vmx->pt_desc.caps,
1866 PT_CAP_cr3_filtering))
1868 msr_info->data = vmx->pt_desc.guest.cr3_match;
1870 case MSR_IA32_RTIT_OUTPUT_BASE:
1871 if (!vmx_pt_mode_is_host_guest() ||
1872 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1873 PT_CAP_topa_output) &&
1874 !intel_pt_validate_cap(vmx->pt_desc.caps,
1875 PT_CAP_single_range_output)))
1877 msr_info->data = vmx->pt_desc.guest.output_base;
1879 case MSR_IA32_RTIT_OUTPUT_MASK:
1880 if (!vmx_pt_mode_is_host_guest() ||
1881 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1882 PT_CAP_topa_output) &&
1883 !intel_pt_validate_cap(vmx->pt_desc.caps,
1884 PT_CAP_single_range_output)))
1886 msr_info->data = vmx->pt_desc.guest.output_mask;
1888 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1889 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1890 if (!vmx_pt_mode_is_host_guest() ||
1891 (index >= 2 * vmx->pt_desc.num_address_ranges))
1894 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1896 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1898 case MSR_IA32_DEBUGCTLMSR:
1899 msr_info->data = vmcs_read64(GUEST_IA32_DEBUGCTL);
1903 msr = vmx_find_uret_msr(vmx, msr_info->index);
1905 msr_info->data = msr->data;
1908 return kvm_get_msr_common(vcpu, msr_info);
1914 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1917 #ifdef CONFIG_X86_64
1918 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1921 return (unsigned long)data;
1924 static u64 vcpu_supported_debugctl(struct kvm_vcpu *vcpu)
1926 u64 debugctl = vmx_supported_debugctl();
1928 if (!intel_pmu_lbr_is_enabled(vcpu))
1929 debugctl &= ~DEBUGCTLMSR_LBR_MASK;
1931 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1932 debugctl &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1938 * Writes msr value into the appropriate "register".
1939 * Returns 0 on success, non-0 otherwise.
1940 * Assumes vcpu_load() was already called.
1942 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1944 struct vcpu_vmx *vmx = to_vmx(vcpu);
1945 struct vmx_uret_msr *msr;
1947 u32 msr_index = msr_info->index;
1948 u64 data = msr_info->data;
1951 switch (msr_index) {
1953 ret = kvm_set_msr_common(vcpu, msr_info);
1955 #ifdef CONFIG_X86_64
1957 vmx_segment_cache_clear(vmx);
1958 vmcs_writel(GUEST_FS_BASE, data);
1961 vmx_segment_cache_clear(vmx);
1962 vmcs_writel(GUEST_GS_BASE, data);
1964 case MSR_KERNEL_GS_BASE:
1965 vmx_write_guest_kernel_gs_base(vmx, data);
1968 case MSR_IA32_SYSENTER_CS:
1969 if (is_guest_mode(vcpu))
1970 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1971 vmcs_write32(GUEST_SYSENTER_CS, data);
1973 case MSR_IA32_SYSENTER_EIP:
1974 if (is_guest_mode(vcpu)) {
1975 data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1976 get_vmcs12(vcpu)->guest_sysenter_eip = data;
1978 vmcs_writel(GUEST_SYSENTER_EIP, data);
1980 case MSR_IA32_SYSENTER_ESP:
1981 if (is_guest_mode(vcpu)) {
1982 data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1983 get_vmcs12(vcpu)->guest_sysenter_esp = data;
1985 vmcs_writel(GUEST_SYSENTER_ESP, data);
1987 case MSR_IA32_DEBUGCTLMSR: {
1988 u64 invalid = data & ~vcpu_supported_debugctl(vcpu);
1989 if (invalid & (DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR)) {
1990 if (report_ignored_msrs)
1991 vcpu_unimpl(vcpu, "%s: BTF|LBR in IA32_DEBUGCTLMSR 0x%llx, nop\n",
1993 data &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1994 invalid &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
2000 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
2001 VM_EXIT_SAVE_DEBUG_CONTROLS)
2002 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2004 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
2005 if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event &&
2006 (data & DEBUGCTLMSR_LBR))
2007 intel_pmu_create_guest_lbr_event(vcpu);
2010 case MSR_IA32_BNDCFGS:
2011 if (!kvm_mpx_supported() ||
2012 (!msr_info->host_initiated &&
2013 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2015 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2016 (data & MSR_IA32_BNDCFGS_RSVD))
2018 vmcs_write64(GUEST_BNDCFGS, data);
2020 case MSR_IA32_UMWAIT_CONTROL:
2021 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2024 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2025 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2028 vmx->msr_ia32_umwait_control = data;
2030 case MSR_IA32_SPEC_CTRL:
2031 if (!msr_info->host_initiated &&
2032 !guest_has_spec_ctrl_msr(vcpu))
2035 if (kvm_spec_ctrl_test_value(data))
2038 vmx->spec_ctrl = data;
2044 * When it's written (to non-zero) for the first time, pass
2048 * The handling of the MSR bitmap for L2 guests is done in
2049 * nested_vmx_prepare_msr_bitmap. We should not touch the
2050 * vmcs02.msr_bitmap here since it gets completely overwritten
2051 * in the merging. We update the vmcs01 here for L1 as well
2052 * since it will end up touching the MSR anyway now.
2054 vmx_disable_intercept_for_msr(vcpu,
2058 case MSR_IA32_TSX_CTRL:
2059 if (!msr_info->host_initiated &&
2060 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2062 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2065 case MSR_IA32_PRED_CMD:
2066 if (!msr_info->host_initiated &&
2067 !guest_has_pred_cmd_msr(vcpu))
2070 if (data & ~PRED_CMD_IBPB)
2072 if (!boot_cpu_has(X86_FEATURE_IBPB))
2077 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2081 * When it's written (to non-zero) for the first time, pass
2085 * The handling of the MSR bitmap for L2 guests is done in
2086 * nested_vmx_prepare_msr_bitmap. We should not touch the
2087 * vmcs02.msr_bitmap here since it gets completely overwritten
2090 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
2092 case MSR_IA32_CR_PAT:
2093 if (!kvm_pat_valid(data))
2096 if (is_guest_mode(vcpu) &&
2097 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2098 get_vmcs12(vcpu)->guest_ia32_pat = data;
2100 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2101 vmcs_write64(GUEST_IA32_PAT, data);
2102 vcpu->arch.pat = data;
2105 ret = kvm_set_msr_common(vcpu, msr_info);
2107 case MSR_IA32_MCG_EXT_CTL:
2108 if ((!msr_info->host_initiated &&
2109 !(to_vmx(vcpu)->msr_ia32_feature_control &
2110 FEAT_CTL_LMCE_ENABLED)) ||
2111 (data & ~MCG_EXT_CTL_LMCE_EN))
2113 vcpu->arch.mcg_ext_ctl = data;
2115 case MSR_IA32_FEAT_CTL:
2116 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2117 (to_vmx(vcpu)->msr_ia32_feature_control &
2118 FEAT_CTL_LOCKED && !msr_info->host_initiated))
2120 vmx->msr_ia32_feature_control = data;
2121 if (msr_info->host_initiated && data == 0)
2122 vmx_leave_nested(vcpu);
2124 /* SGX may be enabled/disabled by guest's firmware */
2125 vmx_write_encls_bitmap(vcpu, NULL);
2127 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
2129 * On real hardware, the LE hash MSRs are writable before
2130 * the firmware sets bit 0 in MSR 0x7a ("activating" SGX),
2131 * at which point SGX related bits in IA32_FEATURE_CONTROL
2134 * KVM does not emulate SGX activation for simplicity, so
2135 * allow writes to the LE hash MSRs if IA32_FEATURE_CONTROL
2136 * is unlocked. This is technically not architectural
2137 * behavior, but it's close enough.
2139 if (!msr_info->host_initiated &&
2140 (!guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC) ||
2141 ((vmx->msr_ia32_feature_control & FEAT_CTL_LOCKED) &&
2142 !(vmx->msr_ia32_feature_control & FEAT_CTL_SGX_LC_ENABLED))))
2144 vmx->msr_ia32_sgxlepubkeyhash
2145 [msr_index - MSR_IA32_SGXLEPUBKEYHASH0] = data;
2147 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2148 if (!msr_info->host_initiated)
2149 return 1; /* they are read-only */
2150 if (!nested_vmx_allowed(vcpu))
2152 return vmx_set_vmx_msr(vcpu, msr_index, data);
2153 case MSR_IA32_RTIT_CTL:
2154 if (!vmx_pt_mode_is_host_guest() ||
2155 vmx_rtit_ctl_check(vcpu, data) ||
2158 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2159 vmx->pt_desc.guest.ctl = data;
2160 pt_update_intercept_for_msr(vcpu);
2162 case MSR_IA32_RTIT_STATUS:
2163 if (!pt_can_write_msr(vmx))
2165 if (data & MSR_IA32_RTIT_STATUS_MASK)
2167 vmx->pt_desc.guest.status = data;
2169 case MSR_IA32_RTIT_CR3_MATCH:
2170 if (!pt_can_write_msr(vmx))
2172 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2173 PT_CAP_cr3_filtering))
2175 vmx->pt_desc.guest.cr3_match = data;
2177 case MSR_IA32_RTIT_OUTPUT_BASE:
2178 if (!pt_can_write_msr(vmx))
2180 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2181 PT_CAP_topa_output) &&
2182 !intel_pt_validate_cap(vmx->pt_desc.caps,
2183 PT_CAP_single_range_output))
2185 if (!pt_output_base_valid(vcpu, data))
2187 vmx->pt_desc.guest.output_base = data;
2189 case MSR_IA32_RTIT_OUTPUT_MASK:
2190 if (!pt_can_write_msr(vmx))
2192 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2193 PT_CAP_topa_output) &&
2194 !intel_pt_validate_cap(vmx->pt_desc.caps,
2195 PT_CAP_single_range_output))
2197 vmx->pt_desc.guest.output_mask = data;
2199 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2200 if (!pt_can_write_msr(vmx))
2202 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2203 if (index >= 2 * vmx->pt_desc.num_address_ranges)
2205 if (is_noncanonical_address(data, vcpu))
2208 vmx->pt_desc.guest.addr_b[index / 2] = data;
2210 vmx->pt_desc.guest.addr_a[index / 2] = data;
2212 case MSR_IA32_PERF_CAPABILITIES:
2213 if (data && !vcpu_to_pmu(vcpu)->version)
2215 if (data & PMU_CAP_LBR_FMT) {
2216 if ((data & PMU_CAP_LBR_FMT) !=
2217 (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
2219 if (!intel_pmu_lbr_is_compatible(vcpu))
2222 ret = kvm_set_msr_common(vcpu, msr_info);
2227 msr = vmx_find_uret_msr(vmx, msr_index);
2229 ret = vmx_set_guest_uret_msr(vmx, msr, data);
2231 ret = kvm_set_msr_common(vcpu, msr_info);
2237 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2239 unsigned long guest_owned_bits;
2241 kvm_register_mark_available(vcpu, reg);
2245 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2248 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2250 case VCPU_EXREG_PDPTR:
2252 ept_save_pdptrs(vcpu);
2254 case VCPU_EXREG_CR0:
2255 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2257 vcpu->arch.cr0 &= ~guest_owned_bits;
2258 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2260 case VCPU_EXREG_CR3:
2262 * When intercepting CR3 loads, e.g. for shadowing paging, KVM's
2263 * CR3 is loaded into hardware, not the guest's CR3.
2265 if (!(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_CR3_LOAD_EXITING))
2266 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2268 case VCPU_EXREG_CR4:
2269 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2271 vcpu->arch.cr4 &= ~guest_owned_bits;
2272 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2275 KVM_BUG_ON(1, vcpu->kvm);
2280 static __init int cpu_has_kvm_support(void)
2282 return cpu_has_vmx();
2285 static __init int vmx_disabled_by_bios(void)
2287 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2288 !boot_cpu_has(X86_FEATURE_VMX);
2291 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2295 cr4_set_bits(X86_CR4_VMXE);
2297 asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2298 _ASM_EXTABLE(1b, %l[fault])
2299 : : [vmxon_pointer] "m"(vmxon_pointer)
2304 WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2305 rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2306 cr4_clear_bits(X86_CR4_VMXE);
2311 static int hardware_enable(void)
2313 int cpu = raw_smp_processor_id();
2314 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2317 if (cr4_read_shadow() & X86_CR4_VMXE)
2321 * This can happen if we hot-added a CPU but failed to allocate
2322 * VP assist page for it.
2324 if (static_branch_unlikely(&enable_evmcs) &&
2325 !hv_get_vp_assist_page(cpu))
2328 intel_pt_handle_vmx(1);
2330 r = kvm_cpu_vmxon(phys_addr);
2332 intel_pt_handle_vmx(0);
2342 static void vmclear_local_loaded_vmcss(void)
2344 int cpu = raw_smp_processor_id();
2345 struct loaded_vmcs *v, *n;
2347 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2348 loaded_vmcss_on_cpu_link)
2349 __loaded_vmcs_clear(v);
2352 static void hardware_disable(void)
2354 vmclear_local_loaded_vmcss();
2357 kvm_spurious_fault();
2359 intel_pt_handle_vmx(0);
2363 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2364 * directly instead of going through cpu_has(), to ensure KVM is trapping
2365 * ENCLS whenever it's supported in hardware. It does not matter whether
2366 * the host OS supports or has enabled SGX.
2368 static bool cpu_has_sgx(void)
2370 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2373 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2374 u32 msr, u32 *result)
2376 u32 vmx_msr_low, vmx_msr_high;
2377 u32 ctl = ctl_min | ctl_opt;
2379 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2381 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2382 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2384 /* Ensure minimum (required) set of control bits are supported. */
2392 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2393 struct vmx_capability *vmx_cap)
2395 u32 vmx_msr_low, vmx_msr_high;
2396 u32 min, opt, min2, opt2;
2397 u32 _pin_based_exec_control = 0;
2398 u32 _cpu_based_exec_control = 0;
2399 u32 _cpu_based_2nd_exec_control = 0;
2400 u32 _vmexit_control = 0;
2401 u32 _vmentry_control = 0;
2403 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2404 min = CPU_BASED_HLT_EXITING |
2405 #ifdef CONFIG_X86_64
2406 CPU_BASED_CR8_LOAD_EXITING |
2407 CPU_BASED_CR8_STORE_EXITING |
2409 CPU_BASED_CR3_LOAD_EXITING |
2410 CPU_BASED_CR3_STORE_EXITING |
2411 CPU_BASED_UNCOND_IO_EXITING |
2412 CPU_BASED_MOV_DR_EXITING |
2413 CPU_BASED_USE_TSC_OFFSETTING |
2414 CPU_BASED_MWAIT_EXITING |
2415 CPU_BASED_MONITOR_EXITING |
2416 CPU_BASED_INVLPG_EXITING |
2417 CPU_BASED_RDPMC_EXITING;
2419 opt = CPU_BASED_TPR_SHADOW |
2420 CPU_BASED_USE_MSR_BITMAPS |
2421 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2422 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2423 &_cpu_based_exec_control) < 0)
2425 #ifdef CONFIG_X86_64
2426 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2427 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2428 ~CPU_BASED_CR8_STORE_EXITING;
2430 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2432 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2433 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2434 SECONDARY_EXEC_WBINVD_EXITING |
2435 SECONDARY_EXEC_ENABLE_VPID |
2436 SECONDARY_EXEC_ENABLE_EPT |
2437 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2438 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2439 SECONDARY_EXEC_DESC |
2440 SECONDARY_EXEC_ENABLE_RDTSCP |
2441 SECONDARY_EXEC_ENABLE_INVPCID |
2442 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2443 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2444 SECONDARY_EXEC_SHADOW_VMCS |
2445 SECONDARY_EXEC_XSAVES |
2446 SECONDARY_EXEC_RDSEED_EXITING |
2447 SECONDARY_EXEC_RDRAND_EXITING |
2448 SECONDARY_EXEC_ENABLE_PML |
2449 SECONDARY_EXEC_TSC_SCALING |
2450 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2451 SECONDARY_EXEC_PT_USE_GPA |
2452 SECONDARY_EXEC_PT_CONCEAL_VMX |
2453 SECONDARY_EXEC_ENABLE_VMFUNC |
2454 SECONDARY_EXEC_BUS_LOCK_DETECTION;
2456 opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2457 if (adjust_vmx_controls(min2, opt2,
2458 MSR_IA32_VMX_PROCBASED_CTLS2,
2459 &_cpu_based_2nd_exec_control) < 0)
2462 #ifndef CONFIG_X86_64
2463 if (!(_cpu_based_2nd_exec_control &
2464 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2465 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2468 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2469 _cpu_based_2nd_exec_control &= ~(
2470 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2471 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2472 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2474 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2475 &vmx_cap->ept, &vmx_cap->vpid);
2477 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2478 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2480 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2481 CPU_BASED_CR3_STORE_EXITING |
2482 CPU_BASED_INVLPG_EXITING);
2483 } else if (vmx_cap->ept) {
2485 pr_warn_once("EPT CAP should not exist if not support "
2486 "1-setting enable EPT VM-execution control\n");
2488 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2491 pr_warn_once("VPID CAP should not exist if not support "
2492 "1-setting enable VPID VM-execution control\n");
2495 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2496 #ifdef CONFIG_X86_64
2497 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2499 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2500 VM_EXIT_LOAD_IA32_PAT |
2501 VM_EXIT_LOAD_IA32_EFER |
2502 VM_EXIT_CLEAR_BNDCFGS |
2503 VM_EXIT_PT_CONCEAL_PIP |
2504 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2505 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2506 &_vmexit_control) < 0)
2509 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2510 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2511 PIN_BASED_VMX_PREEMPTION_TIMER;
2512 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2513 &_pin_based_exec_control) < 0)
2516 if (cpu_has_broken_vmx_preemption_timer())
2517 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2518 if (!(_cpu_based_2nd_exec_control &
2519 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2520 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2522 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2523 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2524 VM_ENTRY_LOAD_IA32_PAT |
2525 VM_ENTRY_LOAD_IA32_EFER |
2526 VM_ENTRY_LOAD_BNDCFGS |
2527 VM_ENTRY_PT_CONCEAL_PIP |
2528 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2529 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2530 &_vmentry_control) < 0)
2534 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2535 * can't be used due to an errata where VM Exit may incorrectly clear
2536 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2537 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2539 if (boot_cpu_data.x86 == 0x6) {
2540 switch (boot_cpu_data.x86_model) {
2541 case 26: /* AAK155 */
2542 case 30: /* AAP115 */
2543 case 37: /* AAT100 */
2544 case 44: /* BC86,AAY89,BD102 */
2546 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2547 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2548 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2549 "does not work properly. Using workaround\n");
2557 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2559 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2560 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2563 #ifdef CONFIG_X86_64
2564 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2565 if (vmx_msr_high & (1u<<16))
2569 /* Require Write-Back (WB) memory type for VMCS accesses. */
2570 if (((vmx_msr_high >> 18) & 15) != 6)
2573 vmcs_conf->size = vmx_msr_high & 0x1fff;
2574 vmcs_conf->order = get_order(vmcs_conf->size);
2575 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2577 vmcs_conf->revision_id = vmx_msr_low;
2579 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2580 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2581 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2582 vmcs_conf->vmexit_ctrl = _vmexit_control;
2583 vmcs_conf->vmentry_ctrl = _vmentry_control;
2585 #if IS_ENABLED(CONFIG_HYPERV)
2586 if (enlightened_vmcs)
2587 evmcs_sanitize_exec_ctrls(vmcs_conf);
2593 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2595 int node = cpu_to_node(cpu);
2599 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2602 vmcs = page_address(pages);
2603 memset(vmcs, 0, vmcs_config.size);
2605 /* KVM supports Enlightened VMCS v1 only */
2606 if (static_branch_unlikely(&enable_evmcs))
2607 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2609 vmcs->hdr.revision_id = vmcs_config.revision_id;
2612 vmcs->hdr.shadow_vmcs = 1;
2616 void free_vmcs(struct vmcs *vmcs)
2618 free_pages((unsigned long)vmcs, vmcs_config.order);
2622 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2624 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2626 if (!loaded_vmcs->vmcs)
2628 loaded_vmcs_clear(loaded_vmcs);
2629 free_vmcs(loaded_vmcs->vmcs);
2630 loaded_vmcs->vmcs = NULL;
2631 if (loaded_vmcs->msr_bitmap)
2632 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2633 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2636 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2638 loaded_vmcs->vmcs = alloc_vmcs(false);
2639 if (!loaded_vmcs->vmcs)
2642 vmcs_clear(loaded_vmcs->vmcs);
2644 loaded_vmcs->shadow_vmcs = NULL;
2645 loaded_vmcs->hv_timer_soft_disabled = false;
2646 loaded_vmcs->cpu = -1;
2647 loaded_vmcs->launched = 0;
2649 if (cpu_has_vmx_msr_bitmap()) {
2650 loaded_vmcs->msr_bitmap = (unsigned long *)
2651 __get_free_page(GFP_KERNEL_ACCOUNT);
2652 if (!loaded_vmcs->msr_bitmap)
2654 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2657 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2658 memset(&loaded_vmcs->controls_shadow, 0,
2659 sizeof(struct vmcs_controls_shadow));
2664 free_loaded_vmcs(loaded_vmcs);
2668 static void free_kvm_area(void)
2672 for_each_possible_cpu(cpu) {
2673 free_vmcs(per_cpu(vmxarea, cpu));
2674 per_cpu(vmxarea, cpu) = NULL;
2678 static __init int alloc_kvm_area(void)
2682 for_each_possible_cpu(cpu) {
2685 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2692 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2693 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2694 * revision_id reported by MSR_IA32_VMX_BASIC.
2696 * However, even though not explicitly documented by
2697 * TLFS, VMXArea passed as VMXON argument should
2698 * still be marked with revision_id reported by
2701 if (static_branch_unlikely(&enable_evmcs))
2702 vmcs->hdr.revision_id = vmcs_config.revision_id;
2704 per_cpu(vmxarea, cpu) = vmcs;
2709 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2710 struct kvm_segment *save)
2712 if (!emulate_invalid_guest_state) {
2714 * CS and SS RPL should be equal during guest entry according
2715 * to VMX spec, but in reality it is not always so. Since vcpu
2716 * is in the middle of the transition from real mode to
2717 * protected mode it is safe to assume that RPL 0 is a good
2720 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2721 save->selector &= ~SEGMENT_RPL_MASK;
2722 save->dpl = save->selector & SEGMENT_RPL_MASK;
2725 __vmx_set_segment(vcpu, save, seg);
2728 static void enter_pmode(struct kvm_vcpu *vcpu)
2730 unsigned long flags;
2731 struct vcpu_vmx *vmx = to_vmx(vcpu);
2734 * Update real mode segment cache. It may be not up-to-date if segment
2735 * register was written while vcpu was in a guest mode.
2737 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2738 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2739 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2740 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2741 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2742 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2744 vmx->rmode.vm86_active = 0;
2746 __vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2748 flags = vmcs_readl(GUEST_RFLAGS);
2749 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2750 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2751 vmcs_writel(GUEST_RFLAGS, flags);
2753 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2754 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2756 vmx_update_exception_bitmap(vcpu);
2758 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2759 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2760 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2761 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2762 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2763 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2766 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2768 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2769 struct kvm_segment var = *save;
2772 if (seg == VCPU_SREG_CS)
2775 if (!emulate_invalid_guest_state) {
2776 var.selector = var.base >> 4;
2777 var.base = var.base & 0xffff0;
2787 if (save->base & 0xf)
2788 printk_once(KERN_WARNING "kvm: segment base is not "
2789 "paragraph aligned when entering "
2790 "protected mode (seg=%d)", seg);
2793 vmcs_write16(sf->selector, var.selector);
2794 vmcs_writel(sf->base, var.base);
2795 vmcs_write32(sf->limit, var.limit);
2796 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2799 static void enter_rmode(struct kvm_vcpu *vcpu)
2801 unsigned long flags;
2802 struct vcpu_vmx *vmx = to_vmx(vcpu);
2803 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2805 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2806 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2807 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2808 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2809 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2810 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2811 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2813 vmx->rmode.vm86_active = 1;
2816 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2817 * vcpu. Warn the user that an update is overdue.
2819 if (!kvm_vmx->tss_addr)
2820 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2821 "called before entering vcpu\n");
2823 vmx_segment_cache_clear(vmx);
2825 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2826 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2827 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2829 flags = vmcs_readl(GUEST_RFLAGS);
2830 vmx->rmode.save_rflags = flags;
2832 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2834 vmcs_writel(GUEST_RFLAGS, flags);
2835 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2836 vmx_update_exception_bitmap(vcpu);
2838 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2839 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2840 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2841 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2842 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2843 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2846 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2848 struct vcpu_vmx *vmx = to_vmx(vcpu);
2849 struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER);
2851 /* Nothing to do if hardware doesn't support EFER. */
2855 vcpu->arch.efer = efer;
2856 if (efer & EFER_LMA) {
2857 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2860 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2862 msr->data = efer & ~EFER_LME;
2864 vmx_setup_uret_msrs(vmx);
2868 #ifdef CONFIG_X86_64
2870 static void enter_lmode(struct kvm_vcpu *vcpu)
2874 vmx_segment_cache_clear(to_vmx(vcpu));
2876 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2877 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2878 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2880 vmcs_write32(GUEST_TR_AR_BYTES,
2881 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2882 | VMX_AR_TYPE_BUSY_64_TSS);
2884 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2887 static void exit_lmode(struct kvm_vcpu *vcpu)
2889 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2890 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2895 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2897 struct vcpu_vmx *vmx = to_vmx(vcpu);
2900 * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2901 * the CPU is not required to invalidate guest-physical mappings on
2902 * VM-Entry, even if VPID is disabled. Guest-physical mappings are
2903 * associated with the root EPT structure and not any particular VPID
2904 * (INVVPID also isn't required to invalidate guest-physical mappings).
2908 } else if (enable_vpid) {
2909 if (cpu_has_vmx_invvpid_global()) {
2910 vpid_sync_vcpu_global();
2912 vpid_sync_vcpu_single(vmx->vpid);
2913 vpid_sync_vcpu_single(vmx->nested.vpid02);
2918 static inline int vmx_get_current_vpid(struct kvm_vcpu *vcpu)
2920 if (is_guest_mode(vcpu))
2921 return nested_get_vpid02(vcpu);
2922 return to_vmx(vcpu)->vpid;
2925 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2927 struct kvm_mmu *mmu = vcpu->arch.mmu;
2928 u64 root_hpa = mmu->root_hpa;
2930 /* No flush required if the current context is invalid. */
2931 if (!VALID_PAGE(root_hpa))
2935 ept_sync_context(construct_eptp(vcpu, root_hpa,
2936 mmu->shadow_root_level));
2938 vpid_sync_context(vmx_get_current_vpid(vcpu));
2941 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2944 * vpid_sync_vcpu_addr() is a nop if vpid==0, see the comment in
2945 * vmx_flush_tlb_guest() for an explanation of why this is ok.
2947 vpid_sync_vcpu_addr(vmx_get_current_vpid(vcpu), addr);
2950 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2953 * vpid_sync_context() is a nop if vpid==0, e.g. if enable_vpid==0 or a
2954 * vpid couldn't be allocated for this vCPU. VM-Enter and VM-Exit are
2955 * required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2956 * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2957 * i.e. no explicit INVVPID is necessary.
2959 vpid_sync_context(vmx_get_current_vpid(vcpu));
2962 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2964 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2966 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2969 if (is_pae_paging(vcpu)) {
2970 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2971 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2972 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2973 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2977 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2979 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2981 if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2984 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2985 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2986 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2987 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2989 kvm_register_mark_available(vcpu, VCPU_EXREG_PDPTR);
2992 #define CR3_EXITING_BITS (CPU_BASED_CR3_LOAD_EXITING | \
2993 CPU_BASED_CR3_STORE_EXITING)
2995 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2997 struct vcpu_vmx *vmx = to_vmx(vcpu);
2998 unsigned long hw_cr0, old_cr0_pg;
3001 old_cr0_pg = kvm_read_cr0_bits(vcpu, X86_CR0_PG);
3003 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3004 if (is_unrestricted_guest(vcpu))
3005 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3007 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3009 hw_cr0 |= X86_CR0_WP;
3011 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3014 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3018 vmcs_writel(CR0_READ_SHADOW, cr0);
3019 vmcs_writel(GUEST_CR0, hw_cr0);
3020 vcpu->arch.cr0 = cr0;
3021 kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3023 #ifdef CONFIG_X86_64
3024 if (vcpu->arch.efer & EFER_LME) {
3025 if (!old_cr0_pg && (cr0 & X86_CR0_PG))
3027 else if (old_cr0_pg && !(cr0 & X86_CR0_PG))
3032 if (enable_ept && !is_unrestricted_guest(vcpu)) {
3034 * Ensure KVM has an up-to-date snapshot of the guest's CR3. If
3035 * the below code _enables_ CR3 exiting, vmx_cache_reg() will
3036 * (correctly) stop reading vmcs.GUEST_CR3 because it thinks
3037 * KVM's CR3 is installed.
3039 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
3040 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
3043 * When running with EPT but not unrestricted guest, KVM must
3044 * intercept CR3 accesses when paging is _disabled_. This is
3045 * necessary because restricted guests can't actually run with
3046 * paging disabled, and so KVM stuffs its own CR3 in order to
3047 * run the guest when identity mapped page tables.
3049 * Do _NOT_ check the old CR0.PG, e.g. to optimize away the
3050 * update, it may be stale with respect to CR3 interception,
3051 * e.g. after nested VM-Enter.
3053 * Lastly, honor L1's desires, i.e. intercept CR3 loads and/or
3054 * stores to forward them to L1, even if KVM does not need to
3055 * intercept them to preserve its identity mapped page tables.
3057 if (!(cr0 & X86_CR0_PG)) {
3058 exec_controls_setbit(vmx, CR3_EXITING_BITS);
3059 } else if (!is_guest_mode(vcpu)) {
3060 exec_controls_clearbit(vmx, CR3_EXITING_BITS);
3062 tmp = exec_controls_get(vmx);
3063 tmp &= ~CR3_EXITING_BITS;
3064 tmp |= get_vmcs12(vcpu)->cpu_based_vm_exec_control & CR3_EXITING_BITS;
3065 exec_controls_set(vmx, tmp);
3068 /* Note, vmx_set_cr4() consumes the new vcpu->arch.cr0. */
3069 if ((old_cr0_pg ^ cr0) & X86_CR0_PG)
3070 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3073 /* depends on vcpu->arch.cr0 to be set to a new value */
3074 vmx->emulation_required = vmx_emulation_required(vcpu);
3077 static int vmx_get_max_tdp_level(void)
3079 if (cpu_has_vmx_ept_5levels())
3084 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level)
3086 u64 eptp = VMX_EPTP_MT_WB;
3088 eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3090 if (enable_ept_ad_bits &&
3091 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3092 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3098 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3101 struct kvm *kvm = vcpu->kvm;
3102 bool update_guest_cr3 = true;
3103 unsigned long guest_cr3;
3107 eptp = construct_eptp(vcpu, root_hpa, root_level);
3108 vmcs_write64(EPT_POINTER, eptp);
3110 hv_track_root_tdp(vcpu, root_hpa);
3112 if (!enable_unrestricted_guest && !is_paging(vcpu))
3113 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3114 else if (kvm_register_is_dirty(vcpu, VCPU_EXREG_CR3))
3115 guest_cr3 = vcpu->arch.cr3;
3116 else /* vmcs.GUEST_CR3 is already up-to-date. */
3117 update_guest_cr3 = false;
3118 vmx_ept_load_pdptrs(vcpu);
3120 guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu);
3123 if (update_guest_cr3)
3124 vmcs_writel(GUEST_CR3, guest_cr3);
3127 static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3130 * We operate under the default treatment of SMM, so VMX cannot be
3131 * enabled under SMM. Note, whether or not VMXE is allowed at all is
3132 * handled by kvm_is_valid_cr4().
3134 if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu))
3137 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3143 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3145 unsigned long old_cr4 = vcpu->arch.cr4;
3146 struct vcpu_vmx *vmx = to_vmx(vcpu);
3148 * Pass through host's Machine Check Enable value to hw_cr4, which
3149 * is in force while we are in guest mode. Do not let guests control
3150 * this bit, even if host CR4.MCE == 0.
3152 unsigned long hw_cr4;
3154 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3155 if (is_unrestricted_guest(vcpu))
3156 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3157 else if (vmx->rmode.vm86_active)
3158 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3160 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3162 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3163 if (cr4 & X86_CR4_UMIP) {
3164 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3165 hw_cr4 &= ~X86_CR4_UMIP;
3166 } else if (!is_guest_mode(vcpu) ||
3167 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3168 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3172 vcpu->arch.cr4 = cr4;
3173 kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3175 if (!is_unrestricted_guest(vcpu)) {
3177 if (!is_paging(vcpu)) {
3178 hw_cr4 &= ~X86_CR4_PAE;
3179 hw_cr4 |= X86_CR4_PSE;
3180 } else if (!(cr4 & X86_CR4_PAE)) {
3181 hw_cr4 &= ~X86_CR4_PAE;
3186 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3187 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3188 * to be manually disabled when guest switches to non-paging
3191 * If !enable_unrestricted_guest, the CPU is always running
3192 * with CR0.PG=1 and CR4 needs to be modified.
3193 * If enable_unrestricted_guest, the CPU automatically
3194 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3196 if (!is_paging(vcpu))
3197 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3200 vmcs_writel(CR4_READ_SHADOW, cr4);
3201 vmcs_writel(GUEST_CR4, hw_cr4);
3203 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
3204 kvm_update_cpuid_runtime(vcpu);
3207 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3209 struct vcpu_vmx *vmx = to_vmx(vcpu);
3212 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3213 *var = vmx->rmode.segs[seg];
3214 if (seg == VCPU_SREG_TR
3215 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3217 var->base = vmx_read_guest_seg_base(vmx, seg);
3218 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3221 var->base = vmx_read_guest_seg_base(vmx, seg);
3222 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3223 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3224 ar = vmx_read_guest_seg_ar(vmx, seg);
3225 var->unusable = (ar >> 16) & 1;
3226 var->type = ar & 15;
3227 var->s = (ar >> 4) & 1;
3228 var->dpl = (ar >> 5) & 3;
3230 * Some userspaces do not preserve unusable property. Since usable
3231 * segment has to be present according to VMX spec we can use present
3232 * property to amend userspace bug by making unusable segment always
3233 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3234 * segment as unusable.
3236 var->present = !var->unusable;
3237 var->avl = (ar >> 12) & 1;
3238 var->l = (ar >> 13) & 1;
3239 var->db = (ar >> 14) & 1;
3240 var->g = (ar >> 15) & 1;
3243 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3245 struct kvm_segment s;
3247 if (to_vmx(vcpu)->rmode.vm86_active) {
3248 vmx_get_segment(vcpu, &s, seg);
3251 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3254 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3256 struct vcpu_vmx *vmx = to_vmx(vcpu);
3258 if (unlikely(vmx->rmode.vm86_active))
3261 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3262 return VMX_AR_DPL(ar);
3266 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3270 if (var->unusable || !var->present)
3273 ar = var->type & 15;
3274 ar |= (var->s & 1) << 4;
3275 ar |= (var->dpl & 3) << 5;
3276 ar |= (var->present & 1) << 7;
3277 ar |= (var->avl & 1) << 12;
3278 ar |= (var->l & 1) << 13;
3279 ar |= (var->db & 1) << 14;
3280 ar |= (var->g & 1) << 15;
3286 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3288 struct vcpu_vmx *vmx = to_vmx(vcpu);
3289 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3291 vmx_segment_cache_clear(vmx);
3293 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3294 vmx->rmode.segs[seg] = *var;
3295 if (seg == VCPU_SREG_TR)
3296 vmcs_write16(sf->selector, var->selector);
3298 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3302 vmcs_writel(sf->base, var->base);
3303 vmcs_write32(sf->limit, var->limit);
3304 vmcs_write16(sf->selector, var->selector);
3307 * Fix the "Accessed" bit in AR field of segment registers for older
3309 * IA32 arch specifies that at the time of processor reset the
3310 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3311 * is setting it to 0 in the userland code. This causes invalid guest
3312 * state vmexit when "unrestricted guest" mode is turned on.
3313 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3314 * tree. Newer qemu binaries with that qemu fix would not need this
3317 if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3318 var->type |= 0x1; /* Accessed */
3320 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3323 static void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3325 __vmx_set_segment(vcpu, var, seg);
3327 to_vmx(vcpu)->emulation_required = vmx_emulation_required(vcpu);
3330 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3332 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3334 *db = (ar >> 14) & 1;
3335 *l = (ar >> 13) & 1;
3338 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3340 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3341 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3344 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3346 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3347 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3350 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3352 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3353 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3356 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3358 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3359 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3362 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3364 struct kvm_segment var;
3367 vmx_get_segment(vcpu, &var, seg);
3369 if (seg == VCPU_SREG_CS)
3371 ar = vmx_segment_access_rights(&var);
3373 if (var.base != (var.selector << 4))
3375 if (var.limit != 0xffff)
3383 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3385 struct kvm_segment cs;
3386 unsigned int cs_rpl;
3388 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3389 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3393 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3397 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3398 if (cs.dpl > cs_rpl)
3401 if (cs.dpl != cs_rpl)
3407 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3411 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3413 struct kvm_segment ss;
3414 unsigned int ss_rpl;
3416 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3417 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3421 if (ss.type != 3 && ss.type != 7)
3425 if (ss.dpl != ss_rpl) /* DPL != RPL */
3433 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3435 struct kvm_segment var;
3438 vmx_get_segment(vcpu, &var, seg);
3439 rpl = var.selector & SEGMENT_RPL_MASK;
3447 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3448 if (var.dpl < rpl) /* DPL < RPL */
3452 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3458 static bool tr_valid(struct kvm_vcpu *vcpu)
3460 struct kvm_segment tr;
3462 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3466 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3468 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3476 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3478 struct kvm_segment ldtr;
3480 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3484 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3494 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3496 struct kvm_segment cs, ss;
3498 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3499 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3501 return ((cs.selector & SEGMENT_RPL_MASK) ==
3502 (ss.selector & SEGMENT_RPL_MASK));
3506 * Check if guest state is valid. Returns true if valid, false if
3508 * We assume that registers are always usable
3510 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu)
3512 /* real mode guest state checks */
3513 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3514 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3516 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3518 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3520 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3522 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3524 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3527 /* protected mode guest state checks */
3528 if (!cs_ss_rpl_check(vcpu))
3530 if (!code_segment_valid(vcpu))
3532 if (!stack_segment_valid(vcpu))
3534 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3536 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3538 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3540 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3542 if (!tr_valid(vcpu))
3544 if (!ldtr_valid(vcpu))
3548 * - Add checks on RIP
3549 * - Add checks on RFLAGS
3555 static int init_rmode_tss(struct kvm *kvm, void __user *ua)
3557 const void *zero_page = (const void *) __va(page_to_phys(ZERO_PAGE(0)));
3561 for (i = 0; i < 3; i++) {
3562 if (__copy_to_user(ua + PAGE_SIZE * i, zero_page, PAGE_SIZE))
3566 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3567 if (__copy_to_user(ua + TSS_IOPB_BASE_OFFSET, &data, sizeof(u16)))
3571 if (__copy_to_user(ua + RMODE_TSS_SIZE - 1, &data, sizeof(u8)))
3577 static int init_rmode_identity_map(struct kvm *kvm)
3579 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3584 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3585 mutex_lock(&kvm->slots_lock);
3587 if (likely(kvm_vmx->ept_identity_pagetable_done))
3590 if (!kvm_vmx->ept_identity_map_addr)
3591 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3593 uaddr = __x86_set_memory_region(kvm,
3594 IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3595 kvm_vmx->ept_identity_map_addr,
3597 if (IS_ERR(uaddr)) {
3602 /* Set up identity-mapping pagetable for EPT in real mode */
3603 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3604 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3605 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3606 if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) {
3611 kvm_vmx->ept_identity_pagetable_done = true;
3614 mutex_unlock(&kvm->slots_lock);
3618 static void seg_setup(int seg)
3620 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3623 vmcs_write16(sf->selector, 0);
3624 vmcs_writel(sf->base, 0);
3625 vmcs_write32(sf->limit, 0xffff);
3627 if (seg == VCPU_SREG_CS)
3628 ar |= 0x08; /* code segment */
3630 vmcs_write32(sf->ar_bytes, ar);
3633 static int alloc_apic_access_page(struct kvm *kvm)
3639 mutex_lock(&kvm->slots_lock);
3640 if (kvm->arch.apic_access_memslot_enabled)
3642 hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3643 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3649 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3650 if (is_error_page(page)) {
3656 * Do not pin the page in memory, so that memory hot-unplug
3657 * is able to migrate it.
3660 kvm->arch.apic_access_memslot_enabled = true;
3662 mutex_unlock(&kvm->slots_lock);
3666 int allocate_vpid(void)
3672 spin_lock(&vmx_vpid_lock);
3673 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3674 if (vpid < VMX_NR_VPIDS)
3675 __set_bit(vpid, vmx_vpid_bitmap);
3678 spin_unlock(&vmx_vpid_lock);
3682 void free_vpid(int vpid)
3684 if (!enable_vpid || vpid == 0)
3686 spin_lock(&vmx_vpid_lock);
3687 __clear_bit(vpid, vmx_vpid_bitmap);
3688 spin_unlock(&vmx_vpid_lock);
3691 static void vmx_msr_bitmap_l01_changed(struct vcpu_vmx *vmx)
3694 * When KVM is a nested hypervisor on top of Hyper-V and uses
3695 * 'Enlightened MSR Bitmap' feature L0 needs to know that MSR
3696 * bitmap has changed.
3698 if (static_branch_unlikely(&enable_evmcs))
3699 evmcs_touch_msr_bitmap();
3701 vmx->nested.force_msr_bitmap_recalc = true;
3704 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3706 struct vcpu_vmx *vmx = to_vmx(vcpu);
3707 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3709 if (!cpu_has_vmx_msr_bitmap())
3712 vmx_msr_bitmap_l01_changed(vmx);
3715 * Mark the desired intercept state in shadow bitmap, this is needed
3716 * for resync when the MSR filters change.
3718 if (is_valid_passthrough_msr(msr)) {
3719 int idx = possible_passthrough_msr_slot(msr);
3721 if (idx != -ENOENT) {
3722 if (type & MSR_TYPE_R)
3723 clear_bit(idx, vmx->shadow_msr_intercept.read);
3724 if (type & MSR_TYPE_W)
3725 clear_bit(idx, vmx->shadow_msr_intercept.write);
3729 if ((type & MSR_TYPE_R) &&
3730 !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) {
3731 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3732 type &= ~MSR_TYPE_R;
3735 if ((type & MSR_TYPE_W) &&
3736 !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) {
3737 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3738 type &= ~MSR_TYPE_W;
3741 if (type & MSR_TYPE_R)
3742 vmx_clear_msr_bitmap_read(msr_bitmap, msr);
3744 if (type & MSR_TYPE_W)
3745 vmx_clear_msr_bitmap_write(msr_bitmap, msr);
3748 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3750 struct vcpu_vmx *vmx = to_vmx(vcpu);
3751 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3753 if (!cpu_has_vmx_msr_bitmap())
3756 vmx_msr_bitmap_l01_changed(vmx);
3759 * Mark the desired intercept state in shadow bitmap, this is needed
3760 * for resync when the MSR filter changes.
3762 if (is_valid_passthrough_msr(msr)) {
3763 int idx = possible_passthrough_msr_slot(msr);
3765 if (idx != -ENOENT) {
3766 if (type & MSR_TYPE_R)
3767 set_bit(idx, vmx->shadow_msr_intercept.read);
3768 if (type & MSR_TYPE_W)
3769 set_bit(idx, vmx->shadow_msr_intercept.write);
3773 if (type & MSR_TYPE_R)
3774 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3776 if (type & MSR_TYPE_W)
3777 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3780 static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode)
3782 unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
3783 unsigned long read_intercept;
3786 read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3788 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3789 unsigned int read_idx = msr / BITS_PER_LONG;
3790 unsigned int write_idx = read_idx + (0x800 / sizeof(long));
3792 msr_bitmap[read_idx] = read_intercept;
3793 msr_bitmap[write_idx] = ~0ul;
3797 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
3799 struct vcpu_vmx *vmx = to_vmx(vcpu);
3802 if (!cpu_has_vmx_msr_bitmap())
3805 if (cpu_has_secondary_exec_ctrls() &&
3806 (secondary_exec_controls_get(vmx) &
3807 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3808 mode = MSR_BITMAP_MODE_X2APIC;
3809 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3810 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3815 if (mode == vmx->x2apic_msr_bitmap_mode)
3818 vmx->x2apic_msr_bitmap_mode = mode;
3820 vmx_reset_x2apic_msrs(vcpu, mode);
3823 * TPR reads and writes can be virtualized even if virtual interrupt
3824 * delivery is not in use.
3826 vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
3827 !(mode & MSR_BITMAP_MODE_X2APIC));
3829 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3830 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
3831 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3832 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3836 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu)
3838 struct vcpu_vmx *vmx = to_vmx(vcpu);
3839 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3842 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
3843 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
3844 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
3845 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
3846 for (i = 0; i < vmx->pt_desc.num_address_ranges; i++) {
3847 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3848 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3852 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3854 struct vcpu_vmx *vmx = to_vmx(vcpu);
3859 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3860 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3861 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3864 rvi = vmx_get_rvi();
3866 vapic_page = vmx->nested.virtual_apic_map.hva;
3867 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3869 return ((rvi & 0xf0) > (vppr & 0xf0));
3872 static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
3874 struct vcpu_vmx *vmx = to_vmx(vcpu);
3878 * Set intercept permissions for all potentially passed through MSRs
3879 * again. They will automatically get filtered through the MSR filter,
3880 * so we are back in sync after this.
3882 for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
3883 u32 msr = vmx_possible_passthrough_msrs[i];
3884 bool read = test_bit(i, vmx->shadow_msr_intercept.read);
3885 bool write = test_bit(i, vmx->shadow_msr_intercept.write);
3887 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
3888 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
3891 pt_update_intercept_for_msr(vcpu);
3894 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3898 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3900 if (vcpu->mode == IN_GUEST_MODE) {
3902 * The vector of interrupt to be delivered to vcpu had
3903 * been set in PIR before this function.
3905 * Following cases will be reached in this block, and
3906 * we always send a notification event in all cases as
3909 * Case 1: vcpu keeps in non-root mode. Sending a
3910 * notification event posts the interrupt to vcpu.
3912 * Case 2: vcpu exits to root mode and is still
3913 * runnable. PIR will be synced to vIRR before the
3914 * next vcpu entry. Sending a notification event in
3915 * this case has no effect, as vcpu is not in root
3918 * Case 3: vcpu exits to root mode and is blocked.
3919 * vcpu_block() has already synced PIR to vIRR and
3920 * never blocks vcpu if vIRR is not cleared. Therefore,
3921 * a blocked vcpu here does not wait for any requested
3922 * interrupts in PIR, and sending a notification event
3923 * which has no effect is safe here.
3926 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3933 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3936 struct vcpu_vmx *vmx = to_vmx(vcpu);
3938 if (is_guest_mode(vcpu) &&
3939 vector == vmx->nested.posted_intr_nv) {
3941 * If a posted intr is not recognized by hardware,
3942 * we will accomplish it in the next vmentry.
3944 vmx->nested.pi_pending = true;
3945 kvm_make_request(KVM_REQ_EVENT, vcpu);
3948 * This pairs with the smp_mb_*() after setting vcpu->mode in
3949 * vcpu_enter_guest() to guarantee the vCPU sees the event
3950 * request if triggering a posted interrupt "fails" because
3951 * vcpu->mode != IN_GUEST_MODE. The extra barrier is needed as
3952 * the smb_wmb() in kvm_make_request() only ensures everything
3953 * done before making the request is visible when the request
3954 * is visible, it doesn't ensure ordering between the store to
3955 * vcpu->requests and the load from vcpu->mode.
3957 smp_mb__after_atomic();
3959 /* the PIR and ON have been set by L1. */
3960 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3961 kvm_vcpu_kick(vcpu);
3967 * Send interrupt to vcpu via posted interrupt way.
3968 * 1. If target vcpu is running(non-root mode), send posted interrupt
3969 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3970 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3971 * interrupt from PIR in next vmentry.
3973 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3975 struct vcpu_vmx *vmx = to_vmx(vcpu);
3978 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3982 if (!vcpu->arch.apicv_active)
3985 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3988 /* If a previous notification has sent the IPI, nothing to do. */
3989 if (pi_test_and_set_on(&vmx->pi_desc))
3993 * The implied barrier in pi_test_and_set_on() pairs with the smp_mb_*()
3994 * after setting vcpu->mode in vcpu_enter_guest(), thus the vCPU is
3995 * guaranteed to see PID.ON=1 and sync the PIR to IRR if triggering a
3996 * posted interrupt "fails" because vcpu->mode != IN_GUEST_MODE.
3998 if (vcpu != kvm_get_running_vcpu() &&
3999 !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
4000 kvm_vcpu_kick(vcpu);
4006 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4007 * will not change in the lifetime of the guest.
4008 * Note that host-state that does change is set elsewhere. E.g., host-state
4009 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4011 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4015 unsigned long cr0, cr3, cr4;
4018 WARN_ON(cr0 & X86_CR0_TS);
4019 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
4022 * Save the most likely value for this task's CR3 in the VMCS.
4023 * We can't use __get_current_cr3_fast() because we're not atomic.
4026 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
4027 vmx->loaded_vmcs->host_state.cr3 = cr3;
4029 /* Save the most likely value for this task's CR4 in the VMCS. */
4030 cr4 = cr4_read_shadow();
4031 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4032 vmx->loaded_vmcs->host_state.cr4 = cr4;
4034 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4035 #ifdef CONFIG_X86_64
4037 * Load null selectors, so we can avoid reloading them in
4038 * vmx_prepare_switch_to_host(), in case userspace uses
4039 * the null selectors too (the expected case).
4041 vmcs_write16(HOST_DS_SELECTOR, 0);
4042 vmcs_write16(HOST_ES_SELECTOR, 0);
4044 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4045 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4047 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4048 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4050 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
4052 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4054 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4055 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4058 * If 32-bit syscall is enabled, vmx_vcpu_load_vcms rewrites
4059 * HOST_IA32_SYSENTER_ESP.
4061 vmcs_writel(HOST_IA32_SYSENTER_ESP, 0);
4062 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4063 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4065 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4066 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4067 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4070 if (cpu_has_load_ia32_efer())
4071 vmcs_write64(HOST_IA32_EFER, host_efer);
4074 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4076 struct kvm_vcpu *vcpu = &vmx->vcpu;
4078 vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
4079 ~vcpu->arch.cr4_guest_rsvd_bits;
4081 vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_TLBFLUSH_BITS;
4082 vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PDPTR_BITS;
4084 if (is_guest_mode(&vmx->vcpu))
4085 vcpu->arch.cr4_guest_owned_bits &=
4086 ~get_vmcs12(vcpu)->cr4_guest_host_mask;
4087 vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits);
4090 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4092 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4094 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4095 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4098 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4100 if (!enable_preemption_timer)
4101 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4103 return pin_based_exec_ctrl;
4106 static u32 vmx_vmentry_ctrl(void)
4108 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
4110 if (vmx_pt_mode_is_system())
4111 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
4112 VM_ENTRY_LOAD_IA32_RTIT_CTL);
4113 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4114 return vmentry_ctrl &
4115 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
4118 static u32 vmx_vmexit_ctrl(void)
4120 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
4122 if (vmx_pt_mode_is_system())
4123 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
4124 VM_EXIT_CLEAR_IA32_RTIT_CTL);
4125 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4126 return vmexit_ctrl &
4127 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
4130 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4132 struct vcpu_vmx *vmx = to_vmx(vcpu);
4134 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4135 if (cpu_has_secondary_exec_ctrls()) {
4136 if (kvm_vcpu_apicv_active(vcpu))
4137 secondary_exec_controls_setbit(vmx,
4138 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4139 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4141 secondary_exec_controls_clearbit(vmx,
4142 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4143 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4146 vmx_update_msr_bitmap_x2apic(vcpu);
4149 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4151 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4153 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4154 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4156 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4157 exec_control &= ~CPU_BASED_TPR_SHADOW;
4158 #ifdef CONFIG_X86_64
4159 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4160 CPU_BASED_CR8_LOAD_EXITING;
4164 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4165 CPU_BASED_CR3_LOAD_EXITING |
4166 CPU_BASED_INVLPG_EXITING;
4167 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4168 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4169 CPU_BASED_MONITOR_EXITING);
4170 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4171 exec_control &= ~CPU_BASED_HLT_EXITING;
4172 return exec_control;
4176 * Adjust a single secondary execution control bit to intercept/allow an
4177 * instruction in the guest. This is usually done based on whether or not a
4178 * feature has been exposed to the guest in order to correctly emulate faults.
4181 vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control,
4182 u32 control, bool enabled, bool exiting)
4185 * If the control is for an opt-in feature, clear the control if the
4186 * feature is not exposed to the guest, i.e. not enabled. If the
4187 * control is opt-out, i.e. an exiting control, clear the control if
4188 * the feature _is_ exposed to the guest, i.e. exiting/interception is
4189 * disabled for the associated instruction. Note, the caller is
4190 * responsible presetting exec_control to set all supported bits.
4192 if (enabled == exiting)
4193 *exec_control &= ~control;
4196 * Update the nested MSR settings so that a nested VMM can/can't set
4197 * controls for features that are/aren't exposed to the guest.
4201 vmx->nested.msrs.secondary_ctls_high |= control;
4203 vmx->nested.msrs.secondary_ctls_high &= ~control;
4208 * Wrapper macro for the common case of adjusting a secondary execution control
4209 * based on a single guest CPUID bit, with a dedicated feature bit. This also
4210 * verifies that the control is actually supported by KVM and hardware.
4212 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \
4216 if (cpu_has_vmx_##name()) { \
4217 __enabled = guest_cpuid_has(&(vmx)->vcpu, \
4218 X86_FEATURE_##feat_name); \
4219 vmx_adjust_secondary_exec_control(vmx, exec_control, \
4220 SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \
4224 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */
4225 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \
4226 vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false)
4228 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \
4229 vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true)
4231 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4233 struct kvm_vcpu *vcpu = &vmx->vcpu;
4235 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4237 if (vmx_pt_mode_is_system())
4238 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4239 if (!cpu_need_virtualize_apic_accesses(vcpu))
4240 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4242 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4244 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4245 enable_unrestricted_guest = 0;
4247 if (!enable_unrestricted_guest)
4248 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4249 if (kvm_pause_in_guest(vmx->vcpu.kvm))
4250 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4251 if (!kvm_vcpu_apicv_active(vcpu))
4252 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4253 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4254 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4256 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4257 * in vmx_set_cr4. */
4258 exec_control &= ~SECONDARY_EXEC_DESC;
4260 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4262 We can NOT enable shadow_vmcs here because we don't have yet
4265 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4268 * PML is enabled/disabled when dirty logging of memsmlots changes, but
4269 * it needs to be set here when dirty logging is already active, e.g.
4270 * if this vCPU was created after dirty logging was enabled.
4272 if (!vcpu->kvm->arch.cpu_dirty_logging_count)
4273 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4275 if (cpu_has_vmx_xsaves()) {
4276 /* Exposing XSAVES only when XSAVE is exposed */
4277 bool xsaves_enabled =
4278 boot_cpu_has(X86_FEATURE_XSAVE) &&
4279 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4280 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4282 vcpu->arch.xsaves_enabled = xsaves_enabled;
4284 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4285 SECONDARY_EXEC_XSAVES,
4286 xsaves_enabled, false);
4290 * RDPID is also gated by ENABLE_RDTSCP, turn on the control if either
4291 * feature is exposed to the guest. This creates a virtualization hole
4292 * if both are supported in hardware but only one is exposed to the
4293 * guest, but letting the guest execute RDTSCP or RDPID when either one
4294 * is advertised is preferable to emulating the advertised instruction
4295 * in KVM on #UD, and obviously better than incorrectly injecting #UD.
4297 if (cpu_has_vmx_rdtscp()) {
4298 bool rdpid_or_rdtscp_enabled =
4299 guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) ||
4300 guest_cpuid_has(vcpu, X86_FEATURE_RDPID);
4302 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4303 SECONDARY_EXEC_ENABLE_RDTSCP,
4304 rdpid_or_rdtscp_enabled, false);
4306 vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID);
4308 vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND);
4309 vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED);
4311 vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG,
4312 ENABLE_USR_WAIT_PAUSE, false);
4314 if (!vcpu->kvm->arch.bus_lock_detection_enabled)
4315 exec_control &= ~SECONDARY_EXEC_BUS_LOCK_DETECTION;
4317 return exec_control;
4320 #define VMX_XSS_EXIT_BITMAP 0
4322 static void init_vmcs(struct vcpu_vmx *vmx)
4325 nested_vmx_set_vmcs_shadowing_bitmap();
4327 if (cpu_has_vmx_msr_bitmap())
4328 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4330 vmcs_write64(VMCS_LINK_POINTER, INVALID_GPA); /* 22.3.1.5 */
4333 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4335 exec_controls_set(vmx, vmx_exec_control(vmx));
4337 if (cpu_has_secondary_exec_ctrls())
4338 secondary_exec_controls_set(vmx, vmx_secondary_exec_control(vmx));
4340 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4341 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4342 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4343 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4344 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4346 vmcs_write16(GUEST_INTR_STATUS, 0);
4348 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4349 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4352 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4353 vmcs_write32(PLE_GAP, ple_gap);
4354 vmx->ple_window = ple_window;
4355 vmx->ple_window_dirty = true;
4358 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4359 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4360 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4362 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4363 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4364 vmx_set_constant_host_state(vmx);
4365 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4366 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4368 if (cpu_has_vmx_vmfunc())
4369 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4371 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4372 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4373 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4374 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4375 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4377 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4378 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4380 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4382 /* 22.2.1, 20.8.1 */
4383 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4385 vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4386 vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4388 set_cr4_guest_host_mask(vmx);
4391 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4393 if (cpu_has_vmx_xsaves())
4394 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4397 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4398 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4401 vmx_write_encls_bitmap(&vmx->vcpu, NULL);
4403 if (vmx_pt_mode_is_host_guest()) {
4404 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4405 /* Bit[6~0] are forced to 1, writes are ignored. */
4406 vmx->pt_desc.guest.output_mask = 0x7F;
4407 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4410 vmcs_write32(GUEST_SYSENTER_CS, 0);
4411 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4412 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4413 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4415 if (cpu_has_vmx_tpr_shadow()) {
4416 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4417 if (cpu_need_tpr_shadow(&vmx->vcpu))
4418 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4419 __pa(vmx->vcpu.arch.apic->regs));
4420 vmcs_write32(TPR_THRESHOLD, 0);
4423 vmx_setup_uret_msrs(vmx);
4426 static void __vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4428 struct vcpu_vmx *vmx = to_vmx(vcpu);
4433 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
4435 vcpu_setup_sgx_lepubkeyhash(vcpu);
4437 vmx->nested.posted_intr_nv = -1;
4438 vmx->nested.vmxon_ptr = INVALID_GPA;
4439 vmx->nested.current_vmptr = INVALID_GPA;
4440 vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
4442 vcpu->arch.microcode_version = 0x100000000ULL;
4443 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
4446 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
4447 * or POSTED_INTR_WAKEUP_VECTOR.
4449 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
4450 vmx->pi_desc.sn = 1;
4453 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4455 struct vcpu_vmx *vmx = to_vmx(vcpu);
4458 __vmx_vcpu_reset(vcpu);
4460 vmx->rmode.vm86_active = 0;
4463 vmx->msr_ia32_umwait_control = 0;
4465 vmx->hv_deadline_tsc = -1;
4466 kvm_set_cr8(vcpu, 0);
4468 vmx_segment_cache_clear(vmx);
4469 kvm_register_mark_available(vcpu, VCPU_EXREG_SEGMENTS);
4471 seg_setup(VCPU_SREG_CS);
4472 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4473 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4475 seg_setup(VCPU_SREG_DS);
4476 seg_setup(VCPU_SREG_ES);
4477 seg_setup(VCPU_SREG_FS);
4478 seg_setup(VCPU_SREG_GS);
4479 seg_setup(VCPU_SREG_SS);
4481 vmcs_write16(GUEST_TR_SELECTOR, 0);
4482 vmcs_writel(GUEST_TR_BASE, 0);
4483 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4484 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4486 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4487 vmcs_writel(GUEST_LDTR_BASE, 0);
4488 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4489 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4491 vmcs_writel(GUEST_GDTR_BASE, 0);
4492 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4494 vmcs_writel(GUEST_IDTR_BASE, 0);
4495 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4497 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4498 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4499 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4500 if (kvm_mpx_supported())
4501 vmcs_write64(GUEST_BNDCFGS, 0);
4503 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4505 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4507 vpid_sync_context(vmx->vpid);
4510 static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
4512 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4515 static void vmx_enable_nmi_window(struct kvm_vcpu *vcpu)
4518 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4519 vmx_enable_irq_window(vcpu);
4523 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4526 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4528 struct vcpu_vmx *vmx = to_vmx(vcpu);
4530 int irq = vcpu->arch.interrupt.nr;
4532 trace_kvm_inj_virq(irq);
4534 ++vcpu->stat.irq_injections;
4535 if (vmx->rmode.vm86_active) {
4537 if (vcpu->arch.interrupt.soft)
4538 inc_eip = vcpu->arch.event_exit_inst_len;
4539 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4542 intr = irq | INTR_INFO_VALID_MASK;
4543 if (vcpu->arch.interrupt.soft) {
4544 intr |= INTR_TYPE_SOFT_INTR;
4545 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4546 vmx->vcpu.arch.event_exit_inst_len);
4548 intr |= INTR_TYPE_EXT_INTR;
4549 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4551 vmx_clear_hlt(vcpu);
4554 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4556 struct vcpu_vmx *vmx = to_vmx(vcpu);
4560 * Tracking the NMI-blocked state in software is built upon
4561 * finding the next open IRQ window. This, in turn, depends on
4562 * well-behaving guests: They have to keep IRQs disabled at
4563 * least as long as the NMI handler runs. Otherwise we may
4564 * cause NMI nesting, maybe breaking the guest. But as this is
4565 * highly unlikely, we can live with the residual risk.
4567 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4568 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4571 ++vcpu->stat.nmi_injections;
4572 vmx->loaded_vmcs->nmi_known_unmasked = false;
4574 if (vmx->rmode.vm86_active) {
4575 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4579 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4580 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4582 vmx_clear_hlt(vcpu);
4585 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4587 struct vcpu_vmx *vmx = to_vmx(vcpu);
4591 return vmx->loaded_vmcs->soft_vnmi_blocked;
4592 if (vmx->loaded_vmcs->nmi_known_unmasked)
4594 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4595 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4599 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4601 struct vcpu_vmx *vmx = to_vmx(vcpu);
4604 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4605 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4606 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4609 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4611 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4612 GUEST_INTR_STATE_NMI);
4614 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4615 GUEST_INTR_STATE_NMI);
4619 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4621 if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4624 if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4627 return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4628 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4629 GUEST_INTR_STATE_NMI));
4632 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4634 if (to_vmx(vcpu)->nested.nested_run_pending)
4637 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
4638 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4641 return !vmx_nmi_blocked(vcpu);
4644 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4646 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4649 return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4650 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4651 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4654 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4656 if (to_vmx(vcpu)->nested.nested_run_pending)
4660 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4661 * e.g. if the IRQ arrived asynchronously after checking nested events.
4663 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4666 return !vmx_interrupt_blocked(vcpu);
4669 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4673 if (enable_unrestricted_guest)
4676 mutex_lock(&kvm->slots_lock);
4677 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4679 mutex_unlock(&kvm->slots_lock);
4682 return PTR_ERR(ret);
4684 to_kvm_vmx(kvm)->tss_addr = addr;
4686 return init_rmode_tss(kvm, ret);
4689 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4691 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4695 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4700 * Update instruction length as we may reinject the exception
4701 * from user space while in guest debugging mode.
4703 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4704 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4705 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4709 return !(vcpu->guest_debug &
4710 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4724 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4725 int vec, u32 err_code)
4728 * Instruction with address size override prefix opcode 0x67
4729 * Cause the #SS fault with 0 error code in VM86 mode.
4731 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4732 if (kvm_emulate_instruction(vcpu, 0)) {
4733 if (vcpu->arch.halt_request) {
4734 vcpu->arch.halt_request = 0;
4735 return kvm_emulate_halt_noskip(vcpu);
4743 * Forward all other exceptions that are valid in real mode.
4744 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4745 * the required debugging infrastructure rework.
4747 kvm_queue_exception(vcpu, vec);
4751 static int handle_machine_check(struct kvm_vcpu *vcpu)
4753 /* handled by vmx_vcpu_run() */
4758 * If the host has split lock detection disabled, then #AC is
4759 * unconditionally injected into the guest, which is the pre split lock
4760 * detection behaviour.
4762 * If the host has split lock detection enabled then #AC is
4763 * only injected into the guest when:
4764 * - Guest CPL == 3 (user mode)
4765 * - Guest has #AC detection enabled in CR0
4766 * - Guest EFLAGS has AC bit set
4768 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu)
4770 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4773 return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4774 (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4777 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4779 struct vcpu_vmx *vmx = to_vmx(vcpu);
4780 struct kvm_run *kvm_run = vcpu->run;
4781 u32 intr_info, ex_no, error_code;
4782 unsigned long cr2, dr6;
4785 vect_info = vmx->idt_vectoring_info;
4786 intr_info = vmx_get_intr_info(vcpu);
4788 if (is_machine_check(intr_info) || is_nmi(intr_info))
4789 return 1; /* handled by handle_exception_nmi_irqoff() */
4791 if (is_invalid_opcode(intr_info))
4792 return handle_ud(vcpu);
4795 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4796 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4798 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4799 WARN_ON_ONCE(!enable_vmware_backdoor);
4802 * VMware backdoor emulation on #GP interception only handles
4803 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4804 * error code on #GP.
4807 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4810 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4814 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4815 * MMIO, it is better to report an internal error.
4816 * See the comments in vmx_handle_exit.
4818 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4819 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4820 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4821 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4822 vcpu->run->internal.ndata = 4;
4823 vcpu->run->internal.data[0] = vect_info;
4824 vcpu->run->internal.data[1] = intr_info;
4825 vcpu->run->internal.data[2] = error_code;
4826 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4830 if (is_page_fault(intr_info)) {
4831 cr2 = vmx_get_exit_qual(vcpu);
4832 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4834 * EPT will cause page fault only if we need to
4835 * detect illegal GPAs.
4837 WARN_ON_ONCE(!allow_smaller_maxphyaddr);
4838 kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4841 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4844 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4846 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4847 return handle_rmode_exception(vcpu, ex_no, error_code);
4851 dr6 = vmx_get_exit_qual(vcpu);
4852 if (!(vcpu->guest_debug &
4853 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4854 if (is_icebp(intr_info))
4855 WARN_ON(!skip_emulated_instruction(vcpu));
4857 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4860 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
4861 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4865 * Update instruction length as we may reinject #BP from
4866 * user space while in guest debugging mode. Reading it for
4867 * #DB as well causes no harm, it is not used in that case.
4869 vmx->vcpu.arch.event_exit_inst_len =
4870 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4871 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4872 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4873 kvm_run->debug.arch.exception = ex_no;
4876 if (vmx_guest_inject_ac(vcpu)) {
4877 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4882 * Handle split lock. Depending on detection mode this will
4883 * either warn and disable split lock detection for this
4884 * task or force SIGBUS on it.
4886 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4890 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4891 kvm_run->ex.exception = ex_no;
4892 kvm_run->ex.error_code = error_code;
4898 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4900 ++vcpu->stat.irq_exits;
4904 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4906 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4907 vcpu->mmio_needed = 0;
4911 static int handle_io(struct kvm_vcpu *vcpu)
4913 unsigned long exit_qualification;
4914 int size, in, string;
4917 exit_qualification = vmx_get_exit_qual(vcpu);
4918 string = (exit_qualification & 16) != 0;
4920 ++vcpu->stat.io_exits;
4923 return kvm_emulate_instruction(vcpu, 0);
4925 port = exit_qualification >> 16;
4926 size = (exit_qualification & 7) + 1;
4927 in = (exit_qualification & 8) != 0;
4929 return kvm_fast_pio(vcpu, size, port, in);
4933 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4936 * Patch in the VMCALL instruction:
4938 hypercall[0] = 0x0f;
4939 hypercall[1] = 0x01;
4940 hypercall[2] = 0xc1;
4943 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4944 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4946 if (is_guest_mode(vcpu)) {
4947 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4948 unsigned long orig_val = val;
4951 * We get here when L2 changed cr0 in a way that did not change
4952 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4953 * but did change L0 shadowed bits. So we first calculate the
4954 * effective cr0 value that L1 would like to write into the
4955 * hardware. It consists of the L2-owned bits from the new
4956 * value combined with the L1-owned bits from L1's guest_cr0.
4958 val = (val & ~vmcs12->cr0_guest_host_mask) |
4959 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4961 if (!nested_guest_cr0_valid(vcpu, val))
4964 if (kvm_set_cr0(vcpu, val))
4966 vmcs_writel(CR0_READ_SHADOW, orig_val);
4969 if (to_vmx(vcpu)->nested.vmxon &&
4970 !nested_host_cr0_valid(vcpu, val))
4973 return kvm_set_cr0(vcpu, val);
4977 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4979 if (is_guest_mode(vcpu)) {
4980 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4981 unsigned long orig_val = val;
4983 /* analogously to handle_set_cr0 */
4984 val = (val & ~vmcs12->cr4_guest_host_mask) |
4985 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4986 if (kvm_set_cr4(vcpu, val))
4988 vmcs_writel(CR4_READ_SHADOW, orig_val);
4991 return kvm_set_cr4(vcpu, val);
4994 static int handle_desc(struct kvm_vcpu *vcpu)
4996 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4997 return kvm_emulate_instruction(vcpu, 0);
5000 static int handle_cr(struct kvm_vcpu *vcpu)
5002 unsigned long exit_qualification, val;
5008 exit_qualification = vmx_get_exit_qual(vcpu);
5009 cr = exit_qualification & 15;
5010 reg = (exit_qualification >> 8) & 15;
5011 switch ((exit_qualification >> 4) & 3) {
5012 case 0: /* mov to cr */
5013 val = kvm_register_read(vcpu, reg);
5014 trace_kvm_cr_write(cr, val);
5017 err = handle_set_cr0(vcpu, val);
5018 return kvm_complete_insn_gp(vcpu, err);
5020 WARN_ON_ONCE(enable_unrestricted_guest);
5022 err = kvm_set_cr3(vcpu, val);
5023 return kvm_complete_insn_gp(vcpu, err);
5025 err = handle_set_cr4(vcpu, val);
5026 return kvm_complete_insn_gp(vcpu, err);
5028 u8 cr8_prev = kvm_get_cr8(vcpu);
5030 err = kvm_set_cr8(vcpu, cr8);
5031 ret = kvm_complete_insn_gp(vcpu, err);
5032 if (lapic_in_kernel(vcpu))
5034 if (cr8_prev <= cr8)
5037 * TODO: we might be squashing a
5038 * KVM_GUESTDBG_SINGLESTEP-triggered
5039 * KVM_EXIT_DEBUG here.
5041 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5047 KVM_BUG(1, vcpu->kvm, "Guest always owns CR0.TS");
5049 case 1: /*mov from cr*/
5052 WARN_ON_ONCE(enable_unrestricted_guest);
5054 val = kvm_read_cr3(vcpu);
5055 kvm_register_write(vcpu, reg, val);
5056 trace_kvm_cr_read(cr, val);
5057 return kvm_skip_emulated_instruction(vcpu);
5059 val = kvm_get_cr8(vcpu);
5060 kvm_register_write(vcpu, reg, val);
5061 trace_kvm_cr_read(cr, val);
5062 return kvm_skip_emulated_instruction(vcpu);
5066 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5067 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5068 kvm_lmsw(vcpu, val);
5070 return kvm_skip_emulated_instruction(vcpu);
5074 vcpu->run->exit_reason = 0;
5075 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5076 (int)(exit_qualification >> 4) & 3, cr);
5080 static int handle_dr(struct kvm_vcpu *vcpu)
5082 unsigned long exit_qualification;
5086 exit_qualification = vmx_get_exit_qual(vcpu);
5087 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5089 /* First, if DR does not exist, trigger UD */
5090 if (!kvm_require_dr(vcpu, dr))
5093 if (kvm_x86_ops.get_cpl(vcpu) > 0)
5096 dr7 = vmcs_readl(GUEST_DR7);
5099 * As the vm-exit takes precedence over the debug trap, we
5100 * need to emulate the latter, either for the host or the
5101 * guest debugging itself.
5103 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5104 vcpu->run->debug.arch.dr6 = DR6_BD | DR6_ACTIVE_LOW;
5105 vcpu->run->debug.arch.dr7 = dr7;
5106 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5107 vcpu->run->debug.arch.exception = DB_VECTOR;
5108 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5111 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5116 if (vcpu->guest_debug == 0) {
5117 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5120 * No more DR vmexits; force a reload of the debug registers
5121 * and reenter on this instruction. The next vmexit will
5122 * retrieve the full state of the debug registers.
5124 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5128 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5129 if (exit_qualification & TYPE_MOV_FROM_DR) {
5132 kvm_get_dr(vcpu, dr, &val);
5133 kvm_register_write(vcpu, reg, val);
5136 err = kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg));
5140 return kvm_complete_insn_gp(vcpu, err);
5143 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5145 get_debugreg(vcpu->arch.db[0], 0);
5146 get_debugreg(vcpu->arch.db[1], 1);
5147 get_debugreg(vcpu->arch.db[2], 2);
5148 get_debugreg(vcpu->arch.db[3], 3);
5149 get_debugreg(vcpu->arch.dr6, 6);
5150 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5152 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5153 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5156 * exc_debug expects dr6 to be cleared after it runs, avoid that it sees
5157 * a stale dr6 from the guest.
5159 set_debugreg(DR6_RESERVED, 6);
5162 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5164 vmcs_writel(GUEST_DR7, val);
5167 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5169 kvm_apic_update_ppr(vcpu);
5173 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5175 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5177 kvm_make_request(KVM_REQ_EVENT, vcpu);
5179 ++vcpu->stat.irq_window_exits;
5183 static int handle_invlpg(struct kvm_vcpu *vcpu)
5185 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5187 kvm_mmu_invlpg(vcpu, exit_qualification);
5188 return kvm_skip_emulated_instruction(vcpu);
5191 static int handle_apic_access(struct kvm_vcpu *vcpu)
5193 if (likely(fasteoi)) {
5194 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5195 int access_type, offset;
5197 access_type = exit_qualification & APIC_ACCESS_TYPE;
5198 offset = exit_qualification & APIC_ACCESS_OFFSET;
5200 * Sane guest uses MOV to write EOI, with written value
5201 * not cared. So make a short-circuit here by avoiding
5202 * heavy instruction emulation.
5204 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5205 (offset == APIC_EOI)) {
5206 kvm_lapic_set_eoi(vcpu);
5207 return kvm_skip_emulated_instruction(vcpu);
5210 return kvm_emulate_instruction(vcpu, 0);
5213 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5215 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5216 int vector = exit_qualification & 0xff;
5218 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5219 kvm_apic_set_eoi_accelerated(vcpu, vector);
5223 static int handle_apic_write(struct kvm_vcpu *vcpu)
5225 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5226 u32 offset = exit_qualification & 0xfff;
5228 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5229 kvm_apic_write_nodecode(vcpu, offset);
5233 static int handle_task_switch(struct kvm_vcpu *vcpu)
5235 struct vcpu_vmx *vmx = to_vmx(vcpu);
5236 unsigned long exit_qualification;
5237 bool has_error_code = false;
5240 int reason, type, idt_v, idt_index;
5242 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5243 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5244 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5246 exit_qualification = vmx_get_exit_qual(vcpu);
5248 reason = (u32)exit_qualification >> 30;
5249 if (reason == TASK_SWITCH_GATE && idt_v) {
5251 case INTR_TYPE_NMI_INTR:
5252 vcpu->arch.nmi_injected = false;
5253 vmx_set_nmi_mask(vcpu, true);
5255 case INTR_TYPE_EXT_INTR:
5256 case INTR_TYPE_SOFT_INTR:
5257 kvm_clear_interrupt_queue(vcpu);
5259 case INTR_TYPE_HARD_EXCEPTION:
5260 if (vmx->idt_vectoring_info &
5261 VECTORING_INFO_DELIVER_CODE_MASK) {
5262 has_error_code = true;
5264 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5267 case INTR_TYPE_SOFT_EXCEPTION:
5268 kvm_clear_exception_queue(vcpu);
5274 tss_selector = exit_qualification;
5276 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5277 type != INTR_TYPE_EXT_INTR &&
5278 type != INTR_TYPE_NMI_INTR))
5279 WARN_ON(!skip_emulated_instruction(vcpu));
5282 * TODO: What about debug traps on tss switch?
5283 * Are we supposed to inject them and update dr6?
5285 return kvm_task_switch(vcpu, tss_selector,
5286 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5287 reason, has_error_code, error_code);
5290 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5292 unsigned long exit_qualification;
5296 exit_qualification = vmx_get_exit_qual(vcpu);
5299 * EPT violation happened while executing iret from NMI,
5300 * "blocked by NMI" bit has to be set before next VM entry.
5301 * There are errata that may cause this bit to not be set:
5304 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5306 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5307 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5309 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5310 trace_kvm_page_fault(gpa, exit_qualification);
5312 /* Is it a read fault? */
5313 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5314 ? PFERR_USER_MASK : 0;
5315 /* Is it a write fault? */
5316 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5317 ? PFERR_WRITE_MASK : 0;
5318 /* Is it a fetch fault? */
5319 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5320 ? PFERR_FETCH_MASK : 0;
5321 /* ept page table entry is present? */
5322 error_code |= (exit_qualification &
5323 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5324 EPT_VIOLATION_EXECUTABLE))
5325 ? PFERR_PRESENT_MASK : 0;
5327 error_code |= (exit_qualification & EPT_VIOLATION_GVA_TRANSLATED) != 0 ?
5328 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5330 vcpu->arch.exit_qualification = exit_qualification;
5333 * Check that the GPA doesn't exceed physical memory limits, as that is
5334 * a guest page fault. We have to emulate the instruction here, because
5335 * if the illegal address is that of a paging structure, then
5336 * EPT_VIOLATION_ACC_WRITE bit is set. Alternatively, if supported we
5337 * would also use advanced VM-exit information for EPT violations to
5338 * reconstruct the page fault error code.
5340 if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa)))
5341 return kvm_emulate_instruction(vcpu, 0);
5343 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5346 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5350 if (!vmx_can_emulate_instruction(vcpu, NULL, 0))
5354 * A nested guest cannot optimize MMIO vmexits, because we have an
5355 * nGPA here instead of the required GPA.
5357 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5358 if (!is_guest_mode(vcpu) &&
5359 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5360 trace_kvm_fast_mmio(gpa);
5361 return kvm_skip_emulated_instruction(vcpu);
5364 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5367 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5369 if (KVM_BUG_ON(!enable_vnmi, vcpu->kvm))
5372 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5373 ++vcpu->stat.nmi_window_exits;
5374 kvm_make_request(KVM_REQ_EVENT, vcpu);
5379 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5381 struct vcpu_vmx *vmx = to_vmx(vcpu);
5382 bool intr_window_requested;
5383 unsigned count = 130;
5385 intr_window_requested = exec_controls_get(vmx) &
5386 CPU_BASED_INTR_WINDOW_EXITING;
5388 while (vmx->emulation_required && count-- != 0) {
5389 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5390 return handle_interrupt_window(&vmx->vcpu);
5392 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5395 if (!kvm_emulate_instruction(vcpu, 0))
5398 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5399 vcpu->arch.exception.pending) {
5400 kvm_prepare_emulation_failure_exit(vcpu);
5404 if (vcpu->arch.halt_request) {
5405 vcpu->arch.halt_request = 0;
5406 return kvm_emulate_halt_noskip(vcpu);
5410 * Note, return 1 and not 0, vcpu_run() will invoke
5411 * xfer_to_guest_mode() which will create a proper return
5414 if (__xfer_to_guest_mode_work_pending())
5421 static void grow_ple_window(struct kvm_vcpu *vcpu)
5423 struct vcpu_vmx *vmx = to_vmx(vcpu);
5424 unsigned int old = vmx->ple_window;
5426 vmx->ple_window = __grow_ple_window(old, ple_window,
5430 if (vmx->ple_window != old) {
5431 vmx->ple_window_dirty = true;
5432 trace_kvm_ple_window_update(vcpu->vcpu_id,
5433 vmx->ple_window, old);
5437 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5439 struct vcpu_vmx *vmx = to_vmx(vcpu);
5440 unsigned int old = vmx->ple_window;
5442 vmx->ple_window = __shrink_ple_window(old, ple_window,
5446 if (vmx->ple_window != old) {
5447 vmx->ple_window_dirty = true;
5448 trace_kvm_ple_window_update(vcpu->vcpu_id,
5449 vmx->ple_window, old);
5454 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5455 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5457 static int handle_pause(struct kvm_vcpu *vcpu)
5459 if (!kvm_pause_in_guest(vcpu->kvm))
5460 grow_ple_window(vcpu);
5463 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5464 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5465 * never set PAUSE_EXITING and just set PLE if supported,
5466 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5468 kvm_vcpu_on_spin(vcpu, true);
5469 return kvm_skip_emulated_instruction(vcpu);
5472 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5477 static int handle_invpcid(struct kvm_vcpu *vcpu)
5479 u32 vmx_instruction_info;
5488 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5489 kvm_queue_exception(vcpu, UD_VECTOR);
5493 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5494 gpr_index = vmx_get_instr_info_reg2(vmx_instruction_info);
5495 type = kvm_register_read(vcpu, gpr_index);
5497 /* According to the Intel instruction reference, the memory operand
5498 * is read even if it isn't needed (e.g., for type==all)
5500 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5501 vmx_instruction_info, false,
5502 sizeof(operand), &gva))
5505 return kvm_handle_invpcid(vcpu, type, gva);
5508 static int handle_pml_full(struct kvm_vcpu *vcpu)
5510 unsigned long exit_qualification;
5512 trace_kvm_pml_full(vcpu->vcpu_id);
5514 exit_qualification = vmx_get_exit_qual(vcpu);
5517 * PML buffer FULL happened while executing iret from NMI,
5518 * "blocked by NMI" bit has to be set before next VM entry.
5520 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5522 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5523 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5524 GUEST_INTR_STATE_NMI);
5527 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5528 * here.., and there's no userspace involvement needed for PML.
5533 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5535 struct vcpu_vmx *vmx = to_vmx(vcpu);
5537 if (!vmx->req_immediate_exit &&
5538 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5539 kvm_lapic_expired_hv_timer(vcpu);
5540 return EXIT_FASTPATH_REENTER_GUEST;
5543 return EXIT_FASTPATH_NONE;
5546 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5548 handle_fastpath_preemption_timer(vcpu);
5553 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5554 * are overwritten by nested_vmx_setup() when nested=1.
5556 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5558 kvm_queue_exception(vcpu, UD_VECTOR);
5562 #ifndef CONFIG_X86_SGX_KVM
5563 static int handle_encls(struct kvm_vcpu *vcpu)
5566 * SGX virtualization is disabled. There is no software enable bit for
5567 * SGX, so KVM intercepts all ENCLS leafs and injects a #UD to prevent
5568 * the guest from executing ENCLS (when SGX is supported by hardware).
5570 kvm_queue_exception(vcpu, UD_VECTOR);
5573 #endif /* CONFIG_X86_SGX_KVM */
5575 static int handle_bus_lock_vmexit(struct kvm_vcpu *vcpu)
5578 * Hardware may or may not set the BUS_LOCK_DETECTED flag on BUS_LOCK
5579 * VM-Exits. Unconditionally set the flag here and leave the handling to
5580 * vmx_handle_exit().
5582 to_vmx(vcpu)->exit_reason.bus_lock_detected = true;
5587 * The exit handlers return 1 if the exit was handled fully and guest execution
5588 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5589 * to be done to userspace and return 0.
5591 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5592 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5593 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5594 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5595 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5596 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5597 [EXIT_REASON_CR_ACCESS] = handle_cr,
5598 [EXIT_REASON_DR_ACCESS] = handle_dr,
5599 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5600 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5601 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
5602 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
5603 [EXIT_REASON_HLT] = kvm_emulate_halt,
5604 [EXIT_REASON_INVD] = kvm_emulate_invd,
5605 [EXIT_REASON_INVLPG] = handle_invlpg,
5606 [EXIT_REASON_RDPMC] = kvm_emulate_rdpmc,
5607 [EXIT_REASON_VMCALL] = kvm_emulate_hypercall,
5608 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5609 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5610 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5611 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5612 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5613 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5614 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5615 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5616 [EXIT_REASON_VMON] = handle_vmx_instruction,
5617 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5618 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5619 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5620 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5621 [EXIT_REASON_WBINVD] = kvm_emulate_wbinvd,
5622 [EXIT_REASON_XSETBV] = kvm_emulate_xsetbv,
5623 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5624 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5625 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5626 [EXIT_REASON_LDTR_TR] = handle_desc,
5627 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5628 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5629 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5630 [EXIT_REASON_MWAIT_INSTRUCTION] = kvm_emulate_mwait,
5631 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5632 [EXIT_REASON_MONITOR_INSTRUCTION] = kvm_emulate_monitor,
5633 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5634 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5635 [EXIT_REASON_RDRAND] = kvm_handle_invalid_op,
5636 [EXIT_REASON_RDSEED] = kvm_handle_invalid_op,
5637 [EXIT_REASON_PML_FULL] = handle_pml_full,
5638 [EXIT_REASON_INVPCID] = handle_invpcid,
5639 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5640 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5641 [EXIT_REASON_ENCLS] = handle_encls,
5642 [EXIT_REASON_BUS_LOCK] = handle_bus_lock_vmexit,
5645 static const int kvm_vmx_max_exit_handlers =
5646 ARRAY_SIZE(kvm_vmx_exit_handlers);
5648 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
5649 u64 *info1, u64 *info2,
5650 u32 *intr_info, u32 *error_code)
5652 struct vcpu_vmx *vmx = to_vmx(vcpu);
5654 *reason = vmx->exit_reason.full;
5655 *info1 = vmx_get_exit_qual(vcpu);
5656 if (!(vmx->exit_reason.failed_vmentry)) {
5657 *info2 = vmx->idt_vectoring_info;
5658 *intr_info = vmx_get_intr_info(vcpu);
5659 if (is_exception_with_error_code(*intr_info))
5660 *error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5670 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5673 __free_page(vmx->pml_pg);
5678 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5680 struct vcpu_vmx *vmx = to_vmx(vcpu);
5684 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5686 /* Do nothing if PML buffer is empty */
5687 if (pml_idx == (PML_ENTITY_NUM - 1))
5690 /* PML index always points to next available PML buffer entity */
5691 if (pml_idx >= PML_ENTITY_NUM)
5696 pml_buf = page_address(vmx->pml_pg);
5697 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5700 gpa = pml_buf[pml_idx];
5701 WARN_ON(gpa & (PAGE_SIZE - 1));
5702 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5705 /* reset PML index */
5706 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5709 static void vmx_dump_sel(char *name, uint32_t sel)
5711 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5712 name, vmcs_read16(sel),
5713 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5714 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5715 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5718 static void vmx_dump_dtsel(char *name, uint32_t limit)
5720 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5721 name, vmcs_read32(limit),
5722 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5725 static void vmx_dump_msrs(char *name, struct vmx_msrs *m)
5728 struct vmx_msr_entry *e;
5730 pr_err("MSR %s:\n", name);
5731 for (i = 0, e = m->val; i < m->nr; ++i, ++e)
5732 pr_err(" %2d: msr=0x%08x value=0x%016llx\n", i, e->index, e->value);
5735 void dump_vmcs(struct kvm_vcpu *vcpu)
5737 struct vcpu_vmx *vmx = to_vmx(vcpu);
5738 u32 vmentry_ctl, vmexit_ctl;
5739 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5743 if (!dump_invalid_vmcs) {
5744 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5748 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5749 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5750 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5751 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5752 cr4 = vmcs_readl(GUEST_CR4);
5753 secondary_exec_control = 0;
5754 if (cpu_has_secondary_exec_ctrls())
5755 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5757 pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
5758 vmx->loaded_vmcs->vmcs, vcpu->arch.last_vmentry_cpu);
5759 pr_err("*** Guest State ***\n");
5760 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5761 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5762 vmcs_readl(CR0_GUEST_HOST_MASK));
5763 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5764 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5765 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5766 if (cpu_has_vmx_ept()) {
5767 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5768 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5769 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5770 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5772 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5773 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5774 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5775 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5776 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5777 vmcs_readl(GUEST_SYSENTER_ESP),
5778 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5779 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5780 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5781 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5782 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5783 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5784 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5785 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5786 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5787 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5788 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5789 efer_slot = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, MSR_EFER);
5790 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_EFER)
5791 pr_err("EFER= 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER));
5792 else if (efer_slot >= 0)
5793 pr_err("EFER= 0x%016llx (autoload)\n",
5794 vmx->msr_autoload.guest.val[efer_slot].value);
5795 else if (vmentry_ctl & VM_ENTRY_IA32E_MODE)
5796 pr_err("EFER= 0x%016llx (effective)\n",
5797 vcpu->arch.efer | (EFER_LMA | EFER_LME));
5799 pr_err("EFER= 0x%016llx (effective)\n",
5800 vcpu->arch.efer & ~(EFER_LMA | EFER_LME));
5801 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PAT)
5802 pr_err("PAT = 0x%016llx\n", vmcs_read64(GUEST_IA32_PAT));
5803 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5804 vmcs_read64(GUEST_IA32_DEBUGCTL),
5805 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5806 if (cpu_has_load_perf_global_ctrl() &&
5807 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5808 pr_err("PerfGlobCtl = 0x%016llx\n",
5809 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5810 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5811 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5812 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5813 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5814 vmcs_read32(GUEST_ACTIVITY_STATE));
5815 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5816 pr_err("InterruptStatus = %04x\n",
5817 vmcs_read16(GUEST_INTR_STATUS));
5818 if (vmcs_read32(VM_ENTRY_MSR_LOAD_COUNT) > 0)
5819 vmx_dump_msrs("guest autoload", &vmx->msr_autoload.guest);
5820 if (vmcs_read32(VM_EXIT_MSR_STORE_COUNT) > 0)
5821 vmx_dump_msrs("guest autostore", &vmx->msr_autostore.guest);
5823 pr_err("*** Host State ***\n");
5824 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5825 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5826 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5827 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5828 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5829 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5830 vmcs_read16(HOST_TR_SELECTOR));
5831 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5832 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5833 vmcs_readl(HOST_TR_BASE));
5834 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5835 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5836 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5837 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5838 vmcs_readl(HOST_CR4));
5839 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5840 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5841 vmcs_read32(HOST_IA32_SYSENTER_CS),
5842 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5843 if (vmexit_ctl & VM_EXIT_LOAD_IA32_EFER)
5844 pr_err("EFER= 0x%016llx\n", vmcs_read64(HOST_IA32_EFER));
5845 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PAT)
5846 pr_err("PAT = 0x%016llx\n", vmcs_read64(HOST_IA32_PAT));
5847 if (cpu_has_load_perf_global_ctrl() &&
5848 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5849 pr_err("PerfGlobCtl = 0x%016llx\n",
5850 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5851 if (vmcs_read32(VM_EXIT_MSR_LOAD_COUNT) > 0)
5852 vmx_dump_msrs("host autoload", &vmx->msr_autoload.host);
5854 pr_err("*** Control State ***\n");
5855 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5856 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5857 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5858 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5859 vmcs_read32(EXCEPTION_BITMAP),
5860 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5861 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5862 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5863 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5864 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5865 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5866 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5867 vmcs_read32(VM_EXIT_INTR_INFO),
5868 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5869 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5870 pr_err(" reason=%08x qualification=%016lx\n",
5871 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5872 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5873 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5874 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5875 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5876 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5877 pr_err("TSC Multiplier = 0x%016llx\n",
5878 vmcs_read64(TSC_MULTIPLIER));
5879 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5880 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5881 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5882 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5884 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5885 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5886 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5887 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5889 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5890 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5891 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5892 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5893 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5894 pr_err("PLE Gap=%08x Window=%08x\n",
5895 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5896 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5897 pr_err("Virtual processor ID = 0x%04x\n",
5898 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5902 * The guest has exited. See if we can fix it or if we need userspace
5905 static int __vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5907 struct vcpu_vmx *vmx = to_vmx(vcpu);
5908 union vmx_exit_reason exit_reason = vmx->exit_reason;
5909 u32 vectoring_info = vmx->idt_vectoring_info;
5910 u16 exit_handler_index;
5913 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5914 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5915 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5916 * mode as if vcpus is in root mode, the PML buffer must has been
5917 * flushed already. Note, PML is never enabled in hardware while
5920 if (enable_pml && !is_guest_mode(vcpu))
5921 vmx_flush_pml_buffer(vcpu);
5924 * We should never reach this point with a pending nested VM-Enter, and
5925 * more specifically emulation of L2 due to invalid guest state (see
5926 * below) should never happen as that means we incorrectly allowed a
5927 * nested VM-Enter with an invalid vmcs12.
5929 if (KVM_BUG_ON(vmx->nested.nested_run_pending, vcpu->kvm))
5932 /* If guest state is invalid, start emulating */
5933 if (vmx->emulation_required)
5934 return handle_invalid_guest_state(vcpu);
5936 if (is_guest_mode(vcpu)) {
5938 * PML is never enabled when running L2, bail immediately if a
5939 * PML full exit occurs as something is horribly wrong.
5941 if (exit_reason.basic == EXIT_REASON_PML_FULL)
5942 goto unexpected_vmexit;
5945 * The host physical addresses of some pages of guest memory
5946 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5947 * Page). The CPU may write to these pages via their host
5948 * physical address while L2 is running, bypassing any
5949 * address-translation-based dirty tracking (e.g. EPT write
5952 * Mark them dirty on every exit from L2 to prevent them from
5953 * getting out of sync with dirty tracking.
5955 nested_mark_vmcs12_pages_dirty(vcpu);
5957 if (nested_vmx_reflect_vmexit(vcpu))
5961 if (exit_reason.failed_vmentry) {
5963 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5964 vcpu->run->fail_entry.hardware_entry_failure_reason
5966 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5970 if (unlikely(vmx->fail)) {
5972 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5973 vcpu->run->fail_entry.hardware_entry_failure_reason
5974 = vmcs_read32(VM_INSTRUCTION_ERROR);
5975 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5981 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5982 * delivery event since it indicates guest is accessing MMIO.
5983 * The vm-exit can be triggered again after return to guest that
5984 * will cause infinite loop.
5986 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5987 (exit_reason.basic != EXIT_REASON_EXCEPTION_NMI &&
5988 exit_reason.basic != EXIT_REASON_EPT_VIOLATION &&
5989 exit_reason.basic != EXIT_REASON_PML_FULL &&
5990 exit_reason.basic != EXIT_REASON_APIC_ACCESS &&
5991 exit_reason.basic != EXIT_REASON_TASK_SWITCH)) {
5994 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5995 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5996 vcpu->run->internal.data[0] = vectoring_info;
5997 vcpu->run->internal.data[1] = exit_reason.full;
5998 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5999 if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG) {
6000 vcpu->run->internal.data[ndata++] =
6001 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6003 vcpu->run->internal.data[ndata++] = vcpu->arch.last_vmentry_cpu;
6004 vcpu->run->internal.ndata = ndata;
6008 if (unlikely(!enable_vnmi &&
6009 vmx->loaded_vmcs->soft_vnmi_blocked)) {
6010 if (!vmx_interrupt_blocked(vcpu)) {
6011 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6012 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
6013 vcpu->arch.nmi_pending) {
6015 * This CPU don't support us in finding the end of an
6016 * NMI-blocked window if the guest runs with IRQs
6017 * disabled. So we pull the trigger after 1 s of
6018 * futile waiting, but inform the user about this.
6020 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6021 "state on VCPU %d after 1 s timeout\n",
6022 __func__, vcpu->vcpu_id);
6023 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6027 if (exit_fastpath != EXIT_FASTPATH_NONE)
6030 if (exit_reason.basic >= kvm_vmx_max_exit_handlers)
6031 goto unexpected_vmexit;
6032 #ifdef CONFIG_RETPOLINE
6033 if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
6034 return kvm_emulate_wrmsr(vcpu);
6035 else if (exit_reason.basic == EXIT_REASON_PREEMPTION_TIMER)
6036 return handle_preemption_timer(vcpu);
6037 else if (exit_reason.basic == EXIT_REASON_INTERRUPT_WINDOW)
6038 return handle_interrupt_window(vcpu);
6039 else if (exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6040 return handle_external_interrupt(vcpu);
6041 else if (exit_reason.basic == EXIT_REASON_HLT)
6042 return kvm_emulate_halt(vcpu);
6043 else if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG)
6044 return handle_ept_misconfig(vcpu);
6047 exit_handler_index = array_index_nospec((u16)exit_reason.basic,
6048 kvm_vmx_max_exit_handlers);
6049 if (!kvm_vmx_exit_handlers[exit_handler_index])
6050 goto unexpected_vmexit;
6052 return kvm_vmx_exit_handlers[exit_handler_index](vcpu);
6055 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
6058 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6059 vcpu->run->internal.suberror =
6060 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6061 vcpu->run->internal.ndata = 2;
6062 vcpu->run->internal.data[0] = exit_reason.full;
6063 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6067 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6069 int ret = __vmx_handle_exit(vcpu, exit_fastpath);
6072 * Exit to user space when bus lock detected to inform that there is
6073 * a bus lock in guest.
6075 if (to_vmx(vcpu)->exit_reason.bus_lock_detected) {
6077 vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
6079 vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
6086 * Software based L1D cache flush which is used when microcode providing
6087 * the cache control MSR is not loaded.
6089 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6090 * flush it is required to read in 64 KiB because the replacement algorithm
6091 * is not exactly LRU. This could be sized at runtime via topology
6092 * information but as all relevant affected CPUs have 32KiB L1D cache size
6093 * there is no point in doing so.
6095 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6097 int size = PAGE_SIZE << L1D_CACHE_ORDER;
6100 * This code is only executed when the the flush mode is 'cond' or
6103 if (static_branch_likely(&vmx_l1d_flush_cond)) {
6107 * Clear the per-vcpu flush bit, it gets set again
6108 * either from vcpu_run() or from one of the unsafe
6111 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6112 vcpu->arch.l1tf_flush_l1d = false;
6115 * Clear the per-cpu flush bit, it gets set again from
6116 * the interrupt handlers.
6118 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6119 kvm_clear_cpu_l1tf_flush_l1d();
6125 vcpu->stat.l1d_flush++;
6127 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6128 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6133 /* First ensure the pages are in the TLB */
6134 "xorl %%eax, %%eax\n"
6135 ".Lpopulate_tlb:\n\t"
6136 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6137 "addl $4096, %%eax\n\t"
6138 "cmpl %%eax, %[size]\n\t"
6139 "jne .Lpopulate_tlb\n\t"
6140 "xorl %%eax, %%eax\n\t"
6142 /* Now fill the cache */
6143 "xorl %%eax, %%eax\n"
6145 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6146 "addl $64, %%eax\n\t"
6147 "cmpl %%eax, %[size]\n\t"
6148 "jne .Lfill_cache\n\t"
6150 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6152 : "eax", "ebx", "ecx", "edx");
6155 static void vmx_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6157 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6160 if (is_guest_mode(vcpu) &&
6161 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6164 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6165 if (is_guest_mode(vcpu))
6166 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6168 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6171 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6173 struct vcpu_vmx *vmx = to_vmx(vcpu);
6174 u32 sec_exec_control;
6176 if (!lapic_in_kernel(vcpu))
6179 if (!flexpriority_enabled &&
6180 !cpu_has_vmx_virtualize_x2apic_mode())
6183 /* Postpone execution until vmcs01 is the current VMCS. */
6184 if (is_guest_mode(vcpu)) {
6185 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6189 sec_exec_control = secondary_exec_controls_get(vmx);
6190 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6191 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6193 switch (kvm_get_apic_mode(vcpu)) {
6194 case LAPIC_MODE_INVALID:
6195 WARN_ONCE(true, "Invalid local APIC state");
6197 case LAPIC_MODE_DISABLED:
6199 case LAPIC_MODE_XAPIC:
6200 if (flexpriority_enabled) {
6202 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6203 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6206 * Flush the TLB, reloading the APIC access page will
6207 * only do so if its physical address has changed, but
6208 * the guest may have inserted a non-APIC mapping into
6209 * the TLB while the APIC access page was disabled.
6211 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6214 case LAPIC_MODE_X2APIC:
6215 if (cpu_has_vmx_virtualize_x2apic_mode())
6217 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6220 secondary_exec_controls_set(vmx, sec_exec_control);
6222 vmx_update_msr_bitmap_x2apic(vcpu);
6225 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6229 /* Defer reload until vmcs01 is the current VMCS. */
6230 if (is_guest_mode(vcpu)) {
6231 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6235 if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6236 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6239 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6240 if (is_error_page(page))
6243 vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6244 vmx_flush_tlb_current(vcpu);
6247 * Do not pin apic access page in memory, the MMU notifier
6248 * will call us again if it is migrated or swapped out.
6253 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6261 status = vmcs_read16(GUEST_INTR_STATUS);
6263 if (max_isr != old) {
6265 status |= max_isr << 8;
6266 vmcs_write16(GUEST_INTR_STATUS, status);
6270 static void vmx_set_rvi(int vector)
6278 status = vmcs_read16(GUEST_INTR_STATUS);
6279 old = (u8)status & 0xff;
6280 if ((u8)vector != old) {
6282 status |= (u8)vector;
6283 vmcs_write16(GUEST_INTR_STATUS, status);
6287 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6290 * When running L2, updating RVI is only relevant when
6291 * vmcs12 virtual-interrupt-delivery enabled.
6292 * However, it can be enabled only when L1 also
6293 * intercepts external-interrupts and in that case
6294 * we should not update vmcs02 RVI but instead intercept
6295 * interrupt. Therefore, do nothing when running L2.
6297 if (!is_guest_mode(vcpu))
6298 vmx_set_rvi(max_irr);
6301 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6303 struct vcpu_vmx *vmx = to_vmx(vcpu);
6305 bool got_posted_interrupt;
6307 if (KVM_BUG_ON(!enable_apicv, vcpu->kvm))
6310 if (pi_test_on(&vmx->pi_desc)) {
6311 pi_clear_on(&vmx->pi_desc);
6313 * IOMMU can write to PID.ON, so the barrier matters even on UP.
6314 * But on x86 this is just a compiler barrier anyway.
6316 smp_mb__after_atomic();
6317 got_posted_interrupt =
6318 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6320 max_irr = kvm_lapic_find_highest_irr(vcpu);
6321 got_posted_interrupt = false;
6325 * Newly recognized interrupts are injected via either virtual interrupt
6326 * delivery (RVI) or KVM_REQ_EVENT. Virtual interrupt delivery is
6327 * disabled in two cases:
6329 * 1) If L2 is running and the vCPU has a new pending interrupt. If L1
6330 * wants to exit on interrupts, KVM_REQ_EVENT is needed to synthesize a
6331 * VM-Exit to L1. If L1 doesn't want to exit, the interrupt is injected
6332 * into L2, but KVM doesn't use virtual interrupt delivery to inject
6333 * interrupts into L2, and so KVM_REQ_EVENT is again needed.
6335 * 2) If APICv is disabled for this vCPU, assigned devices may still
6336 * attempt to post interrupts. The posted interrupt vector will cause
6337 * a VM-Exit and the subsequent entry will call sync_pir_to_irr.
6339 if (!is_guest_mode(vcpu) && kvm_vcpu_apicv_active(vcpu))
6340 vmx_set_rvi(max_irr);
6341 else if (got_posted_interrupt)
6342 kvm_make_request(KVM_REQ_EVENT, vcpu);
6347 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6349 if (!kvm_vcpu_apicv_active(vcpu))
6352 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6353 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6354 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6355 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6358 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6360 struct vcpu_vmx *vmx = to_vmx(vcpu);
6362 pi_clear_on(&vmx->pi_desc);
6363 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6366 void vmx_do_interrupt_nmi_irqoff(unsigned long entry);
6368 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu,
6369 unsigned long entry)
6371 kvm_before_interrupt(vcpu);
6372 vmx_do_interrupt_nmi_irqoff(entry);
6373 kvm_after_interrupt(vcpu);
6376 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6378 const unsigned long nmi_entry = (unsigned long)asm_exc_nmi_noist;
6379 u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6381 /* if exit due to PF check for async PF */
6382 if (is_page_fault(intr_info))
6383 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6384 /* Handle machine checks before interrupts are enabled */
6385 else if (is_machine_check(intr_info))
6386 kvm_machine_check();
6387 /* We need to handle NMIs before interrupts are enabled */
6388 else if (is_nmi(intr_info))
6389 handle_interrupt_nmi_irqoff(&vmx->vcpu, nmi_entry);
6392 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6394 u32 intr_info = vmx_get_intr_info(vcpu);
6395 unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK;
6396 gate_desc *desc = (gate_desc *)host_idt_base + vector;
6398 if (KVM_BUG(!is_external_intr(intr_info), vcpu->kvm,
6399 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6402 handle_interrupt_nmi_irqoff(vcpu, gate_offset(desc));
6405 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6407 struct vcpu_vmx *vmx = to_vmx(vcpu);
6409 if (vmx->emulation_required)
6412 if (vmx->exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6413 handle_external_interrupt_irqoff(vcpu);
6414 else if (vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI)
6415 handle_exception_nmi_irqoff(vmx);
6419 * The kvm parameter can be NULL (module initialization, or invocation before
6420 * VM creation). Be sure to check the kvm parameter before using it.
6422 static bool vmx_has_emulated_msr(struct kvm *kvm, u32 index)
6425 case MSR_IA32_SMBASE:
6427 * We cannot do SMM unless we can run the guest in big
6430 return enable_unrestricted_guest || emulate_invalid_guest_state;
6431 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6433 case MSR_AMD64_VIRT_SPEC_CTRL:
6434 case MSR_AMD64_TSC_RATIO:
6435 /* This is AMD only. */
6442 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6447 bool idtv_info_valid;
6449 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6452 if (vmx->loaded_vmcs->nmi_known_unmasked)
6455 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6456 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6457 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6459 * SDM 3: 27.7.1.2 (September 2008)
6460 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6461 * a guest IRET fault.
6462 * SDM 3: 23.2.2 (September 2008)
6463 * Bit 12 is undefined in any of the following cases:
6464 * If the VM exit sets the valid bit in the IDT-vectoring
6465 * information field.
6466 * If the VM exit is due to a double fault.
6468 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6469 vector != DF_VECTOR && !idtv_info_valid)
6470 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6471 GUEST_INTR_STATE_NMI);
6473 vmx->loaded_vmcs->nmi_known_unmasked =
6474 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6475 & GUEST_INTR_STATE_NMI);
6476 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6477 vmx->loaded_vmcs->vnmi_blocked_time +=
6478 ktime_to_ns(ktime_sub(ktime_get(),
6479 vmx->loaded_vmcs->entry_time));
6482 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6483 u32 idt_vectoring_info,
6484 int instr_len_field,
6485 int error_code_field)
6489 bool idtv_info_valid;
6491 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6493 vcpu->arch.nmi_injected = false;
6494 kvm_clear_exception_queue(vcpu);
6495 kvm_clear_interrupt_queue(vcpu);
6497 if (!idtv_info_valid)
6500 kvm_make_request(KVM_REQ_EVENT, vcpu);
6502 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6503 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6506 case INTR_TYPE_NMI_INTR:
6507 vcpu->arch.nmi_injected = true;
6509 * SDM 3: 27.7.1.2 (September 2008)
6510 * Clear bit "block by NMI" before VM entry if a NMI
6513 vmx_set_nmi_mask(vcpu, false);
6515 case INTR_TYPE_SOFT_EXCEPTION:
6516 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6518 case INTR_TYPE_HARD_EXCEPTION:
6519 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6520 u32 err = vmcs_read32(error_code_field);
6521 kvm_requeue_exception_e(vcpu, vector, err);
6523 kvm_requeue_exception(vcpu, vector);
6525 case INTR_TYPE_SOFT_INTR:
6526 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6528 case INTR_TYPE_EXT_INTR:
6529 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6536 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6538 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6539 VM_EXIT_INSTRUCTION_LEN,
6540 IDT_VECTORING_ERROR_CODE);
6543 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6545 __vmx_complete_interrupts(vcpu,
6546 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6547 VM_ENTRY_INSTRUCTION_LEN,
6548 VM_ENTRY_EXCEPTION_ERROR_CODE);
6550 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6553 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6556 struct perf_guest_switch_msr *msrs;
6558 /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
6559 msrs = perf_guest_get_msrs(&nr_msrs);
6563 for (i = 0; i < nr_msrs; i++)
6564 if (msrs[i].host == msrs[i].guest)
6565 clear_atomic_switch_msr(vmx, msrs[i].msr);
6567 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6568 msrs[i].host, false);
6571 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6573 struct vcpu_vmx *vmx = to_vmx(vcpu);
6577 if (vmx->req_immediate_exit) {
6578 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6579 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6580 } else if (vmx->hv_deadline_tsc != -1) {
6582 if (vmx->hv_deadline_tsc > tscl)
6583 /* set_hv_timer ensures the delta fits in 32-bits */
6584 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6585 cpu_preemption_timer_multi);
6589 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6590 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6591 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6592 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6593 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6597 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6599 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6600 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6601 vmcs_writel(HOST_RSP, host_rsp);
6605 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6607 switch (to_vmx(vcpu)->exit_reason.basic) {
6608 case EXIT_REASON_MSR_WRITE:
6609 return handle_fastpath_set_msr_irqoff(vcpu);
6610 case EXIT_REASON_PREEMPTION_TIMER:
6611 return handle_fastpath_preemption_timer(vcpu);
6613 return EXIT_FASTPATH_NONE;
6617 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6618 struct vcpu_vmx *vmx)
6620 kvm_guest_enter_irqoff();
6622 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6623 if (static_branch_unlikely(&vmx_l1d_should_flush))
6624 vmx_l1d_flush(vcpu);
6625 else if (static_branch_unlikely(&mds_user_clear))
6626 mds_clear_cpu_buffers();
6628 if (vcpu->arch.cr2 != native_read_cr2())
6629 native_write_cr2(vcpu->arch.cr2);
6631 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6632 vmx->loaded_vmcs->launched);
6634 vcpu->arch.cr2 = native_read_cr2();
6636 kvm_guest_exit_irqoff();
6639 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6641 struct vcpu_vmx *vmx = to_vmx(vcpu);
6644 /* Record the guest's net vcpu time for enforced NMI injections. */
6645 if (unlikely(!enable_vnmi &&
6646 vmx->loaded_vmcs->soft_vnmi_blocked))
6647 vmx->loaded_vmcs->entry_time = ktime_get();
6650 * Don't enter VMX if guest state is invalid, let the exit handler
6651 * start emulation until we arrive back to a valid state. Synthesize a
6652 * consistency check VM-Exit due to invalid guest state and bail.
6654 if (unlikely(vmx->emulation_required)) {
6656 /* We don't emulate invalid state of a nested guest */
6657 vmx->fail = is_guest_mode(vcpu);
6659 vmx->exit_reason.full = EXIT_REASON_INVALID_STATE;
6660 vmx->exit_reason.failed_vmentry = 1;
6661 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
6662 vmx->exit_qualification = ENTRY_FAIL_DEFAULT;
6663 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
6664 vmx->exit_intr_info = 0;
6665 return EXIT_FASTPATH_NONE;
6668 trace_kvm_entry(vcpu);
6670 if (vmx->ple_window_dirty) {
6671 vmx->ple_window_dirty = false;
6672 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6676 * We did this in prepare_switch_to_guest, because it needs to
6677 * be within srcu_read_lock.
6679 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6681 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6682 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6683 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6684 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6685 vcpu->arch.regs_dirty = 0;
6687 cr4 = cr4_read_shadow();
6688 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6689 vmcs_writel(HOST_CR4, cr4);
6690 vmx->loaded_vmcs->host_state.cr4 = cr4;
6693 /* When KVM_DEBUGREG_WONT_EXIT, dr6 is accessible in guest. */
6694 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
6695 set_debugreg(vcpu->arch.dr6, 6);
6697 /* When single-stepping over STI and MOV SS, we must clear the
6698 * corresponding interruptibility bits in the guest state. Otherwise
6699 * vmentry fails as it then expects bit 14 (BS) in pending debug
6700 * exceptions being set, but that's not correct for the guest debugging
6702 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6703 vmx_set_interrupt_shadow(vcpu, 0);
6705 kvm_load_guest_xsave_state(vcpu);
6707 pt_guest_enter(vmx);
6709 atomic_switch_perf_msrs(vmx);
6710 if (intel_pmu_lbr_is_enabled(vcpu))
6711 vmx_passthrough_lbr_msrs(vcpu);
6713 if (enable_preemption_timer)
6714 vmx_update_hv_timer(vcpu);
6716 kvm_wait_lapic_expire(vcpu);
6719 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6720 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6721 * is no need to worry about the conditional branch over the wrmsr
6722 * being speculatively taken.
6724 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6726 /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6727 vmx_vcpu_enter_exit(vcpu, vmx);
6730 * We do not use IBRS in the kernel. If this vCPU has used the
6731 * SPEC_CTRL MSR it may have left it on; save the value and
6732 * turn it off. This is much more efficient than blindly adding
6733 * it to the atomic save/restore list. Especially as the former
6734 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6736 * For non-nested case:
6737 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6741 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6744 if (unlikely(!msr_write_intercepted(vmx, MSR_IA32_SPEC_CTRL)))
6745 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6747 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6749 /* All fields are clean at this point */
6750 if (static_branch_unlikely(&enable_evmcs)) {
6751 current_evmcs->hv_clean_fields |=
6752 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6754 current_evmcs->hv_vp_id = kvm_hv_get_vpindex(vcpu);
6757 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6758 if (vmx->host_debugctlmsr)
6759 update_debugctlmsr(vmx->host_debugctlmsr);
6761 #ifndef CONFIG_X86_64
6763 * The sysexit path does not restore ds/es, so we must set them to
6764 * a reasonable value ourselves.
6766 * We can't defer this to vmx_prepare_switch_to_host() since that
6767 * function may be executed in interrupt context, which saves and
6768 * restore segments around it, nullifying its effect.
6770 loadsegment(ds, __USER_DS);
6771 loadsegment(es, __USER_DS);
6774 vcpu->arch.regs_avail &= ~VMX_REGS_LAZY_LOAD_SET;
6778 kvm_load_host_xsave_state(vcpu);
6780 if (is_guest_mode(vcpu)) {
6782 * Track VMLAUNCH/VMRESUME that have made past guest state
6785 if (vmx->nested.nested_run_pending &&
6786 !vmx->exit_reason.failed_vmentry)
6787 ++vcpu->stat.nested_run;
6789 vmx->nested.nested_run_pending = 0;
6792 vmx->idt_vectoring_info = 0;
6794 if (unlikely(vmx->fail)) {
6795 vmx->exit_reason.full = 0xdead;
6796 return EXIT_FASTPATH_NONE;
6799 vmx->exit_reason.full = vmcs_read32(VM_EXIT_REASON);
6800 if (unlikely((u16)vmx->exit_reason.basic == EXIT_REASON_MCE_DURING_VMENTRY))
6801 kvm_machine_check();
6803 if (likely(!vmx->exit_reason.failed_vmentry))
6804 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6806 trace_kvm_exit(vcpu, KVM_ISA_VMX);
6808 if (unlikely(vmx->exit_reason.failed_vmentry))
6809 return EXIT_FASTPATH_NONE;
6811 vmx->loaded_vmcs->launched = 1;
6813 vmx_recover_nmi_blocking(vmx);
6814 vmx_complete_interrupts(vmx);
6816 if (is_guest_mode(vcpu))
6817 return EXIT_FASTPATH_NONE;
6819 return vmx_exit_handlers_fastpath(vcpu);
6822 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6824 struct vcpu_vmx *vmx = to_vmx(vcpu);
6827 vmx_destroy_pml_buffer(vmx);
6828 free_vpid(vmx->vpid);
6829 nested_vmx_free_vcpu(vcpu);
6830 free_loaded_vmcs(vmx->loaded_vmcs);
6833 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6835 struct vmx_uret_msr *tsx_ctrl;
6836 struct vcpu_vmx *vmx;
6839 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6844 vmx->vpid = allocate_vpid();
6847 * If PML is turned on, failure on enabling PML just results in failure
6848 * of creating the vcpu, therefore we can simplify PML logic (by
6849 * avoiding dealing with cases, such as enabling PML partially on vcpus
6850 * for the guest), etc.
6853 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6858 for (i = 0; i < kvm_nr_uret_msrs; ++i)
6859 vmx->guest_uret_msrs[i].mask = -1ull;
6860 if (boot_cpu_has(X86_FEATURE_RTM)) {
6862 * TSX_CTRL_CPUID_CLEAR is handled in the CPUID interception.
6863 * Keep the host value unchanged to avoid changing CPUID bits
6864 * under the host kernel's feet.
6866 tsx_ctrl = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
6868 tsx_ctrl->mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6871 err = alloc_loaded_vmcs(&vmx->vmcs01);
6876 * Use Hyper-V 'Enlightened MSR Bitmap' feature when KVM runs as a
6877 * nested (L1) hypervisor and Hyper-V in L0 supports it. Enable the
6878 * feature only for vmcs01, KVM currently isn't equipped to realize any
6879 * performance benefits from enabling it for vmcs02.
6881 if (IS_ENABLED(CONFIG_HYPERV) && static_branch_unlikely(&enable_evmcs) &&
6882 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
6883 struct hv_enlightened_vmcs *evmcs = (void *)vmx->vmcs01.vmcs;
6885 evmcs->hv_enlightenments_control.msr_bitmap = 1;
6888 /* The MSR bitmap starts with all ones */
6889 bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6890 bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6892 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
6893 #ifdef CONFIG_X86_64
6894 vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
6895 vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
6896 vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6898 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6899 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6900 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6901 if (kvm_cstate_in_guest(vcpu->kvm)) {
6902 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
6903 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6904 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6905 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6908 vmx->loaded_vmcs = &vmx->vmcs01;
6910 if (cpu_need_virtualize_apic_accesses(vcpu)) {
6911 err = alloc_apic_access_page(vcpu->kvm);
6916 if (enable_ept && !enable_unrestricted_guest) {
6917 err = init_rmode_identity_map(vcpu->kvm);
6925 free_loaded_vmcs(vmx->loaded_vmcs);
6927 vmx_destroy_pml_buffer(vmx);
6929 free_vpid(vmx->vpid);
6933 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6934 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6936 static int vmx_vm_init(struct kvm *kvm)
6939 kvm->arch.pause_in_guest = true;
6941 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6942 switch (l1tf_mitigation) {
6943 case L1TF_MITIGATION_OFF:
6944 case L1TF_MITIGATION_FLUSH_NOWARN:
6945 /* 'I explicitly don't care' is set */
6947 case L1TF_MITIGATION_FLUSH:
6948 case L1TF_MITIGATION_FLUSH_NOSMT:
6949 case L1TF_MITIGATION_FULL:
6951 * Warn upon starting the first VM in a potentially
6952 * insecure environment.
6954 if (sched_smt_active())
6955 pr_warn_once(L1TF_MSG_SMT);
6956 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6957 pr_warn_once(L1TF_MSG_L1D);
6959 case L1TF_MITIGATION_FULL_FORCE:
6960 /* Flush is enforced */
6967 static int __init vmx_check_processor_compat(void)
6969 struct vmcs_config vmcs_conf;
6970 struct vmx_capability vmx_cap;
6972 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6973 !this_cpu_has(X86_FEATURE_VMX)) {
6974 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6978 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6981 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6982 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6983 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6984 smp_processor_id());
6990 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6994 /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6995 * memory aliases with conflicting memory types and sometimes MCEs.
6996 * We have to be careful as to what are honored and when.
6998 * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to
6999 * UC. The effective memory type is UC or WC depending on guest PAT.
7000 * This was historically the source of MCEs and we want to be
7003 * When there is no need to deal with noncoherent DMA (e.g., no VT-d
7004 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The
7005 * EPT memory type is set to WB. The effective memory type is forced
7008 * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The
7009 * EPT memory type is used to emulate guest CD/MTRR.
7013 return MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7015 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm))
7016 return (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT) | VMX_EPT_IPAT_BIT;
7018 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
7019 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
7020 cache = MTRR_TYPE_WRBACK;
7022 cache = MTRR_TYPE_UNCACHABLE;
7024 return (cache << VMX_EPT_MT_EPTE_SHIFT) | VMX_EPT_IPAT_BIT;
7027 return kvm_mtrr_get_guest_memory_type(vcpu, gfn) << VMX_EPT_MT_EPTE_SHIFT;
7030 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx, u32 new_ctl)
7033 * These bits in the secondary execution controls field
7034 * are dynamic, the others are mostly based on the hypervisor
7035 * architecture and the guest's CPUID. Do not touch the
7039 SECONDARY_EXEC_SHADOW_VMCS |
7040 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7041 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7042 SECONDARY_EXEC_DESC;
7044 u32 cur_ctl = secondary_exec_controls_get(vmx);
7046 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7050 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7051 * (indicating "allowed-1") if they are supported in the guest's CPUID.
7053 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7055 struct vcpu_vmx *vmx = to_vmx(vcpu);
7056 struct kvm_cpuid_entry2 *entry;
7058 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7059 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7061 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
7062 if (entry && (entry->_reg & (_cpuid_mask))) \
7063 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
7066 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7067 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME));
7068 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME));
7069 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC));
7070 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE));
7071 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE));
7072 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE));
7073 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE));
7074 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE));
7075 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR));
7076 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7077 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX));
7078 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX));
7079 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID));
7080 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE));
7082 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7083 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE));
7084 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP));
7085 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP));
7086 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU));
7087 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP));
7088 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57));
7090 #undef cr4_fixed1_update
7093 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7095 struct vcpu_vmx *vmx = to_vmx(vcpu);
7097 if (kvm_mpx_supported()) {
7098 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7101 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7102 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7104 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7105 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7110 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7112 struct vcpu_vmx *vmx = to_vmx(vcpu);
7113 struct kvm_cpuid_entry2 *best = NULL;
7116 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7117 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7120 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7121 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7122 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7123 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7126 /* Get the number of configurable Address Ranges for filtering */
7127 vmx->pt_desc.num_address_ranges = intel_pt_validate_cap(vmx->pt_desc.caps,
7128 PT_CAP_num_address_ranges);
7130 /* Initialize and clear the no dependency bits */
7131 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7132 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC |
7133 RTIT_CTL_BRANCH_EN);
7136 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7137 * will inject an #GP
7139 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7140 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7143 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7144 * PSBFreq can be set
7146 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7147 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7148 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7151 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn and MTCFreq can be set
7153 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7154 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7155 RTIT_CTL_MTC_RANGE);
7157 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7158 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7159 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7162 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7163 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7164 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7166 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7167 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7168 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7170 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabricEn can be set */
7171 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7172 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7174 /* unmask address range configure area */
7175 for (i = 0; i < vmx->pt_desc.num_address_ranges; i++)
7176 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7179 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7181 struct vcpu_vmx *vmx = to_vmx(vcpu);
7183 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7184 vcpu->arch.xsaves_enabled = false;
7186 vmx_setup_uret_msrs(vmx);
7188 if (cpu_has_secondary_exec_ctrls())
7189 vmcs_set_secondary_exec_control(vmx,
7190 vmx_secondary_exec_control(vmx));
7192 if (nested_vmx_allowed(vcpu))
7193 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7194 FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7195 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7197 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7198 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7199 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7201 if (nested_vmx_allowed(vcpu)) {
7202 nested_vmx_cr_fixed1_bits_update(vcpu);
7203 nested_vmx_entry_exit_ctls_update(vcpu);
7206 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7207 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7208 update_intel_pt_cfg(vcpu);
7210 if (boot_cpu_has(X86_FEATURE_RTM)) {
7211 struct vmx_uret_msr *msr;
7212 msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
7214 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7215 vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7219 set_cr4_guest_host_mask(vmx);
7221 vmx_write_encls_bitmap(vcpu, NULL);
7222 if (guest_cpuid_has(vcpu, X86_FEATURE_SGX))
7223 vmx->msr_ia32_feature_control_valid_bits |= FEAT_CTL_SGX_ENABLED;
7225 vmx->msr_ia32_feature_control_valid_bits &= ~FEAT_CTL_SGX_ENABLED;
7227 if (guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
7228 vmx->msr_ia32_feature_control_valid_bits |=
7229 FEAT_CTL_SGX_LC_ENABLED;
7231 vmx->msr_ia32_feature_control_valid_bits &=
7232 ~FEAT_CTL_SGX_LC_ENABLED;
7234 /* Refresh #PF interception to account for MAXPHYADDR changes. */
7235 vmx_update_exception_bitmap(vcpu);
7238 static __init void vmx_set_cpu_caps(void)
7244 kvm_cpu_cap_set(X86_FEATURE_VMX);
7247 if (kvm_mpx_supported())
7248 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7249 if (!cpu_has_vmx_invpcid())
7250 kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
7251 if (vmx_pt_mode_is_host_guest())
7252 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7255 kvm_cpu_cap_clear(X86_FEATURE_SGX);
7256 kvm_cpu_cap_clear(X86_FEATURE_SGX_LC);
7257 kvm_cpu_cap_clear(X86_FEATURE_SGX1);
7258 kvm_cpu_cap_clear(X86_FEATURE_SGX2);
7261 if (vmx_umip_emulated())
7262 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7266 if (!cpu_has_vmx_xsaves())
7267 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7269 /* CPUID 0x80000001 and 0x7 (RDPID) */
7270 if (!cpu_has_vmx_rdtscp()) {
7271 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7272 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
7275 if (cpu_has_vmx_waitpkg())
7276 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7279 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7281 to_vmx(vcpu)->req_immediate_exit = true;
7284 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7285 struct x86_instruction_info *info)
7287 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7288 unsigned short port;
7292 if (info->intercept == x86_intercept_in ||
7293 info->intercept == x86_intercept_ins) {
7294 port = info->src_val;
7295 size = info->dst_bytes;
7297 port = info->dst_val;
7298 size = info->src_bytes;
7302 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7303 * VM-exits depend on the 'unconditional IO exiting' VM-execution
7306 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7308 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7309 intercept = nested_cpu_has(vmcs12,
7310 CPU_BASED_UNCOND_IO_EXITING);
7312 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7314 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7315 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7318 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7319 struct x86_instruction_info *info,
7320 enum x86_intercept_stage stage,
7321 struct x86_exception *exception)
7323 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7325 switch (info->intercept) {
7327 * RDPID causes #UD if disabled through secondary execution controls.
7328 * Because it is marked as EmulateOnUD, we need to intercept it here.
7329 * Note, RDPID is hidden behind ENABLE_RDTSCP.
7331 case x86_intercept_rdpid:
7332 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) {
7333 exception->vector = UD_VECTOR;
7334 exception->error_code_valid = false;
7335 return X86EMUL_PROPAGATE_FAULT;
7339 case x86_intercept_in:
7340 case x86_intercept_ins:
7341 case x86_intercept_out:
7342 case x86_intercept_outs:
7343 return vmx_check_intercept_io(vcpu, info);
7345 case x86_intercept_lgdt:
7346 case x86_intercept_lidt:
7347 case x86_intercept_lldt:
7348 case x86_intercept_ltr:
7349 case x86_intercept_sgdt:
7350 case x86_intercept_sidt:
7351 case x86_intercept_sldt:
7352 case x86_intercept_str:
7353 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7354 return X86EMUL_CONTINUE;
7356 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7359 /* TODO: check more intercepts... */
7364 return X86EMUL_UNHANDLEABLE;
7367 #ifdef CONFIG_X86_64
7368 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7369 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7370 u64 divisor, u64 *result)
7372 u64 low = a << shift, high = a >> (64 - shift);
7374 /* To avoid the overflow on divq */
7375 if (high >= divisor)
7378 /* Low hold the result, high hold rem which is discarded */
7379 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7380 "rm" (divisor), "0" (low), "1" (high));
7386 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7389 struct vcpu_vmx *vmx;
7390 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7391 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7395 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7396 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7397 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7398 ktimer->timer_advance_ns);
7400 if (delta_tsc > lapic_timer_advance_cycles)
7401 delta_tsc -= lapic_timer_advance_cycles;
7405 /* Convert to host delta tsc if tsc scaling is enabled */
7406 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7407 delta_tsc && u64_shl_div_u64(delta_tsc,
7408 kvm_tsc_scaling_ratio_frac_bits,
7409 vcpu->arch.l1_tsc_scaling_ratio, &delta_tsc))
7413 * If the delta tsc can't fit in the 32 bit after the multi shift,
7414 * we can't use the preemption timer.
7415 * It's possible that it fits on later vmentries, but checking
7416 * on every vmentry is costly so we just use an hrtimer.
7418 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7421 vmx->hv_deadline_tsc = tscl + delta_tsc;
7422 *expired = !delta_tsc;
7426 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7428 to_vmx(vcpu)->hv_deadline_tsc = -1;
7432 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7434 if (!kvm_pause_in_guest(vcpu->kvm))
7435 shrink_ple_window(vcpu);
7438 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu)
7440 struct vcpu_vmx *vmx = to_vmx(vcpu);
7442 if (is_guest_mode(vcpu)) {
7443 vmx->nested.update_vmcs01_cpu_dirty_logging = true;
7448 * Note, cpu_dirty_logging_count can be changed concurrent with this
7449 * code, but in that case another update request will be made and so
7450 * the guest will never run with a stale PML value.
7452 if (vcpu->kvm->arch.cpu_dirty_logging_count)
7453 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7455 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7458 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7460 if (pi_pre_block(vcpu))
7463 if (kvm_lapic_hv_timer_in_use(vcpu))
7464 kvm_lapic_switch_to_sw_timer(vcpu);
7469 static void vmx_post_block(struct kvm_vcpu *vcpu)
7471 if (kvm_x86_ops.set_hv_timer)
7472 kvm_lapic_switch_to_hv_timer(vcpu);
7474 pi_post_block(vcpu);
7477 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7479 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7480 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7481 FEAT_CTL_LMCE_ENABLED;
7483 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7484 ~FEAT_CTL_LMCE_ENABLED;
7487 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7489 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7490 if (to_vmx(vcpu)->nested.nested_run_pending)
7492 return !is_smm(vcpu);
7495 static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7497 struct vcpu_vmx *vmx = to_vmx(vcpu);
7499 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7500 if (vmx->nested.smm.guest_mode)
7501 nested_vmx_vmexit(vcpu, -1, 0, 0);
7503 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7504 vmx->nested.vmxon = false;
7505 vmx_clear_hlt(vcpu);
7509 static int vmx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7511 struct vcpu_vmx *vmx = to_vmx(vcpu);
7514 if (vmx->nested.smm.vmxon) {
7515 vmx->nested.vmxon = true;
7516 vmx->nested.smm.vmxon = false;
7519 if (vmx->nested.smm.guest_mode) {
7520 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7524 vmx->nested.smm.guest_mode = false;
7529 static void vmx_enable_smi_window(struct kvm_vcpu *vcpu)
7531 /* RSM will cause a vmexit anyway. */
7534 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7536 return to_vmx(vcpu)->nested.vmxon && !is_guest_mode(vcpu);
7539 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7541 if (is_guest_mode(vcpu)) {
7542 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7544 if (hrtimer_try_to_cancel(timer) == 1)
7545 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7549 static void hardware_unsetup(void)
7551 kvm_set_posted_intr_wakeup_handler(NULL);
7554 nested_vmx_hardware_unsetup();
7559 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7561 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7562 BIT(APICV_INHIBIT_REASON_ABSENT) |
7563 BIT(APICV_INHIBIT_REASON_HYPERV) |
7564 BIT(APICV_INHIBIT_REASON_BLOCKIRQ);
7566 return supported & BIT(bit);
7569 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7570 .name = "kvm_intel",
7572 .hardware_unsetup = hardware_unsetup,
7574 .hardware_enable = hardware_enable,
7575 .hardware_disable = hardware_disable,
7576 .cpu_has_accelerated_tpr = report_flexpriority,
7577 .has_emulated_msr = vmx_has_emulated_msr,
7579 .vm_size = sizeof(struct kvm_vmx),
7580 .vm_init = vmx_vm_init,
7582 .vcpu_create = vmx_create_vcpu,
7583 .vcpu_free = vmx_free_vcpu,
7584 .vcpu_reset = vmx_vcpu_reset,
7586 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7587 .vcpu_load = vmx_vcpu_load,
7588 .vcpu_put = vmx_vcpu_put,
7590 .update_exception_bitmap = vmx_update_exception_bitmap,
7591 .get_msr_feature = vmx_get_msr_feature,
7592 .get_msr = vmx_get_msr,
7593 .set_msr = vmx_set_msr,
7594 .get_segment_base = vmx_get_segment_base,
7595 .get_segment = vmx_get_segment,
7596 .set_segment = vmx_set_segment,
7597 .get_cpl = vmx_get_cpl,
7598 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7599 .set_cr0 = vmx_set_cr0,
7600 .is_valid_cr4 = vmx_is_valid_cr4,
7601 .set_cr4 = vmx_set_cr4,
7602 .set_efer = vmx_set_efer,
7603 .get_idt = vmx_get_idt,
7604 .set_idt = vmx_set_idt,
7605 .get_gdt = vmx_get_gdt,
7606 .set_gdt = vmx_set_gdt,
7607 .set_dr7 = vmx_set_dr7,
7608 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7609 .cache_reg = vmx_cache_reg,
7610 .get_rflags = vmx_get_rflags,
7611 .set_rflags = vmx_set_rflags,
7613 .tlb_flush_all = vmx_flush_tlb_all,
7614 .tlb_flush_current = vmx_flush_tlb_current,
7615 .tlb_flush_gva = vmx_flush_tlb_gva,
7616 .tlb_flush_guest = vmx_flush_tlb_guest,
7618 .run = vmx_vcpu_run,
7619 .handle_exit = vmx_handle_exit,
7620 .skip_emulated_instruction = vmx_skip_emulated_instruction,
7621 .update_emulated_instruction = vmx_update_emulated_instruction,
7622 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7623 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7624 .patch_hypercall = vmx_patch_hypercall,
7625 .set_irq = vmx_inject_irq,
7626 .set_nmi = vmx_inject_nmi,
7627 .queue_exception = vmx_queue_exception,
7628 .cancel_injection = vmx_cancel_injection,
7629 .interrupt_allowed = vmx_interrupt_allowed,
7630 .nmi_allowed = vmx_nmi_allowed,
7631 .get_nmi_mask = vmx_get_nmi_mask,
7632 .set_nmi_mask = vmx_set_nmi_mask,
7633 .enable_nmi_window = vmx_enable_nmi_window,
7634 .enable_irq_window = vmx_enable_irq_window,
7635 .update_cr8_intercept = vmx_update_cr8_intercept,
7636 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7637 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7638 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7639 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7640 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7641 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7642 .hwapic_irr_update = vmx_hwapic_irr_update,
7643 .hwapic_isr_update = vmx_hwapic_isr_update,
7644 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7645 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7646 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7647 .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
7649 .set_tss_addr = vmx_set_tss_addr,
7650 .set_identity_map_addr = vmx_set_identity_map_addr,
7651 .get_mt_mask = vmx_get_mt_mask,
7653 .get_exit_info = vmx_get_exit_info,
7655 .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7657 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7659 .get_l2_tsc_offset = vmx_get_l2_tsc_offset,
7660 .get_l2_tsc_multiplier = vmx_get_l2_tsc_multiplier,
7661 .write_tsc_offset = vmx_write_tsc_offset,
7662 .write_tsc_multiplier = vmx_write_tsc_multiplier,
7664 .load_mmu_pgd = vmx_load_mmu_pgd,
7666 .check_intercept = vmx_check_intercept,
7667 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7669 .request_immediate_exit = vmx_request_immediate_exit,
7671 .sched_in = vmx_sched_in,
7673 .cpu_dirty_log_size = PML_ENTITY_NUM,
7674 .update_cpu_dirty_logging = vmx_update_cpu_dirty_logging,
7676 .pre_block = vmx_pre_block,
7677 .post_block = vmx_post_block,
7679 .pmu_ops = &intel_pmu_ops,
7680 .nested_ops = &vmx_nested_ops,
7682 .update_pi_irte = pi_update_irte,
7683 .start_assignment = vmx_pi_start_assignment,
7685 #ifdef CONFIG_X86_64
7686 .set_hv_timer = vmx_set_hv_timer,
7687 .cancel_hv_timer = vmx_cancel_hv_timer,
7690 .setup_mce = vmx_setup_mce,
7692 .smi_allowed = vmx_smi_allowed,
7693 .enter_smm = vmx_enter_smm,
7694 .leave_smm = vmx_leave_smm,
7695 .enable_smi_window = vmx_enable_smi_window,
7697 .can_emulate_instruction = vmx_can_emulate_instruction,
7698 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7699 .migrate_timers = vmx_migrate_timers,
7701 .msr_filter_changed = vmx_msr_filter_changed,
7702 .complete_emulated_msr = kvm_complete_insn_gp,
7704 .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector,
7707 static __init void vmx_setup_user_return_msrs(void)
7711 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
7712 * will emulate SYSCALL in legacy mode if the vendor string in guest
7713 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
7714 * support this emulation, MSR_STAR is included in the list for i386,
7715 * but is never loaded into hardware. MSR_CSTAR is also never loaded
7716 * into hardware and is here purely for emulation purposes.
7718 const u32 vmx_uret_msrs_list[] = {
7719 #ifdef CONFIG_X86_64
7720 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
7722 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
7727 BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
7729 for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
7730 kvm_add_user_return_msr(vmx_uret_msrs_list[i]);
7733 static __init int hardware_setup(void)
7735 unsigned long host_bndcfgs;
7740 host_idt_base = dt.address;
7742 vmx_setup_user_return_msrs();
7744 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7747 if (boot_cpu_has(X86_FEATURE_NX))
7748 kvm_enable_efer_bits(EFER_NX);
7750 if (boot_cpu_has(X86_FEATURE_MPX)) {
7751 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7752 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7755 if (!cpu_has_vmx_mpx())
7756 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7757 XFEATURE_MASK_BNDCSR);
7759 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7760 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7763 if (!cpu_has_vmx_ept() ||
7764 !cpu_has_vmx_ept_4levels() ||
7765 !cpu_has_vmx_ept_mt_wb() ||
7766 !cpu_has_vmx_invept_global())
7769 /* NX support is required for shadow paging. */
7770 if (!enable_ept && !boot_cpu_has(X86_FEATURE_NX)) {
7771 pr_err_ratelimited("kvm: NX (Execute Disable) not supported\n");
7775 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7776 enable_ept_ad_bits = 0;
7778 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7779 enable_unrestricted_guest = 0;
7781 if (!cpu_has_vmx_flexpriority())
7782 flexpriority_enabled = 0;
7784 if (!cpu_has_virtual_nmis())
7788 * set_apic_access_page_addr() is used to reload apic access
7789 * page upon invalidation. No need to do anything if not
7790 * using the APIC_ACCESS_ADDR VMCS field.
7792 if (!flexpriority_enabled)
7793 vmx_x86_ops.set_apic_access_page_addr = NULL;
7795 if (!cpu_has_vmx_tpr_shadow())
7796 vmx_x86_ops.update_cr8_intercept = NULL;
7798 #if IS_ENABLED(CONFIG_HYPERV)
7799 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7801 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7802 vmx_x86_ops.tlb_remote_flush_with_range =
7803 hv_remote_flush_tlb_with_range;
7807 if (!cpu_has_vmx_ple()) {
7810 ple_window_grow = 0;
7812 ple_window_shrink = 0;
7815 if (!cpu_has_vmx_apicv())
7818 vmx_x86_ops.sync_pir_to_irr = NULL;
7820 if (cpu_has_vmx_tsc_scaling()) {
7821 kvm_has_tsc_control = true;
7822 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7823 kvm_tsc_scaling_ratio_frac_bits = 48;
7826 kvm_has_bus_lock_exit = cpu_has_vmx_bus_lock_detection();
7828 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7831 kvm_mmu_set_ept_masks(enable_ept_ad_bits,
7832 cpu_has_vmx_ept_execute_only());
7834 kvm_configure_mmu(enable_ept, 0, vmx_get_max_tdp_level(),
7835 ept_caps_to_lpage_level(vmx_capability.ept));
7838 * Only enable PML when hardware supports PML feature, and both EPT
7839 * and EPT A/D bit features are enabled -- PML depends on them to work.
7841 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7845 vmx_x86_ops.cpu_dirty_log_size = 0;
7847 if (!cpu_has_vmx_preemption_timer())
7848 enable_preemption_timer = false;
7850 if (enable_preemption_timer) {
7851 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7854 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7855 cpu_preemption_timer_multi =
7856 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7859 use_timer_freq = (u64)tsc_khz * 1000;
7860 use_timer_freq >>= cpu_preemption_timer_multi;
7863 * KVM "disables" the preemption timer by setting it to its max
7864 * value. Don't use the timer if it might cause spurious exits
7865 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7867 if (use_timer_freq > 0xffffffffu / 10)
7868 enable_preemption_timer = false;
7871 if (!enable_preemption_timer) {
7872 vmx_x86_ops.set_hv_timer = NULL;
7873 vmx_x86_ops.cancel_hv_timer = NULL;
7874 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
7877 kvm_mce_cap_supported |= MCG_LMCE_P;
7879 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7881 if (!enable_ept || !cpu_has_vmx_intel_pt())
7882 pt_mode = PT_MODE_SYSTEM;
7884 setup_default_sgx_lepubkeyhash();
7887 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7888 vmx_capability.ept);
7890 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7897 r = alloc_kvm_area();
7899 nested_vmx_hardware_unsetup();
7901 kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler);
7906 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
7907 .cpu_has_kvm_support = cpu_has_kvm_support,
7908 .disabled_by_bios = vmx_disabled_by_bios,
7909 .check_processor_compatibility = vmx_check_processor_compat,
7910 .hardware_setup = hardware_setup,
7912 .runtime_ops = &vmx_x86_ops,
7915 static void vmx_cleanup_l1d_flush(void)
7917 if (vmx_l1d_flush_pages) {
7918 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7919 vmx_l1d_flush_pages = NULL;
7921 /* Restore state so sysfs ignores VMX */
7922 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7925 static void vmx_exit(void)
7927 #ifdef CONFIG_KEXEC_CORE
7928 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7934 #if IS_ENABLED(CONFIG_HYPERV)
7935 if (static_branch_unlikely(&enable_evmcs)) {
7937 struct hv_vp_assist_page *vp_ap;
7939 * Reset everything to support using non-enlightened VMCS
7940 * access later (e.g. when we reload the module with
7941 * enlightened_vmcs=0)
7943 for_each_online_cpu(cpu) {
7944 vp_ap = hv_get_vp_assist_page(cpu);
7949 vp_ap->nested_control.features.directhypercall = 0;
7950 vp_ap->current_nested_vmcs = 0;
7951 vp_ap->enlighten_vmentry = 0;
7954 static_branch_disable(&enable_evmcs);
7957 vmx_cleanup_l1d_flush();
7959 allow_smaller_maxphyaddr = false;
7961 module_exit(vmx_exit);
7963 static int __init vmx_init(void)
7967 #if IS_ENABLED(CONFIG_HYPERV)
7969 * Enlightened VMCS usage should be recommended and the host needs
7970 * to support eVMCS v1 or above. We can also disable eVMCS support
7971 * with module parameter.
7973 if (enlightened_vmcs &&
7974 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7975 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7976 KVM_EVMCS_VERSION) {
7979 /* Check that we have assist pages on all online CPUs */
7980 for_each_online_cpu(cpu) {
7981 if (!hv_get_vp_assist_page(cpu)) {
7982 enlightened_vmcs = false;
7987 if (enlightened_vmcs) {
7988 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7989 static_branch_enable(&enable_evmcs);
7992 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7993 vmx_x86_ops.enable_direct_tlbflush
7994 = hv_enable_direct_tlbflush;
7997 enlightened_vmcs = false;
8001 r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
8002 __alignof__(struct vcpu_vmx), THIS_MODULE);
8007 * Must be called after kvm_init() so enable_ept is properly set
8008 * up. Hand the parameter mitigation value in which was stored in
8009 * the pre module init parser. If no parameter was given, it will
8010 * contain 'auto' which will be turned into the default 'cond'
8013 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8019 for_each_possible_cpu(cpu) {
8020 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8025 #ifdef CONFIG_KEXEC_CORE
8026 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8027 crash_vmclear_local_loaded_vmcss);
8029 vmx_check_vmcs12_offsets();
8032 * Shadow paging doesn't have a (further) performance penalty
8033 * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it
8037 allow_smaller_maxphyaddr = true;
8041 module_init(vmx_init);