KVM: VMX: Don't redo x2APIC MSR bitmaps when userspace filter is changed
[linux-2.6-microblaze.git] / arch / x86 / kvm / vmx / vmx.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Kernel-based Virtual Machine driver for Linux
4  *
5  * This module enables machines with Intel VT-x extensions to run virtual
6  * machines without emulation or binary translation.
7  *
8  * Copyright (C) 2006 Qumranet, Inc.
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  */
15
16 #include <linux/highmem.h>
17 #include <linux/hrtimer.h>
18 #include <linux/kernel.h>
19 #include <linux/kvm_host.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/mm.h>
24 #include <linux/objtool.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
30 #include <linux/entry-kvm.h>
31
32 #include <asm/apic.h>
33 #include <asm/asm.h>
34 #include <asm/cpu.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/debugreg.h>
37 #include <asm/desc.h>
38 #include <asm/fpu/internal.h>
39 #include <asm/idtentry.h>
40 #include <asm/io.h>
41 #include <asm/irq_remapping.h>
42 #include <asm/kexec.h>
43 #include <asm/perf_event.h>
44 #include <asm/mmu_context.h>
45 #include <asm/mshyperv.h>
46 #include <asm/mwait.h>
47 #include <asm/spec-ctrl.h>
48 #include <asm/virtext.h>
49 #include <asm/vmx.h>
50
51 #include "capabilities.h"
52 #include "cpuid.h"
53 #include "evmcs.h"
54 #include "hyperv.h"
55 #include "kvm_onhyperv.h"
56 #include "irq.h"
57 #include "kvm_cache_regs.h"
58 #include "lapic.h"
59 #include "mmu.h"
60 #include "nested.h"
61 #include "pmu.h"
62 #include "sgx.h"
63 #include "trace.h"
64 #include "vmcs.h"
65 #include "vmcs12.h"
66 #include "vmx.h"
67 #include "x86.h"
68
69 MODULE_AUTHOR("Qumranet");
70 MODULE_LICENSE("GPL");
71
72 #ifdef MODULE
73 static const struct x86_cpu_id vmx_cpu_id[] = {
74         X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
75         {}
76 };
77 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
78 #endif
79
80 bool __read_mostly enable_vpid = 1;
81 module_param_named(vpid, enable_vpid, bool, 0444);
82
83 static bool __read_mostly enable_vnmi = 1;
84 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
85
86 bool __read_mostly flexpriority_enabled = 1;
87 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
88
89 bool __read_mostly enable_ept = 1;
90 module_param_named(ept, enable_ept, bool, S_IRUGO);
91
92 bool __read_mostly enable_unrestricted_guest = 1;
93 module_param_named(unrestricted_guest,
94                         enable_unrestricted_guest, bool, S_IRUGO);
95
96 bool __read_mostly enable_ept_ad_bits = 1;
97 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
98
99 static bool __read_mostly emulate_invalid_guest_state = true;
100 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
101
102 static bool __read_mostly fasteoi = 1;
103 module_param(fasteoi, bool, S_IRUGO);
104
105 module_param(enable_apicv, bool, S_IRUGO);
106
107 /*
108  * If nested=1, nested virtualization is supported, i.e., guests may use
109  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
110  * use VMX instructions.
111  */
112 static bool __read_mostly nested = 1;
113 module_param(nested, bool, S_IRUGO);
114
115 bool __read_mostly enable_pml = 1;
116 module_param_named(pml, enable_pml, bool, S_IRUGO);
117
118 static bool __read_mostly dump_invalid_vmcs = 0;
119 module_param(dump_invalid_vmcs, bool, 0644);
120
121 #define MSR_BITMAP_MODE_X2APIC          1
122 #define MSR_BITMAP_MODE_X2APIC_APICV    2
123
124 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
125
126 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
127 static int __read_mostly cpu_preemption_timer_multi;
128 static bool __read_mostly enable_preemption_timer = 1;
129 #ifdef CONFIG_X86_64
130 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
131 #endif
132
133 extern bool __read_mostly allow_smaller_maxphyaddr;
134 module_param(allow_smaller_maxphyaddr, bool, S_IRUGO);
135
136 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
137 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
138 #define KVM_VM_CR0_ALWAYS_ON                            \
139         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
140
141 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
142 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
143 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
144
145 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
146
147 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
148         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
149         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
150         RTIT_STATUS_BYTECNT))
151
152 /*
153  * List of MSRs that can be directly passed to the guest.
154  * In addition to these x2apic and PT MSRs are handled specially.
155  */
156 static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = {
157         MSR_IA32_SPEC_CTRL,
158         MSR_IA32_PRED_CMD,
159         MSR_IA32_TSC,
160 #ifdef CONFIG_X86_64
161         MSR_FS_BASE,
162         MSR_GS_BASE,
163         MSR_KERNEL_GS_BASE,
164 #endif
165         MSR_IA32_SYSENTER_CS,
166         MSR_IA32_SYSENTER_ESP,
167         MSR_IA32_SYSENTER_EIP,
168         MSR_CORE_C1_RES,
169         MSR_CORE_C3_RESIDENCY,
170         MSR_CORE_C6_RESIDENCY,
171         MSR_CORE_C7_RESIDENCY,
172 };
173
174 /*
175  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
176  * ple_gap:    upper bound on the amount of time between two successive
177  *             executions of PAUSE in a loop. Also indicate if ple enabled.
178  *             According to test, this time is usually smaller than 128 cycles.
179  * ple_window: upper bound on the amount of time a guest is allowed to execute
180  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
181  *             less than 2^12 cycles
182  * Time is measured based on a counter that runs at the same rate as the TSC,
183  * refer SDM volume 3b section 21.6.13 & 22.1.3.
184  */
185 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
186 module_param(ple_gap, uint, 0444);
187
188 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
189 module_param(ple_window, uint, 0444);
190
191 /* Default doubles per-vcpu window every exit. */
192 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
193 module_param(ple_window_grow, uint, 0444);
194
195 /* Default resets per-vcpu window every exit to ple_window. */
196 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
197 module_param(ple_window_shrink, uint, 0444);
198
199 /* Default is to compute the maximum so we can never overflow. */
200 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
201 module_param(ple_window_max, uint, 0444);
202
203 /* Default is SYSTEM mode, 1 for host-guest mode */
204 int __read_mostly pt_mode = PT_MODE_SYSTEM;
205 module_param(pt_mode, int, S_IRUGO);
206
207 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
208 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
209 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
210
211 /* Storage for pre module init parameter parsing */
212 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
213
214 static const struct {
215         const char *option;
216         bool for_parse;
217 } vmentry_l1d_param[] = {
218         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
219         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
220         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
221         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
222         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
223         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
224 };
225
226 #define L1D_CACHE_ORDER 4
227 static void *vmx_l1d_flush_pages;
228
229 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
230 {
231         struct page *page;
232         unsigned int i;
233
234         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
235                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
236                 return 0;
237         }
238
239         if (!enable_ept) {
240                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
241                 return 0;
242         }
243
244         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
245                 u64 msr;
246
247                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
248                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
249                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
250                         return 0;
251                 }
252         }
253
254         /* If set to auto use the default l1tf mitigation method */
255         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
256                 switch (l1tf_mitigation) {
257                 case L1TF_MITIGATION_OFF:
258                         l1tf = VMENTER_L1D_FLUSH_NEVER;
259                         break;
260                 case L1TF_MITIGATION_FLUSH_NOWARN:
261                 case L1TF_MITIGATION_FLUSH:
262                 case L1TF_MITIGATION_FLUSH_NOSMT:
263                         l1tf = VMENTER_L1D_FLUSH_COND;
264                         break;
265                 case L1TF_MITIGATION_FULL:
266                 case L1TF_MITIGATION_FULL_FORCE:
267                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
268                         break;
269                 }
270         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
271                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
272         }
273
274         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
275             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
276                 /*
277                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
278                  * lifetime and so should not be charged to a memcg.
279                  */
280                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
281                 if (!page)
282                         return -ENOMEM;
283                 vmx_l1d_flush_pages = page_address(page);
284
285                 /*
286                  * Initialize each page with a different pattern in
287                  * order to protect against KSM in the nested
288                  * virtualization case.
289                  */
290                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
291                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
292                                PAGE_SIZE);
293                 }
294         }
295
296         l1tf_vmx_mitigation = l1tf;
297
298         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
299                 static_branch_enable(&vmx_l1d_should_flush);
300         else
301                 static_branch_disable(&vmx_l1d_should_flush);
302
303         if (l1tf == VMENTER_L1D_FLUSH_COND)
304                 static_branch_enable(&vmx_l1d_flush_cond);
305         else
306                 static_branch_disable(&vmx_l1d_flush_cond);
307         return 0;
308 }
309
310 static int vmentry_l1d_flush_parse(const char *s)
311 {
312         unsigned int i;
313
314         if (s) {
315                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
316                         if (vmentry_l1d_param[i].for_parse &&
317                             sysfs_streq(s, vmentry_l1d_param[i].option))
318                                 return i;
319                 }
320         }
321         return -EINVAL;
322 }
323
324 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
325 {
326         int l1tf, ret;
327
328         l1tf = vmentry_l1d_flush_parse(s);
329         if (l1tf < 0)
330                 return l1tf;
331
332         if (!boot_cpu_has(X86_BUG_L1TF))
333                 return 0;
334
335         /*
336          * Has vmx_init() run already? If not then this is the pre init
337          * parameter parsing. In that case just store the value and let
338          * vmx_init() do the proper setup after enable_ept has been
339          * established.
340          */
341         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
342                 vmentry_l1d_flush_param = l1tf;
343                 return 0;
344         }
345
346         mutex_lock(&vmx_l1d_flush_mutex);
347         ret = vmx_setup_l1d_flush(l1tf);
348         mutex_unlock(&vmx_l1d_flush_mutex);
349         return ret;
350 }
351
352 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
353 {
354         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
355                 return sprintf(s, "???\n");
356
357         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
358 }
359
360 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
361         .set = vmentry_l1d_flush_set,
362         .get = vmentry_l1d_flush_get,
363 };
364 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
365
366 static u32 vmx_segment_access_rights(struct kvm_segment *var);
367
368 void vmx_vmexit(void);
369
370 #define vmx_insn_failed(fmt...)         \
371 do {                                    \
372         WARN_ONCE(1, fmt);              \
373         pr_warn_ratelimited(fmt);       \
374 } while (0)
375
376 asmlinkage void vmread_error(unsigned long field, bool fault)
377 {
378         if (fault)
379                 kvm_spurious_fault();
380         else
381                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
382 }
383
384 noinline void vmwrite_error(unsigned long field, unsigned long value)
385 {
386         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
387                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
388 }
389
390 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
391 {
392         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
393 }
394
395 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
396 {
397         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
398 }
399
400 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
401 {
402         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
403                         ext, vpid, gva);
404 }
405
406 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
407 {
408         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
409                         ext, eptp, gpa);
410 }
411
412 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
413 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
414 /*
415  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
416  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
417  */
418 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
419
420 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
421 static DEFINE_SPINLOCK(vmx_vpid_lock);
422
423 struct vmcs_config vmcs_config;
424 struct vmx_capability vmx_capability;
425
426 #define VMX_SEGMENT_FIELD(seg)                                  \
427         [VCPU_SREG_##seg] = {                                   \
428                 .selector = GUEST_##seg##_SELECTOR,             \
429                 .base = GUEST_##seg##_BASE,                     \
430                 .limit = GUEST_##seg##_LIMIT,                   \
431                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
432         }
433
434 static const struct kvm_vmx_segment_field {
435         unsigned selector;
436         unsigned base;
437         unsigned limit;
438         unsigned ar_bytes;
439 } kvm_vmx_segment_fields[] = {
440         VMX_SEGMENT_FIELD(CS),
441         VMX_SEGMENT_FIELD(DS),
442         VMX_SEGMENT_FIELD(ES),
443         VMX_SEGMENT_FIELD(FS),
444         VMX_SEGMENT_FIELD(GS),
445         VMX_SEGMENT_FIELD(SS),
446         VMX_SEGMENT_FIELD(TR),
447         VMX_SEGMENT_FIELD(LDTR),
448 };
449
450 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
451 {
452         vmx->segment_cache.bitmask = 0;
453 }
454
455 static unsigned long host_idt_base;
456
457 #if IS_ENABLED(CONFIG_HYPERV)
458 static bool __read_mostly enlightened_vmcs = true;
459 module_param(enlightened_vmcs, bool, 0444);
460
461 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
462 {
463         struct hv_enlightened_vmcs *evmcs;
464         struct hv_partition_assist_pg **p_hv_pa_pg =
465                         &to_kvm_hv(vcpu->kvm)->hv_pa_pg;
466         /*
467          * Synthetic VM-Exit is not enabled in current code and so All
468          * evmcs in singe VM shares same assist page.
469          */
470         if (!*p_hv_pa_pg)
471                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
472
473         if (!*p_hv_pa_pg)
474                 return -ENOMEM;
475
476         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
477
478         evmcs->partition_assist_page =
479                 __pa(*p_hv_pa_pg);
480         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
481         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
482
483         return 0;
484 }
485
486 #endif /* IS_ENABLED(CONFIG_HYPERV) */
487
488 /*
489  * Comment's format: document - errata name - stepping - processor name.
490  * Refer from
491  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
492  */
493 static u32 vmx_preemption_cpu_tfms[] = {
494 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
495 0x000206E6,
496 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
497 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
498 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
499 0x00020652,
500 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
501 0x00020655,
502 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
503 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
504 /*
505  * 320767.pdf - AAP86  - B1 -
506  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
507  */
508 0x000106E5,
509 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
510 0x000106A0,
511 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
512 0x000106A1,
513 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
514 0x000106A4,
515  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
516  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
517  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
518 0x000106A5,
519  /* Xeon E3-1220 V2 */
520 0x000306A8,
521 };
522
523 static inline bool cpu_has_broken_vmx_preemption_timer(void)
524 {
525         u32 eax = cpuid_eax(0x00000001), i;
526
527         /* Clear the reserved bits */
528         eax &= ~(0x3U << 14 | 0xfU << 28);
529         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
530                 if (eax == vmx_preemption_cpu_tfms[i])
531                         return true;
532
533         return false;
534 }
535
536 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
537 {
538         return flexpriority_enabled && lapic_in_kernel(vcpu);
539 }
540
541 static inline bool report_flexpriority(void)
542 {
543         return flexpriority_enabled;
544 }
545
546 static int possible_passthrough_msr_slot(u32 msr)
547 {
548         u32 i;
549
550         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++)
551                 if (vmx_possible_passthrough_msrs[i] == msr)
552                         return i;
553
554         return -ENOENT;
555 }
556
557 static bool is_valid_passthrough_msr(u32 msr)
558 {
559         bool r;
560
561         switch (msr) {
562         case 0x800 ... 0x8ff:
563                 /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */
564                 return true;
565         case MSR_IA32_RTIT_STATUS:
566         case MSR_IA32_RTIT_OUTPUT_BASE:
567         case MSR_IA32_RTIT_OUTPUT_MASK:
568         case MSR_IA32_RTIT_CR3_MATCH:
569         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
570                 /* PT MSRs. These are handled in pt_update_intercept_for_msr() */
571         case MSR_LBR_SELECT:
572         case MSR_LBR_TOS:
573         case MSR_LBR_INFO_0 ... MSR_LBR_INFO_0 + 31:
574         case MSR_LBR_NHM_FROM ... MSR_LBR_NHM_FROM + 31:
575         case MSR_LBR_NHM_TO ... MSR_LBR_NHM_TO + 31:
576         case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8:
577         case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8:
578                 /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */
579                 return true;
580         }
581
582         r = possible_passthrough_msr_slot(msr) != -ENOENT;
583
584         WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr);
585
586         return r;
587 }
588
589 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
590 {
591         int i;
592
593         i = kvm_find_user_return_msr(msr);
594         if (i >= 0)
595                 return &vmx->guest_uret_msrs[i];
596         return NULL;
597 }
598
599 static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx,
600                                   struct vmx_uret_msr *msr, u64 data)
601 {
602         unsigned int slot = msr - vmx->guest_uret_msrs;
603         int ret = 0;
604
605         u64 old_msr_data = msr->data;
606         msr->data = data;
607         if (msr->load_into_hardware) {
608                 preempt_disable();
609                 ret = kvm_set_user_return_msr(slot, msr->data, msr->mask);
610                 preempt_enable();
611                 if (ret)
612                         msr->data = old_msr_data;
613         }
614         return ret;
615 }
616
617 #ifdef CONFIG_KEXEC_CORE
618 static void crash_vmclear_local_loaded_vmcss(void)
619 {
620         int cpu = raw_smp_processor_id();
621         struct loaded_vmcs *v;
622
623         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
624                             loaded_vmcss_on_cpu_link)
625                 vmcs_clear(v->vmcs);
626 }
627 #endif /* CONFIG_KEXEC_CORE */
628
629 static void __loaded_vmcs_clear(void *arg)
630 {
631         struct loaded_vmcs *loaded_vmcs = arg;
632         int cpu = raw_smp_processor_id();
633
634         if (loaded_vmcs->cpu != cpu)
635                 return; /* vcpu migration can race with cpu offline */
636         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
637                 per_cpu(current_vmcs, cpu) = NULL;
638
639         vmcs_clear(loaded_vmcs->vmcs);
640         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
641                 vmcs_clear(loaded_vmcs->shadow_vmcs);
642
643         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
644
645         /*
646          * Ensure all writes to loaded_vmcs, including deleting it from its
647          * current percpu list, complete before setting loaded_vmcs->vcpu to
648          * -1, otherwise a different cpu can see vcpu == -1 first and add
649          * loaded_vmcs to its percpu list before it's deleted from this cpu's
650          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
651          */
652         smp_wmb();
653
654         loaded_vmcs->cpu = -1;
655         loaded_vmcs->launched = 0;
656 }
657
658 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
659 {
660         int cpu = loaded_vmcs->cpu;
661
662         if (cpu != -1)
663                 smp_call_function_single(cpu,
664                          __loaded_vmcs_clear, loaded_vmcs, 1);
665 }
666
667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
668                                        unsigned field)
669 {
670         bool ret;
671         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
672
673         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
674                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
675                 vmx->segment_cache.bitmask = 0;
676         }
677         ret = vmx->segment_cache.bitmask & mask;
678         vmx->segment_cache.bitmask |= mask;
679         return ret;
680 }
681
682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
683 {
684         u16 *p = &vmx->segment_cache.seg[seg].selector;
685
686         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
687                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
688         return *p;
689 }
690
691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
692 {
693         ulong *p = &vmx->segment_cache.seg[seg].base;
694
695         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
696                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
697         return *p;
698 }
699
700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
701 {
702         u32 *p = &vmx->segment_cache.seg[seg].limit;
703
704         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
705                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
706         return *p;
707 }
708
709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
710 {
711         u32 *p = &vmx->segment_cache.seg[seg].ar;
712
713         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
714                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
715         return *p;
716 }
717
718 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu)
719 {
720         u32 eb;
721
722         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
723              (1u << DB_VECTOR) | (1u << AC_VECTOR);
724         /*
725          * Guest access to VMware backdoor ports could legitimately
726          * trigger #GP because of TSS I/O permission bitmap.
727          * We intercept those #GP and allow access to them anyway
728          * as VMware does.
729          */
730         if (enable_vmware_backdoor)
731                 eb |= (1u << GP_VECTOR);
732         if ((vcpu->guest_debug &
733              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
734             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
735                 eb |= 1u << BP_VECTOR;
736         if (to_vmx(vcpu)->rmode.vm86_active)
737                 eb = ~0;
738         if (!vmx_need_pf_intercept(vcpu))
739                 eb &= ~(1u << PF_VECTOR);
740
741         /* When we are running a nested L2 guest and L1 specified for it a
742          * certain exception bitmap, we must trap the same exceptions and pass
743          * them to L1. When running L2, we will only handle the exceptions
744          * specified above if L1 did not want them.
745          */
746         if (is_guest_mode(vcpu))
747                 eb |= get_vmcs12(vcpu)->exception_bitmap;
748         else {
749                 int mask = 0, match = 0;
750
751                 if (enable_ept && (eb & (1u << PF_VECTOR))) {
752                         /*
753                          * If EPT is enabled, #PF is currently only intercepted
754                          * if MAXPHYADDR is smaller on the guest than on the
755                          * host.  In that case we only care about present,
756                          * non-reserved faults.  For vmcs02, however, PFEC_MASK
757                          * and PFEC_MATCH are set in prepare_vmcs02_rare.
758                          */
759                         mask = PFERR_PRESENT_MASK | PFERR_RSVD_MASK;
760                         match = PFERR_PRESENT_MASK;
761                 }
762                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
763                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, match);
764         }
765
766         vmcs_write32(EXCEPTION_BITMAP, eb);
767 }
768
769 /*
770  * Check if MSR is intercepted for currently loaded MSR bitmap.
771  */
772 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
773 {
774         unsigned long *msr_bitmap;
775         int f = sizeof(unsigned long);
776
777         if (!cpu_has_vmx_msr_bitmap())
778                 return true;
779
780         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
781
782         if (msr <= 0x1fff) {
783                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
784         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
785                 msr &= 0x1fff;
786                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
787         }
788
789         return true;
790 }
791
792 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
793                 unsigned long entry, unsigned long exit)
794 {
795         vm_entry_controls_clearbit(vmx, entry);
796         vm_exit_controls_clearbit(vmx, exit);
797 }
798
799 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr)
800 {
801         unsigned int i;
802
803         for (i = 0; i < m->nr; ++i) {
804                 if (m->val[i].index == msr)
805                         return i;
806         }
807         return -ENOENT;
808 }
809
810 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
811 {
812         int i;
813         struct msr_autoload *m = &vmx->msr_autoload;
814
815         switch (msr) {
816         case MSR_EFER:
817                 if (cpu_has_load_ia32_efer()) {
818                         clear_atomic_switch_msr_special(vmx,
819                                         VM_ENTRY_LOAD_IA32_EFER,
820                                         VM_EXIT_LOAD_IA32_EFER);
821                         return;
822                 }
823                 break;
824         case MSR_CORE_PERF_GLOBAL_CTRL:
825                 if (cpu_has_load_perf_global_ctrl()) {
826                         clear_atomic_switch_msr_special(vmx,
827                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
828                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
829                         return;
830                 }
831                 break;
832         }
833         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
834         if (i < 0)
835                 goto skip_guest;
836         --m->guest.nr;
837         m->guest.val[i] = m->guest.val[m->guest.nr];
838         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
839
840 skip_guest:
841         i = vmx_find_loadstore_msr_slot(&m->host, msr);
842         if (i < 0)
843                 return;
844
845         --m->host.nr;
846         m->host.val[i] = m->host.val[m->host.nr];
847         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
848 }
849
850 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
851                 unsigned long entry, unsigned long exit,
852                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
853                 u64 guest_val, u64 host_val)
854 {
855         vmcs_write64(guest_val_vmcs, guest_val);
856         if (host_val_vmcs != HOST_IA32_EFER)
857                 vmcs_write64(host_val_vmcs, host_val);
858         vm_entry_controls_setbit(vmx, entry);
859         vm_exit_controls_setbit(vmx, exit);
860 }
861
862 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
863                                   u64 guest_val, u64 host_val, bool entry_only)
864 {
865         int i, j = 0;
866         struct msr_autoload *m = &vmx->msr_autoload;
867
868         switch (msr) {
869         case MSR_EFER:
870                 if (cpu_has_load_ia32_efer()) {
871                         add_atomic_switch_msr_special(vmx,
872                                         VM_ENTRY_LOAD_IA32_EFER,
873                                         VM_EXIT_LOAD_IA32_EFER,
874                                         GUEST_IA32_EFER,
875                                         HOST_IA32_EFER,
876                                         guest_val, host_val);
877                         return;
878                 }
879                 break;
880         case MSR_CORE_PERF_GLOBAL_CTRL:
881                 if (cpu_has_load_perf_global_ctrl()) {
882                         add_atomic_switch_msr_special(vmx,
883                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
884                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
885                                         GUEST_IA32_PERF_GLOBAL_CTRL,
886                                         HOST_IA32_PERF_GLOBAL_CTRL,
887                                         guest_val, host_val);
888                         return;
889                 }
890                 break;
891         case MSR_IA32_PEBS_ENABLE:
892                 /* PEBS needs a quiescent period after being disabled (to write
893                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
894                  * provide that period, so a CPU could write host's record into
895                  * guest's memory.
896                  */
897                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
898         }
899
900         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
901         if (!entry_only)
902                 j = vmx_find_loadstore_msr_slot(&m->host, msr);
903
904         if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) ||
905             (j < 0 &&  m->host.nr == MAX_NR_LOADSTORE_MSRS)) {
906                 printk_once(KERN_WARNING "Not enough msr switch entries. "
907                                 "Can't add msr %x\n", msr);
908                 return;
909         }
910         if (i < 0) {
911                 i = m->guest.nr++;
912                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
913         }
914         m->guest.val[i].index = msr;
915         m->guest.val[i].value = guest_val;
916
917         if (entry_only)
918                 return;
919
920         if (j < 0) {
921                 j = m->host.nr++;
922                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
923         }
924         m->host.val[j].index = msr;
925         m->host.val[j].value = host_val;
926 }
927
928 static bool update_transition_efer(struct vcpu_vmx *vmx)
929 {
930         u64 guest_efer = vmx->vcpu.arch.efer;
931         u64 ignore_bits = 0;
932         int i;
933
934         /* Shadow paging assumes NX to be available.  */
935         if (!enable_ept)
936                 guest_efer |= EFER_NX;
937
938         /*
939          * LMA and LME handled by hardware; SCE meaningless outside long mode.
940          */
941         ignore_bits |= EFER_SCE;
942 #ifdef CONFIG_X86_64
943         ignore_bits |= EFER_LMA | EFER_LME;
944         /* SCE is meaningful only in long mode on Intel */
945         if (guest_efer & EFER_LMA)
946                 ignore_bits &= ~(u64)EFER_SCE;
947 #endif
948
949         /*
950          * On EPT, we can't emulate NX, so we must switch EFER atomically.
951          * On CPUs that support "load IA32_EFER", always switch EFER
952          * atomically, since it's faster than switching it manually.
953          */
954         if (cpu_has_load_ia32_efer() ||
955             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
956                 if (!(guest_efer & EFER_LMA))
957                         guest_efer &= ~EFER_LME;
958                 if (guest_efer != host_efer)
959                         add_atomic_switch_msr(vmx, MSR_EFER,
960                                               guest_efer, host_efer, false);
961                 else
962                         clear_atomic_switch_msr(vmx, MSR_EFER);
963                 return false;
964         }
965
966         i = kvm_find_user_return_msr(MSR_EFER);
967         if (i < 0)
968                 return false;
969
970         clear_atomic_switch_msr(vmx, MSR_EFER);
971
972         guest_efer &= ~ignore_bits;
973         guest_efer |= host_efer & ignore_bits;
974
975         vmx->guest_uret_msrs[i].data = guest_efer;
976         vmx->guest_uret_msrs[i].mask = ~ignore_bits;
977
978         return true;
979 }
980
981 #ifdef CONFIG_X86_32
982 /*
983  * On 32-bit kernels, VM exits still load the FS and GS bases from the
984  * VMCS rather than the segment table.  KVM uses this helper to figure
985  * out the current bases to poke them into the VMCS before entry.
986  */
987 static unsigned long segment_base(u16 selector)
988 {
989         struct desc_struct *table;
990         unsigned long v;
991
992         if (!(selector & ~SEGMENT_RPL_MASK))
993                 return 0;
994
995         table = get_current_gdt_ro();
996
997         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
998                 u16 ldt_selector = kvm_read_ldt();
999
1000                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1001                         return 0;
1002
1003                 table = (struct desc_struct *)segment_base(ldt_selector);
1004         }
1005         v = get_desc_base(&table[selector >> 3]);
1006         return v;
1007 }
1008 #endif
1009
1010 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1011 {
1012         return vmx_pt_mode_is_host_guest() &&
1013                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1014 }
1015
1016 static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base)
1017 {
1018         /* The base must be 128-byte aligned and a legal physical address. */
1019         return kvm_vcpu_is_legal_aligned_gpa(vcpu, base, 128);
1020 }
1021
1022 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1023 {
1024         u32 i;
1025
1026         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1027         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1028         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1029         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1030         for (i = 0; i < addr_range; i++) {
1031                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1032                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1033         }
1034 }
1035
1036 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1037 {
1038         u32 i;
1039
1040         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1041         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1042         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1043         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1044         for (i = 0; i < addr_range; i++) {
1045                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1046                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1047         }
1048 }
1049
1050 static void pt_guest_enter(struct vcpu_vmx *vmx)
1051 {
1052         if (vmx_pt_mode_is_system())
1053                 return;
1054
1055         /*
1056          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1057          * Save host state before VM entry.
1058          */
1059         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1060         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1061                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1062                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1063                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1064         }
1065 }
1066
1067 static void pt_guest_exit(struct vcpu_vmx *vmx)
1068 {
1069         if (vmx_pt_mode_is_system())
1070                 return;
1071
1072         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1073                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1074                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1075         }
1076
1077         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1078         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1079 }
1080
1081 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1082                         unsigned long fs_base, unsigned long gs_base)
1083 {
1084         if (unlikely(fs_sel != host->fs_sel)) {
1085                 if (!(fs_sel & 7))
1086                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1087                 else
1088                         vmcs_write16(HOST_FS_SELECTOR, 0);
1089                 host->fs_sel = fs_sel;
1090         }
1091         if (unlikely(gs_sel != host->gs_sel)) {
1092                 if (!(gs_sel & 7))
1093                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1094                 else
1095                         vmcs_write16(HOST_GS_SELECTOR, 0);
1096                 host->gs_sel = gs_sel;
1097         }
1098         if (unlikely(fs_base != host->fs_base)) {
1099                 vmcs_writel(HOST_FS_BASE, fs_base);
1100                 host->fs_base = fs_base;
1101         }
1102         if (unlikely(gs_base != host->gs_base)) {
1103                 vmcs_writel(HOST_GS_BASE, gs_base);
1104                 host->gs_base = gs_base;
1105         }
1106 }
1107
1108 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1109 {
1110         struct vcpu_vmx *vmx = to_vmx(vcpu);
1111         struct vmcs_host_state *host_state;
1112 #ifdef CONFIG_X86_64
1113         int cpu = raw_smp_processor_id();
1114 #endif
1115         unsigned long fs_base, gs_base;
1116         u16 fs_sel, gs_sel;
1117         int i;
1118
1119         vmx->req_immediate_exit = false;
1120
1121         /*
1122          * Note that guest MSRs to be saved/restored can also be changed
1123          * when guest state is loaded. This happens when guest transitions
1124          * to/from long-mode by setting MSR_EFER.LMA.
1125          */
1126         if (!vmx->guest_uret_msrs_loaded) {
1127                 vmx->guest_uret_msrs_loaded = true;
1128                 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
1129                         if (!vmx->guest_uret_msrs[i].load_into_hardware)
1130                                 continue;
1131
1132                         kvm_set_user_return_msr(i,
1133                                                 vmx->guest_uret_msrs[i].data,
1134                                                 vmx->guest_uret_msrs[i].mask);
1135                 }
1136         }
1137
1138         if (vmx->nested.need_vmcs12_to_shadow_sync)
1139                 nested_sync_vmcs12_to_shadow(vcpu);
1140
1141         if (vmx->guest_state_loaded)
1142                 return;
1143
1144         host_state = &vmx->loaded_vmcs->host_state;
1145
1146         /*
1147          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1148          * allow segment selectors with cpl > 0 or ti == 1.
1149          */
1150         host_state->ldt_sel = kvm_read_ldt();
1151
1152 #ifdef CONFIG_X86_64
1153         savesegment(ds, host_state->ds_sel);
1154         savesegment(es, host_state->es_sel);
1155
1156         gs_base = cpu_kernelmode_gs_base(cpu);
1157         if (likely(is_64bit_mm(current->mm))) {
1158                 current_save_fsgs();
1159                 fs_sel = current->thread.fsindex;
1160                 gs_sel = current->thread.gsindex;
1161                 fs_base = current->thread.fsbase;
1162                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1163         } else {
1164                 savesegment(fs, fs_sel);
1165                 savesegment(gs, gs_sel);
1166                 fs_base = read_msr(MSR_FS_BASE);
1167                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1168         }
1169
1170         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1171 #else
1172         savesegment(fs, fs_sel);
1173         savesegment(gs, gs_sel);
1174         fs_base = segment_base(fs_sel);
1175         gs_base = segment_base(gs_sel);
1176 #endif
1177
1178         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1179         vmx->guest_state_loaded = true;
1180 }
1181
1182 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1183 {
1184         struct vmcs_host_state *host_state;
1185
1186         if (!vmx->guest_state_loaded)
1187                 return;
1188
1189         host_state = &vmx->loaded_vmcs->host_state;
1190
1191         ++vmx->vcpu.stat.host_state_reload;
1192
1193 #ifdef CONFIG_X86_64
1194         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1195 #endif
1196         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1197                 kvm_load_ldt(host_state->ldt_sel);
1198 #ifdef CONFIG_X86_64
1199                 load_gs_index(host_state->gs_sel);
1200 #else
1201                 loadsegment(gs, host_state->gs_sel);
1202 #endif
1203         }
1204         if (host_state->fs_sel & 7)
1205                 loadsegment(fs, host_state->fs_sel);
1206 #ifdef CONFIG_X86_64
1207         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1208                 loadsegment(ds, host_state->ds_sel);
1209                 loadsegment(es, host_state->es_sel);
1210         }
1211 #endif
1212         invalidate_tss_limit();
1213 #ifdef CONFIG_X86_64
1214         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1215 #endif
1216         load_fixmap_gdt(raw_smp_processor_id());
1217         vmx->guest_state_loaded = false;
1218         vmx->guest_uret_msrs_loaded = false;
1219 }
1220
1221 #ifdef CONFIG_X86_64
1222 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1223 {
1224         preempt_disable();
1225         if (vmx->guest_state_loaded)
1226                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1227         preempt_enable();
1228         return vmx->msr_guest_kernel_gs_base;
1229 }
1230
1231 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1232 {
1233         preempt_disable();
1234         if (vmx->guest_state_loaded)
1235                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1236         preempt_enable();
1237         vmx->msr_guest_kernel_gs_base = data;
1238 }
1239 #endif
1240
1241 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1242                         struct loaded_vmcs *buddy)
1243 {
1244         struct vcpu_vmx *vmx = to_vmx(vcpu);
1245         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1246         struct vmcs *prev;
1247
1248         if (!already_loaded) {
1249                 loaded_vmcs_clear(vmx->loaded_vmcs);
1250                 local_irq_disable();
1251
1252                 /*
1253                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1254                  * this cpu's percpu list, otherwise it may not yet be deleted
1255                  * from its previous cpu's percpu list.  Pairs with the
1256                  * smb_wmb() in __loaded_vmcs_clear().
1257                  */
1258                 smp_rmb();
1259
1260                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1261                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1262                 local_irq_enable();
1263         }
1264
1265         prev = per_cpu(current_vmcs, cpu);
1266         if (prev != vmx->loaded_vmcs->vmcs) {
1267                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1268                 vmcs_load(vmx->loaded_vmcs->vmcs);
1269
1270                 /*
1271                  * No indirect branch prediction barrier needed when switching
1272                  * the active VMCS within a guest, e.g. on nested VM-Enter.
1273                  * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1274                  */
1275                 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1276                         indirect_branch_prediction_barrier();
1277         }
1278
1279         if (!already_loaded) {
1280                 void *gdt = get_current_gdt_ro();
1281                 unsigned long sysenter_esp;
1282
1283                 /*
1284                  * Flush all EPTP/VPID contexts, the new pCPU may have stale
1285                  * TLB entries from its previous association with the vCPU.
1286                  */
1287                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1288
1289                 /*
1290                  * Linux uses per-cpu TSS and GDT, so set these when switching
1291                  * processors.  See 22.2.4.
1292                  */
1293                 vmcs_writel(HOST_TR_BASE,
1294                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1295                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1296
1297                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1298                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1299
1300                 vmx->loaded_vmcs->cpu = cpu;
1301         }
1302 }
1303
1304 /*
1305  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1306  * vcpu mutex is already taken.
1307  */
1308 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1309 {
1310         struct vcpu_vmx *vmx = to_vmx(vcpu);
1311
1312         vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1313
1314         vmx_vcpu_pi_load(vcpu, cpu);
1315
1316         vmx->host_debugctlmsr = get_debugctlmsr();
1317 }
1318
1319 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1320 {
1321         vmx_vcpu_pi_put(vcpu);
1322
1323         vmx_prepare_switch_to_host(to_vmx(vcpu));
1324 }
1325
1326 static bool emulation_required(struct kvm_vcpu *vcpu)
1327 {
1328         return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu);
1329 }
1330
1331 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1332 {
1333         struct vcpu_vmx *vmx = to_vmx(vcpu);
1334         unsigned long rflags, save_rflags;
1335
1336         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1337                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1338                 rflags = vmcs_readl(GUEST_RFLAGS);
1339                 if (vmx->rmode.vm86_active) {
1340                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1341                         save_rflags = vmx->rmode.save_rflags;
1342                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1343                 }
1344                 vmx->rflags = rflags;
1345         }
1346         return vmx->rflags;
1347 }
1348
1349 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1350 {
1351         struct vcpu_vmx *vmx = to_vmx(vcpu);
1352         unsigned long old_rflags;
1353
1354         if (is_unrestricted_guest(vcpu)) {
1355                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1356                 vmx->rflags = rflags;
1357                 vmcs_writel(GUEST_RFLAGS, rflags);
1358                 return;
1359         }
1360
1361         old_rflags = vmx_get_rflags(vcpu);
1362         vmx->rflags = rflags;
1363         if (vmx->rmode.vm86_active) {
1364                 vmx->rmode.save_rflags = rflags;
1365                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1366         }
1367         vmcs_writel(GUEST_RFLAGS, rflags);
1368
1369         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1370                 vmx->emulation_required = emulation_required(vcpu);
1371 }
1372
1373 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1374 {
1375         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1376         int ret = 0;
1377
1378         if (interruptibility & GUEST_INTR_STATE_STI)
1379                 ret |= KVM_X86_SHADOW_INT_STI;
1380         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1381                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1382
1383         return ret;
1384 }
1385
1386 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1387 {
1388         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1389         u32 interruptibility = interruptibility_old;
1390
1391         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1392
1393         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1394                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1395         else if (mask & KVM_X86_SHADOW_INT_STI)
1396                 interruptibility |= GUEST_INTR_STATE_STI;
1397
1398         if ((interruptibility != interruptibility_old))
1399                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1400 }
1401
1402 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1403 {
1404         struct vcpu_vmx *vmx = to_vmx(vcpu);
1405         unsigned long value;
1406
1407         /*
1408          * Any MSR write that attempts to change bits marked reserved will
1409          * case a #GP fault.
1410          */
1411         if (data & vmx->pt_desc.ctl_bitmask)
1412                 return 1;
1413
1414         /*
1415          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1416          * result in a #GP unless the same write also clears TraceEn.
1417          */
1418         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1419                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1420                 return 1;
1421
1422         /*
1423          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1424          * and FabricEn would cause #GP, if
1425          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1426          */
1427         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1428                 !(data & RTIT_CTL_FABRIC_EN) &&
1429                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1430                                         PT_CAP_single_range_output))
1431                 return 1;
1432
1433         /*
1434          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1435          * utilize encodings marked reserved will cause a #GP fault.
1436          */
1437         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1438         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1439                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1440                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1441                 return 1;
1442         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1443                                                 PT_CAP_cycle_thresholds);
1444         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1445                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1446                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1447                 return 1;
1448         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1449         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1450                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1451                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1452                 return 1;
1453
1454         /*
1455          * If ADDRx_CFG is reserved or the encodings is >2 will
1456          * cause a #GP fault.
1457          */
1458         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1459         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1460                 return 1;
1461         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1462         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1463                 return 1;
1464         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1465         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1466                 return 1;
1467         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1468         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1469                 return 1;
1470
1471         return 0;
1472 }
1473
1474 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
1475 {
1476         /*
1477          * Emulation of instructions in SGX enclaves is impossible as RIP does
1478          * not point  tthe failing instruction, and even if it did, the code
1479          * stream is inaccessible.  Inject #UD instead of exiting to userspace
1480          * so that guest userspace can't DoS the guest simply by triggering
1481          * emulation (enclaves are CPL3 only).
1482          */
1483         if (to_vmx(vcpu)->exit_reason.enclave_mode) {
1484                 kvm_queue_exception(vcpu, UD_VECTOR);
1485                 return false;
1486         }
1487         return true;
1488 }
1489
1490 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1491 {
1492         union vmx_exit_reason exit_reason = to_vmx(vcpu)->exit_reason;
1493         unsigned long rip, orig_rip;
1494         u32 instr_len;
1495
1496         /*
1497          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1498          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1499          * set when EPT misconfig occurs.  In practice, real hardware updates
1500          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1501          * (namely Hyper-V) don't set it due to it being undefined behavior,
1502          * i.e. we end up advancing IP with some random value.
1503          */
1504         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1505             exit_reason.basic != EXIT_REASON_EPT_MISCONFIG) {
1506                 instr_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1507
1508                 /*
1509                  * Emulating an enclave's instructions isn't supported as KVM
1510                  * cannot access the enclave's memory or its true RIP, e.g. the
1511                  * vmcs.GUEST_RIP points at the exit point of the enclave, not
1512                  * the RIP that actually triggered the VM-Exit.  But, because
1513                  * most instructions that cause VM-Exit will #UD in an enclave,
1514                  * most instruction-based VM-Exits simply do not occur.
1515                  *
1516                  * There are a few exceptions, notably the debug instructions
1517                  * INT1ICEBRK and INT3, as they are allowed in debug enclaves
1518                  * and generate #DB/#BP as expected, which KVM might intercept.
1519                  * But again, the CPU does the dirty work and saves an instr
1520                  * length of zero so VMMs don't shoot themselves in the foot.
1521                  * WARN if KVM tries to skip a non-zero length instruction on
1522                  * a VM-Exit from an enclave.
1523                  */
1524                 if (!instr_len)
1525                         goto rip_updated;
1526
1527                 WARN(exit_reason.enclave_mode,
1528                      "KVM: skipping instruction after SGX enclave VM-Exit");
1529
1530                 orig_rip = kvm_rip_read(vcpu);
1531                 rip = orig_rip + instr_len;
1532 #ifdef CONFIG_X86_64
1533                 /*
1534                  * We need to mask out the high 32 bits of RIP if not in 64-bit
1535                  * mode, but just finding out that we are in 64-bit mode is
1536                  * quite expensive.  Only do it if there was a carry.
1537                  */
1538                 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1539                         rip = (u32)rip;
1540 #endif
1541                 kvm_rip_write(vcpu, rip);
1542         } else {
1543                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1544                         return 0;
1545         }
1546
1547 rip_updated:
1548         /* skipping an emulated instruction also counts */
1549         vmx_set_interrupt_shadow(vcpu, 0);
1550
1551         return 1;
1552 }
1553
1554 /*
1555  * Recognizes a pending MTF VM-exit and records the nested state for later
1556  * delivery.
1557  */
1558 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1559 {
1560         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1561         struct vcpu_vmx *vmx = to_vmx(vcpu);
1562
1563         if (!is_guest_mode(vcpu))
1564                 return;
1565
1566         /*
1567          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1568          * T-bit traps. As instruction emulation is completed (i.e. at the
1569          * instruction boundary), any #DB exception pending delivery must be a
1570          * debug-trap. Record the pending MTF state to be delivered in
1571          * vmx_check_nested_events().
1572          */
1573         if (nested_cpu_has_mtf(vmcs12) &&
1574             (!vcpu->arch.exception.pending ||
1575              vcpu->arch.exception.nr == DB_VECTOR))
1576                 vmx->nested.mtf_pending = true;
1577         else
1578                 vmx->nested.mtf_pending = false;
1579 }
1580
1581 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1582 {
1583         vmx_update_emulated_instruction(vcpu);
1584         return skip_emulated_instruction(vcpu);
1585 }
1586
1587 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1588 {
1589         /*
1590          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1591          * explicitly skip the instruction because if the HLT state is set,
1592          * then the instruction is already executing and RIP has already been
1593          * advanced.
1594          */
1595         if (kvm_hlt_in_guest(vcpu->kvm) &&
1596                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1597                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1598 }
1599
1600 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1601 {
1602         struct vcpu_vmx *vmx = to_vmx(vcpu);
1603         unsigned nr = vcpu->arch.exception.nr;
1604         bool has_error_code = vcpu->arch.exception.has_error_code;
1605         u32 error_code = vcpu->arch.exception.error_code;
1606         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1607
1608         kvm_deliver_exception_payload(vcpu);
1609
1610         if (has_error_code) {
1611                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1612                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1613         }
1614
1615         if (vmx->rmode.vm86_active) {
1616                 int inc_eip = 0;
1617                 if (kvm_exception_is_soft(nr))
1618                         inc_eip = vcpu->arch.event_exit_inst_len;
1619                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1620                 return;
1621         }
1622
1623         WARN_ON_ONCE(vmx->emulation_required);
1624
1625         if (kvm_exception_is_soft(nr)) {
1626                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1627                              vmx->vcpu.arch.event_exit_inst_len);
1628                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1629         } else
1630                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1631
1632         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1633
1634         vmx_clear_hlt(vcpu);
1635 }
1636
1637 static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr,
1638                                bool load_into_hardware)
1639 {
1640         struct vmx_uret_msr *uret_msr;
1641
1642         uret_msr = vmx_find_uret_msr(vmx, msr);
1643         if (!uret_msr)
1644                 return;
1645
1646         uret_msr->load_into_hardware = load_into_hardware;
1647 }
1648
1649 /*
1650  * Configuring user return MSRs to automatically save, load, and restore MSRs
1651  * that need to be shoved into hardware when running the guest.  Note, omitting
1652  * an MSR here does _NOT_ mean it's not emulated, only that it will not be
1653  * loaded into hardware when running the guest.
1654  */
1655 static void vmx_setup_uret_msrs(struct vcpu_vmx *vmx)
1656 {
1657 #ifdef CONFIG_X86_64
1658         bool load_syscall_msrs;
1659
1660         /*
1661          * The SYSCALL MSRs are only needed on long mode guests, and only
1662          * when EFER.SCE is set.
1663          */
1664         load_syscall_msrs = is_long_mode(&vmx->vcpu) &&
1665                             (vmx->vcpu.arch.efer & EFER_SCE);
1666
1667         vmx_setup_uret_msr(vmx, MSR_STAR, load_syscall_msrs);
1668         vmx_setup_uret_msr(vmx, MSR_LSTAR, load_syscall_msrs);
1669         vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK, load_syscall_msrs);
1670 #endif
1671         vmx_setup_uret_msr(vmx, MSR_EFER, update_transition_efer(vmx));
1672
1673         vmx_setup_uret_msr(vmx, MSR_TSC_AUX,
1674                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP) ||
1675                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDPID));
1676
1677         /*
1678          * hle=0, rtm=0, tsx_ctrl=1 can be found with some combinations of new
1679          * kernel and old userspace.  If those guests run on a tsx=off host, do
1680          * allow guests to use TSX_CTRL, but don't change the value in hardware
1681          * so that TSX remains always disabled.
1682          */
1683         vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL, boot_cpu_has(X86_FEATURE_RTM));
1684
1685         /*
1686          * The set of MSRs to load may have changed, reload MSRs before the
1687          * next VM-Enter.
1688          */
1689         vmx->guest_uret_msrs_loaded = false;
1690 }
1691
1692 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1693 {
1694         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1695
1696         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING))
1697                 return vmcs12->tsc_offset;
1698
1699         return 0;
1700 }
1701
1702 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1703 {
1704         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1705
1706         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING) &&
1707             nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
1708                 return vmcs12->tsc_multiplier;
1709
1710         return kvm_default_tsc_scaling_ratio;
1711 }
1712
1713 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1714 {
1715         vmcs_write64(TSC_OFFSET, offset);
1716 }
1717
1718 static void vmx_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1719 {
1720         vmcs_write64(TSC_MULTIPLIER, multiplier);
1721 }
1722
1723 /*
1724  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1725  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1726  * all guests if the "nested" module option is off, and can also be disabled
1727  * for a single guest by disabling its VMX cpuid bit.
1728  */
1729 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1730 {
1731         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1732 }
1733
1734 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1735                                                  uint64_t val)
1736 {
1737         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1738
1739         return !(val & ~valid_bits);
1740 }
1741
1742 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1743 {
1744         switch (msr->index) {
1745         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1746                 if (!nested)
1747                         return 1;
1748                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1749         case MSR_IA32_PERF_CAPABILITIES:
1750                 msr->data = vmx_get_perf_capabilities();
1751                 return 0;
1752         default:
1753                 return KVM_MSR_RET_INVALID;
1754         }
1755 }
1756
1757 /*
1758  * Reads an msr value (of 'msr_index') into 'pdata'.
1759  * Returns 0 on success, non-0 otherwise.
1760  * Assumes vcpu_load() was already called.
1761  */
1762 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1763 {
1764         struct vcpu_vmx *vmx = to_vmx(vcpu);
1765         struct vmx_uret_msr *msr;
1766         u32 index;
1767
1768         switch (msr_info->index) {
1769 #ifdef CONFIG_X86_64
1770         case MSR_FS_BASE:
1771                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1772                 break;
1773         case MSR_GS_BASE:
1774                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1775                 break;
1776         case MSR_KERNEL_GS_BASE:
1777                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1778                 break;
1779 #endif
1780         case MSR_EFER:
1781                 return kvm_get_msr_common(vcpu, msr_info);
1782         case MSR_IA32_TSX_CTRL:
1783                 if (!msr_info->host_initiated &&
1784                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1785                         return 1;
1786                 goto find_uret_msr;
1787         case MSR_IA32_UMWAIT_CONTROL:
1788                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1789                         return 1;
1790
1791                 msr_info->data = vmx->msr_ia32_umwait_control;
1792                 break;
1793         case MSR_IA32_SPEC_CTRL:
1794                 if (!msr_info->host_initiated &&
1795                     !guest_has_spec_ctrl_msr(vcpu))
1796                         return 1;
1797
1798                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1799                 break;
1800         case MSR_IA32_SYSENTER_CS:
1801                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1802                 break;
1803         case MSR_IA32_SYSENTER_EIP:
1804                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1805                 break;
1806         case MSR_IA32_SYSENTER_ESP:
1807                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1808                 break;
1809         case MSR_IA32_BNDCFGS:
1810                 if (!kvm_mpx_supported() ||
1811                     (!msr_info->host_initiated &&
1812                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1813                         return 1;
1814                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1815                 break;
1816         case MSR_IA32_MCG_EXT_CTL:
1817                 if (!msr_info->host_initiated &&
1818                     !(vmx->msr_ia32_feature_control &
1819                       FEAT_CTL_LMCE_ENABLED))
1820                         return 1;
1821                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1822                 break;
1823         case MSR_IA32_FEAT_CTL:
1824                 msr_info->data = vmx->msr_ia32_feature_control;
1825                 break;
1826         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
1827                 if (!msr_info->host_initiated &&
1828                     !guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
1829                         return 1;
1830                 msr_info->data = to_vmx(vcpu)->msr_ia32_sgxlepubkeyhash
1831                         [msr_info->index - MSR_IA32_SGXLEPUBKEYHASH0];
1832                 break;
1833         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1834                 if (!nested_vmx_allowed(vcpu))
1835                         return 1;
1836                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1837                                     &msr_info->data))
1838                         return 1;
1839                 /*
1840                  * Enlightened VMCS v1 doesn't have certain fields, but buggy
1841                  * Hyper-V versions are still trying to use corresponding
1842                  * features when they are exposed. Filter out the essential
1843                  * minimum.
1844                  */
1845                 if (!msr_info->host_initiated &&
1846                     vmx->nested.enlightened_vmcs_enabled)
1847                         nested_evmcs_filter_control_msr(msr_info->index,
1848                                                         &msr_info->data);
1849                 break;
1850         case MSR_IA32_RTIT_CTL:
1851                 if (!vmx_pt_mode_is_host_guest())
1852                         return 1;
1853                 msr_info->data = vmx->pt_desc.guest.ctl;
1854                 break;
1855         case MSR_IA32_RTIT_STATUS:
1856                 if (!vmx_pt_mode_is_host_guest())
1857                         return 1;
1858                 msr_info->data = vmx->pt_desc.guest.status;
1859                 break;
1860         case MSR_IA32_RTIT_CR3_MATCH:
1861                 if (!vmx_pt_mode_is_host_guest() ||
1862                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1863                                                 PT_CAP_cr3_filtering))
1864                         return 1;
1865                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1866                 break;
1867         case MSR_IA32_RTIT_OUTPUT_BASE:
1868                 if (!vmx_pt_mode_is_host_guest() ||
1869                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1870                                         PT_CAP_topa_output) &&
1871                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1872                                         PT_CAP_single_range_output)))
1873                         return 1;
1874                 msr_info->data = vmx->pt_desc.guest.output_base;
1875                 break;
1876         case MSR_IA32_RTIT_OUTPUT_MASK:
1877                 if (!vmx_pt_mode_is_host_guest() ||
1878                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1879                                         PT_CAP_topa_output) &&
1880                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1881                                         PT_CAP_single_range_output)))
1882                         return 1;
1883                 msr_info->data = vmx->pt_desc.guest.output_mask;
1884                 break;
1885         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1886                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1887                 if (!vmx_pt_mode_is_host_guest() ||
1888                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1889                                         PT_CAP_num_address_ranges)))
1890                         return 1;
1891                 if (index % 2)
1892                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1893                 else
1894                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1895                 break;
1896         case MSR_IA32_DEBUGCTLMSR:
1897                 msr_info->data = vmcs_read64(GUEST_IA32_DEBUGCTL);
1898                 break;
1899         default:
1900         find_uret_msr:
1901                 msr = vmx_find_uret_msr(vmx, msr_info->index);
1902                 if (msr) {
1903                         msr_info->data = msr->data;
1904                         break;
1905                 }
1906                 return kvm_get_msr_common(vcpu, msr_info);
1907         }
1908
1909         return 0;
1910 }
1911
1912 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1913                                                     u64 data)
1914 {
1915 #ifdef CONFIG_X86_64
1916         if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1917                 return (u32)data;
1918 #endif
1919         return (unsigned long)data;
1920 }
1921
1922 static u64 vcpu_supported_debugctl(struct kvm_vcpu *vcpu)
1923 {
1924         u64 debugctl = vmx_supported_debugctl();
1925
1926         if (!intel_pmu_lbr_is_enabled(vcpu))
1927                 debugctl &= ~DEBUGCTLMSR_LBR_MASK;
1928
1929         if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1930                 debugctl &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1931
1932         return debugctl;
1933 }
1934
1935 /*
1936  * Writes msr value into the appropriate "register".
1937  * Returns 0 on success, non-0 otherwise.
1938  * Assumes vcpu_load() was already called.
1939  */
1940 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1941 {
1942         struct vcpu_vmx *vmx = to_vmx(vcpu);
1943         struct vmx_uret_msr *msr;
1944         int ret = 0;
1945         u32 msr_index = msr_info->index;
1946         u64 data = msr_info->data;
1947         u32 index;
1948
1949         switch (msr_index) {
1950         case MSR_EFER:
1951                 ret = kvm_set_msr_common(vcpu, msr_info);
1952                 break;
1953 #ifdef CONFIG_X86_64
1954         case MSR_FS_BASE:
1955                 vmx_segment_cache_clear(vmx);
1956                 vmcs_writel(GUEST_FS_BASE, data);
1957                 break;
1958         case MSR_GS_BASE:
1959                 vmx_segment_cache_clear(vmx);
1960                 vmcs_writel(GUEST_GS_BASE, data);
1961                 break;
1962         case MSR_KERNEL_GS_BASE:
1963                 vmx_write_guest_kernel_gs_base(vmx, data);
1964                 break;
1965 #endif
1966         case MSR_IA32_SYSENTER_CS:
1967                 if (is_guest_mode(vcpu))
1968                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1969                 vmcs_write32(GUEST_SYSENTER_CS, data);
1970                 break;
1971         case MSR_IA32_SYSENTER_EIP:
1972                 if (is_guest_mode(vcpu)) {
1973                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1974                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1975                 }
1976                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1977                 break;
1978         case MSR_IA32_SYSENTER_ESP:
1979                 if (is_guest_mode(vcpu)) {
1980                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1981                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1982                 }
1983                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1984                 break;
1985         case MSR_IA32_DEBUGCTLMSR: {
1986                 u64 invalid = data & ~vcpu_supported_debugctl(vcpu);
1987                 if (invalid & (DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR)) {
1988                         if (report_ignored_msrs)
1989                                 vcpu_unimpl(vcpu, "%s: BTF|LBR in IA32_DEBUGCTLMSR 0x%llx, nop\n",
1990                                             __func__, data);
1991                         data &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1992                         invalid &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1993                 }
1994
1995                 if (invalid)
1996                         return 1;
1997
1998                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1999                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
2000                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2001
2002                 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
2003                 if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event &&
2004                     (data & DEBUGCTLMSR_LBR))
2005                         intel_pmu_create_guest_lbr_event(vcpu);
2006                 return 0;
2007         }
2008         case MSR_IA32_BNDCFGS:
2009                 if (!kvm_mpx_supported() ||
2010                     (!msr_info->host_initiated &&
2011                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2012                         return 1;
2013                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2014                     (data & MSR_IA32_BNDCFGS_RSVD))
2015                         return 1;
2016                 vmcs_write64(GUEST_BNDCFGS, data);
2017                 break;
2018         case MSR_IA32_UMWAIT_CONTROL:
2019                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2020                         return 1;
2021
2022                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2023                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2024                         return 1;
2025
2026                 vmx->msr_ia32_umwait_control = data;
2027                 break;
2028         case MSR_IA32_SPEC_CTRL:
2029                 if (!msr_info->host_initiated &&
2030                     !guest_has_spec_ctrl_msr(vcpu))
2031                         return 1;
2032
2033                 if (kvm_spec_ctrl_test_value(data))
2034                         return 1;
2035
2036                 vmx->spec_ctrl = data;
2037                 if (!data)
2038                         break;
2039
2040                 /*
2041                  * For non-nested:
2042                  * When it's written (to non-zero) for the first time, pass
2043                  * it through.
2044                  *
2045                  * For nested:
2046                  * The handling of the MSR bitmap for L2 guests is done in
2047                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2048                  * vmcs02.msr_bitmap here since it gets completely overwritten
2049                  * in the merging. We update the vmcs01 here for L1 as well
2050                  * since it will end up touching the MSR anyway now.
2051                  */
2052                 vmx_disable_intercept_for_msr(vcpu,
2053                                               MSR_IA32_SPEC_CTRL,
2054                                               MSR_TYPE_RW);
2055                 break;
2056         case MSR_IA32_TSX_CTRL:
2057                 if (!msr_info->host_initiated &&
2058                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2059                         return 1;
2060                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2061                         return 1;
2062                 goto find_uret_msr;
2063         case MSR_IA32_PRED_CMD:
2064                 if (!msr_info->host_initiated &&
2065                     !guest_has_pred_cmd_msr(vcpu))
2066                         return 1;
2067
2068                 if (data & ~PRED_CMD_IBPB)
2069                         return 1;
2070                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2071                         return 1;
2072                 if (!data)
2073                         break;
2074
2075                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2076
2077                 /*
2078                  * For non-nested:
2079                  * When it's written (to non-zero) for the first time, pass
2080                  * it through.
2081                  *
2082                  * For nested:
2083                  * The handling of the MSR bitmap for L2 guests is done in
2084                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2085                  * vmcs02.msr_bitmap here since it gets completely overwritten
2086                  * in the merging.
2087                  */
2088                 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
2089                 break;
2090         case MSR_IA32_CR_PAT:
2091                 if (!kvm_pat_valid(data))
2092                         return 1;
2093
2094                 if (is_guest_mode(vcpu) &&
2095                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2096                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2097
2098                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2099                         vmcs_write64(GUEST_IA32_PAT, data);
2100                         vcpu->arch.pat = data;
2101                         break;
2102                 }
2103                 ret = kvm_set_msr_common(vcpu, msr_info);
2104                 break;
2105         case MSR_IA32_TSC_ADJUST:
2106                 ret = kvm_set_msr_common(vcpu, msr_info);
2107                 break;
2108         case MSR_IA32_MCG_EXT_CTL:
2109                 if ((!msr_info->host_initiated &&
2110                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2111                        FEAT_CTL_LMCE_ENABLED)) ||
2112                     (data & ~MCG_EXT_CTL_LMCE_EN))
2113                         return 1;
2114                 vcpu->arch.mcg_ext_ctl = data;
2115                 break;
2116         case MSR_IA32_FEAT_CTL:
2117                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2118                     (to_vmx(vcpu)->msr_ia32_feature_control &
2119                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2120                         return 1;
2121                 vmx->msr_ia32_feature_control = data;
2122                 if (msr_info->host_initiated && data == 0)
2123                         vmx_leave_nested(vcpu);
2124
2125                 /* SGX may be enabled/disabled by guest's firmware */
2126                 vmx_write_encls_bitmap(vcpu, NULL);
2127                 break;
2128         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
2129                 /*
2130                  * On real hardware, the LE hash MSRs are writable before
2131                  * the firmware sets bit 0 in MSR 0x7a ("activating" SGX),
2132                  * at which point SGX related bits in IA32_FEATURE_CONTROL
2133                  * become writable.
2134                  *
2135                  * KVM does not emulate SGX activation for simplicity, so
2136                  * allow writes to the LE hash MSRs if IA32_FEATURE_CONTROL
2137                  * is unlocked.  This is technically not architectural
2138                  * behavior, but it's close enough.
2139                  */
2140                 if (!msr_info->host_initiated &&
2141                     (!guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC) ||
2142                     ((vmx->msr_ia32_feature_control & FEAT_CTL_LOCKED) &&
2143                     !(vmx->msr_ia32_feature_control & FEAT_CTL_SGX_LC_ENABLED))))
2144                         return 1;
2145                 vmx->msr_ia32_sgxlepubkeyhash
2146                         [msr_index - MSR_IA32_SGXLEPUBKEYHASH0] = data;
2147                 break;
2148         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2149                 if (!msr_info->host_initiated)
2150                         return 1; /* they are read-only */
2151                 if (!nested_vmx_allowed(vcpu))
2152                         return 1;
2153                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2154         case MSR_IA32_RTIT_CTL:
2155                 if (!vmx_pt_mode_is_host_guest() ||
2156                         vmx_rtit_ctl_check(vcpu, data) ||
2157                         vmx->nested.vmxon)
2158                         return 1;
2159                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2160                 vmx->pt_desc.guest.ctl = data;
2161                 pt_update_intercept_for_msr(vcpu);
2162                 break;
2163         case MSR_IA32_RTIT_STATUS:
2164                 if (!pt_can_write_msr(vmx))
2165                         return 1;
2166                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2167                         return 1;
2168                 vmx->pt_desc.guest.status = data;
2169                 break;
2170         case MSR_IA32_RTIT_CR3_MATCH:
2171                 if (!pt_can_write_msr(vmx))
2172                         return 1;
2173                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2174                                            PT_CAP_cr3_filtering))
2175                         return 1;
2176                 vmx->pt_desc.guest.cr3_match = data;
2177                 break;
2178         case MSR_IA32_RTIT_OUTPUT_BASE:
2179                 if (!pt_can_write_msr(vmx))
2180                         return 1;
2181                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2182                                            PT_CAP_topa_output) &&
2183                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2184                                            PT_CAP_single_range_output))
2185                         return 1;
2186                 if (!pt_output_base_valid(vcpu, data))
2187                         return 1;
2188                 vmx->pt_desc.guest.output_base = data;
2189                 break;
2190         case MSR_IA32_RTIT_OUTPUT_MASK:
2191                 if (!pt_can_write_msr(vmx))
2192                         return 1;
2193                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2194                                            PT_CAP_topa_output) &&
2195                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2196                                            PT_CAP_single_range_output))
2197                         return 1;
2198                 vmx->pt_desc.guest.output_mask = data;
2199                 break;
2200         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2201                 if (!pt_can_write_msr(vmx))
2202                         return 1;
2203                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2204                 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2205                                                        PT_CAP_num_address_ranges))
2206                         return 1;
2207                 if (is_noncanonical_address(data, vcpu))
2208                         return 1;
2209                 if (index % 2)
2210                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2211                 else
2212                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2213                 break;
2214         case MSR_IA32_PERF_CAPABILITIES:
2215                 if (data && !vcpu_to_pmu(vcpu)->version)
2216                         return 1;
2217                 if (data & PMU_CAP_LBR_FMT) {
2218                         if ((data & PMU_CAP_LBR_FMT) !=
2219                             (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
2220                                 return 1;
2221                         if (!intel_pmu_lbr_is_compatible(vcpu))
2222                                 return 1;
2223                 }
2224                 ret = kvm_set_msr_common(vcpu, msr_info);
2225                 break;
2226
2227         default:
2228         find_uret_msr:
2229                 msr = vmx_find_uret_msr(vmx, msr_index);
2230                 if (msr)
2231                         ret = vmx_set_guest_uret_msr(vmx, msr, data);
2232                 else
2233                         ret = kvm_set_msr_common(vcpu, msr_info);
2234         }
2235
2236         return ret;
2237 }
2238
2239 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2240 {
2241         unsigned long guest_owned_bits;
2242
2243         kvm_register_mark_available(vcpu, reg);
2244
2245         switch (reg) {
2246         case VCPU_REGS_RSP:
2247                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2248                 break;
2249         case VCPU_REGS_RIP:
2250                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2251                 break;
2252         case VCPU_EXREG_PDPTR:
2253                 if (enable_ept)
2254                         ept_save_pdptrs(vcpu);
2255                 break;
2256         case VCPU_EXREG_CR0:
2257                 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2258
2259                 vcpu->arch.cr0 &= ~guest_owned_bits;
2260                 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2261                 break;
2262         case VCPU_EXREG_CR3:
2263                 /*
2264                  * When intercepting CR3 loads, e.g. for shadowing paging, KVM's
2265                  * CR3 is loaded into hardware, not the guest's CR3.
2266                  */
2267                 if (!(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_CR3_LOAD_EXITING))
2268                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2269                 break;
2270         case VCPU_EXREG_CR4:
2271                 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2272
2273                 vcpu->arch.cr4 &= ~guest_owned_bits;
2274                 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2275                 break;
2276         default:
2277                 KVM_BUG_ON(1, vcpu->kvm);
2278                 break;
2279         }
2280 }
2281
2282 static __init int cpu_has_kvm_support(void)
2283 {
2284         return cpu_has_vmx();
2285 }
2286
2287 static __init int vmx_disabled_by_bios(void)
2288 {
2289         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2290                !boot_cpu_has(X86_FEATURE_VMX);
2291 }
2292
2293 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2294 {
2295         u64 msr;
2296
2297         cr4_set_bits(X86_CR4_VMXE);
2298
2299         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2300                           _ASM_EXTABLE(1b, %l[fault])
2301                           : : [vmxon_pointer] "m"(vmxon_pointer)
2302                           : : fault);
2303         return 0;
2304
2305 fault:
2306         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2307                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2308         cr4_clear_bits(X86_CR4_VMXE);
2309
2310         return -EFAULT;
2311 }
2312
2313 static int hardware_enable(void)
2314 {
2315         int cpu = raw_smp_processor_id();
2316         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2317         int r;
2318
2319         if (cr4_read_shadow() & X86_CR4_VMXE)
2320                 return -EBUSY;
2321
2322         /*
2323          * This can happen if we hot-added a CPU but failed to allocate
2324          * VP assist page for it.
2325          */
2326         if (static_branch_unlikely(&enable_evmcs) &&
2327             !hv_get_vp_assist_page(cpu))
2328                 return -EFAULT;
2329
2330         intel_pt_handle_vmx(1);
2331
2332         r = kvm_cpu_vmxon(phys_addr);
2333         if (r) {
2334                 intel_pt_handle_vmx(0);
2335                 return r;
2336         }
2337
2338         if (enable_ept)
2339                 ept_sync_global();
2340
2341         return 0;
2342 }
2343
2344 static void vmclear_local_loaded_vmcss(void)
2345 {
2346         int cpu = raw_smp_processor_id();
2347         struct loaded_vmcs *v, *n;
2348
2349         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2350                                  loaded_vmcss_on_cpu_link)
2351                 __loaded_vmcs_clear(v);
2352 }
2353
2354 static void hardware_disable(void)
2355 {
2356         vmclear_local_loaded_vmcss();
2357
2358         if (cpu_vmxoff())
2359                 kvm_spurious_fault();
2360
2361         intel_pt_handle_vmx(0);
2362 }
2363
2364 /*
2365  * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2366  * directly instead of going through cpu_has(), to ensure KVM is trapping
2367  * ENCLS whenever it's supported in hardware.  It does not matter whether
2368  * the host OS supports or has enabled SGX.
2369  */
2370 static bool cpu_has_sgx(void)
2371 {
2372         return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2373 }
2374
2375 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2376                                       u32 msr, u32 *result)
2377 {
2378         u32 vmx_msr_low, vmx_msr_high;
2379         u32 ctl = ctl_min | ctl_opt;
2380
2381         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2382
2383         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2384         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2385
2386         /* Ensure minimum (required) set of control bits are supported. */
2387         if (ctl_min & ~ctl)
2388                 return -EIO;
2389
2390         *result = ctl;
2391         return 0;
2392 }
2393
2394 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2395                                     struct vmx_capability *vmx_cap)
2396 {
2397         u32 vmx_msr_low, vmx_msr_high;
2398         u32 min, opt, min2, opt2;
2399         u32 _pin_based_exec_control = 0;
2400         u32 _cpu_based_exec_control = 0;
2401         u32 _cpu_based_2nd_exec_control = 0;
2402         u32 _vmexit_control = 0;
2403         u32 _vmentry_control = 0;
2404
2405         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2406         min = CPU_BASED_HLT_EXITING |
2407 #ifdef CONFIG_X86_64
2408               CPU_BASED_CR8_LOAD_EXITING |
2409               CPU_BASED_CR8_STORE_EXITING |
2410 #endif
2411               CPU_BASED_CR3_LOAD_EXITING |
2412               CPU_BASED_CR3_STORE_EXITING |
2413               CPU_BASED_UNCOND_IO_EXITING |
2414               CPU_BASED_MOV_DR_EXITING |
2415               CPU_BASED_USE_TSC_OFFSETTING |
2416               CPU_BASED_MWAIT_EXITING |
2417               CPU_BASED_MONITOR_EXITING |
2418               CPU_BASED_INVLPG_EXITING |
2419               CPU_BASED_RDPMC_EXITING;
2420
2421         opt = CPU_BASED_TPR_SHADOW |
2422               CPU_BASED_USE_MSR_BITMAPS |
2423               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2424         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2425                                 &_cpu_based_exec_control) < 0)
2426                 return -EIO;
2427 #ifdef CONFIG_X86_64
2428         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2429                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2430                                            ~CPU_BASED_CR8_STORE_EXITING;
2431 #endif
2432         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2433                 min2 = 0;
2434                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2435                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2436                         SECONDARY_EXEC_WBINVD_EXITING |
2437                         SECONDARY_EXEC_ENABLE_VPID |
2438                         SECONDARY_EXEC_ENABLE_EPT |
2439                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2440                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2441                         SECONDARY_EXEC_DESC |
2442                         SECONDARY_EXEC_ENABLE_RDTSCP |
2443                         SECONDARY_EXEC_ENABLE_INVPCID |
2444                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2445                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2446                         SECONDARY_EXEC_SHADOW_VMCS |
2447                         SECONDARY_EXEC_XSAVES |
2448                         SECONDARY_EXEC_RDSEED_EXITING |
2449                         SECONDARY_EXEC_RDRAND_EXITING |
2450                         SECONDARY_EXEC_ENABLE_PML |
2451                         SECONDARY_EXEC_TSC_SCALING |
2452                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2453                         SECONDARY_EXEC_PT_USE_GPA |
2454                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2455                         SECONDARY_EXEC_ENABLE_VMFUNC |
2456                         SECONDARY_EXEC_BUS_LOCK_DETECTION;
2457                 if (cpu_has_sgx())
2458                         opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2459                 if (adjust_vmx_controls(min2, opt2,
2460                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2461                                         &_cpu_based_2nd_exec_control) < 0)
2462                         return -EIO;
2463         }
2464 #ifndef CONFIG_X86_64
2465         if (!(_cpu_based_2nd_exec_control &
2466                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2467                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2468 #endif
2469
2470         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2471                 _cpu_based_2nd_exec_control &= ~(
2472                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2473                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2474                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2475
2476         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2477                 &vmx_cap->ept, &vmx_cap->vpid);
2478
2479         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2480                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2481                    enabled */
2482                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2483                                              CPU_BASED_CR3_STORE_EXITING |
2484                                              CPU_BASED_INVLPG_EXITING);
2485         } else if (vmx_cap->ept) {
2486                 vmx_cap->ept = 0;
2487                 pr_warn_once("EPT CAP should not exist if not support "
2488                                 "1-setting enable EPT VM-execution control\n");
2489         }
2490         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2491                 vmx_cap->vpid) {
2492                 vmx_cap->vpid = 0;
2493                 pr_warn_once("VPID CAP should not exist if not support "
2494                                 "1-setting enable VPID VM-execution control\n");
2495         }
2496
2497         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2498 #ifdef CONFIG_X86_64
2499         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2500 #endif
2501         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2502               VM_EXIT_LOAD_IA32_PAT |
2503               VM_EXIT_LOAD_IA32_EFER |
2504               VM_EXIT_CLEAR_BNDCFGS |
2505               VM_EXIT_PT_CONCEAL_PIP |
2506               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2507         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2508                                 &_vmexit_control) < 0)
2509                 return -EIO;
2510
2511         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2512         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2513                  PIN_BASED_VMX_PREEMPTION_TIMER;
2514         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2515                                 &_pin_based_exec_control) < 0)
2516                 return -EIO;
2517
2518         if (cpu_has_broken_vmx_preemption_timer())
2519                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2520         if (!(_cpu_based_2nd_exec_control &
2521                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2522                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2523
2524         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2525         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2526               VM_ENTRY_LOAD_IA32_PAT |
2527               VM_ENTRY_LOAD_IA32_EFER |
2528               VM_ENTRY_LOAD_BNDCFGS |
2529               VM_ENTRY_PT_CONCEAL_PIP |
2530               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2531         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2532                                 &_vmentry_control) < 0)
2533                 return -EIO;
2534
2535         /*
2536          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2537          * can't be used due to an errata where VM Exit may incorrectly clear
2538          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2539          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2540          */
2541         if (boot_cpu_data.x86 == 0x6) {
2542                 switch (boot_cpu_data.x86_model) {
2543                 case 26: /* AAK155 */
2544                 case 30: /* AAP115 */
2545                 case 37: /* AAT100 */
2546                 case 44: /* BC86,AAY89,BD102 */
2547                 case 46: /* BA97 */
2548                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2549                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2550                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2551                                         "does not work properly. Using workaround\n");
2552                         break;
2553                 default:
2554                         break;
2555                 }
2556         }
2557
2558
2559         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2560
2561         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2562         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2563                 return -EIO;
2564
2565 #ifdef CONFIG_X86_64
2566         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2567         if (vmx_msr_high & (1u<<16))
2568                 return -EIO;
2569 #endif
2570
2571         /* Require Write-Back (WB) memory type for VMCS accesses. */
2572         if (((vmx_msr_high >> 18) & 15) != 6)
2573                 return -EIO;
2574
2575         vmcs_conf->size = vmx_msr_high & 0x1fff;
2576         vmcs_conf->order = get_order(vmcs_conf->size);
2577         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2578
2579         vmcs_conf->revision_id = vmx_msr_low;
2580
2581         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2582         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2583         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2584         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2585         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2586
2587 #if IS_ENABLED(CONFIG_HYPERV)
2588         if (enlightened_vmcs)
2589                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2590 #endif
2591
2592         return 0;
2593 }
2594
2595 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2596 {
2597         int node = cpu_to_node(cpu);
2598         struct page *pages;
2599         struct vmcs *vmcs;
2600
2601         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2602         if (!pages)
2603                 return NULL;
2604         vmcs = page_address(pages);
2605         memset(vmcs, 0, vmcs_config.size);
2606
2607         /* KVM supports Enlightened VMCS v1 only */
2608         if (static_branch_unlikely(&enable_evmcs))
2609                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2610         else
2611                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2612
2613         if (shadow)
2614                 vmcs->hdr.shadow_vmcs = 1;
2615         return vmcs;
2616 }
2617
2618 void free_vmcs(struct vmcs *vmcs)
2619 {
2620         free_pages((unsigned long)vmcs, vmcs_config.order);
2621 }
2622
2623 /*
2624  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2625  */
2626 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2627 {
2628         if (!loaded_vmcs->vmcs)
2629                 return;
2630         loaded_vmcs_clear(loaded_vmcs);
2631         free_vmcs(loaded_vmcs->vmcs);
2632         loaded_vmcs->vmcs = NULL;
2633         if (loaded_vmcs->msr_bitmap)
2634                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2635         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2636 }
2637
2638 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2639 {
2640         loaded_vmcs->vmcs = alloc_vmcs(false);
2641         if (!loaded_vmcs->vmcs)
2642                 return -ENOMEM;
2643
2644         vmcs_clear(loaded_vmcs->vmcs);
2645
2646         loaded_vmcs->shadow_vmcs = NULL;
2647         loaded_vmcs->hv_timer_soft_disabled = false;
2648         loaded_vmcs->cpu = -1;
2649         loaded_vmcs->launched = 0;
2650
2651         if (cpu_has_vmx_msr_bitmap()) {
2652                 loaded_vmcs->msr_bitmap = (unsigned long *)
2653                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2654                 if (!loaded_vmcs->msr_bitmap)
2655                         goto out_vmcs;
2656                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2657
2658                 if (IS_ENABLED(CONFIG_HYPERV) &&
2659                     static_branch_unlikely(&enable_evmcs) &&
2660                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2661                         struct hv_enlightened_vmcs *evmcs =
2662                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2663
2664                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2665                 }
2666         }
2667
2668         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2669         memset(&loaded_vmcs->controls_shadow, 0,
2670                 sizeof(struct vmcs_controls_shadow));
2671
2672         return 0;
2673
2674 out_vmcs:
2675         free_loaded_vmcs(loaded_vmcs);
2676         return -ENOMEM;
2677 }
2678
2679 static void free_kvm_area(void)
2680 {
2681         int cpu;
2682
2683         for_each_possible_cpu(cpu) {
2684                 free_vmcs(per_cpu(vmxarea, cpu));
2685                 per_cpu(vmxarea, cpu) = NULL;
2686         }
2687 }
2688
2689 static __init int alloc_kvm_area(void)
2690 {
2691         int cpu;
2692
2693         for_each_possible_cpu(cpu) {
2694                 struct vmcs *vmcs;
2695
2696                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2697                 if (!vmcs) {
2698                         free_kvm_area();
2699                         return -ENOMEM;
2700                 }
2701
2702                 /*
2703                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2704                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2705                  * revision_id reported by MSR_IA32_VMX_BASIC.
2706                  *
2707                  * However, even though not explicitly documented by
2708                  * TLFS, VMXArea passed as VMXON argument should
2709                  * still be marked with revision_id reported by
2710                  * physical CPU.
2711                  */
2712                 if (static_branch_unlikely(&enable_evmcs))
2713                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2714
2715                 per_cpu(vmxarea, cpu) = vmcs;
2716         }
2717         return 0;
2718 }
2719
2720 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2721                 struct kvm_segment *save)
2722 {
2723         if (!emulate_invalid_guest_state) {
2724                 /*
2725                  * CS and SS RPL should be equal during guest entry according
2726                  * to VMX spec, but in reality it is not always so. Since vcpu
2727                  * is in the middle of the transition from real mode to
2728                  * protected mode it is safe to assume that RPL 0 is a good
2729                  * default value.
2730                  */
2731                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2732                         save->selector &= ~SEGMENT_RPL_MASK;
2733                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2734                 save->s = 1;
2735         }
2736         __vmx_set_segment(vcpu, save, seg);
2737 }
2738
2739 static void enter_pmode(struct kvm_vcpu *vcpu)
2740 {
2741         unsigned long flags;
2742         struct vcpu_vmx *vmx = to_vmx(vcpu);
2743
2744         /*
2745          * Update real mode segment cache. It may be not up-to-date if segment
2746          * register was written while vcpu was in a guest mode.
2747          */
2748         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2749         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2750         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2751         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2752         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2753         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2754
2755         vmx->rmode.vm86_active = 0;
2756
2757         __vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2758
2759         flags = vmcs_readl(GUEST_RFLAGS);
2760         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2761         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2762         vmcs_writel(GUEST_RFLAGS, flags);
2763
2764         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2765                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2766
2767         vmx_update_exception_bitmap(vcpu);
2768
2769         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2770         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2771         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2772         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2773         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2774         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2775 }
2776
2777 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2778 {
2779         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2780         struct kvm_segment var = *save;
2781
2782         var.dpl = 0x3;
2783         if (seg == VCPU_SREG_CS)
2784                 var.type = 0x3;
2785
2786         if (!emulate_invalid_guest_state) {
2787                 var.selector = var.base >> 4;
2788                 var.base = var.base & 0xffff0;
2789                 var.limit = 0xffff;
2790                 var.g = 0;
2791                 var.db = 0;
2792                 var.present = 1;
2793                 var.s = 1;
2794                 var.l = 0;
2795                 var.unusable = 0;
2796                 var.type = 0x3;
2797                 var.avl = 0;
2798                 if (save->base & 0xf)
2799                         printk_once(KERN_WARNING "kvm: segment base is not "
2800                                         "paragraph aligned when entering "
2801                                         "protected mode (seg=%d)", seg);
2802         }
2803
2804         vmcs_write16(sf->selector, var.selector);
2805         vmcs_writel(sf->base, var.base);
2806         vmcs_write32(sf->limit, var.limit);
2807         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2808 }
2809
2810 static void enter_rmode(struct kvm_vcpu *vcpu)
2811 {
2812         unsigned long flags;
2813         struct vcpu_vmx *vmx = to_vmx(vcpu);
2814         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2815
2816         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2817         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2818         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2819         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2820         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2821         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2822         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2823
2824         vmx->rmode.vm86_active = 1;
2825
2826         /*
2827          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2828          * vcpu. Warn the user that an update is overdue.
2829          */
2830         if (!kvm_vmx->tss_addr)
2831                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2832                              "called before entering vcpu\n");
2833
2834         vmx_segment_cache_clear(vmx);
2835
2836         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2837         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2838         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2839
2840         flags = vmcs_readl(GUEST_RFLAGS);
2841         vmx->rmode.save_rflags = flags;
2842
2843         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2844
2845         vmcs_writel(GUEST_RFLAGS, flags);
2846         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2847         vmx_update_exception_bitmap(vcpu);
2848
2849         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2850         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2851         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2852         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2853         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2854         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2855 }
2856
2857 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2858 {
2859         struct vcpu_vmx *vmx = to_vmx(vcpu);
2860         struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER);
2861
2862         /* Nothing to do if hardware doesn't support EFER. */
2863         if (!msr)
2864                 return 0;
2865
2866         vcpu->arch.efer = efer;
2867         if (efer & EFER_LMA) {
2868                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2869                 msr->data = efer;
2870         } else {
2871                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2872
2873                 msr->data = efer & ~EFER_LME;
2874         }
2875         vmx_setup_uret_msrs(vmx);
2876         return 0;
2877 }
2878
2879 #ifdef CONFIG_X86_64
2880
2881 static void enter_lmode(struct kvm_vcpu *vcpu)
2882 {
2883         u32 guest_tr_ar;
2884
2885         vmx_segment_cache_clear(to_vmx(vcpu));
2886
2887         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2888         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2889                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2890                                      __func__);
2891                 vmcs_write32(GUEST_TR_AR_BYTES,
2892                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2893                              | VMX_AR_TYPE_BUSY_64_TSS);
2894         }
2895         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2896 }
2897
2898 static void exit_lmode(struct kvm_vcpu *vcpu)
2899 {
2900         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2901         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2902 }
2903
2904 #endif
2905
2906 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2907 {
2908         struct vcpu_vmx *vmx = to_vmx(vcpu);
2909
2910         /*
2911          * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2912          * the CPU is not required to invalidate guest-physical mappings on
2913          * VM-Entry, even if VPID is disabled.  Guest-physical mappings are
2914          * associated with the root EPT structure and not any particular VPID
2915          * (INVVPID also isn't required to invalidate guest-physical mappings).
2916          */
2917         if (enable_ept) {
2918                 ept_sync_global();
2919         } else if (enable_vpid) {
2920                 if (cpu_has_vmx_invvpid_global()) {
2921                         vpid_sync_vcpu_global();
2922                 } else {
2923                         vpid_sync_vcpu_single(vmx->vpid);
2924                         vpid_sync_vcpu_single(vmx->nested.vpid02);
2925                 }
2926         }
2927 }
2928
2929 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2930 {
2931         struct kvm_mmu *mmu = vcpu->arch.mmu;
2932         u64 root_hpa = mmu->root_hpa;
2933
2934         /* No flush required if the current context is invalid. */
2935         if (!VALID_PAGE(root_hpa))
2936                 return;
2937
2938         if (enable_ept)
2939                 ept_sync_context(construct_eptp(vcpu, root_hpa,
2940                                                 mmu->shadow_root_level));
2941         else if (!is_guest_mode(vcpu))
2942                 vpid_sync_context(to_vmx(vcpu)->vpid);
2943         else
2944                 vpid_sync_context(nested_get_vpid02(vcpu));
2945 }
2946
2947 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2948 {
2949         /*
2950          * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2951          * vmx_flush_tlb_guest() for an explanation of why this is ok.
2952          */
2953         vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2954 }
2955
2956 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2957 {
2958         /*
2959          * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2960          * or a vpid couldn't be allocated for this vCPU.  VM-Enter and VM-Exit
2961          * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2962          * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2963          * i.e. no explicit INVVPID is necessary.
2964          */
2965         vpid_sync_context(to_vmx(vcpu)->vpid);
2966 }
2967
2968 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2969 {
2970         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2971
2972         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2973                 return;
2974
2975         if (is_pae_paging(vcpu)) {
2976                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2977                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2978                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2979                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2980         }
2981 }
2982
2983 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2984 {
2985         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2986
2987         if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2988                 return;
2989
2990         mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2991         mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2992         mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2993         mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2994
2995         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2996 }
2997
2998 #define CR3_EXITING_BITS (CPU_BASED_CR3_LOAD_EXITING | \
2999                           CPU_BASED_CR3_STORE_EXITING)
3000
3001 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3002 {
3003         struct vcpu_vmx *vmx = to_vmx(vcpu);
3004         unsigned long hw_cr0, old_cr0_pg;
3005         u32 tmp;
3006
3007         old_cr0_pg = kvm_read_cr0_bits(vcpu, X86_CR0_PG);
3008
3009         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3010         if (is_unrestricted_guest(vcpu))
3011                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3012         else {
3013                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3014                 if (!enable_ept)
3015                         hw_cr0 |= X86_CR0_WP;
3016
3017                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3018                         enter_pmode(vcpu);
3019
3020                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3021                         enter_rmode(vcpu);
3022         }
3023
3024         vmcs_writel(CR0_READ_SHADOW, cr0);
3025         vmcs_writel(GUEST_CR0, hw_cr0);
3026         vcpu->arch.cr0 = cr0;
3027         kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3028
3029 #ifdef CONFIG_X86_64
3030         if (vcpu->arch.efer & EFER_LME) {
3031                 if (!old_cr0_pg && (cr0 & X86_CR0_PG))
3032                         enter_lmode(vcpu);
3033                 else if (old_cr0_pg && !(cr0 & X86_CR0_PG))
3034                         exit_lmode(vcpu);
3035         }
3036 #endif
3037
3038         if (enable_ept && !is_unrestricted_guest(vcpu)) {
3039                 /*
3040                  * Ensure KVM has an up-to-date snapshot of the guest's CR3.  If
3041                  * the below code _enables_ CR3 exiting, vmx_cache_reg() will
3042                  * (correctly) stop reading vmcs.GUEST_CR3 because it thinks
3043                  * KVM's CR3 is installed.
3044                  */
3045                 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
3046                         vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
3047
3048                 /*
3049                  * When running with EPT but not unrestricted guest, KVM must
3050                  * intercept CR3 accesses when paging is _disabled_.  This is
3051                  * necessary because restricted guests can't actually run with
3052                  * paging disabled, and so KVM stuffs its own CR3 in order to
3053                  * run the guest when identity mapped page tables.
3054                  *
3055                  * Do _NOT_ check the old CR0.PG, e.g. to optimize away the
3056                  * update, it may be stale with respect to CR3 interception,
3057                  * e.g. after nested VM-Enter.
3058                  *
3059                  * Lastly, honor L1's desires, i.e. intercept CR3 loads and/or
3060                  * stores to forward them to L1, even if KVM does not need to
3061                  * intercept them to preserve its identity mapped page tables.
3062                  */
3063                 if (!(cr0 & X86_CR0_PG)) {
3064                         exec_controls_setbit(vmx, CR3_EXITING_BITS);
3065                 } else if (!is_guest_mode(vcpu)) {
3066                         exec_controls_clearbit(vmx, CR3_EXITING_BITS);
3067                 } else {
3068                         tmp = exec_controls_get(vmx);
3069                         tmp &= ~CR3_EXITING_BITS;
3070                         tmp |= get_vmcs12(vcpu)->cpu_based_vm_exec_control & CR3_EXITING_BITS;
3071                         exec_controls_set(vmx, tmp);
3072                 }
3073
3074                 /* Note, vmx_set_cr4() consumes the new vcpu->arch.cr0. */
3075                 if ((old_cr0_pg ^ cr0) & X86_CR0_PG)
3076                         vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3077         }
3078
3079         /* depends on vcpu->arch.cr0 to be set to a new value */
3080         vmx->emulation_required = emulation_required(vcpu);
3081 }
3082
3083 static int vmx_get_max_tdp_level(void)
3084 {
3085         if (cpu_has_vmx_ept_5levels())
3086                 return 5;
3087         return 4;
3088 }
3089
3090 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level)
3091 {
3092         u64 eptp = VMX_EPTP_MT_WB;
3093
3094         eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3095
3096         if (enable_ept_ad_bits &&
3097             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3098                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3099         eptp |= root_hpa;
3100
3101         return eptp;
3102 }
3103
3104 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3105                              int root_level)
3106 {
3107         struct kvm *kvm = vcpu->kvm;
3108         bool update_guest_cr3 = true;
3109         unsigned long guest_cr3;
3110         u64 eptp;
3111
3112         if (enable_ept) {
3113                 eptp = construct_eptp(vcpu, root_hpa, root_level);
3114                 vmcs_write64(EPT_POINTER, eptp);
3115
3116                 hv_track_root_tdp(vcpu, root_hpa);
3117
3118                 if (!enable_unrestricted_guest && !is_paging(vcpu))
3119                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3120                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3121                         guest_cr3 = vcpu->arch.cr3;
3122                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3123                         update_guest_cr3 = false;
3124                 vmx_ept_load_pdptrs(vcpu);
3125         } else {
3126                 guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu);
3127         }
3128
3129         if (update_guest_cr3)
3130                 vmcs_writel(GUEST_CR3, guest_cr3);
3131 }
3132
3133 static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3134 {
3135         /*
3136          * We operate under the default treatment of SMM, so VMX cannot be
3137          * enabled under SMM.  Note, whether or not VMXE is allowed at all is
3138          * handled by kvm_is_valid_cr4().
3139          */
3140         if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu))
3141                 return false;
3142
3143         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3144                 return false;
3145
3146         return true;
3147 }
3148
3149 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3150 {
3151         unsigned long old_cr4 = vcpu->arch.cr4;
3152         struct vcpu_vmx *vmx = to_vmx(vcpu);
3153         /*
3154          * Pass through host's Machine Check Enable value to hw_cr4, which
3155          * is in force while we are in guest mode.  Do not let guests control
3156          * this bit, even if host CR4.MCE == 0.
3157          */
3158         unsigned long hw_cr4;
3159
3160         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3161         if (is_unrestricted_guest(vcpu))
3162                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3163         else if (vmx->rmode.vm86_active)
3164                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3165         else
3166                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3167
3168         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3169                 if (cr4 & X86_CR4_UMIP) {
3170                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3171                         hw_cr4 &= ~X86_CR4_UMIP;
3172                 } else if (!is_guest_mode(vcpu) ||
3173                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3174                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3175                 }
3176         }
3177
3178         vcpu->arch.cr4 = cr4;
3179         kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3180
3181         if (!is_unrestricted_guest(vcpu)) {
3182                 if (enable_ept) {
3183                         if (!is_paging(vcpu)) {
3184                                 hw_cr4 &= ~X86_CR4_PAE;
3185                                 hw_cr4 |= X86_CR4_PSE;
3186                         } else if (!(cr4 & X86_CR4_PAE)) {
3187                                 hw_cr4 &= ~X86_CR4_PAE;
3188                         }
3189                 }
3190
3191                 /*
3192                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3193                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3194                  * to be manually disabled when guest switches to non-paging
3195                  * mode.
3196                  *
3197                  * If !enable_unrestricted_guest, the CPU is always running
3198                  * with CR0.PG=1 and CR4 needs to be modified.
3199                  * If enable_unrestricted_guest, the CPU automatically
3200                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3201                  */
3202                 if (!is_paging(vcpu))
3203                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3204         }
3205
3206         vmcs_writel(CR4_READ_SHADOW, cr4);
3207         vmcs_writel(GUEST_CR4, hw_cr4);
3208
3209         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
3210                 kvm_update_cpuid_runtime(vcpu);
3211 }
3212
3213 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3214 {
3215         struct vcpu_vmx *vmx = to_vmx(vcpu);
3216         u32 ar;
3217
3218         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3219                 *var = vmx->rmode.segs[seg];
3220                 if (seg == VCPU_SREG_TR
3221                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3222                         return;
3223                 var->base = vmx_read_guest_seg_base(vmx, seg);
3224                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3225                 return;
3226         }
3227         var->base = vmx_read_guest_seg_base(vmx, seg);
3228         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3229         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3230         ar = vmx_read_guest_seg_ar(vmx, seg);
3231         var->unusable = (ar >> 16) & 1;
3232         var->type = ar & 15;
3233         var->s = (ar >> 4) & 1;
3234         var->dpl = (ar >> 5) & 3;
3235         /*
3236          * Some userspaces do not preserve unusable property. Since usable
3237          * segment has to be present according to VMX spec we can use present
3238          * property to amend userspace bug by making unusable segment always
3239          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3240          * segment as unusable.
3241          */
3242         var->present = !var->unusable;
3243         var->avl = (ar >> 12) & 1;
3244         var->l = (ar >> 13) & 1;
3245         var->db = (ar >> 14) & 1;
3246         var->g = (ar >> 15) & 1;
3247 }
3248
3249 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3250 {
3251         struct kvm_segment s;
3252
3253         if (to_vmx(vcpu)->rmode.vm86_active) {
3254                 vmx_get_segment(vcpu, &s, seg);
3255                 return s.base;
3256         }
3257         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3258 }
3259
3260 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3261 {
3262         struct vcpu_vmx *vmx = to_vmx(vcpu);
3263
3264         if (unlikely(vmx->rmode.vm86_active))
3265                 return 0;
3266         else {
3267                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3268                 return VMX_AR_DPL(ar);
3269         }
3270 }
3271
3272 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3273 {
3274         u32 ar;
3275
3276         if (var->unusable || !var->present)
3277                 ar = 1 << 16;
3278         else {
3279                 ar = var->type & 15;
3280                 ar |= (var->s & 1) << 4;
3281                 ar |= (var->dpl & 3) << 5;
3282                 ar |= (var->present & 1) << 7;
3283                 ar |= (var->avl & 1) << 12;
3284                 ar |= (var->l & 1) << 13;
3285                 ar |= (var->db & 1) << 14;
3286                 ar |= (var->g & 1) << 15;
3287         }
3288
3289         return ar;
3290 }
3291
3292 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3293 {
3294         struct vcpu_vmx *vmx = to_vmx(vcpu);
3295         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3296
3297         vmx_segment_cache_clear(vmx);
3298
3299         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3300                 vmx->rmode.segs[seg] = *var;
3301                 if (seg == VCPU_SREG_TR)
3302                         vmcs_write16(sf->selector, var->selector);
3303                 else if (var->s)
3304                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3305                 return;
3306         }
3307
3308         vmcs_writel(sf->base, var->base);
3309         vmcs_write32(sf->limit, var->limit);
3310         vmcs_write16(sf->selector, var->selector);
3311
3312         /*
3313          *   Fix the "Accessed" bit in AR field of segment registers for older
3314          * qemu binaries.
3315          *   IA32 arch specifies that at the time of processor reset the
3316          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3317          * is setting it to 0 in the userland code. This causes invalid guest
3318          * state vmexit when "unrestricted guest" mode is turned on.
3319          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3320          * tree. Newer qemu binaries with that qemu fix would not need this
3321          * kvm hack.
3322          */
3323         if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3324                 var->type |= 0x1; /* Accessed */
3325
3326         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3327 }
3328
3329 static void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3330 {
3331         __vmx_set_segment(vcpu, var, seg);
3332
3333         to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
3334 }
3335
3336 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3337 {
3338         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3339
3340         *db = (ar >> 14) & 1;
3341         *l = (ar >> 13) & 1;
3342 }
3343
3344 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3345 {
3346         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3347         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3348 }
3349
3350 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3351 {
3352         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3353         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3354 }
3355
3356 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3357 {
3358         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3359         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3360 }
3361
3362 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3363 {
3364         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3365         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3366 }
3367
3368 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3369 {
3370         struct kvm_segment var;
3371         u32 ar;
3372
3373         vmx_get_segment(vcpu, &var, seg);
3374         var.dpl = 0x3;
3375         if (seg == VCPU_SREG_CS)
3376                 var.type = 0x3;
3377         ar = vmx_segment_access_rights(&var);
3378
3379         if (var.base != (var.selector << 4))
3380                 return false;
3381         if (var.limit != 0xffff)
3382                 return false;
3383         if (ar != 0xf3)
3384                 return false;
3385
3386         return true;
3387 }
3388
3389 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3390 {
3391         struct kvm_segment cs;
3392         unsigned int cs_rpl;
3393
3394         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3395         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3396
3397         if (cs.unusable)
3398                 return false;
3399         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3400                 return false;
3401         if (!cs.s)
3402                 return false;
3403         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3404                 if (cs.dpl > cs_rpl)
3405                         return false;
3406         } else {
3407                 if (cs.dpl != cs_rpl)
3408                         return false;
3409         }
3410         if (!cs.present)
3411                 return false;
3412
3413         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3414         return true;
3415 }
3416
3417 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3418 {
3419         struct kvm_segment ss;
3420         unsigned int ss_rpl;
3421
3422         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3423         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3424
3425         if (ss.unusable)
3426                 return true;
3427         if (ss.type != 3 && ss.type != 7)
3428                 return false;
3429         if (!ss.s)
3430                 return false;
3431         if (ss.dpl != ss_rpl) /* DPL != RPL */
3432                 return false;
3433         if (!ss.present)
3434                 return false;
3435
3436         return true;
3437 }
3438
3439 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3440 {
3441         struct kvm_segment var;
3442         unsigned int rpl;
3443
3444         vmx_get_segment(vcpu, &var, seg);
3445         rpl = var.selector & SEGMENT_RPL_MASK;
3446
3447         if (var.unusable)
3448                 return true;
3449         if (!var.s)
3450                 return false;
3451         if (!var.present)
3452                 return false;
3453         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3454                 if (var.dpl < rpl) /* DPL < RPL */
3455                         return false;
3456         }
3457
3458         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3459          * rights flags
3460          */
3461         return true;
3462 }
3463
3464 static bool tr_valid(struct kvm_vcpu *vcpu)
3465 {
3466         struct kvm_segment tr;
3467
3468         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3469
3470         if (tr.unusable)
3471                 return false;
3472         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3473                 return false;
3474         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3475                 return false;
3476         if (!tr.present)
3477                 return false;
3478
3479         return true;
3480 }
3481
3482 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3483 {
3484         struct kvm_segment ldtr;
3485
3486         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3487
3488         if (ldtr.unusable)
3489                 return true;
3490         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3491                 return false;
3492         if (ldtr.type != 2)
3493                 return false;
3494         if (!ldtr.present)
3495                 return false;
3496
3497         return true;
3498 }
3499
3500 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3501 {
3502         struct kvm_segment cs, ss;
3503
3504         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3505         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3506
3507         return ((cs.selector & SEGMENT_RPL_MASK) ==
3508                  (ss.selector & SEGMENT_RPL_MASK));
3509 }
3510
3511 /*
3512  * Check if guest state is valid. Returns true if valid, false if
3513  * not.
3514  * We assume that registers are always usable
3515  */
3516 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu)
3517 {
3518         /* real mode guest state checks */
3519         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3520                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3521                         return false;
3522                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3523                         return false;
3524                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3525                         return false;
3526                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3527                         return false;
3528                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3529                         return false;
3530                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3531                         return false;
3532         } else {
3533         /* protected mode guest state checks */
3534                 if (!cs_ss_rpl_check(vcpu))
3535                         return false;
3536                 if (!code_segment_valid(vcpu))
3537                         return false;
3538                 if (!stack_segment_valid(vcpu))
3539                         return false;
3540                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3541                         return false;
3542                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3543                         return false;
3544                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3545                         return false;
3546                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3547                         return false;
3548                 if (!tr_valid(vcpu))
3549                         return false;
3550                 if (!ldtr_valid(vcpu))
3551                         return false;
3552         }
3553         /* TODO:
3554          * - Add checks on RIP
3555          * - Add checks on RFLAGS
3556          */
3557
3558         return true;
3559 }
3560
3561 static int init_rmode_tss(struct kvm *kvm, void __user *ua)
3562 {
3563         const void *zero_page = (const void *) __va(page_to_phys(ZERO_PAGE(0)));
3564         u16 data;
3565         int i;
3566
3567         for (i = 0; i < 3; i++) {
3568                 if (__copy_to_user(ua + PAGE_SIZE * i, zero_page, PAGE_SIZE))
3569                         return -EFAULT;
3570         }
3571
3572         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3573         if (__copy_to_user(ua + TSS_IOPB_BASE_OFFSET, &data, sizeof(u16)))
3574                 return -EFAULT;
3575
3576         data = ~0;
3577         if (__copy_to_user(ua + RMODE_TSS_SIZE - 1, &data, sizeof(u8)))
3578                 return -EFAULT;
3579
3580         return 0;
3581 }
3582
3583 static int init_rmode_identity_map(struct kvm *kvm)
3584 {
3585         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3586         int i, r = 0;
3587         void __user *uaddr;
3588         u32 tmp;
3589
3590         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3591         mutex_lock(&kvm->slots_lock);
3592
3593         if (likely(kvm_vmx->ept_identity_pagetable_done))
3594                 goto out;
3595
3596         if (!kvm_vmx->ept_identity_map_addr)
3597                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3598
3599         uaddr = __x86_set_memory_region(kvm,
3600                                         IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3601                                         kvm_vmx->ept_identity_map_addr,
3602                                         PAGE_SIZE);
3603         if (IS_ERR(uaddr)) {
3604                 r = PTR_ERR(uaddr);
3605                 goto out;
3606         }
3607
3608         /* Set up identity-mapping pagetable for EPT in real mode */
3609         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3610                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3611                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3612                 if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) {
3613                         r = -EFAULT;
3614                         goto out;
3615                 }
3616         }
3617         kvm_vmx->ept_identity_pagetable_done = true;
3618
3619 out:
3620         mutex_unlock(&kvm->slots_lock);
3621         return r;
3622 }
3623
3624 static void seg_setup(int seg)
3625 {
3626         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3627         unsigned int ar;
3628
3629         vmcs_write16(sf->selector, 0);
3630         vmcs_writel(sf->base, 0);
3631         vmcs_write32(sf->limit, 0xffff);
3632         ar = 0x93;
3633         if (seg == VCPU_SREG_CS)
3634                 ar |= 0x08; /* code segment */
3635
3636         vmcs_write32(sf->ar_bytes, ar);
3637 }
3638
3639 static int alloc_apic_access_page(struct kvm *kvm)
3640 {
3641         struct page *page;
3642         void __user *hva;
3643         int ret = 0;
3644
3645         mutex_lock(&kvm->slots_lock);
3646         if (kvm->arch.apic_access_memslot_enabled)
3647                 goto out;
3648         hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3649                                       APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3650         if (IS_ERR(hva)) {
3651                 ret = PTR_ERR(hva);
3652                 goto out;
3653         }
3654
3655         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3656         if (is_error_page(page)) {
3657                 ret = -EFAULT;
3658                 goto out;
3659         }
3660
3661         /*
3662          * Do not pin the page in memory, so that memory hot-unplug
3663          * is able to migrate it.
3664          */
3665         put_page(page);
3666         kvm->arch.apic_access_memslot_enabled = true;
3667 out:
3668         mutex_unlock(&kvm->slots_lock);
3669         return ret;
3670 }
3671
3672 int allocate_vpid(void)
3673 {
3674         int vpid;
3675
3676         if (!enable_vpid)
3677                 return 0;
3678         spin_lock(&vmx_vpid_lock);
3679         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3680         if (vpid < VMX_NR_VPIDS)
3681                 __set_bit(vpid, vmx_vpid_bitmap);
3682         else
3683                 vpid = 0;
3684         spin_unlock(&vmx_vpid_lock);
3685         return vpid;
3686 }
3687
3688 void free_vpid(int vpid)
3689 {
3690         if (!enable_vpid || vpid == 0)
3691                 return;
3692         spin_lock(&vmx_vpid_lock);
3693         __clear_bit(vpid, vmx_vpid_bitmap);
3694         spin_unlock(&vmx_vpid_lock);
3695 }
3696
3697 static void vmx_clear_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3698 {
3699         int f = sizeof(unsigned long);
3700
3701         if (msr <= 0x1fff)
3702                 __clear_bit(msr, msr_bitmap + 0x000 / f);
3703         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3704                 __clear_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3705 }
3706
3707 static void vmx_clear_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3708 {
3709         int f = sizeof(unsigned long);
3710
3711         if (msr <= 0x1fff)
3712                 __clear_bit(msr, msr_bitmap + 0x800 / f);
3713         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3714                 __clear_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3715 }
3716
3717 static void vmx_set_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3718 {
3719         int f = sizeof(unsigned long);
3720
3721         if (msr <= 0x1fff)
3722                 __set_bit(msr, msr_bitmap + 0x000 / f);
3723         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3724                 __set_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3725 }
3726
3727 static void vmx_set_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3728 {
3729         int f = sizeof(unsigned long);
3730
3731         if (msr <= 0x1fff)
3732                 __set_bit(msr, msr_bitmap + 0x800 / f);
3733         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3734                 __set_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3735 }
3736
3737 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3738 {
3739         struct vcpu_vmx *vmx = to_vmx(vcpu);
3740         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3741
3742         if (!cpu_has_vmx_msr_bitmap())
3743                 return;
3744
3745         if (static_branch_unlikely(&enable_evmcs))
3746                 evmcs_touch_msr_bitmap();
3747
3748         /*
3749          * Mark the desired intercept state in shadow bitmap, this is needed
3750          * for resync when the MSR filters change.
3751         */
3752         if (is_valid_passthrough_msr(msr)) {
3753                 int idx = possible_passthrough_msr_slot(msr);
3754
3755                 if (idx != -ENOENT) {
3756                         if (type & MSR_TYPE_R)
3757                                 clear_bit(idx, vmx->shadow_msr_intercept.read);
3758                         if (type & MSR_TYPE_W)
3759                                 clear_bit(idx, vmx->shadow_msr_intercept.write);
3760                 }
3761         }
3762
3763         if ((type & MSR_TYPE_R) &&
3764             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) {
3765                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3766                 type &= ~MSR_TYPE_R;
3767         }
3768
3769         if ((type & MSR_TYPE_W) &&
3770             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) {
3771                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3772                 type &= ~MSR_TYPE_W;
3773         }
3774
3775         if (type & MSR_TYPE_R)
3776                 vmx_clear_msr_bitmap_read(msr_bitmap, msr);
3777
3778         if (type & MSR_TYPE_W)
3779                 vmx_clear_msr_bitmap_write(msr_bitmap, msr);
3780 }
3781
3782 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3783 {
3784         struct vcpu_vmx *vmx = to_vmx(vcpu);
3785         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3786
3787         if (!cpu_has_vmx_msr_bitmap())
3788                 return;
3789
3790         if (static_branch_unlikely(&enable_evmcs))
3791                 evmcs_touch_msr_bitmap();
3792
3793         /*
3794          * Mark the desired intercept state in shadow bitmap, this is needed
3795          * for resync when the MSR filter changes.
3796         */
3797         if (is_valid_passthrough_msr(msr)) {
3798                 int idx = possible_passthrough_msr_slot(msr);
3799
3800                 if (idx != -ENOENT) {
3801                         if (type & MSR_TYPE_R)
3802                                 set_bit(idx, vmx->shadow_msr_intercept.read);
3803                         if (type & MSR_TYPE_W)
3804                                 set_bit(idx, vmx->shadow_msr_intercept.write);
3805                 }
3806         }
3807
3808         if (type & MSR_TYPE_R)
3809                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3810
3811         if (type & MSR_TYPE_W)
3812                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3813 }
3814
3815 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3816 {
3817         u8 mode = 0;
3818
3819         if (cpu_has_secondary_exec_ctrls() &&
3820             (secondary_exec_controls_get(to_vmx(vcpu)) &
3821              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3822                 mode |= MSR_BITMAP_MODE_X2APIC;
3823                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3824                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3825         }
3826
3827         return mode;
3828 }
3829
3830 static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode)
3831 {
3832         unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
3833         unsigned long read_intercept;
3834         int msr;
3835
3836         read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3837
3838         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3839                 unsigned int read_idx = msr / BITS_PER_LONG;
3840                 unsigned int write_idx = read_idx + (0x800 / sizeof(long));
3841
3842                 msr_bitmap[read_idx] = read_intercept;
3843                 msr_bitmap[write_idx] = ~0ul;
3844         }
3845 }
3846
3847 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu, u8 mode)
3848 {
3849         if (!cpu_has_vmx_msr_bitmap())
3850                 return;
3851
3852         vmx_reset_x2apic_msrs(vcpu, mode);
3853
3854         /*
3855          * TPR reads and writes can be virtualized even if virtual interrupt
3856          * delivery is not in use.
3857          */
3858         vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
3859                                   !(mode & MSR_BITMAP_MODE_X2APIC));
3860
3861         if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3862                 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
3863                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3864                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3865         }
3866 }
3867
3868 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3869 {
3870         struct vcpu_vmx *vmx = to_vmx(vcpu);
3871         u8 mode = vmx_msr_bitmap_mode(vcpu);
3872         u8 changed = mode ^ vmx->msr_bitmap_mode;
3873
3874         if (!changed)
3875                 return;
3876
3877         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3878                 vmx_update_msr_bitmap_x2apic(vcpu, mode);
3879
3880         vmx->msr_bitmap_mode = mode;
3881 }
3882
3883 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu)
3884 {
3885         struct vcpu_vmx *vmx = to_vmx(vcpu);
3886         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3887         u32 i;
3888
3889         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
3890         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
3891         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
3892         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
3893         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3894                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3895                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3896         }
3897 }
3898
3899 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3900 {
3901         struct vcpu_vmx *vmx = to_vmx(vcpu);
3902         void *vapic_page;
3903         u32 vppr;
3904         int rvi;
3905
3906         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3907                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3908                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3909                 return false;
3910
3911         rvi = vmx_get_rvi();
3912
3913         vapic_page = vmx->nested.virtual_apic_map.hva;
3914         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3915
3916         return ((rvi & 0xf0) > (vppr & 0xf0));
3917 }
3918
3919 static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
3920 {
3921         struct vcpu_vmx *vmx = to_vmx(vcpu);
3922         u32 i;
3923
3924         /*
3925          * Set intercept permissions for all potentially passed through MSRs
3926          * again. They will automatically get filtered through the MSR filter,
3927          * so we are back in sync after this.
3928          */
3929         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
3930                 u32 msr = vmx_possible_passthrough_msrs[i];
3931                 bool read = test_bit(i, vmx->shadow_msr_intercept.read);
3932                 bool write = test_bit(i, vmx->shadow_msr_intercept.write);
3933
3934                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
3935                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
3936         }
3937
3938         pt_update_intercept_for_msr(vcpu);
3939 }
3940
3941 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3942                                                      bool nested)
3943 {
3944 #ifdef CONFIG_SMP
3945         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3946
3947         if (vcpu->mode == IN_GUEST_MODE) {
3948                 /*
3949                  * The vector of interrupt to be delivered to vcpu had
3950                  * been set in PIR before this function.
3951                  *
3952                  * Following cases will be reached in this block, and
3953                  * we always send a notification event in all cases as
3954                  * explained below.
3955                  *
3956                  * Case 1: vcpu keeps in non-root mode. Sending a
3957                  * notification event posts the interrupt to vcpu.
3958                  *
3959                  * Case 2: vcpu exits to root mode and is still
3960                  * runnable. PIR will be synced to vIRR before the
3961                  * next vcpu entry. Sending a notification event in
3962                  * this case has no effect, as vcpu is not in root
3963                  * mode.
3964                  *
3965                  * Case 3: vcpu exits to root mode and is blocked.
3966                  * vcpu_block() has already synced PIR to vIRR and
3967                  * never blocks vcpu if vIRR is not cleared. Therefore,
3968                  * a blocked vcpu here does not wait for any requested
3969                  * interrupts in PIR, and sending a notification event
3970                  * which has no effect is safe here.
3971                  */
3972
3973                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3974                 return true;
3975         }
3976 #endif
3977         return false;
3978 }
3979
3980 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3981                                                 int vector)
3982 {
3983         struct vcpu_vmx *vmx = to_vmx(vcpu);
3984
3985         if (is_guest_mode(vcpu) &&
3986             vector == vmx->nested.posted_intr_nv) {
3987                 /*
3988                  * If a posted intr is not recognized by hardware,
3989                  * we will accomplish it in the next vmentry.
3990                  */
3991                 vmx->nested.pi_pending = true;
3992                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3993                 /* the PIR and ON have been set by L1. */
3994                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3995                         kvm_vcpu_kick(vcpu);
3996                 return 0;
3997         }
3998         return -1;
3999 }
4000 /*
4001  * Send interrupt to vcpu via posted interrupt way.
4002  * 1. If target vcpu is running(non-root mode), send posted interrupt
4003  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4004  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4005  * interrupt from PIR in next vmentry.
4006  */
4007 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4008 {
4009         struct vcpu_vmx *vmx = to_vmx(vcpu);
4010         int r;
4011
4012         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4013         if (!r)
4014                 return 0;
4015
4016         if (!vcpu->arch.apicv_active)
4017                 return -1;
4018
4019         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4020                 return 0;
4021
4022         /* If a previous notification has sent the IPI, nothing to do.  */
4023         if (pi_test_and_set_on(&vmx->pi_desc))
4024                 return 0;
4025
4026         if (vcpu != kvm_get_running_vcpu() &&
4027             !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
4028                 kvm_vcpu_kick(vcpu);
4029
4030         return 0;
4031 }
4032
4033 /*
4034  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4035  * will not change in the lifetime of the guest.
4036  * Note that host-state that does change is set elsewhere. E.g., host-state
4037  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4038  */
4039 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4040 {
4041         u32 low32, high32;
4042         unsigned long tmpl;
4043         unsigned long cr0, cr3, cr4;
4044
4045         cr0 = read_cr0();
4046         WARN_ON(cr0 & X86_CR0_TS);
4047         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
4048
4049         /*
4050          * Save the most likely value for this task's CR3 in the VMCS.
4051          * We can't use __get_current_cr3_fast() because we're not atomic.
4052          */
4053         cr3 = __read_cr3();
4054         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
4055         vmx->loaded_vmcs->host_state.cr3 = cr3;
4056
4057         /* Save the most likely value for this task's CR4 in the VMCS. */
4058         cr4 = cr4_read_shadow();
4059         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4060         vmx->loaded_vmcs->host_state.cr4 = cr4;
4061
4062         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4063 #ifdef CONFIG_X86_64
4064         /*
4065          * Load null selectors, so we can avoid reloading them in
4066          * vmx_prepare_switch_to_host(), in case userspace uses
4067          * the null selectors too (the expected case).
4068          */
4069         vmcs_write16(HOST_DS_SELECTOR, 0);
4070         vmcs_write16(HOST_ES_SELECTOR, 0);
4071 #else
4072         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4073         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4074 #endif
4075         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4076         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4077
4078         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
4079
4080         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4081
4082         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4083         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4084         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4085         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4086
4087         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4088                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4089                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4090         }
4091
4092         if (cpu_has_load_ia32_efer())
4093                 vmcs_write64(HOST_IA32_EFER, host_efer);
4094 }
4095
4096 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4097 {
4098         struct kvm_vcpu *vcpu = &vmx->vcpu;
4099
4100         vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
4101                                           ~vcpu->arch.cr4_guest_rsvd_bits;
4102         if (!enable_ept)
4103                 vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4104         if (is_guest_mode(&vmx->vcpu))
4105                 vcpu->arch.cr4_guest_owned_bits &=
4106                         ~get_vmcs12(vcpu)->cr4_guest_host_mask;
4107         vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits);
4108 }
4109
4110 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4111 {
4112         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4113
4114         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4115                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4116
4117         if (!enable_vnmi)
4118                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4119
4120         if (!enable_preemption_timer)
4121                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4122
4123         return pin_based_exec_ctrl;
4124 }
4125
4126 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4127 {
4128         struct vcpu_vmx *vmx = to_vmx(vcpu);
4129
4130         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4131         if (cpu_has_secondary_exec_ctrls()) {
4132                 if (kvm_vcpu_apicv_active(vcpu))
4133                         secondary_exec_controls_setbit(vmx,
4134                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4135                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4136                 else
4137                         secondary_exec_controls_clearbit(vmx,
4138                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4139                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4140         }
4141
4142         if (cpu_has_vmx_msr_bitmap())
4143                 vmx_update_msr_bitmap(vcpu);
4144 }
4145
4146 u32 vmx_exec_control(struct vcpu_vmx *vmx)
4147 {
4148         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4149
4150         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4151                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4152
4153         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4154                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4155 #ifdef CONFIG_X86_64
4156                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4157                                 CPU_BASED_CR8_LOAD_EXITING;
4158 #endif
4159         }
4160         if (!enable_ept)
4161                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4162                                 CPU_BASED_CR3_LOAD_EXITING  |
4163                                 CPU_BASED_INVLPG_EXITING;
4164         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4165                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4166                                 CPU_BASED_MONITOR_EXITING);
4167         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4168                 exec_control &= ~CPU_BASED_HLT_EXITING;
4169         return exec_control;
4170 }
4171
4172 /*
4173  * Adjust a single secondary execution control bit to intercept/allow an
4174  * instruction in the guest.  This is usually done based on whether or not a
4175  * feature has been exposed to the guest in order to correctly emulate faults.
4176  */
4177 static inline void
4178 vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control,
4179                                   u32 control, bool enabled, bool exiting)
4180 {
4181         /*
4182          * If the control is for an opt-in feature, clear the control if the
4183          * feature is not exposed to the guest, i.e. not enabled.  If the
4184          * control is opt-out, i.e. an exiting control, clear the control if
4185          * the feature _is_ exposed to the guest, i.e. exiting/interception is
4186          * disabled for the associated instruction.  Note, the caller is
4187          * responsible presetting exec_control to set all supported bits.
4188          */
4189         if (enabled == exiting)
4190                 *exec_control &= ~control;
4191
4192         /*
4193          * Update the nested MSR settings so that a nested VMM can/can't set
4194          * controls for features that are/aren't exposed to the guest.
4195          */
4196         if (nested) {
4197                 if (enabled)
4198                         vmx->nested.msrs.secondary_ctls_high |= control;
4199                 else
4200                         vmx->nested.msrs.secondary_ctls_high &= ~control;
4201         }
4202 }
4203
4204 /*
4205  * Wrapper macro for the common case of adjusting a secondary execution control
4206  * based on a single guest CPUID bit, with a dedicated feature bit.  This also
4207  * verifies that the control is actually supported by KVM and hardware.
4208  */
4209 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \
4210 ({                                                                       \
4211         bool __enabled;                                                  \
4212                                                                          \
4213         if (cpu_has_vmx_##name()) {                                      \
4214                 __enabled = guest_cpuid_has(&(vmx)->vcpu,                \
4215                                             X86_FEATURE_##feat_name);    \
4216                 vmx_adjust_secondary_exec_control(vmx, exec_control,     \
4217                         SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \
4218         }                                                                \
4219 })
4220
4221 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */
4222 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \
4223         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false)
4224
4225 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \
4226         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true)
4227
4228 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4229 {
4230         struct kvm_vcpu *vcpu = &vmx->vcpu;
4231
4232         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4233
4234         if (vmx_pt_mode_is_system())
4235                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4236         if (!cpu_need_virtualize_apic_accesses(vcpu))
4237                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4238         if (vmx->vpid == 0)
4239                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4240         if (!enable_ept) {
4241                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4242                 enable_unrestricted_guest = 0;
4243         }
4244         if (!enable_unrestricted_guest)
4245                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4246         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4247                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4248         if (!kvm_vcpu_apicv_active(vcpu))
4249                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4250                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4251         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4252
4253         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4254          * in vmx_set_cr4.  */
4255         exec_control &= ~SECONDARY_EXEC_DESC;
4256
4257         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4258            (handle_vmptrld).
4259            We can NOT enable shadow_vmcs here because we don't have yet
4260            a current VMCS12
4261         */
4262         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4263
4264         /*
4265          * PML is enabled/disabled when dirty logging of memsmlots changes, but
4266          * it needs to be set here when dirty logging is already active, e.g.
4267          * if this vCPU was created after dirty logging was enabled.
4268          */
4269         if (!vcpu->kvm->arch.cpu_dirty_logging_count)
4270                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4271
4272         if (cpu_has_vmx_xsaves()) {
4273                 /* Exposing XSAVES only when XSAVE is exposed */
4274                 bool xsaves_enabled =
4275                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4276                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4277                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4278
4279                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4280
4281                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4282                                                   SECONDARY_EXEC_XSAVES,
4283                                                   xsaves_enabled, false);
4284         }
4285
4286         /*
4287          * RDPID is also gated by ENABLE_RDTSCP, turn on the control if either
4288          * feature is exposed to the guest.  This creates a virtualization hole
4289          * if both are supported in hardware but only one is exposed to the
4290          * guest, but letting the guest execute RDTSCP or RDPID when either one
4291          * is advertised is preferable to emulating the advertised instruction
4292          * in KVM on #UD, and obviously better than incorrectly injecting #UD.
4293          */
4294         if (cpu_has_vmx_rdtscp()) {
4295                 bool rdpid_or_rdtscp_enabled =
4296                         guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) ||
4297                         guest_cpuid_has(vcpu, X86_FEATURE_RDPID);
4298
4299                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4300                                                   SECONDARY_EXEC_ENABLE_RDTSCP,
4301                                                   rdpid_or_rdtscp_enabled, false);
4302         }
4303         vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID);
4304
4305         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND);
4306         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED);
4307
4308         vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG,
4309                                     ENABLE_USR_WAIT_PAUSE, false);
4310
4311         if (!vcpu->kvm->arch.bus_lock_detection_enabled)
4312                 exec_control &= ~SECONDARY_EXEC_BUS_LOCK_DETECTION;
4313
4314         vmx->secondary_exec_control = exec_control;
4315 }
4316
4317 #define VMX_XSS_EXIT_BITMAP 0
4318
4319 /*
4320  * Noting that the initialization of Guest-state Area of VMCS is in
4321  * vmx_vcpu_reset().
4322  */
4323 static void init_vmcs(struct vcpu_vmx *vmx)
4324 {
4325         if (nested)
4326                 nested_vmx_set_vmcs_shadowing_bitmap();
4327
4328         if (cpu_has_vmx_msr_bitmap())
4329                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4330
4331         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4332
4333         /* Control */
4334         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4335
4336         exec_controls_set(vmx, vmx_exec_control(vmx));
4337
4338         if (cpu_has_secondary_exec_ctrls()) {
4339                 vmx_compute_secondary_exec_control(vmx);
4340                 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4341         }
4342
4343         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4344                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4345                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4346                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4347                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4348
4349                 vmcs_write16(GUEST_INTR_STATUS, 0);
4350
4351                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4352                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4353         }
4354
4355         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4356                 vmcs_write32(PLE_GAP, ple_gap);
4357                 vmx->ple_window = ple_window;
4358                 vmx->ple_window_dirty = true;
4359         }
4360
4361         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4362         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4363         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4364
4365         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4366         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4367         vmx_set_constant_host_state(vmx);
4368         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4369         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4370
4371         if (cpu_has_vmx_vmfunc())
4372                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4373
4374         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4375         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4376         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4377         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4378         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4379
4380         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4381                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4382
4383         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4384
4385         /* 22.2.1, 20.8.1 */
4386         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4387
4388         vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4389         vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4390
4391         set_cr4_guest_host_mask(vmx);
4392
4393         if (vmx->vpid != 0)
4394                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4395
4396         if (cpu_has_vmx_xsaves())
4397                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4398
4399         if (enable_pml) {
4400                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4401                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4402         }
4403
4404         vmx_write_encls_bitmap(&vmx->vcpu, NULL);
4405
4406         if (vmx_pt_mode_is_host_guest()) {
4407                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4408                 /* Bit[6~0] are forced to 1, writes are ignored. */
4409                 vmx->pt_desc.guest.output_mask = 0x7F;
4410                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4411         }
4412
4413         vmx_setup_uret_msrs(vmx);
4414 }
4415
4416 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4417 {
4418         struct vcpu_vmx *vmx = to_vmx(vcpu);
4419
4420         vmx->rmode.vm86_active = 0;
4421         vmx->spec_ctrl = 0;
4422
4423         vmx->msr_ia32_umwait_control = 0;
4424
4425         vmx->hv_deadline_tsc = -1;
4426         kvm_set_cr8(vcpu, 0);
4427
4428         vmx_segment_cache_clear(vmx);
4429
4430         seg_setup(VCPU_SREG_CS);
4431         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4432         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4433
4434         seg_setup(VCPU_SREG_DS);
4435         seg_setup(VCPU_SREG_ES);
4436         seg_setup(VCPU_SREG_FS);
4437         seg_setup(VCPU_SREG_GS);
4438         seg_setup(VCPU_SREG_SS);
4439
4440         vmcs_write16(GUEST_TR_SELECTOR, 0);
4441         vmcs_writel(GUEST_TR_BASE, 0);
4442         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4443         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4444
4445         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4446         vmcs_writel(GUEST_LDTR_BASE, 0);
4447         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4448         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4449
4450         if (!init_event) {
4451                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4452                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4453                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4454                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4455         }
4456
4457         vmcs_writel(GUEST_GDTR_BASE, 0);
4458         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4459
4460         vmcs_writel(GUEST_IDTR_BASE, 0);
4461         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4462
4463         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4464         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4465         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4466         if (kvm_mpx_supported())
4467                 vmcs_write64(GUEST_BNDCFGS, 0);
4468
4469         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4470
4471         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4472                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4473                 if (cpu_need_tpr_shadow(vcpu))
4474                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4475                                      __pa(vcpu->arch.apic->regs));
4476                 vmcs_write32(TPR_THRESHOLD, 0);
4477         }
4478
4479         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4480
4481         vpid_sync_context(vmx->vpid);
4482         if (init_event)
4483                 vmx_clear_hlt(vcpu);
4484 }
4485
4486 static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
4487 {
4488         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4489 }
4490
4491 static void vmx_enable_nmi_window(struct kvm_vcpu *vcpu)
4492 {
4493         if (!enable_vnmi ||
4494             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4495                 vmx_enable_irq_window(vcpu);
4496                 return;
4497         }
4498
4499         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4500 }
4501
4502 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4503 {
4504         struct vcpu_vmx *vmx = to_vmx(vcpu);
4505         uint32_t intr;
4506         int irq = vcpu->arch.interrupt.nr;
4507
4508         trace_kvm_inj_virq(irq);
4509
4510         ++vcpu->stat.irq_injections;
4511         if (vmx->rmode.vm86_active) {
4512                 int inc_eip = 0;
4513                 if (vcpu->arch.interrupt.soft)
4514                         inc_eip = vcpu->arch.event_exit_inst_len;
4515                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4516                 return;
4517         }
4518         intr = irq | INTR_INFO_VALID_MASK;
4519         if (vcpu->arch.interrupt.soft) {
4520                 intr |= INTR_TYPE_SOFT_INTR;
4521                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4522                              vmx->vcpu.arch.event_exit_inst_len);
4523         } else
4524                 intr |= INTR_TYPE_EXT_INTR;
4525         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4526
4527         vmx_clear_hlt(vcpu);
4528 }
4529
4530 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4531 {
4532         struct vcpu_vmx *vmx = to_vmx(vcpu);
4533
4534         if (!enable_vnmi) {
4535                 /*
4536                  * Tracking the NMI-blocked state in software is built upon
4537                  * finding the next open IRQ window. This, in turn, depends on
4538                  * well-behaving guests: They have to keep IRQs disabled at
4539                  * least as long as the NMI handler runs. Otherwise we may
4540                  * cause NMI nesting, maybe breaking the guest. But as this is
4541                  * highly unlikely, we can live with the residual risk.
4542                  */
4543                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4544                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4545         }
4546
4547         ++vcpu->stat.nmi_injections;
4548         vmx->loaded_vmcs->nmi_known_unmasked = false;
4549
4550         if (vmx->rmode.vm86_active) {
4551                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4552                 return;
4553         }
4554
4555         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4556                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4557
4558         vmx_clear_hlt(vcpu);
4559 }
4560
4561 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4562 {
4563         struct vcpu_vmx *vmx = to_vmx(vcpu);
4564         bool masked;
4565
4566         if (!enable_vnmi)
4567                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4568         if (vmx->loaded_vmcs->nmi_known_unmasked)
4569                 return false;
4570         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4571         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4572         return masked;
4573 }
4574
4575 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4576 {
4577         struct vcpu_vmx *vmx = to_vmx(vcpu);
4578
4579         if (!enable_vnmi) {
4580                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4581                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4582                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4583                 }
4584         } else {
4585                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4586                 if (masked)
4587                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4588                                       GUEST_INTR_STATE_NMI);
4589                 else
4590                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4591                                         GUEST_INTR_STATE_NMI);
4592         }
4593 }
4594
4595 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4596 {
4597         if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4598                 return false;
4599
4600         if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4601                 return true;
4602
4603         return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4604                 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4605                  GUEST_INTR_STATE_NMI));
4606 }
4607
4608 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4609 {
4610         if (to_vmx(vcpu)->nested.nested_run_pending)
4611                 return -EBUSY;
4612
4613         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
4614         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4615                 return -EBUSY;
4616
4617         return !vmx_nmi_blocked(vcpu);
4618 }
4619
4620 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4621 {
4622         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4623                 return false;
4624
4625         return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4626                (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4627                 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4628 }
4629
4630 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4631 {
4632         if (to_vmx(vcpu)->nested.nested_run_pending)
4633                 return -EBUSY;
4634
4635        /*
4636         * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4637         * e.g. if the IRQ arrived asynchronously after checking nested events.
4638         */
4639         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4640                 return -EBUSY;
4641
4642         return !vmx_interrupt_blocked(vcpu);
4643 }
4644
4645 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4646 {
4647         void __user *ret;
4648
4649         if (enable_unrestricted_guest)
4650                 return 0;
4651
4652         mutex_lock(&kvm->slots_lock);
4653         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4654                                       PAGE_SIZE * 3);
4655         mutex_unlock(&kvm->slots_lock);
4656
4657         if (IS_ERR(ret))
4658                 return PTR_ERR(ret);
4659
4660         to_kvm_vmx(kvm)->tss_addr = addr;
4661
4662         return init_rmode_tss(kvm, ret);
4663 }
4664
4665 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4666 {
4667         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4668         return 0;
4669 }
4670
4671 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4672 {
4673         switch (vec) {
4674         case BP_VECTOR:
4675                 /*
4676                  * Update instruction length as we may reinject the exception
4677                  * from user space while in guest debugging mode.
4678                  */
4679                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4680                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4681                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4682                         return false;
4683                 fallthrough;
4684         case DB_VECTOR:
4685                 return !(vcpu->guest_debug &
4686                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4687         case DE_VECTOR:
4688         case OF_VECTOR:
4689         case BR_VECTOR:
4690         case UD_VECTOR:
4691         case DF_VECTOR:
4692         case SS_VECTOR:
4693         case GP_VECTOR:
4694         case MF_VECTOR:
4695                 return true;
4696         }
4697         return false;
4698 }
4699
4700 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4701                                   int vec, u32 err_code)
4702 {
4703         /*
4704          * Instruction with address size override prefix opcode 0x67
4705          * Cause the #SS fault with 0 error code in VM86 mode.
4706          */
4707         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4708                 if (kvm_emulate_instruction(vcpu, 0)) {
4709                         if (vcpu->arch.halt_request) {
4710                                 vcpu->arch.halt_request = 0;
4711                                 return kvm_vcpu_halt(vcpu);
4712                         }
4713                         return 1;
4714                 }
4715                 return 0;
4716         }
4717
4718         /*
4719          * Forward all other exceptions that are valid in real mode.
4720          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4721          *        the required debugging infrastructure rework.
4722          */
4723         kvm_queue_exception(vcpu, vec);
4724         return 1;
4725 }
4726
4727 static int handle_machine_check(struct kvm_vcpu *vcpu)
4728 {
4729         /* handled by vmx_vcpu_run() */
4730         return 1;
4731 }
4732
4733 /*
4734  * If the host has split lock detection disabled, then #AC is
4735  * unconditionally injected into the guest, which is the pre split lock
4736  * detection behaviour.
4737  *
4738  * If the host has split lock detection enabled then #AC is
4739  * only injected into the guest when:
4740  *  - Guest CPL == 3 (user mode)
4741  *  - Guest has #AC detection enabled in CR0
4742  *  - Guest EFLAGS has AC bit set
4743  */
4744 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu)
4745 {
4746         if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4747                 return true;
4748
4749         return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4750                (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4751 }
4752
4753 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4754 {
4755         struct vcpu_vmx *vmx = to_vmx(vcpu);
4756         struct kvm_run *kvm_run = vcpu->run;
4757         u32 intr_info, ex_no, error_code;
4758         unsigned long cr2, dr6;
4759         u32 vect_info;
4760
4761         vect_info = vmx->idt_vectoring_info;
4762         intr_info = vmx_get_intr_info(vcpu);
4763
4764         if (is_machine_check(intr_info) || is_nmi(intr_info))
4765                 return 1; /* handled by handle_exception_nmi_irqoff() */
4766
4767         if (is_invalid_opcode(intr_info))
4768                 return handle_ud(vcpu);
4769
4770         error_code = 0;
4771         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4772                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4773
4774         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4775                 WARN_ON_ONCE(!enable_vmware_backdoor);
4776
4777                 /*
4778                  * VMware backdoor emulation on #GP interception only handles
4779                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4780                  * error code on #GP.
4781                  */
4782                 if (error_code) {
4783                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4784                         return 1;
4785                 }
4786                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4787         }
4788
4789         /*
4790          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4791          * MMIO, it is better to report an internal error.
4792          * See the comments in vmx_handle_exit.
4793          */
4794         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4795             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4796                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4797                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4798                 vcpu->run->internal.ndata = 4;
4799                 vcpu->run->internal.data[0] = vect_info;
4800                 vcpu->run->internal.data[1] = intr_info;
4801                 vcpu->run->internal.data[2] = error_code;
4802                 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4803                 return 0;
4804         }
4805
4806         if (is_page_fault(intr_info)) {
4807                 cr2 = vmx_get_exit_qual(vcpu);
4808                 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4809                         /*
4810                          * EPT will cause page fault only if we need to
4811                          * detect illegal GPAs.
4812                          */
4813                         WARN_ON_ONCE(!allow_smaller_maxphyaddr);
4814                         kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4815                         return 1;
4816                 } else
4817                         return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4818         }
4819
4820         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4821
4822         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4823                 return handle_rmode_exception(vcpu, ex_no, error_code);
4824
4825         switch (ex_no) {
4826         case DB_VECTOR:
4827                 dr6 = vmx_get_exit_qual(vcpu);
4828                 if (!(vcpu->guest_debug &
4829                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4830                         if (is_icebp(intr_info))
4831                                 WARN_ON(!skip_emulated_instruction(vcpu));
4832
4833                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4834                         return 1;
4835                 }
4836                 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
4837                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4838                 fallthrough;
4839         case BP_VECTOR:
4840                 /*
4841                  * Update instruction length as we may reinject #BP from
4842                  * user space while in guest debugging mode. Reading it for
4843                  * #DB as well causes no harm, it is not used in that case.
4844                  */
4845                 vmx->vcpu.arch.event_exit_inst_len =
4846                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4847                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4848                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4849                 kvm_run->debug.arch.exception = ex_no;
4850                 break;
4851         case AC_VECTOR:
4852                 if (vmx_guest_inject_ac(vcpu)) {
4853                         kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4854                         return 1;
4855                 }
4856
4857                 /*
4858                  * Handle split lock. Depending on detection mode this will
4859                  * either warn and disable split lock detection for this
4860                  * task or force SIGBUS on it.
4861                  */
4862                 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4863                         return 1;
4864                 fallthrough;
4865         default:
4866                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4867                 kvm_run->ex.exception = ex_no;
4868                 kvm_run->ex.error_code = error_code;
4869                 break;
4870         }
4871         return 0;
4872 }
4873
4874 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4875 {
4876         ++vcpu->stat.irq_exits;
4877         return 1;
4878 }
4879
4880 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4881 {
4882         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4883         vcpu->mmio_needed = 0;
4884         return 0;
4885 }
4886
4887 static int handle_io(struct kvm_vcpu *vcpu)
4888 {
4889         unsigned long exit_qualification;
4890         int size, in, string;
4891         unsigned port;
4892
4893         exit_qualification = vmx_get_exit_qual(vcpu);
4894         string = (exit_qualification & 16) != 0;
4895
4896         ++vcpu->stat.io_exits;
4897
4898         if (string)
4899                 return kvm_emulate_instruction(vcpu, 0);
4900
4901         port = exit_qualification >> 16;
4902         size = (exit_qualification & 7) + 1;
4903         in = (exit_qualification & 8) != 0;
4904
4905         return kvm_fast_pio(vcpu, size, port, in);
4906 }
4907
4908 static void
4909 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4910 {
4911         /*
4912          * Patch in the VMCALL instruction:
4913          */
4914         hypercall[0] = 0x0f;
4915         hypercall[1] = 0x01;
4916         hypercall[2] = 0xc1;
4917 }
4918
4919 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4920 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4921 {
4922         if (is_guest_mode(vcpu)) {
4923                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4924                 unsigned long orig_val = val;
4925
4926                 /*
4927                  * We get here when L2 changed cr0 in a way that did not change
4928                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4929                  * but did change L0 shadowed bits. So we first calculate the
4930                  * effective cr0 value that L1 would like to write into the
4931                  * hardware. It consists of the L2-owned bits from the new
4932                  * value combined with the L1-owned bits from L1's guest_cr0.
4933                  */
4934                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4935                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4936
4937                 if (!nested_guest_cr0_valid(vcpu, val))
4938                         return 1;
4939
4940                 if (kvm_set_cr0(vcpu, val))
4941                         return 1;
4942                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4943                 return 0;
4944         } else {
4945                 if (to_vmx(vcpu)->nested.vmxon &&
4946                     !nested_host_cr0_valid(vcpu, val))
4947                         return 1;
4948
4949                 return kvm_set_cr0(vcpu, val);
4950         }
4951 }
4952
4953 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4954 {
4955         if (is_guest_mode(vcpu)) {
4956                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4957                 unsigned long orig_val = val;
4958
4959                 /* analogously to handle_set_cr0 */
4960                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4961                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4962                 if (kvm_set_cr4(vcpu, val))
4963                         return 1;
4964                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4965                 return 0;
4966         } else
4967                 return kvm_set_cr4(vcpu, val);
4968 }
4969
4970 static int handle_desc(struct kvm_vcpu *vcpu)
4971 {
4972         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4973         return kvm_emulate_instruction(vcpu, 0);
4974 }
4975
4976 static int handle_cr(struct kvm_vcpu *vcpu)
4977 {
4978         unsigned long exit_qualification, val;
4979         int cr;
4980         int reg;
4981         int err;
4982         int ret;
4983
4984         exit_qualification = vmx_get_exit_qual(vcpu);
4985         cr = exit_qualification & 15;
4986         reg = (exit_qualification >> 8) & 15;
4987         switch ((exit_qualification >> 4) & 3) {
4988         case 0: /* mov to cr */
4989                 val = kvm_register_read(vcpu, reg);
4990                 trace_kvm_cr_write(cr, val);
4991                 switch (cr) {
4992                 case 0:
4993                         err = handle_set_cr0(vcpu, val);
4994                         return kvm_complete_insn_gp(vcpu, err);
4995                 case 3:
4996                         WARN_ON_ONCE(enable_unrestricted_guest);
4997
4998                         err = kvm_set_cr3(vcpu, val);
4999                         return kvm_complete_insn_gp(vcpu, err);
5000                 case 4:
5001                         err = handle_set_cr4(vcpu, val);
5002                         return kvm_complete_insn_gp(vcpu, err);
5003                 case 8: {
5004                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5005                                 u8 cr8 = (u8)val;
5006                                 err = kvm_set_cr8(vcpu, cr8);
5007                                 ret = kvm_complete_insn_gp(vcpu, err);
5008                                 if (lapic_in_kernel(vcpu))
5009                                         return ret;
5010                                 if (cr8_prev <= cr8)
5011                                         return ret;
5012                                 /*
5013                                  * TODO: we might be squashing a
5014                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5015                                  * KVM_EXIT_DEBUG here.
5016                                  */
5017                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5018                                 return 0;
5019                         }
5020                 }
5021                 break;
5022         case 2: /* clts */
5023                 KVM_BUG(1, vcpu->kvm, "Guest always owns CR0.TS");
5024                 return -EIO;
5025         case 1: /*mov from cr*/
5026                 switch (cr) {
5027                 case 3:
5028                         WARN_ON_ONCE(enable_unrestricted_guest);
5029
5030                         val = kvm_read_cr3(vcpu);
5031                         kvm_register_write(vcpu, reg, val);
5032                         trace_kvm_cr_read(cr, val);
5033                         return kvm_skip_emulated_instruction(vcpu);
5034                 case 8:
5035                         val = kvm_get_cr8(vcpu);
5036                         kvm_register_write(vcpu, reg, val);
5037                         trace_kvm_cr_read(cr, val);
5038                         return kvm_skip_emulated_instruction(vcpu);
5039                 }
5040                 break;
5041         case 3: /* lmsw */
5042                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5043                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5044                 kvm_lmsw(vcpu, val);
5045
5046                 return kvm_skip_emulated_instruction(vcpu);
5047         default:
5048                 break;
5049         }
5050         vcpu->run->exit_reason = 0;
5051         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5052                (int)(exit_qualification >> 4) & 3, cr);
5053         return 0;
5054 }
5055
5056 static int handle_dr(struct kvm_vcpu *vcpu)
5057 {
5058         unsigned long exit_qualification;
5059         int dr, dr7, reg;
5060         int err = 1;
5061
5062         exit_qualification = vmx_get_exit_qual(vcpu);
5063         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5064
5065         /* First, if DR does not exist, trigger UD */
5066         if (!kvm_require_dr(vcpu, dr))
5067                 return 1;
5068
5069         if (kvm_x86_ops.get_cpl(vcpu) > 0)
5070                 goto out;
5071
5072         dr7 = vmcs_readl(GUEST_DR7);
5073         if (dr7 & DR7_GD) {
5074                 /*
5075                  * As the vm-exit takes precedence over the debug trap, we
5076                  * need to emulate the latter, either for the host or the
5077                  * guest debugging itself.
5078                  */
5079                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5080                         vcpu->run->debug.arch.dr6 = DR6_BD | DR6_ACTIVE_LOW;
5081                         vcpu->run->debug.arch.dr7 = dr7;
5082                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5083                         vcpu->run->debug.arch.exception = DB_VECTOR;
5084                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5085                         return 0;
5086                 } else {
5087                         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5088                         return 1;
5089                 }
5090         }
5091
5092         if (vcpu->guest_debug == 0) {
5093                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5094
5095                 /*
5096                  * No more DR vmexits; force a reload of the debug registers
5097                  * and reenter on this instruction.  The next vmexit will
5098                  * retrieve the full state of the debug registers.
5099                  */
5100                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5101                 return 1;
5102         }
5103
5104         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5105         if (exit_qualification & TYPE_MOV_FROM_DR) {
5106                 unsigned long val;
5107
5108                 kvm_get_dr(vcpu, dr, &val);
5109                 kvm_register_write(vcpu, reg, val);
5110                 err = 0;
5111         } else {
5112                 err = kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg));
5113         }
5114
5115 out:
5116         return kvm_complete_insn_gp(vcpu, err);
5117 }
5118
5119 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5120 {
5121         get_debugreg(vcpu->arch.db[0], 0);
5122         get_debugreg(vcpu->arch.db[1], 1);
5123         get_debugreg(vcpu->arch.db[2], 2);
5124         get_debugreg(vcpu->arch.db[3], 3);
5125         get_debugreg(vcpu->arch.dr6, 6);
5126         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5127
5128         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5129         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5130 }
5131
5132 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5133 {
5134         vmcs_writel(GUEST_DR7, val);
5135 }
5136
5137 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5138 {
5139         kvm_apic_update_ppr(vcpu);
5140         return 1;
5141 }
5142
5143 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5144 {
5145         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5146
5147         kvm_make_request(KVM_REQ_EVENT, vcpu);
5148
5149         ++vcpu->stat.irq_window_exits;
5150         return 1;
5151 }
5152
5153 static int handle_invlpg(struct kvm_vcpu *vcpu)
5154 {
5155         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5156
5157         kvm_mmu_invlpg(vcpu, exit_qualification);
5158         return kvm_skip_emulated_instruction(vcpu);
5159 }
5160
5161 static int handle_apic_access(struct kvm_vcpu *vcpu)
5162 {
5163         if (likely(fasteoi)) {
5164                 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5165                 int access_type, offset;
5166
5167                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5168                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5169                 /*
5170                  * Sane guest uses MOV to write EOI, with written value
5171                  * not cared. So make a short-circuit here by avoiding
5172                  * heavy instruction emulation.
5173                  */
5174                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5175                     (offset == APIC_EOI)) {
5176                         kvm_lapic_set_eoi(vcpu);
5177                         return kvm_skip_emulated_instruction(vcpu);
5178                 }
5179         }
5180         return kvm_emulate_instruction(vcpu, 0);
5181 }
5182
5183 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5184 {
5185         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5186         int vector = exit_qualification & 0xff;
5187
5188         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5189         kvm_apic_set_eoi_accelerated(vcpu, vector);
5190         return 1;
5191 }
5192
5193 static int handle_apic_write(struct kvm_vcpu *vcpu)
5194 {
5195         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5196         u32 offset = exit_qualification & 0xfff;
5197
5198         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5199         kvm_apic_write_nodecode(vcpu, offset);
5200         return 1;
5201 }
5202
5203 static int handle_task_switch(struct kvm_vcpu *vcpu)
5204 {
5205         struct vcpu_vmx *vmx = to_vmx(vcpu);
5206         unsigned long exit_qualification;
5207         bool has_error_code = false;
5208         u32 error_code = 0;
5209         u16 tss_selector;
5210         int reason, type, idt_v, idt_index;
5211
5212         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5213         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5214         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5215
5216         exit_qualification = vmx_get_exit_qual(vcpu);
5217
5218         reason = (u32)exit_qualification >> 30;
5219         if (reason == TASK_SWITCH_GATE && idt_v) {
5220                 switch (type) {
5221                 case INTR_TYPE_NMI_INTR:
5222                         vcpu->arch.nmi_injected = false;
5223                         vmx_set_nmi_mask(vcpu, true);
5224                         break;
5225                 case INTR_TYPE_EXT_INTR:
5226                 case INTR_TYPE_SOFT_INTR:
5227                         kvm_clear_interrupt_queue(vcpu);
5228                         break;
5229                 case INTR_TYPE_HARD_EXCEPTION:
5230                         if (vmx->idt_vectoring_info &
5231                             VECTORING_INFO_DELIVER_CODE_MASK) {
5232                                 has_error_code = true;
5233                                 error_code =
5234                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5235                         }
5236                         fallthrough;
5237                 case INTR_TYPE_SOFT_EXCEPTION:
5238                         kvm_clear_exception_queue(vcpu);
5239                         break;
5240                 default:
5241                         break;
5242                 }
5243         }
5244         tss_selector = exit_qualification;
5245
5246         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5247                        type != INTR_TYPE_EXT_INTR &&
5248                        type != INTR_TYPE_NMI_INTR))
5249                 WARN_ON(!skip_emulated_instruction(vcpu));
5250
5251         /*
5252          * TODO: What about debug traps on tss switch?
5253          *       Are we supposed to inject them and update dr6?
5254          */
5255         return kvm_task_switch(vcpu, tss_selector,
5256                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5257                                reason, has_error_code, error_code);
5258 }
5259
5260 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5261 {
5262         unsigned long exit_qualification;
5263         gpa_t gpa;
5264         u64 error_code;
5265
5266         exit_qualification = vmx_get_exit_qual(vcpu);
5267
5268         /*
5269          * EPT violation happened while executing iret from NMI,
5270          * "blocked by NMI" bit has to be set before next VM entry.
5271          * There are errata that may cause this bit to not be set:
5272          * AAK134, BY25.
5273          */
5274         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5275                         enable_vnmi &&
5276                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5277                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5278
5279         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5280         trace_kvm_page_fault(gpa, exit_qualification);
5281
5282         /* Is it a read fault? */
5283         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5284                      ? PFERR_USER_MASK : 0;
5285         /* Is it a write fault? */
5286         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5287                       ? PFERR_WRITE_MASK : 0;
5288         /* Is it a fetch fault? */
5289         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5290                       ? PFERR_FETCH_MASK : 0;
5291         /* ept page table entry is present? */
5292         error_code |= (exit_qualification &
5293                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5294                         EPT_VIOLATION_EXECUTABLE))
5295                       ? PFERR_PRESENT_MASK : 0;
5296
5297         error_code |= (exit_qualification & EPT_VIOLATION_GVA_TRANSLATED) != 0 ?
5298                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5299
5300         vcpu->arch.exit_qualification = exit_qualification;
5301
5302         /*
5303          * Check that the GPA doesn't exceed physical memory limits, as that is
5304          * a guest page fault.  We have to emulate the instruction here, because
5305          * if the illegal address is that of a paging structure, then
5306          * EPT_VIOLATION_ACC_WRITE bit is set.  Alternatively, if supported we
5307          * would also use advanced VM-exit information for EPT violations to
5308          * reconstruct the page fault error code.
5309          */
5310         if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa)))
5311                 return kvm_emulate_instruction(vcpu, 0);
5312
5313         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5314 }
5315
5316 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5317 {
5318         gpa_t gpa;
5319
5320         if (!vmx_can_emulate_instruction(vcpu, NULL, 0))
5321                 return 1;
5322
5323         /*
5324          * A nested guest cannot optimize MMIO vmexits, because we have an
5325          * nGPA here instead of the required GPA.
5326          */
5327         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5328         if (!is_guest_mode(vcpu) &&
5329             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5330                 trace_kvm_fast_mmio(gpa);
5331                 return kvm_skip_emulated_instruction(vcpu);
5332         }
5333
5334         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5335 }
5336
5337 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5338 {
5339         if (KVM_BUG_ON(!enable_vnmi, vcpu->kvm))
5340                 return -EIO;
5341
5342         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5343         ++vcpu->stat.nmi_window_exits;
5344         kvm_make_request(KVM_REQ_EVENT, vcpu);
5345
5346         return 1;
5347 }
5348
5349 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5350 {
5351         struct vcpu_vmx *vmx = to_vmx(vcpu);
5352         bool intr_window_requested;
5353         unsigned count = 130;
5354
5355         intr_window_requested = exec_controls_get(vmx) &
5356                                 CPU_BASED_INTR_WINDOW_EXITING;
5357
5358         while (vmx->emulation_required && count-- != 0) {
5359                 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5360                         return handle_interrupt_window(&vmx->vcpu);
5361
5362                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5363                         return 1;
5364
5365                 if (!kvm_emulate_instruction(vcpu, 0))
5366                         return 0;
5367
5368                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5369                     vcpu->arch.exception.pending) {
5370                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5371                         vcpu->run->internal.suberror =
5372                                                 KVM_INTERNAL_ERROR_EMULATION;
5373                         vcpu->run->internal.ndata = 0;
5374                         return 0;
5375                 }
5376
5377                 if (vcpu->arch.halt_request) {
5378                         vcpu->arch.halt_request = 0;
5379                         return kvm_vcpu_halt(vcpu);
5380                 }
5381
5382                 /*
5383                  * Note, return 1 and not 0, vcpu_run() will invoke
5384                  * xfer_to_guest_mode() which will create a proper return
5385                  * code.
5386                  */
5387                 if (__xfer_to_guest_mode_work_pending())
5388                         return 1;
5389         }
5390
5391         return 1;
5392 }
5393
5394 static void grow_ple_window(struct kvm_vcpu *vcpu)
5395 {
5396         struct vcpu_vmx *vmx = to_vmx(vcpu);
5397         unsigned int old = vmx->ple_window;
5398
5399         vmx->ple_window = __grow_ple_window(old, ple_window,
5400                                             ple_window_grow,
5401                                             ple_window_max);
5402
5403         if (vmx->ple_window != old) {
5404                 vmx->ple_window_dirty = true;
5405                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5406                                             vmx->ple_window, old);
5407         }
5408 }
5409
5410 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5411 {
5412         struct vcpu_vmx *vmx = to_vmx(vcpu);
5413         unsigned int old = vmx->ple_window;
5414
5415         vmx->ple_window = __shrink_ple_window(old, ple_window,
5416                                               ple_window_shrink,
5417                                               ple_window);
5418
5419         if (vmx->ple_window != old) {
5420                 vmx->ple_window_dirty = true;
5421                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5422                                             vmx->ple_window, old);
5423         }
5424 }
5425
5426 /*
5427  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5428  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5429  */
5430 static int handle_pause(struct kvm_vcpu *vcpu)
5431 {
5432         if (!kvm_pause_in_guest(vcpu->kvm))
5433                 grow_ple_window(vcpu);
5434
5435         /*
5436          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5437          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5438          * never set PAUSE_EXITING and just set PLE if supported,
5439          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5440          */
5441         kvm_vcpu_on_spin(vcpu, true);
5442         return kvm_skip_emulated_instruction(vcpu);
5443 }
5444
5445 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5446 {
5447         return 1;
5448 }
5449
5450 static int handle_invpcid(struct kvm_vcpu *vcpu)
5451 {
5452         u32 vmx_instruction_info;
5453         unsigned long type;
5454         gva_t gva;
5455         struct {
5456                 u64 pcid;
5457                 u64 gla;
5458         } operand;
5459
5460         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5461                 kvm_queue_exception(vcpu, UD_VECTOR);
5462                 return 1;
5463         }
5464
5465         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5466         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
5467
5468         if (type > 3) {
5469                 kvm_inject_gp(vcpu, 0);
5470                 return 1;
5471         }
5472
5473         /* According to the Intel instruction reference, the memory operand
5474          * is read even if it isn't needed (e.g., for type==all)
5475          */
5476         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5477                                 vmx_instruction_info, false,
5478                                 sizeof(operand), &gva))
5479                 return 1;
5480
5481         return kvm_handle_invpcid(vcpu, type, gva);
5482 }
5483
5484 static int handle_pml_full(struct kvm_vcpu *vcpu)
5485 {
5486         unsigned long exit_qualification;
5487
5488         trace_kvm_pml_full(vcpu->vcpu_id);
5489
5490         exit_qualification = vmx_get_exit_qual(vcpu);
5491
5492         /*
5493          * PML buffer FULL happened while executing iret from NMI,
5494          * "blocked by NMI" bit has to be set before next VM entry.
5495          */
5496         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5497                         enable_vnmi &&
5498                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5499                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5500                                 GUEST_INTR_STATE_NMI);
5501
5502         /*
5503          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5504          * here.., and there's no userspace involvement needed for PML.
5505          */
5506         return 1;
5507 }
5508
5509 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5510 {
5511         struct vcpu_vmx *vmx = to_vmx(vcpu);
5512
5513         if (!vmx->req_immediate_exit &&
5514             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5515                 kvm_lapic_expired_hv_timer(vcpu);
5516                 return EXIT_FASTPATH_REENTER_GUEST;
5517         }
5518
5519         return EXIT_FASTPATH_NONE;
5520 }
5521
5522 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5523 {
5524         handle_fastpath_preemption_timer(vcpu);
5525         return 1;
5526 }
5527
5528 /*
5529  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5530  * are overwritten by nested_vmx_setup() when nested=1.
5531  */
5532 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5533 {
5534         kvm_queue_exception(vcpu, UD_VECTOR);
5535         return 1;
5536 }
5537
5538 #ifndef CONFIG_X86_SGX_KVM
5539 static int handle_encls(struct kvm_vcpu *vcpu)
5540 {
5541         /*
5542          * SGX virtualization is disabled.  There is no software enable bit for
5543          * SGX, so KVM intercepts all ENCLS leafs and injects a #UD to prevent
5544          * the guest from executing ENCLS (when SGX is supported by hardware).
5545          */
5546         kvm_queue_exception(vcpu, UD_VECTOR);
5547         return 1;
5548 }
5549 #endif /* CONFIG_X86_SGX_KVM */
5550
5551 static int handle_bus_lock_vmexit(struct kvm_vcpu *vcpu)
5552 {
5553         vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
5554         vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
5555         return 0;
5556 }
5557
5558 /*
5559  * The exit handlers return 1 if the exit was handled fully and guest execution
5560  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5561  * to be done to userspace and return 0.
5562  */
5563 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5564         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5565         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5566         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5567         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5568         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5569         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5570         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5571         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5572         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5573         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5574         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5575         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5576         [EXIT_REASON_INVD]                    = kvm_emulate_invd,
5577         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5578         [EXIT_REASON_RDPMC]                   = kvm_emulate_rdpmc,
5579         [EXIT_REASON_VMCALL]                  = kvm_emulate_hypercall,
5580         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5581         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5582         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5583         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5584         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5585         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5586         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5587         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5588         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5589         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5590         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5591         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5592         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5593         [EXIT_REASON_WBINVD]                  = kvm_emulate_wbinvd,
5594         [EXIT_REASON_XSETBV]                  = kvm_emulate_xsetbv,
5595         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5596         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5597         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5598         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5599         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5600         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5601         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5602         [EXIT_REASON_MWAIT_INSTRUCTION]       = kvm_emulate_mwait,
5603         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5604         [EXIT_REASON_MONITOR_INSTRUCTION]     = kvm_emulate_monitor,
5605         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5606         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5607         [EXIT_REASON_RDRAND]                  = kvm_handle_invalid_op,
5608         [EXIT_REASON_RDSEED]                  = kvm_handle_invalid_op,
5609         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5610         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5611         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5612         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5613         [EXIT_REASON_ENCLS]                   = handle_encls,
5614         [EXIT_REASON_BUS_LOCK]                = handle_bus_lock_vmexit,
5615 };
5616
5617 static const int kvm_vmx_max_exit_handlers =
5618         ARRAY_SIZE(kvm_vmx_exit_handlers);
5619
5620 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
5621                               u32 *intr_info, u32 *error_code)
5622 {
5623         struct vcpu_vmx *vmx = to_vmx(vcpu);
5624
5625         *info1 = vmx_get_exit_qual(vcpu);
5626         if (!(vmx->exit_reason.failed_vmentry)) {
5627                 *info2 = vmx->idt_vectoring_info;
5628                 *intr_info = vmx_get_intr_info(vcpu);
5629                 if (is_exception_with_error_code(*intr_info))
5630                         *error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5631                 else
5632                         *error_code = 0;
5633         } else {
5634                 *info2 = 0;
5635                 *intr_info = 0;
5636                 *error_code = 0;
5637         }
5638 }
5639
5640 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5641 {
5642         if (vmx->pml_pg) {
5643                 __free_page(vmx->pml_pg);
5644                 vmx->pml_pg = NULL;
5645         }
5646 }
5647
5648 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5649 {
5650         struct vcpu_vmx *vmx = to_vmx(vcpu);
5651         u64 *pml_buf;
5652         u16 pml_idx;
5653
5654         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5655
5656         /* Do nothing if PML buffer is empty */
5657         if (pml_idx == (PML_ENTITY_NUM - 1))
5658                 return;
5659
5660         /* PML index always points to next available PML buffer entity */
5661         if (pml_idx >= PML_ENTITY_NUM)
5662                 pml_idx = 0;
5663         else
5664                 pml_idx++;
5665
5666         pml_buf = page_address(vmx->pml_pg);
5667         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5668                 u64 gpa;
5669
5670                 gpa = pml_buf[pml_idx];
5671                 WARN_ON(gpa & (PAGE_SIZE - 1));
5672                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5673         }
5674
5675         /* reset PML index */
5676         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5677 }
5678
5679 static void vmx_dump_sel(char *name, uint32_t sel)
5680 {
5681         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5682                name, vmcs_read16(sel),
5683                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5684                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5685                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5686 }
5687
5688 static void vmx_dump_dtsel(char *name, uint32_t limit)
5689 {
5690         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5691                name, vmcs_read32(limit),
5692                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5693 }
5694
5695 static void vmx_dump_msrs(char *name, struct vmx_msrs *m)
5696 {
5697         unsigned int i;
5698         struct vmx_msr_entry *e;
5699
5700         pr_err("MSR %s:\n", name);
5701         for (i = 0, e = m->val; i < m->nr; ++i, ++e)
5702                 pr_err("  %2d: msr=0x%08x value=0x%016llx\n", i, e->index, e->value);
5703 }
5704
5705 void dump_vmcs(struct kvm_vcpu *vcpu)
5706 {
5707         struct vcpu_vmx *vmx = to_vmx(vcpu);
5708         u32 vmentry_ctl, vmexit_ctl;
5709         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5710         unsigned long cr4;
5711         int efer_slot;
5712
5713         if (!dump_invalid_vmcs) {
5714                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5715                 return;
5716         }
5717
5718         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5719         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5720         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5721         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5722         cr4 = vmcs_readl(GUEST_CR4);
5723         secondary_exec_control = 0;
5724         if (cpu_has_secondary_exec_ctrls())
5725                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5726
5727         pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
5728                vmx->loaded_vmcs->vmcs, vcpu->arch.last_vmentry_cpu);
5729         pr_err("*** Guest State ***\n");
5730         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5731                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5732                vmcs_readl(CR0_GUEST_HOST_MASK));
5733         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5734                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5735         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5736         if (cpu_has_vmx_ept()) {
5737                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5738                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5739                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5740                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5741         }
5742         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5743                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5744         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5745                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5746         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5747                vmcs_readl(GUEST_SYSENTER_ESP),
5748                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5749         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5750         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5751         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5752         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5753         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5754         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5755         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5756         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5757         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5758         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5759         efer_slot = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, MSR_EFER);
5760         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_EFER)
5761                 pr_err("EFER= 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER));
5762         else if (efer_slot >= 0)
5763                 pr_err("EFER= 0x%016llx (autoload)\n",
5764                        vmx->msr_autoload.guest.val[efer_slot].value);
5765         else if (vmentry_ctl & VM_ENTRY_IA32E_MODE)
5766                 pr_err("EFER= 0x%016llx (effective)\n",
5767                        vcpu->arch.efer | (EFER_LMA | EFER_LME));
5768         else
5769                 pr_err("EFER= 0x%016llx (effective)\n",
5770                        vcpu->arch.efer & ~(EFER_LMA | EFER_LME));
5771         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PAT)
5772                 pr_err("PAT = 0x%016llx\n", vmcs_read64(GUEST_IA32_PAT));
5773         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5774                vmcs_read64(GUEST_IA32_DEBUGCTL),
5775                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5776         if (cpu_has_load_perf_global_ctrl() &&
5777             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5778                 pr_err("PerfGlobCtl = 0x%016llx\n",
5779                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5780         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5781                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5782         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5783                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5784                vmcs_read32(GUEST_ACTIVITY_STATE));
5785         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5786                 pr_err("InterruptStatus = %04x\n",
5787                        vmcs_read16(GUEST_INTR_STATUS));
5788         if (vmcs_read32(VM_ENTRY_MSR_LOAD_COUNT) > 0)
5789                 vmx_dump_msrs("guest autoload", &vmx->msr_autoload.guest);
5790         if (vmcs_read32(VM_EXIT_MSR_STORE_COUNT) > 0)
5791                 vmx_dump_msrs("guest autostore", &vmx->msr_autostore.guest);
5792
5793         pr_err("*** Host State ***\n");
5794         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5795                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5796         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5797                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5798                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5799                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5800                vmcs_read16(HOST_TR_SELECTOR));
5801         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5802                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5803                vmcs_readl(HOST_TR_BASE));
5804         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5805                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5806         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5807                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5808                vmcs_readl(HOST_CR4));
5809         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5810                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5811                vmcs_read32(HOST_IA32_SYSENTER_CS),
5812                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5813         if (vmexit_ctl & VM_EXIT_LOAD_IA32_EFER)
5814                 pr_err("EFER= 0x%016llx\n", vmcs_read64(HOST_IA32_EFER));
5815         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PAT)
5816                 pr_err("PAT = 0x%016llx\n", vmcs_read64(HOST_IA32_PAT));
5817         if (cpu_has_load_perf_global_ctrl() &&
5818             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5819                 pr_err("PerfGlobCtl = 0x%016llx\n",
5820                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5821         if (vmcs_read32(VM_EXIT_MSR_LOAD_COUNT) > 0)
5822                 vmx_dump_msrs("host autoload", &vmx->msr_autoload.host);
5823
5824         pr_err("*** Control State ***\n");
5825         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5826                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5827         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5828         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5829                vmcs_read32(EXCEPTION_BITMAP),
5830                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5831                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5832         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5833                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5834                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5835                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5836         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5837                vmcs_read32(VM_EXIT_INTR_INFO),
5838                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5839                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5840         pr_err("        reason=%08x qualification=%016lx\n",
5841                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5842         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5843                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5844                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5845         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5846         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5847                 pr_err("TSC Multiplier = 0x%016llx\n",
5848                        vmcs_read64(TSC_MULTIPLIER));
5849         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5850                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5851                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5852                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5853                 }
5854                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5855                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5856                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5857                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5858         }
5859         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5860                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5861         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5862                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5863         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5864                 pr_err("PLE Gap=%08x Window=%08x\n",
5865                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5866         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5867                 pr_err("Virtual processor ID = 0x%04x\n",
5868                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5869 }
5870
5871 /*
5872  * The guest has exited.  See if we can fix it or if we need userspace
5873  * assistance.
5874  */
5875 static int __vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5876 {
5877         struct vcpu_vmx *vmx = to_vmx(vcpu);
5878         union vmx_exit_reason exit_reason = vmx->exit_reason;
5879         u32 vectoring_info = vmx->idt_vectoring_info;
5880         u16 exit_handler_index;
5881
5882         /*
5883          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5884          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5885          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5886          * mode as if vcpus is in root mode, the PML buffer must has been
5887          * flushed already.  Note, PML is never enabled in hardware while
5888          * running L2.
5889          */
5890         if (enable_pml && !is_guest_mode(vcpu))
5891                 vmx_flush_pml_buffer(vcpu);
5892
5893         /*
5894          * We should never reach this point with a pending nested VM-Enter, and
5895          * more specifically emulation of L2 due to invalid guest state (see
5896          * below) should never happen as that means we incorrectly allowed a
5897          * nested VM-Enter with an invalid vmcs12.
5898          */
5899         if (KVM_BUG_ON(vmx->nested.nested_run_pending, vcpu->kvm))
5900                 return -EIO;
5901
5902         /* If guest state is invalid, start emulating */
5903         if (vmx->emulation_required)
5904                 return handle_invalid_guest_state(vcpu);
5905
5906         if (is_guest_mode(vcpu)) {
5907                 /*
5908                  * PML is never enabled when running L2, bail immediately if a
5909                  * PML full exit occurs as something is horribly wrong.
5910                  */
5911                 if (exit_reason.basic == EXIT_REASON_PML_FULL)
5912                         goto unexpected_vmexit;
5913
5914                 /*
5915                  * The host physical addresses of some pages of guest memory
5916                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5917                  * Page). The CPU may write to these pages via their host
5918                  * physical address while L2 is running, bypassing any
5919                  * address-translation-based dirty tracking (e.g. EPT write
5920                  * protection).
5921                  *
5922                  * Mark them dirty on every exit from L2 to prevent them from
5923                  * getting out of sync with dirty tracking.
5924                  */
5925                 nested_mark_vmcs12_pages_dirty(vcpu);
5926
5927                 if (nested_vmx_reflect_vmexit(vcpu))
5928                         return 1;
5929         }
5930
5931         if (exit_reason.failed_vmentry) {
5932                 dump_vmcs(vcpu);
5933                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5934                 vcpu->run->fail_entry.hardware_entry_failure_reason
5935                         = exit_reason.full;
5936                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5937                 return 0;
5938         }
5939
5940         if (unlikely(vmx->fail)) {
5941                 dump_vmcs(vcpu);
5942                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5943                 vcpu->run->fail_entry.hardware_entry_failure_reason
5944                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5945                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5946                 return 0;
5947         }
5948
5949         /*
5950          * Note:
5951          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5952          * delivery event since it indicates guest is accessing MMIO.
5953          * The vm-exit can be triggered again after return to guest that
5954          * will cause infinite loop.
5955          */
5956         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5957             (exit_reason.basic != EXIT_REASON_EXCEPTION_NMI &&
5958              exit_reason.basic != EXIT_REASON_EPT_VIOLATION &&
5959              exit_reason.basic != EXIT_REASON_PML_FULL &&
5960              exit_reason.basic != EXIT_REASON_APIC_ACCESS &&
5961              exit_reason.basic != EXIT_REASON_TASK_SWITCH)) {
5962                 int ndata = 3;
5963
5964                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5965                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5966                 vcpu->run->internal.data[0] = vectoring_info;
5967                 vcpu->run->internal.data[1] = exit_reason.full;
5968                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5969                 if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG) {
5970                         vcpu->run->internal.data[ndata++] =
5971                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5972                 }
5973                 vcpu->run->internal.data[ndata++] = vcpu->arch.last_vmentry_cpu;
5974                 vcpu->run->internal.ndata = ndata;
5975                 return 0;
5976         }
5977
5978         if (unlikely(!enable_vnmi &&
5979                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5980                 if (!vmx_interrupt_blocked(vcpu)) {
5981                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5982                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5983                            vcpu->arch.nmi_pending) {
5984                         /*
5985                          * This CPU don't support us in finding the end of an
5986                          * NMI-blocked window if the guest runs with IRQs
5987                          * disabled. So we pull the trigger after 1 s of
5988                          * futile waiting, but inform the user about this.
5989                          */
5990                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5991                                "state on VCPU %d after 1 s timeout\n",
5992                                __func__, vcpu->vcpu_id);
5993                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5994                 }
5995         }
5996
5997         if (exit_fastpath != EXIT_FASTPATH_NONE)
5998                 return 1;
5999
6000         if (exit_reason.basic >= kvm_vmx_max_exit_handlers)
6001                 goto unexpected_vmexit;
6002 #ifdef CONFIG_RETPOLINE
6003         if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
6004                 return kvm_emulate_wrmsr(vcpu);
6005         else if (exit_reason.basic == EXIT_REASON_PREEMPTION_TIMER)
6006                 return handle_preemption_timer(vcpu);
6007         else if (exit_reason.basic == EXIT_REASON_INTERRUPT_WINDOW)
6008                 return handle_interrupt_window(vcpu);
6009         else if (exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6010                 return handle_external_interrupt(vcpu);
6011         else if (exit_reason.basic == EXIT_REASON_HLT)
6012                 return kvm_emulate_halt(vcpu);
6013         else if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG)
6014                 return handle_ept_misconfig(vcpu);
6015 #endif
6016
6017         exit_handler_index = array_index_nospec((u16)exit_reason.basic,
6018                                                 kvm_vmx_max_exit_handlers);
6019         if (!kvm_vmx_exit_handlers[exit_handler_index])
6020                 goto unexpected_vmexit;
6021
6022         return kvm_vmx_exit_handlers[exit_handler_index](vcpu);
6023
6024 unexpected_vmexit:
6025         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
6026                     exit_reason.full);
6027         dump_vmcs(vcpu);
6028         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6029         vcpu->run->internal.suberror =
6030                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6031         vcpu->run->internal.ndata = 2;
6032         vcpu->run->internal.data[0] = exit_reason.full;
6033         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6034         return 0;
6035 }
6036
6037 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6038 {
6039         int ret = __vmx_handle_exit(vcpu, exit_fastpath);
6040
6041         /*
6042          * Even when current exit reason is handled by KVM internally, we
6043          * still need to exit to user space when bus lock detected to inform
6044          * that there is a bus lock in guest.
6045          */
6046         if (to_vmx(vcpu)->exit_reason.bus_lock_detected) {
6047                 if (ret > 0)
6048                         vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
6049
6050                 vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
6051                 return 0;
6052         }
6053         return ret;
6054 }
6055
6056 /*
6057  * Software based L1D cache flush which is used when microcode providing
6058  * the cache control MSR is not loaded.
6059  *
6060  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6061  * flush it is required to read in 64 KiB because the replacement algorithm
6062  * is not exactly LRU. This could be sized at runtime via topology
6063  * information but as all relevant affected CPUs have 32KiB L1D cache size
6064  * there is no point in doing so.
6065  */
6066 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6067 {
6068         int size = PAGE_SIZE << L1D_CACHE_ORDER;
6069
6070         /*
6071          * This code is only executed when the the flush mode is 'cond' or
6072          * 'always'
6073          */
6074         if (static_branch_likely(&vmx_l1d_flush_cond)) {
6075                 bool flush_l1d;
6076
6077                 /*
6078                  * Clear the per-vcpu flush bit, it gets set again
6079                  * either from vcpu_run() or from one of the unsafe
6080                  * VMEXIT handlers.
6081                  */
6082                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6083                 vcpu->arch.l1tf_flush_l1d = false;
6084
6085                 /*
6086                  * Clear the per-cpu flush bit, it gets set again from
6087                  * the interrupt handlers.
6088                  */
6089                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6090                 kvm_clear_cpu_l1tf_flush_l1d();
6091
6092                 if (!flush_l1d)
6093                         return;
6094         }
6095
6096         vcpu->stat.l1d_flush++;
6097
6098         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6099                 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6100                 return;
6101         }
6102
6103         asm volatile(
6104                 /* First ensure the pages are in the TLB */
6105                 "xorl   %%eax, %%eax\n"
6106                 ".Lpopulate_tlb:\n\t"
6107                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6108                 "addl   $4096, %%eax\n\t"
6109                 "cmpl   %%eax, %[size]\n\t"
6110                 "jne    .Lpopulate_tlb\n\t"
6111                 "xorl   %%eax, %%eax\n\t"
6112                 "cpuid\n\t"
6113                 /* Now fill the cache */
6114                 "xorl   %%eax, %%eax\n"
6115                 ".Lfill_cache:\n"
6116                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6117                 "addl   $64, %%eax\n\t"
6118                 "cmpl   %%eax, %[size]\n\t"
6119                 "jne    .Lfill_cache\n\t"
6120                 "lfence\n"
6121                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6122                     [size] "r" (size)
6123                 : "eax", "ebx", "ecx", "edx");
6124 }
6125
6126 static void vmx_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6127 {
6128         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6129         int tpr_threshold;
6130
6131         if (is_guest_mode(vcpu) &&
6132                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6133                 return;
6134
6135         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6136         if (is_guest_mode(vcpu))
6137                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6138         else
6139                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6140 }
6141
6142 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6143 {
6144         struct vcpu_vmx *vmx = to_vmx(vcpu);
6145         u32 sec_exec_control;
6146
6147         if (!lapic_in_kernel(vcpu))
6148                 return;
6149
6150         if (!flexpriority_enabled &&
6151             !cpu_has_vmx_virtualize_x2apic_mode())
6152                 return;
6153
6154         /* Postpone execution until vmcs01 is the current VMCS. */
6155         if (is_guest_mode(vcpu)) {
6156                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6157                 return;
6158         }
6159
6160         sec_exec_control = secondary_exec_controls_get(vmx);
6161         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6162                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6163
6164         switch (kvm_get_apic_mode(vcpu)) {
6165         case LAPIC_MODE_INVALID:
6166                 WARN_ONCE(true, "Invalid local APIC state");
6167                 break;
6168         case LAPIC_MODE_DISABLED:
6169                 break;
6170         case LAPIC_MODE_XAPIC:
6171                 if (flexpriority_enabled) {
6172                         sec_exec_control |=
6173                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6174                         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6175
6176                         /*
6177                          * Flush the TLB, reloading the APIC access page will
6178                          * only do so if its physical address has changed, but
6179                          * the guest may have inserted a non-APIC mapping into
6180                          * the TLB while the APIC access page was disabled.
6181                          */
6182                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6183                 }
6184                 break;
6185         case LAPIC_MODE_X2APIC:
6186                 if (cpu_has_vmx_virtualize_x2apic_mode())
6187                         sec_exec_control |=
6188                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6189                 break;
6190         }
6191         secondary_exec_controls_set(vmx, sec_exec_control);
6192
6193         vmx_update_msr_bitmap(vcpu);
6194 }
6195
6196 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6197 {
6198         struct page *page;
6199
6200         /* Defer reload until vmcs01 is the current VMCS. */
6201         if (is_guest_mode(vcpu)) {
6202                 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6203                 return;
6204         }
6205
6206         if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6207             SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6208                 return;
6209
6210         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6211         if (is_error_page(page))
6212                 return;
6213
6214         vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6215         vmx_flush_tlb_current(vcpu);
6216
6217         /*
6218          * Do not pin apic access page in memory, the MMU notifier
6219          * will call us again if it is migrated or swapped out.
6220          */
6221         put_page(page);
6222 }
6223
6224 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6225 {
6226         u16 status;
6227         u8 old;
6228
6229         if (max_isr == -1)
6230                 max_isr = 0;
6231
6232         status = vmcs_read16(GUEST_INTR_STATUS);
6233         old = status >> 8;
6234         if (max_isr != old) {
6235                 status &= 0xff;
6236                 status |= max_isr << 8;
6237                 vmcs_write16(GUEST_INTR_STATUS, status);
6238         }
6239 }
6240
6241 static void vmx_set_rvi(int vector)
6242 {
6243         u16 status;
6244         u8 old;
6245
6246         if (vector == -1)
6247                 vector = 0;
6248
6249         status = vmcs_read16(GUEST_INTR_STATUS);
6250         old = (u8)status & 0xff;
6251         if ((u8)vector != old) {
6252                 status &= ~0xff;
6253                 status |= (u8)vector;
6254                 vmcs_write16(GUEST_INTR_STATUS, status);
6255         }
6256 }
6257
6258 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6259 {
6260         /*
6261          * When running L2, updating RVI is only relevant when
6262          * vmcs12 virtual-interrupt-delivery enabled.
6263          * However, it can be enabled only when L1 also
6264          * intercepts external-interrupts and in that case
6265          * we should not update vmcs02 RVI but instead intercept
6266          * interrupt. Therefore, do nothing when running L2.
6267          */
6268         if (!is_guest_mode(vcpu))
6269                 vmx_set_rvi(max_irr);
6270 }
6271
6272 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6273 {
6274         struct vcpu_vmx *vmx = to_vmx(vcpu);
6275         int max_irr;
6276         bool max_irr_updated;
6277
6278         if (KVM_BUG_ON(!vcpu->arch.apicv_active, vcpu->kvm))
6279                 return -EIO;
6280
6281         if (pi_test_on(&vmx->pi_desc)) {
6282                 pi_clear_on(&vmx->pi_desc);
6283                 /*
6284                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6285                  * But on x86 this is just a compiler barrier anyway.
6286                  */
6287                 smp_mb__after_atomic();
6288                 max_irr_updated =
6289                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6290
6291                 /*
6292                  * If we are running L2 and L1 has a new pending interrupt
6293                  * which can be injected, we should re-evaluate
6294                  * what should be done with this new L1 interrupt.
6295                  * If L1 intercepts external-interrupts, we should
6296                  * exit from L2 to L1. Otherwise, interrupt should be
6297                  * delivered directly to L2.
6298                  */
6299                 if (is_guest_mode(vcpu) && max_irr_updated) {
6300                         if (nested_exit_on_intr(vcpu))
6301                                 kvm_vcpu_exiting_guest_mode(vcpu);
6302                         else
6303                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6304                 }
6305         } else {
6306                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6307         }
6308         vmx_hwapic_irr_update(vcpu, max_irr);
6309         return max_irr;
6310 }
6311
6312 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6313 {
6314         if (!kvm_vcpu_apicv_active(vcpu))
6315                 return;
6316
6317         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6318         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6319         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6320         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6321 }
6322
6323 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6324 {
6325         struct vcpu_vmx *vmx = to_vmx(vcpu);
6326
6327         pi_clear_on(&vmx->pi_desc);
6328         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6329 }
6330
6331 void vmx_do_interrupt_nmi_irqoff(unsigned long entry);
6332
6333 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu,
6334                                         unsigned long entry)
6335 {
6336         kvm_before_interrupt(vcpu);
6337         vmx_do_interrupt_nmi_irqoff(entry);
6338         kvm_after_interrupt(vcpu);
6339 }
6340
6341 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6342 {
6343         const unsigned long nmi_entry = (unsigned long)asm_exc_nmi_noist;
6344         u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6345
6346         /* if exit due to PF check for async PF */
6347         if (is_page_fault(intr_info))
6348                 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6349         /* Handle machine checks before interrupts are enabled */
6350         else if (is_machine_check(intr_info))
6351                 kvm_machine_check();
6352         /* We need to handle NMIs before interrupts are enabled */
6353         else if (is_nmi(intr_info))
6354                 handle_interrupt_nmi_irqoff(&vmx->vcpu, nmi_entry);
6355 }
6356
6357 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6358 {
6359         u32 intr_info = vmx_get_intr_info(vcpu);
6360         unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK;
6361         gate_desc *desc = (gate_desc *)host_idt_base + vector;
6362
6363         if (KVM_BUG(!is_external_intr(intr_info), vcpu->kvm,
6364             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6365                 return;
6366
6367         handle_interrupt_nmi_irqoff(vcpu, gate_offset(desc));
6368 }
6369
6370 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6371 {
6372         struct vcpu_vmx *vmx = to_vmx(vcpu);
6373
6374         if (vmx->exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6375                 handle_external_interrupt_irqoff(vcpu);
6376         else if (vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI)
6377                 handle_exception_nmi_irqoff(vmx);
6378 }
6379
6380 /*
6381  * The kvm parameter can be NULL (module initialization, or invocation before
6382  * VM creation). Be sure to check the kvm parameter before using it.
6383  */
6384 static bool vmx_has_emulated_msr(struct kvm *kvm, u32 index)
6385 {
6386         switch (index) {
6387         case MSR_IA32_SMBASE:
6388                 /*
6389                  * We cannot do SMM unless we can run the guest in big
6390                  * real mode.
6391                  */
6392                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6393         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6394                 return nested;
6395         case MSR_AMD64_VIRT_SPEC_CTRL:
6396                 /* This is AMD only.  */
6397                 return false;
6398         default:
6399                 return true;
6400         }
6401 }
6402
6403 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6404 {
6405         u32 exit_intr_info;
6406         bool unblock_nmi;
6407         u8 vector;
6408         bool idtv_info_valid;
6409
6410         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6411
6412         if (enable_vnmi) {
6413                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6414                         return;
6415
6416                 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6417                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6418                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6419                 /*
6420                  * SDM 3: 27.7.1.2 (September 2008)
6421                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6422                  * a guest IRET fault.
6423                  * SDM 3: 23.2.2 (September 2008)
6424                  * Bit 12 is undefined in any of the following cases:
6425                  *  If the VM exit sets the valid bit in the IDT-vectoring
6426                  *   information field.
6427                  *  If the VM exit is due to a double fault.
6428                  */
6429                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6430                     vector != DF_VECTOR && !idtv_info_valid)
6431                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6432                                       GUEST_INTR_STATE_NMI);
6433                 else
6434                         vmx->loaded_vmcs->nmi_known_unmasked =
6435                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6436                                   & GUEST_INTR_STATE_NMI);
6437         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6438                 vmx->loaded_vmcs->vnmi_blocked_time +=
6439                         ktime_to_ns(ktime_sub(ktime_get(),
6440                                               vmx->loaded_vmcs->entry_time));
6441 }
6442
6443 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6444                                       u32 idt_vectoring_info,
6445                                       int instr_len_field,
6446                                       int error_code_field)
6447 {
6448         u8 vector;
6449         int type;
6450         bool idtv_info_valid;
6451
6452         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6453
6454         vcpu->arch.nmi_injected = false;
6455         kvm_clear_exception_queue(vcpu);
6456         kvm_clear_interrupt_queue(vcpu);
6457
6458         if (!idtv_info_valid)
6459                 return;
6460
6461         kvm_make_request(KVM_REQ_EVENT, vcpu);
6462
6463         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6464         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6465
6466         switch (type) {
6467         case INTR_TYPE_NMI_INTR:
6468                 vcpu->arch.nmi_injected = true;
6469                 /*
6470                  * SDM 3: 27.7.1.2 (September 2008)
6471                  * Clear bit "block by NMI" before VM entry if a NMI
6472                  * delivery faulted.
6473                  */
6474                 vmx_set_nmi_mask(vcpu, false);
6475                 break;
6476         case INTR_TYPE_SOFT_EXCEPTION:
6477                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6478                 fallthrough;
6479         case INTR_TYPE_HARD_EXCEPTION:
6480                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6481                         u32 err = vmcs_read32(error_code_field);
6482                         kvm_requeue_exception_e(vcpu, vector, err);
6483                 } else
6484                         kvm_requeue_exception(vcpu, vector);
6485                 break;
6486         case INTR_TYPE_SOFT_INTR:
6487                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6488                 fallthrough;
6489         case INTR_TYPE_EXT_INTR:
6490                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6491                 break;
6492         default:
6493                 break;
6494         }
6495 }
6496
6497 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6498 {
6499         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6500                                   VM_EXIT_INSTRUCTION_LEN,
6501                                   IDT_VECTORING_ERROR_CODE);
6502 }
6503
6504 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6505 {
6506         __vmx_complete_interrupts(vcpu,
6507                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6508                                   VM_ENTRY_INSTRUCTION_LEN,
6509                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6510
6511         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6512 }
6513
6514 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6515 {
6516         int i, nr_msrs;
6517         struct perf_guest_switch_msr *msrs;
6518
6519         /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
6520         msrs = perf_guest_get_msrs(&nr_msrs);
6521         if (!msrs)
6522                 return;
6523
6524         for (i = 0; i < nr_msrs; i++)
6525                 if (msrs[i].host == msrs[i].guest)
6526                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6527                 else
6528                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6529                                         msrs[i].host, false);
6530 }
6531
6532 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6533 {
6534         struct vcpu_vmx *vmx = to_vmx(vcpu);
6535         u64 tscl;
6536         u32 delta_tsc;
6537
6538         if (vmx->req_immediate_exit) {
6539                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6540                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6541         } else if (vmx->hv_deadline_tsc != -1) {
6542                 tscl = rdtsc();
6543                 if (vmx->hv_deadline_tsc > tscl)
6544                         /* set_hv_timer ensures the delta fits in 32-bits */
6545                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6546                                 cpu_preemption_timer_multi);
6547                 else
6548                         delta_tsc = 0;
6549
6550                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6551                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6552         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6553                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6554                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6555         }
6556 }
6557
6558 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6559 {
6560         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6561                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6562                 vmcs_writel(HOST_RSP, host_rsp);
6563         }
6564 }
6565
6566 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6567 {
6568         switch (to_vmx(vcpu)->exit_reason.basic) {
6569         case EXIT_REASON_MSR_WRITE:
6570                 return handle_fastpath_set_msr_irqoff(vcpu);
6571         case EXIT_REASON_PREEMPTION_TIMER:
6572                 return handle_fastpath_preemption_timer(vcpu);
6573         default:
6574                 return EXIT_FASTPATH_NONE;
6575         }
6576 }
6577
6578 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6579                                         struct vcpu_vmx *vmx)
6580 {
6581         kvm_guest_enter_irqoff();
6582
6583         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6584         if (static_branch_unlikely(&vmx_l1d_should_flush))
6585                 vmx_l1d_flush(vcpu);
6586         else if (static_branch_unlikely(&mds_user_clear))
6587                 mds_clear_cpu_buffers();
6588
6589         if (vcpu->arch.cr2 != native_read_cr2())
6590                 native_write_cr2(vcpu->arch.cr2);
6591
6592         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6593                                    vmx->loaded_vmcs->launched);
6594
6595         vcpu->arch.cr2 = native_read_cr2();
6596
6597         kvm_guest_exit_irqoff();
6598 }
6599
6600 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6601 {
6602         struct vcpu_vmx *vmx = to_vmx(vcpu);
6603         unsigned long cr3, cr4;
6604
6605         /* Record the guest's net vcpu time for enforced NMI injections. */
6606         if (unlikely(!enable_vnmi &&
6607                      vmx->loaded_vmcs->soft_vnmi_blocked))
6608                 vmx->loaded_vmcs->entry_time = ktime_get();
6609
6610         /* Don't enter VMX if guest state is invalid, let the exit handler
6611            start emulation until we arrive back to a valid state */
6612         if (vmx->emulation_required)
6613                 return EXIT_FASTPATH_NONE;
6614
6615         trace_kvm_entry(vcpu);
6616
6617         if (vmx->ple_window_dirty) {
6618                 vmx->ple_window_dirty = false;
6619                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6620         }
6621
6622         /*
6623          * We did this in prepare_switch_to_guest, because it needs to
6624          * be within srcu_read_lock.
6625          */
6626         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6627
6628         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6629                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6630         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6631                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6632
6633         cr3 = __get_current_cr3_fast();
6634         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6635                 vmcs_writel(HOST_CR3, cr3);
6636                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6637         }
6638
6639         cr4 = cr4_read_shadow();
6640         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6641                 vmcs_writel(HOST_CR4, cr4);
6642                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6643         }
6644
6645         /* When single-stepping over STI and MOV SS, we must clear the
6646          * corresponding interruptibility bits in the guest state. Otherwise
6647          * vmentry fails as it then expects bit 14 (BS) in pending debug
6648          * exceptions being set, but that's not correct for the guest debugging
6649          * case. */
6650         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6651                 vmx_set_interrupt_shadow(vcpu, 0);
6652
6653         kvm_load_guest_xsave_state(vcpu);
6654
6655         pt_guest_enter(vmx);
6656
6657         atomic_switch_perf_msrs(vmx);
6658         if (intel_pmu_lbr_is_enabled(vcpu))
6659                 vmx_passthrough_lbr_msrs(vcpu);
6660
6661         if (enable_preemption_timer)
6662                 vmx_update_hv_timer(vcpu);
6663
6664         kvm_wait_lapic_expire(vcpu);
6665
6666         /*
6667          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6668          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6669          * is no need to worry about the conditional branch over the wrmsr
6670          * being speculatively taken.
6671          */
6672         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6673
6674         /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6675         vmx_vcpu_enter_exit(vcpu, vmx);
6676
6677         /*
6678          * We do not use IBRS in the kernel. If this vCPU has used the
6679          * SPEC_CTRL MSR it may have left it on; save the value and
6680          * turn it off. This is much more efficient than blindly adding
6681          * it to the atomic save/restore list. Especially as the former
6682          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6683          *
6684          * For non-nested case:
6685          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6686          * save it.
6687          *
6688          * For nested case:
6689          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6690          * save it.
6691          */
6692         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6693                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6694
6695         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6696
6697         /* All fields are clean at this point */
6698         if (static_branch_unlikely(&enable_evmcs)) {
6699                 current_evmcs->hv_clean_fields |=
6700                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6701
6702                 current_evmcs->hv_vp_id = kvm_hv_get_vpindex(vcpu);
6703         }
6704
6705         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6706         if (vmx->host_debugctlmsr)
6707                 update_debugctlmsr(vmx->host_debugctlmsr);
6708
6709 #ifndef CONFIG_X86_64
6710         /*
6711          * The sysexit path does not restore ds/es, so we must set them to
6712          * a reasonable value ourselves.
6713          *
6714          * We can't defer this to vmx_prepare_switch_to_host() since that
6715          * function may be executed in interrupt context, which saves and
6716          * restore segments around it, nullifying its effect.
6717          */
6718         loadsegment(ds, __USER_DS);
6719         loadsegment(es, __USER_DS);
6720 #endif
6721
6722         vmx_register_cache_reset(vcpu);
6723
6724         pt_guest_exit(vmx);
6725
6726         kvm_load_host_xsave_state(vcpu);
6727
6728         if (is_guest_mode(vcpu)) {
6729                 /*
6730                  * Track VMLAUNCH/VMRESUME that have made past guest state
6731                  * checking.
6732                  */
6733                 if (vmx->nested.nested_run_pending &&
6734                     !vmx->exit_reason.failed_vmentry)
6735                         ++vcpu->stat.nested_run;
6736
6737                 vmx->nested.nested_run_pending = 0;
6738         }
6739
6740         vmx->idt_vectoring_info = 0;
6741
6742         if (unlikely(vmx->fail)) {
6743                 vmx->exit_reason.full = 0xdead;
6744                 return EXIT_FASTPATH_NONE;
6745         }
6746
6747         vmx->exit_reason.full = vmcs_read32(VM_EXIT_REASON);
6748         if (unlikely((u16)vmx->exit_reason.basic == EXIT_REASON_MCE_DURING_VMENTRY))
6749                 kvm_machine_check();
6750
6751         if (likely(!vmx->exit_reason.failed_vmentry))
6752                 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6753
6754         trace_kvm_exit(vmx->exit_reason.full, vcpu, KVM_ISA_VMX);
6755
6756         if (unlikely(vmx->exit_reason.failed_vmentry))
6757                 return EXIT_FASTPATH_NONE;
6758
6759         vmx->loaded_vmcs->launched = 1;
6760
6761         vmx_recover_nmi_blocking(vmx);
6762         vmx_complete_interrupts(vmx);
6763
6764         if (is_guest_mode(vcpu))
6765                 return EXIT_FASTPATH_NONE;
6766
6767         return vmx_exit_handlers_fastpath(vcpu);
6768 }
6769
6770 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6771 {
6772         struct vcpu_vmx *vmx = to_vmx(vcpu);
6773
6774         if (enable_pml)
6775                 vmx_destroy_pml_buffer(vmx);
6776         free_vpid(vmx->vpid);
6777         nested_vmx_free_vcpu(vcpu);
6778         free_loaded_vmcs(vmx->loaded_vmcs);
6779 }
6780
6781 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6782 {
6783         struct vmx_uret_msr *tsx_ctrl;
6784         struct vcpu_vmx *vmx;
6785         int i, cpu, err;
6786
6787         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6788         vmx = to_vmx(vcpu);
6789
6790         err = -ENOMEM;
6791
6792         vmx->vpid = allocate_vpid();
6793
6794         /*
6795          * If PML is turned on, failure on enabling PML just results in failure
6796          * of creating the vcpu, therefore we can simplify PML logic (by
6797          * avoiding dealing with cases, such as enabling PML partially on vcpus
6798          * for the guest), etc.
6799          */
6800         if (enable_pml) {
6801                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6802                 if (!vmx->pml_pg)
6803                         goto free_vpid;
6804         }
6805
6806         for (i = 0; i < kvm_nr_uret_msrs; ++i) {
6807                 vmx->guest_uret_msrs[i].data = 0;
6808                 vmx->guest_uret_msrs[i].mask = -1ull;
6809         }
6810         if (boot_cpu_has(X86_FEATURE_RTM)) {
6811                 /*
6812                  * TSX_CTRL_CPUID_CLEAR is handled in the CPUID interception.
6813                  * Keep the host value unchanged to avoid changing CPUID bits
6814                  * under the host kernel's feet.
6815                  */
6816                 tsx_ctrl = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
6817                 if (tsx_ctrl)
6818                         vmx->guest_uret_msrs[i].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6819         }
6820
6821         err = alloc_loaded_vmcs(&vmx->vmcs01);
6822         if (err < 0)
6823                 goto free_pml;
6824
6825         /* The MSR bitmap starts with all ones */
6826         bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6827         bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6828
6829         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
6830 #ifdef CONFIG_X86_64
6831         vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
6832         vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
6833         vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6834 #endif
6835         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6836         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6837         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6838         if (kvm_cstate_in_guest(vcpu->kvm)) {
6839                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
6840                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6841                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6842                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6843         }
6844         vmx->msr_bitmap_mode = 0;
6845
6846         vmx->loaded_vmcs = &vmx->vmcs01;
6847         cpu = get_cpu();
6848         vmx_vcpu_load(vcpu, cpu);
6849         vcpu->cpu = cpu;
6850         init_vmcs(vmx);
6851         vmx_vcpu_put(vcpu);
6852         put_cpu();
6853         if (cpu_need_virtualize_apic_accesses(vcpu)) {
6854                 err = alloc_apic_access_page(vcpu->kvm);
6855                 if (err)
6856                         goto free_vmcs;
6857         }
6858
6859         if (enable_ept && !enable_unrestricted_guest) {
6860                 err = init_rmode_identity_map(vcpu->kvm);
6861                 if (err)
6862                         goto free_vmcs;
6863         }
6864
6865         if (nested)
6866                 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
6867         else
6868                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6869
6870         vcpu_setup_sgx_lepubkeyhash(vcpu);
6871
6872         vmx->nested.posted_intr_nv = -1;
6873         vmx->nested.current_vmptr = -1ull;
6874         vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
6875
6876         vcpu->arch.microcode_version = 0x100000000ULL;
6877         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6878
6879         /*
6880          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6881          * or POSTED_INTR_WAKEUP_VECTOR.
6882          */
6883         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6884         vmx->pi_desc.sn = 1;
6885
6886         return 0;
6887
6888 free_vmcs:
6889         free_loaded_vmcs(vmx->loaded_vmcs);
6890 free_pml:
6891         vmx_destroy_pml_buffer(vmx);
6892 free_vpid:
6893         free_vpid(vmx->vpid);
6894         return err;
6895 }
6896
6897 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6898 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6899
6900 static int vmx_vm_init(struct kvm *kvm)
6901 {
6902         if (!ple_gap)
6903                 kvm->arch.pause_in_guest = true;
6904
6905         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6906                 switch (l1tf_mitigation) {
6907                 case L1TF_MITIGATION_OFF:
6908                 case L1TF_MITIGATION_FLUSH_NOWARN:
6909                         /* 'I explicitly don't care' is set */
6910                         break;
6911                 case L1TF_MITIGATION_FLUSH:
6912                 case L1TF_MITIGATION_FLUSH_NOSMT:
6913                 case L1TF_MITIGATION_FULL:
6914                         /*
6915                          * Warn upon starting the first VM in a potentially
6916                          * insecure environment.
6917                          */
6918                         if (sched_smt_active())
6919                                 pr_warn_once(L1TF_MSG_SMT);
6920                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6921                                 pr_warn_once(L1TF_MSG_L1D);
6922                         break;
6923                 case L1TF_MITIGATION_FULL_FORCE:
6924                         /* Flush is enforced */
6925                         break;
6926                 }
6927         }
6928         return 0;
6929 }
6930
6931 static int __init vmx_check_processor_compat(void)
6932 {
6933         struct vmcs_config vmcs_conf;
6934         struct vmx_capability vmx_cap;
6935
6936         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6937             !this_cpu_has(X86_FEATURE_VMX)) {
6938                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6939                 return -EIO;
6940         }
6941
6942         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6943                 return -EIO;
6944         if (nested)
6945                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6946         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6947                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6948                                 smp_processor_id());
6949                 return -EIO;
6950         }
6951         return 0;
6952 }
6953
6954 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6955 {
6956         u8 cache;
6957         u64 ipat = 0;
6958
6959         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6960          * memory aliases with conflicting memory types and sometimes MCEs.
6961          * We have to be careful as to what are honored and when.
6962          *
6963          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
6964          * UC.  The effective memory type is UC or WC depending on guest PAT.
6965          * This was historically the source of MCEs and we want to be
6966          * conservative.
6967          *
6968          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6969          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
6970          * EPT memory type is set to WB.  The effective memory type is forced
6971          * WB.
6972          *
6973          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
6974          * EPT memory type is used to emulate guest CD/MTRR.
6975          */
6976
6977         if (is_mmio) {
6978                 cache = MTRR_TYPE_UNCACHABLE;
6979                 goto exit;
6980         }
6981
6982         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6983                 ipat = VMX_EPT_IPAT_BIT;
6984                 cache = MTRR_TYPE_WRBACK;
6985                 goto exit;
6986         }
6987
6988         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6989                 ipat = VMX_EPT_IPAT_BIT;
6990                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6991                         cache = MTRR_TYPE_WRBACK;
6992                 else
6993                         cache = MTRR_TYPE_UNCACHABLE;
6994                 goto exit;
6995         }
6996
6997         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6998
6999 exit:
7000         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
7001 }
7002
7003 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
7004 {
7005         /*
7006          * These bits in the secondary execution controls field
7007          * are dynamic, the others are mostly based on the hypervisor
7008          * architecture and the guest's CPUID.  Do not touch the
7009          * dynamic bits.
7010          */
7011         u32 mask =
7012                 SECONDARY_EXEC_SHADOW_VMCS |
7013                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7014                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7015                 SECONDARY_EXEC_DESC;
7016
7017         u32 new_ctl = vmx->secondary_exec_control;
7018         u32 cur_ctl = secondary_exec_controls_get(vmx);
7019
7020         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7021 }
7022
7023 /*
7024  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7025  * (indicating "allowed-1") if they are supported in the guest's CPUID.
7026  */
7027 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7028 {
7029         struct vcpu_vmx *vmx = to_vmx(vcpu);
7030         struct kvm_cpuid_entry2 *entry;
7031
7032         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7033         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7034
7035 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
7036         if (entry && (entry->_reg & (_cpuid_mask)))                     \
7037                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
7038 } while (0)
7039
7040         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7041         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
7042         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
7043         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
7044         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
7045         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
7046         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
7047         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
7048         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
7049         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
7050         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7051         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
7052         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
7053         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
7054         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
7055
7056         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7057         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
7058         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
7059         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
7060         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
7061         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
7062         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
7063
7064 #undef cr4_fixed1_update
7065 }
7066
7067 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7068 {
7069         struct vcpu_vmx *vmx = to_vmx(vcpu);
7070
7071         if (kvm_mpx_supported()) {
7072                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7073
7074                 if (mpx_enabled) {
7075                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7076                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7077                 } else {
7078                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7079                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7080                 }
7081         }
7082 }
7083
7084 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7085 {
7086         struct vcpu_vmx *vmx = to_vmx(vcpu);
7087         struct kvm_cpuid_entry2 *best = NULL;
7088         int i;
7089
7090         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7091                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7092                 if (!best)
7093                         return;
7094                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7095                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7096                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7097                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7098         }
7099
7100         /* Get the number of configurable Address Ranges for filtering */
7101         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7102                                                 PT_CAP_num_address_ranges);
7103
7104         /* Initialize and clear the no dependency bits */
7105         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7106                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7107
7108         /*
7109          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7110          * will inject an #GP
7111          */
7112         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7113                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7114
7115         /*
7116          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7117          * PSBFreq can be set
7118          */
7119         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7120                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7121                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7122
7123         /*
7124          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7125          * MTCFreq can be set
7126          */
7127         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7128                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7129                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7130
7131         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7132         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7133                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7134                                                         RTIT_CTL_PTW_EN);
7135
7136         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7137         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7138                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7139
7140         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7141         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7142                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7143
7144         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabricEn can be set */
7145         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7146                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7147
7148         /* unmask address range configure area */
7149         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7150                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7151 }
7152
7153 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7154 {
7155         struct vcpu_vmx *vmx = to_vmx(vcpu);
7156
7157         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7158         vcpu->arch.xsaves_enabled = false;
7159
7160         vmx_setup_uret_msrs(vmx);
7161
7162         if (cpu_has_secondary_exec_ctrls()) {
7163                 vmx_compute_secondary_exec_control(vmx);
7164                 vmcs_set_secondary_exec_control(vmx);
7165         }
7166
7167         if (nested_vmx_allowed(vcpu))
7168                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7169                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7170                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7171         else
7172                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7173                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7174                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7175
7176         if (nested_vmx_allowed(vcpu)) {
7177                 nested_vmx_cr_fixed1_bits_update(vcpu);
7178                 nested_vmx_entry_exit_ctls_update(vcpu);
7179         }
7180
7181         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7182                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7183                 update_intel_pt_cfg(vcpu);
7184
7185         if (boot_cpu_has(X86_FEATURE_RTM)) {
7186                 struct vmx_uret_msr *msr;
7187                 msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
7188                 if (msr) {
7189                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7190                         vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7191                 }
7192         }
7193
7194         set_cr4_guest_host_mask(vmx);
7195
7196         vmx_write_encls_bitmap(vcpu, NULL);
7197         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX))
7198                 vmx->msr_ia32_feature_control_valid_bits |= FEAT_CTL_SGX_ENABLED;
7199         else
7200                 vmx->msr_ia32_feature_control_valid_bits &= ~FEAT_CTL_SGX_ENABLED;
7201
7202         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
7203                 vmx->msr_ia32_feature_control_valid_bits |=
7204                         FEAT_CTL_SGX_LC_ENABLED;
7205         else
7206                 vmx->msr_ia32_feature_control_valid_bits &=
7207                         ~FEAT_CTL_SGX_LC_ENABLED;
7208
7209         /* Refresh #PF interception to account for MAXPHYADDR changes. */
7210         vmx_update_exception_bitmap(vcpu);
7211 }
7212
7213 static __init void vmx_set_cpu_caps(void)
7214 {
7215         kvm_set_cpu_caps();
7216
7217         /* CPUID 0x1 */
7218         if (nested)
7219                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7220
7221         /* CPUID 0x7 */
7222         if (kvm_mpx_supported())
7223                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7224         if (!cpu_has_vmx_invpcid())
7225                 kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
7226         if (vmx_pt_mode_is_host_guest())
7227                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7228
7229         if (!enable_sgx) {
7230                 kvm_cpu_cap_clear(X86_FEATURE_SGX);
7231                 kvm_cpu_cap_clear(X86_FEATURE_SGX_LC);
7232                 kvm_cpu_cap_clear(X86_FEATURE_SGX1);
7233                 kvm_cpu_cap_clear(X86_FEATURE_SGX2);
7234         }
7235
7236         if (vmx_umip_emulated())
7237                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7238
7239         /* CPUID 0xD.1 */
7240         supported_xss = 0;
7241         if (!cpu_has_vmx_xsaves())
7242                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7243
7244         /* CPUID 0x80000001 and 0x7 (RDPID) */
7245         if (!cpu_has_vmx_rdtscp()) {
7246                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7247                 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
7248         }
7249
7250         if (cpu_has_vmx_waitpkg())
7251                 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7252 }
7253
7254 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7255 {
7256         to_vmx(vcpu)->req_immediate_exit = true;
7257 }
7258
7259 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7260                                   struct x86_instruction_info *info)
7261 {
7262         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7263         unsigned short port;
7264         bool intercept;
7265         int size;
7266
7267         if (info->intercept == x86_intercept_in ||
7268             info->intercept == x86_intercept_ins) {
7269                 port = info->src_val;
7270                 size = info->dst_bytes;
7271         } else {
7272                 port = info->dst_val;
7273                 size = info->src_bytes;
7274         }
7275
7276         /*
7277          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7278          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7279          * control.
7280          *
7281          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7282          */
7283         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7284                 intercept = nested_cpu_has(vmcs12,
7285                                            CPU_BASED_UNCOND_IO_EXITING);
7286         else
7287                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7288
7289         /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7290         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7291 }
7292
7293 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7294                                struct x86_instruction_info *info,
7295                                enum x86_intercept_stage stage,
7296                                struct x86_exception *exception)
7297 {
7298         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7299
7300         switch (info->intercept) {
7301         /*
7302          * RDPID causes #UD if disabled through secondary execution controls.
7303          * Because it is marked as EmulateOnUD, we need to intercept it here.
7304          * Note, RDPID is hidden behind ENABLE_RDTSCP.
7305          */
7306         case x86_intercept_rdpid:
7307                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) {
7308                         exception->vector = UD_VECTOR;
7309                         exception->error_code_valid = false;
7310                         return X86EMUL_PROPAGATE_FAULT;
7311                 }
7312                 break;
7313
7314         case x86_intercept_in:
7315         case x86_intercept_ins:
7316         case x86_intercept_out:
7317         case x86_intercept_outs:
7318                 return vmx_check_intercept_io(vcpu, info);
7319
7320         case x86_intercept_lgdt:
7321         case x86_intercept_lidt:
7322         case x86_intercept_lldt:
7323         case x86_intercept_ltr:
7324         case x86_intercept_sgdt:
7325         case x86_intercept_sidt:
7326         case x86_intercept_sldt:
7327         case x86_intercept_str:
7328                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7329                         return X86EMUL_CONTINUE;
7330
7331                 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7332                 break;
7333
7334         /* TODO: check more intercepts... */
7335         default:
7336                 break;
7337         }
7338
7339         return X86EMUL_UNHANDLEABLE;
7340 }
7341
7342 #ifdef CONFIG_X86_64
7343 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7344 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7345                                   u64 divisor, u64 *result)
7346 {
7347         u64 low = a << shift, high = a >> (64 - shift);
7348
7349         /* To avoid the overflow on divq */
7350         if (high >= divisor)
7351                 return 1;
7352
7353         /* Low hold the result, high hold rem which is discarded */
7354         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7355             "rm" (divisor), "0" (low), "1" (high));
7356         *result = low;
7357
7358         return 0;
7359 }
7360
7361 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7362                             bool *expired)
7363 {
7364         struct vcpu_vmx *vmx;
7365         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7366         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7367
7368         vmx = to_vmx(vcpu);
7369         tscl = rdtsc();
7370         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7371         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7372         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7373                                                     ktimer->timer_advance_ns);
7374
7375         if (delta_tsc > lapic_timer_advance_cycles)
7376                 delta_tsc -= lapic_timer_advance_cycles;
7377         else
7378                 delta_tsc = 0;
7379
7380         /* Convert to host delta tsc if tsc scaling is enabled */
7381         if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7382             delta_tsc && u64_shl_div_u64(delta_tsc,
7383                                 kvm_tsc_scaling_ratio_frac_bits,
7384                                 vcpu->arch.l1_tsc_scaling_ratio, &delta_tsc))
7385                 return -ERANGE;
7386
7387         /*
7388          * If the delta tsc can't fit in the 32 bit after the multi shift,
7389          * we can't use the preemption timer.
7390          * It's possible that it fits on later vmentries, but checking
7391          * on every vmentry is costly so we just use an hrtimer.
7392          */
7393         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7394                 return -ERANGE;
7395
7396         vmx->hv_deadline_tsc = tscl + delta_tsc;
7397         *expired = !delta_tsc;
7398         return 0;
7399 }
7400
7401 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7402 {
7403         to_vmx(vcpu)->hv_deadline_tsc = -1;
7404 }
7405 #endif
7406
7407 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7408 {
7409         if (!kvm_pause_in_guest(vcpu->kvm))
7410                 shrink_ple_window(vcpu);
7411 }
7412
7413 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu)
7414 {
7415         struct vcpu_vmx *vmx = to_vmx(vcpu);
7416
7417         if (is_guest_mode(vcpu)) {
7418                 vmx->nested.update_vmcs01_cpu_dirty_logging = true;
7419                 return;
7420         }
7421
7422         /*
7423          * Note, cpu_dirty_logging_count can be changed concurrent with this
7424          * code, but in that case another update request will be made and so
7425          * the guest will never run with a stale PML value.
7426          */
7427         if (vcpu->kvm->arch.cpu_dirty_logging_count)
7428                 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7429         else
7430                 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7431 }
7432
7433 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7434 {
7435         if (pi_pre_block(vcpu))
7436                 return 1;
7437
7438         if (kvm_lapic_hv_timer_in_use(vcpu))
7439                 kvm_lapic_switch_to_sw_timer(vcpu);
7440
7441         return 0;
7442 }
7443
7444 static void vmx_post_block(struct kvm_vcpu *vcpu)
7445 {
7446         if (kvm_x86_ops.set_hv_timer)
7447                 kvm_lapic_switch_to_hv_timer(vcpu);
7448
7449         pi_post_block(vcpu);
7450 }
7451
7452 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7453 {
7454         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7455                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7456                         FEAT_CTL_LMCE_ENABLED;
7457         else
7458                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7459                         ~FEAT_CTL_LMCE_ENABLED;
7460 }
7461
7462 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7463 {
7464         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7465         if (to_vmx(vcpu)->nested.nested_run_pending)
7466                 return -EBUSY;
7467         return !is_smm(vcpu);
7468 }
7469
7470 static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7471 {
7472         struct vcpu_vmx *vmx = to_vmx(vcpu);
7473
7474         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7475         if (vmx->nested.smm.guest_mode)
7476                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7477
7478         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7479         vmx->nested.vmxon = false;
7480         vmx_clear_hlt(vcpu);
7481         return 0;
7482 }
7483
7484 static int vmx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7485 {
7486         struct vcpu_vmx *vmx = to_vmx(vcpu);
7487         int ret;
7488
7489         if (vmx->nested.smm.vmxon) {
7490                 vmx->nested.vmxon = true;
7491                 vmx->nested.smm.vmxon = false;
7492         }
7493
7494         if (vmx->nested.smm.guest_mode) {
7495                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7496                 if (ret)
7497                         return ret;
7498
7499                 vmx->nested.smm.guest_mode = false;
7500         }
7501         return 0;
7502 }
7503
7504 static void vmx_enable_smi_window(struct kvm_vcpu *vcpu)
7505 {
7506         /* RSM will cause a vmexit anyway.  */
7507 }
7508
7509 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7510 {
7511         return to_vmx(vcpu)->nested.vmxon && !is_guest_mode(vcpu);
7512 }
7513
7514 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7515 {
7516         if (is_guest_mode(vcpu)) {
7517                 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7518
7519                 if (hrtimer_try_to_cancel(timer) == 1)
7520                         hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7521         }
7522 }
7523
7524 static void hardware_unsetup(void)
7525 {
7526         if (nested)
7527                 nested_vmx_hardware_unsetup();
7528
7529         free_kvm_area();
7530 }
7531
7532 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7533 {
7534         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7535                           BIT(APICV_INHIBIT_REASON_HYPERV);
7536
7537         return supported & BIT(bit);
7538 }
7539
7540 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7541         .hardware_unsetup = hardware_unsetup,
7542
7543         .hardware_enable = hardware_enable,
7544         .hardware_disable = hardware_disable,
7545         .cpu_has_accelerated_tpr = report_flexpriority,
7546         .has_emulated_msr = vmx_has_emulated_msr,
7547
7548         .vm_size = sizeof(struct kvm_vmx),
7549         .vm_init = vmx_vm_init,
7550
7551         .vcpu_create = vmx_create_vcpu,
7552         .vcpu_free = vmx_free_vcpu,
7553         .vcpu_reset = vmx_vcpu_reset,
7554
7555         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7556         .vcpu_load = vmx_vcpu_load,
7557         .vcpu_put = vmx_vcpu_put,
7558
7559         .update_exception_bitmap = vmx_update_exception_bitmap,
7560         .get_msr_feature = vmx_get_msr_feature,
7561         .get_msr = vmx_get_msr,
7562         .set_msr = vmx_set_msr,
7563         .get_segment_base = vmx_get_segment_base,
7564         .get_segment = vmx_get_segment,
7565         .set_segment = vmx_set_segment,
7566         .get_cpl = vmx_get_cpl,
7567         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7568         .set_cr0 = vmx_set_cr0,
7569         .is_valid_cr4 = vmx_is_valid_cr4,
7570         .set_cr4 = vmx_set_cr4,
7571         .set_efer = vmx_set_efer,
7572         .get_idt = vmx_get_idt,
7573         .set_idt = vmx_set_idt,
7574         .get_gdt = vmx_get_gdt,
7575         .set_gdt = vmx_set_gdt,
7576         .set_dr7 = vmx_set_dr7,
7577         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7578         .cache_reg = vmx_cache_reg,
7579         .get_rflags = vmx_get_rflags,
7580         .set_rflags = vmx_set_rflags,
7581
7582         .tlb_flush_all = vmx_flush_tlb_all,
7583         .tlb_flush_current = vmx_flush_tlb_current,
7584         .tlb_flush_gva = vmx_flush_tlb_gva,
7585         .tlb_flush_guest = vmx_flush_tlb_guest,
7586
7587         .run = vmx_vcpu_run,
7588         .handle_exit = vmx_handle_exit,
7589         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7590         .update_emulated_instruction = vmx_update_emulated_instruction,
7591         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7592         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7593         .patch_hypercall = vmx_patch_hypercall,
7594         .set_irq = vmx_inject_irq,
7595         .set_nmi = vmx_inject_nmi,
7596         .queue_exception = vmx_queue_exception,
7597         .cancel_injection = vmx_cancel_injection,
7598         .interrupt_allowed = vmx_interrupt_allowed,
7599         .nmi_allowed = vmx_nmi_allowed,
7600         .get_nmi_mask = vmx_get_nmi_mask,
7601         .set_nmi_mask = vmx_set_nmi_mask,
7602         .enable_nmi_window = vmx_enable_nmi_window,
7603         .enable_irq_window = vmx_enable_irq_window,
7604         .update_cr8_intercept = vmx_update_cr8_intercept,
7605         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7606         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7607         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7608         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7609         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7610         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7611         .hwapic_irr_update = vmx_hwapic_irr_update,
7612         .hwapic_isr_update = vmx_hwapic_isr_update,
7613         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7614         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7615         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7616         .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
7617
7618         .set_tss_addr = vmx_set_tss_addr,
7619         .set_identity_map_addr = vmx_set_identity_map_addr,
7620         .get_mt_mask = vmx_get_mt_mask,
7621
7622         .get_exit_info = vmx_get_exit_info,
7623
7624         .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7625
7626         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7627
7628         .get_l2_tsc_offset = vmx_get_l2_tsc_offset,
7629         .get_l2_tsc_multiplier = vmx_get_l2_tsc_multiplier,
7630         .write_tsc_offset = vmx_write_tsc_offset,
7631         .write_tsc_multiplier = vmx_write_tsc_multiplier,
7632
7633         .load_mmu_pgd = vmx_load_mmu_pgd,
7634
7635         .check_intercept = vmx_check_intercept,
7636         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7637
7638         .request_immediate_exit = vmx_request_immediate_exit,
7639
7640         .sched_in = vmx_sched_in,
7641
7642         .cpu_dirty_log_size = PML_ENTITY_NUM,
7643         .update_cpu_dirty_logging = vmx_update_cpu_dirty_logging,
7644
7645         .pre_block = vmx_pre_block,
7646         .post_block = vmx_post_block,
7647
7648         .pmu_ops = &intel_pmu_ops,
7649         .nested_ops = &vmx_nested_ops,
7650
7651         .update_pi_irte = pi_update_irte,
7652         .start_assignment = vmx_pi_start_assignment,
7653
7654 #ifdef CONFIG_X86_64
7655         .set_hv_timer = vmx_set_hv_timer,
7656         .cancel_hv_timer = vmx_cancel_hv_timer,
7657 #endif
7658
7659         .setup_mce = vmx_setup_mce,
7660
7661         .smi_allowed = vmx_smi_allowed,
7662         .enter_smm = vmx_enter_smm,
7663         .leave_smm = vmx_leave_smm,
7664         .enable_smi_window = vmx_enable_smi_window,
7665
7666         .can_emulate_instruction = vmx_can_emulate_instruction,
7667         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7668         .migrate_timers = vmx_migrate_timers,
7669
7670         .msr_filter_changed = vmx_msr_filter_changed,
7671         .complete_emulated_msr = kvm_complete_insn_gp,
7672
7673         .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector,
7674 };
7675
7676 static __init void vmx_setup_user_return_msrs(void)
7677 {
7678
7679         /*
7680          * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
7681          * will emulate SYSCALL in legacy mode if the vendor string in guest
7682          * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
7683          * support this emulation, MSR_STAR is included in the list for i386,
7684          * but is never loaded into hardware.  MSR_CSTAR is also never loaded
7685          * into hardware and is here purely for emulation purposes.
7686          */
7687         const u32 vmx_uret_msrs_list[] = {
7688         #ifdef CONFIG_X86_64
7689                 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
7690         #endif
7691                 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
7692                 MSR_IA32_TSX_CTRL,
7693         };
7694         int i;
7695
7696         BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
7697
7698         for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
7699                 kvm_add_user_return_msr(vmx_uret_msrs_list[i]);
7700 }
7701
7702 static __init int hardware_setup(void)
7703 {
7704         unsigned long host_bndcfgs;
7705         struct desc_ptr dt;
7706         int r, ept_lpage_level;
7707
7708         store_idt(&dt);
7709         host_idt_base = dt.address;
7710
7711         vmx_setup_user_return_msrs();
7712
7713         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7714                 return -EIO;
7715
7716         if (boot_cpu_has(X86_FEATURE_NX))
7717                 kvm_enable_efer_bits(EFER_NX);
7718
7719         if (boot_cpu_has(X86_FEATURE_MPX)) {
7720                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7721                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7722         }
7723
7724         if (!cpu_has_vmx_mpx())
7725                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7726                                     XFEATURE_MASK_BNDCSR);
7727
7728         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7729             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7730                 enable_vpid = 0;
7731
7732         if (!cpu_has_vmx_ept() ||
7733             !cpu_has_vmx_ept_4levels() ||
7734             !cpu_has_vmx_ept_mt_wb() ||
7735             !cpu_has_vmx_invept_global())
7736                 enable_ept = 0;
7737
7738         /* NX support is required for shadow paging. */
7739         if (!enable_ept && !boot_cpu_has(X86_FEATURE_NX)) {
7740                 pr_err_ratelimited("kvm: NX (Execute Disable) not supported\n");
7741                 return -EOPNOTSUPP;
7742         }
7743
7744         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7745                 enable_ept_ad_bits = 0;
7746
7747         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7748                 enable_unrestricted_guest = 0;
7749
7750         if (!cpu_has_vmx_flexpriority())
7751                 flexpriority_enabled = 0;
7752
7753         if (!cpu_has_virtual_nmis())
7754                 enable_vnmi = 0;
7755
7756         /*
7757          * set_apic_access_page_addr() is used to reload apic access
7758          * page upon invalidation.  No need to do anything if not
7759          * using the APIC_ACCESS_ADDR VMCS field.
7760          */
7761         if (!flexpriority_enabled)
7762                 vmx_x86_ops.set_apic_access_page_addr = NULL;
7763
7764         if (!cpu_has_vmx_tpr_shadow())
7765                 vmx_x86_ops.update_cr8_intercept = NULL;
7766
7767 #if IS_ENABLED(CONFIG_HYPERV)
7768         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7769             && enable_ept) {
7770                 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7771                 vmx_x86_ops.tlb_remote_flush_with_range =
7772                                 hv_remote_flush_tlb_with_range;
7773         }
7774 #endif
7775
7776         if (!cpu_has_vmx_ple()) {
7777                 ple_gap = 0;
7778                 ple_window = 0;
7779                 ple_window_grow = 0;
7780                 ple_window_max = 0;
7781                 ple_window_shrink = 0;
7782         }
7783
7784         if (!cpu_has_vmx_apicv()) {
7785                 enable_apicv = 0;
7786                 vmx_x86_ops.sync_pir_to_irr = NULL;
7787         }
7788
7789         if (cpu_has_vmx_tsc_scaling()) {
7790                 kvm_has_tsc_control = true;
7791                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7792                 kvm_tsc_scaling_ratio_frac_bits = 48;
7793         }
7794
7795         kvm_has_bus_lock_exit = cpu_has_vmx_bus_lock_detection();
7796
7797         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7798
7799         if (enable_ept)
7800                 kvm_mmu_set_ept_masks(enable_ept_ad_bits,
7801                                       cpu_has_vmx_ept_execute_only());
7802
7803         if (!enable_ept)
7804                 ept_lpage_level = 0;
7805         else if (cpu_has_vmx_ept_1g_page())
7806                 ept_lpage_level = PG_LEVEL_1G;
7807         else if (cpu_has_vmx_ept_2m_page())
7808                 ept_lpage_level = PG_LEVEL_2M;
7809         else
7810                 ept_lpage_level = PG_LEVEL_4K;
7811         kvm_configure_mmu(enable_ept, vmx_get_max_tdp_level(), ept_lpage_level);
7812
7813         /*
7814          * Only enable PML when hardware supports PML feature, and both EPT
7815          * and EPT A/D bit features are enabled -- PML depends on them to work.
7816          */
7817         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7818                 enable_pml = 0;
7819
7820         if (!enable_pml)
7821                 vmx_x86_ops.cpu_dirty_log_size = 0;
7822
7823         if (!cpu_has_vmx_preemption_timer())
7824                 enable_preemption_timer = false;
7825
7826         if (enable_preemption_timer) {
7827                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7828                 u64 vmx_msr;
7829
7830                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7831                 cpu_preemption_timer_multi =
7832                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7833
7834                 if (tsc_khz)
7835                         use_timer_freq = (u64)tsc_khz * 1000;
7836                 use_timer_freq >>= cpu_preemption_timer_multi;
7837
7838                 /*
7839                  * KVM "disables" the preemption timer by setting it to its max
7840                  * value.  Don't use the timer if it might cause spurious exits
7841                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7842                  */
7843                 if (use_timer_freq > 0xffffffffu / 10)
7844                         enable_preemption_timer = false;
7845         }
7846
7847         if (!enable_preemption_timer) {
7848                 vmx_x86_ops.set_hv_timer = NULL;
7849                 vmx_x86_ops.cancel_hv_timer = NULL;
7850                 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
7851         }
7852
7853         kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler);
7854
7855         kvm_mce_cap_supported |= MCG_LMCE_P;
7856
7857         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7858                 return -EINVAL;
7859         if (!enable_ept || !cpu_has_vmx_intel_pt())
7860                 pt_mode = PT_MODE_SYSTEM;
7861
7862         setup_default_sgx_lepubkeyhash();
7863
7864         if (nested) {
7865                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7866                                            vmx_capability.ept);
7867
7868                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7869                 if (r)
7870                         return r;
7871         }
7872
7873         vmx_set_cpu_caps();
7874
7875         r = alloc_kvm_area();
7876         if (r)
7877                 nested_vmx_hardware_unsetup();
7878         return r;
7879 }
7880
7881 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
7882         .cpu_has_kvm_support = cpu_has_kvm_support,
7883         .disabled_by_bios = vmx_disabled_by_bios,
7884         .check_processor_compatibility = vmx_check_processor_compat,
7885         .hardware_setup = hardware_setup,
7886
7887         .runtime_ops = &vmx_x86_ops,
7888 };
7889
7890 static void vmx_cleanup_l1d_flush(void)
7891 {
7892         if (vmx_l1d_flush_pages) {
7893                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7894                 vmx_l1d_flush_pages = NULL;
7895         }
7896         /* Restore state so sysfs ignores VMX */
7897         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7898 }
7899
7900 static void vmx_exit(void)
7901 {
7902 #ifdef CONFIG_KEXEC_CORE
7903         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7904         synchronize_rcu();
7905 #endif
7906
7907         kvm_exit();
7908
7909 #if IS_ENABLED(CONFIG_HYPERV)
7910         if (static_branch_unlikely(&enable_evmcs)) {
7911                 int cpu;
7912                 struct hv_vp_assist_page *vp_ap;
7913                 /*
7914                  * Reset everything to support using non-enlightened VMCS
7915                  * access later (e.g. when we reload the module with
7916                  * enlightened_vmcs=0)
7917                  */
7918                 for_each_online_cpu(cpu) {
7919                         vp_ap = hv_get_vp_assist_page(cpu);
7920
7921                         if (!vp_ap)
7922                                 continue;
7923
7924                         vp_ap->nested_control.features.directhypercall = 0;
7925                         vp_ap->current_nested_vmcs = 0;
7926                         vp_ap->enlighten_vmentry = 0;
7927                 }
7928
7929                 static_branch_disable(&enable_evmcs);
7930         }
7931 #endif
7932         vmx_cleanup_l1d_flush();
7933
7934         allow_smaller_maxphyaddr = false;
7935 }
7936 module_exit(vmx_exit);
7937
7938 static int __init vmx_init(void)
7939 {
7940         int r, cpu;
7941
7942 #if IS_ENABLED(CONFIG_HYPERV)
7943         /*
7944          * Enlightened VMCS usage should be recommended and the host needs
7945          * to support eVMCS v1 or above. We can also disable eVMCS support
7946          * with module parameter.
7947          */
7948         if (enlightened_vmcs &&
7949             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7950             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7951             KVM_EVMCS_VERSION) {
7952                 int cpu;
7953
7954                 /* Check that we have assist pages on all online CPUs */
7955                 for_each_online_cpu(cpu) {
7956                         if (!hv_get_vp_assist_page(cpu)) {
7957                                 enlightened_vmcs = false;
7958                                 break;
7959                         }
7960                 }
7961
7962                 if (enlightened_vmcs) {
7963                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7964                         static_branch_enable(&enable_evmcs);
7965                 }
7966
7967                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7968                         vmx_x86_ops.enable_direct_tlbflush
7969                                 = hv_enable_direct_tlbflush;
7970
7971         } else {
7972                 enlightened_vmcs = false;
7973         }
7974 #endif
7975
7976         r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
7977                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7978         if (r)
7979                 return r;
7980
7981         /*
7982          * Must be called after kvm_init() so enable_ept is properly set
7983          * up. Hand the parameter mitigation value in which was stored in
7984          * the pre module init parser. If no parameter was given, it will
7985          * contain 'auto' which will be turned into the default 'cond'
7986          * mitigation mode.
7987          */
7988         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7989         if (r) {
7990                 vmx_exit();
7991                 return r;
7992         }
7993
7994         for_each_possible_cpu(cpu) {
7995                 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
7996
7997                 pi_init_cpu(cpu);
7998         }
7999
8000 #ifdef CONFIG_KEXEC_CORE
8001         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8002                            crash_vmclear_local_loaded_vmcss);
8003 #endif
8004         vmx_check_vmcs12_offsets();
8005
8006         /*
8007          * Shadow paging doesn't have a (further) performance penalty
8008          * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it
8009          * by default
8010          */
8011         if (!enable_ept)
8012                 allow_smaller_maxphyaddr = true;
8013
8014         return 0;
8015 }
8016 module_init(vmx_init);