1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/frame.h>
17 #include <linux/highmem.h>
18 #include <linux/hrtimer.h>
19 #include <linux/kernel.h>
20 #include <linux/kvm_host.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/mod_devicetable.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
30 #include <linux/entry-kvm.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/debugreg.h>
38 #include <asm/fpu/internal.h>
40 #include <asm/irq_remapping.h>
41 #include <asm/kexec.h>
42 #include <asm/perf_event.h>
44 #include <asm/mmu_context.h>
45 #include <asm/mshyperv.h>
46 #include <asm/mwait.h>
47 #include <asm/spec-ctrl.h>
48 #include <asm/virtext.h>
51 #include "capabilities.h"
55 #include "kvm_cache_regs.h"
67 MODULE_AUTHOR("Qumranet");
68 MODULE_LICENSE("GPL");
71 static const struct x86_cpu_id vmx_cpu_id[] = {
72 X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
75 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
78 bool __read_mostly enable_vpid = 1;
79 module_param_named(vpid, enable_vpid, bool, 0444);
81 static bool __read_mostly enable_vnmi = 1;
82 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
84 bool __read_mostly flexpriority_enabled = 1;
85 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
87 bool __read_mostly enable_ept = 1;
88 module_param_named(ept, enable_ept, bool, S_IRUGO);
90 bool __read_mostly enable_unrestricted_guest = 1;
91 module_param_named(unrestricted_guest,
92 enable_unrestricted_guest, bool, S_IRUGO);
94 bool __read_mostly enable_ept_ad_bits = 1;
95 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
97 static bool __read_mostly emulate_invalid_guest_state = true;
98 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
100 static bool __read_mostly fasteoi = 1;
101 module_param(fasteoi, bool, S_IRUGO);
103 bool __read_mostly enable_apicv = 1;
104 module_param(enable_apicv, bool, S_IRUGO);
107 * If nested=1, nested virtualization is supported, i.e., guests may use
108 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
109 * use VMX instructions.
111 static bool __read_mostly nested = 1;
112 module_param(nested, bool, S_IRUGO);
114 bool __read_mostly enable_pml = 1;
115 module_param_named(pml, enable_pml, bool, S_IRUGO);
117 static bool __read_mostly dump_invalid_vmcs = 0;
118 module_param(dump_invalid_vmcs, bool, 0644);
120 #define MSR_BITMAP_MODE_X2APIC 1
121 #define MSR_BITMAP_MODE_X2APIC_APICV 2
123 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
125 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
126 static int __read_mostly cpu_preemption_timer_multi;
127 static bool __read_mostly enable_preemption_timer = 1;
129 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
132 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
133 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
134 #define KVM_VM_CR0_ALWAYS_ON \
135 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
136 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
147 RTIT_STATUS_BYTECNT))
149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
150 (~((1UL << cpuid_maxphyaddr(vcpu)) - 1) | 0x7f)
153 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
154 * ple_gap: upper bound on the amount of time between two successive
155 * executions of PAUSE in a loop. Also indicate if ple enabled.
156 * According to test, this time is usually smaller than 128 cycles.
157 * ple_window: upper bound on the amount of time a guest is allowed to execute
158 * in a PAUSE loop. Tests indicate that most spinlocks are held for
159 * less than 2^12 cycles
160 * Time is measured based on a counter that runs at the same rate as the TSC,
161 * refer SDM volume 3b section 21.6.13 & 22.1.3.
163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
164 module_param(ple_gap, uint, 0444);
166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167 module_param(ple_window, uint, 0444);
169 /* Default doubles per-vcpu window every exit. */
170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
171 module_param(ple_window_grow, uint, 0444);
173 /* Default resets per-vcpu window every exit to ple_window. */
174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
175 module_param(ple_window_shrink, uint, 0444);
177 /* Default is to compute the maximum so we can never overflow. */
178 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179 module_param(ple_window_max, uint, 0444);
181 /* Default is SYSTEM mode, 1 for host-guest mode */
182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
183 module_param(pt_mode, int, S_IRUGO);
185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
189 /* Storage for pre module init parameter parsing */
190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
192 static const struct {
195 } vmentry_l1d_param[] = {
196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
198 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
204 #define L1D_CACHE_ORDER 4
205 static void *vmx_l1d_flush_pages;
207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
212 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
218 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
222 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
225 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
226 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
227 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
232 /* If set to auto use the default l1tf mitigation method */
233 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
234 switch (l1tf_mitigation) {
235 case L1TF_MITIGATION_OFF:
236 l1tf = VMENTER_L1D_FLUSH_NEVER;
238 case L1TF_MITIGATION_FLUSH_NOWARN:
239 case L1TF_MITIGATION_FLUSH:
240 case L1TF_MITIGATION_FLUSH_NOSMT:
241 l1tf = VMENTER_L1D_FLUSH_COND;
243 case L1TF_MITIGATION_FULL:
244 case L1TF_MITIGATION_FULL_FORCE:
245 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
248 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
249 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
252 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
253 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
255 * This allocation for vmx_l1d_flush_pages is not tied to a VM
256 * lifetime and so should not be charged to a memcg.
258 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
261 vmx_l1d_flush_pages = page_address(page);
264 * Initialize each page with a different pattern in
265 * order to protect against KSM in the nested
266 * virtualization case.
268 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
269 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
274 l1tf_vmx_mitigation = l1tf;
276 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
277 static_branch_enable(&vmx_l1d_should_flush);
279 static_branch_disable(&vmx_l1d_should_flush);
281 if (l1tf == VMENTER_L1D_FLUSH_COND)
282 static_branch_enable(&vmx_l1d_flush_cond);
284 static_branch_disable(&vmx_l1d_flush_cond);
288 static int vmentry_l1d_flush_parse(const char *s)
293 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
294 if (vmentry_l1d_param[i].for_parse &&
295 sysfs_streq(s, vmentry_l1d_param[i].option))
302 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
306 l1tf = vmentry_l1d_flush_parse(s);
310 if (!boot_cpu_has(X86_BUG_L1TF))
314 * Has vmx_init() run already? If not then this is the pre init
315 * parameter parsing. In that case just store the value and let
316 * vmx_init() do the proper setup after enable_ept has been
319 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
320 vmentry_l1d_flush_param = l1tf;
324 mutex_lock(&vmx_l1d_flush_mutex);
325 ret = vmx_setup_l1d_flush(l1tf);
326 mutex_unlock(&vmx_l1d_flush_mutex);
330 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
332 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
333 return sprintf(s, "???\n");
335 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
338 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
339 .set = vmentry_l1d_flush_set,
340 .get = vmentry_l1d_flush_get,
342 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
344 static bool guest_state_valid(struct kvm_vcpu *vcpu);
345 static u32 vmx_segment_access_rights(struct kvm_segment *var);
346 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
349 void vmx_vmexit(void);
351 #define vmx_insn_failed(fmt...) \
354 pr_warn_ratelimited(fmt); \
357 asmlinkage void vmread_error(unsigned long field, bool fault)
360 kvm_spurious_fault();
362 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
365 noinline void vmwrite_error(unsigned long field, unsigned long value)
367 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
368 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
371 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
373 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
376 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
378 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
381 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
383 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
387 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
389 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
393 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
394 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
396 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
397 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
399 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
402 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
403 * can find which vCPU should be waken up.
405 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
406 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
408 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
409 static DEFINE_SPINLOCK(vmx_vpid_lock);
411 struct vmcs_config vmcs_config;
412 struct vmx_capability vmx_capability;
414 #define VMX_SEGMENT_FIELD(seg) \
415 [VCPU_SREG_##seg] = { \
416 .selector = GUEST_##seg##_SELECTOR, \
417 .base = GUEST_##seg##_BASE, \
418 .limit = GUEST_##seg##_LIMIT, \
419 .ar_bytes = GUEST_##seg##_AR_BYTES, \
422 static const struct kvm_vmx_segment_field {
427 } kvm_vmx_segment_fields[] = {
428 VMX_SEGMENT_FIELD(CS),
429 VMX_SEGMENT_FIELD(DS),
430 VMX_SEGMENT_FIELD(ES),
431 VMX_SEGMENT_FIELD(FS),
432 VMX_SEGMENT_FIELD(GS),
433 VMX_SEGMENT_FIELD(SS),
434 VMX_SEGMENT_FIELD(TR),
435 VMX_SEGMENT_FIELD(LDTR),
438 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
440 vmx->segment_cache.bitmask = 0;
443 static unsigned long host_idt_base;
446 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
447 * will emulate SYSCALL in legacy mode if the vendor string in guest
448 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
449 * support this emulation, IA32_STAR must always be included in
450 * vmx_msr_index[], even in i386 builds.
452 const u32 vmx_msr_index[] = {
454 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
456 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
460 #if IS_ENABLED(CONFIG_HYPERV)
461 static bool __read_mostly enlightened_vmcs = true;
462 module_param(enlightened_vmcs, bool, 0444);
464 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
465 static void check_ept_pointer_match(struct kvm *kvm)
467 struct kvm_vcpu *vcpu;
468 u64 tmp_eptp = INVALID_PAGE;
471 kvm_for_each_vcpu(i, vcpu, kvm) {
472 if (!VALID_PAGE(tmp_eptp)) {
473 tmp_eptp = to_vmx(vcpu)->ept_pointer;
474 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
475 to_kvm_vmx(kvm)->ept_pointers_match
476 = EPT_POINTERS_MISMATCH;
481 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
484 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
487 struct kvm_tlb_range *range = data;
489 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
493 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
494 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
496 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
499 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
500 * of the base of EPT PML4 table, strip off EPT configuration
504 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
505 kvm_fill_hv_flush_list_func, (void *)range);
507 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
510 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
511 struct kvm_tlb_range *range)
513 struct kvm_vcpu *vcpu;
516 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
518 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
519 check_ept_pointer_match(kvm);
521 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
522 kvm_for_each_vcpu(i, vcpu, kvm) {
523 /* If ept_pointer is invalid pointer, bypass flush request. */
524 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
525 ret |= __hv_remote_flush_tlb_with_range(
529 ret = __hv_remote_flush_tlb_with_range(kvm,
530 kvm_get_vcpu(kvm, 0), range);
533 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
536 static int hv_remote_flush_tlb(struct kvm *kvm)
538 return hv_remote_flush_tlb_with_range(kvm, NULL);
541 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
543 struct hv_enlightened_vmcs *evmcs;
544 struct hv_partition_assist_pg **p_hv_pa_pg =
545 &vcpu->kvm->arch.hyperv.hv_pa_pg;
547 * Synthetic VM-Exit is not enabled in current code and so All
548 * evmcs in singe VM shares same assist page.
551 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
556 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
558 evmcs->partition_assist_page =
560 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
561 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
566 #endif /* IS_ENABLED(CONFIG_HYPERV) */
569 * Comment's format: document - errata name - stepping - processor name.
571 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
573 static u32 vmx_preemption_cpu_tfms[] = {
574 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
576 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
577 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
578 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
580 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
582 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
583 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
585 * 320767.pdf - AAP86 - B1 -
586 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
589 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
591 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
593 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
595 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
596 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
597 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
599 /* Xeon E3-1220 V2 */
603 static inline bool cpu_has_broken_vmx_preemption_timer(void)
605 u32 eax = cpuid_eax(0x00000001), i;
607 /* Clear the reserved bits */
608 eax &= ~(0x3U << 14 | 0xfU << 28);
609 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
610 if (eax == vmx_preemption_cpu_tfms[i])
616 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
618 return flexpriority_enabled && lapic_in_kernel(vcpu);
621 static inline bool report_flexpriority(void)
623 return flexpriority_enabled;
626 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
630 for (i = 0; i < vmx->nmsrs; ++i)
631 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
636 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
640 i = __find_msr_index(vmx, msr);
642 return &vmx->guest_msrs[i];
646 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
650 u64 old_msr_data = msr->data;
652 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
654 ret = kvm_set_shared_msr(msr->index, msr->data,
658 msr->data = old_msr_data;
663 #ifdef CONFIG_KEXEC_CORE
664 static void crash_vmclear_local_loaded_vmcss(void)
666 int cpu = raw_smp_processor_id();
667 struct loaded_vmcs *v;
669 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
670 loaded_vmcss_on_cpu_link)
673 #endif /* CONFIG_KEXEC_CORE */
675 static void __loaded_vmcs_clear(void *arg)
677 struct loaded_vmcs *loaded_vmcs = arg;
678 int cpu = raw_smp_processor_id();
680 if (loaded_vmcs->cpu != cpu)
681 return; /* vcpu migration can race with cpu offline */
682 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
683 per_cpu(current_vmcs, cpu) = NULL;
685 vmcs_clear(loaded_vmcs->vmcs);
686 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
687 vmcs_clear(loaded_vmcs->shadow_vmcs);
689 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
692 * Ensure all writes to loaded_vmcs, including deleting it from its
693 * current percpu list, complete before setting loaded_vmcs->vcpu to
694 * -1, otherwise a different cpu can see vcpu == -1 first and add
695 * loaded_vmcs to its percpu list before it's deleted from this cpu's
696 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
700 loaded_vmcs->cpu = -1;
701 loaded_vmcs->launched = 0;
704 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
706 int cpu = loaded_vmcs->cpu;
709 smp_call_function_single(cpu,
710 __loaded_vmcs_clear, loaded_vmcs, 1);
713 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
717 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
719 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
720 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
721 vmx->segment_cache.bitmask = 0;
723 ret = vmx->segment_cache.bitmask & mask;
724 vmx->segment_cache.bitmask |= mask;
728 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
730 u16 *p = &vmx->segment_cache.seg[seg].selector;
732 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
733 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
737 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
739 ulong *p = &vmx->segment_cache.seg[seg].base;
741 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
742 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
746 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
748 u32 *p = &vmx->segment_cache.seg[seg].limit;
750 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
751 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
755 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
757 u32 *p = &vmx->segment_cache.seg[seg].ar;
759 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
760 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
764 void update_exception_bitmap(struct kvm_vcpu *vcpu)
768 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
769 (1u << DB_VECTOR) | (1u << AC_VECTOR);
771 * Guest access to VMware backdoor ports could legitimately
772 * trigger #GP because of TSS I/O permission bitmap.
773 * We intercept those #GP and allow access to them anyway
776 if (enable_vmware_backdoor)
777 eb |= (1u << GP_VECTOR);
778 if ((vcpu->guest_debug &
779 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
780 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
781 eb |= 1u << BP_VECTOR;
782 if (to_vmx(vcpu)->rmode.vm86_active)
784 if (!vmx_need_pf_intercept(vcpu))
785 eb &= ~(1u << PF_VECTOR);
787 /* When we are running a nested L2 guest and L1 specified for it a
788 * certain exception bitmap, we must trap the same exceptions and pass
789 * them to L1. When running L2, we will only handle the exceptions
790 * specified above if L1 did not want them.
792 if (is_guest_mode(vcpu))
793 eb |= get_vmcs12(vcpu)->exception_bitmap;
795 vmcs_write32(EXCEPTION_BITMAP, eb);
799 * Check if MSR is intercepted for currently loaded MSR bitmap.
801 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
803 unsigned long *msr_bitmap;
804 int f = sizeof(unsigned long);
806 if (!cpu_has_vmx_msr_bitmap())
809 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
812 return !!test_bit(msr, msr_bitmap + 0x800 / f);
813 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
815 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
821 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
822 unsigned long entry, unsigned long exit)
824 vm_entry_controls_clearbit(vmx, entry);
825 vm_exit_controls_clearbit(vmx, exit);
828 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
832 for (i = 0; i < m->nr; ++i) {
833 if (m->val[i].index == msr)
839 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
842 struct msr_autoload *m = &vmx->msr_autoload;
846 if (cpu_has_load_ia32_efer()) {
847 clear_atomic_switch_msr_special(vmx,
848 VM_ENTRY_LOAD_IA32_EFER,
849 VM_EXIT_LOAD_IA32_EFER);
853 case MSR_CORE_PERF_GLOBAL_CTRL:
854 if (cpu_has_load_perf_global_ctrl()) {
855 clear_atomic_switch_msr_special(vmx,
856 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
857 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
862 i = vmx_find_msr_index(&m->guest, msr);
866 m->guest.val[i] = m->guest.val[m->guest.nr];
867 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
870 i = vmx_find_msr_index(&m->host, msr);
875 m->host.val[i] = m->host.val[m->host.nr];
876 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
879 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
880 unsigned long entry, unsigned long exit,
881 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
882 u64 guest_val, u64 host_val)
884 vmcs_write64(guest_val_vmcs, guest_val);
885 if (host_val_vmcs != HOST_IA32_EFER)
886 vmcs_write64(host_val_vmcs, host_val);
887 vm_entry_controls_setbit(vmx, entry);
888 vm_exit_controls_setbit(vmx, exit);
891 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
892 u64 guest_val, u64 host_val, bool entry_only)
895 struct msr_autoload *m = &vmx->msr_autoload;
899 if (cpu_has_load_ia32_efer()) {
900 add_atomic_switch_msr_special(vmx,
901 VM_ENTRY_LOAD_IA32_EFER,
902 VM_EXIT_LOAD_IA32_EFER,
905 guest_val, host_val);
909 case MSR_CORE_PERF_GLOBAL_CTRL:
910 if (cpu_has_load_perf_global_ctrl()) {
911 add_atomic_switch_msr_special(vmx,
912 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
913 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
914 GUEST_IA32_PERF_GLOBAL_CTRL,
915 HOST_IA32_PERF_GLOBAL_CTRL,
916 guest_val, host_val);
920 case MSR_IA32_PEBS_ENABLE:
921 /* PEBS needs a quiescent period after being disabled (to write
922 * a record). Disabling PEBS through VMX MSR swapping doesn't
923 * provide that period, so a CPU could write host's record into
926 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
929 i = vmx_find_msr_index(&m->guest, msr);
931 j = vmx_find_msr_index(&m->host, msr);
933 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
934 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) {
935 printk_once(KERN_WARNING "Not enough msr switch entries. "
936 "Can't add msr %x\n", msr);
941 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
943 m->guest.val[i].index = msr;
944 m->guest.val[i].value = guest_val;
951 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
953 m->host.val[j].index = msr;
954 m->host.val[j].value = host_val;
957 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
959 u64 guest_efer = vmx->vcpu.arch.efer;
962 /* Shadow paging assumes NX to be available. */
964 guest_efer |= EFER_NX;
967 * LMA and LME handled by hardware; SCE meaningless outside long mode.
969 ignore_bits |= EFER_SCE;
971 ignore_bits |= EFER_LMA | EFER_LME;
972 /* SCE is meaningful only in long mode on Intel */
973 if (guest_efer & EFER_LMA)
974 ignore_bits &= ~(u64)EFER_SCE;
978 * On EPT, we can't emulate NX, so we must switch EFER atomically.
979 * On CPUs that support "load IA32_EFER", always switch EFER
980 * atomically, since it's faster than switching it manually.
982 if (cpu_has_load_ia32_efer() ||
983 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
984 if (!(guest_efer & EFER_LMA))
985 guest_efer &= ~EFER_LME;
986 if (guest_efer != host_efer)
987 add_atomic_switch_msr(vmx, MSR_EFER,
988 guest_efer, host_efer, false);
990 clear_atomic_switch_msr(vmx, MSR_EFER);
993 clear_atomic_switch_msr(vmx, MSR_EFER);
995 guest_efer &= ~ignore_bits;
996 guest_efer |= host_efer & ignore_bits;
998 vmx->guest_msrs[efer_offset].data = guest_efer;
999 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1005 #ifdef CONFIG_X86_32
1007 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1008 * VMCS rather than the segment table. KVM uses this helper to figure
1009 * out the current bases to poke them into the VMCS before entry.
1011 static unsigned long segment_base(u16 selector)
1013 struct desc_struct *table;
1016 if (!(selector & ~SEGMENT_RPL_MASK))
1019 table = get_current_gdt_ro();
1021 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1022 u16 ldt_selector = kvm_read_ldt();
1024 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1027 table = (struct desc_struct *)segment_base(ldt_selector);
1029 v = get_desc_base(&table[selector >> 3]);
1034 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1036 return vmx_pt_mode_is_host_guest() &&
1037 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1040 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1044 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1045 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1046 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1047 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1048 for (i = 0; i < addr_range; i++) {
1049 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1050 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1054 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1058 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1059 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1060 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1061 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1062 for (i = 0; i < addr_range; i++) {
1063 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1064 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1068 static void pt_guest_enter(struct vcpu_vmx *vmx)
1070 if (vmx_pt_mode_is_system())
1074 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1075 * Save host state before VM entry.
1077 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1078 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1079 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1080 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1081 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1085 static void pt_guest_exit(struct vcpu_vmx *vmx)
1087 if (vmx_pt_mode_is_system())
1090 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1091 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1092 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1095 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1096 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1099 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1100 unsigned long fs_base, unsigned long gs_base)
1102 if (unlikely(fs_sel != host->fs_sel)) {
1104 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1106 vmcs_write16(HOST_FS_SELECTOR, 0);
1107 host->fs_sel = fs_sel;
1109 if (unlikely(gs_sel != host->gs_sel)) {
1111 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1113 vmcs_write16(HOST_GS_SELECTOR, 0);
1114 host->gs_sel = gs_sel;
1116 if (unlikely(fs_base != host->fs_base)) {
1117 vmcs_writel(HOST_FS_BASE, fs_base);
1118 host->fs_base = fs_base;
1120 if (unlikely(gs_base != host->gs_base)) {
1121 vmcs_writel(HOST_GS_BASE, gs_base);
1122 host->gs_base = gs_base;
1126 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1128 struct vcpu_vmx *vmx = to_vmx(vcpu);
1129 struct vmcs_host_state *host_state;
1130 #ifdef CONFIG_X86_64
1131 int cpu = raw_smp_processor_id();
1133 unsigned long fs_base, gs_base;
1137 vmx->req_immediate_exit = false;
1140 * Note that guest MSRs to be saved/restored can also be changed
1141 * when guest state is loaded. This happens when guest transitions
1142 * to/from long-mode by setting MSR_EFER.LMA.
1144 if (!vmx->guest_msrs_ready) {
1145 vmx->guest_msrs_ready = true;
1146 for (i = 0; i < vmx->save_nmsrs; ++i)
1147 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1148 vmx->guest_msrs[i].data,
1149 vmx->guest_msrs[i].mask);
1153 if (vmx->nested.need_vmcs12_to_shadow_sync)
1154 nested_sync_vmcs12_to_shadow(vcpu);
1156 if (vmx->guest_state_loaded)
1159 host_state = &vmx->loaded_vmcs->host_state;
1162 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1163 * allow segment selectors with cpl > 0 or ti == 1.
1165 host_state->ldt_sel = kvm_read_ldt();
1167 #ifdef CONFIG_X86_64
1168 savesegment(ds, host_state->ds_sel);
1169 savesegment(es, host_state->es_sel);
1171 gs_base = cpu_kernelmode_gs_base(cpu);
1172 if (likely(is_64bit_mm(current->mm))) {
1173 current_save_fsgs();
1174 fs_sel = current->thread.fsindex;
1175 gs_sel = current->thread.gsindex;
1176 fs_base = current->thread.fsbase;
1177 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1179 savesegment(fs, fs_sel);
1180 savesegment(gs, gs_sel);
1181 fs_base = read_msr(MSR_FS_BASE);
1182 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1185 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1187 savesegment(fs, fs_sel);
1188 savesegment(gs, gs_sel);
1189 fs_base = segment_base(fs_sel);
1190 gs_base = segment_base(gs_sel);
1193 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1194 vmx->guest_state_loaded = true;
1197 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1199 struct vmcs_host_state *host_state;
1201 if (!vmx->guest_state_loaded)
1204 host_state = &vmx->loaded_vmcs->host_state;
1206 ++vmx->vcpu.stat.host_state_reload;
1208 #ifdef CONFIG_X86_64
1209 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1211 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1212 kvm_load_ldt(host_state->ldt_sel);
1213 #ifdef CONFIG_X86_64
1214 load_gs_index(host_state->gs_sel);
1216 loadsegment(gs, host_state->gs_sel);
1219 if (host_state->fs_sel & 7)
1220 loadsegment(fs, host_state->fs_sel);
1221 #ifdef CONFIG_X86_64
1222 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1223 loadsegment(ds, host_state->ds_sel);
1224 loadsegment(es, host_state->es_sel);
1227 invalidate_tss_limit();
1228 #ifdef CONFIG_X86_64
1229 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1231 load_fixmap_gdt(raw_smp_processor_id());
1232 vmx->guest_state_loaded = false;
1233 vmx->guest_msrs_ready = false;
1236 #ifdef CONFIG_X86_64
1237 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1240 if (vmx->guest_state_loaded)
1241 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1243 return vmx->msr_guest_kernel_gs_base;
1246 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1249 if (vmx->guest_state_loaded)
1250 wrmsrl(MSR_KERNEL_GS_BASE, data);
1252 vmx->msr_guest_kernel_gs_base = data;
1256 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1258 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1259 struct pi_desc old, new;
1263 * In case of hot-plug or hot-unplug, we may have to undo
1264 * vmx_vcpu_pi_put even if there is no assigned device. And we
1265 * always keep PI.NDST up to date for simplicity: it makes the
1266 * code easier, and CPU migration is not a fast path.
1268 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1272 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1273 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1274 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1275 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1278 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1279 pi_clear_sn(pi_desc);
1280 goto after_clear_sn;
1283 /* The full case. */
1285 old.control = new.control = pi_desc->control;
1287 dest = cpu_physical_id(cpu);
1289 if (x2apic_enabled())
1292 new.ndst = (dest << 8) & 0xFF00;
1295 } while (cmpxchg64(&pi_desc->control, old.control,
1296 new.control) != old.control);
1301 * Clear SN before reading the bitmap. The VT-d firmware
1302 * writes the bitmap and reads SN atomically (5.2.3 in the
1303 * spec), so it doesn't really have a memory barrier that
1304 * pairs with this, but we cannot do that and we need one.
1306 smp_mb__after_atomic();
1308 if (!pi_is_pir_empty(pi_desc))
1312 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1313 struct loaded_vmcs *buddy)
1315 struct vcpu_vmx *vmx = to_vmx(vcpu);
1316 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1319 if (!already_loaded) {
1320 loaded_vmcs_clear(vmx->loaded_vmcs);
1321 local_irq_disable();
1324 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1325 * this cpu's percpu list, otherwise it may not yet be deleted
1326 * from its previous cpu's percpu list. Pairs with the
1327 * smb_wmb() in __loaded_vmcs_clear().
1331 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1332 &per_cpu(loaded_vmcss_on_cpu, cpu));
1336 prev = per_cpu(current_vmcs, cpu);
1337 if (prev != vmx->loaded_vmcs->vmcs) {
1338 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1339 vmcs_load(vmx->loaded_vmcs->vmcs);
1342 * No indirect branch prediction barrier needed when switching
1343 * the active VMCS within a guest, e.g. on nested VM-Enter.
1344 * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1346 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1347 indirect_branch_prediction_barrier();
1350 if (!already_loaded) {
1351 void *gdt = get_current_gdt_ro();
1352 unsigned long sysenter_esp;
1355 * Flush all EPTP/VPID contexts, the new pCPU may have stale
1356 * TLB entries from its previous association with the vCPU.
1358 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1361 * Linux uses per-cpu TSS and GDT, so set these when switching
1362 * processors. See 22.2.4.
1364 vmcs_writel(HOST_TR_BASE,
1365 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1366 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1368 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1369 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1371 vmx->loaded_vmcs->cpu = cpu;
1374 /* Setup TSC multiplier */
1375 if (kvm_has_tsc_control &&
1376 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1377 decache_tsc_multiplier(vmx);
1381 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1382 * vcpu mutex is already taken.
1384 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1386 struct vcpu_vmx *vmx = to_vmx(vcpu);
1388 vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1390 vmx_vcpu_pi_load(vcpu, cpu);
1392 vmx->host_debugctlmsr = get_debugctlmsr();
1395 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1397 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1399 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1400 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1401 !kvm_vcpu_apicv_active(vcpu))
1404 /* Set SN when the vCPU is preempted */
1405 if (vcpu->preempted)
1409 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1411 vmx_vcpu_pi_put(vcpu);
1413 vmx_prepare_switch_to_host(to_vmx(vcpu));
1416 static bool emulation_required(struct kvm_vcpu *vcpu)
1418 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1421 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1423 struct vcpu_vmx *vmx = to_vmx(vcpu);
1424 unsigned long rflags, save_rflags;
1426 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1427 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1428 rflags = vmcs_readl(GUEST_RFLAGS);
1429 if (vmx->rmode.vm86_active) {
1430 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1431 save_rflags = vmx->rmode.save_rflags;
1432 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1434 vmx->rflags = rflags;
1439 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1441 struct vcpu_vmx *vmx = to_vmx(vcpu);
1442 unsigned long old_rflags;
1444 if (is_unrestricted_guest(vcpu)) {
1445 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1446 vmx->rflags = rflags;
1447 vmcs_writel(GUEST_RFLAGS, rflags);
1451 old_rflags = vmx_get_rflags(vcpu);
1452 vmx->rflags = rflags;
1453 if (vmx->rmode.vm86_active) {
1454 vmx->rmode.save_rflags = rflags;
1455 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1457 vmcs_writel(GUEST_RFLAGS, rflags);
1459 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1460 vmx->emulation_required = emulation_required(vcpu);
1463 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1465 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1468 if (interruptibility & GUEST_INTR_STATE_STI)
1469 ret |= KVM_X86_SHADOW_INT_STI;
1470 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1471 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1476 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1478 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1479 u32 interruptibility = interruptibility_old;
1481 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1483 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1484 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1485 else if (mask & KVM_X86_SHADOW_INT_STI)
1486 interruptibility |= GUEST_INTR_STATE_STI;
1488 if ((interruptibility != interruptibility_old))
1489 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1492 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1494 struct vcpu_vmx *vmx = to_vmx(vcpu);
1495 unsigned long value;
1498 * Any MSR write that attempts to change bits marked reserved will
1501 if (data & vmx->pt_desc.ctl_bitmask)
1505 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1506 * result in a #GP unless the same write also clears TraceEn.
1508 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1509 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1513 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1514 * and FabricEn would cause #GP, if
1515 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1517 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1518 !(data & RTIT_CTL_FABRIC_EN) &&
1519 !intel_pt_validate_cap(vmx->pt_desc.caps,
1520 PT_CAP_single_range_output))
1524 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1525 * utilize encodings marked reserved will casue a #GP fault.
1527 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1528 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1529 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1530 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1532 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1533 PT_CAP_cycle_thresholds);
1534 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1535 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1536 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1538 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1539 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1540 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1541 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1545 * If ADDRx_CFG is reserved or the encodings is >2 will
1546 * cause a #GP fault.
1548 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1549 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1551 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1552 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1554 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1555 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1557 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1558 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1564 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
1569 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1571 unsigned long rip, orig_rip;
1574 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1575 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1576 * set when EPT misconfig occurs. In practice, real hardware updates
1577 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1578 * (namely Hyper-V) don't set it due to it being undefined behavior,
1579 * i.e. we end up advancing IP with some random value.
1581 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1582 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1583 orig_rip = kvm_rip_read(vcpu);
1584 rip = orig_rip + vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1585 #ifdef CONFIG_X86_64
1587 * We need to mask out the high 32 bits of RIP if not in 64-bit
1588 * mode, but just finding out that we are in 64-bit mode is
1589 * quite expensive. Only do it if there was a carry.
1591 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1594 kvm_rip_write(vcpu, rip);
1596 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1600 /* skipping an emulated instruction also counts */
1601 vmx_set_interrupt_shadow(vcpu, 0);
1607 * Recognizes a pending MTF VM-exit and records the nested state for later
1610 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1612 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1613 struct vcpu_vmx *vmx = to_vmx(vcpu);
1615 if (!is_guest_mode(vcpu))
1619 * Per the SDM, MTF takes priority over debug-trap exceptions besides
1620 * T-bit traps. As instruction emulation is completed (i.e. at the
1621 * instruction boundary), any #DB exception pending delivery must be a
1622 * debug-trap. Record the pending MTF state to be delivered in
1623 * vmx_check_nested_events().
1625 if (nested_cpu_has_mtf(vmcs12) &&
1626 (!vcpu->arch.exception.pending ||
1627 vcpu->arch.exception.nr == DB_VECTOR))
1628 vmx->nested.mtf_pending = true;
1630 vmx->nested.mtf_pending = false;
1633 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1635 vmx_update_emulated_instruction(vcpu);
1636 return skip_emulated_instruction(vcpu);
1639 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1642 * Ensure that we clear the HLT state in the VMCS. We don't need to
1643 * explicitly skip the instruction because if the HLT state is set,
1644 * then the instruction is already executing and RIP has already been
1647 if (kvm_hlt_in_guest(vcpu->kvm) &&
1648 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1649 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1652 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1654 struct vcpu_vmx *vmx = to_vmx(vcpu);
1655 unsigned nr = vcpu->arch.exception.nr;
1656 bool has_error_code = vcpu->arch.exception.has_error_code;
1657 u32 error_code = vcpu->arch.exception.error_code;
1658 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1660 kvm_deliver_exception_payload(vcpu);
1662 if (has_error_code) {
1663 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1664 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1667 if (vmx->rmode.vm86_active) {
1669 if (kvm_exception_is_soft(nr))
1670 inc_eip = vcpu->arch.event_exit_inst_len;
1671 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1675 WARN_ON_ONCE(vmx->emulation_required);
1677 if (kvm_exception_is_soft(nr)) {
1678 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1679 vmx->vcpu.arch.event_exit_inst_len);
1680 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1682 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1684 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1686 vmx_clear_hlt(vcpu);
1690 * Swap MSR entry in host/guest MSR entry array.
1692 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1694 struct shared_msr_entry tmp;
1696 tmp = vmx->guest_msrs[to];
1697 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1698 vmx->guest_msrs[from] = tmp;
1702 * Set up the vmcs to automatically save and restore system
1703 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1704 * mode, as fiddling with msrs is very expensive.
1706 static void setup_msrs(struct vcpu_vmx *vmx)
1708 int save_nmsrs, index;
1711 #ifdef CONFIG_X86_64
1713 * The SYSCALL MSRs are only needed on long mode guests, and only
1714 * when EFER.SCE is set.
1716 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1717 index = __find_msr_index(vmx, MSR_STAR);
1719 move_msr_up(vmx, index, save_nmsrs++);
1720 index = __find_msr_index(vmx, MSR_LSTAR);
1722 move_msr_up(vmx, index, save_nmsrs++);
1723 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1725 move_msr_up(vmx, index, save_nmsrs++);
1728 index = __find_msr_index(vmx, MSR_EFER);
1729 if (index >= 0 && update_transition_efer(vmx, index))
1730 move_msr_up(vmx, index, save_nmsrs++);
1731 index = __find_msr_index(vmx, MSR_TSC_AUX);
1732 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1733 move_msr_up(vmx, index, save_nmsrs++);
1734 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1736 move_msr_up(vmx, index, save_nmsrs++);
1738 vmx->save_nmsrs = save_nmsrs;
1739 vmx->guest_msrs_ready = false;
1741 if (cpu_has_vmx_msr_bitmap())
1742 vmx_update_msr_bitmap(&vmx->vcpu);
1745 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1747 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1748 u64 g_tsc_offset = 0;
1751 * We're here if L1 chose not to trap WRMSR to TSC. According
1752 * to the spec, this should set L1's TSC; The offset that L1
1753 * set for L2 remains unchanged, and still needs to be added
1754 * to the newly set TSC to get L2's TSC.
1756 if (is_guest_mode(vcpu) &&
1757 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1758 g_tsc_offset = vmcs12->tsc_offset;
1760 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1761 vcpu->arch.tsc_offset - g_tsc_offset,
1763 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1764 return offset + g_tsc_offset;
1768 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1769 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1770 * all guests if the "nested" module option is off, and can also be disabled
1771 * for a single guest by disabling its VMX cpuid bit.
1773 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1775 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1778 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1781 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1783 return !(val & ~valid_bits);
1786 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1788 switch (msr->index) {
1789 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1792 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1793 case MSR_IA32_PERF_CAPABILITIES:
1794 msr->data = vmx_get_perf_capabilities();
1797 return KVM_MSR_RET_INVALID;
1802 * Reads an msr value (of 'msr_index') into 'pdata'.
1803 * Returns 0 on success, non-0 otherwise.
1804 * Assumes vcpu_load() was already called.
1806 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1808 struct vcpu_vmx *vmx = to_vmx(vcpu);
1809 struct shared_msr_entry *msr;
1812 switch (msr_info->index) {
1813 #ifdef CONFIG_X86_64
1815 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1818 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1820 case MSR_KERNEL_GS_BASE:
1821 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1825 return kvm_get_msr_common(vcpu, msr_info);
1826 case MSR_IA32_TSX_CTRL:
1827 if (!msr_info->host_initiated &&
1828 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1830 goto find_shared_msr;
1831 case MSR_IA32_UMWAIT_CONTROL:
1832 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1835 msr_info->data = vmx->msr_ia32_umwait_control;
1837 case MSR_IA32_SPEC_CTRL:
1838 if (!msr_info->host_initiated &&
1839 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1842 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1844 case MSR_IA32_SYSENTER_CS:
1845 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1847 case MSR_IA32_SYSENTER_EIP:
1848 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1850 case MSR_IA32_SYSENTER_ESP:
1851 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1853 case MSR_IA32_BNDCFGS:
1854 if (!kvm_mpx_supported() ||
1855 (!msr_info->host_initiated &&
1856 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1858 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1860 case MSR_IA32_MCG_EXT_CTL:
1861 if (!msr_info->host_initiated &&
1862 !(vmx->msr_ia32_feature_control &
1863 FEAT_CTL_LMCE_ENABLED))
1865 msr_info->data = vcpu->arch.mcg_ext_ctl;
1867 case MSR_IA32_FEAT_CTL:
1868 msr_info->data = vmx->msr_ia32_feature_control;
1870 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1871 if (!nested_vmx_allowed(vcpu))
1873 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1877 * Enlightened VMCS v1 doesn't have certain fields, but buggy
1878 * Hyper-V versions are still trying to use corresponding
1879 * features when they are exposed. Filter out the essential
1882 if (!msr_info->host_initiated &&
1883 vmx->nested.enlightened_vmcs_enabled)
1884 nested_evmcs_filter_control_msr(msr_info->index,
1887 case MSR_IA32_RTIT_CTL:
1888 if (!vmx_pt_mode_is_host_guest())
1890 msr_info->data = vmx->pt_desc.guest.ctl;
1892 case MSR_IA32_RTIT_STATUS:
1893 if (!vmx_pt_mode_is_host_guest())
1895 msr_info->data = vmx->pt_desc.guest.status;
1897 case MSR_IA32_RTIT_CR3_MATCH:
1898 if (!vmx_pt_mode_is_host_guest() ||
1899 !intel_pt_validate_cap(vmx->pt_desc.caps,
1900 PT_CAP_cr3_filtering))
1902 msr_info->data = vmx->pt_desc.guest.cr3_match;
1904 case MSR_IA32_RTIT_OUTPUT_BASE:
1905 if (!vmx_pt_mode_is_host_guest() ||
1906 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1907 PT_CAP_topa_output) &&
1908 !intel_pt_validate_cap(vmx->pt_desc.caps,
1909 PT_CAP_single_range_output)))
1911 msr_info->data = vmx->pt_desc.guest.output_base;
1913 case MSR_IA32_RTIT_OUTPUT_MASK:
1914 if (!vmx_pt_mode_is_host_guest() ||
1915 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1916 PT_CAP_topa_output) &&
1917 !intel_pt_validate_cap(vmx->pt_desc.caps,
1918 PT_CAP_single_range_output)))
1920 msr_info->data = vmx->pt_desc.guest.output_mask;
1922 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1923 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1924 if (!vmx_pt_mode_is_host_guest() ||
1925 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1926 PT_CAP_num_address_ranges)))
1929 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1931 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1934 if (!msr_info->host_initiated &&
1935 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1937 goto find_shared_msr;
1940 msr = find_msr_entry(vmx, msr_info->index);
1942 msr_info->data = msr->data;
1945 return kvm_get_msr_common(vcpu, msr_info);
1951 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1954 #ifdef CONFIG_X86_64
1955 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1958 return (unsigned long)data;
1962 * Writes msr value into the appropriate "register".
1963 * Returns 0 on success, non-0 otherwise.
1964 * Assumes vcpu_load() was already called.
1966 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1968 struct vcpu_vmx *vmx = to_vmx(vcpu);
1969 struct shared_msr_entry *msr;
1971 u32 msr_index = msr_info->index;
1972 u64 data = msr_info->data;
1975 switch (msr_index) {
1977 ret = kvm_set_msr_common(vcpu, msr_info);
1979 #ifdef CONFIG_X86_64
1981 vmx_segment_cache_clear(vmx);
1982 vmcs_writel(GUEST_FS_BASE, data);
1985 vmx_segment_cache_clear(vmx);
1986 vmcs_writel(GUEST_GS_BASE, data);
1988 case MSR_KERNEL_GS_BASE:
1989 vmx_write_guest_kernel_gs_base(vmx, data);
1992 case MSR_IA32_SYSENTER_CS:
1993 if (is_guest_mode(vcpu))
1994 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1995 vmcs_write32(GUEST_SYSENTER_CS, data);
1997 case MSR_IA32_SYSENTER_EIP:
1998 if (is_guest_mode(vcpu)) {
1999 data = nested_vmx_truncate_sysenter_addr(vcpu, data);
2000 get_vmcs12(vcpu)->guest_sysenter_eip = data;
2002 vmcs_writel(GUEST_SYSENTER_EIP, data);
2004 case MSR_IA32_SYSENTER_ESP:
2005 if (is_guest_mode(vcpu)) {
2006 data = nested_vmx_truncate_sysenter_addr(vcpu, data);
2007 get_vmcs12(vcpu)->guest_sysenter_esp = data;
2009 vmcs_writel(GUEST_SYSENTER_ESP, data);
2011 case MSR_IA32_DEBUGCTLMSR:
2012 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
2013 VM_EXIT_SAVE_DEBUG_CONTROLS)
2014 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2016 ret = kvm_set_msr_common(vcpu, msr_info);
2019 case MSR_IA32_BNDCFGS:
2020 if (!kvm_mpx_supported() ||
2021 (!msr_info->host_initiated &&
2022 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2024 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2025 (data & MSR_IA32_BNDCFGS_RSVD))
2027 vmcs_write64(GUEST_BNDCFGS, data);
2029 case MSR_IA32_UMWAIT_CONTROL:
2030 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2033 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2034 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2037 vmx->msr_ia32_umwait_control = data;
2039 case MSR_IA32_SPEC_CTRL:
2040 if (!msr_info->host_initiated &&
2041 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2044 if (kvm_spec_ctrl_test_value(data))
2047 vmx->spec_ctrl = data;
2053 * When it's written (to non-zero) for the first time, pass
2057 * The handling of the MSR bitmap for L2 guests is done in
2058 * nested_vmx_prepare_msr_bitmap. We should not touch the
2059 * vmcs02.msr_bitmap here since it gets completely overwritten
2060 * in the merging. We update the vmcs01 here for L1 as well
2061 * since it will end up touching the MSR anyway now.
2063 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2067 case MSR_IA32_TSX_CTRL:
2068 if (!msr_info->host_initiated &&
2069 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2071 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2073 goto find_shared_msr;
2074 case MSR_IA32_PRED_CMD:
2075 if (!msr_info->host_initiated &&
2076 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2079 if (data & ~PRED_CMD_IBPB)
2081 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2086 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2090 * When it's written (to non-zero) for the first time, pass
2094 * The handling of the MSR bitmap for L2 guests is done in
2095 * nested_vmx_prepare_msr_bitmap. We should not touch the
2096 * vmcs02.msr_bitmap here since it gets completely overwritten
2099 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2102 case MSR_IA32_CR_PAT:
2103 if (!kvm_pat_valid(data))
2106 if (is_guest_mode(vcpu) &&
2107 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2108 get_vmcs12(vcpu)->guest_ia32_pat = data;
2110 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2111 vmcs_write64(GUEST_IA32_PAT, data);
2112 vcpu->arch.pat = data;
2115 ret = kvm_set_msr_common(vcpu, msr_info);
2117 case MSR_IA32_TSC_ADJUST:
2118 ret = kvm_set_msr_common(vcpu, msr_info);
2120 case MSR_IA32_MCG_EXT_CTL:
2121 if ((!msr_info->host_initiated &&
2122 !(to_vmx(vcpu)->msr_ia32_feature_control &
2123 FEAT_CTL_LMCE_ENABLED)) ||
2124 (data & ~MCG_EXT_CTL_LMCE_EN))
2126 vcpu->arch.mcg_ext_ctl = data;
2128 case MSR_IA32_FEAT_CTL:
2129 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2130 (to_vmx(vcpu)->msr_ia32_feature_control &
2131 FEAT_CTL_LOCKED && !msr_info->host_initiated))
2133 vmx->msr_ia32_feature_control = data;
2134 if (msr_info->host_initiated && data == 0)
2135 vmx_leave_nested(vcpu);
2137 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2138 if (!msr_info->host_initiated)
2139 return 1; /* they are read-only */
2140 if (!nested_vmx_allowed(vcpu))
2142 return vmx_set_vmx_msr(vcpu, msr_index, data);
2143 case MSR_IA32_RTIT_CTL:
2144 if (!vmx_pt_mode_is_host_guest() ||
2145 vmx_rtit_ctl_check(vcpu, data) ||
2148 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2149 vmx->pt_desc.guest.ctl = data;
2150 pt_update_intercept_for_msr(vmx);
2152 case MSR_IA32_RTIT_STATUS:
2153 if (!pt_can_write_msr(vmx))
2155 if (data & MSR_IA32_RTIT_STATUS_MASK)
2157 vmx->pt_desc.guest.status = data;
2159 case MSR_IA32_RTIT_CR3_MATCH:
2160 if (!pt_can_write_msr(vmx))
2162 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2163 PT_CAP_cr3_filtering))
2165 vmx->pt_desc.guest.cr3_match = data;
2167 case MSR_IA32_RTIT_OUTPUT_BASE:
2168 if (!pt_can_write_msr(vmx))
2170 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2171 PT_CAP_topa_output) &&
2172 !intel_pt_validate_cap(vmx->pt_desc.caps,
2173 PT_CAP_single_range_output))
2175 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
2177 vmx->pt_desc.guest.output_base = data;
2179 case MSR_IA32_RTIT_OUTPUT_MASK:
2180 if (!pt_can_write_msr(vmx))
2182 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2183 PT_CAP_topa_output) &&
2184 !intel_pt_validate_cap(vmx->pt_desc.caps,
2185 PT_CAP_single_range_output))
2187 vmx->pt_desc.guest.output_mask = data;
2189 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2190 if (!pt_can_write_msr(vmx))
2192 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2193 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2194 PT_CAP_num_address_ranges))
2196 if (is_noncanonical_address(data, vcpu))
2199 vmx->pt_desc.guest.addr_b[index / 2] = data;
2201 vmx->pt_desc.guest.addr_a[index / 2] = data;
2204 if (!msr_info->host_initiated &&
2205 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2207 /* Check reserved bit, higher 32 bits should be zero */
2208 if ((data >> 32) != 0)
2210 goto find_shared_msr;
2214 msr = find_msr_entry(vmx, msr_index);
2216 ret = vmx_set_guest_msr(vmx, msr, data);
2218 ret = kvm_set_msr_common(vcpu, msr_info);
2224 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2226 unsigned long guest_owned_bits;
2228 kvm_register_mark_available(vcpu, reg);
2232 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2235 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2237 case VCPU_EXREG_PDPTR:
2239 ept_save_pdptrs(vcpu);
2241 case VCPU_EXREG_CR0:
2242 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2244 vcpu->arch.cr0 &= ~guest_owned_bits;
2245 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2247 case VCPU_EXREG_CR3:
2248 if (is_unrestricted_guest(vcpu) ||
2249 (enable_ept && is_paging(vcpu)))
2250 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2252 case VCPU_EXREG_CR4:
2253 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2255 vcpu->arch.cr4 &= ~guest_owned_bits;
2256 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2264 static __init int cpu_has_kvm_support(void)
2266 return cpu_has_vmx();
2269 static __init int vmx_disabled_by_bios(void)
2271 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2272 !boot_cpu_has(X86_FEATURE_VMX);
2275 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2279 cr4_set_bits(X86_CR4_VMXE);
2280 intel_pt_handle_vmx(1);
2282 asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2283 _ASM_EXTABLE(1b, %l[fault])
2284 : : [vmxon_pointer] "m"(vmxon_pointer)
2289 WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2290 rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2291 intel_pt_handle_vmx(0);
2292 cr4_clear_bits(X86_CR4_VMXE);
2297 static int hardware_enable(void)
2299 int cpu = raw_smp_processor_id();
2300 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2303 if (cr4_read_shadow() & X86_CR4_VMXE)
2307 * This can happen if we hot-added a CPU but failed to allocate
2308 * VP assist page for it.
2310 if (static_branch_unlikely(&enable_evmcs) &&
2311 !hv_get_vp_assist_page(cpu))
2314 r = kvm_cpu_vmxon(phys_addr);
2324 static void vmclear_local_loaded_vmcss(void)
2326 int cpu = raw_smp_processor_id();
2327 struct loaded_vmcs *v, *n;
2329 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2330 loaded_vmcss_on_cpu_link)
2331 __loaded_vmcs_clear(v);
2335 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2338 static void kvm_cpu_vmxoff(void)
2340 asm volatile (__ex("vmxoff"));
2342 intel_pt_handle_vmx(0);
2343 cr4_clear_bits(X86_CR4_VMXE);
2346 static void hardware_disable(void)
2348 vmclear_local_loaded_vmcss();
2353 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2354 * directly instead of going through cpu_has(), to ensure KVM is trapping
2355 * ENCLS whenever it's supported in hardware. It does not matter whether
2356 * the host OS supports or has enabled SGX.
2358 static bool cpu_has_sgx(void)
2360 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2363 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2364 u32 msr, u32 *result)
2366 u32 vmx_msr_low, vmx_msr_high;
2367 u32 ctl = ctl_min | ctl_opt;
2369 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2371 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2372 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2374 /* Ensure minimum (required) set of control bits are supported. */
2382 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2383 struct vmx_capability *vmx_cap)
2385 u32 vmx_msr_low, vmx_msr_high;
2386 u32 min, opt, min2, opt2;
2387 u32 _pin_based_exec_control = 0;
2388 u32 _cpu_based_exec_control = 0;
2389 u32 _cpu_based_2nd_exec_control = 0;
2390 u32 _vmexit_control = 0;
2391 u32 _vmentry_control = 0;
2393 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2394 min = CPU_BASED_HLT_EXITING |
2395 #ifdef CONFIG_X86_64
2396 CPU_BASED_CR8_LOAD_EXITING |
2397 CPU_BASED_CR8_STORE_EXITING |
2399 CPU_BASED_CR3_LOAD_EXITING |
2400 CPU_BASED_CR3_STORE_EXITING |
2401 CPU_BASED_UNCOND_IO_EXITING |
2402 CPU_BASED_MOV_DR_EXITING |
2403 CPU_BASED_USE_TSC_OFFSETTING |
2404 CPU_BASED_MWAIT_EXITING |
2405 CPU_BASED_MONITOR_EXITING |
2406 CPU_BASED_INVLPG_EXITING |
2407 CPU_BASED_RDPMC_EXITING;
2409 opt = CPU_BASED_TPR_SHADOW |
2410 CPU_BASED_USE_MSR_BITMAPS |
2411 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2412 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2413 &_cpu_based_exec_control) < 0)
2415 #ifdef CONFIG_X86_64
2416 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2417 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2418 ~CPU_BASED_CR8_STORE_EXITING;
2420 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2422 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2423 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2424 SECONDARY_EXEC_WBINVD_EXITING |
2425 SECONDARY_EXEC_ENABLE_VPID |
2426 SECONDARY_EXEC_ENABLE_EPT |
2427 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2428 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2429 SECONDARY_EXEC_DESC |
2430 SECONDARY_EXEC_RDTSCP |
2431 SECONDARY_EXEC_ENABLE_INVPCID |
2432 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2433 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2434 SECONDARY_EXEC_SHADOW_VMCS |
2435 SECONDARY_EXEC_XSAVES |
2436 SECONDARY_EXEC_RDSEED_EXITING |
2437 SECONDARY_EXEC_RDRAND_EXITING |
2438 SECONDARY_EXEC_ENABLE_PML |
2439 SECONDARY_EXEC_TSC_SCALING |
2440 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2441 SECONDARY_EXEC_PT_USE_GPA |
2442 SECONDARY_EXEC_PT_CONCEAL_VMX |
2443 SECONDARY_EXEC_ENABLE_VMFUNC;
2445 opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2446 if (adjust_vmx_controls(min2, opt2,
2447 MSR_IA32_VMX_PROCBASED_CTLS2,
2448 &_cpu_based_2nd_exec_control) < 0)
2451 #ifndef CONFIG_X86_64
2452 if (!(_cpu_based_2nd_exec_control &
2453 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2454 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2457 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2458 _cpu_based_2nd_exec_control &= ~(
2459 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2460 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2461 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2463 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2464 &vmx_cap->ept, &vmx_cap->vpid);
2466 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2467 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2469 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2470 CPU_BASED_CR3_STORE_EXITING |
2471 CPU_BASED_INVLPG_EXITING);
2472 } else if (vmx_cap->ept) {
2474 pr_warn_once("EPT CAP should not exist if not support "
2475 "1-setting enable EPT VM-execution control\n");
2477 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2480 pr_warn_once("VPID CAP should not exist if not support "
2481 "1-setting enable VPID VM-execution control\n");
2484 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2485 #ifdef CONFIG_X86_64
2486 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2488 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2489 VM_EXIT_LOAD_IA32_PAT |
2490 VM_EXIT_LOAD_IA32_EFER |
2491 VM_EXIT_CLEAR_BNDCFGS |
2492 VM_EXIT_PT_CONCEAL_PIP |
2493 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2494 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2495 &_vmexit_control) < 0)
2498 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2499 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2500 PIN_BASED_VMX_PREEMPTION_TIMER;
2501 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2502 &_pin_based_exec_control) < 0)
2505 if (cpu_has_broken_vmx_preemption_timer())
2506 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2507 if (!(_cpu_based_2nd_exec_control &
2508 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2509 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2511 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2512 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2513 VM_ENTRY_LOAD_IA32_PAT |
2514 VM_ENTRY_LOAD_IA32_EFER |
2515 VM_ENTRY_LOAD_BNDCFGS |
2516 VM_ENTRY_PT_CONCEAL_PIP |
2517 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2518 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2519 &_vmentry_control) < 0)
2523 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2524 * can't be used due to an errata where VM Exit may incorrectly clear
2525 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2526 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2528 if (boot_cpu_data.x86 == 0x6) {
2529 switch (boot_cpu_data.x86_model) {
2530 case 26: /* AAK155 */
2531 case 30: /* AAP115 */
2532 case 37: /* AAT100 */
2533 case 44: /* BC86,AAY89,BD102 */
2535 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2536 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2537 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2538 "does not work properly. Using workaround\n");
2546 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2548 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2549 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2552 #ifdef CONFIG_X86_64
2553 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2554 if (vmx_msr_high & (1u<<16))
2558 /* Require Write-Back (WB) memory type for VMCS accesses. */
2559 if (((vmx_msr_high >> 18) & 15) != 6)
2562 vmcs_conf->size = vmx_msr_high & 0x1fff;
2563 vmcs_conf->order = get_order(vmcs_conf->size);
2564 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2566 vmcs_conf->revision_id = vmx_msr_low;
2568 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2569 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2570 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2571 vmcs_conf->vmexit_ctrl = _vmexit_control;
2572 vmcs_conf->vmentry_ctrl = _vmentry_control;
2574 if (static_branch_unlikely(&enable_evmcs))
2575 evmcs_sanitize_exec_ctrls(vmcs_conf);
2580 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2582 int node = cpu_to_node(cpu);
2586 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2589 vmcs = page_address(pages);
2590 memset(vmcs, 0, vmcs_config.size);
2592 /* KVM supports Enlightened VMCS v1 only */
2593 if (static_branch_unlikely(&enable_evmcs))
2594 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2596 vmcs->hdr.revision_id = vmcs_config.revision_id;
2599 vmcs->hdr.shadow_vmcs = 1;
2603 void free_vmcs(struct vmcs *vmcs)
2605 free_pages((unsigned long)vmcs, vmcs_config.order);
2609 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2611 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2613 if (!loaded_vmcs->vmcs)
2615 loaded_vmcs_clear(loaded_vmcs);
2616 free_vmcs(loaded_vmcs->vmcs);
2617 loaded_vmcs->vmcs = NULL;
2618 if (loaded_vmcs->msr_bitmap)
2619 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2620 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2623 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2625 loaded_vmcs->vmcs = alloc_vmcs(false);
2626 if (!loaded_vmcs->vmcs)
2629 vmcs_clear(loaded_vmcs->vmcs);
2631 loaded_vmcs->shadow_vmcs = NULL;
2632 loaded_vmcs->hv_timer_soft_disabled = false;
2633 loaded_vmcs->cpu = -1;
2634 loaded_vmcs->launched = 0;
2636 if (cpu_has_vmx_msr_bitmap()) {
2637 loaded_vmcs->msr_bitmap = (unsigned long *)
2638 __get_free_page(GFP_KERNEL_ACCOUNT);
2639 if (!loaded_vmcs->msr_bitmap)
2641 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2643 if (IS_ENABLED(CONFIG_HYPERV) &&
2644 static_branch_unlikely(&enable_evmcs) &&
2645 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2646 struct hv_enlightened_vmcs *evmcs =
2647 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2649 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2653 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2654 memset(&loaded_vmcs->controls_shadow, 0,
2655 sizeof(struct vmcs_controls_shadow));
2660 free_loaded_vmcs(loaded_vmcs);
2664 static void free_kvm_area(void)
2668 for_each_possible_cpu(cpu) {
2669 free_vmcs(per_cpu(vmxarea, cpu));
2670 per_cpu(vmxarea, cpu) = NULL;
2674 static __init int alloc_kvm_area(void)
2678 for_each_possible_cpu(cpu) {
2681 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2688 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2689 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2690 * revision_id reported by MSR_IA32_VMX_BASIC.
2692 * However, even though not explicitly documented by
2693 * TLFS, VMXArea passed as VMXON argument should
2694 * still be marked with revision_id reported by
2697 if (static_branch_unlikely(&enable_evmcs))
2698 vmcs->hdr.revision_id = vmcs_config.revision_id;
2700 per_cpu(vmxarea, cpu) = vmcs;
2705 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2706 struct kvm_segment *save)
2708 if (!emulate_invalid_guest_state) {
2710 * CS and SS RPL should be equal during guest entry according
2711 * to VMX spec, but in reality it is not always so. Since vcpu
2712 * is in the middle of the transition from real mode to
2713 * protected mode it is safe to assume that RPL 0 is a good
2716 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2717 save->selector &= ~SEGMENT_RPL_MASK;
2718 save->dpl = save->selector & SEGMENT_RPL_MASK;
2721 vmx_set_segment(vcpu, save, seg);
2724 static void enter_pmode(struct kvm_vcpu *vcpu)
2726 unsigned long flags;
2727 struct vcpu_vmx *vmx = to_vmx(vcpu);
2730 * Update real mode segment cache. It may be not up-to-date if sement
2731 * register was written while vcpu was in a guest mode.
2733 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2734 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2735 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2736 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2737 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2738 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2740 vmx->rmode.vm86_active = 0;
2742 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2744 flags = vmcs_readl(GUEST_RFLAGS);
2745 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2746 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2747 vmcs_writel(GUEST_RFLAGS, flags);
2749 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2750 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2752 update_exception_bitmap(vcpu);
2754 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2755 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2756 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2757 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2758 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2759 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2762 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2764 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2765 struct kvm_segment var = *save;
2768 if (seg == VCPU_SREG_CS)
2771 if (!emulate_invalid_guest_state) {
2772 var.selector = var.base >> 4;
2773 var.base = var.base & 0xffff0;
2783 if (save->base & 0xf)
2784 printk_once(KERN_WARNING "kvm: segment base is not "
2785 "paragraph aligned when entering "
2786 "protected mode (seg=%d)", seg);
2789 vmcs_write16(sf->selector, var.selector);
2790 vmcs_writel(sf->base, var.base);
2791 vmcs_write32(sf->limit, var.limit);
2792 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2795 static void enter_rmode(struct kvm_vcpu *vcpu)
2797 unsigned long flags;
2798 struct vcpu_vmx *vmx = to_vmx(vcpu);
2799 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2801 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2802 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2803 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2804 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2805 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2806 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2807 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2809 vmx->rmode.vm86_active = 1;
2812 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2813 * vcpu. Warn the user that an update is overdue.
2815 if (!kvm_vmx->tss_addr)
2816 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2817 "called before entering vcpu\n");
2819 vmx_segment_cache_clear(vmx);
2821 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2822 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2823 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2825 flags = vmcs_readl(GUEST_RFLAGS);
2826 vmx->rmode.save_rflags = flags;
2828 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2830 vmcs_writel(GUEST_RFLAGS, flags);
2831 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2832 update_exception_bitmap(vcpu);
2834 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2835 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2836 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2837 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2838 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2839 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2841 kvm_mmu_reset_context(vcpu);
2844 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2846 struct vcpu_vmx *vmx = to_vmx(vcpu);
2847 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2852 vcpu->arch.efer = efer;
2853 if (efer & EFER_LMA) {
2854 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2857 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2859 msr->data = efer & ~EFER_LME;
2864 #ifdef CONFIG_X86_64
2866 static void enter_lmode(struct kvm_vcpu *vcpu)
2870 vmx_segment_cache_clear(to_vmx(vcpu));
2872 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2873 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2874 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2876 vmcs_write32(GUEST_TR_AR_BYTES,
2877 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2878 | VMX_AR_TYPE_BUSY_64_TSS);
2880 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2883 static void exit_lmode(struct kvm_vcpu *vcpu)
2885 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2886 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2891 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2893 struct vcpu_vmx *vmx = to_vmx(vcpu);
2896 * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2897 * the CPU is not required to invalidate guest-physical mappings on
2898 * VM-Entry, even if VPID is disabled. Guest-physical mappings are
2899 * associated with the root EPT structure and not any particular VPID
2900 * (INVVPID also isn't required to invalidate guest-physical mappings).
2904 } else if (enable_vpid) {
2905 if (cpu_has_vmx_invvpid_global()) {
2906 vpid_sync_vcpu_global();
2908 vpid_sync_vcpu_single(vmx->vpid);
2909 vpid_sync_vcpu_single(vmx->nested.vpid02);
2914 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2916 struct kvm_mmu *mmu = vcpu->arch.mmu;
2917 u64 root_hpa = mmu->root_hpa;
2919 /* No flush required if the current context is invalid. */
2920 if (!VALID_PAGE(root_hpa))
2924 ept_sync_context(construct_eptp(vcpu, root_hpa,
2925 mmu->shadow_root_level));
2926 else if (!is_guest_mode(vcpu))
2927 vpid_sync_context(to_vmx(vcpu)->vpid);
2929 vpid_sync_context(nested_get_vpid02(vcpu));
2932 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2935 * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2936 * vmx_flush_tlb_guest() for an explanation of why this is ok.
2938 vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2941 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2944 * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2945 * or a vpid couldn't be allocated for this vCPU. VM-Enter and VM-Exit
2946 * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2947 * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2948 * i.e. no explicit INVVPID is necessary.
2950 vpid_sync_context(to_vmx(vcpu)->vpid);
2953 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2955 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2957 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2960 if (is_pae_paging(vcpu)) {
2961 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2962 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2963 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2964 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2968 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2970 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2972 if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2975 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2976 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2977 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2978 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2980 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2983 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2985 struct kvm_vcpu *vcpu)
2987 struct vcpu_vmx *vmx = to_vmx(vcpu);
2989 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2990 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2991 if (!(cr0 & X86_CR0_PG)) {
2992 /* From paging/starting to nonpaging */
2993 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2994 CPU_BASED_CR3_STORE_EXITING);
2995 vcpu->arch.cr0 = cr0;
2996 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2997 } else if (!is_paging(vcpu)) {
2998 /* From nonpaging to paging */
2999 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
3000 CPU_BASED_CR3_STORE_EXITING);
3001 vcpu->arch.cr0 = cr0;
3002 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3005 if (!(cr0 & X86_CR0_WP))
3006 *hw_cr0 &= ~X86_CR0_WP;
3009 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3011 struct vcpu_vmx *vmx = to_vmx(vcpu);
3012 unsigned long hw_cr0;
3014 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3015 if (is_unrestricted_guest(vcpu))
3016 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3018 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3020 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3023 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3027 #ifdef CONFIG_X86_64
3028 if (vcpu->arch.efer & EFER_LME) {
3029 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3031 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3036 if (enable_ept && !is_unrestricted_guest(vcpu))
3037 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3039 vmcs_writel(CR0_READ_SHADOW, cr0);
3040 vmcs_writel(GUEST_CR0, hw_cr0);
3041 vcpu->arch.cr0 = cr0;
3042 kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3044 /* depends on vcpu->arch.cr0 to be set to a new value */
3045 vmx->emulation_required = emulation_required(vcpu);
3048 static int vmx_get_max_tdp_level(void)
3050 if (cpu_has_vmx_ept_5levels())
3055 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa,
3058 u64 eptp = VMX_EPTP_MT_WB;
3060 eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3062 if (enable_ept_ad_bits &&
3063 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3064 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3065 eptp |= (root_hpa & PAGE_MASK);
3070 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long pgd,
3073 struct kvm *kvm = vcpu->kvm;
3074 bool update_guest_cr3 = true;
3075 unsigned long guest_cr3;
3079 eptp = construct_eptp(vcpu, pgd, pgd_level);
3080 vmcs_write64(EPT_POINTER, eptp);
3082 if (kvm_x86_ops.tlb_remote_flush) {
3083 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3084 to_vmx(vcpu)->ept_pointer = eptp;
3085 to_kvm_vmx(kvm)->ept_pointers_match
3086 = EPT_POINTERS_CHECK;
3087 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3090 if (!enable_unrestricted_guest && !is_paging(vcpu))
3091 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3092 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3093 guest_cr3 = vcpu->arch.cr3;
3094 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3095 update_guest_cr3 = false;
3096 vmx_ept_load_pdptrs(vcpu);
3101 if (update_guest_cr3)
3102 vmcs_writel(GUEST_CR3, guest_cr3);
3105 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3107 struct vcpu_vmx *vmx = to_vmx(vcpu);
3109 * Pass through host's Machine Check Enable value to hw_cr4, which
3110 * is in force while we are in guest mode. Do not let guests control
3111 * this bit, even if host CR4.MCE == 0.
3113 unsigned long hw_cr4;
3115 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3116 if (is_unrestricted_guest(vcpu))
3117 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3118 else if (vmx->rmode.vm86_active)
3119 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3121 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3123 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3124 if (cr4 & X86_CR4_UMIP) {
3125 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3126 hw_cr4 &= ~X86_CR4_UMIP;
3127 } else if (!is_guest_mode(vcpu) ||
3128 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3129 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3133 if (cr4 & X86_CR4_VMXE) {
3135 * To use VMXON (and later other VMX instructions), a guest
3136 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3137 * So basically the check on whether to allow nested VMX
3138 * is here. We operate under the default treatment of SMM,
3139 * so VMX cannot be enabled under SMM.
3141 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3145 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3148 vcpu->arch.cr4 = cr4;
3149 kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3151 if (!is_unrestricted_guest(vcpu)) {
3153 if (!is_paging(vcpu)) {
3154 hw_cr4 &= ~X86_CR4_PAE;
3155 hw_cr4 |= X86_CR4_PSE;
3156 } else if (!(cr4 & X86_CR4_PAE)) {
3157 hw_cr4 &= ~X86_CR4_PAE;
3162 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3163 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3164 * to be manually disabled when guest switches to non-paging
3167 * If !enable_unrestricted_guest, the CPU is always running
3168 * with CR0.PG=1 and CR4 needs to be modified.
3169 * If enable_unrestricted_guest, the CPU automatically
3170 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3172 if (!is_paging(vcpu))
3173 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3176 vmcs_writel(CR4_READ_SHADOW, cr4);
3177 vmcs_writel(GUEST_CR4, hw_cr4);
3181 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3183 struct vcpu_vmx *vmx = to_vmx(vcpu);
3186 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3187 *var = vmx->rmode.segs[seg];
3188 if (seg == VCPU_SREG_TR
3189 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3191 var->base = vmx_read_guest_seg_base(vmx, seg);
3192 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3195 var->base = vmx_read_guest_seg_base(vmx, seg);
3196 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3197 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3198 ar = vmx_read_guest_seg_ar(vmx, seg);
3199 var->unusable = (ar >> 16) & 1;
3200 var->type = ar & 15;
3201 var->s = (ar >> 4) & 1;
3202 var->dpl = (ar >> 5) & 3;
3204 * Some userspaces do not preserve unusable property. Since usable
3205 * segment has to be present according to VMX spec we can use present
3206 * property to amend userspace bug by making unusable segment always
3207 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3208 * segment as unusable.
3210 var->present = !var->unusable;
3211 var->avl = (ar >> 12) & 1;
3212 var->l = (ar >> 13) & 1;
3213 var->db = (ar >> 14) & 1;
3214 var->g = (ar >> 15) & 1;
3217 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3219 struct kvm_segment s;
3221 if (to_vmx(vcpu)->rmode.vm86_active) {
3222 vmx_get_segment(vcpu, &s, seg);
3225 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3228 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3230 struct vcpu_vmx *vmx = to_vmx(vcpu);
3232 if (unlikely(vmx->rmode.vm86_active))
3235 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3236 return VMX_AR_DPL(ar);
3240 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3244 if (var->unusable || !var->present)
3247 ar = var->type & 15;
3248 ar |= (var->s & 1) << 4;
3249 ar |= (var->dpl & 3) << 5;
3250 ar |= (var->present & 1) << 7;
3251 ar |= (var->avl & 1) << 12;
3252 ar |= (var->l & 1) << 13;
3253 ar |= (var->db & 1) << 14;
3254 ar |= (var->g & 1) << 15;
3260 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3262 struct vcpu_vmx *vmx = to_vmx(vcpu);
3263 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3265 vmx_segment_cache_clear(vmx);
3267 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3268 vmx->rmode.segs[seg] = *var;
3269 if (seg == VCPU_SREG_TR)
3270 vmcs_write16(sf->selector, var->selector);
3272 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3276 vmcs_writel(sf->base, var->base);
3277 vmcs_write32(sf->limit, var->limit);
3278 vmcs_write16(sf->selector, var->selector);
3281 * Fix the "Accessed" bit in AR field of segment registers for older
3283 * IA32 arch specifies that at the time of processor reset the
3284 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3285 * is setting it to 0 in the userland code. This causes invalid guest
3286 * state vmexit when "unrestricted guest" mode is turned on.
3287 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3288 * tree. Newer qemu binaries with that qemu fix would not need this
3291 if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3292 var->type |= 0x1; /* Accessed */
3294 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3297 vmx->emulation_required = emulation_required(vcpu);
3300 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3302 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3304 *db = (ar >> 14) & 1;
3305 *l = (ar >> 13) & 1;
3308 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3310 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3311 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3314 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3316 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3317 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3320 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3322 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3323 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3326 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3328 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3329 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3332 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3334 struct kvm_segment var;
3337 vmx_get_segment(vcpu, &var, seg);
3339 if (seg == VCPU_SREG_CS)
3341 ar = vmx_segment_access_rights(&var);
3343 if (var.base != (var.selector << 4))
3345 if (var.limit != 0xffff)
3353 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3355 struct kvm_segment cs;
3356 unsigned int cs_rpl;
3358 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3359 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3363 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3367 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3368 if (cs.dpl > cs_rpl)
3371 if (cs.dpl != cs_rpl)
3377 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3381 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3383 struct kvm_segment ss;
3384 unsigned int ss_rpl;
3386 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3387 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3391 if (ss.type != 3 && ss.type != 7)
3395 if (ss.dpl != ss_rpl) /* DPL != RPL */
3403 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3405 struct kvm_segment var;
3408 vmx_get_segment(vcpu, &var, seg);
3409 rpl = var.selector & SEGMENT_RPL_MASK;
3417 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3418 if (var.dpl < rpl) /* DPL < RPL */
3422 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3428 static bool tr_valid(struct kvm_vcpu *vcpu)
3430 struct kvm_segment tr;
3432 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3436 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3438 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3446 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3448 struct kvm_segment ldtr;
3450 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3454 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3464 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3466 struct kvm_segment cs, ss;
3468 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3469 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3471 return ((cs.selector & SEGMENT_RPL_MASK) ==
3472 (ss.selector & SEGMENT_RPL_MASK));
3476 * Check if guest state is valid. Returns true if valid, false if
3478 * We assume that registers are always usable
3480 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3482 if (is_unrestricted_guest(vcpu))
3485 /* real mode guest state checks */
3486 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3487 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3489 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3491 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3493 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3495 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3497 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3500 /* protected mode guest state checks */
3501 if (!cs_ss_rpl_check(vcpu))
3503 if (!code_segment_valid(vcpu))
3505 if (!stack_segment_valid(vcpu))
3507 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3509 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3511 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3513 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3515 if (!tr_valid(vcpu))
3517 if (!ldtr_valid(vcpu))
3521 * - Add checks on RIP
3522 * - Add checks on RFLAGS
3528 static int init_rmode_tss(struct kvm *kvm)
3534 idx = srcu_read_lock(&kvm->srcu);
3535 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3536 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3539 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3540 r = kvm_write_guest_page(kvm, fn++, &data,
3541 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3544 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3547 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3551 r = kvm_write_guest_page(kvm, fn, &data,
3552 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3555 srcu_read_unlock(&kvm->srcu, idx);
3559 static int init_rmode_identity_map(struct kvm *kvm)
3561 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3563 kvm_pfn_t identity_map_pfn;
3566 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3567 mutex_lock(&kvm->slots_lock);
3569 if (likely(kvm_vmx->ept_identity_pagetable_done))
3572 if (!kvm_vmx->ept_identity_map_addr)
3573 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3574 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3576 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3577 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3581 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3584 /* Set up identity-mapping pagetable for EPT in real mode */
3585 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3586 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3587 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3588 r = kvm_write_guest_page(kvm, identity_map_pfn,
3589 &tmp, i * sizeof(tmp), sizeof(tmp));
3593 kvm_vmx->ept_identity_pagetable_done = true;
3596 mutex_unlock(&kvm->slots_lock);
3600 static void seg_setup(int seg)
3602 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3605 vmcs_write16(sf->selector, 0);
3606 vmcs_writel(sf->base, 0);
3607 vmcs_write32(sf->limit, 0xffff);
3609 if (seg == VCPU_SREG_CS)
3610 ar |= 0x08; /* code segment */
3612 vmcs_write32(sf->ar_bytes, ar);
3615 static int alloc_apic_access_page(struct kvm *kvm)
3620 mutex_lock(&kvm->slots_lock);
3621 if (kvm->arch.apic_access_page_done)
3623 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3624 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3628 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3629 if (is_error_page(page)) {
3635 * Do not pin the page in memory, so that memory hot-unplug
3636 * is able to migrate it.
3639 kvm->arch.apic_access_page_done = true;
3641 mutex_unlock(&kvm->slots_lock);
3645 int allocate_vpid(void)
3651 spin_lock(&vmx_vpid_lock);
3652 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3653 if (vpid < VMX_NR_VPIDS)
3654 __set_bit(vpid, vmx_vpid_bitmap);
3657 spin_unlock(&vmx_vpid_lock);
3661 void free_vpid(int vpid)
3663 if (!enable_vpid || vpid == 0)
3665 spin_lock(&vmx_vpid_lock);
3666 __clear_bit(vpid, vmx_vpid_bitmap);
3667 spin_unlock(&vmx_vpid_lock);
3670 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3673 int f = sizeof(unsigned long);
3675 if (!cpu_has_vmx_msr_bitmap())
3678 if (static_branch_unlikely(&enable_evmcs))
3679 evmcs_touch_msr_bitmap();
3682 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3683 * have the write-low and read-high bitmap offsets the wrong way round.
3684 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3686 if (msr <= 0x1fff) {
3687 if (type & MSR_TYPE_R)
3689 __clear_bit(msr, msr_bitmap + 0x000 / f);
3691 if (type & MSR_TYPE_W)
3693 __clear_bit(msr, msr_bitmap + 0x800 / f);
3695 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3697 if (type & MSR_TYPE_R)
3699 __clear_bit(msr, msr_bitmap + 0x400 / f);
3701 if (type & MSR_TYPE_W)
3703 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3708 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3711 int f = sizeof(unsigned long);
3713 if (!cpu_has_vmx_msr_bitmap())
3716 if (static_branch_unlikely(&enable_evmcs))
3717 evmcs_touch_msr_bitmap();
3720 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3721 * have the write-low and read-high bitmap offsets the wrong way round.
3722 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3724 if (msr <= 0x1fff) {
3725 if (type & MSR_TYPE_R)
3727 __set_bit(msr, msr_bitmap + 0x000 / f);
3729 if (type & MSR_TYPE_W)
3731 __set_bit(msr, msr_bitmap + 0x800 / f);
3733 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3735 if (type & MSR_TYPE_R)
3737 __set_bit(msr, msr_bitmap + 0x400 / f);
3739 if (type & MSR_TYPE_W)
3741 __set_bit(msr, msr_bitmap + 0xc00 / f);
3746 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3747 u32 msr, int type, bool value)
3750 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3752 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3755 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3759 if (cpu_has_secondary_exec_ctrls() &&
3760 (secondary_exec_controls_get(to_vmx(vcpu)) &
3761 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3762 mode |= MSR_BITMAP_MODE_X2APIC;
3763 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3764 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3770 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3775 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3776 unsigned word = msr / BITS_PER_LONG;
3777 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3778 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3781 if (mode & MSR_BITMAP_MODE_X2APIC) {
3783 * TPR reads and writes can be virtualized even if virtual interrupt
3784 * delivery is not in use.
3786 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3787 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3788 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3789 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3790 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3795 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3797 struct vcpu_vmx *vmx = to_vmx(vcpu);
3798 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3799 u8 mode = vmx_msr_bitmap_mode(vcpu);
3800 u8 changed = mode ^ vmx->msr_bitmap_mode;
3805 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3806 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3808 vmx->msr_bitmap_mode = mode;
3811 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3813 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3814 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3817 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3819 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3821 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3823 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3825 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3826 vmx_set_intercept_for_msr(msr_bitmap,
3827 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3828 vmx_set_intercept_for_msr(msr_bitmap,
3829 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3833 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3835 struct vcpu_vmx *vmx = to_vmx(vcpu);
3840 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3841 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3842 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3845 rvi = vmx_get_rvi();
3847 vapic_page = vmx->nested.virtual_apic_map.hva;
3848 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3850 return ((rvi & 0xf0) > (vppr & 0xf0));
3853 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3857 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3859 if (vcpu->mode == IN_GUEST_MODE) {
3861 * The vector of interrupt to be delivered to vcpu had
3862 * been set in PIR before this function.
3864 * Following cases will be reached in this block, and
3865 * we always send a notification event in all cases as
3868 * Case 1: vcpu keeps in non-root mode. Sending a
3869 * notification event posts the interrupt to vcpu.
3871 * Case 2: vcpu exits to root mode and is still
3872 * runnable. PIR will be synced to vIRR before the
3873 * next vcpu entry. Sending a notification event in
3874 * this case has no effect, as vcpu is not in root
3877 * Case 3: vcpu exits to root mode and is blocked.
3878 * vcpu_block() has already synced PIR to vIRR and
3879 * never blocks vcpu if vIRR is not cleared. Therefore,
3880 * a blocked vcpu here does not wait for any requested
3881 * interrupts in PIR, and sending a notification event
3882 * which has no effect is safe here.
3885 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3892 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3895 struct vcpu_vmx *vmx = to_vmx(vcpu);
3897 if (is_guest_mode(vcpu) &&
3898 vector == vmx->nested.posted_intr_nv) {
3900 * If a posted intr is not recognized by hardware,
3901 * we will accomplish it in the next vmentry.
3903 vmx->nested.pi_pending = true;
3904 kvm_make_request(KVM_REQ_EVENT, vcpu);
3905 /* the PIR and ON have been set by L1. */
3906 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3907 kvm_vcpu_kick(vcpu);
3913 * Send interrupt to vcpu via posted interrupt way.
3914 * 1. If target vcpu is running(non-root mode), send posted interrupt
3915 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3916 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3917 * interrupt from PIR in next vmentry.
3919 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3921 struct vcpu_vmx *vmx = to_vmx(vcpu);
3924 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3928 if (!vcpu->arch.apicv_active)
3931 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3934 /* If a previous notification has sent the IPI, nothing to do. */
3935 if (pi_test_and_set_on(&vmx->pi_desc))
3938 if (vcpu != kvm_get_running_vcpu() &&
3939 !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3940 kvm_vcpu_kick(vcpu);
3946 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3947 * will not change in the lifetime of the guest.
3948 * Note that host-state that does change is set elsewhere. E.g., host-state
3949 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3951 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3955 unsigned long cr0, cr3, cr4;
3958 WARN_ON(cr0 & X86_CR0_TS);
3959 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3962 * Save the most likely value for this task's CR3 in the VMCS.
3963 * We can't use __get_current_cr3_fast() because we're not atomic.
3966 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
3967 vmx->loaded_vmcs->host_state.cr3 = cr3;
3969 /* Save the most likely value for this task's CR4 in the VMCS. */
3970 cr4 = cr4_read_shadow();
3971 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
3972 vmx->loaded_vmcs->host_state.cr4 = cr4;
3974 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3975 #ifdef CONFIG_X86_64
3977 * Load null selectors, so we can avoid reloading them in
3978 * vmx_prepare_switch_to_host(), in case userspace uses
3979 * the null selectors too (the expected case).
3981 vmcs_write16(HOST_DS_SELECTOR, 0);
3982 vmcs_write16(HOST_ES_SELECTOR, 0);
3984 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3985 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3987 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3988 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3990 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
3992 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3994 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3995 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3996 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3997 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3999 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4000 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4001 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4004 if (cpu_has_load_ia32_efer())
4005 vmcs_write64(HOST_IA32_EFER, host_efer);
4008 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4010 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS;
4012 vmx->vcpu.arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4013 if (is_guest_mode(&vmx->vcpu))
4014 vmx->vcpu.arch.cr4_guest_owned_bits &=
4015 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4016 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4019 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4021 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4023 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4024 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4027 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4029 if (!enable_preemption_timer)
4030 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4032 return pin_based_exec_ctrl;
4035 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4037 struct vcpu_vmx *vmx = to_vmx(vcpu);
4039 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4040 if (cpu_has_secondary_exec_ctrls()) {
4041 if (kvm_vcpu_apicv_active(vcpu))
4042 secondary_exec_controls_setbit(vmx,
4043 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4044 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4046 secondary_exec_controls_clearbit(vmx,
4047 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4048 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4051 if (cpu_has_vmx_msr_bitmap())
4052 vmx_update_msr_bitmap(vcpu);
4055 u32 vmx_exec_control(struct vcpu_vmx *vmx)
4057 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4059 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4060 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4062 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4063 exec_control &= ~CPU_BASED_TPR_SHADOW;
4064 #ifdef CONFIG_X86_64
4065 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4066 CPU_BASED_CR8_LOAD_EXITING;
4070 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4071 CPU_BASED_CR3_LOAD_EXITING |
4072 CPU_BASED_INVLPG_EXITING;
4073 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4074 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4075 CPU_BASED_MONITOR_EXITING);
4076 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4077 exec_control &= ~CPU_BASED_HLT_EXITING;
4078 return exec_control;
4082 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4084 struct kvm_vcpu *vcpu = &vmx->vcpu;
4086 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4088 if (vmx_pt_mode_is_system())
4089 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4090 if (!cpu_need_virtualize_apic_accesses(vcpu))
4091 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4093 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4095 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4096 enable_unrestricted_guest = 0;
4098 if (!enable_unrestricted_guest)
4099 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4100 if (kvm_pause_in_guest(vmx->vcpu.kvm))
4101 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4102 if (!kvm_vcpu_apicv_active(vcpu))
4103 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4104 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4105 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4107 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4108 * in vmx_set_cr4. */
4109 exec_control &= ~SECONDARY_EXEC_DESC;
4111 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4113 We can NOT enable shadow_vmcs here because we don't have yet
4116 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4119 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4121 if (vmx_xsaves_supported()) {
4122 /* Exposing XSAVES only when XSAVE is exposed */
4123 bool xsaves_enabled =
4124 boot_cpu_has(X86_FEATURE_XSAVE) &&
4125 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4126 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4128 vcpu->arch.xsaves_enabled = xsaves_enabled;
4130 if (!xsaves_enabled)
4131 exec_control &= ~SECONDARY_EXEC_XSAVES;
4135 vmx->nested.msrs.secondary_ctls_high |=
4136 SECONDARY_EXEC_XSAVES;
4138 vmx->nested.msrs.secondary_ctls_high &=
4139 ~SECONDARY_EXEC_XSAVES;
4143 if (cpu_has_vmx_rdtscp()) {
4144 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4145 if (!rdtscp_enabled)
4146 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4150 vmx->nested.msrs.secondary_ctls_high |=
4151 SECONDARY_EXEC_RDTSCP;
4153 vmx->nested.msrs.secondary_ctls_high &=
4154 ~SECONDARY_EXEC_RDTSCP;
4158 if (cpu_has_vmx_invpcid()) {
4159 /* Exposing INVPCID only when PCID is exposed */
4160 bool invpcid_enabled =
4161 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4162 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4164 if (!invpcid_enabled) {
4165 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4166 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4170 if (invpcid_enabled)
4171 vmx->nested.msrs.secondary_ctls_high |=
4172 SECONDARY_EXEC_ENABLE_INVPCID;
4174 vmx->nested.msrs.secondary_ctls_high &=
4175 ~SECONDARY_EXEC_ENABLE_INVPCID;
4179 if (vmx_rdrand_supported()) {
4180 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4182 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4186 vmx->nested.msrs.secondary_ctls_high |=
4187 SECONDARY_EXEC_RDRAND_EXITING;
4189 vmx->nested.msrs.secondary_ctls_high &=
4190 ~SECONDARY_EXEC_RDRAND_EXITING;
4194 if (vmx_rdseed_supported()) {
4195 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4197 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4201 vmx->nested.msrs.secondary_ctls_high |=
4202 SECONDARY_EXEC_RDSEED_EXITING;
4204 vmx->nested.msrs.secondary_ctls_high &=
4205 ~SECONDARY_EXEC_RDSEED_EXITING;
4209 if (vmx_waitpkg_supported()) {
4210 bool waitpkg_enabled =
4211 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4213 if (!waitpkg_enabled)
4214 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4217 if (waitpkg_enabled)
4218 vmx->nested.msrs.secondary_ctls_high |=
4219 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4221 vmx->nested.msrs.secondary_ctls_high &=
4222 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4226 vmx->secondary_exec_control = exec_control;
4229 static void ept_set_mmio_spte_mask(void)
4232 * EPT Misconfigurations can be generated if the value of bits 2:0
4233 * of an EPT paging-structure entry is 110b (write/execute).
4235 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE, 0);
4238 #define VMX_XSS_EXIT_BITMAP 0
4241 * Noting that the initialization of Guest-state Area of VMCS is in
4244 static void init_vmcs(struct vcpu_vmx *vmx)
4247 nested_vmx_set_vmcs_shadowing_bitmap();
4249 if (cpu_has_vmx_msr_bitmap())
4250 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4252 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4255 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4257 exec_controls_set(vmx, vmx_exec_control(vmx));
4259 if (cpu_has_secondary_exec_ctrls()) {
4260 vmx_compute_secondary_exec_control(vmx);
4261 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4264 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4265 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4266 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4267 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4268 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4270 vmcs_write16(GUEST_INTR_STATUS, 0);
4272 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4273 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4276 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4277 vmcs_write32(PLE_GAP, ple_gap);
4278 vmx->ple_window = ple_window;
4279 vmx->ple_window_dirty = true;
4282 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4283 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4284 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4286 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4287 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4288 vmx_set_constant_host_state(vmx);
4289 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4290 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4292 if (cpu_has_vmx_vmfunc())
4293 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4295 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4296 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4297 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4298 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4299 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4301 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4302 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4304 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4306 /* 22.2.1, 20.8.1 */
4307 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4309 vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4310 vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4312 set_cr4_guest_host_mask(vmx);
4315 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4317 if (vmx_xsaves_supported())
4318 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4321 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4322 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4325 if (cpu_has_vmx_encls_vmexit())
4326 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4328 if (vmx_pt_mode_is_host_guest()) {
4329 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4330 /* Bit[6~0] are forced to 1, writes are ignored. */
4331 vmx->pt_desc.guest.output_mask = 0x7F;
4332 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4336 * If EPT is enabled, #PF is only trapped if MAXPHYADDR is mismatched
4337 * between guest and host. In that case we only care about present
4341 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, PFERR_PRESENT_MASK);
4342 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, PFERR_PRESENT_MASK);
4346 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4348 struct vcpu_vmx *vmx = to_vmx(vcpu);
4349 struct msr_data apic_base_msr;
4352 vmx->rmode.vm86_active = 0;
4355 vmx->msr_ia32_umwait_control = 0;
4357 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4358 vmx->hv_deadline_tsc = -1;
4359 kvm_set_cr8(vcpu, 0);
4362 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4363 MSR_IA32_APICBASE_ENABLE;
4364 if (kvm_vcpu_is_reset_bsp(vcpu))
4365 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4366 apic_base_msr.host_initiated = true;
4367 kvm_set_apic_base(vcpu, &apic_base_msr);
4370 vmx_segment_cache_clear(vmx);
4372 seg_setup(VCPU_SREG_CS);
4373 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4374 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4376 seg_setup(VCPU_SREG_DS);
4377 seg_setup(VCPU_SREG_ES);
4378 seg_setup(VCPU_SREG_FS);
4379 seg_setup(VCPU_SREG_GS);
4380 seg_setup(VCPU_SREG_SS);
4382 vmcs_write16(GUEST_TR_SELECTOR, 0);
4383 vmcs_writel(GUEST_TR_BASE, 0);
4384 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4385 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4387 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4388 vmcs_writel(GUEST_LDTR_BASE, 0);
4389 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4390 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4393 vmcs_write32(GUEST_SYSENTER_CS, 0);
4394 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4395 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4396 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4399 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4400 kvm_rip_write(vcpu, 0xfff0);
4402 vmcs_writel(GUEST_GDTR_BASE, 0);
4403 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4405 vmcs_writel(GUEST_IDTR_BASE, 0);
4406 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4408 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4409 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4410 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4411 if (kvm_mpx_supported())
4412 vmcs_write64(GUEST_BNDCFGS, 0);
4416 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4418 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4419 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4420 if (cpu_need_tpr_shadow(vcpu))
4421 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4422 __pa(vcpu->arch.apic->regs));
4423 vmcs_write32(TPR_THRESHOLD, 0);
4426 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4428 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4429 vmx->vcpu.arch.cr0 = cr0;
4430 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4431 vmx_set_cr4(vcpu, 0);
4432 vmx_set_efer(vcpu, 0);
4434 update_exception_bitmap(vcpu);
4436 vpid_sync_context(vmx->vpid);
4438 vmx_clear_hlt(vcpu);
4441 static void enable_irq_window(struct kvm_vcpu *vcpu)
4443 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4446 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4449 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4450 enable_irq_window(vcpu);
4454 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4457 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4459 struct vcpu_vmx *vmx = to_vmx(vcpu);
4461 int irq = vcpu->arch.interrupt.nr;
4463 trace_kvm_inj_virq(irq);
4465 ++vcpu->stat.irq_injections;
4466 if (vmx->rmode.vm86_active) {
4468 if (vcpu->arch.interrupt.soft)
4469 inc_eip = vcpu->arch.event_exit_inst_len;
4470 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4473 intr = irq | INTR_INFO_VALID_MASK;
4474 if (vcpu->arch.interrupt.soft) {
4475 intr |= INTR_TYPE_SOFT_INTR;
4476 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4477 vmx->vcpu.arch.event_exit_inst_len);
4479 intr |= INTR_TYPE_EXT_INTR;
4480 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4482 vmx_clear_hlt(vcpu);
4485 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4487 struct vcpu_vmx *vmx = to_vmx(vcpu);
4491 * Tracking the NMI-blocked state in software is built upon
4492 * finding the next open IRQ window. This, in turn, depends on
4493 * well-behaving guests: They have to keep IRQs disabled at
4494 * least as long as the NMI handler runs. Otherwise we may
4495 * cause NMI nesting, maybe breaking the guest. But as this is
4496 * highly unlikely, we can live with the residual risk.
4498 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4499 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4502 ++vcpu->stat.nmi_injections;
4503 vmx->loaded_vmcs->nmi_known_unmasked = false;
4505 if (vmx->rmode.vm86_active) {
4506 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4510 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4511 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4513 vmx_clear_hlt(vcpu);
4516 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4518 struct vcpu_vmx *vmx = to_vmx(vcpu);
4522 return vmx->loaded_vmcs->soft_vnmi_blocked;
4523 if (vmx->loaded_vmcs->nmi_known_unmasked)
4525 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4526 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4530 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4532 struct vcpu_vmx *vmx = to_vmx(vcpu);
4535 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4536 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4537 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4540 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4542 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4543 GUEST_INTR_STATE_NMI);
4545 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4546 GUEST_INTR_STATE_NMI);
4550 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4552 if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4555 if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4558 return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4559 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4560 GUEST_INTR_STATE_NMI));
4563 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4565 if (to_vmx(vcpu)->nested.nested_run_pending)
4568 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
4569 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4572 return !vmx_nmi_blocked(vcpu);
4575 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4577 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4580 return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4581 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4582 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4585 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4587 if (to_vmx(vcpu)->nested.nested_run_pending)
4591 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4592 * e.g. if the IRQ arrived asynchronously after checking nested events.
4594 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4597 return !vmx_interrupt_blocked(vcpu);
4600 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4604 if (enable_unrestricted_guest)
4607 mutex_lock(&kvm->slots_lock);
4608 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4610 mutex_unlock(&kvm->slots_lock);
4614 to_kvm_vmx(kvm)->tss_addr = addr;
4615 return init_rmode_tss(kvm);
4618 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4620 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4624 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4629 * Update instruction length as we may reinject the exception
4630 * from user space while in guest debugging mode.
4632 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4633 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4634 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4638 return !(vcpu->guest_debug &
4639 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4653 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4654 int vec, u32 err_code)
4657 * Instruction with address size override prefix opcode 0x67
4658 * Cause the #SS fault with 0 error code in VM86 mode.
4660 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4661 if (kvm_emulate_instruction(vcpu, 0)) {
4662 if (vcpu->arch.halt_request) {
4663 vcpu->arch.halt_request = 0;
4664 return kvm_vcpu_halt(vcpu);
4672 * Forward all other exceptions that are valid in real mode.
4673 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4674 * the required debugging infrastructure rework.
4676 kvm_queue_exception(vcpu, vec);
4681 * Trigger machine check on the host. We assume all the MSRs are already set up
4682 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4683 * We pass a fake environment to the machine check handler because we want
4684 * the guest to be always treated like user space, no matter what context
4685 * it used internally.
4687 static void kvm_machine_check(void)
4689 #if defined(CONFIG_X86_MCE)
4690 struct pt_regs regs = {
4691 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4692 .flags = X86_EFLAGS_IF,
4695 do_machine_check(®s);
4699 static int handle_machine_check(struct kvm_vcpu *vcpu)
4701 /* handled by vmx_vcpu_run() */
4706 * If the host has split lock detection disabled, then #AC is
4707 * unconditionally injected into the guest, which is the pre split lock
4708 * detection behaviour.
4710 * If the host has split lock detection enabled then #AC is
4711 * only injected into the guest when:
4712 * - Guest CPL == 3 (user mode)
4713 * - Guest has #AC detection enabled in CR0
4714 * - Guest EFLAGS has AC bit set
4716 static inline bool guest_inject_ac(struct kvm_vcpu *vcpu)
4718 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4721 return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4722 (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4725 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4727 struct vcpu_vmx *vmx = to_vmx(vcpu);
4728 struct kvm_run *kvm_run = vcpu->run;
4729 u32 intr_info, ex_no, error_code;
4730 unsigned long cr2, rip, dr6;
4733 vect_info = vmx->idt_vectoring_info;
4734 intr_info = vmx_get_intr_info(vcpu);
4736 if (is_machine_check(intr_info) || is_nmi(intr_info))
4737 return 1; /* handled by handle_exception_nmi_irqoff() */
4739 if (is_invalid_opcode(intr_info))
4740 return handle_ud(vcpu);
4743 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4744 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4746 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4747 WARN_ON_ONCE(!enable_vmware_backdoor);
4750 * VMware backdoor emulation on #GP interception only handles
4751 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4752 * error code on #GP.
4755 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4758 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4762 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4763 * MMIO, it is better to report an internal error.
4764 * See the comments in vmx_handle_exit.
4766 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4767 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4768 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4769 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4770 vcpu->run->internal.ndata = 4;
4771 vcpu->run->internal.data[0] = vect_info;
4772 vcpu->run->internal.data[1] = intr_info;
4773 vcpu->run->internal.data[2] = error_code;
4774 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4778 if (is_page_fault(intr_info)) {
4779 cr2 = vmx_get_exit_qual(vcpu);
4780 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4782 * EPT will cause page fault only if we need to
4783 * detect illegal GPAs.
4785 kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4788 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4791 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4793 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4794 return handle_rmode_exception(vcpu, ex_no, error_code);
4798 dr6 = vmx_get_exit_qual(vcpu);
4799 if (!(vcpu->guest_debug &
4800 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4801 if (is_icebp(intr_info))
4802 WARN_ON(!skip_emulated_instruction(vcpu));
4804 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4807 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4808 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4812 * Update instruction length as we may reinject #BP from
4813 * user space while in guest debugging mode. Reading it for
4814 * #DB as well causes no harm, it is not used in that case.
4816 vmx->vcpu.arch.event_exit_inst_len =
4817 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4818 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4819 rip = kvm_rip_read(vcpu);
4820 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4821 kvm_run->debug.arch.exception = ex_no;
4824 if (guest_inject_ac(vcpu)) {
4825 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4830 * Handle split lock. Depending on detection mode this will
4831 * either warn and disable split lock detection for this
4832 * task or force SIGBUS on it.
4834 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4838 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4839 kvm_run->ex.exception = ex_no;
4840 kvm_run->ex.error_code = error_code;
4846 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4848 ++vcpu->stat.irq_exits;
4852 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4854 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4855 vcpu->mmio_needed = 0;
4859 static int handle_io(struct kvm_vcpu *vcpu)
4861 unsigned long exit_qualification;
4862 int size, in, string;
4865 exit_qualification = vmx_get_exit_qual(vcpu);
4866 string = (exit_qualification & 16) != 0;
4868 ++vcpu->stat.io_exits;
4871 return kvm_emulate_instruction(vcpu, 0);
4873 port = exit_qualification >> 16;
4874 size = (exit_qualification & 7) + 1;
4875 in = (exit_qualification & 8) != 0;
4877 return kvm_fast_pio(vcpu, size, port, in);
4881 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4884 * Patch in the VMCALL instruction:
4886 hypercall[0] = 0x0f;
4887 hypercall[1] = 0x01;
4888 hypercall[2] = 0xc1;
4891 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4892 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4894 if (is_guest_mode(vcpu)) {
4895 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4896 unsigned long orig_val = val;
4899 * We get here when L2 changed cr0 in a way that did not change
4900 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4901 * but did change L0 shadowed bits. So we first calculate the
4902 * effective cr0 value that L1 would like to write into the
4903 * hardware. It consists of the L2-owned bits from the new
4904 * value combined with the L1-owned bits from L1's guest_cr0.
4906 val = (val & ~vmcs12->cr0_guest_host_mask) |
4907 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4909 if (!nested_guest_cr0_valid(vcpu, val))
4912 if (kvm_set_cr0(vcpu, val))
4914 vmcs_writel(CR0_READ_SHADOW, orig_val);
4917 if (to_vmx(vcpu)->nested.vmxon &&
4918 !nested_host_cr0_valid(vcpu, val))
4921 return kvm_set_cr0(vcpu, val);
4925 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4927 if (is_guest_mode(vcpu)) {
4928 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4929 unsigned long orig_val = val;
4931 /* analogously to handle_set_cr0 */
4932 val = (val & ~vmcs12->cr4_guest_host_mask) |
4933 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4934 if (kvm_set_cr4(vcpu, val))
4936 vmcs_writel(CR4_READ_SHADOW, orig_val);
4939 return kvm_set_cr4(vcpu, val);
4942 static int handle_desc(struct kvm_vcpu *vcpu)
4944 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4945 return kvm_emulate_instruction(vcpu, 0);
4948 static int handle_cr(struct kvm_vcpu *vcpu)
4950 unsigned long exit_qualification, val;
4956 exit_qualification = vmx_get_exit_qual(vcpu);
4957 cr = exit_qualification & 15;
4958 reg = (exit_qualification >> 8) & 15;
4959 switch ((exit_qualification >> 4) & 3) {
4960 case 0: /* mov to cr */
4961 val = kvm_register_readl(vcpu, reg);
4962 trace_kvm_cr_write(cr, val);
4965 err = handle_set_cr0(vcpu, val);
4966 return kvm_complete_insn_gp(vcpu, err);
4968 WARN_ON_ONCE(enable_unrestricted_guest);
4969 err = kvm_set_cr3(vcpu, val);
4970 return kvm_complete_insn_gp(vcpu, err);
4972 err = handle_set_cr4(vcpu, val);
4973 return kvm_complete_insn_gp(vcpu, err);
4975 u8 cr8_prev = kvm_get_cr8(vcpu);
4977 err = kvm_set_cr8(vcpu, cr8);
4978 ret = kvm_complete_insn_gp(vcpu, err);
4979 if (lapic_in_kernel(vcpu))
4981 if (cr8_prev <= cr8)
4984 * TODO: we might be squashing a
4985 * KVM_GUESTDBG_SINGLESTEP-triggered
4986 * KVM_EXIT_DEBUG here.
4988 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4994 WARN_ONCE(1, "Guest should always own CR0.TS");
4995 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4996 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4997 return kvm_skip_emulated_instruction(vcpu);
4998 case 1: /*mov from cr*/
5001 WARN_ON_ONCE(enable_unrestricted_guest);
5002 val = kvm_read_cr3(vcpu);
5003 kvm_register_write(vcpu, reg, val);
5004 trace_kvm_cr_read(cr, val);
5005 return kvm_skip_emulated_instruction(vcpu);
5007 val = kvm_get_cr8(vcpu);
5008 kvm_register_write(vcpu, reg, val);
5009 trace_kvm_cr_read(cr, val);
5010 return kvm_skip_emulated_instruction(vcpu);
5014 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5015 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5016 kvm_lmsw(vcpu, val);
5018 return kvm_skip_emulated_instruction(vcpu);
5022 vcpu->run->exit_reason = 0;
5023 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5024 (int)(exit_qualification >> 4) & 3, cr);
5028 static int handle_dr(struct kvm_vcpu *vcpu)
5030 unsigned long exit_qualification;
5033 exit_qualification = vmx_get_exit_qual(vcpu);
5034 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5036 /* First, if DR does not exist, trigger UD */
5037 if (!kvm_require_dr(vcpu, dr))
5040 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5041 if (!kvm_require_cpl(vcpu, 0))
5043 dr7 = vmcs_readl(GUEST_DR7);
5046 * As the vm-exit takes precedence over the debug trap, we
5047 * need to emulate the latter, either for the host or the
5048 * guest debugging itself.
5050 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5051 vcpu->run->debug.arch.dr6 = DR6_BD | DR6_RTM | DR6_FIXED_1;
5052 vcpu->run->debug.arch.dr7 = dr7;
5053 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5054 vcpu->run->debug.arch.exception = DB_VECTOR;
5055 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5058 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5063 if (vcpu->guest_debug == 0) {
5064 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5067 * No more DR vmexits; force a reload of the debug registers
5068 * and reenter on this instruction. The next vmexit will
5069 * retrieve the full state of the debug registers.
5071 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5075 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5076 if (exit_qualification & TYPE_MOV_FROM_DR) {
5079 if (kvm_get_dr(vcpu, dr, &val))
5081 kvm_register_write(vcpu, reg, val);
5083 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5086 return kvm_skip_emulated_instruction(vcpu);
5089 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5091 get_debugreg(vcpu->arch.db[0], 0);
5092 get_debugreg(vcpu->arch.db[1], 1);
5093 get_debugreg(vcpu->arch.db[2], 2);
5094 get_debugreg(vcpu->arch.db[3], 3);
5095 get_debugreg(vcpu->arch.dr6, 6);
5096 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5098 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5099 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5102 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5104 vmcs_writel(GUEST_DR7, val);
5107 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5109 kvm_apic_update_ppr(vcpu);
5113 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5115 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5117 kvm_make_request(KVM_REQ_EVENT, vcpu);
5119 ++vcpu->stat.irq_window_exits;
5123 static int handle_vmcall(struct kvm_vcpu *vcpu)
5125 return kvm_emulate_hypercall(vcpu);
5128 static int handle_invd(struct kvm_vcpu *vcpu)
5130 /* Treat an INVD instruction as a NOP and just skip it. */
5131 return kvm_skip_emulated_instruction(vcpu);
5134 static int handle_invlpg(struct kvm_vcpu *vcpu)
5136 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5138 kvm_mmu_invlpg(vcpu, exit_qualification);
5139 return kvm_skip_emulated_instruction(vcpu);
5142 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5146 err = kvm_rdpmc(vcpu);
5147 return kvm_complete_insn_gp(vcpu, err);
5150 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5152 return kvm_emulate_wbinvd(vcpu);
5155 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5157 u64 new_bv = kvm_read_edx_eax(vcpu);
5158 u32 index = kvm_rcx_read(vcpu);
5160 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5161 return kvm_skip_emulated_instruction(vcpu);
5165 static int handle_apic_access(struct kvm_vcpu *vcpu)
5167 if (likely(fasteoi)) {
5168 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5169 int access_type, offset;
5171 access_type = exit_qualification & APIC_ACCESS_TYPE;
5172 offset = exit_qualification & APIC_ACCESS_OFFSET;
5174 * Sane guest uses MOV to write EOI, with written value
5175 * not cared. So make a short-circuit here by avoiding
5176 * heavy instruction emulation.
5178 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5179 (offset == APIC_EOI)) {
5180 kvm_lapic_set_eoi(vcpu);
5181 return kvm_skip_emulated_instruction(vcpu);
5184 return kvm_emulate_instruction(vcpu, 0);
5187 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5189 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5190 int vector = exit_qualification & 0xff;
5192 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5193 kvm_apic_set_eoi_accelerated(vcpu, vector);
5197 static int handle_apic_write(struct kvm_vcpu *vcpu)
5199 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5200 u32 offset = exit_qualification & 0xfff;
5202 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5203 kvm_apic_write_nodecode(vcpu, offset);
5207 static int handle_task_switch(struct kvm_vcpu *vcpu)
5209 struct vcpu_vmx *vmx = to_vmx(vcpu);
5210 unsigned long exit_qualification;
5211 bool has_error_code = false;
5214 int reason, type, idt_v, idt_index;
5216 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5217 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5218 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5220 exit_qualification = vmx_get_exit_qual(vcpu);
5222 reason = (u32)exit_qualification >> 30;
5223 if (reason == TASK_SWITCH_GATE && idt_v) {
5225 case INTR_TYPE_NMI_INTR:
5226 vcpu->arch.nmi_injected = false;
5227 vmx_set_nmi_mask(vcpu, true);
5229 case INTR_TYPE_EXT_INTR:
5230 case INTR_TYPE_SOFT_INTR:
5231 kvm_clear_interrupt_queue(vcpu);
5233 case INTR_TYPE_HARD_EXCEPTION:
5234 if (vmx->idt_vectoring_info &
5235 VECTORING_INFO_DELIVER_CODE_MASK) {
5236 has_error_code = true;
5238 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5241 case INTR_TYPE_SOFT_EXCEPTION:
5242 kvm_clear_exception_queue(vcpu);
5248 tss_selector = exit_qualification;
5250 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5251 type != INTR_TYPE_EXT_INTR &&
5252 type != INTR_TYPE_NMI_INTR))
5253 WARN_ON(!skip_emulated_instruction(vcpu));
5256 * TODO: What about debug traps on tss switch?
5257 * Are we supposed to inject them and update dr6?
5259 return kvm_task_switch(vcpu, tss_selector,
5260 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5261 reason, has_error_code, error_code);
5264 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5266 unsigned long exit_qualification;
5270 exit_qualification = vmx_get_exit_qual(vcpu);
5273 * EPT violation happened while executing iret from NMI,
5274 * "blocked by NMI" bit has to be set before next VM entry.
5275 * There are errata that may cause this bit to not be set:
5278 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5280 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5281 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5283 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5284 trace_kvm_page_fault(gpa, exit_qualification);
5286 /* Is it a read fault? */
5287 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5288 ? PFERR_USER_MASK : 0;
5289 /* Is it a write fault? */
5290 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5291 ? PFERR_WRITE_MASK : 0;
5292 /* Is it a fetch fault? */
5293 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5294 ? PFERR_FETCH_MASK : 0;
5295 /* ept page table entry is present? */
5296 error_code |= (exit_qualification &
5297 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5298 EPT_VIOLATION_EXECUTABLE))
5299 ? PFERR_PRESENT_MASK : 0;
5301 error_code |= (exit_qualification & 0x100) != 0 ?
5302 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5304 vcpu->arch.exit_qualification = exit_qualification;
5307 * Check that the GPA doesn't exceed physical memory limits, as that is
5308 * a guest page fault. We have to emulate the instruction here, because
5309 * if the illegal address is that of a paging structure, then
5310 * EPT_VIOLATION_ACC_WRITE bit is set. Alternatively, if supported we
5311 * would also use advanced VM-exit information for EPT violations to
5312 * reconstruct the page fault error code.
5314 if (unlikely(kvm_mmu_is_illegal_gpa(vcpu, gpa)))
5315 return kvm_emulate_instruction(vcpu, 0);
5317 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5320 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5325 * A nested guest cannot optimize MMIO vmexits, because we have an
5326 * nGPA here instead of the required GPA.
5328 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5329 if (!is_guest_mode(vcpu) &&
5330 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5331 trace_kvm_fast_mmio(gpa);
5332 return kvm_skip_emulated_instruction(vcpu);
5335 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5338 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5340 WARN_ON_ONCE(!enable_vnmi);
5341 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5342 ++vcpu->stat.nmi_window_exits;
5343 kvm_make_request(KVM_REQ_EVENT, vcpu);
5348 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5350 struct vcpu_vmx *vmx = to_vmx(vcpu);
5351 bool intr_window_requested;
5352 unsigned count = 130;
5354 intr_window_requested = exec_controls_get(vmx) &
5355 CPU_BASED_INTR_WINDOW_EXITING;
5357 while (vmx->emulation_required && count-- != 0) {
5358 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5359 return handle_interrupt_window(&vmx->vcpu);
5361 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5364 if (!kvm_emulate_instruction(vcpu, 0))
5367 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5368 vcpu->arch.exception.pending) {
5369 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5370 vcpu->run->internal.suberror =
5371 KVM_INTERNAL_ERROR_EMULATION;
5372 vcpu->run->internal.ndata = 0;
5376 if (vcpu->arch.halt_request) {
5377 vcpu->arch.halt_request = 0;
5378 return kvm_vcpu_halt(vcpu);
5382 * Note, return 1 and not 0, vcpu_run() will invoke
5383 * xfer_to_guest_mode() which will create a proper return
5386 if (__xfer_to_guest_mode_work_pending())
5393 static void grow_ple_window(struct kvm_vcpu *vcpu)
5395 struct vcpu_vmx *vmx = to_vmx(vcpu);
5396 unsigned int old = vmx->ple_window;
5398 vmx->ple_window = __grow_ple_window(old, ple_window,
5402 if (vmx->ple_window != old) {
5403 vmx->ple_window_dirty = true;
5404 trace_kvm_ple_window_update(vcpu->vcpu_id,
5405 vmx->ple_window, old);
5409 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5411 struct vcpu_vmx *vmx = to_vmx(vcpu);
5412 unsigned int old = vmx->ple_window;
5414 vmx->ple_window = __shrink_ple_window(old, ple_window,
5418 if (vmx->ple_window != old) {
5419 vmx->ple_window_dirty = true;
5420 trace_kvm_ple_window_update(vcpu->vcpu_id,
5421 vmx->ple_window, old);
5426 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5428 static void wakeup_handler(void)
5430 struct kvm_vcpu *vcpu;
5431 int cpu = smp_processor_id();
5433 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5434 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5435 blocked_vcpu_list) {
5436 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5438 if (pi_test_on(pi_desc) == 1)
5439 kvm_vcpu_kick(vcpu);
5441 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5444 static void vmx_enable_tdp(void)
5446 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5447 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5448 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5449 0ull, VMX_EPT_EXECUTABLE_MASK,
5450 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5451 VMX_EPT_RWX_MASK, 0ull);
5453 ept_set_mmio_spte_mask();
5457 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5458 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5460 static int handle_pause(struct kvm_vcpu *vcpu)
5462 if (!kvm_pause_in_guest(vcpu->kvm))
5463 grow_ple_window(vcpu);
5466 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5467 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5468 * never set PAUSE_EXITING and just set PLE if supported,
5469 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5471 kvm_vcpu_on_spin(vcpu, true);
5472 return kvm_skip_emulated_instruction(vcpu);
5475 static int handle_nop(struct kvm_vcpu *vcpu)
5477 return kvm_skip_emulated_instruction(vcpu);
5480 static int handle_mwait(struct kvm_vcpu *vcpu)
5482 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5483 return handle_nop(vcpu);
5486 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5488 kvm_queue_exception(vcpu, UD_VECTOR);
5492 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5497 static int handle_monitor(struct kvm_vcpu *vcpu)
5499 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5500 return handle_nop(vcpu);
5503 static int handle_invpcid(struct kvm_vcpu *vcpu)
5505 u32 vmx_instruction_info;
5513 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5514 kvm_queue_exception(vcpu, UD_VECTOR);
5518 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5519 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5522 kvm_inject_gp(vcpu, 0);
5526 /* According to the Intel instruction reference, the memory operand
5527 * is read even if it isn't needed (e.g., for type==all)
5529 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5530 vmx_instruction_info, false,
5531 sizeof(operand), &gva))
5534 return kvm_handle_invpcid(vcpu, type, gva);
5537 static int handle_pml_full(struct kvm_vcpu *vcpu)
5539 unsigned long exit_qualification;
5541 trace_kvm_pml_full(vcpu->vcpu_id);
5543 exit_qualification = vmx_get_exit_qual(vcpu);
5546 * PML buffer FULL happened while executing iret from NMI,
5547 * "blocked by NMI" bit has to be set before next VM entry.
5549 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5551 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5552 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5553 GUEST_INTR_STATE_NMI);
5556 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5557 * here.., and there's no userspace involvement needed for PML.
5562 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5564 struct vcpu_vmx *vmx = to_vmx(vcpu);
5566 if (!vmx->req_immediate_exit &&
5567 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5568 kvm_lapic_expired_hv_timer(vcpu);
5569 return EXIT_FASTPATH_REENTER_GUEST;
5572 return EXIT_FASTPATH_NONE;
5575 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5577 handle_fastpath_preemption_timer(vcpu);
5582 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5583 * are overwritten by nested_vmx_setup() when nested=1.
5585 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5587 kvm_queue_exception(vcpu, UD_VECTOR);
5591 static int handle_encls(struct kvm_vcpu *vcpu)
5594 * SGX virtualization is not yet supported. There is no software
5595 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5596 * to prevent the guest from executing ENCLS.
5598 kvm_queue_exception(vcpu, UD_VECTOR);
5603 * The exit handlers return 1 if the exit was handled fully and guest execution
5604 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5605 * to be done to userspace and return 0.
5607 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5608 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5609 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5610 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5611 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5612 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5613 [EXIT_REASON_CR_ACCESS] = handle_cr,
5614 [EXIT_REASON_DR_ACCESS] = handle_dr,
5615 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5616 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5617 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
5618 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
5619 [EXIT_REASON_HLT] = kvm_emulate_halt,
5620 [EXIT_REASON_INVD] = handle_invd,
5621 [EXIT_REASON_INVLPG] = handle_invlpg,
5622 [EXIT_REASON_RDPMC] = handle_rdpmc,
5623 [EXIT_REASON_VMCALL] = handle_vmcall,
5624 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5625 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5626 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5627 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5628 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5629 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5630 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5631 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5632 [EXIT_REASON_VMON] = handle_vmx_instruction,
5633 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5634 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5635 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5636 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5637 [EXIT_REASON_WBINVD] = handle_wbinvd,
5638 [EXIT_REASON_XSETBV] = handle_xsetbv,
5639 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5640 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5641 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5642 [EXIT_REASON_LDTR_TR] = handle_desc,
5643 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5644 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5645 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5646 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5647 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5648 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5649 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5650 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5651 [EXIT_REASON_RDRAND] = handle_invalid_op,
5652 [EXIT_REASON_RDSEED] = handle_invalid_op,
5653 [EXIT_REASON_PML_FULL] = handle_pml_full,
5654 [EXIT_REASON_INVPCID] = handle_invpcid,
5655 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5656 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5657 [EXIT_REASON_ENCLS] = handle_encls,
5660 static const int kvm_vmx_max_exit_handlers =
5661 ARRAY_SIZE(kvm_vmx_exit_handlers);
5663 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5665 *info1 = vmx_get_exit_qual(vcpu);
5666 *info2 = vmx_get_intr_info(vcpu);
5669 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5672 __free_page(vmx->pml_pg);
5677 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5679 struct vcpu_vmx *vmx = to_vmx(vcpu);
5683 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5685 /* Do nothing if PML buffer is empty */
5686 if (pml_idx == (PML_ENTITY_NUM - 1))
5689 /* PML index always points to next available PML buffer entity */
5690 if (pml_idx >= PML_ENTITY_NUM)
5695 pml_buf = page_address(vmx->pml_pg);
5696 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5699 gpa = pml_buf[pml_idx];
5700 WARN_ON(gpa & (PAGE_SIZE - 1));
5701 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5704 /* reset PML index */
5705 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5709 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5710 * Called before reporting dirty_bitmap to userspace.
5712 static void kvm_flush_pml_buffers(struct kvm *kvm)
5715 struct kvm_vcpu *vcpu;
5717 * We only need to kick vcpu out of guest mode here, as PML buffer
5718 * is flushed at beginning of all VMEXITs, and it's obvious that only
5719 * vcpus running in guest are possible to have unflushed GPAs in PML
5722 kvm_for_each_vcpu(i, vcpu, kvm)
5723 kvm_vcpu_kick(vcpu);
5726 static void vmx_dump_sel(char *name, uint32_t sel)
5728 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5729 name, vmcs_read16(sel),
5730 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5731 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5732 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5735 static void vmx_dump_dtsel(char *name, uint32_t limit)
5737 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5738 name, vmcs_read32(limit),
5739 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5742 void dump_vmcs(void)
5744 u32 vmentry_ctl, vmexit_ctl;
5745 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5749 if (!dump_invalid_vmcs) {
5750 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5754 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5755 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5756 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5757 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5758 cr4 = vmcs_readl(GUEST_CR4);
5759 efer = vmcs_read64(GUEST_IA32_EFER);
5760 secondary_exec_control = 0;
5761 if (cpu_has_secondary_exec_ctrls())
5762 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5764 pr_err("*** Guest State ***\n");
5765 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5766 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5767 vmcs_readl(CR0_GUEST_HOST_MASK));
5768 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5769 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5770 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5771 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5772 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5774 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5775 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5776 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5777 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5779 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5780 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5781 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5782 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5783 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5784 vmcs_readl(GUEST_SYSENTER_ESP),
5785 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5786 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5787 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5788 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5789 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5790 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5791 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5792 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5793 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5794 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5795 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5796 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5797 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5798 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5799 efer, vmcs_read64(GUEST_IA32_PAT));
5800 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5801 vmcs_read64(GUEST_IA32_DEBUGCTL),
5802 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5803 if (cpu_has_load_perf_global_ctrl() &&
5804 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5805 pr_err("PerfGlobCtl = 0x%016llx\n",
5806 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5807 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5808 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5809 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5810 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5811 vmcs_read32(GUEST_ACTIVITY_STATE));
5812 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5813 pr_err("InterruptStatus = %04x\n",
5814 vmcs_read16(GUEST_INTR_STATUS));
5816 pr_err("*** Host State ***\n");
5817 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5818 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5819 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5820 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5821 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5822 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5823 vmcs_read16(HOST_TR_SELECTOR));
5824 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5825 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5826 vmcs_readl(HOST_TR_BASE));
5827 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5828 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5829 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5830 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5831 vmcs_readl(HOST_CR4));
5832 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5833 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5834 vmcs_read32(HOST_IA32_SYSENTER_CS),
5835 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5836 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5837 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5838 vmcs_read64(HOST_IA32_EFER),
5839 vmcs_read64(HOST_IA32_PAT));
5840 if (cpu_has_load_perf_global_ctrl() &&
5841 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5842 pr_err("PerfGlobCtl = 0x%016llx\n",
5843 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5845 pr_err("*** Control State ***\n");
5846 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5847 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5848 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5849 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5850 vmcs_read32(EXCEPTION_BITMAP),
5851 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5852 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5853 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5854 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5855 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5856 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5857 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5858 vmcs_read32(VM_EXIT_INTR_INFO),
5859 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5860 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5861 pr_err(" reason=%08x qualification=%016lx\n",
5862 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5863 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5864 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5865 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5866 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5867 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5868 pr_err("TSC Multiplier = 0x%016llx\n",
5869 vmcs_read64(TSC_MULTIPLIER));
5870 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5871 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5872 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5873 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5875 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5876 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5877 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5878 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5880 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5881 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5882 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5883 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5884 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5885 pr_err("PLE Gap=%08x Window=%08x\n",
5886 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5887 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5888 pr_err("Virtual processor ID = 0x%04x\n",
5889 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5893 * The guest has exited. See if we can fix it or if we need userspace
5896 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5898 struct vcpu_vmx *vmx = to_vmx(vcpu);
5899 u32 exit_reason = vmx->exit_reason;
5900 u32 vectoring_info = vmx->idt_vectoring_info;
5903 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5904 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5905 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5906 * mode as if vcpus is in root mode, the PML buffer must has been
5910 vmx_flush_pml_buffer(vcpu);
5913 * We should never reach this point with a pending nested VM-Enter, and
5914 * more specifically emulation of L2 due to invalid guest state (see
5915 * below) should never happen as that means we incorrectly allowed a
5916 * nested VM-Enter with an invalid vmcs12.
5918 WARN_ON_ONCE(vmx->nested.nested_run_pending);
5920 /* If guest state is invalid, start emulating */
5921 if (vmx->emulation_required)
5922 return handle_invalid_guest_state(vcpu);
5924 if (is_guest_mode(vcpu)) {
5926 * The host physical addresses of some pages of guest memory
5927 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5928 * Page). The CPU may write to these pages via their host
5929 * physical address while L2 is running, bypassing any
5930 * address-translation-based dirty tracking (e.g. EPT write
5933 * Mark them dirty on every exit from L2 to prevent them from
5934 * getting out of sync with dirty tracking.
5936 nested_mark_vmcs12_pages_dirty(vcpu);
5938 if (nested_vmx_reflect_vmexit(vcpu))
5942 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5944 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5945 vcpu->run->fail_entry.hardware_entry_failure_reason
5947 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5951 if (unlikely(vmx->fail)) {
5953 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5954 vcpu->run->fail_entry.hardware_entry_failure_reason
5955 = vmcs_read32(VM_INSTRUCTION_ERROR);
5956 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5962 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5963 * delivery event since it indicates guest is accessing MMIO.
5964 * The vm-exit can be triggered again after return to guest that
5965 * will cause infinite loop.
5967 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5968 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5969 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5970 exit_reason != EXIT_REASON_PML_FULL &&
5971 exit_reason != EXIT_REASON_APIC_ACCESS &&
5972 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5973 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5974 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5975 vcpu->run->internal.ndata = 3;
5976 vcpu->run->internal.data[0] = vectoring_info;
5977 vcpu->run->internal.data[1] = exit_reason;
5978 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5979 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5980 vcpu->run->internal.ndata++;
5981 vcpu->run->internal.data[3] =
5982 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5984 vcpu->run->internal.data[vcpu->run->internal.ndata++] =
5985 vcpu->arch.last_vmentry_cpu;
5989 if (unlikely(!enable_vnmi &&
5990 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5991 if (!vmx_interrupt_blocked(vcpu)) {
5992 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5993 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5994 vcpu->arch.nmi_pending) {
5996 * This CPU don't support us in finding the end of an
5997 * NMI-blocked window if the guest runs with IRQs
5998 * disabled. So we pull the trigger after 1 s of
5999 * futile waiting, but inform the user about this.
6001 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6002 "state on VCPU %d after 1 s timeout\n",
6003 __func__, vcpu->vcpu_id);
6004 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6008 if (exit_fastpath != EXIT_FASTPATH_NONE)
6011 if (exit_reason >= kvm_vmx_max_exit_handlers)
6012 goto unexpected_vmexit;
6013 #ifdef CONFIG_RETPOLINE
6014 if (exit_reason == EXIT_REASON_MSR_WRITE)
6015 return kvm_emulate_wrmsr(vcpu);
6016 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
6017 return handle_preemption_timer(vcpu);
6018 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
6019 return handle_interrupt_window(vcpu);
6020 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6021 return handle_external_interrupt(vcpu);
6022 else if (exit_reason == EXIT_REASON_HLT)
6023 return kvm_emulate_halt(vcpu);
6024 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
6025 return handle_ept_misconfig(vcpu);
6028 exit_reason = array_index_nospec(exit_reason,
6029 kvm_vmx_max_exit_handlers);
6030 if (!kvm_vmx_exit_handlers[exit_reason])
6031 goto unexpected_vmexit;
6033 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6036 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
6038 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6039 vcpu->run->internal.suberror =
6040 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6041 vcpu->run->internal.ndata = 2;
6042 vcpu->run->internal.data[0] = exit_reason;
6043 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6048 * Software based L1D cache flush which is used when microcode providing
6049 * the cache control MSR is not loaded.
6051 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6052 * flush it is required to read in 64 KiB because the replacement algorithm
6053 * is not exactly LRU. This could be sized at runtime via topology
6054 * information but as all relevant affected CPUs have 32KiB L1D cache size
6055 * there is no point in doing so.
6057 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6059 int size = PAGE_SIZE << L1D_CACHE_ORDER;
6062 * This code is only executed when the the flush mode is 'cond' or
6065 if (static_branch_likely(&vmx_l1d_flush_cond)) {
6069 * Clear the per-vcpu flush bit, it gets set again
6070 * either from vcpu_run() or from one of the unsafe
6073 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6074 vcpu->arch.l1tf_flush_l1d = false;
6077 * Clear the per-cpu flush bit, it gets set again from
6078 * the interrupt handlers.
6080 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6081 kvm_clear_cpu_l1tf_flush_l1d();
6087 vcpu->stat.l1d_flush++;
6089 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6090 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6095 /* First ensure the pages are in the TLB */
6096 "xorl %%eax, %%eax\n"
6097 ".Lpopulate_tlb:\n\t"
6098 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6099 "addl $4096, %%eax\n\t"
6100 "cmpl %%eax, %[size]\n\t"
6101 "jne .Lpopulate_tlb\n\t"
6102 "xorl %%eax, %%eax\n\t"
6104 /* Now fill the cache */
6105 "xorl %%eax, %%eax\n"
6107 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6108 "addl $64, %%eax\n\t"
6109 "cmpl %%eax, %[size]\n\t"
6110 "jne .Lfill_cache\n\t"
6112 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6114 : "eax", "ebx", "ecx", "edx");
6117 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6119 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6122 if (is_guest_mode(vcpu) &&
6123 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6126 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6127 if (is_guest_mode(vcpu))
6128 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6130 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6133 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6135 struct vcpu_vmx *vmx = to_vmx(vcpu);
6136 u32 sec_exec_control;
6138 if (!lapic_in_kernel(vcpu))
6141 if (!flexpriority_enabled &&
6142 !cpu_has_vmx_virtualize_x2apic_mode())
6145 /* Postpone execution until vmcs01 is the current VMCS. */
6146 if (is_guest_mode(vcpu)) {
6147 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6151 sec_exec_control = secondary_exec_controls_get(vmx);
6152 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6153 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6155 switch (kvm_get_apic_mode(vcpu)) {
6156 case LAPIC_MODE_INVALID:
6157 WARN_ONCE(true, "Invalid local APIC state");
6158 case LAPIC_MODE_DISABLED:
6160 case LAPIC_MODE_XAPIC:
6161 if (flexpriority_enabled) {
6163 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6164 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6167 * Flush the TLB, reloading the APIC access page will
6168 * only do so if its physical address has changed, but
6169 * the guest may have inserted a non-APIC mapping into
6170 * the TLB while the APIC access page was disabled.
6172 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6175 case LAPIC_MODE_X2APIC:
6176 if (cpu_has_vmx_virtualize_x2apic_mode())
6178 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6181 secondary_exec_controls_set(vmx, sec_exec_control);
6183 vmx_update_msr_bitmap(vcpu);
6186 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6190 /* Defer reload until vmcs01 is the current VMCS. */
6191 if (is_guest_mode(vcpu)) {
6192 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6196 if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6197 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6200 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6201 if (is_error_page(page))
6204 vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6205 vmx_flush_tlb_current(vcpu);
6208 * Do not pin apic access page in memory, the MMU notifier
6209 * will call us again if it is migrated or swapped out.
6214 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6222 status = vmcs_read16(GUEST_INTR_STATUS);
6224 if (max_isr != old) {
6226 status |= max_isr << 8;
6227 vmcs_write16(GUEST_INTR_STATUS, status);
6231 static void vmx_set_rvi(int vector)
6239 status = vmcs_read16(GUEST_INTR_STATUS);
6240 old = (u8)status & 0xff;
6241 if ((u8)vector != old) {
6243 status |= (u8)vector;
6244 vmcs_write16(GUEST_INTR_STATUS, status);
6248 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6251 * When running L2, updating RVI is only relevant when
6252 * vmcs12 virtual-interrupt-delivery enabled.
6253 * However, it can be enabled only when L1 also
6254 * intercepts external-interrupts and in that case
6255 * we should not update vmcs02 RVI but instead intercept
6256 * interrupt. Therefore, do nothing when running L2.
6258 if (!is_guest_mode(vcpu))
6259 vmx_set_rvi(max_irr);
6262 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6264 struct vcpu_vmx *vmx = to_vmx(vcpu);
6266 bool max_irr_updated;
6268 WARN_ON(!vcpu->arch.apicv_active);
6269 if (pi_test_on(&vmx->pi_desc)) {
6270 pi_clear_on(&vmx->pi_desc);
6272 * IOMMU can write to PID.ON, so the barrier matters even on UP.
6273 * But on x86 this is just a compiler barrier anyway.
6275 smp_mb__after_atomic();
6277 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6280 * If we are running L2 and L1 has a new pending interrupt
6281 * which can be injected, we should re-evaluate
6282 * what should be done with this new L1 interrupt.
6283 * If L1 intercepts external-interrupts, we should
6284 * exit from L2 to L1. Otherwise, interrupt should be
6285 * delivered directly to L2.
6287 if (is_guest_mode(vcpu) && max_irr_updated) {
6288 if (nested_exit_on_intr(vcpu))
6289 kvm_vcpu_exiting_guest_mode(vcpu);
6291 kvm_make_request(KVM_REQ_EVENT, vcpu);
6294 max_irr = kvm_lapic_find_highest_irr(vcpu);
6296 vmx_hwapic_irr_update(vcpu, max_irr);
6300 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6302 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6304 return pi_test_on(pi_desc) ||
6305 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6308 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6310 if (!kvm_vcpu_apicv_active(vcpu))
6313 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6314 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6315 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6316 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6319 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6321 struct vcpu_vmx *vmx = to_vmx(vcpu);
6323 pi_clear_on(&vmx->pi_desc);
6324 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6327 void vmx_do_interrupt_nmi_irqoff(unsigned long entry);
6329 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu, u32 intr_info)
6331 unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK;
6332 gate_desc *desc = (gate_desc *)host_idt_base + vector;
6334 kvm_before_interrupt(vcpu);
6335 vmx_do_interrupt_nmi_irqoff(gate_offset(desc));
6336 kvm_after_interrupt(vcpu);
6339 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6341 u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6343 /* if exit due to PF check for async PF */
6344 if (is_page_fault(intr_info))
6345 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6346 /* Handle machine checks before interrupts are enabled */
6347 else if (is_machine_check(intr_info))
6348 kvm_machine_check();
6349 /* We need to handle NMIs before interrupts are enabled */
6350 else if (is_nmi(intr_info))
6351 handle_interrupt_nmi_irqoff(&vmx->vcpu, intr_info);
6354 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6356 u32 intr_info = vmx_get_intr_info(vcpu);
6358 if (WARN_ONCE(!is_external_intr(intr_info),
6359 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6362 handle_interrupt_nmi_irqoff(vcpu, intr_info);
6365 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6367 struct vcpu_vmx *vmx = to_vmx(vcpu);
6369 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6370 handle_external_interrupt_irqoff(vcpu);
6371 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6372 handle_exception_nmi_irqoff(vmx);
6375 static bool vmx_has_emulated_msr(u32 index)
6378 case MSR_IA32_SMBASE:
6380 * We cannot do SMM unless we can run the guest in big
6383 return enable_unrestricted_guest || emulate_invalid_guest_state;
6384 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6386 case MSR_AMD64_VIRT_SPEC_CTRL:
6387 /* This is AMD only. */
6394 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6399 bool idtv_info_valid;
6401 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6404 if (vmx->loaded_vmcs->nmi_known_unmasked)
6407 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6408 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6409 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6411 * SDM 3: 27.7.1.2 (September 2008)
6412 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6413 * a guest IRET fault.
6414 * SDM 3: 23.2.2 (September 2008)
6415 * Bit 12 is undefined in any of the following cases:
6416 * If the VM exit sets the valid bit in the IDT-vectoring
6417 * information field.
6418 * If the VM exit is due to a double fault.
6420 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6421 vector != DF_VECTOR && !idtv_info_valid)
6422 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6423 GUEST_INTR_STATE_NMI);
6425 vmx->loaded_vmcs->nmi_known_unmasked =
6426 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6427 & GUEST_INTR_STATE_NMI);
6428 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6429 vmx->loaded_vmcs->vnmi_blocked_time +=
6430 ktime_to_ns(ktime_sub(ktime_get(),
6431 vmx->loaded_vmcs->entry_time));
6434 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6435 u32 idt_vectoring_info,
6436 int instr_len_field,
6437 int error_code_field)
6441 bool idtv_info_valid;
6443 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6445 vcpu->arch.nmi_injected = false;
6446 kvm_clear_exception_queue(vcpu);
6447 kvm_clear_interrupt_queue(vcpu);
6449 if (!idtv_info_valid)
6452 kvm_make_request(KVM_REQ_EVENT, vcpu);
6454 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6455 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6458 case INTR_TYPE_NMI_INTR:
6459 vcpu->arch.nmi_injected = true;
6461 * SDM 3: 27.7.1.2 (September 2008)
6462 * Clear bit "block by NMI" before VM entry if a NMI
6465 vmx_set_nmi_mask(vcpu, false);
6467 case INTR_TYPE_SOFT_EXCEPTION:
6468 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6470 case INTR_TYPE_HARD_EXCEPTION:
6471 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6472 u32 err = vmcs_read32(error_code_field);
6473 kvm_requeue_exception_e(vcpu, vector, err);
6475 kvm_requeue_exception(vcpu, vector);
6477 case INTR_TYPE_SOFT_INTR:
6478 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6480 case INTR_TYPE_EXT_INTR:
6481 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6488 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6490 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6491 VM_EXIT_INSTRUCTION_LEN,
6492 IDT_VECTORING_ERROR_CODE);
6495 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6497 __vmx_complete_interrupts(vcpu,
6498 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6499 VM_ENTRY_INSTRUCTION_LEN,
6500 VM_ENTRY_EXCEPTION_ERROR_CODE);
6502 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6505 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6508 struct perf_guest_switch_msr *msrs;
6510 msrs = perf_guest_get_msrs(&nr_msrs);
6515 for (i = 0; i < nr_msrs; i++)
6516 if (msrs[i].host == msrs[i].guest)
6517 clear_atomic_switch_msr(vmx, msrs[i].msr);
6519 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6520 msrs[i].host, false);
6523 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6525 struct vcpu_vmx *vmx = to_vmx(vcpu);
6529 if (vmx->req_immediate_exit) {
6530 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6531 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6532 } else if (vmx->hv_deadline_tsc != -1) {
6534 if (vmx->hv_deadline_tsc > tscl)
6535 /* set_hv_timer ensures the delta fits in 32-bits */
6536 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6537 cpu_preemption_timer_multi);
6541 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6542 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6543 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6544 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6545 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6549 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6551 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6552 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6553 vmcs_writel(HOST_RSP, host_rsp);
6557 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6559 switch (to_vmx(vcpu)->exit_reason) {
6560 case EXIT_REASON_MSR_WRITE:
6561 return handle_fastpath_set_msr_irqoff(vcpu);
6562 case EXIT_REASON_PREEMPTION_TIMER:
6563 return handle_fastpath_preemption_timer(vcpu);
6565 return EXIT_FASTPATH_NONE;
6569 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6571 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6572 struct vcpu_vmx *vmx)
6575 * VMENTER enables interrupts (host state), but the kernel state is
6576 * interrupts disabled when this is invoked. Also tell RCU about
6577 * it. This is the same logic as for exit_to_user_mode().
6579 * This ensures that e.g. latency analysis on the host observes
6580 * guest mode as interrupt enabled.
6582 * guest_enter_irqoff() informs context tracking about the
6583 * transition to guest mode and if enabled adjusts RCU state
6586 instrumentation_begin();
6587 trace_hardirqs_on_prepare();
6588 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
6589 instrumentation_end();
6591 guest_enter_irqoff();
6592 lockdep_hardirqs_on(CALLER_ADDR0);
6594 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6595 if (static_branch_unlikely(&vmx_l1d_should_flush))
6596 vmx_l1d_flush(vcpu);
6597 else if (static_branch_unlikely(&mds_user_clear))
6598 mds_clear_cpu_buffers();
6600 if (vcpu->arch.cr2 != native_read_cr2())
6601 native_write_cr2(vcpu->arch.cr2);
6603 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6604 vmx->loaded_vmcs->launched);
6606 vcpu->arch.cr2 = native_read_cr2();
6609 * VMEXIT disables interrupts (host state), but tracing and lockdep
6610 * have them in state 'on' as recorded before entering guest mode.
6611 * Same as enter_from_user_mode().
6613 * guest_exit_irqoff() restores host context and reinstates RCU if
6614 * enabled and required.
6616 * This needs to be done before the below as native_read_msr()
6617 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
6618 * into world and some more.
6620 lockdep_hardirqs_off(CALLER_ADDR0);
6621 guest_exit_irqoff();
6623 instrumentation_begin();
6624 trace_hardirqs_off_finish();
6625 instrumentation_end();
6628 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6630 fastpath_t exit_fastpath;
6631 struct vcpu_vmx *vmx = to_vmx(vcpu);
6632 unsigned long cr3, cr4;
6635 /* Record the guest's net vcpu time for enforced NMI injections. */
6636 if (unlikely(!enable_vnmi &&
6637 vmx->loaded_vmcs->soft_vnmi_blocked))
6638 vmx->loaded_vmcs->entry_time = ktime_get();
6640 /* Don't enter VMX if guest state is invalid, let the exit handler
6641 start emulation until we arrive back to a valid state */
6642 if (vmx->emulation_required)
6643 return EXIT_FASTPATH_NONE;
6645 if (vmx->ple_window_dirty) {
6646 vmx->ple_window_dirty = false;
6647 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6651 * We did this in prepare_switch_to_guest, because it needs to
6652 * be within srcu_read_lock.
6654 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6656 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6657 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6658 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6659 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6661 cr3 = __get_current_cr3_fast();
6662 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6663 vmcs_writel(HOST_CR3, cr3);
6664 vmx->loaded_vmcs->host_state.cr3 = cr3;
6667 cr4 = cr4_read_shadow();
6668 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6669 vmcs_writel(HOST_CR4, cr4);
6670 vmx->loaded_vmcs->host_state.cr4 = cr4;
6673 /* When single-stepping over STI and MOV SS, we must clear the
6674 * corresponding interruptibility bits in the guest state. Otherwise
6675 * vmentry fails as it then expects bit 14 (BS) in pending debug
6676 * exceptions being set, but that's not correct for the guest debugging
6678 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6679 vmx_set_interrupt_shadow(vcpu, 0);
6681 kvm_load_guest_xsave_state(vcpu);
6683 pt_guest_enter(vmx);
6685 atomic_switch_perf_msrs(vmx);
6687 if (enable_preemption_timer)
6688 vmx_update_hv_timer(vcpu);
6690 kvm_wait_lapic_expire(vcpu);
6693 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6694 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6695 * is no need to worry about the conditional branch over the wrmsr
6696 * being speculatively taken.
6698 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6700 /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6701 vmx_vcpu_enter_exit(vcpu, vmx);
6704 * We do not use IBRS in the kernel. If this vCPU has used the
6705 * SPEC_CTRL MSR it may have left it on; save the value and
6706 * turn it off. This is much more efficient than blindly adding
6707 * it to the atomic save/restore list. Especially as the former
6708 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6710 * For non-nested case:
6711 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6715 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6718 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6719 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6721 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6723 /* All fields are clean at this point */
6724 if (static_branch_unlikely(&enable_evmcs))
6725 current_evmcs->hv_clean_fields |=
6726 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6728 if (static_branch_unlikely(&enable_evmcs))
6729 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6731 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6732 if (vmx->host_debugctlmsr)
6733 update_debugctlmsr(vmx->host_debugctlmsr);
6735 #ifndef CONFIG_X86_64
6737 * The sysexit path does not restore ds/es, so we must set them to
6738 * a reasonable value ourselves.
6740 * We can't defer this to vmx_prepare_switch_to_host() since that
6741 * function may be executed in interrupt context, which saves and
6742 * restore segments around it, nullifying its effect.
6744 loadsegment(ds, __USER_DS);
6745 loadsegment(es, __USER_DS);
6748 vmx_register_cache_reset(vcpu);
6752 kvm_load_host_xsave_state(vcpu);
6754 vmx->nested.nested_run_pending = 0;
6755 vmx->idt_vectoring_info = 0;
6757 if (unlikely(vmx->fail)) {
6758 vmx->exit_reason = 0xdead;
6759 return EXIT_FASTPATH_NONE;
6762 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6763 if (unlikely((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY))
6764 kvm_machine_check();
6766 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6768 if (unlikely(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6769 return EXIT_FASTPATH_NONE;
6771 vmx->loaded_vmcs->launched = 1;
6772 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6774 vmx_recover_nmi_blocking(vmx);
6775 vmx_complete_interrupts(vmx);
6777 if (is_guest_mode(vcpu))
6778 return EXIT_FASTPATH_NONE;
6780 exit_fastpath = vmx_exit_handlers_fastpath(vcpu);
6781 if (exit_fastpath == EXIT_FASTPATH_REENTER_GUEST) {
6782 if (!kvm_vcpu_exit_request(vcpu)) {
6784 * FIXME: this goto should be a loop in vcpu_enter_guest,
6785 * but it would incur the cost of a retpoline for now.
6786 * Revisit once static calls are available.
6788 if (vcpu->arch.apicv_active)
6789 vmx_sync_pir_to_irr(vcpu);
6792 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
6795 return exit_fastpath;
6798 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6800 struct vcpu_vmx *vmx = to_vmx(vcpu);
6803 vmx_destroy_pml_buffer(vmx);
6804 free_vpid(vmx->vpid);
6805 nested_vmx_free_vcpu(vcpu);
6806 free_loaded_vmcs(vmx->loaded_vmcs);
6809 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6811 struct vcpu_vmx *vmx;
6812 unsigned long *msr_bitmap;
6815 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6820 vmx->vpid = allocate_vpid();
6823 * If PML is turned on, failure on enabling PML just results in failure
6824 * of creating the vcpu, therefore we can simplify PML logic (by
6825 * avoiding dealing with cases, such as enabling PML partially on vcpus
6826 * for the guest), etc.
6829 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6834 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
6836 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6837 u32 index = vmx_msr_index[i];
6838 u32 data_low, data_high;
6841 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6843 if (wrmsr_safe(index, data_low, data_high) < 0)
6846 vmx->guest_msrs[j].index = i;
6847 vmx->guest_msrs[j].data = 0;
6849 case MSR_IA32_TSX_CTRL:
6851 * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6852 * let's avoid changing CPUID bits under the host
6855 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6858 vmx->guest_msrs[j].mask = -1ull;
6864 err = alloc_loaded_vmcs(&vmx->vmcs01);
6868 msr_bitmap = vmx->vmcs01.msr_bitmap;
6869 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6870 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6871 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6872 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6873 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6874 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6875 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6876 if (kvm_cstate_in_guest(vcpu->kvm)) {
6877 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6878 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6879 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6880 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6882 vmx->msr_bitmap_mode = 0;
6884 vmx->loaded_vmcs = &vmx->vmcs01;
6886 vmx_vcpu_load(vcpu, cpu);
6891 if (cpu_need_virtualize_apic_accesses(vcpu)) {
6892 err = alloc_apic_access_page(vcpu->kvm);
6897 if (enable_ept && !enable_unrestricted_guest) {
6898 err = init_rmode_identity_map(vcpu->kvm);
6904 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
6906 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6908 vmx->nested.posted_intr_nv = -1;
6909 vmx->nested.current_vmptr = -1ull;
6911 vcpu->arch.microcode_version = 0x100000000ULL;
6912 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6915 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6916 * or POSTED_INTR_WAKEUP_VECTOR.
6918 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6919 vmx->pi_desc.sn = 1;
6921 vmx->ept_pointer = INVALID_PAGE;
6926 free_loaded_vmcs(vmx->loaded_vmcs);
6928 vmx_destroy_pml_buffer(vmx);
6930 free_vpid(vmx->vpid);
6934 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6935 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6937 static int vmx_vm_init(struct kvm *kvm)
6939 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6942 kvm->arch.pause_in_guest = true;
6944 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6945 switch (l1tf_mitigation) {
6946 case L1TF_MITIGATION_OFF:
6947 case L1TF_MITIGATION_FLUSH_NOWARN:
6948 /* 'I explicitly don't care' is set */
6950 case L1TF_MITIGATION_FLUSH:
6951 case L1TF_MITIGATION_FLUSH_NOSMT:
6952 case L1TF_MITIGATION_FULL:
6954 * Warn upon starting the first VM in a potentially
6955 * insecure environment.
6957 if (sched_smt_active())
6958 pr_warn_once(L1TF_MSG_SMT);
6959 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6960 pr_warn_once(L1TF_MSG_L1D);
6962 case L1TF_MITIGATION_FULL_FORCE:
6963 /* Flush is enforced */
6967 kvm_apicv_init(kvm, enable_apicv);
6971 static int __init vmx_check_processor_compat(void)
6973 struct vmcs_config vmcs_conf;
6974 struct vmx_capability vmx_cap;
6976 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6977 !this_cpu_has(X86_FEATURE_VMX)) {
6978 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6982 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6985 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6986 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6987 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6988 smp_processor_id());
6994 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6999 /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
7000 * memory aliases with conflicting memory types and sometimes MCEs.
7001 * We have to be careful as to what are honored and when.
7003 * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to
7004 * UC. The effective memory type is UC or WC depending on guest PAT.
7005 * This was historically the source of MCEs and we want to be
7008 * When there is no need to deal with noncoherent DMA (e.g., no VT-d
7009 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The
7010 * EPT memory type is set to WB. The effective memory type is forced
7013 * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The
7014 * EPT memory type is used to emulate guest CD/MTRR.
7018 cache = MTRR_TYPE_UNCACHABLE;
7022 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
7023 ipat = VMX_EPT_IPAT_BIT;
7024 cache = MTRR_TYPE_WRBACK;
7028 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
7029 ipat = VMX_EPT_IPAT_BIT;
7030 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
7031 cache = MTRR_TYPE_WRBACK;
7033 cache = MTRR_TYPE_UNCACHABLE;
7037 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
7040 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
7043 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
7046 * These bits in the secondary execution controls field
7047 * are dynamic, the others are mostly based on the hypervisor
7048 * architecture and the guest's CPUID. Do not touch the
7052 SECONDARY_EXEC_SHADOW_VMCS |
7053 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7054 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7055 SECONDARY_EXEC_DESC;
7057 u32 new_ctl = vmx->secondary_exec_control;
7058 u32 cur_ctl = secondary_exec_controls_get(vmx);
7060 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7064 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7065 * (indicating "allowed-1") if they are supported in the guest's CPUID.
7067 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7069 struct vcpu_vmx *vmx = to_vmx(vcpu);
7070 struct kvm_cpuid_entry2 *entry;
7072 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7073 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7075 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
7076 if (entry && (entry->_reg & (_cpuid_mask))) \
7077 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
7080 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7081 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME));
7082 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME));
7083 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC));
7084 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE));
7085 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE));
7086 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE));
7087 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE));
7088 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE));
7089 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR));
7090 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7091 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX));
7092 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX));
7093 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID));
7094 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE));
7096 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7097 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE));
7098 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP));
7099 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP));
7100 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU));
7101 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP));
7102 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57));
7104 #undef cr4_fixed1_update
7107 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7109 struct vcpu_vmx *vmx = to_vmx(vcpu);
7111 if (kvm_mpx_supported()) {
7112 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7115 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7116 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7118 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7119 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7124 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7126 struct vcpu_vmx *vmx = to_vmx(vcpu);
7127 struct kvm_cpuid_entry2 *best = NULL;
7130 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7131 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7134 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7135 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7136 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7137 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7140 /* Get the number of configurable Address Ranges for filtering */
7141 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7142 PT_CAP_num_address_ranges);
7144 /* Initialize and clear the no dependency bits */
7145 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7146 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7149 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7150 * will inject an #GP
7152 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7153 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7156 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7157 * PSBFreq can be set
7159 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7160 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7161 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7164 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7165 * MTCFreq can be set
7167 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7168 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7169 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7171 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7172 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7173 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7176 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7177 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7178 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7180 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7181 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7182 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7184 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7185 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7186 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7188 /* unmask address range configure area */
7189 for (i = 0; i < vmx->pt_desc.addr_range; i++)
7190 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7193 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7195 struct vcpu_vmx *vmx = to_vmx(vcpu);
7197 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7198 vcpu->arch.xsaves_enabled = false;
7200 if (cpu_has_secondary_exec_ctrls()) {
7201 vmx_compute_secondary_exec_control(vmx);
7202 vmcs_set_secondary_exec_control(vmx);
7205 if (nested_vmx_allowed(vcpu))
7206 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7207 FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7208 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7210 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7211 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7212 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7214 if (nested_vmx_allowed(vcpu)) {
7215 nested_vmx_cr_fixed1_bits_update(vcpu);
7216 nested_vmx_entry_exit_ctls_update(vcpu);
7219 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7220 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7221 update_intel_pt_cfg(vcpu);
7223 if (boot_cpu_has(X86_FEATURE_RTM)) {
7224 struct shared_msr_entry *msr;
7225 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7227 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7228 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7233 static __init void vmx_set_cpu_caps(void)
7239 kvm_cpu_cap_set(X86_FEATURE_VMX);
7242 if (kvm_mpx_supported())
7243 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7244 if (cpu_has_vmx_invpcid())
7245 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
7246 if (vmx_pt_mode_is_host_guest())
7247 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7249 if (vmx_umip_emulated())
7250 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7254 if (!vmx_xsaves_supported())
7255 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7257 /* CPUID 0x80000001 */
7258 if (!cpu_has_vmx_rdtscp())
7259 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7261 if (vmx_waitpkg_supported())
7262 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7265 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7267 to_vmx(vcpu)->req_immediate_exit = true;
7270 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7271 struct x86_instruction_info *info)
7273 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7274 unsigned short port;
7278 if (info->intercept == x86_intercept_in ||
7279 info->intercept == x86_intercept_ins) {
7280 port = info->src_val;
7281 size = info->dst_bytes;
7283 port = info->dst_val;
7284 size = info->src_bytes;
7288 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7289 * VM-exits depend on the 'unconditional IO exiting' VM-execution
7292 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7294 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7295 intercept = nested_cpu_has(vmcs12,
7296 CPU_BASED_UNCOND_IO_EXITING);
7298 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7300 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7301 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7304 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7305 struct x86_instruction_info *info,
7306 enum x86_intercept_stage stage,
7307 struct x86_exception *exception)
7309 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7311 switch (info->intercept) {
7313 * RDPID causes #UD if disabled through secondary execution controls.
7314 * Because it is marked as EmulateOnUD, we need to intercept it here.
7316 case x86_intercept_rdtscp:
7317 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7318 exception->vector = UD_VECTOR;
7319 exception->error_code_valid = false;
7320 return X86EMUL_PROPAGATE_FAULT;
7324 case x86_intercept_in:
7325 case x86_intercept_ins:
7326 case x86_intercept_out:
7327 case x86_intercept_outs:
7328 return vmx_check_intercept_io(vcpu, info);
7330 case x86_intercept_lgdt:
7331 case x86_intercept_lidt:
7332 case x86_intercept_lldt:
7333 case x86_intercept_ltr:
7334 case x86_intercept_sgdt:
7335 case x86_intercept_sidt:
7336 case x86_intercept_sldt:
7337 case x86_intercept_str:
7338 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7339 return X86EMUL_CONTINUE;
7341 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7344 /* TODO: check more intercepts... */
7349 return X86EMUL_UNHANDLEABLE;
7352 #ifdef CONFIG_X86_64
7353 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7354 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7355 u64 divisor, u64 *result)
7357 u64 low = a << shift, high = a >> (64 - shift);
7359 /* To avoid the overflow on divq */
7360 if (high >= divisor)
7363 /* Low hold the result, high hold rem which is discarded */
7364 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7365 "rm" (divisor), "0" (low), "1" (high));
7371 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7374 struct vcpu_vmx *vmx;
7375 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7376 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7380 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7381 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7382 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7383 ktimer->timer_advance_ns);
7385 if (delta_tsc > lapic_timer_advance_cycles)
7386 delta_tsc -= lapic_timer_advance_cycles;
7390 /* Convert to host delta tsc if tsc scaling is enabled */
7391 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7392 delta_tsc && u64_shl_div_u64(delta_tsc,
7393 kvm_tsc_scaling_ratio_frac_bits,
7394 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7398 * If the delta tsc can't fit in the 32 bit after the multi shift,
7399 * we can't use the preemption timer.
7400 * It's possible that it fits on later vmentries, but checking
7401 * on every vmentry is costly so we just use an hrtimer.
7403 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7406 vmx->hv_deadline_tsc = tscl + delta_tsc;
7407 *expired = !delta_tsc;
7411 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7413 to_vmx(vcpu)->hv_deadline_tsc = -1;
7417 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7419 if (!kvm_pause_in_guest(vcpu->kvm))
7420 shrink_ple_window(vcpu);
7423 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7424 struct kvm_memory_slot *slot)
7426 if (!kvm_dirty_log_manual_protect_and_init_set(kvm))
7427 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7428 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7431 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7432 struct kvm_memory_slot *slot)
7434 kvm_mmu_slot_set_dirty(kvm, slot);
7437 static void vmx_flush_log_dirty(struct kvm *kvm)
7439 kvm_flush_pml_buffers(kvm);
7442 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7443 struct kvm_memory_slot *memslot,
7444 gfn_t offset, unsigned long mask)
7446 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7449 static void __pi_post_block(struct kvm_vcpu *vcpu)
7451 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7452 struct pi_desc old, new;
7456 old.control = new.control = pi_desc->control;
7457 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7458 "Wakeup handler not enabled while the VCPU is blocked\n");
7460 dest = cpu_physical_id(vcpu->cpu);
7462 if (x2apic_enabled())
7465 new.ndst = (dest << 8) & 0xFF00;
7467 /* set 'NV' to 'notification vector' */
7468 new.nv = POSTED_INTR_VECTOR;
7469 } while (cmpxchg64(&pi_desc->control, old.control,
7470 new.control) != old.control);
7472 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7473 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7474 list_del(&vcpu->blocked_vcpu_list);
7475 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7476 vcpu->pre_pcpu = -1;
7481 * This routine does the following things for vCPU which is going
7482 * to be blocked if VT-d PI is enabled.
7483 * - Store the vCPU to the wakeup list, so when interrupts happen
7484 * we can find the right vCPU to wake up.
7485 * - Change the Posted-interrupt descriptor as below:
7486 * 'NDST' <-- vcpu->pre_pcpu
7487 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7488 * - If 'ON' is set during this process, which means at least one
7489 * interrupt is posted for this vCPU, we cannot block it, in
7490 * this case, return 1, otherwise, return 0.
7493 static int pi_pre_block(struct kvm_vcpu *vcpu)
7496 struct pi_desc old, new;
7497 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7499 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7500 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7501 !kvm_vcpu_apicv_active(vcpu))
7504 WARN_ON(irqs_disabled());
7505 local_irq_disable();
7506 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7507 vcpu->pre_pcpu = vcpu->cpu;
7508 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7509 list_add_tail(&vcpu->blocked_vcpu_list,
7510 &per_cpu(blocked_vcpu_on_cpu,
7512 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7516 old.control = new.control = pi_desc->control;
7518 WARN((pi_desc->sn == 1),
7519 "Warning: SN field of posted-interrupts "
7520 "is set before blocking\n");
7523 * Since vCPU can be preempted during this process,
7524 * vcpu->cpu could be different with pre_pcpu, we
7525 * need to set pre_pcpu as the destination of wakeup
7526 * notification event, then we can find the right vCPU
7527 * to wakeup in wakeup handler if interrupts happen
7528 * when the vCPU is in blocked state.
7530 dest = cpu_physical_id(vcpu->pre_pcpu);
7532 if (x2apic_enabled())
7535 new.ndst = (dest << 8) & 0xFF00;
7537 /* set 'NV' to 'wakeup vector' */
7538 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7539 } while (cmpxchg64(&pi_desc->control, old.control,
7540 new.control) != old.control);
7542 /* We should not block the vCPU if an interrupt is posted for it. */
7543 if (pi_test_on(pi_desc) == 1)
7544 __pi_post_block(vcpu);
7547 return (vcpu->pre_pcpu == -1);
7550 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7552 if (pi_pre_block(vcpu))
7555 if (kvm_lapic_hv_timer_in_use(vcpu))
7556 kvm_lapic_switch_to_sw_timer(vcpu);
7561 static void pi_post_block(struct kvm_vcpu *vcpu)
7563 if (vcpu->pre_pcpu == -1)
7566 WARN_ON(irqs_disabled());
7567 local_irq_disable();
7568 __pi_post_block(vcpu);
7572 static void vmx_post_block(struct kvm_vcpu *vcpu)
7574 if (kvm_x86_ops.set_hv_timer)
7575 kvm_lapic_switch_to_hv_timer(vcpu);
7577 pi_post_block(vcpu);
7581 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7584 * @host_irq: host irq of the interrupt
7585 * @guest_irq: gsi of the interrupt
7586 * @set: set or unset PI
7587 * returns 0 on success, < 0 on failure
7589 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7590 uint32_t guest_irq, bool set)
7592 struct kvm_kernel_irq_routing_entry *e;
7593 struct kvm_irq_routing_table *irq_rt;
7594 struct kvm_lapic_irq irq;
7595 struct kvm_vcpu *vcpu;
7596 struct vcpu_data vcpu_info;
7599 if (!kvm_arch_has_assigned_device(kvm) ||
7600 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7601 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7604 idx = srcu_read_lock(&kvm->irq_srcu);
7605 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7606 if (guest_irq >= irq_rt->nr_rt_entries ||
7607 hlist_empty(&irq_rt->map[guest_irq])) {
7608 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7609 guest_irq, irq_rt->nr_rt_entries);
7613 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7614 if (e->type != KVM_IRQ_ROUTING_MSI)
7617 * VT-d PI cannot support posting multicast/broadcast
7618 * interrupts to a vCPU, we still use interrupt remapping
7619 * for these kind of interrupts.
7621 * For lowest-priority interrupts, we only support
7622 * those with single CPU as the destination, e.g. user
7623 * configures the interrupts via /proc/irq or uses
7624 * irqbalance to make the interrupts single-CPU.
7626 * We will support full lowest-priority interrupt later.
7628 * In addition, we can only inject generic interrupts using
7629 * the PI mechanism, refuse to route others through it.
7632 kvm_set_msi_irq(kvm, e, &irq);
7633 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7634 !kvm_irq_is_postable(&irq)) {
7636 * Make sure the IRTE is in remapped mode if
7637 * we don't handle it in posted mode.
7639 ret = irq_set_vcpu_affinity(host_irq, NULL);
7642 "failed to back to remapped mode, irq: %u\n",
7650 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7651 vcpu_info.vector = irq.vector;
7653 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7654 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7657 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7659 ret = irq_set_vcpu_affinity(host_irq, NULL);
7662 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7670 srcu_read_unlock(&kvm->irq_srcu, idx);
7674 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7676 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7677 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7678 FEAT_CTL_LMCE_ENABLED;
7680 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7681 ~FEAT_CTL_LMCE_ENABLED;
7684 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7686 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7687 if (to_vmx(vcpu)->nested.nested_run_pending)
7689 return !is_smm(vcpu);
7692 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7694 struct vcpu_vmx *vmx = to_vmx(vcpu);
7696 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7697 if (vmx->nested.smm.guest_mode)
7698 nested_vmx_vmexit(vcpu, -1, 0, 0);
7700 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7701 vmx->nested.vmxon = false;
7702 vmx_clear_hlt(vcpu);
7706 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7708 struct vcpu_vmx *vmx = to_vmx(vcpu);
7711 if (vmx->nested.smm.vmxon) {
7712 vmx->nested.vmxon = true;
7713 vmx->nested.smm.vmxon = false;
7716 if (vmx->nested.smm.guest_mode) {
7717 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7721 vmx->nested.smm.guest_mode = false;
7726 static void enable_smi_window(struct kvm_vcpu *vcpu)
7728 /* RSM will cause a vmexit anyway. */
7731 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7733 return to_vmx(vcpu)->nested.vmxon;
7736 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7738 if (is_guest_mode(vcpu)) {
7739 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7741 if (hrtimer_try_to_cancel(timer) == 1)
7742 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7746 static void hardware_unsetup(void)
7749 nested_vmx_hardware_unsetup();
7754 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7756 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7757 BIT(APICV_INHIBIT_REASON_HYPERV);
7759 return supported & BIT(bit);
7762 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7763 .hardware_unsetup = hardware_unsetup,
7765 .hardware_enable = hardware_enable,
7766 .hardware_disable = hardware_disable,
7767 .cpu_has_accelerated_tpr = report_flexpriority,
7768 .has_emulated_msr = vmx_has_emulated_msr,
7770 .vm_size = sizeof(struct kvm_vmx),
7771 .vm_init = vmx_vm_init,
7773 .vcpu_create = vmx_create_vcpu,
7774 .vcpu_free = vmx_free_vcpu,
7775 .vcpu_reset = vmx_vcpu_reset,
7777 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7778 .vcpu_load = vmx_vcpu_load,
7779 .vcpu_put = vmx_vcpu_put,
7781 .update_exception_bitmap = update_exception_bitmap,
7782 .get_msr_feature = vmx_get_msr_feature,
7783 .get_msr = vmx_get_msr,
7784 .set_msr = vmx_set_msr,
7785 .get_segment_base = vmx_get_segment_base,
7786 .get_segment = vmx_get_segment,
7787 .set_segment = vmx_set_segment,
7788 .get_cpl = vmx_get_cpl,
7789 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7790 .set_cr0 = vmx_set_cr0,
7791 .set_cr4 = vmx_set_cr4,
7792 .set_efer = vmx_set_efer,
7793 .get_idt = vmx_get_idt,
7794 .set_idt = vmx_set_idt,
7795 .get_gdt = vmx_get_gdt,
7796 .set_gdt = vmx_set_gdt,
7797 .set_dr7 = vmx_set_dr7,
7798 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7799 .cache_reg = vmx_cache_reg,
7800 .get_rflags = vmx_get_rflags,
7801 .set_rflags = vmx_set_rflags,
7803 .tlb_flush_all = vmx_flush_tlb_all,
7804 .tlb_flush_current = vmx_flush_tlb_current,
7805 .tlb_flush_gva = vmx_flush_tlb_gva,
7806 .tlb_flush_guest = vmx_flush_tlb_guest,
7808 .run = vmx_vcpu_run,
7809 .handle_exit = vmx_handle_exit,
7810 .skip_emulated_instruction = vmx_skip_emulated_instruction,
7811 .update_emulated_instruction = vmx_update_emulated_instruction,
7812 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7813 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7814 .patch_hypercall = vmx_patch_hypercall,
7815 .set_irq = vmx_inject_irq,
7816 .set_nmi = vmx_inject_nmi,
7817 .queue_exception = vmx_queue_exception,
7818 .cancel_injection = vmx_cancel_injection,
7819 .interrupt_allowed = vmx_interrupt_allowed,
7820 .nmi_allowed = vmx_nmi_allowed,
7821 .get_nmi_mask = vmx_get_nmi_mask,
7822 .set_nmi_mask = vmx_set_nmi_mask,
7823 .enable_nmi_window = enable_nmi_window,
7824 .enable_irq_window = enable_irq_window,
7825 .update_cr8_intercept = update_cr8_intercept,
7826 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7827 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7828 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7829 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7830 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7831 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7832 .hwapic_irr_update = vmx_hwapic_irr_update,
7833 .hwapic_isr_update = vmx_hwapic_isr_update,
7834 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7835 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7836 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7837 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7839 .set_tss_addr = vmx_set_tss_addr,
7840 .set_identity_map_addr = vmx_set_identity_map_addr,
7841 .get_mt_mask = vmx_get_mt_mask,
7843 .get_exit_info = vmx_get_exit_info,
7845 .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7847 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7849 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7851 .load_mmu_pgd = vmx_load_mmu_pgd,
7853 .check_intercept = vmx_check_intercept,
7854 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7856 .request_immediate_exit = vmx_request_immediate_exit,
7858 .sched_in = vmx_sched_in,
7860 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7861 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7862 .flush_log_dirty = vmx_flush_log_dirty,
7863 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7865 .pre_block = vmx_pre_block,
7866 .post_block = vmx_post_block,
7868 .pmu_ops = &intel_pmu_ops,
7869 .nested_ops = &vmx_nested_ops,
7871 .update_pi_irte = vmx_update_pi_irte,
7873 #ifdef CONFIG_X86_64
7874 .set_hv_timer = vmx_set_hv_timer,
7875 .cancel_hv_timer = vmx_cancel_hv_timer,
7878 .setup_mce = vmx_setup_mce,
7880 .smi_allowed = vmx_smi_allowed,
7881 .pre_enter_smm = vmx_pre_enter_smm,
7882 .pre_leave_smm = vmx_pre_leave_smm,
7883 .enable_smi_window = enable_smi_window,
7885 .can_emulate_instruction = vmx_can_emulate_instruction,
7886 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7887 .migrate_timers = vmx_migrate_timers,
7890 static __init int hardware_setup(void)
7892 unsigned long host_bndcfgs;
7894 int r, i, ept_lpage_level;
7897 host_idt_base = dt.address;
7899 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7900 kvm_define_shared_msr(i, vmx_msr_index[i]);
7902 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7905 if (boot_cpu_has(X86_FEATURE_NX))
7906 kvm_enable_efer_bits(EFER_NX);
7908 if (boot_cpu_has(X86_FEATURE_MPX)) {
7909 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7910 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7913 if (!cpu_has_vmx_mpx())
7914 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7915 XFEATURE_MASK_BNDCSR);
7917 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7918 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7921 if (!cpu_has_vmx_ept() ||
7922 !cpu_has_vmx_ept_4levels() ||
7923 !cpu_has_vmx_ept_mt_wb() ||
7924 !cpu_has_vmx_invept_global())
7927 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7928 enable_ept_ad_bits = 0;
7930 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7931 enable_unrestricted_guest = 0;
7933 if (!cpu_has_vmx_flexpriority())
7934 flexpriority_enabled = 0;
7936 if (!cpu_has_virtual_nmis())
7940 * set_apic_access_page_addr() is used to reload apic access
7941 * page upon invalidation. No need to do anything if not
7942 * using the APIC_ACCESS_ADDR VMCS field.
7944 if (!flexpriority_enabled)
7945 vmx_x86_ops.set_apic_access_page_addr = NULL;
7947 if (!cpu_has_vmx_tpr_shadow())
7948 vmx_x86_ops.update_cr8_intercept = NULL;
7950 #if IS_ENABLED(CONFIG_HYPERV)
7951 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7953 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7954 vmx_x86_ops.tlb_remote_flush_with_range =
7955 hv_remote_flush_tlb_with_range;
7959 if (!cpu_has_vmx_ple()) {
7962 ple_window_grow = 0;
7964 ple_window_shrink = 0;
7967 if (!cpu_has_vmx_apicv()) {
7969 vmx_x86_ops.sync_pir_to_irr = NULL;
7972 if (cpu_has_vmx_tsc_scaling()) {
7973 kvm_has_tsc_control = true;
7974 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7975 kvm_tsc_scaling_ratio_frac_bits = 48;
7978 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7984 ept_lpage_level = 0;
7985 else if (cpu_has_vmx_ept_1g_page())
7986 ept_lpage_level = PG_LEVEL_1G;
7987 else if (cpu_has_vmx_ept_2m_page())
7988 ept_lpage_level = PG_LEVEL_2M;
7990 ept_lpage_level = PG_LEVEL_4K;
7991 kvm_configure_mmu(enable_ept, vmx_get_max_tdp_level(), ept_lpage_level);
7994 * Only enable PML when hardware supports PML feature, and both EPT
7995 * and EPT A/D bit features are enabled -- PML depends on them to work.
7997 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
8001 vmx_x86_ops.slot_enable_log_dirty = NULL;
8002 vmx_x86_ops.slot_disable_log_dirty = NULL;
8003 vmx_x86_ops.flush_log_dirty = NULL;
8004 vmx_x86_ops.enable_log_dirty_pt_masked = NULL;
8007 if (!cpu_has_vmx_preemption_timer())
8008 enable_preemption_timer = false;
8010 if (enable_preemption_timer) {
8011 u64 use_timer_freq = 5000ULL * 1000 * 1000;
8014 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
8015 cpu_preemption_timer_multi =
8016 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
8019 use_timer_freq = (u64)tsc_khz * 1000;
8020 use_timer_freq >>= cpu_preemption_timer_multi;
8023 * KVM "disables" the preemption timer by setting it to its max
8024 * value. Don't use the timer if it might cause spurious exits
8025 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
8027 if (use_timer_freq > 0xffffffffu / 10)
8028 enable_preemption_timer = false;
8031 if (!enable_preemption_timer) {
8032 vmx_x86_ops.set_hv_timer = NULL;
8033 vmx_x86_ops.cancel_hv_timer = NULL;
8034 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
8037 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
8039 kvm_mce_cap_supported |= MCG_LMCE_P;
8041 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
8043 if (!enable_ept || !cpu_has_vmx_intel_pt())
8044 pt_mode = PT_MODE_SYSTEM;
8047 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
8048 vmx_capability.ept);
8050 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
8057 r = alloc_kvm_area();
8059 nested_vmx_hardware_unsetup();
8063 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
8064 .cpu_has_kvm_support = cpu_has_kvm_support,
8065 .disabled_by_bios = vmx_disabled_by_bios,
8066 .check_processor_compatibility = vmx_check_processor_compat,
8067 .hardware_setup = hardware_setup,
8069 .runtime_ops = &vmx_x86_ops,
8072 static void vmx_cleanup_l1d_flush(void)
8074 if (vmx_l1d_flush_pages) {
8075 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
8076 vmx_l1d_flush_pages = NULL;
8078 /* Restore state so sysfs ignores VMX */
8079 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
8082 static void vmx_exit(void)
8084 #ifdef CONFIG_KEXEC_CORE
8085 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8091 #if IS_ENABLED(CONFIG_HYPERV)
8092 if (static_branch_unlikely(&enable_evmcs)) {
8094 struct hv_vp_assist_page *vp_ap;
8096 * Reset everything to support using non-enlightened VMCS
8097 * access later (e.g. when we reload the module with
8098 * enlightened_vmcs=0)
8100 for_each_online_cpu(cpu) {
8101 vp_ap = hv_get_vp_assist_page(cpu);
8106 vp_ap->nested_control.features.directhypercall = 0;
8107 vp_ap->current_nested_vmcs = 0;
8108 vp_ap->enlighten_vmentry = 0;
8111 static_branch_disable(&enable_evmcs);
8114 vmx_cleanup_l1d_flush();
8116 module_exit(vmx_exit);
8118 static int __init vmx_init(void)
8122 #if IS_ENABLED(CONFIG_HYPERV)
8124 * Enlightened VMCS usage should be recommended and the host needs
8125 * to support eVMCS v1 or above. We can also disable eVMCS support
8126 * with module parameter.
8128 if (enlightened_vmcs &&
8129 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8130 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8131 KVM_EVMCS_VERSION) {
8134 /* Check that we have assist pages on all online CPUs */
8135 for_each_online_cpu(cpu) {
8136 if (!hv_get_vp_assist_page(cpu)) {
8137 enlightened_vmcs = false;
8142 if (enlightened_vmcs) {
8143 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8144 static_branch_enable(&enable_evmcs);
8147 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8148 vmx_x86_ops.enable_direct_tlbflush
8149 = hv_enable_direct_tlbflush;
8152 enlightened_vmcs = false;
8156 r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
8157 __alignof__(struct vcpu_vmx), THIS_MODULE);
8162 * Must be called after kvm_init() so enable_ept is properly set
8163 * up. Hand the parameter mitigation value in which was stored in
8164 * the pre module init parser. If no parameter was given, it will
8165 * contain 'auto' which will be turned into the default 'cond'
8168 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8174 for_each_possible_cpu(cpu) {
8175 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8176 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
8177 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8180 #ifdef CONFIG_KEXEC_CORE
8181 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8182 crash_vmclear_local_loaded_vmcss);
8184 vmx_check_vmcs12_offsets();
8187 * Intel processors don't have problems with
8188 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable
8189 * it for VMX by default
8191 allow_smaller_maxphyaddr = true;
8195 module_init(vmx_init);