1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/frame.h>
17 #include <linux/highmem.h>
18 #include <linux/hrtimer.h>
19 #include <linux/kernel.h>
20 #include <linux/kvm_host.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/mod_devicetable.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
34 #include <asm/debugreg.h>
36 #include <asm/fpu/internal.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/kexec.h>
40 #include <asm/perf_event.h>
42 #include <asm/mmu_context.h>
43 #include <asm/mshyperv.h>
44 #include <asm/spec-ctrl.h>
45 #include <asm/virtext.h>
48 #include "capabilities.h"
52 #include "kvm_cache_regs.h"
64 MODULE_AUTHOR("Qumranet");
65 MODULE_LICENSE("GPL");
67 static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
73 bool __read_mostly enable_vpid = 1;
74 module_param_named(vpid, enable_vpid, bool, 0444);
76 static bool __read_mostly enable_vnmi = 1;
77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
79 bool __read_mostly flexpriority_enabled = 1;
80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
82 bool __read_mostly enable_ept = 1;
83 module_param_named(ept, enable_ept, bool, S_IRUGO);
85 bool __read_mostly enable_unrestricted_guest = 1;
86 module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
89 bool __read_mostly enable_ept_ad_bits = 1;
90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
92 static bool __read_mostly emulate_invalid_guest_state = true;
93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
95 static bool __read_mostly fasteoi = 1;
96 module_param(fasteoi, bool, S_IRUGO);
98 static bool __read_mostly enable_apicv = 1;
99 module_param(enable_apicv, bool, S_IRUGO);
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
106 static bool __read_mostly nested = 1;
107 module_param(nested, bool, S_IRUGO);
109 bool __read_mostly enable_pml = 1;
110 module_param_named(pml, enable_pml, bool, S_IRUGO);
112 static bool __read_mostly dump_invalid_vmcs = 0;
113 module_param(dump_invalid_vmcs, bool, 0644);
115 #define MSR_BITMAP_MODE_X2APIC 1
116 #define MSR_BITMAP_MODE_X2APIC_APICV 2
118 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
120 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
121 static int __read_mostly cpu_preemption_timer_multi;
122 static bool __read_mostly enable_preemption_timer = 1;
124 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
127 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
128 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
129 #define KVM_VM_CR0_ALWAYS_ON \
130 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
131 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
132 #define KVM_CR4_GUEST_OWNED_BITS \
133 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
134 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
136 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
137 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
138 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
140 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
142 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
143 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
144 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
145 RTIT_STATUS_BYTECNT))
147 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
148 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
151 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
152 * ple_gap: upper bound on the amount of time between two successive
153 * executions of PAUSE in a loop. Also indicate if ple enabled.
154 * According to test, this time is usually smaller than 128 cycles.
155 * ple_window: upper bound on the amount of time a guest is allowed to execute
156 * in a PAUSE loop. Tests indicate that most spinlocks are held for
157 * less than 2^12 cycles
158 * Time is measured based on a counter that runs at the same rate as the TSC,
159 * refer SDM volume 3b section 21.6.13 & 22.1.3.
161 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
162 module_param(ple_gap, uint, 0444);
164 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
165 module_param(ple_window, uint, 0444);
167 /* Default doubles per-vcpu window every exit. */
168 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
169 module_param(ple_window_grow, uint, 0444);
171 /* Default resets per-vcpu window every exit to ple_window. */
172 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
173 module_param(ple_window_shrink, uint, 0444);
175 /* Default is to compute the maximum so we can never overflow. */
176 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
177 module_param(ple_window_max, uint, 0444);
179 /* Default is SYSTEM mode, 1 for host-guest mode */
180 int __read_mostly pt_mode = PT_MODE_SYSTEM;
181 module_param(pt_mode, int, S_IRUGO);
183 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
184 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
185 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
187 /* Storage for pre module init parameter parsing */
188 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
190 static const struct {
193 } vmentry_l1d_param[] = {
194 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
195 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
196 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
197 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
198 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
199 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
202 #define L1D_CACHE_ORDER 4
203 static void *vmx_l1d_flush_pages;
205 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
210 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
211 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
216 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
220 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
223 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
224 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
225 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
230 /* If set to auto use the default l1tf mitigation method */
231 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
232 switch (l1tf_mitigation) {
233 case L1TF_MITIGATION_OFF:
234 l1tf = VMENTER_L1D_FLUSH_NEVER;
236 case L1TF_MITIGATION_FLUSH_NOWARN:
237 case L1TF_MITIGATION_FLUSH:
238 case L1TF_MITIGATION_FLUSH_NOSMT:
239 l1tf = VMENTER_L1D_FLUSH_COND;
241 case L1TF_MITIGATION_FULL:
242 case L1TF_MITIGATION_FULL_FORCE:
243 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
246 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
247 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
250 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
251 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
253 * This allocation for vmx_l1d_flush_pages is not tied to a VM
254 * lifetime and so should not be charged to a memcg.
256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
259 vmx_l1d_flush_pages = page_address(page);
262 * Initialize each page with a different pattern in
263 * order to protect against KSM in the nested
264 * virtualization case.
266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
272 l1tf_vmx_mitigation = l1tf;
274 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
275 static_branch_enable(&vmx_l1d_should_flush);
277 static_branch_disable(&vmx_l1d_should_flush);
279 if (l1tf == VMENTER_L1D_FLUSH_COND)
280 static_branch_enable(&vmx_l1d_flush_cond);
282 static_branch_disable(&vmx_l1d_flush_cond);
286 static int vmentry_l1d_flush_parse(const char *s)
291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
292 if (vmentry_l1d_param[i].for_parse &&
293 sysfs_streq(s, vmentry_l1d_param[i].option))
300 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
304 l1tf = vmentry_l1d_flush_parse(s);
308 if (!boot_cpu_has(X86_BUG_L1TF))
312 * Has vmx_init() run already? If not then this is the pre init
313 * parameter parsing. In that case just store the value and let
314 * vmx_init() do the proper setup after enable_ept has been
317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
318 vmentry_l1d_flush_param = l1tf;
322 mutex_lock(&vmx_l1d_flush_mutex);
323 ret = vmx_setup_l1d_flush(l1tf);
324 mutex_unlock(&vmx_l1d_flush_mutex);
328 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
331 return sprintf(s, "???\n");
333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
336 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
337 .set = vmentry_l1d_flush_set,
338 .get = vmentry_l1d_flush_get,
340 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
342 static bool guest_state_valid(struct kvm_vcpu *vcpu);
343 static u32 vmx_segment_access_rights(struct kvm_segment *var);
344 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
347 void vmx_vmexit(void);
349 #define vmx_insn_failed(fmt...) \
352 pr_warn_ratelimited(fmt); \
355 asmlinkage void vmread_error(unsigned long field, bool fault)
358 kvm_spurious_fault();
360 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
363 noinline void vmwrite_error(unsigned long field, unsigned long value)
365 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
366 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
369 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
371 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
374 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
376 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
379 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
381 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
385 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
387 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
391 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
392 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
394 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
395 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
397 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
400 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
401 * can find which vCPU should be waken up.
403 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
404 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
406 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
407 static DEFINE_SPINLOCK(vmx_vpid_lock);
409 struct vmcs_config vmcs_config;
410 struct vmx_capability vmx_capability;
412 #define VMX_SEGMENT_FIELD(seg) \
413 [VCPU_SREG_##seg] = { \
414 .selector = GUEST_##seg##_SELECTOR, \
415 .base = GUEST_##seg##_BASE, \
416 .limit = GUEST_##seg##_LIMIT, \
417 .ar_bytes = GUEST_##seg##_AR_BYTES, \
420 static const struct kvm_vmx_segment_field {
425 } kvm_vmx_segment_fields[] = {
426 VMX_SEGMENT_FIELD(CS),
427 VMX_SEGMENT_FIELD(DS),
428 VMX_SEGMENT_FIELD(ES),
429 VMX_SEGMENT_FIELD(FS),
430 VMX_SEGMENT_FIELD(GS),
431 VMX_SEGMENT_FIELD(SS),
432 VMX_SEGMENT_FIELD(TR),
433 VMX_SEGMENT_FIELD(LDTR),
437 static unsigned long host_idt_base;
440 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
441 * will emulate SYSCALL in legacy mode if the vendor string in guest
442 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
443 * support this emulation, IA32_STAR must always be included in
444 * vmx_msr_index[], even in i386 builds.
446 const u32 vmx_msr_index[] = {
448 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
450 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
453 #if IS_ENABLED(CONFIG_HYPERV)
454 static bool __read_mostly enlightened_vmcs = true;
455 module_param(enlightened_vmcs, bool, 0444);
457 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
458 static void check_ept_pointer_match(struct kvm *kvm)
460 struct kvm_vcpu *vcpu;
461 u64 tmp_eptp = INVALID_PAGE;
464 kvm_for_each_vcpu(i, vcpu, kvm) {
465 if (!VALID_PAGE(tmp_eptp)) {
466 tmp_eptp = to_vmx(vcpu)->ept_pointer;
467 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
468 to_kvm_vmx(kvm)->ept_pointers_match
469 = EPT_POINTERS_MISMATCH;
474 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
477 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
480 struct kvm_tlb_range *range = data;
482 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
486 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
487 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
489 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
492 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
493 * of the base of EPT PML4 table, strip off EPT configuration
497 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
498 kvm_fill_hv_flush_list_func, (void *)range);
500 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
503 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
504 struct kvm_tlb_range *range)
506 struct kvm_vcpu *vcpu;
509 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
511 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
512 check_ept_pointer_match(kvm);
514 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
515 kvm_for_each_vcpu(i, vcpu, kvm) {
516 /* If ept_pointer is invalid pointer, bypass flush request. */
517 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
518 ret |= __hv_remote_flush_tlb_with_range(
522 ret = __hv_remote_flush_tlb_with_range(kvm,
523 kvm_get_vcpu(kvm, 0), range);
526 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
529 static int hv_remote_flush_tlb(struct kvm *kvm)
531 return hv_remote_flush_tlb_with_range(kvm, NULL);
534 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
536 struct hv_enlightened_vmcs *evmcs;
537 struct hv_partition_assist_pg **p_hv_pa_pg =
538 &vcpu->kvm->arch.hyperv.hv_pa_pg;
540 * Synthetic VM-Exit is not enabled in current code and so All
541 * evmcs in singe VM shares same assist page.
544 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
549 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
551 evmcs->partition_assist_page =
553 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
554 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
559 #endif /* IS_ENABLED(CONFIG_HYPERV) */
562 * Comment's format: document - errata name - stepping - processor name.
564 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
566 static u32 vmx_preemption_cpu_tfms[] = {
567 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
569 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
570 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
571 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
573 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
575 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
576 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
578 * 320767.pdf - AAP86 - B1 -
579 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
582 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
584 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
586 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
588 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
589 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
590 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
592 /* Xeon E3-1220 V2 */
596 static inline bool cpu_has_broken_vmx_preemption_timer(void)
598 u32 eax = cpuid_eax(0x00000001), i;
600 /* Clear the reserved bits */
601 eax &= ~(0x3U << 14 | 0xfU << 28);
602 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
603 if (eax == vmx_preemption_cpu_tfms[i])
609 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
611 return flexpriority_enabled && lapic_in_kernel(vcpu);
614 static inline bool report_flexpriority(void)
616 return flexpriority_enabled;
619 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
623 for (i = 0; i < vmx->nmsrs; ++i)
624 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
629 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
633 i = __find_msr_index(vmx, msr);
635 return &vmx->guest_msrs[i];
639 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
641 vmcs_clear(loaded_vmcs->vmcs);
642 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
643 vmcs_clear(loaded_vmcs->shadow_vmcs);
644 loaded_vmcs->cpu = -1;
645 loaded_vmcs->launched = 0;
648 #ifdef CONFIG_KEXEC_CORE
650 * This bitmap is used to indicate whether the vmclear
651 * operation is enabled on all cpus. All disabled by
654 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
656 static inline void crash_enable_local_vmclear(int cpu)
658 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
661 static inline void crash_disable_local_vmclear(int cpu)
663 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
666 static inline int crash_local_vmclear_enabled(int cpu)
668 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
671 static void crash_vmclear_local_loaded_vmcss(void)
673 int cpu = raw_smp_processor_id();
674 struct loaded_vmcs *v;
676 if (!crash_local_vmclear_enabled(cpu))
679 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
680 loaded_vmcss_on_cpu_link)
684 static inline void crash_enable_local_vmclear(int cpu) { }
685 static inline void crash_disable_local_vmclear(int cpu) { }
686 #endif /* CONFIG_KEXEC_CORE */
688 static void __loaded_vmcs_clear(void *arg)
690 struct loaded_vmcs *loaded_vmcs = arg;
691 int cpu = raw_smp_processor_id();
693 if (loaded_vmcs->cpu != cpu)
694 return; /* vcpu migration can race with cpu offline */
695 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
696 per_cpu(current_vmcs, cpu) = NULL;
697 crash_disable_local_vmclear(cpu);
698 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
701 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
702 * is before setting loaded_vmcs->vcpu to -1 which is done in
703 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
704 * then adds the vmcs into percpu list before it is deleted.
708 loaded_vmcs_init(loaded_vmcs);
709 crash_enable_local_vmclear(cpu);
712 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
714 int cpu = loaded_vmcs->cpu;
717 smp_call_function_single(cpu,
718 __loaded_vmcs_clear, loaded_vmcs, 1);
721 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
725 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
727 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
728 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
729 vmx->segment_cache.bitmask = 0;
731 ret = vmx->segment_cache.bitmask & mask;
732 vmx->segment_cache.bitmask |= mask;
736 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
738 u16 *p = &vmx->segment_cache.seg[seg].selector;
740 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
741 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
745 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
747 ulong *p = &vmx->segment_cache.seg[seg].base;
749 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
750 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
754 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
756 u32 *p = &vmx->segment_cache.seg[seg].limit;
758 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
759 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
763 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
765 u32 *p = &vmx->segment_cache.seg[seg].ar;
767 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
768 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
772 void update_exception_bitmap(struct kvm_vcpu *vcpu)
776 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
777 (1u << DB_VECTOR) | (1u << AC_VECTOR);
779 * Guest access to VMware backdoor ports could legitimately
780 * trigger #GP because of TSS I/O permission bitmap.
781 * We intercept those #GP and allow access to them anyway
784 if (enable_vmware_backdoor)
785 eb |= (1u << GP_VECTOR);
786 if ((vcpu->guest_debug &
787 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
788 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
789 eb |= 1u << BP_VECTOR;
790 if (to_vmx(vcpu)->rmode.vm86_active)
793 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
795 /* When we are running a nested L2 guest and L1 specified for it a
796 * certain exception bitmap, we must trap the same exceptions and pass
797 * them to L1. When running L2, we will only handle the exceptions
798 * specified above if L1 did not want them.
800 if (is_guest_mode(vcpu))
801 eb |= get_vmcs12(vcpu)->exception_bitmap;
803 vmcs_write32(EXCEPTION_BITMAP, eb);
807 * Check if MSR is intercepted for currently loaded MSR bitmap.
809 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
811 unsigned long *msr_bitmap;
812 int f = sizeof(unsigned long);
814 if (!cpu_has_vmx_msr_bitmap())
817 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
820 return !!test_bit(msr, msr_bitmap + 0x800 / f);
821 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
823 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
829 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
830 unsigned long entry, unsigned long exit)
832 vm_entry_controls_clearbit(vmx, entry);
833 vm_exit_controls_clearbit(vmx, exit);
836 static int find_msr(struct vmx_msrs *m, unsigned int msr)
840 for (i = 0; i < m->nr; ++i) {
841 if (m->val[i].index == msr)
847 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
850 struct msr_autoload *m = &vmx->msr_autoload;
854 if (cpu_has_load_ia32_efer()) {
855 clear_atomic_switch_msr_special(vmx,
856 VM_ENTRY_LOAD_IA32_EFER,
857 VM_EXIT_LOAD_IA32_EFER);
861 case MSR_CORE_PERF_GLOBAL_CTRL:
862 if (cpu_has_load_perf_global_ctrl()) {
863 clear_atomic_switch_msr_special(vmx,
864 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
865 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
870 i = find_msr(&m->guest, msr);
874 m->guest.val[i] = m->guest.val[m->guest.nr];
875 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
878 i = find_msr(&m->host, msr);
883 m->host.val[i] = m->host.val[m->host.nr];
884 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
887 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
888 unsigned long entry, unsigned long exit,
889 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
890 u64 guest_val, u64 host_val)
892 vmcs_write64(guest_val_vmcs, guest_val);
893 if (host_val_vmcs != HOST_IA32_EFER)
894 vmcs_write64(host_val_vmcs, host_val);
895 vm_entry_controls_setbit(vmx, entry);
896 vm_exit_controls_setbit(vmx, exit);
899 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
900 u64 guest_val, u64 host_val, bool entry_only)
903 struct msr_autoload *m = &vmx->msr_autoload;
907 if (cpu_has_load_ia32_efer()) {
908 add_atomic_switch_msr_special(vmx,
909 VM_ENTRY_LOAD_IA32_EFER,
910 VM_EXIT_LOAD_IA32_EFER,
913 guest_val, host_val);
917 case MSR_CORE_PERF_GLOBAL_CTRL:
918 if (cpu_has_load_perf_global_ctrl()) {
919 add_atomic_switch_msr_special(vmx,
920 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
921 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
922 GUEST_IA32_PERF_GLOBAL_CTRL,
923 HOST_IA32_PERF_GLOBAL_CTRL,
924 guest_val, host_val);
928 case MSR_IA32_PEBS_ENABLE:
929 /* PEBS needs a quiescent period after being disabled (to write
930 * a record). Disabling PEBS through VMX MSR swapping doesn't
931 * provide that period, so a CPU could write host's record into
934 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
937 i = find_msr(&m->guest, msr);
939 j = find_msr(&m->host, msr);
941 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
942 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) {
943 printk_once(KERN_WARNING "Not enough msr switch entries. "
944 "Can't add msr %x\n", msr);
949 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
951 m->guest.val[i].index = msr;
952 m->guest.val[i].value = guest_val;
959 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
961 m->host.val[j].index = msr;
962 m->host.val[j].value = host_val;
965 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
967 u64 guest_efer = vmx->vcpu.arch.efer;
972 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
973 * host CPUID is more efficient than testing guest CPUID
974 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
976 if (boot_cpu_has(X86_FEATURE_SMEP))
977 guest_efer |= EFER_NX;
978 else if (!(guest_efer & EFER_NX))
979 ignore_bits |= EFER_NX;
983 * LMA and LME handled by hardware; SCE meaningless outside long mode.
985 ignore_bits |= EFER_SCE;
987 ignore_bits |= EFER_LMA | EFER_LME;
988 /* SCE is meaningful only in long mode on Intel */
989 if (guest_efer & EFER_LMA)
990 ignore_bits &= ~(u64)EFER_SCE;
994 * On EPT, we can't emulate NX, so we must switch EFER atomically.
995 * On CPUs that support "load IA32_EFER", always switch EFER
996 * atomically, since it's faster than switching it manually.
998 if (cpu_has_load_ia32_efer() ||
999 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1000 if (!(guest_efer & EFER_LMA))
1001 guest_efer &= ~EFER_LME;
1002 if (guest_efer != host_efer)
1003 add_atomic_switch_msr(vmx, MSR_EFER,
1004 guest_efer, host_efer, false);
1006 clear_atomic_switch_msr(vmx, MSR_EFER);
1009 clear_atomic_switch_msr(vmx, MSR_EFER);
1011 guest_efer &= ~ignore_bits;
1012 guest_efer |= host_efer & ignore_bits;
1014 vmx->guest_msrs[efer_offset].data = guest_efer;
1015 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1021 #ifdef CONFIG_X86_32
1023 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1024 * VMCS rather than the segment table. KVM uses this helper to figure
1025 * out the current bases to poke them into the VMCS before entry.
1027 static unsigned long segment_base(u16 selector)
1029 struct desc_struct *table;
1032 if (!(selector & ~SEGMENT_RPL_MASK))
1035 table = get_current_gdt_ro();
1037 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1038 u16 ldt_selector = kvm_read_ldt();
1040 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1043 table = (struct desc_struct *)segment_base(ldt_selector);
1045 v = get_desc_base(&table[selector >> 3]);
1050 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1054 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1055 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1056 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1057 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1058 for (i = 0; i < addr_range; i++) {
1059 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1060 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1064 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1068 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1069 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1070 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1071 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1072 for (i = 0; i < addr_range; i++) {
1073 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1074 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1078 static void pt_guest_enter(struct vcpu_vmx *vmx)
1080 if (pt_mode == PT_MODE_SYSTEM)
1084 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1085 * Save host state before VM entry.
1087 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1088 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1089 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1090 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1091 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1095 static void pt_guest_exit(struct vcpu_vmx *vmx)
1097 if (pt_mode == PT_MODE_SYSTEM)
1100 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1101 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1102 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1105 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1106 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1109 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1110 unsigned long fs_base, unsigned long gs_base)
1112 if (unlikely(fs_sel != host->fs_sel)) {
1114 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1116 vmcs_write16(HOST_FS_SELECTOR, 0);
1117 host->fs_sel = fs_sel;
1119 if (unlikely(gs_sel != host->gs_sel)) {
1121 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1123 vmcs_write16(HOST_GS_SELECTOR, 0);
1124 host->gs_sel = gs_sel;
1126 if (unlikely(fs_base != host->fs_base)) {
1127 vmcs_writel(HOST_FS_BASE, fs_base);
1128 host->fs_base = fs_base;
1130 if (unlikely(gs_base != host->gs_base)) {
1131 vmcs_writel(HOST_GS_BASE, gs_base);
1132 host->gs_base = gs_base;
1136 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1138 struct vcpu_vmx *vmx = to_vmx(vcpu);
1139 struct vmcs_host_state *host_state;
1140 #ifdef CONFIG_X86_64
1141 int cpu = raw_smp_processor_id();
1143 unsigned long fs_base, gs_base;
1147 vmx->req_immediate_exit = false;
1150 * Note that guest MSRs to be saved/restored can also be changed
1151 * when guest state is loaded. This happens when guest transitions
1152 * to/from long-mode by setting MSR_EFER.LMA.
1154 if (!vmx->guest_msrs_ready) {
1155 vmx->guest_msrs_ready = true;
1156 for (i = 0; i < vmx->save_nmsrs; ++i)
1157 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1158 vmx->guest_msrs[i].data,
1159 vmx->guest_msrs[i].mask);
1162 if (vmx->guest_state_loaded)
1165 host_state = &vmx->loaded_vmcs->host_state;
1168 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1169 * allow segment selectors with cpl > 0 or ti == 1.
1171 host_state->ldt_sel = kvm_read_ldt();
1173 #ifdef CONFIG_X86_64
1174 savesegment(ds, host_state->ds_sel);
1175 savesegment(es, host_state->es_sel);
1177 gs_base = cpu_kernelmode_gs_base(cpu);
1178 if (likely(is_64bit_mm(current->mm))) {
1179 save_fsgs_for_kvm();
1180 fs_sel = current->thread.fsindex;
1181 gs_sel = current->thread.gsindex;
1182 fs_base = current->thread.fsbase;
1183 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1185 savesegment(fs, fs_sel);
1186 savesegment(gs, gs_sel);
1187 fs_base = read_msr(MSR_FS_BASE);
1188 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1191 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1193 savesegment(fs, fs_sel);
1194 savesegment(gs, gs_sel);
1195 fs_base = segment_base(fs_sel);
1196 gs_base = segment_base(gs_sel);
1199 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1200 vmx->guest_state_loaded = true;
1203 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1205 struct vmcs_host_state *host_state;
1207 if (!vmx->guest_state_loaded)
1210 host_state = &vmx->loaded_vmcs->host_state;
1212 ++vmx->vcpu.stat.host_state_reload;
1214 #ifdef CONFIG_X86_64
1215 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1217 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1218 kvm_load_ldt(host_state->ldt_sel);
1219 #ifdef CONFIG_X86_64
1220 load_gs_index(host_state->gs_sel);
1222 loadsegment(gs, host_state->gs_sel);
1225 if (host_state->fs_sel & 7)
1226 loadsegment(fs, host_state->fs_sel);
1227 #ifdef CONFIG_X86_64
1228 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1229 loadsegment(ds, host_state->ds_sel);
1230 loadsegment(es, host_state->es_sel);
1233 invalidate_tss_limit();
1234 #ifdef CONFIG_X86_64
1235 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1237 load_fixmap_gdt(raw_smp_processor_id());
1238 vmx->guest_state_loaded = false;
1239 vmx->guest_msrs_ready = false;
1242 #ifdef CONFIG_X86_64
1243 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1246 if (vmx->guest_state_loaded)
1247 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1249 return vmx->msr_guest_kernel_gs_base;
1252 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1255 if (vmx->guest_state_loaded)
1256 wrmsrl(MSR_KERNEL_GS_BASE, data);
1258 vmx->msr_guest_kernel_gs_base = data;
1262 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1264 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1265 struct pi_desc old, new;
1269 * In case of hot-plug or hot-unplug, we may have to undo
1270 * vmx_vcpu_pi_put even if there is no assigned device. And we
1271 * always keep PI.NDST up to date for simplicity: it makes the
1272 * code easier, and CPU migration is not a fast path.
1274 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1277 /* The full case. */
1279 old.control = new.control = pi_desc->control;
1281 dest = cpu_physical_id(cpu);
1283 if (x2apic_enabled())
1286 new.ndst = (dest << 8) & 0xFF00;
1289 } while (cmpxchg64(&pi_desc->control, old.control,
1290 new.control) != old.control);
1293 * Clear SN before reading the bitmap. The VT-d firmware
1294 * writes the bitmap and reads SN atomically (5.2.3 in the
1295 * spec), so it doesn't really have a memory barrier that
1296 * pairs with this, but we cannot do that and we need one.
1298 smp_mb__after_atomic();
1300 if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
1304 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1306 struct vcpu_vmx *vmx = to_vmx(vcpu);
1307 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1309 if (!already_loaded) {
1310 loaded_vmcs_clear(vmx->loaded_vmcs);
1311 local_irq_disable();
1312 crash_disable_local_vmclear(cpu);
1315 * Read loaded_vmcs->cpu should be before fetching
1316 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1317 * See the comments in __loaded_vmcs_clear().
1321 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1322 &per_cpu(loaded_vmcss_on_cpu, cpu));
1323 crash_enable_local_vmclear(cpu);
1327 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1328 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1329 vmcs_load(vmx->loaded_vmcs->vmcs);
1330 indirect_branch_prediction_barrier();
1333 if (!already_loaded) {
1334 void *gdt = get_current_gdt_ro();
1335 unsigned long sysenter_esp;
1337 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1340 * Linux uses per-cpu TSS and GDT, so set these when switching
1341 * processors. See 22.2.4.
1343 vmcs_writel(HOST_TR_BASE,
1344 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1345 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1348 * VM exits change the host TR limit to 0x67 after a VM
1349 * exit. This is okay, since 0x67 covers everything except
1350 * the IO bitmap and have have code to handle the IO bitmap
1351 * being lost after a VM exit.
1353 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1355 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1356 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1358 vmx->loaded_vmcs->cpu = cpu;
1361 /* Setup TSC multiplier */
1362 if (kvm_has_tsc_control &&
1363 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1364 decache_tsc_multiplier(vmx);
1368 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1369 * vcpu mutex is already taken.
1371 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1373 struct vcpu_vmx *vmx = to_vmx(vcpu);
1375 vmx_vcpu_load_vmcs(vcpu, cpu);
1377 vmx_vcpu_pi_load(vcpu, cpu);
1379 vmx->host_pkru = read_pkru();
1380 vmx->host_debugctlmsr = get_debugctlmsr();
1383 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1385 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1387 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1388 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1389 !kvm_vcpu_apicv_active(vcpu))
1392 /* Set SN when the vCPU is preempted */
1393 if (vcpu->preempted)
1397 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1399 vmx_vcpu_pi_put(vcpu);
1401 vmx_prepare_switch_to_host(to_vmx(vcpu));
1404 static bool emulation_required(struct kvm_vcpu *vcpu)
1406 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1409 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1411 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1413 struct vcpu_vmx *vmx = to_vmx(vcpu);
1414 unsigned long rflags, save_rflags;
1416 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1417 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1418 rflags = vmcs_readl(GUEST_RFLAGS);
1419 if (vmx->rmode.vm86_active) {
1420 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1421 save_rflags = vmx->rmode.save_rflags;
1422 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1424 vmx->rflags = rflags;
1429 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1431 struct vcpu_vmx *vmx = to_vmx(vcpu);
1432 unsigned long old_rflags;
1434 if (enable_unrestricted_guest) {
1435 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1436 vmx->rflags = rflags;
1437 vmcs_writel(GUEST_RFLAGS, rflags);
1441 old_rflags = vmx_get_rflags(vcpu);
1442 vmx->rflags = rflags;
1443 if (vmx->rmode.vm86_active) {
1444 vmx->rmode.save_rflags = rflags;
1445 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1447 vmcs_writel(GUEST_RFLAGS, rflags);
1449 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1450 vmx->emulation_required = emulation_required(vcpu);
1453 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1455 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1458 if (interruptibility & GUEST_INTR_STATE_STI)
1459 ret |= KVM_X86_SHADOW_INT_STI;
1460 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1461 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1466 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1468 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1469 u32 interruptibility = interruptibility_old;
1471 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1473 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1474 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1475 else if (mask & KVM_X86_SHADOW_INT_STI)
1476 interruptibility |= GUEST_INTR_STATE_STI;
1478 if ((interruptibility != interruptibility_old))
1479 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1482 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1484 struct vcpu_vmx *vmx = to_vmx(vcpu);
1485 unsigned long value;
1488 * Any MSR write that attempts to change bits marked reserved will
1491 if (data & vmx->pt_desc.ctl_bitmask)
1495 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1496 * result in a #GP unless the same write also clears TraceEn.
1498 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1499 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1503 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1504 * and FabricEn would cause #GP, if
1505 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1507 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1508 !(data & RTIT_CTL_FABRIC_EN) &&
1509 !intel_pt_validate_cap(vmx->pt_desc.caps,
1510 PT_CAP_single_range_output))
1514 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1515 * utilize encodings marked reserved will casue a #GP fault.
1517 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1518 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1519 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1520 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1522 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1523 PT_CAP_cycle_thresholds);
1524 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1525 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1526 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1528 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1529 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1530 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1531 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1535 * If ADDRx_CFG is reserved or the encodings is >2 will
1536 * cause a #GP fault.
1538 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1539 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1541 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1542 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1544 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1545 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1547 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1548 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1554 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1559 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1560 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1561 * set when EPT misconfig occurs. In practice, real hardware updates
1562 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1563 * (namely Hyper-V) don't set it due to it being undefined behavior,
1564 * i.e. we end up advancing IP with some random value.
1566 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1567 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1568 rip = kvm_rip_read(vcpu);
1569 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1570 kvm_rip_write(vcpu, rip);
1572 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1576 /* skipping an emulated instruction also counts */
1577 vmx_set_interrupt_shadow(vcpu, 0);
1582 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1585 * Ensure that we clear the HLT state in the VMCS. We don't need to
1586 * explicitly skip the instruction because if the HLT state is set,
1587 * then the instruction is already executing and RIP has already been
1590 if (kvm_hlt_in_guest(vcpu->kvm) &&
1591 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1592 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1595 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1597 struct vcpu_vmx *vmx = to_vmx(vcpu);
1598 unsigned nr = vcpu->arch.exception.nr;
1599 bool has_error_code = vcpu->arch.exception.has_error_code;
1600 u32 error_code = vcpu->arch.exception.error_code;
1601 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1603 kvm_deliver_exception_payload(vcpu);
1605 if (has_error_code) {
1606 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1607 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1610 if (vmx->rmode.vm86_active) {
1612 if (kvm_exception_is_soft(nr))
1613 inc_eip = vcpu->arch.event_exit_inst_len;
1614 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1618 WARN_ON_ONCE(vmx->emulation_required);
1620 if (kvm_exception_is_soft(nr)) {
1621 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1622 vmx->vcpu.arch.event_exit_inst_len);
1623 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1625 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1627 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1629 vmx_clear_hlt(vcpu);
1632 static bool vmx_rdtscp_supported(void)
1634 return cpu_has_vmx_rdtscp();
1637 static bool vmx_invpcid_supported(void)
1639 return cpu_has_vmx_invpcid();
1643 * Swap MSR entry in host/guest MSR entry array.
1645 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1647 struct shared_msr_entry tmp;
1649 tmp = vmx->guest_msrs[to];
1650 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1651 vmx->guest_msrs[from] = tmp;
1655 * Set up the vmcs to automatically save and restore system
1656 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1657 * mode, as fiddling with msrs is very expensive.
1659 static void setup_msrs(struct vcpu_vmx *vmx)
1661 int save_nmsrs, index;
1664 #ifdef CONFIG_X86_64
1666 * The SYSCALL MSRs are only needed on long mode guests, and only
1667 * when EFER.SCE is set.
1669 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1670 index = __find_msr_index(vmx, MSR_STAR);
1672 move_msr_up(vmx, index, save_nmsrs++);
1673 index = __find_msr_index(vmx, MSR_LSTAR);
1675 move_msr_up(vmx, index, save_nmsrs++);
1676 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1678 move_msr_up(vmx, index, save_nmsrs++);
1681 index = __find_msr_index(vmx, MSR_EFER);
1682 if (index >= 0 && update_transition_efer(vmx, index))
1683 move_msr_up(vmx, index, save_nmsrs++);
1684 index = __find_msr_index(vmx, MSR_TSC_AUX);
1685 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1686 move_msr_up(vmx, index, save_nmsrs++);
1688 vmx->save_nmsrs = save_nmsrs;
1689 vmx->guest_msrs_ready = false;
1691 if (cpu_has_vmx_msr_bitmap())
1692 vmx_update_msr_bitmap(&vmx->vcpu);
1695 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1697 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1699 if (is_guest_mode(vcpu) &&
1700 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1701 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1703 return vcpu->arch.tsc_offset;
1706 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1708 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1709 u64 g_tsc_offset = 0;
1712 * We're here if L1 chose not to trap WRMSR to TSC. According
1713 * to the spec, this should set L1's TSC; The offset that L1
1714 * set for L2 remains unchanged, and still needs to be added
1715 * to the newly set TSC to get L2's TSC.
1717 if (is_guest_mode(vcpu) &&
1718 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1719 g_tsc_offset = vmcs12->tsc_offset;
1721 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1722 vcpu->arch.tsc_offset - g_tsc_offset,
1724 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1725 return offset + g_tsc_offset;
1729 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1730 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1731 * all guests if the "nested" module option is off, and can also be disabled
1732 * for a single guest by disabling its VMX cpuid bit.
1734 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1736 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1739 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1742 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1744 return !(val & ~valid_bits);
1747 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1749 switch (msr->index) {
1750 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1753 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1762 * Reads an msr value (of 'msr_index') into 'pdata'.
1763 * Returns 0 on success, non-0 otherwise.
1764 * Assumes vcpu_load() was already called.
1766 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1768 struct vcpu_vmx *vmx = to_vmx(vcpu);
1769 struct shared_msr_entry *msr;
1772 switch (msr_info->index) {
1773 #ifdef CONFIG_X86_64
1775 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1778 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1780 case MSR_KERNEL_GS_BASE:
1781 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1785 return kvm_get_msr_common(vcpu, msr_info);
1786 case MSR_IA32_UMWAIT_CONTROL:
1787 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1790 msr_info->data = vmx->msr_ia32_umwait_control;
1792 case MSR_IA32_SPEC_CTRL:
1793 if (!msr_info->host_initiated &&
1794 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1797 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1799 case MSR_IA32_SYSENTER_CS:
1800 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1802 case MSR_IA32_SYSENTER_EIP:
1803 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1805 case MSR_IA32_SYSENTER_ESP:
1806 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1808 case MSR_IA32_BNDCFGS:
1809 if (!kvm_mpx_supported() ||
1810 (!msr_info->host_initiated &&
1811 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1813 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1815 case MSR_IA32_MCG_EXT_CTL:
1816 if (!msr_info->host_initiated &&
1817 !(vmx->msr_ia32_feature_control &
1818 FEATURE_CONTROL_LMCE))
1820 msr_info->data = vcpu->arch.mcg_ext_ctl;
1822 case MSR_IA32_FEATURE_CONTROL:
1823 msr_info->data = vmx->msr_ia32_feature_control;
1825 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1826 if (!nested_vmx_allowed(vcpu))
1828 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1830 case MSR_IA32_RTIT_CTL:
1831 if (pt_mode != PT_MODE_HOST_GUEST)
1833 msr_info->data = vmx->pt_desc.guest.ctl;
1835 case MSR_IA32_RTIT_STATUS:
1836 if (pt_mode != PT_MODE_HOST_GUEST)
1838 msr_info->data = vmx->pt_desc.guest.status;
1840 case MSR_IA32_RTIT_CR3_MATCH:
1841 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1842 !intel_pt_validate_cap(vmx->pt_desc.caps,
1843 PT_CAP_cr3_filtering))
1845 msr_info->data = vmx->pt_desc.guest.cr3_match;
1847 case MSR_IA32_RTIT_OUTPUT_BASE:
1848 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1849 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1850 PT_CAP_topa_output) &&
1851 !intel_pt_validate_cap(vmx->pt_desc.caps,
1852 PT_CAP_single_range_output)))
1854 msr_info->data = vmx->pt_desc.guest.output_base;
1856 case MSR_IA32_RTIT_OUTPUT_MASK:
1857 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1858 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1859 PT_CAP_topa_output) &&
1860 !intel_pt_validate_cap(vmx->pt_desc.caps,
1861 PT_CAP_single_range_output)))
1863 msr_info->data = vmx->pt_desc.guest.output_mask;
1865 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1866 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1867 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1868 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1869 PT_CAP_num_address_ranges)))
1872 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1874 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1877 if (!msr_info->host_initiated &&
1878 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1880 /* Else, falls through */
1882 msr = find_msr_entry(vmx, msr_info->index);
1884 msr_info->data = msr->data;
1887 return kvm_get_msr_common(vcpu, msr_info);
1894 * Writes msr value into into the appropriate "register".
1895 * Returns 0 on success, non-0 otherwise.
1896 * Assumes vcpu_load() was already called.
1898 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1900 struct vcpu_vmx *vmx = to_vmx(vcpu);
1901 struct shared_msr_entry *msr;
1903 u32 msr_index = msr_info->index;
1904 u64 data = msr_info->data;
1907 switch (msr_index) {
1909 ret = kvm_set_msr_common(vcpu, msr_info);
1911 #ifdef CONFIG_X86_64
1913 vmx_segment_cache_clear(vmx);
1914 vmcs_writel(GUEST_FS_BASE, data);
1917 vmx_segment_cache_clear(vmx);
1918 vmcs_writel(GUEST_GS_BASE, data);
1920 case MSR_KERNEL_GS_BASE:
1921 vmx_write_guest_kernel_gs_base(vmx, data);
1924 case MSR_IA32_SYSENTER_CS:
1925 if (is_guest_mode(vcpu))
1926 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1927 vmcs_write32(GUEST_SYSENTER_CS, data);
1929 case MSR_IA32_SYSENTER_EIP:
1930 if (is_guest_mode(vcpu))
1931 get_vmcs12(vcpu)->guest_sysenter_eip = data;
1932 vmcs_writel(GUEST_SYSENTER_EIP, data);
1934 case MSR_IA32_SYSENTER_ESP:
1935 if (is_guest_mode(vcpu))
1936 get_vmcs12(vcpu)->guest_sysenter_esp = data;
1937 vmcs_writel(GUEST_SYSENTER_ESP, data);
1939 case MSR_IA32_DEBUGCTLMSR:
1940 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1941 VM_EXIT_SAVE_DEBUG_CONTROLS)
1942 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1944 ret = kvm_set_msr_common(vcpu, msr_info);
1947 case MSR_IA32_BNDCFGS:
1948 if (!kvm_mpx_supported() ||
1949 (!msr_info->host_initiated &&
1950 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1952 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1953 (data & MSR_IA32_BNDCFGS_RSVD))
1955 vmcs_write64(GUEST_BNDCFGS, data);
1957 case MSR_IA32_UMWAIT_CONTROL:
1958 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1961 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
1962 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
1965 vmx->msr_ia32_umwait_control = data;
1967 case MSR_IA32_SPEC_CTRL:
1968 if (!msr_info->host_initiated &&
1969 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1972 /* The STIBP bit doesn't fault even if it's not advertised */
1973 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
1976 vmx->spec_ctrl = data;
1983 * When it's written (to non-zero) for the first time, pass
1987 * The handling of the MSR bitmap for L2 guests is done in
1988 * nested_vmx_merge_msr_bitmap. We should not touch the
1989 * vmcs02.msr_bitmap here since it gets completely overwritten
1990 * in the merging. We update the vmcs01 here for L1 as well
1991 * since it will end up touching the MSR anyway now.
1993 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
1997 case MSR_IA32_PRED_CMD:
1998 if (!msr_info->host_initiated &&
1999 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2002 if (data & ~PRED_CMD_IBPB)
2008 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2012 * When it's written (to non-zero) for the first time, pass
2016 * The handling of the MSR bitmap for L2 guests is done in
2017 * nested_vmx_merge_msr_bitmap. We should not touch the
2018 * vmcs02.msr_bitmap here since it gets completely overwritten
2021 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2024 case MSR_IA32_CR_PAT:
2025 if (!kvm_pat_valid(data))
2028 if (is_guest_mode(vcpu) &&
2029 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2030 get_vmcs12(vcpu)->guest_ia32_pat = data;
2032 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2033 vmcs_write64(GUEST_IA32_PAT, data);
2034 vcpu->arch.pat = data;
2037 ret = kvm_set_msr_common(vcpu, msr_info);
2039 case MSR_IA32_TSC_ADJUST:
2040 ret = kvm_set_msr_common(vcpu, msr_info);
2042 case MSR_IA32_MCG_EXT_CTL:
2043 if ((!msr_info->host_initiated &&
2044 !(to_vmx(vcpu)->msr_ia32_feature_control &
2045 FEATURE_CONTROL_LMCE)) ||
2046 (data & ~MCG_EXT_CTL_LMCE_EN))
2048 vcpu->arch.mcg_ext_ctl = data;
2050 case MSR_IA32_FEATURE_CONTROL:
2051 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2052 (to_vmx(vcpu)->msr_ia32_feature_control &
2053 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2055 vmx->msr_ia32_feature_control = data;
2056 if (msr_info->host_initiated && data == 0)
2057 vmx_leave_nested(vcpu);
2059 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2060 if (!msr_info->host_initiated)
2061 return 1; /* they are read-only */
2062 if (!nested_vmx_allowed(vcpu))
2064 return vmx_set_vmx_msr(vcpu, msr_index, data);
2065 case MSR_IA32_RTIT_CTL:
2066 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2067 vmx_rtit_ctl_check(vcpu, data) ||
2070 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2071 vmx->pt_desc.guest.ctl = data;
2072 pt_update_intercept_for_msr(vmx);
2074 case MSR_IA32_RTIT_STATUS:
2075 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2076 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2077 (data & MSR_IA32_RTIT_STATUS_MASK))
2079 vmx->pt_desc.guest.status = data;
2081 case MSR_IA32_RTIT_CR3_MATCH:
2082 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2083 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2084 !intel_pt_validate_cap(vmx->pt_desc.caps,
2085 PT_CAP_cr3_filtering))
2087 vmx->pt_desc.guest.cr3_match = data;
2089 case MSR_IA32_RTIT_OUTPUT_BASE:
2090 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2091 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2092 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2093 PT_CAP_topa_output) &&
2094 !intel_pt_validate_cap(vmx->pt_desc.caps,
2095 PT_CAP_single_range_output)) ||
2096 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2098 vmx->pt_desc.guest.output_base = data;
2100 case MSR_IA32_RTIT_OUTPUT_MASK:
2101 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2102 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2103 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2104 PT_CAP_topa_output) &&
2105 !intel_pt_validate_cap(vmx->pt_desc.caps,
2106 PT_CAP_single_range_output)))
2108 vmx->pt_desc.guest.output_mask = data;
2110 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2111 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2112 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2113 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2114 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2115 PT_CAP_num_address_ranges)))
2118 vmx->pt_desc.guest.addr_b[index / 2] = data;
2120 vmx->pt_desc.guest.addr_a[index / 2] = data;
2123 if (!msr_info->host_initiated &&
2124 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2126 /* Check reserved bit, higher 32 bits should be zero */
2127 if ((data >> 32) != 0)
2129 /* Else, falls through */
2131 msr = find_msr_entry(vmx, msr_index);
2133 u64 old_msr_data = msr->data;
2135 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2137 ret = kvm_set_shared_msr(msr->index, msr->data,
2141 msr->data = old_msr_data;
2145 ret = kvm_set_msr_common(vcpu, msr_info);
2151 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2153 kvm_register_mark_available(vcpu, reg);
2157 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2160 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2162 case VCPU_EXREG_PDPTR:
2164 ept_save_pdptrs(vcpu);
2166 case VCPU_EXREG_CR3:
2167 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2168 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2176 static __init int cpu_has_kvm_support(void)
2178 return cpu_has_vmx();
2181 static __init int vmx_disabled_by_bios(void)
2185 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2186 if (msr & FEATURE_CONTROL_LOCKED) {
2187 /* launched w/ TXT and VMX disabled */
2188 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2191 /* launched w/o TXT and VMX only enabled w/ TXT */
2192 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2193 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2194 && !tboot_enabled()) {
2195 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2196 "activate TXT before enabling KVM\n");
2199 /* launched w/o TXT and VMX disabled */
2200 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2201 && !tboot_enabled())
2208 static void kvm_cpu_vmxon(u64 addr)
2210 cr4_set_bits(X86_CR4_VMXE);
2211 intel_pt_handle_vmx(1);
2213 asm volatile ("vmxon %0" : : "m"(addr));
2216 static int hardware_enable(void)
2218 int cpu = raw_smp_processor_id();
2219 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2222 if (cr4_read_shadow() & X86_CR4_VMXE)
2226 * This can happen if we hot-added a CPU but failed to allocate
2227 * VP assist page for it.
2229 if (static_branch_unlikely(&enable_evmcs) &&
2230 !hv_get_vp_assist_page(cpu))
2233 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2234 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2235 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2238 * Now we can enable the vmclear operation in kdump
2239 * since the loaded_vmcss_on_cpu list on this cpu
2240 * has been initialized.
2242 * Though the cpu is not in VMX operation now, there
2243 * is no problem to enable the vmclear operation
2244 * for the loaded_vmcss_on_cpu list is empty!
2246 crash_enable_local_vmclear(cpu);
2248 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2250 test_bits = FEATURE_CONTROL_LOCKED;
2251 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2252 if (tboot_enabled())
2253 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2255 if ((old & test_bits) != test_bits) {
2256 /* enable and lock */
2257 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2259 kvm_cpu_vmxon(phys_addr);
2266 static void vmclear_local_loaded_vmcss(void)
2268 int cpu = raw_smp_processor_id();
2269 struct loaded_vmcs *v, *n;
2271 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2272 loaded_vmcss_on_cpu_link)
2273 __loaded_vmcs_clear(v);
2277 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2280 static void kvm_cpu_vmxoff(void)
2282 asm volatile (__ex("vmxoff"));
2284 intel_pt_handle_vmx(0);
2285 cr4_clear_bits(X86_CR4_VMXE);
2288 static void hardware_disable(void)
2290 vmclear_local_loaded_vmcss();
2294 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2295 u32 msr, u32 *result)
2297 u32 vmx_msr_low, vmx_msr_high;
2298 u32 ctl = ctl_min | ctl_opt;
2300 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2302 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2303 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2305 /* Ensure minimum (required) set of control bits are supported. */
2313 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2314 struct vmx_capability *vmx_cap)
2316 u32 vmx_msr_low, vmx_msr_high;
2317 u32 min, opt, min2, opt2;
2318 u32 _pin_based_exec_control = 0;
2319 u32 _cpu_based_exec_control = 0;
2320 u32 _cpu_based_2nd_exec_control = 0;
2321 u32 _vmexit_control = 0;
2322 u32 _vmentry_control = 0;
2324 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2325 min = CPU_BASED_HLT_EXITING |
2326 #ifdef CONFIG_X86_64
2327 CPU_BASED_CR8_LOAD_EXITING |
2328 CPU_BASED_CR8_STORE_EXITING |
2330 CPU_BASED_CR3_LOAD_EXITING |
2331 CPU_BASED_CR3_STORE_EXITING |
2332 CPU_BASED_UNCOND_IO_EXITING |
2333 CPU_BASED_MOV_DR_EXITING |
2334 CPU_BASED_USE_TSC_OFFSETING |
2335 CPU_BASED_MWAIT_EXITING |
2336 CPU_BASED_MONITOR_EXITING |
2337 CPU_BASED_INVLPG_EXITING |
2338 CPU_BASED_RDPMC_EXITING;
2340 opt = CPU_BASED_TPR_SHADOW |
2341 CPU_BASED_USE_MSR_BITMAPS |
2342 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2343 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2344 &_cpu_based_exec_control) < 0)
2346 #ifdef CONFIG_X86_64
2347 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2348 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2349 ~CPU_BASED_CR8_STORE_EXITING;
2351 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2353 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2354 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2355 SECONDARY_EXEC_WBINVD_EXITING |
2356 SECONDARY_EXEC_ENABLE_VPID |
2357 SECONDARY_EXEC_ENABLE_EPT |
2358 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2359 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2360 SECONDARY_EXEC_DESC |
2361 SECONDARY_EXEC_RDTSCP |
2362 SECONDARY_EXEC_ENABLE_INVPCID |
2363 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2364 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2365 SECONDARY_EXEC_SHADOW_VMCS |
2366 SECONDARY_EXEC_XSAVES |
2367 SECONDARY_EXEC_RDSEED_EXITING |
2368 SECONDARY_EXEC_RDRAND_EXITING |
2369 SECONDARY_EXEC_ENABLE_PML |
2370 SECONDARY_EXEC_TSC_SCALING |
2371 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2372 SECONDARY_EXEC_PT_USE_GPA |
2373 SECONDARY_EXEC_PT_CONCEAL_VMX |
2374 SECONDARY_EXEC_ENABLE_VMFUNC |
2375 SECONDARY_EXEC_ENCLS_EXITING;
2376 if (adjust_vmx_controls(min2, opt2,
2377 MSR_IA32_VMX_PROCBASED_CTLS2,
2378 &_cpu_based_2nd_exec_control) < 0)
2381 #ifndef CONFIG_X86_64
2382 if (!(_cpu_based_2nd_exec_control &
2383 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2384 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2387 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2388 _cpu_based_2nd_exec_control &= ~(
2389 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2390 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2391 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2393 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2394 &vmx_cap->ept, &vmx_cap->vpid);
2396 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2397 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2399 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2400 CPU_BASED_CR3_STORE_EXITING |
2401 CPU_BASED_INVLPG_EXITING);
2402 } else if (vmx_cap->ept) {
2404 pr_warn_once("EPT CAP should not exist if not support "
2405 "1-setting enable EPT VM-execution control\n");
2407 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2410 pr_warn_once("VPID CAP should not exist if not support "
2411 "1-setting enable VPID VM-execution control\n");
2414 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2415 #ifdef CONFIG_X86_64
2416 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2418 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2419 VM_EXIT_LOAD_IA32_PAT |
2420 VM_EXIT_LOAD_IA32_EFER |
2421 VM_EXIT_CLEAR_BNDCFGS |
2422 VM_EXIT_PT_CONCEAL_PIP |
2423 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2424 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2425 &_vmexit_control) < 0)
2428 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2429 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2430 PIN_BASED_VMX_PREEMPTION_TIMER;
2431 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2432 &_pin_based_exec_control) < 0)
2435 if (cpu_has_broken_vmx_preemption_timer())
2436 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2437 if (!(_cpu_based_2nd_exec_control &
2438 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2439 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2441 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2442 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2443 VM_ENTRY_LOAD_IA32_PAT |
2444 VM_ENTRY_LOAD_IA32_EFER |
2445 VM_ENTRY_LOAD_BNDCFGS |
2446 VM_ENTRY_PT_CONCEAL_PIP |
2447 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2448 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2449 &_vmentry_control) < 0)
2453 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2454 * can't be used due to an errata where VM Exit may incorrectly clear
2455 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2456 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2458 if (boot_cpu_data.x86 == 0x6) {
2459 switch (boot_cpu_data.x86_model) {
2460 case 26: /* AAK155 */
2461 case 30: /* AAP115 */
2462 case 37: /* AAT100 */
2463 case 44: /* BC86,AAY89,BD102 */
2465 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2466 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2467 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2468 "does not work properly. Using workaround\n");
2476 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2478 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2479 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2482 #ifdef CONFIG_X86_64
2483 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2484 if (vmx_msr_high & (1u<<16))
2488 /* Require Write-Back (WB) memory type for VMCS accesses. */
2489 if (((vmx_msr_high >> 18) & 15) != 6)
2492 vmcs_conf->size = vmx_msr_high & 0x1fff;
2493 vmcs_conf->order = get_order(vmcs_conf->size);
2494 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2496 vmcs_conf->revision_id = vmx_msr_low;
2498 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2499 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2500 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2501 vmcs_conf->vmexit_ctrl = _vmexit_control;
2502 vmcs_conf->vmentry_ctrl = _vmentry_control;
2504 if (static_branch_unlikely(&enable_evmcs))
2505 evmcs_sanitize_exec_ctrls(vmcs_conf);
2510 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2512 int node = cpu_to_node(cpu);
2516 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2519 vmcs = page_address(pages);
2520 memset(vmcs, 0, vmcs_config.size);
2522 /* KVM supports Enlightened VMCS v1 only */
2523 if (static_branch_unlikely(&enable_evmcs))
2524 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2526 vmcs->hdr.revision_id = vmcs_config.revision_id;
2529 vmcs->hdr.shadow_vmcs = 1;
2533 void free_vmcs(struct vmcs *vmcs)
2535 free_pages((unsigned long)vmcs, vmcs_config.order);
2539 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2541 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2543 if (!loaded_vmcs->vmcs)
2545 loaded_vmcs_clear(loaded_vmcs);
2546 free_vmcs(loaded_vmcs->vmcs);
2547 loaded_vmcs->vmcs = NULL;
2548 if (loaded_vmcs->msr_bitmap)
2549 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2550 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2553 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2555 loaded_vmcs->vmcs = alloc_vmcs(false);
2556 if (!loaded_vmcs->vmcs)
2559 loaded_vmcs->shadow_vmcs = NULL;
2560 loaded_vmcs->hv_timer_soft_disabled = false;
2561 loaded_vmcs_init(loaded_vmcs);
2563 if (cpu_has_vmx_msr_bitmap()) {
2564 loaded_vmcs->msr_bitmap = (unsigned long *)
2565 __get_free_page(GFP_KERNEL_ACCOUNT);
2566 if (!loaded_vmcs->msr_bitmap)
2568 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2570 if (IS_ENABLED(CONFIG_HYPERV) &&
2571 static_branch_unlikely(&enable_evmcs) &&
2572 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2573 struct hv_enlightened_vmcs *evmcs =
2574 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2576 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2580 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2581 memset(&loaded_vmcs->controls_shadow, 0,
2582 sizeof(struct vmcs_controls_shadow));
2587 free_loaded_vmcs(loaded_vmcs);
2591 static void free_kvm_area(void)
2595 for_each_possible_cpu(cpu) {
2596 free_vmcs(per_cpu(vmxarea, cpu));
2597 per_cpu(vmxarea, cpu) = NULL;
2601 static __init int alloc_kvm_area(void)
2605 for_each_possible_cpu(cpu) {
2608 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2615 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2616 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2617 * revision_id reported by MSR_IA32_VMX_BASIC.
2619 * However, even though not explicitly documented by
2620 * TLFS, VMXArea passed as VMXON argument should
2621 * still be marked with revision_id reported by
2624 if (static_branch_unlikely(&enable_evmcs))
2625 vmcs->hdr.revision_id = vmcs_config.revision_id;
2627 per_cpu(vmxarea, cpu) = vmcs;
2632 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2633 struct kvm_segment *save)
2635 if (!emulate_invalid_guest_state) {
2637 * CS and SS RPL should be equal during guest entry according
2638 * to VMX spec, but in reality it is not always so. Since vcpu
2639 * is in the middle of the transition from real mode to
2640 * protected mode it is safe to assume that RPL 0 is a good
2643 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2644 save->selector &= ~SEGMENT_RPL_MASK;
2645 save->dpl = save->selector & SEGMENT_RPL_MASK;
2648 vmx_set_segment(vcpu, save, seg);
2651 static void enter_pmode(struct kvm_vcpu *vcpu)
2653 unsigned long flags;
2654 struct vcpu_vmx *vmx = to_vmx(vcpu);
2657 * Update real mode segment cache. It may be not up-to-date if sement
2658 * register was written while vcpu was in a guest mode.
2660 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2661 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2662 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2663 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2664 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2665 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2667 vmx->rmode.vm86_active = 0;
2669 vmx_segment_cache_clear(vmx);
2671 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2673 flags = vmcs_readl(GUEST_RFLAGS);
2674 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2675 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2676 vmcs_writel(GUEST_RFLAGS, flags);
2678 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2679 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2681 update_exception_bitmap(vcpu);
2683 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2684 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2685 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2686 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2687 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2688 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2691 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2693 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2694 struct kvm_segment var = *save;
2697 if (seg == VCPU_SREG_CS)
2700 if (!emulate_invalid_guest_state) {
2701 var.selector = var.base >> 4;
2702 var.base = var.base & 0xffff0;
2712 if (save->base & 0xf)
2713 printk_once(KERN_WARNING "kvm: segment base is not "
2714 "paragraph aligned when entering "
2715 "protected mode (seg=%d)", seg);
2718 vmcs_write16(sf->selector, var.selector);
2719 vmcs_writel(sf->base, var.base);
2720 vmcs_write32(sf->limit, var.limit);
2721 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2724 static void enter_rmode(struct kvm_vcpu *vcpu)
2726 unsigned long flags;
2727 struct vcpu_vmx *vmx = to_vmx(vcpu);
2728 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2730 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2731 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2732 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2733 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2734 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2735 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2736 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2738 vmx->rmode.vm86_active = 1;
2741 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2742 * vcpu. Warn the user that an update is overdue.
2744 if (!kvm_vmx->tss_addr)
2745 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2746 "called before entering vcpu\n");
2748 vmx_segment_cache_clear(vmx);
2750 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2751 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2752 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2754 flags = vmcs_readl(GUEST_RFLAGS);
2755 vmx->rmode.save_rflags = flags;
2757 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2759 vmcs_writel(GUEST_RFLAGS, flags);
2760 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2761 update_exception_bitmap(vcpu);
2763 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2764 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2765 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2766 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2767 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2768 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2770 kvm_mmu_reset_context(vcpu);
2773 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2775 struct vcpu_vmx *vmx = to_vmx(vcpu);
2776 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2781 vcpu->arch.efer = efer;
2782 if (efer & EFER_LMA) {
2783 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2786 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2788 msr->data = efer & ~EFER_LME;
2793 #ifdef CONFIG_X86_64
2795 static void enter_lmode(struct kvm_vcpu *vcpu)
2799 vmx_segment_cache_clear(to_vmx(vcpu));
2801 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2802 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2803 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2805 vmcs_write32(GUEST_TR_AR_BYTES,
2806 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2807 | VMX_AR_TYPE_BUSY_64_TSS);
2809 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2812 static void exit_lmode(struct kvm_vcpu *vcpu)
2814 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2815 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2820 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2822 int vpid = to_vmx(vcpu)->vpid;
2824 if (!vpid_sync_vcpu_addr(vpid, addr))
2825 vpid_sync_context(vpid);
2828 * If VPIDs are not supported or enabled, then the above is a no-op.
2829 * But we don't really need a TLB flush in that case anyway, because
2830 * each VM entry/exit includes an implicit flush when VPID is 0.
2834 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2836 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2838 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2839 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2842 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2844 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2846 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2847 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2850 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2852 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2854 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2857 if (is_pae_paging(vcpu)) {
2858 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2859 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2860 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2861 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2865 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2867 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2869 if (is_pae_paging(vcpu)) {
2870 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2871 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2872 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2873 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2876 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2879 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2881 struct kvm_vcpu *vcpu)
2883 struct vcpu_vmx *vmx = to_vmx(vcpu);
2885 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2886 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2887 if (!(cr0 & X86_CR0_PG)) {
2888 /* From paging/starting to nonpaging */
2889 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2890 CPU_BASED_CR3_STORE_EXITING);
2891 vcpu->arch.cr0 = cr0;
2892 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2893 } else if (!is_paging(vcpu)) {
2894 /* From nonpaging to paging */
2895 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2896 CPU_BASED_CR3_STORE_EXITING);
2897 vcpu->arch.cr0 = cr0;
2898 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2901 if (!(cr0 & X86_CR0_WP))
2902 *hw_cr0 &= ~X86_CR0_WP;
2905 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2907 struct vcpu_vmx *vmx = to_vmx(vcpu);
2908 unsigned long hw_cr0;
2910 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2911 if (enable_unrestricted_guest)
2912 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2914 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2916 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2919 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2923 #ifdef CONFIG_X86_64
2924 if (vcpu->arch.efer & EFER_LME) {
2925 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2927 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2932 if (enable_ept && !enable_unrestricted_guest)
2933 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2935 vmcs_writel(CR0_READ_SHADOW, cr0);
2936 vmcs_writel(GUEST_CR0, hw_cr0);
2937 vcpu->arch.cr0 = cr0;
2939 /* depends on vcpu->arch.cr0 to be set to a new value */
2940 vmx->emulation_required = emulation_required(vcpu);
2943 static int get_ept_level(struct kvm_vcpu *vcpu)
2945 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2950 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2952 u64 eptp = VMX_EPTP_MT_WB;
2954 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2956 if (enable_ept_ad_bits &&
2957 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2958 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2959 eptp |= (root_hpa & PAGE_MASK);
2964 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2966 struct kvm *kvm = vcpu->kvm;
2967 bool update_guest_cr3 = true;
2968 unsigned long guest_cr3;
2973 eptp = construct_eptp(vcpu, cr3);
2974 vmcs_write64(EPT_POINTER, eptp);
2976 if (kvm_x86_ops->tlb_remote_flush) {
2977 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2978 to_vmx(vcpu)->ept_pointer = eptp;
2979 to_kvm_vmx(kvm)->ept_pointers_match
2980 = EPT_POINTERS_CHECK;
2981 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2984 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
2985 if (is_guest_mode(vcpu))
2986 update_guest_cr3 = false;
2987 else if (!enable_unrestricted_guest && !is_paging(vcpu))
2988 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
2989 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2990 guest_cr3 = vcpu->arch.cr3;
2991 else /* vmcs01.GUEST_CR3 is already up-to-date. */
2992 update_guest_cr3 = false;
2993 ept_load_pdptrs(vcpu);
2996 if (update_guest_cr3)
2997 vmcs_writel(GUEST_CR3, guest_cr3);
3000 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3002 struct vcpu_vmx *vmx = to_vmx(vcpu);
3004 * Pass through host's Machine Check Enable value to hw_cr4, which
3005 * is in force while we are in guest mode. Do not let guests control
3006 * this bit, even if host CR4.MCE == 0.
3008 unsigned long hw_cr4;
3010 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3011 if (enable_unrestricted_guest)
3012 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3013 else if (vmx->rmode.vm86_active)
3014 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3016 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3018 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3019 if (cr4 & X86_CR4_UMIP) {
3020 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3021 hw_cr4 &= ~X86_CR4_UMIP;
3022 } else if (!is_guest_mode(vcpu) ||
3023 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3024 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3028 if (cr4 & X86_CR4_VMXE) {
3030 * To use VMXON (and later other VMX instructions), a guest
3031 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3032 * So basically the check on whether to allow nested VMX
3033 * is here. We operate under the default treatment of SMM,
3034 * so VMX cannot be enabled under SMM.
3036 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3040 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3043 vcpu->arch.cr4 = cr4;
3045 if (!enable_unrestricted_guest) {
3047 if (!is_paging(vcpu)) {
3048 hw_cr4 &= ~X86_CR4_PAE;
3049 hw_cr4 |= X86_CR4_PSE;
3050 } else if (!(cr4 & X86_CR4_PAE)) {
3051 hw_cr4 &= ~X86_CR4_PAE;
3056 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3057 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3058 * to be manually disabled when guest switches to non-paging
3061 * If !enable_unrestricted_guest, the CPU is always running
3062 * with CR0.PG=1 and CR4 needs to be modified.
3063 * If enable_unrestricted_guest, the CPU automatically
3064 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3066 if (!is_paging(vcpu))
3067 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3070 vmcs_writel(CR4_READ_SHADOW, cr4);
3071 vmcs_writel(GUEST_CR4, hw_cr4);
3075 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3077 struct vcpu_vmx *vmx = to_vmx(vcpu);
3080 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3081 *var = vmx->rmode.segs[seg];
3082 if (seg == VCPU_SREG_TR
3083 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3085 var->base = vmx_read_guest_seg_base(vmx, seg);
3086 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3089 var->base = vmx_read_guest_seg_base(vmx, seg);
3090 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3091 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3092 ar = vmx_read_guest_seg_ar(vmx, seg);
3093 var->unusable = (ar >> 16) & 1;
3094 var->type = ar & 15;
3095 var->s = (ar >> 4) & 1;
3096 var->dpl = (ar >> 5) & 3;
3098 * Some userspaces do not preserve unusable property. Since usable
3099 * segment has to be present according to VMX spec we can use present
3100 * property to amend userspace bug by making unusable segment always
3101 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3102 * segment as unusable.
3104 var->present = !var->unusable;
3105 var->avl = (ar >> 12) & 1;
3106 var->l = (ar >> 13) & 1;
3107 var->db = (ar >> 14) & 1;
3108 var->g = (ar >> 15) & 1;
3111 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3113 struct kvm_segment s;
3115 if (to_vmx(vcpu)->rmode.vm86_active) {
3116 vmx_get_segment(vcpu, &s, seg);
3119 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3122 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3124 struct vcpu_vmx *vmx = to_vmx(vcpu);
3126 if (unlikely(vmx->rmode.vm86_active))
3129 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3130 return VMX_AR_DPL(ar);
3134 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3138 if (var->unusable || !var->present)
3141 ar = var->type & 15;
3142 ar |= (var->s & 1) << 4;
3143 ar |= (var->dpl & 3) << 5;
3144 ar |= (var->present & 1) << 7;
3145 ar |= (var->avl & 1) << 12;
3146 ar |= (var->l & 1) << 13;
3147 ar |= (var->db & 1) << 14;
3148 ar |= (var->g & 1) << 15;
3154 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3156 struct vcpu_vmx *vmx = to_vmx(vcpu);
3157 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3159 vmx_segment_cache_clear(vmx);
3161 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3162 vmx->rmode.segs[seg] = *var;
3163 if (seg == VCPU_SREG_TR)
3164 vmcs_write16(sf->selector, var->selector);
3166 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3170 vmcs_writel(sf->base, var->base);
3171 vmcs_write32(sf->limit, var->limit);
3172 vmcs_write16(sf->selector, var->selector);
3175 * Fix the "Accessed" bit in AR field of segment registers for older
3177 * IA32 arch specifies that at the time of processor reset the
3178 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3179 * is setting it to 0 in the userland code. This causes invalid guest
3180 * state vmexit when "unrestricted guest" mode is turned on.
3181 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3182 * tree. Newer qemu binaries with that qemu fix would not need this
3185 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3186 var->type |= 0x1; /* Accessed */
3188 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3191 vmx->emulation_required = emulation_required(vcpu);
3194 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3196 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3198 *db = (ar >> 14) & 1;
3199 *l = (ar >> 13) & 1;
3202 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3204 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3205 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3208 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3210 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3211 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3214 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3216 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3217 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3220 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3222 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3223 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3226 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3228 struct kvm_segment var;
3231 vmx_get_segment(vcpu, &var, seg);
3233 if (seg == VCPU_SREG_CS)
3235 ar = vmx_segment_access_rights(&var);
3237 if (var.base != (var.selector << 4))
3239 if (var.limit != 0xffff)
3247 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3249 struct kvm_segment cs;
3250 unsigned int cs_rpl;
3252 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3253 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3257 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3261 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3262 if (cs.dpl > cs_rpl)
3265 if (cs.dpl != cs_rpl)
3271 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3275 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3277 struct kvm_segment ss;
3278 unsigned int ss_rpl;
3280 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3281 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3285 if (ss.type != 3 && ss.type != 7)
3289 if (ss.dpl != ss_rpl) /* DPL != RPL */
3297 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3299 struct kvm_segment var;
3302 vmx_get_segment(vcpu, &var, seg);
3303 rpl = var.selector & SEGMENT_RPL_MASK;
3311 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3312 if (var.dpl < rpl) /* DPL < RPL */
3316 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3322 static bool tr_valid(struct kvm_vcpu *vcpu)
3324 struct kvm_segment tr;
3326 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3330 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3332 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3340 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3342 struct kvm_segment ldtr;
3344 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3348 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3358 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3360 struct kvm_segment cs, ss;
3362 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3363 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3365 return ((cs.selector & SEGMENT_RPL_MASK) ==
3366 (ss.selector & SEGMENT_RPL_MASK));
3370 * Check if guest state is valid. Returns true if valid, false if
3372 * We assume that registers are always usable
3374 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3376 if (enable_unrestricted_guest)
3379 /* real mode guest state checks */
3380 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3381 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3383 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3385 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3387 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3389 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3391 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3394 /* protected mode guest state checks */
3395 if (!cs_ss_rpl_check(vcpu))
3397 if (!code_segment_valid(vcpu))
3399 if (!stack_segment_valid(vcpu))
3401 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3403 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3405 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3407 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3409 if (!tr_valid(vcpu))
3411 if (!ldtr_valid(vcpu))
3415 * - Add checks on RIP
3416 * - Add checks on RFLAGS
3422 static int init_rmode_tss(struct kvm *kvm)
3428 idx = srcu_read_lock(&kvm->srcu);
3429 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3430 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3433 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3434 r = kvm_write_guest_page(kvm, fn++, &data,
3435 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3438 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3441 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3445 r = kvm_write_guest_page(kvm, fn, &data,
3446 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3449 srcu_read_unlock(&kvm->srcu, idx);
3453 static int init_rmode_identity_map(struct kvm *kvm)
3455 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3457 kvm_pfn_t identity_map_pfn;
3460 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3461 mutex_lock(&kvm->slots_lock);
3463 if (likely(kvm_vmx->ept_identity_pagetable_done))
3466 if (!kvm_vmx->ept_identity_map_addr)
3467 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3468 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3470 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3471 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3475 idx = srcu_read_lock(&kvm->srcu);
3476 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3479 /* Set up identity-mapping pagetable for EPT in real mode */
3480 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3481 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3482 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3483 r = kvm_write_guest_page(kvm, identity_map_pfn,
3484 &tmp, i * sizeof(tmp), sizeof(tmp));
3488 kvm_vmx->ept_identity_pagetable_done = true;
3491 srcu_read_unlock(&kvm->srcu, idx);
3494 mutex_unlock(&kvm->slots_lock);
3498 static void seg_setup(int seg)
3500 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3503 vmcs_write16(sf->selector, 0);
3504 vmcs_writel(sf->base, 0);
3505 vmcs_write32(sf->limit, 0xffff);
3507 if (seg == VCPU_SREG_CS)
3508 ar |= 0x08; /* code segment */
3510 vmcs_write32(sf->ar_bytes, ar);
3513 static int alloc_apic_access_page(struct kvm *kvm)
3518 mutex_lock(&kvm->slots_lock);
3519 if (kvm->arch.apic_access_page_done)
3521 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3522 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3526 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3527 if (is_error_page(page)) {
3533 * Do not pin the page in memory, so that memory hot-unplug
3534 * is able to migrate it.
3537 kvm->arch.apic_access_page_done = true;
3539 mutex_unlock(&kvm->slots_lock);
3543 int allocate_vpid(void)
3549 spin_lock(&vmx_vpid_lock);
3550 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3551 if (vpid < VMX_NR_VPIDS)
3552 __set_bit(vpid, vmx_vpid_bitmap);
3555 spin_unlock(&vmx_vpid_lock);
3559 void free_vpid(int vpid)
3561 if (!enable_vpid || vpid == 0)
3563 spin_lock(&vmx_vpid_lock);
3564 __clear_bit(vpid, vmx_vpid_bitmap);
3565 spin_unlock(&vmx_vpid_lock);
3568 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3571 int f = sizeof(unsigned long);
3573 if (!cpu_has_vmx_msr_bitmap())
3576 if (static_branch_unlikely(&enable_evmcs))
3577 evmcs_touch_msr_bitmap();
3580 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3581 * have the write-low and read-high bitmap offsets the wrong way round.
3582 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3584 if (msr <= 0x1fff) {
3585 if (type & MSR_TYPE_R)
3587 __clear_bit(msr, msr_bitmap + 0x000 / f);
3589 if (type & MSR_TYPE_W)
3591 __clear_bit(msr, msr_bitmap + 0x800 / f);
3593 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3595 if (type & MSR_TYPE_R)
3597 __clear_bit(msr, msr_bitmap + 0x400 / f);
3599 if (type & MSR_TYPE_W)
3601 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3606 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3609 int f = sizeof(unsigned long);
3611 if (!cpu_has_vmx_msr_bitmap())
3614 if (static_branch_unlikely(&enable_evmcs))
3615 evmcs_touch_msr_bitmap();
3618 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3619 * have the write-low and read-high bitmap offsets the wrong way round.
3620 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3622 if (msr <= 0x1fff) {
3623 if (type & MSR_TYPE_R)
3625 __set_bit(msr, msr_bitmap + 0x000 / f);
3627 if (type & MSR_TYPE_W)
3629 __set_bit(msr, msr_bitmap + 0x800 / f);
3631 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3633 if (type & MSR_TYPE_R)
3635 __set_bit(msr, msr_bitmap + 0x400 / f);
3637 if (type & MSR_TYPE_W)
3639 __set_bit(msr, msr_bitmap + 0xc00 / f);
3644 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3645 u32 msr, int type, bool value)
3648 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3650 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3653 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3657 if (cpu_has_secondary_exec_ctrls() &&
3658 (secondary_exec_controls_get(to_vmx(vcpu)) &
3659 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3660 mode |= MSR_BITMAP_MODE_X2APIC;
3661 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3662 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3668 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3673 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3674 unsigned word = msr / BITS_PER_LONG;
3675 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3676 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3679 if (mode & MSR_BITMAP_MODE_X2APIC) {
3681 * TPR reads and writes can be virtualized even if virtual interrupt
3682 * delivery is not in use.
3684 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3685 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3686 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3687 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3688 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3693 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3695 struct vcpu_vmx *vmx = to_vmx(vcpu);
3696 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3697 u8 mode = vmx_msr_bitmap_mode(vcpu);
3698 u8 changed = mode ^ vmx->msr_bitmap_mode;
3703 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3704 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3706 vmx->msr_bitmap_mode = mode;
3709 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3711 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3712 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3715 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3717 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3719 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3721 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3723 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3724 vmx_set_intercept_for_msr(msr_bitmap,
3725 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3726 vmx_set_intercept_for_msr(msr_bitmap,
3727 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3731 static bool vmx_get_enable_apicv(struct kvm *kvm)
3733 return enable_apicv;
3736 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3738 struct vcpu_vmx *vmx = to_vmx(vcpu);
3743 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3744 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3745 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3748 rvi = vmx_get_rvi();
3750 vapic_page = vmx->nested.virtual_apic_map.hva;
3751 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3753 return ((rvi & 0xf0) > (vppr & 0xf0));
3756 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3760 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3762 if (vcpu->mode == IN_GUEST_MODE) {
3764 * The vector of interrupt to be delivered to vcpu had
3765 * been set in PIR before this function.
3767 * Following cases will be reached in this block, and
3768 * we always send a notification event in all cases as
3771 * Case 1: vcpu keeps in non-root mode. Sending a
3772 * notification event posts the interrupt to vcpu.
3774 * Case 2: vcpu exits to root mode and is still
3775 * runnable. PIR will be synced to vIRR before the
3776 * next vcpu entry. Sending a notification event in
3777 * this case has no effect, as vcpu is not in root
3780 * Case 3: vcpu exits to root mode and is blocked.
3781 * vcpu_block() has already synced PIR to vIRR and
3782 * never blocks vcpu if vIRR is not cleared. Therefore,
3783 * a blocked vcpu here does not wait for any requested
3784 * interrupts in PIR, and sending a notification event
3785 * which has no effect is safe here.
3788 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3795 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3798 struct vcpu_vmx *vmx = to_vmx(vcpu);
3800 if (is_guest_mode(vcpu) &&
3801 vector == vmx->nested.posted_intr_nv) {
3803 * If a posted intr is not recognized by hardware,
3804 * we will accomplish it in the next vmentry.
3806 vmx->nested.pi_pending = true;
3807 kvm_make_request(KVM_REQ_EVENT, vcpu);
3808 /* the PIR and ON have been set by L1. */
3809 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3810 kvm_vcpu_kick(vcpu);
3816 * Send interrupt to vcpu via posted interrupt way.
3817 * 1. If target vcpu is running(non-root mode), send posted interrupt
3818 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3819 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3820 * interrupt from PIR in next vmentry.
3822 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3824 struct vcpu_vmx *vmx = to_vmx(vcpu);
3827 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3831 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3834 /* If a previous notification has sent the IPI, nothing to do. */
3835 if (pi_test_and_set_on(&vmx->pi_desc))
3838 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3839 kvm_vcpu_kick(vcpu);
3843 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3844 * will not change in the lifetime of the guest.
3845 * Note that host-state that does change is set elsewhere. E.g., host-state
3846 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3848 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3852 unsigned long cr0, cr3, cr4;
3855 WARN_ON(cr0 & X86_CR0_TS);
3856 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3859 * Save the most likely value for this task's CR3 in the VMCS.
3860 * We can't use __get_current_cr3_fast() because we're not atomic.
3863 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
3864 vmx->loaded_vmcs->host_state.cr3 = cr3;
3866 /* Save the most likely value for this task's CR4 in the VMCS. */
3867 cr4 = cr4_read_shadow();
3868 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
3869 vmx->loaded_vmcs->host_state.cr4 = cr4;
3871 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3872 #ifdef CONFIG_X86_64
3874 * Load null selectors, so we can avoid reloading them in
3875 * vmx_prepare_switch_to_host(), in case userspace uses
3876 * the null selectors too (the expected case).
3878 vmcs_write16(HOST_DS_SELECTOR, 0);
3879 vmcs_write16(HOST_ES_SELECTOR, 0);
3881 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3882 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3884 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3885 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3887 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
3889 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3891 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3892 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3893 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3894 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3896 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3897 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3898 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3901 if (cpu_has_load_ia32_efer())
3902 vmcs_write64(HOST_IA32_EFER, host_efer);
3905 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3907 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3909 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3910 if (is_guest_mode(&vmx->vcpu))
3911 vmx->vcpu.arch.cr4_guest_owned_bits &=
3912 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3913 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3916 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3918 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3920 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3921 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3924 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3926 if (!enable_preemption_timer)
3927 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3929 return pin_based_exec_ctrl;
3932 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3934 struct vcpu_vmx *vmx = to_vmx(vcpu);
3936 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3937 if (cpu_has_secondary_exec_ctrls()) {
3938 if (kvm_vcpu_apicv_active(vcpu))
3939 secondary_exec_controls_setbit(vmx,
3940 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3941 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3943 secondary_exec_controls_clearbit(vmx,
3944 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3945 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3948 if (cpu_has_vmx_msr_bitmap())
3949 vmx_update_msr_bitmap(vcpu);
3952 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3954 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3956 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3957 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3959 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3960 exec_control &= ~CPU_BASED_TPR_SHADOW;
3961 #ifdef CONFIG_X86_64
3962 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3963 CPU_BASED_CR8_LOAD_EXITING;
3967 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3968 CPU_BASED_CR3_LOAD_EXITING |
3969 CPU_BASED_INVLPG_EXITING;
3970 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3971 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3972 CPU_BASED_MONITOR_EXITING);
3973 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3974 exec_control &= ~CPU_BASED_HLT_EXITING;
3975 return exec_control;
3979 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
3981 struct kvm_vcpu *vcpu = &vmx->vcpu;
3983 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3985 if (pt_mode == PT_MODE_SYSTEM)
3986 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
3987 if (!cpu_need_virtualize_apic_accesses(vcpu))
3988 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3990 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3992 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3993 enable_unrestricted_guest = 0;
3995 if (!enable_unrestricted_guest)
3996 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3997 if (kvm_pause_in_guest(vmx->vcpu.kvm))
3998 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3999 if (!kvm_vcpu_apicv_active(vcpu))
4000 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4001 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4002 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4004 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4005 * in vmx_set_cr4. */
4006 exec_control &= ~SECONDARY_EXEC_DESC;
4008 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4010 We can NOT enable shadow_vmcs here because we don't have yet
4013 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4016 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4018 if (vmx_xsaves_supported()) {
4019 /* Exposing XSAVES only when XSAVE is exposed */
4020 bool xsaves_enabled =
4021 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4022 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4024 vcpu->arch.xsaves_enabled = xsaves_enabled;
4026 if (!xsaves_enabled)
4027 exec_control &= ~SECONDARY_EXEC_XSAVES;
4031 vmx->nested.msrs.secondary_ctls_high |=
4032 SECONDARY_EXEC_XSAVES;
4034 vmx->nested.msrs.secondary_ctls_high &=
4035 ~SECONDARY_EXEC_XSAVES;
4039 if (vmx_rdtscp_supported()) {
4040 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4041 if (!rdtscp_enabled)
4042 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4046 vmx->nested.msrs.secondary_ctls_high |=
4047 SECONDARY_EXEC_RDTSCP;
4049 vmx->nested.msrs.secondary_ctls_high &=
4050 ~SECONDARY_EXEC_RDTSCP;
4054 if (vmx_invpcid_supported()) {
4055 /* Exposing INVPCID only when PCID is exposed */
4056 bool invpcid_enabled =
4057 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4058 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4060 if (!invpcid_enabled) {
4061 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4062 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4066 if (invpcid_enabled)
4067 vmx->nested.msrs.secondary_ctls_high |=
4068 SECONDARY_EXEC_ENABLE_INVPCID;
4070 vmx->nested.msrs.secondary_ctls_high &=
4071 ~SECONDARY_EXEC_ENABLE_INVPCID;
4075 if (vmx_rdrand_supported()) {
4076 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4078 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4082 vmx->nested.msrs.secondary_ctls_high |=
4083 SECONDARY_EXEC_RDRAND_EXITING;
4085 vmx->nested.msrs.secondary_ctls_high &=
4086 ~SECONDARY_EXEC_RDRAND_EXITING;
4090 if (vmx_rdseed_supported()) {
4091 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4093 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4097 vmx->nested.msrs.secondary_ctls_high |=
4098 SECONDARY_EXEC_RDSEED_EXITING;
4100 vmx->nested.msrs.secondary_ctls_high &=
4101 ~SECONDARY_EXEC_RDSEED_EXITING;
4105 if (vmx_waitpkg_supported()) {
4106 bool waitpkg_enabled =
4107 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4109 if (!waitpkg_enabled)
4110 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4113 if (waitpkg_enabled)
4114 vmx->nested.msrs.secondary_ctls_high |=
4115 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4117 vmx->nested.msrs.secondary_ctls_high &=
4118 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4122 vmx->secondary_exec_control = exec_control;
4125 static void ept_set_mmio_spte_mask(void)
4128 * EPT Misconfigurations can be generated if the value of bits 2:0
4129 * of an EPT paging-structure entry is 110b (write/execute).
4131 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4132 VMX_EPT_MISCONFIG_WX_VALUE, 0);
4135 #define VMX_XSS_EXIT_BITMAP 0
4138 * Noting that the initialization of Guest-state Area of VMCS is in
4141 static void init_vmcs(struct vcpu_vmx *vmx)
4144 nested_vmx_set_vmcs_shadowing_bitmap();
4146 if (cpu_has_vmx_msr_bitmap())
4147 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4149 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4152 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4154 exec_controls_set(vmx, vmx_exec_control(vmx));
4156 if (cpu_has_secondary_exec_ctrls()) {
4157 vmx_compute_secondary_exec_control(vmx);
4158 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4161 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4162 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4163 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4164 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4165 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4167 vmcs_write16(GUEST_INTR_STATUS, 0);
4169 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4170 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4173 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4174 vmcs_write32(PLE_GAP, ple_gap);
4175 vmx->ple_window = ple_window;
4176 vmx->ple_window_dirty = true;
4179 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4180 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4181 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4183 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4184 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4185 vmx_set_constant_host_state(vmx);
4186 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4187 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4189 if (cpu_has_vmx_vmfunc())
4190 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4192 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4193 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4194 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4195 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4196 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4198 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4199 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4201 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4203 /* 22.2.1, 20.8.1 */
4204 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4206 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4207 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4209 set_cr4_guest_host_mask(vmx);
4212 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4214 if (vmx_xsaves_supported())
4215 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4218 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4219 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4222 if (cpu_has_vmx_encls_vmexit())
4223 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4225 if (pt_mode == PT_MODE_HOST_GUEST) {
4226 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4227 /* Bit[6~0] are forced to 1, writes are ignored. */
4228 vmx->pt_desc.guest.output_mask = 0x7F;
4229 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4233 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4235 struct vcpu_vmx *vmx = to_vmx(vcpu);
4236 struct msr_data apic_base_msr;
4239 vmx->rmode.vm86_active = 0;
4242 vmx->msr_ia32_umwait_control = 0;
4244 vcpu->arch.microcode_version = 0x100000000ULL;
4245 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4246 vmx->hv_deadline_tsc = -1;
4247 kvm_set_cr8(vcpu, 0);
4250 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4251 MSR_IA32_APICBASE_ENABLE;
4252 if (kvm_vcpu_is_reset_bsp(vcpu))
4253 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4254 apic_base_msr.host_initiated = true;
4255 kvm_set_apic_base(vcpu, &apic_base_msr);
4258 vmx_segment_cache_clear(vmx);
4260 seg_setup(VCPU_SREG_CS);
4261 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4262 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4264 seg_setup(VCPU_SREG_DS);
4265 seg_setup(VCPU_SREG_ES);
4266 seg_setup(VCPU_SREG_FS);
4267 seg_setup(VCPU_SREG_GS);
4268 seg_setup(VCPU_SREG_SS);
4270 vmcs_write16(GUEST_TR_SELECTOR, 0);
4271 vmcs_writel(GUEST_TR_BASE, 0);
4272 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4273 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4275 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4276 vmcs_writel(GUEST_LDTR_BASE, 0);
4277 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4278 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4281 vmcs_write32(GUEST_SYSENTER_CS, 0);
4282 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4283 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4284 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4287 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4288 kvm_rip_write(vcpu, 0xfff0);
4290 vmcs_writel(GUEST_GDTR_BASE, 0);
4291 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4293 vmcs_writel(GUEST_IDTR_BASE, 0);
4294 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4296 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4297 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4298 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4299 if (kvm_mpx_supported())
4300 vmcs_write64(GUEST_BNDCFGS, 0);
4304 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4306 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4307 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4308 if (cpu_need_tpr_shadow(vcpu))
4309 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4310 __pa(vcpu->arch.apic->regs));
4311 vmcs_write32(TPR_THRESHOLD, 0);
4314 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4316 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4317 vmx->vcpu.arch.cr0 = cr0;
4318 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4319 vmx_set_cr4(vcpu, 0);
4320 vmx_set_efer(vcpu, 0);
4322 update_exception_bitmap(vcpu);
4324 vpid_sync_context(vmx->vpid);
4326 vmx_clear_hlt(vcpu);
4329 static void enable_irq_window(struct kvm_vcpu *vcpu)
4331 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4334 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4337 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4338 enable_irq_window(vcpu);
4342 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
4345 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4347 struct vcpu_vmx *vmx = to_vmx(vcpu);
4349 int irq = vcpu->arch.interrupt.nr;
4351 trace_kvm_inj_virq(irq);
4353 ++vcpu->stat.irq_injections;
4354 if (vmx->rmode.vm86_active) {
4356 if (vcpu->arch.interrupt.soft)
4357 inc_eip = vcpu->arch.event_exit_inst_len;
4358 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4361 intr = irq | INTR_INFO_VALID_MASK;
4362 if (vcpu->arch.interrupt.soft) {
4363 intr |= INTR_TYPE_SOFT_INTR;
4364 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4365 vmx->vcpu.arch.event_exit_inst_len);
4367 intr |= INTR_TYPE_EXT_INTR;
4368 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4370 vmx_clear_hlt(vcpu);
4373 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4375 struct vcpu_vmx *vmx = to_vmx(vcpu);
4379 * Tracking the NMI-blocked state in software is built upon
4380 * finding the next open IRQ window. This, in turn, depends on
4381 * well-behaving guests: They have to keep IRQs disabled at
4382 * least as long as the NMI handler runs. Otherwise we may
4383 * cause NMI nesting, maybe breaking the guest. But as this is
4384 * highly unlikely, we can live with the residual risk.
4386 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4387 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4390 ++vcpu->stat.nmi_injections;
4391 vmx->loaded_vmcs->nmi_known_unmasked = false;
4393 if (vmx->rmode.vm86_active) {
4394 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4398 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4399 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4401 vmx_clear_hlt(vcpu);
4404 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4406 struct vcpu_vmx *vmx = to_vmx(vcpu);
4410 return vmx->loaded_vmcs->soft_vnmi_blocked;
4411 if (vmx->loaded_vmcs->nmi_known_unmasked)
4413 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4414 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4418 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4420 struct vcpu_vmx *vmx = to_vmx(vcpu);
4423 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4424 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4425 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4428 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4430 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4431 GUEST_INTR_STATE_NMI);
4433 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4434 GUEST_INTR_STATE_NMI);
4438 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4440 if (to_vmx(vcpu)->nested.nested_run_pending)
4444 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4447 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4448 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4449 | GUEST_INTR_STATE_NMI));
4452 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4454 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4455 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4456 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4457 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4460 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4464 if (enable_unrestricted_guest)
4467 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4471 to_kvm_vmx(kvm)->tss_addr = addr;
4472 return init_rmode_tss(kvm);
4475 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4477 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4481 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4486 * Update instruction length as we may reinject the exception
4487 * from user space while in guest debugging mode.
4489 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4490 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4491 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4495 if (vcpu->guest_debug &
4496 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4513 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4514 int vec, u32 err_code)
4517 * Instruction with address size override prefix opcode 0x67
4518 * Cause the #SS fault with 0 error code in VM86 mode.
4520 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4521 if (kvm_emulate_instruction(vcpu, 0)) {
4522 if (vcpu->arch.halt_request) {
4523 vcpu->arch.halt_request = 0;
4524 return kvm_vcpu_halt(vcpu);
4532 * Forward all other exceptions that are valid in real mode.
4533 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4534 * the required debugging infrastructure rework.
4536 kvm_queue_exception(vcpu, vec);
4541 * Trigger machine check on the host. We assume all the MSRs are already set up
4542 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4543 * We pass a fake environment to the machine check handler because we want
4544 * the guest to be always treated like user space, no matter what context
4545 * it used internally.
4547 static void kvm_machine_check(void)
4549 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4550 struct pt_regs regs = {
4551 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4552 .flags = X86_EFLAGS_IF,
4555 do_machine_check(®s, 0);
4559 static int handle_machine_check(struct kvm_vcpu *vcpu)
4561 /* handled by vmx_vcpu_run() */
4565 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4567 struct vcpu_vmx *vmx = to_vmx(vcpu);
4568 struct kvm_run *kvm_run = vcpu->run;
4569 u32 intr_info, ex_no, error_code;
4570 unsigned long cr2, rip, dr6;
4573 vect_info = vmx->idt_vectoring_info;
4574 intr_info = vmx->exit_intr_info;
4576 if (is_machine_check(intr_info) || is_nmi(intr_info))
4577 return 1; /* handled by handle_exception_nmi_irqoff() */
4579 if (is_invalid_opcode(intr_info))
4580 return handle_ud(vcpu);
4583 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4584 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4586 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4587 WARN_ON_ONCE(!enable_vmware_backdoor);
4590 * VMware backdoor emulation on #GP interception only handles
4591 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4592 * error code on #GP.
4595 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4598 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4602 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4603 * MMIO, it is better to report an internal error.
4604 * See the comments in vmx_handle_exit.
4606 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4607 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4608 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4609 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4610 vcpu->run->internal.ndata = 3;
4611 vcpu->run->internal.data[0] = vect_info;
4612 vcpu->run->internal.data[1] = intr_info;
4613 vcpu->run->internal.data[2] = error_code;
4617 if (is_page_fault(intr_info)) {
4618 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4619 /* EPT won't cause page fault directly */
4620 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4621 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4624 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4626 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4627 return handle_rmode_exception(vcpu, ex_no, error_code);
4631 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4634 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4635 if (!(vcpu->guest_debug &
4636 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4637 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4638 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4639 if (is_icebp(intr_info))
4640 WARN_ON(!skip_emulated_instruction(vcpu));
4642 kvm_queue_exception(vcpu, DB_VECTOR);
4645 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4646 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4650 * Update instruction length as we may reinject #BP from
4651 * user space while in guest debugging mode. Reading it for
4652 * #DB as well causes no harm, it is not used in that case.
4654 vmx->vcpu.arch.event_exit_inst_len =
4655 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4656 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4657 rip = kvm_rip_read(vcpu);
4658 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4659 kvm_run->debug.arch.exception = ex_no;
4662 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4663 kvm_run->ex.exception = ex_no;
4664 kvm_run->ex.error_code = error_code;
4670 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4672 ++vcpu->stat.irq_exits;
4676 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4678 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4679 vcpu->mmio_needed = 0;
4683 static int handle_io(struct kvm_vcpu *vcpu)
4685 unsigned long exit_qualification;
4686 int size, in, string;
4689 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4690 string = (exit_qualification & 16) != 0;
4692 ++vcpu->stat.io_exits;
4695 return kvm_emulate_instruction(vcpu, 0);
4697 port = exit_qualification >> 16;
4698 size = (exit_qualification & 7) + 1;
4699 in = (exit_qualification & 8) != 0;
4701 return kvm_fast_pio(vcpu, size, port, in);
4705 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4708 * Patch in the VMCALL instruction:
4710 hypercall[0] = 0x0f;
4711 hypercall[1] = 0x01;
4712 hypercall[2] = 0xc1;
4715 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4716 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4718 if (is_guest_mode(vcpu)) {
4719 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4720 unsigned long orig_val = val;
4723 * We get here when L2 changed cr0 in a way that did not change
4724 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4725 * but did change L0 shadowed bits. So we first calculate the
4726 * effective cr0 value that L1 would like to write into the
4727 * hardware. It consists of the L2-owned bits from the new
4728 * value combined with the L1-owned bits from L1's guest_cr0.
4730 val = (val & ~vmcs12->cr0_guest_host_mask) |
4731 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4733 if (!nested_guest_cr0_valid(vcpu, val))
4736 if (kvm_set_cr0(vcpu, val))
4738 vmcs_writel(CR0_READ_SHADOW, orig_val);
4741 if (to_vmx(vcpu)->nested.vmxon &&
4742 !nested_host_cr0_valid(vcpu, val))
4745 return kvm_set_cr0(vcpu, val);
4749 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4751 if (is_guest_mode(vcpu)) {
4752 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4753 unsigned long orig_val = val;
4755 /* analogously to handle_set_cr0 */
4756 val = (val & ~vmcs12->cr4_guest_host_mask) |
4757 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4758 if (kvm_set_cr4(vcpu, val))
4760 vmcs_writel(CR4_READ_SHADOW, orig_val);
4763 return kvm_set_cr4(vcpu, val);
4766 static int handle_desc(struct kvm_vcpu *vcpu)
4768 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4769 return kvm_emulate_instruction(vcpu, 0);
4772 static int handle_cr(struct kvm_vcpu *vcpu)
4774 unsigned long exit_qualification, val;
4780 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4781 cr = exit_qualification & 15;
4782 reg = (exit_qualification >> 8) & 15;
4783 switch ((exit_qualification >> 4) & 3) {
4784 case 0: /* mov to cr */
4785 val = kvm_register_readl(vcpu, reg);
4786 trace_kvm_cr_write(cr, val);
4789 err = handle_set_cr0(vcpu, val);
4790 return kvm_complete_insn_gp(vcpu, err);
4792 WARN_ON_ONCE(enable_unrestricted_guest);
4793 err = kvm_set_cr3(vcpu, val);
4794 return kvm_complete_insn_gp(vcpu, err);
4796 err = handle_set_cr4(vcpu, val);
4797 return kvm_complete_insn_gp(vcpu, err);
4799 u8 cr8_prev = kvm_get_cr8(vcpu);
4801 err = kvm_set_cr8(vcpu, cr8);
4802 ret = kvm_complete_insn_gp(vcpu, err);
4803 if (lapic_in_kernel(vcpu))
4805 if (cr8_prev <= cr8)
4808 * TODO: we might be squashing a
4809 * KVM_GUESTDBG_SINGLESTEP-triggered
4810 * KVM_EXIT_DEBUG here.
4812 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4818 WARN_ONCE(1, "Guest should always own CR0.TS");
4819 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4820 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4821 return kvm_skip_emulated_instruction(vcpu);
4822 case 1: /*mov from cr*/
4825 WARN_ON_ONCE(enable_unrestricted_guest);
4826 val = kvm_read_cr3(vcpu);
4827 kvm_register_write(vcpu, reg, val);
4828 trace_kvm_cr_read(cr, val);
4829 return kvm_skip_emulated_instruction(vcpu);
4831 val = kvm_get_cr8(vcpu);
4832 kvm_register_write(vcpu, reg, val);
4833 trace_kvm_cr_read(cr, val);
4834 return kvm_skip_emulated_instruction(vcpu);
4838 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4839 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4840 kvm_lmsw(vcpu, val);
4842 return kvm_skip_emulated_instruction(vcpu);
4846 vcpu->run->exit_reason = 0;
4847 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4848 (int)(exit_qualification >> 4) & 3, cr);
4852 static int handle_dr(struct kvm_vcpu *vcpu)
4854 unsigned long exit_qualification;
4857 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4858 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4860 /* First, if DR does not exist, trigger UD */
4861 if (!kvm_require_dr(vcpu, dr))
4864 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4865 if (!kvm_require_cpl(vcpu, 0))
4867 dr7 = vmcs_readl(GUEST_DR7);
4870 * As the vm-exit takes precedence over the debug trap, we
4871 * need to emulate the latter, either for the host or the
4872 * guest debugging itself.
4874 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4875 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4876 vcpu->run->debug.arch.dr7 = dr7;
4877 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4878 vcpu->run->debug.arch.exception = DB_VECTOR;
4879 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4882 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4883 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4884 kvm_queue_exception(vcpu, DB_VECTOR);
4889 if (vcpu->guest_debug == 0) {
4890 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4893 * No more DR vmexits; force a reload of the debug registers
4894 * and reenter on this instruction. The next vmexit will
4895 * retrieve the full state of the debug registers.
4897 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4901 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4902 if (exit_qualification & TYPE_MOV_FROM_DR) {
4905 if (kvm_get_dr(vcpu, dr, &val))
4907 kvm_register_write(vcpu, reg, val);
4909 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4912 return kvm_skip_emulated_instruction(vcpu);
4915 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4917 return vcpu->arch.dr6;
4920 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4924 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4926 get_debugreg(vcpu->arch.db[0], 0);
4927 get_debugreg(vcpu->arch.db[1], 1);
4928 get_debugreg(vcpu->arch.db[2], 2);
4929 get_debugreg(vcpu->arch.db[3], 3);
4930 get_debugreg(vcpu->arch.dr6, 6);
4931 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4933 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4934 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4937 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4939 vmcs_writel(GUEST_DR7, val);
4942 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4944 kvm_apic_update_ppr(vcpu);
4948 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4950 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4952 kvm_make_request(KVM_REQ_EVENT, vcpu);
4954 ++vcpu->stat.irq_window_exits;
4958 static int handle_vmcall(struct kvm_vcpu *vcpu)
4960 return kvm_emulate_hypercall(vcpu);
4963 static int handle_invd(struct kvm_vcpu *vcpu)
4965 return kvm_emulate_instruction(vcpu, 0);
4968 static int handle_invlpg(struct kvm_vcpu *vcpu)
4970 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4972 kvm_mmu_invlpg(vcpu, exit_qualification);
4973 return kvm_skip_emulated_instruction(vcpu);
4976 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4980 err = kvm_rdpmc(vcpu);
4981 return kvm_complete_insn_gp(vcpu, err);
4984 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4986 return kvm_emulate_wbinvd(vcpu);
4989 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4991 u64 new_bv = kvm_read_edx_eax(vcpu);
4992 u32 index = kvm_rcx_read(vcpu);
4994 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4995 return kvm_skip_emulated_instruction(vcpu);
4999 static int handle_apic_access(struct kvm_vcpu *vcpu)
5001 if (likely(fasteoi)) {
5002 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5003 int access_type, offset;
5005 access_type = exit_qualification & APIC_ACCESS_TYPE;
5006 offset = exit_qualification & APIC_ACCESS_OFFSET;
5008 * Sane guest uses MOV to write EOI, with written value
5009 * not cared. So make a short-circuit here by avoiding
5010 * heavy instruction emulation.
5012 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5013 (offset == APIC_EOI)) {
5014 kvm_lapic_set_eoi(vcpu);
5015 return kvm_skip_emulated_instruction(vcpu);
5018 return kvm_emulate_instruction(vcpu, 0);
5021 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5023 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5024 int vector = exit_qualification & 0xff;
5026 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5027 kvm_apic_set_eoi_accelerated(vcpu, vector);
5031 static int handle_apic_write(struct kvm_vcpu *vcpu)
5033 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5034 u32 offset = exit_qualification & 0xfff;
5036 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5037 kvm_apic_write_nodecode(vcpu, offset);
5041 static int handle_task_switch(struct kvm_vcpu *vcpu)
5043 struct vcpu_vmx *vmx = to_vmx(vcpu);
5044 unsigned long exit_qualification;
5045 bool has_error_code = false;
5048 int reason, type, idt_v, idt_index;
5050 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5051 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5052 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5054 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5056 reason = (u32)exit_qualification >> 30;
5057 if (reason == TASK_SWITCH_GATE && idt_v) {
5059 case INTR_TYPE_NMI_INTR:
5060 vcpu->arch.nmi_injected = false;
5061 vmx_set_nmi_mask(vcpu, true);
5063 case INTR_TYPE_EXT_INTR:
5064 case INTR_TYPE_SOFT_INTR:
5065 kvm_clear_interrupt_queue(vcpu);
5067 case INTR_TYPE_HARD_EXCEPTION:
5068 if (vmx->idt_vectoring_info &
5069 VECTORING_INFO_DELIVER_CODE_MASK) {
5070 has_error_code = true;
5072 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5075 case INTR_TYPE_SOFT_EXCEPTION:
5076 kvm_clear_exception_queue(vcpu);
5082 tss_selector = exit_qualification;
5084 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5085 type != INTR_TYPE_EXT_INTR &&
5086 type != INTR_TYPE_NMI_INTR))
5087 WARN_ON(!skip_emulated_instruction(vcpu));
5090 * TODO: What about debug traps on tss switch?
5091 * Are we supposed to inject them and update dr6?
5093 return kvm_task_switch(vcpu, tss_selector,
5094 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5095 reason, has_error_code, error_code);
5098 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5100 unsigned long exit_qualification;
5104 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5107 * EPT violation happened while executing iret from NMI,
5108 * "blocked by NMI" bit has to be set before next VM entry.
5109 * There are errata that may cause this bit to not be set:
5112 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5114 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5115 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5117 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5118 trace_kvm_page_fault(gpa, exit_qualification);
5120 /* Is it a read fault? */
5121 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5122 ? PFERR_USER_MASK : 0;
5123 /* Is it a write fault? */
5124 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5125 ? PFERR_WRITE_MASK : 0;
5126 /* Is it a fetch fault? */
5127 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5128 ? PFERR_FETCH_MASK : 0;
5129 /* ept page table entry is present? */
5130 error_code |= (exit_qualification &
5131 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5132 EPT_VIOLATION_EXECUTABLE))
5133 ? PFERR_PRESENT_MASK : 0;
5135 error_code |= (exit_qualification & 0x100) != 0 ?
5136 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5138 vcpu->arch.exit_qualification = exit_qualification;
5139 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5142 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5147 * A nested guest cannot optimize MMIO vmexits, because we have an
5148 * nGPA here instead of the required GPA.
5150 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5151 if (!is_guest_mode(vcpu) &&
5152 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5153 trace_kvm_fast_mmio(gpa);
5154 return kvm_skip_emulated_instruction(vcpu);
5157 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5160 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5162 WARN_ON_ONCE(!enable_vnmi);
5163 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
5164 ++vcpu->stat.nmi_window_exits;
5165 kvm_make_request(KVM_REQ_EVENT, vcpu);
5170 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5172 struct vcpu_vmx *vmx = to_vmx(vcpu);
5173 bool intr_window_requested;
5174 unsigned count = 130;
5177 * We should never reach the point where we are emulating L2
5178 * due to invalid guest state as that means we incorrectly
5179 * allowed a nested VMEntry with an invalid vmcs12.
5181 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5183 intr_window_requested = exec_controls_get(vmx) &
5184 CPU_BASED_VIRTUAL_INTR_PENDING;
5186 while (vmx->emulation_required && count-- != 0) {
5187 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5188 return handle_interrupt_window(&vmx->vcpu);
5190 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5193 if (!kvm_emulate_instruction(vcpu, 0))
5196 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5197 vcpu->arch.exception.pending) {
5198 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5199 vcpu->run->internal.suberror =
5200 KVM_INTERNAL_ERROR_EMULATION;
5201 vcpu->run->internal.ndata = 0;
5205 if (vcpu->arch.halt_request) {
5206 vcpu->arch.halt_request = 0;
5207 return kvm_vcpu_halt(vcpu);
5211 * Note, return 1 and not 0, vcpu_run() is responsible for
5212 * morphing the pending signal into the proper return code.
5214 if (signal_pending(current))
5224 static void grow_ple_window(struct kvm_vcpu *vcpu)
5226 struct vcpu_vmx *vmx = to_vmx(vcpu);
5227 unsigned int old = vmx->ple_window;
5229 vmx->ple_window = __grow_ple_window(old, ple_window,
5233 if (vmx->ple_window != old) {
5234 vmx->ple_window_dirty = true;
5235 trace_kvm_ple_window_update(vcpu->vcpu_id,
5236 vmx->ple_window, old);
5240 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5242 struct vcpu_vmx *vmx = to_vmx(vcpu);
5243 unsigned int old = vmx->ple_window;
5245 vmx->ple_window = __shrink_ple_window(old, ple_window,
5249 if (vmx->ple_window != old) {
5250 vmx->ple_window_dirty = true;
5251 trace_kvm_ple_window_update(vcpu->vcpu_id,
5252 vmx->ple_window, old);
5257 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5259 static void wakeup_handler(void)
5261 struct kvm_vcpu *vcpu;
5262 int cpu = smp_processor_id();
5264 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5265 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5266 blocked_vcpu_list) {
5267 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5269 if (pi_test_on(pi_desc) == 1)
5270 kvm_vcpu_kick(vcpu);
5272 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5275 static void vmx_enable_tdp(void)
5277 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5278 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5279 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5280 0ull, VMX_EPT_EXECUTABLE_MASK,
5281 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5282 VMX_EPT_RWX_MASK, 0ull);
5284 ept_set_mmio_spte_mask();
5289 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5290 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5292 static int handle_pause(struct kvm_vcpu *vcpu)
5294 if (!kvm_pause_in_guest(vcpu->kvm))
5295 grow_ple_window(vcpu);
5298 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5299 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5300 * never set PAUSE_EXITING and just set PLE if supported,
5301 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5303 kvm_vcpu_on_spin(vcpu, true);
5304 return kvm_skip_emulated_instruction(vcpu);
5307 static int handle_nop(struct kvm_vcpu *vcpu)
5309 return kvm_skip_emulated_instruction(vcpu);
5312 static int handle_mwait(struct kvm_vcpu *vcpu)
5314 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5315 return handle_nop(vcpu);
5318 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5320 kvm_queue_exception(vcpu, UD_VECTOR);
5324 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5329 static int handle_monitor(struct kvm_vcpu *vcpu)
5331 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5332 return handle_nop(vcpu);
5335 static int handle_invpcid(struct kvm_vcpu *vcpu)
5337 u32 vmx_instruction_info;
5341 struct x86_exception e;
5343 unsigned long roots_to_free = 0;
5349 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5350 kvm_queue_exception(vcpu, UD_VECTOR);
5354 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5355 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5358 kvm_inject_gp(vcpu, 0);
5362 /* According to the Intel instruction reference, the memory operand
5363 * is read even if it isn't needed (e.g., for type==all)
5365 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5366 vmx_instruction_info, false,
5367 sizeof(operand), &gva))
5370 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5371 kvm_inject_page_fault(vcpu, &e);
5375 if (operand.pcid >> 12 != 0) {
5376 kvm_inject_gp(vcpu, 0);
5380 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5383 case INVPCID_TYPE_INDIV_ADDR:
5384 if ((!pcid_enabled && (operand.pcid != 0)) ||
5385 is_noncanonical_address(operand.gla, vcpu)) {
5386 kvm_inject_gp(vcpu, 0);
5389 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5390 return kvm_skip_emulated_instruction(vcpu);
5392 case INVPCID_TYPE_SINGLE_CTXT:
5393 if (!pcid_enabled && (operand.pcid != 0)) {
5394 kvm_inject_gp(vcpu, 0);
5398 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5399 kvm_mmu_sync_roots(vcpu);
5400 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5403 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5404 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5406 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5408 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5410 * If neither the current cr3 nor any of the prev_roots use the
5411 * given PCID, then nothing needs to be done here because a
5412 * resync will happen anyway before switching to any other CR3.
5415 return kvm_skip_emulated_instruction(vcpu);
5417 case INVPCID_TYPE_ALL_NON_GLOBAL:
5419 * Currently, KVM doesn't mark global entries in the shadow
5420 * page tables, so a non-global flush just degenerates to a
5421 * global flush. If needed, we could optimize this later by
5422 * keeping track of global entries in shadow page tables.
5426 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5427 kvm_mmu_unload(vcpu);
5428 return kvm_skip_emulated_instruction(vcpu);
5431 BUG(); /* We have already checked above that type <= 3 */
5435 static int handle_pml_full(struct kvm_vcpu *vcpu)
5437 unsigned long exit_qualification;
5439 trace_kvm_pml_full(vcpu->vcpu_id);
5441 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5444 * PML buffer FULL happened while executing iret from NMI,
5445 * "blocked by NMI" bit has to be set before next VM entry.
5447 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5449 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5450 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5451 GUEST_INTR_STATE_NMI);
5454 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5455 * here.., and there's no userspace involvement needed for PML.
5460 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5462 struct vcpu_vmx *vmx = to_vmx(vcpu);
5464 if (!vmx->req_immediate_exit &&
5465 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5466 kvm_lapic_expired_hv_timer(vcpu);
5472 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5473 * are overwritten by nested_vmx_setup() when nested=1.
5475 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5477 kvm_queue_exception(vcpu, UD_VECTOR);
5481 static int handle_encls(struct kvm_vcpu *vcpu)
5484 * SGX virtualization is not yet supported. There is no software
5485 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5486 * to prevent the guest from executing ENCLS.
5488 kvm_queue_exception(vcpu, UD_VECTOR);
5493 * The exit handlers return 1 if the exit was handled fully and guest execution
5494 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5495 * to be done to userspace and return 0.
5497 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5498 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5499 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5500 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5501 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5502 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5503 [EXIT_REASON_CR_ACCESS] = handle_cr,
5504 [EXIT_REASON_DR_ACCESS] = handle_dr,
5505 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5506 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5507 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
5508 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5509 [EXIT_REASON_HLT] = kvm_emulate_halt,
5510 [EXIT_REASON_INVD] = handle_invd,
5511 [EXIT_REASON_INVLPG] = handle_invlpg,
5512 [EXIT_REASON_RDPMC] = handle_rdpmc,
5513 [EXIT_REASON_VMCALL] = handle_vmcall,
5514 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5515 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5516 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5517 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5518 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5519 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5520 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5521 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5522 [EXIT_REASON_VMON] = handle_vmx_instruction,
5523 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5524 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5525 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5526 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5527 [EXIT_REASON_WBINVD] = handle_wbinvd,
5528 [EXIT_REASON_XSETBV] = handle_xsetbv,
5529 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5530 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5531 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5532 [EXIT_REASON_LDTR_TR] = handle_desc,
5533 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5534 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5535 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5536 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5537 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5538 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5539 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5540 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5541 [EXIT_REASON_RDRAND] = handle_invalid_op,
5542 [EXIT_REASON_RDSEED] = handle_invalid_op,
5543 [EXIT_REASON_PML_FULL] = handle_pml_full,
5544 [EXIT_REASON_INVPCID] = handle_invpcid,
5545 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5546 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5547 [EXIT_REASON_ENCLS] = handle_encls,
5550 static const int kvm_vmx_max_exit_handlers =
5551 ARRAY_SIZE(kvm_vmx_exit_handlers);
5553 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5555 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5556 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5559 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5562 __free_page(vmx->pml_pg);
5567 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5569 struct vcpu_vmx *vmx = to_vmx(vcpu);
5573 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5575 /* Do nothing if PML buffer is empty */
5576 if (pml_idx == (PML_ENTITY_NUM - 1))
5579 /* PML index always points to next available PML buffer entity */
5580 if (pml_idx >= PML_ENTITY_NUM)
5585 pml_buf = page_address(vmx->pml_pg);
5586 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5589 gpa = pml_buf[pml_idx];
5590 WARN_ON(gpa & (PAGE_SIZE - 1));
5591 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5594 /* reset PML index */
5595 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5599 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5600 * Called before reporting dirty_bitmap to userspace.
5602 static void kvm_flush_pml_buffers(struct kvm *kvm)
5605 struct kvm_vcpu *vcpu;
5607 * We only need to kick vcpu out of guest mode here, as PML buffer
5608 * is flushed at beginning of all VMEXITs, and it's obvious that only
5609 * vcpus running in guest are possible to have unflushed GPAs in PML
5612 kvm_for_each_vcpu(i, vcpu, kvm)
5613 kvm_vcpu_kick(vcpu);
5616 static void vmx_dump_sel(char *name, uint32_t sel)
5618 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5619 name, vmcs_read16(sel),
5620 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5621 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5622 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5625 static void vmx_dump_dtsel(char *name, uint32_t limit)
5627 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5628 name, vmcs_read32(limit),
5629 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5632 void dump_vmcs(void)
5634 u32 vmentry_ctl, vmexit_ctl;
5635 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5640 if (!dump_invalid_vmcs) {
5641 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5645 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5646 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5647 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5648 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5649 cr4 = vmcs_readl(GUEST_CR4);
5650 efer = vmcs_read64(GUEST_IA32_EFER);
5651 secondary_exec_control = 0;
5652 if (cpu_has_secondary_exec_ctrls())
5653 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5655 pr_err("*** Guest State ***\n");
5656 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5657 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5658 vmcs_readl(CR0_GUEST_HOST_MASK));
5659 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5660 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5661 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5662 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5663 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5665 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5666 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5667 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5668 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5670 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5671 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5672 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5673 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5674 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5675 vmcs_readl(GUEST_SYSENTER_ESP),
5676 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5677 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5678 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5679 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5680 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5681 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5682 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5683 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5684 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5685 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5686 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5687 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5688 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5689 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5690 efer, vmcs_read64(GUEST_IA32_PAT));
5691 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5692 vmcs_read64(GUEST_IA32_DEBUGCTL),
5693 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5694 if (cpu_has_load_perf_global_ctrl() &&
5695 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5696 pr_err("PerfGlobCtl = 0x%016llx\n",
5697 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5698 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5699 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5700 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5701 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5702 vmcs_read32(GUEST_ACTIVITY_STATE));
5703 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5704 pr_err("InterruptStatus = %04x\n",
5705 vmcs_read16(GUEST_INTR_STATUS));
5707 pr_err("*** Host State ***\n");
5708 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5709 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5710 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5711 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5712 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5713 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5714 vmcs_read16(HOST_TR_SELECTOR));
5715 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5716 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5717 vmcs_readl(HOST_TR_BASE));
5718 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5719 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5720 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5721 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5722 vmcs_readl(HOST_CR4));
5723 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5724 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5725 vmcs_read32(HOST_IA32_SYSENTER_CS),
5726 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5727 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5728 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5729 vmcs_read64(HOST_IA32_EFER),
5730 vmcs_read64(HOST_IA32_PAT));
5731 if (cpu_has_load_perf_global_ctrl() &&
5732 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5733 pr_err("PerfGlobCtl = 0x%016llx\n",
5734 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5736 pr_err("*** Control State ***\n");
5737 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5738 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5739 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5740 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5741 vmcs_read32(EXCEPTION_BITMAP),
5742 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5743 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5744 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5745 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5746 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5747 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5748 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5749 vmcs_read32(VM_EXIT_INTR_INFO),
5750 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5751 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5752 pr_err(" reason=%08x qualification=%016lx\n",
5753 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5754 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5755 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5756 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5757 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5758 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5759 pr_err("TSC Multiplier = 0x%016llx\n",
5760 vmcs_read64(TSC_MULTIPLIER));
5761 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5762 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5763 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5764 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5766 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5767 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5768 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5769 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5771 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5772 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5773 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5774 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5775 n = vmcs_read32(CR3_TARGET_COUNT);
5776 for (i = 0; i + 1 < n; i += 4)
5777 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5778 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5779 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5781 pr_err("CR3 target%u=%016lx\n",
5782 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5783 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5784 pr_err("PLE Gap=%08x Window=%08x\n",
5785 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5786 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5787 pr_err("Virtual processor ID = 0x%04x\n",
5788 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5792 * The guest has exited. See if we can fix it or if we need userspace
5795 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5797 struct vcpu_vmx *vmx = to_vmx(vcpu);
5798 u32 exit_reason = vmx->exit_reason;
5799 u32 vectoring_info = vmx->idt_vectoring_info;
5801 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5804 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5805 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5806 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5807 * mode as if vcpus is in root mode, the PML buffer must has been
5811 vmx_flush_pml_buffer(vcpu);
5813 /* If guest state is invalid, start emulating */
5814 if (vmx->emulation_required)
5815 return handle_invalid_guest_state(vcpu);
5817 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5818 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5820 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5822 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5823 vcpu->run->fail_entry.hardware_entry_failure_reason
5828 if (unlikely(vmx->fail)) {
5830 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5831 vcpu->run->fail_entry.hardware_entry_failure_reason
5832 = vmcs_read32(VM_INSTRUCTION_ERROR);
5838 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5839 * delivery event since it indicates guest is accessing MMIO.
5840 * The vm-exit can be triggered again after return to guest that
5841 * will cause infinite loop.
5843 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5844 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5845 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5846 exit_reason != EXIT_REASON_PML_FULL &&
5847 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5848 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5849 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5850 vcpu->run->internal.ndata = 3;
5851 vcpu->run->internal.data[0] = vectoring_info;
5852 vcpu->run->internal.data[1] = exit_reason;
5853 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5854 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5855 vcpu->run->internal.ndata++;
5856 vcpu->run->internal.data[3] =
5857 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5862 if (unlikely(!enable_vnmi &&
5863 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5864 if (vmx_interrupt_allowed(vcpu)) {
5865 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5866 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5867 vcpu->arch.nmi_pending) {
5869 * This CPU don't support us in finding the end of an
5870 * NMI-blocked window if the guest runs with IRQs
5871 * disabled. So we pull the trigger after 1 s of
5872 * futile waiting, but inform the user about this.
5874 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5875 "state on VCPU %d after 1 s timeout\n",
5876 __func__, vcpu->vcpu_id);
5877 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5881 if (exit_reason < kvm_vmx_max_exit_handlers
5882 && kvm_vmx_exit_handlers[exit_reason]) {
5883 #ifdef CONFIG_RETPOLINE
5884 if (exit_reason == EXIT_REASON_MSR_WRITE)
5885 return kvm_emulate_wrmsr(vcpu);
5886 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5887 return handle_preemption_timer(vcpu);
5888 else if (exit_reason == EXIT_REASON_PENDING_INTERRUPT)
5889 return handle_interrupt_window(vcpu);
5890 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5891 return handle_external_interrupt(vcpu);
5892 else if (exit_reason == EXIT_REASON_HLT)
5893 return kvm_emulate_halt(vcpu);
5894 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5895 return handle_ept_misconfig(vcpu);
5897 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5899 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5902 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5903 vcpu->run->internal.suberror =
5904 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5905 vcpu->run->internal.ndata = 1;
5906 vcpu->run->internal.data[0] = exit_reason;
5912 * Software based L1D cache flush which is used when microcode providing
5913 * the cache control MSR is not loaded.
5915 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5916 * flush it is required to read in 64 KiB because the replacement algorithm
5917 * is not exactly LRU. This could be sized at runtime via topology
5918 * information but as all relevant affected CPUs have 32KiB L1D cache size
5919 * there is no point in doing so.
5921 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5923 int size = PAGE_SIZE << L1D_CACHE_ORDER;
5926 * This code is only executed when the the flush mode is 'cond' or
5929 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5933 * Clear the per-vcpu flush bit, it gets set again
5934 * either from vcpu_run() or from one of the unsafe
5937 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5938 vcpu->arch.l1tf_flush_l1d = false;
5941 * Clear the per-cpu flush bit, it gets set again from
5942 * the interrupt handlers.
5944 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5945 kvm_clear_cpu_l1tf_flush_l1d();
5951 vcpu->stat.l1d_flush++;
5953 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5954 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5959 /* First ensure the pages are in the TLB */
5960 "xorl %%eax, %%eax\n"
5961 ".Lpopulate_tlb:\n\t"
5962 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5963 "addl $4096, %%eax\n\t"
5964 "cmpl %%eax, %[size]\n\t"
5965 "jne .Lpopulate_tlb\n\t"
5966 "xorl %%eax, %%eax\n\t"
5968 /* Now fill the cache */
5969 "xorl %%eax, %%eax\n"
5971 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5972 "addl $64, %%eax\n\t"
5973 "cmpl %%eax, %[size]\n\t"
5974 "jne .Lfill_cache\n\t"
5976 :: [flush_pages] "r" (vmx_l1d_flush_pages),
5978 : "eax", "ebx", "ecx", "edx");
5981 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5983 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5986 if (is_guest_mode(vcpu) &&
5987 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
5990 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
5991 if (is_guest_mode(vcpu))
5992 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
5994 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
5997 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5999 struct vcpu_vmx *vmx = to_vmx(vcpu);
6000 u32 sec_exec_control;
6002 if (!lapic_in_kernel(vcpu))
6005 if (!flexpriority_enabled &&
6006 !cpu_has_vmx_virtualize_x2apic_mode())
6009 /* Postpone execution until vmcs01 is the current VMCS. */
6010 if (is_guest_mode(vcpu)) {
6011 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6015 sec_exec_control = secondary_exec_controls_get(vmx);
6016 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6017 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6019 switch (kvm_get_apic_mode(vcpu)) {
6020 case LAPIC_MODE_INVALID:
6021 WARN_ONCE(true, "Invalid local APIC state");
6022 case LAPIC_MODE_DISABLED:
6024 case LAPIC_MODE_XAPIC:
6025 if (flexpriority_enabled) {
6027 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6028 vmx_flush_tlb(vcpu, true);
6031 case LAPIC_MODE_X2APIC:
6032 if (cpu_has_vmx_virtualize_x2apic_mode())
6034 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6037 secondary_exec_controls_set(vmx, sec_exec_control);
6039 vmx_update_msr_bitmap(vcpu);
6042 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6044 if (!is_guest_mode(vcpu)) {
6045 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6046 vmx_flush_tlb(vcpu, true);
6050 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6058 status = vmcs_read16(GUEST_INTR_STATUS);
6060 if (max_isr != old) {
6062 status |= max_isr << 8;
6063 vmcs_write16(GUEST_INTR_STATUS, status);
6067 static void vmx_set_rvi(int vector)
6075 status = vmcs_read16(GUEST_INTR_STATUS);
6076 old = (u8)status & 0xff;
6077 if ((u8)vector != old) {
6079 status |= (u8)vector;
6080 vmcs_write16(GUEST_INTR_STATUS, status);
6084 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6087 * When running L2, updating RVI is only relevant when
6088 * vmcs12 virtual-interrupt-delivery enabled.
6089 * However, it can be enabled only when L1 also
6090 * intercepts external-interrupts and in that case
6091 * we should not update vmcs02 RVI but instead intercept
6092 * interrupt. Therefore, do nothing when running L2.
6094 if (!is_guest_mode(vcpu))
6095 vmx_set_rvi(max_irr);
6098 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6100 struct vcpu_vmx *vmx = to_vmx(vcpu);
6102 bool max_irr_updated;
6104 WARN_ON(!vcpu->arch.apicv_active);
6105 if (pi_test_on(&vmx->pi_desc)) {
6106 pi_clear_on(&vmx->pi_desc);
6108 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
6109 * But on x86 this is just a compiler barrier anyway.
6111 smp_mb__after_atomic();
6113 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6116 * If we are running L2 and L1 has a new pending interrupt
6117 * which can be injected, we should re-evaluate
6118 * what should be done with this new L1 interrupt.
6119 * If L1 intercepts external-interrupts, we should
6120 * exit from L2 to L1. Otherwise, interrupt should be
6121 * delivered directly to L2.
6123 if (is_guest_mode(vcpu) && max_irr_updated) {
6124 if (nested_exit_on_intr(vcpu))
6125 kvm_vcpu_exiting_guest_mode(vcpu);
6127 kvm_make_request(KVM_REQ_EVENT, vcpu);
6130 max_irr = kvm_lapic_find_highest_irr(vcpu);
6132 vmx_hwapic_irr_update(vcpu, max_irr);
6136 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6138 return pi_test_on(vcpu_to_pi_desc(vcpu));
6141 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6143 if (!kvm_vcpu_apicv_active(vcpu))
6146 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6147 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6148 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6149 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6152 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6154 struct vcpu_vmx *vmx = to_vmx(vcpu);
6156 pi_clear_on(&vmx->pi_desc);
6157 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6160 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6162 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6164 /* if exit due to PF check for async PF */
6165 if (is_page_fault(vmx->exit_intr_info))
6166 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6168 /* Handle machine checks before interrupts are enabled */
6169 if (is_machine_check(vmx->exit_intr_info))
6170 kvm_machine_check();
6172 /* We need to handle NMIs before interrupts are enabled */
6173 if (is_nmi(vmx->exit_intr_info)) {
6174 kvm_before_interrupt(&vmx->vcpu);
6176 kvm_after_interrupt(&vmx->vcpu);
6180 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6182 unsigned int vector;
6183 unsigned long entry;
6184 #ifdef CONFIG_X86_64
6190 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6191 if (WARN_ONCE(!is_external_intr(intr_info),
6192 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6195 vector = intr_info & INTR_INFO_VECTOR_MASK;
6196 desc = (gate_desc *)host_idt_base + vector;
6197 entry = gate_offset(desc);
6199 kvm_before_interrupt(vcpu);
6202 #ifdef CONFIG_X86_64
6203 "mov %%" _ASM_SP ", %[sp]\n\t"
6204 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6209 __ASM_SIZE(push) " $%c[cs]\n\t"
6212 #ifdef CONFIG_X86_64
6217 THUNK_TARGET(entry),
6218 [ss]"i"(__KERNEL_DS),
6219 [cs]"i"(__KERNEL_CS)
6222 kvm_after_interrupt(vcpu);
6224 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6226 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6228 struct vcpu_vmx *vmx = to_vmx(vcpu);
6230 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6231 handle_external_interrupt_irqoff(vcpu);
6232 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6233 handle_exception_nmi_irqoff(vmx);
6236 static bool vmx_has_emulated_msr(int index)
6239 case MSR_IA32_SMBASE:
6241 * We cannot do SMM unless we can run the guest in big
6244 return enable_unrestricted_guest || emulate_invalid_guest_state;
6245 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6247 case MSR_AMD64_VIRT_SPEC_CTRL:
6248 /* This is AMD only. */
6255 static bool vmx_pt_supported(void)
6257 return pt_mode == PT_MODE_HOST_GUEST;
6260 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6265 bool idtv_info_valid;
6267 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6270 if (vmx->loaded_vmcs->nmi_known_unmasked)
6273 * Can't use vmx->exit_intr_info since we're not sure what
6274 * the exit reason is.
6276 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6277 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6278 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6280 * SDM 3: 27.7.1.2 (September 2008)
6281 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6282 * a guest IRET fault.
6283 * SDM 3: 23.2.2 (September 2008)
6284 * Bit 12 is undefined in any of the following cases:
6285 * If the VM exit sets the valid bit in the IDT-vectoring
6286 * information field.
6287 * If the VM exit is due to a double fault.
6289 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6290 vector != DF_VECTOR && !idtv_info_valid)
6291 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6292 GUEST_INTR_STATE_NMI);
6294 vmx->loaded_vmcs->nmi_known_unmasked =
6295 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6296 & GUEST_INTR_STATE_NMI);
6297 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6298 vmx->loaded_vmcs->vnmi_blocked_time +=
6299 ktime_to_ns(ktime_sub(ktime_get(),
6300 vmx->loaded_vmcs->entry_time));
6303 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6304 u32 idt_vectoring_info,
6305 int instr_len_field,
6306 int error_code_field)
6310 bool idtv_info_valid;
6312 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6314 vcpu->arch.nmi_injected = false;
6315 kvm_clear_exception_queue(vcpu);
6316 kvm_clear_interrupt_queue(vcpu);
6318 if (!idtv_info_valid)
6321 kvm_make_request(KVM_REQ_EVENT, vcpu);
6323 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6324 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6327 case INTR_TYPE_NMI_INTR:
6328 vcpu->arch.nmi_injected = true;
6330 * SDM 3: 27.7.1.2 (September 2008)
6331 * Clear bit "block by NMI" before VM entry if a NMI
6334 vmx_set_nmi_mask(vcpu, false);
6336 case INTR_TYPE_SOFT_EXCEPTION:
6337 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6339 case INTR_TYPE_HARD_EXCEPTION:
6340 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6341 u32 err = vmcs_read32(error_code_field);
6342 kvm_requeue_exception_e(vcpu, vector, err);
6344 kvm_requeue_exception(vcpu, vector);
6346 case INTR_TYPE_SOFT_INTR:
6347 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6349 case INTR_TYPE_EXT_INTR:
6350 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6357 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6359 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6360 VM_EXIT_INSTRUCTION_LEN,
6361 IDT_VECTORING_ERROR_CODE);
6364 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6366 __vmx_complete_interrupts(vcpu,
6367 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6368 VM_ENTRY_INSTRUCTION_LEN,
6369 VM_ENTRY_EXCEPTION_ERROR_CODE);
6371 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6374 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6377 struct perf_guest_switch_msr *msrs;
6379 msrs = perf_guest_get_msrs(&nr_msrs);
6384 for (i = 0; i < nr_msrs; i++)
6385 if (msrs[i].host == msrs[i].guest)
6386 clear_atomic_switch_msr(vmx, msrs[i].msr);
6388 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6389 msrs[i].host, false);
6392 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6394 u32 host_umwait_control;
6396 if (!vmx_has_waitpkg(vmx))
6399 host_umwait_control = get_umwait_control_msr();
6401 if (vmx->msr_ia32_umwait_control != host_umwait_control)
6402 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6403 vmx->msr_ia32_umwait_control,
6404 host_umwait_control, false);
6406 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6409 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6411 struct vcpu_vmx *vmx = to_vmx(vcpu);
6415 if (vmx->req_immediate_exit) {
6416 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6417 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6418 } else if (vmx->hv_deadline_tsc != -1) {
6420 if (vmx->hv_deadline_tsc > tscl)
6421 /* set_hv_timer ensures the delta fits in 32-bits */
6422 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6423 cpu_preemption_timer_multi);
6427 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6428 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6429 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6430 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6431 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6435 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6437 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6438 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6439 vmcs_writel(HOST_RSP, host_rsp);
6443 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6445 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6447 struct vcpu_vmx *vmx = to_vmx(vcpu);
6448 unsigned long cr3, cr4;
6450 /* Record the guest's net vcpu time for enforced NMI injections. */
6451 if (unlikely(!enable_vnmi &&
6452 vmx->loaded_vmcs->soft_vnmi_blocked))
6453 vmx->loaded_vmcs->entry_time = ktime_get();
6455 /* Don't enter VMX if guest state is invalid, let the exit handler
6456 start emulation until we arrive back to a valid state */
6457 if (vmx->emulation_required)
6460 if (vmx->ple_window_dirty) {
6461 vmx->ple_window_dirty = false;
6462 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6465 if (vmx->nested.need_vmcs12_to_shadow_sync)
6466 nested_sync_vmcs12_to_shadow(vcpu);
6468 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6469 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6470 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6471 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6473 cr3 = __get_current_cr3_fast();
6474 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6475 vmcs_writel(HOST_CR3, cr3);
6476 vmx->loaded_vmcs->host_state.cr3 = cr3;
6479 cr4 = cr4_read_shadow();
6480 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6481 vmcs_writel(HOST_CR4, cr4);
6482 vmx->loaded_vmcs->host_state.cr4 = cr4;
6485 /* When single-stepping over STI and MOV SS, we must clear the
6486 * corresponding interruptibility bits in the guest state. Otherwise
6487 * vmentry fails as it then expects bit 14 (BS) in pending debug
6488 * exceptions being set, but that's not correct for the guest debugging
6490 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6491 vmx_set_interrupt_shadow(vcpu, 0);
6493 kvm_load_guest_xsave_state(vcpu);
6495 if (static_cpu_has(X86_FEATURE_PKU) &&
6496 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6497 vcpu->arch.pkru != vmx->host_pkru)
6498 __write_pkru(vcpu->arch.pkru);
6500 pt_guest_enter(vmx);
6502 atomic_switch_perf_msrs(vmx);
6503 atomic_switch_umwait_control_msr(vmx);
6505 if (enable_preemption_timer)
6506 vmx_update_hv_timer(vcpu);
6508 if (lapic_in_kernel(vcpu) &&
6509 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6510 kvm_wait_lapic_expire(vcpu);
6513 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6514 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6515 * is no need to worry about the conditional branch over the wrmsr
6516 * being speculatively taken.
6518 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6520 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6521 if (static_branch_unlikely(&vmx_l1d_should_flush))
6522 vmx_l1d_flush(vcpu);
6523 else if (static_branch_unlikely(&mds_user_clear))
6524 mds_clear_cpu_buffers();
6526 if (vcpu->arch.cr2 != read_cr2())
6527 write_cr2(vcpu->arch.cr2);
6529 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6530 vmx->loaded_vmcs->launched);
6532 vcpu->arch.cr2 = read_cr2();
6535 * We do not use IBRS in the kernel. If this vCPU has used the
6536 * SPEC_CTRL MSR it may have left it on; save the value and
6537 * turn it off. This is much more efficient than blindly adding
6538 * it to the atomic save/restore list. Especially as the former
6539 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6541 * For non-nested case:
6542 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6546 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6549 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6550 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6552 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6554 /* All fields are clean at this point */
6555 if (static_branch_unlikely(&enable_evmcs))
6556 current_evmcs->hv_clean_fields |=
6557 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6559 if (static_branch_unlikely(&enable_evmcs))
6560 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6562 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6563 if (vmx->host_debugctlmsr)
6564 update_debugctlmsr(vmx->host_debugctlmsr);
6566 #ifndef CONFIG_X86_64
6568 * The sysexit path does not restore ds/es, so we must set them to
6569 * a reasonable value ourselves.
6571 * We can't defer this to vmx_prepare_switch_to_host() since that
6572 * function may be executed in interrupt context, which saves and
6573 * restore segments around it, nullifying its effect.
6575 loadsegment(ds, __USER_DS);
6576 loadsegment(es, __USER_DS);
6579 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6580 | (1 << VCPU_EXREG_RFLAGS)
6581 | (1 << VCPU_EXREG_PDPTR)
6582 | (1 << VCPU_EXREG_SEGMENTS)
6583 | (1 << VCPU_EXREG_CR3));
6584 vcpu->arch.regs_dirty = 0;
6589 * eager fpu is enabled if PKEY is supported and CR4 is switched
6590 * back on host, so it is safe to read guest PKRU from current
6593 if (static_cpu_has(X86_FEATURE_PKU) &&
6594 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6595 vcpu->arch.pkru = rdpkru();
6596 if (vcpu->arch.pkru != vmx->host_pkru)
6597 __write_pkru(vmx->host_pkru);
6600 kvm_load_host_xsave_state(vcpu);
6602 vmx->nested.nested_run_pending = 0;
6603 vmx->idt_vectoring_info = 0;
6605 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6606 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6607 kvm_machine_check();
6609 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6612 vmx->loaded_vmcs->launched = 1;
6613 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6615 vmx_recover_nmi_blocking(vmx);
6616 vmx_complete_interrupts(vmx);
6619 static struct kvm *vmx_vm_alloc(void)
6621 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6622 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6624 return &kvm_vmx->kvm;
6627 static void vmx_vm_free(struct kvm *kvm)
6629 kfree(kvm->arch.hyperv.hv_pa_pg);
6630 vfree(to_kvm_vmx(kvm));
6633 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6635 struct vcpu_vmx *vmx = to_vmx(vcpu);
6638 vmx_destroy_pml_buffer(vmx);
6639 free_vpid(vmx->vpid);
6640 nested_vmx_free_vcpu(vcpu);
6641 free_loaded_vmcs(vmx->loaded_vmcs);
6642 kfree(vmx->guest_msrs);
6643 kvm_vcpu_uninit(vcpu);
6644 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6645 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6646 kmem_cache_free(kvm_vcpu_cache, vmx);
6649 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6652 struct vcpu_vmx *vmx;
6653 unsigned long *msr_bitmap;
6656 BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
6657 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
6659 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
6661 return ERR_PTR(-ENOMEM);
6663 vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6664 GFP_KERNEL_ACCOUNT);
6665 if (!vmx->vcpu.arch.user_fpu) {
6666 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6668 goto free_partial_vcpu;
6671 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6672 GFP_KERNEL_ACCOUNT);
6673 if (!vmx->vcpu.arch.guest_fpu) {
6674 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6679 vmx->vpid = allocate_vpid();
6681 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6688 * If PML is turned on, failure on enabling PML just results in failure
6689 * of creating the vcpu, therefore we can simplify PML logic (by
6690 * avoiding dealing with cases, such as enabling PML partially on vcpus
6691 * for the guest, etc.
6694 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6699 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
6700 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6703 if (!vmx->guest_msrs)
6706 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6707 u32 index = vmx_msr_index[i];
6708 u32 data_low, data_high;
6711 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6713 if (wrmsr_safe(index, data_low, data_high) < 0)
6715 vmx->guest_msrs[j].index = i;
6716 vmx->guest_msrs[j].data = 0;
6717 vmx->guest_msrs[j].mask = -1ull;
6721 err = alloc_loaded_vmcs(&vmx->vmcs01);
6725 msr_bitmap = vmx->vmcs01.msr_bitmap;
6726 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6727 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6728 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6729 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6730 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6731 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6732 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6733 if (kvm_cstate_in_guest(kvm)) {
6734 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6735 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6736 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6737 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6739 vmx->msr_bitmap_mode = 0;
6741 vmx->loaded_vmcs = &vmx->vmcs01;
6743 vmx_vcpu_load(&vmx->vcpu, cpu);
6744 vmx->vcpu.cpu = cpu;
6746 vmx_vcpu_put(&vmx->vcpu);
6748 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6749 err = alloc_apic_access_page(kvm);
6754 if (enable_ept && !enable_unrestricted_guest) {
6755 err = init_rmode_identity_map(kvm);
6761 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6763 kvm_vcpu_apicv_active(&vmx->vcpu));
6765 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6767 vmx->nested.posted_intr_nv = -1;
6768 vmx->nested.current_vmptr = -1ull;
6770 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
6773 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6774 * or POSTED_INTR_WAKEUP_VECTOR.
6776 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6777 vmx->pi_desc.sn = 1;
6779 vmx->ept_pointer = INVALID_PAGE;
6784 free_loaded_vmcs(vmx->loaded_vmcs);
6786 kfree(vmx->guest_msrs);
6788 vmx_destroy_pml_buffer(vmx);
6790 kvm_vcpu_uninit(&vmx->vcpu);
6792 free_vpid(vmx->vpid);
6793 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6795 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6797 kmem_cache_free(kvm_vcpu_cache, vmx);
6798 return ERR_PTR(err);
6801 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6802 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6804 static int vmx_vm_init(struct kvm *kvm)
6806 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6809 kvm->arch.pause_in_guest = true;
6811 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6812 switch (l1tf_mitigation) {
6813 case L1TF_MITIGATION_OFF:
6814 case L1TF_MITIGATION_FLUSH_NOWARN:
6815 /* 'I explicitly don't care' is set */
6817 case L1TF_MITIGATION_FLUSH:
6818 case L1TF_MITIGATION_FLUSH_NOSMT:
6819 case L1TF_MITIGATION_FULL:
6821 * Warn upon starting the first VM in a potentially
6822 * insecure environment.
6824 if (sched_smt_active())
6825 pr_warn_once(L1TF_MSG_SMT);
6826 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6827 pr_warn_once(L1TF_MSG_L1D);
6829 case L1TF_MITIGATION_FULL_FORCE:
6830 /* Flush is enforced */
6837 static int __init vmx_check_processor_compat(void)
6839 struct vmcs_config vmcs_conf;
6840 struct vmx_capability vmx_cap;
6842 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6845 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6847 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6848 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6849 smp_processor_id());
6855 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6860 /* For VT-d and EPT combination
6861 * 1. MMIO: always map as UC
6863 * a. VT-d without snooping control feature: can't guarantee the
6864 * result, try to trust guest.
6865 * b. VT-d with snooping control feature: snooping control feature of
6866 * VT-d engine can guarantee the cache correctness. Just set it
6867 * to WB to keep consistent with host. So the same as item 3.
6868 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6869 * consistent with host MTRR
6872 cache = MTRR_TYPE_UNCACHABLE;
6876 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6877 ipat = VMX_EPT_IPAT_BIT;
6878 cache = MTRR_TYPE_WRBACK;
6882 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6883 ipat = VMX_EPT_IPAT_BIT;
6884 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6885 cache = MTRR_TYPE_WRBACK;
6887 cache = MTRR_TYPE_UNCACHABLE;
6891 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6894 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6897 static int vmx_get_lpage_level(void)
6899 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6900 return PT_DIRECTORY_LEVEL;
6902 /* For shadow and EPT supported 1GB page */
6903 return PT_PDPE_LEVEL;
6906 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6909 * These bits in the secondary execution controls field
6910 * are dynamic, the others are mostly based on the hypervisor
6911 * architecture and the guest's CPUID. Do not touch the
6915 SECONDARY_EXEC_SHADOW_VMCS |
6916 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6917 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6918 SECONDARY_EXEC_DESC;
6920 u32 new_ctl = vmx->secondary_exec_control;
6921 u32 cur_ctl = secondary_exec_controls_get(vmx);
6923 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6927 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6928 * (indicating "allowed-1") if they are supported in the guest's CPUID.
6930 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6932 struct vcpu_vmx *vmx = to_vmx(vcpu);
6933 struct kvm_cpuid_entry2 *entry;
6935 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6936 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6938 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6939 if (entry && (entry->_reg & (_cpuid_mask))) \
6940 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6943 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6944 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6945 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6946 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6947 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6948 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6949 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6950 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6951 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6952 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6953 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6954 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6955 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6956 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6957 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
6959 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6960 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6961 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
6962 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
6963 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
6964 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
6966 #undef cr4_fixed1_update
6969 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6971 struct vcpu_vmx *vmx = to_vmx(vcpu);
6973 if (kvm_mpx_supported()) {
6974 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
6977 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6978 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6980 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6981 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6986 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6988 struct vcpu_vmx *vmx = to_vmx(vcpu);
6989 struct kvm_cpuid_entry2 *best = NULL;
6992 for (i = 0; i < PT_CPUID_LEAVES; i++) {
6993 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
6996 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
6997 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
6998 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
6999 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7002 /* Get the number of configurable Address Ranges for filtering */
7003 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7004 PT_CAP_num_address_ranges);
7006 /* Initialize and clear the no dependency bits */
7007 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7008 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7011 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7012 * will inject an #GP
7014 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7015 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7018 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7019 * PSBFreq can be set
7021 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7022 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7023 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7026 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7027 * MTCFreq can be set
7029 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7030 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7031 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7033 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7034 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7035 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7038 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7039 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7040 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7042 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7043 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7044 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7046 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7047 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7048 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7050 /* unmask address range configure area */
7051 for (i = 0; i < vmx->pt_desc.addr_range; i++)
7052 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7055 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7057 struct vcpu_vmx *vmx = to_vmx(vcpu);
7059 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7060 vcpu->arch.xsaves_enabled = false;
7062 if (cpu_has_secondary_exec_ctrls()) {
7063 vmx_compute_secondary_exec_control(vmx);
7064 vmcs_set_secondary_exec_control(vmx);
7067 if (nested_vmx_allowed(vcpu))
7068 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7069 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7071 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7072 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7074 if (nested_vmx_allowed(vcpu)) {
7075 nested_vmx_cr_fixed1_bits_update(vcpu);
7076 nested_vmx_entry_exit_ctls_update(vcpu);
7079 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7080 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7081 update_intel_pt_cfg(vcpu);
7084 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7086 if (func == 1 && nested)
7087 entry->ecx |= bit(X86_FEATURE_VMX);
7090 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7092 to_vmx(vcpu)->req_immediate_exit = true;
7095 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7096 struct x86_instruction_info *info,
7097 enum x86_intercept_stage stage)
7099 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7100 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7103 * RDPID causes #UD if disabled through secondary execution controls.
7104 * Because it is marked as EmulateOnUD, we need to intercept it here.
7106 if (info->intercept == x86_intercept_rdtscp &&
7107 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7108 ctxt->exception.vector = UD_VECTOR;
7109 ctxt->exception.error_code_valid = false;
7110 return X86EMUL_PROPAGATE_FAULT;
7113 /* TODO: check more intercepts... */
7114 return X86EMUL_CONTINUE;
7117 #ifdef CONFIG_X86_64
7118 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7119 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7120 u64 divisor, u64 *result)
7122 u64 low = a << shift, high = a >> (64 - shift);
7124 /* To avoid the overflow on divq */
7125 if (high >= divisor)
7128 /* Low hold the result, high hold rem which is discarded */
7129 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7130 "rm" (divisor), "0" (low), "1" (high));
7136 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7139 struct vcpu_vmx *vmx;
7140 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7141 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7143 if (kvm_mwait_in_guest(vcpu->kvm) ||
7144 kvm_can_post_timer_interrupt(vcpu))
7149 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7150 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7151 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7152 ktimer->timer_advance_ns);
7154 if (delta_tsc > lapic_timer_advance_cycles)
7155 delta_tsc -= lapic_timer_advance_cycles;
7159 /* Convert to host delta tsc if tsc scaling is enabled */
7160 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7161 delta_tsc && u64_shl_div_u64(delta_tsc,
7162 kvm_tsc_scaling_ratio_frac_bits,
7163 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7167 * If the delta tsc can't fit in the 32 bit after the multi shift,
7168 * we can't use the preemption timer.
7169 * It's possible that it fits on later vmentries, but checking
7170 * on every vmentry is costly so we just use an hrtimer.
7172 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7175 vmx->hv_deadline_tsc = tscl + delta_tsc;
7176 *expired = !delta_tsc;
7180 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7182 to_vmx(vcpu)->hv_deadline_tsc = -1;
7186 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7188 if (!kvm_pause_in_guest(vcpu->kvm))
7189 shrink_ple_window(vcpu);
7192 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7193 struct kvm_memory_slot *slot)
7195 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7196 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7199 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7200 struct kvm_memory_slot *slot)
7202 kvm_mmu_slot_set_dirty(kvm, slot);
7205 static void vmx_flush_log_dirty(struct kvm *kvm)
7207 kvm_flush_pml_buffers(kvm);
7210 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7212 struct vmcs12 *vmcs12;
7213 struct vcpu_vmx *vmx = to_vmx(vcpu);
7216 if (is_guest_mode(vcpu)) {
7217 WARN_ON_ONCE(vmx->nested.pml_full);
7220 * Check if PML is enabled for the nested guest.
7221 * Whether eptp bit 6 is set is already checked
7222 * as part of A/D emulation.
7224 vmcs12 = get_vmcs12(vcpu);
7225 if (!nested_cpu_has_pml(vmcs12))
7228 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7229 vmx->nested.pml_full = true;
7233 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7234 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7236 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7237 offset_in_page(dst), sizeof(gpa)))
7240 vmcs12->guest_pml_index--;
7246 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7247 struct kvm_memory_slot *memslot,
7248 gfn_t offset, unsigned long mask)
7250 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7253 static void __pi_post_block(struct kvm_vcpu *vcpu)
7255 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7256 struct pi_desc old, new;
7260 old.control = new.control = pi_desc->control;
7261 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7262 "Wakeup handler not enabled while the VCPU is blocked\n");
7264 dest = cpu_physical_id(vcpu->cpu);
7266 if (x2apic_enabled())
7269 new.ndst = (dest << 8) & 0xFF00;
7271 /* set 'NV' to 'notification vector' */
7272 new.nv = POSTED_INTR_VECTOR;
7273 } while (cmpxchg64(&pi_desc->control, old.control,
7274 new.control) != old.control);
7276 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7277 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7278 list_del(&vcpu->blocked_vcpu_list);
7279 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7280 vcpu->pre_pcpu = -1;
7285 * This routine does the following things for vCPU which is going
7286 * to be blocked if VT-d PI is enabled.
7287 * - Store the vCPU to the wakeup list, so when interrupts happen
7288 * we can find the right vCPU to wake up.
7289 * - Change the Posted-interrupt descriptor as below:
7290 * 'NDST' <-- vcpu->pre_pcpu
7291 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7292 * - If 'ON' is set during this process, which means at least one
7293 * interrupt is posted for this vCPU, we cannot block it, in
7294 * this case, return 1, otherwise, return 0.
7297 static int pi_pre_block(struct kvm_vcpu *vcpu)
7300 struct pi_desc old, new;
7301 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7303 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7304 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7305 !kvm_vcpu_apicv_active(vcpu))
7308 WARN_ON(irqs_disabled());
7309 local_irq_disable();
7310 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7311 vcpu->pre_pcpu = vcpu->cpu;
7312 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7313 list_add_tail(&vcpu->blocked_vcpu_list,
7314 &per_cpu(blocked_vcpu_on_cpu,
7316 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7320 old.control = new.control = pi_desc->control;
7322 WARN((pi_desc->sn == 1),
7323 "Warning: SN field of posted-interrupts "
7324 "is set before blocking\n");
7327 * Since vCPU can be preempted during this process,
7328 * vcpu->cpu could be different with pre_pcpu, we
7329 * need to set pre_pcpu as the destination of wakeup
7330 * notification event, then we can find the right vCPU
7331 * to wakeup in wakeup handler if interrupts happen
7332 * when the vCPU is in blocked state.
7334 dest = cpu_physical_id(vcpu->pre_pcpu);
7336 if (x2apic_enabled())
7339 new.ndst = (dest << 8) & 0xFF00;
7341 /* set 'NV' to 'wakeup vector' */
7342 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7343 } while (cmpxchg64(&pi_desc->control, old.control,
7344 new.control) != old.control);
7346 /* We should not block the vCPU if an interrupt is posted for it. */
7347 if (pi_test_on(pi_desc) == 1)
7348 __pi_post_block(vcpu);
7351 return (vcpu->pre_pcpu == -1);
7354 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7356 if (pi_pre_block(vcpu))
7359 if (kvm_lapic_hv_timer_in_use(vcpu))
7360 kvm_lapic_switch_to_sw_timer(vcpu);
7365 static void pi_post_block(struct kvm_vcpu *vcpu)
7367 if (vcpu->pre_pcpu == -1)
7370 WARN_ON(irqs_disabled());
7371 local_irq_disable();
7372 __pi_post_block(vcpu);
7376 static void vmx_post_block(struct kvm_vcpu *vcpu)
7378 if (kvm_x86_ops->set_hv_timer)
7379 kvm_lapic_switch_to_hv_timer(vcpu);
7381 pi_post_block(vcpu);
7385 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7388 * @host_irq: host irq of the interrupt
7389 * @guest_irq: gsi of the interrupt
7390 * @set: set or unset PI
7391 * returns 0 on success, < 0 on failure
7393 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7394 uint32_t guest_irq, bool set)
7396 struct kvm_kernel_irq_routing_entry *e;
7397 struct kvm_irq_routing_table *irq_rt;
7398 struct kvm_lapic_irq irq;
7399 struct kvm_vcpu *vcpu;
7400 struct vcpu_data vcpu_info;
7403 if (!kvm_arch_has_assigned_device(kvm) ||
7404 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7405 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7408 idx = srcu_read_lock(&kvm->irq_srcu);
7409 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7410 if (guest_irq >= irq_rt->nr_rt_entries ||
7411 hlist_empty(&irq_rt->map[guest_irq])) {
7412 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7413 guest_irq, irq_rt->nr_rt_entries);
7417 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7418 if (e->type != KVM_IRQ_ROUTING_MSI)
7421 * VT-d PI cannot support posting multicast/broadcast
7422 * interrupts to a vCPU, we still use interrupt remapping
7423 * for these kind of interrupts.
7425 * For lowest-priority interrupts, we only support
7426 * those with single CPU as the destination, e.g. user
7427 * configures the interrupts via /proc/irq or uses
7428 * irqbalance to make the interrupts single-CPU.
7430 * We will support full lowest-priority interrupt later.
7432 * In addition, we can only inject generic interrupts using
7433 * the PI mechanism, refuse to route others through it.
7436 kvm_set_msi_irq(kvm, e, &irq);
7437 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7438 !kvm_irq_is_postable(&irq)) {
7440 * Make sure the IRTE is in remapped mode if
7441 * we don't handle it in posted mode.
7443 ret = irq_set_vcpu_affinity(host_irq, NULL);
7446 "failed to back to remapped mode, irq: %u\n",
7454 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7455 vcpu_info.vector = irq.vector;
7457 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7458 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7461 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7463 ret = irq_set_vcpu_affinity(host_irq, NULL);
7466 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7474 srcu_read_unlock(&kvm->irq_srcu, idx);
7478 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7480 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7481 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7482 FEATURE_CONTROL_LMCE;
7484 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7485 ~FEATURE_CONTROL_LMCE;
7488 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7490 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7491 if (to_vmx(vcpu)->nested.nested_run_pending)
7496 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7498 struct vcpu_vmx *vmx = to_vmx(vcpu);
7500 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7501 if (vmx->nested.smm.guest_mode)
7502 nested_vmx_vmexit(vcpu, -1, 0, 0);
7504 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7505 vmx->nested.vmxon = false;
7506 vmx_clear_hlt(vcpu);
7510 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7512 struct vcpu_vmx *vmx = to_vmx(vcpu);
7515 if (vmx->nested.smm.vmxon) {
7516 vmx->nested.vmxon = true;
7517 vmx->nested.smm.vmxon = false;
7520 if (vmx->nested.smm.guest_mode) {
7521 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7525 vmx->nested.smm.guest_mode = false;
7530 static int enable_smi_window(struct kvm_vcpu *vcpu)
7535 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7540 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7542 return to_vmx(vcpu)->nested.vmxon;
7545 static __init int hardware_setup(void)
7547 unsigned long host_bndcfgs;
7551 rdmsrl_safe(MSR_EFER, &host_efer);
7554 host_idt_base = dt.address;
7556 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7557 kvm_define_shared_msr(i, vmx_msr_index[i]);
7559 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7562 if (boot_cpu_has(X86_FEATURE_NX))
7563 kvm_enable_efer_bits(EFER_NX);
7565 if (boot_cpu_has(X86_FEATURE_MPX)) {
7566 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7567 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7570 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7571 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7574 if (!cpu_has_vmx_ept() ||
7575 !cpu_has_vmx_ept_4levels() ||
7576 !cpu_has_vmx_ept_mt_wb() ||
7577 !cpu_has_vmx_invept_global())
7580 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7581 enable_ept_ad_bits = 0;
7583 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7584 enable_unrestricted_guest = 0;
7586 if (!cpu_has_vmx_flexpriority())
7587 flexpriority_enabled = 0;
7589 if (!cpu_has_virtual_nmis())
7593 * set_apic_access_page_addr() is used to reload apic access
7594 * page upon invalidation. No need to do anything if not
7595 * using the APIC_ACCESS_ADDR VMCS field.
7597 if (!flexpriority_enabled)
7598 kvm_x86_ops->set_apic_access_page_addr = NULL;
7600 if (!cpu_has_vmx_tpr_shadow())
7601 kvm_x86_ops->update_cr8_intercept = NULL;
7603 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7604 kvm_disable_largepages();
7606 #if IS_ENABLED(CONFIG_HYPERV)
7607 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7609 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7610 kvm_x86_ops->tlb_remote_flush_with_range =
7611 hv_remote_flush_tlb_with_range;
7615 if (!cpu_has_vmx_ple()) {
7618 ple_window_grow = 0;
7620 ple_window_shrink = 0;
7623 if (!cpu_has_vmx_apicv()) {
7625 kvm_x86_ops->sync_pir_to_irr = NULL;
7628 if (cpu_has_vmx_tsc_scaling()) {
7629 kvm_has_tsc_control = true;
7630 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7631 kvm_tsc_scaling_ratio_frac_bits = 48;
7634 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7642 * Only enable PML when hardware supports PML feature, and both EPT
7643 * and EPT A/D bit features are enabled -- PML depends on them to work.
7645 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7649 kvm_x86_ops->slot_enable_log_dirty = NULL;
7650 kvm_x86_ops->slot_disable_log_dirty = NULL;
7651 kvm_x86_ops->flush_log_dirty = NULL;
7652 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7655 if (!cpu_has_vmx_preemption_timer())
7656 enable_preemption_timer = false;
7658 if (enable_preemption_timer) {
7659 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7662 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7663 cpu_preemption_timer_multi =
7664 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7667 use_timer_freq = (u64)tsc_khz * 1000;
7668 use_timer_freq >>= cpu_preemption_timer_multi;
7671 * KVM "disables" the preemption timer by setting it to its max
7672 * value. Don't use the timer if it might cause spurious exits
7673 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7675 if (use_timer_freq > 0xffffffffu / 10)
7676 enable_preemption_timer = false;
7679 if (!enable_preemption_timer) {
7680 kvm_x86_ops->set_hv_timer = NULL;
7681 kvm_x86_ops->cancel_hv_timer = NULL;
7682 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7685 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7687 kvm_mce_cap_supported |= MCG_LMCE_P;
7689 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7691 if (!enable_ept || !cpu_has_vmx_intel_pt())
7692 pt_mode = PT_MODE_SYSTEM;
7695 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7696 vmx_capability.ept, enable_apicv);
7698 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7703 r = alloc_kvm_area();
7705 nested_vmx_hardware_unsetup();
7709 static __exit void hardware_unsetup(void)
7712 nested_vmx_hardware_unsetup();
7717 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7718 .cpu_has_kvm_support = cpu_has_kvm_support,
7719 .disabled_by_bios = vmx_disabled_by_bios,
7720 .hardware_setup = hardware_setup,
7721 .hardware_unsetup = hardware_unsetup,
7722 .check_processor_compatibility = vmx_check_processor_compat,
7723 .hardware_enable = hardware_enable,
7724 .hardware_disable = hardware_disable,
7725 .cpu_has_accelerated_tpr = report_flexpriority,
7726 .has_emulated_msr = vmx_has_emulated_msr,
7728 .vm_init = vmx_vm_init,
7729 .vm_alloc = vmx_vm_alloc,
7730 .vm_free = vmx_vm_free,
7732 .vcpu_create = vmx_create_vcpu,
7733 .vcpu_free = vmx_free_vcpu,
7734 .vcpu_reset = vmx_vcpu_reset,
7736 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7737 .vcpu_load = vmx_vcpu_load,
7738 .vcpu_put = vmx_vcpu_put,
7740 .update_bp_intercept = update_exception_bitmap,
7741 .get_msr_feature = vmx_get_msr_feature,
7742 .get_msr = vmx_get_msr,
7743 .set_msr = vmx_set_msr,
7744 .get_segment_base = vmx_get_segment_base,
7745 .get_segment = vmx_get_segment,
7746 .set_segment = vmx_set_segment,
7747 .get_cpl = vmx_get_cpl,
7748 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7749 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7750 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7751 .set_cr0 = vmx_set_cr0,
7752 .set_cr3 = vmx_set_cr3,
7753 .set_cr4 = vmx_set_cr4,
7754 .set_efer = vmx_set_efer,
7755 .get_idt = vmx_get_idt,
7756 .set_idt = vmx_set_idt,
7757 .get_gdt = vmx_get_gdt,
7758 .set_gdt = vmx_set_gdt,
7759 .get_dr6 = vmx_get_dr6,
7760 .set_dr6 = vmx_set_dr6,
7761 .set_dr7 = vmx_set_dr7,
7762 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7763 .cache_reg = vmx_cache_reg,
7764 .get_rflags = vmx_get_rflags,
7765 .set_rflags = vmx_set_rflags,
7767 .tlb_flush = vmx_flush_tlb,
7768 .tlb_flush_gva = vmx_flush_tlb_gva,
7770 .run = vmx_vcpu_run,
7771 .handle_exit = vmx_handle_exit,
7772 .skip_emulated_instruction = skip_emulated_instruction,
7773 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7774 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7775 .patch_hypercall = vmx_patch_hypercall,
7776 .set_irq = vmx_inject_irq,
7777 .set_nmi = vmx_inject_nmi,
7778 .queue_exception = vmx_queue_exception,
7779 .cancel_injection = vmx_cancel_injection,
7780 .interrupt_allowed = vmx_interrupt_allowed,
7781 .nmi_allowed = vmx_nmi_allowed,
7782 .get_nmi_mask = vmx_get_nmi_mask,
7783 .set_nmi_mask = vmx_set_nmi_mask,
7784 .enable_nmi_window = enable_nmi_window,
7785 .enable_irq_window = enable_irq_window,
7786 .update_cr8_intercept = update_cr8_intercept,
7787 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7788 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7789 .get_enable_apicv = vmx_get_enable_apicv,
7790 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7791 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7792 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7793 .hwapic_irr_update = vmx_hwapic_irr_update,
7794 .hwapic_isr_update = vmx_hwapic_isr_update,
7795 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7796 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7797 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7798 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7800 .set_tss_addr = vmx_set_tss_addr,
7801 .set_identity_map_addr = vmx_set_identity_map_addr,
7802 .get_tdp_level = get_ept_level,
7803 .get_mt_mask = vmx_get_mt_mask,
7805 .get_exit_info = vmx_get_exit_info,
7807 .get_lpage_level = vmx_get_lpage_level,
7809 .cpuid_update = vmx_cpuid_update,
7811 .rdtscp_supported = vmx_rdtscp_supported,
7812 .invpcid_supported = vmx_invpcid_supported,
7814 .set_supported_cpuid = vmx_set_supported_cpuid,
7816 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7818 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7819 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7821 .set_tdp_cr3 = vmx_set_cr3,
7823 .check_intercept = vmx_check_intercept,
7824 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7825 .mpx_supported = vmx_mpx_supported,
7826 .xsaves_supported = vmx_xsaves_supported,
7827 .umip_emulated = vmx_umip_emulated,
7828 .pt_supported = vmx_pt_supported,
7830 .request_immediate_exit = vmx_request_immediate_exit,
7832 .sched_in = vmx_sched_in,
7834 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7835 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7836 .flush_log_dirty = vmx_flush_log_dirty,
7837 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7838 .write_log_dirty = vmx_write_pml_buffer,
7840 .pre_block = vmx_pre_block,
7841 .post_block = vmx_post_block,
7843 .pmu_ops = &intel_pmu_ops,
7845 .update_pi_irte = vmx_update_pi_irte,
7847 #ifdef CONFIG_X86_64
7848 .set_hv_timer = vmx_set_hv_timer,
7849 .cancel_hv_timer = vmx_cancel_hv_timer,
7852 .setup_mce = vmx_setup_mce,
7854 .smi_allowed = vmx_smi_allowed,
7855 .pre_enter_smm = vmx_pre_enter_smm,
7856 .pre_leave_smm = vmx_pre_leave_smm,
7857 .enable_smi_window = enable_smi_window,
7859 .check_nested_events = NULL,
7860 .get_nested_state = NULL,
7861 .set_nested_state = NULL,
7862 .get_vmcs12_pages = NULL,
7863 .nested_enable_evmcs = NULL,
7864 .nested_get_evmcs_version = NULL,
7865 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7866 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7869 static void vmx_cleanup_l1d_flush(void)
7871 if (vmx_l1d_flush_pages) {
7872 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7873 vmx_l1d_flush_pages = NULL;
7875 /* Restore state so sysfs ignores VMX */
7876 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7879 static void vmx_exit(void)
7881 #ifdef CONFIG_KEXEC_CORE
7882 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7888 #if IS_ENABLED(CONFIG_HYPERV)
7889 if (static_branch_unlikely(&enable_evmcs)) {
7891 struct hv_vp_assist_page *vp_ap;
7893 * Reset everything to support using non-enlightened VMCS
7894 * access later (e.g. when we reload the module with
7895 * enlightened_vmcs=0)
7897 for_each_online_cpu(cpu) {
7898 vp_ap = hv_get_vp_assist_page(cpu);
7903 vp_ap->nested_control.features.directhypercall = 0;
7904 vp_ap->current_nested_vmcs = 0;
7905 vp_ap->enlighten_vmentry = 0;
7908 static_branch_disable(&enable_evmcs);
7911 vmx_cleanup_l1d_flush();
7913 module_exit(vmx_exit);
7915 static int __init vmx_init(void)
7919 #if IS_ENABLED(CONFIG_HYPERV)
7921 * Enlightened VMCS usage should be recommended and the host needs
7922 * to support eVMCS v1 or above. We can also disable eVMCS support
7923 * with module parameter.
7925 if (enlightened_vmcs &&
7926 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7927 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7928 KVM_EVMCS_VERSION) {
7931 /* Check that we have assist pages on all online CPUs */
7932 for_each_online_cpu(cpu) {
7933 if (!hv_get_vp_assist_page(cpu)) {
7934 enlightened_vmcs = false;
7939 if (enlightened_vmcs) {
7940 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7941 static_branch_enable(&enable_evmcs);
7944 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7945 vmx_x86_ops.enable_direct_tlbflush
7946 = hv_enable_direct_tlbflush;
7949 enlightened_vmcs = false;
7953 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7954 __alignof__(struct vcpu_vmx), THIS_MODULE);
7959 * Must be called after kvm_init() so enable_ept is properly set
7960 * up. Hand the parameter mitigation value in which was stored in
7961 * the pre module init parser. If no parameter was given, it will
7962 * contain 'auto' which will be turned into the default 'cond'
7965 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7971 #ifdef CONFIG_KEXEC_CORE
7972 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7973 crash_vmclear_local_loaded_vmcss);
7975 vmx_check_vmcs12_offsets();
7979 module_init(vmx_init);