1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/frame.h>
17 #include <linux/highmem.h>
18 #include <linux/hrtimer.h>
19 #include <linux/kernel.h>
20 #include <linux/kvm_host.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/mod_devicetable.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
34 #include <asm/debugreg.h>
36 #include <asm/fpu/internal.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/kexec.h>
40 #include <asm/perf_event.h>
42 #include <asm/mmu_context.h>
43 #include <asm/mshyperv.h>
44 #include <asm/spec-ctrl.h>
45 #include <asm/virtext.h>
48 #include "capabilities.h"
52 #include "kvm_cache_regs.h"
64 MODULE_AUTHOR("Qumranet");
65 MODULE_LICENSE("GPL");
67 static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
73 bool __read_mostly enable_vpid = 1;
74 module_param_named(vpid, enable_vpid, bool, 0444);
76 static bool __read_mostly enable_vnmi = 1;
77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
79 bool __read_mostly flexpriority_enabled = 1;
80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
82 bool __read_mostly enable_ept = 1;
83 module_param_named(ept, enable_ept, bool, S_IRUGO);
85 bool __read_mostly enable_unrestricted_guest = 1;
86 module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
89 bool __read_mostly enable_ept_ad_bits = 1;
90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
92 static bool __read_mostly emulate_invalid_guest_state = true;
93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
95 static bool __read_mostly fasteoi = 1;
96 module_param(fasteoi, bool, S_IRUGO);
98 static bool __read_mostly enable_apicv = 1;
99 module_param(enable_apicv, bool, S_IRUGO);
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
106 static bool __read_mostly nested = 1;
107 module_param(nested, bool, S_IRUGO);
109 bool __read_mostly enable_pml = 1;
110 module_param_named(pml, enable_pml, bool, S_IRUGO);
112 static bool __read_mostly dump_invalid_vmcs = 0;
113 module_param(dump_invalid_vmcs, bool, 0644);
115 #define MSR_BITMAP_MODE_X2APIC 1
116 #define MSR_BITMAP_MODE_X2APIC_APICV 2
118 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
120 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
121 static int __read_mostly cpu_preemption_timer_multi;
122 static bool __read_mostly enable_preemption_timer = 1;
124 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
127 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
128 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
129 #define KVM_VM_CR0_ALWAYS_ON \
130 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
131 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
132 #define KVM_CR4_GUEST_OWNED_BITS \
133 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
134 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
136 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
137 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
138 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
140 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
142 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
143 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
144 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
145 RTIT_STATUS_BYTECNT))
147 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
148 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
151 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
152 * ple_gap: upper bound on the amount of time between two successive
153 * executions of PAUSE in a loop. Also indicate if ple enabled.
154 * According to test, this time is usually smaller than 128 cycles.
155 * ple_window: upper bound on the amount of time a guest is allowed to execute
156 * in a PAUSE loop. Tests indicate that most spinlocks are held for
157 * less than 2^12 cycles
158 * Time is measured based on a counter that runs at the same rate as the TSC,
159 * refer SDM volume 3b section 21.6.13 & 22.1.3.
161 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
162 module_param(ple_gap, uint, 0444);
164 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
165 module_param(ple_window, uint, 0444);
167 /* Default doubles per-vcpu window every exit. */
168 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
169 module_param(ple_window_grow, uint, 0444);
171 /* Default resets per-vcpu window every exit to ple_window. */
172 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
173 module_param(ple_window_shrink, uint, 0444);
175 /* Default is to compute the maximum so we can never overflow. */
176 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
177 module_param(ple_window_max, uint, 0444);
179 /* Default is SYSTEM mode, 1 for host-guest mode */
180 int __read_mostly pt_mode = PT_MODE_SYSTEM;
181 module_param(pt_mode, int, S_IRUGO);
183 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
184 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
185 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
187 /* Storage for pre module init parameter parsing */
188 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
190 static const struct {
193 } vmentry_l1d_param[] = {
194 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
195 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
196 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
197 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
198 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
199 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
202 #define L1D_CACHE_ORDER 4
203 static void *vmx_l1d_flush_pages;
205 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
210 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
211 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
216 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
220 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
223 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
224 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
225 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
230 /* If set to auto use the default l1tf mitigation method */
231 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
232 switch (l1tf_mitigation) {
233 case L1TF_MITIGATION_OFF:
234 l1tf = VMENTER_L1D_FLUSH_NEVER;
236 case L1TF_MITIGATION_FLUSH_NOWARN:
237 case L1TF_MITIGATION_FLUSH:
238 case L1TF_MITIGATION_FLUSH_NOSMT:
239 l1tf = VMENTER_L1D_FLUSH_COND;
241 case L1TF_MITIGATION_FULL:
242 case L1TF_MITIGATION_FULL_FORCE:
243 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
246 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
247 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
250 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
251 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
253 * This allocation for vmx_l1d_flush_pages is not tied to a VM
254 * lifetime and so should not be charged to a memcg.
256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
259 vmx_l1d_flush_pages = page_address(page);
262 * Initialize each page with a different pattern in
263 * order to protect against KSM in the nested
264 * virtualization case.
266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
272 l1tf_vmx_mitigation = l1tf;
274 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
275 static_branch_enable(&vmx_l1d_should_flush);
277 static_branch_disable(&vmx_l1d_should_flush);
279 if (l1tf == VMENTER_L1D_FLUSH_COND)
280 static_branch_enable(&vmx_l1d_flush_cond);
282 static_branch_disable(&vmx_l1d_flush_cond);
286 static int vmentry_l1d_flush_parse(const char *s)
291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
292 if (vmentry_l1d_param[i].for_parse &&
293 sysfs_streq(s, vmentry_l1d_param[i].option))
300 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
304 l1tf = vmentry_l1d_flush_parse(s);
308 if (!boot_cpu_has(X86_BUG_L1TF))
312 * Has vmx_init() run already? If not then this is the pre init
313 * parameter parsing. In that case just store the value and let
314 * vmx_init() do the proper setup after enable_ept has been
317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
318 vmentry_l1d_flush_param = l1tf;
322 mutex_lock(&vmx_l1d_flush_mutex);
323 ret = vmx_setup_l1d_flush(l1tf);
324 mutex_unlock(&vmx_l1d_flush_mutex);
328 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
331 return sprintf(s, "???\n");
333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
336 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
337 .set = vmentry_l1d_flush_set,
338 .get = vmentry_l1d_flush_get,
340 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
342 static bool guest_state_valid(struct kvm_vcpu *vcpu);
343 static u32 vmx_segment_access_rights(struct kvm_segment *var);
344 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
347 void vmx_vmexit(void);
349 #define vmx_insn_failed(fmt...) \
352 pr_warn_ratelimited(fmt); \
355 asmlinkage void vmread_error(unsigned long field, bool fault)
358 kvm_spurious_fault();
360 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
363 noinline void vmwrite_error(unsigned long field, unsigned long value)
365 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
366 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
369 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
371 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
374 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
376 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
379 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
381 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
385 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
387 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
391 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
392 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
394 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
395 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
397 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
400 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
401 * can find which vCPU should be waken up.
403 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
404 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
406 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
407 static DEFINE_SPINLOCK(vmx_vpid_lock);
409 struct vmcs_config vmcs_config;
410 struct vmx_capability vmx_capability;
412 #define VMX_SEGMENT_FIELD(seg) \
413 [VCPU_SREG_##seg] = { \
414 .selector = GUEST_##seg##_SELECTOR, \
415 .base = GUEST_##seg##_BASE, \
416 .limit = GUEST_##seg##_LIMIT, \
417 .ar_bytes = GUEST_##seg##_AR_BYTES, \
420 static const struct kvm_vmx_segment_field {
425 } kvm_vmx_segment_fields[] = {
426 VMX_SEGMENT_FIELD(CS),
427 VMX_SEGMENT_FIELD(DS),
428 VMX_SEGMENT_FIELD(ES),
429 VMX_SEGMENT_FIELD(FS),
430 VMX_SEGMENT_FIELD(GS),
431 VMX_SEGMENT_FIELD(SS),
432 VMX_SEGMENT_FIELD(TR),
433 VMX_SEGMENT_FIELD(LDTR),
437 static unsigned long host_idt_base;
440 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
441 * will emulate SYSCALL in legacy mode if the vendor string in guest
442 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
443 * support this emulation, IA32_STAR must always be included in
444 * vmx_msr_index[], even in i386 builds.
446 const u32 vmx_msr_index[] = {
448 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
450 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
454 #if IS_ENABLED(CONFIG_HYPERV)
455 static bool __read_mostly enlightened_vmcs = true;
456 module_param(enlightened_vmcs, bool, 0444);
458 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
459 static void check_ept_pointer_match(struct kvm *kvm)
461 struct kvm_vcpu *vcpu;
462 u64 tmp_eptp = INVALID_PAGE;
465 kvm_for_each_vcpu(i, vcpu, kvm) {
466 if (!VALID_PAGE(tmp_eptp)) {
467 tmp_eptp = to_vmx(vcpu)->ept_pointer;
468 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
469 to_kvm_vmx(kvm)->ept_pointers_match
470 = EPT_POINTERS_MISMATCH;
475 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
478 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
481 struct kvm_tlb_range *range = data;
483 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
487 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
488 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
490 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
493 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
494 * of the base of EPT PML4 table, strip off EPT configuration
498 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
499 kvm_fill_hv_flush_list_func, (void *)range);
501 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
504 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
505 struct kvm_tlb_range *range)
507 struct kvm_vcpu *vcpu;
510 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
512 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
513 check_ept_pointer_match(kvm);
515 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
516 kvm_for_each_vcpu(i, vcpu, kvm) {
517 /* If ept_pointer is invalid pointer, bypass flush request. */
518 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
519 ret |= __hv_remote_flush_tlb_with_range(
523 ret = __hv_remote_flush_tlb_with_range(kvm,
524 kvm_get_vcpu(kvm, 0), range);
527 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
530 static int hv_remote_flush_tlb(struct kvm *kvm)
532 return hv_remote_flush_tlb_with_range(kvm, NULL);
535 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
537 struct hv_enlightened_vmcs *evmcs;
538 struct hv_partition_assist_pg **p_hv_pa_pg =
539 &vcpu->kvm->arch.hyperv.hv_pa_pg;
541 * Synthetic VM-Exit is not enabled in current code and so All
542 * evmcs in singe VM shares same assist page.
545 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
550 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
552 evmcs->partition_assist_page =
554 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
555 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
560 #endif /* IS_ENABLED(CONFIG_HYPERV) */
563 * Comment's format: document - errata name - stepping - processor name.
565 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
567 static u32 vmx_preemption_cpu_tfms[] = {
568 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
570 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
571 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
572 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
574 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
576 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
577 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
579 * 320767.pdf - AAP86 - B1 -
580 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
583 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
585 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
587 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
589 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
590 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
591 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
593 /* Xeon E3-1220 V2 */
597 static inline bool cpu_has_broken_vmx_preemption_timer(void)
599 u32 eax = cpuid_eax(0x00000001), i;
601 /* Clear the reserved bits */
602 eax &= ~(0x3U << 14 | 0xfU << 28);
603 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
604 if (eax == vmx_preemption_cpu_tfms[i])
610 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
612 return flexpriority_enabled && lapic_in_kernel(vcpu);
615 static inline bool report_flexpriority(void)
617 return flexpriority_enabled;
620 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
624 for (i = 0; i < vmx->nmsrs; ++i)
625 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
630 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
634 i = __find_msr_index(vmx, msr);
636 return &vmx->guest_msrs[i];
640 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
644 u64 old_msr_data = msr->data;
646 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
648 ret = kvm_set_shared_msr(msr->index, msr->data,
652 msr->data = old_msr_data;
657 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
659 vmcs_clear(loaded_vmcs->vmcs);
660 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
661 vmcs_clear(loaded_vmcs->shadow_vmcs);
662 loaded_vmcs->cpu = -1;
663 loaded_vmcs->launched = 0;
666 #ifdef CONFIG_KEXEC_CORE
668 * This bitmap is used to indicate whether the vmclear
669 * operation is enabled on all cpus. All disabled by
672 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
674 static inline void crash_enable_local_vmclear(int cpu)
676 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
679 static inline void crash_disable_local_vmclear(int cpu)
681 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
684 static inline int crash_local_vmclear_enabled(int cpu)
686 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
689 static void crash_vmclear_local_loaded_vmcss(void)
691 int cpu = raw_smp_processor_id();
692 struct loaded_vmcs *v;
694 if (!crash_local_vmclear_enabled(cpu))
697 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
698 loaded_vmcss_on_cpu_link)
702 static inline void crash_enable_local_vmclear(int cpu) { }
703 static inline void crash_disable_local_vmclear(int cpu) { }
704 #endif /* CONFIG_KEXEC_CORE */
706 static void __loaded_vmcs_clear(void *arg)
708 struct loaded_vmcs *loaded_vmcs = arg;
709 int cpu = raw_smp_processor_id();
711 if (loaded_vmcs->cpu != cpu)
712 return; /* vcpu migration can race with cpu offline */
713 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
714 per_cpu(current_vmcs, cpu) = NULL;
715 crash_disable_local_vmclear(cpu);
716 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
719 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
720 * is before setting loaded_vmcs->vcpu to -1 which is done in
721 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
722 * then adds the vmcs into percpu list before it is deleted.
726 loaded_vmcs_init(loaded_vmcs);
727 crash_enable_local_vmclear(cpu);
730 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
732 int cpu = loaded_vmcs->cpu;
735 smp_call_function_single(cpu,
736 __loaded_vmcs_clear, loaded_vmcs, 1);
739 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
743 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
745 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
746 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
747 vmx->segment_cache.bitmask = 0;
749 ret = vmx->segment_cache.bitmask & mask;
750 vmx->segment_cache.bitmask |= mask;
754 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
756 u16 *p = &vmx->segment_cache.seg[seg].selector;
758 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
759 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
763 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
765 ulong *p = &vmx->segment_cache.seg[seg].base;
767 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
768 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
772 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
774 u32 *p = &vmx->segment_cache.seg[seg].limit;
776 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
777 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
781 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
783 u32 *p = &vmx->segment_cache.seg[seg].ar;
785 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
786 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
790 void update_exception_bitmap(struct kvm_vcpu *vcpu)
794 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
795 (1u << DB_VECTOR) | (1u << AC_VECTOR);
797 * Guest access to VMware backdoor ports could legitimately
798 * trigger #GP because of TSS I/O permission bitmap.
799 * We intercept those #GP and allow access to them anyway
802 if (enable_vmware_backdoor)
803 eb |= (1u << GP_VECTOR);
804 if ((vcpu->guest_debug &
805 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
806 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
807 eb |= 1u << BP_VECTOR;
808 if (to_vmx(vcpu)->rmode.vm86_active)
811 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
813 /* When we are running a nested L2 guest and L1 specified for it a
814 * certain exception bitmap, we must trap the same exceptions and pass
815 * them to L1. When running L2, we will only handle the exceptions
816 * specified above if L1 did not want them.
818 if (is_guest_mode(vcpu))
819 eb |= get_vmcs12(vcpu)->exception_bitmap;
821 vmcs_write32(EXCEPTION_BITMAP, eb);
825 * Check if MSR is intercepted for currently loaded MSR bitmap.
827 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
829 unsigned long *msr_bitmap;
830 int f = sizeof(unsigned long);
832 if (!cpu_has_vmx_msr_bitmap())
835 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
838 return !!test_bit(msr, msr_bitmap + 0x800 / f);
839 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
841 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
847 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
848 unsigned long entry, unsigned long exit)
850 vm_entry_controls_clearbit(vmx, entry);
851 vm_exit_controls_clearbit(vmx, exit);
854 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
858 for (i = 0; i < m->nr; ++i) {
859 if (m->val[i].index == msr)
865 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
868 struct msr_autoload *m = &vmx->msr_autoload;
872 if (cpu_has_load_ia32_efer()) {
873 clear_atomic_switch_msr_special(vmx,
874 VM_ENTRY_LOAD_IA32_EFER,
875 VM_EXIT_LOAD_IA32_EFER);
879 case MSR_CORE_PERF_GLOBAL_CTRL:
880 if (cpu_has_load_perf_global_ctrl()) {
881 clear_atomic_switch_msr_special(vmx,
882 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
883 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
888 i = vmx_find_msr_index(&m->guest, msr);
892 m->guest.val[i] = m->guest.val[m->guest.nr];
893 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
896 i = vmx_find_msr_index(&m->host, msr);
901 m->host.val[i] = m->host.val[m->host.nr];
902 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
905 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
906 unsigned long entry, unsigned long exit,
907 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
908 u64 guest_val, u64 host_val)
910 vmcs_write64(guest_val_vmcs, guest_val);
911 if (host_val_vmcs != HOST_IA32_EFER)
912 vmcs_write64(host_val_vmcs, host_val);
913 vm_entry_controls_setbit(vmx, entry);
914 vm_exit_controls_setbit(vmx, exit);
917 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
918 u64 guest_val, u64 host_val, bool entry_only)
921 struct msr_autoload *m = &vmx->msr_autoload;
925 if (cpu_has_load_ia32_efer()) {
926 add_atomic_switch_msr_special(vmx,
927 VM_ENTRY_LOAD_IA32_EFER,
928 VM_EXIT_LOAD_IA32_EFER,
931 guest_val, host_val);
935 case MSR_CORE_PERF_GLOBAL_CTRL:
936 if (cpu_has_load_perf_global_ctrl()) {
937 add_atomic_switch_msr_special(vmx,
938 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
939 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
940 GUEST_IA32_PERF_GLOBAL_CTRL,
941 HOST_IA32_PERF_GLOBAL_CTRL,
942 guest_val, host_val);
946 case MSR_IA32_PEBS_ENABLE:
947 /* PEBS needs a quiescent period after being disabled (to write
948 * a record). Disabling PEBS through VMX MSR swapping doesn't
949 * provide that period, so a CPU could write host's record into
952 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
955 i = vmx_find_msr_index(&m->guest, msr);
957 j = vmx_find_msr_index(&m->host, msr);
959 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
960 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) {
961 printk_once(KERN_WARNING "Not enough msr switch entries. "
962 "Can't add msr %x\n", msr);
967 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
969 m->guest.val[i].index = msr;
970 m->guest.val[i].value = guest_val;
977 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
979 m->host.val[j].index = msr;
980 m->host.val[j].value = host_val;
983 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
985 u64 guest_efer = vmx->vcpu.arch.efer;
988 /* Shadow paging assumes NX to be available. */
990 guest_efer |= EFER_NX;
993 * LMA and LME handled by hardware; SCE meaningless outside long mode.
995 ignore_bits |= EFER_SCE;
997 ignore_bits |= EFER_LMA | EFER_LME;
998 /* SCE is meaningful only in long mode on Intel */
999 if (guest_efer & EFER_LMA)
1000 ignore_bits &= ~(u64)EFER_SCE;
1004 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1005 * On CPUs that support "load IA32_EFER", always switch EFER
1006 * atomically, since it's faster than switching it manually.
1008 if (cpu_has_load_ia32_efer() ||
1009 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1010 if (!(guest_efer & EFER_LMA))
1011 guest_efer &= ~EFER_LME;
1012 if (guest_efer != host_efer)
1013 add_atomic_switch_msr(vmx, MSR_EFER,
1014 guest_efer, host_efer, false);
1016 clear_atomic_switch_msr(vmx, MSR_EFER);
1019 clear_atomic_switch_msr(vmx, MSR_EFER);
1021 guest_efer &= ~ignore_bits;
1022 guest_efer |= host_efer & ignore_bits;
1024 vmx->guest_msrs[efer_offset].data = guest_efer;
1025 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1031 #ifdef CONFIG_X86_32
1033 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1034 * VMCS rather than the segment table. KVM uses this helper to figure
1035 * out the current bases to poke them into the VMCS before entry.
1037 static unsigned long segment_base(u16 selector)
1039 struct desc_struct *table;
1042 if (!(selector & ~SEGMENT_RPL_MASK))
1045 table = get_current_gdt_ro();
1047 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1048 u16 ldt_selector = kvm_read_ldt();
1050 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1053 table = (struct desc_struct *)segment_base(ldt_selector);
1055 v = get_desc_base(&table[selector >> 3]);
1060 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1064 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1065 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1066 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1067 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1068 for (i = 0; i < addr_range; i++) {
1069 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1070 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1074 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1078 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1079 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1080 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1081 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1082 for (i = 0; i < addr_range; i++) {
1083 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1084 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1088 static void pt_guest_enter(struct vcpu_vmx *vmx)
1090 if (pt_mode == PT_MODE_SYSTEM)
1094 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1095 * Save host state before VM entry.
1097 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1098 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1099 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1100 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1101 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1105 static void pt_guest_exit(struct vcpu_vmx *vmx)
1107 if (pt_mode == PT_MODE_SYSTEM)
1110 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1111 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1112 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1115 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1116 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1119 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1120 unsigned long fs_base, unsigned long gs_base)
1122 if (unlikely(fs_sel != host->fs_sel)) {
1124 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1126 vmcs_write16(HOST_FS_SELECTOR, 0);
1127 host->fs_sel = fs_sel;
1129 if (unlikely(gs_sel != host->gs_sel)) {
1131 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1133 vmcs_write16(HOST_GS_SELECTOR, 0);
1134 host->gs_sel = gs_sel;
1136 if (unlikely(fs_base != host->fs_base)) {
1137 vmcs_writel(HOST_FS_BASE, fs_base);
1138 host->fs_base = fs_base;
1140 if (unlikely(gs_base != host->gs_base)) {
1141 vmcs_writel(HOST_GS_BASE, gs_base);
1142 host->gs_base = gs_base;
1146 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1148 struct vcpu_vmx *vmx = to_vmx(vcpu);
1149 struct vmcs_host_state *host_state;
1150 #ifdef CONFIG_X86_64
1151 int cpu = raw_smp_processor_id();
1153 unsigned long fs_base, gs_base;
1157 vmx->req_immediate_exit = false;
1160 * Note that guest MSRs to be saved/restored can also be changed
1161 * when guest state is loaded. This happens when guest transitions
1162 * to/from long-mode by setting MSR_EFER.LMA.
1164 if (!vmx->guest_msrs_ready) {
1165 vmx->guest_msrs_ready = true;
1166 for (i = 0; i < vmx->save_nmsrs; ++i)
1167 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1168 vmx->guest_msrs[i].data,
1169 vmx->guest_msrs[i].mask);
1172 if (vmx->guest_state_loaded)
1175 host_state = &vmx->loaded_vmcs->host_state;
1178 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1179 * allow segment selectors with cpl > 0 or ti == 1.
1181 host_state->ldt_sel = kvm_read_ldt();
1183 #ifdef CONFIG_X86_64
1184 savesegment(ds, host_state->ds_sel);
1185 savesegment(es, host_state->es_sel);
1187 gs_base = cpu_kernelmode_gs_base(cpu);
1188 if (likely(is_64bit_mm(current->mm))) {
1189 save_fsgs_for_kvm();
1190 fs_sel = current->thread.fsindex;
1191 gs_sel = current->thread.gsindex;
1192 fs_base = current->thread.fsbase;
1193 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1195 savesegment(fs, fs_sel);
1196 savesegment(gs, gs_sel);
1197 fs_base = read_msr(MSR_FS_BASE);
1198 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1201 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1203 savesegment(fs, fs_sel);
1204 savesegment(gs, gs_sel);
1205 fs_base = segment_base(fs_sel);
1206 gs_base = segment_base(gs_sel);
1209 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1210 vmx->guest_state_loaded = true;
1213 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1215 struct vmcs_host_state *host_state;
1217 if (!vmx->guest_state_loaded)
1220 host_state = &vmx->loaded_vmcs->host_state;
1222 ++vmx->vcpu.stat.host_state_reload;
1224 #ifdef CONFIG_X86_64
1225 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1227 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1228 kvm_load_ldt(host_state->ldt_sel);
1229 #ifdef CONFIG_X86_64
1230 load_gs_index(host_state->gs_sel);
1232 loadsegment(gs, host_state->gs_sel);
1235 if (host_state->fs_sel & 7)
1236 loadsegment(fs, host_state->fs_sel);
1237 #ifdef CONFIG_X86_64
1238 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1239 loadsegment(ds, host_state->ds_sel);
1240 loadsegment(es, host_state->es_sel);
1243 invalidate_tss_limit();
1244 #ifdef CONFIG_X86_64
1245 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1247 load_fixmap_gdt(raw_smp_processor_id());
1248 vmx->guest_state_loaded = false;
1249 vmx->guest_msrs_ready = false;
1252 #ifdef CONFIG_X86_64
1253 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1256 if (vmx->guest_state_loaded)
1257 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1259 return vmx->msr_guest_kernel_gs_base;
1262 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1265 if (vmx->guest_state_loaded)
1266 wrmsrl(MSR_KERNEL_GS_BASE, data);
1268 vmx->msr_guest_kernel_gs_base = data;
1272 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1274 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1275 struct pi_desc old, new;
1279 * In case of hot-plug or hot-unplug, we may have to undo
1280 * vmx_vcpu_pi_put even if there is no assigned device. And we
1281 * always keep PI.NDST up to date for simplicity: it makes the
1282 * code easier, and CPU migration is not a fast path.
1284 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1288 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1289 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1290 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1291 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1294 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1295 pi_clear_sn(pi_desc);
1296 goto after_clear_sn;
1299 /* The full case. */
1301 old.control = new.control = pi_desc->control;
1303 dest = cpu_physical_id(cpu);
1305 if (x2apic_enabled())
1308 new.ndst = (dest << 8) & 0xFF00;
1311 } while (cmpxchg64(&pi_desc->control, old.control,
1312 new.control) != old.control);
1317 * Clear SN before reading the bitmap. The VT-d firmware
1318 * writes the bitmap and reads SN atomically (5.2.3 in the
1319 * spec), so it doesn't really have a memory barrier that
1320 * pairs with this, but we cannot do that and we need one.
1322 smp_mb__after_atomic();
1324 if (!pi_is_pir_empty(pi_desc))
1328 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1330 struct vcpu_vmx *vmx = to_vmx(vcpu);
1331 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1333 if (!already_loaded) {
1334 loaded_vmcs_clear(vmx->loaded_vmcs);
1335 local_irq_disable();
1336 crash_disable_local_vmclear(cpu);
1339 * Read loaded_vmcs->cpu should be before fetching
1340 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1341 * See the comments in __loaded_vmcs_clear().
1345 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1346 &per_cpu(loaded_vmcss_on_cpu, cpu));
1347 crash_enable_local_vmclear(cpu);
1351 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1352 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1353 vmcs_load(vmx->loaded_vmcs->vmcs);
1354 indirect_branch_prediction_barrier();
1357 if (!already_loaded) {
1358 void *gdt = get_current_gdt_ro();
1359 unsigned long sysenter_esp;
1361 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1364 * Linux uses per-cpu TSS and GDT, so set these when switching
1365 * processors. See 22.2.4.
1367 vmcs_writel(HOST_TR_BASE,
1368 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1369 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1371 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1372 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1374 vmx->loaded_vmcs->cpu = cpu;
1377 /* Setup TSC multiplier */
1378 if (kvm_has_tsc_control &&
1379 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1380 decache_tsc_multiplier(vmx);
1384 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1385 * vcpu mutex is already taken.
1387 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1389 struct vcpu_vmx *vmx = to_vmx(vcpu);
1391 vmx_vcpu_load_vmcs(vcpu, cpu);
1393 vmx_vcpu_pi_load(vcpu, cpu);
1395 vmx->host_pkru = read_pkru();
1396 vmx->host_debugctlmsr = get_debugctlmsr();
1399 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1401 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1403 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1404 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1405 !kvm_vcpu_apicv_active(vcpu))
1408 /* Set SN when the vCPU is preempted */
1409 if (vcpu->preempted)
1413 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1415 vmx_vcpu_pi_put(vcpu);
1417 vmx_prepare_switch_to_host(to_vmx(vcpu));
1420 static bool emulation_required(struct kvm_vcpu *vcpu)
1422 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1425 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1427 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1429 struct vcpu_vmx *vmx = to_vmx(vcpu);
1430 unsigned long rflags, save_rflags;
1432 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1433 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1434 rflags = vmcs_readl(GUEST_RFLAGS);
1435 if (vmx->rmode.vm86_active) {
1436 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1437 save_rflags = vmx->rmode.save_rflags;
1438 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1440 vmx->rflags = rflags;
1445 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1447 struct vcpu_vmx *vmx = to_vmx(vcpu);
1448 unsigned long old_rflags;
1450 if (enable_unrestricted_guest) {
1451 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1452 vmx->rflags = rflags;
1453 vmcs_writel(GUEST_RFLAGS, rflags);
1457 old_rflags = vmx_get_rflags(vcpu);
1458 vmx->rflags = rflags;
1459 if (vmx->rmode.vm86_active) {
1460 vmx->rmode.save_rflags = rflags;
1461 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1463 vmcs_writel(GUEST_RFLAGS, rflags);
1465 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1466 vmx->emulation_required = emulation_required(vcpu);
1469 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1471 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1474 if (interruptibility & GUEST_INTR_STATE_STI)
1475 ret |= KVM_X86_SHADOW_INT_STI;
1476 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1477 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1482 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1484 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1485 u32 interruptibility = interruptibility_old;
1487 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1489 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1490 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1491 else if (mask & KVM_X86_SHADOW_INT_STI)
1492 interruptibility |= GUEST_INTR_STATE_STI;
1494 if ((interruptibility != interruptibility_old))
1495 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1498 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1500 struct vcpu_vmx *vmx = to_vmx(vcpu);
1501 unsigned long value;
1504 * Any MSR write that attempts to change bits marked reserved will
1507 if (data & vmx->pt_desc.ctl_bitmask)
1511 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1512 * result in a #GP unless the same write also clears TraceEn.
1514 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1515 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1519 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1520 * and FabricEn would cause #GP, if
1521 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1523 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1524 !(data & RTIT_CTL_FABRIC_EN) &&
1525 !intel_pt_validate_cap(vmx->pt_desc.caps,
1526 PT_CAP_single_range_output))
1530 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1531 * utilize encodings marked reserved will casue a #GP fault.
1533 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1534 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1535 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1536 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1538 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1539 PT_CAP_cycle_thresholds);
1540 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1541 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1542 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1544 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1545 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1546 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1547 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1551 * If ADDRx_CFG is reserved or the encodings is >2 will
1552 * cause a #GP fault.
1554 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1555 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1557 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1558 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1560 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1561 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1563 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1564 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1570 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1575 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1576 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1577 * set when EPT misconfig occurs. In practice, real hardware updates
1578 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1579 * (namely Hyper-V) don't set it due to it being undefined behavior,
1580 * i.e. we end up advancing IP with some random value.
1582 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1583 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1584 rip = kvm_rip_read(vcpu);
1585 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1586 kvm_rip_write(vcpu, rip);
1588 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1592 /* skipping an emulated instruction also counts */
1593 vmx_set_interrupt_shadow(vcpu, 0);
1598 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1601 * Ensure that we clear the HLT state in the VMCS. We don't need to
1602 * explicitly skip the instruction because if the HLT state is set,
1603 * then the instruction is already executing and RIP has already been
1606 if (kvm_hlt_in_guest(vcpu->kvm) &&
1607 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1608 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1611 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1613 struct vcpu_vmx *vmx = to_vmx(vcpu);
1614 unsigned nr = vcpu->arch.exception.nr;
1615 bool has_error_code = vcpu->arch.exception.has_error_code;
1616 u32 error_code = vcpu->arch.exception.error_code;
1617 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1619 kvm_deliver_exception_payload(vcpu);
1621 if (has_error_code) {
1622 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1623 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1626 if (vmx->rmode.vm86_active) {
1628 if (kvm_exception_is_soft(nr))
1629 inc_eip = vcpu->arch.event_exit_inst_len;
1630 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1634 WARN_ON_ONCE(vmx->emulation_required);
1636 if (kvm_exception_is_soft(nr)) {
1637 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1638 vmx->vcpu.arch.event_exit_inst_len);
1639 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1641 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1643 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1645 vmx_clear_hlt(vcpu);
1648 static bool vmx_rdtscp_supported(void)
1650 return cpu_has_vmx_rdtscp();
1653 static bool vmx_invpcid_supported(void)
1655 return cpu_has_vmx_invpcid();
1659 * Swap MSR entry in host/guest MSR entry array.
1661 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1663 struct shared_msr_entry tmp;
1665 tmp = vmx->guest_msrs[to];
1666 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1667 vmx->guest_msrs[from] = tmp;
1671 * Set up the vmcs to automatically save and restore system
1672 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1673 * mode, as fiddling with msrs is very expensive.
1675 static void setup_msrs(struct vcpu_vmx *vmx)
1677 int save_nmsrs, index;
1680 #ifdef CONFIG_X86_64
1682 * The SYSCALL MSRs are only needed on long mode guests, and only
1683 * when EFER.SCE is set.
1685 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1686 index = __find_msr_index(vmx, MSR_STAR);
1688 move_msr_up(vmx, index, save_nmsrs++);
1689 index = __find_msr_index(vmx, MSR_LSTAR);
1691 move_msr_up(vmx, index, save_nmsrs++);
1692 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1694 move_msr_up(vmx, index, save_nmsrs++);
1697 index = __find_msr_index(vmx, MSR_EFER);
1698 if (index >= 0 && update_transition_efer(vmx, index))
1699 move_msr_up(vmx, index, save_nmsrs++);
1700 index = __find_msr_index(vmx, MSR_TSC_AUX);
1701 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1702 move_msr_up(vmx, index, save_nmsrs++);
1703 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1705 move_msr_up(vmx, index, save_nmsrs++);
1707 vmx->save_nmsrs = save_nmsrs;
1708 vmx->guest_msrs_ready = false;
1710 if (cpu_has_vmx_msr_bitmap())
1711 vmx_update_msr_bitmap(&vmx->vcpu);
1714 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1716 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1718 if (is_guest_mode(vcpu) &&
1719 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1720 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1722 return vcpu->arch.tsc_offset;
1725 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1727 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1728 u64 g_tsc_offset = 0;
1731 * We're here if L1 chose not to trap WRMSR to TSC. According
1732 * to the spec, this should set L1's TSC; The offset that L1
1733 * set for L2 remains unchanged, and still needs to be added
1734 * to the newly set TSC to get L2's TSC.
1736 if (is_guest_mode(vcpu) &&
1737 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1738 g_tsc_offset = vmcs12->tsc_offset;
1740 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1741 vcpu->arch.tsc_offset - g_tsc_offset,
1743 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1744 return offset + g_tsc_offset;
1748 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1749 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1750 * all guests if the "nested" module option is off, and can also be disabled
1751 * for a single guest by disabling its VMX cpuid bit.
1753 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1755 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1758 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1761 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1763 return !(val & ~valid_bits);
1766 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1768 switch (msr->index) {
1769 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1772 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1779 * Reads an msr value (of 'msr_index') into 'pdata'.
1780 * Returns 0 on success, non-0 otherwise.
1781 * Assumes vcpu_load() was already called.
1783 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1785 struct vcpu_vmx *vmx = to_vmx(vcpu);
1786 struct shared_msr_entry *msr;
1789 switch (msr_info->index) {
1790 #ifdef CONFIG_X86_64
1792 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1795 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1797 case MSR_KERNEL_GS_BASE:
1798 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1802 return kvm_get_msr_common(vcpu, msr_info);
1803 case MSR_IA32_TSX_CTRL:
1804 if (!msr_info->host_initiated &&
1805 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1807 goto find_shared_msr;
1808 case MSR_IA32_UMWAIT_CONTROL:
1809 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1812 msr_info->data = vmx->msr_ia32_umwait_control;
1814 case MSR_IA32_SPEC_CTRL:
1815 if (!msr_info->host_initiated &&
1816 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1819 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1821 case MSR_IA32_SYSENTER_CS:
1822 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1824 case MSR_IA32_SYSENTER_EIP:
1825 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1827 case MSR_IA32_SYSENTER_ESP:
1828 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1830 case MSR_IA32_BNDCFGS:
1831 if (!kvm_mpx_supported() ||
1832 (!msr_info->host_initiated &&
1833 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1835 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1837 case MSR_IA32_MCG_EXT_CTL:
1838 if (!msr_info->host_initiated &&
1839 !(vmx->msr_ia32_feature_control &
1840 FEATURE_CONTROL_LMCE))
1842 msr_info->data = vcpu->arch.mcg_ext_ctl;
1844 case MSR_IA32_FEATURE_CONTROL:
1845 msr_info->data = vmx->msr_ia32_feature_control;
1847 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1848 if (!nested_vmx_allowed(vcpu))
1850 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1852 case MSR_IA32_RTIT_CTL:
1853 if (pt_mode != PT_MODE_HOST_GUEST)
1855 msr_info->data = vmx->pt_desc.guest.ctl;
1857 case MSR_IA32_RTIT_STATUS:
1858 if (pt_mode != PT_MODE_HOST_GUEST)
1860 msr_info->data = vmx->pt_desc.guest.status;
1862 case MSR_IA32_RTIT_CR3_MATCH:
1863 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1864 !intel_pt_validate_cap(vmx->pt_desc.caps,
1865 PT_CAP_cr3_filtering))
1867 msr_info->data = vmx->pt_desc.guest.cr3_match;
1869 case MSR_IA32_RTIT_OUTPUT_BASE:
1870 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1871 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1872 PT_CAP_topa_output) &&
1873 !intel_pt_validate_cap(vmx->pt_desc.caps,
1874 PT_CAP_single_range_output)))
1876 msr_info->data = vmx->pt_desc.guest.output_base;
1878 case MSR_IA32_RTIT_OUTPUT_MASK:
1879 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1880 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1881 PT_CAP_topa_output) &&
1882 !intel_pt_validate_cap(vmx->pt_desc.caps,
1883 PT_CAP_single_range_output)))
1885 msr_info->data = vmx->pt_desc.guest.output_mask;
1887 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1888 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1889 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1890 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1891 PT_CAP_num_address_ranges)))
1894 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1896 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1899 if (!msr_info->host_initiated &&
1900 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1902 goto find_shared_msr;
1905 msr = find_msr_entry(vmx, msr_info->index);
1907 msr_info->data = msr->data;
1910 return kvm_get_msr_common(vcpu, msr_info);
1917 * Writes msr value into into the appropriate "register".
1918 * Returns 0 on success, non-0 otherwise.
1919 * Assumes vcpu_load() was already called.
1921 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1923 struct vcpu_vmx *vmx = to_vmx(vcpu);
1924 struct shared_msr_entry *msr;
1926 u32 msr_index = msr_info->index;
1927 u64 data = msr_info->data;
1930 switch (msr_index) {
1932 ret = kvm_set_msr_common(vcpu, msr_info);
1934 #ifdef CONFIG_X86_64
1936 vmx_segment_cache_clear(vmx);
1937 vmcs_writel(GUEST_FS_BASE, data);
1940 vmx_segment_cache_clear(vmx);
1941 vmcs_writel(GUEST_GS_BASE, data);
1943 case MSR_KERNEL_GS_BASE:
1944 vmx_write_guest_kernel_gs_base(vmx, data);
1947 case MSR_IA32_SYSENTER_CS:
1948 if (is_guest_mode(vcpu))
1949 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1950 vmcs_write32(GUEST_SYSENTER_CS, data);
1952 case MSR_IA32_SYSENTER_EIP:
1953 if (is_guest_mode(vcpu))
1954 get_vmcs12(vcpu)->guest_sysenter_eip = data;
1955 vmcs_writel(GUEST_SYSENTER_EIP, data);
1957 case MSR_IA32_SYSENTER_ESP:
1958 if (is_guest_mode(vcpu))
1959 get_vmcs12(vcpu)->guest_sysenter_esp = data;
1960 vmcs_writel(GUEST_SYSENTER_ESP, data);
1962 case MSR_IA32_DEBUGCTLMSR:
1963 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1964 VM_EXIT_SAVE_DEBUG_CONTROLS)
1965 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1967 ret = kvm_set_msr_common(vcpu, msr_info);
1970 case MSR_IA32_BNDCFGS:
1971 if (!kvm_mpx_supported() ||
1972 (!msr_info->host_initiated &&
1973 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1975 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1976 (data & MSR_IA32_BNDCFGS_RSVD))
1978 vmcs_write64(GUEST_BNDCFGS, data);
1980 case MSR_IA32_UMWAIT_CONTROL:
1981 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1984 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
1985 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
1988 vmx->msr_ia32_umwait_control = data;
1990 case MSR_IA32_SPEC_CTRL:
1991 if (!msr_info->host_initiated &&
1992 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1995 /* The STIBP bit doesn't fault even if it's not advertised */
1996 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
1999 vmx->spec_ctrl = data;
2006 * When it's written (to non-zero) for the first time, pass
2010 * The handling of the MSR bitmap for L2 guests is done in
2011 * nested_vmx_merge_msr_bitmap. We should not touch the
2012 * vmcs02.msr_bitmap here since it gets completely overwritten
2013 * in the merging. We update the vmcs01 here for L1 as well
2014 * since it will end up touching the MSR anyway now.
2016 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2020 case MSR_IA32_TSX_CTRL:
2021 if (!msr_info->host_initiated &&
2022 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2024 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2026 goto find_shared_msr;
2027 case MSR_IA32_PRED_CMD:
2028 if (!msr_info->host_initiated &&
2029 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2032 if (data & ~PRED_CMD_IBPB)
2038 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2042 * When it's written (to non-zero) for the first time, pass
2046 * The handling of the MSR bitmap for L2 guests is done in
2047 * nested_vmx_merge_msr_bitmap. We should not touch the
2048 * vmcs02.msr_bitmap here since it gets completely overwritten
2051 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2054 case MSR_IA32_CR_PAT:
2055 if (!kvm_pat_valid(data))
2058 if (is_guest_mode(vcpu) &&
2059 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2060 get_vmcs12(vcpu)->guest_ia32_pat = data;
2062 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2063 vmcs_write64(GUEST_IA32_PAT, data);
2064 vcpu->arch.pat = data;
2067 ret = kvm_set_msr_common(vcpu, msr_info);
2069 case MSR_IA32_TSC_ADJUST:
2070 ret = kvm_set_msr_common(vcpu, msr_info);
2072 case MSR_IA32_MCG_EXT_CTL:
2073 if ((!msr_info->host_initiated &&
2074 !(to_vmx(vcpu)->msr_ia32_feature_control &
2075 FEATURE_CONTROL_LMCE)) ||
2076 (data & ~MCG_EXT_CTL_LMCE_EN))
2078 vcpu->arch.mcg_ext_ctl = data;
2080 case MSR_IA32_FEATURE_CONTROL:
2081 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2082 (to_vmx(vcpu)->msr_ia32_feature_control &
2083 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2085 vmx->msr_ia32_feature_control = data;
2086 if (msr_info->host_initiated && data == 0)
2087 vmx_leave_nested(vcpu);
2089 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2090 if (!msr_info->host_initiated)
2091 return 1; /* they are read-only */
2092 if (!nested_vmx_allowed(vcpu))
2094 return vmx_set_vmx_msr(vcpu, msr_index, data);
2095 case MSR_IA32_RTIT_CTL:
2096 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2097 vmx_rtit_ctl_check(vcpu, data) ||
2100 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2101 vmx->pt_desc.guest.ctl = data;
2102 pt_update_intercept_for_msr(vmx);
2104 case MSR_IA32_RTIT_STATUS:
2105 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2106 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2107 (data & MSR_IA32_RTIT_STATUS_MASK))
2109 vmx->pt_desc.guest.status = data;
2111 case MSR_IA32_RTIT_CR3_MATCH:
2112 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2113 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2114 !intel_pt_validate_cap(vmx->pt_desc.caps,
2115 PT_CAP_cr3_filtering))
2117 vmx->pt_desc.guest.cr3_match = data;
2119 case MSR_IA32_RTIT_OUTPUT_BASE:
2120 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2121 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2122 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2123 PT_CAP_topa_output) &&
2124 !intel_pt_validate_cap(vmx->pt_desc.caps,
2125 PT_CAP_single_range_output)) ||
2126 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2128 vmx->pt_desc.guest.output_base = data;
2130 case MSR_IA32_RTIT_OUTPUT_MASK:
2131 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2132 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2133 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2134 PT_CAP_topa_output) &&
2135 !intel_pt_validate_cap(vmx->pt_desc.caps,
2136 PT_CAP_single_range_output)))
2138 vmx->pt_desc.guest.output_mask = data;
2140 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2141 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2142 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2143 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2144 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2145 PT_CAP_num_address_ranges)))
2148 vmx->pt_desc.guest.addr_b[index / 2] = data;
2150 vmx->pt_desc.guest.addr_a[index / 2] = data;
2153 if (!msr_info->host_initiated &&
2154 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2156 /* Check reserved bit, higher 32 bits should be zero */
2157 if ((data >> 32) != 0)
2159 goto find_shared_msr;
2163 msr = find_msr_entry(vmx, msr_index);
2165 ret = vmx_set_guest_msr(vmx, msr, data);
2167 ret = kvm_set_msr_common(vcpu, msr_info);
2173 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2175 kvm_register_mark_available(vcpu, reg);
2179 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2182 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2184 case VCPU_EXREG_PDPTR:
2186 ept_save_pdptrs(vcpu);
2188 case VCPU_EXREG_CR3:
2189 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2190 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2198 static __init int cpu_has_kvm_support(void)
2200 return cpu_has_vmx();
2203 static __init int vmx_disabled_by_bios(void)
2207 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2208 if (msr & FEATURE_CONTROL_LOCKED) {
2209 /* launched w/ TXT and VMX disabled */
2210 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2213 /* launched w/o TXT and VMX only enabled w/ TXT */
2214 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2215 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2216 && !tboot_enabled()) {
2217 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2218 "activate TXT before enabling KVM\n");
2221 /* launched w/o TXT and VMX disabled */
2222 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2223 && !tboot_enabled())
2230 static void kvm_cpu_vmxon(u64 addr)
2232 cr4_set_bits(X86_CR4_VMXE);
2233 intel_pt_handle_vmx(1);
2235 asm volatile ("vmxon %0" : : "m"(addr));
2238 static int hardware_enable(void)
2240 int cpu = raw_smp_processor_id();
2241 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2244 if (cr4_read_shadow() & X86_CR4_VMXE)
2248 * This can happen if we hot-added a CPU but failed to allocate
2249 * VP assist page for it.
2251 if (static_branch_unlikely(&enable_evmcs) &&
2252 !hv_get_vp_assist_page(cpu))
2255 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2256 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2257 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2260 * Now we can enable the vmclear operation in kdump
2261 * since the loaded_vmcss_on_cpu list on this cpu
2262 * has been initialized.
2264 * Though the cpu is not in VMX operation now, there
2265 * is no problem to enable the vmclear operation
2266 * for the loaded_vmcss_on_cpu list is empty!
2268 crash_enable_local_vmclear(cpu);
2270 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2272 test_bits = FEATURE_CONTROL_LOCKED;
2273 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2274 if (tboot_enabled())
2275 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2277 if ((old & test_bits) != test_bits) {
2278 /* enable and lock */
2279 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2281 kvm_cpu_vmxon(phys_addr);
2288 static void vmclear_local_loaded_vmcss(void)
2290 int cpu = raw_smp_processor_id();
2291 struct loaded_vmcs *v, *n;
2293 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2294 loaded_vmcss_on_cpu_link)
2295 __loaded_vmcs_clear(v);
2299 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2302 static void kvm_cpu_vmxoff(void)
2304 asm volatile (__ex("vmxoff"));
2306 intel_pt_handle_vmx(0);
2307 cr4_clear_bits(X86_CR4_VMXE);
2310 static void hardware_disable(void)
2312 vmclear_local_loaded_vmcss();
2316 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2317 u32 msr, u32 *result)
2319 u32 vmx_msr_low, vmx_msr_high;
2320 u32 ctl = ctl_min | ctl_opt;
2322 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2324 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2325 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2327 /* Ensure minimum (required) set of control bits are supported. */
2335 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2336 struct vmx_capability *vmx_cap)
2338 u32 vmx_msr_low, vmx_msr_high;
2339 u32 min, opt, min2, opt2;
2340 u32 _pin_based_exec_control = 0;
2341 u32 _cpu_based_exec_control = 0;
2342 u32 _cpu_based_2nd_exec_control = 0;
2343 u32 _vmexit_control = 0;
2344 u32 _vmentry_control = 0;
2346 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2347 min = CPU_BASED_HLT_EXITING |
2348 #ifdef CONFIG_X86_64
2349 CPU_BASED_CR8_LOAD_EXITING |
2350 CPU_BASED_CR8_STORE_EXITING |
2352 CPU_BASED_CR3_LOAD_EXITING |
2353 CPU_BASED_CR3_STORE_EXITING |
2354 CPU_BASED_UNCOND_IO_EXITING |
2355 CPU_BASED_MOV_DR_EXITING |
2356 CPU_BASED_USE_TSC_OFFSETTING |
2357 CPU_BASED_MWAIT_EXITING |
2358 CPU_BASED_MONITOR_EXITING |
2359 CPU_BASED_INVLPG_EXITING |
2360 CPU_BASED_RDPMC_EXITING;
2362 opt = CPU_BASED_TPR_SHADOW |
2363 CPU_BASED_USE_MSR_BITMAPS |
2364 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2365 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2366 &_cpu_based_exec_control) < 0)
2368 #ifdef CONFIG_X86_64
2369 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2370 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2371 ~CPU_BASED_CR8_STORE_EXITING;
2373 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2375 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2376 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2377 SECONDARY_EXEC_WBINVD_EXITING |
2378 SECONDARY_EXEC_ENABLE_VPID |
2379 SECONDARY_EXEC_ENABLE_EPT |
2380 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2381 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2382 SECONDARY_EXEC_DESC |
2383 SECONDARY_EXEC_RDTSCP |
2384 SECONDARY_EXEC_ENABLE_INVPCID |
2385 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2386 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2387 SECONDARY_EXEC_SHADOW_VMCS |
2388 SECONDARY_EXEC_XSAVES |
2389 SECONDARY_EXEC_RDSEED_EXITING |
2390 SECONDARY_EXEC_RDRAND_EXITING |
2391 SECONDARY_EXEC_ENABLE_PML |
2392 SECONDARY_EXEC_TSC_SCALING |
2393 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2394 SECONDARY_EXEC_PT_USE_GPA |
2395 SECONDARY_EXEC_PT_CONCEAL_VMX |
2396 SECONDARY_EXEC_ENABLE_VMFUNC |
2397 SECONDARY_EXEC_ENCLS_EXITING;
2398 if (adjust_vmx_controls(min2, opt2,
2399 MSR_IA32_VMX_PROCBASED_CTLS2,
2400 &_cpu_based_2nd_exec_control) < 0)
2403 #ifndef CONFIG_X86_64
2404 if (!(_cpu_based_2nd_exec_control &
2405 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2406 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2409 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2410 _cpu_based_2nd_exec_control &= ~(
2411 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2412 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2413 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2415 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2416 &vmx_cap->ept, &vmx_cap->vpid);
2418 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2419 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2421 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2422 CPU_BASED_CR3_STORE_EXITING |
2423 CPU_BASED_INVLPG_EXITING);
2424 } else if (vmx_cap->ept) {
2426 pr_warn_once("EPT CAP should not exist if not support "
2427 "1-setting enable EPT VM-execution control\n");
2429 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2432 pr_warn_once("VPID CAP should not exist if not support "
2433 "1-setting enable VPID VM-execution control\n");
2436 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2437 #ifdef CONFIG_X86_64
2438 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2440 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2441 VM_EXIT_LOAD_IA32_PAT |
2442 VM_EXIT_LOAD_IA32_EFER |
2443 VM_EXIT_CLEAR_BNDCFGS |
2444 VM_EXIT_PT_CONCEAL_PIP |
2445 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2446 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2447 &_vmexit_control) < 0)
2450 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2451 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2452 PIN_BASED_VMX_PREEMPTION_TIMER;
2453 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2454 &_pin_based_exec_control) < 0)
2457 if (cpu_has_broken_vmx_preemption_timer())
2458 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2459 if (!(_cpu_based_2nd_exec_control &
2460 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2461 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2463 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2464 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2465 VM_ENTRY_LOAD_IA32_PAT |
2466 VM_ENTRY_LOAD_IA32_EFER |
2467 VM_ENTRY_LOAD_BNDCFGS |
2468 VM_ENTRY_PT_CONCEAL_PIP |
2469 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2470 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2471 &_vmentry_control) < 0)
2475 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2476 * can't be used due to an errata where VM Exit may incorrectly clear
2477 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2478 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2480 if (boot_cpu_data.x86 == 0x6) {
2481 switch (boot_cpu_data.x86_model) {
2482 case 26: /* AAK155 */
2483 case 30: /* AAP115 */
2484 case 37: /* AAT100 */
2485 case 44: /* BC86,AAY89,BD102 */
2487 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2488 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2489 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2490 "does not work properly. Using workaround\n");
2498 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2500 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2501 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2504 #ifdef CONFIG_X86_64
2505 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2506 if (vmx_msr_high & (1u<<16))
2510 /* Require Write-Back (WB) memory type for VMCS accesses. */
2511 if (((vmx_msr_high >> 18) & 15) != 6)
2514 vmcs_conf->size = vmx_msr_high & 0x1fff;
2515 vmcs_conf->order = get_order(vmcs_conf->size);
2516 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2518 vmcs_conf->revision_id = vmx_msr_low;
2520 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2521 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2522 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2523 vmcs_conf->vmexit_ctrl = _vmexit_control;
2524 vmcs_conf->vmentry_ctrl = _vmentry_control;
2526 if (static_branch_unlikely(&enable_evmcs))
2527 evmcs_sanitize_exec_ctrls(vmcs_conf);
2532 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2534 int node = cpu_to_node(cpu);
2538 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2541 vmcs = page_address(pages);
2542 memset(vmcs, 0, vmcs_config.size);
2544 /* KVM supports Enlightened VMCS v1 only */
2545 if (static_branch_unlikely(&enable_evmcs))
2546 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2548 vmcs->hdr.revision_id = vmcs_config.revision_id;
2551 vmcs->hdr.shadow_vmcs = 1;
2555 void free_vmcs(struct vmcs *vmcs)
2557 free_pages((unsigned long)vmcs, vmcs_config.order);
2561 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2563 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2565 if (!loaded_vmcs->vmcs)
2567 loaded_vmcs_clear(loaded_vmcs);
2568 free_vmcs(loaded_vmcs->vmcs);
2569 loaded_vmcs->vmcs = NULL;
2570 if (loaded_vmcs->msr_bitmap)
2571 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2572 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2575 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2577 loaded_vmcs->vmcs = alloc_vmcs(false);
2578 if (!loaded_vmcs->vmcs)
2581 loaded_vmcs->shadow_vmcs = NULL;
2582 loaded_vmcs->hv_timer_soft_disabled = false;
2583 loaded_vmcs_init(loaded_vmcs);
2585 if (cpu_has_vmx_msr_bitmap()) {
2586 loaded_vmcs->msr_bitmap = (unsigned long *)
2587 __get_free_page(GFP_KERNEL_ACCOUNT);
2588 if (!loaded_vmcs->msr_bitmap)
2590 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2592 if (IS_ENABLED(CONFIG_HYPERV) &&
2593 static_branch_unlikely(&enable_evmcs) &&
2594 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2595 struct hv_enlightened_vmcs *evmcs =
2596 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2598 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2602 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2603 memset(&loaded_vmcs->controls_shadow, 0,
2604 sizeof(struct vmcs_controls_shadow));
2609 free_loaded_vmcs(loaded_vmcs);
2613 static void free_kvm_area(void)
2617 for_each_possible_cpu(cpu) {
2618 free_vmcs(per_cpu(vmxarea, cpu));
2619 per_cpu(vmxarea, cpu) = NULL;
2623 static __init int alloc_kvm_area(void)
2627 for_each_possible_cpu(cpu) {
2630 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2637 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2638 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2639 * revision_id reported by MSR_IA32_VMX_BASIC.
2641 * However, even though not explicitly documented by
2642 * TLFS, VMXArea passed as VMXON argument should
2643 * still be marked with revision_id reported by
2646 if (static_branch_unlikely(&enable_evmcs))
2647 vmcs->hdr.revision_id = vmcs_config.revision_id;
2649 per_cpu(vmxarea, cpu) = vmcs;
2654 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2655 struct kvm_segment *save)
2657 if (!emulate_invalid_guest_state) {
2659 * CS and SS RPL should be equal during guest entry according
2660 * to VMX spec, but in reality it is not always so. Since vcpu
2661 * is in the middle of the transition from real mode to
2662 * protected mode it is safe to assume that RPL 0 is a good
2665 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2666 save->selector &= ~SEGMENT_RPL_MASK;
2667 save->dpl = save->selector & SEGMENT_RPL_MASK;
2670 vmx_set_segment(vcpu, save, seg);
2673 static void enter_pmode(struct kvm_vcpu *vcpu)
2675 unsigned long flags;
2676 struct vcpu_vmx *vmx = to_vmx(vcpu);
2679 * Update real mode segment cache. It may be not up-to-date if sement
2680 * register was written while vcpu was in a guest mode.
2682 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2683 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2684 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2685 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2686 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2687 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2689 vmx->rmode.vm86_active = 0;
2691 vmx_segment_cache_clear(vmx);
2693 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2695 flags = vmcs_readl(GUEST_RFLAGS);
2696 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2697 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2698 vmcs_writel(GUEST_RFLAGS, flags);
2700 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2701 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2703 update_exception_bitmap(vcpu);
2705 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2706 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2707 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2708 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2709 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2710 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2713 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2715 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2716 struct kvm_segment var = *save;
2719 if (seg == VCPU_SREG_CS)
2722 if (!emulate_invalid_guest_state) {
2723 var.selector = var.base >> 4;
2724 var.base = var.base & 0xffff0;
2734 if (save->base & 0xf)
2735 printk_once(KERN_WARNING "kvm: segment base is not "
2736 "paragraph aligned when entering "
2737 "protected mode (seg=%d)", seg);
2740 vmcs_write16(sf->selector, var.selector);
2741 vmcs_writel(sf->base, var.base);
2742 vmcs_write32(sf->limit, var.limit);
2743 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2746 static void enter_rmode(struct kvm_vcpu *vcpu)
2748 unsigned long flags;
2749 struct vcpu_vmx *vmx = to_vmx(vcpu);
2750 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2752 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2753 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2754 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2755 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2756 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2757 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2758 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2760 vmx->rmode.vm86_active = 1;
2763 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2764 * vcpu. Warn the user that an update is overdue.
2766 if (!kvm_vmx->tss_addr)
2767 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2768 "called before entering vcpu\n");
2770 vmx_segment_cache_clear(vmx);
2772 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2773 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2774 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2776 flags = vmcs_readl(GUEST_RFLAGS);
2777 vmx->rmode.save_rflags = flags;
2779 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2781 vmcs_writel(GUEST_RFLAGS, flags);
2782 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2783 update_exception_bitmap(vcpu);
2785 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2786 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2787 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2788 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2789 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2790 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2792 kvm_mmu_reset_context(vcpu);
2795 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2797 struct vcpu_vmx *vmx = to_vmx(vcpu);
2798 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2803 vcpu->arch.efer = efer;
2804 if (efer & EFER_LMA) {
2805 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2808 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2810 msr->data = efer & ~EFER_LME;
2815 #ifdef CONFIG_X86_64
2817 static void enter_lmode(struct kvm_vcpu *vcpu)
2821 vmx_segment_cache_clear(to_vmx(vcpu));
2823 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2824 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2825 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2827 vmcs_write32(GUEST_TR_AR_BYTES,
2828 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2829 | VMX_AR_TYPE_BUSY_64_TSS);
2831 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2834 static void exit_lmode(struct kvm_vcpu *vcpu)
2836 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2837 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2842 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2844 int vpid = to_vmx(vcpu)->vpid;
2846 if (!vpid_sync_vcpu_addr(vpid, addr))
2847 vpid_sync_context(vpid);
2850 * If VPIDs are not supported or enabled, then the above is a no-op.
2851 * But we don't really need a TLB flush in that case anyway, because
2852 * each VM entry/exit includes an implicit flush when VPID is 0.
2856 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2858 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2860 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2861 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2864 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2866 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2868 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2869 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2872 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2874 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2876 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2879 if (is_pae_paging(vcpu)) {
2880 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2881 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2882 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2883 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2887 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2889 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2891 if (is_pae_paging(vcpu)) {
2892 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2893 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2894 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2895 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2898 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2901 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2903 struct kvm_vcpu *vcpu)
2905 struct vcpu_vmx *vmx = to_vmx(vcpu);
2907 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2908 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2909 if (!(cr0 & X86_CR0_PG)) {
2910 /* From paging/starting to nonpaging */
2911 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2912 CPU_BASED_CR3_STORE_EXITING);
2913 vcpu->arch.cr0 = cr0;
2914 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2915 } else if (!is_paging(vcpu)) {
2916 /* From nonpaging to paging */
2917 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2918 CPU_BASED_CR3_STORE_EXITING);
2919 vcpu->arch.cr0 = cr0;
2920 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2923 if (!(cr0 & X86_CR0_WP))
2924 *hw_cr0 &= ~X86_CR0_WP;
2927 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2929 struct vcpu_vmx *vmx = to_vmx(vcpu);
2930 unsigned long hw_cr0;
2932 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2933 if (enable_unrestricted_guest)
2934 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2936 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2938 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2941 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2945 #ifdef CONFIG_X86_64
2946 if (vcpu->arch.efer & EFER_LME) {
2947 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2949 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2954 if (enable_ept && !enable_unrestricted_guest)
2955 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2957 vmcs_writel(CR0_READ_SHADOW, cr0);
2958 vmcs_writel(GUEST_CR0, hw_cr0);
2959 vcpu->arch.cr0 = cr0;
2961 /* depends on vcpu->arch.cr0 to be set to a new value */
2962 vmx->emulation_required = emulation_required(vcpu);
2965 static int get_ept_level(struct kvm_vcpu *vcpu)
2967 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2972 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2974 u64 eptp = VMX_EPTP_MT_WB;
2976 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2978 if (enable_ept_ad_bits &&
2979 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2980 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2981 eptp |= (root_hpa & PAGE_MASK);
2986 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2988 struct kvm *kvm = vcpu->kvm;
2989 bool update_guest_cr3 = true;
2990 unsigned long guest_cr3;
2995 eptp = construct_eptp(vcpu, cr3);
2996 vmcs_write64(EPT_POINTER, eptp);
2998 if (kvm_x86_ops->tlb_remote_flush) {
2999 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3000 to_vmx(vcpu)->ept_pointer = eptp;
3001 to_kvm_vmx(kvm)->ept_pointers_match
3002 = EPT_POINTERS_CHECK;
3003 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3006 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3007 if (is_guest_mode(vcpu))
3008 update_guest_cr3 = false;
3009 else if (!enable_unrestricted_guest && !is_paging(vcpu))
3010 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3011 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3012 guest_cr3 = vcpu->arch.cr3;
3013 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3014 update_guest_cr3 = false;
3015 ept_load_pdptrs(vcpu);
3018 if (update_guest_cr3)
3019 vmcs_writel(GUEST_CR3, guest_cr3);
3022 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3024 struct vcpu_vmx *vmx = to_vmx(vcpu);
3026 * Pass through host's Machine Check Enable value to hw_cr4, which
3027 * is in force while we are in guest mode. Do not let guests control
3028 * this bit, even if host CR4.MCE == 0.
3030 unsigned long hw_cr4;
3032 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3033 if (enable_unrestricted_guest)
3034 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3035 else if (vmx->rmode.vm86_active)
3036 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3038 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3040 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3041 if (cr4 & X86_CR4_UMIP) {
3042 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3043 hw_cr4 &= ~X86_CR4_UMIP;
3044 } else if (!is_guest_mode(vcpu) ||
3045 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3046 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3050 if (cr4 & X86_CR4_VMXE) {
3052 * To use VMXON (and later other VMX instructions), a guest
3053 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3054 * So basically the check on whether to allow nested VMX
3055 * is here. We operate under the default treatment of SMM,
3056 * so VMX cannot be enabled under SMM.
3058 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3062 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3065 vcpu->arch.cr4 = cr4;
3067 if (!enable_unrestricted_guest) {
3069 if (!is_paging(vcpu)) {
3070 hw_cr4 &= ~X86_CR4_PAE;
3071 hw_cr4 |= X86_CR4_PSE;
3072 } else if (!(cr4 & X86_CR4_PAE)) {
3073 hw_cr4 &= ~X86_CR4_PAE;
3078 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3079 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3080 * to be manually disabled when guest switches to non-paging
3083 * If !enable_unrestricted_guest, the CPU is always running
3084 * with CR0.PG=1 and CR4 needs to be modified.
3085 * If enable_unrestricted_guest, the CPU automatically
3086 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3088 if (!is_paging(vcpu))
3089 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3092 vmcs_writel(CR4_READ_SHADOW, cr4);
3093 vmcs_writel(GUEST_CR4, hw_cr4);
3097 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3099 struct vcpu_vmx *vmx = to_vmx(vcpu);
3102 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3103 *var = vmx->rmode.segs[seg];
3104 if (seg == VCPU_SREG_TR
3105 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3107 var->base = vmx_read_guest_seg_base(vmx, seg);
3108 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3111 var->base = vmx_read_guest_seg_base(vmx, seg);
3112 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3113 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3114 ar = vmx_read_guest_seg_ar(vmx, seg);
3115 var->unusable = (ar >> 16) & 1;
3116 var->type = ar & 15;
3117 var->s = (ar >> 4) & 1;
3118 var->dpl = (ar >> 5) & 3;
3120 * Some userspaces do not preserve unusable property. Since usable
3121 * segment has to be present according to VMX spec we can use present
3122 * property to amend userspace bug by making unusable segment always
3123 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3124 * segment as unusable.
3126 var->present = !var->unusable;
3127 var->avl = (ar >> 12) & 1;
3128 var->l = (ar >> 13) & 1;
3129 var->db = (ar >> 14) & 1;
3130 var->g = (ar >> 15) & 1;
3133 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3135 struct kvm_segment s;
3137 if (to_vmx(vcpu)->rmode.vm86_active) {
3138 vmx_get_segment(vcpu, &s, seg);
3141 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3144 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3146 struct vcpu_vmx *vmx = to_vmx(vcpu);
3148 if (unlikely(vmx->rmode.vm86_active))
3151 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3152 return VMX_AR_DPL(ar);
3156 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3160 if (var->unusable || !var->present)
3163 ar = var->type & 15;
3164 ar |= (var->s & 1) << 4;
3165 ar |= (var->dpl & 3) << 5;
3166 ar |= (var->present & 1) << 7;
3167 ar |= (var->avl & 1) << 12;
3168 ar |= (var->l & 1) << 13;
3169 ar |= (var->db & 1) << 14;
3170 ar |= (var->g & 1) << 15;
3176 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3178 struct vcpu_vmx *vmx = to_vmx(vcpu);
3179 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3181 vmx_segment_cache_clear(vmx);
3183 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3184 vmx->rmode.segs[seg] = *var;
3185 if (seg == VCPU_SREG_TR)
3186 vmcs_write16(sf->selector, var->selector);
3188 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3192 vmcs_writel(sf->base, var->base);
3193 vmcs_write32(sf->limit, var->limit);
3194 vmcs_write16(sf->selector, var->selector);
3197 * Fix the "Accessed" bit in AR field of segment registers for older
3199 * IA32 arch specifies that at the time of processor reset the
3200 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3201 * is setting it to 0 in the userland code. This causes invalid guest
3202 * state vmexit when "unrestricted guest" mode is turned on.
3203 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3204 * tree. Newer qemu binaries with that qemu fix would not need this
3207 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3208 var->type |= 0x1; /* Accessed */
3210 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3213 vmx->emulation_required = emulation_required(vcpu);
3216 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3218 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3220 *db = (ar >> 14) & 1;
3221 *l = (ar >> 13) & 1;
3224 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3226 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3227 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3230 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3232 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3233 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3236 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3238 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3239 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3242 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3244 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3245 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3248 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3250 struct kvm_segment var;
3253 vmx_get_segment(vcpu, &var, seg);
3255 if (seg == VCPU_SREG_CS)
3257 ar = vmx_segment_access_rights(&var);
3259 if (var.base != (var.selector << 4))
3261 if (var.limit != 0xffff)
3269 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3271 struct kvm_segment cs;
3272 unsigned int cs_rpl;
3274 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3275 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3279 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3283 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3284 if (cs.dpl > cs_rpl)
3287 if (cs.dpl != cs_rpl)
3293 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3297 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3299 struct kvm_segment ss;
3300 unsigned int ss_rpl;
3302 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3303 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3307 if (ss.type != 3 && ss.type != 7)
3311 if (ss.dpl != ss_rpl) /* DPL != RPL */
3319 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3321 struct kvm_segment var;
3324 vmx_get_segment(vcpu, &var, seg);
3325 rpl = var.selector & SEGMENT_RPL_MASK;
3333 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3334 if (var.dpl < rpl) /* DPL < RPL */
3338 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3344 static bool tr_valid(struct kvm_vcpu *vcpu)
3346 struct kvm_segment tr;
3348 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3352 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3354 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3362 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3364 struct kvm_segment ldtr;
3366 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3370 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3380 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3382 struct kvm_segment cs, ss;
3384 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3385 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3387 return ((cs.selector & SEGMENT_RPL_MASK) ==
3388 (ss.selector & SEGMENT_RPL_MASK));
3392 * Check if guest state is valid. Returns true if valid, false if
3394 * We assume that registers are always usable
3396 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3398 if (enable_unrestricted_guest)
3401 /* real mode guest state checks */
3402 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3403 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3405 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3407 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3409 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3411 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3413 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3416 /* protected mode guest state checks */
3417 if (!cs_ss_rpl_check(vcpu))
3419 if (!code_segment_valid(vcpu))
3421 if (!stack_segment_valid(vcpu))
3423 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3425 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3427 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3429 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3431 if (!tr_valid(vcpu))
3433 if (!ldtr_valid(vcpu))
3437 * - Add checks on RIP
3438 * - Add checks on RFLAGS
3444 static int init_rmode_tss(struct kvm *kvm)
3450 idx = srcu_read_lock(&kvm->srcu);
3451 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3452 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3455 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3456 r = kvm_write_guest_page(kvm, fn++, &data,
3457 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3460 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3463 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3467 r = kvm_write_guest_page(kvm, fn, &data,
3468 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3471 srcu_read_unlock(&kvm->srcu, idx);
3475 static int init_rmode_identity_map(struct kvm *kvm)
3477 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3479 kvm_pfn_t identity_map_pfn;
3482 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3483 mutex_lock(&kvm->slots_lock);
3485 if (likely(kvm_vmx->ept_identity_pagetable_done))
3488 if (!kvm_vmx->ept_identity_map_addr)
3489 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3490 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3492 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3493 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3497 idx = srcu_read_lock(&kvm->srcu);
3498 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3501 /* Set up identity-mapping pagetable for EPT in real mode */
3502 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3503 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3504 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3505 r = kvm_write_guest_page(kvm, identity_map_pfn,
3506 &tmp, i * sizeof(tmp), sizeof(tmp));
3510 kvm_vmx->ept_identity_pagetable_done = true;
3513 srcu_read_unlock(&kvm->srcu, idx);
3516 mutex_unlock(&kvm->slots_lock);
3520 static void seg_setup(int seg)
3522 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3525 vmcs_write16(sf->selector, 0);
3526 vmcs_writel(sf->base, 0);
3527 vmcs_write32(sf->limit, 0xffff);
3529 if (seg == VCPU_SREG_CS)
3530 ar |= 0x08; /* code segment */
3532 vmcs_write32(sf->ar_bytes, ar);
3535 static int alloc_apic_access_page(struct kvm *kvm)
3540 mutex_lock(&kvm->slots_lock);
3541 if (kvm->arch.apic_access_page_done)
3543 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3544 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3548 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3549 if (is_error_page(page)) {
3555 * Do not pin the page in memory, so that memory hot-unplug
3556 * is able to migrate it.
3559 kvm->arch.apic_access_page_done = true;
3561 mutex_unlock(&kvm->slots_lock);
3565 int allocate_vpid(void)
3571 spin_lock(&vmx_vpid_lock);
3572 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3573 if (vpid < VMX_NR_VPIDS)
3574 __set_bit(vpid, vmx_vpid_bitmap);
3577 spin_unlock(&vmx_vpid_lock);
3581 void free_vpid(int vpid)
3583 if (!enable_vpid || vpid == 0)
3585 spin_lock(&vmx_vpid_lock);
3586 __clear_bit(vpid, vmx_vpid_bitmap);
3587 spin_unlock(&vmx_vpid_lock);
3590 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3593 int f = sizeof(unsigned long);
3595 if (!cpu_has_vmx_msr_bitmap())
3598 if (static_branch_unlikely(&enable_evmcs))
3599 evmcs_touch_msr_bitmap();
3602 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3603 * have the write-low and read-high bitmap offsets the wrong way round.
3604 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3606 if (msr <= 0x1fff) {
3607 if (type & MSR_TYPE_R)
3609 __clear_bit(msr, msr_bitmap + 0x000 / f);
3611 if (type & MSR_TYPE_W)
3613 __clear_bit(msr, msr_bitmap + 0x800 / f);
3615 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3617 if (type & MSR_TYPE_R)
3619 __clear_bit(msr, msr_bitmap + 0x400 / f);
3621 if (type & MSR_TYPE_W)
3623 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3628 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3631 int f = sizeof(unsigned long);
3633 if (!cpu_has_vmx_msr_bitmap())
3636 if (static_branch_unlikely(&enable_evmcs))
3637 evmcs_touch_msr_bitmap();
3640 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3641 * have the write-low and read-high bitmap offsets the wrong way round.
3642 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3644 if (msr <= 0x1fff) {
3645 if (type & MSR_TYPE_R)
3647 __set_bit(msr, msr_bitmap + 0x000 / f);
3649 if (type & MSR_TYPE_W)
3651 __set_bit(msr, msr_bitmap + 0x800 / f);
3653 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3655 if (type & MSR_TYPE_R)
3657 __set_bit(msr, msr_bitmap + 0x400 / f);
3659 if (type & MSR_TYPE_W)
3661 __set_bit(msr, msr_bitmap + 0xc00 / f);
3666 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3667 u32 msr, int type, bool value)
3670 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3672 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3675 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3679 if (cpu_has_secondary_exec_ctrls() &&
3680 (secondary_exec_controls_get(to_vmx(vcpu)) &
3681 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3682 mode |= MSR_BITMAP_MODE_X2APIC;
3683 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3684 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3690 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3695 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3696 unsigned word = msr / BITS_PER_LONG;
3697 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3698 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3701 if (mode & MSR_BITMAP_MODE_X2APIC) {
3703 * TPR reads and writes can be virtualized even if virtual interrupt
3704 * delivery is not in use.
3706 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3707 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3708 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3709 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3710 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3715 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3717 struct vcpu_vmx *vmx = to_vmx(vcpu);
3718 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3719 u8 mode = vmx_msr_bitmap_mode(vcpu);
3720 u8 changed = mode ^ vmx->msr_bitmap_mode;
3725 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3726 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3728 vmx->msr_bitmap_mode = mode;
3731 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3733 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3734 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3737 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3739 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3741 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3743 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3745 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3746 vmx_set_intercept_for_msr(msr_bitmap,
3747 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3748 vmx_set_intercept_for_msr(msr_bitmap,
3749 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3753 static bool vmx_get_enable_apicv(struct kvm *kvm)
3755 return enable_apicv;
3758 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3760 struct vcpu_vmx *vmx = to_vmx(vcpu);
3765 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3766 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3767 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3770 rvi = vmx_get_rvi();
3772 vapic_page = vmx->nested.virtual_apic_map.hva;
3773 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3775 return ((rvi & 0xf0) > (vppr & 0xf0));
3778 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3782 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3784 if (vcpu->mode == IN_GUEST_MODE) {
3786 * The vector of interrupt to be delivered to vcpu had
3787 * been set in PIR before this function.
3789 * Following cases will be reached in this block, and
3790 * we always send a notification event in all cases as
3793 * Case 1: vcpu keeps in non-root mode. Sending a
3794 * notification event posts the interrupt to vcpu.
3796 * Case 2: vcpu exits to root mode and is still
3797 * runnable. PIR will be synced to vIRR before the
3798 * next vcpu entry. Sending a notification event in
3799 * this case has no effect, as vcpu is not in root
3802 * Case 3: vcpu exits to root mode and is blocked.
3803 * vcpu_block() has already synced PIR to vIRR and
3804 * never blocks vcpu if vIRR is not cleared. Therefore,
3805 * a blocked vcpu here does not wait for any requested
3806 * interrupts in PIR, and sending a notification event
3807 * which has no effect is safe here.
3810 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3817 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3820 struct vcpu_vmx *vmx = to_vmx(vcpu);
3822 if (is_guest_mode(vcpu) &&
3823 vector == vmx->nested.posted_intr_nv) {
3825 * If a posted intr is not recognized by hardware,
3826 * we will accomplish it in the next vmentry.
3828 vmx->nested.pi_pending = true;
3829 kvm_make_request(KVM_REQ_EVENT, vcpu);
3830 /* the PIR and ON have been set by L1. */
3831 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3832 kvm_vcpu_kick(vcpu);
3838 * Send interrupt to vcpu via posted interrupt way.
3839 * 1. If target vcpu is running(non-root mode), send posted interrupt
3840 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3841 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3842 * interrupt from PIR in next vmentry.
3844 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3846 struct vcpu_vmx *vmx = to_vmx(vcpu);
3849 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3853 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3856 /* If a previous notification has sent the IPI, nothing to do. */
3857 if (pi_test_and_set_on(&vmx->pi_desc))
3860 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3861 kvm_vcpu_kick(vcpu);
3865 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3866 * will not change in the lifetime of the guest.
3867 * Note that host-state that does change is set elsewhere. E.g., host-state
3868 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3870 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3874 unsigned long cr0, cr3, cr4;
3877 WARN_ON(cr0 & X86_CR0_TS);
3878 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3881 * Save the most likely value for this task's CR3 in the VMCS.
3882 * We can't use __get_current_cr3_fast() because we're not atomic.
3885 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
3886 vmx->loaded_vmcs->host_state.cr3 = cr3;
3888 /* Save the most likely value for this task's CR4 in the VMCS. */
3889 cr4 = cr4_read_shadow();
3890 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
3891 vmx->loaded_vmcs->host_state.cr4 = cr4;
3893 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3894 #ifdef CONFIG_X86_64
3896 * Load null selectors, so we can avoid reloading them in
3897 * vmx_prepare_switch_to_host(), in case userspace uses
3898 * the null selectors too (the expected case).
3900 vmcs_write16(HOST_DS_SELECTOR, 0);
3901 vmcs_write16(HOST_ES_SELECTOR, 0);
3903 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3904 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3906 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3907 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3909 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
3911 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3913 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3914 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3915 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3916 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3918 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3919 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3920 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3923 if (cpu_has_load_ia32_efer())
3924 vmcs_write64(HOST_IA32_EFER, host_efer);
3927 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3929 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3931 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3932 if (is_guest_mode(&vmx->vcpu))
3933 vmx->vcpu.arch.cr4_guest_owned_bits &=
3934 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3935 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3938 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3940 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3942 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3943 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3946 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3948 if (!enable_preemption_timer)
3949 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3951 return pin_based_exec_ctrl;
3954 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3956 struct vcpu_vmx *vmx = to_vmx(vcpu);
3958 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3959 if (cpu_has_secondary_exec_ctrls()) {
3960 if (kvm_vcpu_apicv_active(vcpu))
3961 secondary_exec_controls_setbit(vmx,
3962 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3963 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3965 secondary_exec_controls_clearbit(vmx,
3966 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3967 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3970 if (cpu_has_vmx_msr_bitmap())
3971 vmx_update_msr_bitmap(vcpu);
3974 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3976 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3978 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3979 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3981 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3982 exec_control &= ~CPU_BASED_TPR_SHADOW;
3983 #ifdef CONFIG_X86_64
3984 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3985 CPU_BASED_CR8_LOAD_EXITING;
3989 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3990 CPU_BASED_CR3_LOAD_EXITING |
3991 CPU_BASED_INVLPG_EXITING;
3992 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3993 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3994 CPU_BASED_MONITOR_EXITING);
3995 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3996 exec_control &= ~CPU_BASED_HLT_EXITING;
3997 return exec_control;
4001 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4003 struct kvm_vcpu *vcpu = &vmx->vcpu;
4005 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4007 if (pt_mode == PT_MODE_SYSTEM)
4008 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4009 if (!cpu_need_virtualize_apic_accesses(vcpu))
4010 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4012 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4014 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4015 enable_unrestricted_guest = 0;
4017 if (!enable_unrestricted_guest)
4018 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4019 if (kvm_pause_in_guest(vmx->vcpu.kvm))
4020 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4021 if (!kvm_vcpu_apicv_active(vcpu))
4022 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4023 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4024 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4026 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4027 * in vmx_set_cr4. */
4028 exec_control &= ~SECONDARY_EXEC_DESC;
4030 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4032 We can NOT enable shadow_vmcs here because we don't have yet
4035 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4038 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4040 if (vmx_xsaves_supported()) {
4041 /* Exposing XSAVES only when XSAVE is exposed */
4042 bool xsaves_enabled =
4043 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4044 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4046 vcpu->arch.xsaves_enabled = xsaves_enabled;
4048 if (!xsaves_enabled)
4049 exec_control &= ~SECONDARY_EXEC_XSAVES;
4053 vmx->nested.msrs.secondary_ctls_high |=
4054 SECONDARY_EXEC_XSAVES;
4056 vmx->nested.msrs.secondary_ctls_high &=
4057 ~SECONDARY_EXEC_XSAVES;
4061 if (vmx_rdtscp_supported()) {
4062 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4063 if (!rdtscp_enabled)
4064 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4068 vmx->nested.msrs.secondary_ctls_high |=
4069 SECONDARY_EXEC_RDTSCP;
4071 vmx->nested.msrs.secondary_ctls_high &=
4072 ~SECONDARY_EXEC_RDTSCP;
4076 if (vmx_invpcid_supported()) {
4077 /* Exposing INVPCID only when PCID is exposed */
4078 bool invpcid_enabled =
4079 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4080 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4082 if (!invpcid_enabled) {
4083 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4084 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4088 if (invpcid_enabled)
4089 vmx->nested.msrs.secondary_ctls_high |=
4090 SECONDARY_EXEC_ENABLE_INVPCID;
4092 vmx->nested.msrs.secondary_ctls_high &=
4093 ~SECONDARY_EXEC_ENABLE_INVPCID;
4097 if (vmx_rdrand_supported()) {
4098 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4100 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4104 vmx->nested.msrs.secondary_ctls_high |=
4105 SECONDARY_EXEC_RDRAND_EXITING;
4107 vmx->nested.msrs.secondary_ctls_high &=
4108 ~SECONDARY_EXEC_RDRAND_EXITING;
4112 if (vmx_rdseed_supported()) {
4113 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4115 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4119 vmx->nested.msrs.secondary_ctls_high |=
4120 SECONDARY_EXEC_RDSEED_EXITING;
4122 vmx->nested.msrs.secondary_ctls_high &=
4123 ~SECONDARY_EXEC_RDSEED_EXITING;
4127 if (vmx_waitpkg_supported()) {
4128 bool waitpkg_enabled =
4129 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4131 if (!waitpkg_enabled)
4132 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4135 if (waitpkg_enabled)
4136 vmx->nested.msrs.secondary_ctls_high |=
4137 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4139 vmx->nested.msrs.secondary_ctls_high &=
4140 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4144 vmx->secondary_exec_control = exec_control;
4147 static void ept_set_mmio_spte_mask(void)
4150 * EPT Misconfigurations can be generated if the value of bits 2:0
4151 * of an EPT paging-structure entry is 110b (write/execute).
4153 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4154 VMX_EPT_MISCONFIG_WX_VALUE, 0);
4157 #define VMX_XSS_EXIT_BITMAP 0
4160 * Noting that the initialization of Guest-state Area of VMCS is in
4163 static void init_vmcs(struct vcpu_vmx *vmx)
4166 nested_vmx_set_vmcs_shadowing_bitmap();
4168 if (cpu_has_vmx_msr_bitmap())
4169 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4171 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4174 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4176 exec_controls_set(vmx, vmx_exec_control(vmx));
4178 if (cpu_has_secondary_exec_ctrls()) {
4179 vmx_compute_secondary_exec_control(vmx);
4180 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4183 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4184 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4185 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4186 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4187 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4189 vmcs_write16(GUEST_INTR_STATUS, 0);
4191 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4192 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4195 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4196 vmcs_write32(PLE_GAP, ple_gap);
4197 vmx->ple_window = ple_window;
4198 vmx->ple_window_dirty = true;
4201 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4202 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4203 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4205 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4206 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4207 vmx_set_constant_host_state(vmx);
4208 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4209 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4211 if (cpu_has_vmx_vmfunc())
4212 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4214 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4215 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4216 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4217 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4218 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4220 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4221 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4223 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4225 /* 22.2.1, 20.8.1 */
4226 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4228 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4229 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4231 set_cr4_guest_host_mask(vmx);
4234 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4236 if (vmx_xsaves_supported())
4237 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4240 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4241 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4244 if (cpu_has_vmx_encls_vmexit())
4245 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4247 if (pt_mode == PT_MODE_HOST_GUEST) {
4248 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4249 /* Bit[6~0] are forced to 1, writes are ignored. */
4250 vmx->pt_desc.guest.output_mask = 0x7F;
4251 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4255 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4257 struct vcpu_vmx *vmx = to_vmx(vcpu);
4258 struct msr_data apic_base_msr;
4261 vmx->rmode.vm86_active = 0;
4264 vmx->msr_ia32_umwait_control = 0;
4266 vcpu->arch.microcode_version = 0x100000000ULL;
4267 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4268 vmx->hv_deadline_tsc = -1;
4269 kvm_set_cr8(vcpu, 0);
4272 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4273 MSR_IA32_APICBASE_ENABLE;
4274 if (kvm_vcpu_is_reset_bsp(vcpu))
4275 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4276 apic_base_msr.host_initiated = true;
4277 kvm_set_apic_base(vcpu, &apic_base_msr);
4280 vmx_segment_cache_clear(vmx);
4282 seg_setup(VCPU_SREG_CS);
4283 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4284 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4286 seg_setup(VCPU_SREG_DS);
4287 seg_setup(VCPU_SREG_ES);
4288 seg_setup(VCPU_SREG_FS);
4289 seg_setup(VCPU_SREG_GS);
4290 seg_setup(VCPU_SREG_SS);
4292 vmcs_write16(GUEST_TR_SELECTOR, 0);
4293 vmcs_writel(GUEST_TR_BASE, 0);
4294 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4295 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4297 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4298 vmcs_writel(GUEST_LDTR_BASE, 0);
4299 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4300 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4303 vmcs_write32(GUEST_SYSENTER_CS, 0);
4304 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4305 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4306 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4309 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4310 kvm_rip_write(vcpu, 0xfff0);
4312 vmcs_writel(GUEST_GDTR_BASE, 0);
4313 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4315 vmcs_writel(GUEST_IDTR_BASE, 0);
4316 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4318 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4319 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4320 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4321 if (kvm_mpx_supported())
4322 vmcs_write64(GUEST_BNDCFGS, 0);
4326 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4328 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4329 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4330 if (cpu_need_tpr_shadow(vcpu))
4331 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4332 __pa(vcpu->arch.apic->regs));
4333 vmcs_write32(TPR_THRESHOLD, 0);
4336 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4338 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4339 vmx->vcpu.arch.cr0 = cr0;
4340 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4341 vmx_set_cr4(vcpu, 0);
4342 vmx_set_efer(vcpu, 0);
4344 update_exception_bitmap(vcpu);
4346 vpid_sync_context(vmx->vpid);
4348 vmx_clear_hlt(vcpu);
4351 static void enable_irq_window(struct kvm_vcpu *vcpu)
4353 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4356 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4359 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4360 enable_irq_window(vcpu);
4364 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4367 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4369 struct vcpu_vmx *vmx = to_vmx(vcpu);
4371 int irq = vcpu->arch.interrupt.nr;
4373 trace_kvm_inj_virq(irq);
4375 ++vcpu->stat.irq_injections;
4376 if (vmx->rmode.vm86_active) {
4378 if (vcpu->arch.interrupt.soft)
4379 inc_eip = vcpu->arch.event_exit_inst_len;
4380 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4383 intr = irq | INTR_INFO_VALID_MASK;
4384 if (vcpu->arch.interrupt.soft) {
4385 intr |= INTR_TYPE_SOFT_INTR;
4386 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4387 vmx->vcpu.arch.event_exit_inst_len);
4389 intr |= INTR_TYPE_EXT_INTR;
4390 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4392 vmx_clear_hlt(vcpu);
4395 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4397 struct vcpu_vmx *vmx = to_vmx(vcpu);
4401 * Tracking the NMI-blocked state in software is built upon
4402 * finding the next open IRQ window. This, in turn, depends on
4403 * well-behaving guests: They have to keep IRQs disabled at
4404 * least as long as the NMI handler runs. Otherwise we may
4405 * cause NMI nesting, maybe breaking the guest. But as this is
4406 * highly unlikely, we can live with the residual risk.
4408 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4409 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4412 ++vcpu->stat.nmi_injections;
4413 vmx->loaded_vmcs->nmi_known_unmasked = false;
4415 if (vmx->rmode.vm86_active) {
4416 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4420 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4421 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4423 vmx_clear_hlt(vcpu);
4426 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4428 struct vcpu_vmx *vmx = to_vmx(vcpu);
4432 return vmx->loaded_vmcs->soft_vnmi_blocked;
4433 if (vmx->loaded_vmcs->nmi_known_unmasked)
4435 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4436 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4440 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4442 struct vcpu_vmx *vmx = to_vmx(vcpu);
4445 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4446 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4447 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4450 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4452 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4453 GUEST_INTR_STATE_NMI);
4455 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4456 GUEST_INTR_STATE_NMI);
4460 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4462 if (to_vmx(vcpu)->nested.nested_run_pending)
4466 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4469 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4470 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4471 | GUEST_INTR_STATE_NMI));
4474 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4476 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4477 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4478 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4479 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4482 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4486 if (enable_unrestricted_guest)
4489 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4493 to_kvm_vmx(kvm)->tss_addr = addr;
4494 return init_rmode_tss(kvm);
4497 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4499 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4503 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4508 * Update instruction length as we may reinject the exception
4509 * from user space while in guest debugging mode.
4511 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4512 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4513 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4517 if (vcpu->guest_debug &
4518 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4535 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4536 int vec, u32 err_code)
4539 * Instruction with address size override prefix opcode 0x67
4540 * Cause the #SS fault with 0 error code in VM86 mode.
4542 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4543 if (kvm_emulate_instruction(vcpu, 0)) {
4544 if (vcpu->arch.halt_request) {
4545 vcpu->arch.halt_request = 0;
4546 return kvm_vcpu_halt(vcpu);
4554 * Forward all other exceptions that are valid in real mode.
4555 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4556 * the required debugging infrastructure rework.
4558 kvm_queue_exception(vcpu, vec);
4563 * Trigger machine check on the host. We assume all the MSRs are already set up
4564 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4565 * We pass a fake environment to the machine check handler because we want
4566 * the guest to be always treated like user space, no matter what context
4567 * it used internally.
4569 static void kvm_machine_check(void)
4571 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4572 struct pt_regs regs = {
4573 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4574 .flags = X86_EFLAGS_IF,
4577 do_machine_check(®s, 0);
4581 static int handle_machine_check(struct kvm_vcpu *vcpu)
4583 /* handled by vmx_vcpu_run() */
4587 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4589 struct vcpu_vmx *vmx = to_vmx(vcpu);
4590 struct kvm_run *kvm_run = vcpu->run;
4591 u32 intr_info, ex_no, error_code;
4592 unsigned long cr2, rip, dr6;
4595 vect_info = vmx->idt_vectoring_info;
4596 intr_info = vmx->exit_intr_info;
4598 if (is_machine_check(intr_info) || is_nmi(intr_info))
4599 return 1; /* handled by handle_exception_nmi_irqoff() */
4601 if (is_invalid_opcode(intr_info))
4602 return handle_ud(vcpu);
4605 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4606 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4608 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4609 WARN_ON_ONCE(!enable_vmware_backdoor);
4612 * VMware backdoor emulation on #GP interception only handles
4613 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4614 * error code on #GP.
4617 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4620 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4624 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4625 * MMIO, it is better to report an internal error.
4626 * See the comments in vmx_handle_exit.
4628 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4629 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4630 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4631 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4632 vcpu->run->internal.ndata = 3;
4633 vcpu->run->internal.data[0] = vect_info;
4634 vcpu->run->internal.data[1] = intr_info;
4635 vcpu->run->internal.data[2] = error_code;
4639 if (is_page_fault(intr_info)) {
4640 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4641 /* EPT won't cause page fault directly */
4642 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4643 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4646 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4648 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4649 return handle_rmode_exception(vcpu, ex_no, error_code);
4653 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4656 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4657 if (!(vcpu->guest_debug &
4658 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4659 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4660 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4661 if (is_icebp(intr_info))
4662 WARN_ON(!skip_emulated_instruction(vcpu));
4664 kvm_queue_exception(vcpu, DB_VECTOR);
4667 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4668 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4672 * Update instruction length as we may reinject #BP from
4673 * user space while in guest debugging mode. Reading it for
4674 * #DB as well causes no harm, it is not used in that case.
4676 vmx->vcpu.arch.event_exit_inst_len =
4677 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4678 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4679 rip = kvm_rip_read(vcpu);
4680 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4681 kvm_run->debug.arch.exception = ex_no;
4684 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4685 kvm_run->ex.exception = ex_no;
4686 kvm_run->ex.error_code = error_code;
4692 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4694 ++vcpu->stat.irq_exits;
4698 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4700 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4701 vcpu->mmio_needed = 0;
4705 static int handle_io(struct kvm_vcpu *vcpu)
4707 unsigned long exit_qualification;
4708 int size, in, string;
4711 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4712 string = (exit_qualification & 16) != 0;
4714 ++vcpu->stat.io_exits;
4717 return kvm_emulate_instruction(vcpu, 0);
4719 port = exit_qualification >> 16;
4720 size = (exit_qualification & 7) + 1;
4721 in = (exit_qualification & 8) != 0;
4723 return kvm_fast_pio(vcpu, size, port, in);
4727 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4730 * Patch in the VMCALL instruction:
4732 hypercall[0] = 0x0f;
4733 hypercall[1] = 0x01;
4734 hypercall[2] = 0xc1;
4737 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4738 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4740 if (is_guest_mode(vcpu)) {
4741 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4742 unsigned long orig_val = val;
4745 * We get here when L2 changed cr0 in a way that did not change
4746 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4747 * but did change L0 shadowed bits. So we first calculate the
4748 * effective cr0 value that L1 would like to write into the
4749 * hardware. It consists of the L2-owned bits from the new
4750 * value combined with the L1-owned bits from L1's guest_cr0.
4752 val = (val & ~vmcs12->cr0_guest_host_mask) |
4753 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4755 if (!nested_guest_cr0_valid(vcpu, val))
4758 if (kvm_set_cr0(vcpu, val))
4760 vmcs_writel(CR0_READ_SHADOW, orig_val);
4763 if (to_vmx(vcpu)->nested.vmxon &&
4764 !nested_host_cr0_valid(vcpu, val))
4767 return kvm_set_cr0(vcpu, val);
4771 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4773 if (is_guest_mode(vcpu)) {
4774 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4775 unsigned long orig_val = val;
4777 /* analogously to handle_set_cr0 */
4778 val = (val & ~vmcs12->cr4_guest_host_mask) |
4779 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4780 if (kvm_set_cr4(vcpu, val))
4782 vmcs_writel(CR4_READ_SHADOW, orig_val);
4785 return kvm_set_cr4(vcpu, val);
4788 static int handle_desc(struct kvm_vcpu *vcpu)
4790 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4791 return kvm_emulate_instruction(vcpu, 0);
4794 static int handle_cr(struct kvm_vcpu *vcpu)
4796 unsigned long exit_qualification, val;
4802 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4803 cr = exit_qualification & 15;
4804 reg = (exit_qualification >> 8) & 15;
4805 switch ((exit_qualification >> 4) & 3) {
4806 case 0: /* mov to cr */
4807 val = kvm_register_readl(vcpu, reg);
4808 trace_kvm_cr_write(cr, val);
4811 err = handle_set_cr0(vcpu, val);
4812 return kvm_complete_insn_gp(vcpu, err);
4814 WARN_ON_ONCE(enable_unrestricted_guest);
4815 err = kvm_set_cr3(vcpu, val);
4816 return kvm_complete_insn_gp(vcpu, err);
4818 err = handle_set_cr4(vcpu, val);
4819 return kvm_complete_insn_gp(vcpu, err);
4821 u8 cr8_prev = kvm_get_cr8(vcpu);
4823 err = kvm_set_cr8(vcpu, cr8);
4824 ret = kvm_complete_insn_gp(vcpu, err);
4825 if (lapic_in_kernel(vcpu))
4827 if (cr8_prev <= cr8)
4830 * TODO: we might be squashing a
4831 * KVM_GUESTDBG_SINGLESTEP-triggered
4832 * KVM_EXIT_DEBUG here.
4834 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4840 WARN_ONCE(1, "Guest should always own CR0.TS");
4841 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4842 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4843 return kvm_skip_emulated_instruction(vcpu);
4844 case 1: /*mov from cr*/
4847 WARN_ON_ONCE(enable_unrestricted_guest);
4848 val = kvm_read_cr3(vcpu);
4849 kvm_register_write(vcpu, reg, val);
4850 trace_kvm_cr_read(cr, val);
4851 return kvm_skip_emulated_instruction(vcpu);
4853 val = kvm_get_cr8(vcpu);
4854 kvm_register_write(vcpu, reg, val);
4855 trace_kvm_cr_read(cr, val);
4856 return kvm_skip_emulated_instruction(vcpu);
4860 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4861 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4862 kvm_lmsw(vcpu, val);
4864 return kvm_skip_emulated_instruction(vcpu);
4868 vcpu->run->exit_reason = 0;
4869 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4870 (int)(exit_qualification >> 4) & 3, cr);
4874 static int handle_dr(struct kvm_vcpu *vcpu)
4876 unsigned long exit_qualification;
4879 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4880 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4882 /* First, if DR does not exist, trigger UD */
4883 if (!kvm_require_dr(vcpu, dr))
4886 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4887 if (!kvm_require_cpl(vcpu, 0))
4889 dr7 = vmcs_readl(GUEST_DR7);
4892 * As the vm-exit takes precedence over the debug trap, we
4893 * need to emulate the latter, either for the host or the
4894 * guest debugging itself.
4896 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4897 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4898 vcpu->run->debug.arch.dr7 = dr7;
4899 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4900 vcpu->run->debug.arch.exception = DB_VECTOR;
4901 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4904 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4905 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4906 kvm_queue_exception(vcpu, DB_VECTOR);
4911 if (vcpu->guest_debug == 0) {
4912 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4915 * No more DR vmexits; force a reload of the debug registers
4916 * and reenter on this instruction. The next vmexit will
4917 * retrieve the full state of the debug registers.
4919 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4923 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4924 if (exit_qualification & TYPE_MOV_FROM_DR) {
4927 if (kvm_get_dr(vcpu, dr, &val))
4929 kvm_register_write(vcpu, reg, val);
4931 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4934 return kvm_skip_emulated_instruction(vcpu);
4937 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4939 return vcpu->arch.dr6;
4942 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4946 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4948 get_debugreg(vcpu->arch.db[0], 0);
4949 get_debugreg(vcpu->arch.db[1], 1);
4950 get_debugreg(vcpu->arch.db[2], 2);
4951 get_debugreg(vcpu->arch.db[3], 3);
4952 get_debugreg(vcpu->arch.dr6, 6);
4953 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4955 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4956 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4959 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4961 vmcs_writel(GUEST_DR7, val);
4964 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4966 kvm_apic_update_ppr(vcpu);
4970 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4972 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4974 kvm_make_request(KVM_REQ_EVENT, vcpu);
4976 ++vcpu->stat.irq_window_exits;
4980 static int handle_vmcall(struct kvm_vcpu *vcpu)
4982 return kvm_emulate_hypercall(vcpu);
4985 static int handle_invd(struct kvm_vcpu *vcpu)
4987 return kvm_emulate_instruction(vcpu, 0);
4990 static int handle_invlpg(struct kvm_vcpu *vcpu)
4992 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4994 kvm_mmu_invlpg(vcpu, exit_qualification);
4995 return kvm_skip_emulated_instruction(vcpu);
4998 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5002 err = kvm_rdpmc(vcpu);
5003 return kvm_complete_insn_gp(vcpu, err);
5006 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5008 return kvm_emulate_wbinvd(vcpu);
5011 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5013 u64 new_bv = kvm_read_edx_eax(vcpu);
5014 u32 index = kvm_rcx_read(vcpu);
5016 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5017 return kvm_skip_emulated_instruction(vcpu);
5021 static int handle_apic_access(struct kvm_vcpu *vcpu)
5023 if (likely(fasteoi)) {
5024 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5025 int access_type, offset;
5027 access_type = exit_qualification & APIC_ACCESS_TYPE;
5028 offset = exit_qualification & APIC_ACCESS_OFFSET;
5030 * Sane guest uses MOV to write EOI, with written value
5031 * not cared. So make a short-circuit here by avoiding
5032 * heavy instruction emulation.
5034 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5035 (offset == APIC_EOI)) {
5036 kvm_lapic_set_eoi(vcpu);
5037 return kvm_skip_emulated_instruction(vcpu);
5040 return kvm_emulate_instruction(vcpu, 0);
5043 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5045 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5046 int vector = exit_qualification & 0xff;
5048 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5049 kvm_apic_set_eoi_accelerated(vcpu, vector);
5053 static int handle_apic_write(struct kvm_vcpu *vcpu)
5055 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5056 u32 offset = exit_qualification & 0xfff;
5058 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5059 kvm_apic_write_nodecode(vcpu, offset);
5063 static int handle_task_switch(struct kvm_vcpu *vcpu)
5065 struct vcpu_vmx *vmx = to_vmx(vcpu);
5066 unsigned long exit_qualification;
5067 bool has_error_code = false;
5070 int reason, type, idt_v, idt_index;
5072 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5073 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5074 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5076 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5078 reason = (u32)exit_qualification >> 30;
5079 if (reason == TASK_SWITCH_GATE && idt_v) {
5081 case INTR_TYPE_NMI_INTR:
5082 vcpu->arch.nmi_injected = false;
5083 vmx_set_nmi_mask(vcpu, true);
5085 case INTR_TYPE_EXT_INTR:
5086 case INTR_TYPE_SOFT_INTR:
5087 kvm_clear_interrupt_queue(vcpu);
5089 case INTR_TYPE_HARD_EXCEPTION:
5090 if (vmx->idt_vectoring_info &
5091 VECTORING_INFO_DELIVER_CODE_MASK) {
5092 has_error_code = true;
5094 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5097 case INTR_TYPE_SOFT_EXCEPTION:
5098 kvm_clear_exception_queue(vcpu);
5104 tss_selector = exit_qualification;
5106 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5107 type != INTR_TYPE_EXT_INTR &&
5108 type != INTR_TYPE_NMI_INTR))
5109 WARN_ON(!skip_emulated_instruction(vcpu));
5112 * TODO: What about debug traps on tss switch?
5113 * Are we supposed to inject them and update dr6?
5115 return kvm_task_switch(vcpu, tss_selector,
5116 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5117 reason, has_error_code, error_code);
5120 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5122 unsigned long exit_qualification;
5126 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5129 * EPT violation happened while executing iret from NMI,
5130 * "blocked by NMI" bit has to be set before next VM entry.
5131 * There are errata that may cause this bit to not be set:
5134 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5136 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5137 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5139 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5140 trace_kvm_page_fault(gpa, exit_qualification);
5142 /* Is it a read fault? */
5143 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5144 ? PFERR_USER_MASK : 0;
5145 /* Is it a write fault? */
5146 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5147 ? PFERR_WRITE_MASK : 0;
5148 /* Is it a fetch fault? */
5149 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5150 ? PFERR_FETCH_MASK : 0;
5151 /* ept page table entry is present? */
5152 error_code |= (exit_qualification &
5153 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5154 EPT_VIOLATION_EXECUTABLE))
5155 ? PFERR_PRESENT_MASK : 0;
5157 error_code |= (exit_qualification & 0x100) != 0 ?
5158 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5160 vcpu->arch.exit_qualification = exit_qualification;
5161 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5164 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5169 * A nested guest cannot optimize MMIO vmexits, because we have an
5170 * nGPA here instead of the required GPA.
5172 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5173 if (!is_guest_mode(vcpu) &&
5174 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5175 trace_kvm_fast_mmio(gpa);
5176 return kvm_skip_emulated_instruction(vcpu);
5179 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5182 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5184 WARN_ON_ONCE(!enable_vnmi);
5185 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5186 ++vcpu->stat.nmi_window_exits;
5187 kvm_make_request(KVM_REQ_EVENT, vcpu);
5192 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5194 struct vcpu_vmx *vmx = to_vmx(vcpu);
5195 bool intr_window_requested;
5196 unsigned count = 130;
5199 * We should never reach the point where we are emulating L2
5200 * due to invalid guest state as that means we incorrectly
5201 * allowed a nested VMEntry with an invalid vmcs12.
5203 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5205 intr_window_requested = exec_controls_get(vmx) &
5206 CPU_BASED_INTR_WINDOW_EXITING;
5208 while (vmx->emulation_required && count-- != 0) {
5209 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5210 return handle_interrupt_window(&vmx->vcpu);
5212 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5215 if (!kvm_emulate_instruction(vcpu, 0))
5218 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5219 vcpu->arch.exception.pending) {
5220 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5221 vcpu->run->internal.suberror =
5222 KVM_INTERNAL_ERROR_EMULATION;
5223 vcpu->run->internal.ndata = 0;
5227 if (vcpu->arch.halt_request) {
5228 vcpu->arch.halt_request = 0;
5229 return kvm_vcpu_halt(vcpu);
5233 * Note, return 1 and not 0, vcpu_run() is responsible for
5234 * morphing the pending signal into the proper return code.
5236 if (signal_pending(current))
5246 static void grow_ple_window(struct kvm_vcpu *vcpu)
5248 struct vcpu_vmx *vmx = to_vmx(vcpu);
5249 unsigned int old = vmx->ple_window;
5251 vmx->ple_window = __grow_ple_window(old, ple_window,
5255 if (vmx->ple_window != old) {
5256 vmx->ple_window_dirty = true;
5257 trace_kvm_ple_window_update(vcpu->vcpu_id,
5258 vmx->ple_window, old);
5262 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5264 struct vcpu_vmx *vmx = to_vmx(vcpu);
5265 unsigned int old = vmx->ple_window;
5267 vmx->ple_window = __shrink_ple_window(old, ple_window,
5271 if (vmx->ple_window != old) {
5272 vmx->ple_window_dirty = true;
5273 trace_kvm_ple_window_update(vcpu->vcpu_id,
5274 vmx->ple_window, old);
5279 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5281 static void wakeup_handler(void)
5283 struct kvm_vcpu *vcpu;
5284 int cpu = smp_processor_id();
5286 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5287 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5288 blocked_vcpu_list) {
5289 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5291 if (pi_test_on(pi_desc) == 1)
5292 kvm_vcpu_kick(vcpu);
5294 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5297 static void vmx_enable_tdp(void)
5299 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5300 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5301 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5302 0ull, VMX_EPT_EXECUTABLE_MASK,
5303 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5304 VMX_EPT_RWX_MASK, 0ull);
5306 ept_set_mmio_spte_mask();
5311 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5312 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5314 static int handle_pause(struct kvm_vcpu *vcpu)
5316 if (!kvm_pause_in_guest(vcpu->kvm))
5317 grow_ple_window(vcpu);
5320 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5321 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5322 * never set PAUSE_EXITING and just set PLE if supported,
5323 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5325 kvm_vcpu_on_spin(vcpu, true);
5326 return kvm_skip_emulated_instruction(vcpu);
5329 static int handle_nop(struct kvm_vcpu *vcpu)
5331 return kvm_skip_emulated_instruction(vcpu);
5334 static int handle_mwait(struct kvm_vcpu *vcpu)
5336 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5337 return handle_nop(vcpu);
5340 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5342 kvm_queue_exception(vcpu, UD_VECTOR);
5346 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5351 static int handle_monitor(struct kvm_vcpu *vcpu)
5353 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5354 return handle_nop(vcpu);
5357 static int handle_invpcid(struct kvm_vcpu *vcpu)
5359 u32 vmx_instruction_info;
5363 struct x86_exception e;
5365 unsigned long roots_to_free = 0;
5371 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5372 kvm_queue_exception(vcpu, UD_VECTOR);
5376 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5377 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5380 kvm_inject_gp(vcpu, 0);
5384 /* According to the Intel instruction reference, the memory operand
5385 * is read even if it isn't needed (e.g., for type==all)
5387 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5388 vmx_instruction_info, false,
5389 sizeof(operand), &gva))
5392 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5393 kvm_inject_page_fault(vcpu, &e);
5397 if (operand.pcid >> 12 != 0) {
5398 kvm_inject_gp(vcpu, 0);
5402 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5405 case INVPCID_TYPE_INDIV_ADDR:
5406 if ((!pcid_enabled && (operand.pcid != 0)) ||
5407 is_noncanonical_address(operand.gla, vcpu)) {
5408 kvm_inject_gp(vcpu, 0);
5411 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5412 return kvm_skip_emulated_instruction(vcpu);
5414 case INVPCID_TYPE_SINGLE_CTXT:
5415 if (!pcid_enabled && (operand.pcid != 0)) {
5416 kvm_inject_gp(vcpu, 0);
5420 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5421 kvm_mmu_sync_roots(vcpu);
5422 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5425 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5426 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5428 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5430 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5432 * If neither the current cr3 nor any of the prev_roots use the
5433 * given PCID, then nothing needs to be done here because a
5434 * resync will happen anyway before switching to any other CR3.
5437 return kvm_skip_emulated_instruction(vcpu);
5439 case INVPCID_TYPE_ALL_NON_GLOBAL:
5441 * Currently, KVM doesn't mark global entries in the shadow
5442 * page tables, so a non-global flush just degenerates to a
5443 * global flush. If needed, we could optimize this later by
5444 * keeping track of global entries in shadow page tables.
5448 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5449 kvm_mmu_unload(vcpu);
5450 return kvm_skip_emulated_instruction(vcpu);
5453 BUG(); /* We have already checked above that type <= 3 */
5457 static int handle_pml_full(struct kvm_vcpu *vcpu)
5459 unsigned long exit_qualification;
5461 trace_kvm_pml_full(vcpu->vcpu_id);
5463 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5466 * PML buffer FULL happened while executing iret from NMI,
5467 * "blocked by NMI" bit has to be set before next VM entry.
5469 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5471 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5472 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5473 GUEST_INTR_STATE_NMI);
5476 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5477 * here.., and there's no userspace involvement needed for PML.
5482 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5484 struct vcpu_vmx *vmx = to_vmx(vcpu);
5486 if (!vmx->req_immediate_exit &&
5487 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5488 kvm_lapic_expired_hv_timer(vcpu);
5494 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5495 * are overwritten by nested_vmx_setup() when nested=1.
5497 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5499 kvm_queue_exception(vcpu, UD_VECTOR);
5503 static int handle_encls(struct kvm_vcpu *vcpu)
5506 * SGX virtualization is not yet supported. There is no software
5507 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5508 * to prevent the guest from executing ENCLS.
5510 kvm_queue_exception(vcpu, UD_VECTOR);
5515 * The exit handlers return 1 if the exit was handled fully and guest execution
5516 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5517 * to be done to userspace and return 0.
5519 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5520 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5521 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5522 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5523 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5524 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5525 [EXIT_REASON_CR_ACCESS] = handle_cr,
5526 [EXIT_REASON_DR_ACCESS] = handle_dr,
5527 [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
5528 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
5529 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
5530 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
5531 [EXIT_REASON_HLT] = kvm_emulate_halt,
5532 [EXIT_REASON_INVD] = handle_invd,
5533 [EXIT_REASON_INVLPG] = handle_invlpg,
5534 [EXIT_REASON_RDPMC] = handle_rdpmc,
5535 [EXIT_REASON_VMCALL] = handle_vmcall,
5536 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5537 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5538 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5539 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5540 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5541 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5542 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5543 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5544 [EXIT_REASON_VMON] = handle_vmx_instruction,
5545 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5546 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5547 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5548 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5549 [EXIT_REASON_WBINVD] = handle_wbinvd,
5550 [EXIT_REASON_XSETBV] = handle_xsetbv,
5551 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5552 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5553 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5554 [EXIT_REASON_LDTR_TR] = handle_desc,
5555 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5556 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5557 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5558 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5559 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5560 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5561 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5562 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5563 [EXIT_REASON_RDRAND] = handle_invalid_op,
5564 [EXIT_REASON_RDSEED] = handle_invalid_op,
5565 [EXIT_REASON_PML_FULL] = handle_pml_full,
5566 [EXIT_REASON_INVPCID] = handle_invpcid,
5567 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5568 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5569 [EXIT_REASON_ENCLS] = handle_encls,
5572 static const int kvm_vmx_max_exit_handlers =
5573 ARRAY_SIZE(kvm_vmx_exit_handlers);
5575 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5577 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5578 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5581 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5584 __free_page(vmx->pml_pg);
5589 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5591 struct vcpu_vmx *vmx = to_vmx(vcpu);
5595 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5597 /* Do nothing if PML buffer is empty */
5598 if (pml_idx == (PML_ENTITY_NUM - 1))
5601 /* PML index always points to next available PML buffer entity */
5602 if (pml_idx >= PML_ENTITY_NUM)
5607 pml_buf = page_address(vmx->pml_pg);
5608 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5611 gpa = pml_buf[pml_idx];
5612 WARN_ON(gpa & (PAGE_SIZE - 1));
5613 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5616 /* reset PML index */
5617 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5621 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5622 * Called before reporting dirty_bitmap to userspace.
5624 static void kvm_flush_pml_buffers(struct kvm *kvm)
5627 struct kvm_vcpu *vcpu;
5629 * We only need to kick vcpu out of guest mode here, as PML buffer
5630 * is flushed at beginning of all VMEXITs, and it's obvious that only
5631 * vcpus running in guest are possible to have unflushed GPAs in PML
5634 kvm_for_each_vcpu(i, vcpu, kvm)
5635 kvm_vcpu_kick(vcpu);
5638 static void vmx_dump_sel(char *name, uint32_t sel)
5640 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5641 name, vmcs_read16(sel),
5642 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5643 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5644 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5647 static void vmx_dump_dtsel(char *name, uint32_t limit)
5649 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5650 name, vmcs_read32(limit),
5651 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5654 void dump_vmcs(void)
5656 u32 vmentry_ctl, vmexit_ctl;
5657 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5662 if (!dump_invalid_vmcs) {
5663 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5667 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5668 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5669 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5670 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5671 cr4 = vmcs_readl(GUEST_CR4);
5672 efer = vmcs_read64(GUEST_IA32_EFER);
5673 secondary_exec_control = 0;
5674 if (cpu_has_secondary_exec_ctrls())
5675 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5677 pr_err("*** Guest State ***\n");
5678 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5679 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5680 vmcs_readl(CR0_GUEST_HOST_MASK));
5681 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5682 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5683 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5684 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5685 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5687 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5688 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5689 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5690 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5692 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5693 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5694 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5695 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5696 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5697 vmcs_readl(GUEST_SYSENTER_ESP),
5698 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5699 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5700 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5701 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5702 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5703 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5704 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5705 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5706 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5707 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5708 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5709 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5710 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5711 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5712 efer, vmcs_read64(GUEST_IA32_PAT));
5713 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5714 vmcs_read64(GUEST_IA32_DEBUGCTL),
5715 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5716 if (cpu_has_load_perf_global_ctrl() &&
5717 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5718 pr_err("PerfGlobCtl = 0x%016llx\n",
5719 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5720 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5721 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5722 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5723 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5724 vmcs_read32(GUEST_ACTIVITY_STATE));
5725 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5726 pr_err("InterruptStatus = %04x\n",
5727 vmcs_read16(GUEST_INTR_STATUS));
5729 pr_err("*** Host State ***\n");
5730 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5731 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5732 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5733 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5734 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5735 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5736 vmcs_read16(HOST_TR_SELECTOR));
5737 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5738 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5739 vmcs_readl(HOST_TR_BASE));
5740 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5741 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5742 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5743 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5744 vmcs_readl(HOST_CR4));
5745 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5746 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5747 vmcs_read32(HOST_IA32_SYSENTER_CS),
5748 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5749 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5750 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5751 vmcs_read64(HOST_IA32_EFER),
5752 vmcs_read64(HOST_IA32_PAT));
5753 if (cpu_has_load_perf_global_ctrl() &&
5754 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5755 pr_err("PerfGlobCtl = 0x%016llx\n",
5756 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5758 pr_err("*** Control State ***\n");
5759 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5760 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5761 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5762 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5763 vmcs_read32(EXCEPTION_BITMAP),
5764 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5765 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5766 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5767 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5768 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5769 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5770 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5771 vmcs_read32(VM_EXIT_INTR_INFO),
5772 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5773 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5774 pr_err(" reason=%08x qualification=%016lx\n",
5775 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5776 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5777 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5778 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5779 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5780 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5781 pr_err("TSC Multiplier = 0x%016llx\n",
5782 vmcs_read64(TSC_MULTIPLIER));
5783 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5784 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5785 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5786 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5788 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5789 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5790 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5791 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5793 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5794 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5795 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5796 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5797 n = vmcs_read32(CR3_TARGET_COUNT);
5798 for (i = 0; i + 1 < n; i += 4)
5799 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5800 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5801 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5803 pr_err("CR3 target%u=%016lx\n",
5804 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5805 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5806 pr_err("PLE Gap=%08x Window=%08x\n",
5807 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5808 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5809 pr_err("Virtual processor ID = 0x%04x\n",
5810 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5814 * The guest has exited. See if we can fix it or if we need userspace
5817 static int vmx_handle_exit(struct kvm_vcpu *vcpu,
5818 enum exit_fastpath_completion exit_fastpath)
5820 struct vcpu_vmx *vmx = to_vmx(vcpu);
5821 u32 exit_reason = vmx->exit_reason;
5822 u32 vectoring_info = vmx->idt_vectoring_info;
5824 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5827 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5828 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5829 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5830 * mode as if vcpus is in root mode, the PML buffer must has been
5834 vmx_flush_pml_buffer(vcpu);
5836 /* If guest state is invalid, start emulating */
5837 if (vmx->emulation_required)
5838 return handle_invalid_guest_state(vcpu);
5840 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5841 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5843 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5845 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5846 vcpu->run->fail_entry.hardware_entry_failure_reason
5851 if (unlikely(vmx->fail)) {
5853 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5854 vcpu->run->fail_entry.hardware_entry_failure_reason
5855 = vmcs_read32(VM_INSTRUCTION_ERROR);
5861 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5862 * delivery event since it indicates guest is accessing MMIO.
5863 * The vm-exit can be triggered again after return to guest that
5864 * will cause infinite loop.
5866 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5867 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5868 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5869 exit_reason != EXIT_REASON_PML_FULL &&
5870 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5871 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5872 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5873 vcpu->run->internal.ndata = 3;
5874 vcpu->run->internal.data[0] = vectoring_info;
5875 vcpu->run->internal.data[1] = exit_reason;
5876 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5877 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5878 vcpu->run->internal.ndata++;
5879 vcpu->run->internal.data[3] =
5880 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5885 if (unlikely(!enable_vnmi &&
5886 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5887 if (vmx_interrupt_allowed(vcpu)) {
5888 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5889 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5890 vcpu->arch.nmi_pending) {
5892 * This CPU don't support us in finding the end of an
5893 * NMI-blocked window if the guest runs with IRQs
5894 * disabled. So we pull the trigger after 1 s of
5895 * futile waiting, but inform the user about this.
5897 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5898 "state on VCPU %d after 1 s timeout\n",
5899 __func__, vcpu->vcpu_id);
5900 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5904 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5905 kvm_skip_emulated_instruction(vcpu);
5907 } else if (exit_reason < kvm_vmx_max_exit_handlers
5908 && kvm_vmx_exit_handlers[exit_reason]) {
5909 #ifdef CONFIG_RETPOLINE
5910 if (exit_reason == EXIT_REASON_MSR_WRITE)
5911 return kvm_emulate_wrmsr(vcpu);
5912 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5913 return handle_preemption_timer(vcpu);
5914 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
5915 return handle_interrupt_window(vcpu);
5916 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5917 return handle_external_interrupt(vcpu);
5918 else if (exit_reason == EXIT_REASON_HLT)
5919 return kvm_emulate_halt(vcpu);
5920 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5921 return handle_ept_misconfig(vcpu);
5923 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5925 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5928 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5929 vcpu->run->internal.suberror =
5930 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5931 vcpu->run->internal.ndata = 1;
5932 vcpu->run->internal.data[0] = exit_reason;
5938 * Software based L1D cache flush which is used when microcode providing
5939 * the cache control MSR is not loaded.
5941 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5942 * flush it is required to read in 64 KiB because the replacement algorithm
5943 * is not exactly LRU. This could be sized at runtime via topology
5944 * information but as all relevant affected CPUs have 32KiB L1D cache size
5945 * there is no point in doing so.
5947 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5949 int size = PAGE_SIZE << L1D_CACHE_ORDER;
5952 * This code is only executed when the the flush mode is 'cond' or
5955 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5959 * Clear the per-vcpu flush bit, it gets set again
5960 * either from vcpu_run() or from one of the unsafe
5963 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5964 vcpu->arch.l1tf_flush_l1d = false;
5967 * Clear the per-cpu flush bit, it gets set again from
5968 * the interrupt handlers.
5970 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5971 kvm_clear_cpu_l1tf_flush_l1d();
5977 vcpu->stat.l1d_flush++;
5979 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5980 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5985 /* First ensure the pages are in the TLB */
5986 "xorl %%eax, %%eax\n"
5987 ".Lpopulate_tlb:\n\t"
5988 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5989 "addl $4096, %%eax\n\t"
5990 "cmpl %%eax, %[size]\n\t"
5991 "jne .Lpopulate_tlb\n\t"
5992 "xorl %%eax, %%eax\n\t"
5994 /* Now fill the cache */
5995 "xorl %%eax, %%eax\n"
5997 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5998 "addl $64, %%eax\n\t"
5999 "cmpl %%eax, %[size]\n\t"
6000 "jne .Lfill_cache\n\t"
6002 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6004 : "eax", "ebx", "ecx", "edx");
6007 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6009 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6012 if (is_guest_mode(vcpu) &&
6013 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6016 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6017 if (is_guest_mode(vcpu))
6018 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6020 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6023 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6025 struct vcpu_vmx *vmx = to_vmx(vcpu);
6026 u32 sec_exec_control;
6028 if (!lapic_in_kernel(vcpu))
6031 if (!flexpriority_enabled &&
6032 !cpu_has_vmx_virtualize_x2apic_mode())
6035 /* Postpone execution until vmcs01 is the current VMCS. */
6036 if (is_guest_mode(vcpu)) {
6037 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6041 sec_exec_control = secondary_exec_controls_get(vmx);
6042 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6043 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6045 switch (kvm_get_apic_mode(vcpu)) {
6046 case LAPIC_MODE_INVALID:
6047 WARN_ONCE(true, "Invalid local APIC state");
6048 case LAPIC_MODE_DISABLED:
6050 case LAPIC_MODE_XAPIC:
6051 if (flexpriority_enabled) {
6053 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6054 vmx_flush_tlb(vcpu, true);
6057 case LAPIC_MODE_X2APIC:
6058 if (cpu_has_vmx_virtualize_x2apic_mode())
6060 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6063 secondary_exec_controls_set(vmx, sec_exec_control);
6065 vmx_update_msr_bitmap(vcpu);
6068 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6070 if (!is_guest_mode(vcpu)) {
6071 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6072 vmx_flush_tlb(vcpu, true);
6076 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6084 status = vmcs_read16(GUEST_INTR_STATUS);
6086 if (max_isr != old) {
6088 status |= max_isr << 8;
6089 vmcs_write16(GUEST_INTR_STATUS, status);
6093 static void vmx_set_rvi(int vector)
6101 status = vmcs_read16(GUEST_INTR_STATUS);
6102 old = (u8)status & 0xff;
6103 if ((u8)vector != old) {
6105 status |= (u8)vector;
6106 vmcs_write16(GUEST_INTR_STATUS, status);
6110 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6113 * When running L2, updating RVI is only relevant when
6114 * vmcs12 virtual-interrupt-delivery enabled.
6115 * However, it can be enabled only when L1 also
6116 * intercepts external-interrupts and in that case
6117 * we should not update vmcs02 RVI but instead intercept
6118 * interrupt. Therefore, do nothing when running L2.
6120 if (!is_guest_mode(vcpu))
6121 vmx_set_rvi(max_irr);
6124 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6126 struct vcpu_vmx *vmx = to_vmx(vcpu);
6128 bool max_irr_updated;
6130 WARN_ON(!vcpu->arch.apicv_active);
6131 if (pi_test_on(&vmx->pi_desc)) {
6132 pi_clear_on(&vmx->pi_desc);
6134 * IOMMU can write to PID.ON, so the barrier matters even on UP.
6135 * But on x86 this is just a compiler barrier anyway.
6137 smp_mb__after_atomic();
6139 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6142 * If we are running L2 and L1 has a new pending interrupt
6143 * which can be injected, we should re-evaluate
6144 * what should be done with this new L1 interrupt.
6145 * If L1 intercepts external-interrupts, we should
6146 * exit from L2 to L1. Otherwise, interrupt should be
6147 * delivered directly to L2.
6149 if (is_guest_mode(vcpu) && max_irr_updated) {
6150 if (nested_exit_on_intr(vcpu))
6151 kvm_vcpu_exiting_guest_mode(vcpu);
6153 kvm_make_request(KVM_REQ_EVENT, vcpu);
6156 max_irr = kvm_lapic_find_highest_irr(vcpu);
6158 vmx_hwapic_irr_update(vcpu, max_irr);
6162 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6164 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6166 return pi_test_on(pi_desc) ||
6167 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6170 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6172 if (!kvm_vcpu_apicv_active(vcpu))
6175 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6176 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6177 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6178 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6181 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6183 struct vcpu_vmx *vmx = to_vmx(vcpu);
6185 pi_clear_on(&vmx->pi_desc);
6186 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6189 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6191 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6193 /* if exit due to PF check for async PF */
6194 if (is_page_fault(vmx->exit_intr_info))
6195 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6197 /* Handle machine checks before interrupts are enabled */
6198 if (is_machine_check(vmx->exit_intr_info))
6199 kvm_machine_check();
6201 /* We need to handle NMIs before interrupts are enabled */
6202 if (is_nmi(vmx->exit_intr_info)) {
6203 kvm_before_interrupt(&vmx->vcpu);
6205 kvm_after_interrupt(&vmx->vcpu);
6209 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6211 unsigned int vector;
6212 unsigned long entry;
6213 #ifdef CONFIG_X86_64
6219 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6220 if (WARN_ONCE(!is_external_intr(intr_info),
6221 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6224 vector = intr_info & INTR_INFO_VECTOR_MASK;
6225 desc = (gate_desc *)host_idt_base + vector;
6226 entry = gate_offset(desc);
6228 kvm_before_interrupt(vcpu);
6231 #ifdef CONFIG_X86_64
6232 "mov %%" _ASM_SP ", %[sp]\n\t"
6233 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6238 __ASM_SIZE(push) " $%c[cs]\n\t"
6241 #ifdef CONFIG_X86_64
6246 THUNK_TARGET(entry),
6247 [ss]"i"(__KERNEL_DS),
6248 [cs]"i"(__KERNEL_CS)
6251 kvm_after_interrupt(vcpu);
6253 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6255 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6256 enum exit_fastpath_completion *exit_fastpath)
6258 struct vcpu_vmx *vmx = to_vmx(vcpu);
6260 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6261 handle_external_interrupt_irqoff(vcpu);
6262 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6263 handle_exception_nmi_irqoff(vmx);
6264 else if (!is_guest_mode(vcpu) &&
6265 vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6266 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
6269 static bool vmx_has_emulated_msr(int index)
6272 case MSR_IA32_SMBASE:
6274 * We cannot do SMM unless we can run the guest in big
6277 return enable_unrestricted_guest || emulate_invalid_guest_state;
6278 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6280 case MSR_AMD64_VIRT_SPEC_CTRL:
6281 /* This is AMD only. */
6288 static bool vmx_pt_supported(void)
6290 return pt_mode == PT_MODE_HOST_GUEST;
6293 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6298 bool idtv_info_valid;
6300 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6303 if (vmx->loaded_vmcs->nmi_known_unmasked)
6306 * Can't use vmx->exit_intr_info since we're not sure what
6307 * the exit reason is.
6309 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6310 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6311 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6313 * SDM 3: 27.7.1.2 (September 2008)
6314 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6315 * a guest IRET fault.
6316 * SDM 3: 23.2.2 (September 2008)
6317 * Bit 12 is undefined in any of the following cases:
6318 * If the VM exit sets the valid bit in the IDT-vectoring
6319 * information field.
6320 * If the VM exit is due to a double fault.
6322 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6323 vector != DF_VECTOR && !idtv_info_valid)
6324 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6325 GUEST_INTR_STATE_NMI);
6327 vmx->loaded_vmcs->nmi_known_unmasked =
6328 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6329 & GUEST_INTR_STATE_NMI);
6330 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6331 vmx->loaded_vmcs->vnmi_blocked_time +=
6332 ktime_to_ns(ktime_sub(ktime_get(),
6333 vmx->loaded_vmcs->entry_time));
6336 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6337 u32 idt_vectoring_info,
6338 int instr_len_field,
6339 int error_code_field)
6343 bool idtv_info_valid;
6345 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6347 vcpu->arch.nmi_injected = false;
6348 kvm_clear_exception_queue(vcpu);
6349 kvm_clear_interrupt_queue(vcpu);
6351 if (!idtv_info_valid)
6354 kvm_make_request(KVM_REQ_EVENT, vcpu);
6356 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6357 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6360 case INTR_TYPE_NMI_INTR:
6361 vcpu->arch.nmi_injected = true;
6363 * SDM 3: 27.7.1.2 (September 2008)
6364 * Clear bit "block by NMI" before VM entry if a NMI
6367 vmx_set_nmi_mask(vcpu, false);
6369 case INTR_TYPE_SOFT_EXCEPTION:
6370 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6372 case INTR_TYPE_HARD_EXCEPTION:
6373 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6374 u32 err = vmcs_read32(error_code_field);
6375 kvm_requeue_exception_e(vcpu, vector, err);
6377 kvm_requeue_exception(vcpu, vector);
6379 case INTR_TYPE_SOFT_INTR:
6380 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6382 case INTR_TYPE_EXT_INTR:
6383 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6390 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6392 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6393 VM_EXIT_INSTRUCTION_LEN,
6394 IDT_VECTORING_ERROR_CODE);
6397 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6399 __vmx_complete_interrupts(vcpu,
6400 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6401 VM_ENTRY_INSTRUCTION_LEN,
6402 VM_ENTRY_EXCEPTION_ERROR_CODE);
6404 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6407 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6410 struct perf_guest_switch_msr *msrs;
6412 msrs = perf_guest_get_msrs(&nr_msrs);
6417 for (i = 0; i < nr_msrs; i++)
6418 if (msrs[i].host == msrs[i].guest)
6419 clear_atomic_switch_msr(vmx, msrs[i].msr);
6421 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6422 msrs[i].host, false);
6425 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6427 u32 host_umwait_control;
6429 if (!vmx_has_waitpkg(vmx))
6432 host_umwait_control = get_umwait_control_msr();
6434 if (vmx->msr_ia32_umwait_control != host_umwait_control)
6435 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6436 vmx->msr_ia32_umwait_control,
6437 host_umwait_control, false);
6439 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6442 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6444 struct vcpu_vmx *vmx = to_vmx(vcpu);
6448 if (vmx->req_immediate_exit) {
6449 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6450 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6451 } else if (vmx->hv_deadline_tsc != -1) {
6453 if (vmx->hv_deadline_tsc > tscl)
6454 /* set_hv_timer ensures the delta fits in 32-bits */
6455 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6456 cpu_preemption_timer_multi);
6460 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6461 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6462 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6463 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6464 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6468 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6470 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6471 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6472 vmcs_writel(HOST_RSP, host_rsp);
6476 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6478 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6480 struct vcpu_vmx *vmx = to_vmx(vcpu);
6481 unsigned long cr3, cr4;
6483 /* Record the guest's net vcpu time for enforced NMI injections. */
6484 if (unlikely(!enable_vnmi &&
6485 vmx->loaded_vmcs->soft_vnmi_blocked))
6486 vmx->loaded_vmcs->entry_time = ktime_get();
6488 /* Don't enter VMX if guest state is invalid, let the exit handler
6489 start emulation until we arrive back to a valid state */
6490 if (vmx->emulation_required)
6493 if (vmx->ple_window_dirty) {
6494 vmx->ple_window_dirty = false;
6495 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6498 if (vmx->nested.need_vmcs12_to_shadow_sync)
6499 nested_sync_vmcs12_to_shadow(vcpu);
6501 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6502 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6503 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6504 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6506 cr3 = __get_current_cr3_fast();
6507 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6508 vmcs_writel(HOST_CR3, cr3);
6509 vmx->loaded_vmcs->host_state.cr3 = cr3;
6512 cr4 = cr4_read_shadow();
6513 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6514 vmcs_writel(HOST_CR4, cr4);
6515 vmx->loaded_vmcs->host_state.cr4 = cr4;
6518 /* When single-stepping over STI and MOV SS, we must clear the
6519 * corresponding interruptibility bits in the guest state. Otherwise
6520 * vmentry fails as it then expects bit 14 (BS) in pending debug
6521 * exceptions being set, but that's not correct for the guest debugging
6523 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6524 vmx_set_interrupt_shadow(vcpu, 0);
6526 kvm_load_guest_xsave_state(vcpu);
6528 if (static_cpu_has(X86_FEATURE_PKU) &&
6529 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6530 vcpu->arch.pkru != vmx->host_pkru)
6531 __write_pkru(vcpu->arch.pkru);
6533 pt_guest_enter(vmx);
6535 atomic_switch_perf_msrs(vmx);
6536 atomic_switch_umwait_control_msr(vmx);
6538 if (enable_preemption_timer)
6539 vmx_update_hv_timer(vcpu);
6541 if (lapic_in_kernel(vcpu) &&
6542 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6543 kvm_wait_lapic_expire(vcpu);
6546 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6547 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6548 * is no need to worry about the conditional branch over the wrmsr
6549 * being speculatively taken.
6551 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6553 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6554 if (static_branch_unlikely(&vmx_l1d_should_flush))
6555 vmx_l1d_flush(vcpu);
6556 else if (static_branch_unlikely(&mds_user_clear))
6557 mds_clear_cpu_buffers();
6559 if (vcpu->arch.cr2 != read_cr2())
6560 write_cr2(vcpu->arch.cr2);
6562 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6563 vmx->loaded_vmcs->launched);
6565 vcpu->arch.cr2 = read_cr2();
6568 * We do not use IBRS in the kernel. If this vCPU has used the
6569 * SPEC_CTRL MSR it may have left it on; save the value and
6570 * turn it off. This is much more efficient than blindly adding
6571 * it to the atomic save/restore list. Especially as the former
6572 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6574 * For non-nested case:
6575 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6579 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6582 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6583 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6585 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6587 /* All fields are clean at this point */
6588 if (static_branch_unlikely(&enable_evmcs))
6589 current_evmcs->hv_clean_fields |=
6590 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6592 if (static_branch_unlikely(&enable_evmcs))
6593 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6595 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6596 if (vmx->host_debugctlmsr)
6597 update_debugctlmsr(vmx->host_debugctlmsr);
6599 #ifndef CONFIG_X86_64
6601 * The sysexit path does not restore ds/es, so we must set them to
6602 * a reasonable value ourselves.
6604 * We can't defer this to vmx_prepare_switch_to_host() since that
6605 * function may be executed in interrupt context, which saves and
6606 * restore segments around it, nullifying its effect.
6608 loadsegment(ds, __USER_DS);
6609 loadsegment(es, __USER_DS);
6612 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6613 | (1 << VCPU_EXREG_RFLAGS)
6614 | (1 << VCPU_EXREG_PDPTR)
6615 | (1 << VCPU_EXREG_SEGMENTS)
6616 | (1 << VCPU_EXREG_CR3));
6617 vcpu->arch.regs_dirty = 0;
6622 * eager fpu is enabled if PKEY is supported and CR4 is switched
6623 * back on host, so it is safe to read guest PKRU from current
6626 if (static_cpu_has(X86_FEATURE_PKU) &&
6627 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6628 vcpu->arch.pkru = rdpkru();
6629 if (vcpu->arch.pkru != vmx->host_pkru)
6630 __write_pkru(vmx->host_pkru);
6633 kvm_load_host_xsave_state(vcpu);
6635 vmx->nested.nested_run_pending = 0;
6636 vmx->idt_vectoring_info = 0;
6638 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6639 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6640 kvm_machine_check();
6642 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6645 vmx->loaded_vmcs->launched = 1;
6646 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6648 vmx_recover_nmi_blocking(vmx);
6649 vmx_complete_interrupts(vmx);
6652 static struct kvm *vmx_vm_alloc(void)
6654 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6655 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6657 return &kvm_vmx->kvm;
6660 static void vmx_vm_free(struct kvm *kvm)
6662 kfree(kvm->arch.hyperv.hv_pa_pg);
6663 vfree(to_kvm_vmx(kvm));
6666 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6668 struct vcpu_vmx *vmx = to_vmx(vcpu);
6671 vmx_destroy_pml_buffer(vmx);
6672 free_vpid(vmx->vpid);
6673 nested_vmx_free_vcpu(vcpu);
6674 free_loaded_vmcs(vmx->loaded_vmcs);
6675 kvm_vcpu_uninit(vcpu);
6676 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6677 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6678 kmem_cache_free(kvm_vcpu_cache, vmx);
6681 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6684 struct vcpu_vmx *vmx;
6685 unsigned long *msr_bitmap;
6688 BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
6689 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
6691 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
6693 return ERR_PTR(-ENOMEM);
6695 vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6696 GFP_KERNEL_ACCOUNT);
6697 if (!vmx->vcpu.arch.user_fpu) {
6698 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6700 goto free_partial_vcpu;
6703 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6704 GFP_KERNEL_ACCOUNT);
6705 if (!vmx->vcpu.arch.guest_fpu) {
6706 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6711 vmx->vpid = allocate_vpid();
6713 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6720 * If PML is turned on, failure on enabling PML just results in failure
6721 * of creating the vcpu, therefore we can simplify PML logic (by
6722 * avoiding dealing with cases, such as enabling PML partially on vcpus
6723 * for the guest, etc.
6726 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6731 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
6733 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6734 u32 index = vmx_msr_index[i];
6735 u32 data_low, data_high;
6738 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6740 if (wrmsr_safe(index, data_low, data_high) < 0)
6743 vmx->guest_msrs[j].index = i;
6744 vmx->guest_msrs[j].data = 0;
6746 case MSR_IA32_TSX_CTRL:
6748 * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6749 * let's avoid changing CPUID bits under the host
6752 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6755 vmx->guest_msrs[j].mask = -1ull;
6761 err = alloc_loaded_vmcs(&vmx->vmcs01);
6765 msr_bitmap = vmx->vmcs01.msr_bitmap;
6766 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6767 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6768 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6769 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6770 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6771 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6772 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6773 if (kvm_cstate_in_guest(kvm)) {
6774 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6775 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6776 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6777 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6779 vmx->msr_bitmap_mode = 0;
6781 vmx->loaded_vmcs = &vmx->vmcs01;
6783 vmx_vcpu_load(&vmx->vcpu, cpu);
6784 vmx->vcpu.cpu = cpu;
6786 vmx_vcpu_put(&vmx->vcpu);
6788 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6789 err = alloc_apic_access_page(kvm);
6794 if (enable_ept && !enable_unrestricted_guest) {
6795 err = init_rmode_identity_map(kvm);
6801 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6803 kvm_vcpu_apicv_active(&vmx->vcpu));
6805 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6807 vmx->nested.posted_intr_nv = -1;
6808 vmx->nested.current_vmptr = -1ull;
6810 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
6813 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6814 * or POSTED_INTR_WAKEUP_VECTOR.
6816 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6817 vmx->pi_desc.sn = 1;
6819 vmx->ept_pointer = INVALID_PAGE;
6824 free_loaded_vmcs(vmx->loaded_vmcs);
6826 vmx_destroy_pml_buffer(vmx);
6828 kvm_vcpu_uninit(&vmx->vcpu);
6830 free_vpid(vmx->vpid);
6831 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6833 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6835 kmem_cache_free(kvm_vcpu_cache, vmx);
6836 return ERR_PTR(err);
6839 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6840 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6842 static int vmx_vm_init(struct kvm *kvm)
6844 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6847 kvm->arch.pause_in_guest = true;
6849 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6850 switch (l1tf_mitigation) {
6851 case L1TF_MITIGATION_OFF:
6852 case L1TF_MITIGATION_FLUSH_NOWARN:
6853 /* 'I explicitly don't care' is set */
6855 case L1TF_MITIGATION_FLUSH:
6856 case L1TF_MITIGATION_FLUSH_NOSMT:
6857 case L1TF_MITIGATION_FULL:
6859 * Warn upon starting the first VM in a potentially
6860 * insecure environment.
6862 if (sched_smt_active())
6863 pr_warn_once(L1TF_MSG_SMT);
6864 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6865 pr_warn_once(L1TF_MSG_L1D);
6867 case L1TF_MITIGATION_FULL_FORCE:
6868 /* Flush is enforced */
6875 static int __init vmx_check_processor_compat(void)
6877 struct vmcs_config vmcs_conf;
6878 struct vmx_capability vmx_cap;
6880 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6883 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6885 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6886 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6887 smp_processor_id());
6893 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6898 /* For VT-d and EPT combination
6899 * 1. MMIO: always map as UC
6901 * a. VT-d without snooping control feature: can't guarantee the
6902 * result, try to trust guest.
6903 * b. VT-d with snooping control feature: snooping control feature of
6904 * VT-d engine can guarantee the cache correctness. Just set it
6905 * to WB to keep consistent with host. So the same as item 3.
6906 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6907 * consistent with host MTRR
6910 cache = MTRR_TYPE_UNCACHABLE;
6914 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6915 ipat = VMX_EPT_IPAT_BIT;
6916 cache = MTRR_TYPE_WRBACK;
6920 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6921 ipat = VMX_EPT_IPAT_BIT;
6922 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6923 cache = MTRR_TYPE_WRBACK;
6925 cache = MTRR_TYPE_UNCACHABLE;
6929 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6932 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6935 static int vmx_get_lpage_level(void)
6937 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6938 return PT_DIRECTORY_LEVEL;
6940 /* For shadow and EPT supported 1GB page */
6941 return PT_PDPE_LEVEL;
6944 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6947 * These bits in the secondary execution controls field
6948 * are dynamic, the others are mostly based on the hypervisor
6949 * architecture and the guest's CPUID. Do not touch the
6953 SECONDARY_EXEC_SHADOW_VMCS |
6954 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6955 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6956 SECONDARY_EXEC_DESC;
6958 u32 new_ctl = vmx->secondary_exec_control;
6959 u32 cur_ctl = secondary_exec_controls_get(vmx);
6961 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6965 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6966 * (indicating "allowed-1") if they are supported in the guest's CPUID.
6968 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6970 struct vcpu_vmx *vmx = to_vmx(vcpu);
6971 struct kvm_cpuid_entry2 *entry;
6973 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6974 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6976 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6977 if (entry && (entry->_reg & (_cpuid_mask))) \
6978 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6981 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6982 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6983 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6984 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6985 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6986 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6987 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6988 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6989 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6990 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6991 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6992 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6993 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6994 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6995 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
6997 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6998 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6999 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
7000 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
7001 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
7002 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
7003 cr4_fixed1_update(X86_CR4_LA57, ecx, bit(X86_FEATURE_LA57));
7005 #undef cr4_fixed1_update
7008 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7010 struct vcpu_vmx *vmx = to_vmx(vcpu);
7012 if (kvm_mpx_supported()) {
7013 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7016 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7017 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7019 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7020 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7025 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7027 struct vcpu_vmx *vmx = to_vmx(vcpu);
7028 struct kvm_cpuid_entry2 *best = NULL;
7031 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7032 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7035 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7036 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7037 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7038 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7041 /* Get the number of configurable Address Ranges for filtering */
7042 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7043 PT_CAP_num_address_ranges);
7045 /* Initialize and clear the no dependency bits */
7046 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7047 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7050 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7051 * will inject an #GP
7053 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7054 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7057 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7058 * PSBFreq can be set
7060 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7061 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7062 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7065 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7066 * MTCFreq can be set
7068 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7069 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7070 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7072 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7073 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7074 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7077 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7078 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7079 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7081 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7082 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7083 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7085 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7086 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7087 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7089 /* unmask address range configure area */
7090 for (i = 0; i < vmx->pt_desc.addr_range; i++)
7091 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7094 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7096 struct vcpu_vmx *vmx = to_vmx(vcpu);
7098 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7099 vcpu->arch.xsaves_enabled = false;
7101 if (cpu_has_secondary_exec_ctrls()) {
7102 vmx_compute_secondary_exec_control(vmx);
7103 vmcs_set_secondary_exec_control(vmx);
7106 if (nested_vmx_allowed(vcpu))
7107 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7108 FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX |
7109 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7111 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7112 ~(FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX |
7113 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX);
7115 if (nested_vmx_allowed(vcpu)) {
7116 nested_vmx_cr_fixed1_bits_update(vcpu);
7117 nested_vmx_entry_exit_ctls_update(vcpu);
7120 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7121 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7122 update_intel_pt_cfg(vcpu);
7124 if (boot_cpu_has(X86_FEATURE_RTM)) {
7125 struct shared_msr_entry *msr;
7126 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7128 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7129 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7134 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7136 if (func == 1 && nested)
7137 entry->ecx |= bit(X86_FEATURE_VMX);
7140 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7142 to_vmx(vcpu)->req_immediate_exit = true;
7145 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7146 struct x86_instruction_info *info,
7147 enum x86_intercept_stage stage)
7149 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7150 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7153 * RDPID causes #UD if disabled through secondary execution controls.
7154 * Because it is marked as EmulateOnUD, we need to intercept it here.
7156 if (info->intercept == x86_intercept_rdtscp &&
7157 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7158 ctxt->exception.vector = UD_VECTOR;
7159 ctxt->exception.error_code_valid = false;
7160 return X86EMUL_PROPAGATE_FAULT;
7163 /* TODO: check more intercepts... */
7164 return X86EMUL_CONTINUE;
7167 #ifdef CONFIG_X86_64
7168 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7169 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7170 u64 divisor, u64 *result)
7172 u64 low = a << shift, high = a >> (64 - shift);
7174 /* To avoid the overflow on divq */
7175 if (high >= divisor)
7178 /* Low hold the result, high hold rem which is discarded */
7179 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7180 "rm" (divisor), "0" (low), "1" (high));
7186 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7189 struct vcpu_vmx *vmx;
7190 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7191 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7193 if (kvm_mwait_in_guest(vcpu->kvm) ||
7194 kvm_can_post_timer_interrupt(vcpu))
7199 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7200 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7201 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7202 ktimer->timer_advance_ns);
7204 if (delta_tsc > lapic_timer_advance_cycles)
7205 delta_tsc -= lapic_timer_advance_cycles;
7209 /* Convert to host delta tsc if tsc scaling is enabled */
7210 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7211 delta_tsc && u64_shl_div_u64(delta_tsc,
7212 kvm_tsc_scaling_ratio_frac_bits,
7213 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7217 * If the delta tsc can't fit in the 32 bit after the multi shift,
7218 * we can't use the preemption timer.
7219 * It's possible that it fits on later vmentries, but checking
7220 * on every vmentry is costly so we just use an hrtimer.
7222 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7225 vmx->hv_deadline_tsc = tscl + delta_tsc;
7226 *expired = !delta_tsc;
7230 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7232 to_vmx(vcpu)->hv_deadline_tsc = -1;
7236 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7238 if (!kvm_pause_in_guest(vcpu->kvm))
7239 shrink_ple_window(vcpu);
7242 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7243 struct kvm_memory_slot *slot)
7245 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7246 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7249 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7250 struct kvm_memory_slot *slot)
7252 kvm_mmu_slot_set_dirty(kvm, slot);
7255 static void vmx_flush_log_dirty(struct kvm *kvm)
7257 kvm_flush_pml_buffers(kvm);
7260 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7262 struct vmcs12 *vmcs12;
7263 struct vcpu_vmx *vmx = to_vmx(vcpu);
7266 if (is_guest_mode(vcpu)) {
7267 WARN_ON_ONCE(vmx->nested.pml_full);
7270 * Check if PML is enabled for the nested guest.
7271 * Whether eptp bit 6 is set is already checked
7272 * as part of A/D emulation.
7274 vmcs12 = get_vmcs12(vcpu);
7275 if (!nested_cpu_has_pml(vmcs12))
7278 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7279 vmx->nested.pml_full = true;
7283 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7284 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7286 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7287 offset_in_page(dst), sizeof(gpa)))
7290 vmcs12->guest_pml_index--;
7296 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7297 struct kvm_memory_slot *memslot,
7298 gfn_t offset, unsigned long mask)
7300 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7303 static void __pi_post_block(struct kvm_vcpu *vcpu)
7305 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7306 struct pi_desc old, new;
7310 old.control = new.control = pi_desc->control;
7311 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7312 "Wakeup handler not enabled while the VCPU is blocked\n");
7314 dest = cpu_physical_id(vcpu->cpu);
7316 if (x2apic_enabled())
7319 new.ndst = (dest << 8) & 0xFF00;
7321 /* set 'NV' to 'notification vector' */
7322 new.nv = POSTED_INTR_VECTOR;
7323 } while (cmpxchg64(&pi_desc->control, old.control,
7324 new.control) != old.control);
7326 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7327 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7328 list_del(&vcpu->blocked_vcpu_list);
7329 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7330 vcpu->pre_pcpu = -1;
7335 * This routine does the following things for vCPU which is going
7336 * to be blocked if VT-d PI is enabled.
7337 * - Store the vCPU to the wakeup list, so when interrupts happen
7338 * we can find the right vCPU to wake up.
7339 * - Change the Posted-interrupt descriptor as below:
7340 * 'NDST' <-- vcpu->pre_pcpu
7341 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7342 * - If 'ON' is set during this process, which means at least one
7343 * interrupt is posted for this vCPU, we cannot block it, in
7344 * this case, return 1, otherwise, return 0.
7347 static int pi_pre_block(struct kvm_vcpu *vcpu)
7350 struct pi_desc old, new;
7351 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7353 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7354 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7355 !kvm_vcpu_apicv_active(vcpu))
7358 WARN_ON(irqs_disabled());
7359 local_irq_disable();
7360 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7361 vcpu->pre_pcpu = vcpu->cpu;
7362 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7363 list_add_tail(&vcpu->blocked_vcpu_list,
7364 &per_cpu(blocked_vcpu_on_cpu,
7366 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7370 old.control = new.control = pi_desc->control;
7372 WARN((pi_desc->sn == 1),
7373 "Warning: SN field of posted-interrupts "
7374 "is set before blocking\n");
7377 * Since vCPU can be preempted during this process,
7378 * vcpu->cpu could be different with pre_pcpu, we
7379 * need to set pre_pcpu as the destination of wakeup
7380 * notification event, then we can find the right vCPU
7381 * to wakeup in wakeup handler if interrupts happen
7382 * when the vCPU is in blocked state.
7384 dest = cpu_physical_id(vcpu->pre_pcpu);
7386 if (x2apic_enabled())
7389 new.ndst = (dest << 8) & 0xFF00;
7391 /* set 'NV' to 'wakeup vector' */
7392 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7393 } while (cmpxchg64(&pi_desc->control, old.control,
7394 new.control) != old.control);
7396 /* We should not block the vCPU if an interrupt is posted for it. */
7397 if (pi_test_on(pi_desc) == 1)
7398 __pi_post_block(vcpu);
7401 return (vcpu->pre_pcpu == -1);
7404 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7406 if (pi_pre_block(vcpu))
7409 if (kvm_lapic_hv_timer_in_use(vcpu))
7410 kvm_lapic_switch_to_sw_timer(vcpu);
7415 static void pi_post_block(struct kvm_vcpu *vcpu)
7417 if (vcpu->pre_pcpu == -1)
7420 WARN_ON(irqs_disabled());
7421 local_irq_disable();
7422 __pi_post_block(vcpu);
7426 static void vmx_post_block(struct kvm_vcpu *vcpu)
7428 if (kvm_x86_ops->set_hv_timer)
7429 kvm_lapic_switch_to_hv_timer(vcpu);
7431 pi_post_block(vcpu);
7435 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7438 * @host_irq: host irq of the interrupt
7439 * @guest_irq: gsi of the interrupt
7440 * @set: set or unset PI
7441 * returns 0 on success, < 0 on failure
7443 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7444 uint32_t guest_irq, bool set)
7446 struct kvm_kernel_irq_routing_entry *e;
7447 struct kvm_irq_routing_table *irq_rt;
7448 struct kvm_lapic_irq irq;
7449 struct kvm_vcpu *vcpu;
7450 struct vcpu_data vcpu_info;
7453 if (!kvm_arch_has_assigned_device(kvm) ||
7454 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7455 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7458 idx = srcu_read_lock(&kvm->irq_srcu);
7459 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7460 if (guest_irq >= irq_rt->nr_rt_entries ||
7461 hlist_empty(&irq_rt->map[guest_irq])) {
7462 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7463 guest_irq, irq_rt->nr_rt_entries);
7467 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7468 if (e->type != KVM_IRQ_ROUTING_MSI)
7471 * VT-d PI cannot support posting multicast/broadcast
7472 * interrupts to a vCPU, we still use interrupt remapping
7473 * for these kind of interrupts.
7475 * For lowest-priority interrupts, we only support
7476 * those with single CPU as the destination, e.g. user
7477 * configures the interrupts via /proc/irq or uses
7478 * irqbalance to make the interrupts single-CPU.
7480 * We will support full lowest-priority interrupt later.
7482 * In addition, we can only inject generic interrupts using
7483 * the PI mechanism, refuse to route others through it.
7486 kvm_set_msi_irq(kvm, e, &irq);
7487 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7488 !kvm_irq_is_postable(&irq)) {
7490 * Make sure the IRTE is in remapped mode if
7491 * we don't handle it in posted mode.
7493 ret = irq_set_vcpu_affinity(host_irq, NULL);
7496 "failed to back to remapped mode, irq: %u\n",
7504 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7505 vcpu_info.vector = irq.vector;
7507 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7508 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7511 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7513 ret = irq_set_vcpu_affinity(host_irq, NULL);
7516 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7524 srcu_read_unlock(&kvm->irq_srcu, idx);
7528 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7530 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7531 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7532 FEATURE_CONTROL_LMCE;
7534 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7535 ~FEATURE_CONTROL_LMCE;
7538 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7540 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7541 if (to_vmx(vcpu)->nested.nested_run_pending)
7546 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7548 struct vcpu_vmx *vmx = to_vmx(vcpu);
7550 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7551 if (vmx->nested.smm.guest_mode)
7552 nested_vmx_vmexit(vcpu, -1, 0, 0);
7554 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7555 vmx->nested.vmxon = false;
7556 vmx_clear_hlt(vcpu);
7560 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7562 struct vcpu_vmx *vmx = to_vmx(vcpu);
7565 if (vmx->nested.smm.vmxon) {
7566 vmx->nested.vmxon = true;
7567 vmx->nested.smm.vmxon = false;
7570 if (vmx->nested.smm.guest_mode) {
7571 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7575 vmx->nested.smm.guest_mode = false;
7580 static int enable_smi_window(struct kvm_vcpu *vcpu)
7585 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7590 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7592 return to_vmx(vcpu)->nested.vmxon;
7595 static __init int hardware_setup(void)
7597 unsigned long host_bndcfgs;
7601 rdmsrl_safe(MSR_EFER, &host_efer);
7604 host_idt_base = dt.address;
7606 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7607 kvm_define_shared_msr(i, vmx_msr_index[i]);
7609 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7612 if (boot_cpu_has(X86_FEATURE_NX))
7613 kvm_enable_efer_bits(EFER_NX);
7615 if (boot_cpu_has(X86_FEATURE_MPX)) {
7616 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7617 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7620 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7621 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7624 if (!cpu_has_vmx_ept() ||
7625 !cpu_has_vmx_ept_4levels() ||
7626 !cpu_has_vmx_ept_mt_wb() ||
7627 !cpu_has_vmx_invept_global())
7630 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7631 enable_ept_ad_bits = 0;
7633 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7634 enable_unrestricted_guest = 0;
7636 if (!cpu_has_vmx_flexpriority())
7637 flexpriority_enabled = 0;
7639 if (!cpu_has_virtual_nmis())
7643 * set_apic_access_page_addr() is used to reload apic access
7644 * page upon invalidation. No need to do anything if not
7645 * using the APIC_ACCESS_ADDR VMCS field.
7647 if (!flexpriority_enabled)
7648 kvm_x86_ops->set_apic_access_page_addr = NULL;
7650 if (!cpu_has_vmx_tpr_shadow())
7651 kvm_x86_ops->update_cr8_intercept = NULL;
7653 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7654 kvm_disable_largepages();
7656 #if IS_ENABLED(CONFIG_HYPERV)
7657 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7659 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7660 kvm_x86_ops->tlb_remote_flush_with_range =
7661 hv_remote_flush_tlb_with_range;
7665 if (!cpu_has_vmx_ple()) {
7668 ple_window_grow = 0;
7670 ple_window_shrink = 0;
7673 if (!cpu_has_vmx_apicv()) {
7675 kvm_x86_ops->sync_pir_to_irr = NULL;
7678 if (cpu_has_vmx_tsc_scaling()) {
7679 kvm_has_tsc_control = true;
7680 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7681 kvm_tsc_scaling_ratio_frac_bits = 48;
7684 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7692 * Only enable PML when hardware supports PML feature, and both EPT
7693 * and EPT A/D bit features are enabled -- PML depends on them to work.
7695 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7699 kvm_x86_ops->slot_enable_log_dirty = NULL;
7700 kvm_x86_ops->slot_disable_log_dirty = NULL;
7701 kvm_x86_ops->flush_log_dirty = NULL;
7702 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7705 if (!cpu_has_vmx_preemption_timer())
7706 enable_preemption_timer = false;
7708 if (enable_preemption_timer) {
7709 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7712 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7713 cpu_preemption_timer_multi =
7714 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7717 use_timer_freq = (u64)tsc_khz * 1000;
7718 use_timer_freq >>= cpu_preemption_timer_multi;
7721 * KVM "disables" the preemption timer by setting it to its max
7722 * value. Don't use the timer if it might cause spurious exits
7723 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7725 if (use_timer_freq > 0xffffffffu / 10)
7726 enable_preemption_timer = false;
7729 if (!enable_preemption_timer) {
7730 kvm_x86_ops->set_hv_timer = NULL;
7731 kvm_x86_ops->cancel_hv_timer = NULL;
7732 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7735 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7737 kvm_mce_cap_supported |= MCG_LMCE_P;
7739 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7741 if (!enable_ept || !cpu_has_vmx_intel_pt())
7742 pt_mode = PT_MODE_SYSTEM;
7745 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7746 vmx_capability.ept, enable_apicv);
7748 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7753 r = alloc_kvm_area();
7755 nested_vmx_hardware_unsetup();
7759 static __exit void hardware_unsetup(void)
7762 nested_vmx_hardware_unsetup();
7767 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7768 .cpu_has_kvm_support = cpu_has_kvm_support,
7769 .disabled_by_bios = vmx_disabled_by_bios,
7770 .hardware_setup = hardware_setup,
7771 .hardware_unsetup = hardware_unsetup,
7772 .check_processor_compatibility = vmx_check_processor_compat,
7773 .hardware_enable = hardware_enable,
7774 .hardware_disable = hardware_disable,
7775 .cpu_has_accelerated_tpr = report_flexpriority,
7776 .has_emulated_msr = vmx_has_emulated_msr,
7778 .vm_init = vmx_vm_init,
7779 .vm_alloc = vmx_vm_alloc,
7780 .vm_free = vmx_vm_free,
7782 .vcpu_create = vmx_create_vcpu,
7783 .vcpu_free = vmx_free_vcpu,
7784 .vcpu_reset = vmx_vcpu_reset,
7786 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7787 .vcpu_load = vmx_vcpu_load,
7788 .vcpu_put = vmx_vcpu_put,
7790 .update_bp_intercept = update_exception_bitmap,
7791 .get_msr_feature = vmx_get_msr_feature,
7792 .get_msr = vmx_get_msr,
7793 .set_msr = vmx_set_msr,
7794 .get_segment_base = vmx_get_segment_base,
7795 .get_segment = vmx_get_segment,
7796 .set_segment = vmx_set_segment,
7797 .get_cpl = vmx_get_cpl,
7798 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7799 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7800 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7801 .set_cr0 = vmx_set_cr0,
7802 .set_cr3 = vmx_set_cr3,
7803 .set_cr4 = vmx_set_cr4,
7804 .set_efer = vmx_set_efer,
7805 .get_idt = vmx_get_idt,
7806 .set_idt = vmx_set_idt,
7807 .get_gdt = vmx_get_gdt,
7808 .set_gdt = vmx_set_gdt,
7809 .get_dr6 = vmx_get_dr6,
7810 .set_dr6 = vmx_set_dr6,
7811 .set_dr7 = vmx_set_dr7,
7812 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7813 .cache_reg = vmx_cache_reg,
7814 .get_rflags = vmx_get_rflags,
7815 .set_rflags = vmx_set_rflags,
7817 .tlb_flush = vmx_flush_tlb,
7818 .tlb_flush_gva = vmx_flush_tlb_gva,
7820 .run = vmx_vcpu_run,
7821 .handle_exit = vmx_handle_exit,
7822 .skip_emulated_instruction = skip_emulated_instruction,
7823 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7824 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7825 .patch_hypercall = vmx_patch_hypercall,
7826 .set_irq = vmx_inject_irq,
7827 .set_nmi = vmx_inject_nmi,
7828 .queue_exception = vmx_queue_exception,
7829 .cancel_injection = vmx_cancel_injection,
7830 .interrupt_allowed = vmx_interrupt_allowed,
7831 .nmi_allowed = vmx_nmi_allowed,
7832 .get_nmi_mask = vmx_get_nmi_mask,
7833 .set_nmi_mask = vmx_set_nmi_mask,
7834 .enable_nmi_window = enable_nmi_window,
7835 .enable_irq_window = enable_irq_window,
7836 .update_cr8_intercept = update_cr8_intercept,
7837 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7838 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7839 .get_enable_apicv = vmx_get_enable_apicv,
7840 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7841 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7842 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7843 .hwapic_irr_update = vmx_hwapic_irr_update,
7844 .hwapic_isr_update = vmx_hwapic_isr_update,
7845 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7846 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7847 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7848 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7850 .set_tss_addr = vmx_set_tss_addr,
7851 .set_identity_map_addr = vmx_set_identity_map_addr,
7852 .get_tdp_level = get_ept_level,
7853 .get_mt_mask = vmx_get_mt_mask,
7855 .get_exit_info = vmx_get_exit_info,
7857 .get_lpage_level = vmx_get_lpage_level,
7859 .cpuid_update = vmx_cpuid_update,
7861 .rdtscp_supported = vmx_rdtscp_supported,
7862 .invpcid_supported = vmx_invpcid_supported,
7864 .set_supported_cpuid = vmx_set_supported_cpuid,
7866 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7868 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7869 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7871 .set_tdp_cr3 = vmx_set_cr3,
7873 .check_intercept = vmx_check_intercept,
7874 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7875 .mpx_supported = vmx_mpx_supported,
7876 .xsaves_supported = vmx_xsaves_supported,
7877 .umip_emulated = vmx_umip_emulated,
7878 .pt_supported = vmx_pt_supported,
7880 .request_immediate_exit = vmx_request_immediate_exit,
7882 .sched_in = vmx_sched_in,
7884 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7885 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7886 .flush_log_dirty = vmx_flush_log_dirty,
7887 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7888 .write_log_dirty = vmx_write_pml_buffer,
7890 .pre_block = vmx_pre_block,
7891 .post_block = vmx_post_block,
7893 .pmu_ops = &intel_pmu_ops,
7895 .update_pi_irte = vmx_update_pi_irte,
7897 #ifdef CONFIG_X86_64
7898 .set_hv_timer = vmx_set_hv_timer,
7899 .cancel_hv_timer = vmx_cancel_hv_timer,
7902 .setup_mce = vmx_setup_mce,
7904 .smi_allowed = vmx_smi_allowed,
7905 .pre_enter_smm = vmx_pre_enter_smm,
7906 .pre_leave_smm = vmx_pre_leave_smm,
7907 .enable_smi_window = enable_smi_window,
7909 .check_nested_events = NULL,
7910 .get_nested_state = NULL,
7911 .set_nested_state = NULL,
7912 .get_vmcs12_pages = NULL,
7913 .nested_enable_evmcs = NULL,
7914 .nested_get_evmcs_version = NULL,
7915 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7916 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7919 static void vmx_cleanup_l1d_flush(void)
7921 if (vmx_l1d_flush_pages) {
7922 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7923 vmx_l1d_flush_pages = NULL;
7925 /* Restore state so sysfs ignores VMX */
7926 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7929 static void vmx_exit(void)
7931 #ifdef CONFIG_KEXEC_CORE
7932 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7938 #if IS_ENABLED(CONFIG_HYPERV)
7939 if (static_branch_unlikely(&enable_evmcs)) {
7941 struct hv_vp_assist_page *vp_ap;
7943 * Reset everything to support using non-enlightened VMCS
7944 * access later (e.g. when we reload the module with
7945 * enlightened_vmcs=0)
7947 for_each_online_cpu(cpu) {
7948 vp_ap = hv_get_vp_assist_page(cpu);
7953 vp_ap->nested_control.features.directhypercall = 0;
7954 vp_ap->current_nested_vmcs = 0;
7955 vp_ap->enlighten_vmentry = 0;
7958 static_branch_disable(&enable_evmcs);
7961 vmx_cleanup_l1d_flush();
7963 module_exit(vmx_exit);
7965 static int __init vmx_init(void)
7969 #if IS_ENABLED(CONFIG_HYPERV)
7971 * Enlightened VMCS usage should be recommended and the host needs
7972 * to support eVMCS v1 or above. We can also disable eVMCS support
7973 * with module parameter.
7975 if (enlightened_vmcs &&
7976 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7977 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7978 KVM_EVMCS_VERSION) {
7981 /* Check that we have assist pages on all online CPUs */
7982 for_each_online_cpu(cpu) {
7983 if (!hv_get_vp_assist_page(cpu)) {
7984 enlightened_vmcs = false;
7989 if (enlightened_vmcs) {
7990 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7991 static_branch_enable(&enable_evmcs);
7994 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7995 vmx_x86_ops.enable_direct_tlbflush
7996 = hv_enable_direct_tlbflush;
7999 enlightened_vmcs = false;
8003 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8004 __alignof__(struct vcpu_vmx), THIS_MODULE);
8009 * Must be called after kvm_init() so enable_ept is properly set
8010 * up. Hand the parameter mitigation value in which was stored in
8011 * the pre module init parser. If no parameter was given, it will
8012 * contain 'auto' which will be turned into the default 'cond'
8015 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8021 #ifdef CONFIG_KEXEC_CORE
8022 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8023 crash_vmclear_local_loaded_vmcss);
8025 vmx_check_vmcs12_offsets();
8029 module_init(vmx_init);