arch/x86/kvm/vmx/nested.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __KVM_X86_VMX_NESTED_H
   3 #define __KVM_X86_VMX_NESTED_H
   4
   5 #include "kvm_cache_regs.h"
   6 #include "vmcs12.h"
   7 #include "vmx.h"
   8
   9 void vmx_leave_nested(struct kvm_vcpu *vcpu);
  10 void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps,
  11                                 bool apicv);
  12 void nested_vmx_hardware_unsetup(void);
  13 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *));
  14 void nested_vmx_vcpu_setup(void);
  15 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu);
  16 int nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry);
  17 bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason);
  18 void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
  19                        u32 exit_intr_info, unsigned long exit_qualification);
  20 void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu);
  21 int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
  22 int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata);
  23 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification,
  24                         u32 vmx_instruction_info, bool wr, int len, gva_t *ret);
  25
  26 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
  27 {
  28         return to_vmx(vcpu)->nested.cached_vmcs12;
  29 }
  30
  31 static inline struct vmcs12 *get_shadow_vmcs12(struct kvm_vcpu *vcpu)
  32 {
  33         return to_vmx(vcpu)->nested.cached_shadow_vmcs12;
  34 }
  35
  36 static inline int vmx_has_valid_vmcs12(struct kvm_vcpu *vcpu)
  37 {
  38         struct vcpu_vmx *vmx = to_vmx(vcpu);
  39
  40         /*
  41          * In case we do two consecutive get/set_nested_state()s while L2 was
  42          * running hv_evmcs may end up not being mapped (we map it from
  43          * nested_vmx_run()/vmx_vcpu_run()). Check is_guest_mode() as we always
  44          * have vmcs12 if it is true.
  45          */
  46         return is_guest_mode(vcpu) || vmx->nested.current_vmptr != -1ull ||
  47                 vmx->nested.hv_evmcs;
  48 }
  49
  50 static inline unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
  51 {
  52         /* return the page table to be shadowed - in our case, EPT12 */
  53         return get_vmcs12(vcpu)->ept_pointer;
  54 }
  55
  56 static inline bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
  57 {
  58         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
  59 }
  60
  61 /*
  62  * Reflect a VM Exit into L1.
  63  */
  64 static inline int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu,
  65                                             u32 exit_reason)
  66 {
  67         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
  68
  69         /*
  70          * At this point, the exit interruption info in exit_intr_info
  71          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
  72          * we need to query the in-kernel LAPIC.
  73          */
  74         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
  75         if ((exit_intr_info &
  76              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
  77             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
  78                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
  79
  80                 vmcs12->vm_exit_intr_error_code =
  81                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
  82         }
  83
  84         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
  85                           vmcs_readl(EXIT_QUALIFICATION));
  86         return 1;
  87 }
  88
  89 /*
  90  * Return the cr0 value that a nested guest would read. This is a combination
  91  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
  92  * its hypervisor (cr0_read_shadow).
  93  */
  94 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
  95 {
  96         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
  97                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
  98 }
  99 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
 100 {
 101         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
 102                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
 103 }
 104
 105 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
 106 {
 107         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
 108 }
 109
 110 /*
 111  * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
 112  * to modify any valid field of the VMCS, or are the VM-exit
 113  * information fields read-only?
 114  */
 115 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
 116 {
 117         return to_vmx(vcpu)->nested.msrs.misc_low &
 118                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
 119 }
 120
 121 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)
 122 {
 123         return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS;
 124 }
 125
 126 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu)
 127 {
 128         return to_vmx(vcpu)->nested.msrs.procbased_ctls_high &
 129                         CPU_BASED_MONITOR_TRAP_FLAG;
 130 }
 131
 132 static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu *vcpu)
 133 {
 134         return to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
 135                 SECONDARY_EXEC_SHADOW_VMCS;
 136 }
 137
 138 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 139 {
 140         return vmcs12->cpu_based_vm_exec_control & bit;
 141 }
 142
 143 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 144 {
 145         return (vmcs12->cpu_based_vm_exec_control &
 146                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 147                 (vmcs12->secondary_vm_exec_control & bit);
 148 }
 149
 150 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
 151 {
 152         return vmcs12->pin_based_vm_exec_control &
 153                 PIN_BASED_VMX_PREEMPTION_TIMER;
 154 }
 155
 156 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
 157 {
 158         return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
 159 }
 160
 161 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
 162 {
 163         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 164 }
 165
 166 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
 167 {
 168         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
 169 }
 170
 171 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
 172 {
 173         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
 174 }
 175
 176 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
 177 {
 178         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
 179 }
 180
 181 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
 182 {
 183         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
 184 }
 185
 186 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
 187 {
 188         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
 189 }
 190
 191 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
 192 {
 193         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
 194 }
 195
 196 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
 197 {
 198         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
 199 }
 200
 201 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
 202 {
 203         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
 204 }
 205
 206 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
 207 {
 208         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
 209 }
 210
 211 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
 212 {
 213         return nested_cpu_has_vmfunc(vmcs12) &&
 214                 (vmcs12->vm_function_control &
 215                  VMX_VMFUNC_EPTP_SWITCHING);
 216 }
 217
 218 static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12 *vmcs12)
 219 {
 220         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS);
 221 }
 222
 223 static inline bool nested_cpu_has_save_preemption_timer(struct vmcs12 *vmcs12)
 224 {
 225         return vmcs12->vm_exit_controls &
 226             VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
 227 }
 228
 229 /*
 230  * In nested virtualization, check if L1 asked to exit on external interrupts.
 231  * For most existing hypervisors, this will always return true.
 232  */
 233 static inline bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
 234 {
 235         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
 236                 PIN_BASED_EXT_INTR_MASK;
 237 }
 238
 239 /*
 240  * if fixed0[i] == 1: val[i] must be 1
 241  * if fixed1[i] == 0: val[i] must be 0
 242  */
 243 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
 244 {
 245         return ((val & fixed1) | fixed0) == val;
 246 }
 247
 248 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
 249 {
 250         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
 251         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
 252         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 253
 254         if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
 255                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
 256             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
 257                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
 258
 259         return fixed_bits_valid(val, fixed0, fixed1);
 260 }
 261
 262 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
 263 {
 264         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
 265         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
 266
 267         return fixed_bits_valid(val, fixed0, fixed1);
 268 }
 269
 270 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
 271 {
 272         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
 273         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
 274
 275         return fixed_bits_valid(val, fixed0, fixed1);
 276 }
 277
 278 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
 279 #define nested_guest_cr4_valid  nested_cr4_valid
 280 #define nested_host_cr4_valid   nested_cr4_valid
 281
 282 #endif /* __KVM_X86_VMX_NESTED_H */