1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/objtool.h>
4 #include <linux/percpu.h>
6 #include <asm/debugreg.h>
7 #include <asm/mmu_context.h>
19 static bool __read_mostly enable_shadow_vmcs = 1;
20 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
22 static bool __read_mostly nested_early_check = 0;
23 module_param(nested_early_check, bool, S_IRUGO);
25 #define CC KVM_NESTED_VMENTER_CONSISTENCY_CHECK
28 * Hyper-V requires all of these, so mark them as supported even though
29 * they are just treated the same as all-context.
31 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
32 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
33 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
34 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
35 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
37 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
44 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
46 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
47 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
49 struct shadow_vmcs_field {
53 static struct shadow_vmcs_field shadow_read_only_fields[] = {
54 #define SHADOW_FIELD_RO(x, y) { x, offsetof(struct vmcs12, y) },
55 #include "vmcs_shadow_fields.h"
57 static int max_shadow_read_only_fields =
58 ARRAY_SIZE(shadow_read_only_fields);
60 static struct shadow_vmcs_field shadow_read_write_fields[] = {
61 #define SHADOW_FIELD_RW(x, y) { x, offsetof(struct vmcs12, y) },
62 #include "vmcs_shadow_fields.h"
64 static int max_shadow_read_write_fields =
65 ARRAY_SIZE(shadow_read_write_fields);
67 static void init_vmcs_shadow_fields(void)
71 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
72 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
74 for (i = j = 0; i < max_shadow_read_only_fields; i++) {
75 struct shadow_vmcs_field entry = shadow_read_only_fields[i];
76 u16 field = entry.encoding;
78 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
79 (i + 1 == max_shadow_read_only_fields ||
80 shadow_read_only_fields[i + 1].encoding != field + 1))
81 pr_err("Missing field from shadow_read_only_field %x\n",
84 clear_bit(field, vmx_vmread_bitmap);
89 entry.offset += sizeof(u32);
91 shadow_read_only_fields[j++] = entry;
93 max_shadow_read_only_fields = j;
95 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
96 struct shadow_vmcs_field entry = shadow_read_write_fields[i];
97 u16 field = entry.encoding;
99 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
100 (i + 1 == max_shadow_read_write_fields ||
101 shadow_read_write_fields[i + 1].encoding != field + 1))
102 pr_err("Missing field from shadow_read_write_field %x\n",
105 WARN_ONCE(field >= GUEST_ES_AR_BYTES &&
106 field <= GUEST_TR_AR_BYTES,
107 "Update vmcs12_write_any() to drop reserved bits from AR_BYTES");
110 * PML and the preemption timer can be emulated, but the
111 * processor cannot vmwrite to fields that don't exist
115 case GUEST_PML_INDEX:
116 if (!cpu_has_vmx_pml())
119 case VMX_PREEMPTION_TIMER_VALUE:
120 if (!cpu_has_vmx_preemption_timer())
123 case GUEST_INTR_STATUS:
124 if (!cpu_has_vmx_apicv())
131 clear_bit(field, vmx_vmwrite_bitmap);
132 clear_bit(field, vmx_vmread_bitmap);
137 entry.offset += sizeof(u32);
139 shadow_read_write_fields[j++] = entry;
141 max_shadow_read_write_fields = j;
145 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
146 * set the success or error code of an emulated VMX instruction (as specified
147 * by Vol 2B, VMX Instruction Reference, "Conventions"), and skip the emulated
150 static int nested_vmx_succeed(struct kvm_vcpu *vcpu)
152 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
153 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
154 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
155 return kvm_skip_emulated_instruction(vcpu);
158 static int nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
160 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
161 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
162 X86_EFLAGS_SF | X86_EFLAGS_OF))
164 return kvm_skip_emulated_instruction(vcpu);
167 static int nested_vmx_failValid(struct kvm_vcpu *vcpu,
168 u32 vm_instruction_error)
170 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
171 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
172 X86_EFLAGS_SF | X86_EFLAGS_OF))
174 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
176 * We don't need to force sync to shadow VMCS because
177 * VM_INSTRUCTION_ERROR is not shadowed. Enlightened VMCS 'shadows' all
178 * fields and thus must be synced.
180 if (to_vmx(vcpu)->nested.hv_evmcs_vmptr != EVMPTR_INVALID)
181 to_vmx(vcpu)->nested.need_vmcs12_to_shadow_sync = true;
183 return kvm_skip_emulated_instruction(vcpu);
186 static int nested_vmx_fail(struct kvm_vcpu *vcpu, u32 vm_instruction_error)
188 struct vcpu_vmx *vmx = to_vmx(vcpu);
191 * failValid writes the error number to the current VMCS, which
192 * can't be done if there isn't a current VMCS.
194 if (vmx->nested.current_vmptr == -1ull &&
195 !evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
196 return nested_vmx_failInvalid(vcpu);
198 return nested_vmx_failValid(vcpu, vm_instruction_error);
201 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
203 /* TODO: not to reset guest simply here. */
204 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
205 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
208 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
210 return fixed_bits_valid(control, low, high);
213 static inline u64 vmx_control_msr(u32 low, u32 high)
215 return low | ((u64)high << 32);
218 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
220 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
221 vmcs_write64(VMCS_LINK_POINTER, -1ull);
222 vmx->nested.need_vmcs12_to_shadow_sync = false;
225 static inline void nested_release_evmcs(struct kvm_vcpu *vcpu)
227 struct vcpu_vmx *vmx = to_vmx(vcpu);
229 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) {
230 kvm_vcpu_unmap(vcpu, &vmx->nested.hv_evmcs_map, true);
231 vmx->nested.hv_evmcs = NULL;
234 vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
237 static void vmx_sync_vmcs_host_state(struct vcpu_vmx *vmx,
238 struct loaded_vmcs *prev)
240 struct vmcs_host_state *dest, *src;
242 if (unlikely(!vmx->guest_state_loaded))
245 src = &prev->host_state;
246 dest = &vmx->loaded_vmcs->host_state;
248 vmx_set_host_fs_gs(dest, src->fs_sel, src->gs_sel, src->fs_base, src->gs_base);
249 dest->ldt_sel = src->ldt_sel;
251 dest->ds_sel = src->ds_sel;
252 dest->es_sel = src->es_sel;
256 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
258 struct vcpu_vmx *vmx = to_vmx(vcpu);
259 struct loaded_vmcs *prev;
262 if (WARN_ON_ONCE(vmx->loaded_vmcs == vmcs))
266 prev = vmx->loaded_vmcs;
267 vmx->loaded_vmcs = vmcs;
268 vmx_vcpu_load_vmcs(vcpu, cpu, prev);
269 vmx_sync_vmcs_host_state(vmx, prev);
272 vmx_register_cache_reset(vcpu);
276 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
277 * just stops using VMX.
279 static void free_nested(struct kvm_vcpu *vcpu)
281 struct vcpu_vmx *vmx = to_vmx(vcpu);
283 if (WARN_ON_ONCE(vmx->loaded_vmcs != &vmx->vmcs01))
284 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
286 if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
289 kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu);
291 vmx->nested.vmxon = false;
292 vmx->nested.smm.vmxon = false;
293 free_vpid(vmx->nested.vpid02);
294 vmx->nested.posted_intr_nv = -1;
295 vmx->nested.current_vmptr = -1ull;
296 if (enable_shadow_vmcs) {
297 vmx_disable_shadow_vmcs(vmx);
298 vmcs_clear(vmx->vmcs01.shadow_vmcs);
299 free_vmcs(vmx->vmcs01.shadow_vmcs);
300 vmx->vmcs01.shadow_vmcs = NULL;
302 kfree(vmx->nested.cached_vmcs12);
303 vmx->nested.cached_vmcs12 = NULL;
304 kfree(vmx->nested.cached_shadow_vmcs12);
305 vmx->nested.cached_shadow_vmcs12 = NULL;
306 /* Unpin physical memory we referred to in the vmcs02 */
307 if (vmx->nested.apic_access_page) {
308 kvm_release_page_clean(vmx->nested.apic_access_page);
309 vmx->nested.apic_access_page = NULL;
311 kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true);
312 kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true);
313 vmx->nested.pi_desc = NULL;
315 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
317 nested_release_evmcs(vcpu);
319 free_loaded_vmcs(&vmx->nested.vmcs02);
323 * Ensure that the current vmcs of the logical processor is the
324 * vmcs01 of the vcpu before calling free_nested().
326 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu)
329 vmx_leave_nested(vcpu);
333 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
334 struct x86_exception *fault)
336 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
337 struct vcpu_vmx *vmx = to_vmx(vcpu);
339 unsigned long exit_qualification = vcpu->arch.exit_qualification;
341 if (vmx->nested.pml_full) {
342 vm_exit_reason = EXIT_REASON_PML_FULL;
343 vmx->nested.pml_full = false;
344 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
345 } else if (fault->error_code & PFERR_RSVD_MASK)
346 vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
348 vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
350 nested_vmx_vmexit(vcpu, vm_exit_reason, 0, exit_qualification);
351 vmcs12->guest_physical_address = fault->address;
354 static void nested_ept_new_eptp(struct kvm_vcpu *vcpu)
356 kvm_init_shadow_ept_mmu(vcpu,
357 to_vmx(vcpu)->nested.msrs.ept_caps &
358 VMX_EPT_EXECUTE_ONLY_BIT,
359 nested_ept_ad_enabled(vcpu),
360 nested_ept_get_eptp(vcpu));
363 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
365 WARN_ON(mmu_is_nested(vcpu));
367 vcpu->arch.mmu = &vcpu->arch.guest_mmu;
368 nested_ept_new_eptp(vcpu);
369 vcpu->arch.mmu->get_guest_pgd = nested_ept_get_eptp;
370 vcpu->arch.mmu->inject_page_fault = nested_ept_inject_page_fault;
371 vcpu->arch.mmu->get_pdptr = kvm_pdptr_read;
373 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
376 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
378 vcpu->arch.mmu = &vcpu->arch.root_mmu;
379 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
382 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
385 bool inequality, bit;
387 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
389 (error_code & vmcs12->page_fault_error_code_mask) !=
390 vmcs12->page_fault_error_code_match;
391 return inequality ^ bit;
396 * KVM wants to inject page-faults which it got to the guest. This function
397 * checks whether in a nested guest, we need to inject them to L1 or L2.
399 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
401 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
402 unsigned int nr = vcpu->arch.exception.nr;
403 bool has_payload = vcpu->arch.exception.has_payload;
404 unsigned long payload = vcpu->arch.exception.payload;
406 if (nr == PF_VECTOR) {
407 if (vcpu->arch.exception.nested_apf) {
408 *exit_qual = vcpu->arch.apf.nested_apf_token;
411 if (nested_vmx_is_page_fault_vmexit(vmcs12,
412 vcpu->arch.exception.error_code)) {
413 *exit_qual = has_payload ? payload : vcpu->arch.cr2;
416 } else if (vmcs12->exception_bitmap & (1u << nr)) {
417 if (nr == DB_VECTOR) {
419 payload = vcpu->arch.dr6;
421 payload ^= DR6_ACTIVE_LOW;
423 *exit_qual = payload;
433 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
434 struct x86_exception *fault)
436 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
438 WARN_ON(!is_guest_mode(vcpu));
440 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
441 !to_vmx(vcpu)->nested.nested_run_pending) {
442 vmcs12->vm_exit_intr_error_code = fault->error_code;
443 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
444 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
445 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
448 kvm_inject_page_fault(vcpu, fault);
452 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
453 struct vmcs12 *vmcs12)
455 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
458 if (CC(!page_address_valid(vcpu, vmcs12->io_bitmap_a)) ||
459 CC(!page_address_valid(vcpu, vmcs12->io_bitmap_b)))
465 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
466 struct vmcs12 *vmcs12)
468 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
471 if (CC(!page_address_valid(vcpu, vmcs12->msr_bitmap)))
477 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
478 struct vmcs12 *vmcs12)
480 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
483 if (CC(!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr)))
490 * Check if MSR is intercepted for L01 MSR bitmap.
492 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
494 unsigned long *msr_bitmap;
495 int f = sizeof(unsigned long);
497 if (!cpu_has_vmx_msr_bitmap())
500 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
503 return !!test_bit(msr, msr_bitmap + 0x800 / f);
504 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
506 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
513 * If a msr is allowed by L0, we should check whether it is allowed by L1.
514 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
516 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
517 unsigned long *msr_bitmap_nested,
520 int f = sizeof(unsigned long);
523 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
524 * have the write-low and read-high bitmap offsets the wrong way round.
525 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
528 if (type & MSR_TYPE_R &&
529 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
531 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
533 if (type & MSR_TYPE_W &&
534 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
536 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
538 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
540 if (type & MSR_TYPE_R &&
541 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
543 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
545 if (type & MSR_TYPE_W &&
546 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
548 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
553 static inline void enable_x2apic_msr_intercepts(unsigned long *msr_bitmap)
557 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
558 unsigned word = msr / BITS_PER_LONG;
560 msr_bitmap[word] = ~0;
561 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
566 * Merge L0's and L1's MSR bitmap, return false to indicate that
567 * we do not use the hardware.
569 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
570 struct vmcs12 *vmcs12)
573 unsigned long *msr_bitmap_l1;
574 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
575 struct kvm_host_map *map = &to_vmx(vcpu)->nested.msr_bitmap_map;
577 /* Nothing to do if the MSR bitmap is not in use. */
578 if (!cpu_has_vmx_msr_bitmap() ||
579 !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
582 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->msr_bitmap), map))
585 msr_bitmap_l1 = (unsigned long *)map->hva;
588 * To keep the control flow simple, pay eight 8-byte writes (sixteen
589 * 4-byte writes on 32-bit systems) up front to enable intercepts for
590 * the x2APIC MSR range and selectively disable them below.
592 enable_x2apic_msr_intercepts(msr_bitmap_l0);
594 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
595 if (nested_cpu_has_apic_reg_virt(vmcs12)) {
597 * L0 need not intercept reads for MSRs between 0x800
598 * and 0x8ff, it just lets the processor take the value
599 * from the virtual-APIC page; take those 256 bits
600 * directly from the L1 bitmap.
602 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
603 unsigned word = msr / BITS_PER_LONG;
605 msr_bitmap_l0[word] = msr_bitmap_l1[word];
609 nested_vmx_disable_intercept_for_msr(
610 msr_bitmap_l1, msr_bitmap_l0,
611 X2APIC_MSR(APIC_TASKPRI),
612 MSR_TYPE_R | MSR_TYPE_W);
614 if (nested_cpu_has_vid(vmcs12)) {
615 nested_vmx_disable_intercept_for_msr(
616 msr_bitmap_l1, msr_bitmap_l0,
617 X2APIC_MSR(APIC_EOI),
619 nested_vmx_disable_intercept_for_msr(
620 msr_bitmap_l1, msr_bitmap_l0,
621 X2APIC_MSR(APIC_SELF_IPI),
626 /* KVM unconditionally exposes the FS/GS base MSRs to L1. */
628 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0,
629 MSR_FS_BASE, MSR_TYPE_RW);
631 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0,
632 MSR_GS_BASE, MSR_TYPE_RW);
634 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0,
635 MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
639 * Checking the L0->L1 bitmap is trying to verify two things:
641 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
642 * ensures that we do not accidentally generate an L02 MSR bitmap
643 * from the L12 MSR bitmap that is too permissive.
644 * 2. That L1 or L2s have actually used the MSR. This avoids
645 * unnecessarily merging of the bitmap if the MSR is unused. This
646 * works properly because we only update the L01 MSR bitmap lazily.
647 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
648 * updated to reflect this when L1 (or its L2s) actually write to
651 if (!msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL))
652 nested_vmx_disable_intercept_for_msr(
653 msr_bitmap_l1, msr_bitmap_l0,
655 MSR_TYPE_R | MSR_TYPE_W);
657 if (!msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD))
658 nested_vmx_disable_intercept_for_msr(
659 msr_bitmap_l1, msr_bitmap_l0,
663 kvm_vcpu_unmap(vcpu, &to_vmx(vcpu)->nested.msr_bitmap_map, false);
668 static void nested_cache_shadow_vmcs12(struct kvm_vcpu *vcpu,
669 struct vmcs12 *vmcs12)
671 struct kvm_host_map map;
672 struct vmcs12 *shadow;
674 if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
675 vmcs12->vmcs_link_pointer == -1ull)
678 shadow = get_shadow_vmcs12(vcpu);
680 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->vmcs_link_pointer), &map))
683 memcpy(shadow, map.hva, VMCS12_SIZE);
684 kvm_vcpu_unmap(vcpu, &map, false);
687 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu *vcpu,
688 struct vmcs12 *vmcs12)
690 struct vcpu_vmx *vmx = to_vmx(vcpu);
692 if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
693 vmcs12->vmcs_link_pointer == -1ull)
696 kvm_write_guest(vmx->vcpu.kvm, vmcs12->vmcs_link_pointer,
697 get_shadow_vmcs12(vcpu), VMCS12_SIZE);
701 * In nested virtualization, check if L1 has set
702 * VM_EXIT_ACK_INTR_ON_EXIT
704 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
706 return get_vmcs12(vcpu)->vm_exit_controls &
707 VM_EXIT_ACK_INTR_ON_EXIT;
710 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
711 struct vmcs12 *vmcs12)
713 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
714 CC(!page_address_valid(vcpu, vmcs12->apic_access_addr)))
720 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
721 struct vmcs12 *vmcs12)
723 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
724 !nested_cpu_has_apic_reg_virt(vmcs12) &&
725 !nested_cpu_has_vid(vmcs12) &&
726 !nested_cpu_has_posted_intr(vmcs12))
730 * If virtualize x2apic mode is enabled,
731 * virtualize apic access must be disabled.
733 if (CC(nested_cpu_has_virt_x2apic_mode(vmcs12) &&
734 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)))
738 * If virtual interrupt delivery is enabled,
739 * we must exit on external interrupts.
741 if (CC(nested_cpu_has_vid(vmcs12) && !nested_exit_on_intr(vcpu)))
745 * bits 15:8 should be zero in posted_intr_nv,
746 * the descriptor address has been already checked
747 * in nested_get_vmcs12_pages.
749 * bits 5:0 of posted_intr_desc_addr should be zero.
751 if (nested_cpu_has_posted_intr(vmcs12) &&
752 (CC(!nested_cpu_has_vid(vmcs12)) ||
753 CC(!nested_exit_intr_ack_set(vcpu)) ||
754 CC((vmcs12->posted_intr_nv & 0xff00)) ||
755 CC(!kvm_vcpu_is_legal_aligned_gpa(vcpu, vmcs12->posted_intr_desc_addr, 64))))
758 /* tpr shadow is needed by all apicv features. */
759 if (CC(!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)))
765 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
771 if (!kvm_vcpu_is_legal_aligned_gpa(vcpu, addr, 16) ||
772 !kvm_vcpu_is_legal_gpa(vcpu, (addr + count * sizeof(struct vmx_msr_entry) - 1)))
778 static int nested_vmx_check_exit_msr_switch_controls(struct kvm_vcpu *vcpu,
779 struct vmcs12 *vmcs12)
781 if (CC(nested_vmx_check_msr_switch(vcpu,
782 vmcs12->vm_exit_msr_load_count,
783 vmcs12->vm_exit_msr_load_addr)) ||
784 CC(nested_vmx_check_msr_switch(vcpu,
785 vmcs12->vm_exit_msr_store_count,
786 vmcs12->vm_exit_msr_store_addr)))
792 static int nested_vmx_check_entry_msr_switch_controls(struct kvm_vcpu *vcpu,
793 struct vmcs12 *vmcs12)
795 if (CC(nested_vmx_check_msr_switch(vcpu,
796 vmcs12->vm_entry_msr_load_count,
797 vmcs12->vm_entry_msr_load_addr)))
803 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
804 struct vmcs12 *vmcs12)
806 if (!nested_cpu_has_pml(vmcs12))
809 if (CC(!nested_cpu_has_ept(vmcs12)) ||
810 CC(!page_address_valid(vcpu, vmcs12->pml_address)))
816 static int nested_vmx_check_unrestricted_guest_controls(struct kvm_vcpu *vcpu,
817 struct vmcs12 *vmcs12)
819 if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST) &&
820 !nested_cpu_has_ept(vmcs12)))
825 static int nested_vmx_check_mode_based_ept_exec_controls(struct kvm_vcpu *vcpu,
826 struct vmcs12 *vmcs12)
828 if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_MODE_BASED_EPT_EXEC) &&
829 !nested_cpu_has_ept(vmcs12)))
834 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu *vcpu,
835 struct vmcs12 *vmcs12)
837 if (!nested_cpu_has_shadow_vmcs(vmcs12))
840 if (CC(!page_address_valid(vcpu, vmcs12->vmread_bitmap)) ||
841 CC(!page_address_valid(vcpu, vmcs12->vmwrite_bitmap)))
847 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
848 struct vmx_msr_entry *e)
850 /* x2APIC MSR accesses are not allowed */
851 if (CC(vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8))
853 if (CC(e->index == MSR_IA32_UCODE_WRITE) || /* SDM Table 35-2 */
854 CC(e->index == MSR_IA32_UCODE_REV))
856 if (CC(e->reserved != 0))
861 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
862 struct vmx_msr_entry *e)
864 if (CC(e->index == MSR_FS_BASE) ||
865 CC(e->index == MSR_GS_BASE) ||
866 CC(e->index == MSR_IA32_SMM_MONITOR_CTL) || /* SMM is not supported */
867 nested_vmx_msr_check_common(vcpu, e))
872 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
873 struct vmx_msr_entry *e)
875 if (CC(e->index == MSR_IA32_SMBASE) || /* SMM is not supported */
876 nested_vmx_msr_check_common(vcpu, e))
881 static u32 nested_vmx_max_atomic_switch_msrs(struct kvm_vcpu *vcpu)
883 struct vcpu_vmx *vmx = to_vmx(vcpu);
884 u64 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
885 vmx->nested.msrs.misc_high);
887 return (vmx_misc_max_msr(vmx_misc) + 1) * VMX_MISC_MSR_LIST_MULTIPLIER;
891 * Load guest's/host's msr at nested entry/exit.
892 * return 0 for success, entry index for failure.
894 * One of the failure modes for MSR load/store is when a list exceeds the
895 * virtual hardware's capacity. To maintain compatibility with hardware inasmuch
896 * as possible, process all valid entries before failing rather than precheck
897 * for a capacity violation.
899 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
902 struct vmx_msr_entry e;
903 u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu);
905 for (i = 0; i < count; i++) {
906 if (unlikely(i >= max_msr_list_size))
909 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
911 pr_debug_ratelimited(
912 "%s cannot read MSR entry (%u, 0x%08llx)\n",
913 __func__, i, gpa + i * sizeof(e));
916 if (nested_vmx_load_msr_check(vcpu, &e)) {
917 pr_debug_ratelimited(
918 "%s check failed (%u, 0x%x, 0x%x)\n",
919 __func__, i, e.index, e.reserved);
922 if (kvm_set_msr(vcpu, e.index, e.value)) {
923 pr_debug_ratelimited(
924 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
925 __func__, i, e.index, e.value);
931 /* Note, max_msr_list_size is at most 4096, i.e. this can't wrap. */
935 static bool nested_vmx_get_vmexit_msr_value(struct kvm_vcpu *vcpu,
939 struct vcpu_vmx *vmx = to_vmx(vcpu);
942 * If the L0 hypervisor stored a more accurate value for the TSC that
943 * does not include the time taken for emulation of the L2->L1
944 * VM-exit in L0, use the more accurate value.
946 if (msr_index == MSR_IA32_TSC) {
947 int i = vmx_find_loadstore_msr_slot(&vmx->msr_autostore.guest,
951 u64 val = vmx->msr_autostore.guest.val[i].value;
953 *data = kvm_read_l1_tsc(vcpu, val);
958 if (kvm_get_msr(vcpu, msr_index, data)) {
959 pr_debug_ratelimited("%s cannot read MSR (0x%x)\n", __func__,
966 static bool read_and_check_msr_entry(struct kvm_vcpu *vcpu, u64 gpa, int i,
967 struct vmx_msr_entry *e)
969 if (kvm_vcpu_read_guest(vcpu,
970 gpa + i * sizeof(*e),
971 e, 2 * sizeof(u32))) {
972 pr_debug_ratelimited(
973 "%s cannot read MSR entry (%u, 0x%08llx)\n",
974 __func__, i, gpa + i * sizeof(*e));
977 if (nested_vmx_store_msr_check(vcpu, e)) {
978 pr_debug_ratelimited(
979 "%s check failed (%u, 0x%x, 0x%x)\n",
980 __func__, i, e->index, e->reserved);
986 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
990 struct vmx_msr_entry e;
991 u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu);
993 for (i = 0; i < count; i++) {
994 if (unlikely(i >= max_msr_list_size))
997 if (!read_and_check_msr_entry(vcpu, gpa, i, &e))
1000 if (!nested_vmx_get_vmexit_msr_value(vcpu, e.index, &data))
1003 if (kvm_vcpu_write_guest(vcpu,
1004 gpa + i * sizeof(e) +
1005 offsetof(struct vmx_msr_entry, value),
1006 &data, sizeof(data))) {
1007 pr_debug_ratelimited(
1008 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
1009 __func__, i, e.index, data);
1016 static bool nested_msr_store_list_has_msr(struct kvm_vcpu *vcpu, u32 msr_index)
1018 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1019 u32 count = vmcs12->vm_exit_msr_store_count;
1020 u64 gpa = vmcs12->vm_exit_msr_store_addr;
1021 struct vmx_msr_entry e;
1024 for (i = 0; i < count; i++) {
1025 if (!read_and_check_msr_entry(vcpu, gpa, i, &e))
1028 if (e.index == msr_index)
1034 static void prepare_vmx_msr_autostore_list(struct kvm_vcpu *vcpu,
1037 struct vcpu_vmx *vmx = to_vmx(vcpu);
1038 struct vmx_msrs *autostore = &vmx->msr_autostore.guest;
1039 bool in_vmcs12_store_list;
1040 int msr_autostore_slot;
1041 bool in_autostore_list;
1044 msr_autostore_slot = vmx_find_loadstore_msr_slot(autostore, msr_index);
1045 in_autostore_list = msr_autostore_slot >= 0;
1046 in_vmcs12_store_list = nested_msr_store_list_has_msr(vcpu, msr_index);
1048 if (in_vmcs12_store_list && !in_autostore_list) {
1049 if (autostore->nr == MAX_NR_LOADSTORE_MSRS) {
1051 * Emulated VMEntry does not fail here. Instead a less
1052 * accurate value will be returned by
1053 * nested_vmx_get_vmexit_msr_value() using kvm_get_msr()
1054 * instead of reading the value from the vmcs02 VMExit
1057 pr_warn_ratelimited(
1058 "Not enough msr entries in msr_autostore. Can't add msr %x\n",
1062 last = autostore->nr++;
1063 autostore->val[last].index = msr_index;
1064 } else if (!in_vmcs12_store_list && in_autostore_list) {
1065 last = --autostore->nr;
1066 autostore->val[msr_autostore_slot] = autostore->val[last];
1071 * Load guest's/host's cr3 at nested entry/exit. @nested_ept is true if we are
1072 * emulating VM-Entry into a guest with EPT enabled. On failure, the expected
1073 * Exit Qualification (for a VM-Entry consistency check VM-Exit) is assigned to
1074 * @entry_failure_code.
1076 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3,
1077 bool nested_ept, bool reload_pdptrs,
1078 enum vm_entry_failure_code *entry_failure_code)
1080 if (CC(kvm_vcpu_is_illegal_gpa(vcpu, cr3))) {
1081 *entry_failure_code = ENTRY_FAIL_DEFAULT;
1086 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
1087 * must not be dereferenced.
1089 if (reload_pdptrs && !nested_ept && is_pae_paging(vcpu) &&
1090 CC(!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))) {
1091 *entry_failure_code = ENTRY_FAIL_PDPTE;
1096 kvm_mmu_new_pgd(vcpu, cr3);
1098 vcpu->arch.cr3 = cr3;
1099 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1101 /* Re-initialize the MMU, e.g. to pick up CR4 MMU role changes. */
1108 * Returns if KVM is able to config CPU to tag TLB entries
1109 * populated by L2 differently than TLB entries populated
1112 * If L0 uses EPT, L1 and L2 run with different EPTP because
1113 * guest_mode is part of kvm_mmu_page_role. Thus, TLB entries
1114 * are tagged with different EPTP.
1116 * If L1 uses VPID and we allocated a vpid02, TLB entries are tagged
1117 * with different VPID (L1 entries are tagged with vmx->vpid
1118 * while L2 entries are tagged with vmx->nested.vpid02).
1120 static bool nested_has_guest_tlb_tag(struct kvm_vcpu *vcpu)
1122 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1124 return enable_ept ||
1125 (nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02);
1128 static void nested_vmx_transition_tlb_flush(struct kvm_vcpu *vcpu,
1129 struct vmcs12 *vmcs12,
1132 struct vcpu_vmx *vmx = to_vmx(vcpu);
1135 * If vmcs12 doesn't use VPID, L1 expects linear and combined mappings
1136 * for *all* contexts to be flushed on VM-Enter/VM-Exit, i.e. it's a
1137 * full TLB flush from the guest's perspective. This is required even
1138 * if VPID is disabled in the host as KVM may need to synchronize the
1139 * MMU in response to the guest TLB flush.
1141 * Note, using TLB_FLUSH_GUEST is correct even if nested EPT is in use.
1142 * EPT is a special snowflake, as guest-physical mappings aren't
1143 * flushed on VPID invalidations, including VM-Enter or VM-Exit with
1144 * VPID disabled. As a result, KVM _never_ needs to sync nEPT
1145 * entries on VM-Enter because L1 can't rely on VM-Enter to flush
1148 if (!nested_cpu_has_vpid(vmcs12)) {
1149 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1153 /* L2 should never have a VPID if VPID is disabled. */
1154 WARN_ON(!enable_vpid);
1157 * If VPID is enabled and used by vmc12, but L2 does not have a unique
1158 * TLB tag (ASID), i.e. EPT is disabled and KVM was unable to allocate
1159 * a VPID for L2, flush the current context as the effective ASID is
1160 * common to both L1 and L2.
1162 * Defer the flush so that it runs after vmcs02.EPTP has been set by
1163 * KVM_REQ_LOAD_MMU_PGD (if nested EPT is enabled) and to avoid
1164 * redundant flushes further down the nested pipeline.
1166 * If a TLB flush isn't required due to any of the above, and vpid12 is
1167 * changing then the new "virtual" VPID (vpid12) will reuse the same
1168 * "real" VPID (vpid02), and so needs to be flushed. There's no direct
1169 * mapping between vpid02 and vpid12, vpid02 is per-vCPU and reused for
1170 * all nested vCPUs. Remember, a flush on VM-Enter does not invalidate
1171 * guest-physical mappings, so there is no need to sync the nEPT MMU.
1173 if (!nested_has_guest_tlb_tag(vcpu)) {
1174 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1175 } else if (is_vmenter &&
1176 vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
1177 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
1178 vpid_sync_context(nested_get_vpid02(vcpu));
1182 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
1187 return (superset | subset) == superset;
1190 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
1192 const u64 feature_and_reserved =
1193 /* feature (except bit 48; see below) */
1194 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
1196 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
1197 u64 vmx_basic = vmx->nested.msrs.basic;
1199 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
1203 * KVM does not emulate a version of VMX that constrains physical
1204 * addresses of VMX structures (e.g. VMCS) to 32-bits.
1206 if (data & BIT_ULL(48))
1209 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
1210 vmx_basic_vmcs_revision_id(data))
1213 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
1216 vmx->nested.msrs.basic = data;
1221 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
1226 switch (msr_index) {
1227 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1228 lowp = &vmx->nested.msrs.pinbased_ctls_low;
1229 highp = &vmx->nested.msrs.pinbased_ctls_high;
1231 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1232 lowp = &vmx->nested.msrs.procbased_ctls_low;
1233 highp = &vmx->nested.msrs.procbased_ctls_high;
1235 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1236 lowp = &vmx->nested.msrs.exit_ctls_low;
1237 highp = &vmx->nested.msrs.exit_ctls_high;
1239 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1240 lowp = &vmx->nested.msrs.entry_ctls_low;
1241 highp = &vmx->nested.msrs.entry_ctls_high;
1243 case MSR_IA32_VMX_PROCBASED_CTLS2:
1244 lowp = &vmx->nested.msrs.secondary_ctls_low;
1245 highp = &vmx->nested.msrs.secondary_ctls_high;
1251 supported = vmx_control_msr(*lowp, *highp);
1253 /* Check must-be-1 bits are still 1. */
1254 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
1257 /* Check must-be-0 bits are still 0. */
1258 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
1262 *highp = data >> 32;
1266 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
1268 const u64 feature_and_reserved_bits =
1270 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
1271 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
1273 GENMASK_ULL(13, 9) | BIT_ULL(31);
1276 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
1277 vmx->nested.msrs.misc_high);
1279 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
1282 if ((vmx->nested.msrs.pinbased_ctls_high &
1283 PIN_BASED_VMX_PREEMPTION_TIMER) &&
1284 vmx_misc_preemption_timer_rate(data) !=
1285 vmx_misc_preemption_timer_rate(vmx_misc))
1288 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
1291 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
1294 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
1297 vmx->nested.msrs.misc_low = data;
1298 vmx->nested.msrs.misc_high = data >> 32;
1303 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
1305 u64 vmx_ept_vpid_cap;
1307 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
1308 vmx->nested.msrs.vpid_caps);
1310 /* Every bit is either reserved or a feature bit. */
1311 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
1314 vmx->nested.msrs.ept_caps = data;
1315 vmx->nested.msrs.vpid_caps = data >> 32;
1319 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
1323 switch (msr_index) {
1324 case MSR_IA32_VMX_CR0_FIXED0:
1325 msr = &vmx->nested.msrs.cr0_fixed0;
1327 case MSR_IA32_VMX_CR4_FIXED0:
1328 msr = &vmx->nested.msrs.cr4_fixed0;
1335 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
1336 * must be 1 in the restored value.
1338 if (!is_bitwise_subset(data, *msr, -1ULL))
1346 * Called when userspace is restoring VMX MSRs.
1348 * Returns 0 on success, non-0 otherwise.
1350 int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1352 struct vcpu_vmx *vmx = to_vmx(vcpu);
1355 * Don't allow changes to the VMX capability MSRs while the vCPU
1356 * is in VMX operation.
1358 if (vmx->nested.vmxon)
1361 switch (msr_index) {
1362 case MSR_IA32_VMX_BASIC:
1363 return vmx_restore_vmx_basic(vmx, data);
1364 case MSR_IA32_VMX_PINBASED_CTLS:
1365 case MSR_IA32_VMX_PROCBASED_CTLS:
1366 case MSR_IA32_VMX_EXIT_CTLS:
1367 case MSR_IA32_VMX_ENTRY_CTLS:
1369 * The "non-true" VMX capability MSRs are generated from the
1370 * "true" MSRs, so we do not support restoring them directly.
1372 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
1373 * should restore the "true" MSRs with the must-be-1 bits
1374 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
1375 * DEFAULT SETTINGS".
1378 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1379 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1380 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1381 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1382 case MSR_IA32_VMX_PROCBASED_CTLS2:
1383 return vmx_restore_control_msr(vmx, msr_index, data);
1384 case MSR_IA32_VMX_MISC:
1385 return vmx_restore_vmx_misc(vmx, data);
1386 case MSR_IA32_VMX_CR0_FIXED0:
1387 case MSR_IA32_VMX_CR4_FIXED0:
1388 return vmx_restore_fixed0_msr(vmx, msr_index, data);
1389 case MSR_IA32_VMX_CR0_FIXED1:
1390 case MSR_IA32_VMX_CR4_FIXED1:
1392 * These MSRs are generated based on the vCPU's CPUID, so we
1393 * do not support restoring them directly.
1396 case MSR_IA32_VMX_EPT_VPID_CAP:
1397 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
1398 case MSR_IA32_VMX_VMCS_ENUM:
1399 vmx->nested.msrs.vmcs_enum = data;
1401 case MSR_IA32_VMX_VMFUNC:
1402 if (data & ~vmx->nested.msrs.vmfunc_controls)
1404 vmx->nested.msrs.vmfunc_controls = data;
1408 * The rest of the VMX capability MSRs do not support restore.
1414 /* Returns 0 on success, non-0 otherwise. */
1415 int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
1417 switch (msr_index) {
1418 case MSR_IA32_VMX_BASIC:
1419 *pdata = msrs->basic;
1421 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1422 case MSR_IA32_VMX_PINBASED_CTLS:
1423 *pdata = vmx_control_msr(
1424 msrs->pinbased_ctls_low,
1425 msrs->pinbased_ctls_high);
1426 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
1427 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
1429 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1430 case MSR_IA32_VMX_PROCBASED_CTLS:
1431 *pdata = vmx_control_msr(
1432 msrs->procbased_ctls_low,
1433 msrs->procbased_ctls_high);
1434 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
1435 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
1437 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1438 case MSR_IA32_VMX_EXIT_CTLS:
1439 *pdata = vmx_control_msr(
1440 msrs->exit_ctls_low,
1441 msrs->exit_ctls_high);
1442 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
1443 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
1445 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1446 case MSR_IA32_VMX_ENTRY_CTLS:
1447 *pdata = vmx_control_msr(
1448 msrs->entry_ctls_low,
1449 msrs->entry_ctls_high);
1450 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
1451 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
1453 case MSR_IA32_VMX_MISC:
1454 *pdata = vmx_control_msr(
1458 case MSR_IA32_VMX_CR0_FIXED0:
1459 *pdata = msrs->cr0_fixed0;
1461 case MSR_IA32_VMX_CR0_FIXED1:
1462 *pdata = msrs->cr0_fixed1;
1464 case MSR_IA32_VMX_CR4_FIXED0:
1465 *pdata = msrs->cr4_fixed0;
1467 case MSR_IA32_VMX_CR4_FIXED1:
1468 *pdata = msrs->cr4_fixed1;
1470 case MSR_IA32_VMX_VMCS_ENUM:
1471 *pdata = msrs->vmcs_enum;
1473 case MSR_IA32_VMX_PROCBASED_CTLS2:
1474 *pdata = vmx_control_msr(
1475 msrs->secondary_ctls_low,
1476 msrs->secondary_ctls_high);
1478 case MSR_IA32_VMX_EPT_VPID_CAP:
1479 *pdata = msrs->ept_caps |
1480 ((u64)msrs->vpid_caps << 32);
1482 case MSR_IA32_VMX_VMFUNC:
1483 *pdata = msrs->vmfunc_controls;
1493 * Copy the writable VMCS shadow fields back to the VMCS12, in case they have
1494 * been modified by the L1 guest. Note, "writable" in this context means
1495 * "writable by the guest", i.e. tagged SHADOW_FIELD_RW; the set of
1496 * fields tagged SHADOW_FIELD_RO may or may not align with the "read-only"
1497 * VM-exit information fields (which are actually writable if the vCPU is
1498 * configured to support "VMWRITE to any supported field in the VMCS").
1500 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
1502 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
1503 struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu);
1504 struct shadow_vmcs_field field;
1508 if (WARN_ON(!shadow_vmcs))
1513 vmcs_load(shadow_vmcs);
1515 for (i = 0; i < max_shadow_read_write_fields; i++) {
1516 field = shadow_read_write_fields[i];
1517 val = __vmcs_readl(field.encoding);
1518 vmcs12_write_any(vmcs12, field.encoding, field.offset, val);
1521 vmcs_clear(shadow_vmcs);
1522 vmcs_load(vmx->loaded_vmcs->vmcs);
1527 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
1529 const struct shadow_vmcs_field *fields[] = {
1530 shadow_read_write_fields,
1531 shadow_read_only_fields
1533 const int max_fields[] = {
1534 max_shadow_read_write_fields,
1535 max_shadow_read_only_fields
1537 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
1538 struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu);
1539 struct shadow_vmcs_field field;
1543 if (WARN_ON(!shadow_vmcs))
1546 vmcs_load(shadow_vmcs);
1548 for (q = 0; q < ARRAY_SIZE(fields); q++) {
1549 for (i = 0; i < max_fields[q]; i++) {
1550 field = fields[q][i];
1551 val = vmcs12_read_any(vmcs12, field.encoding,
1553 __vmcs_writel(field.encoding, val);
1557 vmcs_clear(shadow_vmcs);
1558 vmcs_load(vmx->loaded_vmcs->vmcs);
1561 static void copy_enlightened_to_vmcs12(struct vcpu_vmx *vmx, u32 hv_clean_fields)
1563 struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12;
1564 struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs;
1566 /* HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE */
1567 vmcs12->tpr_threshold = evmcs->tpr_threshold;
1568 vmcs12->guest_rip = evmcs->guest_rip;
1570 if (unlikely(!(hv_clean_fields &
1571 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC))) {
1572 vmcs12->guest_rsp = evmcs->guest_rsp;
1573 vmcs12->guest_rflags = evmcs->guest_rflags;
1574 vmcs12->guest_interruptibility_info =
1575 evmcs->guest_interruptibility_info;
1578 if (unlikely(!(hv_clean_fields &
1579 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC))) {
1580 vmcs12->cpu_based_vm_exec_control =
1581 evmcs->cpu_based_vm_exec_control;
1584 if (unlikely(!(hv_clean_fields &
1585 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN))) {
1586 vmcs12->exception_bitmap = evmcs->exception_bitmap;
1589 if (unlikely(!(hv_clean_fields &
1590 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY))) {
1591 vmcs12->vm_entry_controls = evmcs->vm_entry_controls;
1594 if (unlikely(!(hv_clean_fields &
1595 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT))) {
1596 vmcs12->vm_entry_intr_info_field =
1597 evmcs->vm_entry_intr_info_field;
1598 vmcs12->vm_entry_exception_error_code =
1599 evmcs->vm_entry_exception_error_code;
1600 vmcs12->vm_entry_instruction_len =
1601 evmcs->vm_entry_instruction_len;
1604 if (unlikely(!(hv_clean_fields &
1605 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1))) {
1606 vmcs12->host_ia32_pat = evmcs->host_ia32_pat;
1607 vmcs12->host_ia32_efer = evmcs->host_ia32_efer;
1608 vmcs12->host_cr0 = evmcs->host_cr0;
1609 vmcs12->host_cr3 = evmcs->host_cr3;
1610 vmcs12->host_cr4 = evmcs->host_cr4;
1611 vmcs12->host_ia32_sysenter_esp = evmcs->host_ia32_sysenter_esp;
1612 vmcs12->host_ia32_sysenter_eip = evmcs->host_ia32_sysenter_eip;
1613 vmcs12->host_rip = evmcs->host_rip;
1614 vmcs12->host_ia32_sysenter_cs = evmcs->host_ia32_sysenter_cs;
1615 vmcs12->host_es_selector = evmcs->host_es_selector;
1616 vmcs12->host_cs_selector = evmcs->host_cs_selector;
1617 vmcs12->host_ss_selector = evmcs->host_ss_selector;
1618 vmcs12->host_ds_selector = evmcs->host_ds_selector;
1619 vmcs12->host_fs_selector = evmcs->host_fs_selector;
1620 vmcs12->host_gs_selector = evmcs->host_gs_selector;
1621 vmcs12->host_tr_selector = evmcs->host_tr_selector;
1624 if (unlikely(!(hv_clean_fields &
1625 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1))) {
1626 vmcs12->pin_based_vm_exec_control =
1627 evmcs->pin_based_vm_exec_control;
1628 vmcs12->vm_exit_controls = evmcs->vm_exit_controls;
1629 vmcs12->secondary_vm_exec_control =
1630 evmcs->secondary_vm_exec_control;
1633 if (unlikely(!(hv_clean_fields &
1634 HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP))) {
1635 vmcs12->io_bitmap_a = evmcs->io_bitmap_a;
1636 vmcs12->io_bitmap_b = evmcs->io_bitmap_b;
1639 if (unlikely(!(hv_clean_fields &
1640 HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP))) {
1641 vmcs12->msr_bitmap = evmcs->msr_bitmap;
1644 if (unlikely(!(hv_clean_fields &
1645 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2))) {
1646 vmcs12->guest_es_base = evmcs->guest_es_base;
1647 vmcs12->guest_cs_base = evmcs->guest_cs_base;
1648 vmcs12->guest_ss_base = evmcs->guest_ss_base;
1649 vmcs12->guest_ds_base = evmcs->guest_ds_base;
1650 vmcs12->guest_fs_base = evmcs->guest_fs_base;
1651 vmcs12->guest_gs_base = evmcs->guest_gs_base;
1652 vmcs12->guest_ldtr_base = evmcs->guest_ldtr_base;
1653 vmcs12->guest_tr_base = evmcs->guest_tr_base;
1654 vmcs12->guest_gdtr_base = evmcs->guest_gdtr_base;
1655 vmcs12->guest_idtr_base = evmcs->guest_idtr_base;
1656 vmcs12->guest_es_limit = evmcs->guest_es_limit;
1657 vmcs12->guest_cs_limit = evmcs->guest_cs_limit;
1658 vmcs12->guest_ss_limit = evmcs->guest_ss_limit;
1659 vmcs12->guest_ds_limit = evmcs->guest_ds_limit;
1660 vmcs12->guest_fs_limit = evmcs->guest_fs_limit;
1661 vmcs12->guest_gs_limit = evmcs->guest_gs_limit;
1662 vmcs12->guest_ldtr_limit = evmcs->guest_ldtr_limit;
1663 vmcs12->guest_tr_limit = evmcs->guest_tr_limit;
1664 vmcs12->guest_gdtr_limit = evmcs->guest_gdtr_limit;
1665 vmcs12->guest_idtr_limit = evmcs->guest_idtr_limit;
1666 vmcs12->guest_es_ar_bytes = evmcs->guest_es_ar_bytes;
1667 vmcs12->guest_cs_ar_bytes = evmcs->guest_cs_ar_bytes;
1668 vmcs12->guest_ss_ar_bytes = evmcs->guest_ss_ar_bytes;
1669 vmcs12->guest_ds_ar_bytes = evmcs->guest_ds_ar_bytes;
1670 vmcs12->guest_fs_ar_bytes = evmcs->guest_fs_ar_bytes;
1671 vmcs12->guest_gs_ar_bytes = evmcs->guest_gs_ar_bytes;
1672 vmcs12->guest_ldtr_ar_bytes = evmcs->guest_ldtr_ar_bytes;
1673 vmcs12->guest_tr_ar_bytes = evmcs->guest_tr_ar_bytes;
1674 vmcs12->guest_es_selector = evmcs->guest_es_selector;
1675 vmcs12->guest_cs_selector = evmcs->guest_cs_selector;
1676 vmcs12->guest_ss_selector = evmcs->guest_ss_selector;
1677 vmcs12->guest_ds_selector = evmcs->guest_ds_selector;
1678 vmcs12->guest_fs_selector = evmcs->guest_fs_selector;
1679 vmcs12->guest_gs_selector = evmcs->guest_gs_selector;
1680 vmcs12->guest_ldtr_selector = evmcs->guest_ldtr_selector;
1681 vmcs12->guest_tr_selector = evmcs->guest_tr_selector;
1684 if (unlikely(!(hv_clean_fields &
1685 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2))) {
1686 vmcs12->tsc_offset = evmcs->tsc_offset;
1687 vmcs12->virtual_apic_page_addr = evmcs->virtual_apic_page_addr;
1688 vmcs12->xss_exit_bitmap = evmcs->xss_exit_bitmap;
1691 if (unlikely(!(hv_clean_fields &
1692 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR))) {
1693 vmcs12->cr0_guest_host_mask = evmcs->cr0_guest_host_mask;
1694 vmcs12->cr4_guest_host_mask = evmcs->cr4_guest_host_mask;
1695 vmcs12->cr0_read_shadow = evmcs->cr0_read_shadow;
1696 vmcs12->cr4_read_shadow = evmcs->cr4_read_shadow;
1697 vmcs12->guest_cr0 = evmcs->guest_cr0;
1698 vmcs12->guest_cr3 = evmcs->guest_cr3;
1699 vmcs12->guest_cr4 = evmcs->guest_cr4;
1700 vmcs12->guest_dr7 = evmcs->guest_dr7;
1703 if (unlikely(!(hv_clean_fields &
1704 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER))) {
1705 vmcs12->host_fs_base = evmcs->host_fs_base;
1706 vmcs12->host_gs_base = evmcs->host_gs_base;
1707 vmcs12->host_tr_base = evmcs->host_tr_base;
1708 vmcs12->host_gdtr_base = evmcs->host_gdtr_base;
1709 vmcs12->host_idtr_base = evmcs->host_idtr_base;
1710 vmcs12->host_rsp = evmcs->host_rsp;
1713 if (unlikely(!(hv_clean_fields &
1714 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT))) {
1715 vmcs12->ept_pointer = evmcs->ept_pointer;
1716 vmcs12->virtual_processor_id = evmcs->virtual_processor_id;
1719 if (unlikely(!(hv_clean_fields &
1720 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1))) {
1721 vmcs12->vmcs_link_pointer = evmcs->vmcs_link_pointer;
1722 vmcs12->guest_ia32_debugctl = evmcs->guest_ia32_debugctl;
1723 vmcs12->guest_ia32_pat = evmcs->guest_ia32_pat;
1724 vmcs12->guest_ia32_efer = evmcs->guest_ia32_efer;
1725 vmcs12->guest_pdptr0 = evmcs->guest_pdptr0;
1726 vmcs12->guest_pdptr1 = evmcs->guest_pdptr1;
1727 vmcs12->guest_pdptr2 = evmcs->guest_pdptr2;
1728 vmcs12->guest_pdptr3 = evmcs->guest_pdptr3;
1729 vmcs12->guest_pending_dbg_exceptions =
1730 evmcs->guest_pending_dbg_exceptions;
1731 vmcs12->guest_sysenter_esp = evmcs->guest_sysenter_esp;
1732 vmcs12->guest_sysenter_eip = evmcs->guest_sysenter_eip;
1733 vmcs12->guest_bndcfgs = evmcs->guest_bndcfgs;
1734 vmcs12->guest_activity_state = evmcs->guest_activity_state;
1735 vmcs12->guest_sysenter_cs = evmcs->guest_sysenter_cs;
1740 * vmcs12->vm_exit_msr_store_addr = evmcs->vm_exit_msr_store_addr;
1741 * vmcs12->vm_exit_msr_load_addr = evmcs->vm_exit_msr_load_addr;
1742 * vmcs12->vm_entry_msr_load_addr = evmcs->vm_entry_msr_load_addr;
1743 * vmcs12->page_fault_error_code_mask =
1744 * evmcs->page_fault_error_code_mask;
1745 * vmcs12->page_fault_error_code_match =
1746 * evmcs->page_fault_error_code_match;
1747 * vmcs12->cr3_target_count = evmcs->cr3_target_count;
1748 * vmcs12->vm_exit_msr_store_count = evmcs->vm_exit_msr_store_count;
1749 * vmcs12->vm_exit_msr_load_count = evmcs->vm_exit_msr_load_count;
1750 * vmcs12->vm_entry_msr_load_count = evmcs->vm_entry_msr_load_count;
1755 * vmcs12->guest_physical_address = evmcs->guest_physical_address;
1756 * vmcs12->vm_instruction_error = evmcs->vm_instruction_error;
1757 * vmcs12->vm_exit_reason = evmcs->vm_exit_reason;
1758 * vmcs12->vm_exit_intr_info = evmcs->vm_exit_intr_info;
1759 * vmcs12->vm_exit_intr_error_code = evmcs->vm_exit_intr_error_code;
1760 * vmcs12->idt_vectoring_info_field = evmcs->idt_vectoring_info_field;
1761 * vmcs12->idt_vectoring_error_code = evmcs->idt_vectoring_error_code;
1762 * vmcs12->vm_exit_instruction_len = evmcs->vm_exit_instruction_len;
1763 * vmcs12->vmx_instruction_info = evmcs->vmx_instruction_info;
1764 * vmcs12->exit_qualification = evmcs->exit_qualification;
1765 * vmcs12->guest_linear_address = evmcs->guest_linear_address;
1767 * Not present in struct vmcs12:
1768 * vmcs12->exit_io_instruction_ecx = evmcs->exit_io_instruction_ecx;
1769 * vmcs12->exit_io_instruction_esi = evmcs->exit_io_instruction_esi;
1770 * vmcs12->exit_io_instruction_edi = evmcs->exit_io_instruction_edi;
1771 * vmcs12->exit_io_instruction_eip = evmcs->exit_io_instruction_eip;
1777 static void copy_vmcs12_to_enlightened(struct vcpu_vmx *vmx)
1779 struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12;
1780 struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs;
1783 * Should not be changed by KVM:
1785 * evmcs->host_es_selector = vmcs12->host_es_selector;
1786 * evmcs->host_cs_selector = vmcs12->host_cs_selector;
1787 * evmcs->host_ss_selector = vmcs12->host_ss_selector;
1788 * evmcs->host_ds_selector = vmcs12->host_ds_selector;
1789 * evmcs->host_fs_selector = vmcs12->host_fs_selector;
1790 * evmcs->host_gs_selector = vmcs12->host_gs_selector;
1791 * evmcs->host_tr_selector = vmcs12->host_tr_selector;
1792 * evmcs->host_ia32_pat = vmcs12->host_ia32_pat;
1793 * evmcs->host_ia32_efer = vmcs12->host_ia32_efer;
1794 * evmcs->host_cr0 = vmcs12->host_cr0;
1795 * evmcs->host_cr3 = vmcs12->host_cr3;
1796 * evmcs->host_cr4 = vmcs12->host_cr4;
1797 * evmcs->host_ia32_sysenter_esp = vmcs12->host_ia32_sysenter_esp;
1798 * evmcs->host_ia32_sysenter_eip = vmcs12->host_ia32_sysenter_eip;
1799 * evmcs->host_rip = vmcs12->host_rip;
1800 * evmcs->host_ia32_sysenter_cs = vmcs12->host_ia32_sysenter_cs;
1801 * evmcs->host_fs_base = vmcs12->host_fs_base;
1802 * evmcs->host_gs_base = vmcs12->host_gs_base;
1803 * evmcs->host_tr_base = vmcs12->host_tr_base;
1804 * evmcs->host_gdtr_base = vmcs12->host_gdtr_base;
1805 * evmcs->host_idtr_base = vmcs12->host_idtr_base;
1806 * evmcs->host_rsp = vmcs12->host_rsp;
1807 * sync_vmcs02_to_vmcs12() doesn't read these:
1808 * evmcs->io_bitmap_a = vmcs12->io_bitmap_a;
1809 * evmcs->io_bitmap_b = vmcs12->io_bitmap_b;
1810 * evmcs->msr_bitmap = vmcs12->msr_bitmap;
1811 * evmcs->ept_pointer = vmcs12->ept_pointer;
1812 * evmcs->xss_exit_bitmap = vmcs12->xss_exit_bitmap;
1813 * evmcs->vm_exit_msr_store_addr = vmcs12->vm_exit_msr_store_addr;
1814 * evmcs->vm_exit_msr_load_addr = vmcs12->vm_exit_msr_load_addr;
1815 * evmcs->vm_entry_msr_load_addr = vmcs12->vm_entry_msr_load_addr;
1816 * evmcs->tpr_threshold = vmcs12->tpr_threshold;
1817 * evmcs->virtual_processor_id = vmcs12->virtual_processor_id;
1818 * evmcs->exception_bitmap = vmcs12->exception_bitmap;
1819 * evmcs->vmcs_link_pointer = vmcs12->vmcs_link_pointer;
1820 * evmcs->pin_based_vm_exec_control = vmcs12->pin_based_vm_exec_control;
1821 * evmcs->vm_exit_controls = vmcs12->vm_exit_controls;
1822 * evmcs->secondary_vm_exec_control = vmcs12->secondary_vm_exec_control;
1823 * evmcs->page_fault_error_code_mask =
1824 * vmcs12->page_fault_error_code_mask;
1825 * evmcs->page_fault_error_code_match =
1826 * vmcs12->page_fault_error_code_match;
1827 * evmcs->cr3_target_count = vmcs12->cr3_target_count;
1828 * evmcs->virtual_apic_page_addr = vmcs12->virtual_apic_page_addr;
1829 * evmcs->tsc_offset = vmcs12->tsc_offset;
1830 * evmcs->guest_ia32_debugctl = vmcs12->guest_ia32_debugctl;
1831 * evmcs->cr0_guest_host_mask = vmcs12->cr0_guest_host_mask;
1832 * evmcs->cr4_guest_host_mask = vmcs12->cr4_guest_host_mask;
1833 * evmcs->cr0_read_shadow = vmcs12->cr0_read_shadow;
1834 * evmcs->cr4_read_shadow = vmcs12->cr4_read_shadow;
1835 * evmcs->vm_exit_msr_store_count = vmcs12->vm_exit_msr_store_count;
1836 * evmcs->vm_exit_msr_load_count = vmcs12->vm_exit_msr_load_count;
1837 * evmcs->vm_entry_msr_load_count = vmcs12->vm_entry_msr_load_count;
1839 * Not present in struct vmcs12:
1840 * evmcs->exit_io_instruction_ecx = vmcs12->exit_io_instruction_ecx;
1841 * evmcs->exit_io_instruction_esi = vmcs12->exit_io_instruction_esi;
1842 * evmcs->exit_io_instruction_edi = vmcs12->exit_io_instruction_edi;
1843 * evmcs->exit_io_instruction_eip = vmcs12->exit_io_instruction_eip;
1846 evmcs->guest_es_selector = vmcs12->guest_es_selector;
1847 evmcs->guest_cs_selector = vmcs12->guest_cs_selector;
1848 evmcs->guest_ss_selector = vmcs12->guest_ss_selector;
1849 evmcs->guest_ds_selector = vmcs12->guest_ds_selector;
1850 evmcs->guest_fs_selector = vmcs12->guest_fs_selector;
1851 evmcs->guest_gs_selector = vmcs12->guest_gs_selector;
1852 evmcs->guest_ldtr_selector = vmcs12->guest_ldtr_selector;
1853 evmcs->guest_tr_selector = vmcs12->guest_tr_selector;
1855 evmcs->guest_es_limit = vmcs12->guest_es_limit;
1856 evmcs->guest_cs_limit = vmcs12->guest_cs_limit;
1857 evmcs->guest_ss_limit = vmcs12->guest_ss_limit;
1858 evmcs->guest_ds_limit = vmcs12->guest_ds_limit;
1859 evmcs->guest_fs_limit = vmcs12->guest_fs_limit;
1860 evmcs->guest_gs_limit = vmcs12->guest_gs_limit;
1861 evmcs->guest_ldtr_limit = vmcs12->guest_ldtr_limit;
1862 evmcs->guest_tr_limit = vmcs12->guest_tr_limit;
1863 evmcs->guest_gdtr_limit = vmcs12->guest_gdtr_limit;
1864 evmcs->guest_idtr_limit = vmcs12->guest_idtr_limit;
1866 evmcs->guest_es_ar_bytes = vmcs12->guest_es_ar_bytes;
1867 evmcs->guest_cs_ar_bytes = vmcs12->guest_cs_ar_bytes;
1868 evmcs->guest_ss_ar_bytes = vmcs12->guest_ss_ar_bytes;
1869 evmcs->guest_ds_ar_bytes = vmcs12->guest_ds_ar_bytes;
1870 evmcs->guest_fs_ar_bytes = vmcs12->guest_fs_ar_bytes;
1871 evmcs->guest_gs_ar_bytes = vmcs12->guest_gs_ar_bytes;
1872 evmcs->guest_ldtr_ar_bytes = vmcs12->guest_ldtr_ar_bytes;
1873 evmcs->guest_tr_ar_bytes = vmcs12->guest_tr_ar_bytes;
1875 evmcs->guest_es_base = vmcs12->guest_es_base;
1876 evmcs->guest_cs_base = vmcs12->guest_cs_base;
1877 evmcs->guest_ss_base = vmcs12->guest_ss_base;
1878 evmcs->guest_ds_base = vmcs12->guest_ds_base;
1879 evmcs->guest_fs_base = vmcs12->guest_fs_base;
1880 evmcs->guest_gs_base = vmcs12->guest_gs_base;
1881 evmcs->guest_ldtr_base = vmcs12->guest_ldtr_base;
1882 evmcs->guest_tr_base = vmcs12->guest_tr_base;
1883 evmcs->guest_gdtr_base = vmcs12->guest_gdtr_base;
1884 evmcs->guest_idtr_base = vmcs12->guest_idtr_base;
1886 evmcs->guest_ia32_pat = vmcs12->guest_ia32_pat;
1887 evmcs->guest_ia32_efer = vmcs12->guest_ia32_efer;
1889 evmcs->guest_pdptr0 = vmcs12->guest_pdptr0;
1890 evmcs->guest_pdptr1 = vmcs12->guest_pdptr1;
1891 evmcs->guest_pdptr2 = vmcs12->guest_pdptr2;
1892 evmcs->guest_pdptr3 = vmcs12->guest_pdptr3;
1894 evmcs->guest_pending_dbg_exceptions =
1895 vmcs12->guest_pending_dbg_exceptions;
1896 evmcs->guest_sysenter_esp = vmcs12->guest_sysenter_esp;
1897 evmcs->guest_sysenter_eip = vmcs12->guest_sysenter_eip;
1899 evmcs->guest_activity_state = vmcs12->guest_activity_state;
1900 evmcs->guest_sysenter_cs = vmcs12->guest_sysenter_cs;
1902 evmcs->guest_cr0 = vmcs12->guest_cr0;
1903 evmcs->guest_cr3 = vmcs12->guest_cr3;
1904 evmcs->guest_cr4 = vmcs12->guest_cr4;
1905 evmcs->guest_dr7 = vmcs12->guest_dr7;
1907 evmcs->guest_physical_address = vmcs12->guest_physical_address;
1909 evmcs->vm_instruction_error = vmcs12->vm_instruction_error;
1910 evmcs->vm_exit_reason = vmcs12->vm_exit_reason;
1911 evmcs->vm_exit_intr_info = vmcs12->vm_exit_intr_info;
1912 evmcs->vm_exit_intr_error_code = vmcs12->vm_exit_intr_error_code;
1913 evmcs->idt_vectoring_info_field = vmcs12->idt_vectoring_info_field;
1914 evmcs->idt_vectoring_error_code = vmcs12->idt_vectoring_error_code;
1915 evmcs->vm_exit_instruction_len = vmcs12->vm_exit_instruction_len;
1916 evmcs->vmx_instruction_info = vmcs12->vmx_instruction_info;
1918 evmcs->exit_qualification = vmcs12->exit_qualification;
1920 evmcs->guest_linear_address = vmcs12->guest_linear_address;
1921 evmcs->guest_rsp = vmcs12->guest_rsp;
1922 evmcs->guest_rflags = vmcs12->guest_rflags;
1924 evmcs->guest_interruptibility_info =
1925 vmcs12->guest_interruptibility_info;
1926 evmcs->cpu_based_vm_exec_control = vmcs12->cpu_based_vm_exec_control;
1927 evmcs->vm_entry_controls = vmcs12->vm_entry_controls;
1928 evmcs->vm_entry_intr_info_field = vmcs12->vm_entry_intr_info_field;
1929 evmcs->vm_entry_exception_error_code =
1930 vmcs12->vm_entry_exception_error_code;
1931 evmcs->vm_entry_instruction_len = vmcs12->vm_entry_instruction_len;
1933 evmcs->guest_rip = vmcs12->guest_rip;
1935 evmcs->guest_bndcfgs = vmcs12->guest_bndcfgs;
1941 * This is an equivalent of the nested hypervisor executing the vmptrld
1944 static enum nested_evmptrld_status nested_vmx_handle_enlightened_vmptrld(
1945 struct kvm_vcpu *vcpu, bool from_launch)
1947 struct vcpu_vmx *vmx = to_vmx(vcpu);
1948 bool evmcs_gpa_changed = false;
1951 if (likely(!vmx->nested.enlightened_vmcs_enabled))
1952 return EVMPTRLD_DISABLED;
1954 if (!nested_enlightened_vmentry(vcpu, &evmcs_gpa)) {
1955 nested_release_evmcs(vcpu);
1956 return EVMPTRLD_DISABLED;
1959 if (unlikely(evmcs_gpa != vmx->nested.hv_evmcs_vmptr)) {
1960 vmx->nested.current_vmptr = -1ull;
1962 nested_release_evmcs(vcpu);
1964 if (kvm_vcpu_map(vcpu, gpa_to_gfn(evmcs_gpa),
1965 &vmx->nested.hv_evmcs_map))
1966 return EVMPTRLD_ERROR;
1968 vmx->nested.hv_evmcs = vmx->nested.hv_evmcs_map.hva;
1971 * Currently, KVM only supports eVMCS version 1
1972 * (== KVM_EVMCS_VERSION) and thus we expect guest to set this
1973 * value to first u32 field of eVMCS which should specify eVMCS
1976 * Guest should be aware of supported eVMCS versions by host by
1977 * examining CPUID.0x4000000A.EAX[0:15]. Host userspace VMM is
1978 * expected to set this CPUID leaf according to the value
1979 * returned in vmcs_version from nested_enable_evmcs().
1981 * However, it turns out that Microsoft Hyper-V fails to comply
1982 * to their own invented interface: When Hyper-V use eVMCS, it
1983 * just sets first u32 field of eVMCS to revision_id specified
1984 * in MSR_IA32_VMX_BASIC. Instead of used eVMCS version number
1985 * which is one of the supported versions specified in
1986 * CPUID.0x4000000A.EAX[0:15].
1988 * To overcome Hyper-V bug, we accept here either a supported
1989 * eVMCS version or VMCS12 revision_id as valid values for first
1990 * u32 field of eVMCS.
1992 if ((vmx->nested.hv_evmcs->revision_id != KVM_EVMCS_VERSION) &&
1993 (vmx->nested.hv_evmcs->revision_id != VMCS12_REVISION)) {
1994 nested_release_evmcs(vcpu);
1995 return EVMPTRLD_VMFAIL;
1998 vmx->nested.hv_evmcs_vmptr = evmcs_gpa;
2000 evmcs_gpa_changed = true;
2002 * Unlike normal vmcs12, enlightened vmcs12 is not fully
2003 * reloaded from guest's memory (read only fields, fields not
2004 * present in struct hv_enlightened_vmcs, ...). Make sure there
2008 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2009 memset(vmcs12, 0, sizeof(*vmcs12));
2010 vmcs12->hdr.revision_id = VMCS12_REVISION;
2016 * Clean fields data can't be used on VMLAUNCH and when we switch
2017 * between different L2 guests as KVM keeps a single VMCS12 per L1.
2019 if (from_launch || evmcs_gpa_changed)
2020 vmx->nested.hv_evmcs->hv_clean_fields &=
2021 ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
2023 return EVMPTRLD_SUCCEEDED;
2026 void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu)
2028 struct vcpu_vmx *vmx = to_vmx(vcpu);
2030 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
2031 copy_vmcs12_to_enlightened(vmx);
2033 copy_vmcs12_to_shadow(vmx);
2035 vmx->nested.need_vmcs12_to_shadow_sync = false;
2038 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
2040 struct vcpu_vmx *vmx =
2041 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
2043 vmx->nested.preemption_timer_expired = true;
2044 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
2045 kvm_vcpu_kick(&vmx->vcpu);
2047 return HRTIMER_NORESTART;
2050 static u64 vmx_calc_preemption_timer_value(struct kvm_vcpu *vcpu)
2052 struct vcpu_vmx *vmx = to_vmx(vcpu);
2053 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2055 u64 l1_scaled_tsc = kvm_read_l1_tsc(vcpu, rdtsc()) >>
2056 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
2058 if (!vmx->nested.has_preemption_timer_deadline) {
2059 vmx->nested.preemption_timer_deadline =
2060 vmcs12->vmx_preemption_timer_value + l1_scaled_tsc;
2061 vmx->nested.has_preemption_timer_deadline = true;
2063 return vmx->nested.preemption_timer_deadline - l1_scaled_tsc;
2066 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu,
2067 u64 preemption_timeout)
2069 struct vcpu_vmx *vmx = to_vmx(vcpu);
2072 * A timer value of zero is architecturally guaranteed to cause
2073 * a VMExit prior to executing any instructions in the guest.
2075 if (preemption_timeout == 0) {
2076 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
2080 if (vcpu->arch.virtual_tsc_khz == 0)
2083 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
2084 preemption_timeout *= 1000000;
2085 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
2086 hrtimer_start(&vmx->nested.preemption_timer,
2087 ktime_add_ns(ktime_get(), preemption_timeout),
2088 HRTIMER_MODE_ABS_PINNED);
2091 static u64 nested_vmx_calc_efer(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
2093 if (vmx->nested.nested_run_pending &&
2094 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
2095 return vmcs12->guest_ia32_efer;
2096 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
2097 return vmx->vcpu.arch.efer | (EFER_LMA | EFER_LME);
2099 return vmx->vcpu.arch.efer & ~(EFER_LMA | EFER_LME);
2102 static void prepare_vmcs02_constant_state(struct vcpu_vmx *vmx)
2105 * If vmcs02 hasn't been initialized, set the constant vmcs02 state
2106 * according to L0's settings (vmcs12 is irrelevant here). Host
2107 * fields that come from L0 and are not constant, e.g. HOST_CR3,
2108 * will be set as needed prior to VMLAUNCH/VMRESUME.
2110 if (vmx->nested.vmcs02_initialized)
2112 vmx->nested.vmcs02_initialized = true;
2115 * We don't care what the EPTP value is we just need to guarantee
2116 * it's valid so we don't get a false positive when doing early
2117 * consistency checks.
2119 if (enable_ept && nested_early_check)
2120 vmcs_write64(EPT_POINTER,
2121 construct_eptp(&vmx->vcpu, 0, PT64_ROOT_4LEVEL));
2123 /* All VMFUNCs are currently emulated through L0 vmexits. */
2124 if (cpu_has_vmx_vmfunc())
2125 vmcs_write64(VM_FUNCTION_CONTROL, 0);
2127 if (cpu_has_vmx_posted_intr())
2128 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
2130 if (cpu_has_vmx_msr_bitmap())
2131 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
2134 * PML is emulated for L2, but never enabled in hardware as the MMU
2135 * handles A/D emulation. Disabling PML for L2 also avoids having to
2136 * deal with filtering out L2 GPAs from the buffer.
2139 vmcs_write64(PML_ADDRESS, 0);
2140 vmcs_write16(GUEST_PML_INDEX, -1);
2143 if (cpu_has_vmx_encls_vmexit())
2144 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
2147 * Set the MSR load/store lists to match L0's settings. Only the
2148 * addresses are constant (for vmcs02), the counts can change based
2149 * on L2's behavior, e.g. switching to/from long mode.
2151 vmcs_write64(VM_EXIT_MSR_STORE_ADDR, __pa(vmx->msr_autostore.guest.val));
2152 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2153 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
2155 vmx_set_constant_host_state(vmx);
2158 static void prepare_vmcs02_early_rare(struct vcpu_vmx *vmx,
2159 struct vmcs12 *vmcs12)
2161 prepare_vmcs02_constant_state(vmx);
2163 vmcs_write64(VMCS_LINK_POINTER, -1ull);
2166 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
2167 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
2169 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2173 static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
2176 u64 guest_efer = nested_vmx_calc_efer(vmx, vmcs12);
2178 if (vmx->nested.dirty_vmcs12 || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
2179 prepare_vmcs02_early_rare(vmx, vmcs12);
2184 exec_control = vmx_pin_based_exec_ctrl(vmx);
2185 exec_control |= (vmcs12->pin_based_vm_exec_control &
2186 ~PIN_BASED_VMX_PREEMPTION_TIMER);
2188 /* Posted interrupts setting is only taken from vmcs12. */
2189 if (nested_cpu_has_posted_intr(vmcs12)) {
2190 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
2191 vmx->nested.pi_pending = false;
2193 exec_control &= ~PIN_BASED_POSTED_INTR;
2195 pin_controls_set(vmx, exec_control);
2200 exec_control = vmx_exec_control(vmx); /* L0's desires */
2201 exec_control &= ~CPU_BASED_INTR_WINDOW_EXITING;
2202 exec_control &= ~CPU_BASED_NMI_WINDOW_EXITING;
2203 exec_control &= ~CPU_BASED_TPR_SHADOW;
2204 exec_control |= vmcs12->cpu_based_vm_exec_control;
2206 vmx->nested.l1_tpr_threshold = -1;
2207 if (exec_control & CPU_BASED_TPR_SHADOW)
2208 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
2209 #ifdef CONFIG_X86_64
2211 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
2212 CPU_BASED_CR8_STORE_EXITING;
2216 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
2217 * for I/O port accesses.
2219 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
2220 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
2223 * This bit will be computed in nested_get_vmcs12_pages, because
2224 * we do not have access to L1's MSR bitmap yet. For now, keep
2225 * the same bit as before, hoping to avoid multiple VMWRITEs that
2226 * only set/clear this bit.
2228 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
2229 exec_control |= exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS;
2231 exec_controls_set(vmx, exec_control);
2234 * SECONDARY EXEC CONTROLS
2236 if (cpu_has_secondary_exec_ctrls()) {
2237 exec_control = vmx->secondary_exec_control;
2239 /* Take the following fields only from vmcs12 */
2240 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2241 SECONDARY_EXEC_ENABLE_INVPCID |
2242 SECONDARY_EXEC_ENABLE_RDTSCP |
2243 SECONDARY_EXEC_XSAVES |
2244 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2245 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2246 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2247 SECONDARY_EXEC_ENABLE_VMFUNC |
2248 SECONDARY_EXEC_TSC_SCALING);
2249 if (nested_cpu_has(vmcs12,
2250 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
2251 exec_control |= vmcs12->secondary_vm_exec_control;
2253 /* PML is emulated and never enabled in hardware for L2. */
2254 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
2256 /* VMCS shadowing for L2 is emulated for now */
2257 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
2260 * Preset *DT exiting when emulating UMIP, so that vmx_set_cr4()
2261 * will not have to rewrite the controls just for this bit.
2263 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated() &&
2264 (vmcs12->guest_cr4 & X86_CR4_UMIP))
2265 exec_control |= SECONDARY_EXEC_DESC;
2267 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
2268 vmcs_write16(GUEST_INTR_STATUS,
2269 vmcs12->guest_intr_status);
2271 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
2272 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2274 if (exec_control & SECONDARY_EXEC_ENCLS_EXITING)
2275 vmx_write_encls_bitmap(&vmx->vcpu, vmcs12);
2277 secondary_exec_controls_set(vmx, exec_control);
2283 * vmcs12's VM_{ENTRY,EXIT}_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE
2284 * are emulated by vmx_set_efer() in prepare_vmcs02(), but speculate
2285 * on the related bits (if supported by the CPU) in the hope that
2286 * we can avoid VMWrites during vmx_set_efer().
2288 exec_control = (vmcs12->vm_entry_controls | vmx_vmentry_ctrl()) &
2289 ~VM_ENTRY_IA32E_MODE & ~VM_ENTRY_LOAD_IA32_EFER;
2290 if (cpu_has_load_ia32_efer()) {
2291 if (guest_efer & EFER_LMA)
2292 exec_control |= VM_ENTRY_IA32E_MODE;
2293 if (guest_efer != host_efer)
2294 exec_control |= VM_ENTRY_LOAD_IA32_EFER;
2296 vm_entry_controls_set(vmx, exec_control);
2301 * L2->L1 exit controls are emulated - the hardware exit is to L0 so
2302 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
2303 * bits may be modified by vmx_set_efer() in prepare_vmcs02().
2305 exec_control = vmx_vmexit_ctrl();
2306 if (cpu_has_load_ia32_efer() && guest_efer != host_efer)
2307 exec_control |= VM_EXIT_LOAD_IA32_EFER;
2308 vm_exit_controls_set(vmx, exec_control);
2311 * Interrupt/Exception Fields
2313 if (vmx->nested.nested_run_pending) {
2314 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2315 vmcs12->vm_entry_intr_info_field);
2316 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2317 vmcs12->vm_entry_exception_error_code);
2318 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2319 vmcs12->vm_entry_instruction_len);
2320 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
2321 vmcs12->guest_interruptibility_info);
2322 vmx->loaded_vmcs->nmi_known_unmasked =
2323 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
2325 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
2329 static void prepare_vmcs02_rare(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
2331 struct hv_enlightened_vmcs *hv_evmcs = vmx->nested.hv_evmcs;
2333 if (!hv_evmcs || !(hv_evmcs->hv_clean_fields &
2334 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2)) {
2335 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
2336 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
2337 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
2338 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
2339 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
2340 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
2341 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
2342 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
2343 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
2344 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
2345 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
2346 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
2347 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
2348 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
2349 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
2350 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
2351 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
2352 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
2353 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
2354 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
2355 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
2356 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
2357 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
2358 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
2359 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
2360 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
2361 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
2362 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
2363 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
2364 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
2365 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
2366 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
2367 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
2368 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
2369 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
2370 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
2372 vmx->segment_cache.bitmask = 0;
2375 if (!hv_evmcs || !(hv_evmcs->hv_clean_fields &
2376 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1)) {
2377 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
2378 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
2379 vmcs12->guest_pending_dbg_exceptions);
2380 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
2381 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
2384 * L1 may access the L2's PDPTR, so save them to construct
2388 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
2389 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
2390 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
2391 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
2394 if (kvm_mpx_supported() && vmx->nested.nested_run_pending &&
2395 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
2396 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
2399 if (nested_cpu_has_xsaves(vmcs12))
2400 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
2403 * Whether page-faults are trapped is determined by a combination of
2404 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. If L0
2405 * doesn't care about page faults then we should set all of these to
2406 * L1's desires. However, if L0 does care about (some) page faults, it
2407 * is not easy (if at all possible?) to merge L0 and L1's desires, we
2408 * simply ask to exit on each and every L2 page fault. This is done by
2409 * setting MASK=MATCH=0 and (see below) EB.PF=1.
2410 * Note that below we don't need special code to set EB.PF beyond the
2411 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
2412 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
2413 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
2415 if (vmx_need_pf_intercept(&vmx->vcpu)) {
2417 * TODO: if both L0 and L1 need the same MASK and MATCH,
2418 * go ahead and use it?
2420 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
2421 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
2423 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, vmcs12->page_fault_error_code_mask);
2424 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, vmcs12->page_fault_error_code_match);
2427 if (cpu_has_vmx_apicv()) {
2428 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
2429 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
2430 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
2431 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
2435 * Make sure the msr_autostore list is up to date before we set the
2436 * count in the vmcs02.
2438 prepare_vmx_msr_autostore_list(&vmx->vcpu, MSR_IA32_TSC);
2440 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, vmx->msr_autostore.guest.nr);
2441 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
2442 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
2444 set_cr4_guest_host_mask(vmx);
2448 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
2449 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
2450 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
2451 * guest in a way that will both be appropriate to L1's requests, and our
2452 * needs. In addition to modifying the active vmcs (which is vmcs02), this
2453 * function also has additional necessary side-effects, like setting various
2454 * vcpu->arch fields.
2455 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
2456 * is assigned to entry_failure_code on failure.
2458 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
2460 enum vm_entry_failure_code *entry_failure_code)
2462 struct vcpu_vmx *vmx = to_vmx(vcpu);
2463 bool load_guest_pdptrs_vmcs12 = false;
2465 if (vmx->nested.dirty_vmcs12 || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) {
2466 prepare_vmcs02_rare(vmx, vmcs12);
2467 vmx->nested.dirty_vmcs12 = false;
2469 load_guest_pdptrs_vmcs12 = !evmptr_is_valid(vmx->nested.hv_evmcs_vmptr) ||
2470 !(vmx->nested.hv_evmcs->hv_clean_fields &
2471 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1);
2474 if (vmx->nested.nested_run_pending &&
2475 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
2476 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
2477 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
2479 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
2480 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
2482 if (kvm_mpx_supported() && (!vmx->nested.nested_run_pending ||
2483 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)))
2484 vmcs_write64(GUEST_BNDCFGS, vmx->nested.vmcs01_guest_bndcfgs);
2485 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
2487 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
2488 * bitwise-or of what L1 wants to trap for L2, and what we want to
2489 * trap. Note that CR0.TS also needs updating - we do this later.
2491 vmx_update_exception_bitmap(vcpu);
2492 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
2493 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2495 if (vmx->nested.nested_run_pending &&
2496 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
2497 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
2498 vcpu->arch.pat = vmcs12->guest_ia32_pat;
2499 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2500 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
2503 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2504 vcpu->arch.l1_tsc_offset,
2505 vmx_get_l2_tsc_offset(vcpu),
2506 vmx_get_l2_tsc_multiplier(vcpu));
2508 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2509 vcpu->arch.l1_tsc_scaling_ratio,
2510 vmx_get_l2_tsc_multiplier(vcpu));
2512 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
2513 if (kvm_has_tsc_control)
2514 vmcs_write64(TSC_MULTIPLIER, vcpu->arch.tsc_scaling_ratio);
2516 nested_vmx_transition_tlb_flush(vcpu, vmcs12, true);
2518 if (nested_cpu_has_ept(vmcs12))
2519 nested_ept_init_mmu_context(vcpu);
2522 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
2523 * bits which we consider mandatory enabled.
2524 * The CR0_READ_SHADOW is what L2 should have expected to read given
2525 * the specifications by L1; It's not enough to take
2526 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
2527 * have more bits than L1 expected.
2529 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
2530 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2532 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
2533 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
2535 vcpu->arch.efer = nested_vmx_calc_efer(vmx, vmcs12);
2536 /* Note: may modify VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
2537 vmx_set_efer(vcpu, vcpu->arch.efer);
2540 * Guest state is invalid and unrestricted guest is disabled,
2541 * which means L1 attempted VMEntry to L2 with invalid state.
2544 if (CC(!vmx_guest_state_valid(vcpu))) {
2545 *entry_failure_code = ENTRY_FAIL_DEFAULT;
2549 /* Shadow page tables on either EPT or shadow page tables. */
2550 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
2551 from_vmentry, entry_failure_code))
2555 * Immediately write vmcs02.GUEST_CR3. It will be propagated to vmcs12
2556 * on nested VM-Exit, which can occur without actually running L2 and
2557 * thus without hitting vmx_load_mmu_pgd(), e.g. if L1 is entering L2 with
2558 * vmcs12.GUEST_ACTIVITYSTATE=HLT, in which case KVM will intercept the
2559 * transition to HLT instead of running L2.
2562 vmcs_writel(GUEST_CR3, vmcs12->guest_cr3);
2564 /* Late preparation of GUEST_PDPTRs now that EFER and CRs are set. */
2565 if (load_guest_pdptrs_vmcs12 && nested_cpu_has_ept(vmcs12) &&
2566 is_pae_paging(vcpu)) {
2567 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
2568 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
2569 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
2570 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
2574 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
2576 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
2577 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
2578 vmcs12->guest_ia32_perf_global_ctrl)))
2581 kvm_rsp_write(vcpu, vmcs12->guest_rsp);
2582 kvm_rip_write(vcpu, vmcs12->guest_rip);
2585 * It was observed that genuine Hyper-V running in L1 doesn't reset
2586 * 'hv_clean_fields' by itself, it only sets the corresponding dirty
2587 * bits when it changes a field in eVMCS. Mark all fields as clean
2590 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
2591 vmx->nested.hv_evmcs->hv_clean_fields |=
2592 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
2597 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
2599 if (CC(!nested_cpu_has_nmi_exiting(vmcs12) &&
2600 nested_cpu_has_virtual_nmis(vmcs12)))
2603 if (CC(!nested_cpu_has_virtual_nmis(vmcs12) &&
2604 nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING)))
2610 static bool nested_vmx_check_eptp(struct kvm_vcpu *vcpu, u64 new_eptp)
2612 struct vcpu_vmx *vmx = to_vmx(vcpu);
2614 /* Check for memory type validity */
2615 switch (new_eptp & VMX_EPTP_MT_MASK) {
2616 case VMX_EPTP_MT_UC:
2617 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT)))
2620 case VMX_EPTP_MT_WB:
2621 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT)))
2628 /* Page-walk levels validity. */
2629 switch (new_eptp & VMX_EPTP_PWL_MASK) {
2630 case VMX_EPTP_PWL_5:
2631 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_PAGE_WALK_5_BIT)))
2634 case VMX_EPTP_PWL_4:
2635 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_PAGE_WALK_4_BIT)))
2642 /* Reserved bits should not be set */
2643 if (CC(kvm_vcpu_is_illegal_gpa(vcpu, new_eptp) || ((new_eptp >> 7) & 0x1f)))
2646 /* AD, if set, should be supported */
2647 if (new_eptp & VMX_EPTP_AD_ENABLE_BIT) {
2648 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT)))
2656 * Checks related to VM-Execution Control Fields
2658 static int nested_check_vm_execution_controls(struct kvm_vcpu *vcpu,
2659 struct vmcs12 *vmcs12)
2661 struct vcpu_vmx *vmx = to_vmx(vcpu);
2663 if (CC(!vmx_control_verify(vmcs12->pin_based_vm_exec_control,
2664 vmx->nested.msrs.pinbased_ctls_low,
2665 vmx->nested.msrs.pinbased_ctls_high)) ||
2666 CC(!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
2667 vmx->nested.msrs.procbased_ctls_low,
2668 vmx->nested.msrs.procbased_ctls_high)))
2671 if (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
2672 CC(!vmx_control_verify(vmcs12->secondary_vm_exec_control,
2673 vmx->nested.msrs.secondary_ctls_low,
2674 vmx->nested.msrs.secondary_ctls_high)))
2677 if (CC(vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) ||
2678 nested_vmx_check_io_bitmap_controls(vcpu, vmcs12) ||
2679 nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12) ||
2680 nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12) ||
2681 nested_vmx_check_apic_access_controls(vcpu, vmcs12) ||
2682 nested_vmx_check_apicv_controls(vcpu, vmcs12) ||
2683 nested_vmx_check_nmi_controls(vmcs12) ||
2684 nested_vmx_check_pml_controls(vcpu, vmcs12) ||
2685 nested_vmx_check_unrestricted_guest_controls(vcpu, vmcs12) ||
2686 nested_vmx_check_mode_based_ept_exec_controls(vcpu, vmcs12) ||
2687 nested_vmx_check_shadow_vmcs_controls(vcpu, vmcs12) ||
2688 CC(nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id))
2691 if (!nested_cpu_has_preemption_timer(vmcs12) &&
2692 nested_cpu_has_save_preemption_timer(vmcs12))
2695 if (nested_cpu_has_ept(vmcs12) &&
2696 CC(!nested_vmx_check_eptp(vcpu, vmcs12->ept_pointer)))
2699 if (nested_cpu_has_vmfunc(vmcs12)) {
2700 if (CC(vmcs12->vm_function_control &
2701 ~vmx->nested.msrs.vmfunc_controls))
2704 if (nested_cpu_has_eptp_switching(vmcs12)) {
2705 if (CC(!nested_cpu_has_ept(vmcs12)) ||
2706 CC(!page_address_valid(vcpu, vmcs12->eptp_list_address)))
2715 * Checks related to VM-Exit Control Fields
2717 static int nested_check_vm_exit_controls(struct kvm_vcpu *vcpu,
2718 struct vmcs12 *vmcs12)
2720 struct vcpu_vmx *vmx = to_vmx(vcpu);
2722 if (CC(!vmx_control_verify(vmcs12->vm_exit_controls,
2723 vmx->nested.msrs.exit_ctls_low,
2724 vmx->nested.msrs.exit_ctls_high)) ||
2725 CC(nested_vmx_check_exit_msr_switch_controls(vcpu, vmcs12)))
2732 * Checks related to VM-Entry Control Fields
2734 static int nested_check_vm_entry_controls(struct kvm_vcpu *vcpu,
2735 struct vmcs12 *vmcs12)
2737 struct vcpu_vmx *vmx = to_vmx(vcpu);
2739 if (CC(!vmx_control_verify(vmcs12->vm_entry_controls,
2740 vmx->nested.msrs.entry_ctls_low,
2741 vmx->nested.msrs.entry_ctls_high)))
2745 * From the Intel SDM, volume 3:
2746 * Fields relevant to VM-entry event injection must be set properly.
2747 * These fields are the VM-entry interruption-information field, the
2748 * VM-entry exception error code, and the VM-entry instruction length.
2750 if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) {
2751 u32 intr_info = vmcs12->vm_entry_intr_info_field;
2752 u8 vector = intr_info & INTR_INFO_VECTOR_MASK;
2753 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK;
2754 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK;
2755 bool should_have_error_code;
2756 bool urg = nested_cpu_has2(vmcs12,
2757 SECONDARY_EXEC_UNRESTRICTED_GUEST);
2758 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE;
2760 /* VM-entry interruption-info field: interruption type */
2761 if (CC(intr_type == INTR_TYPE_RESERVED) ||
2762 CC(intr_type == INTR_TYPE_OTHER_EVENT &&
2763 !nested_cpu_supports_monitor_trap_flag(vcpu)))
2766 /* VM-entry interruption-info field: vector */
2767 if (CC(intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) ||
2768 CC(intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) ||
2769 CC(intr_type == INTR_TYPE_OTHER_EVENT && vector != 0))
2772 /* VM-entry interruption-info field: deliver error code */
2773 should_have_error_code =
2774 intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode &&
2775 x86_exception_has_error_code(vector);
2776 if (CC(has_error_code != should_have_error_code))
2779 /* VM-entry exception error code */
2780 if (CC(has_error_code &&
2781 vmcs12->vm_entry_exception_error_code & GENMASK(31, 16)))
2784 /* VM-entry interruption-info field: reserved bits */
2785 if (CC(intr_info & INTR_INFO_RESVD_BITS_MASK))
2788 /* VM-entry instruction length */
2789 switch (intr_type) {
2790 case INTR_TYPE_SOFT_EXCEPTION:
2791 case INTR_TYPE_SOFT_INTR:
2792 case INTR_TYPE_PRIV_SW_EXCEPTION:
2793 if (CC(vmcs12->vm_entry_instruction_len > 15) ||
2794 CC(vmcs12->vm_entry_instruction_len == 0 &&
2795 CC(!nested_cpu_has_zero_length_injection(vcpu))))
2800 if (nested_vmx_check_entry_msr_switch_controls(vcpu, vmcs12))
2806 static int nested_vmx_check_controls(struct kvm_vcpu *vcpu,
2807 struct vmcs12 *vmcs12)
2809 if (nested_check_vm_execution_controls(vcpu, vmcs12) ||
2810 nested_check_vm_exit_controls(vcpu, vmcs12) ||
2811 nested_check_vm_entry_controls(vcpu, vmcs12))
2814 if (to_vmx(vcpu)->nested.enlightened_vmcs_enabled)
2815 return nested_evmcs_check_controls(vmcs12);
2820 static int nested_vmx_check_host_state(struct kvm_vcpu *vcpu,
2821 struct vmcs12 *vmcs12)
2825 if (CC(!nested_host_cr0_valid(vcpu, vmcs12->host_cr0)) ||
2826 CC(!nested_host_cr4_valid(vcpu, vmcs12->host_cr4)) ||
2827 CC(kvm_vcpu_is_illegal_gpa(vcpu, vmcs12->host_cr3)))
2830 if (CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_esp, vcpu)) ||
2831 CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_eip, vcpu)))
2834 if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) &&
2835 CC(!kvm_pat_valid(vmcs12->host_ia32_pat)))
2838 if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) &&
2839 CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu),
2840 vmcs12->host_ia32_perf_global_ctrl)))
2843 #ifdef CONFIG_X86_64
2844 ia32e = !!(vcpu->arch.efer & EFER_LMA);
2850 if (CC(!(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)) ||
2851 CC(!(vmcs12->host_cr4 & X86_CR4_PAE)))
2854 if (CC(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) ||
2855 CC(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) ||
2856 CC(vmcs12->host_cr4 & X86_CR4_PCIDE) ||
2857 CC((vmcs12->host_rip) >> 32))
2861 if (CC(vmcs12->host_cs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2862 CC(vmcs12->host_ss_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2863 CC(vmcs12->host_ds_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2864 CC(vmcs12->host_es_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2865 CC(vmcs12->host_fs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2866 CC(vmcs12->host_gs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2867 CC(vmcs12->host_tr_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2868 CC(vmcs12->host_cs_selector == 0) ||
2869 CC(vmcs12->host_tr_selector == 0) ||
2870 CC(vmcs12->host_ss_selector == 0 && !ia32e))
2873 if (CC(is_noncanonical_address(vmcs12->host_fs_base, vcpu)) ||
2874 CC(is_noncanonical_address(vmcs12->host_gs_base, vcpu)) ||
2875 CC(is_noncanonical_address(vmcs12->host_gdtr_base, vcpu)) ||
2876 CC(is_noncanonical_address(vmcs12->host_idtr_base, vcpu)) ||
2877 CC(is_noncanonical_address(vmcs12->host_tr_base, vcpu)) ||
2878 CC(is_noncanonical_address(vmcs12->host_rip, vcpu)))
2882 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
2883 * IA32_EFER MSR must be 0 in the field for that register. In addition,
2884 * the values of the LMA and LME bits in the field must each be that of
2885 * the host address-space size VM-exit control.
2887 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
2888 if (CC(!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer)) ||
2889 CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA)) ||
2890 CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)))
2897 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu,
2898 struct vmcs12 *vmcs12)
2901 struct vmcs12 *shadow;
2902 struct kvm_host_map map;
2904 if (vmcs12->vmcs_link_pointer == -1ull)
2907 if (CC(!page_address_valid(vcpu, vmcs12->vmcs_link_pointer)))
2910 if (CC(kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->vmcs_link_pointer), &map)))
2915 if (CC(shadow->hdr.revision_id != VMCS12_REVISION) ||
2916 CC(shadow->hdr.shadow_vmcs != nested_cpu_has_shadow_vmcs(vmcs12)))
2919 kvm_vcpu_unmap(vcpu, &map, false);
2924 * Checks related to Guest Non-register State
2926 static int nested_check_guest_non_reg_state(struct vmcs12 *vmcs12)
2928 if (CC(vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
2929 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT &&
2930 vmcs12->guest_activity_state != GUEST_ACTIVITY_WAIT_SIPI))
2936 static int nested_vmx_check_guest_state(struct kvm_vcpu *vcpu,
2937 struct vmcs12 *vmcs12,
2938 enum vm_entry_failure_code *entry_failure_code)
2942 *entry_failure_code = ENTRY_FAIL_DEFAULT;
2944 if (CC(!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0)) ||
2945 CC(!nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)))
2948 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) &&
2949 CC(!kvm_dr7_valid(vmcs12->guest_dr7)))
2952 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) &&
2953 CC(!kvm_pat_valid(vmcs12->guest_ia32_pat)))
2956 if (nested_vmx_check_vmcs_link_ptr(vcpu, vmcs12)) {
2957 *entry_failure_code = ENTRY_FAIL_VMCS_LINK_PTR;
2961 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
2962 CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu),
2963 vmcs12->guest_ia32_perf_global_ctrl)))
2967 * If the load IA32_EFER VM-entry control is 1, the following checks
2968 * are performed on the field for the IA32_EFER MSR:
2969 * - Bits reserved in the IA32_EFER MSR must be 0.
2970 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
2971 * the IA-32e mode guest VM-exit control. It must also be identical
2972 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
2975 if (to_vmx(vcpu)->nested.nested_run_pending &&
2976 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
2977 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
2978 if (CC(!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer)) ||
2979 CC(ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA)) ||
2980 CC(((vmcs12->guest_cr0 & X86_CR0_PG) &&
2981 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))))
2985 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
2986 (CC(is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu)) ||
2987 CC((vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD))))
2990 if (nested_check_guest_non_reg_state(vmcs12))
2996 static int nested_vmx_check_vmentry_hw(struct kvm_vcpu *vcpu)
2998 struct vcpu_vmx *vmx = to_vmx(vcpu);
2999 unsigned long cr3, cr4;
3002 if (!nested_early_check)
3005 if (vmx->msr_autoload.host.nr)
3006 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3007 if (vmx->msr_autoload.guest.nr)
3008 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3012 vmx_prepare_switch_to_guest(vcpu);
3015 * Induce a consistency check VMExit by clearing bit 1 in GUEST_RFLAGS,
3016 * which is reserved to '1' by hardware. GUEST_RFLAGS is guaranteed to
3017 * be written (by prepare_vmcs02()) before the "real" VMEnter, i.e.
3018 * there is no need to preserve other bits or save/restore the field.
3020 vmcs_writel(GUEST_RFLAGS, 0);
3022 cr3 = __get_current_cr3_fast();
3023 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
3024 vmcs_writel(HOST_CR3, cr3);
3025 vmx->loaded_vmcs->host_state.cr3 = cr3;
3028 cr4 = cr4_read_shadow();
3029 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
3030 vmcs_writel(HOST_CR4, cr4);
3031 vmx->loaded_vmcs->host_state.cr4 = cr4;
3034 vm_fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
3035 vmx->loaded_vmcs->launched);
3037 if (vmx->msr_autoload.host.nr)
3038 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
3039 if (vmx->msr_autoload.guest.nr)
3040 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
3043 u32 error = vmcs_read32(VM_INSTRUCTION_ERROR);
3047 trace_kvm_nested_vmenter_failed(
3048 "early hardware check VM-instruction error: ", error);
3049 WARN_ON_ONCE(error != VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3054 * VMExit clears RFLAGS.IF and DR7, even on a consistency check.
3056 if (hw_breakpoint_active())
3057 set_debugreg(__this_cpu_read(cpu_dr7), 7);
3062 * A non-failing VMEntry means we somehow entered guest mode with
3063 * an illegal RIP, and that's just the tip of the iceberg. There
3064 * is no telling what memory has been modified or what state has
3065 * been exposed to unknown code. Hitting this all but guarantees
3066 * a (very critical) hardware issue.
3068 WARN_ON(!(vmcs_read32(VM_EXIT_REASON) &
3069 VMX_EXIT_REASONS_FAILED_VMENTRY));
3074 static bool nested_get_evmcs_page(struct kvm_vcpu *vcpu)
3076 struct vcpu_vmx *vmx = to_vmx(vcpu);
3079 * hv_evmcs may end up being not mapped after migration (when
3080 * L2 was running), map it here to make sure vmcs12 changes are
3081 * properly reflected.
3083 if (vmx->nested.enlightened_vmcs_enabled &&
3084 vmx->nested.hv_evmcs_vmptr == EVMPTR_MAP_PENDING) {
3085 enum nested_evmptrld_status evmptrld_status =
3086 nested_vmx_handle_enlightened_vmptrld(vcpu, false);
3088 if (evmptrld_status == EVMPTRLD_VMFAIL ||
3089 evmptrld_status == EVMPTRLD_ERROR)
3093 * Post migration VMCS12 always provides the most actual
3094 * information, copy it to eVMCS upon entry.
3096 vmx->nested.need_vmcs12_to_shadow_sync = true;
3102 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
3104 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3105 struct vcpu_vmx *vmx = to_vmx(vcpu);
3106 struct kvm_host_map *map;
3110 if (!vcpu->arch.pdptrs_from_userspace &&
3111 !nested_cpu_has_ept(vmcs12) && is_pae_paging(vcpu)) {
3113 * Reload the guest's PDPTRs since after a migration
3114 * the guest CR3 might be restored prior to setting the nested
3115 * state which can lead to a load of wrong PDPTRs.
3117 if (CC(!load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3)))
3122 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
3124 * Translate L1 physical address to host physical
3125 * address for vmcs02. Keep the page pinned, so this
3126 * physical address remains valid. We keep a reference
3127 * to it so we can release it later.
3129 if (vmx->nested.apic_access_page) { /* shouldn't happen */
3130 kvm_release_page_clean(vmx->nested.apic_access_page);
3131 vmx->nested.apic_access_page = NULL;
3133 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
3134 if (!is_error_page(page)) {
3135 vmx->nested.apic_access_page = page;
3136 hpa = page_to_phys(vmx->nested.apic_access_page);
3137 vmcs_write64(APIC_ACCESS_ADDR, hpa);
3139 pr_debug_ratelimited("%s: no backing 'struct page' for APIC-access address in vmcs12\n",
3141 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3142 vcpu->run->internal.suberror =
3143 KVM_INTERNAL_ERROR_EMULATION;
3144 vcpu->run->internal.ndata = 0;
3149 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
3150 map = &vmx->nested.virtual_apic_map;
3152 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->virtual_apic_page_addr), map)) {
3153 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, pfn_to_hpa(map->pfn));
3154 } else if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING) &&
3155 nested_cpu_has(vmcs12, CPU_BASED_CR8_STORE_EXITING) &&
3156 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
3158 * The processor will never use the TPR shadow, simply
3159 * clear the bit from the execution control. Such a
3160 * configuration is useless, but it happens in tests.
3161 * For any other configuration, failing the vm entry is
3162 * _not_ what the processor does but it's basically the
3163 * only possibility we have.
3165 exec_controls_clearbit(vmx, CPU_BASED_TPR_SHADOW);
3168 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR to
3169 * force VM-Entry to fail.
3171 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
3175 if (nested_cpu_has_posted_intr(vmcs12)) {
3176 map = &vmx->nested.pi_desc_map;
3178 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->posted_intr_desc_addr), map)) {
3179 vmx->nested.pi_desc =
3180 (struct pi_desc *)(((void *)map->hva) +
3181 offset_in_page(vmcs12->posted_intr_desc_addr));
3182 vmcs_write64(POSTED_INTR_DESC_ADDR,
3183 pfn_to_hpa(map->pfn) + offset_in_page(vmcs12->posted_intr_desc_addr));
3186 * Defer the KVM_INTERNAL_EXIT until KVM tries to
3187 * access the contents of the VMCS12 posted interrupt
3188 * descriptor. (Note that KVM may do this when it
3189 * should not, per the architectural specification.)
3191 vmx->nested.pi_desc = NULL;
3192 pin_controls_clearbit(vmx, PIN_BASED_POSTED_INTR);
3195 if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
3196 exec_controls_setbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
3198 exec_controls_clearbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
3203 static bool vmx_get_nested_state_pages(struct kvm_vcpu *vcpu)
3205 if (!nested_get_evmcs_page(vcpu)) {
3206 pr_debug_ratelimited("%s: enlightened vmptrld failed\n",
3208 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3209 vcpu->run->internal.suberror =
3210 KVM_INTERNAL_ERROR_EMULATION;
3211 vcpu->run->internal.ndata = 0;
3216 if (is_guest_mode(vcpu) && !nested_get_vmcs12_pages(vcpu))
3222 static int nested_vmx_write_pml_buffer(struct kvm_vcpu *vcpu, gpa_t gpa)
3224 struct vmcs12 *vmcs12;
3225 struct vcpu_vmx *vmx = to_vmx(vcpu);
3228 if (WARN_ON_ONCE(!is_guest_mode(vcpu)))
3231 if (WARN_ON_ONCE(vmx->nested.pml_full))
3235 * Check if PML is enabled for the nested guest. Whether eptp bit 6 is
3236 * set is already checked as part of A/D emulation.
3238 vmcs12 = get_vmcs12(vcpu);
3239 if (!nested_cpu_has_pml(vmcs12))
3242 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
3243 vmx->nested.pml_full = true;
3248 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
3250 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
3251 offset_in_page(dst), sizeof(gpa)))
3254 vmcs12->guest_pml_index--;
3260 * Intel's VMX Instruction Reference specifies a common set of prerequisites
3261 * for running VMX instructions (except VMXON, whose prerequisites are
3262 * slightly different). It also specifies what exception to inject otherwise.
3263 * Note that many of these exceptions have priority over VM exits, so they
3264 * don't have to be checked again here.
3266 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
3268 if (!to_vmx(vcpu)->nested.vmxon) {
3269 kvm_queue_exception(vcpu, UD_VECTOR);
3273 if (vmx_get_cpl(vcpu)) {
3274 kvm_inject_gp(vcpu, 0);
3281 static u8 vmx_has_apicv_interrupt(struct kvm_vcpu *vcpu)
3283 u8 rvi = vmx_get_rvi();
3284 u8 vppr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_PROCPRI);
3286 return ((rvi & 0xf0) > (vppr & 0xf0));
3289 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
3290 struct vmcs12 *vmcs12);
3293 * If from_vmentry is false, this is being called from state restore (either RSM
3294 * or KVM_SET_NESTED_STATE). Otherwise it's called from vmlaunch/vmresume.
3297 * NVMX_VMENTRY_SUCCESS: Entered VMX non-root mode
3298 * NVMX_VMENTRY_VMFAIL: Consistency check VMFail
3299 * NVMX_VMENTRY_VMEXIT: Consistency check VMExit
3300 * NVMX_VMENTRY_KVM_INTERNAL_ERROR: KVM internal error
3302 enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
3305 struct vcpu_vmx *vmx = to_vmx(vcpu);
3306 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3307 enum vm_entry_failure_code entry_failure_code;
3308 bool evaluate_pending_interrupts;
3309 union vmx_exit_reason exit_reason = {
3310 .basic = EXIT_REASON_INVALID_STATE,
3311 .failed_vmentry = 1,
3315 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3316 kvm_vcpu_flush_tlb_current(vcpu);
3318 evaluate_pending_interrupts = exec_controls_get(vmx) &
3319 (CPU_BASED_INTR_WINDOW_EXITING | CPU_BASED_NMI_WINDOW_EXITING);
3320 if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu))
3321 evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu);
3323 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
3324 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
3325 if (kvm_mpx_supported() &&
3326 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
3327 vmx->nested.vmcs01_guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
3330 * Overwrite vmcs01.GUEST_CR3 with L1's CR3 if EPT is disabled *and*
3331 * nested early checks are disabled. In the event of a "late" VM-Fail,
3332 * i.e. a VM-Fail detected by hardware but not KVM, KVM must unwind its
3333 * software model to the pre-VMEntry host state. When EPT is disabled,
3334 * GUEST_CR3 holds KVM's shadow CR3, not L1's "real" CR3, which causes
3335 * nested_vmx_restore_host_state() to corrupt vcpu->arch.cr3. Stuffing
3336 * vmcs01.GUEST_CR3 results in the unwind naturally setting arch.cr3 to
3337 * the correct value. Smashing vmcs01.GUEST_CR3 is safe because nested
3338 * VM-Exits, and the unwind, reset KVM's MMU, i.e. vmcs01.GUEST_CR3 is
3339 * guaranteed to be overwritten with a shadow CR3 prior to re-entering
3340 * L1. Don't stuff vmcs01.GUEST_CR3 when using nested early checks as
3341 * KVM modifies vcpu->arch.cr3 if and only if the early hardware checks
3342 * pass, and early VM-Fails do not reset KVM's MMU, i.e. the VM-Fail
3343 * path would need to manually save/restore vmcs01.GUEST_CR3.
3345 if (!enable_ept && !nested_early_check)
3346 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3348 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
3350 prepare_vmcs02_early(vmx, vmcs12);
3353 if (unlikely(!nested_get_vmcs12_pages(vcpu))) {
3354 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3355 return NVMX_VMENTRY_KVM_INTERNAL_ERROR;
3358 if (nested_vmx_check_vmentry_hw(vcpu)) {
3359 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3360 return NVMX_VMENTRY_VMFAIL;
3363 if (nested_vmx_check_guest_state(vcpu, vmcs12,
3364 &entry_failure_code)) {
3365 exit_reason.basic = EXIT_REASON_INVALID_STATE;
3366 vmcs12->exit_qualification = entry_failure_code;
3367 goto vmentry_fail_vmexit;
3371 enter_guest_mode(vcpu);
3373 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &entry_failure_code)) {
3374 exit_reason.basic = EXIT_REASON_INVALID_STATE;
3375 vmcs12->exit_qualification = entry_failure_code;
3376 goto vmentry_fail_vmexit_guest_mode;
3380 failed_index = nested_vmx_load_msr(vcpu,
3381 vmcs12->vm_entry_msr_load_addr,
3382 vmcs12->vm_entry_msr_load_count);
3384 exit_reason.basic = EXIT_REASON_MSR_LOAD_FAIL;
3385 vmcs12->exit_qualification = failed_index;
3386 goto vmentry_fail_vmexit_guest_mode;
3390 * The MMU is not initialized to point at the right entities yet and
3391 * "get pages" would need to read data from the guest (i.e. we will
3392 * need to perform gpa to hpa translation). Request a call
3393 * to nested_get_vmcs12_pages before the next VM-entry. The MSRs
3394 * have already been set at vmentry time and should not be reset.
3396 kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu);
3400 * If L1 had a pending IRQ/NMI until it executed
3401 * VMLAUNCH/VMRESUME which wasn't delivered because it was
3402 * disallowed (e.g. interrupts disabled), L0 needs to
3403 * evaluate if this pending event should cause an exit from L2
3404 * to L1 or delivered directly to L2 (e.g. In case L1 don't
3405 * intercept EXTERNAL_INTERRUPT).
3407 * Usually this would be handled by the processor noticing an
3408 * IRQ/NMI window request, or checking RVI during evaluation of
3409 * pending virtual interrupts. However, this setting was done
3410 * on VMCS01 and now VMCS02 is active instead. Thus, we force L0
3411 * to perform pending event evaluation by requesting a KVM_REQ_EVENT.
3413 if (unlikely(evaluate_pending_interrupts))
3414 kvm_make_request(KVM_REQ_EVENT, vcpu);
3417 * Do not start the preemption timer hrtimer until after we know
3418 * we are successful, so that only nested_vmx_vmexit needs to cancel
3421 vmx->nested.preemption_timer_expired = false;
3422 if (nested_cpu_has_preemption_timer(vmcs12)) {
3423 u64 timer_value = vmx_calc_preemption_timer_value(vcpu);
3424 vmx_start_preemption_timer(vcpu, timer_value);
3428 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
3429 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
3430 * returned as far as L1 is concerned. It will only return (and set
3431 * the success flag) when L2 exits (see nested_vmx_vmexit()).
3433 return NVMX_VMENTRY_SUCCESS;
3436 * A failed consistency check that leads to a VMExit during L1's
3437 * VMEnter to L2 is a variation of a normal VMexit, as explained in
3438 * 26.7 "VM-entry failures during or after loading guest state".
3440 vmentry_fail_vmexit_guest_mode:
3441 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)
3442 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
3443 leave_guest_mode(vcpu);
3445 vmentry_fail_vmexit:
3446 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3449 return NVMX_VMENTRY_VMEXIT;
3451 load_vmcs12_host_state(vcpu, vmcs12);
3452 vmcs12->vm_exit_reason = exit_reason.full;
3453 if (enable_shadow_vmcs || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
3454 vmx->nested.need_vmcs12_to_shadow_sync = true;
3455 return NVMX_VMENTRY_VMEXIT;
3459 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
3460 * for running an L2 nested guest.
3462 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
3464 struct vmcs12 *vmcs12;
3465 enum nvmx_vmentry_status status;
3466 struct vcpu_vmx *vmx = to_vmx(vcpu);
3467 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
3468 enum nested_evmptrld_status evmptrld_status;
3470 if (!nested_vmx_check_permission(vcpu))
3473 evmptrld_status = nested_vmx_handle_enlightened_vmptrld(vcpu, launch);
3474 if (evmptrld_status == EVMPTRLD_ERROR) {
3475 kvm_queue_exception(vcpu, UD_VECTOR);
3477 } else if (CC(evmptrld_status == EVMPTRLD_VMFAIL)) {
3478 return nested_vmx_failInvalid(vcpu);
3481 if (CC(!evmptr_is_valid(vmx->nested.hv_evmcs_vmptr) &&
3482 vmx->nested.current_vmptr == -1ull))
3483 return nested_vmx_failInvalid(vcpu);
3485 vmcs12 = get_vmcs12(vcpu);
3488 * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact
3489 * that there *is* a valid VMCS pointer, RFLAGS.CF is set
3490 * rather than RFLAGS.ZF, and no error number is stored to the
3491 * VM-instruction error field.
3493 if (CC(vmcs12->hdr.shadow_vmcs))
3494 return nested_vmx_failInvalid(vcpu);
3496 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) {
3497 copy_enlightened_to_vmcs12(vmx, vmx->nested.hv_evmcs->hv_clean_fields);
3498 /* Enlightened VMCS doesn't have launch state */
3499 vmcs12->launch_state = !launch;
3500 } else if (enable_shadow_vmcs) {
3501 copy_shadow_to_vmcs12(vmx);
3505 * The nested entry process starts with enforcing various prerequisites
3506 * on vmcs12 as required by the Intel SDM, and act appropriately when
3507 * they fail: As the SDM explains, some conditions should cause the
3508 * instruction to fail, while others will cause the instruction to seem
3509 * to succeed, but return an EXIT_REASON_INVALID_STATE.
3510 * To speed up the normal (success) code path, we should avoid checking
3511 * for misconfigurations which will anyway be caught by the processor
3512 * when using the merged vmcs02.
3514 if (CC(interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS))
3515 return nested_vmx_fail(vcpu, VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
3517 if (CC(vmcs12->launch_state == launch))
3518 return nested_vmx_fail(vcpu,
3519 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
3520 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
3522 if (nested_vmx_check_controls(vcpu, vmcs12))
3523 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3525 if (nested_vmx_check_host_state(vcpu, vmcs12))
3526 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
3529 * We're finally done with prerequisite checking, and can start with
3532 vmx->nested.nested_run_pending = 1;
3533 vmx->nested.has_preemption_timer_deadline = false;
3534 status = nested_vmx_enter_non_root_mode(vcpu, true);
3535 if (unlikely(status != NVMX_VMENTRY_SUCCESS))
3536 goto vmentry_failed;
3538 /* Emulate processing of posted interrupts on VM-Enter. */
3539 if (nested_cpu_has_posted_intr(vmcs12) &&
3540 kvm_apic_has_interrupt(vcpu) == vmx->nested.posted_intr_nv) {
3541 vmx->nested.pi_pending = true;
3542 kvm_make_request(KVM_REQ_EVENT, vcpu);
3543 kvm_apic_clear_irr(vcpu, vmx->nested.posted_intr_nv);
3546 /* Hide L1D cache contents from the nested guest. */
3547 vmx->vcpu.arch.l1tf_flush_l1d = true;
3550 * Must happen outside of nested_vmx_enter_non_root_mode() as it will
3551 * also be used as part of restoring nVMX state for
3552 * snapshot restore (migration).
3554 * In this flow, it is assumed that vmcs12 cache was
3555 * transferred as part of captured nVMX state and should
3556 * therefore not be read from guest memory (which may not
3557 * exist on destination host yet).
3559 nested_cache_shadow_vmcs12(vcpu, vmcs12);
3561 switch (vmcs12->guest_activity_state) {
3562 case GUEST_ACTIVITY_HLT:
3564 * If we're entering a halted L2 vcpu and the L2 vcpu won't be
3565 * awakened by event injection or by an NMI-window VM-exit or
3566 * by an interrupt-window VM-exit, halt the vcpu.
3568 if (!(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) &&
3569 !nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING) &&
3570 !(nested_cpu_has(vmcs12, CPU_BASED_INTR_WINDOW_EXITING) &&
3571 (vmcs12->guest_rflags & X86_EFLAGS_IF))) {
3572 vmx->nested.nested_run_pending = 0;
3573 return kvm_vcpu_halt(vcpu);
3576 case GUEST_ACTIVITY_WAIT_SIPI:
3577 vmx->nested.nested_run_pending = 0;
3578 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
3587 vmx->nested.nested_run_pending = 0;
3588 if (status == NVMX_VMENTRY_KVM_INTERNAL_ERROR)
3590 if (status == NVMX_VMENTRY_VMEXIT)
3592 WARN_ON_ONCE(status != NVMX_VMENTRY_VMFAIL);
3593 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3597 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
3598 * because L2 may have changed some cr0 bits directly (CR0_GUEST_HOST_MASK).
3599 * This function returns the new value we should put in vmcs12.guest_cr0.
3600 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
3601 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
3602 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
3603 * didn't trap the bit, because if L1 did, so would L0).
3604 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
3605 * been modified by L2, and L1 knows it. So just leave the old value of
3606 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
3607 * isn't relevant, because if L0 traps this bit it can set it to anything.
3608 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
3609 * changed these bits, and therefore they need to be updated, but L0
3610 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
3611 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
3613 static inline unsigned long
3614 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
3617 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
3618 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
3619 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
3620 vcpu->arch.cr0_guest_owned_bits));
3623 static inline unsigned long
3624 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
3627 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
3628 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
3629 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
3630 vcpu->arch.cr4_guest_owned_bits));
3633 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
3634 struct vmcs12 *vmcs12)
3639 if (vcpu->arch.exception.injected) {
3640 nr = vcpu->arch.exception.nr;
3641 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
3643 if (kvm_exception_is_soft(nr)) {
3644 vmcs12->vm_exit_instruction_len =
3645 vcpu->arch.event_exit_inst_len;
3646 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
3648 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
3650 if (vcpu->arch.exception.has_error_code) {
3651 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
3652 vmcs12->idt_vectoring_error_code =
3653 vcpu->arch.exception.error_code;
3656 vmcs12->idt_vectoring_info_field = idt_vectoring;
3657 } else if (vcpu->arch.nmi_injected) {
3658 vmcs12->idt_vectoring_info_field =
3659 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
3660 } else if (vcpu->arch.interrupt.injected) {
3661 nr = vcpu->arch.interrupt.nr;
3662 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
3664 if (vcpu->arch.interrupt.soft) {
3665 idt_vectoring |= INTR_TYPE_SOFT_INTR;
3666 vmcs12->vm_entry_instruction_len =
3667 vcpu->arch.event_exit_inst_len;
3669 idt_vectoring |= INTR_TYPE_EXT_INTR;
3671 vmcs12->idt_vectoring_info_field = idt_vectoring;
3676 void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
3678 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3682 * Don't need to mark the APIC access page dirty; it is never
3683 * written to by the CPU during APIC virtualization.
3686 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
3687 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
3688 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3691 if (nested_cpu_has_posted_intr(vmcs12)) {
3692 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
3693 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3697 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
3699 struct vcpu_vmx *vmx = to_vmx(vcpu);
3704 if (!vmx->nested.pi_pending)
3707 if (!vmx->nested.pi_desc)
3710 vmx->nested.pi_pending = false;
3712 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
3715 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
3716 if (max_irr != 256) {
3717 vapic_page = vmx->nested.virtual_apic_map.hva;
3721 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
3722 vapic_page, &max_irr);
3723 status = vmcs_read16(GUEST_INTR_STATUS);
3724 if ((u8)max_irr > ((u8)status & 0xff)) {
3726 status |= (u8)max_irr;
3727 vmcs_write16(GUEST_INTR_STATUS, status);
3731 nested_mark_vmcs12_pages_dirty(vcpu);
3735 kvm_handle_memory_failure(vcpu, X86EMUL_IO_NEEDED, NULL);
3739 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
3740 unsigned long exit_qual)
3742 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3743 unsigned int nr = vcpu->arch.exception.nr;
3744 u32 intr_info = nr | INTR_INFO_VALID_MASK;
3746 if (vcpu->arch.exception.has_error_code) {
3747 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
3748 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3751 if (kvm_exception_is_soft(nr))
3752 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3754 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3756 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
3757 vmx_get_nmi_mask(vcpu))
3758 intr_info |= INTR_INFO_UNBLOCK_NMI;
3760 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
3764 * Returns true if a debug trap is pending delivery.
3766 * In KVM, debug traps bear an exception payload. As such, the class of a #DB
3767 * exception may be inferred from the presence of an exception payload.
3769 static inline bool vmx_pending_dbg_trap(struct kvm_vcpu *vcpu)
3771 return vcpu->arch.exception.pending &&
3772 vcpu->arch.exception.nr == DB_VECTOR &&
3773 vcpu->arch.exception.payload;
3777 * Certain VM-exits set the 'pending debug exceptions' field to indicate a
3778 * recognized #DB (data or single-step) that has yet to be delivered. Since KVM
3779 * represents these debug traps with a payload that is said to be compatible
3780 * with the 'pending debug exceptions' field, write the payload to the VMCS
3781 * field if a VM-exit is delivered before the debug trap.
3783 static void nested_vmx_update_pending_dbg(struct kvm_vcpu *vcpu)
3785 if (vmx_pending_dbg_trap(vcpu))
3786 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
3787 vcpu->arch.exception.payload);
3790 static bool nested_vmx_preemption_timer_pending(struct kvm_vcpu *vcpu)
3792 return nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
3793 to_vmx(vcpu)->nested.preemption_timer_expired;
3796 static int vmx_check_nested_events(struct kvm_vcpu *vcpu)
3798 struct vcpu_vmx *vmx = to_vmx(vcpu);
3799 unsigned long exit_qual;
3800 bool block_nested_events =
3801 vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
3802 bool mtf_pending = vmx->nested.mtf_pending;
3803 struct kvm_lapic *apic = vcpu->arch.apic;
3806 * Clear the MTF state. If a higher priority VM-exit is delivered first,
3807 * this state is discarded.
3809 if (!block_nested_events)
3810 vmx->nested.mtf_pending = false;
3812 if (lapic_in_kernel(vcpu) &&
3813 test_bit(KVM_APIC_INIT, &apic->pending_events)) {
3814 if (block_nested_events)
3816 nested_vmx_update_pending_dbg(vcpu);
3817 clear_bit(KVM_APIC_INIT, &apic->pending_events);
3818 if (vcpu->arch.mp_state != KVM_MP_STATE_INIT_RECEIVED)
3819 nested_vmx_vmexit(vcpu, EXIT_REASON_INIT_SIGNAL, 0, 0);
3823 if (lapic_in_kernel(vcpu) &&
3824 test_bit(KVM_APIC_SIPI, &apic->pending_events)) {
3825 if (block_nested_events)
3828 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
3829 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3830 nested_vmx_vmexit(vcpu, EXIT_REASON_SIPI_SIGNAL, 0,
3831 apic->sipi_vector & 0xFFUL);
3836 * Process any exceptions that are not debug traps before MTF.
3838 * Note that only a pending nested run can block a pending exception.
3839 * Otherwise an injected NMI/interrupt should either be
3840 * lost or delivered to the nested hypervisor in the IDT_VECTORING_INFO,
3841 * while delivering the pending exception.
3844 if (vcpu->arch.exception.pending && !vmx_pending_dbg_trap(vcpu)) {
3845 if (vmx->nested.nested_run_pending)
3847 if (!nested_vmx_check_exception(vcpu, &exit_qual))
3849 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
3854 if (block_nested_events)
3856 nested_vmx_update_pending_dbg(vcpu);
3857 nested_vmx_vmexit(vcpu, EXIT_REASON_MONITOR_TRAP_FLAG, 0, 0);
3861 if (vcpu->arch.exception.pending) {
3862 if (vmx->nested.nested_run_pending)
3864 if (!nested_vmx_check_exception(vcpu, &exit_qual))
3866 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
3870 if (nested_vmx_preemption_timer_pending(vcpu)) {
3871 if (block_nested_events)
3873 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
3877 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
3878 if (block_nested_events)
3883 if (vcpu->arch.nmi_pending && !vmx_nmi_blocked(vcpu)) {
3884 if (block_nested_events)
3886 if (!nested_exit_on_nmi(vcpu))
3889 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
3890 NMI_VECTOR | INTR_TYPE_NMI_INTR |
3891 INTR_INFO_VALID_MASK, 0);
3893 * The NMI-triggered VM exit counts as injection:
3894 * clear this one and block further NMIs.
3896 vcpu->arch.nmi_pending = 0;
3897 vmx_set_nmi_mask(vcpu, true);
3901 if (kvm_cpu_has_interrupt(vcpu) && !vmx_interrupt_blocked(vcpu)) {
3902 if (block_nested_events)
3904 if (!nested_exit_on_intr(vcpu))
3906 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
3911 return vmx_complete_nested_posted_interrupt(vcpu);
3914 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
3917 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
3920 if (ktime_to_ns(remaining) <= 0)
3923 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
3924 do_div(value, 1000000);
3925 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
3928 static bool is_vmcs12_ext_field(unsigned long field)
3931 case GUEST_ES_SELECTOR:
3932 case GUEST_CS_SELECTOR:
3933 case GUEST_SS_SELECTOR:
3934 case GUEST_DS_SELECTOR:
3935 case GUEST_FS_SELECTOR:
3936 case GUEST_GS_SELECTOR:
3937 case GUEST_LDTR_SELECTOR:
3938 case GUEST_TR_SELECTOR:
3939 case GUEST_ES_LIMIT:
3940 case GUEST_CS_LIMIT:
3941 case GUEST_SS_LIMIT:
3942 case GUEST_DS_LIMIT:
3943 case GUEST_FS_LIMIT:
3944 case GUEST_GS_LIMIT:
3945 case GUEST_LDTR_LIMIT:
3946 case GUEST_TR_LIMIT:
3947 case GUEST_GDTR_LIMIT:
3948 case GUEST_IDTR_LIMIT:
3949 case GUEST_ES_AR_BYTES:
3950 case GUEST_DS_AR_BYTES:
3951 case GUEST_FS_AR_BYTES:
3952 case GUEST_GS_AR_BYTES:
3953 case GUEST_LDTR_AR_BYTES:
3954 case GUEST_TR_AR_BYTES:
3961 case GUEST_LDTR_BASE:
3963 case GUEST_GDTR_BASE:
3964 case GUEST_IDTR_BASE:
3965 case GUEST_PENDING_DBG_EXCEPTIONS:
3975 static void sync_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu,
3976 struct vmcs12 *vmcs12)
3978 struct vcpu_vmx *vmx = to_vmx(vcpu);
3980 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
3981 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
3982 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
3983 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
3984 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
3985 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
3986 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
3987 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
3988 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
3989 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
3990 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
3991 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
3992 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
3993 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
3994 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
3995 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
3996 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
3997 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
3998 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
3999 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
4000 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
4001 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
4002 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
4003 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
4004 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
4005 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
4006 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
4007 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
4008 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
4009 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
4010 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
4011 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
4012 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
4013 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
4014 vmcs12->guest_pending_dbg_exceptions =
4015 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
4016 if (kvm_mpx_supported())
4017 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4019 vmx->nested.need_sync_vmcs02_to_vmcs12_rare = false;
4022 static void copy_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu,
4023 struct vmcs12 *vmcs12)
4025 struct vcpu_vmx *vmx = to_vmx(vcpu);
4028 if (!vmx->nested.need_sync_vmcs02_to_vmcs12_rare)
4032 WARN_ON_ONCE(vmx->loaded_vmcs != &vmx->vmcs01);
4035 vmx->loaded_vmcs = &vmx->nested.vmcs02;
4036 vmx_vcpu_load_vmcs(vcpu, cpu, &vmx->vmcs01);
4038 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
4040 vmx->loaded_vmcs = &vmx->vmcs01;
4041 vmx_vcpu_load_vmcs(vcpu, cpu, &vmx->nested.vmcs02);
4046 * Update the guest state fields of vmcs12 to reflect changes that
4047 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
4048 * VM-entry controls is also updated, since this is really a guest
4051 static void sync_vmcs02_to_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4053 struct vcpu_vmx *vmx = to_vmx(vcpu);
4055 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
4056 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
4058 vmx->nested.need_sync_vmcs02_to_vmcs12_rare =
4059 !evmptr_is_valid(vmx->nested.hv_evmcs_vmptr);
4061 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
4062 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
4064 vmcs12->guest_rsp = kvm_rsp_read(vcpu);
4065 vmcs12->guest_rip = kvm_rip_read(vcpu);
4066 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
4068 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
4069 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
4071 vmcs12->guest_interruptibility_info =
4072 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
4074 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
4075 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
4076 else if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4077 vmcs12->guest_activity_state = GUEST_ACTIVITY_WAIT_SIPI;
4079 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4081 if (nested_cpu_has_preemption_timer(vmcs12) &&
4082 vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER &&
4083 !vmx->nested.nested_run_pending)
4084 vmcs12->vmx_preemption_timer_value =
4085 vmx_get_preemption_timer_value(vcpu);
4088 * In some cases (usually, nested EPT), L2 is allowed to change its
4089 * own CR3 without exiting. If it has changed it, we must keep it.
4090 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
4091 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
4093 * Additionally, restore L2's PDPTR to vmcs12.
4096 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
4097 if (nested_cpu_has_ept(vmcs12) && is_pae_paging(vcpu)) {
4098 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
4099 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
4100 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
4101 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
4105 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
4107 if (nested_cpu_has_vid(vmcs12))
4108 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
4110 vmcs12->vm_entry_controls =
4111 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
4112 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
4114 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS)
4115 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
4117 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
4118 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4122 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
4123 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
4124 * and this function updates it to reflect the changes to the guest state while
4125 * L2 was running (and perhaps made some exits which were handled directly by L0
4126 * without going back to L1), and to reflect the exit reason.
4127 * Note that we do not have to copy here all VMCS fields, just those that
4128 * could have changed by the L2 guest or the exit - i.e., the guest-state and
4129 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
4130 * which already writes to vmcs12 directly.
4132 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
4133 u32 vm_exit_reason, u32 exit_intr_info,
4134 unsigned long exit_qualification)
4136 /* update exit information fields: */
4137 vmcs12->vm_exit_reason = vm_exit_reason;
4138 if (to_vmx(vcpu)->exit_reason.enclave_mode)
4139 vmcs12->vm_exit_reason |= VMX_EXIT_REASONS_SGX_ENCLAVE_MODE;
4140 vmcs12->exit_qualification = exit_qualification;
4141 vmcs12->vm_exit_intr_info = exit_intr_info;
4143 vmcs12->idt_vectoring_info_field = 0;
4144 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4145 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
4147 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
4148 vmcs12->launch_state = 1;
4150 /* vm_entry_intr_info_field is cleared on exit. Emulate this
4151 * instead of reading the real value. */
4152 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
4155 * Transfer the event that L0 or L1 may wanted to inject into
4156 * L2 to IDT_VECTORING_INFO_FIELD.
4158 vmcs12_save_pending_event(vcpu, vmcs12);
4161 * According to spec, there's no need to store the guest's
4162 * MSRs if the exit is due to a VM-entry failure that occurs
4163 * during or after loading the guest state. Since this exit
4164 * does not fall in that category, we need to save the MSRs.
4166 if (nested_vmx_store_msr(vcpu,
4167 vmcs12->vm_exit_msr_store_addr,
4168 vmcs12->vm_exit_msr_store_count))
4169 nested_vmx_abort(vcpu,
4170 VMX_ABORT_SAVE_GUEST_MSR_FAIL);
4174 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
4175 * preserved above and would only end up incorrectly in L1.
4177 vcpu->arch.nmi_injected = false;
4178 kvm_clear_exception_queue(vcpu);
4179 kvm_clear_interrupt_queue(vcpu);
4183 * A part of what we need to when the nested L2 guest exits and we want to
4184 * run its L1 parent, is to reset L1's guest state to the host state specified
4186 * This function is to be called not only on normal nested exit, but also on
4187 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
4188 * Failures During or After Loading Guest State").
4189 * This function should be called when the active VMCS is L1's (vmcs01).
4191 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
4192 struct vmcs12 *vmcs12)
4194 enum vm_entry_failure_code ignored;
4195 struct kvm_segment seg;
4197 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
4198 vcpu->arch.efer = vmcs12->host_ia32_efer;
4199 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4200 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
4202 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
4203 vmx_set_efer(vcpu, vcpu->arch.efer);
4205 kvm_rsp_write(vcpu, vmcs12->host_rsp);
4206 kvm_rip_write(vcpu, vmcs12->host_rip);
4207 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4208 vmx_set_interrupt_shadow(vcpu, 0);
4211 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
4212 * actually changed, because vmx_set_cr0 refers to efer set above.
4214 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
4215 * (KVM doesn't change it);
4217 vcpu->arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4218 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4220 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
4221 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
4222 vmx_set_cr4(vcpu, vmcs12->host_cr4);
4224 nested_ept_uninit_mmu_context(vcpu);
4227 * Only PDPTE load can fail as the value of cr3 was checked on entry and
4228 * couldn't have changed.
4230 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, true, &ignored))
4231 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
4233 nested_vmx_transition_tlb_flush(vcpu, vmcs12, false);
4235 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
4236 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
4237 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
4238 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
4239 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4240 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
4241 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
4243 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
4244 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
4245 vmcs_write64(GUEST_BNDCFGS, 0);
4247 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4248 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
4249 vcpu->arch.pat = vmcs12->host_ia32_pat;
4251 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
4252 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
4253 vmcs12->host_ia32_perf_global_ctrl));
4255 /* Set L1 segment info according to Intel SDM
4256 27.5.2 Loading Host Segment and Descriptor-Table Registers */
4257 seg = (struct kvm_segment) {
4259 .limit = 0xFFFFFFFF,
4260 .selector = vmcs12->host_cs_selector,
4266 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4270 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
4271 seg = (struct kvm_segment) {
4273 .limit = 0xFFFFFFFF,
4280 seg.selector = vmcs12->host_ds_selector;
4281 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
4282 seg.selector = vmcs12->host_es_selector;
4283 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
4284 seg.selector = vmcs12->host_ss_selector;
4285 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
4286 seg.selector = vmcs12->host_fs_selector;
4287 seg.base = vmcs12->host_fs_base;
4288 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
4289 seg.selector = vmcs12->host_gs_selector;
4290 seg.base = vmcs12->host_gs_base;
4291 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
4292 seg = (struct kvm_segment) {
4293 .base = vmcs12->host_tr_base,
4295 .selector = vmcs12->host_tr_selector,
4299 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
4301 kvm_set_dr(vcpu, 7, 0x400);
4302 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4304 if (cpu_has_vmx_msr_bitmap())
4305 vmx_update_msr_bitmap(vcpu);
4307 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
4308 vmcs12->vm_exit_msr_load_count))
4309 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4312 static inline u64 nested_vmx_get_vmcs01_guest_efer(struct vcpu_vmx *vmx)
4314 struct vmx_uret_msr *efer_msr;
4317 if (vm_entry_controls_get(vmx) & VM_ENTRY_LOAD_IA32_EFER)
4318 return vmcs_read64(GUEST_IA32_EFER);
4320 if (cpu_has_load_ia32_efer())
4323 for (i = 0; i < vmx->msr_autoload.guest.nr; ++i) {
4324 if (vmx->msr_autoload.guest.val[i].index == MSR_EFER)
4325 return vmx->msr_autoload.guest.val[i].value;
4328 efer_msr = vmx_find_uret_msr(vmx, MSR_EFER);
4330 return efer_msr->data;
4335 static void nested_vmx_restore_host_state(struct kvm_vcpu *vcpu)
4337 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4338 struct vcpu_vmx *vmx = to_vmx(vcpu);
4339 struct vmx_msr_entry g, h;
4343 vcpu->arch.pat = vmcs_read64(GUEST_IA32_PAT);
4345 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
4347 * L1's host DR7 is lost if KVM_GUESTDBG_USE_HW_BP is set
4348 * as vmcs01.GUEST_DR7 contains a userspace defined value
4349 * and vcpu->arch.dr7 is not squirreled away before the
4350 * nested VMENTER (not worth adding a variable in nested_vmx).
4352 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
4353 kvm_set_dr(vcpu, 7, DR7_FIXED_1);
4355 WARN_ON(kvm_set_dr(vcpu, 7, vmcs_readl(GUEST_DR7)));
4359 * Note that calling vmx_set_{efer,cr0,cr4} is important as they
4360 * handle a variety of side effects to KVM's software model.
4362 vmx_set_efer(vcpu, nested_vmx_get_vmcs01_guest_efer(vmx));
4364 vcpu->arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4365 vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW));
4367 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
4368 vmx_set_cr4(vcpu, vmcs_readl(CR4_READ_SHADOW));
4370 nested_ept_uninit_mmu_context(vcpu);
4371 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4372 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
4375 * Use ept_save_pdptrs(vcpu) to load the MMU's cached PDPTRs
4376 * from vmcs01 (if necessary). The PDPTRs are not loaded on
4377 * VMFail, like everything else we just need to ensure our
4378 * software model is up-to-date.
4380 if (enable_ept && is_pae_paging(vcpu))
4381 ept_save_pdptrs(vcpu);
4383 kvm_mmu_reset_context(vcpu);
4385 if (cpu_has_vmx_msr_bitmap())
4386 vmx_update_msr_bitmap(vcpu);
4389 * This nasty bit of open coding is a compromise between blindly
4390 * loading L1's MSRs using the exit load lists (incorrect emulation
4391 * of VMFail), leaving the nested VM's MSRs in the software model
4392 * (incorrect behavior) and snapshotting the modified MSRs (too
4393 * expensive since the lists are unbound by hardware). For each
4394 * MSR that was (prematurely) loaded from the nested VMEntry load
4395 * list, reload it from the exit load list if it exists and differs
4396 * from the guest value. The intent is to stuff host state as
4397 * silently as possible, not to fully process the exit load list.
4399 for (i = 0; i < vmcs12->vm_entry_msr_load_count; i++) {
4400 gpa = vmcs12->vm_entry_msr_load_addr + (i * sizeof(g));
4401 if (kvm_vcpu_read_guest(vcpu, gpa, &g, sizeof(g))) {
4402 pr_debug_ratelimited(
4403 "%s read MSR index failed (%u, 0x%08llx)\n",
4408 for (j = 0; j < vmcs12->vm_exit_msr_load_count; j++) {
4409 gpa = vmcs12->vm_exit_msr_load_addr + (j * sizeof(h));
4410 if (kvm_vcpu_read_guest(vcpu, gpa, &h, sizeof(h))) {
4411 pr_debug_ratelimited(
4412 "%s read MSR failed (%u, 0x%08llx)\n",
4416 if (h.index != g.index)
4418 if (h.value == g.value)
4421 if (nested_vmx_load_msr_check(vcpu, &h)) {
4422 pr_debug_ratelimited(
4423 "%s check failed (%u, 0x%x, 0x%x)\n",
4424 __func__, j, h.index, h.reserved);
4428 if (kvm_set_msr(vcpu, h.index, h.value)) {
4429 pr_debug_ratelimited(
4430 "%s WRMSR failed (%u, 0x%x, 0x%llx)\n",
4431 __func__, j, h.index, h.value);
4440 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4444 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
4445 * and modify vmcs12 to make it see what it would expect to see there if
4446 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
4448 void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason,
4449 u32 exit_intr_info, unsigned long exit_qualification)
4451 struct vcpu_vmx *vmx = to_vmx(vcpu);
4452 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4454 /* trying to cancel vmlaunch/vmresume is a bug */
4455 WARN_ON_ONCE(vmx->nested.nested_run_pending);
4457 /* Similarly, triple faults in L2 should never escape. */
4458 WARN_ON_ONCE(kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu));
4460 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
4462 * KVM_REQ_GET_NESTED_STATE_PAGES is also used to map
4463 * Enlightened VMCS after migration and we still need to
4464 * do that when something is forcing L2->L1 exit prior to
4467 (void)nested_get_evmcs_page(vcpu);
4470 /* Service the TLB flush request for L2 before switching to L1. */
4471 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
4472 kvm_vcpu_flush_tlb_current(vcpu);
4475 * VCPU_EXREG_PDPTR will be clobbered in arch/x86/kvm/vmx/vmx.h between
4476 * now and the new vmentry. Ensure that the VMCS02 PDPTR fields are
4477 * up-to-date before switching to L1.
4479 if (enable_ept && is_pae_paging(vcpu))
4480 vmx_ept_load_pdptrs(vcpu);
4482 leave_guest_mode(vcpu);
4484 if (nested_cpu_has_preemption_timer(vmcs12))
4485 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
4487 if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING)) {
4488 vcpu->arch.tsc_offset = vcpu->arch.l1_tsc_offset;
4489 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
4490 vcpu->arch.tsc_scaling_ratio = vcpu->arch.l1_tsc_scaling_ratio;
4493 if (likely(!vmx->fail)) {
4494 sync_vmcs02_to_vmcs12(vcpu, vmcs12);
4496 if (vm_exit_reason != -1)
4497 prepare_vmcs12(vcpu, vmcs12, vm_exit_reason,
4498 exit_intr_info, exit_qualification);
4501 * Must happen outside of sync_vmcs02_to_vmcs12() as it will
4502 * also be used to capture vmcs12 cache as part of
4503 * capturing nVMX state for snapshot (migration).
4505 * Otherwise, this flush will dirty guest memory at a
4506 * point it is already assumed by user-space to be
4509 nested_flush_cached_shadow_vmcs12(vcpu, vmcs12);
4512 * The only expected VM-instruction error is "VM entry with
4513 * invalid control field(s)." Anything else indicates a
4514 * problem with L0. And we should never get here with a
4515 * VMFail of any type if early consistency checks are enabled.
4517 WARN_ON_ONCE(vmcs_read32(VM_INSTRUCTION_ERROR) !=
4518 VMXERR_ENTRY_INVALID_CONTROL_FIELD);
4519 WARN_ON_ONCE(nested_early_check);
4522 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
4524 /* Update any VMCS fields that might have changed while L2 ran */
4525 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
4526 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
4527 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
4528 if (kvm_has_tsc_control)
4529 vmcs_write64(TSC_MULTIPLIER, vcpu->arch.tsc_scaling_ratio);
4531 if (vmx->nested.l1_tpr_threshold != -1)
4532 vmcs_write32(TPR_THRESHOLD, vmx->nested.l1_tpr_threshold);
4534 if (vmx->nested.change_vmcs01_virtual_apic_mode) {
4535 vmx->nested.change_vmcs01_virtual_apic_mode = false;
4536 vmx_set_virtual_apic_mode(vcpu);
4539 if (vmx->nested.update_vmcs01_cpu_dirty_logging) {
4540 vmx->nested.update_vmcs01_cpu_dirty_logging = false;
4541 vmx_update_cpu_dirty_logging(vcpu);
4544 /* Unpin physical memory we referred to in vmcs02 */
4545 if (vmx->nested.apic_access_page) {
4546 kvm_release_page_clean(vmx->nested.apic_access_page);
4547 vmx->nested.apic_access_page = NULL;
4549 kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true);
4550 kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true);
4551 vmx->nested.pi_desc = NULL;
4553 if (vmx->nested.reload_vmcs01_apic_access_page) {
4554 vmx->nested.reload_vmcs01_apic_access_page = false;
4555 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4558 if ((vm_exit_reason != -1) &&
4559 (enable_shadow_vmcs || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)))
4560 vmx->nested.need_vmcs12_to_shadow_sync = true;
4562 /* in case we halted in L2 */
4563 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4565 if (likely(!vmx->fail)) {
4566 if ((u16)vm_exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
4567 nested_exit_intr_ack_set(vcpu)) {
4568 int irq = kvm_cpu_get_interrupt(vcpu);
4570 vmcs12->vm_exit_intr_info = irq |
4571 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
4574 if (vm_exit_reason != -1)
4575 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
4576 vmcs12->exit_qualification,
4577 vmcs12->idt_vectoring_info_field,
4578 vmcs12->vm_exit_intr_info,
4579 vmcs12->vm_exit_intr_error_code,
4582 load_vmcs12_host_state(vcpu, vmcs12);
4588 * After an early L2 VM-entry failure, we're now back
4589 * in L1 which thinks it just finished a VMLAUNCH or
4590 * VMRESUME instruction, so we need to set the failure
4591 * flag and the VM-instruction error field of the VMCS
4592 * accordingly, and skip the emulated instruction.
4594 (void)nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
4597 * Restore L1's host state to KVM's software model. We're here
4598 * because a consistency check was caught by hardware, which
4599 * means some amount of guest state has been propagated to KVM's
4600 * model and needs to be unwound to the host's state.
4602 nested_vmx_restore_host_state(vcpu);
4607 static void nested_vmx_triple_fault(struct kvm_vcpu *vcpu)
4609 nested_vmx_vmexit(vcpu, EXIT_REASON_TRIPLE_FAULT, 0, 0);
4613 * Decode the memory-address operand of a vmx instruction, as recorded on an
4614 * exit caused by such an instruction (run by a guest hypervisor).
4615 * On success, returns 0. When the operand is invalid, returns 1 and throws
4618 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification,
4619 u32 vmx_instruction_info, bool wr, int len, gva_t *ret)
4623 struct kvm_segment s;
4626 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4627 * Execution", on an exit, vmx_instruction_info holds most of the
4628 * addressing components of the operand. Only the displacement part
4629 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4630 * For how an actual address is calculated from all these components,
4631 * refer to Vol. 1, "Operand Addressing".
4633 int scaling = vmx_instruction_info & 3;
4634 int addr_size = (vmx_instruction_info >> 7) & 7;
4635 bool is_reg = vmx_instruction_info & (1u << 10);
4636 int seg_reg = (vmx_instruction_info >> 15) & 7;
4637 int index_reg = (vmx_instruction_info >> 18) & 0xf;
4638 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4639 int base_reg = (vmx_instruction_info >> 23) & 0xf;
4640 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
4643 kvm_queue_exception(vcpu, UD_VECTOR);
4647 /* Addr = segment_base + offset */
4648 /* offset = base + [index * scale] + displacement */
4649 off = exit_qualification; /* holds the displacement */
4651 off = (gva_t)sign_extend64(off, 31);
4652 else if (addr_size == 0)
4653 off = (gva_t)sign_extend64(off, 15);
4655 off += kvm_register_read(vcpu, base_reg);
4657 off += kvm_register_read(vcpu, index_reg) << scaling;
4658 vmx_get_segment(vcpu, &s, seg_reg);
4661 * The effective address, i.e. @off, of a memory operand is truncated
4662 * based on the address size of the instruction. Note that this is
4663 * the *effective address*, i.e. the address prior to accounting for
4664 * the segment's base.
4666 if (addr_size == 1) /* 32 bit */
4668 else if (addr_size == 0) /* 16 bit */
4671 /* Checks for #GP/#SS exceptions. */
4673 if (is_long_mode(vcpu)) {
4675 * The virtual/linear address is never truncated in 64-bit
4676 * mode, e.g. a 32-bit address size can yield a 64-bit virtual
4677 * address when using FS/GS with a non-zero base.
4679 if (seg_reg == VCPU_SREG_FS || seg_reg == VCPU_SREG_GS)
4680 *ret = s.base + off;
4684 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
4685 * non-canonical form. This is the only check on the memory
4686 * destination for long mode!
4688 exn = is_noncanonical_address(*ret, vcpu);
4691 * When not in long mode, the virtual/linear address is
4692 * unconditionally truncated to 32 bits regardless of the
4695 *ret = (s.base + off) & 0xffffffff;
4697 /* Protected mode: apply checks for segment validity in the
4699 * - segment type check (#GP(0) may be thrown)
4700 * - usability check (#GP(0)/#SS(0))
4701 * - limit check (#GP(0)/#SS(0))
4704 /* #GP(0) if the destination operand is located in a
4705 * read-only data segment or any code segment.
4707 exn = ((s.type & 0xa) == 0 || (s.type & 8));
4709 /* #GP(0) if the source operand is located in an
4710 * execute-only code segment
4712 exn = ((s.type & 0xa) == 8);
4714 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4717 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
4719 exn = (s.unusable != 0);
4722 * Protected mode: #GP(0)/#SS(0) if the memory operand is
4723 * outside the segment limit. All CPUs that support VMX ignore
4724 * limit checks for flat segments, i.e. segments with base==0,
4725 * limit==0xffffffff and of type expand-up data or code.
4727 if (!(s.base == 0 && s.limit == 0xffffffff &&
4728 ((s.type & 8) || !(s.type & 4))))
4729 exn = exn || ((u64)off + len - 1 > s.limit);
4732 kvm_queue_exception_e(vcpu,
4733 seg_reg == VCPU_SREG_SS ?
4734 SS_VECTOR : GP_VECTOR,
4742 void nested_vmx_pmu_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
4744 struct vcpu_vmx *vmx;
4746 if (!nested_vmx_allowed(vcpu))
4750 if (kvm_x86_ops.pmu_ops->is_valid_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL)) {
4751 vmx->nested.msrs.entry_ctls_high |=
4752 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
4753 vmx->nested.msrs.exit_ctls_high |=
4754 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
4756 vmx->nested.msrs.entry_ctls_high &=
4757 ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
4758 vmx->nested.msrs.exit_ctls_high &=
4759 ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
4763 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer,
4767 struct x86_exception e;
4770 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
4771 vmcs_read32(VMX_INSTRUCTION_INFO), false,
4772 sizeof(*vmpointer), &gva)) {
4777 r = kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e);
4778 if (r != X86EMUL_CONTINUE) {
4779 *ret = kvm_handle_memory_failure(vcpu, r, &e);
4787 * Allocate a shadow VMCS and associate it with the currently loaded
4788 * VMCS, unless such a shadow VMCS already exists. The newly allocated
4789 * VMCS is also VMCLEARed, so that it is ready for use.
4791 static struct vmcs *alloc_shadow_vmcs(struct kvm_vcpu *vcpu)
4793 struct vcpu_vmx *vmx = to_vmx(vcpu);
4794 struct loaded_vmcs *loaded_vmcs = vmx->loaded_vmcs;
4797 * We should allocate a shadow vmcs for vmcs01 only when L1
4798 * executes VMXON and free it when L1 executes VMXOFF.
4799 * As it is invalid to execute VMXON twice, we shouldn't reach
4800 * here when vmcs01 already have an allocated shadow vmcs.
4802 WARN_ON(loaded_vmcs == &vmx->vmcs01 && loaded_vmcs->shadow_vmcs);
4804 if (!loaded_vmcs->shadow_vmcs) {
4805 loaded_vmcs->shadow_vmcs = alloc_vmcs(true);
4806 if (loaded_vmcs->shadow_vmcs)
4807 vmcs_clear(loaded_vmcs->shadow_vmcs);
4809 return loaded_vmcs->shadow_vmcs;
4812 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
4814 struct vcpu_vmx *vmx = to_vmx(vcpu);
4817 r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
4821 vmx->nested.cached_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT);
4822 if (!vmx->nested.cached_vmcs12)
4823 goto out_cached_vmcs12;
4825 vmx->nested.cached_shadow_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT);
4826 if (!vmx->nested.cached_shadow_vmcs12)
4827 goto out_cached_shadow_vmcs12;
4829 if (enable_shadow_vmcs && !alloc_shadow_vmcs(vcpu))
4830 goto out_shadow_vmcs;
4832 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
4833 HRTIMER_MODE_ABS_PINNED);
4834 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
4836 vmx->nested.vpid02 = allocate_vpid();
4838 vmx->nested.vmcs02_initialized = false;
4839 vmx->nested.vmxon = true;
4841 if (vmx_pt_mode_is_host_guest()) {
4842 vmx->pt_desc.guest.ctl = 0;
4843 pt_update_intercept_for_msr(vcpu);
4849 kfree(vmx->nested.cached_shadow_vmcs12);
4851 out_cached_shadow_vmcs12:
4852 kfree(vmx->nested.cached_vmcs12);
4855 free_loaded_vmcs(&vmx->nested.vmcs02);
4862 * Emulate the VMXON instruction.
4863 * Currently, we just remember that VMX is active, and do not save or even
4864 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4865 * do not currently need to store anything in that guest-allocated memory
4866 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4867 * argument is different from the VMXON pointer (which the spec says they do).
4869 static int handle_vmon(struct kvm_vcpu *vcpu)
4874 struct vcpu_vmx *vmx = to_vmx(vcpu);
4875 const u64 VMXON_NEEDED_FEATURES = FEAT_CTL_LOCKED
4876 | FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
4879 * The Intel VMX Instruction Reference lists a bunch of bits that are
4880 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
4881 * 1 (see vmx_is_valid_cr4() for when we allow the guest to set this).
4882 * Otherwise, we should fail with #UD. But most faulting conditions
4883 * have already been checked by hardware, prior to the VM-exit for
4884 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
4885 * that bit set to 1 in non-root mode.
4887 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
4888 kvm_queue_exception(vcpu, UD_VECTOR);
4892 /* CPL=0 must be checked manually. */
4893 if (vmx_get_cpl(vcpu)) {
4894 kvm_inject_gp(vcpu, 0);
4898 if (vmx->nested.vmxon)
4899 return nested_vmx_fail(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
4901 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
4902 != VMXON_NEEDED_FEATURES) {
4903 kvm_inject_gp(vcpu, 0);
4907 if (nested_vmx_get_vmptr(vcpu, &vmptr, &ret))
4912 * The first 4 bytes of VMXON region contain the supported
4913 * VMCS revision identifier
4915 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
4916 * which replaces physical address width with 32
4918 if (!page_address_valid(vcpu, vmptr))
4919 return nested_vmx_failInvalid(vcpu);
4921 if (kvm_read_guest(vcpu->kvm, vmptr, &revision, sizeof(revision)) ||
4922 revision != VMCS12_REVISION)
4923 return nested_vmx_failInvalid(vcpu);
4925 vmx->nested.vmxon_ptr = vmptr;
4926 ret = enter_vmx_operation(vcpu);
4930 return nested_vmx_succeed(vcpu);
4933 static inline void nested_release_vmcs12(struct kvm_vcpu *vcpu)
4935 struct vcpu_vmx *vmx = to_vmx(vcpu);
4937 if (vmx->nested.current_vmptr == -1ull)
4940 copy_vmcs02_to_vmcs12_rare(vcpu, get_vmcs12(vcpu));
4942 if (enable_shadow_vmcs) {
4943 /* copy to memory all shadowed fields in case
4944 they were modified */
4945 copy_shadow_to_vmcs12(vmx);
4946 vmx_disable_shadow_vmcs(vmx);
4948 vmx->nested.posted_intr_nv = -1;
4950 /* Flush VMCS12 to guest memory */
4951 kvm_vcpu_write_guest_page(vcpu,
4952 vmx->nested.current_vmptr >> PAGE_SHIFT,
4953 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
4955 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4957 vmx->nested.current_vmptr = -1ull;
4960 /* Emulate the VMXOFF instruction */
4961 static int handle_vmoff(struct kvm_vcpu *vcpu)
4963 if (!nested_vmx_check_permission(vcpu))
4968 /* Process a latched INIT during time CPU was in VMX operation */
4969 kvm_make_request(KVM_REQ_EVENT, vcpu);
4971 return nested_vmx_succeed(vcpu);
4974 /* Emulate the VMCLEAR instruction */
4975 static int handle_vmclear(struct kvm_vcpu *vcpu)
4977 struct vcpu_vmx *vmx = to_vmx(vcpu);
4983 if (!nested_vmx_check_permission(vcpu))
4986 if (nested_vmx_get_vmptr(vcpu, &vmptr, &r))
4989 if (!page_address_valid(vcpu, vmptr))
4990 return nested_vmx_fail(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
4992 if (vmptr == vmx->nested.vmxon_ptr)
4993 return nested_vmx_fail(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
4996 * When Enlightened VMEntry is enabled on the calling CPU we treat
4997 * memory area pointer by vmptr as Enlightened VMCS (as there's no good
4998 * way to distinguish it from VMCS12) and we must not corrupt it by
4999 * writing to the non-existent 'launch_state' field. The area doesn't
5000 * have to be the currently active EVMCS on the calling CPU and there's
5001 * nothing KVM has to do to transition it from 'active' to 'non-active'
5002 * state. It is possible that the area will stay mapped as
5003 * vmx->nested.hv_evmcs but this shouldn't be a problem.
5005 if (likely(!vmx->nested.enlightened_vmcs_enabled ||
5006 !nested_enlightened_vmentry(vcpu, &evmcs_gpa))) {
5007 if (vmptr == vmx->nested.current_vmptr)
5008 nested_release_vmcs12(vcpu);
5010 kvm_vcpu_write_guest(vcpu,
5011 vmptr + offsetof(struct vmcs12,
5013 &zero, sizeof(zero));
5014 } else if (vmx->nested.hv_evmcs && vmptr == vmx->nested.hv_evmcs_vmptr) {
5015 nested_release_evmcs(vcpu);
5018 return nested_vmx_succeed(vcpu);
5021 /* Emulate the VMLAUNCH instruction */
5022 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5024 return nested_vmx_run(vcpu, true);
5027 /* Emulate the VMRESUME instruction */
5028 static int handle_vmresume(struct kvm_vcpu *vcpu)
5031 return nested_vmx_run(vcpu, false);
5034 static int handle_vmread(struct kvm_vcpu *vcpu)
5036 struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu)
5038 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5039 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5040 struct vcpu_vmx *vmx = to_vmx(vcpu);
5041 struct x86_exception e;
5042 unsigned long field;
5048 if (!nested_vmx_check_permission(vcpu))
5052 * In VMX non-root operation, when the VMCS-link pointer is -1ull,
5053 * any VMREAD sets the ALU flags for VMfailInvalid.
5055 if (vmx->nested.current_vmptr == -1ull ||
5056 (is_guest_mode(vcpu) &&
5057 get_vmcs12(vcpu)->vmcs_link_pointer == -1ull))
5058 return nested_vmx_failInvalid(vcpu);
5060 /* Decode instruction info and find the field to read */
5061 field = kvm_register_read(vcpu, (((instr_info) >> 28) & 0xf));
5063 offset = vmcs_field_to_offset(field);
5065 return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5067 if (!is_guest_mode(vcpu) && is_vmcs12_ext_field(field))
5068 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
5070 /* Read the field, zero-extended to a u64 value */
5071 value = vmcs12_read_any(vmcs12, field, offset);
5074 * Now copy part of this value to register or memory, as requested.
5075 * Note that the number of bits actually copied is 32 or 64 depending
5076 * on the guest's mode (32 or 64 bit), not on the given field's length.
5078 if (instr_info & BIT(10)) {
5079 kvm_register_write(vcpu, (((instr_info) >> 3) & 0xf), value);
5081 len = is_64_bit_mode(vcpu) ? 8 : 4;
5082 if (get_vmx_mem_address(vcpu, exit_qualification,
5083 instr_info, true, len, &gva))
5085 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
5086 r = kvm_write_guest_virt_system(vcpu, gva, &value, len, &e);
5087 if (r != X86EMUL_CONTINUE)
5088 return kvm_handle_memory_failure(vcpu, r, &e);
5091 return nested_vmx_succeed(vcpu);
5094 static bool is_shadow_field_rw(unsigned long field)
5097 #define SHADOW_FIELD_RW(x, y) case x:
5098 #include "vmcs_shadow_fields.h"
5106 static bool is_shadow_field_ro(unsigned long field)
5109 #define SHADOW_FIELD_RO(x, y) case x:
5110 #include "vmcs_shadow_fields.h"
5118 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5120 struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu)
5122 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5123 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5124 struct vcpu_vmx *vmx = to_vmx(vcpu);
5125 struct x86_exception e;
5126 unsigned long field;
5132 * The value to write might be 32 or 64 bits, depending on L1's long
5133 * mode, and eventually we need to write that into a field of several
5134 * possible lengths. The code below first zero-extends the value to 64
5135 * bit (value), and then copies only the appropriate number of
5136 * bits into the vmcs12 field.
5140 if (!nested_vmx_check_permission(vcpu))
5144 * In VMX non-root operation, when the VMCS-link pointer is -1ull,
5145 * any VMWRITE sets the ALU flags for VMfailInvalid.
5147 if (vmx->nested.current_vmptr == -1ull ||
5148 (is_guest_mode(vcpu) &&
5149 get_vmcs12(vcpu)->vmcs_link_pointer == -1ull))
5150 return nested_vmx_failInvalid(vcpu);
5152 if (instr_info & BIT(10))
5153 value = kvm_register_read(vcpu, (((instr_info) >> 3) & 0xf));
5155 len = is_64_bit_mode(vcpu) ? 8 : 4;
5156 if (get_vmx_mem_address(vcpu, exit_qualification,
5157 instr_info, false, len, &gva))
5159 r = kvm_read_guest_virt(vcpu, gva, &value, len, &e);
5160 if (r != X86EMUL_CONTINUE)
5161 return kvm_handle_memory_failure(vcpu, r, &e);
5164 field = kvm_register_read(vcpu, (((instr_info) >> 28) & 0xf));
5166 offset = vmcs_field_to_offset(field);
5168 return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5171 * If the vCPU supports "VMWRITE to any supported field in the
5172 * VMCS," then the "read-only" fields are actually read/write.
5174 if (vmcs_field_readonly(field) &&
5175 !nested_cpu_has_vmwrite_any_field(vcpu))
5176 return nested_vmx_fail(vcpu, VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5179 * Ensure vmcs12 is up-to-date before any VMWRITE that dirties
5180 * vmcs12, else we may crush a field or consume a stale value.
5182 if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field))
5183 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
5186 * Some Intel CPUs intentionally drop the reserved bits of the AR byte
5187 * fields on VMWRITE. Emulate this behavior to ensure consistent KVM
5188 * behavior regardless of the underlying hardware, e.g. if an AR_BYTE
5189 * field is intercepted for VMWRITE but not VMREAD (in L1), then VMREAD
5190 * from L1 will return a different value than VMREAD from L2 (L1 sees
5191 * the stripped down value, L2 sees the full value as stored by KVM).
5193 if (field >= GUEST_ES_AR_BYTES && field <= GUEST_TR_AR_BYTES)
5196 vmcs12_write_any(vmcs12, field, offset, value);
5199 * Do not track vmcs12 dirty-state if in guest-mode as we actually
5200 * dirty shadow vmcs12 instead of vmcs12. Fields that can be updated
5201 * by L1 without a vmexit are always updated in the vmcs02, i.e. don't
5202 * "dirty" vmcs12, all others go down the prepare_vmcs02() slow path.
5204 if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field)) {
5206 * L1 can read these fields without exiting, ensure the
5207 * shadow VMCS is up-to-date.
5209 if (enable_shadow_vmcs && is_shadow_field_ro(field)) {
5211 vmcs_load(vmx->vmcs01.shadow_vmcs);
5213 __vmcs_writel(field, value);
5215 vmcs_clear(vmx->vmcs01.shadow_vmcs);
5216 vmcs_load(vmx->loaded_vmcs->vmcs);
5219 vmx->nested.dirty_vmcs12 = true;
5222 return nested_vmx_succeed(vcpu);
5225 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
5227 vmx->nested.current_vmptr = vmptr;
5228 if (enable_shadow_vmcs) {
5229 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
5230 vmcs_write64(VMCS_LINK_POINTER,
5231 __pa(vmx->vmcs01.shadow_vmcs));
5232 vmx->nested.need_vmcs12_to_shadow_sync = true;
5234 vmx->nested.dirty_vmcs12 = true;
5237 /* Emulate the VMPTRLD instruction */
5238 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5240 struct vcpu_vmx *vmx = to_vmx(vcpu);
5244 if (!nested_vmx_check_permission(vcpu))
5247 if (nested_vmx_get_vmptr(vcpu, &vmptr, &r))
5250 if (!page_address_valid(vcpu, vmptr))
5251 return nested_vmx_fail(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5253 if (vmptr == vmx->nested.vmxon_ptr)
5254 return nested_vmx_fail(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
5256 /* Forbid normal VMPTRLD if Enlightened version was used */
5257 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
5260 if (vmx->nested.current_vmptr != vmptr) {
5261 struct kvm_host_map map;
5262 struct vmcs12 *new_vmcs12;
5264 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmptr), &map)) {
5266 * Reads from an unbacked page return all 1s,
5267 * which means that the 32 bits located at the
5268 * given physical address won't match the required
5269 * VMCS12_REVISION identifier.
5271 return nested_vmx_fail(vcpu,
5272 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5275 new_vmcs12 = map.hva;
5277 if (new_vmcs12->hdr.revision_id != VMCS12_REVISION ||
5278 (new_vmcs12->hdr.shadow_vmcs &&
5279 !nested_cpu_has_vmx_shadow_vmcs(vcpu))) {
5280 kvm_vcpu_unmap(vcpu, &map, false);
5281 return nested_vmx_fail(vcpu,
5282 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5285 nested_release_vmcs12(vcpu);
5288 * Load VMCS12 from guest memory since it is not already
5291 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
5292 kvm_vcpu_unmap(vcpu, &map, false);
5294 set_current_vmptr(vmx, vmptr);
5297 return nested_vmx_succeed(vcpu);
5300 /* Emulate the VMPTRST instruction */
5301 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5303 unsigned long exit_qual = vmx_get_exit_qual(vcpu);
5304 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5305 gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr;
5306 struct x86_exception e;
5310 if (!nested_vmx_check_permission(vcpu))
5313 if (unlikely(evmptr_is_valid(to_vmx(vcpu)->nested.hv_evmcs_vmptr)))
5316 if (get_vmx_mem_address(vcpu, exit_qual, instr_info,
5317 true, sizeof(gpa_t), &gva))
5319 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
5320 r = kvm_write_guest_virt_system(vcpu, gva, (void *)¤t_vmptr,
5322 if (r != X86EMUL_CONTINUE)
5323 return kvm_handle_memory_failure(vcpu, r, &e);
5325 return nested_vmx_succeed(vcpu);
5328 #define EPTP_PA_MASK GENMASK_ULL(51, 12)
5330 static bool nested_ept_root_matches(hpa_t root_hpa, u64 root_eptp, u64 eptp)
5332 return VALID_PAGE(root_hpa) &&
5333 ((root_eptp & EPTP_PA_MASK) == (eptp & EPTP_PA_MASK));
5336 /* Emulate the INVEPT instruction */
5337 static int handle_invept(struct kvm_vcpu *vcpu)
5339 struct vcpu_vmx *vmx = to_vmx(vcpu);
5340 u32 vmx_instruction_info, types;
5341 unsigned long type, roots_to_free;
5342 struct kvm_mmu *mmu;
5344 struct x86_exception e;
5350 if (!(vmx->nested.msrs.secondary_ctls_high &
5351 SECONDARY_EXEC_ENABLE_EPT) ||
5352 !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
5353 kvm_queue_exception(vcpu, UD_VECTOR);
5357 if (!nested_vmx_check_permission(vcpu))
5360 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5361 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
5363 types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
5365 if (type >= 32 || !(types & (1 << type)))
5366 return nested_vmx_fail(vcpu, VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5368 /* According to the Intel VMX instruction reference, the memory
5369 * operand is read even if it isn't needed (e.g., for type==global)
5371 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5372 vmx_instruction_info, false, sizeof(operand), &gva))
5374 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
5375 if (r != X86EMUL_CONTINUE)
5376 return kvm_handle_memory_failure(vcpu, r, &e);
5379 * Nested EPT roots are always held through guest_mmu,
5382 mmu = &vcpu->arch.guest_mmu;
5385 case VMX_EPT_EXTENT_CONTEXT:
5386 if (!nested_vmx_check_eptp(vcpu, operand.eptp))
5387 return nested_vmx_fail(vcpu,
5388 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5391 if (nested_ept_root_matches(mmu->root_hpa, mmu->root_pgd,
5393 roots_to_free |= KVM_MMU_ROOT_CURRENT;
5395 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5396 if (nested_ept_root_matches(mmu->prev_roots[i].hpa,
5397 mmu->prev_roots[i].pgd,
5399 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5402 case VMX_EPT_EXTENT_GLOBAL:
5403 roots_to_free = KVM_MMU_ROOTS_ALL;
5411 kvm_mmu_free_roots(vcpu, mmu, roots_to_free);
5413 return nested_vmx_succeed(vcpu);
5416 static int handle_invvpid(struct kvm_vcpu *vcpu)
5418 struct vcpu_vmx *vmx = to_vmx(vcpu);
5419 u32 vmx_instruction_info;
5420 unsigned long type, types;
5422 struct x86_exception e;
5430 if (!(vmx->nested.msrs.secondary_ctls_high &
5431 SECONDARY_EXEC_ENABLE_VPID) ||
5432 !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
5433 kvm_queue_exception(vcpu, UD_VECTOR);
5437 if (!nested_vmx_check_permission(vcpu))
5440 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5441 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
5443 types = (vmx->nested.msrs.vpid_caps &
5444 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
5446 if (type >= 32 || !(types & (1 << type)))
5447 return nested_vmx_fail(vcpu,
5448 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5450 /* according to the intel vmx instruction reference, the memory
5451 * operand is read even if it isn't needed (e.g., for type==global)
5453 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5454 vmx_instruction_info, false, sizeof(operand), &gva))
5456 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
5457 if (r != X86EMUL_CONTINUE)
5458 return kvm_handle_memory_failure(vcpu, r, &e);
5460 if (operand.vpid >> 16)
5461 return nested_vmx_fail(vcpu,
5462 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5464 vpid02 = nested_get_vpid02(vcpu);
5466 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
5467 if (!operand.vpid ||
5468 is_noncanonical_address(operand.gla, vcpu))
5469 return nested_vmx_fail(vcpu,
5470 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5471 vpid_sync_vcpu_addr(vpid02, operand.gla);
5473 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
5474 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
5476 return nested_vmx_fail(vcpu,
5477 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5478 vpid_sync_context(vpid02);
5480 case VMX_VPID_EXTENT_ALL_CONTEXT:
5481 vpid_sync_context(vpid02);
5485 return kvm_skip_emulated_instruction(vcpu);
5489 * Sync the shadow page tables if EPT is disabled, L1 is invalidating
5490 * linear mappings for L2 (tagged with L2's VPID). Free all guest
5491 * roots as VPIDs are not tracked in the MMU role.
5493 * Note, this operates on root_mmu, not guest_mmu, as L1 and L2 share
5494 * an MMU when EPT is disabled.
5496 * TODO: sync only the affected SPTEs for INVDIVIDUAL_ADDR.
5499 kvm_mmu_free_guest_mode_roots(vcpu, &vcpu->arch.root_mmu);
5501 return nested_vmx_succeed(vcpu);
5504 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
5505 struct vmcs12 *vmcs12)
5507 u32 index = kvm_rcx_read(vcpu);
5510 if (WARN_ON_ONCE(!nested_cpu_has_ept(vmcs12)))
5512 if (index >= VMFUNC_EPTP_ENTRIES)
5515 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
5516 &new_eptp, index * 8, 8))
5520 * If the (L2) guest does a vmfunc to the currently
5521 * active ept pointer, we don't have to do anything else
5523 if (vmcs12->ept_pointer != new_eptp) {
5524 if (!nested_vmx_check_eptp(vcpu, new_eptp))
5527 vmcs12->ept_pointer = new_eptp;
5528 nested_ept_new_eptp(vcpu);
5530 if (!nested_cpu_has_vpid(vmcs12))
5531 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
5537 static int handle_vmfunc(struct kvm_vcpu *vcpu)
5539 struct vcpu_vmx *vmx = to_vmx(vcpu);
5540 struct vmcs12 *vmcs12;
5541 u32 function = kvm_rax_read(vcpu);
5544 * VMFUNC is only supported for nested guests, but we always enable the
5545 * secondary control for simplicity; for non-nested mode, fake that we
5546 * didn't by injecting #UD.
5548 if (!is_guest_mode(vcpu)) {
5549 kvm_queue_exception(vcpu, UD_VECTOR);
5553 vmcs12 = get_vmcs12(vcpu);
5556 * #UD on out-of-bounds function has priority over VM-Exit, and VMFUNC
5557 * is enabled in vmcs02 if and only if it's enabled in vmcs12.
5559 if (WARN_ON_ONCE((function > 63) || !nested_cpu_has_vmfunc(vmcs12))) {
5560 kvm_queue_exception(vcpu, UD_VECTOR);
5564 if (!(vmcs12->vm_function_control & BIT_ULL(function)))
5569 if (nested_vmx_eptp_switching(vcpu, vmcs12))
5575 return kvm_skip_emulated_instruction(vcpu);
5579 * This is effectively a reflected VM-Exit, as opposed to a synthesized
5580 * nested VM-Exit. Pass the original exit reason, i.e. don't hardcode
5581 * EXIT_REASON_VMFUNC as the exit reason.
5583 nested_vmx_vmexit(vcpu, vmx->exit_reason.full,
5584 vmx_get_intr_info(vcpu),
5585 vmx_get_exit_qual(vcpu));
5590 * Return true if an IO instruction with the specified port and size should cause
5591 * a VM-exit into L1.
5593 bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port,
5596 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5597 gpa_t bitmap, last_bitmap;
5600 last_bitmap = (gpa_t)-1;
5605 bitmap = vmcs12->io_bitmap_a;
5606 else if (port < 0x10000)
5607 bitmap = vmcs12->io_bitmap_b;
5610 bitmap += (port & 0x7fff) / 8;
5612 if (last_bitmap != bitmap)
5613 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
5615 if (b & (1 << (port & 7)))
5620 last_bitmap = bitmap;
5626 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5627 struct vmcs12 *vmcs12)
5629 unsigned long exit_qualification;
5630 unsigned short port;
5633 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5634 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
5636 exit_qualification = vmx_get_exit_qual(vcpu);
5638 port = exit_qualification >> 16;
5639 size = (exit_qualification & 7) + 1;
5641 return nested_vmx_check_io_bitmaps(vcpu, port, size);
5645 * Return 1 if we should exit from L2 to L1 to handle an MSR access,
5646 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5647 * disinterest in the current event (read or write a specific MSR) by using an
5648 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5650 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5651 struct vmcs12 *vmcs12,
5652 union vmx_exit_reason exit_reason)
5654 u32 msr_index = kvm_rcx_read(vcpu);
5657 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
5661 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5662 * for the four combinations of read/write and low/high MSR numbers.
5663 * First we need to figure out which of the four to use:
5665 bitmap = vmcs12->msr_bitmap;
5666 if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
5668 if (msr_index >= 0xc0000000) {
5669 msr_index -= 0xc0000000;
5673 /* Then read the msr_index'th bit from this bitmap: */
5674 if (msr_index < 1024*8) {
5676 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
5678 return 1 & (b >> (msr_index & 7));
5680 return true; /* let L1 handle the wrong parameter */
5684 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5685 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5686 * intercept (via guest_host_mask etc.) the current event.
5688 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5689 struct vmcs12 *vmcs12)
5691 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5692 int cr = exit_qualification & 15;
5696 switch ((exit_qualification >> 4) & 3) {
5697 case 0: /* mov to cr */
5698 reg = (exit_qualification >> 8) & 15;
5699 val = kvm_register_read(vcpu, reg);
5702 if (vmcs12->cr0_guest_host_mask &
5703 (val ^ vmcs12->cr0_read_shadow))
5707 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5711 if (vmcs12->cr4_guest_host_mask &
5712 (vmcs12->cr4_read_shadow ^ val))
5716 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5722 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5723 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5726 case 1: /* mov from cr */
5729 if (vmcs12->cpu_based_vm_exec_control &
5730 CPU_BASED_CR3_STORE_EXITING)
5734 if (vmcs12->cpu_based_vm_exec_control &
5735 CPU_BASED_CR8_STORE_EXITING)
5742 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5743 * cr0. Other attempted changes are ignored, with no exit.
5745 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5746 if (vmcs12->cr0_guest_host_mask & 0xe &
5747 (val ^ vmcs12->cr0_read_shadow))
5749 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5750 !(vmcs12->cr0_read_shadow & 0x1) &&
5758 static bool nested_vmx_exit_handled_encls(struct kvm_vcpu *vcpu,
5759 struct vmcs12 *vmcs12)
5763 if (!guest_cpuid_has(vcpu, X86_FEATURE_SGX) ||
5764 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENCLS_EXITING))
5767 encls_leaf = kvm_rax_read(vcpu);
5768 if (encls_leaf > 62)
5770 return vmcs12->encls_exiting_bitmap & BIT_ULL(encls_leaf);
5773 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu,
5774 struct vmcs12 *vmcs12, gpa_t bitmap)
5776 u32 vmx_instruction_info;
5777 unsigned long field;
5780 if (!nested_cpu_has_shadow_vmcs(vmcs12))
5783 /* Decode instruction info and find the field to access */
5784 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5785 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5787 /* Out-of-range fields always cause a VM exit from L2 to L1 */
5791 if (kvm_vcpu_read_guest(vcpu, bitmap + field/8, &b, 1))
5794 return 1 & (b >> (field & 7));
5797 static bool nested_vmx_exit_handled_mtf(struct vmcs12 *vmcs12)
5799 u32 entry_intr_info = vmcs12->vm_entry_intr_info_field;
5801 if (nested_cpu_has_mtf(vmcs12))
5805 * An MTF VM-exit may be injected into the guest by setting the
5806 * interruption-type to 7 (other event) and the vector field to 0. Such
5807 * is the case regardless of the 'monitor trap flag' VM-execution
5810 return entry_intr_info == (INTR_INFO_VALID_MASK
5811 | INTR_TYPE_OTHER_EVENT);
5815 * Return true if L0 wants to handle an exit from L2 regardless of whether or not
5816 * L1 wants the exit. Only call this when in is_guest_mode (L2).
5818 static bool nested_vmx_l0_wants_exit(struct kvm_vcpu *vcpu,
5819 union vmx_exit_reason exit_reason)
5823 switch ((u16)exit_reason.basic) {
5824 case EXIT_REASON_EXCEPTION_NMI:
5825 intr_info = vmx_get_intr_info(vcpu);
5826 if (is_nmi(intr_info))
5828 else if (is_page_fault(intr_info))
5829 return vcpu->arch.apf.host_apf_flags || !enable_ept;
5830 else if (is_debug(intr_info) &&
5832 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5834 else if (is_breakpoint(intr_info) &&
5835 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5837 else if (is_alignment_check(intr_info) &&
5838 !vmx_guest_inject_ac(vcpu))
5841 case EXIT_REASON_EXTERNAL_INTERRUPT:
5843 case EXIT_REASON_MCE_DURING_VMENTRY:
5845 case EXIT_REASON_EPT_VIOLATION:
5847 * L0 always deals with the EPT violation. If nested EPT is
5848 * used, and the nested mmu code discovers that the address is
5849 * missing in the guest EPT table (EPT12), the EPT violation
5850 * will be injected with nested_ept_inject_page_fault()
5853 case EXIT_REASON_EPT_MISCONFIG:
5855 * L2 never uses directly L1's EPT, but rather L0's own EPT
5856 * table (shadow on EPT) or a merged EPT table that L0 built
5857 * (EPT on EPT). So any problems with the structure of the
5858 * table is L0's fault.
5861 case EXIT_REASON_PREEMPTION_TIMER:
5863 case EXIT_REASON_PML_FULL:
5865 * PML is emulated for an L1 VMM and should never be enabled in
5866 * vmcs02, always "handle" PML_FULL by exiting to userspace.
5869 case EXIT_REASON_VMFUNC:
5870 /* VM functions are emulated through L2->L0 vmexits. */
5879 * Return 1 if L1 wants to intercept an exit from L2. Only call this when in
5880 * is_guest_mode (L2).
5882 static bool nested_vmx_l1_wants_exit(struct kvm_vcpu *vcpu,
5883 union vmx_exit_reason exit_reason)
5885 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5888 switch ((u16)exit_reason.basic) {
5889 case EXIT_REASON_EXCEPTION_NMI:
5890 intr_info = vmx_get_intr_info(vcpu);
5891 if (is_nmi(intr_info))
5893 else if (is_page_fault(intr_info))
5895 return vmcs12->exception_bitmap &
5896 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5897 case EXIT_REASON_EXTERNAL_INTERRUPT:
5898 return nested_exit_on_intr(vcpu);
5899 case EXIT_REASON_TRIPLE_FAULT:
5901 case EXIT_REASON_INTERRUPT_WINDOW:
5902 return nested_cpu_has(vmcs12, CPU_BASED_INTR_WINDOW_EXITING);
5903 case EXIT_REASON_NMI_WINDOW:
5904 return nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING);
5905 case EXIT_REASON_TASK_SWITCH:
5907 case EXIT_REASON_CPUID:
5909 case EXIT_REASON_HLT:
5910 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5911 case EXIT_REASON_INVD:
5913 case EXIT_REASON_INVLPG:
5914 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5915 case EXIT_REASON_RDPMC:
5916 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5917 case EXIT_REASON_RDRAND:
5918 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
5919 case EXIT_REASON_RDSEED:
5920 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
5921 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
5922 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5923 case EXIT_REASON_VMREAD:
5924 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
5925 vmcs12->vmread_bitmap);
5926 case EXIT_REASON_VMWRITE:
5927 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
5928 vmcs12->vmwrite_bitmap);
5929 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5930 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5931 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMRESUME:
5932 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5933 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
5935 * VMX instructions trap unconditionally. This allows L1 to
5936 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5939 case EXIT_REASON_CR_ACCESS:
5940 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5941 case EXIT_REASON_DR_ACCESS:
5942 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5943 case EXIT_REASON_IO_INSTRUCTION:
5944 return nested_vmx_exit_handled_io(vcpu, vmcs12);
5945 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
5946 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
5947 case EXIT_REASON_MSR_READ:
5948 case EXIT_REASON_MSR_WRITE:
5949 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5950 case EXIT_REASON_INVALID_STATE:
5952 case EXIT_REASON_MWAIT_INSTRUCTION:
5953 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5954 case EXIT_REASON_MONITOR_TRAP_FLAG:
5955 return nested_vmx_exit_handled_mtf(vmcs12);
5956 case EXIT_REASON_MONITOR_INSTRUCTION:
5957 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5958 case EXIT_REASON_PAUSE_INSTRUCTION:
5959 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5960 nested_cpu_has2(vmcs12,
5961 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5962 case EXIT_REASON_MCE_DURING_VMENTRY:
5964 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5965 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
5966 case EXIT_REASON_APIC_ACCESS:
5967 case EXIT_REASON_APIC_WRITE:
5968 case EXIT_REASON_EOI_INDUCED:
5970 * The controls for "virtualize APIC accesses," "APIC-
5971 * register virtualization," and "virtual-interrupt
5972 * delivery" only come from vmcs12.
5975 case EXIT_REASON_INVPCID:
5977 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
5978 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5979 case EXIT_REASON_WBINVD:
5980 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5981 case EXIT_REASON_XSETBV:
5983 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
5985 * This should never happen, since it is not possible to
5986 * set XSS to a non-zero value---neither in L1 nor in L2.
5987 * If if it were, XSS would have to be checked against
5988 * the XSS exit bitmap in vmcs12.
5990 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
5991 case EXIT_REASON_UMWAIT:
5992 case EXIT_REASON_TPAUSE:
5993 return nested_cpu_has2(vmcs12,
5994 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE);
5995 case EXIT_REASON_ENCLS:
5996 return nested_vmx_exit_handled_encls(vcpu, vmcs12);
6003 * Conditionally reflect a VM-Exit into L1. Returns %true if the VM-Exit was
6004 * reflected into L1.
6006 bool nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu)
6008 struct vcpu_vmx *vmx = to_vmx(vcpu);
6009 union vmx_exit_reason exit_reason = vmx->exit_reason;
6010 unsigned long exit_qual;
6013 WARN_ON_ONCE(vmx->nested.nested_run_pending);
6016 * Late nested VM-Fail shares the same flow as nested VM-Exit since KVM
6017 * has already loaded L2's state.
6019 if (unlikely(vmx->fail)) {
6020 trace_kvm_nested_vmenter_failed(
6021 "hardware VM-instruction error: ",
6022 vmcs_read32(VM_INSTRUCTION_ERROR));
6025 goto reflect_vmexit;
6028 trace_kvm_nested_vmexit(exit_reason.full, vcpu, KVM_ISA_VMX);
6030 /* If L0 (KVM) wants the exit, it trumps L1's desires. */
6031 if (nested_vmx_l0_wants_exit(vcpu, exit_reason))
6034 /* If L1 doesn't want the exit, handle it in L0. */
6035 if (!nested_vmx_l1_wants_exit(vcpu, exit_reason))
6039 * vmcs.VM_EXIT_INTR_INFO is only valid for EXCEPTION_NMI exits. For
6040 * EXTERNAL_INTERRUPT, the value for vmcs12->vm_exit_intr_info would
6041 * need to be synthesized by querying the in-kernel LAPIC, but external
6042 * interrupts are never reflected to L1 so it's a non-issue.
6044 exit_intr_info = vmx_get_intr_info(vcpu);
6045 if (is_exception_with_error_code(exit_intr_info)) {
6046 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6048 vmcs12->vm_exit_intr_error_code =
6049 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6051 exit_qual = vmx_get_exit_qual(vcpu);
6054 nested_vmx_vmexit(vcpu, exit_reason.full, exit_intr_info, exit_qual);
6058 static int vmx_get_nested_state(struct kvm_vcpu *vcpu,
6059 struct kvm_nested_state __user *user_kvm_nested_state,
6062 struct vcpu_vmx *vmx;
6063 struct vmcs12 *vmcs12;
6064 struct kvm_nested_state kvm_state = {
6066 .format = KVM_STATE_NESTED_FORMAT_VMX,
6067 .size = sizeof(kvm_state),
6069 .hdr.vmx.vmxon_pa = -1ull,
6070 .hdr.vmx.vmcs12_pa = -1ull,
6071 .hdr.vmx.preemption_timer_deadline = 0,
6073 struct kvm_vmx_nested_state_data __user *user_vmx_nested_state =
6074 &user_kvm_nested_state->data.vmx[0];
6077 return kvm_state.size + sizeof(*user_vmx_nested_state);
6080 vmcs12 = get_vmcs12(vcpu);
6082 if (nested_vmx_allowed(vcpu) &&
6083 (vmx->nested.vmxon || vmx->nested.smm.vmxon)) {
6084 kvm_state.hdr.vmx.vmxon_pa = vmx->nested.vmxon_ptr;
6085 kvm_state.hdr.vmx.vmcs12_pa = vmx->nested.current_vmptr;
6087 if (vmx_has_valid_vmcs12(vcpu)) {
6088 kvm_state.size += sizeof(user_vmx_nested_state->vmcs12);
6090 /* 'hv_evmcs_vmptr' can also be EVMPTR_MAP_PENDING here */
6091 if (vmx->nested.hv_evmcs_vmptr != EVMPTR_INVALID)
6092 kvm_state.flags |= KVM_STATE_NESTED_EVMCS;
6094 if (is_guest_mode(vcpu) &&
6095 nested_cpu_has_shadow_vmcs(vmcs12) &&
6096 vmcs12->vmcs_link_pointer != -1ull)
6097 kvm_state.size += sizeof(user_vmx_nested_state->shadow_vmcs12);
6100 if (vmx->nested.smm.vmxon)
6101 kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_VMXON;
6103 if (vmx->nested.smm.guest_mode)
6104 kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_GUEST_MODE;
6106 if (is_guest_mode(vcpu)) {
6107 kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE;
6109 if (vmx->nested.nested_run_pending)
6110 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING;
6112 if (vmx->nested.mtf_pending)
6113 kvm_state.flags |= KVM_STATE_NESTED_MTF_PENDING;
6115 if (nested_cpu_has_preemption_timer(vmcs12) &&
6116 vmx->nested.has_preemption_timer_deadline) {
6117 kvm_state.hdr.vmx.flags |=
6118 KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE;
6119 kvm_state.hdr.vmx.preemption_timer_deadline =
6120 vmx->nested.preemption_timer_deadline;
6125 if (user_data_size < kvm_state.size)
6128 if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state)))
6131 if (!vmx_has_valid_vmcs12(vcpu))
6135 * When running L2, the authoritative vmcs12 state is in the
6136 * vmcs02. When running L1, the authoritative vmcs12 state is
6137 * in the shadow or enlightened vmcs linked to vmcs01, unless
6138 * need_vmcs12_to_shadow_sync is set, in which case, the authoritative
6139 * vmcs12 state is in the vmcs12 already.
6141 if (is_guest_mode(vcpu)) {
6142 sync_vmcs02_to_vmcs12(vcpu, vmcs12);
6143 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
6145 copy_vmcs02_to_vmcs12_rare(vcpu, get_vmcs12(vcpu));
6146 if (!vmx->nested.need_vmcs12_to_shadow_sync) {
6147 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
6149 * L1 hypervisor is not obliged to keep eVMCS
6150 * clean fields data always up-to-date while
6151 * not in guest mode, 'hv_clean_fields' is only
6152 * supposed to be actual upon vmentry so we need
6153 * to ignore it here and do full copy.
6155 copy_enlightened_to_vmcs12(vmx, 0);
6156 else if (enable_shadow_vmcs)
6157 copy_shadow_to_vmcs12(vmx);
6161 BUILD_BUG_ON(sizeof(user_vmx_nested_state->vmcs12) < VMCS12_SIZE);
6162 BUILD_BUG_ON(sizeof(user_vmx_nested_state->shadow_vmcs12) < VMCS12_SIZE);
6165 * Copy over the full allocated size of vmcs12 rather than just the size
6168 if (copy_to_user(user_vmx_nested_state->vmcs12, vmcs12, VMCS12_SIZE))
6171 if (nested_cpu_has_shadow_vmcs(vmcs12) &&
6172 vmcs12->vmcs_link_pointer != -1ull) {
6173 if (copy_to_user(user_vmx_nested_state->shadow_vmcs12,
6174 get_shadow_vmcs12(vcpu), VMCS12_SIZE))
6178 return kvm_state.size;
6182 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
6184 void vmx_leave_nested(struct kvm_vcpu *vcpu)
6186 if (is_guest_mode(vcpu)) {
6187 to_vmx(vcpu)->nested.nested_run_pending = 0;
6188 nested_vmx_vmexit(vcpu, -1, 0, 0);
6193 static int vmx_set_nested_state(struct kvm_vcpu *vcpu,
6194 struct kvm_nested_state __user *user_kvm_nested_state,
6195 struct kvm_nested_state *kvm_state)
6197 struct vcpu_vmx *vmx = to_vmx(vcpu);
6198 struct vmcs12 *vmcs12;
6199 enum vm_entry_failure_code ignored;
6200 struct kvm_vmx_nested_state_data __user *user_vmx_nested_state =
6201 &user_kvm_nested_state->data.vmx[0];
6204 if (kvm_state->format != KVM_STATE_NESTED_FORMAT_VMX)
6207 if (kvm_state->hdr.vmx.vmxon_pa == -1ull) {
6208 if (kvm_state->hdr.vmx.smm.flags)
6211 if (kvm_state->hdr.vmx.vmcs12_pa != -1ull)
6215 * KVM_STATE_NESTED_EVMCS used to signal that KVM should
6216 * enable eVMCS capability on vCPU. However, since then
6217 * code was changed such that flag signals vmcs12 should
6218 * be copied into eVMCS in guest memory.
6220 * To preserve backwards compatability, allow user
6221 * to set this flag even when there is no VMXON region.
6223 if (kvm_state->flags & ~KVM_STATE_NESTED_EVMCS)
6226 if (!nested_vmx_allowed(vcpu))
6229 if (!page_address_valid(vcpu, kvm_state->hdr.vmx.vmxon_pa))
6233 if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
6234 (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
6237 if (kvm_state->hdr.vmx.smm.flags &
6238 ~(KVM_STATE_NESTED_SMM_GUEST_MODE | KVM_STATE_NESTED_SMM_VMXON))
6241 if (kvm_state->hdr.vmx.flags & ~KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE)
6245 * SMM temporarily disables VMX, so we cannot be in guest mode,
6246 * nor can VMLAUNCH/VMRESUME be pending. Outside SMM, SMM flags
6251 (KVM_STATE_NESTED_GUEST_MODE | KVM_STATE_NESTED_RUN_PENDING))
6252 : kvm_state->hdr.vmx.smm.flags)
6255 if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
6256 !(kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON))
6259 if ((kvm_state->flags & KVM_STATE_NESTED_EVMCS) &&
6260 (!nested_vmx_allowed(vcpu) || !vmx->nested.enlightened_vmcs_enabled))
6263 vmx_leave_nested(vcpu);
6265 if (kvm_state->hdr.vmx.vmxon_pa == -1ull)
6268 vmx->nested.vmxon_ptr = kvm_state->hdr.vmx.vmxon_pa;
6269 ret = enter_vmx_operation(vcpu);
6273 /* Empty 'VMXON' state is permitted if no VMCS loaded */
6274 if (kvm_state->size < sizeof(*kvm_state) + sizeof(*vmcs12)) {
6275 /* See vmx_has_valid_vmcs12. */
6276 if ((kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE) ||
6277 (kvm_state->flags & KVM_STATE_NESTED_EVMCS) ||
6278 (kvm_state->hdr.vmx.vmcs12_pa != -1ull))
6284 if (kvm_state->hdr.vmx.vmcs12_pa != -1ull) {
6285 if (kvm_state->hdr.vmx.vmcs12_pa == kvm_state->hdr.vmx.vmxon_pa ||
6286 !page_address_valid(vcpu, kvm_state->hdr.vmx.vmcs12_pa))
6289 set_current_vmptr(vmx, kvm_state->hdr.vmx.vmcs12_pa);
6290 } else if (kvm_state->flags & KVM_STATE_NESTED_EVMCS) {
6292 * nested_vmx_handle_enlightened_vmptrld() cannot be called
6293 * directly from here as HV_X64_MSR_VP_ASSIST_PAGE may not be
6294 * restored yet. EVMCS will be mapped from
6295 * nested_get_vmcs12_pages().
6297 vmx->nested.hv_evmcs_vmptr = EVMPTR_MAP_PENDING;
6298 kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu);
6303 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON) {
6304 vmx->nested.smm.vmxon = true;
6305 vmx->nested.vmxon = false;
6307 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE)
6308 vmx->nested.smm.guest_mode = true;
6311 vmcs12 = get_vmcs12(vcpu);
6312 if (copy_from_user(vmcs12, user_vmx_nested_state->vmcs12, sizeof(*vmcs12)))
6315 if (vmcs12->hdr.revision_id != VMCS12_REVISION)
6318 if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
6321 vmx->nested.nested_run_pending =
6322 !!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);
6324 vmx->nested.mtf_pending =
6325 !!(kvm_state->flags & KVM_STATE_NESTED_MTF_PENDING);
6328 if (nested_cpu_has_shadow_vmcs(vmcs12) &&
6329 vmcs12->vmcs_link_pointer != -1ull) {
6330 struct vmcs12 *shadow_vmcs12 = get_shadow_vmcs12(vcpu);
6332 if (kvm_state->size <
6333 sizeof(*kvm_state) +
6334 sizeof(user_vmx_nested_state->vmcs12) + sizeof(*shadow_vmcs12))
6335 goto error_guest_mode;
6337 if (copy_from_user(shadow_vmcs12,
6338 user_vmx_nested_state->shadow_vmcs12,
6339 sizeof(*shadow_vmcs12))) {
6341 goto error_guest_mode;
6344 if (shadow_vmcs12->hdr.revision_id != VMCS12_REVISION ||
6345 !shadow_vmcs12->hdr.shadow_vmcs)
6346 goto error_guest_mode;
6349 vmx->nested.has_preemption_timer_deadline = false;
6350 if (kvm_state->hdr.vmx.flags & KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE) {
6351 vmx->nested.has_preemption_timer_deadline = true;
6352 vmx->nested.preemption_timer_deadline =
6353 kvm_state->hdr.vmx.preemption_timer_deadline;
6356 if (nested_vmx_check_controls(vcpu, vmcs12) ||
6357 nested_vmx_check_host_state(vcpu, vmcs12) ||
6358 nested_vmx_check_guest_state(vcpu, vmcs12, &ignored))
6359 goto error_guest_mode;
6361 vmx->nested.dirty_vmcs12 = true;
6362 ret = nested_vmx_enter_non_root_mode(vcpu, false);
6364 goto error_guest_mode;
6369 vmx->nested.nested_run_pending = 0;
6373 void nested_vmx_set_vmcs_shadowing_bitmap(void)
6375 if (enable_shadow_vmcs) {
6376 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6377 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
6382 * Indexing into the vmcs12 uses the VMCS encoding rotated left by 6. Undo
6383 * that madness to get the encoding for comparison.
6385 #define VMCS12_IDX_TO_ENC(idx) ((u16)(((u16)(idx) >> 6) | ((u16)(idx) << 10)))
6387 static u64 nested_vmx_calc_vmcs_enum_msr(void)
6390 * Note these are the so called "index" of the VMCS field encoding, not
6391 * the index into vmcs12.
6393 unsigned int max_idx, idx;
6397 * For better or worse, KVM allows VMREAD/VMWRITE to all fields in
6398 * vmcs12, regardless of whether or not the associated feature is
6399 * exposed to L1. Simply find the field with the highest index.
6402 for (i = 0; i < nr_vmcs12_fields; i++) {
6403 /* The vmcs12 table is very, very sparsely populated. */
6404 if (!vmcs_field_to_offset_table[i])
6407 idx = vmcs_field_index(VMCS12_IDX_TO_ENC(i));
6412 return (u64)max_idx << VMCS_FIELD_INDEX_SHIFT;
6416 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
6417 * returned for the various VMX controls MSRs when nested VMX is enabled.
6418 * The same values should also be used to verify that vmcs12 control fields are
6419 * valid during nested entry from L1 to L2.
6420 * Each of these control msrs has a low and high 32-bit half: A low bit is on
6421 * if the corresponding bit in the (32-bit) control field *must* be on, and a
6422 * bit in the high half is on if the corresponding bit in the control field
6423 * may be on. See also vmx_control_verify().
6425 void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps)
6428 * Note that as a general rule, the high half of the MSRs (bits in
6429 * the control fields which may be 1) should be initialized by the
6430 * intersection of the underlying hardware's MSR (i.e., features which
6431 * can be supported) and the list of features we want to expose -
6432 * because they are known to be properly supported in our code.
6433 * Also, usually, the low half of the MSRs (bits which must be 1) can
6434 * be set to 0, meaning that L1 may turn off any of these bits. The
6435 * reason is that if one of these bits is necessary, it will appear
6436 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
6437 * fields of vmcs01 and vmcs02, will turn these bits off - and
6438 * nested_vmx_l1_wants_exit() will not pass related exits to L1.
6439 * These rules have exceptions below.
6442 /* pin-based controls */
6443 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
6444 msrs->pinbased_ctls_low,
6445 msrs->pinbased_ctls_high);
6446 msrs->pinbased_ctls_low |=
6447 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
6448 msrs->pinbased_ctls_high &=
6449 PIN_BASED_EXT_INTR_MASK |
6450 PIN_BASED_NMI_EXITING |
6451 PIN_BASED_VIRTUAL_NMIS |
6452 (enable_apicv ? PIN_BASED_POSTED_INTR : 0);
6453 msrs->pinbased_ctls_high |=
6454 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
6455 PIN_BASED_VMX_PREEMPTION_TIMER;
6458 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
6459 msrs->exit_ctls_low,
6460 msrs->exit_ctls_high);
6461 msrs->exit_ctls_low =
6462 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
6464 msrs->exit_ctls_high &=
6465 #ifdef CONFIG_X86_64
6466 VM_EXIT_HOST_ADDR_SPACE_SIZE |
6468 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
6469 VM_EXIT_CLEAR_BNDCFGS | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
6470 msrs->exit_ctls_high |=
6471 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
6472 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
6473 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
6475 /* We support free control of debug control saving. */
6476 msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
6478 /* entry controls */
6479 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
6480 msrs->entry_ctls_low,
6481 msrs->entry_ctls_high);
6482 msrs->entry_ctls_low =
6483 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
6484 msrs->entry_ctls_high &=
6485 #ifdef CONFIG_X86_64
6486 VM_ENTRY_IA32E_MODE |
6488 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS |
6489 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
6490 msrs->entry_ctls_high |=
6491 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
6493 /* We support free control of debug control loading. */
6494 msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
6496 /* cpu-based controls */
6497 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
6498 msrs->procbased_ctls_low,
6499 msrs->procbased_ctls_high);
6500 msrs->procbased_ctls_low =
6501 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
6502 msrs->procbased_ctls_high &=
6503 CPU_BASED_INTR_WINDOW_EXITING |
6504 CPU_BASED_NMI_WINDOW_EXITING | CPU_BASED_USE_TSC_OFFSETTING |
6505 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
6506 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
6507 CPU_BASED_CR3_STORE_EXITING |
6508 #ifdef CONFIG_X86_64
6509 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
6511 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
6512 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
6513 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
6514 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
6515 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
6517 * We can allow some features even when not supported by the
6518 * hardware. For example, L1 can specify an MSR bitmap - and we
6519 * can use it to avoid exits to L1 - even when L0 runs L2
6520 * without MSR bitmaps.
6522 msrs->procbased_ctls_high |=
6523 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
6524 CPU_BASED_USE_MSR_BITMAPS;
6526 /* We support free control of CR3 access interception. */
6527 msrs->procbased_ctls_low &=
6528 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
6531 * secondary cpu-based controls. Do not include those that
6532 * depend on CPUID bits, they are added later by
6533 * vmx_vcpu_after_set_cpuid.
6535 if (msrs->procbased_ctls_high & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
6536 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
6537 msrs->secondary_ctls_low,
6538 msrs->secondary_ctls_high);
6540 msrs->secondary_ctls_low = 0;
6541 msrs->secondary_ctls_high &=
6542 SECONDARY_EXEC_DESC |
6543 SECONDARY_EXEC_ENABLE_RDTSCP |
6544 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6545 SECONDARY_EXEC_WBINVD_EXITING |
6546 SECONDARY_EXEC_APIC_REGISTER_VIRT |
6547 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
6548 SECONDARY_EXEC_RDRAND_EXITING |
6549 SECONDARY_EXEC_ENABLE_INVPCID |
6550 SECONDARY_EXEC_RDSEED_EXITING |
6551 SECONDARY_EXEC_XSAVES |
6552 SECONDARY_EXEC_TSC_SCALING;
6555 * We can emulate "VMCS shadowing," even if the hardware
6556 * doesn't support it.
6558 msrs->secondary_ctls_high |=
6559 SECONDARY_EXEC_SHADOW_VMCS;
6562 /* nested EPT: emulate EPT also to L1 */
6563 msrs->secondary_ctls_high |=
6564 SECONDARY_EXEC_ENABLE_EPT;
6566 VMX_EPT_PAGE_WALK_4_BIT |
6567 VMX_EPT_PAGE_WALK_5_BIT |
6569 VMX_EPT_INVEPT_BIT |
6570 VMX_EPT_EXECUTE_ONLY_BIT;
6572 msrs->ept_caps &= ept_caps;
6573 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
6574 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
6575 VMX_EPT_1GB_PAGE_BIT;
6576 if (enable_ept_ad_bits) {
6577 msrs->secondary_ctls_high |=
6578 SECONDARY_EXEC_ENABLE_PML;
6579 msrs->ept_caps |= VMX_EPT_AD_BIT;
6583 if (cpu_has_vmx_vmfunc()) {
6584 msrs->secondary_ctls_high |=
6585 SECONDARY_EXEC_ENABLE_VMFUNC;
6587 * Advertise EPTP switching unconditionally
6588 * since we emulate it
6591 msrs->vmfunc_controls =
6592 VMX_VMFUNC_EPTP_SWITCHING;
6596 * Old versions of KVM use the single-context version without
6597 * checking for support, so declare that it is supported even
6598 * though it is treated as global context. The alternative is
6599 * not failing the single-context invvpid, and it is worse.
6602 msrs->secondary_ctls_high |=
6603 SECONDARY_EXEC_ENABLE_VPID;
6604 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
6605 VMX_VPID_EXTENT_SUPPORTED_MASK;
6608 if (enable_unrestricted_guest)
6609 msrs->secondary_ctls_high |=
6610 SECONDARY_EXEC_UNRESTRICTED_GUEST;
6612 if (flexpriority_enabled)
6613 msrs->secondary_ctls_high |=
6614 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6617 msrs->secondary_ctls_high |= SECONDARY_EXEC_ENCLS_EXITING;
6619 /* miscellaneous data */
6620 rdmsr(MSR_IA32_VMX_MISC,
6623 msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
6625 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
6626 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
6627 VMX_MISC_ACTIVITY_HLT |
6628 VMX_MISC_ACTIVITY_WAIT_SIPI;
6629 msrs->misc_high = 0;
6632 * This MSR reports some information about VMX support. We
6633 * should return information about the VMX we emulate for the
6634 * guest, and the VMCS structure we give it - not about the
6635 * VMX support of the underlying hardware.
6639 VMX_BASIC_TRUE_CTLS |
6640 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
6641 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
6643 if (cpu_has_vmx_basic_inout())
6644 msrs->basic |= VMX_BASIC_INOUT;
6647 * These MSRs specify bits which the guest must keep fixed on
6648 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
6649 * We picked the standard core2 setting.
6651 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
6652 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
6653 msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
6654 msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
6656 /* These MSRs specify bits which the guest must keep fixed off. */
6657 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
6658 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
6660 msrs->vmcs_enum = nested_vmx_calc_vmcs_enum_msr();
6663 void nested_vmx_hardware_unsetup(void)
6667 if (enable_shadow_vmcs) {
6668 for (i = 0; i < VMX_BITMAP_NR; i++)
6669 free_page((unsigned long)vmx_bitmap[i]);
6673 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *))
6677 if (!cpu_has_vmx_shadow_vmcs())
6678 enable_shadow_vmcs = 0;
6679 if (enable_shadow_vmcs) {
6680 for (i = 0; i < VMX_BITMAP_NR; i++) {
6682 * The vmx_bitmap is not tied to a VM and so should
6683 * not be charged to a memcg.
6685 vmx_bitmap[i] = (unsigned long *)
6686 __get_free_page(GFP_KERNEL);
6687 if (!vmx_bitmap[i]) {
6688 nested_vmx_hardware_unsetup();
6693 init_vmcs_shadow_fields();
6696 exit_handlers[EXIT_REASON_VMCLEAR] = handle_vmclear;
6697 exit_handlers[EXIT_REASON_VMLAUNCH] = handle_vmlaunch;
6698 exit_handlers[EXIT_REASON_VMPTRLD] = handle_vmptrld;
6699 exit_handlers[EXIT_REASON_VMPTRST] = handle_vmptrst;
6700 exit_handlers[EXIT_REASON_VMREAD] = handle_vmread;
6701 exit_handlers[EXIT_REASON_VMRESUME] = handle_vmresume;
6702 exit_handlers[EXIT_REASON_VMWRITE] = handle_vmwrite;
6703 exit_handlers[EXIT_REASON_VMOFF] = handle_vmoff;
6704 exit_handlers[EXIT_REASON_VMON] = handle_vmon;
6705 exit_handlers[EXIT_REASON_INVEPT] = handle_invept;
6706 exit_handlers[EXIT_REASON_INVVPID] = handle_invvpid;
6707 exit_handlers[EXIT_REASON_VMFUNC] = handle_vmfunc;
6712 struct kvm_x86_nested_ops vmx_nested_ops = {
6713 .check_events = vmx_check_nested_events,
6714 .hv_timer_pending = nested_vmx_preemption_timer_pending,
6715 .triple_fault = nested_vmx_triple_fault,
6716 .get_state = vmx_get_nested_state,
6717 .set_state = vmx_set_nested_state,
6718 .get_nested_state_pages = vmx_get_nested_state_pages,
6719 .write_log_dirty = nested_vmx_write_pml_buffer,
6720 .enable_evmcs = nested_enable_evmcs,
6721 .get_evmcs_version = nested_get_evmcs_version,