1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/frame.h>
4 #include <linux/percpu.h>
6 #include <asm/debugreg.h>
7 #include <asm/mmu_context.h>
17 static bool __read_mostly enable_shadow_vmcs = 1;
18 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
20 static bool __read_mostly nested_early_check = 0;
21 module_param(nested_early_check, bool, S_IRUGO);
23 #define CC(consistency_check) \
25 bool failed = (consistency_check); \
27 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \
32 * Hyper-V requires all of these, so mark them as supported even though
33 * they are just treated the same as all-context.
35 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
36 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
37 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
38 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
39 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
41 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
48 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
50 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
51 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
53 struct shadow_vmcs_field {
57 static struct shadow_vmcs_field shadow_read_only_fields[] = {
58 #define SHADOW_FIELD_RO(x, y) { x, offsetof(struct vmcs12, y) },
59 #include "vmcs_shadow_fields.h"
61 static int max_shadow_read_only_fields =
62 ARRAY_SIZE(shadow_read_only_fields);
64 static struct shadow_vmcs_field shadow_read_write_fields[] = {
65 #define SHADOW_FIELD_RW(x, y) { x, offsetof(struct vmcs12, y) },
66 #include "vmcs_shadow_fields.h"
68 static int max_shadow_read_write_fields =
69 ARRAY_SIZE(shadow_read_write_fields);
71 static void init_vmcs_shadow_fields(void)
75 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
76 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
78 for (i = j = 0; i < max_shadow_read_only_fields; i++) {
79 struct shadow_vmcs_field entry = shadow_read_only_fields[i];
80 u16 field = entry.encoding;
82 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
83 (i + 1 == max_shadow_read_only_fields ||
84 shadow_read_only_fields[i + 1].encoding != field + 1))
85 pr_err("Missing field from shadow_read_only_field %x\n",
88 clear_bit(field, vmx_vmread_bitmap);
93 entry.offset += sizeof(u32);
95 shadow_read_only_fields[j++] = entry;
97 max_shadow_read_only_fields = j;
99 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
100 struct shadow_vmcs_field entry = shadow_read_write_fields[i];
101 u16 field = entry.encoding;
103 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
104 (i + 1 == max_shadow_read_write_fields ||
105 shadow_read_write_fields[i + 1].encoding != field + 1))
106 pr_err("Missing field from shadow_read_write_field %x\n",
109 WARN_ONCE(field >= GUEST_ES_AR_BYTES &&
110 field <= GUEST_TR_AR_BYTES,
111 "Update vmcs12_write_any() to drop reserved bits from AR_BYTES");
114 * PML and the preemption timer can be emulated, but the
115 * processor cannot vmwrite to fields that don't exist
119 case GUEST_PML_INDEX:
120 if (!cpu_has_vmx_pml())
123 case VMX_PREEMPTION_TIMER_VALUE:
124 if (!cpu_has_vmx_preemption_timer())
127 case GUEST_INTR_STATUS:
128 if (!cpu_has_vmx_apicv())
135 clear_bit(field, vmx_vmwrite_bitmap);
136 clear_bit(field, vmx_vmread_bitmap);
141 entry.offset += sizeof(u32);
143 shadow_read_write_fields[j++] = entry;
145 max_shadow_read_write_fields = j;
149 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
150 * set the success or error code of an emulated VMX instruction (as specified
151 * by Vol 2B, VMX Instruction Reference, "Conventions"), and skip the emulated
154 static int nested_vmx_succeed(struct kvm_vcpu *vcpu)
156 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
157 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
158 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
159 return kvm_skip_emulated_instruction(vcpu);
162 static int nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
164 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
165 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
166 X86_EFLAGS_SF | X86_EFLAGS_OF))
168 return kvm_skip_emulated_instruction(vcpu);
171 static int nested_vmx_failValid(struct kvm_vcpu *vcpu,
172 u32 vm_instruction_error)
174 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
175 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
176 X86_EFLAGS_SF | X86_EFLAGS_OF))
178 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
180 * We don't need to force a shadow sync because
181 * VM_INSTRUCTION_ERROR is not shadowed
183 return kvm_skip_emulated_instruction(vcpu);
186 static int nested_vmx_fail(struct kvm_vcpu *vcpu, u32 vm_instruction_error)
188 struct vcpu_vmx *vmx = to_vmx(vcpu);
191 * failValid writes the error number to the current VMCS, which
192 * can't be done if there isn't a current VMCS.
194 if (vmx->nested.current_vmptr == -1ull && !vmx->nested.hv_evmcs)
195 return nested_vmx_failInvalid(vcpu);
197 return nested_vmx_failValid(vcpu, vm_instruction_error);
200 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
202 /* TODO: not to reset guest simply here. */
203 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
204 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
207 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
209 return fixed_bits_valid(control, low, high);
212 static inline u64 vmx_control_msr(u32 low, u32 high)
214 return low | ((u64)high << 32);
217 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
219 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
220 vmcs_write64(VMCS_LINK_POINTER, -1ull);
221 vmx->nested.need_vmcs12_to_shadow_sync = false;
224 static inline void nested_release_evmcs(struct kvm_vcpu *vcpu)
226 struct vcpu_vmx *vmx = to_vmx(vcpu);
228 if (!vmx->nested.hv_evmcs)
231 kvm_vcpu_unmap(vcpu, &vmx->nested.hv_evmcs_map, true);
232 vmx->nested.hv_evmcs_vmptr = 0;
233 vmx->nested.hv_evmcs = NULL;
237 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
238 * just stops using VMX.
240 static void free_nested(struct kvm_vcpu *vcpu)
242 struct vcpu_vmx *vmx = to_vmx(vcpu);
244 if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
247 kvm_clear_request(KVM_REQ_GET_VMCS12_PAGES, vcpu);
249 vmx->nested.vmxon = false;
250 vmx->nested.smm.vmxon = false;
251 free_vpid(vmx->nested.vpid02);
252 vmx->nested.posted_intr_nv = -1;
253 vmx->nested.current_vmptr = -1ull;
254 if (enable_shadow_vmcs) {
255 vmx_disable_shadow_vmcs(vmx);
256 vmcs_clear(vmx->vmcs01.shadow_vmcs);
257 free_vmcs(vmx->vmcs01.shadow_vmcs);
258 vmx->vmcs01.shadow_vmcs = NULL;
260 kfree(vmx->nested.cached_vmcs12);
261 vmx->nested.cached_vmcs12 = NULL;
262 kfree(vmx->nested.cached_shadow_vmcs12);
263 vmx->nested.cached_shadow_vmcs12 = NULL;
264 /* Unpin physical memory we referred to in the vmcs02 */
265 if (vmx->nested.apic_access_page) {
266 kvm_release_page_clean(vmx->nested.apic_access_page);
267 vmx->nested.apic_access_page = NULL;
269 kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true);
270 kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true);
271 vmx->nested.pi_desc = NULL;
273 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
275 nested_release_evmcs(vcpu);
277 free_loaded_vmcs(&vmx->nested.vmcs02);
280 static void vmx_sync_vmcs_host_state(struct vcpu_vmx *vmx,
281 struct loaded_vmcs *prev)
283 struct vmcs_host_state *dest, *src;
285 if (unlikely(!vmx->guest_state_loaded))
288 src = &prev->host_state;
289 dest = &vmx->loaded_vmcs->host_state;
291 vmx_set_host_fs_gs(dest, src->fs_sel, src->gs_sel, src->fs_base, src->gs_base);
292 dest->ldt_sel = src->ldt_sel;
294 dest->ds_sel = src->ds_sel;
295 dest->es_sel = src->es_sel;
299 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
301 struct vcpu_vmx *vmx = to_vmx(vcpu);
302 struct loaded_vmcs *prev;
305 if (vmx->loaded_vmcs == vmcs)
309 prev = vmx->loaded_vmcs;
310 vmx->loaded_vmcs = vmcs;
311 vmx_vcpu_load_vmcs(vcpu, cpu, prev);
312 vmx_sync_vmcs_host_state(vmx, prev);
315 vmx_register_cache_reset(vcpu);
319 * Ensure that the current vmcs of the logical processor is the
320 * vmcs01 of the vcpu before calling free_nested().
322 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu)
325 vmx_leave_nested(vcpu);
326 vmx_switch_vmcs(vcpu, &to_vmx(vcpu)->vmcs01);
331 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
332 struct x86_exception *fault)
334 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
335 struct vcpu_vmx *vmx = to_vmx(vcpu);
337 unsigned long exit_qualification = vcpu->arch.exit_qualification;
339 if (vmx->nested.pml_full) {
340 vm_exit_reason = EXIT_REASON_PML_FULL;
341 vmx->nested.pml_full = false;
342 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
343 } else if (fault->error_code & PFERR_RSVD_MASK)
344 vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
346 vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
348 nested_vmx_vmexit(vcpu, vm_exit_reason, 0, exit_qualification);
349 vmcs12->guest_physical_address = fault->address;
352 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
354 WARN_ON(mmu_is_nested(vcpu));
356 vcpu->arch.mmu = &vcpu->arch.guest_mmu;
357 kvm_init_shadow_ept_mmu(vcpu,
358 to_vmx(vcpu)->nested.msrs.ept_caps &
359 VMX_EPT_EXECUTE_ONLY_BIT,
360 nested_ept_ad_enabled(vcpu),
361 nested_ept_get_eptp(vcpu));
362 vcpu->arch.mmu->get_guest_pgd = nested_ept_get_eptp;
363 vcpu->arch.mmu->inject_page_fault = nested_ept_inject_page_fault;
364 vcpu->arch.mmu->get_pdptr = kvm_pdptr_read;
366 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
369 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
371 vcpu->arch.mmu = &vcpu->arch.root_mmu;
372 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
375 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
378 bool inequality, bit;
380 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
382 (error_code & vmcs12->page_fault_error_code_mask) !=
383 vmcs12->page_fault_error_code_match;
384 return inequality ^ bit;
389 * KVM wants to inject page-faults which it got to the guest. This function
390 * checks whether in a nested guest, we need to inject them to L1 or L2.
392 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
394 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
395 unsigned int nr = vcpu->arch.exception.nr;
396 bool has_payload = vcpu->arch.exception.has_payload;
397 unsigned long payload = vcpu->arch.exception.payload;
399 if (nr == PF_VECTOR) {
400 if (vcpu->arch.exception.nested_apf) {
401 *exit_qual = vcpu->arch.apf.nested_apf_token;
404 if (nested_vmx_is_page_fault_vmexit(vmcs12,
405 vcpu->arch.exception.error_code)) {
406 *exit_qual = has_payload ? payload : vcpu->arch.cr2;
409 } else if (vmcs12->exception_bitmap & (1u << nr)) {
410 if (nr == DB_VECTOR) {
412 payload = vcpu->arch.dr6;
413 payload &= ~(DR6_FIXED_1 | DR6_BT);
416 *exit_qual = payload;
426 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
427 struct x86_exception *fault)
429 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
431 WARN_ON(!is_guest_mode(vcpu));
433 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
434 !to_vmx(vcpu)->nested.nested_run_pending) {
435 vmcs12->vm_exit_intr_error_code = fault->error_code;
436 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
437 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
438 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
441 kvm_inject_page_fault(vcpu, fault);
445 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
446 struct vmcs12 *vmcs12)
448 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
451 if (CC(!page_address_valid(vcpu, vmcs12->io_bitmap_a)) ||
452 CC(!page_address_valid(vcpu, vmcs12->io_bitmap_b)))
458 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
459 struct vmcs12 *vmcs12)
461 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
464 if (CC(!page_address_valid(vcpu, vmcs12->msr_bitmap)))
470 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
471 struct vmcs12 *vmcs12)
473 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
476 if (CC(!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr)))
483 * Check if MSR is intercepted for L01 MSR bitmap.
485 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
487 unsigned long *msr_bitmap;
488 int f = sizeof(unsigned long);
490 if (!cpu_has_vmx_msr_bitmap())
493 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
496 return !!test_bit(msr, msr_bitmap + 0x800 / f);
497 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
499 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
506 * If a msr is allowed by L0, we should check whether it is allowed by L1.
507 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
509 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
510 unsigned long *msr_bitmap_nested,
513 int f = sizeof(unsigned long);
516 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
517 * have the write-low and read-high bitmap offsets the wrong way round.
518 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
521 if (type & MSR_TYPE_R &&
522 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
524 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
526 if (type & MSR_TYPE_W &&
527 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
529 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
531 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
533 if (type & MSR_TYPE_R &&
534 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
536 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
538 if (type & MSR_TYPE_W &&
539 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
541 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
546 static inline void enable_x2apic_msr_intercepts(unsigned long *msr_bitmap)
550 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
551 unsigned word = msr / BITS_PER_LONG;
553 msr_bitmap[word] = ~0;
554 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
559 * Merge L0's and L1's MSR bitmap, return false to indicate that
560 * we do not use the hardware.
562 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
563 struct vmcs12 *vmcs12)
566 unsigned long *msr_bitmap_l1;
567 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
568 struct kvm_host_map *map = &to_vmx(vcpu)->nested.msr_bitmap_map;
570 /* Nothing to do if the MSR bitmap is not in use. */
571 if (!cpu_has_vmx_msr_bitmap() ||
572 !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
575 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->msr_bitmap), map))
578 msr_bitmap_l1 = (unsigned long *)map->hva;
581 * To keep the control flow simple, pay eight 8-byte writes (sixteen
582 * 4-byte writes on 32-bit systems) up front to enable intercepts for
583 * the x2APIC MSR range and selectively disable them below.
585 enable_x2apic_msr_intercepts(msr_bitmap_l0);
587 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
588 if (nested_cpu_has_apic_reg_virt(vmcs12)) {
590 * L0 need not intercept reads for MSRs between 0x800
591 * and 0x8ff, it just lets the processor take the value
592 * from the virtual-APIC page; take those 256 bits
593 * directly from the L1 bitmap.
595 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
596 unsigned word = msr / BITS_PER_LONG;
598 msr_bitmap_l0[word] = msr_bitmap_l1[word];
602 nested_vmx_disable_intercept_for_msr(
603 msr_bitmap_l1, msr_bitmap_l0,
604 X2APIC_MSR(APIC_TASKPRI),
605 MSR_TYPE_R | MSR_TYPE_W);
607 if (nested_cpu_has_vid(vmcs12)) {
608 nested_vmx_disable_intercept_for_msr(
609 msr_bitmap_l1, msr_bitmap_l0,
610 X2APIC_MSR(APIC_EOI),
612 nested_vmx_disable_intercept_for_msr(
613 msr_bitmap_l1, msr_bitmap_l0,
614 X2APIC_MSR(APIC_SELF_IPI),
619 /* KVM unconditionally exposes the FS/GS base MSRs to L1. */
620 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0,
621 MSR_FS_BASE, MSR_TYPE_RW);
623 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0,
624 MSR_GS_BASE, MSR_TYPE_RW);
626 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0,
627 MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
630 * Checking the L0->L1 bitmap is trying to verify two things:
632 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
633 * ensures that we do not accidentally generate an L02 MSR bitmap
634 * from the L12 MSR bitmap that is too permissive.
635 * 2. That L1 or L2s have actually used the MSR. This avoids
636 * unnecessarily merging of the bitmap if the MSR is unused. This
637 * works properly because we only update the L01 MSR bitmap lazily.
638 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
639 * updated to reflect this when L1 (or its L2s) actually write to
642 if (!msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL))
643 nested_vmx_disable_intercept_for_msr(
644 msr_bitmap_l1, msr_bitmap_l0,
646 MSR_TYPE_R | MSR_TYPE_W);
648 if (!msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD))
649 nested_vmx_disable_intercept_for_msr(
650 msr_bitmap_l1, msr_bitmap_l0,
654 kvm_vcpu_unmap(vcpu, &to_vmx(vcpu)->nested.msr_bitmap_map, false);
659 static void nested_cache_shadow_vmcs12(struct kvm_vcpu *vcpu,
660 struct vmcs12 *vmcs12)
662 struct kvm_host_map map;
663 struct vmcs12 *shadow;
665 if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
666 vmcs12->vmcs_link_pointer == -1ull)
669 shadow = get_shadow_vmcs12(vcpu);
671 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->vmcs_link_pointer), &map))
674 memcpy(shadow, map.hva, VMCS12_SIZE);
675 kvm_vcpu_unmap(vcpu, &map, false);
678 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu *vcpu,
679 struct vmcs12 *vmcs12)
681 struct vcpu_vmx *vmx = to_vmx(vcpu);
683 if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
684 vmcs12->vmcs_link_pointer == -1ull)
687 kvm_write_guest(vmx->vcpu.kvm, vmcs12->vmcs_link_pointer,
688 get_shadow_vmcs12(vcpu), VMCS12_SIZE);
692 * In nested virtualization, check if L1 has set
693 * VM_EXIT_ACK_INTR_ON_EXIT
695 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
697 return get_vmcs12(vcpu)->vm_exit_controls &
698 VM_EXIT_ACK_INTR_ON_EXIT;
701 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
702 struct vmcs12 *vmcs12)
704 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
705 CC(!page_address_valid(vcpu, vmcs12->apic_access_addr)))
711 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
712 struct vmcs12 *vmcs12)
714 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
715 !nested_cpu_has_apic_reg_virt(vmcs12) &&
716 !nested_cpu_has_vid(vmcs12) &&
717 !nested_cpu_has_posted_intr(vmcs12))
721 * If virtualize x2apic mode is enabled,
722 * virtualize apic access must be disabled.
724 if (CC(nested_cpu_has_virt_x2apic_mode(vmcs12) &&
725 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)))
729 * If virtual interrupt delivery is enabled,
730 * we must exit on external interrupts.
732 if (CC(nested_cpu_has_vid(vmcs12) && !nested_exit_on_intr(vcpu)))
736 * bits 15:8 should be zero in posted_intr_nv,
737 * the descriptor address has been already checked
738 * in nested_get_vmcs12_pages.
740 * bits 5:0 of posted_intr_desc_addr should be zero.
742 if (nested_cpu_has_posted_intr(vmcs12) &&
743 (CC(!nested_cpu_has_vid(vmcs12)) ||
744 CC(!nested_exit_intr_ack_set(vcpu)) ||
745 CC((vmcs12->posted_intr_nv & 0xff00)) ||
746 CC((vmcs12->posted_intr_desc_addr & 0x3f)) ||
747 CC((vmcs12->posted_intr_desc_addr >> cpuid_maxphyaddr(vcpu)))))
750 /* tpr shadow is needed by all apicv features. */
751 if (CC(!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)))
757 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
764 maxphyaddr = cpuid_maxphyaddr(vcpu);
765 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
766 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr)
772 static int nested_vmx_check_exit_msr_switch_controls(struct kvm_vcpu *vcpu,
773 struct vmcs12 *vmcs12)
775 if (CC(nested_vmx_check_msr_switch(vcpu,
776 vmcs12->vm_exit_msr_load_count,
777 vmcs12->vm_exit_msr_load_addr)) ||
778 CC(nested_vmx_check_msr_switch(vcpu,
779 vmcs12->vm_exit_msr_store_count,
780 vmcs12->vm_exit_msr_store_addr)))
786 static int nested_vmx_check_entry_msr_switch_controls(struct kvm_vcpu *vcpu,
787 struct vmcs12 *vmcs12)
789 if (CC(nested_vmx_check_msr_switch(vcpu,
790 vmcs12->vm_entry_msr_load_count,
791 vmcs12->vm_entry_msr_load_addr)))
797 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
798 struct vmcs12 *vmcs12)
800 if (!nested_cpu_has_pml(vmcs12))
803 if (CC(!nested_cpu_has_ept(vmcs12)) ||
804 CC(!page_address_valid(vcpu, vmcs12->pml_address)))
810 static int nested_vmx_check_unrestricted_guest_controls(struct kvm_vcpu *vcpu,
811 struct vmcs12 *vmcs12)
813 if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST) &&
814 !nested_cpu_has_ept(vmcs12)))
819 static int nested_vmx_check_mode_based_ept_exec_controls(struct kvm_vcpu *vcpu,
820 struct vmcs12 *vmcs12)
822 if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_MODE_BASED_EPT_EXEC) &&
823 !nested_cpu_has_ept(vmcs12)))
828 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu *vcpu,
829 struct vmcs12 *vmcs12)
831 if (!nested_cpu_has_shadow_vmcs(vmcs12))
834 if (CC(!page_address_valid(vcpu, vmcs12->vmread_bitmap)) ||
835 CC(!page_address_valid(vcpu, vmcs12->vmwrite_bitmap)))
841 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
842 struct vmx_msr_entry *e)
844 /* x2APIC MSR accesses are not allowed */
845 if (CC(vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8))
847 if (CC(e->index == MSR_IA32_UCODE_WRITE) || /* SDM Table 35-2 */
848 CC(e->index == MSR_IA32_UCODE_REV))
850 if (CC(e->reserved != 0))
855 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
856 struct vmx_msr_entry *e)
858 if (CC(e->index == MSR_FS_BASE) ||
859 CC(e->index == MSR_GS_BASE) ||
860 CC(e->index == MSR_IA32_SMM_MONITOR_CTL) || /* SMM is not supported */
861 nested_vmx_msr_check_common(vcpu, e))
866 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
867 struct vmx_msr_entry *e)
869 if (CC(e->index == MSR_IA32_SMBASE) || /* SMM is not supported */
870 nested_vmx_msr_check_common(vcpu, e))
875 static u32 nested_vmx_max_atomic_switch_msrs(struct kvm_vcpu *vcpu)
877 struct vcpu_vmx *vmx = to_vmx(vcpu);
878 u64 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
879 vmx->nested.msrs.misc_high);
881 return (vmx_misc_max_msr(vmx_misc) + 1) * VMX_MISC_MSR_LIST_MULTIPLIER;
885 * Load guest's/host's msr at nested entry/exit.
886 * return 0 for success, entry index for failure.
888 * One of the failure modes for MSR load/store is when a list exceeds the
889 * virtual hardware's capacity. To maintain compatibility with hardware inasmuch
890 * as possible, process all valid entries before failing rather than precheck
891 * for a capacity violation.
893 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
896 struct vmx_msr_entry e;
897 u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu);
899 for (i = 0; i < count; i++) {
900 if (unlikely(i >= max_msr_list_size))
903 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
905 pr_debug_ratelimited(
906 "%s cannot read MSR entry (%u, 0x%08llx)\n",
907 __func__, i, gpa + i * sizeof(e));
910 if (nested_vmx_load_msr_check(vcpu, &e)) {
911 pr_debug_ratelimited(
912 "%s check failed (%u, 0x%x, 0x%x)\n",
913 __func__, i, e.index, e.reserved);
916 if (kvm_set_msr(vcpu, e.index, e.value)) {
917 pr_debug_ratelimited(
918 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
919 __func__, i, e.index, e.value);
925 /* Note, max_msr_list_size is at most 4096, i.e. this can't wrap. */
929 static bool nested_vmx_get_vmexit_msr_value(struct kvm_vcpu *vcpu,
933 struct vcpu_vmx *vmx = to_vmx(vcpu);
936 * If the L0 hypervisor stored a more accurate value for the TSC that
937 * does not include the time taken for emulation of the L2->L1
938 * VM-exit in L0, use the more accurate value.
940 if (msr_index == MSR_IA32_TSC) {
941 int index = vmx_find_msr_index(&vmx->msr_autostore.guest,
945 u64 val = vmx->msr_autostore.guest.val[index].value;
947 *data = kvm_read_l1_tsc(vcpu, val);
952 if (kvm_get_msr(vcpu, msr_index, data)) {
953 pr_debug_ratelimited("%s cannot read MSR (0x%x)\n", __func__,
960 static bool read_and_check_msr_entry(struct kvm_vcpu *vcpu, u64 gpa, int i,
961 struct vmx_msr_entry *e)
963 if (kvm_vcpu_read_guest(vcpu,
964 gpa + i * sizeof(*e),
965 e, 2 * sizeof(u32))) {
966 pr_debug_ratelimited(
967 "%s cannot read MSR entry (%u, 0x%08llx)\n",
968 __func__, i, gpa + i * sizeof(*e));
971 if (nested_vmx_store_msr_check(vcpu, e)) {
972 pr_debug_ratelimited(
973 "%s check failed (%u, 0x%x, 0x%x)\n",
974 __func__, i, e->index, e->reserved);
980 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
984 struct vmx_msr_entry e;
985 u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu);
987 for (i = 0; i < count; i++) {
988 if (unlikely(i >= max_msr_list_size))
991 if (!read_and_check_msr_entry(vcpu, gpa, i, &e))
994 if (!nested_vmx_get_vmexit_msr_value(vcpu, e.index, &data))
997 if (kvm_vcpu_write_guest(vcpu,
998 gpa + i * sizeof(e) +
999 offsetof(struct vmx_msr_entry, value),
1000 &data, sizeof(data))) {
1001 pr_debug_ratelimited(
1002 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
1003 __func__, i, e.index, data);
1010 static bool nested_msr_store_list_has_msr(struct kvm_vcpu *vcpu, u32 msr_index)
1012 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1013 u32 count = vmcs12->vm_exit_msr_store_count;
1014 u64 gpa = vmcs12->vm_exit_msr_store_addr;
1015 struct vmx_msr_entry e;
1018 for (i = 0; i < count; i++) {
1019 if (!read_and_check_msr_entry(vcpu, gpa, i, &e))
1022 if (e.index == msr_index)
1028 static void prepare_vmx_msr_autostore_list(struct kvm_vcpu *vcpu,
1031 struct vcpu_vmx *vmx = to_vmx(vcpu);
1032 struct vmx_msrs *autostore = &vmx->msr_autostore.guest;
1033 bool in_vmcs12_store_list;
1034 int msr_autostore_index;
1035 bool in_autostore_list;
1038 msr_autostore_index = vmx_find_msr_index(autostore, msr_index);
1039 in_autostore_list = msr_autostore_index >= 0;
1040 in_vmcs12_store_list = nested_msr_store_list_has_msr(vcpu, msr_index);
1042 if (in_vmcs12_store_list && !in_autostore_list) {
1043 if (autostore->nr == NR_LOADSTORE_MSRS) {
1045 * Emulated VMEntry does not fail here. Instead a less
1046 * accurate value will be returned by
1047 * nested_vmx_get_vmexit_msr_value() using kvm_get_msr()
1048 * instead of reading the value from the vmcs02 VMExit
1051 pr_warn_ratelimited(
1052 "Not enough msr entries in msr_autostore. Can't add msr %x\n",
1056 last = autostore->nr++;
1057 autostore->val[last].index = msr_index;
1058 } else if (!in_vmcs12_store_list && in_autostore_list) {
1059 last = --autostore->nr;
1060 autostore->val[msr_autostore_index] = autostore->val[last];
1064 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
1066 unsigned long invalid_mask;
1068 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
1069 return (val & invalid_mask) == 0;
1073 * Returns true if the MMU needs to be sync'd on nested VM-Enter/VM-Exit.
1074 * tl;dr: the MMU needs a sync if L0 is using shadow paging and L1 didn't
1075 * enable VPID for L2 (implying it expects a TLB flush on VMX transitions).
1078 * If EPT is enabled by L0 a sync is never needed:
1079 * - if it is disabled by L1, then L0 is not shadowing L1 or L2 PTEs, there
1080 * cannot be unsync'd SPTEs for either L1 or L2.
1082 * - if it is also enabled by L1, then L0 doesn't need to sync on VM-Enter
1083 * VM-Enter as VM-Enter isn't required to invalidate guest-physical mappings
1084 * (irrespective of VPID), i.e. L1 can't rely on the (virtual) CPU to flush
1085 * stale guest-physical mappings for L2 from the TLB. And as above, L0 isn't
1086 * shadowing L1 PTEs so there are no unsync'd SPTEs to sync on VM-Exit.
1088 * If EPT is disabled by L0:
1089 * - if VPID is enabled by L1 (for L2), the situation is similar to when L1
1090 * enables EPT: L0 doesn't need to sync as VM-Enter and VM-Exit aren't
1091 * required to invalidate linear mappings (EPT is disabled so there are
1092 * no combined or guest-physical mappings), i.e. L1 can't rely on the
1093 * (virtual) CPU to flush stale linear mappings for either L2 or itself (L1).
1095 * - however if VPID is disabled by L1, then a sync is needed as L1 expects all
1096 * linear mappings (EPT is disabled so there are no combined or guest-physical
1097 * mappings) to be invalidated on both VM-Enter and VM-Exit.
1099 * Note, this logic is subtly different than nested_has_guest_tlb_tag(), which
1100 * additionally checks that L2 has been assigned a VPID (when EPT is disabled).
1101 * Whether or not L2 has been assigned a VPID by L0 is irrelevant with respect
1102 * to L1's expectations, e.g. L0 needs to invalidate hardware TLB entries if L2
1103 * doesn't have a unique VPID to prevent reusing L1's entries (assuming L1 has
1104 * been assigned a VPID), but L0 doesn't need to do a MMU sync because L1
1105 * doesn't expect stale (virtual) TLB entries to be flushed, i.e. L1 doesn't
1106 * know that L0 will flush the TLB and so L1 will do INVVPID as needed to flush
1107 * stale TLB entries, at which point L0 will sync L2's MMU.
1109 static bool nested_vmx_transition_mmu_sync(struct kvm_vcpu *vcpu)
1111 return !enable_ept && !nested_cpu_has_vpid(get_vmcs12(vcpu));
1115 * Load guest's/host's cr3 at nested entry/exit. @nested_ept is true if we are
1116 * emulating VM-Entry into a guest with EPT enabled. On failure, the expected
1117 * Exit Qualification (for a VM-Entry consistency check VM-Exit) is assigned to
1118 * @entry_failure_code.
1120 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
1121 enum vm_entry_failure_code *entry_failure_code)
1123 if (CC(!nested_cr3_valid(vcpu, cr3))) {
1124 *entry_failure_code = ENTRY_FAIL_DEFAULT;
1129 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
1130 * must not be dereferenced.
1132 if (!nested_ept && is_pae_paging(vcpu) &&
1133 (cr3 != kvm_read_cr3(vcpu) || pdptrs_changed(vcpu))) {
1134 if (CC(!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))) {
1135 *entry_failure_code = ENTRY_FAIL_PDPTE;
1141 * Unconditionally skip the TLB flush on fast CR3 switch, all TLB
1142 * flushes are handled by nested_vmx_transition_tlb_flush(). See
1143 * nested_vmx_transition_mmu_sync for details on skipping the MMU sync.
1146 kvm_mmu_new_pgd(vcpu, cr3, true,
1147 !nested_vmx_transition_mmu_sync(vcpu));
1149 vcpu->arch.cr3 = cr3;
1150 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1152 kvm_init_mmu(vcpu, false);
1158 * Returns if KVM is able to config CPU to tag TLB entries
1159 * populated by L2 differently than TLB entries populated
1162 * If L0 uses EPT, L1 and L2 run with different EPTP because
1163 * guest_mode is part of kvm_mmu_page_role. Thus, TLB entries
1164 * are tagged with different EPTP.
1166 * If L1 uses VPID and we allocated a vpid02, TLB entries are tagged
1167 * with different VPID (L1 entries are tagged with vmx->vpid
1168 * while L2 entries are tagged with vmx->nested.vpid02).
1170 static bool nested_has_guest_tlb_tag(struct kvm_vcpu *vcpu)
1172 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1174 return enable_ept ||
1175 (nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02);
1178 static void nested_vmx_transition_tlb_flush(struct kvm_vcpu *vcpu,
1179 struct vmcs12 *vmcs12,
1182 struct vcpu_vmx *vmx = to_vmx(vcpu);
1185 * If VPID is disabled, linear and combined mappings are flushed on
1186 * VM-Enter/VM-Exit, and guest-physical mappings are valid only for
1187 * their associated EPTP.
1193 * If vmcs12 doesn't use VPID, L1 expects linear and combined mappings
1194 * for *all* contexts to be flushed on VM-Enter/VM-Exit.
1196 * If VPID is enabled and used by vmc12, but L2 does not have a unique
1197 * TLB tag (ASID), i.e. EPT is disabled and KVM was unable to allocate
1198 * a VPID for L2, flush the current context as the effective ASID is
1199 * common to both L1 and L2.
1201 * Defer the flush so that it runs after vmcs02.EPTP has been set by
1202 * KVM_REQ_LOAD_MMU_PGD (if nested EPT is enabled) and to avoid
1203 * redundant flushes further down the nested pipeline.
1205 * If a TLB flush isn't required due to any of the above, and vpid12 is
1206 * changing then the new "virtual" VPID (vpid12) will reuse the same
1207 * "real" VPID (vpid02), and so needs to be sync'd. There is no direct
1208 * mapping between vpid02 and vpid12, vpid02 is per-vCPU and reused for
1211 if (!nested_cpu_has_vpid(vmcs12)) {
1212 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1213 } else if (!nested_has_guest_tlb_tag(vcpu)) {
1214 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1215 } else if (is_vmenter &&
1216 vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
1217 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
1218 vpid_sync_context(nested_get_vpid02(vcpu));
1222 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
1227 return (superset | subset) == superset;
1230 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
1232 const u64 feature_and_reserved =
1233 /* feature (except bit 48; see below) */
1234 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
1236 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
1237 u64 vmx_basic = vmx->nested.msrs.basic;
1239 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
1243 * KVM does not emulate a version of VMX that constrains physical
1244 * addresses of VMX structures (e.g. VMCS) to 32-bits.
1246 if (data & BIT_ULL(48))
1249 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
1250 vmx_basic_vmcs_revision_id(data))
1253 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
1256 vmx->nested.msrs.basic = data;
1261 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
1266 switch (msr_index) {
1267 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1268 lowp = &vmx->nested.msrs.pinbased_ctls_low;
1269 highp = &vmx->nested.msrs.pinbased_ctls_high;
1271 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1272 lowp = &vmx->nested.msrs.procbased_ctls_low;
1273 highp = &vmx->nested.msrs.procbased_ctls_high;
1275 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1276 lowp = &vmx->nested.msrs.exit_ctls_low;
1277 highp = &vmx->nested.msrs.exit_ctls_high;
1279 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1280 lowp = &vmx->nested.msrs.entry_ctls_low;
1281 highp = &vmx->nested.msrs.entry_ctls_high;
1283 case MSR_IA32_VMX_PROCBASED_CTLS2:
1284 lowp = &vmx->nested.msrs.secondary_ctls_low;
1285 highp = &vmx->nested.msrs.secondary_ctls_high;
1291 supported = vmx_control_msr(*lowp, *highp);
1293 /* Check must-be-1 bits are still 1. */
1294 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
1297 /* Check must-be-0 bits are still 0. */
1298 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
1302 *highp = data >> 32;
1306 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
1308 const u64 feature_and_reserved_bits =
1310 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
1311 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
1313 GENMASK_ULL(13, 9) | BIT_ULL(31);
1316 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
1317 vmx->nested.msrs.misc_high);
1319 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
1322 if ((vmx->nested.msrs.pinbased_ctls_high &
1323 PIN_BASED_VMX_PREEMPTION_TIMER) &&
1324 vmx_misc_preemption_timer_rate(data) !=
1325 vmx_misc_preemption_timer_rate(vmx_misc))
1328 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
1331 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
1334 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
1337 vmx->nested.msrs.misc_low = data;
1338 vmx->nested.msrs.misc_high = data >> 32;
1343 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
1345 u64 vmx_ept_vpid_cap;
1347 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
1348 vmx->nested.msrs.vpid_caps);
1350 /* Every bit is either reserved or a feature bit. */
1351 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
1354 vmx->nested.msrs.ept_caps = data;
1355 vmx->nested.msrs.vpid_caps = data >> 32;
1359 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
1363 switch (msr_index) {
1364 case MSR_IA32_VMX_CR0_FIXED0:
1365 msr = &vmx->nested.msrs.cr0_fixed0;
1367 case MSR_IA32_VMX_CR4_FIXED0:
1368 msr = &vmx->nested.msrs.cr4_fixed0;
1375 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
1376 * must be 1 in the restored value.
1378 if (!is_bitwise_subset(data, *msr, -1ULL))
1386 * Called when userspace is restoring VMX MSRs.
1388 * Returns 0 on success, non-0 otherwise.
1390 int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1392 struct vcpu_vmx *vmx = to_vmx(vcpu);
1395 * Don't allow changes to the VMX capability MSRs while the vCPU
1396 * is in VMX operation.
1398 if (vmx->nested.vmxon)
1401 switch (msr_index) {
1402 case MSR_IA32_VMX_BASIC:
1403 return vmx_restore_vmx_basic(vmx, data);
1404 case MSR_IA32_VMX_PINBASED_CTLS:
1405 case MSR_IA32_VMX_PROCBASED_CTLS:
1406 case MSR_IA32_VMX_EXIT_CTLS:
1407 case MSR_IA32_VMX_ENTRY_CTLS:
1409 * The "non-true" VMX capability MSRs are generated from the
1410 * "true" MSRs, so we do not support restoring them directly.
1412 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
1413 * should restore the "true" MSRs with the must-be-1 bits
1414 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
1415 * DEFAULT SETTINGS".
1418 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1419 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1420 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1421 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1422 case MSR_IA32_VMX_PROCBASED_CTLS2:
1423 return vmx_restore_control_msr(vmx, msr_index, data);
1424 case MSR_IA32_VMX_MISC:
1425 return vmx_restore_vmx_misc(vmx, data);
1426 case MSR_IA32_VMX_CR0_FIXED0:
1427 case MSR_IA32_VMX_CR4_FIXED0:
1428 return vmx_restore_fixed0_msr(vmx, msr_index, data);
1429 case MSR_IA32_VMX_CR0_FIXED1:
1430 case MSR_IA32_VMX_CR4_FIXED1:
1432 * These MSRs are generated based on the vCPU's CPUID, so we
1433 * do not support restoring them directly.
1436 case MSR_IA32_VMX_EPT_VPID_CAP:
1437 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
1438 case MSR_IA32_VMX_VMCS_ENUM:
1439 vmx->nested.msrs.vmcs_enum = data;
1441 case MSR_IA32_VMX_VMFUNC:
1442 if (data & ~vmx->nested.msrs.vmfunc_controls)
1444 vmx->nested.msrs.vmfunc_controls = data;
1448 * The rest of the VMX capability MSRs do not support restore.
1454 /* Returns 0 on success, non-0 otherwise. */
1455 int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
1457 switch (msr_index) {
1458 case MSR_IA32_VMX_BASIC:
1459 *pdata = msrs->basic;
1461 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1462 case MSR_IA32_VMX_PINBASED_CTLS:
1463 *pdata = vmx_control_msr(
1464 msrs->pinbased_ctls_low,
1465 msrs->pinbased_ctls_high);
1466 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
1467 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
1469 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1470 case MSR_IA32_VMX_PROCBASED_CTLS:
1471 *pdata = vmx_control_msr(
1472 msrs->procbased_ctls_low,
1473 msrs->procbased_ctls_high);
1474 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
1475 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
1477 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1478 case MSR_IA32_VMX_EXIT_CTLS:
1479 *pdata = vmx_control_msr(
1480 msrs->exit_ctls_low,
1481 msrs->exit_ctls_high);
1482 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
1483 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
1485 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1486 case MSR_IA32_VMX_ENTRY_CTLS:
1487 *pdata = vmx_control_msr(
1488 msrs->entry_ctls_low,
1489 msrs->entry_ctls_high);
1490 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
1491 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
1493 case MSR_IA32_VMX_MISC:
1494 *pdata = vmx_control_msr(
1498 case MSR_IA32_VMX_CR0_FIXED0:
1499 *pdata = msrs->cr0_fixed0;
1501 case MSR_IA32_VMX_CR0_FIXED1:
1502 *pdata = msrs->cr0_fixed1;
1504 case MSR_IA32_VMX_CR4_FIXED0:
1505 *pdata = msrs->cr4_fixed0;
1507 case MSR_IA32_VMX_CR4_FIXED1:
1508 *pdata = msrs->cr4_fixed1;
1510 case MSR_IA32_VMX_VMCS_ENUM:
1511 *pdata = msrs->vmcs_enum;
1513 case MSR_IA32_VMX_PROCBASED_CTLS2:
1514 *pdata = vmx_control_msr(
1515 msrs->secondary_ctls_low,
1516 msrs->secondary_ctls_high);
1518 case MSR_IA32_VMX_EPT_VPID_CAP:
1519 *pdata = msrs->ept_caps |
1520 ((u64)msrs->vpid_caps << 32);
1522 case MSR_IA32_VMX_VMFUNC:
1523 *pdata = msrs->vmfunc_controls;
1533 * Copy the writable VMCS shadow fields back to the VMCS12, in case they have
1534 * been modified by the L1 guest. Note, "writable" in this context means
1535 * "writable by the guest", i.e. tagged SHADOW_FIELD_RW; the set of
1536 * fields tagged SHADOW_FIELD_RO may or may not align with the "read-only"
1537 * VM-exit information fields (which are actually writable if the vCPU is
1538 * configured to support "VMWRITE to any supported field in the VMCS").
1540 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
1542 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
1543 struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu);
1544 struct shadow_vmcs_field field;
1548 if (WARN_ON(!shadow_vmcs))
1553 vmcs_load(shadow_vmcs);
1555 for (i = 0; i < max_shadow_read_write_fields; i++) {
1556 field = shadow_read_write_fields[i];
1557 val = __vmcs_readl(field.encoding);
1558 vmcs12_write_any(vmcs12, field.encoding, field.offset, val);
1561 vmcs_clear(shadow_vmcs);
1562 vmcs_load(vmx->loaded_vmcs->vmcs);
1567 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
1569 const struct shadow_vmcs_field *fields[] = {
1570 shadow_read_write_fields,
1571 shadow_read_only_fields
1573 const int max_fields[] = {
1574 max_shadow_read_write_fields,
1575 max_shadow_read_only_fields
1577 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
1578 struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu);
1579 struct shadow_vmcs_field field;
1583 if (WARN_ON(!shadow_vmcs))
1586 vmcs_load(shadow_vmcs);
1588 for (q = 0; q < ARRAY_SIZE(fields); q++) {
1589 for (i = 0; i < max_fields[q]; i++) {
1590 field = fields[q][i];
1591 val = vmcs12_read_any(vmcs12, field.encoding,
1593 __vmcs_writel(field.encoding, val);
1597 vmcs_clear(shadow_vmcs);
1598 vmcs_load(vmx->loaded_vmcs->vmcs);
1601 static int copy_enlightened_to_vmcs12(struct vcpu_vmx *vmx)
1603 struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12;
1604 struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs;
1606 /* HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE */
1607 vmcs12->tpr_threshold = evmcs->tpr_threshold;
1608 vmcs12->guest_rip = evmcs->guest_rip;
1610 if (unlikely(!(evmcs->hv_clean_fields &
1611 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC))) {
1612 vmcs12->guest_rsp = evmcs->guest_rsp;
1613 vmcs12->guest_rflags = evmcs->guest_rflags;
1614 vmcs12->guest_interruptibility_info =
1615 evmcs->guest_interruptibility_info;
1618 if (unlikely(!(evmcs->hv_clean_fields &
1619 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC))) {
1620 vmcs12->cpu_based_vm_exec_control =
1621 evmcs->cpu_based_vm_exec_control;
1624 if (unlikely(!(evmcs->hv_clean_fields &
1625 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN))) {
1626 vmcs12->exception_bitmap = evmcs->exception_bitmap;
1629 if (unlikely(!(evmcs->hv_clean_fields &
1630 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY))) {
1631 vmcs12->vm_entry_controls = evmcs->vm_entry_controls;
1634 if (unlikely(!(evmcs->hv_clean_fields &
1635 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT))) {
1636 vmcs12->vm_entry_intr_info_field =
1637 evmcs->vm_entry_intr_info_field;
1638 vmcs12->vm_entry_exception_error_code =
1639 evmcs->vm_entry_exception_error_code;
1640 vmcs12->vm_entry_instruction_len =
1641 evmcs->vm_entry_instruction_len;
1644 if (unlikely(!(evmcs->hv_clean_fields &
1645 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1))) {
1646 vmcs12->host_ia32_pat = evmcs->host_ia32_pat;
1647 vmcs12->host_ia32_efer = evmcs->host_ia32_efer;
1648 vmcs12->host_cr0 = evmcs->host_cr0;
1649 vmcs12->host_cr3 = evmcs->host_cr3;
1650 vmcs12->host_cr4 = evmcs->host_cr4;
1651 vmcs12->host_ia32_sysenter_esp = evmcs->host_ia32_sysenter_esp;
1652 vmcs12->host_ia32_sysenter_eip = evmcs->host_ia32_sysenter_eip;
1653 vmcs12->host_rip = evmcs->host_rip;
1654 vmcs12->host_ia32_sysenter_cs = evmcs->host_ia32_sysenter_cs;
1655 vmcs12->host_es_selector = evmcs->host_es_selector;
1656 vmcs12->host_cs_selector = evmcs->host_cs_selector;
1657 vmcs12->host_ss_selector = evmcs->host_ss_selector;
1658 vmcs12->host_ds_selector = evmcs->host_ds_selector;
1659 vmcs12->host_fs_selector = evmcs->host_fs_selector;
1660 vmcs12->host_gs_selector = evmcs->host_gs_selector;
1661 vmcs12->host_tr_selector = evmcs->host_tr_selector;
1664 if (unlikely(!(evmcs->hv_clean_fields &
1665 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1))) {
1666 vmcs12->pin_based_vm_exec_control =
1667 evmcs->pin_based_vm_exec_control;
1668 vmcs12->vm_exit_controls = evmcs->vm_exit_controls;
1669 vmcs12->secondary_vm_exec_control =
1670 evmcs->secondary_vm_exec_control;
1673 if (unlikely(!(evmcs->hv_clean_fields &
1674 HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP))) {
1675 vmcs12->io_bitmap_a = evmcs->io_bitmap_a;
1676 vmcs12->io_bitmap_b = evmcs->io_bitmap_b;
1679 if (unlikely(!(evmcs->hv_clean_fields &
1680 HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP))) {
1681 vmcs12->msr_bitmap = evmcs->msr_bitmap;
1684 if (unlikely(!(evmcs->hv_clean_fields &
1685 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2))) {
1686 vmcs12->guest_es_base = evmcs->guest_es_base;
1687 vmcs12->guest_cs_base = evmcs->guest_cs_base;
1688 vmcs12->guest_ss_base = evmcs->guest_ss_base;
1689 vmcs12->guest_ds_base = evmcs->guest_ds_base;
1690 vmcs12->guest_fs_base = evmcs->guest_fs_base;
1691 vmcs12->guest_gs_base = evmcs->guest_gs_base;
1692 vmcs12->guest_ldtr_base = evmcs->guest_ldtr_base;
1693 vmcs12->guest_tr_base = evmcs->guest_tr_base;
1694 vmcs12->guest_gdtr_base = evmcs->guest_gdtr_base;
1695 vmcs12->guest_idtr_base = evmcs->guest_idtr_base;
1696 vmcs12->guest_es_limit = evmcs->guest_es_limit;
1697 vmcs12->guest_cs_limit = evmcs->guest_cs_limit;
1698 vmcs12->guest_ss_limit = evmcs->guest_ss_limit;
1699 vmcs12->guest_ds_limit = evmcs->guest_ds_limit;
1700 vmcs12->guest_fs_limit = evmcs->guest_fs_limit;
1701 vmcs12->guest_gs_limit = evmcs->guest_gs_limit;
1702 vmcs12->guest_ldtr_limit = evmcs->guest_ldtr_limit;
1703 vmcs12->guest_tr_limit = evmcs->guest_tr_limit;
1704 vmcs12->guest_gdtr_limit = evmcs->guest_gdtr_limit;
1705 vmcs12->guest_idtr_limit = evmcs->guest_idtr_limit;
1706 vmcs12->guest_es_ar_bytes = evmcs->guest_es_ar_bytes;
1707 vmcs12->guest_cs_ar_bytes = evmcs->guest_cs_ar_bytes;
1708 vmcs12->guest_ss_ar_bytes = evmcs->guest_ss_ar_bytes;
1709 vmcs12->guest_ds_ar_bytes = evmcs->guest_ds_ar_bytes;
1710 vmcs12->guest_fs_ar_bytes = evmcs->guest_fs_ar_bytes;
1711 vmcs12->guest_gs_ar_bytes = evmcs->guest_gs_ar_bytes;
1712 vmcs12->guest_ldtr_ar_bytes = evmcs->guest_ldtr_ar_bytes;
1713 vmcs12->guest_tr_ar_bytes = evmcs->guest_tr_ar_bytes;
1714 vmcs12->guest_es_selector = evmcs->guest_es_selector;
1715 vmcs12->guest_cs_selector = evmcs->guest_cs_selector;
1716 vmcs12->guest_ss_selector = evmcs->guest_ss_selector;
1717 vmcs12->guest_ds_selector = evmcs->guest_ds_selector;
1718 vmcs12->guest_fs_selector = evmcs->guest_fs_selector;
1719 vmcs12->guest_gs_selector = evmcs->guest_gs_selector;
1720 vmcs12->guest_ldtr_selector = evmcs->guest_ldtr_selector;
1721 vmcs12->guest_tr_selector = evmcs->guest_tr_selector;
1724 if (unlikely(!(evmcs->hv_clean_fields &
1725 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2))) {
1726 vmcs12->tsc_offset = evmcs->tsc_offset;
1727 vmcs12->virtual_apic_page_addr = evmcs->virtual_apic_page_addr;
1728 vmcs12->xss_exit_bitmap = evmcs->xss_exit_bitmap;
1731 if (unlikely(!(evmcs->hv_clean_fields &
1732 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR))) {
1733 vmcs12->cr0_guest_host_mask = evmcs->cr0_guest_host_mask;
1734 vmcs12->cr4_guest_host_mask = evmcs->cr4_guest_host_mask;
1735 vmcs12->cr0_read_shadow = evmcs->cr0_read_shadow;
1736 vmcs12->cr4_read_shadow = evmcs->cr4_read_shadow;
1737 vmcs12->guest_cr0 = evmcs->guest_cr0;
1738 vmcs12->guest_cr3 = evmcs->guest_cr3;
1739 vmcs12->guest_cr4 = evmcs->guest_cr4;
1740 vmcs12->guest_dr7 = evmcs->guest_dr7;
1743 if (unlikely(!(evmcs->hv_clean_fields &
1744 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER))) {
1745 vmcs12->host_fs_base = evmcs->host_fs_base;
1746 vmcs12->host_gs_base = evmcs->host_gs_base;
1747 vmcs12->host_tr_base = evmcs->host_tr_base;
1748 vmcs12->host_gdtr_base = evmcs->host_gdtr_base;
1749 vmcs12->host_idtr_base = evmcs->host_idtr_base;
1750 vmcs12->host_rsp = evmcs->host_rsp;
1753 if (unlikely(!(evmcs->hv_clean_fields &
1754 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT))) {
1755 vmcs12->ept_pointer = evmcs->ept_pointer;
1756 vmcs12->virtual_processor_id = evmcs->virtual_processor_id;
1759 if (unlikely(!(evmcs->hv_clean_fields &
1760 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1))) {
1761 vmcs12->vmcs_link_pointer = evmcs->vmcs_link_pointer;
1762 vmcs12->guest_ia32_debugctl = evmcs->guest_ia32_debugctl;
1763 vmcs12->guest_ia32_pat = evmcs->guest_ia32_pat;
1764 vmcs12->guest_ia32_efer = evmcs->guest_ia32_efer;
1765 vmcs12->guest_pdptr0 = evmcs->guest_pdptr0;
1766 vmcs12->guest_pdptr1 = evmcs->guest_pdptr1;
1767 vmcs12->guest_pdptr2 = evmcs->guest_pdptr2;
1768 vmcs12->guest_pdptr3 = evmcs->guest_pdptr3;
1769 vmcs12->guest_pending_dbg_exceptions =
1770 evmcs->guest_pending_dbg_exceptions;
1771 vmcs12->guest_sysenter_esp = evmcs->guest_sysenter_esp;
1772 vmcs12->guest_sysenter_eip = evmcs->guest_sysenter_eip;
1773 vmcs12->guest_bndcfgs = evmcs->guest_bndcfgs;
1774 vmcs12->guest_activity_state = evmcs->guest_activity_state;
1775 vmcs12->guest_sysenter_cs = evmcs->guest_sysenter_cs;
1780 * vmcs12->vm_exit_msr_store_addr = evmcs->vm_exit_msr_store_addr;
1781 * vmcs12->vm_exit_msr_load_addr = evmcs->vm_exit_msr_load_addr;
1782 * vmcs12->vm_entry_msr_load_addr = evmcs->vm_entry_msr_load_addr;
1783 * vmcs12->page_fault_error_code_mask =
1784 * evmcs->page_fault_error_code_mask;
1785 * vmcs12->page_fault_error_code_match =
1786 * evmcs->page_fault_error_code_match;
1787 * vmcs12->cr3_target_count = evmcs->cr3_target_count;
1788 * vmcs12->vm_exit_msr_store_count = evmcs->vm_exit_msr_store_count;
1789 * vmcs12->vm_exit_msr_load_count = evmcs->vm_exit_msr_load_count;
1790 * vmcs12->vm_entry_msr_load_count = evmcs->vm_entry_msr_load_count;
1795 * vmcs12->guest_physical_address = evmcs->guest_physical_address;
1796 * vmcs12->vm_instruction_error = evmcs->vm_instruction_error;
1797 * vmcs12->vm_exit_reason = evmcs->vm_exit_reason;
1798 * vmcs12->vm_exit_intr_info = evmcs->vm_exit_intr_info;
1799 * vmcs12->vm_exit_intr_error_code = evmcs->vm_exit_intr_error_code;
1800 * vmcs12->idt_vectoring_info_field = evmcs->idt_vectoring_info_field;
1801 * vmcs12->idt_vectoring_error_code = evmcs->idt_vectoring_error_code;
1802 * vmcs12->vm_exit_instruction_len = evmcs->vm_exit_instruction_len;
1803 * vmcs12->vmx_instruction_info = evmcs->vmx_instruction_info;
1804 * vmcs12->exit_qualification = evmcs->exit_qualification;
1805 * vmcs12->guest_linear_address = evmcs->guest_linear_address;
1807 * Not present in struct vmcs12:
1808 * vmcs12->exit_io_instruction_ecx = evmcs->exit_io_instruction_ecx;
1809 * vmcs12->exit_io_instruction_esi = evmcs->exit_io_instruction_esi;
1810 * vmcs12->exit_io_instruction_edi = evmcs->exit_io_instruction_edi;
1811 * vmcs12->exit_io_instruction_eip = evmcs->exit_io_instruction_eip;
1817 static int copy_vmcs12_to_enlightened(struct vcpu_vmx *vmx)
1819 struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12;
1820 struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs;
1823 * Should not be changed by KVM:
1825 * evmcs->host_es_selector = vmcs12->host_es_selector;
1826 * evmcs->host_cs_selector = vmcs12->host_cs_selector;
1827 * evmcs->host_ss_selector = vmcs12->host_ss_selector;
1828 * evmcs->host_ds_selector = vmcs12->host_ds_selector;
1829 * evmcs->host_fs_selector = vmcs12->host_fs_selector;
1830 * evmcs->host_gs_selector = vmcs12->host_gs_selector;
1831 * evmcs->host_tr_selector = vmcs12->host_tr_selector;
1832 * evmcs->host_ia32_pat = vmcs12->host_ia32_pat;
1833 * evmcs->host_ia32_efer = vmcs12->host_ia32_efer;
1834 * evmcs->host_cr0 = vmcs12->host_cr0;
1835 * evmcs->host_cr3 = vmcs12->host_cr3;
1836 * evmcs->host_cr4 = vmcs12->host_cr4;
1837 * evmcs->host_ia32_sysenter_esp = vmcs12->host_ia32_sysenter_esp;
1838 * evmcs->host_ia32_sysenter_eip = vmcs12->host_ia32_sysenter_eip;
1839 * evmcs->host_rip = vmcs12->host_rip;
1840 * evmcs->host_ia32_sysenter_cs = vmcs12->host_ia32_sysenter_cs;
1841 * evmcs->host_fs_base = vmcs12->host_fs_base;
1842 * evmcs->host_gs_base = vmcs12->host_gs_base;
1843 * evmcs->host_tr_base = vmcs12->host_tr_base;
1844 * evmcs->host_gdtr_base = vmcs12->host_gdtr_base;
1845 * evmcs->host_idtr_base = vmcs12->host_idtr_base;
1846 * evmcs->host_rsp = vmcs12->host_rsp;
1847 * sync_vmcs02_to_vmcs12() doesn't read these:
1848 * evmcs->io_bitmap_a = vmcs12->io_bitmap_a;
1849 * evmcs->io_bitmap_b = vmcs12->io_bitmap_b;
1850 * evmcs->msr_bitmap = vmcs12->msr_bitmap;
1851 * evmcs->ept_pointer = vmcs12->ept_pointer;
1852 * evmcs->xss_exit_bitmap = vmcs12->xss_exit_bitmap;
1853 * evmcs->vm_exit_msr_store_addr = vmcs12->vm_exit_msr_store_addr;
1854 * evmcs->vm_exit_msr_load_addr = vmcs12->vm_exit_msr_load_addr;
1855 * evmcs->vm_entry_msr_load_addr = vmcs12->vm_entry_msr_load_addr;
1856 * evmcs->tpr_threshold = vmcs12->tpr_threshold;
1857 * evmcs->virtual_processor_id = vmcs12->virtual_processor_id;
1858 * evmcs->exception_bitmap = vmcs12->exception_bitmap;
1859 * evmcs->vmcs_link_pointer = vmcs12->vmcs_link_pointer;
1860 * evmcs->pin_based_vm_exec_control = vmcs12->pin_based_vm_exec_control;
1861 * evmcs->vm_exit_controls = vmcs12->vm_exit_controls;
1862 * evmcs->secondary_vm_exec_control = vmcs12->secondary_vm_exec_control;
1863 * evmcs->page_fault_error_code_mask =
1864 * vmcs12->page_fault_error_code_mask;
1865 * evmcs->page_fault_error_code_match =
1866 * vmcs12->page_fault_error_code_match;
1867 * evmcs->cr3_target_count = vmcs12->cr3_target_count;
1868 * evmcs->virtual_apic_page_addr = vmcs12->virtual_apic_page_addr;
1869 * evmcs->tsc_offset = vmcs12->tsc_offset;
1870 * evmcs->guest_ia32_debugctl = vmcs12->guest_ia32_debugctl;
1871 * evmcs->cr0_guest_host_mask = vmcs12->cr0_guest_host_mask;
1872 * evmcs->cr4_guest_host_mask = vmcs12->cr4_guest_host_mask;
1873 * evmcs->cr0_read_shadow = vmcs12->cr0_read_shadow;
1874 * evmcs->cr4_read_shadow = vmcs12->cr4_read_shadow;
1875 * evmcs->vm_exit_msr_store_count = vmcs12->vm_exit_msr_store_count;
1876 * evmcs->vm_exit_msr_load_count = vmcs12->vm_exit_msr_load_count;
1877 * evmcs->vm_entry_msr_load_count = vmcs12->vm_entry_msr_load_count;
1879 * Not present in struct vmcs12:
1880 * evmcs->exit_io_instruction_ecx = vmcs12->exit_io_instruction_ecx;
1881 * evmcs->exit_io_instruction_esi = vmcs12->exit_io_instruction_esi;
1882 * evmcs->exit_io_instruction_edi = vmcs12->exit_io_instruction_edi;
1883 * evmcs->exit_io_instruction_eip = vmcs12->exit_io_instruction_eip;
1886 evmcs->guest_es_selector = vmcs12->guest_es_selector;
1887 evmcs->guest_cs_selector = vmcs12->guest_cs_selector;
1888 evmcs->guest_ss_selector = vmcs12->guest_ss_selector;
1889 evmcs->guest_ds_selector = vmcs12->guest_ds_selector;
1890 evmcs->guest_fs_selector = vmcs12->guest_fs_selector;
1891 evmcs->guest_gs_selector = vmcs12->guest_gs_selector;
1892 evmcs->guest_ldtr_selector = vmcs12->guest_ldtr_selector;
1893 evmcs->guest_tr_selector = vmcs12->guest_tr_selector;
1895 evmcs->guest_es_limit = vmcs12->guest_es_limit;
1896 evmcs->guest_cs_limit = vmcs12->guest_cs_limit;
1897 evmcs->guest_ss_limit = vmcs12->guest_ss_limit;
1898 evmcs->guest_ds_limit = vmcs12->guest_ds_limit;
1899 evmcs->guest_fs_limit = vmcs12->guest_fs_limit;
1900 evmcs->guest_gs_limit = vmcs12->guest_gs_limit;
1901 evmcs->guest_ldtr_limit = vmcs12->guest_ldtr_limit;
1902 evmcs->guest_tr_limit = vmcs12->guest_tr_limit;
1903 evmcs->guest_gdtr_limit = vmcs12->guest_gdtr_limit;
1904 evmcs->guest_idtr_limit = vmcs12->guest_idtr_limit;
1906 evmcs->guest_es_ar_bytes = vmcs12->guest_es_ar_bytes;
1907 evmcs->guest_cs_ar_bytes = vmcs12->guest_cs_ar_bytes;
1908 evmcs->guest_ss_ar_bytes = vmcs12->guest_ss_ar_bytes;
1909 evmcs->guest_ds_ar_bytes = vmcs12->guest_ds_ar_bytes;
1910 evmcs->guest_fs_ar_bytes = vmcs12->guest_fs_ar_bytes;
1911 evmcs->guest_gs_ar_bytes = vmcs12->guest_gs_ar_bytes;
1912 evmcs->guest_ldtr_ar_bytes = vmcs12->guest_ldtr_ar_bytes;
1913 evmcs->guest_tr_ar_bytes = vmcs12->guest_tr_ar_bytes;
1915 evmcs->guest_es_base = vmcs12->guest_es_base;
1916 evmcs->guest_cs_base = vmcs12->guest_cs_base;
1917 evmcs->guest_ss_base = vmcs12->guest_ss_base;
1918 evmcs->guest_ds_base = vmcs12->guest_ds_base;
1919 evmcs->guest_fs_base = vmcs12->guest_fs_base;
1920 evmcs->guest_gs_base = vmcs12->guest_gs_base;
1921 evmcs->guest_ldtr_base = vmcs12->guest_ldtr_base;
1922 evmcs->guest_tr_base = vmcs12->guest_tr_base;
1923 evmcs->guest_gdtr_base = vmcs12->guest_gdtr_base;
1924 evmcs->guest_idtr_base = vmcs12->guest_idtr_base;
1926 evmcs->guest_ia32_pat = vmcs12->guest_ia32_pat;
1927 evmcs->guest_ia32_efer = vmcs12->guest_ia32_efer;
1929 evmcs->guest_pdptr0 = vmcs12->guest_pdptr0;
1930 evmcs->guest_pdptr1 = vmcs12->guest_pdptr1;
1931 evmcs->guest_pdptr2 = vmcs12->guest_pdptr2;
1932 evmcs->guest_pdptr3 = vmcs12->guest_pdptr3;
1934 evmcs->guest_pending_dbg_exceptions =
1935 vmcs12->guest_pending_dbg_exceptions;
1936 evmcs->guest_sysenter_esp = vmcs12->guest_sysenter_esp;
1937 evmcs->guest_sysenter_eip = vmcs12->guest_sysenter_eip;
1939 evmcs->guest_activity_state = vmcs12->guest_activity_state;
1940 evmcs->guest_sysenter_cs = vmcs12->guest_sysenter_cs;
1942 evmcs->guest_cr0 = vmcs12->guest_cr0;
1943 evmcs->guest_cr3 = vmcs12->guest_cr3;
1944 evmcs->guest_cr4 = vmcs12->guest_cr4;
1945 evmcs->guest_dr7 = vmcs12->guest_dr7;
1947 evmcs->guest_physical_address = vmcs12->guest_physical_address;
1949 evmcs->vm_instruction_error = vmcs12->vm_instruction_error;
1950 evmcs->vm_exit_reason = vmcs12->vm_exit_reason;
1951 evmcs->vm_exit_intr_info = vmcs12->vm_exit_intr_info;
1952 evmcs->vm_exit_intr_error_code = vmcs12->vm_exit_intr_error_code;
1953 evmcs->idt_vectoring_info_field = vmcs12->idt_vectoring_info_field;
1954 evmcs->idt_vectoring_error_code = vmcs12->idt_vectoring_error_code;
1955 evmcs->vm_exit_instruction_len = vmcs12->vm_exit_instruction_len;
1956 evmcs->vmx_instruction_info = vmcs12->vmx_instruction_info;
1958 evmcs->exit_qualification = vmcs12->exit_qualification;
1960 evmcs->guest_linear_address = vmcs12->guest_linear_address;
1961 evmcs->guest_rsp = vmcs12->guest_rsp;
1962 evmcs->guest_rflags = vmcs12->guest_rflags;
1964 evmcs->guest_interruptibility_info =
1965 vmcs12->guest_interruptibility_info;
1966 evmcs->cpu_based_vm_exec_control = vmcs12->cpu_based_vm_exec_control;
1967 evmcs->vm_entry_controls = vmcs12->vm_entry_controls;
1968 evmcs->vm_entry_intr_info_field = vmcs12->vm_entry_intr_info_field;
1969 evmcs->vm_entry_exception_error_code =
1970 vmcs12->vm_entry_exception_error_code;
1971 evmcs->vm_entry_instruction_len = vmcs12->vm_entry_instruction_len;
1973 evmcs->guest_rip = vmcs12->guest_rip;
1975 evmcs->guest_bndcfgs = vmcs12->guest_bndcfgs;
1981 * This is an equivalent of the nested hypervisor executing the vmptrld
1984 static enum nested_evmptrld_status nested_vmx_handle_enlightened_vmptrld(
1985 struct kvm_vcpu *vcpu, bool from_launch)
1987 struct vcpu_vmx *vmx = to_vmx(vcpu);
1988 bool evmcs_gpa_changed = false;
1991 if (likely(!vmx->nested.enlightened_vmcs_enabled))
1992 return EVMPTRLD_DISABLED;
1994 if (!nested_enlightened_vmentry(vcpu, &evmcs_gpa))
1995 return EVMPTRLD_DISABLED;
1997 if (unlikely(!vmx->nested.hv_evmcs ||
1998 evmcs_gpa != vmx->nested.hv_evmcs_vmptr)) {
1999 if (!vmx->nested.hv_evmcs)
2000 vmx->nested.current_vmptr = -1ull;
2002 nested_release_evmcs(vcpu);
2004 if (kvm_vcpu_map(vcpu, gpa_to_gfn(evmcs_gpa),
2005 &vmx->nested.hv_evmcs_map))
2006 return EVMPTRLD_ERROR;
2008 vmx->nested.hv_evmcs = vmx->nested.hv_evmcs_map.hva;
2011 * Currently, KVM only supports eVMCS version 1
2012 * (== KVM_EVMCS_VERSION) and thus we expect guest to set this
2013 * value to first u32 field of eVMCS which should specify eVMCS
2016 * Guest should be aware of supported eVMCS versions by host by
2017 * examining CPUID.0x4000000A.EAX[0:15]. Host userspace VMM is
2018 * expected to set this CPUID leaf according to the value
2019 * returned in vmcs_version from nested_enable_evmcs().
2021 * However, it turns out that Microsoft Hyper-V fails to comply
2022 * to their own invented interface: When Hyper-V use eVMCS, it
2023 * just sets first u32 field of eVMCS to revision_id specified
2024 * in MSR_IA32_VMX_BASIC. Instead of used eVMCS version number
2025 * which is one of the supported versions specified in
2026 * CPUID.0x4000000A.EAX[0:15].
2028 * To overcome Hyper-V bug, we accept here either a supported
2029 * eVMCS version or VMCS12 revision_id as valid values for first
2030 * u32 field of eVMCS.
2032 if ((vmx->nested.hv_evmcs->revision_id != KVM_EVMCS_VERSION) &&
2033 (vmx->nested.hv_evmcs->revision_id != VMCS12_REVISION)) {
2034 nested_release_evmcs(vcpu);
2035 return EVMPTRLD_VMFAIL;
2038 vmx->nested.dirty_vmcs12 = true;
2039 vmx->nested.hv_evmcs_vmptr = evmcs_gpa;
2041 evmcs_gpa_changed = true;
2043 * Unlike normal vmcs12, enlightened vmcs12 is not fully
2044 * reloaded from guest's memory (read only fields, fields not
2045 * present in struct hv_enlightened_vmcs, ...). Make sure there
2049 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2050 memset(vmcs12, 0, sizeof(*vmcs12));
2051 vmcs12->hdr.revision_id = VMCS12_REVISION;
2057 * Clean fields data can't be used on VMLAUNCH and when we switch
2058 * between different L2 guests as KVM keeps a single VMCS12 per L1.
2060 if (from_launch || evmcs_gpa_changed)
2061 vmx->nested.hv_evmcs->hv_clean_fields &=
2062 ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
2064 return EVMPTRLD_SUCCEEDED;
2067 void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu)
2069 struct vcpu_vmx *vmx = to_vmx(vcpu);
2071 if (vmx->nested.hv_evmcs) {
2072 copy_vmcs12_to_enlightened(vmx);
2073 /* All fields are clean */
2074 vmx->nested.hv_evmcs->hv_clean_fields |=
2075 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
2077 copy_vmcs12_to_shadow(vmx);
2080 vmx->nested.need_vmcs12_to_shadow_sync = false;
2083 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
2085 struct vcpu_vmx *vmx =
2086 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
2088 vmx->nested.preemption_timer_expired = true;
2089 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
2090 kvm_vcpu_kick(&vmx->vcpu);
2092 return HRTIMER_NORESTART;
2095 static u64 vmx_calc_preemption_timer_value(struct kvm_vcpu *vcpu)
2097 struct vcpu_vmx *vmx = to_vmx(vcpu);
2098 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100 u64 l1_scaled_tsc = kvm_read_l1_tsc(vcpu, rdtsc()) >>
2101 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
2103 if (!vmx->nested.has_preemption_timer_deadline) {
2104 vmx->nested.preemption_timer_deadline =
2105 vmcs12->vmx_preemption_timer_value + l1_scaled_tsc;
2106 vmx->nested.has_preemption_timer_deadline = true;
2108 return vmx->nested.preemption_timer_deadline - l1_scaled_tsc;
2111 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu,
2112 u64 preemption_timeout)
2114 struct vcpu_vmx *vmx = to_vmx(vcpu);
2117 * A timer value of zero is architecturally guaranteed to cause
2118 * a VMExit prior to executing any instructions in the guest.
2120 if (preemption_timeout == 0) {
2121 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
2125 if (vcpu->arch.virtual_tsc_khz == 0)
2128 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
2129 preemption_timeout *= 1000000;
2130 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
2131 hrtimer_start(&vmx->nested.preemption_timer,
2132 ktime_add_ns(ktime_get(), preemption_timeout),
2133 HRTIMER_MODE_ABS_PINNED);
2136 static u64 nested_vmx_calc_efer(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
2138 if (vmx->nested.nested_run_pending &&
2139 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
2140 return vmcs12->guest_ia32_efer;
2141 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
2142 return vmx->vcpu.arch.efer | (EFER_LMA | EFER_LME);
2144 return vmx->vcpu.arch.efer & ~(EFER_LMA | EFER_LME);
2147 static void prepare_vmcs02_constant_state(struct vcpu_vmx *vmx)
2150 * If vmcs02 hasn't been initialized, set the constant vmcs02 state
2151 * according to L0's settings (vmcs12 is irrelevant here). Host
2152 * fields that come from L0 and are not constant, e.g. HOST_CR3,
2153 * will be set as needed prior to VMLAUNCH/VMRESUME.
2155 if (vmx->nested.vmcs02_initialized)
2157 vmx->nested.vmcs02_initialized = true;
2160 * We don't care what the EPTP value is we just need to guarantee
2161 * it's valid so we don't get a false positive when doing early
2162 * consistency checks.
2164 if (enable_ept && nested_early_check)
2165 vmcs_write64(EPT_POINTER,
2166 construct_eptp(&vmx->vcpu, 0, PT64_ROOT_4LEVEL));
2168 /* All VMFUNCs are currently emulated through L0 vmexits. */
2169 if (cpu_has_vmx_vmfunc())
2170 vmcs_write64(VM_FUNCTION_CONTROL, 0);
2172 if (cpu_has_vmx_posted_intr())
2173 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
2175 if (cpu_has_vmx_msr_bitmap())
2176 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
2179 * The PML address never changes, so it is constant in vmcs02.
2180 * Conceptually we want to copy the PML index from vmcs01 here,
2181 * and then back to vmcs01 on nested vmexit. But since we flush
2182 * the log and reset GUEST_PML_INDEX on each vmexit, the PML
2183 * index is also effectively constant in vmcs02.
2186 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
2187 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
2190 if (cpu_has_vmx_encls_vmexit())
2191 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
2194 * Set the MSR load/store lists to match L0's settings. Only the
2195 * addresses are constant (for vmcs02), the counts can change based
2196 * on L2's behavior, e.g. switching to/from long mode.
2198 vmcs_write64(VM_EXIT_MSR_STORE_ADDR, __pa(vmx->msr_autostore.guest.val));
2199 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2200 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
2202 vmx_set_constant_host_state(vmx);
2205 static void prepare_vmcs02_early_rare(struct vcpu_vmx *vmx,
2206 struct vmcs12 *vmcs12)
2208 prepare_vmcs02_constant_state(vmx);
2210 vmcs_write64(VMCS_LINK_POINTER, -1ull);
2213 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
2214 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
2216 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2220 static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
2222 u32 exec_control, vmcs12_exec_ctrl;
2223 u64 guest_efer = nested_vmx_calc_efer(vmx, vmcs12);
2225 if (vmx->nested.dirty_vmcs12 || vmx->nested.hv_evmcs)
2226 prepare_vmcs02_early_rare(vmx, vmcs12);
2231 exec_control = vmx_pin_based_exec_ctrl(vmx);
2232 exec_control |= (vmcs12->pin_based_vm_exec_control &
2233 ~PIN_BASED_VMX_PREEMPTION_TIMER);
2235 /* Posted interrupts setting is only taken from vmcs12. */
2236 if (nested_cpu_has_posted_intr(vmcs12)) {
2237 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
2238 vmx->nested.pi_pending = false;
2240 exec_control &= ~PIN_BASED_POSTED_INTR;
2242 pin_controls_set(vmx, exec_control);
2247 exec_control = vmx_exec_control(vmx); /* L0's desires */
2248 exec_control &= ~CPU_BASED_INTR_WINDOW_EXITING;
2249 exec_control &= ~CPU_BASED_NMI_WINDOW_EXITING;
2250 exec_control &= ~CPU_BASED_TPR_SHADOW;
2251 exec_control |= vmcs12->cpu_based_vm_exec_control;
2253 vmx->nested.l1_tpr_threshold = -1;
2254 if (exec_control & CPU_BASED_TPR_SHADOW)
2255 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
2256 #ifdef CONFIG_X86_64
2258 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
2259 CPU_BASED_CR8_STORE_EXITING;
2263 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
2264 * for I/O port accesses.
2266 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
2267 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
2270 * This bit will be computed in nested_get_vmcs12_pages, because
2271 * we do not have access to L1's MSR bitmap yet. For now, keep
2272 * the same bit as before, hoping to avoid multiple VMWRITEs that
2273 * only set/clear this bit.
2275 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
2276 exec_control |= exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS;
2278 exec_controls_set(vmx, exec_control);
2281 * SECONDARY EXEC CONTROLS
2283 if (cpu_has_secondary_exec_ctrls()) {
2284 exec_control = vmx->secondary_exec_control;
2286 /* Take the following fields only from vmcs12 */
2287 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2288 SECONDARY_EXEC_ENABLE_INVPCID |
2289 SECONDARY_EXEC_RDTSCP |
2290 SECONDARY_EXEC_XSAVES |
2291 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2292 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2293 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2294 SECONDARY_EXEC_ENABLE_VMFUNC);
2295 if (nested_cpu_has(vmcs12,
2296 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
2297 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
2298 ~SECONDARY_EXEC_ENABLE_PML;
2299 exec_control |= vmcs12_exec_ctrl;
2302 /* VMCS shadowing for L2 is emulated for now */
2303 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
2306 * Preset *DT exiting when emulating UMIP, so that vmx_set_cr4()
2307 * will not have to rewrite the controls just for this bit.
2309 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated() &&
2310 (vmcs12->guest_cr4 & X86_CR4_UMIP))
2311 exec_control |= SECONDARY_EXEC_DESC;
2313 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
2314 vmcs_write16(GUEST_INTR_STATUS,
2315 vmcs12->guest_intr_status);
2317 secondary_exec_controls_set(vmx, exec_control);
2323 * vmcs12's VM_{ENTRY,EXIT}_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE
2324 * are emulated by vmx_set_efer() in prepare_vmcs02(), but speculate
2325 * on the related bits (if supported by the CPU) in the hope that
2326 * we can avoid VMWrites during vmx_set_efer().
2328 exec_control = (vmcs12->vm_entry_controls | vmx_vmentry_ctrl()) &
2329 ~VM_ENTRY_IA32E_MODE & ~VM_ENTRY_LOAD_IA32_EFER;
2330 if (cpu_has_load_ia32_efer()) {
2331 if (guest_efer & EFER_LMA)
2332 exec_control |= VM_ENTRY_IA32E_MODE;
2333 if (guest_efer != host_efer)
2334 exec_control |= VM_ENTRY_LOAD_IA32_EFER;
2336 vm_entry_controls_set(vmx, exec_control);
2341 * L2->L1 exit controls are emulated - the hardware exit is to L0 so
2342 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
2343 * bits may be modified by vmx_set_efer() in prepare_vmcs02().
2345 exec_control = vmx_vmexit_ctrl();
2346 if (cpu_has_load_ia32_efer() && guest_efer != host_efer)
2347 exec_control |= VM_EXIT_LOAD_IA32_EFER;
2348 vm_exit_controls_set(vmx, exec_control);
2351 * Interrupt/Exception Fields
2353 if (vmx->nested.nested_run_pending) {
2354 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2355 vmcs12->vm_entry_intr_info_field);
2356 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2357 vmcs12->vm_entry_exception_error_code);
2358 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2359 vmcs12->vm_entry_instruction_len);
2360 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
2361 vmcs12->guest_interruptibility_info);
2362 vmx->loaded_vmcs->nmi_known_unmasked =
2363 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
2365 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
2369 static void prepare_vmcs02_rare(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
2371 struct hv_enlightened_vmcs *hv_evmcs = vmx->nested.hv_evmcs;
2373 if (!hv_evmcs || !(hv_evmcs->hv_clean_fields &
2374 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2)) {
2375 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
2376 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
2377 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
2378 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
2379 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
2380 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
2381 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
2382 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
2383 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
2384 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
2385 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
2386 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
2387 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
2388 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
2389 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
2390 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
2391 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
2392 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
2393 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
2394 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
2395 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
2396 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
2397 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
2398 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
2399 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
2400 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
2401 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
2402 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
2403 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
2404 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
2405 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
2406 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
2407 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
2408 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
2409 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
2410 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
2413 if (!hv_evmcs || !(hv_evmcs->hv_clean_fields &
2414 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1)) {
2415 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
2416 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
2417 vmcs12->guest_pending_dbg_exceptions);
2418 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
2419 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
2422 * L1 may access the L2's PDPTR, so save them to construct
2426 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
2427 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
2428 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
2429 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
2432 if (kvm_mpx_supported() && vmx->nested.nested_run_pending &&
2433 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
2434 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
2437 if (nested_cpu_has_xsaves(vmcs12))
2438 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
2441 * Whether page-faults are trapped is determined by a combination of
2442 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. If L0
2443 * doesn't care about page faults then we should set all of these to
2444 * L1's desires. However, if L0 does care about (some) page faults, it
2445 * is not easy (if at all possible?) to merge L0 and L1's desires, we
2446 * simply ask to exit on each and every L2 page fault. This is done by
2447 * setting MASK=MATCH=0 and (see below) EB.PF=1.
2448 * Note that below we don't need special code to set EB.PF beyond the
2449 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
2450 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
2451 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
2453 if (vmx_need_pf_intercept(&vmx->vcpu)) {
2455 * TODO: if both L0 and L1 need the same MASK and MATCH,
2456 * go ahead and use it?
2458 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
2459 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
2461 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, vmcs12->page_fault_error_code_mask);
2462 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, vmcs12->page_fault_error_code_match);
2465 if (cpu_has_vmx_apicv()) {
2466 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
2467 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
2468 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
2469 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
2473 * Make sure the msr_autostore list is up to date before we set the
2474 * count in the vmcs02.
2476 prepare_vmx_msr_autostore_list(&vmx->vcpu, MSR_IA32_TSC);
2478 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, vmx->msr_autostore.guest.nr);
2479 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
2480 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
2482 set_cr4_guest_host_mask(vmx);
2486 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
2487 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
2488 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
2489 * guest in a way that will both be appropriate to L1's requests, and our
2490 * needs. In addition to modifying the active vmcs (which is vmcs02), this
2491 * function also has additional necessary side-effects, like setting various
2492 * vcpu->arch fields.
2493 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
2494 * is assigned to entry_failure_code on failure.
2496 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
2497 enum vm_entry_failure_code *entry_failure_code)
2499 struct vcpu_vmx *vmx = to_vmx(vcpu);
2500 struct hv_enlightened_vmcs *hv_evmcs = vmx->nested.hv_evmcs;
2501 bool load_guest_pdptrs_vmcs12 = false;
2503 if (vmx->nested.dirty_vmcs12 || hv_evmcs) {
2504 prepare_vmcs02_rare(vmx, vmcs12);
2505 vmx->nested.dirty_vmcs12 = false;
2507 load_guest_pdptrs_vmcs12 = !hv_evmcs ||
2508 !(hv_evmcs->hv_clean_fields &
2509 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1);
2512 if (vmx->nested.nested_run_pending &&
2513 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
2514 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
2515 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
2517 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
2518 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
2520 if (kvm_mpx_supported() && (!vmx->nested.nested_run_pending ||
2521 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)))
2522 vmcs_write64(GUEST_BNDCFGS, vmx->nested.vmcs01_guest_bndcfgs);
2523 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
2525 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
2526 * bitwise-or of what L1 wants to trap for L2, and what we want to
2527 * trap. Note that CR0.TS also needs updating - we do this later.
2529 update_exception_bitmap(vcpu);
2530 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
2531 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2533 if (vmx->nested.nested_run_pending &&
2534 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
2535 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
2536 vcpu->arch.pat = vmcs12->guest_ia32_pat;
2537 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2538 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
2541 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
2543 if (kvm_has_tsc_control)
2544 decache_tsc_multiplier(vmx);
2546 nested_vmx_transition_tlb_flush(vcpu, vmcs12, true);
2548 if (nested_cpu_has_ept(vmcs12))
2549 nested_ept_init_mmu_context(vcpu);
2552 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
2553 * bits which we consider mandatory enabled.
2554 * The CR0_READ_SHADOW is what L2 should have expected to read given
2555 * the specifications by L1; It's not enough to take
2556 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
2557 * have more bits than L1 expected.
2559 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
2560 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2562 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
2563 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
2565 vcpu->arch.efer = nested_vmx_calc_efer(vmx, vmcs12);
2566 /* Note: may modify VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
2567 vmx_set_efer(vcpu, vcpu->arch.efer);
2570 * Guest state is invalid and unrestricted guest is disabled,
2571 * which means L1 attempted VMEntry to L2 with invalid state.
2574 if (vmx->emulation_required) {
2575 *entry_failure_code = ENTRY_FAIL_DEFAULT;
2579 /* Shadow page tables on either EPT or shadow page tables. */
2580 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
2581 entry_failure_code))
2585 * Immediately write vmcs02.GUEST_CR3. It will be propagated to vmcs12
2586 * on nested VM-Exit, which can occur without actually running L2 and
2587 * thus without hitting vmx_load_mmu_pgd(), e.g. if L1 is entering L2 with
2588 * vmcs12.GUEST_ACTIVITYSTATE=HLT, in which case KVM will intercept the
2589 * transition to HLT instead of running L2.
2592 vmcs_writel(GUEST_CR3, vmcs12->guest_cr3);
2594 /* Late preparation of GUEST_PDPTRs now that EFER and CRs are set. */
2595 if (load_guest_pdptrs_vmcs12 && nested_cpu_has_ept(vmcs12) &&
2596 is_pae_paging(vcpu)) {
2597 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
2598 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
2599 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
2600 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
2604 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
2606 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
2607 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
2608 vmcs12->guest_ia32_perf_global_ctrl)))
2611 kvm_rsp_write(vcpu, vmcs12->guest_rsp);
2612 kvm_rip_write(vcpu, vmcs12->guest_rip);
2616 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
2618 if (CC(!nested_cpu_has_nmi_exiting(vmcs12) &&
2619 nested_cpu_has_virtual_nmis(vmcs12)))
2622 if (CC(!nested_cpu_has_virtual_nmis(vmcs12) &&
2623 nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING)))
2629 static bool nested_vmx_check_eptp(struct kvm_vcpu *vcpu, u64 new_eptp)
2631 struct vcpu_vmx *vmx = to_vmx(vcpu);
2632 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2634 /* Check for memory type validity */
2635 switch (new_eptp & VMX_EPTP_MT_MASK) {
2636 case VMX_EPTP_MT_UC:
2637 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT)))
2640 case VMX_EPTP_MT_WB:
2641 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT)))
2648 /* Page-walk levels validity. */
2649 switch (new_eptp & VMX_EPTP_PWL_MASK) {
2650 case VMX_EPTP_PWL_5:
2651 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_PAGE_WALK_5_BIT)))
2654 case VMX_EPTP_PWL_4:
2655 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_PAGE_WALK_4_BIT)))
2662 /* Reserved bits should not be set */
2663 if (CC(new_eptp >> maxphyaddr || ((new_eptp >> 7) & 0x1f)))
2666 /* AD, if set, should be supported */
2667 if (new_eptp & VMX_EPTP_AD_ENABLE_BIT) {
2668 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT)))
2676 * Checks related to VM-Execution Control Fields
2678 static int nested_check_vm_execution_controls(struct kvm_vcpu *vcpu,
2679 struct vmcs12 *vmcs12)
2681 struct vcpu_vmx *vmx = to_vmx(vcpu);
2683 if (CC(!vmx_control_verify(vmcs12->pin_based_vm_exec_control,
2684 vmx->nested.msrs.pinbased_ctls_low,
2685 vmx->nested.msrs.pinbased_ctls_high)) ||
2686 CC(!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
2687 vmx->nested.msrs.procbased_ctls_low,
2688 vmx->nested.msrs.procbased_ctls_high)))
2691 if (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
2692 CC(!vmx_control_verify(vmcs12->secondary_vm_exec_control,
2693 vmx->nested.msrs.secondary_ctls_low,
2694 vmx->nested.msrs.secondary_ctls_high)))
2697 if (CC(vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) ||
2698 nested_vmx_check_io_bitmap_controls(vcpu, vmcs12) ||
2699 nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12) ||
2700 nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12) ||
2701 nested_vmx_check_apic_access_controls(vcpu, vmcs12) ||
2702 nested_vmx_check_apicv_controls(vcpu, vmcs12) ||
2703 nested_vmx_check_nmi_controls(vmcs12) ||
2704 nested_vmx_check_pml_controls(vcpu, vmcs12) ||
2705 nested_vmx_check_unrestricted_guest_controls(vcpu, vmcs12) ||
2706 nested_vmx_check_mode_based_ept_exec_controls(vcpu, vmcs12) ||
2707 nested_vmx_check_shadow_vmcs_controls(vcpu, vmcs12) ||
2708 CC(nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id))
2711 if (!nested_cpu_has_preemption_timer(vmcs12) &&
2712 nested_cpu_has_save_preemption_timer(vmcs12))
2715 if (nested_cpu_has_ept(vmcs12) &&
2716 CC(!nested_vmx_check_eptp(vcpu, vmcs12->ept_pointer)))
2719 if (nested_cpu_has_vmfunc(vmcs12)) {
2720 if (CC(vmcs12->vm_function_control &
2721 ~vmx->nested.msrs.vmfunc_controls))
2724 if (nested_cpu_has_eptp_switching(vmcs12)) {
2725 if (CC(!nested_cpu_has_ept(vmcs12)) ||
2726 CC(!page_address_valid(vcpu, vmcs12->eptp_list_address)))
2735 * Checks related to VM-Exit Control Fields
2737 static int nested_check_vm_exit_controls(struct kvm_vcpu *vcpu,
2738 struct vmcs12 *vmcs12)
2740 struct vcpu_vmx *vmx = to_vmx(vcpu);
2742 if (CC(!vmx_control_verify(vmcs12->vm_exit_controls,
2743 vmx->nested.msrs.exit_ctls_low,
2744 vmx->nested.msrs.exit_ctls_high)) ||
2745 CC(nested_vmx_check_exit_msr_switch_controls(vcpu, vmcs12)))
2752 * Checks related to VM-Entry Control Fields
2754 static int nested_check_vm_entry_controls(struct kvm_vcpu *vcpu,
2755 struct vmcs12 *vmcs12)
2757 struct vcpu_vmx *vmx = to_vmx(vcpu);
2759 if (CC(!vmx_control_verify(vmcs12->vm_entry_controls,
2760 vmx->nested.msrs.entry_ctls_low,
2761 vmx->nested.msrs.entry_ctls_high)))
2765 * From the Intel SDM, volume 3:
2766 * Fields relevant to VM-entry event injection must be set properly.
2767 * These fields are the VM-entry interruption-information field, the
2768 * VM-entry exception error code, and the VM-entry instruction length.
2770 if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) {
2771 u32 intr_info = vmcs12->vm_entry_intr_info_field;
2772 u8 vector = intr_info & INTR_INFO_VECTOR_MASK;
2773 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK;
2774 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK;
2775 bool should_have_error_code;
2776 bool urg = nested_cpu_has2(vmcs12,
2777 SECONDARY_EXEC_UNRESTRICTED_GUEST);
2778 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE;
2780 /* VM-entry interruption-info field: interruption type */
2781 if (CC(intr_type == INTR_TYPE_RESERVED) ||
2782 CC(intr_type == INTR_TYPE_OTHER_EVENT &&
2783 !nested_cpu_supports_monitor_trap_flag(vcpu)))
2786 /* VM-entry interruption-info field: vector */
2787 if (CC(intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) ||
2788 CC(intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) ||
2789 CC(intr_type == INTR_TYPE_OTHER_EVENT && vector != 0))
2792 /* VM-entry interruption-info field: deliver error code */
2793 should_have_error_code =
2794 intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode &&
2795 x86_exception_has_error_code(vector);
2796 if (CC(has_error_code != should_have_error_code))
2799 /* VM-entry exception error code */
2800 if (CC(has_error_code &&
2801 vmcs12->vm_entry_exception_error_code & GENMASK(31, 16)))
2804 /* VM-entry interruption-info field: reserved bits */
2805 if (CC(intr_info & INTR_INFO_RESVD_BITS_MASK))
2808 /* VM-entry instruction length */
2809 switch (intr_type) {
2810 case INTR_TYPE_SOFT_EXCEPTION:
2811 case INTR_TYPE_SOFT_INTR:
2812 case INTR_TYPE_PRIV_SW_EXCEPTION:
2813 if (CC(vmcs12->vm_entry_instruction_len > 15) ||
2814 CC(vmcs12->vm_entry_instruction_len == 0 &&
2815 CC(!nested_cpu_has_zero_length_injection(vcpu))))
2820 if (nested_vmx_check_entry_msr_switch_controls(vcpu, vmcs12))
2826 static int nested_vmx_check_controls(struct kvm_vcpu *vcpu,
2827 struct vmcs12 *vmcs12)
2829 if (nested_check_vm_execution_controls(vcpu, vmcs12) ||
2830 nested_check_vm_exit_controls(vcpu, vmcs12) ||
2831 nested_check_vm_entry_controls(vcpu, vmcs12))
2834 if (to_vmx(vcpu)->nested.enlightened_vmcs_enabled)
2835 return nested_evmcs_check_controls(vmcs12);
2840 static int nested_vmx_check_host_state(struct kvm_vcpu *vcpu,
2841 struct vmcs12 *vmcs12)
2845 if (CC(!nested_host_cr0_valid(vcpu, vmcs12->host_cr0)) ||
2846 CC(!nested_host_cr4_valid(vcpu, vmcs12->host_cr4)) ||
2847 CC(!nested_cr3_valid(vcpu, vmcs12->host_cr3)))
2850 if (CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_esp, vcpu)) ||
2851 CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_eip, vcpu)))
2854 if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) &&
2855 CC(!kvm_pat_valid(vmcs12->host_ia32_pat)))
2858 if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) &&
2859 CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu),
2860 vmcs12->host_ia32_perf_global_ctrl)))
2863 #ifdef CONFIG_X86_64
2864 ia32e = !!(vcpu->arch.efer & EFER_LMA);
2870 if (CC(!(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)) ||
2871 CC(!(vmcs12->host_cr4 & X86_CR4_PAE)))
2874 if (CC(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) ||
2875 CC(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) ||
2876 CC(vmcs12->host_cr4 & X86_CR4_PCIDE) ||
2877 CC((vmcs12->host_rip) >> 32))
2881 if (CC(vmcs12->host_cs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2882 CC(vmcs12->host_ss_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2883 CC(vmcs12->host_ds_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2884 CC(vmcs12->host_es_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2885 CC(vmcs12->host_fs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2886 CC(vmcs12->host_gs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2887 CC(vmcs12->host_tr_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2888 CC(vmcs12->host_cs_selector == 0) ||
2889 CC(vmcs12->host_tr_selector == 0) ||
2890 CC(vmcs12->host_ss_selector == 0 && !ia32e))
2893 if (CC(is_noncanonical_address(vmcs12->host_fs_base, vcpu)) ||
2894 CC(is_noncanonical_address(vmcs12->host_gs_base, vcpu)) ||
2895 CC(is_noncanonical_address(vmcs12->host_gdtr_base, vcpu)) ||
2896 CC(is_noncanonical_address(vmcs12->host_idtr_base, vcpu)) ||
2897 CC(is_noncanonical_address(vmcs12->host_tr_base, vcpu)) ||
2898 CC(is_noncanonical_address(vmcs12->host_rip, vcpu)))
2902 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
2903 * IA32_EFER MSR must be 0 in the field for that register. In addition,
2904 * the values of the LMA and LME bits in the field must each be that of
2905 * the host address-space size VM-exit control.
2907 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
2908 if (CC(!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer)) ||
2909 CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA)) ||
2910 CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)))
2917 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu,
2918 struct vmcs12 *vmcs12)
2921 struct vmcs12 *shadow;
2922 struct kvm_host_map map;
2924 if (vmcs12->vmcs_link_pointer == -1ull)
2927 if (CC(!page_address_valid(vcpu, vmcs12->vmcs_link_pointer)))
2930 if (CC(kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->vmcs_link_pointer), &map)))
2935 if (CC(shadow->hdr.revision_id != VMCS12_REVISION) ||
2936 CC(shadow->hdr.shadow_vmcs != nested_cpu_has_shadow_vmcs(vmcs12)))
2939 kvm_vcpu_unmap(vcpu, &map, false);
2944 * Checks related to Guest Non-register State
2946 static int nested_check_guest_non_reg_state(struct vmcs12 *vmcs12)
2948 if (CC(vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
2949 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT))
2955 static int nested_vmx_check_guest_state(struct kvm_vcpu *vcpu,
2956 struct vmcs12 *vmcs12,
2957 enum vm_entry_failure_code *entry_failure_code)
2961 *entry_failure_code = ENTRY_FAIL_DEFAULT;
2963 if (CC(!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0)) ||
2964 CC(!nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)))
2967 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) &&
2968 CC(!kvm_dr7_valid(vmcs12->guest_dr7)))
2971 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) &&
2972 CC(!kvm_pat_valid(vmcs12->guest_ia32_pat)))
2975 if (nested_vmx_check_vmcs_link_ptr(vcpu, vmcs12)) {
2976 *entry_failure_code = ENTRY_FAIL_VMCS_LINK_PTR;
2980 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
2981 CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu),
2982 vmcs12->guest_ia32_perf_global_ctrl)))
2986 * If the load IA32_EFER VM-entry control is 1, the following checks
2987 * are performed on the field for the IA32_EFER MSR:
2988 * - Bits reserved in the IA32_EFER MSR must be 0.
2989 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
2990 * the IA-32e mode guest VM-exit control. It must also be identical
2991 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
2994 if (to_vmx(vcpu)->nested.nested_run_pending &&
2995 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
2996 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
2997 if (CC(!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer)) ||
2998 CC(ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA)) ||
2999 CC(((vmcs12->guest_cr0 & X86_CR0_PG) &&
3000 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))))
3004 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
3005 (CC(is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu)) ||
3006 CC((vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD))))
3009 if (nested_check_guest_non_reg_state(vmcs12))
3015 static int nested_vmx_check_vmentry_hw(struct kvm_vcpu *vcpu)
3017 struct vcpu_vmx *vmx = to_vmx(vcpu);
3018 unsigned long cr3, cr4;
3021 if (!nested_early_check)
3024 if (vmx->msr_autoload.host.nr)
3025 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3026 if (vmx->msr_autoload.guest.nr)
3027 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3031 vmx_prepare_switch_to_guest(vcpu);
3034 * Induce a consistency check VMExit by clearing bit 1 in GUEST_RFLAGS,
3035 * which is reserved to '1' by hardware. GUEST_RFLAGS is guaranteed to
3036 * be written (by prepare_vmcs02()) before the "real" VMEnter, i.e.
3037 * there is no need to preserve other bits or save/restore the field.
3039 vmcs_writel(GUEST_RFLAGS, 0);
3041 cr3 = __get_current_cr3_fast();
3042 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
3043 vmcs_writel(HOST_CR3, cr3);
3044 vmx->loaded_vmcs->host_state.cr3 = cr3;
3047 cr4 = cr4_read_shadow();
3048 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
3049 vmcs_writel(HOST_CR4, cr4);
3050 vmx->loaded_vmcs->host_state.cr4 = cr4;
3054 "sub $%c[wordsize], %%" _ASM_SP "\n\t" /* temporarily adjust RSP for CALL */
3055 "cmp %%" _ASM_SP ", %c[host_state_rsp](%[loaded_vmcs]) \n\t"
3057 __ex("vmwrite %%" _ASM_SP ", %[HOST_RSP]") "\n\t"
3058 "mov %%" _ASM_SP ", %c[host_state_rsp](%[loaded_vmcs]) \n\t"
3060 "add $%c[wordsize], %%" _ASM_SP "\n\t" /* un-adjust RSP */
3062 /* Check if vmlaunch or vmresume is needed */
3063 "cmpb $0, %c[launched](%[loaded_vmcs])\n\t"
3066 * VMLAUNCH and VMRESUME clear RFLAGS.{CF,ZF} on VM-Exit, set
3067 * RFLAGS.CF on VM-Fail Invalid and set RFLAGS.ZF on VM-Fail
3068 * Valid. vmx_vmenter() directly "returns" RFLAGS, and so the
3069 * results of VM-Enter is captured via CC_{SET,OUT} to vm_fail.
3071 "call vmx_vmenter\n\t"
3074 : ASM_CALL_CONSTRAINT, CC_OUT(be) (vm_fail)
3075 : [HOST_RSP]"r"((unsigned long)HOST_RSP),
3076 [loaded_vmcs]"r"(vmx->loaded_vmcs),
3077 [launched]"i"(offsetof(struct loaded_vmcs, launched)),
3078 [host_state_rsp]"i"(offsetof(struct loaded_vmcs, host_state.rsp)),
3079 [wordsize]"i"(sizeof(ulong))
3083 if (vmx->msr_autoload.host.nr)
3084 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
3085 if (vmx->msr_autoload.guest.nr)
3086 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
3089 u32 error = vmcs_read32(VM_INSTRUCTION_ERROR);
3093 trace_kvm_nested_vmenter_failed(
3094 "early hardware check VM-instruction error: ", error);
3095 WARN_ON_ONCE(error != VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3100 * VMExit clears RFLAGS.IF and DR7, even on a consistency check.
3102 if (hw_breakpoint_active())
3103 set_debugreg(__this_cpu_read(cpu_dr7), 7);
3108 * A non-failing VMEntry means we somehow entered guest mode with
3109 * an illegal RIP, and that's just the tip of the iceberg. There
3110 * is no telling what memory has been modified or what state has
3111 * been exposed to unknown code. Hitting this all but guarantees
3112 * a (very critical) hardware issue.
3114 WARN_ON(!(vmcs_read32(VM_EXIT_REASON) &
3115 VMX_EXIT_REASONS_FAILED_VMENTRY));
3120 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
3122 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3123 struct vcpu_vmx *vmx = to_vmx(vcpu);
3124 struct kvm_host_map *map;
3129 * hv_evmcs may end up being not mapped after migration (when
3130 * L2 was running), map it here to make sure vmcs12 changes are
3131 * properly reflected.
3133 if (vmx->nested.enlightened_vmcs_enabled && !vmx->nested.hv_evmcs) {
3134 enum nested_evmptrld_status evmptrld_status =
3135 nested_vmx_handle_enlightened_vmptrld(vcpu, false);
3137 if (evmptrld_status == EVMPTRLD_VMFAIL ||
3138 evmptrld_status == EVMPTRLD_ERROR) {
3139 pr_debug_ratelimited("%s: enlightened vmptrld failed\n",
3141 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3142 vcpu->run->internal.suberror =
3143 KVM_INTERNAL_ERROR_EMULATION;
3144 vcpu->run->internal.ndata = 0;
3149 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
3151 * Translate L1 physical address to host physical
3152 * address for vmcs02. Keep the page pinned, so this
3153 * physical address remains valid. We keep a reference
3154 * to it so we can release it later.
3156 if (vmx->nested.apic_access_page) { /* shouldn't happen */
3157 kvm_release_page_clean(vmx->nested.apic_access_page);
3158 vmx->nested.apic_access_page = NULL;
3160 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
3161 if (!is_error_page(page)) {
3162 vmx->nested.apic_access_page = page;
3163 hpa = page_to_phys(vmx->nested.apic_access_page);
3164 vmcs_write64(APIC_ACCESS_ADDR, hpa);
3166 pr_debug_ratelimited("%s: no backing 'struct page' for APIC-access address in vmcs12\n",
3168 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3169 vcpu->run->internal.suberror =
3170 KVM_INTERNAL_ERROR_EMULATION;
3171 vcpu->run->internal.ndata = 0;
3176 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
3177 map = &vmx->nested.virtual_apic_map;
3179 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->virtual_apic_page_addr), map)) {
3180 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, pfn_to_hpa(map->pfn));
3181 } else if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING) &&
3182 nested_cpu_has(vmcs12, CPU_BASED_CR8_STORE_EXITING) &&
3183 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
3185 * The processor will never use the TPR shadow, simply
3186 * clear the bit from the execution control. Such a
3187 * configuration is useless, but it happens in tests.
3188 * For any other configuration, failing the vm entry is
3189 * _not_ what the processor does but it's basically the
3190 * only possibility we have.
3192 exec_controls_clearbit(vmx, CPU_BASED_TPR_SHADOW);
3195 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR to
3196 * force VM-Entry to fail.
3198 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
3202 if (nested_cpu_has_posted_intr(vmcs12)) {
3203 map = &vmx->nested.pi_desc_map;
3205 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->posted_intr_desc_addr), map)) {
3206 vmx->nested.pi_desc =
3207 (struct pi_desc *)(((void *)map->hva) +
3208 offset_in_page(vmcs12->posted_intr_desc_addr));
3209 vmcs_write64(POSTED_INTR_DESC_ADDR,
3210 pfn_to_hpa(map->pfn) + offset_in_page(vmcs12->posted_intr_desc_addr));
3213 if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
3214 exec_controls_setbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
3216 exec_controls_clearbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
3220 static int nested_vmx_write_pml_buffer(struct kvm_vcpu *vcpu, gpa_t gpa)
3222 struct vmcs12 *vmcs12;
3223 struct vcpu_vmx *vmx = to_vmx(vcpu);
3226 if (WARN_ON_ONCE(!is_guest_mode(vcpu)))
3229 if (WARN_ON_ONCE(vmx->nested.pml_full))
3233 * Check if PML is enabled for the nested guest. Whether eptp bit 6 is
3234 * set is already checked as part of A/D emulation.
3236 vmcs12 = get_vmcs12(vcpu);
3237 if (!nested_cpu_has_pml(vmcs12))
3240 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
3241 vmx->nested.pml_full = true;
3246 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
3248 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
3249 offset_in_page(dst), sizeof(gpa)))
3252 vmcs12->guest_pml_index--;
3258 * Intel's VMX Instruction Reference specifies a common set of prerequisites
3259 * for running VMX instructions (except VMXON, whose prerequisites are
3260 * slightly different). It also specifies what exception to inject otherwise.
3261 * Note that many of these exceptions have priority over VM exits, so they
3262 * don't have to be checked again here.
3264 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
3266 if (!to_vmx(vcpu)->nested.vmxon) {
3267 kvm_queue_exception(vcpu, UD_VECTOR);
3271 if (vmx_get_cpl(vcpu)) {
3272 kvm_inject_gp(vcpu, 0);
3279 static u8 vmx_has_apicv_interrupt(struct kvm_vcpu *vcpu)
3281 u8 rvi = vmx_get_rvi();
3282 u8 vppr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_PROCPRI);
3284 return ((rvi & 0xf0) > (vppr & 0xf0));
3287 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
3288 struct vmcs12 *vmcs12);
3291 * If from_vmentry is false, this is being called from state restore (either RSM
3292 * or KVM_SET_NESTED_STATE). Otherwise it's called from vmlaunch/vmresume.
3295 * NVMX_VMENTRY_SUCCESS: Entered VMX non-root mode
3296 * NVMX_VMENTRY_VMFAIL: Consistency check VMFail
3297 * NVMX_VMENTRY_VMEXIT: Consistency check VMExit
3298 * NVMX_VMENTRY_KVM_INTERNAL_ERROR: KVM internal error
3300 enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
3303 struct vcpu_vmx *vmx = to_vmx(vcpu);
3304 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3305 enum vm_entry_failure_code entry_failure_code;
3306 bool evaluate_pending_interrupts;
3307 u32 exit_reason, failed_index;
3309 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3310 kvm_vcpu_flush_tlb_current(vcpu);
3312 evaluate_pending_interrupts = exec_controls_get(vmx) &
3313 (CPU_BASED_INTR_WINDOW_EXITING | CPU_BASED_NMI_WINDOW_EXITING);
3314 if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu))
3315 evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu);
3317 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
3318 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
3319 if (kvm_mpx_supported() &&
3320 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
3321 vmx->nested.vmcs01_guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
3324 * Overwrite vmcs01.GUEST_CR3 with L1's CR3 if EPT is disabled *and*
3325 * nested early checks are disabled. In the event of a "late" VM-Fail,
3326 * i.e. a VM-Fail detected by hardware but not KVM, KVM must unwind its
3327 * software model to the pre-VMEntry host state. When EPT is disabled,
3328 * GUEST_CR3 holds KVM's shadow CR3, not L1's "real" CR3, which causes
3329 * nested_vmx_restore_host_state() to corrupt vcpu->arch.cr3. Stuffing
3330 * vmcs01.GUEST_CR3 results in the unwind naturally setting arch.cr3 to
3331 * the correct value. Smashing vmcs01.GUEST_CR3 is safe because nested
3332 * VM-Exits, and the unwind, reset KVM's MMU, i.e. vmcs01.GUEST_CR3 is
3333 * guaranteed to be overwritten with a shadow CR3 prior to re-entering
3334 * L1. Don't stuff vmcs01.GUEST_CR3 when using nested early checks as
3335 * KVM modifies vcpu->arch.cr3 if and only if the early hardware checks
3336 * pass, and early VM-Fails do not reset KVM's MMU, i.e. the VM-Fail
3337 * path would need to manually save/restore vmcs01.GUEST_CR3.
3339 if (!enable_ept && !nested_early_check)
3340 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3342 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
3344 prepare_vmcs02_early(vmx, vmcs12);
3347 if (unlikely(!nested_get_vmcs12_pages(vcpu)))
3348 return NVMX_VMENTRY_KVM_INTERNAL_ERROR;
3350 if (nested_vmx_check_vmentry_hw(vcpu)) {
3351 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3352 return NVMX_VMENTRY_VMFAIL;
3355 if (nested_vmx_check_guest_state(vcpu, vmcs12,
3356 &entry_failure_code)) {
3357 exit_reason = EXIT_REASON_INVALID_STATE;
3358 vmcs12->exit_qualification = entry_failure_code;
3359 goto vmentry_fail_vmexit;
3363 enter_guest_mode(vcpu);
3364 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)
3365 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
3367 if (prepare_vmcs02(vcpu, vmcs12, &entry_failure_code)) {
3368 exit_reason = EXIT_REASON_INVALID_STATE;
3369 vmcs12->exit_qualification = entry_failure_code;
3370 goto vmentry_fail_vmexit_guest_mode;
3374 failed_index = nested_vmx_load_msr(vcpu,
3375 vmcs12->vm_entry_msr_load_addr,
3376 vmcs12->vm_entry_msr_load_count);
3378 exit_reason = EXIT_REASON_MSR_LOAD_FAIL;
3379 vmcs12->exit_qualification = failed_index;
3380 goto vmentry_fail_vmexit_guest_mode;
3384 * The MMU is not initialized to point at the right entities yet and
3385 * "get pages" would need to read data from the guest (i.e. we will
3386 * need to perform gpa to hpa translation). Request a call
3387 * to nested_get_vmcs12_pages before the next VM-entry. The MSRs
3388 * have already been set at vmentry time and should not be reset.
3390 kvm_make_request(KVM_REQ_GET_VMCS12_PAGES, vcpu);
3394 * If L1 had a pending IRQ/NMI until it executed
3395 * VMLAUNCH/VMRESUME which wasn't delivered because it was
3396 * disallowed (e.g. interrupts disabled), L0 needs to
3397 * evaluate if this pending event should cause an exit from L2
3398 * to L1 or delivered directly to L2 (e.g. In case L1 don't
3399 * intercept EXTERNAL_INTERRUPT).
3401 * Usually this would be handled by the processor noticing an
3402 * IRQ/NMI window request, or checking RVI during evaluation of
3403 * pending virtual interrupts. However, this setting was done
3404 * on VMCS01 and now VMCS02 is active instead. Thus, we force L0
3405 * to perform pending event evaluation by requesting a KVM_REQ_EVENT.
3407 if (unlikely(evaluate_pending_interrupts))
3408 kvm_make_request(KVM_REQ_EVENT, vcpu);
3411 * Do not start the preemption timer hrtimer until after we know
3412 * we are successful, so that only nested_vmx_vmexit needs to cancel
3415 vmx->nested.preemption_timer_expired = false;
3416 if (nested_cpu_has_preemption_timer(vmcs12)) {
3417 u64 timer_value = vmx_calc_preemption_timer_value(vcpu);
3418 vmx_start_preemption_timer(vcpu, timer_value);
3422 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
3423 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
3424 * returned as far as L1 is concerned. It will only return (and set
3425 * the success flag) when L2 exits (see nested_vmx_vmexit()).
3427 return NVMX_VMENTRY_SUCCESS;
3430 * A failed consistency check that leads to a VMExit during L1's
3431 * VMEnter to L2 is a variation of a normal VMexit, as explained in
3432 * 26.7 "VM-entry failures during or after loading guest state".
3434 vmentry_fail_vmexit_guest_mode:
3435 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)
3436 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
3437 leave_guest_mode(vcpu);
3439 vmentry_fail_vmexit:
3440 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3443 return NVMX_VMENTRY_VMEXIT;
3445 load_vmcs12_host_state(vcpu, vmcs12);
3446 vmcs12->vm_exit_reason = exit_reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
3447 if (enable_shadow_vmcs || vmx->nested.hv_evmcs)
3448 vmx->nested.need_vmcs12_to_shadow_sync = true;
3449 return NVMX_VMENTRY_VMEXIT;
3453 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
3454 * for running an L2 nested guest.
3456 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
3458 struct vmcs12 *vmcs12;
3459 enum nvmx_vmentry_status status;
3460 struct vcpu_vmx *vmx = to_vmx(vcpu);
3461 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
3462 enum nested_evmptrld_status evmptrld_status;
3464 if (!nested_vmx_check_permission(vcpu))
3467 evmptrld_status = nested_vmx_handle_enlightened_vmptrld(vcpu, launch);
3468 if (evmptrld_status == EVMPTRLD_ERROR) {
3469 kvm_queue_exception(vcpu, UD_VECTOR);
3471 } else if (evmptrld_status == EVMPTRLD_VMFAIL) {
3472 return nested_vmx_failInvalid(vcpu);
3475 if (!vmx->nested.hv_evmcs && vmx->nested.current_vmptr == -1ull)
3476 return nested_vmx_failInvalid(vcpu);
3478 vmcs12 = get_vmcs12(vcpu);
3481 * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact
3482 * that there *is* a valid VMCS pointer, RFLAGS.CF is set
3483 * rather than RFLAGS.ZF, and no error number is stored to the
3484 * VM-instruction error field.
3486 if (vmcs12->hdr.shadow_vmcs)
3487 return nested_vmx_failInvalid(vcpu);
3489 if (vmx->nested.hv_evmcs) {
3490 copy_enlightened_to_vmcs12(vmx);
3491 /* Enlightened VMCS doesn't have launch state */
3492 vmcs12->launch_state = !launch;
3493 } else if (enable_shadow_vmcs) {
3494 copy_shadow_to_vmcs12(vmx);
3498 * The nested entry process starts with enforcing various prerequisites
3499 * on vmcs12 as required by the Intel SDM, and act appropriately when
3500 * they fail: As the SDM explains, some conditions should cause the
3501 * instruction to fail, while others will cause the instruction to seem
3502 * to succeed, but return an EXIT_REASON_INVALID_STATE.
3503 * To speed up the normal (success) code path, we should avoid checking
3504 * for misconfigurations which will anyway be caught by the processor
3505 * when using the merged vmcs02.
3507 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS)
3508 return nested_vmx_fail(vcpu, VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
3510 if (vmcs12->launch_state == launch)
3511 return nested_vmx_fail(vcpu,
3512 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
3513 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
3515 if (nested_vmx_check_controls(vcpu, vmcs12))
3516 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3518 if (nested_vmx_check_host_state(vcpu, vmcs12))
3519 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
3522 * We're finally done with prerequisite checking, and can start with
3525 vmx->nested.nested_run_pending = 1;
3526 vmx->nested.has_preemption_timer_deadline = false;
3527 status = nested_vmx_enter_non_root_mode(vcpu, true);
3528 if (unlikely(status != NVMX_VMENTRY_SUCCESS))
3529 goto vmentry_failed;
3531 /* Hide L1D cache contents from the nested guest. */
3532 vmx->vcpu.arch.l1tf_flush_l1d = true;
3535 * Must happen outside of nested_vmx_enter_non_root_mode() as it will
3536 * also be used as part of restoring nVMX state for
3537 * snapshot restore (migration).
3539 * In this flow, it is assumed that vmcs12 cache was
3540 * trasferred as part of captured nVMX state and should
3541 * therefore not be read from guest memory (which may not
3542 * exist on destination host yet).
3544 nested_cache_shadow_vmcs12(vcpu, vmcs12);
3547 * If we're entering a halted L2 vcpu and the L2 vcpu won't be
3548 * awakened by event injection or by an NMI-window VM-exit or
3549 * by an interrupt-window VM-exit, halt the vcpu.
3551 if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
3552 !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) &&
3553 !(vmcs12->cpu_based_vm_exec_control & CPU_BASED_NMI_WINDOW_EXITING) &&
3554 !((vmcs12->cpu_based_vm_exec_control & CPU_BASED_INTR_WINDOW_EXITING) &&
3555 (vmcs12->guest_rflags & X86_EFLAGS_IF))) {
3556 vmx->nested.nested_run_pending = 0;
3557 return kvm_vcpu_halt(vcpu);
3562 vmx->nested.nested_run_pending = 0;
3563 if (status == NVMX_VMENTRY_KVM_INTERNAL_ERROR)
3565 if (status == NVMX_VMENTRY_VMEXIT)
3567 WARN_ON_ONCE(status != NVMX_VMENTRY_VMFAIL);
3568 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3572 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
3573 * because L2 may have changed some cr0 bits directly (CR0_GUEST_HOST_MASK).
3574 * This function returns the new value we should put in vmcs12.guest_cr0.
3575 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
3576 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
3577 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
3578 * didn't trap the bit, because if L1 did, so would L0).
3579 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
3580 * been modified by L2, and L1 knows it. So just leave the old value of
3581 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
3582 * isn't relevant, because if L0 traps this bit it can set it to anything.
3583 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
3584 * changed these bits, and therefore they need to be updated, but L0
3585 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
3586 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
3588 static inline unsigned long
3589 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
3592 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
3593 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
3594 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
3595 vcpu->arch.cr0_guest_owned_bits));
3598 static inline unsigned long
3599 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
3602 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
3603 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
3604 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
3605 vcpu->arch.cr4_guest_owned_bits));
3608 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
3609 struct vmcs12 *vmcs12)
3614 if (vcpu->arch.exception.injected) {
3615 nr = vcpu->arch.exception.nr;
3616 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
3618 if (kvm_exception_is_soft(nr)) {
3619 vmcs12->vm_exit_instruction_len =
3620 vcpu->arch.event_exit_inst_len;
3621 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
3623 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
3625 if (vcpu->arch.exception.has_error_code) {
3626 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
3627 vmcs12->idt_vectoring_error_code =
3628 vcpu->arch.exception.error_code;
3631 vmcs12->idt_vectoring_info_field = idt_vectoring;
3632 } else if (vcpu->arch.nmi_injected) {
3633 vmcs12->idt_vectoring_info_field =
3634 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
3635 } else if (vcpu->arch.interrupt.injected) {
3636 nr = vcpu->arch.interrupt.nr;
3637 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
3639 if (vcpu->arch.interrupt.soft) {
3640 idt_vectoring |= INTR_TYPE_SOFT_INTR;
3641 vmcs12->vm_entry_instruction_len =
3642 vcpu->arch.event_exit_inst_len;
3644 idt_vectoring |= INTR_TYPE_EXT_INTR;
3646 vmcs12->idt_vectoring_info_field = idt_vectoring;
3651 void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
3653 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3657 * Don't need to mark the APIC access page dirty; it is never
3658 * written to by the CPU during APIC virtualization.
3661 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
3662 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
3663 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3666 if (nested_cpu_has_posted_intr(vmcs12)) {
3667 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
3668 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3672 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
3674 struct vcpu_vmx *vmx = to_vmx(vcpu);
3679 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
3682 vmx->nested.pi_pending = false;
3683 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
3686 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
3687 if (max_irr != 256) {
3688 vapic_page = vmx->nested.virtual_apic_map.hva;
3692 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
3693 vapic_page, &max_irr);
3694 status = vmcs_read16(GUEST_INTR_STATUS);
3695 if ((u8)max_irr > ((u8)status & 0xff)) {
3697 status |= (u8)max_irr;
3698 vmcs_write16(GUEST_INTR_STATUS, status);
3702 nested_mark_vmcs12_pages_dirty(vcpu);
3705 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
3706 unsigned long exit_qual)
3708 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3709 unsigned int nr = vcpu->arch.exception.nr;
3710 u32 intr_info = nr | INTR_INFO_VALID_MASK;
3712 if (vcpu->arch.exception.has_error_code) {
3713 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
3714 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3717 if (kvm_exception_is_soft(nr))
3718 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3720 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3722 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
3723 vmx_get_nmi_mask(vcpu))
3724 intr_info |= INTR_INFO_UNBLOCK_NMI;
3726 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
3730 * Returns true if a debug trap is pending delivery.
3732 * In KVM, debug traps bear an exception payload. As such, the class of a #DB
3733 * exception may be inferred from the presence of an exception payload.
3735 static inline bool vmx_pending_dbg_trap(struct kvm_vcpu *vcpu)
3737 return vcpu->arch.exception.pending &&
3738 vcpu->arch.exception.nr == DB_VECTOR &&
3739 vcpu->arch.exception.payload;
3743 * Certain VM-exits set the 'pending debug exceptions' field to indicate a
3744 * recognized #DB (data or single-step) that has yet to be delivered. Since KVM
3745 * represents these debug traps with a payload that is said to be compatible
3746 * with the 'pending debug exceptions' field, write the payload to the VMCS
3747 * field if a VM-exit is delivered before the debug trap.
3749 static void nested_vmx_update_pending_dbg(struct kvm_vcpu *vcpu)
3751 if (vmx_pending_dbg_trap(vcpu))
3752 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
3753 vcpu->arch.exception.payload);
3756 static bool nested_vmx_preemption_timer_pending(struct kvm_vcpu *vcpu)
3758 return nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
3759 to_vmx(vcpu)->nested.preemption_timer_expired;
3762 static int vmx_check_nested_events(struct kvm_vcpu *vcpu)
3764 struct vcpu_vmx *vmx = to_vmx(vcpu);
3765 unsigned long exit_qual;
3766 bool block_nested_events =
3767 vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
3768 bool mtf_pending = vmx->nested.mtf_pending;
3769 struct kvm_lapic *apic = vcpu->arch.apic;
3772 * Clear the MTF state. If a higher priority VM-exit is delivered first,
3773 * this state is discarded.
3775 if (!block_nested_events)
3776 vmx->nested.mtf_pending = false;
3778 if (lapic_in_kernel(vcpu) &&
3779 test_bit(KVM_APIC_INIT, &apic->pending_events)) {
3780 if (block_nested_events)
3782 nested_vmx_update_pending_dbg(vcpu);
3783 clear_bit(KVM_APIC_INIT, &apic->pending_events);
3784 nested_vmx_vmexit(vcpu, EXIT_REASON_INIT_SIGNAL, 0, 0);
3789 * Process any exceptions that are not debug traps before MTF.
3791 if (vcpu->arch.exception.pending && !vmx_pending_dbg_trap(vcpu)) {
3792 if (block_nested_events)
3794 if (!nested_vmx_check_exception(vcpu, &exit_qual))
3796 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
3801 if (block_nested_events)
3803 nested_vmx_update_pending_dbg(vcpu);
3804 nested_vmx_vmexit(vcpu, EXIT_REASON_MONITOR_TRAP_FLAG, 0, 0);
3808 if (vcpu->arch.exception.pending) {
3809 if (block_nested_events)
3811 if (!nested_vmx_check_exception(vcpu, &exit_qual))
3813 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
3817 if (nested_vmx_preemption_timer_pending(vcpu)) {
3818 if (block_nested_events)
3820 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
3824 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
3825 if (block_nested_events)
3830 if (vcpu->arch.nmi_pending && !vmx_nmi_blocked(vcpu)) {
3831 if (block_nested_events)
3833 if (!nested_exit_on_nmi(vcpu))
3836 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
3837 NMI_VECTOR | INTR_TYPE_NMI_INTR |
3838 INTR_INFO_VALID_MASK, 0);
3840 * The NMI-triggered VM exit counts as injection:
3841 * clear this one and block further NMIs.
3843 vcpu->arch.nmi_pending = 0;
3844 vmx_set_nmi_mask(vcpu, true);
3848 if (kvm_cpu_has_interrupt(vcpu) && !vmx_interrupt_blocked(vcpu)) {
3849 if (block_nested_events)
3851 if (!nested_exit_on_intr(vcpu))
3853 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
3858 vmx_complete_nested_posted_interrupt(vcpu);
3862 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
3865 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
3868 if (ktime_to_ns(remaining) <= 0)
3871 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
3872 do_div(value, 1000000);
3873 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
3876 static bool is_vmcs12_ext_field(unsigned long field)
3879 case GUEST_ES_SELECTOR:
3880 case GUEST_CS_SELECTOR:
3881 case GUEST_SS_SELECTOR:
3882 case GUEST_DS_SELECTOR:
3883 case GUEST_FS_SELECTOR:
3884 case GUEST_GS_SELECTOR:
3885 case GUEST_LDTR_SELECTOR:
3886 case GUEST_TR_SELECTOR:
3887 case GUEST_ES_LIMIT:
3888 case GUEST_CS_LIMIT:
3889 case GUEST_SS_LIMIT:
3890 case GUEST_DS_LIMIT:
3891 case GUEST_FS_LIMIT:
3892 case GUEST_GS_LIMIT:
3893 case GUEST_LDTR_LIMIT:
3894 case GUEST_TR_LIMIT:
3895 case GUEST_GDTR_LIMIT:
3896 case GUEST_IDTR_LIMIT:
3897 case GUEST_ES_AR_BYTES:
3898 case GUEST_DS_AR_BYTES:
3899 case GUEST_FS_AR_BYTES:
3900 case GUEST_GS_AR_BYTES:
3901 case GUEST_LDTR_AR_BYTES:
3902 case GUEST_TR_AR_BYTES:
3909 case GUEST_LDTR_BASE:
3911 case GUEST_GDTR_BASE:
3912 case GUEST_IDTR_BASE:
3913 case GUEST_PENDING_DBG_EXCEPTIONS:
3923 static void sync_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu,
3924 struct vmcs12 *vmcs12)
3926 struct vcpu_vmx *vmx = to_vmx(vcpu);
3928 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
3929 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
3930 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
3931 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
3932 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
3933 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
3934 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
3935 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
3936 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
3937 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
3938 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
3939 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
3940 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
3941 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
3942 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
3943 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
3944 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
3945 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
3946 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
3947 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
3948 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
3949 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
3950 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
3951 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
3952 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
3953 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
3954 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
3955 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
3956 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
3957 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
3958 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
3959 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
3960 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
3961 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
3962 vmcs12->guest_pending_dbg_exceptions =
3963 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3964 if (kvm_mpx_supported())
3965 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
3967 vmx->nested.need_sync_vmcs02_to_vmcs12_rare = false;
3970 static void copy_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu,
3971 struct vmcs12 *vmcs12)
3973 struct vcpu_vmx *vmx = to_vmx(vcpu);
3976 if (!vmx->nested.need_sync_vmcs02_to_vmcs12_rare)
3980 WARN_ON_ONCE(vmx->loaded_vmcs != &vmx->vmcs01);
3983 vmx->loaded_vmcs = &vmx->nested.vmcs02;
3984 vmx_vcpu_load_vmcs(vcpu, cpu, &vmx->vmcs01);
3986 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
3988 vmx->loaded_vmcs = &vmx->vmcs01;
3989 vmx_vcpu_load_vmcs(vcpu, cpu, &vmx->nested.vmcs02);
3994 * Update the guest state fields of vmcs12 to reflect changes that
3995 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
3996 * VM-entry controls is also updated, since this is really a guest
3999 static void sync_vmcs02_to_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4001 struct vcpu_vmx *vmx = to_vmx(vcpu);
4003 if (vmx->nested.hv_evmcs)
4004 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
4006 vmx->nested.need_sync_vmcs02_to_vmcs12_rare = !vmx->nested.hv_evmcs;
4008 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
4009 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
4011 vmcs12->guest_rsp = kvm_rsp_read(vcpu);
4012 vmcs12->guest_rip = kvm_rip_read(vcpu);
4013 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
4015 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
4016 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
4018 vmcs12->guest_interruptibility_info =
4019 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
4021 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
4022 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
4024 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4026 if (nested_cpu_has_preemption_timer(vmcs12) &&
4027 vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER &&
4028 !vmx->nested.nested_run_pending)
4029 vmcs12->vmx_preemption_timer_value =
4030 vmx_get_preemption_timer_value(vcpu);
4033 * In some cases (usually, nested EPT), L2 is allowed to change its
4034 * own CR3 without exiting. If it has changed it, we must keep it.
4035 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
4036 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
4038 * Additionally, restore L2's PDPTR to vmcs12.
4041 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
4042 if (nested_cpu_has_ept(vmcs12) && is_pae_paging(vcpu)) {
4043 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
4044 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
4045 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
4046 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
4050 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
4052 if (nested_cpu_has_vid(vmcs12))
4053 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
4055 vmcs12->vm_entry_controls =
4056 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
4057 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
4059 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS)
4060 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
4062 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
4063 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4067 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
4068 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
4069 * and this function updates it to reflect the changes to the guest state while
4070 * L2 was running (and perhaps made some exits which were handled directly by L0
4071 * without going back to L1), and to reflect the exit reason.
4072 * Note that we do not have to copy here all VMCS fields, just those that
4073 * could have changed by the L2 guest or the exit - i.e., the guest-state and
4074 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
4075 * which already writes to vmcs12 directly.
4077 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
4078 u32 vm_exit_reason, u32 exit_intr_info,
4079 unsigned long exit_qualification)
4081 /* update exit information fields: */
4082 vmcs12->vm_exit_reason = vm_exit_reason;
4083 vmcs12->exit_qualification = exit_qualification;
4084 vmcs12->vm_exit_intr_info = exit_intr_info;
4086 vmcs12->idt_vectoring_info_field = 0;
4087 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4088 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
4090 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
4091 vmcs12->launch_state = 1;
4093 /* vm_entry_intr_info_field is cleared on exit. Emulate this
4094 * instead of reading the real value. */
4095 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
4098 * Transfer the event that L0 or L1 may wanted to inject into
4099 * L2 to IDT_VECTORING_INFO_FIELD.
4101 vmcs12_save_pending_event(vcpu, vmcs12);
4104 * According to spec, there's no need to store the guest's
4105 * MSRs if the exit is due to a VM-entry failure that occurs
4106 * during or after loading the guest state. Since this exit
4107 * does not fall in that category, we need to save the MSRs.
4109 if (nested_vmx_store_msr(vcpu,
4110 vmcs12->vm_exit_msr_store_addr,
4111 vmcs12->vm_exit_msr_store_count))
4112 nested_vmx_abort(vcpu,
4113 VMX_ABORT_SAVE_GUEST_MSR_FAIL);
4117 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
4118 * preserved above and would only end up incorrectly in L1.
4120 vcpu->arch.nmi_injected = false;
4121 kvm_clear_exception_queue(vcpu);
4122 kvm_clear_interrupt_queue(vcpu);
4126 * A part of what we need to when the nested L2 guest exits and we want to
4127 * run its L1 parent, is to reset L1's guest state to the host state specified
4129 * This function is to be called not only on normal nested exit, but also on
4130 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
4131 * Failures During or After Loading Guest State").
4132 * This function should be called when the active VMCS is L1's (vmcs01).
4134 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
4135 struct vmcs12 *vmcs12)
4137 enum vm_entry_failure_code ignored;
4138 struct kvm_segment seg;
4140 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
4141 vcpu->arch.efer = vmcs12->host_ia32_efer;
4142 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4143 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
4145 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
4146 vmx_set_efer(vcpu, vcpu->arch.efer);
4148 kvm_rsp_write(vcpu, vmcs12->host_rsp);
4149 kvm_rip_write(vcpu, vmcs12->host_rip);
4150 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4151 vmx_set_interrupt_shadow(vcpu, 0);
4154 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
4155 * actually changed, because vmx_set_cr0 refers to efer set above.
4157 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
4158 * (KVM doesn't change it);
4160 vcpu->arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4161 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4163 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
4164 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
4165 vmx_set_cr4(vcpu, vmcs12->host_cr4);
4167 nested_ept_uninit_mmu_context(vcpu);
4170 * Only PDPTE load can fail as the value of cr3 was checked on entry and
4171 * couldn't have changed.
4173 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &ignored))
4174 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
4177 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
4179 nested_vmx_transition_tlb_flush(vcpu, vmcs12, false);
4181 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
4182 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
4183 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
4184 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
4185 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4186 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
4187 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
4189 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
4190 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
4191 vmcs_write64(GUEST_BNDCFGS, 0);
4193 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4194 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
4195 vcpu->arch.pat = vmcs12->host_ia32_pat;
4197 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
4198 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
4199 vmcs12->host_ia32_perf_global_ctrl));
4201 /* Set L1 segment info according to Intel SDM
4202 27.5.2 Loading Host Segment and Descriptor-Table Registers */
4203 seg = (struct kvm_segment) {
4205 .limit = 0xFFFFFFFF,
4206 .selector = vmcs12->host_cs_selector,
4212 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4216 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
4217 seg = (struct kvm_segment) {
4219 .limit = 0xFFFFFFFF,
4226 seg.selector = vmcs12->host_ds_selector;
4227 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
4228 seg.selector = vmcs12->host_es_selector;
4229 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
4230 seg.selector = vmcs12->host_ss_selector;
4231 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
4232 seg.selector = vmcs12->host_fs_selector;
4233 seg.base = vmcs12->host_fs_base;
4234 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
4235 seg.selector = vmcs12->host_gs_selector;
4236 seg.base = vmcs12->host_gs_base;
4237 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
4238 seg = (struct kvm_segment) {
4239 .base = vmcs12->host_tr_base,
4241 .selector = vmcs12->host_tr_selector,
4245 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
4247 kvm_set_dr(vcpu, 7, 0x400);
4248 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4250 if (cpu_has_vmx_msr_bitmap())
4251 vmx_update_msr_bitmap(vcpu);
4253 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
4254 vmcs12->vm_exit_msr_load_count))
4255 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4258 static inline u64 nested_vmx_get_vmcs01_guest_efer(struct vcpu_vmx *vmx)
4260 struct shared_msr_entry *efer_msr;
4263 if (vm_entry_controls_get(vmx) & VM_ENTRY_LOAD_IA32_EFER)
4264 return vmcs_read64(GUEST_IA32_EFER);
4266 if (cpu_has_load_ia32_efer())
4269 for (i = 0; i < vmx->msr_autoload.guest.nr; ++i) {
4270 if (vmx->msr_autoload.guest.val[i].index == MSR_EFER)
4271 return vmx->msr_autoload.guest.val[i].value;
4274 efer_msr = find_msr_entry(vmx, MSR_EFER);
4276 return efer_msr->data;
4281 static void nested_vmx_restore_host_state(struct kvm_vcpu *vcpu)
4283 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4284 struct vcpu_vmx *vmx = to_vmx(vcpu);
4285 struct vmx_msr_entry g, h;
4289 vcpu->arch.pat = vmcs_read64(GUEST_IA32_PAT);
4291 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
4293 * L1's host DR7 is lost if KVM_GUESTDBG_USE_HW_BP is set
4294 * as vmcs01.GUEST_DR7 contains a userspace defined value
4295 * and vcpu->arch.dr7 is not squirreled away before the
4296 * nested VMENTER (not worth adding a variable in nested_vmx).
4298 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
4299 kvm_set_dr(vcpu, 7, DR7_FIXED_1);
4301 WARN_ON(kvm_set_dr(vcpu, 7, vmcs_readl(GUEST_DR7)));
4305 * Note that calling vmx_set_{efer,cr0,cr4} is important as they
4306 * handle a variety of side effects to KVM's software model.
4308 vmx_set_efer(vcpu, nested_vmx_get_vmcs01_guest_efer(vmx));
4310 vcpu->arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4311 vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW));
4313 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
4314 vmx_set_cr4(vcpu, vmcs_readl(CR4_READ_SHADOW));
4316 nested_ept_uninit_mmu_context(vcpu);
4317 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4318 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
4321 * Use ept_save_pdptrs(vcpu) to load the MMU's cached PDPTRs
4322 * from vmcs01 (if necessary). The PDPTRs are not loaded on
4323 * VMFail, like everything else we just need to ensure our
4324 * software model is up-to-date.
4326 if (enable_ept && is_pae_paging(vcpu))
4327 ept_save_pdptrs(vcpu);
4329 kvm_mmu_reset_context(vcpu);
4331 if (cpu_has_vmx_msr_bitmap())
4332 vmx_update_msr_bitmap(vcpu);
4335 * This nasty bit of open coding is a compromise between blindly
4336 * loading L1's MSRs using the exit load lists (incorrect emulation
4337 * of VMFail), leaving the nested VM's MSRs in the software model
4338 * (incorrect behavior) and snapshotting the modified MSRs (too
4339 * expensive since the lists are unbound by hardware). For each
4340 * MSR that was (prematurely) loaded from the nested VMEntry load
4341 * list, reload it from the exit load list if it exists and differs
4342 * from the guest value. The intent is to stuff host state as
4343 * silently as possible, not to fully process the exit load list.
4345 for (i = 0; i < vmcs12->vm_entry_msr_load_count; i++) {
4346 gpa = vmcs12->vm_entry_msr_load_addr + (i * sizeof(g));
4347 if (kvm_vcpu_read_guest(vcpu, gpa, &g, sizeof(g))) {
4348 pr_debug_ratelimited(
4349 "%s read MSR index failed (%u, 0x%08llx)\n",
4354 for (j = 0; j < vmcs12->vm_exit_msr_load_count; j++) {
4355 gpa = vmcs12->vm_exit_msr_load_addr + (j * sizeof(h));
4356 if (kvm_vcpu_read_guest(vcpu, gpa, &h, sizeof(h))) {
4357 pr_debug_ratelimited(
4358 "%s read MSR failed (%u, 0x%08llx)\n",
4362 if (h.index != g.index)
4364 if (h.value == g.value)
4367 if (nested_vmx_load_msr_check(vcpu, &h)) {
4368 pr_debug_ratelimited(
4369 "%s check failed (%u, 0x%x, 0x%x)\n",
4370 __func__, j, h.index, h.reserved);
4374 if (kvm_set_msr(vcpu, h.index, h.value)) {
4375 pr_debug_ratelimited(
4376 "%s WRMSR failed (%u, 0x%x, 0x%llx)\n",
4377 __func__, j, h.index, h.value);
4386 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4390 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
4391 * and modify vmcs12 to make it see what it would expect to see there if
4392 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
4394 void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason,
4395 u32 exit_intr_info, unsigned long exit_qualification)
4397 struct vcpu_vmx *vmx = to_vmx(vcpu);
4398 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4400 /* trying to cancel vmlaunch/vmresume is a bug */
4401 WARN_ON_ONCE(vmx->nested.nested_run_pending);
4403 /* Service the TLB flush request for L2 before switching to L1. */
4404 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
4405 kvm_vcpu_flush_tlb_current(vcpu);
4408 * VCPU_EXREG_PDPTR will be clobbered in arch/x86/kvm/vmx/vmx.h between
4409 * now and the new vmentry. Ensure that the VMCS02 PDPTR fields are
4410 * up-to-date before switching to L1.
4412 if (enable_ept && is_pae_paging(vcpu))
4413 vmx_ept_load_pdptrs(vcpu);
4415 leave_guest_mode(vcpu);
4417 if (nested_cpu_has_preemption_timer(vmcs12))
4418 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
4420 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)
4421 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
4423 if (likely(!vmx->fail)) {
4424 sync_vmcs02_to_vmcs12(vcpu, vmcs12);
4426 if (vm_exit_reason != -1)
4427 prepare_vmcs12(vcpu, vmcs12, vm_exit_reason,
4428 exit_intr_info, exit_qualification);
4431 * Must happen outside of sync_vmcs02_to_vmcs12() as it will
4432 * also be used to capture vmcs12 cache as part of
4433 * capturing nVMX state for snapshot (migration).
4435 * Otherwise, this flush will dirty guest memory at a
4436 * point it is already assumed by user-space to be
4439 nested_flush_cached_shadow_vmcs12(vcpu, vmcs12);
4442 * The only expected VM-instruction error is "VM entry with
4443 * invalid control field(s)." Anything else indicates a
4444 * problem with L0. And we should never get here with a
4445 * VMFail of any type if early consistency checks are enabled.
4447 WARN_ON_ONCE(vmcs_read32(VM_INSTRUCTION_ERROR) !=
4448 VMXERR_ENTRY_INVALID_CONTROL_FIELD);
4449 WARN_ON_ONCE(nested_early_check);
4452 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
4454 /* Update any VMCS fields that might have changed while L2 ran */
4455 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
4456 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
4457 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
4458 if (vmx->nested.l1_tpr_threshold != -1)
4459 vmcs_write32(TPR_THRESHOLD, vmx->nested.l1_tpr_threshold);
4461 if (kvm_has_tsc_control)
4462 decache_tsc_multiplier(vmx);
4464 if (vmx->nested.change_vmcs01_virtual_apic_mode) {
4465 vmx->nested.change_vmcs01_virtual_apic_mode = false;
4466 vmx_set_virtual_apic_mode(vcpu);
4469 /* Unpin physical memory we referred to in vmcs02 */
4470 if (vmx->nested.apic_access_page) {
4471 kvm_release_page_clean(vmx->nested.apic_access_page);
4472 vmx->nested.apic_access_page = NULL;
4474 kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true);
4475 kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true);
4476 vmx->nested.pi_desc = NULL;
4478 if (vmx->nested.reload_vmcs01_apic_access_page) {
4479 vmx->nested.reload_vmcs01_apic_access_page = false;
4480 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4483 if ((vm_exit_reason != -1) &&
4484 (enable_shadow_vmcs || vmx->nested.hv_evmcs))
4485 vmx->nested.need_vmcs12_to_shadow_sync = true;
4487 /* in case we halted in L2 */
4488 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4490 if (likely(!vmx->fail)) {
4491 if ((u16)vm_exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
4492 nested_exit_intr_ack_set(vcpu)) {
4493 int irq = kvm_cpu_get_interrupt(vcpu);
4495 vmcs12->vm_exit_intr_info = irq |
4496 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
4499 if (vm_exit_reason != -1)
4500 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
4501 vmcs12->exit_qualification,
4502 vmcs12->idt_vectoring_info_field,
4503 vmcs12->vm_exit_intr_info,
4504 vmcs12->vm_exit_intr_error_code,
4507 load_vmcs12_host_state(vcpu, vmcs12);
4513 * After an early L2 VM-entry failure, we're now back
4514 * in L1 which thinks it just finished a VMLAUNCH or
4515 * VMRESUME instruction, so we need to set the failure
4516 * flag and the VM-instruction error field of the VMCS
4517 * accordingly, and skip the emulated instruction.
4519 (void)nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
4522 * Restore L1's host state to KVM's software model. We're here
4523 * because a consistency check was caught by hardware, which
4524 * means some amount of guest state has been propagated to KVM's
4525 * model and needs to be unwound to the host's state.
4527 nested_vmx_restore_host_state(vcpu);
4533 * Decode the memory-address operand of a vmx instruction, as recorded on an
4534 * exit caused by such an instruction (run by a guest hypervisor).
4535 * On success, returns 0. When the operand is invalid, returns 1 and throws
4538 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification,
4539 u32 vmx_instruction_info, bool wr, int len, gva_t *ret)
4543 struct kvm_segment s;
4546 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4547 * Execution", on an exit, vmx_instruction_info holds most of the
4548 * addressing components of the operand. Only the displacement part
4549 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4550 * For how an actual address is calculated from all these components,
4551 * refer to Vol. 1, "Operand Addressing".
4553 int scaling = vmx_instruction_info & 3;
4554 int addr_size = (vmx_instruction_info >> 7) & 7;
4555 bool is_reg = vmx_instruction_info & (1u << 10);
4556 int seg_reg = (vmx_instruction_info >> 15) & 7;
4557 int index_reg = (vmx_instruction_info >> 18) & 0xf;
4558 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4559 int base_reg = (vmx_instruction_info >> 23) & 0xf;
4560 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
4563 kvm_queue_exception(vcpu, UD_VECTOR);
4567 /* Addr = segment_base + offset */
4568 /* offset = base + [index * scale] + displacement */
4569 off = exit_qualification; /* holds the displacement */
4571 off = (gva_t)sign_extend64(off, 31);
4572 else if (addr_size == 0)
4573 off = (gva_t)sign_extend64(off, 15);
4575 off += kvm_register_read(vcpu, base_reg);
4577 off += kvm_register_read(vcpu, index_reg) << scaling;
4578 vmx_get_segment(vcpu, &s, seg_reg);
4581 * The effective address, i.e. @off, of a memory operand is truncated
4582 * based on the address size of the instruction. Note that this is
4583 * the *effective address*, i.e. the address prior to accounting for
4584 * the segment's base.
4586 if (addr_size == 1) /* 32 bit */
4588 else if (addr_size == 0) /* 16 bit */
4591 /* Checks for #GP/#SS exceptions. */
4593 if (is_long_mode(vcpu)) {
4595 * The virtual/linear address is never truncated in 64-bit
4596 * mode, e.g. a 32-bit address size can yield a 64-bit virtual
4597 * address when using FS/GS with a non-zero base.
4599 if (seg_reg == VCPU_SREG_FS || seg_reg == VCPU_SREG_GS)
4600 *ret = s.base + off;
4604 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
4605 * non-canonical form. This is the only check on the memory
4606 * destination for long mode!
4608 exn = is_noncanonical_address(*ret, vcpu);
4611 * When not in long mode, the virtual/linear address is
4612 * unconditionally truncated to 32 bits regardless of the
4615 *ret = (s.base + off) & 0xffffffff;
4617 /* Protected mode: apply checks for segment validity in the
4619 * - segment type check (#GP(0) may be thrown)
4620 * - usability check (#GP(0)/#SS(0))
4621 * - limit check (#GP(0)/#SS(0))
4624 /* #GP(0) if the destination operand is located in a
4625 * read-only data segment or any code segment.
4627 exn = ((s.type & 0xa) == 0 || (s.type & 8));
4629 /* #GP(0) if the source operand is located in an
4630 * execute-only code segment
4632 exn = ((s.type & 0xa) == 8);
4634 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4637 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
4639 exn = (s.unusable != 0);
4642 * Protected mode: #GP(0)/#SS(0) if the memory operand is
4643 * outside the segment limit. All CPUs that support VMX ignore
4644 * limit checks for flat segments, i.e. segments with base==0,
4645 * limit==0xffffffff and of type expand-up data or code.
4647 if (!(s.base == 0 && s.limit == 0xffffffff &&
4648 ((s.type & 8) || !(s.type & 4))))
4649 exn = exn || ((u64)off + len - 1 > s.limit);
4652 kvm_queue_exception_e(vcpu,
4653 seg_reg == VCPU_SREG_SS ?
4654 SS_VECTOR : GP_VECTOR,
4662 void nested_vmx_pmu_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
4664 struct vcpu_vmx *vmx;
4666 if (!nested_vmx_allowed(vcpu))
4670 if (kvm_x86_ops.pmu_ops->is_valid_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL)) {
4671 vmx->nested.msrs.entry_ctls_high |=
4672 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
4673 vmx->nested.msrs.exit_ctls_high |=
4674 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
4676 vmx->nested.msrs.entry_ctls_high &=
4677 ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
4678 vmx->nested.msrs.exit_ctls_high &=
4679 ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
4683 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer,
4687 struct x86_exception e;
4690 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
4691 vmcs_read32(VMX_INSTRUCTION_INFO), false,
4692 sizeof(*vmpointer), &gva)) {
4697 r = kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e);
4698 if (r != X86EMUL_CONTINUE) {
4699 *ret = kvm_handle_memory_failure(vcpu, r, &e);
4707 * Allocate a shadow VMCS and associate it with the currently loaded
4708 * VMCS, unless such a shadow VMCS already exists. The newly allocated
4709 * VMCS is also VMCLEARed, so that it is ready for use.
4711 static struct vmcs *alloc_shadow_vmcs(struct kvm_vcpu *vcpu)
4713 struct vcpu_vmx *vmx = to_vmx(vcpu);
4714 struct loaded_vmcs *loaded_vmcs = vmx->loaded_vmcs;
4717 * We should allocate a shadow vmcs for vmcs01 only when L1
4718 * executes VMXON and free it when L1 executes VMXOFF.
4719 * As it is invalid to execute VMXON twice, we shouldn't reach
4720 * here when vmcs01 already have an allocated shadow vmcs.
4722 WARN_ON(loaded_vmcs == &vmx->vmcs01 && loaded_vmcs->shadow_vmcs);
4724 if (!loaded_vmcs->shadow_vmcs) {
4725 loaded_vmcs->shadow_vmcs = alloc_vmcs(true);
4726 if (loaded_vmcs->shadow_vmcs)
4727 vmcs_clear(loaded_vmcs->shadow_vmcs);
4729 return loaded_vmcs->shadow_vmcs;
4732 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
4734 struct vcpu_vmx *vmx = to_vmx(vcpu);
4737 r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
4741 vmx->nested.cached_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT);
4742 if (!vmx->nested.cached_vmcs12)
4743 goto out_cached_vmcs12;
4745 vmx->nested.cached_shadow_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT);
4746 if (!vmx->nested.cached_shadow_vmcs12)
4747 goto out_cached_shadow_vmcs12;
4749 if (enable_shadow_vmcs && !alloc_shadow_vmcs(vcpu))
4750 goto out_shadow_vmcs;
4752 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
4753 HRTIMER_MODE_ABS_PINNED);
4754 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
4756 vmx->nested.vpid02 = allocate_vpid();
4758 vmx->nested.vmcs02_initialized = false;
4759 vmx->nested.vmxon = true;
4761 if (vmx_pt_mode_is_host_guest()) {
4762 vmx->pt_desc.guest.ctl = 0;
4763 pt_update_intercept_for_msr(vmx);
4769 kfree(vmx->nested.cached_shadow_vmcs12);
4771 out_cached_shadow_vmcs12:
4772 kfree(vmx->nested.cached_vmcs12);
4775 free_loaded_vmcs(&vmx->nested.vmcs02);
4782 * Emulate the VMXON instruction.
4783 * Currently, we just remember that VMX is active, and do not save or even
4784 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4785 * do not currently need to store anything in that guest-allocated memory
4786 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4787 * argument is different from the VMXON pointer (which the spec says they do).
4789 static int handle_vmon(struct kvm_vcpu *vcpu)
4794 struct vcpu_vmx *vmx = to_vmx(vcpu);
4795 const u64 VMXON_NEEDED_FEATURES = FEAT_CTL_LOCKED
4796 | FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
4799 * The Intel VMX Instruction Reference lists a bunch of bits that are
4800 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
4801 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
4802 * Otherwise, we should fail with #UD. But most faulting conditions
4803 * have already been checked by hardware, prior to the VM-exit for
4804 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
4805 * that bit set to 1 in non-root mode.
4807 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
4808 kvm_queue_exception(vcpu, UD_VECTOR);
4812 /* CPL=0 must be checked manually. */
4813 if (vmx_get_cpl(vcpu)) {
4814 kvm_inject_gp(vcpu, 0);
4818 if (vmx->nested.vmxon)
4819 return nested_vmx_fail(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
4821 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
4822 != VMXON_NEEDED_FEATURES) {
4823 kvm_inject_gp(vcpu, 0);
4827 if (nested_vmx_get_vmptr(vcpu, &vmptr, &ret))
4832 * The first 4 bytes of VMXON region contain the supported
4833 * VMCS revision identifier
4835 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
4836 * which replaces physical address width with 32
4838 if (!page_address_valid(vcpu, vmptr))
4839 return nested_vmx_failInvalid(vcpu);
4841 if (kvm_read_guest(vcpu->kvm, vmptr, &revision, sizeof(revision)) ||
4842 revision != VMCS12_REVISION)
4843 return nested_vmx_failInvalid(vcpu);
4845 vmx->nested.vmxon_ptr = vmptr;
4846 ret = enter_vmx_operation(vcpu);
4850 return nested_vmx_succeed(vcpu);
4853 static inline void nested_release_vmcs12(struct kvm_vcpu *vcpu)
4855 struct vcpu_vmx *vmx = to_vmx(vcpu);
4857 if (vmx->nested.current_vmptr == -1ull)
4860 copy_vmcs02_to_vmcs12_rare(vcpu, get_vmcs12(vcpu));
4862 if (enable_shadow_vmcs) {
4863 /* copy to memory all shadowed fields in case
4864 they were modified */
4865 copy_shadow_to_vmcs12(vmx);
4866 vmx_disable_shadow_vmcs(vmx);
4868 vmx->nested.posted_intr_nv = -1;
4870 /* Flush VMCS12 to guest memory */
4871 kvm_vcpu_write_guest_page(vcpu,
4872 vmx->nested.current_vmptr >> PAGE_SHIFT,
4873 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
4875 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4877 vmx->nested.current_vmptr = -1ull;
4880 /* Emulate the VMXOFF instruction */
4881 static int handle_vmoff(struct kvm_vcpu *vcpu)
4883 if (!nested_vmx_check_permission(vcpu))
4888 /* Process a latched INIT during time CPU was in VMX operation */
4889 kvm_make_request(KVM_REQ_EVENT, vcpu);
4891 return nested_vmx_succeed(vcpu);
4894 /* Emulate the VMCLEAR instruction */
4895 static int handle_vmclear(struct kvm_vcpu *vcpu)
4897 struct vcpu_vmx *vmx = to_vmx(vcpu);
4903 if (!nested_vmx_check_permission(vcpu))
4906 if (nested_vmx_get_vmptr(vcpu, &vmptr, &r))
4909 if (!page_address_valid(vcpu, vmptr))
4910 return nested_vmx_fail(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
4912 if (vmptr == vmx->nested.vmxon_ptr)
4913 return nested_vmx_fail(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
4916 * When Enlightened VMEntry is enabled on the calling CPU we treat
4917 * memory area pointer by vmptr as Enlightened VMCS (as there's no good
4918 * way to distinguish it from VMCS12) and we must not corrupt it by
4919 * writing to the non-existent 'launch_state' field. The area doesn't
4920 * have to be the currently active EVMCS on the calling CPU and there's
4921 * nothing KVM has to do to transition it from 'active' to 'non-active'
4922 * state. It is possible that the area will stay mapped as
4923 * vmx->nested.hv_evmcs but this shouldn't be a problem.
4925 if (likely(!vmx->nested.enlightened_vmcs_enabled ||
4926 !nested_enlightened_vmentry(vcpu, &evmcs_gpa))) {
4927 if (vmptr == vmx->nested.current_vmptr)
4928 nested_release_vmcs12(vcpu);
4930 kvm_vcpu_write_guest(vcpu,
4931 vmptr + offsetof(struct vmcs12,
4933 &zero, sizeof(zero));
4936 return nested_vmx_succeed(vcpu);
4939 /* Emulate the VMLAUNCH instruction */
4940 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
4942 return nested_vmx_run(vcpu, true);
4945 /* Emulate the VMRESUME instruction */
4946 static int handle_vmresume(struct kvm_vcpu *vcpu)
4949 return nested_vmx_run(vcpu, false);
4952 static int handle_vmread(struct kvm_vcpu *vcpu)
4954 struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu)
4956 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
4957 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
4958 struct vcpu_vmx *vmx = to_vmx(vcpu);
4959 struct x86_exception e;
4960 unsigned long field;
4966 if (!nested_vmx_check_permission(vcpu))
4970 * In VMX non-root operation, when the VMCS-link pointer is -1ull,
4971 * any VMREAD sets the ALU flags for VMfailInvalid.
4973 if (vmx->nested.current_vmptr == -1ull ||
4974 (is_guest_mode(vcpu) &&
4975 get_vmcs12(vcpu)->vmcs_link_pointer == -1ull))
4976 return nested_vmx_failInvalid(vcpu);
4978 /* Decode instruction info and find the field to read */
4979 field = kvm_register_readl(vcpu, (((instr_info) >> 28) & 0xf));
4981 offset = vmcs_field_to_offset(field);
4983 return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
4985 if (!is_guest_mode(vcpu) && is_vmcs12_ext_field(field))
4986 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
4988 /* Read the field, zero-extended to a u64 value */
4989 value = vmcs12_read_any(vmcs12, field, offset);
4992 * Now copy part of this value to register or memory, as requested.
4993 * Note that the number of bits actually copied is 32 or 64 depending
4994 * on the guest's mode (32 or 64 bit), not on the given field's length.
4996 if (instr_info & BIT(10)) {
4997 kvm_register_writel(vcpu, (((instr_info) >> 3) & 0xf), value);
4999 len = is_64_bit_mode(vcpu) ? 8 : 4;
5000 if (get_vmx_mem_address(vcpu, exit_qualification,
5001 instr_info, true, len, &gva))
5003 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
5004 r = kvm_write_guest_virt_system(vcpu, gva, &value, len, &e);
5005 if (r != X86EMUL_CONTINUE)
5006 return kvm_handle_memory_failure(vcpu, r, &e);
5009 return nested_vmx_succeed(vcpu);
5012 static bool is_shadow_field_rw(unsigned long field)
5015 #define SHADOW_FIELD_RW(x, y) case x:
5016 #include "vmcs_shadow_fields.h"
5024 static bool is_shadow_field_ro(unsigned long field)
5027 #define SHADOW_FIELD_RO(x, y) case x:
5028 #include "vmcs_shadow_fields.h"
5036 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5038 struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu)
5040 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5041 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5042 struct vcpu_vmx *vmx = to_vmx(vcpu);
5043 struct x86_exception e;
5044 unsigned long field;
5050 * The value to write might be 32 or 64 bits, depending on L1's long
5051 * mode, and eventually we need to write that into a field of several
5052 * possible lengths. The code below first zero-extends the value to 64
5053 * bit (value), and then copies only the appropriate number of
5054 * bits into the vmcs12 field.
5058 if (!nested_vmx_check_permission(vcpu))
5062 * In VMX non-root operation, when the VMCS-link pointer is -1ull,
5063 * any VMWRITE sets the ALU flags for VMfailInvalid.
5065 if (vmx->nested.current_vmptr == -1ull ||
5066 (is_guest_mode(vcpu) &&
5067 get_vmcs12(vcpu)->vmcs_link_pointer == -1ull))
5068 return nested_vmx_failInvalid(vcpu);
5070 if (instr_info & BIT(10))
5071 value = kvm_register_readl(vcpu, (((instr_info) >> 3) & 0xf));
5073 len = is_64_bit_mode(vcpu) ? 8 : 4;
5074 if (get_vmx_mem_address(vcpu, exit_qualification,
5075 instr_info, false, len, &gva))
5077 r = kvm_read_guest_virt(vcpu, gva, &value, len, &e);
5078 if (r != X86EMUL_CONTINUE)
5079 return kvm_handle_memory_failure(vcpu, r, &e);
5082 field = kvm_register_readl(vcpu, (((instr_info) >> 28) & 0xf));
5084 offset = vmcs_field_to_offset(field);
5086 return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5089 * If the vCPU supports "VMWRITE to any supported field in the
5090 * VMCS," then the "read-only" fields are actually read/write.
5092 if (vmcs_field_readonly(field) &&
5093 !nested_cpu_has_vmwrite_any_field(vcpu))
5094 return nested_vmx_fail(vcpu, VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5097 * Ensure vmcs12 is up-to-date before any VMWRITE that dirties
5098 * vmcs12, else we may crush a field or consume a stale value.
5100 if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field))
5101 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
5104 * Some Intel CPUs intentionally drop the reserved bits of the AR byte
5105 * fields on VMWRITE. Emulate this behavior to ensure consistent KVM
5106 * behavior regardless of the underlying hardware, e.g. if an AR_BYTE
5107 * field is intercepted for VMWRITE but not VMREAD (in L1), then VMREAD
5108 * from L1 will return a different value than VMREAD from L2 (L1 sees
5109 * the stripped down value, L2 sees the full value as stored by KVM).
5111 if (field >= GUEST_ES_AR_BYTES && field <= GUEST_TR_AR_BYTES)
5114 vmcs12_write_any(vmcs12, field, offset, value);
5117 * Do not track vmcs12 dirty-state if in guest-mode as we actually
5118 * dirty shadow vmcs12 instead of vmcs12. Fields that can be updated
5119 * by L1 without a vmexit are always updated in the vmcs02, i.e. don't
5120 * "dirty" vmcs12, all others go down the prepare_vmcs02() slow path.
5122 if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field)) {
5124 * L1 can read these fields without exiting, ensure the
5125 * shadow VMCS is up-to-date.
5127 if (enable_shadow_vmcs && is_shadow_field_ro(field)) {
5129 vmcs_load(vmx->vmcs01.shadow_vmcs);
5131 __vmcs_writel(field, value);
5133 vmcs_clear(vmx->vmcs01.shadow_vmcs);
5134 vmcs_load(vmx->loaded_vmcs->vmcs);
5137 vmx->nested.dirty_vmcs12 = true;
5140 return nested_vmx_succeed(vcpu);
5143 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
5145 vmx->nested.current_vmptr = vmptr;
5146 if (enable_shadow_vmcs) {
5147 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
5148 vmcs_write64(VMCS_LINK_POINTER,
5149 __pa(vmx->vmcs01.shadow_vmcs));
5150 vmx->nested.need_vmcs12_to_shadow_sync = true;
5152 vmx->nested.dirty_vmcs12 = true;
5155 /* Emulate the VMPTRLD instruction */
5156 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5158 struct vcpu_vmx *vmx = to_vmx(vcpu);
5162 if (!nested_vmx_check_permission(vcpu))
5165 if (nested_vmx_get_vmptr(vcpu, &vmptr, &r))
5168 if (!page_address_valid(vcpu, vmptr))
5169 return nested_vmx_fail(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5171 if (vmptr == vmx->nested.vmxon_ptr)
5172 return nested_vmx_fail(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
5174 /* Forbid normal VMPTRLD if Enlightened version was used */
5175 if (vmx->nested.hv_evmcs)
5178 if (vmx->nested.current_vmptr != vmptr) {
5179 struct kvm_host_map map;
5180 struct vmcs12 *new_vmcs12;
5182 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmptr), &map)) {
5184 * Reads from an unbacked page return all 1s,
5185 * which means that the 32 bits located at the
5186 * given physical address won't match the required
5187 * VMCS12_REVISION identifier.
5189 return nested_vmx_fail(vcpu,
5190 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5193 new_vmcs12 = map.hva;
5195 if (new_vmcs12->hdr.revision_id != VMCS12_REVISION ||
5196 (new_vmcs12->hdr.shadow_vmcs &&
5197 !nested_cpu_has_vmx_shadow_vmcs(vcpu))) {
5198 kvm_vcpu_unmap(vcpu, &map, false);
5199 return nested_vmx_fail(vcpu,
5200 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5203 nested_release_vmcs12(vcpu);
5206 * Load VMCS12 from guest memory since it is not already
5209 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
5210 kvm_vcpu_unmap(vcpu, &map, false);
5212 set_current_vmptr(vmx, vmptr);
5215 return nested_vmx_succeed(vcpu);
5218 /* Emulate the VMPTRST instruction */
5219 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5221 unsigned long exit_qual = vmx_get_exit_qual(vcpu);
5222 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5223 gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr;
5224 struct x86_exception e;
5228 if (!nested_vmx_check_permission(vcpu))
5231 if (unlikely(to_vmx(vcpu)->nested.hv_evmcs))
5234 if (get_vmx_mem_address(vcpu, exit_qual, instr_info,
5235 true, sizeof(gpa_t), &gva))
5237 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
5238 r = kvm_write_guest_virt_system(vcpu, gva, (void *)¤t_vmptr,
5240 if (r != X86EMUL_CONTINUE)
5241 return kvm_handle_memory_failure(vcpu, r, &e);
5243 return nested_vmx_succeed(vcpu);
5246 #define EPTP_PA_MASK GENMASK_ULL(51, 12)
5248 static bool nested_ept_root_matches(hpa_t root_hpa, u64 root_eptp, u64 eptp)
5250 return VALID_PAGE(root_hpa) &&
5251 ((root_eptp & EPTP_PA_MASK) == (eptp & EPTP_PA_MASK));
5254 /* Emulate the INVEPT instruction */
5255 static int handle_invept(struct kvm_vcpu *vcpu)
5257 struct vcpu_vmx *vmx = to_vmx(vcpu);
5258 u32 vmx_instruction_info, types;
5259 unsigned long type, roots_to_free;
5260 struct kvm_mmu *mmu;
5262 struct x86_exception e;
5268 if (!(vmx->nested.msrs.secondary_ctls_high &
5269 SECONDARY_EXEC_ENABLE_EPT) ||
5270 !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
5271 kvm_queue_exception(vcpu, UD_VECTOR);
5275 if (!nested_vmx_check_permission(vcpu))
5278 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5279 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5281 types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
5283 if (type >= 32 || !(types & (1 << type)))
5284 return nested_vmx_fail(vcpu, VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5286 /* According to the Intel VMX instruction reference, the memory
5287 * operand is read even if it isn't needed (e.g., for type==global)
5289 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5290 vmx_instruction_info, false, sizeof(operand), &gva))
5292 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
5293 if (r != X86EMUL_CONTINUE)
5294 return kvm_handle_memory_failure(vcpu, r, &e);
5297 * Nested EPT roots are always held through guest_mmu,
5300 mmu = &vcpu->arch.guest_mmu;
5303 case VMX_EPT_EXTENT_CONTEXT:
5304 if (!nested_vmx_check_eptp(vcpu, operand.eptp))
5305 return nested_vmx_fail(vcpu,
5306 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5309 if (nested_ept_root_matches(mmu->root_hpa, mmu->root_pgd,
5311 roots_to_free |= KVM_MMU_ROOT_CURRENT;
5313 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5314 if (nested_ept_root_matches(mmu->prev_roots[i].hpa,
5315 mmu->prev_roots[i].pgd,
5317 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5320 case VMX_EPT_EXTENT_GLOBAL:
5321 roots_to_free = KVM_MMU_ROOTS_ALL;
5329 kvm_mmu_free_roots(vcpu, mmu, roots_to_free);
5331 return nested_vmx_succeed(vcpu);
5334 static int handle_invvpid(struct kvm_vcpu *vcpu)
5336 struct vcpu_vmx *vmx = to_vmx(vcpu);
5337 u32 vmx_instruction_info;
5338 unsigned long type, types;
5340 struct x86_exception e;
5348 if (!(vmx->nested.msrs.secondary_ctls_high &
5349 SECONDARY_EXEC_ENABLE_VPID) ||
5350 !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
5351 kvm_queue_exception(vcpu, UD_VECTOR);
5355 if (!nested_vmx_check_permission(vcpu))
5358 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5359 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5361 types = (vmx->nested.msrs.vpid_caps &
5362 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
5364 if (type >= 32 || !(types & (1 << type)))
5365 return nested_vmx_fail(vcpu,
5366 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5368 /* according to the intel vmx instruction reference, the memory
5369 * operand is read even if it isn't needed (e.g., for type==global)
5371 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5372 vmx_instruction_info, false, sizeof(operand), &gva))
5374 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
5375 if (r != X86EMUL_CONTINUE)
5376 return kvm_handle_memory_failure(vcpu, r, &e);
5378 if (operand.vpid >> 16)
5379 return nested_vmx_fail(vcpu,
5380 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5382 vpid02 = nested_get_vpid02(vcpu);
5384 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
5385 if (!operand.vpid ||
5386 is_noncanonical_address(operand.gla, vcpu))
5387 return nested_vmx_fail(vcpu,
5388 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5389 vpid_sync_vcpu_addr(vpid02, operand.gla);
5391 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
5392 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
5394 return nested_vmx_fail(vcpu,
5395 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5396 vpid_sync_context(vpid02);
5398 case VMX_VPID_EXTENT_ALL_CONTEXT:
5399 vpid_sync_context(vpid02);
5403 return kvm_skip_emulated_instruction(vcpu);
5407 * Sync the shadow page tables if EPT is disabled, L1 is invalidating
5408 * linear mappings for L2 (tagged with L2's VPID). Free all roots as
5409 * VPIDs are not tracked in the MMU role.
5411 * Note, this operates on root_mmu, not guest_mmu, as L1 and L2 share
5412 * an MMU when EPT is disabled.
5414 * TODO: sync only the affected SPTEs for INVDIVIDUAL_ADDR.
5417 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu,
5420 return nested_vmx_succeed(vcpu);
5423 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
5424 struct vmcs12 *vmcs12)
5426 u32 index = kvm_rcx_read(vcpu);
5428 bool accessed_dirty;
5429 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
5431 if (!nested_cpu_has_eptp_switching(vmcs12) ||
5432 !nested_cpu_has_ept(vmcs12))
5435 if (index >= VMFUNC_EPTP_ENTRIES)
5439 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
5440 &new_eptp, index * 8, 8))
5443 accessed_dirty = !!(new_eptp & VMX_EPTP_AD_ENABLE_BIT);
5446 * If the (L2) guest does a vmfunc to the currently
5447 * active ept pointer, we don't have to do anything else
5449 if (vmcs12->ept_pointer != new_eptp) {
5450 if (!nested_vmx_check_eptp(vcpu, new_eptp))
5453 kvm_mmu_unload(vcpu);
5454 mmu->ept_ad = accessed_dirty;
5455 mmu->mmu_role.base.ad_disabled = !accessed_dirty;
5456 vmcs12->ept_pointer = new_eptp;
5458 * TODO: Check what's the correct approach in case
5459 * mmu reload fails. Currently, we just let the next
5460 * reload potentially fail
5462 kvm_mmu_reload(vcpu);
5468 static int handle_vmfunc(struct kvm_vcpu *vcpu)
5470 struct vcpu_vmx *vmx = to_vmx(vcpu);
5471 struct vmcs12 *vmcs12;
5472 u32 function = kvm_rax_read(vcpu);
5475 * VMFUNC is only supported for nested guests, but we always enable the
5476 * secondary control for simplicity; for non-nested mode, fake that we
5477 * didn't by injecting #UD.
5479 if (!is_guest_mode(vcpu)) {
5480 kvm_queue_exception(vcpu, UD_VECTOR);
5484 vmcs12 = get_vmcs12(vcpu);
5485 if ((vmcs12->vm_function_control & (1 << function)) == 0)
5490 if (nested_vmx_eptp_switching(vcpu, vmcs12))
5496 return kvm_skip_emulated_instruction(vcpu);
5499 nested_vmx_vmexit(vcpu, vmx->exit_reason,
5500 vmx_get_intr_info(vcpu),
5501 vmx_get_exit_qual(vcpu));
5506 * Return true if an IO instruction with the specified port and size should cause
5507 * a VM-exit into L1.
5509 bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port,
5512 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5513 gpa_t bitmap, last_bitmap;
5516 last_bitmap = (gpa_t)-1;
5521 bitmap = vmcs12->io_bitmap_a;
5522 else if (port < 0x10000)
5523 bitmap = vmcs12->io_bitmap_b;
5526 bitmap += (port & 0x7fff) / 8;
5528 if (last_bitmap != bitmap)
5529 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
5531 if (b & (1 << (port & 7)))
5536 last_bitmap = bitmap;
5542 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5543 struct vmcs12 *vmcs12)
5545 unsigned long exit_qualification;
5546 unsigned short port;
5549 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5550 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
5552 exit_qualification = vmx_get_exit_qual(vcpu);
5554 port = exit_qualification >> 16;
5555 size = (exit_qualification & 7) + 1;
5557 return nested_vmx_check_io_bitmaps(vcpu, port, size);
5561 * Return 1 if we should exit from L2 to L1 to handle an MSR access,
5562 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5563 * disinterest in the current event (read or write a specific MSR) by using an
5564 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5566 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5567 struct vmcs12 *vmcs12, u32 exit_reason)
5569 u32 msr_index = kvm_rcx_read(vcpu);
5572 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
5576 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5577 * for the four combinations of read/write and low/high MSR numbers.
5578 * First we need to figure out which of the four to use:
5580 bitmap = vmcs12->msr_bitmap;
5581 if (exit_reason == EXIT_REASON_MSR_WRITE)
5583 if (msr_index >= 0xc0000000) {
5584 msr_index -= 0xc0000000;
5588 /* Then read the msr_index'th bit from this bitmap: */
5589 if (msr_index < 1024*8) {
5591 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
5593 return 1 & (b >> (msr_index & 7));
5595 return true; /* let L1 handle the wrong parameter */
5599 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5600 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5601 * intercept (via guest_host_mask etc.) the current event.
5603 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5604 struct vmcs12 *vmcs12)
5606 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5607 int cr = exit_qualification & 15;
5611 switch ((exit_qualification >> 4) & 3) {
5612 case 0: /* mov to cr */
5613 reg = (exit_qualification >> 8) & 15;
5614 val = kvm_register_readl(vcpu, reg);
5617 if (vmcs12->cr0_guest_host_mask &
5618 (val ^ vmcs12->cr0_read_shadow))
5622 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5626 if (vmcs12->cr4_guest_host_mask &
5627 (vmcs12->cr4_read_shadow ^ val))
5631 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5637 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5638 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5641 case 1: /* mov from cr */
5644 if (vmcs12->cpu_based_vm_exec_control &
5645 CPU_BASED_CR3_STORE_EXITING)
5649 if (vmcs12->cpu_based_vm_exec_control &
5650 CPU_BASED_CR8_STORE_EXITING)
5657 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5658 * cr0. Other attempted changes are ignored, with no exit.
5660 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5661 if (vmcs12->cr0_guest_host_mask & 0xe &
5662 (val ^ vmcs12->cr0_read_shadow))
5664 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5665 !(vmcs12->cr0_read_shadow & 0x1) &&
5673 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu,
5674 struct vmcs12 *vmcs12, gpa_t bitmap)
5676 u32 vmx_instruction_info;
5677 unsigned long field;
5680 if (!nested_cpu_has_shadow_vmcs(vmcs12))
5683 /* Decode instruction info and find the field to access */
5684 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5685 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5687 /* Out-of-range fields always cause a VM exit from L2 to L1 */
5691 if (kvm_vcpu_read_guest(vcpu, bitmap + field/8, &b, 1))
5694 return 1 & (b >> (field & 7));
5697 static bool nested_vmx_exit_handled_mtf(struct vmcs12 *vmcs12)
5699 u32 entry_intr_info = vmcs12->vm_entry_intr_info_field;
5701 if (nested_cpu_has_mtf(vmcs12))
5705 * An MTF VM-exit may be injected into the guest by setting the
5706 * interruption-type to 7 (other event) and the vector field to 0. Such
5707 * is the case regardless of the 'monitor trap flag' VM-execution
5710 return entry_intr_info == (INTR_INFO_VALID_MASK
5711 | INTR_TYPE_OTHER_EVENT);
5715 * Return true if L0 wants to handle an exit from L2 regardless of whether or not
5716 * L1 wants the exit. Only call this when in is_guest_mode (L2).
5718 static bool nested_vmx_l0_wants_exit(struct kvm_vcpu *vcpu, u32 exit_reason)
5722 switch ((u16)exit_reason) {
5723 case EXIT_REASON_EXCEPTION_NMI:
5724 intr_info = vmx_get_intr_info(vcpu);
5725 if (is_nmi(intr_info))
5727 else if (is_page_fault(intr_info))
5728 return vcpu->arch.apf.host_apf_flags || !enable_ept;
5729 else if (is_debug(intr_info) &&
5731 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5733 else if (is_breakpoint(intr_info) &&
5734 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5737 case EXIT_REASON_EXTERNAL_INTERRUPT:
5739 case EXIT_REASON_MCE_DURING_VMENTRY:
5741 case EXIT_REASON_EPT_VIOLATION:
5743 * L0 always deals with the EPT violation. If nested EPT is
5744 * used, and the nested mmu code discovers that the address is
5745 * missing in the guest EPT table (EPT12), the EPT violation
5746 * will be injected with nested_ept_inject_page_fault()
5749 case EXIT_REASON_EPT_MISCONFIG:
5751 * L2 never uses directly L1's EPT, but rather L0's own EPT
5752 * table (shadow on EPT) or a merged EPT table that L0 built
5753 * (EPT on EPT). So any problems with the structure of the
5754 * table is L0's fault.
5757 case EXIT_REASON_PREEMPTION_TIMER:
5759 case EXIT_REASON_PML_FULL:
5760 /* We emulate PML support to L1. */
5762 case EXIT_REASON_VMFUNC:
5763 /* VM functions are emulated through L2->L0 vmexits. */
5765 case EXIT_REASON_ENCLS:
5766 /* SGX is never exposed to L1 */
5775 * Return 1 if L1 wants to intercept an exit from L2. Only call this when in
5776 * is_guest_mode (L2).
5778 static bool nested_vmx_l1_wants_exit(struct kvm_vcpu *vcpu, u32 exit_reason)
5780 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5783 switch ((u16)exit_reason) {
5784 case EXIT_REASON_EXCEPTION_NMI:
5785 intr_info = vmx_get_intr_info(vcpu);
5786 if (is_nmi(intr_info))
5788 else if (is_page_fault(intr_info))
5790 return vmcs12->exception_bitmap &
5791 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5792 case EXIT_REASON_EXTERNAL_INTERRUPT:
5793 return nested_exit_on_intr(vcpu);
5794 case EXIT_REASON_TRIPLE_FAULT:
5796 case EXIT_REASON_INTERRUPT_WINDOW:
5797 return nested_cpu_has(vmcs12, CPU_BASED_INTR_WINDOW_EXITING);
5798 case EXIT_REASON_NMI_WINDOW:
5799 return nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING);
5800 case EXIT_REASON_TASK_SWITCH:
5802 case EXIT_REASON_CPUID:
5804 case EXIT_REASON_HLT:
5805 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5806 case EXIT_REASON_INVD:
5808 case EXIT_REASON_INVLPG:
5809 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5810 case EXIT_REASON_RDPMC:
5811 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5812 case EXIT_REASON_RDRAND:
5813 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
5814 case EXIT_REASON_RDSEED:
5815 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
5816 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
5817 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5818 case EXIT_REASON_VMREAD:
5819 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
5820 vmcs12->vmread_bitmap);
5821 case EXIT_REASON_VMWRITE:
5822 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
5823 vmcs12->vmwrite_bitmap);
5824 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5825 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5826 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMRESUME:
5827 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5828 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
5830 * VMX instructions trap unconditionally. This allows L1 to
5831 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5834 case EXIT_REASON_CR_ACCESS:
5835 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5836 case EXIT_REASON_DR_ACCESS:
5837 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5838 case EXIT_REASON_IO_INSTRUCTION:
5839 return nested_vmx_exit_handled_io(vcpu, vmcs12);
5840 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
5841 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
5842 case EXIT_REASON_MSR_READ:
5843 case EXIT_REASON_MSR_WRITE:
5844 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5845 case EXIT_REASON_INVALID_STATE:
5847 case EXIT_REASON_MWAIT_INSTRUCTION:
5848 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5849 case EXIT_REASON_MONITOR_TRAP_FLAG:
5850 return nested_vmx_exit_handled_mtf(vmcs12);
5851 case EXIT_REASON_MONITOR_INSTRUCTION:
5852 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5853 case EXIT_REASON_PAUSE_INSTRUCTION:
5854 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5855 nested_cpu_has2(vmcs12,
5856 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5857 case EXIT_REASON_MCE_DURING_VMENTRY:
5859 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5860 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
5861 case EXIT_REASON_APIC_ACCESS:
5862 case EXIT_REASON_APIC_WRITE:
5863 case EXIT_REASON_EOI_INDUCED:
5865 * The controls for "virtualize APIC accesses," "APIC-
5866 * register virtualization," and "virtual-interrupt
5867 * delivery" only come from vmcs12.
5870 case EXIT_REASON_INVPCID:
5872 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
5873 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5874 case EXIT_REASON_WBINVD:
5875 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5876 case EXIT_REASON_XSETBV:
5878 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
5880 * This should never happen, since it is not possible to
5881 * set XSS to a non-zero value---neither in L1 nor in L2.
5882 * If if it were, XSS would have to be checked against
5883 * the XSS exit bitmap in vmcs12.
5885 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
5886 case EXIT_REASON_UMWAIT:
5887 case EXIT_REASON_TPAUSE:
5888 return nested_cpu_has2(vmcs12,
5889 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE);
5896 * Conditionally reflect a VM-Exit into L1. Returns %true if the VM-Exit was
5897 * reflected into L1.
5899 bool nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu)
5901 struct vcpu_vmx *vmx = to_vmx(vcpu);
5902 u32 exit_reason = vmx->exit_reason;
5903 unsigned long exit_qual;
5906 WARN_ON_ONCE(vmx->nested.nested_run_pending);
5909 * Late nested VM-Fail shares the same flow as nested VM-Exit since KVM
5910 * has already loaded L2's state.
5912 if (unlikely(vmx->fail)) {
5913 trace_kvm_nested_vmenter_failed(
5914 "hardware VM-instruction error: ",
5915 vmcs_read32(VM_INSTRUCTION_ERROR));
5918 goto reflect_vmexit;
5921 exit_intr_info = vmx_get_intr_info(vcpu);
5922 exit_qual = vmx_get_exit_qual(vcpu);
5924 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, exit_qual,
5925 vmx->idt_vectoring_info, exit_intr_info,
5926 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5929 /* If L0 (KVM) wants the exit, it trumps L1's desires. */
5930 if (nested_vmx_l0_wants_exit(vcpu, exit_reason))
5933 /* If L1 doesn't want the exit, handle it in L0. */
5934 if (!nested_vmx_l1_wants_exit(vcpu, exit_reason))
5938 * vmcs.VM_EXIT_INTR_INFO is only valid for EXCEPTION_NMI exits. For
5939 * EXTERNAL_INTERRUPT, the value for vmcs12->vm_exit_intr_info would
5940 * need to be synthesized by querying the in-kernel LAPIC, but external
5941 * interrupts are never reflected to L1 so it's a non-issue.
5943 if ((exit_intr_info &
5944 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
5945 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
5946 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5948 vmcs12->vm_exit_intr_error_code =
5949 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5953 nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info, exit_qual);
5957 static int vmx_get_nested_state(struct kvm_vcpu *vcpu,
5958 struct kvm_nested_state __user *user_kvm_nested_state,
5961 struct vcpu_vmx *vmx;
5962 struct vmcs12 *vmcs12;
5963 struct kvm_nested_state kvm_state = {
5965 .format = KVM_STATE_NESTED_FORMAT_VMX,
5966 .size = sizeof(kvm_state),
5968 .hdr.vmx.vmxon_pa = -1ull,
5969 .hdr.vmx.vmcs12_pa = -1ull,
5970 .hdr.vmx.preemption_timer_deadline = 0,
5972 struct kvm_vmx_nested_state_data __user *user_vmx_nested_state =
5973 &user_kvm_nested_state->data.vmx[0];
5976 return kvm_state.size + sizeof(*user_vmx_nested_state);
5979 vmcs12 = get_vmcs12(vcpu);
5981 if (nested_vmx_allowed(vcpu) &&
5982 (vmx->nested.vmxon || vmx->nested.smm.vmxon)) {
5983 kvm_state.hdr.vmx.vmxon_pa = vmx->nested.vmxon_ptr;
5984 kvm_state.hdr.vmx.vmcs12_pa = vmx->nested.current_vmptr;
5986 if (vmx_has_valid_vmcs12(vcpu)) {
5987 kvm_state.size += sizeof(user_vmx_nested_state->vmcs12);
5989 if (vmx->nested.hv_evmcs)
5990 kvm_state.flags |= KVM_STATE_NESTED_EVMCS;
5992 if (is_guest_mode(vcpu) &&
5993 nested_cpu_has_shadow_vmcs(vmcs12) &&
5994 vmcs12->vmcs_link_pointer != -1ull)
5995 kvm_state.size += sizeof(user_vmx_nested_state->shadow_vmcs12);
5998 if (vmx->nested.smm.vmxon)
5999 kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_VMXON;
6001 if (vmx->nested.smm.guest_mode)
6002 kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_GUEST_MODE;
6004 if (is_guest_mode(vcpu)) {
6005 kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE;
6007 if (vmx->nested.nested_run_pending)
6008 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING;
6010 if (vmx->nested.mtf_pending)
6011 kvm_state.flags |= KVM_STATE_NESTED_MTF_PENDING;
6013 if (nested_cpu_has_preemption_timer(vmcs12) &&
6014 vmx->nested.has_preemption_timer_deadline) {
6015 kvm_state.hdr.vmx.flags |=
6016 KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE;
6017 kvm_state.hdr.vmx.preemption_timer_deadline =
6018 vmx->nested.preemption_timer_deadline;
6023 if (user_data_size < kvm_state.size)
6026 if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state)))
6029 if (!vmx_has_valid_vmcs12(vcpu))
6033 * When running L2, the authoritative vmcs12 state is in the
6034 * vmcs02. When running L1, the authoritative vmcs12 state is
6035 * in the shadow or enlightened vmcs linked to vmcs01, unless
6036 * need_vmcs12_to_shadow_sync is set, in which case, the authoritative
6037 * vmcs12 state is in the vmcs12 already.
6039 if (is_guest_mode(vcpu)) {
6040 sync_vmcs02_to_vmcs12(vcpu, vmcs12);
6041 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
6042 } else if (!vmx->nested.need_vmcs12_to_shadow_sync) {
6043 if (vmx->nested.hv_evmcs)
6044 copy_enlightened_to_vmcs12(vmx);
6045 else if (enable_shadow_vmcs)
6046 copy_shadow_to_vmcs12(vmx);
6049 BUILD_BUG_ON(sizeof(user_vmx_nested_state->vmcs12) < VMCS12_SIZE);
6050 BUILD_BUG_ON(sizeof(user_vmx_nested_state->shadow_vmcs12) < VMCS12_SIZE);
6053 * Copy over the full allocated size of vmcs12 rather than just the size
6056 if (copy_to_user(user_vmx_nested_state->vmcs12, vmcs12, VMCS12_SIZE))
6059 if (nested_cpu_has_shadow_vmcs(vmcs12) &&
6060 vmcs12->vmcs_link_pointer != -1ull) {
6061 if (copy_to_user(user_vmx_nested_state->shadow_vmcs12,
6062 get_shadow_vmcs12(vcpu), VMCS12_SIZE))
6066 return kvm_state.size;
6070 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
6072 void vmx_leave_nested(struct kvm_vcpu *vcpu)
6074 if (is_guest_mode(vcpu)) {
6075 to_vmx(vcpu)->nested.nested_run_pending = 0;
6076 nested_vmx_vmexit(vcpu, -1, 0, 0);
6081 static int vmx_set_nested_state(struct kvm_vcpu *vcpu,
6082 struct kvm_nested_state __user *user_kvm_nested_state,
6083 struct kvm_nested_state *kvm_state)
6085 struct vcpu_vmx *vmx = to_vmx(vcpu);
6086 struct vmcs12 *vmcs12;
6087 enum vm_entry_failure_code ignored;
6088 struct kvm_vmx_nested_state_data __user *user_vmx_nested_state =
6089 &user_kvm_nested_state->data.vmx[0];
6092 if (kvm_state->format != KVM_STATE_NESTED_FORMAT_VMX)
6095 if (kvm_state->hdr.vmx.vmxon_pa == -1ull) {
6096 if (kvm_state->hdr.vmx.smm.flags)
6099 if (kvm_state->hdr.vmx.vmcs12_pa != -1ull)
6103 * KVM_STATE_NESTED_EVMCS used to signal that KVM should
6104 * enable eVMCS capability on vCPU. However, since then
6105 * code was changed such that flag signals vmcs12 should
6106 * be copied into eVMCS in guest memory.
6108 * To preserve backwards compatability, allow user
6109 * to set this flag even when there is no VMXON region.
6111 if (kvm_state->flags & ~KVM_STATE_NESTED_EVMCS)
6114 if (!nested_vmx_allowed(vcpu))
6117 if (!page_address_valid(vcpu, kvm_state->hdr.vmx.vmxon_pa))
6121 if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
6122 (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
6125 if (kvm_state->hdr.vmx.smm.flags &
6126 ~(KVM_STATE_NESTED_SMM_GUEST_MODE | KVM_STATE_NESTED_SMM_VMXON))
6129 if (kvm_state->hdr.vmx.flags & ~KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE)
6133 * SMM temporarily disables VMX, so we cannot be in guest mode,
6134 * nor can VMLAUNCH/VMRESUME be pending. Outside SMM, SMM flags
6139 (KVM_STATE_NESTED_GUEST_MODE | KVM_STATE_NESTED_RUN_PENDING))
6140 : kvm_state->hdr.vmx.smm.flags)
6143 if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
6144 !(kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON))
6147 if ((kvm_state->flags & KVM_STATE_NESTED_EVMCS) &&
6148 (!nested_vmx_allowed(vcpu) || !vmx->nested.enlightened_vmcs_enabled))
6151 vmx_leave_nested(vcpu);
6153 if (kvm_state->hdr.vmx.vmxon_pa == -1ull)
6156 vmx->nested.vmxon_ptr = kvm_state->hdr.vmx.vmxon_pa;
6157 ret = enter_vmx_operation(vcpu);
6161 /* Empty 'VMXON' state is permitted if no VMCS loaded */
6162 if (kvm_state->size < sizeof(*kvm_state) + sizeof(*vmcs12)) {
6163 /* See vmx_has_valid_vmcs12. */
6164 if ((kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE) ||
6165 (kvm_state->flags & KVM_STATE_NESTED_EVMCS) ||
6166 (kvm_state->hdr.vmx.vmcs12_pa != -1ull))
6172 if (kvm_state->hdr.vmx.vmcs12_pa != -1ull) {
6173 if (kvm_state->hdr.vmx.vmcs12_pa == kvm_state->hdr.vmx.vmxon_pa ||
6174 !page_address_valid(vcpu, kvm_state->hdr.vmx.vmcs12_pa))
6177 set_current_vmptr(vmx, kvm_state->hdr.vmx.vmcs12_pa);
6178 } else if (kvm_state->flags & KVM_STATE_NESTED_EVMCS) {
6180 * nested_vmx_handle_enlightened_vmptrld() cannot be called
6181 * directly from here as HV_X64_MSR_VP_ASSIST_PAGE may not be
6182 * restored yet. EVMCS will be mapped from
6183 * nested_get_vmcs12_pages().
6185 kvm_make_request(KVM_REQ_GET_VMCS12_PAGES, vcpu);
6190 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON) {
6191 vmx->nested.smm.vmxon = true;
6192 vmx->nested.vmxon = false;
6194 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE)
6195 vmx->nested.smm.guest_mode = true;
6198 vmcs12 = get_vmcs12(vcpu);
6199 if (copy_from_user(vmcs12, user_vmx_nested_state->vmcs12, sizeof(*vmcs12)))
6202 if (vmcs12->hdr.revision_id != VMCS12_REVISION)
6205 if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
6208 vmx->nested.nested_run_pending =
6209 !!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);
6211 vmx->nested.mtf_pending =
6212 !!(kvm_state->flags & KVM_STATE_NESTED_MTF_PENDING);
6215 if (nested_cpu_has_shadow_vmcs(vmcs12) &&
6216 vmcs12->vmcs_link_pointer != -1ull) {
6217 struct vmcs12 *shadow_vmcs12 = get_shadow_vmcs12(vcpu);
6219 if (kvm_state->size <
6220 sizeof(*kvm_state) +
6221 sizeof(user_vmx_nested_state->vmcs12) + sizeof(*shadow_vmcs12))
6222 goto error_guest_mode;
6224 if (copy_from_user(shadow_vmcs12,
6225 user_vmx_nested_state->shadow_vmcs12,
6226 sizeof(*shadow_vmcs12))) {
6228 goto error_guest_mode;
6231 if (shadow_vmcs12->hdr.revision_id != VMCS12_REVISION ||
6232 !shadow_vmcs12->hdr.shadow_vmcs)
6233 goto error_guest_mode;
6236 vmx->nested.has_preemption_timer_deadline = false;
6237 if (kvm_state->hdr.vmx.flags & KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE) {
6238 vmx->nested.has_preemption_timer_deadline = true;
6239 vmx->nested.preemption_timer_deadline =
6240 kvm_state->hdr.vmx.preemption_timer_deadline;
6243 if (nested_vmx_check_controls(vcpu, vmcs12) ||
6244 nested_vmx_check_host_state(vcpu, vmcs12) ||
6245 nested_vmx_check_guest_state(vcpu, vmcs12, &ignored))
6246 goto error_guest_mode;
6248 vmx->nested.dirty_vmcs12 = true;
6249 ret = nested_vmx_enter_non_root_mode(vcpu, false);
6251 goto error_guest_mode;
6256 vmx->nested.nested_run_pending = 0;
6260 void nested_vmx_set_vmcs_shadowing_bitmap(void)
6262 if (enable_shadow_vmcs) {
6263 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6264 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
6269 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
6270 * returned for the various VMX controls MSRs when nested VMX is enabled.
6271 * The same values should also be used to verify that vmcs12 control fields are
6272 * valid during nested entry from L1 to L2.
6273 * Each of these control msrs has a low and high 32-bit half: A low bit is on
6274 * if the corresponding bit in the (32-bit) control field *must* be on, and a
6275 * bit in the high half is on if the corresponding bit in the control field
6276 * may be on. See also vmx_control_verify().
6278 void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps)
6281 * Note that as a general rule, the high half of the MSRs (bits in
6282 * the control fields which may be 1) should be initialized by the
6283 * intersection of the underlying hardware's MSR (i.e., features which
6284 * can be supported) and the list of features we want to expose -
6285 * because they are known to be properly supported in our code.
6286 * Also, usually, the low half of the MSRs (bits which must be 1) can
6287 * be set to 0, meaning that L1 may turn off any of these bits. The
6288 * reason is that if one of these bits is necessary, it will appear
6289 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
6290 * fields of vmcs01 and vmcs02, will turn these bits off - and
6291 * nested_vmx_l1_wants_exit() will not pass related exits to L1.
6292 * These rules have exceptions below.
6295 /* pin-based controls */
6296 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
6297 msrs->pinbased_ctls_low,
6298 msrs->pinbased_ctls_high);
6299 msrs->pinbased_ctls_low |=
6300 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
6301 msrs->pinbased_ctls_high &=
6302 PIN_BASED_EXT_INTR_MASK |
6303 PIN_BASED_NMI_EXITING |
6304 PIN_BASED_VIRTUAL_NMIS |
6305 (enable_apicv ? PIN_BASED_POSTED_INTR : 0);
6306 msrs->pinbased_ctls_high |=
6307 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
6308 PIN_BASED_VMX_PREEMPTION_TIMER;
6311 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
6312 msrs->exit_ctls_low,
6313 msrs->exit_ctls_high);
6314 msrs->exit_ctls_low =
6315 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
6317 msrs->exit_ctls_high &=
6318 #ifdef CONFIG_X86_64
6319 VM_EXIT_HOST_ADDR_SPACE_SIZE |
6321 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
6322 VM_EXIT_CLEAR_BNDCFGS | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
6323 msrs->exit_ctls_high |=
6324 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
6325 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
6326 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
6328 /* We support free control of debug control saving. */
6329 msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
6331 /* entry controls */
6332 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
6333 msrs->entry_ctls_low,
6334 msrs->entry_ctls_high);
6335 msrs->entry_ctls_low =
6336 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
6337 msrs->entry_ctls_high &=
6338 #ifdef CONFIG_X86_64
6339 VM_ENTRY_IA32E_MODE |
6341 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS |
6342 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
6343 msrs->entry_ctls_high |=
6344 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
6346 /* We support free control of debug control loading. */
6347 msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
6349 /* cpu-based controls */
6350 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
6351 msrs->procbased_ctls_low,
6352 msrs->procbased_ctls_high);
6353 msrs->procbased_ctls_low =
6354 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
6355 msrs->procbased_ctls_high &=
6356 CPU_BASED_INTR_WINDOW_EXITING |
6357 CPU_BASED_NMI_WINDOW_EXITING | CPU_BASED_USE_TSC_OFFSETTING |
6358 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
6359 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
6360 CPU_BASED_CR3_STORE_EXITING |
6361 #ifdef CONFIG_X86_64
6362 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
6364 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
6365 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
6366 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
6367 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
6368 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
6370 * We can allow some features even when not supported by the
6371 * hardware. For example, L1 can specify an MSR bitmap - and we
6372 * can use it to avoid exits to L1 - even when L0 runs L2
6373 * without MSR bitmaps.
6375 msrs->procbased_ctls_high |=
6376 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
6377 CPU_BASED_USE_MSR_BITMAPS;
6379 /* We support free control of CR3 access interception. */
6380 msrs->procbased_ctls_low &=
6381 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
6384 * secondary cpu-based controls. Do not include those that
6385 * depend on CPUID bits, they are added later by
6386 * vmx_vcpu_after_set_cpuid.
6388 if (msrs->procbased_ctls_high & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
6389 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
6390 msrs->secondary_ctls_low,
6391 msrs->secondary_ctls_high);
6393 msrs->secondary_ctls_low = 0;
6394 msrs->secondary_ctls_high &=
6395 SECONDARY_EXEC_DESC |
6396 SECONDARY_EXEC_RDTSCP |
6397 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6398 SECONDARY_EXEC_WBINVD_EXITING |
6399 SECONDARY_EXEC_APIC_REGISTER_VIRT |
6400 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
6401 SECONDARY_EXEC_RDRAND_EXITING |
6402 SECONDARY_EXEC_ENABLE_INVPCID |
6403 SECONDARY_EXEC_RDSEED_EXITING |
6404 SECONDARY_EXEC_XSAVES;
6407 * We can emulate "VMCS shadowing," even if the hardware
6408 * doesn't support it.
6410 msrs->secondary_ctls_high |=
6411 SECONDARY_EXEC_SHADOW_VMCS;
6414 /* nested EPT: emulate EPT also to L1 */
6415 msrs->secondary_ctls_high |=
6416 SECONDARY_EXEC_ENABLE_EPT;
6418 VMX_EPT_PAGE_WALK_4_BIT |
6419 VMX_EPT_PAGE_WALK_5_BIT |
6421 VMX_EPT_INVEPT_BIT |
6422 VMX_EPT_EXECUTE_ONLY_BIT;
6424 msrs->ept_caps &= ept_caps;
6425 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
6426 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
6427 VMX_EPT_1GB_PAGE_BIT;
6428 if (enable_ept_ad_bits) {
6429 msrs->secondary_ctls_high |=
6430 SECONDARY_EXEC_ENABLE_PML;
6431 msrs->ept_caps |= VMX_EPT_AD_BIT;
6435 if (cpu_has_vmx_vmfunc()) {
6436 msrs->secondary_ctls_high |=
6437 SECONDARY_EXEC_ENABLE_VMFUNC;
6439 * Advertise EPTP switching unconditionally
6440 * since we emulate it
6443 msrs->vmfunc_controls =
6444 VMX_VMFUNC_EPTP_SWITCHING;
6448 * Old versions of KVM use the single-context version without
6449 * checking for support, so declare that it is supported even
6450 * though it is treated as global context. The alternative is
6451 * not failing the single-context invvpid, and it is worse.
6454 msrs->secondary_ctls_high |=
6455 SECONDARY_EXEC_ENABLE_VPID;
6456 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
6457 VMX_VPID_EXTENT_SUPPORTED_MASK;
6460 if (enable_unrestricted_guest)
6461 msrs->secondary_ctls_high |=
6462 SECONDARY_EXEC_UNRESTRICTED_GUEST;
6464 if (flexpriority_enabled)
6465 msrs->secondary_ctls_high |=
6466 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6468 /* miscellaneous data */
6469 rdmsr(MSR_IA32_VMX_MISC,
6472 msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
6474 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
6475 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
6476 VMX_MISC_ACTIVITY_HLT;
6477 msrs->misc_high = 0;
6480 * This MSR reports some information about VMX support. We
6481 * should return information about the VMX we emulate for the
6482 * guest, and the VMCS structure we give it - not about the
6483 * VMX support of the underlying hardware.
6487 VMX_BASIC_TRUE_CTLS |
6488 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
6489 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
6491 if (cpu_has_vmx_basic_inout())
6492 msrs->basic |= VMX_BASIC_INOUT;
6495 * These MSRs specify bits which the guest must keep fixed on
6496 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
6497 * We picked the standard core2 setting.
6499 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
6500 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
6501 msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
6502 msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
6504 /* These MSRs specify bits which the guest must keep fixed off. */
6505 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
6506 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
6508 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
6509 msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
6512 void nested_vmx_hardware_unsetup(void)
6516 if (enable_shadow_vmcs) {
6517 for (i = 0; i < VMX_BITMAP_NR; i++)
6518 free_page((unsigned long)vmx_bitmap[i]);
6522 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *))
6526 if (!cpu_has_vmx_shadow_vmcs())
6527 enable_shadow_vmcs = 0;
6528 if (enable_shadow_vmcs) {
6529 for (i = 0; i < VMX_BITMAP_NR; i++) {
6531 * The vmx_bitmap is not tied to a VM and so should
6532 * not be charged to a memcg.
6534 vmx_bitmap[i] = (unsigned long *)
6535 __get_free_page(GFP_KERNEL);
6536 if (!vmx_bitmap[i]) {
6537 nested_vmx_hardware_unsetup();
6542 init_vmcs_shadow_fields();
6545 exit_handlers[EXIT_REASON_VMCLEAR] = handle_vmclear;
6546 exit_handlers[EXIT_REASON_VMLAUNCH] = handle_vmlaunch;
6547 exit_handlers[EXIT_REASON_VMPTRLD] = handle_vmptrld;
6548 exit_handlers[EXIT_REASON_VMPTRST] = handle_vmptrst;
6549 exit_handlers[EXIT_REASON_VMREAD] = handle_vmread;
6550 exit_handlers[EXIT_REASON_VMRESUME] = handle_vmresume;
6551 exit_handlers[EXIT_REASON_VMWRITE] = handle_vmwrite;
6552 exit_handlers[EXIT_REASON_VMOFF] = handle_vmoff;
6553 exit_handlers[EXIT_REASON_VMON] = handle_vmon;
6554 exit_handlers[EXIT_REASON_INVEPT] = handle_invept;
6555 exit_handlers[EXIT_REASON_INVVPID] = handle_invvpid;
6556 exit_handlers[EXIT_REASON_VMFUNC] = handle_vmfunc;
6561 struct kvm_x86_nested_ops vmx_nested_ops = {
6562 .check_events = vmx_check_nested_events,
6563 .hv_timer_pending = nested_vmx_preemption_timer_pending,
6564 .get_state = vmx_get_nested_state,
6565 .set_state = vmx_set_nested_state,
6566 .get_vmcs12_pages = nested_get_vmcs12_pages,
6567 .write_log_dirty = nested_vmx_write_pml_buffer,
6568 .enable_evmcs = nested_enable_evmcs,
6569 .get_evmcs_version = nested_get_evmcs_version,