arch/x86/kvm/vmx/nested.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include <linux/objtool.h>
   4 #include <linux/percpu.h>
   5
   6 #include <asm/debugreg.h>
   7 #include <asm/mmu_context.h>
   8
   9 #include "cpuid.h"
  10 #include "evmcs.h"
  11 #include "hyperv.h"
  12 #include "mmu.h"
  13 #include "nested.h"
  14 #include "pmu.h"
  15 #include "sgx.h"
  16 #include "trace.h"
  17 #include "vmx.h"
  18 #include "x86.h"
  19
  20 static bool __read_mostly enable_shadow_vmcs = 1;
  21 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  22
  23 static bool __read_mostly nested_early_check = 0;
  24 module_param(nested_early_check, bool, S_IRUGO);
  25
  26 #define CC KVM_NESTED_VMENTER_CONSISTENCY_CHECK
  27
  28 /*
  29  * Hyper-V requires all of these, so mark them as supported even though
  30  * they are just treated the same as all-context.
  31  */
  32 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
  33         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
  34         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
  35         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
  36         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
  37
  38 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
  39
  40 enum {
  41         VMX_VMREAD_BITMAP,
  42         VMX_VMWRITE_BITMAP,
  43         VMX_BITMAP_NR
  44 };
  45 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
  46
  47 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
  48 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
  49
  50 struct shadow_vmcs_field {
  51         u16     encoding;
  52         u16     offset;
  53 };
  54 static struct shadow_vmcs_field shadow_read_only_fields[] = {
  55 #define SHADOW_FIELD_RO(x, y) { x, offsetof(struct vmcs12, y) },
  56 #include "vmcs_shadow_fields.h"
  57 };
  58 static int max_shadow_read_only_fields =
  59         ARRAY_SIZE(shadow_read_only_fields);
  60
  61 static struct shadow_vmcs_field shadow_read_write_fields[] = {
  62 #define SHADOW_FIELD_RW(x, y) { x, offsetof(struct vmcs12, y) },
  63 #include "vmcs_shadow_fields.h"
  64 };
  65 static int max_shadow_read_write_fields =
  66         ARRAY_SIZE(shadow_read_write_fields);
  67
  68 static void init_vmcs_shadow_fields(void)
  69 {
  70         int i, j;
  71
  72         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
  73         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
  74
  75         for (i = j = 0; i < max_shadow_read_only_fields; i++) {
  76                 struct shadow_vmcs_field entry = shadow_read_only_fields[i];
  77                 u16 field = entry.encoding;
  78
  79                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
  80                     (i + 1 == max_shadow_read_only_fields ||
  81                      shadow_read_only_fields[i + 1].encoding != field + 1))
  82                         pr_err("Missing field from shadow_read_only_field %x\n",
  83                                field + 1);
  84
  85                 clear_bit(field, vmx_vmread_bitmap);
  86                 if (field & 1)
  87 #ifdef CONFIG_X86_64
  88                         continue;
  89 #else
  90                         entry.offset += sizeof(u32);
  91 #endif
  92                 shadow_read_only_fields[j++] = entry;
  93         }
  94         max_shadow_read_only_fields = j;
  95
  96         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
  97                 struct shadow_vmcs_field entry = shadow_read_write_fields[i];
  98                 u16 field = entry.encoding;
  99
 100                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
 101                     (i + 1 == max_shadow_read_write_fields ||
 102                      shadow_read_write_fields[i + 1].encoding != field + 1))
 103                         pr_err("Missing field from shadow_read_write_field %x\n",
 104                                field + 1);
 105
 106                 WARN_ONCE(field >= GUEST_ES_AR_BYTES &&
 107                           field <= GUEST_TR_AR_BYTES,
 108                           "Update vmcs12_write_any() to drop reserved bits from AR_BYTES");
 109
 110                 /*
 111                  * PML and the preemption timer can be emulated, but the
 112                  * processor cannot vmwrite to fields that don't exist
 113                  * on bare metal.
 114                  */
 115                 switch (field) {
 116                 case GUEST_PML_INDEX:
 117                         if (!cpu_has_vmx_pml())
 118                                 continue;
 119                         break;
 120                 case VMX_PREEMPTION_TIMER_VALUE:
 121                         if (!cpu_has_vmx_preemption_timer())
 122                                 continue;
 123                         break;
 124                 case GUEST_INTR_STATUS:
 125                         if (!cpu_has_vmx_apicv())
 126                                 continue;
 127                         break;
 128                 default:
 129                         break;
 130                 }
 131
 132                 clear_bit(field, vmx_vmwrite_bitmap);
 133                 clear_bit(field, vmx_vmread_bitmap);
 134                 if (field & 1)
 135 #ifdef CONFIG_X86_64
 136                         continue;
 137 #else
 138                         entry.offset += sizeof(u32);
 139 #endif
 140                 shadow_read_write_fields[j++] = entry;
 141         }
 142         max_shadow_read_write_fields = j;
 143 }
 144
 145 /*
 146  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
 147  * set the success or error code of an emulated VMX instruction (as specified
 148  * by Vol 2B, VMX Instruction Reference, "Conventions"), and skip the emulated
 149  * instruction.
 150  */
 151 static int nested_vmx_succeed(struct kvm_vcpu *vcpu)
 152 {
 153         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
 154                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
 155                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
 156         return kvm_skip_emulated_instruction(vcpu);
 157 }
 158
 159 static int nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
 160 {
 161         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
 162                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
 163                             X86_EFLAGS_SF | X86_EFLAGS_OF))
 164                         | X86_EFLAGS_CF);
 165         return kvm_skip_emulated_instruction(vcpu);
 166 }
 167
 168 static int nested_vmx_failValid(struct kvm_vcpu *vcpu,
 169                                 u32 vm_instruction_error)
 170 {
 171         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
 172                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
 173                             X86_EFLAGS_SF | X86_EFLAGS_OF))
 174                         | X86_EFLAGS_ZF);
 175         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
 176         /*
 177          * We don't need to force sync to shadow VMCS because
 178          * VM_INSTRUCTION_ERROR is not shadowed. Enlightened VMCS 'shadows' all
 179          * fields and thus must be synced.
 180          */
 181         if (to_vmx(vcpu)->nested.hv_evmcs_vmptr != EVMPTR_INVALID)
 182                 to_vmx(vcpu)->nested.need_vmcs12_to_shadow_sync = true;
 183
 184         return kvm_skip_emulated_instruction(vcpu);
 185 }
 186
 187 static int nested_vmx_fail(struct kvm_vcpu *vcpu, u32 vm_instruction_error)
 188 {
 189         struct vcpu_vmx *vmx = to_vmx(vcpu);
 190
 191         /*
 192          * failValid writes the error number to the current VMCS, which
 193          * can't be done if there isn't a current VMCS.
 194          */
 195         if (vmx->nested.current_vmptr == INVALID_GPA &&
 196             !evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
 197                 return nested_vmx_failInvalid(vcpu);
 198
 199         return nested_vmx_failValid(vcpu, vm_instruction_error);
 200 }
 201
 202 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
 203 {
 204         /* TODO: not to reset guest simply here. */
 205         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 206         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
 207 }
 208
 209 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
 210 {
 211         return fixed_bits_valid(control, low, high);
 212 }
 213
 214 static inline u64 vmx_control_msr(u32 low, u32 high)
 215 {
 216         return low | ((u64)high << 32);
 217 }
 218
 219 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
 220 {
 221         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
 222         vmcs_write64(VMCS_LINK_POINTER, INVALID_GPA);
 223         vmx->nested.need_vmcs12_to_shadow_sync = false;
 224 }
 225
 226 static inline void nested_release_evmcs(struct kvm_vcpu *vcpu)
 227 {
 228         struct vcpu_vmx *vmx = to_vmx(vcpu);
 229
 230         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) {
 231                 kvm_vcpu_unmap(vcpu, &vmx->nested.hv_evmcs_map, true);
 232                 vmx->nested.hv_evmcs = NULL;
 233         }
 234
 235         vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
 236 }
 237
 238 static void vmx_sync_vmcs_host_state(struct vcpu_vmx *vmx,
 239                                      struct loaded_vmcs *prev)
 240 {
 241         struct vmcs_host_state *dest, *src;
 242
 243         if (unlikely(!vmx->guest_state_loaded))
 244                 return;
 245
 246         src = &prev->host_state;
 247         dest = &vmx->loaded_vmcs->host_state;
 248
 249         vmx_set_host_fs_gs(dest, src->fs_sel, src->gs_sel, src->fs_base, src->gs_base);
 250         dest->ldt_sel = src->ldt_sel;
 251 #ifdef CONFIG_X86_64
 252         dest->ds_sel = src->ds_sel;
 253         dest->es_sel = src->es_sel;
 254 #endif
 255 }
 256
 257 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
 258 {
 259         struct vcpu_vmx *vmx = to_vmx(vcpu);
 260         struct loaded_vmcs *prev;
 261         int cpu;
 262
 263         if (WARN_ON_ONCE(vmx->loaded_vmcs == vmcs))
 264                 return;
 265
 266         cpu = get_cpu();
 267         prev = vmx->loaded_vmcs;
 268         vmx->loaded_vmcs = vmcs;
 269         vmx_vcpu_load_vmcs(vcpu, cpu, prev);
 270         vmx_sync_vmcs_host_state(vmx, prev);
 271         put_cpu();
 272
 273         vcpu->arch.regs_avail = ~VMX_REGS_LAZY_LOAD_SET;
 274
 275         /*
 276          * All lazily updated registers will be reloaded from VMCS12 on both
 277          * vmentry and vmexit.
 278          */
 279         vcpu->arch.regs_dirty = 0;
 280 }
 281
 282 /*
 283  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
 284  * just stops using VMX.
 285  */
 286 static void free_nested(struct kvm_vcpu *vcpu)
 287 {
 288         struct vcpu_vmx *vmx = to_vmx(vcpu);
 289
 290         if (WARN_ON_ONCE(vmx->loaded_vmcs != &vmx->vmcs01))
 291                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
 292
 293         if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
 294                 return;
 295
 296         kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu);
 297
 298         vmx->nested.vmxon = false;
 299         vmx->nested.smm.vmxon = false;
 300         vmx->nested.vmxon_ptr = INVALID_GPA;
 301         free_vpid(vmx->nested.vpid02);
 302         vmx->nested.posted_intr_nv = -1;
 303         vmx->nested.current_vmptr = INVALID_GPA;
 304         if (enable_shadow_vmcs) {
 305                 vmx_disable_shadow_vmcs(vmx);
 306                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
 307                 free_vmcs(vmx->vmcs01.shadow_vmcs);
 308                 vmx->vmcs01.shadow_vmcs = NULL;
 309         }
 310         kfree(vmx->nested.cached_vmcs12);
 311         vmx->nested.cached_vmcs12 = NULL;
 312         kfree(vmx->nested.cached_shadow_vmcs12);
 313         vmx->nested.cached_shadow_vmcs12 = NULL;
 314         /*
 315          * Unpin physical memory we referred to in the vmcs02.  The APIC access
 316          * page's backing page (yeah, confusing) shouldn't actually be accessed,
 317          * and if it is written, the contents are irrelevant.
 318          */
 319         kvm_vcpu_unmap(vcpu, &vmx->nested.apic_access_page_map, false);
 320         kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true);
 321         kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true);
 322         vmx->nested.pi_desc = NULL;
 323
 324         kvm_mmu_free_roots(vcpu->kvm, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
 325
 326         nested_release_evmcs(vcpu);
 327
 328         free_loaded_vmcs(&vmx->nested.vmcs02);
 329 }
 330
 331 /*
 332  * Ensure that the current vmcs of the logical processor is the
 333  * vmcs01 of the vcpu before calling free_nested().
 334  */
 335 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu)
 336 {
 337         vcpu_load(vcpu);
 338         vmx_leave_nested(vcpu);
 339         vcpu_put(vcpu);
 340 }
 341
 342 #define EPTP_PA_MASK   GENMASK_ULL(51, 12)
 343
 344 static bool nested_ept_root_matches(hpa_t root_hpa, u64 root_eptp, u64 eptp)
 345 {
 346         return VALID_PAGE(root_hpa) &&
 347                ((root_eptp & EPTP_PA_MASK) == (eptp & EPTP_PA_MASK));
 348 }
 349
 350 static void nested_ept_invalidate_addr(struct kvm_vcpu *vcpu, gpa_t eptp,
 351                                        gpa_t addr)
 352 {
 353         uint i;
 354         struct kvm_mmu_root_info *cached_root;
 355
 356         WARN_ON_ONCE(!mmu_is_nested(vcpu));
 357
 358         for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
 359                 cached_root = &vcpu->arch.mmu->prev_roots[i];
 360
 361                 if (nested_ept_root_matches(cached_root->hpa, cached_root->pgd,
 362                                             eptp))
 363                         vcpu->arch.mmu->invlpg(vcpu, addr, cached_root->hpa);
 364         }
 365 }
 366
 367 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
 368                 struct x86_exception *fault)
 369 {
 370         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 371         struct vcpu_vmx *vmx = to_vmx(vcpu);
 372         u32 vm_exit_reason;
 373         unsigned long exit_qualification = vcpu->arch.exit_qualification;
 374
 375         if (vmx->nested.pml_full) {
 376                 vm_exit_reason = EXIT_REASON_PML_FULL;
 377                 vmx->nested.pml_full = false;
 378                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
 379         } else {
 380                 if (fault->error_code & PFERR_RSVD_MASK)
 381                         vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
 382                 else
 383                         vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
 384
 385                 /*
 386                  * Although the caller (kvm_inject_emulated_page_fault) would
 387                  * have already synced the faulting address in the shadow EPT
 388                  * tables for the current EPTP12, we also need to sync it for
 389                  * any other cached EPTP02s based on the same EP4TA, since the
 390                  * TLB associates mappings to the EP4TA rather than the full EPTP.
 391                  */
 392                 nested_ept_invalidate_addr(vcpu, vmcs12->ept_pointer,
 393                                            fault->address);
 394         }
 395
 396         nested_vmx_vmexit(vcpu, vm_exit_reason, 0, exit_qualification);
 397         vmcs12->guest_physical_address = fault->address;
 398 }
 399
 400 static void nested_ept_new_eptp(struct kvm_vcpu *vcpu)
 401 {
 402         struct vcpu_vmx *vmx = to_vmx(vcpu);
 403         bool execonly = vmx->nested.msrs.ept_caps & VMX_EPT_EXECUTE_ONLY_BIT;
 404         int ept_lpage_level = ept_caps_to_lpage_level(vmx->nested.msrs.ept_caps);
 405
 406         kvm_init_shadow_ept_mmu(vcpu, execonly, ept_lpage_level,
 407                                 nested_ept_ad_enabled(vcpu),
 408                                 nested_ept_get_eptp(vcpu));
 409 }
 410
 411 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
 412 {
 413         WARN_ON(mmu_is_nested(vcpu));
 414
 415         vcpu->arch.mmu = &vcpu->arch.guest_mmu;
 416         nested_ept_new_eptp(vcpu);
 417         vcpu->arch.mmu->get_guest_pgd     = nested_ept_get_eptp;
 418         vcpu->arch.mmu->inject_page_fault = nested_ept_inject_page_fault;
 419         vcpu->arch.mmu->get_pdptr         = kvm_pdptr_read;
 420
 421         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
 422 }
 423
 424 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
 425 {
 426         vcpu->arch.mmu = &vcpu->arch.root_mmu;
 427         vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
 428 }
 429
 430 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
 431                                             u16 error_code)
 432 {
 433         bool inequality, bit;
 434
 435         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
 436         inequality =
 437                 (error_code & vmcs12->page_fault_error_code_mask) !=
 438                  vmcs12->page_fault_error_code_match;
 439         return inequality ^ bit;
 440 }
 441
 442
 443 /*
 444  * KVM wants to inject page-faults which it got to the guest. This function
 445  * checks whether in a nested guest, we need to inject them to L1 or L2.
 446  */
 447 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
 448 {
 449         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 450         unsigned int nr = vcpu->arch.exception.nr;
 451         bool has_payload = vcpu->arch.exception.has_payload;
 452         unsigned long payload = vcpu->arch.exception.payload;
 453
 454         if (nr == PF_VECTOR) {
 455                 if (vcpu->arch.exception.nested_apf) {
 456                         *exit_qual = vcpu->arch.apf.nested_apf_token;
 457                         return 1;
 458                 }
 459                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
 460                                                     vcpu->arch.exception.error_code)) {
 461                         *exit_qual = has_payload ? payload : vcpu->arch.cr2;
 462                         return 1;
 463                 }
 464         } else if (vmcs12->exception_bitmap & (1u << nr)) {
 465                 if (nr == DB_VECTOR) {
 466                         if (!has_payload) {
 467                                 payload = vcpu->arch.dr6;
 468                                 payload &= ~DR6_BT;
 469                                 payload ^= DR6_ACTIVE_LOW;
 470                         }
 471                         *exit_qual = payload;
 472                 } else
 473                         *exit_qual = 0;
 474                 return 1;
 475         }
 476
 477         return 0;
 478 }
 479
 480 static bool nested_vmx_handle_page_fault_workaround(struct kvm_vcpu *vcpu,
 481                                                     struct x86_exception *fault)
 482 {
 483         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 484
 485         WARN_ON(!is_guest_mode(vcpu));
 486
 487         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
 488             !WARN_ON_ONCE(to_vmx(vcpu)->nested.nested_run_pending)) {
 489                 vmcs12->vm_exit_intr_error_code = fault->error_code;
 490                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
 491                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
 492                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
 493                                   fault->address);
 494                 return true;
 495         }
 496         return false;
 497 }
 498
 499 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
 500                                                struct vmcs12 *vmcs12)
 501 {
 502         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
 503                 return 0;
 504
 505         if (CC(!page_address_valid(vcpu, vmcs12->io_bitmap_a)) ||
 506             CC(!page_address_valid(vcpu, vmcs12->io_bitmap_b)))
 507                 return -EINVAL;
 508
 509         return 0;
 510 }
 511
 512 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
 513                                                 struct vmcs12 *vmcs12)
 514 {
 515         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
 516                 return 0;
 517
 518         if (CC(!page_address_valid(vcpu, vmcs12->msr_bitmap)))
 519                 return -EINVAL;
 520
 521         return 0;
 522 }
 523
 524 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
 525                                                 struct vmcs12 *vmcs12)
 526 {
 527         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
 528                 return 0;
 529
 530         if (CC(!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr)))
 531                 return -EINVAL;
 532
 533         return 0;
 534 }
 535
 536 /*
 537  * For x2APIC MSRs, ignore the vmcs01 bitmap.  L1 can enable x2APIC without L1
 538  * itself utilizing x2APIC.  All MSRs were previously set to be intercepted,
 539  * only the "disable intercept" case needs to be handled.
 540  */
 541 static void nested_vmx_disable_intercept_for_x2apic_msr(unsigned long *msr_bitmap_l1,
 542                                                         unsigned long *msr_bitmap_l0,
 543                                                         u32 msr, int type)
 544 {
 545         if (type & MSR_TYPE_R && !vmx_test_msr_bitmap_read(msr_bitmap_l1, msr))
 546                 vmx_clear_msr_bitmap_read(msr_bitmap_l0, msr);
 547
 548         if (type & MSR_TYPE_W && !vmx_test_msr_bitmap_write(msr_bitmap_l1, msr))
 549                 vmx_clear_msr_bitmap_write(msr_bitmap_l0, msr);
 550 }
 551
 552 static inline void enable_x2apic_msr_intercepts(unsigned long *msr_bitmap)
 553 {
 554         int msr;
 555
 556         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
 557                 unsigned word = msr / BITS_PER_LONG;
 558
 559                 msr_bitmap[word] = ~0;
 560                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
 561         }
 562 }
 563
 564 #define BUILD_NVMX_MSR_INTERCEPT_HELPER(rw)                                     \
 565 static inline                                                                   \
 566 void nested_vmx_set_msr_##rw##_intercept(struct vcpu_vmx *vmx,                  \
 567                                          unsigned long *msr_bitmap_l1,          \
 568                                          unsigned long *msr_bitmap_l0, u32 msr) \
 569 {                                                                               \
 570         if (vmx_test_msr_bitmap_##rw(vmx->vmcs01.msr_bitmap, msr) ||            \
 571             vmx_test_msr_bitmap_##rw(msr_bitmap_l1, msr))                       \
 572                 vmx_set_msr_bitmap_##rw(msr_bitmap_l0, msr);                    \
 573         else                                                                    \
 574                 vmx_clear_msr_bitmap_##rw(msr_bitmap_l0, msr);                  \
 575 }
 576 BUILD_NVMX_MSR_INTERCEPT_HELPER(read)
 577 BUILD_NVMX_MSR_INTERCEPT_HELPER(write)
 578
 579 static inline void nested_vmx_set_intercept_for_msr(struct vcpu_vmx *vmx,
 580                                                     unsigned long *msr_bitmap_l1,
 581                                                     unsigned long *msr_bitmap_l0,
 582                                                     u32 msr, int types)
 583 {
 584         if (types & MSR_TYPE_R)
 585                 nested_vmx_set_msr_read_intercept(vmx, msr_bitmap_l1,
 586                                                   msr_bitmap_l0, msr);
 587         if (types & MSR_TYPE_W)
 588                 nested_vmx_set_msr_write_intercept(vmx, msr_bitmap_l1,
 589                                                    msr_bitmap_l0, msr);
 590 }
 591
 592 /*
 593  * Merge L0's and L1's MSR bitmap, return false to indicate that
 594  * we do not use the hardware.
 595  */
 596 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
 597                                                  struct vmcs12 *vmcs12)
 598 {
 599         struct vcpu_vmx *vmx = to_vmx(vcpu);
 600         int msr;
 601         unsigned long *msr_bitmap_l1;
 602         unsigned long *msr_bitmap_l0 = vmx->nested.vmcs02.msr_bitmap;
 603         struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs;
 604         struct kvm_host_map *map = &vmx->nested.msr_bitmap_map;
 605
 606         /* Nothing to do if the MSR bitmap is not in use.  */
 607         if (!cpu_has_vmx_msr_bitmap() ||
 608             !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
 609                 return false;
 610
 611         /*
 612          * MSR bitmap update can be skipped when:
 613          * - MSR bitmap for L1 hasn't changed.
 614          * - Nested hypervisor (L1) is attempting to launch the same L2 as
 615          *   before.
 616          * - Nested hypervisor (L1) has enabled 'Enlightened MSR Bitmap' feature
 617          *   and tells KVM (L0) there were no changes in MSR bitmap for L2.
 618          */
 619         if (!vmx->nested.force_msr_bitmap_recalc && evmcs &&
 620             evmcs->hv_enlightenments_control.msr_bitmap &&
 621             evmcs->hv_clean_fields & HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP)
 622                 return true;
 623
 624         if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->msr_bitmap), map))
 625                 return false;
 626
 627         msr_bitmap_l1 = (unsigned long *)map->hva;
 628
 629         /*
 630          * To keep the control flow simple, pay eight 8-byte writes (sixteen
 631          * 4-byte writes on 32-bit systems) up front to enable intercepts for
 632          * the x2APIC MSR range and selectively toggle those relevant to L2.
 633          */
 634         enable_x2apic_msr_intercepts(msr_bitmap_l0);
 635
 636         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
 637                 if (nested_cpu_has_apic_reg_virt(vmcs12)) {
 638                         /*
 639                          * L0 need not intercept reads for MSRs between 0x800
 640                          * and 0x8ff, it just lets the processor take the value
 641                          * from the virtual-APIC page; take those 256 bits
 642                          * directly from the L1 bitmap.
 643                          */
 644                         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
 645                                 unsigned word = msr / BITS_PER_LONG;
 646
 647                                 msr_bitmap_l0[word] = msr_bitmap_l1[word];
 648                         }
 649                 }
 650
 651                 nested_vmx_disable_intercept_for_x2apic_msr(
 652                         msr_bitmap_l1, msr_bitmap_l0,
 653                         X2APIC_MSR(APIC_TASKPRI),
 654                         MSR_TYPE_R | MSR_TYPE_W);
 655
 656                 if (nested_cpu_has_vid(vmcs12)) {
 657                         nested_vmx_disable_intercept_for_x2apic_msr(
 658                                 msr_bitmap_l1, msr_bitmap_l0,
 659                                 X2APIC_MSR(APIC_EOI),
 660                                 MSR_TYPE_W);
 661                         nested_vmx_disable_intercept_for_x2apic_msr(
 662                                 msr_bitmap_l1, msr_bitmap_l0,
 663                                 X2APIC_MSR(APIC_SELF_IPI),
 664                                 MSR_TYPE_W);
 665                 }
 666         }
 667
 668         /*
 669          * Always check vmcs01's bitmap to honor userspace MSR filters and any
 670          * other runtime changes to vmcs01's bitmap, e.g. dynamic pass-through.
 671          */
 672 #ifdef CONFIG_X86_64
 673         nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
 674                                          MSR_FS_BASE, MSR_TYPE_RW);
 675
 676         nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
 677                                          MSR_GS_BASE, MSR_TYPE_RW);
 678
 679         nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
 680                                          MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
 681 #endif
 682         nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
 683                                          MSR_IA32_SPEC_CTRL, MSR_TYPE_RW);
 684
 685         nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
 686                                          MSR_IA32_PRED_CMD, MSR_TYPE_W);
 687
 688         kvm_vcpu_unmap(vcpu, &vmx->nested.msr_bitmap_map, false);
 689
 690         vmx->nested.force_msr_bitmap_recalc = false;
 691
 692         return true;
 693 }
 694
 695 static void nested_cache_shadow_vmcs12(struct kvm_vcpu *vcpu,
 696                                        struct vmcs12 *vmcs12)
 697 {
 698         struct vcpu_vmx *vmx = to_vmx(vcpu);
 699         struct gfn_to_hva_cache *ghc = &vmx->nested.shadow_vmcs12_cache;
 700
 701         if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
 702             vmcs12->vmcs_link_pointer == INVALID_GPA)
 703                 return;
 704
 705         if (ghc->gpa != vmcs12->vmcs_link_pointer &&
 706             kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc,
 707                                       vmcs12->vmcs_link_pointer, VMCS12_SIZE))
 708                 return;
 709
 710         kvm_read_guest_cached(vmx->vcpu.kvm, ghc, get_shadow_vmcs12(vcpu),
 711                               VMCS12_SIZE);
 712 }
 713
 714 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu *vcpu,
 715                                               struct vmcs12 *vmcs12)
 716 {
 717         struct vcpu_vmx *vmx = to_vmx(vcpu);
 718         struct gfn_to_hva_cache *ghc = &vmx->nested.shadow_vmcs12_cache;
 719
 720         if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
 721             vmcs12->vmcs_link_pointer == INVALID_GPA)
 722                 return;
 723
 724         if (ghc->gpa != vmcs12->vmcs_link_pointer &&
 725             kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc,
 726                                       vmcs12->vmcs_link_pointer, VMCS12_SIZE))
 727                 return;
 728
 729         kvm_write_guest_cached(vmx->vcpu.kvm, ghc, get_shadow_vmcs12(vcpu),
 730                                VMCS12_SIZE);
 731 }
 732
 733 /*
 734  * In nested virtualization, check if L1 has set
 735  * VM_EXIT_ACK_INTR_ON_EXIT
 736  */
 737 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
 738 {
 739         return get_vmcs12(vcpu)->vm_exit_controls &
 740                 VM_EXIT_ACK_INTR_ON_EXIT;
 741 }
 742
 743 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
 744                                           struct vmcs12 *vmcs12)
 745 {
 746         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
 747             CC(!page_address_valid(vcpu, vmcs12->apic_access_addr)))
 748                 return -EINVAL;
 749         else
 750                 return 0;
 751 }
 752
 753 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
 754                                            struct vmcs12 *vmcs12)
 755 {
 756         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
 757             !nested_cpu_has_apic_reg_virt(vmcs12) &&
 758             !nested_cpu_has_vid(vmcs12) &&
 759             !nested_cpu_has_posted_intr(vmcs12))
 760                 return 0;
 761
 762         /*
 763          * If virtualize x2apic mode is enabled,
 764          * virtualize apic access must be disabled.
 765          */
 766         if (CC(nested_cpu_has_virt_x2apic_mode(vmcs12) &&
 767                nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)))
 768                 return -EINVAL;
 769
 770         /*
 771          * If virtual interrupt delivery is enabled,
 772          * we must exit on external interrupts.
 773          */
 774         if (CC(nested_cpu_has_vid(vmcs12) && !nested_exit_on_intr(vcpu)))
 775                 return -EINVAL;
 776
 777         /*
 778          * bits 15:8 should be zero in posted_intr_nv,
 779          * the descriptor address has been already checked
 780          * in nested_get_vmcs12_pages.
 781          *
 782          * bits 5:0 of posted_intr_desc_addr should be zero.
 783          */
 784         if (nested_cpu_has_posted_intr(vmcs12) &&
 785            (CC(!nested_cpu_has_vid(vmcs12)) ||
 786             CC(!nested_exit_intr_ack_set(vcpu)) ||
 787             CC((vmcs12->posted_intr_nv & 0xff00)) ||
 788             CC(!kvm_vcpu_is_legal_aligned_gpa(vcpu, vmcs12->posted_intr_desc_addr, 64))))
 789                 return -EINVAL;
 790
 791         /* tpr shadow is needed by all apicv features. */
 792         if (CC(!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)))
 793                 return -EINVAL;
 794
 795         return 0;
 796 }
 797
 798 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
 799                                        u32 count, u64 addr)
 800 {
 801         if (count == 0)
 802                 return 0;
 803
 804         if (!kvm_vcpu_is_legal_aligned_gpa(vcpu, addr, 16) ||
 805             !kvm_vcpu_is_legal_gpa(vcpu, (addr + count * sizeof(struct vmx_msr_entry) - 1)))
 806                 return -EINVAL;
 807
 808         return 0;
 809 }
 810
 811 static int nested_vmx_check_exit_msr_switch_controls(struct kvm_vcpu *vcpu,
 812                                                      struct vmcs12 *vmcs12)
 813 {
 814         if (CC(nested_vmx_check_msr_switch(vcpu,
 815                                            vmcs12->vm_exit_msr_load_count,
 816                                            vmcs12->vm_exit_msr_load_addr)) ||
 817             CC(nested_vmx_check_msr_switch(vcpu,
 818                                            vmcs12->vm_exit_msr_store_count,
 819                                            vmcs12->vm_exit_msr_store_addr)))
 820                 return -EINVAL;
 821
 822         return 0;
 823 }
 824
 825 static int nested_vmx_check_entry_msr_switch_controls(struct kvm_vcpu *vcpu,
 826                                                       struct vmcs12 *vmcs12)
 827 {
 828         if (CC(nested_vmx_check_msr_switch(vcpu,
 829                                            vmcs12->vm_entry_msr_load_count,
 830                                            vmcs12->vm_entry_msr_load_addr)))
 831                 return -EINVAL;
 832
 833         return 0;
 834 }
 835
 836 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
 837                                          struct vmcs12 *vmcs12)
 838 {
 839         if (!nested_cpu_has_pml(vmcs12))
 840                 return 0;
 841
 842         if (CC(!nested_cpu_has_ept(vmcs12)) ||
 843             CC(!page_address_valid(vcpu, vmcs12->pml_address)))
 844                 return -EINVAL;
 845
 846         return 0;
 847 }
 848
 849 static int nested_vmx_check_unrestricted_guest_controls(struct kvm_vcpu *vcpu,
 850                                                         struct vmcs12 *vmcs12)
 851 {
 852         if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST) &&
 853                !nested_cpu_has_ept(vmcs12)))
 854                 return -EINVAL;
 855         return 0;
 856 }
 857
 858 static int nested_vmx_check_mode_based_ept_exec_controls(struct kvm_vcpu *vcpu,
 859                                                          struct vmcs12 *vmcs12)
 860 {
 861         if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_MODE_BASED_EPT_EXEC) &&
 862                !nested_cpu_has_ept(vmcs12)))
 863                 return -EINVAL;
 864         return 0;
 865 }
 866
 867 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu *vcpu,
 868                                                  struct vmcs12 *vmcs12)
 869 {
 870         if (!nested_cpu_has_shadow_vmcs(vmcs12))
 871                 return 0;
 872
 873         if (CC(!page_address_valid(vcpu, vmcs12->vmread_bitmap)) ||
 874             CC(!page_address_valid(vcpu, vmcs12->vmwrite_bitmap)))
 875                 return -EINVAL;
 876
 877         return 0;
 878 }
 879
 880 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
 881                                        struct vmx_msr_entry *e)
 882 {
 883         /* x2APIC MSR accesses are not allowed */
 884         if (CC(vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8))
 885                 return -EINVAL;
 886         if (CC(e->index == MSR_IA32_UCODE_WRITE) || /* SDM Table 35-2 */
 887             CC(e->index == MSR_IA32_UCODE_REV))
 888                 return -EINVAL;
 889         if (CC(e->reserved != 0))
 890                 return -EINVAL;
 891         return 0;
 892 }
 893
 894 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
 895                                      struct vmx_msr_entry *e)
 896 {
 897         if (CC(e->index == MSR_FS_BASE) ||
 898             CC(e->index == MSR_GS_BASE) ||
 899             CC(e->index == MSR_IA32_SMM_MONITOR_CTL) || /* SMM is not supported */
 900             nested_vmx_msr_check_common(vcpu, e))
 901                 return -EINVAL;
 902         return 0;
 903 }
 904
 905 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
 906                                       struct vmx_msr_entry *e)
 907 {
 908         if (CC(e->index == MSR_IA32_SMBASE) || /* SMM is not supported */
 909             nested_vmx_msr_check_common(vcpu, e))
 910                 return -EINVAL;
 911         return 0;
 912 }
 913
 914 static u32 nested_vmx_max_atomic_switch_msrs(struct kvm_vcpu *vcpu)
 915 {
 916         struct vcpu_vmx *vmx = to_vmx(vcpu);
 917         u64 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
 918                                        vmx->nested.msrs.misc_high);
 919
 920         return (vmx_misc_max_msr(vmx_misc) + 1) * VMX_MISC_MSR_LIST_MULTIPLIER;
 921 }
 922
 923 /*
 924  * Load guest's/host's msr at nested entry/exit.
 925  * return 0 for success, entry index for failure.
 926  *
 927  * One of the failure modes for MSR load/store is when a list exceeds the
 928  * virtual hardware's capacity. To maintain compatibility with hardware inasmuch
 929  * as possible, process all valid entries before failing rather than precheck
 930  * for a capacity violation.
 931  */
 932 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
 933 {
 934         u32 i;
 935         struct vmx_msr_entry e;
 936         u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu);
 937
 938         for (i = 0; i < count; i++) {
 939                 if (unlikely(i >= max_msr_list_size))
 940                         goto fail;
 941
 942                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
 943                                         &e, sizeof(e))) {
 944                         pr_debug_ratelimited(
 945                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
 946                                 __func__, i, gpa + i * sizeof(e));
 947                         goto fail;
 948                 }
 949                 if (nested_vmx_load_msr_check(vcpu, &e)) {
 950                         pr_debug_ratelimited(
 951                                 "%s check failed (%u, 0x%x, 0x%x)\n",
 952                                 __func__, i, e.index, e.reserved);
 953                         goto fail;
 954                 }
 955                 if (kvm_set_msr(vcpu, e.index, e.value)) {
 956                         pr_debug_ratelimited(
 957                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
 958                                 __func__, i, e.index, e.value);
 959                         goto fail;
 960                 }
 961         }
 962         return 0;
 963 fail:
 964         /* Note, max_msr_list_size is at most 4096, i.e. this can't wrap. */
 965         return i + 1;
 966 }
 967
 968 static bool nested_vmx_get_vmexit_msr_value(struct kvm_vcpu *vcpu,
 969                                             u32 msr_index,
 970                                             u64 *data)
 971 {
 972         struct vcpu_vmx *vmx = to_vmx(vcpu);
 973
 974         /*
 975          * If the L0 hypervisor stored a more accurate value for the TSC that
 976          * does not include the time taken for emulation of the L2->L1
 977          * VM-exit in L0, use the more accurate value.
 978          */
 979         if (msr_index == MSR_IA32_TSC) {
 980                 int i = vmx_find_loadstore_msr_slot(&vmx->msr_autostore.guest,
 981                                                     MSR_IA32_TSC);
 982
 983                 if (i >= 0) {
 984                         u64 val = vmx->msr_autostore.guest.val[i].value;
 985
 986                         *data = kvm_read_l1_tsc(vcpu, val);
 987                         return true;
 988                 }
 989         }
 990
 991         if (kvm_get_msr(vcpu, msr_index, data)) {
 992                 pr_debug_ratelimited("%s cannot read MSR (0x%x)\n", __func__,
 993                         msr_index);
 994                 return false;
 995         }
 996         return true;
 997 }
 998
 999 static bool read_and_check_msr_entry(struct kvm_vcpu *vcpu, u64 gpa, int i,
1000                                      struct vmx_msr_entry *e)
1001 {
1002         if (kvm_vcpu_read_guest(vcpu,
1003                                 gpa + i * sizeof(*e),
1004                                 e, 2 * sizeof(u32))) {
1005                 pr_debug_ratelimited(
1006                         "%s cannot read MSR entry (%u, 0x%08llx)\n",
1007                         __func__, i, gpa + i * sizeof(*e));
1008                 return false;
1009         }
1010         if (nested_vmx_store_msr_check(vcpu, e)) {
1011                 pr_debug_ratelimited(
1012                         "%s check failed (%u, 0x%x, 0x%x)\n",
1013                         __func__, i, e->index, e->reserved);
1014                 return false;
1015         }
1016         return true;
1017 }
1018
1019 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
1020 {
1021         u64 data;
1022         u32 i;
1023         struct vmx_msr_entry e;
1024         u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu);
1025
1026         for (i = 0; i < count; i++) {
1027                 if (unlikely(i >= max_msr_list_size))
1028                         return -EINVAL;
1029
1030                 if (!read_and_check_msr_entry(vcpu, gpa, i, &e))
1031                         return -EINVAL;
1032
1033                 if (!nested_vmx_get_vmexit_msr_value(vcpu, e.index, &data))
1034                         return -EINVAL;
1035
1036                 if (kvm_vcpu_write_guest(vcpu,
1037                                          gpa + i * sizeof(e) +
1038                                              offsetof(struct vmx_msr_entry, value),
1039                                          &data, sizeof(data))) {
1040                         pr_debug_ratelimited(
1041                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
1042                                 __func__, i, e.index, data);
1043                         return -EINVAL;
1044                 }
1045         }
1046         return 0;
1047 }
1048
1049 static bool nested_msr_store_list_has_msr(struct kvm_vcpu *vcpu, u32 msr_index)
1050 {
1051         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1052         u32 count = vmcs12->vm_exit_msr_store_count;
1053         u64 gpa = vmcs12->vm_exit_msr_store_addr;
1054         struct vmx_msr_entry e;
1055         u32 i;
1056
1057         for (i = 0; i < count; i++) {
1058                 if (!read_and_check_msr_entry(vcpu, gpa, i, &e))
1059                         return false;
1060
1061                 if (e.index == msr_index)
1062                         return true;
1063         }
1064         return false;
1065 }
1066
1067 static void prepare_vmx_msr_autostore_list(struct kvm_vcpu *vcpu,
1068                                            u32 msr_index)
1069 {
1070         struct vcpu_vmx *vmx = to_vmx(vcpu);
1071         struct vmx_msrs *autostore = &vmx->msr_autostore.guest;
1072         bool in_vmcs12_store_list;
1073         int msr_autostore_slot;
1074         bool in_autostore_list;
1075         int last;
1076
1077         msr_autostore_slot = vmx_find_loadstore_msr_slot(autostore, msr_index);
1078         in_autostore_list = msr_autostore_slot >= 0;
1079         in_vmcs12_store_list = nested_msr_store_list_has_msr(vcpu, msr_index);
1080
1081         if (in_vmcs12_store_list && !in_autostore_list) {
1082                 if (autostore->nr == MAX_NR_LOADSTORE_MSRS) {
1083                         /*
1084                          * Emulated VMEntry does not fail here.  Instead a less
1085                          * accurate value will be returned by
1086                          * nested_vmx_get_vmexit_msr_value() using kvm_get_msr()
1087                          * instead of reading the value from the vmcs02 VMExit
1088                          * MSR-store area.
1089                          */
1090                         pr_warn_ratelimited(
1091                                 "Not enough msr entries in msr_autostore.  Can't add msr %x\n",
1092                                 msr_index);
1093                         return;
1094                 }
1095                 last = autostore->nr++;
1096                 autostore->val[last].index = msr_index;
1097         } else if (!in_vmcs12_store_list && in_autostore_list) {
1098                 last = --autostore->nr;
1099                 autostore->val[msr_autostore_slot] = autostore->val[last];
1100         }
1101 }
1102
1103 /*
1104  * Load guest's/host's cr3 at nested entry/exit.  @nested_ept is true if we are
1105  * emulating VM-Entry into a guest with EPT enabled.  On failure, the expected
1106  * Exit Qualification (for a VM-Entry consistency check VM-Exit) is assigned to
1107  * @entry_failure_code.
1108  */
1109 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3,
1110                                bool nested_ept, bool reload_pdptrs,
1111                                enum vm_entry_failure_code *entry_failure_code)
1112 {
1113         if (CC(kvm_vcpu_is_illegal_gpa(vcpu, cr3))) {
1114                 *entry_failure_code = ENTRY_FAIL_DEFAULT;
1115                 return -EINVAL;
1116         }
1117
1118         /*
1119          * If PAE paging and EPT are both on, CR3 is not used by the CPU and
1120          * must not be dereferenced.
1121          */
1122         if (reload_pdptrs && !nested_ept && is_pae_paging(vcpu) &&
1123             CC(!load_pdptrs(vcpu, cr3))) {
1124                 *entry_failure_code = ENTRY_FAIL_PDPTE;
1125                 return -EINVAL;
1126         }
1127
1128         vcpu->arch.cr3 = cr3;
1129         kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1130
1131         /* Re-initialize the MMU, e.g. to pick up CR4 MMU role changes. */
1132         kvm_init_mmu(vcpu);
1133
1134         if (!nested_ept)
1135                 kvm_mmu_new_pgd(vcpu, cr3);
1136
1137         return 0;
1138 }
1139
1140 /*
1141  * Returns if KVM is able to config CPU to tag TLB entries
1142  * populated by L2 differently than TLB entries populated
1143  * by L1.
1144  *
1145  * If L0 uses EPT, L1 and L2 run with different EPTP because
1146  * guest_mode is part of kvm_mmu_page_role. Thus, TLB entries
1147  * are tagged with different EPTP.
1148  *
1149  * If L1 uses VPID and we allocated a vpid02, TLB entries are tagged
1150  * with different VPID (L1 entries are tagged with vmx->vpid
1151  * while L2 entries are tagged with vmx->nested.vpid02).
1152  */
1153 static bool nested_has_guest_tlb_tag(struct kvm_vcpu *vcpu)
1154 {
1155         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1156
1157         return enable_ept ||
1158                (nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02);
1159 }
1160
1161 static void nested_vmx_transition_tlb_flush(struct kvm_vcpu *vcpu,
1162                                             struct vmcs12 *vmcs12,
1163                                             bool is_vmenter)
1164 {
1165         struct vcpu_vmx *vmx = to_vmx(vcpu);
1166
1167         /*
1168          * If vmcs12 doesn't use VPID, L1 expects linear and combined mappings
1169          * for *all* contexts to be flushed on VM-Enter/VM-Exit, i.e. it's a
1170          * full TLB flush from the guest's perspective.  This is required even
1171          * if VPID is disabled in the host as KVM may need to synchronize the
1172          * MMU in response to the guest TLB flush.
1173          *
1174          * Note, using TLB_FLUSH_GUEST is correct even if nested EPT is in use.
1175          * EPT is a special snowflake, as guest-physical mappings aren't
1176          * flushed on VPID invalidations, including VM-Enter or VM-Exit with
1177          * VPID disabled.  As a result, KVM _never_ needs to sync nEPT
1178          * entries on VM-Enter because L1 can't rely on VM-Enter to flush
1179          * those mappings.
1180          */
1181         if (!nested_cpu_has_vpid(vmcs12)) {
1182                 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1183                 return;
1184         }
1185
1186         /* L2 should never have a VPID if VPID is disabled. */
1187         WARN_ON(!enable_vpid);
1188
1189         /*
1190          * VPID is enabled and in use by vmcs12.  If vpid12 is changing, then
1191          * emulate a guest TLB flush as KVM does not track vpid12 history nor
1192          * is the VPID incorporated into the MMU context.  I.e. KVM must assume
1193          * that the new vpid12 has never been used and thus represents a new
1194          * guest ASID that cannot have entries in the TLB.
1195          */
1196         if (is_vmenter && vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
1197                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
1198                 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1199                 return;
1200         }
1201
1202         /*
1203          * If VPID is enabled, used by vmc12, and vpid12 is not changing but
1204          * does not have a unique TLB tag (ASID), i.e. EPT is disabled and
1205          * KVM was unable to allocate a VPID for L2, flush the current context
1206          * as the effective ASID is common to both L1 and L2.
1207          */
1208         if (!nested_has_guest_tlb_tag(vcpu))
1209                 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1210 }
1211
1212 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
1213 {
1214         superset &= mask;
1215         subset &= mask;
1216
1217         return (superset | subset) == superset;
1218 }
1219
1220 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
1221 {
1222         const u64 feature_and_reserved =
1223                 /* feature (except bit 48; see below) */
1224                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
1225                 /* reserved */
1226                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
1227         u64 vmx_basic = vmx->nested.msrs.basic;
1228
1229         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
1230                 return -EINVAL;
1231
1232         /*
1233          * KVM does not emulate a version of VMX that constrains physical
1234          * addresses of VMX structures (e.g. VMCS) to 32-bits.
1235          */
1236         if (data & BIT_ULL(48))
1237                 return -EINVAL;
1238
1239         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
1240             vmx_basic_vmcs_revision_id(data))
1241                 return -EINVAL;
1242
1243         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
1244                 return -EINVAL;
1245
1246         vmx->nested.msrs.basic = data;
1247         return 0;
1248 }
1249
1250 static int
1251 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
1252 {
1253         u64 supported;
1254         u32 *lowp, *highp;
1255
1256         switch (msr_index) {
1257         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1258                 lowp = &vmx->nested.msrs.pinbased_ctls_low;
1259                 highp = &vmx->nested.msrs.pinbased_ctls_high;
1260                 break;
1261         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1262                 lowp = &vmx->nested.msrs.procbased_ctls_low;
1263                 highp = &vmx->nested.msrs.procbased_ctls_high;
1264                 break;
1265         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1266                 lowp = &vmx->nested.msrs.exit_ctls_low;
1267                 highp = &vmx->nested.msrs.exit_ctls_high;
1268                 break;
1269         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1270                 lowp = &vmx->nested.msrs.entry_ctls_low;
1271                 highp = &vmx->nested.msrs.entry_ctls_high;
1272                 break;
1273         case MSR_IA32_VMX_PROCBASED_CTLS2:
1274                 lowp = &vmx->nested.msrs.secondary_ctls_low;
1275                 highp = &vmx->nested.msrs.secondary_ctls_high;
1276                 break;
1277         default:
1278                 BUG();
1279         }
1280
1281         supported = vmx_control_msr(*lowp, *highp);
1282
1283         /* Check must-be-1 bits are still 1. */
1284         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
1285                 return -EINVAL;
1286
1287         /* Check must-be-0 bits are still 0. */
1288         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
1289                 return -EINVAL;
1290
1291         *lowp = data;
1292         *highp = data >> 32;
1293         return 0;
1294 }
1295
1296 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
1297 {
1298         const u64 feature_and_reserved_bits =
1299                 /* feature */
1300                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
1301                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
1302                 /* reserved */
1303                 GENMASK_ULL(13, 9) | BIT_ULL(31);
1304         u64 vmx_misc;
1305
1306         vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
1307                                    vmx->nested.msrs.misc_high);
1308
1309         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
1310                 return -EINVAL;
1311
1312         if ((vmx->nested.msrs.pinbased_ctls_high &
1313              PIN_BASED_VMX_PREEMPTION_TIMER) &&
1314             vmx_misc_preemption_timer_rate(data) !=
1315             vmx_misc_preemption_timer_rate(vmx_misc))
1316                 return -EINVAL;
1317
1318         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
1319                 return -EINVAL;
1320
1321         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
1322                 return -EINVAL;
1323
1324         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
1325                 return -EINVAL;
1326
1327         vmx->nested.msrs.misc_low = data;
1328         vmx->nested.msrs.misc_high = data >> 32;
1329
1330         return 0;
1331 }
1332
1333 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
1334 {
1335         u64 vmx_ept_vpid_cap;
1336
1337         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
1338                                            vmx->nested.msrs.vpid_caps);
1339
1340         /* Every bit is either reserved or a feature bit. */
1341         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
1342                 return -EINVAL;
1343
1344         vmx->nested.msrs.ept_caps = data;
1345         vmx->nested.msrs.vpid_caps = data >> 32;
1346         return 0;
1347 }
1348
1349 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
1350 {
1351         u64 *msr;
1352
1353         switch (msr_index) {
1354         case MSR_IA32_VMX_CR0_FIXED0:
1355                 msr = &vmx->nested.msrs.cr0_fixed0;
1356                 break;
1357         case MSR_IA32_VMX_CR4_FIXED0:
1358                 msr = &vmx->nested.msrs.cr4_fixed0;
1359                 break;
1360         default:
1361                 BUG();
1362         }
1363
1364         /*
1365          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
1366          * must be 1 in the restored value.
1367          */
1368         if (!is_bitwise_subset(data, *msr, -1ULL))
1369                 return -EINVAL;
1370
1371         *msr = data;
1372         return 0;
1373 }
1374
1375 /*
1376  * Called when userspace is restoring VMX MSRs.
1377  *
1378  * Returns 0 on success, non-0 otherwise.
1379  */
1380 int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1381 {
1382         struct vcpu_vmx *vmx = to_vmx(vcpu);
1383
1384         /*
1385          * Don't allow changes to the VMX capability MSRs while the vCPU
1386          * is in VMX operation.
1387          */
1388         if (vmx->nested.vmxon)
1389                 return -EBUSY;
1390
1391         switch (msr_index) {
1392         case MSR_IA32_VMX_BASIC:
1393                 return vmx_restore_vmx_basic(vmx, data);
1394         case MSR_IA32_VMX_PINBASED_CTLS:
1395         case MSR_IA32_VMX_PROCBASED_CTLS:
1396         case MSR_IA32_VMX_EXIT_CTLS:
1397         case MSR_IA32_VMX_ENTRY_CTLS:
1398                 /*
1399                  * The "non-true" VMX capability MSRs are generated from the
1400                  * "true" MSRs, so we do not support restoring them directly.
1401                  *
1402                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
1403                  * should restore the "true" MSRs with the must-be-1 bits
1404                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
1405                  * DEFAULT SETTINGS".
1406                  */
1407                 return -EINVAL;
1408         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1409         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1410         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1411         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1412         case MSR_IA32_VMX_PROCBASED_CTLS2:
1413                 return vmx_restore_control_msr(vmx, msr_index, data);
1414         case MSR_IA32_VMX_MISC:
1415                 return vmx_restore_vmx_misc(vmx, data);
1416         case MSR_IA32_VMX_CR0_FIXED0:
1417         case MSR_IA32_VMX_CR4_FIXED0:
1418                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
1419         case MSR_IA32_VMX_CR0_FIXED1:
1420         case MSR_IA32_VMX_CR4_FIXED1:
1421                 /*
1422                  * These MSRs are generated based on the vCPU's CPUID, so we
1423                  * do not support restoring them directly.
1424                  */
1425                 return -EINVAL;
1426         case MSR_IA32_VMX_EPT_VPID_CAP:
1427                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
1428         case MSR_IA32_VMX_VMCS_ENUM:
1429                 vmx->nested.msrs.vmcs_enum = data;
1430                 return 0;
1431         case MSR_IA32_VMX_VMFUNC:
1432                 if (data & ~vmx->nested.msrs.vmfunc_controls)
1433                         return -EINVAL;
1434                 vmx->nested.msrs.vmfunc_controls = data;
1435                 return 0;
1436         default:
1437                 /*
1438                  * The rest of the VMX capability MSRs do not support restore.
1439                  */
1440                 return -EINVAL;
1441         }
1442 }
1443
1444 /* Returns 0 on success, non-0 otherwise. */
1445 int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
1446 {
1447         switch (msr_index) {
1448         case MSR_IA32_VMX_BASIC:
1449                 *pdata = msrs->basic;
1450                 break;
1451         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1452         case MSR_IA32_VMX_PINBASED_CTLS:
1453                 *pdata = vmx_control_msr(
1454                         msrs->pinbased_ctls_low,
1455                         msrs->pinbased_ctls_high);
1456                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
1457                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
1458                 break;
1459         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1460         case MSR_IA32_VMX_PROCBASED_CTLS:
1461                 *pdata = vmx_control_msr(
1462                         msrs->procbased_ctls_low,
1463                         msrs->procbased_ctls_high);
1464                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
1465                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
1466                 break;
1467         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1468         case MSR_IA32_VMX_EXIT_CTLS:
1469                 *pdata = vmx_control_msr(
1470                         msrs->exit_ctls_low,
1471                         msrs->exit_ctls_high);
1472                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
1473                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
1474                 break;
1475         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1476         case MSR_IA32_VMX_ENTRY_CTLS:
1477                 *pdata = vmx_control_msr(
1478                         msrs->entry_ctls_low,
1479                         msrs->entry_ctls_high);
1480                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
1481                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
1482                 break;
1483         case MSR_IA32_VMX_MISC:
1484                 *pdata = vmx_control_msr(
1485                         msrs->misc_low,
1486                         msrs->misc_high);
1487                 break;
1488         case MSR_IA32_VMX_CR0_FIXED0:
1489                 *pdata = msrs->cr0_fixed0;
1490                 break;
1491         case MSR_IA32_VMX_CR0_FIXED1:
1492                 *pdata = msrs->cr0_fixed1;
1493                 break;
1494         case MSR_IA32_VMX_CR4_FIXED0:
1495                 *pdata = msrs->cr4_fixed0;
1496                 break;
1497         case MSR_IA32_VMX_CR4_FIXED1:
1498                 *pdata = msrs->cr4_fixed1;
1499                 break;
1500         case MSR_IA32_VMX_VMCS_ENUM:
1501                 *pdata = msrs->vmcs_enum;
1502                 break;
1503         case MSR_IA32_VMX_PROCBASED_CTLS2:
1504                 *pdata = vmx_control_msr(
1505                         msrs->secondary_ctls_low,
1506                         msrs->secondary_ctls_high);
1507                 break;
1508         case MSR_IA32_VMX_EPT_VPID_CAP:
1509                 *pdata = msrs->ept_caps |
1510                         ((u64)msrs->vpid_caps << 32);
1511                 break;
1512         case MSR_IA32_VMX_VMFUNC:
1513                 *pdata = msrs->vmfunc_controls;
1514                 break;
1515         default:
1516                 return 1;
1517         }
1518
1519         return 0;
1520 }
1521
1522 /*
1523  * Copy the writable VMCS shadow fields back to the VMCS12, in case they have
1524  * been modified by the L1 guest.  Note, "writable" in this context means
1525  * "writable by the guest", i.e. tagged SHADOW_FIELD_RW; the set of
1526  * fields tagged SHADOW_FIELD_RO may or may not align with the "read-only"
1527  * VM-exit information fields (which are actually writable if the vCPU is
1528  * configured to support "VMWRITE to any supported field in the VMCS").
1529  */
1530 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
1531 {
1532         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
1533         struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu);
1534         struct shadow_vmcs_field field;
1535         unsigned long val;
1536         int i;
1537
1538         if (WARN_ON(!shadow_vmcs))
1539                 return;
1540
1541         preempt_disable();
1542
1543         vmcs_load(shadow_vmcs);
1544
1545         for (i = 0; i < max_shadow_read_write_fields; i++) {
1546                 field = shadow_read_write_fields[i];
1547                 val = __vmcs_readl(field.encoding);
1548                 vmcs12_write_any(vmcs12, field.encoding, field.offset, val);
1549         }
1550
1551         vmcs_clear(shadow_vmcs);
1552         vmcs_load(vmx->loaded_vmcs->vmcs);
1553
1554         preempt_enable();
1555 }
1556
1557 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
1558 {
1559         const struct shadow_vmcs_field *fields[] = {
1560                 shadow_read_write_fields,
1561                 shadow_read_only_fields
1562         };
1563         const int max_fields[] = {
1564                 max_shadow_read_write_fields,
1565                 max_shadow_read_only_fields
1566         };
1567         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
1568         struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu);
1569         struct shadow_vmcs_field field;
1570         unsigned long val;
1571         int i, q;
1572
1573         if (WARN_ON(!shadow_vmcs))
1574                 return;
1575
1576         vmcs_load(shadow_vmcs);
1577
1578         for (q = 0; q < ARRAY_SIZE(fields); q++) {
1579                 for (i = 0; i < max_fields[q]; i++) {
1580                         field = fields[q][i];
1581                         val = vmcs12_read_any(vmcs12, field.encoding,
1582                                               field.offset);
1583                         __vmcs_writel(field.encoding, val);
1584                 }
1585         }
1586
1587         vmcs_clear(shadow_vmcs);
1588         vmcs_load(vmx->loaded_vmcs->vmcs);
1589 }
1590
1591 static void copy_enlightened_to_vmcs12(struct vcpu_vmx *vmx, u32 hv_clean_fields)
1592 {
1593         struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12;
1594         struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs;
1595
1596         /* HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE */
1597         vmcs12->tpr_threshold = evmcs->tpr_threshold;
1598         vmcs12->guest_rip = evmcs->guest_rip;
1599
1600         if (unlikely(!(hv_clean_fields &
1601                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC))) {
1602                 vmcs12->guest_rsp = evmcs->guest_rsp;
1603                 vmcs12->guest_rflags = evmcs->guest_rflags;
1604                 vmcs12->guest_interruptibility_info =
1605                         evmcs->guest_interruptibility_info;
1606         }
1607
1608         if (unlikely(!(hv_clean_fields &
1609                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC))) {
1610                 vmcs12->cpu_based_vm_exec_control =
1611                         evmcs->cpu_based_vm_exec_control;
1612         }
1613
1614         if (unlikely(!(hv_clean_fields &
1615                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN))) {
1616                 vmcs12->exception_bitmap = evmcs->exception_bitmap;
1617         }
1618
1619         if (unlikely(!(hv_clean_fields &
1620                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY))) {
1621                 vmcs12->vm_entry_controls = evmcs->vm_entry_controls;
1622         }
1623
1624         if (unlikely(!(hv_clean_fields &
1625                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT))) {
1626                 vmcs12->vm_entry_intr_info_field =
1627                         evmcs->vm_entry_intr_info_field;
1628                 vmcs12->vm_entry_exception_error_code =
1629                         evmcs->vm_entry_exception_error_code;
1630                 vmcs12->vm_entry_instruction_len =
1631                         evmcs->vm_entry_instruction_len;
1632         }
1633
1634         if (unlikely(!(hv_clean_fields &
1635                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1))) {
1636                 vmcs12->host_ia32_pat = evmcs->host_ia32_pat;
1637                 vmcs12->host_ia32_efer = evmcs->host_ia32_efer;
1638                 vmcs12->host_cr0 = evmcs->host_cr0;
1639                 vmcs12->host_cr3 = evmcs->host_cr3;
1640                 vmcs12->host_cr4 = evmcs->host_cr4;
1641                 vmcs12->host_ia32_sysenter_esp = evmcs->host_ia32_sysenter_esp;
1642                 vmcs12->host_ia32_sysenter_eip = evmcs->host_ia32_sysenter_eip;
1643                 vmcs12->host_rip = evmcs->host_rip;
1644                 vmcs12->host_ia32_sysenter_cs = evmcs->host_ia32_sysenter_cs;
1645                 vmcs12->host_es_selector = evmcs->host_es_selector;
1646                 vmcs12->host_cs_selector = evmcs->host_cs_selector;
1647                 vmcs12->host_ss_selector = evmcs->host_ss_selector;
1648                 vmcs12->host_ds_selector = evmcs->host_ds_selector;
1649                 vmcs12->host_fs_selector = evmcs->host_fs_selector;
1650                 vmcs12->host_gs_selector = evmcs->host_gs_selector;
1651                 vmcs12->host_tr_selector = evmcs->host_tr_selector;
1652         }
1653
1654         if (unlikely(!(hv_clean_fields &
1655                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1))) {
1656                 vmcs12->pin_based_vm_exec_control =
1657                         evmcs->pin_based_vm_exec_control;
1658                 vmcs12->vm_exit_controls = evmcs->vm_exit_controls;
1659                 vmcs12->secondary_vm_exec_control =
1660                         evmcs->secondary_vm_exec_control;
1661         }
1662
1663         if (unlikely(!(hv_clean_fields &
1664                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP))) {
1665                 vmcs12->io_bitmap_a = evmcs->io_bitmap_a;
1666                 vmcs12->io_bitmap_b = evmcs->io_bitmap_b;
1667         }
1668
1669         if (unlikely(!(hv_clean_fields &
1670                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP))) {
1671                 vmcs12->msr_bitmap = evmcs->msr_bitmap;
1672         }
1673
1674         if (unlikely(!(hv_clean_fields &
1675                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2))) {
1676                 vmcs12->guest_es_base = evmcs->guest_es_base;
1677                 vmcs12->guest_cs_base = evmcs->guest_cs_base;
1678                 vmcs12->guest_ss_base = evmcs->guest_ss_base;
1679                 vmcs12->guest_ds_base = evmcs->guest_ds_base;
1680                 vmcs12->guest_fs_base = evmcs->guest_fs_base;
1681                 vmcs12->guest_gs_base = evmcs->guest_gs_base;
1682                 vmcs12->guest_ldtr_base = evmcs->guest_ldtr_base;
1683                 vmcs12->guest_tr_base = evmcs->guest_tr_base;
1684                 vmcs12->guest_gdtr_base = evmcs->guest_gdtr_base;
1685                 vmcs12->guest_idtr_base = evmcs->guest_idtr_base;
1686                 vmcs12->guest_es_limit = evmcs->guest_es_limit;
1687                 vmcs12->guest_cs_limit = evmcs->guest_cs_limit;
1688                 vmcs12->guest_ss_limit = evmcs->guest_ss_limit;
1689                 vmcs12->guest_ds_limit = evmcs->guest_ds_limit;
1690                 vmcs12->guest_fs_limit = evmcs->guest_fs_limit;
1691                 vmcs12->guest_gs_limit = evmcs->guest_gs_limit;
1692                 vmcs12->guest_ldtr_limit = evmcs->guest_ldtr_limit;
1693                 vmcs12->guest_tr_limit = evmcs->guest_tr_limit;
1694                 vmcs12->guest_gdtr_limit = evmcs->guest_gdtr_limit;
1695                 vmcs12->guest_idtr_limit = evmcs->guest_idtr_limit;
1696                 vmcs12->guest_es_ar_bytes = evmcs->guest_es_ar_bytes;
1697                 vmcs12->guest_cs_ar_bytes = evmcs->guest_cs_ar_bytes;
1698                 vmcs12->guest_ss_ar_bytes = evmcs->guest_ss_ar_bytes;
1699                 vmcs12->guest_ds_ar_bytes = evmcs->guest_ds_ar_bytes;
1700                 vmcs12->guest_fs_ar_bytes = evmcs->guest_fs_ar_bytes;
1701                 vmcs12->guest_gs_ar_bytes = evmcs->guest_gs_ar_bytes;
1702                 vmcs12->guest_ldtr_ar_bytes = evmcs->guest_ldtr_ar_bytes;
1703                 vmcs12->guest_tr_ar_bytes = evmcs->guest_tr_ar_bytes;
1704                 vmcs12->guest_es_selector = evmcs->guest_es_selector;
1705                 vmcs12->guest_cs_selector = evmcs->guest_cs_selector;
1706                 vmcs12->guest_ss_selector = evmcs->guest_ss_selector;
1707                 vmcs12->guest_ds_selector = evmcs->guest_ds_selector;
1708                 vmcs12->guest_fs_selector = evmcs->guest_fs_selector;
1709                 vmcs12->guest_gs_selector = evmcs->guest_gs_selector;
1710                 vmcs12->guest_ldtr_selector = evmcs->guest_ldtr_selector;
1711                 vmcs12->guest_tr_selector = evmcs->guest_tr_selector;
1712         }
1713
1714         if (unlikely(!(hv_clean_fields &
1715                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2))) {
1716                 vmcs12->tsc_offset = evmcs->tsc_offset;
1717                 vmcs12->virtual_apic_page_addr = evmcs->virtual_apic_page_addr;
1718                 vmcs12->xss_exit_bitmap = evmcs->xss_exit_bitmap;
1719         }
1720
1721         if (unlikely(!(hv_clean_fields &
1722                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR))) {
1723                 vmcs12->cr0_guest_host_mask = evmcs->cr0_guest_host_mask;
1724                 vmcs12->cr4_guest_host_mask = evmcs->cr4_guest_host_mask;
1725                 vmcs12->cr0_read_shadow = evmcs->cr0_read_shadow;
1726                 vmcs12->cr4_read_shadow = evmcs->cr4_read_shadow;
1727                 vmcs12->guest_cr0 = evmcs->guest_cr0;
1728                 vmcs12->guest_cr3 = evmcs->guest_cr3;
1729                 vmcs12->guest_cr4 = evmcs->guest_cr4;
1730                 vmcs12->guest_dr7 = evmcs->guest_dr7;
1731         }
1732
1733         if (unlikely(!(hv_clean_fields &
1734                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER))) {
1735                 vmcs12->host_fs_base = evmcs->host_fs_base;
1736                 vmcs12->host_gs_base = evmcs->host_gs_base;
1737                 vmcs12->host_tr_base = evmcs->host_tr_base;
1738                 vmcs12->host_gdtr_base = evmcs->host_gdtr_base;
1739                 vmcs12->host_idtr_base = evmcs->host_idtr_base;
1740                 vmcs12->host_rsp = evmcs->host_rsp;
1741         }
1742
1743         if (unlikely(!(hv_clean_fields &
1744                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT))) {
1745                 vmcs12->ept_pointer = evmcs->ept_pointer;
1746                 vmcs12->virtual_processor_id = evmcs->virtual_processor_id;
1747         }
1748
1749         if (unlikely(!(hv_clean_fields &
1750                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1))) {
1751                 vmcs12->vmcs_link_pointer = evmcs->vmcs_link_pointer;
1752                 vmcs12->guest_ia32_debugctl = evmcs->guest_ia32_debugctl;
1753                 vmcs12->guest_ia32_pat = evmcs->guest_ia32_pat;
1754                 vmcs12->guest_ia32_efer = evmcs->guest_ia32_efer;
1755                 vmcs12->guest_pdptr0 = evmcs->guest_pdptr0;
1756                 vmcs12->guest_pdptr1 = evmcs->guest_pdptr1;
1757                 vmcs12->guest_pdptr2 = evmcs->guest_pdptr2;
1758                 vmcs12->guest_pdptr3 = evmcs->guest_pdptr3;
1759                 vmcs12->guest_pending_dbg_exceptions =
1760                         evmcs->guest_pending_dbg_exceptions;
1761                 vmcs12->guest_sysenter_esp = evmcs->guest_sysenter_esp;
1762                 vmcs12->guest_sysenter_eip = evmcs->guest_sysenter_eip;
1763                 vmcs12->guest_bndcfgs = evmcs->guest_bndcfgs;
1764                 vmcs12->guest_activity_state = evmcs->guest_activity_state;
1765                 vmcs12->guest_sysenter_cs = evmcs->guest_sysenter_cs;
1766         }
1767
1768         /*
1769          * Not used?
1770          * vmcs12->vm_exit_msr_store_addr = evmcs->vm_exit_msr_store_addr;
1771          * vmcs12->vm_exit_msr_load_addr = evmcs->vm_exit_msr_load_addr;
1772          * vmcs12->vm_entry_msr_load_addr = evmcs->vm_entry_msr_load_addr;
1773          * vmcs12->page_fault_error_code_mask =
1774          *              evmcs->page_fault_error_code_mask;
1775          * vmcs12->page_fault_error_code_match =
1776          *              evmcs->page_fault_error_code_match;
1777          * vmcs12->cr3_target_count = evmcs->cr3_target_count;
1778          * vmcs12->vm_exit_msr_store_count = evmcs->vm_exit_msr_store_count;
1779          * vmcs12->vm_exit_msr_load_count = evmcs->vm_exit_msr_load_count;
1780          * vmcs12->vm_entry_msr_load_count = evmcs->vm_entry_msr_load_count;
1781          */
1782
1783         /*
1784          * Read only fields:
1785          * vmcs12->guest_physical_address = evmcs->guest_physical_address;
1786          * vmcs12->vm_instruction_error = evmcs->vm_instruction_error;
1787          * vmcs12->vm_exit_reason = evmcs->vm_exit_reason;
1788          * vmcs12->vm_exit_intr_info = evmcs->vm_exit_intr_info;
1789          * vmcs12->vm_exit_intr_error_code = evmcs->vm_exit_intr_error_code;
1790          * vmcs12->idt_vectoring_info_field = evmcs->idt_vectoring_info_field;
1791          * vmcs12->idt_vectoring_error_code = evmcs->idt_vectoring_error_code;
1792          * vmcs12->vm_exit_instruction_len = evmcs->vm_exit_instruction_len;
1793          * vmcs12->vmx_instruction_info = evmcs->vmx_instruction_info;
1794          * vmcs12->exit_qualification = evmcs->exit_qualification;
1795          * vmcs12->guest_linear_address = evmcs->guest_linear_address;
1796          *
1797          * Not present in struct vmcs12:
1798          * vmcs12->exit_io_instruction_ecx = evmcs->exit_io_instruction_ecx;
1799          * vmcs12->exit_io_instruction_esi = evmcs->exit_io_instruction_esi;
1800          * vmcs12->exit_io_instruction_edi = evmcs->exit_io_instruction_edi;
1801          * vmcs12->exit_io_instruction_eip = evmcs->exit_io_instruction_eip;
1802          */
1803
1804         return;
1805 }
1806
1807 static void copy_vmcs12_to_enlightened(struct vcpu_vmx *vmx)
1808 {
1809         struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12;
1810         struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs;
1811
1812         /*
1813          * Should not be changed by KVM:
1814          *
1815          * evmcs->host_es_selector = vmcs12->host_es_selector;
1816          * evmcs->host_cs_selector = vmcs12->host_cs_selector;
1817          * evmcs->host_ss_selector = vmcs12->host_ss_selector;
1818          * evmcs->host_ds_selector = vmcs12->host_ds_selector;
1819          * evmcs->host_fs_selector = vmcs12->host_fs_selector;
1820          * evmcs->host_gs_selector = vmcs12->host_gs_selector;
1821          * evmcs->host_tr_selector = vmcs12->host_tr_selector;
1822          * evmcs->host_ia32_pat = vmcs12->host_ia32_pat;
1823          * evmcs->host_ia32_efer = vmcs12->host_ia32_efer;
1824          * evmcs->host_cr0 = vmcs12->host_cr0;
1825          * evmcs->host_cr3 = vmcs12->host_cr3;
1826          * evmcs->host_cr4 = vmcs12->host_cr4;
1827          * evmcs->host_ia32_sysenter_esp = vmcs12->host_ia32_sysenter_esp;
1828          * evmcs->host_ia32_sysenter_eip = vmcs12->host_ia32_sysenter_eip;
1829          * evmcs->host_rip = vmcs12->host_rip;
1830          * evmcs->host_ia32_sysenter_cs = vmcs12->host_ia32_sysenter_cs;
1831          * evmcs->host_fs_base = vmcs12->host_fs_base;
1832          * evmcs->host_gs_base = vmcs12->host_gs_base;
1833          * evmcs->host_tr_base = vmcs12->host_tr_base;
1834          * evmcs->host_gdtr_base = vmcs12->host_gdtr_base;
1835          * evmcs->host_idtr_base = vmcs12->host_idtr_base;
1836          * evmcs->host_rsp = vmcs12->host_rsp;
1837          * sync_vmcs02_to_vmcs12() doesn't read these:
1838          * evmcs->io_bitmap_a = vmcs12->io_bitmap_a;
1839          * evmcs->io_bitmap_b = vmcs12->io_bitmap_b;
1840          * evmcs->msr_bitmap = vmcs12->msr_bitmap;
1841          * evmcs->ept_pointer = vmcs12->ept_pointer;
1842          * evmcs->xss_exit_bitmap = vmcs12->xss_exit_bitmap;
1843          * evmcs->vm_exit_msr_store_addr = vmcs12->vm_exit_msr_store_addr;
1844          * evmcs->vm_exit_msr_load_addr = vmcs12->vm_exit_msr_load_addr;
1845          * evmcs->vm_entry_msr_load_addr = vmcs12->vm_entry_msr_load_addr;
1846          * evmcs->tpr_threshold = vmcs12->tpr_threshold;
1847          * evmcs->virtual_processor_id = vmcs12->virtual_processor_id;
1848          * evmcs->exception_bitmap = vmcs12->exception_bitmap;
1849          * evmcs->vmcs_link_pointer = vmcs12->vmcs_link_pointer;
1850          * evmcs->pin_based_vm_exec_control = vmcs12->pin_based_vm_exec_control;
1851          * evmcs->vm_exit_controls = vmcs12->vm_exit_controls;
1852          * evmcs->secondary_vm_exec_control = vmcs12->secondary_vm_exec_control;
1853          * evmcs->page_fault_error_code_mask =
1854          *              vmcs12->page_fault_error_code_mask;
1855          * evmcs->page_fault_error_code_match =
1856          *              vmcs12->page_fault_error_code_match;
1857          * evmcs->cr3_target_count = vmcs12->cr3_target_count;
1858          * evmcs->virtual_apic_page_addr = vmcs12->virtual_apic_page_addr;
1859          * evmcs->tsc_offset = vmcs12->tsc_offset;
1860          * evmcs->guest_ia32_debugctl = vmcs12->guest_ia32_debugctl;
1861          * evmcs->cr0_guest_host_mask = vmcs12->cr0_guest_host_mask;
1862          * evmcs->cr4_guest_host_mask = vmcs12->cr4_guest_host_mask;
1863          * evmcs->cr0_read_shadow = vmcs12->cr0_read_shadow;
1864          * evmcs->cr4_read_shadow = vmcs12->cr4_read_shadow;
1865          * evmcs->vm_exit_msr_store_count = vmcs12->vm_exit_msr_store_count;
1866          * evmcs->vm_exit_msr_load_count = vmcs12->vm_exit_msr_load_count;
1867          * evmcs->vm_entry_msr_load_count = vmcs12->vm_entry_msr_load_count;
1868          *
1869          * Not present in struct vmcs12:
1870          * evmcs->exit_io_instruction_ecx = vmcs12->exit_io_instruction_ecx;
1871          * evmcs->exit_io_instruction_esi = vmcs12->exit_io_instruction_esi;
1872          * evmcs->exit_io_instruction_edi = vmcs12->exit_io_instruction_edi;
1873          * evmcs->exit_io_instruction_eip = vmcs12->exit_io_instruction_eip;
1874          */
1875
1876         evmcs->guest_es_selector = vmcs12->guest_es_selector;
1877         evmcs->guest_cs_selector = vmcs12->guest_cs_selector;
1878         evmcs->guest_ss_selector = vmcs12->guest_ss_selector;
1879         evmcs->guest_ds_selector = vmcs12->guest_ds_selector;
1880         evmcs->guest_fs_selector = vmcs12->guest_fs_selector;
1881         evmcs->guest_gs_selector = vmcs12->guest_gs_selector;
1882         evmcs->guest_ldtr_selector = vmcs12->guest_ldtr_selector;
1883         evmcs->guest_tr_selector = vmcs12->guest_tr_selector;
1884
1885         evmcs->guest_es_limit = vmcs12->guest_es_limit;
1886         evmcs->guest_cs_limit = vmcs12->guest_cs_limit;
1887         evmcs->guest_ss_limit = vmcs12->guest_ss_limit;
1888         evmcs->guest_ds_limit = vmcs12->guest_ds_limit;
1889         evmcs->guest_fs_limit = vmcs12->guest_fs_limit;
1890         evmcs->guest_gs_limit = vmcs12->guest_gs_limit;
1891         evmcs->guest_ldtr_limit = vmcs12->guest_ldtr_limit;
1892         evmcs->guest_tr_limit = vmcs12->guest_tr_limit;
1893         evmcs->guest_gdtr_limit = vmcs12->guest_gdtr_limit;
1894         evmcs->guest_idtr_limit = vmcs12->guest_idtr_limit;
1895
1896         evmcs->guest_es_ar_bytes = vmcs12->guest_es_ar_bytes;
1897         evmcs->guest_cs_ar_bytes = vmcs12->guest_cs_ar_bytes;
1898         evmcs->guest_ss_ar_bytes = vmcs12->guest_ss_ar_bytes;
1899         evmcs->guest_ds_ar_bytes = vmcs12->guest_ds_ar_bytes;
1900         evmcs->guest_fs_ar_bytes = vmcs12->guest_fs_ar_bytes;
1901         evmcs->guest_gs_ar_bytes = vmcs12->guest_gs_ar_bytes;
1902         evmcs->guest_ldtr_ar_bytes = vmcs12->guest_ldtr_ar_bytes;
1903         evmcs->guest_tr_ar_bytes = vmcs12->guest_tr_ar_bytes;
1904
1905         evmcs->guest_es_base = vmcs12->guest_es_base;
1906         evmcs->guest_cs_base = vmcs12->guest_cs_base;
1907         evmcs->guest_ss_base = vmcs12->guest_ss_base;
1908         evmcs->guest_ds_base = vmcs12->guest_ds_base;
1909         evmcs->guest_fs_base = vmcs12->guest_fs_base;
1910         evmcs->guest_gs_base = vmcs12->guest_gs_base;
1911         evmcs->guest_ldtr_base = vmcs12->guest_ldtr_base;
1912         evmcs->guest_tr_base = vmcs12->guest_tr_base;
1913         evmcs->guest_gdtr_base = vmcs12->guest_gdtr_base;
1914         evmcs->guest_idtr_base = vmcs12->guest_idtr_base;
1915
1916         evmcs->guest_ia32_pat = vmcs12->guest_ia32_pat;
1917         evmcs->guest_ia32_efer = vmcs12->guest_ia32_efer;
1918
1919         evmcs->guest_pdptr0 = vmcs12->guest_pdptr0;
1920         evmcs->guest_pdptr1 = vmcs12->guest_pdptr1;
1921         evmcs->guest_pdptr2 = vmcs12->guest_pdptr2;
1922         evmcs->guest_pdptr3 = vmcs12->guest_pdptr3;
1923
1924         evmcs->guest_pending_dbg_exceptions =
1925                 vmcs12->guest_pending_dbg_exceptions;
1926         evmcs->guest_sysenter_esp = vmcs12->guest_sysenter_esp;
1927         evmcs->guest_sysenter_eip = vmcs12->guest_sysenter_eip;
1928
1929         evmcs->guest_activity_state = vmcs12->guest_activity_state;
1930         evmcs->guest_sysenter_cs = vmcs12->guest_sysenter_cs;
1931
1932         evmcs->guest_cr0 = vmcs12->guest_cr0;
1933         evmcs->guest_cr3 = vmcs12->guest_cr3;
1934         evmcs->guest_cr4 = vmcs12->guest_cr4;
1935         evmcs->guest_dr7 = vmcs12->guest_dr7;
1936
1937         evmcs->guest_physical_address = vmcs12->guest_physical_address;
1938
1939         evmcs->vm_instruction_error = vmcs12->vm_instruction_error;
1940         evmcs->vm_exit_reason = vmcs12->vm_exit_reason;
1941         evmcs->vm_exit_intr_info = vmcs12->vm_exit_intr_info;
1942         evmcs->vm_exit_intr_error_code = vmcs12->vm_exit_intr_error_code;
1943         evmcs->idt_vectoring_info_field = vmcs12->idt_vectoring_info_field;
1944         evmcs->idt_vectoring_error_code = vmcs12->idt_vectoring_error_code;
1945         evmcs->vm_exit_instruction_len = vmcs12->vm_exit_instruction_len;
1946         evmcs->vmx_instruction_info = vmcs12->vmx_instruction_info;
1947
1948         evmcs->exit_qualification = vmcs12->exit_qualification;
1949
1950         evmcs->guest_linear_address = vmcs12->guest_linear_address;
1951         evmcs->guest_rsp = vmcs12->guest_rsp;
1952         evmcs->guest_rflags = vmcs12->guest_rflags;
1953
1954         evmcs->guest_interruptibility_info =
1955                 vmcs12->guest_interruptibility_info;
1956         evmcs->cpu_based_vm_exec_control = vmcs12->cpu_based_vm_exec_control;
1957         evmcs->vm_entry_controls = vmcs12->vm_entry_controls;
1958         evmcs->vm_entry_intr_info_field = vmcs12->vm_entry_intr_info_field;
1959         evmcs->vm_entry_exception_error_code =
1960                 vmcs12->vm_entry_exception_error_code;
1961         evmcs->vm_entry_instruction_len = vmcs12->vm_entry_instruction_len;
1962
1963         evmcs->guest_rip = vmcs12->guest_rip;
1964
1965         evmcs->guest_bndcfgs = vmcs12->guest_bndcfgs;
1966
1967         return;
1968 }
1969
1970 /*
1971  * This is an equivalent of the nested hypervisor executing the vmptrld
1972  * instruction.
1973  */
1974 static enum nested_evmptrld_status nested_vmx_handle_enlightened_vmptrld(
1975         struct kvm_vcpu *vcpu, bool from_launch)
1976 {
1977         struct vcpu_vmx *vmx = to_vmx(vcpu);
1978         bool evmcs_gpa_changed = false;
1979         u64 evmcs_gpa;
1980
1981         if (likely(!vmx->nested.enlightened_vmcs_enabled))
1982                 return EVMPTRLD_DISABLED;
1983
1984         if (!nested_enlightened_vmentry(vcpu, &evmcs_gpa)) {
1985                 nested_release_evmcs(vcpu);
1986                 return EVMPTRLD_DISABLED;
1987         }
1988
1989         if (unlikely(evmcs_gpa != vmx->nested.hv_evmcs_vmptr)) {
1990                 vmx->nested.current_vmptr = INVALID_GPA;
1991
1992                 nested_release_evmcs(vcpu);
1993
1994                 if (kvm_vcpu_map(vcpu, gpa_to_gfn(evmcs_gpa),
1995                                  &vmx->nested.hv_evmcs_map))
1996                         return EVMPTRLD_ERROR;
1997
1998                 vmx->nested.hv_evmcs = vmx->nested.hv_evmcs_map.hva;
1999
2000                 /*
2001                  * Currently, KVM only supports eVMCS version 1
2002                  * (== KVM_EVMCS_VERSION) and thus we expect guest to set this
2003                  * value to first u32 field of eVMCS which should specify eVMCS
2004                  * VersionNumber.
2005                  *
2006                  * Guest should be aware of supported eVMCS versions by host by
2007                  * examining CPUID.0x4000000A.EAX[0:15]. Host userspace VMM is
2008                  * expected to set this CPUID leaf according to the value
2009                  * returned in vmcs_version from nested_enable_evmcs().
2010                  *
2011                  * However, it turns out that Microsoft Hyper-V fails to comply
2012                  * to their own invented interface: When Hyper-V use eVMCS, it
2013                  * just sets first u32 field of eVMCS to revision_id specified
2014                  * in MSR_IA32_VMX_BASIC. Instead of used eVMCS version number
2015                  * which is one of the supported versions specified in
2016                  * CPUID.0x4000000A.EAX[0:15].
2017                  *
2018                  * To overcome Hyper-V bug, we accept here either a supported
2019                  * eVMCS version or VMCS12 revision_id as valid values for first
2020                  * u32 field of eVMCS.
2021                  */
2022                 if ((vmx->nested.hv_evmcs->revision_id != KVM_EVMCS_VERSION) &&
2023                     (vmx->nested.hv_evmcs->revision_id != VMCS12_REVISION)) {
2024                         nested_release_evmcs(vcpu);
2025                         return EVMPTRLD_VMFAIL;
2026                 }
2027
2028                 vmx->nested.hv_evmcs_vmptr = evmcs_gpa;
2029
2030                 evmcs_gpa_changed = true;
2031                 /*
2032                  * Unlike normal vmcs12, enlightened vmcs12 is not fully
2033                  * reloaded from guest's memory (read only fields, fields not
2034                  * present in struct hv_enlightened_vmcs, ...). Make sure there
2035                  * are no leftovers.
2036                  */
2037                 if (from_launch) {
2038                         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2039                         memset(vmcs12, 0, sizeof(*vmcs12));
2040                         vmcs12->hdr.revision_id = VMCS12_REVISION;
2041                 }
2042
2043         }
2044
2045         /*
2046          * Clean fields data can't be used on VMLAUNCH and when we switch
2047          * between different L2 guests as KVM keeps a single VMCS12 per L1.
2048          */
2049         if (from_launch || evmcs_gpa_changed) {
2050                 vmx->nested.hv_evmcs->hv_clean_fields &=
2051                         ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
2052
2053                 vmx->nested.force_msr_bitmap_recalc = true;
2054         }
2055
2056         return EVMPTRLD_SUCCEEDED;
2057 }
2058
2059 void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu)
2060 {
2061         struct vcpu_vmx *vmx = to_vmx(vcpu);
2062
2063         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
2064                 copy_vmcs12_to_enlightened(vmx);
2065         else
2066                 copy_vmcs12_to_shadow(vmx);
2067
2068         vmx->nested.need_vmcs12_to_shadow_sync = false;
2069 }
2070
2071 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
2072 {
2073         struct vcpu_vmx *vmx =
2074                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
2075
2076         vmx->nested.preemption_timer_expired = true;
2077         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
2078         kvm_vcpu_kick(&vmx->vcpu);
2079
2080         return HRTIMER_NORESTART;
2081 }
2082
2083 static u64 vmx_calc_preemption_timer_value(struct kvm_vcpu *vcpu)
2084 {
2085         struct vcpu_vmx *vmx = to_vmx(vcpu);
2086         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2087
2088         u64 l1_scaled_tsc = kvm_read_l1_tsc(vcpu, rdtsc()) >>
2089                             VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
2090
2091         if (!vmx->nested.has_preemption_timer_deadline) {
2092                 vmx->nested.preemption_timer_deadline =
2093                         vmcs12->vmx_preemption_timer_value + l1_scaled_tsc;
2094                 vmx->nested.has_preemption_timer_deadline = true;
2095         }
2096         return vmx->nested.preemption_timer_deadline - l1_scaled_tsc;
2097 }
2098
2099 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu,
2100                                         u64 preemption_timeout)
2101 {
2102         struct vcpu_vmx *vmx = to_vmx(vcpu);
2103
2104         /*
2105          * A timer value of zero is architecturally guaranteed to cause
2106          * a VMExit prior to executing any instructions in the guest.
2107          */
2108         if (preemption_timeout == 0) {
2109                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
2110                 return;
2111         }
2112
2113         if (vcpu->arch.virtual_tsc_khz == 0)
2114                 return;
2115
2116         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
2117         preemption_timeout *= 1000000;
2118         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
2119         hrtimer_start(&vmx->nested.preemption_timer,
2120                       ktime_add_ns(ktime_get(), preemption_timeout),
2121                       HRTIMER_MODE_ABS_PINNED);
2122 }
2123
2124 static u64 nested_vmx_calc_efer(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
2125 {
2126         if (vmx->nested.nested_run_pending &&
2127             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
2128                 return vmcs12->guest_ia32_efer;
2129         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
2130                 return vmx->vcpu.arch.efer | (EFER_LMA | EFER_LME);
2131         else
2132                 return vmx->vcpu.arch.efer & ~(EFER_LMA | EFER_LME);
2133 }
2134
2135 static void prepare_vmcs02_constant_state(struct vcpu_vmx *vmx)
2136 {
2137         struct kvm *kvm = vmx->vcpu.kvm;
2138
2139         /*
2140          * If vmcs02 hasn't been initialized, set the constant vmcs02 state
2141          * according to L0's settings (vmcs12 is irrelevant here).  Host
2142          * fields that come from L0 and are not constant, e.g. HOST_CR3,
2143          * will be set as needed prior to VMLAUNCH/VMRESUME.
2144          */
2145         if (vmx->nested.vmcs02_initialized)
2146                 return;
2147         vmx->nested.vmcs02_initialized = true;
2148
2149         /*
2150          * We don't care what the EPTP value is we just need to guarantee
2151          * it's valid so we don't get a false positive when doing early
2152          * consistency checks.
2153          */
2154         if (enable_ept && nested_early_check)
2155                 vmcs_write64(EPT_POINTER,
2156                              construct_eptp(&vmx->vcpu, 0, PT64_ROOT_4LEVEL));
2157
2158         /* All VMFUNCs are currently emulated through L0 vmexits.  */
2159         if (cpu_has_vmx_vmfunc())
2160                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
2161
2162         if (cpu_has_vmx_posted_intr())
2163                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
2164
2165         if (cpu_has_vmx_msr_bitmap())
2166                 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
2167
2168         /*
2169          * PML is emulated for L2, but never enabled in hardware as the MMU
2170          * handles A/D emulation.  Disabling PML for L2 also avoids having to
2171          * deal with filtering out L2 GPAs from the buffer.
2172          */
2173         if (enable_pml) {
2174                 vmcs_write64(PML_ADDRESS, 0);
2175                 vmcs_write16(GUEST_PML_INDEX, -1);
2176         }
2177
2178         if (cpu_has_vmx_encls_vmexit())
2179                 vmcs_write64(ENCLS_EXITING_BITMAP, INVALID_GPA);
2180
2181         if (kvm_notify_vmexit_enabled(kvm))
2182                 vmcs_write32(NOTIFY_WINDOW, kvm->arch.notify_window);
2183
2184         /*
2185          * Set the MSR load/store lists to match L0's settings.  Only the
2186          * addresses are constant (for vmcs02), the counts can change based
2187          * on L2's behavior, e.g. switching to/from long mode.
2188          */
2189         vmcs_write64(VM_EXIT_MSR_STORE_ADDR, __pa(vmx->msr_autostore.guest.val));
2190         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2191         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
2192
2193         vmx_set_constant_host_state(vmx);
2194 }
2195
2196 static void prepare_vmcs02_early_rare(struct vcpu_vmx *vmx,
2197                                       struct vmcs12 *vmcs12)
2198 {
2199         prepare_vmcs02_constant_state(vmx);
2200
2201         vmcs_write64(VMCS_LINK_POINTER, INVALID_GPA);
2202
2203         if (enable_vpid) {
2204                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
2205                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
2206                 else
2207                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2208         }
2209 }
2210
2211 static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct loaded_vmcs *vmcs01,
2212                                  struct vmcs12 *vmcs12)
2213 {
2214         u32 exec_control;
2215         u64 guest_efer = nested_vmx_calc_efer(vmx, vmcs12);
2216
2217         if (vmx->nested.dirty_vmcs12 || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
2218                 prepare_vmcs02_early_rare(vmx, vmcs12);
2219
2220         /*
2221          * PIN CONTROLS
2222          */
2223         exec_control = __pin_controls_get(vmcs01);
2224         exec_control |= (vmcs12->pin_based_vm_exec_control &
2225                          ~PIN_BASED_VMX_PREEMPTION_TIMER);
2226
2227         /* Posted interrupts setting is only taken from vmcs12.  */
2228         vmx->nested.pi_pending = false;
2229         if (nested_cpu_has_posted_intr(vmcs12))
2230                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
2231         else
2232                 exec_control &= ~PIN_BASED_POSTED_INTR;
2233         pin_controls_set(vmx, exec_control);
2234
2235         /*
2236          * EXEC CONTROLS
2237          */
2238         exec_control = __exec_controls_get(vmcs01); /* L0's desires */
2239         exec_control &= ~CPU_BASED_INTR_WINDOW_EXITING;
2240         exec_control &= ~CPU_BASED_NMI_WINDOW_EXITING;
2241         exec_control &= ~CPU_BASED_TPR_SHADOW;
2242         exec_control |= vmcs12->cpu_based_vm_exec_control;
2243
2244         vmx->nested.l1_tpr_threshold = -1;
2245         if (exec_control & CPU_BASED_TPR_SHADOW)
2246                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
2247 #ifdef CONFIG_X86_64
2248         else
2249                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
2250                                 CPU_BASED_CR8_STORE_EXITING;
2251 #endif
2252
2253         /*
2254          * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
2255          * for I/O port accesses.
2256          */
2257         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
2258         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
2259
2260         /*
2261          * This bit will be computed in nested_get_vmcs12_pages, because
2262          * we do not have access to L1's MSR bitmap yet.  For now, keep
2263          * the same bit as before, hoping to avoid multiple VMWRITEs that
2264          * only set/clear this bit.
2265          */
2266         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
2267         exec_control |= exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS;
2268
2269         exec_controls_set(vmx, exec_control);
2270
2271         /*
2272          * SECONDARY EXEC CONTROLS
2273          */
2274         if (cpu_has_secondary_exec_ctrls()) {
2275                 exec_control = __secondary_exec_controls_get(vmcs01);
2276
2277                 /* Take the following fields only from vmcs12 */
2278                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2279                                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2280                                   SECONDARY_EXEC_ENABLE_INVPCID |
2281                                   SECONDARY_EXEC_ENABLE_RDTSCP |
2282                                   SECONDARY_EXEC_XSAVES |
2283                                   SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2284                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2285                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
2286                                   SECONDARY_EXEC_ENABLE_VMFUNC |
2287                                   SECONDARY_EXEC_DESC);
2288
2289                 if (nested_cpu_has(vmcs12,
2290                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
2291                         exec_control |= vmcs12->secondary_vm_exec_control;
2292
2293                 /* PML is emulated and never enabled in hardware for L2. */
2294                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
2295
2296                 /* VMCS shadowing for L2 is emulated for now */
2297                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
2298
2299                 /*
2300                  * Preset *DT exiting when emulating UMIP, so that vmx_set_cr4()
2301                  * will not have to rewrite the controls just for this bit.
2302                  */
2303                 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated() &&
2304                     (vmcs12->guest_cr4 & X86_CR4_UMIP))
2305                         exec_control |= SECONDARY_EXEC_DESC;
2306
2307                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
2308                         vmcs_write16(GUEST_INTR_STATUS,
2309                                 vmcs12->guest_intr_status);
2310
2311                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
2312                     exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2313
2314                 if (exec_control & SECONDARY_EXEC_ENCLS_EXITING)
2315                         vmx_write_encls_bitmap(&vmx->vcpu, vmcs12);
2316
2317                 secondary_exec_controls_set(vmx, exec_control);
2318         }
2319
2320         /*
2321          * ENTRY CONTROLS
2322          *
2323          * vmcs12's VM_{ENTRY,EXIT}_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE
2324          * are emulated by vmx_set_efer() in prepare_vmcs02(), but speculate
2325          * on the related bits (if supported by the CPU) in the hope that
2326          * we can avoid VMWrites during vmx_set_efer().
2327          */
2328         exec_control = __vm_entry_controls_get(vmcs01);
2329         exec_control |= vmcs12->vm_entry_controls;
2330         exec_control &= ~(VM_ENTRY_IA32E_MODE | VM_ENTRY_LOAD_IA32_EFER);
2331         if (cpu_has_load_ia32_efer()) {
2332                 if (guest_efer & EFER_LMA)
2333                         exec_control |= VM_ENTRY_IA32E_MODE;
2334                 if (guest_efer != host_efer)
2335                         exec_control |= VM_ENTRY_LOAD_IA32_EFER;
2336         }
2337         vm_entry_controls_set(vmx, exec_control);
2338
2339         /*
2340          * EXIT CONTROLS
2341          *
2342          * L2->L1 exit controls are emulated - the hardware exit is to L0 so
2343          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
2344          * bits may be modified by vmx_set_efer() in prepare_vmcs02().
2345          */
2346         exec_control = __vm_exit_controls_get(vmcs01);
2347         if (cpu_has_load_ia32_efer() && guest_efer != host_efer)
2348                 exec_control |= VM_EXIT_LOAD_IA32_EFER;
2349         else
2350                 exec_control &= ~VM_EXIT_LOAD_IA32_EFER;
2351         vm_exit_controls_set(vmx, exec_control);
2352
2353         /*
2354          * Interrupt/Exception Fields
2355          */
2356         if (vmx->nested.nested_run_pending) {
2357                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2358                              vmcs12->vm_entry_intr_info_field);
2359                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2360                              vmcs12->vm_entry_exception_error_code);
2361                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2362                              vmcs12->vm_entry_instruction_len);
2363                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
2364                              vmcs12->guest_interruptibility_info);
2365                 vmx->loaded_vmcs->nmi_known_unmasked =
2366                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
2367         } else {
2368                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
2369         }
2370 }
2371
2372 static void prepare_vmcs02_rare(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
2373 {
2374         struct hv_enlightened_vmcs *hv_evmcs = vmx->nested.hv_evmcs;
2375
2376         if (!hv_evmcs || !(hv_evmcs->hv_clean_fields &
2377                            HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2)) {
2378                 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
2379                 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
2380                 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
2381                 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
2382                 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
2383                 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
2384                 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
2385                 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
2386                 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
2387                 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
2388                 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
2389                 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
2390                 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
2391                 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
2392                 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
2393                 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
2394                 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
2395                 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
2396                 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
2397                 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
2398                 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
2399                 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
2400                 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
2401                 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
2402                 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
2403                 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
2404                 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
2405                 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
2406                 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
2407                 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
2408                 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
2409                 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
2410                 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
2411                 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
2412                 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
2413                 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
2414
2415                 vmx->segment_cache.bitmask = 0;
2416         }
2417
2418         if (!hv_evmcs || !(hv_evmcs->hv_clean_fields &
2419                            HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1)) {
2420                 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
2421                 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
2422                             vmcs12->guest_pending_dbg_exceptions);
2423                 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
2424                 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
2425
2426                 /*
2427                  * L1 may access the L2's PDPTR, so save them to construct
2428                  * vmcs12
2429                  */
2430                 if (enable_ept) {
2431                         vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
2432                         vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
2433                         vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
2434                         vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
2435                 }
2436
2437                 if (kvm_mpx_supported() && vmx->nested.nested_run_pending &&
2438                     (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
2439                         vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
2440         }
2441
2442         if (nested_cpu_has_xsaves(vmcs12))
2443                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
2444
2445         /*
2446          * Whether page-faults are trapped is determined by a combination of
2447          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.  If L0
2448          * doesn't care about page faults then we should set all of these to
2449          * L1's desires. However, if L0 does care about (some) page faults, it
2450          * is not easy (if at all possible?) to merge L0 and L1's desires, we
2451          * simply ask to exit on each and every L2 page fault. This is done by
2452          * setting MASK=MATCH=0 and (see below) EB.PF=1.
2453          * Note that below we don't need special code to set EB.PF beyond the
2454          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
2455          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
2456          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
2457          */
2458         if (vmx_need_pf_intercept(&vmx->vcpu)) {
2459                 /*
2460                  * TODO: if both L0 and L1 need the same MASK and MATCH,
2461                  * go ahead and use it?
2462                  */
2463                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
2464                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
2465         } else {
2466                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, vmcs12->page_fault_error_code_mask);
2467                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, vmcs12->page_fault_error_code_match);
2468         }
2469
2470         if (cpu_has_vmx_apicv()) {
2471                 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
2472                 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
2473                 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
2474                 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
2475         }
2476
2477         /*
2478          * Make sure the msr_autostore list is up to date before we set the
2479          * count in the vmcs02.
2480          */
2481         prepare_vmx_msr_autostore_list(&vmx->vcpu, MSR_IA32_TSC);
2482
2483         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, vmx->msr_autostore.guest.nr);
2484         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
2485         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
2486
2487         set_cr4_guest_host_mask(vmx);
2488 }
2489
2490 /*
2491  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
2492  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
2493  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
2494  * guest in a way that will both be appropriate to L1's requests, and our
2495  * needs. In addition to modifying the active vmcs (which is vmcs02), this
2496  * function also has additional necessary side-effects, like setting various
2497  * vcpu->arch fields.
2498  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
2499  * is assigned to entry_failure_code on failure.
2500  */
2501 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
2502                           bool from_vmentry,
2503                           enum vm_entry_failure_code *entry_failure_code)
2504 {
2505         struct vcpu_vmx *vmx = to_vmx(vcpu);
2506         bool load_guest_pdptrs_vmcs12 = false;
2507
2508         if (vmx->nested.dirty_vmcs12 || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) {
2509                 prepare_vmcs02_rare(vmx, vmcs12);
2510                 vmx->nested.dirty_vmcs12 = false;
2511
2512                 load_guest_pdptrs_vmcs12 = !evmptr_is_valid(vmx->nested.hv_evmcs_vmptr) ||
2513                         !(vmx->nested.hv_evmcs->hv_clean_fields &
2514                           HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1);
2515         }
2516
2517         if (vmx->nested.nested_run_pending &&
2518             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
2519                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
2520                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
2521         } else {
2522                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
2523                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.pre_vmenter_debugctl);
2524         }
2525         if (kvm_mpx_supported() && (!vmx->nested.nested_run_pending ||
2526             !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)))
2527                 vmcs_write64(GUEST_BNDCFGS, vmx->nested.pre_vmenter_bndcfgs);
2528         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
2529
2530         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
2531          * bitwise-or of what L1 wants to trap for L2, and what we want to
2532          * trap. Note that CR0.TS also needs updating - we do this later.
2533          */
2534         vmx_update_exception_bitmap(vcpu);
2535         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
2536         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2537
2538         if (vmx->nested.nested_run_pending &&
2539             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
2540                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
2541                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
2542         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2543                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
2544         }
2545
2546         vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2547                         vcpu->arch.l1_tsc_offset,
2548                         vmx_get_l2_tsc_offset(vcpu),
2549                         vmx_get_l2_tsc_multiplier(vcpu));
2550
2551         vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2552                         vcpu->arch.l1_tsc_scaling_ratio,
2553                         vmx_get_l2_tsc_multiplier(vcpu));
2554
2555         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
2556         if (kvm_caps.has_tsc_control)
2557                 vmcs_write64(TSC_MULTIPLIER, vcpu->arch.tsc_scaling_ratio);
2558
2559         nested_vmx_transition_tlb_flush(vcpu, vmcs12, true);
2560
2561         if (nested_cpu_has_ept(vmcs12))
2562                 nested_ept_init_mmu_context(vcpu);
2563
2564         /*
2565          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
2566          * bits which we consider mandatory enabled.
2567          * The CR0_READ_SHADOW is what L2 should have expected to read given
2568          * the specifications by L1; It's not enough to take
2569          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
2570          * have more bits than L1 expected.
2571          */
2572         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
2573         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2574
2575         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
2576         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
2577
2578         vcpu->arch.efer = nested_vmx_calc_efer(vmx, vmcs12);
2579         /* Note: may modify VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
2580         vmx_set_efer(vcpu, vcpu->arch.efer);
2581
2582         /*
2583          * Guest state is invalid and unrestricted guest is disabled,
2584          * which means L1 attempted VMEntry to L2 with invalid state.
2585          * Fail the VMEntry.
2586          *
2587          * However when force loading the guest state (SMM exit or
2588          * loading nested state after migration, it is possible to
2589          * have invalid guest state now, which will be later fixed by
2590          * restoring L2 register state
2591          */
2592         if (CC(from_vmentry && !vmx_guest_state_valid(vcpu))) {
2593                 *entry_failure_code = ENTRY_FAIL_DEFAULT;
2594                 return -EINVAL;
2595         }
2596
2597         /* Shadow page tables on either EPT or shadow page tables. */
2598         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
2599                                 from_vmentry, entry_failure_code))
2600                 return -EINVAL;
2601
2602         /*
2603          * Immediately write vmcs02.GUEST_CR3.  It will be propagated to vmcs12
2604          * on nested VM-Exit, which can occur without actually running L2 and
2605          * thus without hitting vmx_load_mmu_pgd(), e.g. if L1 is entering L2 with
2606          * vmcs12.GUEST_ACTIVITYSTATE=HLT, in which case KVM will intercept the
2607          * transition to HLT instead of running L2.
2608          */
2609         if (enable_ept)
2610                 vmcs_writel(GUEST_CR3, vmcs12->guest_cr3);
2611
2612         /* Late preparation of GUEST_PDPTRs now that EFER and CRs are set. */
2613         if (load_guest_pdptrs_vmcs12 && nested_cpu_has_ept(vmcs12) &&
2614             is_pae_paging(vcpu)) {
2615                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
2616                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
2617                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
2618                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
2619         }
2620
2621         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
2622             WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
2623                                      vmcs12->guest_ia32_perf_global_ctrl))) {
2624                 *entry_failure_code = ENTRY_FAIL_DEFAULT;
2625                 return -EINVAL;
2626         }
2627
2628         kvm_rsp_write(vcpu, vmcs12->guest_rsp);
2629         kvm_rip_write(vcpu, vmcs12->guest_rip);
2630
2631         /*
2632          * It was observed that genuine Hyper-V running in L1 doesn't reset
2633          * 'hv_clean_fields' by itself, it only sets the corresponding dirty
2634          * bits when it changes a field in eVMCS. Mark all fields as clean
2635          * here.
2636          */
2637         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
2638                 vmx->nested.hv_evmcs->hv_clean_fields |=
2639                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
2640
2641         return 0;
2642 }
2643
2644 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
2645 {
2646         if (CC(!nested_cpu_has_nmi_exiting(vmcs12) &&
2647                nested_cpu_has_virtual_nmis(vmcs12)))
2648                 return -EINVAL;
2649
2650         if (CC(!nested_cpu_has_virtual_nmis(vmcs12) &&
2651                nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING)))
2652                 return -EINVAL;
2653
2654         return 0;
2655 }
2656
2657 static bool nested_vmx_check_eptp(struct kvm_vcpu *vcpu, u64 new_eptp)
2658 {
2659         struct vcpu_vmx *vmx = to_vmx(vcpu);
2660
2661         /* Check for memory type validity */
2662         switch (new_eptp & VMX_EPTP_MT_MASK) {
2663         case VMX_EPTP_MT_UC:
2664                 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT)))
2665                         return false;
2666                 break;
2667         case VMX_EPTP_MT_WB:
2668                 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT)))
2669                         return false;
2670                 break;
2671         default:
2672                 return false;
2673         }
2674
2675         /* Page-walk levels validity. */
2676         switch (new_eptp & VMX_EPTP_PWL_MASK) {
2677         case VMX_EPTP_PWL_5:
2678                 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_PAGE_WALK_5_BIT)))
2679                         return false;
2680                 break;
2681         case VMX_EPTP_PWL_4:
2682                 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_PAGE_WALK_4_BIT)))
2683                         return false;
2684                 break;
2685         default:
2686                 return false;
2687         }
2688
2689         /* Reserved bits should not be set */
2690         if (CC(kvm_vcpu_is_illegal_gpa(vcpu, new_eptp) || ((new_eptp >> 7) & 0x1f)))
2691                 return false;
2692
2693         /* AD, if set, should be supported */
2694         if (new_eptp & VMX_EPTP_AD_ENABLE_BIT) {
2695                 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT)))
2696                         return false;
2697         }
2698
2699         return true;
2700 }
2701
2702 /*
2703  * Checks related to VM-Execution Control Fields
2704  */
2705 static int nested_check_vm_execution_controls(struct kvm_vcpu *vcpu,
2706                                               struct vmcs12 *vmcs12)
2707 {
2708         struct vcpu_vmx *vmx = to_vmx(vcpu);
2709
2710         if (CC(!vmx_control_verify(vmcs12->pin_based_vm_exec_control,
2711                                    vmx->nested.msrs.pinbased_ctls_low,
2712                                    vmx->nested.msrs.pinbased_ctls_high)) ||
2713             CC(!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
2714                                    vmx->nested.msrs.procbased_ctls_low,
2715                                    vmx->nested.msrs.procbased_ctls_high)))
2716                 return -EINVAL;
2717
2718         if (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
2719             CC(!vmx_control_verify(vmcs12->secondary_vm_exec_control,
2720                                    vmx->nested.msrs.secondary_ctls_low,
2721                                    vmx->nested.msrs.secondary_ctls_high)))
2722                 return -EINVAL;
2723
2724         if (CC(vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) ||
2725             nested_vmx_check_io_bitmap_controls(vcpu, vmcs12) ||
2726             nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12) ||
2727             nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12) ||
2728             nested_vmx_check_apic_access_controls(vcpu, vmcs12) ||
2729             nested_vmx_check_apicv_controls(vcpu, vmcs12) ||
2730             nested_vmx_check_nmi_controls(vmcs12) ||
2731             nested_vmx_check_pml_controls(vcpu, vmcs12) ||
2732             nested_vmx_check_unrestricted_guest_controls(vcpu, vmcs12) ||
2733             nested_vmx_check_mode_based_ept_exec_controls(vcpu, vmcs12) ||
2734             nested_vmx_check_shadow_vmcs_controls(vcpu, vmcs12) ||
2735             CC(nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id))
2736                 return -EINVAL;
2737
2738         if (!nested_cpu_has_preemption_timer(vmcs12) &&
2739             nested_cpu_has_save_preemption_timer(vmcs12))
2740                 return -EINVAL;
2741
2742         if (nested_cpu_has_ept(vmcs12) &&
2743             CC(!nested_vmx_check_eptp(vcpu, vmcs12->ept_pointer)))
2744                 return -EINVAL;
2745
2746         if (nested_cpu_has_vmfunc(vmcs12)) {
2747                 if (CC(vmcs12->vm_function_control &
2748                        ~vmx->nested.msrs.vmfunc_controls))
2749                         return -EINVAL;
2750
2751                 if (nested_cpu_has_eptp_switching(vmcs12)) {
2752                         if (CC(!nested_cpu_has_ept(vmcs12)) ||
2753                             CC(!page_address_valid(vcpu, vmcs12->eptp_list_address)))
2754                                 return -EINVAL;
2755                 }
2756         }
2757
2758         return 0;
2759 }
2760
2761 /*
2762  * Checks related to VM-Exit Control Fields
2763  */
2764 static int nested_check_vm_exit_controls(struct kvm_vcpu *vcpu,
2765                                          struct vmcs12 *vmcs12)
2766 {
2767         struct vcpu_vmx *vmx = to_vmx(vcpu);
2768
2769         if (CC(!vmx_control_verify(vmcs12->vm_exit_controls,
2770                                     vmx->nested.msrs.exit_ctls_low,
2771                                     vmx->nested.msrs.exit_ctls_high)) ||
2772             CC(nested_vmx_check_exit_msr_switch_controls(vcpu, vmcs12)))
2773                 return -EINVAL;
2774
2775         return 0;
2776 }
2777
2778 /*
2779  * Checks related to VM-Entry Control Fields
2780  */
2781 static int nested_check_vm_entry_controls(struct kvm_vcpu *vcpu,
2782                                           struct vmcs12 *vmcs12)
2783 {
2784         struct vcpu_vmx *vmx = to_vmx(vcpu);
2785
2786         if (CC(!vmx_control_verify(vmcs12->vm_entry_controls,
2787                                     vmx->nested.msrs.entry_ctls_low,
2788                                     vmx->nested.msrs.entry_ctls_high)))
2789                 return -EINVAL;
2790
2791         /*
2792          * From the Intel SDM, volume 3:
2793          * Fields relevant to VM-entry event injection must be set properly.
2794          * These fields are the VM-entry interruption-information field, the
2795          * VM-entry exception error code, and the VM-entry instruction length.
2796          */
2797         if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) {
2798                 u32 intr_info = vmcs12->vm_entry_intr_info_field;
2799                 u8 vector = intr_info & INTR_INFO_VECTOR_MASK;
2800                 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK;
2801                 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK;
2802                 bool should_have_error_code;
2803                 bool urg = nested_cpu_has2(vmcs12,
2804                                            SECONDARY_EXEC_UNRESTRICTED_GUEST);
2805                 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE;
2806
2807                 /* VM-entry interruption-info field: interruption type */
2808                 if (CC(intr_type == INTR_TYPE_RESERVED) ||
2809                     CC(intr_type == INTR_TYPE_OTHER_EVENT &&
2810                        !nested_cpu_supports_monitor_trap_flag(vcpu)))
2811                         return -EINVAL;
2812
2813                 /* VM-entry interruption-info field: vector */
2814                 if (CC(intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) ||
2815                     CC(intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) ||
2816                     CC(intr_type == INTR_TYPE_OTHER_EVENT && vector != 0))
2817                         return -EINVAL;
2818
2819                 /* VM-entry interruption-info field: deliver error code */
2820                 should_have_error_code =
2821                         intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode &&
2822                         x86_exception_has_error_code(vector);
2823                 if (CC(has_error_code != should_have_error_code))
2824                         return -EINVAL;
2825
2826                 /* VM-entry exception error code */
2827                 if (CC(has_error_code &&
2828                        vmcs12->vm_entry_exception_error_code & GENMASK(31, 16)))
2829                         return -EINVAL;
2830
2831                 /* VM-entry interruption-info field: reserved bits */
2832                 if (CC(intr_info & INTR_INFO_RESVD_BITS_MASK))
2833                         return -EINVAL;
2834
2835                 /* VM-entry instruction length */
2836                 switch (intr_type) {
2837                 case INTR_TYPE_SOFT_EXCEPTION:
2838                 case INTR_TYPE_SOFT_INTR:
2839                 case INTR_TYPE_PRIV_SW_EXCEPTION:
2840                         if (CC(vmcs12->vm_entry_instruction_len > 15) ||
2841                             CC(vmcs12->vm_entry_instruction_len == 0 &&
2842                             CC(!nested_cpu_has_zero_length_injection(vcpu))))
2843                                 return -EINVAL;
2844                 }
2845         }
2846
2847         if (nested_vmx_check_entry_msr_switch_controls(vcpu, vmcs12))
2848                 return -EINVAL;
2849
2850         return 0;
2851 }
2852
2853 static int nested_vmx_check_controls(struct kvm_vcpu *vcpu,
2854                                      struct vmcs12 *vmcs12)
2855 {
2856         if (nested_check_vm_execution_controls(vcpu, vmcs12) ||
2857             nested_check_vm_exit_controls(vcpu, vmcs12) ||
2858             nested_check_vm_entry_controls(vcpu, vmcs12))
2859                 return -EINVAL;
2860
2861         if (to_vmx(vcpu)->nested.enlightened_vmcs_enabled)
2862                 return nested_evmcs_check_controls(vmcs12);
2863
2864         return 0;
2865 }
2866
2867 static int nested_vmx_check_address_space_size(struct kvm_vcpu *vcpu,
2868                                        struct vmcs12 *vmcs12)
2869 {
2870 #ifdef CONFIG_X86_64
2871         if (CC(!!(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) !=
2872                 !!(vcpu->arch.efer & EFER_LMA)))
2873                 return -EINVAL;
2874 #endif
2875         return 0;
2876 }
2877
2878 static int nested_vmx_check_host_state(struct kvm_vcpu *vcpu,
2879                                        struct vmcs12 *vmcs12)
2880 {
2881         bool ia32e;
2882
2883         if (CC(!nested_host_cr0_valid(vcpu, vmcs12->host_cr0)) ||
2884             CC(!nested_host_cr4_valid(vcpu, vmcs12->host_cr4)) ||
2885             CC(kvm_vcpu_is_illegal_gpa(vcpu, vmcs12->host_cr3)))
2886                 return -EINVAL;
2887
2888         if (CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_esp, vcpu)) ||
2889             CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_eip, vcpu)))
2890                 return -EINVAL;
2891
2892         if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) &&
2893             CC(!kvm_pat_valid(vmcs12->host_ia32_pat)))
2894                 return -EINVAL;
2895
2896         if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) &&
2897             CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu),
2898                                            vmcs12->host_ia32_perf_global_ctrl)))
2899                 return -EINVAL;
2900
2901 #ifdef CONFIG_X86_64
2902         ia32e = !!(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE);
2903 #else
2904         ia32e = false;
2905 #endif
2906
2907         if (ia32e) {
2908                 if (CC(!(vmcs12->host_cr4 & X86_CR4_PAE)))
2909                         return -EINVAL;
2910         } else {
2911                 if (CC(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) ||
2912                     CC(vmcs12->host_cr4 & X86_CR4_PCIDE) ||
2913                     CC((vmcs12->host_rip) >> 32))
2914                         return -EINVAL;
2915         }
2916
2917         if (CC(vmcs12->host_cs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2918             CC(vmcs12->host_ss_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2919             CC(vmcs12->host_ds_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2920             CC(vmcs12->host_es_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2921             CC(vmcs12->host_fs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2922             CC(vmcs12->host_gs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2923             CC(vmcs12->host_tr_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2924             CC(vmcs12->host_cs_selector == 0) ||
2925             CC(vmcs12->host_tr_selector == 0) ||
2926             CC(vmcs12->host_ss_selector == 0 && !ia32e))
2927                 return -EINVAL;
2928
2929         if (CC(is_noncanonical_address(vmcs12->host_fs_base, vcpu)) ||
2930             CC(is_noncanonical_address(vmcs12->host_gs_base, vcpu)) ||
2931             CC(is_noncanonical_address(vmcs12->host_gdtr_base, vcpu)) ||
2932             CC(is_noncanonical_address(vmcs12->host_idtr_base, vcpu)) ||
2933             CC(is_noncanonical_address(vmcs12->host_tr_base, vcpu)) ||
2934             CC(is_noncanonical_address(vmcs12->host_rip, vcpu)))
2935                 return -EINVAL;
2936
2937         /*
2938          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
2939          * IA32_EFER MSR must be 0 in the field for that register. In addition,
2940          * the values of the LMA and LME bits in the field must each be that of
2941          * the host address-space size VM-exit control.
2942          */
2943         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
2944                 if (CC(!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer)) ||
2945                     CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA)) ||
2946                     CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)))
2947                         return -EINVAL;
2948         }
2949
2950         return 0;
2951 }
2952
2953 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu,
2954                                           struct vmcs12 *vmcs12)
2955 {
2956         struct vcpu_vmx *vmx = to_vmx(vcpu);
2957         struct gfn_to_hva_cache *ghc = &vmx->nested.shadow_vmcs12_cache;
2958         struct vmcs_hdr hdr;
2959
2960         if (vmcs12->vmcs_link_pointer == INVALID_GPA)
2961                 return 0;
2962
2963         if (CC(!page_address_valid(vcpu, vmcs12->vmcs_link_pointer)))
2964                 return -EINVAL;
2965
2966         if (ghc->gpa != vmcs12->vmcs_link_pointer &&
2967             CC(kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc,
2968                                          vmcs12->vmcs_link_pointer, VMCS12_SIZE)))
2969                 return -EINVAL;
2970
2971         if (CC(kvm_read_guest_offset_cached(vcpu->kvm, ghc, &hdr,
2972                                             offsetof(struct vmcs12, hdr),
2973                                             sizeof(hdr))))
2974                 return -EINVAL;
2975
2976         if (CC(hdr.revision_id != VMCS12_REVISION) ||
2977             CC(hdr.shadow_vmcs != nested_cpu_has_shadow_vmcs(vmcs12)))
2978                 return -EINVAL;
2979
2980         return 0;
2981 }
2982
2983 /*
2984  * Checks related to Guest Non-register State
2985  */
2986 static int nested_check_guest_non_reg_state(struct vmcs12 *vmcs12)
2987 {
2988         if (CC(vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
2989                vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT &&
2990                vmcs12->guest_activity_state != GUEST_ACTIVITY_WAIT_SIPI))
2991                 return -EINVAL;
2992
2993         return 0;
2994 }
2995
2996 static int nested_vmx_check_guest_state(struct kvm_vcpu *vcpu,
2997                                         struct vmcs12 *vmcs12,
2998                                         enum vm_entry_failure_code *entry_failure_code)
2999 {
3000         bool ia32e;
3001
3002         *entry_failure_code = ENTRY_FAIL_DEFAULT;
3003
3004         if (CC(!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0)) ||
3005             CC(!nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)))
3006                 return -EINVAL;
3007
3008         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) &&
3009             CC(!kvm_dr7_valid(vmcs12->guest_dr7)))
3010                 return -EINVAL;
3011
3012         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) &&
3013             CC(!kvm_pat_valid(vmcs12->guest_ia32_pat)))
3014                 return -EINVAL;
3015
3016         if (nested_vmx_check_vmcs_link_ptr(vcpu, vmcs12)) {
3017                 *entry_failure_code = ENTRY_FAIL_VMCS_LINK_PTR;
3018                 return -EINVAL;
3019         }
3020
3021         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
3022             CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu),
3023                                            vmcs12->guest_ia32_perf_global_ctrl)))
3024                 return -EINVAL;
3025
3026         /*
3027          * If the load IA32_EFER VM-entry control is 1, the following checks
3028          * are performed on the field for the IA32_EFER MSR:
3029          * - Bits reserved in the IA32_EFER MSR must be 0.
3030          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
3031          *   the IA-32e mode guest VM-exit control. It must also be identical
3032          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
3033          *   CR0.PG) is 1.
3034          */
3035         if (to_vmx(vcpu)->nested.nested_run_pending &&
3036             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
3037                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
3038                 if (CC(!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer)) ||
3039                     CC(ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA)) ||
3040                     CC(((vmcs12->guest_cr0 & X86_CR0_PG) &&
3041                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))))
3042                         return -EINVAL;
3043         }
3044
3045         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
3046             (CC(is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu)) ||
3047              CC((vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD))))
3048                 return -EINVAL;
3049
3050         if (nested_check_guest_non_reg_state(vmcs12))
3051                 return -EINVAL;
3052
3053         return 0;
3054 }
3055
3056 static int nested_vmx_check_vmentry_hw(struct kvm_vcpu *vcpu)
3057 {
3058         struct vcpu_vmx *vmx = to_vmx(vcpu);
3059         unsigned long cr3, cr4;
3060         bool vm_fail;
3061
3062         if (!nested_early_check)
3063                 return 0;
3064
3065         if (vmx->msr_autoload.host.nr)
3066                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3067         if (vmx->msr_autoload.guest.nr)
3068                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3069
3070         preempt_disable();
3071
3072         vmx_prepare_switch_to_guest(vcpu);
3073
3074         /*
3075          * Induce a consistency check VMExit by clearing bit 1 in GUEST_RFLAGS,
3076          * which is reserved to '1' by hardware.  GUEST_RFLAGS is guaranteed to
3077          * be written (by prepare_vmcs02()) before the "real" VMEnter, i.e.
3078          * there is no need to preserve other bits or save/restore the field.
3079          */
3080         vmcs_writel(GUEST_RFLAGS, 0);
3081
3082         cr3 = __get_current_cr3_fast();
3083         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
3084                 vmcs_writel(HOST_CR3, cr3);
3085                 vmx->loaded_vmcs->host_state.cr3 = cr3;
3086         }
3087
3088         cr4 = cr4_read_shadow();
3089         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
3090                 vmcs_writel(HOST_CR4, cr4);
3091                 vmx->loaded_vmcs->host_state.cr4 = cr4;
3092         }
3093
3094         vm_fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
3095                                  vmx->loaded_vmcs->launched);
3096
3097         if (vmx->msr_autoload.host.nr)
3098                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
3099         if (vmx->msr_autoload.guest.nr)
3100                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
3101
3102         if (vm_fail) {
3103                 u32 error = vmcs_read32(VM_INSTRUCTION_ERROR);
3104
3105                 preempt_enable();
3106
3107                 trace_kvm_nested_vmenter_failed(
3108                         "early hardware check VM-instruction error: ", error);
3109                 WARN_ON_ONCE(error != VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3110                 return 1;
3111         }
3112
3113         /*
3114          * VMExit clears RFLAGS.IF and DR7, even on a consistency check.
3115          */
3116         if (hw_breakpoint_active())
3117                 set_debugreg(__this_cpu_read(cpu_dr7), 7);
3118         local_irq_enable();
3119         preempt_enable();
3120
3121         /*
3122          * A non-failing VMEntry means we somehow entered guest mode with
3123          * an illegal RIP, and that's just the tip of the iceberg.  There
3124          * is no telling what memory has been modified or what state has
3125          * been exposed to unknown code.  Hitting this all but guarantees
3126          * a (very critical) hardware issue.
3127          */
3128         WARN_ON(!(vmcs_read32(VM_EXIT_REASON) &
3129                 VMX_EXIT_REASONS_FAILED_VMENTRY));
3130
3131         return 0;
3132 }
3133
3134 static bool nested_get_evmcs_page(struct kvm_vcpu *vcpu)
3135 {
3136         struct vcpu_vmx *vmx = to_vmx(vcpu);
3137
3138         /*
3139          * hv_evmcs may end up being not mapped after migration (when
3140          * L2 was running), map it here to make sure vmcs12 changes are
3141          * properly reflected.
3142          */
3143         if (vmx->nested.enlightened_vmcs_enabled &&
3144             vmx->nested.hv_evmcs_vmptr == EVMPTR_MAP_PENDING) {
3145                 enum nested_evmptrld_status evmptrld_status =
3146                         nested_vmx_handle_enlightened_vmptrld(vcpu, false);
3147
3148                 if (evmptrld_status == EVMPTRLD_VMFAIL ||
3149                     evmptrld_status == EVMPTRLD_ERROR)
3150                         return false;
3151
3152                 /*
3153                  * Post migration VMCS12 always provides the most actual
3154                  * information, copy it to eVMCS upon entry.
3155                  */
3156                 vmx->nested.need_vmcs12_to_shadow_sync = true;
3157         }
3158
3159         return true;
3160 }
3161
3162 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
3163 {
3164         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3165         struct vcpu_vmx *vmx = to_vmx(vcpu);
3166         struct kvm_host_map *map;
3167
3168         if (!vcpu->arch.pdptrs_from_userspace &&
3169             !nested_cpu_has_ept(vmcs12) && is_pae_paging(vcpu)) {
3170                 /*
3171                  * Reload the guest's PDPTRs since after a migration
3172                  * the guest CR3 might be restored prior to setting the nested
3173                  * state which can lead to a load of wrong PDPTRs.
3174                  */
3175                 if (CC(!load_pdptrs(vcpu, vcpu->arch.cr3)))
3176                         return false;
3177         }
3178
3179
3180         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
3181                 map = &vmx->nested.apic_access_page_map;
3182
3183                 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->apic_access_addr), map)) {
3184                         vmcs_write64(APIC_ACCESS_ADDR, pfn_to_hpa(map->pfn));
3185                 } else {
3186                         pr_debug_ratelimited("%s: no backing for APIC-access address in vmcs12\n",
3187                                              __func__);
3188                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3189                         vcpu->run->internal.suberror =
3190                                 KVM_INTERNAL_ERROR_EMULATION;
3191                         vcpu->run->internal.ndata = 0;
3192                         return false;
3193                 }
3194         }
3195
3196         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
3197                 map = &vmx->nested.virtual_apic_map;
3198
3199                 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->virtual_apic_page_addr), map)) {
3200                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, pfn_to_hpa(map->pfn));
3201                 } else if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING) &&
3202                            nested_cpu_has(vmcs12, CPU_BASED_CR8_STORE_EXITING) &&
3203                            !nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
3204                         /*
3205                          * The processor will never use the TPR shadow, simply
3206                          * clear the bit from the execution control.  Such a
3207                          * configuration is useless, but it happens in tests.
3208                          * For any other configuration, failing the vm entry is
3209                          * _not_ what the processor does but it's basically the
3210                          * only possibility we have.
3211                          */
3212                         exec_controls_clearbit(vmx, CPU_BASED_TPR_SHADOW);
3213                 } else {
3214                         /*
3215                          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR to
3216                          * force VM-Entry to fail.
3217                          */
3218                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, INVALID_GPA);
3219                 }
3220         }
3221
3222         if (nested_cpu_has_posted_intr(vmcs12)) {
3223                 map = &vmx->nested.pi_desc_map;
3224
3225                 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->posted_intr_desc_addr), map)) {
3226                         vmx->nested.pi_desc =
3227                                 (struct pi_desc *)(((void *)map->hva) +
3228                                 offset_in_page(vmcs12->posted_intr_desc_addr));
3229                         vmcs_write64(POSTED_INTR_DESC_ADDR,
3230                                      pfn_to_hpa(map->pfn) + offset_in_page(vmcs12->posted_intr_desc_addr));
3231                 } else {
3232                         /*
3233                          * Defer the KVM_INTERNAL_EXIT until KVM tries to
3234                          * access the contents of the VMCS12 posted interrupt
3235                          * descriptor. (Note that KVM may do this when it
3236                          * should not, per the architectural specification.)
3237                          */
3238                         vmx->nested.pi_desc = NULL;
3239                         pin_controls_clearbit(vmx, PIN_BASED_POSTED_INTR);
3240                 }
3241         }
3242         if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
3243                 exec_controls_setbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
3244         else
3245                 exec_controls_clearbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
3246
3247         return true;
3248 }
3249
3250 static bool vmx_get_nested_state_pages(struct kvm_vcpu *vcpu)
3251 {
3252         if (!nested_get_evmcs_page(vcpu)) {
3253                 pr_debug_ratelimited("%s: enlightened vmptrld failed\n",
3254                                      __func__);
3255                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3256                 vcpu->run->internal.suberror =
3257                         KVM_INTERNAL_ERROR_EMULATION;
3258                 vcpu->run->internal.ndata = 0;
3259
3260                 return false;
3261         }
3262
3263         if (is_guest_mode(vcpu) && !nested_get_vmcs12_pages(vcpu))
3264                 return false;
3265
3266         return true;
3267 }
3268
3269 static int nested_vmx_write_pml_buffer(struct kvm_vcpu *vcpu, gpa_t gpa)
3270 {
3271         struct vmcs12 *vmcs12;
3272         struct vcpu_vmx *vmx = to_vmx(vcpu);
3273         gpa_t dst;
3274
3275         if (WARN_ON_ONCE(!is_guest_mode(vcpu)))
3276                 return 0;
3277
3278         if (WARN_ON_ONCE(vmx->nested.pml_full))
3279                 return 1;
3280
3281         /*
3282          * Check if PML is enabled for the nested guest. Whether eptp bit 6 is
3283          * set is already checked as part of A/D emulation.
3284          */
3285         vmcs12 = get_vmcs12(vcpu);
3286         if (!nested_cpu_has_pml(vmcs12))
3287                 return 0;
3288
3289         if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
3290                 vmx->nested.pml_full = true;
3291                 return 1;
3292         }
3293
3294         gpa &= ~0xFFFull;
3295         dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
3296
3297         if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
3298                                  offset_in_page(dst), sizeof(gpa)))
3299                 return 0;
3300
3301         vmcs12->guest_pml_index--;
3302
3303         return 0;
3304 }
3305
3306 /*
3307  * Intel's VMX Instruction Reference specifies a common set of prerequisites
3308  * for running VMX instructions (except VMXON, whose prerequisites are
3309  * slightly different). It also specifies what exception to inject otherwise.
3310  * Note that many of these exceptions have priority over VM exits, so they
3311  * don't have to be checked again here.
3312  */
3313 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
3314 {
3315         if (!to_vmx(vcpu)->nested.vmxon) {
3316                 kvm_queue_exception(vcpu, UD_VECTOR);
3317                 return 0;
3318         }
3319
3320         if (vmx_get_cpl(vcpu)) {
3321                 kvm_inject_gp(vcpu, 0);
3322                 return 0;
3323         }
3324
3325         return 1;
3326 }
3327
3328 static u8 vmx_has_apicv_interrupt(struct kvm_vcpu *vcpu)
3329 {
3330         u8 rvi = vmx_get_rvi();
3331         u8 vppr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_PROCPRI);
3332
3333         return ((rvi & 0xf0) > (vppr & 0xf0));
3334 }
3335
3336 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
3337                                    struct vmcs12 *vmcs12);
3338
3339 /*
3340  * If from_vmentry is false, this is being called from state restore (either RSM
3341  * or KVM_SET_NESTED_STATE).  Otherwise it's called from vmlaunch/vmresume.
3342  *
3343  * Returns:
3344  *      NVMX_VMENTRY_SUCCESS: Entered VMX non-root mode
3345  *      NVMX_VMENTRY_VMFAIL:  Consistency check VMFail
3346  *      NVMX_VMENTRY_VMEXIT:  Consistency check VMExit
3347  *      NVMX_VMENTRY_KVM_INTERNAL_ERROR: KVM internal error
3348  */
3349 enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
3350                                                         bool from_vmentry)
3351 {
3352         struct vcpu_vmx *vmx = to_vmx(vcpu);
3353         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3354         enum vm_entry_failure_code entry_failure_code;
3355         bool evaluate_pending_interrupts;
3356         union vmx_exit_reason exit_reason = {
3357                 .basic = EXIT_REASON_INVALID_STATE,
3358                 .failed_vmentry = 1,
3359         };
3360         u32 failed_index;
3361
3362         kvm_service_local_tlb_flush_requests(vcpu);
3363
3364         evaluate_pending_interrupts = exec_controls_get(vmx) &
3365                 (CPU_BASED_INTR_WINDOW_EXITING | CPU_BASED_NMI_WINDOW_EXITING);
3366         if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu))
3367                 evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu);
3368
3369         if (!vmx->nested.nested_run_pending ||
3370             !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
3371                 vmx->nested.pre_vmenter_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
3372         if (kvm_mpx_supported() &&
3373             (!vmx->nested.nested_run_pending ||
3374              !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)))
3375                 vmx->nested.pre_vmenter_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
3376
3377         /*
3378          * Overwrite vmcs01.GUEST_CR3 with L1's CR3 if EPT is disabled *and*
3379          * nested early checks are disabled.  In the event of a "late" VM-Fail,
3380          * i.e. a VM-Fail detected by hardware but not KVM, KVM must unwind its
3381          * software model to the pre-VMEntry host state.  When EPT is disabled,
3382          * GUEST_CR3 holds KVM's shadow CR3, not L1's "real" CR3, which causes
3383          * nested_vmx_restore_host_state() to corrupt vcpu->arch.cr3.  Stuffing
3384          * vmcs01.GUEST_CR3 results in the unwind naturally setting arch.cr3 to
3385          * the correct value.  Smashing vmcs01.GUEST_CR3 is safe because nested
3386          * VM-Exits, and the unwind, reset KVM's MMU, i.e. vmcs01.GUEST_CR3 is
3387          * guaranteed to be overwritten with a shadow CR3 prior to re-entering
3388          * L1.  Don't stuff vmcs01.GUEST_CR3 when using nested early checks as
3389          * KVM modifies vcpu->arch.cr3 if and only if the early hardware checks
3390          * pass, and early VM-Fails do not reset KVM's MMU, i.e. the VM-Fail
3391          * path would need to manually save/restore vmcs01.GUEST_CR3.
3392          */
3393         if (!enable_ept && !nested_early_check)
3394                 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3395
3396         vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
3397
3398         prepare_vmcs02_early(vmx, &vmx->vmcs01, vmcs12);
3399
3400         if (from_vmentry) {
3401                 if (unlikely(!nested_get_vmcs12_pages(vcpu))) {
3402                         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3403                         return NVMX_VMENTRY_KVM_INTERNAL_ERROR;
3404                 }
3405
3406                 if (nested_vmx_check_vmentry_hw(vcpu)) {
3407                         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3408                         return NVMX_VMENTRY_VMFAIL;
3409                 }
3410
3411                 if (nested_vmx_check_guest_state(vcpu, vmcs12,
3412                                                  &entry_failure_code)) {
3413                         exit_reason.basic = EXIT_REASON_INVALID_STATE;
3414                         vmcs12->exit_qualification = entry_failure_code;
3415                         goto vmentry_fail_vmexit;
3416                 }
3417         }
3418
3419         enter_guest_mode(vcpu);
3420
3421         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &entry_failure_code)) {
3422                 exit_reason.basic = EXIT_REASON_INVALID_STATE;
3423                 vmcs12->exit_qualification = entry_failure_code;
3424                 goto vmentry_fail_vmexit_guest_mode;
3425         }
3426
3427         if (from_vmentry) {
3428                 failed_index = nested_vmx_load_msr(vcpu,
3429                                                    vmcs12->vm_entry_msr_load_addr,
3430                                                    vmcs12->vm_entry_msr_load_count);
3431                 if (failed_index) {
3432                         exit_reason.basic = EXIT_REASON_MSR_LOAD_FAIL;
3433                         vmcs12->exit_qualification = failed_index;
3434                         goto vmentry_fail_vmexit_guest_mode;
3435                 }
3436         } else {
3437                 /*
3438                  * The MMU is not initialized to point at the right entities yet and
3439                  * "get pages" would need to read data from the guest (i.e. we will
3440                  * need to perform gpa to hpa translation). Request a call
3441                  * to nested_get_vmcs12_pages before the next VM-entry.  The MSRs
3442                  * have already been set at vmentry time and should not be reset.
3443                  */
3444                 kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu);
3445         }
3446
3447         /*
3448          * If L1 had a pending IRQ/NMI until it executed
3449          * VMLAUNCH/VMRESUME which wasn't delivered because it was
3450          * disallowed (e.g. interrupts disabled), L0 needs to
3451          * evaluate if this pending event should cause an exit from L2
3452          * to L1 or delivered directly to L2 (e.g. In case L1 don't
3453          * intercept EXTERNAL_INTERRUPT).
3454          *
3455          * Usually this would be handled by the processor noticing an
3456          * IRQ/NMI window request, or checking RVI during evaluation of
3457          * pending virtual interrupts.  However, this setting was done
3458          * on VMCS01 and now VMCS02 is active instead. Thus, we force L0
3459          * to perform pending event evaluation by requesting a KVM_REQ_EVENT.
3460          */
3461         if (unlikely(evaluate_pending_interrupts))
3462                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3463
3464         /*
3465          * Do not start the preemption timer hrtimer until after we know
3466          * we are successful, so that only nested_vmx_vmexit needs to cancel
3467          * the timer.
3468          */
3469         vmx->nested.preemption_timer_expired = false;
3470         if (nested_cpu_has_preemption_timer(vmcs12)) {
3471                 u64 timer_value = vmx_calc_preemption_timer_value(vcpu);
3472                 vmx_start_preemption_timer(vcpu, timer_value);
3473         }
3474
3475         /*
3476          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
3477          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
3478          * returned as far as L1 is concerned. It will only return (and set
3479          * the success flag) when L2 exits (see nested_vmx_vmexit()).
3480          */
3481         return NVMX_VMENTRY_SUCCESS;
3482
3483         /*
3484          * A failed consistency check that leads to a VMExit during L1's
3485          * VMEnter to L2 is a variation of a normal VMexit, as explained in
3486          * 26.7 "VM-entry failures during or after loading guest state".
3487          */
3488 vmentry_fail_vmexit_guest_mode:
3489         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)
3490                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
3491         leave_guest_mode(vcpu);
3492
3493 vmentry_fail_vmexit:
3494         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3495
3496         if (!from_vmentry)
3497                 return NVMX_VMENTRY_VMEXIT;
3498
3499         load_vmcs12_host_state(vcpu, vmcs12);
3500         vmcs12->vm_exit_reason = exit_reason.full;
3501         if (enable_shadow_vmcs || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
3502                 vmx->nested.need_vmcs12_to_shadow_sync = true;
3503         return NVMX_VMENTRY_VMEXIT;
3504 }
3505
3506 /*
3507  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
3508  * for running an L2 nested guest.
3509  */
3510 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
3511 {
3512         struct vmcs12 *vmcs12;
3513         enum nvmx_vmentry_status status;
3514         struct vcpu_vmx *vmx = to_vmx(vcpu);
3515         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
3516         enum nested_evmptrld_status evmptrld_status;
3517
3518         if (!nested_vmx_check_permission(vcpu))
3519                 return 1;
3520
3521         evmptrld_status = nested_vmx_handle_enlightened_vmptrld(vcpu, launch);
3522         if (evmptrld_status == EVMPTRLD_ERROR) {
3523                 kvm_queue_exception(vcpu, UD_VECTOR);
3524                 return 1;
3525         }
3526
3527         kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
3528
3529         if (CC(evmptrld_status == EVMPTRLD_VMFAIL))
3530                 return nested_vmx_failInvalid(vcpu);
3531
3532         if (CC(!evmptr_is_valid(vmx->nested.hv_evmcs_vmptr) &&
3533                vmx->nested.current_vmptr == INVALID_GPA))
3534                 return nested_vmx_failInvalid(vcpu);
3535
3536         vmcs12 = get_vmcs12(vcpu);
3537
3538         /*
3539          * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact
3540          * that there *is* a valid VMCS pointer, RFLAGS.CF is set
3541          * rather than RFLAGS.ZF, and no error number is stored to the
3542          * VM-instruction error field.
3543          */
3544         if (CC(vmcs12->hdr.shadow_vmcs))
3545                 return nested_vmx_failInvalid(vcpu);
3546
3547         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) {
3548                 copy_enlightened_to_vmcs12(vmx, vmx->nested.hv_evmcs->hv_clean_fields);
3549                 /* Enlightened VMCS doesn't have launch state */
3550                 vmcs12->launch_state = !launch;
3551         } else if (enable_shadow_vmcs) {
3552                 copy_shadow_to_vmcs12(vmx);
3553         }
3554
3555         /*
3556          * The nested entry process starts with enforcing various prerequisites
3557          * on vmcs12 as required by the Intel SDM, and act appropriately when
3558          * they fail: As the SDM explains, some conditions should cause the
3559          * instruction to fail, while others will cause the instruction to seem
3560          * to succeed, but return an EXIT_REASON_INVALID_STATE.
3561          * To speed up the normal (success) code path, we should avoid checking
3562          * for misconfigurations which will anyway be caught by the processor
3563          * when using the merged vmcs02.
3564          */
3565         if (CC(interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS))
3566                 return nested_vmx_fail(vcpu, VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
3567
3568         if (CC(vmcs12->launch_state == launch))
3569                 return nested_vmx_fail(vcpu,
3570                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
3571                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
3572
3573         if (nested_vmx_check_controls(vcpu, vmcs12))
3574                 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3575
3576         if (nested_vmx_check_address_space_size(vcpu, vmcs12))
3577                 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
3578
3579         if (nested_vmx_check_host_state(vcpu, vmcs12))
3580                 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
3581
3582         /*
3583          * We're finally done with prerequisite checking, and can start with
3584          * the nested entry.
3585          */
3586         vmx->nested.nested_run_pending = 1;
3587         vmx->nested.has_preemption_timer_deadline = false;
3588         status = nested_vmx_enter_non_root_mode(vcpu, true);
3589         if (unlikely(status != NVMX_VMENTRY_SUCCESS))
3590                 goto vmentry_failed;
3591
3592         /* Emulate processing of posted interrupts on VM-Enter. */
3593         if (nested_cpu_has_posted_intr(vmcs12) &&
3594             kvm_apic_has_interrupt(vcpu) == vmx->nested.posted_intr_nv) {
3595                 vmx->nested.pi_pending = true;
3596                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3597                 kvm_apic_clear_irr(vcpu, vmx->nested.posted_intr_nv);
3598         }
3599
3600         /* Hide L1D cache contents from the nested guest.  */
3601         vmx->vcpu.arch.l1tf_flush_l1d = true;
3602
3603         /*
3604          * Must happen outside of nested_vmx_enter_non_root_mode() as it will
3605          * also be used as part of restoring nVMX state for
3606          * snapshot restore (migration).
3607          *
3608          * In this flow, it is assumed that vmcs12 cache was
3609          * transferred as part of captured nVMX state and should
3610          * therefore not be read from guest memory (which may not
3611          * exist on destination host yet).
3612          */
3613         nested_cache_shadow_vmcs12(vcpu, vmcs12);
3614
3615         switch (vmcs12->guest_activity_state) {
3616         case GUEST_ACTIVITY_HLT:
3617                 /*
3618                  * If we're entering a halted L2 vcpu and the L2 vcpu won't be
3619                  * awakened by event injection or by an NMI-window VM-exit or
3620                  * by an interrupt-window VM-exit, halt the vcpu.
3621                  */
3622                 if (!(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) &&
3623                     !nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING) &&
3624                     !(nested_cpu_has(vmcs12, CPU_BASED_INTR_WINDOW_EXITING) &&
3625                       (vmcs12->guest_rflags & X86_EFLAGS_IF))) {
3626                         vmx->nested.nested_run_pending = 0;
3627                         return kvm_emulate_halt_noskip(vcpu);
3628                 }
3629                 break;
3630         case GUEST_ACTIVITY_WAIT_SIPI:
3631                 vmx->nested.nested_run_pending = 0;
3632                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
3633                 break;
3634         default:
3635                 break;
3636         }
3637
3638         return 1;
3639
3640 vmentry_failed:
3641         vmx->nested.nested_run_pending = 0;
3642         if (status == NVMX_VMENTRY_KVM_INTERNAL_ERROR)
3643                 return 0;
3644         if (status == NVMX_VMENTRY_VMEXIT)
3645                 return 1;
3646         WARN_ON_ONCE(status != NVMX_VMENTRY_VMFAIL);
3647         return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3648 }
3649
3650 /*
3651  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
3652  * because L2 may have changed some cr0 bits directly (CR0_GUEST_HOST_MASK).
3653  * This function returns the new value we should put in vmcs12.guest_cr0.
3654  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
3655  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
3656  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
3657  *     didn't trap the bit, because if L1 did, so would L0).
3658  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
3659  *     been modified by L2, and L1 knows it. So just leave the old value of
3660  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
3661  *     isn't relevant, because if L0 traps this bit it can set it to anything.
3662  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
3663  *     changed these bits, and therefore they need to be updated, but L0
3664  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
3665  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
3666  */
3667 static inline unsigned long
3668 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
3669 {
3670         return
3671         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
3672         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
3673         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
3674                         vcpu->arch.cr0_guest_owned_bits));
3675 }
3676
3677 static inline unsigned long
3678 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
3679 {
3680         return
3681         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
3682         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
3683         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
3684                         vcpu->arch.cr4_guest_owned_bits));
3685 }
3686
3687 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
3688                                       struct vmcs12 *vmcs12,
3689                                       u32 vm_exit_reason, u32 exit_intr_info)
3690 {
3691         u32 idt_vectoring;
3692         unsigned int nr;
3693
3694         /*
3695          * Per the SDM, VM-Exits due to double and triple faults are never
3696          * considered to occur during event delivery, even if the double/triple
3697          * fault is the result of an escalating vectoring issue.
3698          *
3699          * Note, the SDM qualifies the double fault behavior with "The original
3700          * event results in a double-fault exception".  It's unclear why the
3701          * qualification exists since exits due to double fault can occur only
3702          * while vectoring a different exception (injected events are never
3703          * subject to interception), i.e. there's _always_ an original event.
3704          *
3705          * The SDM also uses NMI as a confusing example for the "original event
3706          * causes the VM exit directly" clause.  NMI isn't special in any way,
3707          * the same rule applies to all events that cause an exit directly.
3708          * NMI is an odd choice for the example because NMIs can only occur on
3709          * instruction boundaries, i.e. they _can't_ occur during vectoring.
3710          */
3711         if ((u16)vm_exit_reason == EXIT_REASON_TRIPLE_FAULT ||
3712             ((u16)vm_exit_reason == EXIT_REASON_EXCEPTION_NMI &&
3713              is_double_fault(exit_intr_info))) {
3714                 vmcs12->idt_vectoring_info_field = 0;
3715         } else if (vcpu->arch.exception.injected) {
3716                 nr = vcpu->arch.exception.nr;
3717                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
3718
3719                 if (kvm_exception_is_soft(nr)) {
3720                         vmcs12->vm_exit_instruction_len =
3721                                 vcpu->arch.event_exit_inst_len;
3722                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
3723                 } else
3724                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
3725
3726                 if (vcpu->arch.exception.has_error_code) {
3727                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
3728                         vmcs12->idt_vectoring_error_code =
3729                                 vcpu->arch.exception.error_code;
3730                 }
3731
3732                 vmcs12->idt_vectoring_info_field = idt_vectoring;
3733         } else if (vcpu->arch.nmi_injected) {
3734                 vmcs12->idt_vectoring_info_field =
3735                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
3736         } else if (vcpu->arch.interrupt.injected) {
3737                 nr = vcpu->arch.interrupt.nr;
3738                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
3739
3740                 if (vcpu->arch.interrupt.soft) {
3741                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
3742                         vmcs12->vm_entry_instruction_len =
3743                                 vcpu->arch.event_exit_inst_len;
3744                 } else
3745                         idt_vectoring |= INTR_TYPE_EXT_INTR;
3746
3747                 vmcs12->idt_vectoring_info_field = idt_vectoring;
3748         } else {
3749                 vmcs12->idt_vectoring_info_field = 0;
3750         }
3751 }
3752
3753
3754 void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
3755 {
3756         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3757         gfn_t gfn;
3758
3759         /*
3760          * Don't need to mark the APIC access page dirty; it is never
3761          * written to by the CPU during APIC virtualization.
3762          */
3763
3764         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
3765                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
3766                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3767         }
3768
3769         if (nested_cpu_has_posted_intr(vmcs12)) {
3770                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
3771                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3772         }
3773 }
3774
3775 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
3776 {
3777         struct vcpu_vmx *vmx = to_vmx(vcpu);
3778         int max_irr;
3779         void *vapic_page;
3780         u16 status;
3781
3782         if (!vmx->nested.pi_pending)
3783                 return 0;
3784
3785         if (!vmx->nested.pi_desc)
3786                 goto mmio_needed;
3787
3788         vmx->nested.pi_pending = false;
3789
3790         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
3791                 return 0;
3792
3793         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
3794         if (max_irr != 256) {
3795                 vapic_page = vmx->nested.virtual_apic_map.hva;
3796                 if (!vapic_page)
3797                         goto mmio_needed;
3798
3799                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
3800                         vapic_page, &max_irr);
3801                 status = vmcs_read16(GUEST_INTR_STATUS);
3802                 if ((u8)max_irr > ((u8)status & 0xff)) {
3803                         status &= ~0xff;
3804                         status |= (u8)max_irr;
3805                         vmcs_write16(GUEST_INTR_STATUS, status);
3806                 }
3807         }
3808
3809         nested_mark_vmcs12_pages_dirty(vcpu);
3810         return 0;
3811
3812 mmio_needed:
3813         kvm_handle_memory_failure(vcpu, X86EMUL_IO_NEEDED, NULL);
3814         return -ENXIO;
3815 }
3816
3817 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
3818                                                unsigned long exit_qual)
3819 {
3820         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3821         unsigned int nr = vcpu->arch.exception.nr;
3822         u32 intr_info = nr | INTR_INFO_VALID_MASK;
3823
3824         if (vcpu->arch.exception.has_error_code) {
3825                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
3826                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3827         }
3828
3829         if (kvm_exception_is_soft(nr))
3830                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3831         else
3832                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3833
3834         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
3835             vmx_get_nmi_mask(vcpu))
3836                 intr_info |= INTR_INFO_UNBLOCK_NMI;
3837
3838         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
3839 }
3840
3841 /*
3842  * Returns true if a debug trap is pending delivery.
3843  *
3844  * In KVM, debug traps bear an exception payload. As such, the class of a #DB
3845  * exception may be inferred from the presence of an exception payload.
3846  */
3847 static inline bool vmx_pending_dbg_trap(struct kvm_vcpu *vcpu)
3848 {
3849         return vcpu->arch.exception.pending &&
3850                         vcpu->arch.exception.nr == DB_VECTOR &&
3851                         vcpu->arch.exception.payload;
3852 }
3853
3854 /*
3855  * Certain VM-exits set the 'pending debug exceptions' field to indicate a
3856  * recognized #DB (data or single-step) that has yet to be delivered. Since KVM
3857  * represents these debug traps with a payload that is said to be compatible
3858  * with the 'pending debug exceptions' field, write the payload to the VMCS
3859  * field if a VM-exit is delivered before the debug trap.
3860  */
3861 static void nested_vmx_update_pending_dbg(struct kvm_vcpu *vcpu)
3862 {
3863         if (vmx_pending_dbg_trap(vcpu))
3864                 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
3865                             vcpu->arch.exception.payload);
3866 }
3867
3868 static bool nested_vmx_preemption_timer_pending(struct kvm_vcpu *vcpu)
3869 {
3870         return nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
3871                to_vmx(vcpu)->nested.preemption_timer_expired;
3872 }
3873
3874 static int vmx_check_nested_events(struct kvm_vcpu *vcpu)
3875 {
3876         struct vcpu_vmx *vmx = to_vmx(vcpu);
3877         unsigned long exit_qual;
3878         bool block_nested_events =
3879             vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
3880         bool mtf_pending = vmx->nested.mtf_pending;
3881         struct kvm_lapic *apic = vcpu->arch.apic;
3882
3883         /*
3884          * Clear the MTF state. If a higher priority VM-exit is delivered first,
3885          * this state is discarded.
3886          */
3887         if (!block_nested_events)
3888                 vmx->nested.mtf_pending = false;
3889
3890         if (lapic_in_kernel(vcpu) &&
3891                 test_bit(KVM_APIC_INIT, &apic->pending_events)) {
3892                 if (block_nested_events)
3893                         return -EBUSY;
3894                 nested_vmx_update_pending_dbg(vcpu);
3895                 clear_bit(KVM_APIC_INIT, &apic->pending_events);
3896                 if (vcpu->arch.mp_state != KVM_MP_STATE_INIT_RECEIVED)
3897                         nested_vmx_vmexit(vcpu, EXIT_REASON_INIT_SIGNAL, 0, 0);
3898                 return 0;
3899         }
3900
3901         if (lapic_in_kernel(vcpu) &&
3902             test_bit(KVM_APIC_SIPI, &apic->pending_events)) {
3903                 if (block_nested_events)
3904                         return -EBUSY;
3905
3906                 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
3907                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3908                         nested_vmx_vmexit(vcpu, EXIT_REASON_SIPI_SIGNAL, 0,
3909                                                 apic->sipi_vector & 0xFFUL);
3910                 return 0;
3911         }
3912
3913         /*
3914          * Process any exceptions that are not debug traps before MTF.
3915          *
3916          * Note that only a pending nested run can block a pending exception.
3917          * Otherwise an injected NMI/interrupt should either be
3918          * lost or delivered to the nested hypervisor in the IDT_VECTORING_INFO,
3919          * while delivering the pending exception.
3920          */
3921
3922         if (vcpu->arch.exception.pending && !vmx_pending_dbg_trap(vcpu)) {
3923                 if (vmx->nested.nested_run_pending)
3924                         return -EBUSY;
3925                 if (!nested_vmx_check_exception(vcpu, &exit_qual))
3926                         goto no_vmexit;
3927                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
3928                 return 0;
3929         }
3930
3931         if (mtf_pending) {
3932                 if (block_nested_events)
3933                         return -EBUSY;
3934                 nested_vmx_update_pending_dbg(vcpu);
3935                 nested_vmx_vmexit(vcpu, EXIT_REASON_MONITOR_TRAP_FLAG, 0, 0);
3936                 return 0;
3937         }
3938
3939         if (vcpu->arch.exception.pending) {
3940                 if (vmx->nested.nested_run_pending)
3941                         return -EBUSY;
3942                 if (!nested_vmx_check_exception(vcpu, &exit_qual))
3943                         goto no_vmexit;
3944                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
3945                 return 0;
3946         }
3947
3948         if (nested_vmx_preemption_timer_pending(vcpu)) {
3949                 if (block_nested_events)
3950                         return -EBUSY;
3951                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
3952                 return 0;
3953         }
3954
3955         if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
3956                 if (block_nested_events)
3957                         return -EBUSY;
3958                 goto no_vmexit;
3959         }
3960
3961         if (vcpu->arch.nmi_pending && !vmx_nmi_blocked(vcpu)) {
3962                 if (block_nested_events)
3963                         return -EBUSY;
3964                 if (!nested_exit_on_nmi(vcpu))
3965                         goto no_vmexit;
3966
3967                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
3968                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
3969                                   INTR_INFO_VALID_MASK, 0);
3970                 /*
3971                  * The NMI-triggered VM exit counts as injection:
3972                  * clear this one and block further NMIs.
3973                  */
3974                 vcpu->arch.nmi_pending = 0;
3975                 vmx_set_nmi_mask(vcpu, true);
3976                 return 0;
3977         }
3978
3979         if (kvm_cpu_has_interrupt(vcpu) && !vmx_interrupt_blocked(vcpu)) {
3980                 if (block_nested_events)
3981                         return -EBUSY;
3982                 if (!nested_exit_on_intr(vcpu))
3983                         goto no_vmexit;
3984                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
3985                 return 0;
3986         }
3987
3988 no_vmexit:
3989         return vmx_complete_nested_posted_interrupt(vcpu);
3990 }
3991
3992 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
3993 {
3994         ktime_t remaining =
3995                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
3996         u64 value;
3997
3998         if (ktime_to_ns(remaining) <= 0)
3999                 return 0;
4000
4001         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
4002         do_div(value, 1000000);
4003         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
4004 }
4005
4006 static bool is_vmcs12_ext_field(unsigned long field)
4007 {
4008         switch (field) {
4009         case GUEST_ES_SELECTOR:
4010         case GUEST_CS_SELECTOR:
4011         case GUEST_SS_SELECTOR:
4012         case GUEST_DS_SELECTOR:
4013         case GUEST_FS_SELECTOR:
4014         case GUEST_GS_SELECTOR:
4015         case GUEST_LDTR_SELECTOR:
4016         case GUEST_TR_SELECTOR:
4017         case GUEST_ES_LIMIT:
4018         case GUEST_CS_LIMIT:
4019         case GUEST_SS_LIMIT:
4020         case GUEST_DS_LIMIT:
4021         case GUEST_FS_LIMIT:
4022         case GUEST_GS_LIMIT:
4023         case GUEST_LDTR_LIMIT:
4024         case GUEST_TR_LIMIT:
4025         case GUEST_GDTR_LIMIT:
4026         case GUEST_IDTR_LIMIT:
4027         case GUEST_ES_AR_BYTES:
4028         case GUEST_DS_AR_BYTES:
4029         case GUEST_FS_AR_BYTES:
4030         case GUEST_GS_AR_BYTES:
4031         case GUEST_LDTR_AR_BYTES:
4032         case GUEST_TR_AR_BYTES:
4033         case GUEST_ES_BASE:
4034         case GUEST_CS_BASE:
4035         case GUEST_SS_BASE:
4036         case GUEST_DS_BASE:
4037         case GUEST_FS_BASE:
4038         case GUEST_GS_BASE:
4039         case GUEST_LDTR_BASE:
4040         case GUEST_TR_BASE:
4041         case GUEST_GDTR_BASE:
4042         case GUEST_IDTR_BASE:
4043         case GUEST_PENDING_DBG_EXCEPTIONS:
4044         case GUEST_BNDCFGS:
4045                 return true;
4046         default:
4047                 break;
4048         }
4049
4050         return false;
4051 }
4052
4053 static void sync_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu,
4054                                        struct vmcs12 *vmcs12)
4055 {
4056         struct vcpu_vmx *vmx = to_vmx(vcpu);
4057
4058         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
4059         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
4060         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
4061         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
4062         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
4063         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
4064         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
4065         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
4066         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
4067         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
4068         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
4069         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
4070         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
4071         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
4072         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
4073         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
4074         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
4075         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
4076         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
4077         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
4078         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
4079         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
4080         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
4081         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
4082         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
4083         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
4084         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
4085         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
4086         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
4087         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
4088         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
4089         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
4090         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
4091         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
4092         vmcs12->guest_pending_dbg_exceptions =
4093                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
4094
4095         vmx->nested.need_sync_vmcs02_to_vmcs12_rare = false;
4096 }
4097
4098 static void copy_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu,
4099                                        struct vmcs12 *vmcs12)
4100 {
4101         struct vcpu_vmx *vmx = to_vmx(vcpu);
4102         int cpu;
4103
4104         if (!vmx->nested.need_sync_vmcs02_to_vmcs12_rare)
4105                 return;
4106
4107
4108         WARN_ON_ONCE(vmx->loaded_vmcs != &vmx->vmcs01);
4109
4110         cpu = get_cpu();
4111         vmx->loaded_vmcs = &vmx->nested.vmcs02;
4112         vmx_vcpu_load_vmcs(vcpu, cpu, &vmx->vmcs01);
4113
4114         sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
4115
4116         vmx->loaded_vmcs = &vmx->vmcs01;
4117         vmx_vcpu_load_vmcs(vcpu, cpu, &vmx->nested.vmcs02);
4118         put_cpu();
4119 }
4120
4121 /*
4122  * Update the guest state fields of vmcs12 to reflect changes that
4123  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
4124  * VM-entry controls is also updated, since this is really a guest
4125  * state bit.)
4126  */
4127 static void sync_vmcs02_to_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4128 {
4129         struct vcpu_vmx *vmx = to_vmx(vcpu);
4130
4131         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
4132                 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
4133
4134         vmx->nested.need_sync_vmcs02_to_vmcs12_rare =
4135                 !evmptr_is_valid(vmx->nested.hv_evmcs_vmptr);
4136
4137         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
4138         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
4139
4140         vmcs12->guest_rsp = kvm_rsp_read(vcpu);
4141         vmcs12->guest_rip = kvm_rip_read(vcpu);
4142         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
4143
4144         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
4145         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
4146
4147         vmcs12->guest_interruptibility_info =
4148                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
4149
4150         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
4151                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
4152         else if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4153                 vmcs12->guest_activity_state = GUEST_ACTIVITY_WAIT_SIPI;
4154         else
4155                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4156
4157         if (nested_cpu_has_preemption_timer(vmcs12) &&
4158             vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER &&
4159             !vmx->nested.nested_run_pending)
4160                 vmcs12->vmx_preemption_timer_value =
4161                         vmx_get_preemption_timer_value(vcpu);
4162
4163         /*
4164          * In some cases (usually, nested EPT), L2 is allowed to change its
4165          * own CR3 without exiting. If it has changed it, we must keep it.
4166          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
4167          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
4168          *
4169          * Additionally, restore L2's PDPTR to vmcs12.
4170          */
4171         if (enable_ept) {
4172                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
4173                 if (nested_cpu_has_ept(vmcs12) && is_pae_paging(vcpu)) {
4174                         vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
4175                         vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
4176                         vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
4177                         vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
4178                 }
4179         }
4180
4181         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
4182
4183         if (nested_cpu_has_vid(vmcs12))
4184                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
4185
4186         vmcs12->vm_entry_controls =
4187                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
4188                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
4189
4190         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS)
4191                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
4192
4193         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
4194                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4195 }
4196
4197 /*
4198  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
4199  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
4200  * and this function updates it to reflect the changes to the guest state while
4201  * L2 was running (and perhaps made some exits which were handled directly by L0
4202  * without going back to L1), and to reflect the exit reason.
4203  * Note that we do not have to copy here all VMCS fields, just those that
4204  * could have changed by the L2 guest or the exit - i.e., the guest-state and
4205  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
4206  * which already writes to vmcs12 directly.
4207  */
4208 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
4209                            u32 vm_exit_reason, u32 exit_intr_info,
4210                            unsigned long exit_qualification)
4211 {
4212         /* update exit information fields: */
4213         vmcs12->vm_exit_reason = vm_exit_reason;
4214         if (to_vmx(vcpu)->exit_reason.enclave_mode)
4215                 vmcs12->vm_exit_reason |= VMX_EXIT_REASONS_SGX_ENCLAVE_MODE;
4216         vmcs12->exit_qualification = exit_qualification;
4217
4218         /*
4219          * On VM-Exit due to a failed VM-Entry, the VMCS isn't marked launched
4220          * and only EXIT_REASON and EXIT_QUALIFICATION are updated, all other
4221          * exit info fields are unmodified.
4222          */
4223         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
4224                 vmcs12->launch_state = 1;
4225
4226                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
4227                  * instead of reading the real value. */
4228                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
4229
4230                 /*
4231                  * Transfer the event that L0 or L1 may wanted to inject into
4232                  * L2 to IDT_VECTORING_INFO_FIELD.
4233                  */
4234                 vmcs12_save_pending_event(vcpu, vmcs12,
4235                                           vm_exit_reason, exit_intr_info);
4236
4237                 vmcs12->vm_exit_intr_info = exit_intr_info;
4238                 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4239                 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
4240
4241                 /*
4242                  * According to spec, there's no need to store the guest's
4243                  * MSRs if the exit is due to a VM-entry failure that occurs
4244                  * during or after loading the guest state. Since this exit
4245                  * does not fall in that category, we need to save the MSRs.
4246                  */
4247                 if (nested_vmx_store_msr(vcpu,
4248                                          vmcs12->vm_exit_msr_store_addr,
4249                                          vmcs12->vm_exit_msr_store_count))
4250                         nested_vmx_abort(vcpu,
4251                                          VMX_ABORT_SAVE_GUEST_MSR_FAIL);
4252         }
4253
4254         /*
4255          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
4256          * preserved above and would only end up incorrectly in L1.
4257          */
4258         vcpu->arch.nmi_injected = false;
4259         kvm_clear_exception_queue(vcpu);
4260         kvm_clear_interrupt_queue(vcpu);
4261 }
4262
4263 /*
4264  * A part of what we need to when the nested L2 guest exits and we want to
4265  * run its L1 parent, is to reset L1's guest state to the host state specified
4266  * in vmcs12.
4267  * This function is to be called not only on normal nested exit, but also on
4268  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
4269  * Failures During or After Loading Guest State").
4270  * This function should be called when the active VMCS is L1's (vmcs01).
4271  */
4272 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
4273                                    struct vmcs12 *vmcs12)
4274 {
4275         enum vm_entry_failure_code ignored;
4276         struct kvm_segment seg;
4277
4278         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
4279                 vcpu->arch.efer = vmcs12->host_ia32_efer;
4280         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4281                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
4282         else
4283                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
4284         vmx_set_efer(vcpu, vcpu->arch.efer);
4285
4286         kvm_rsp_write(vcpu, vmcs12->host_rsp);
4287         kvm_rip_write(vcpu, vmcs12->host_rip);
4288         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4289         vmx_set_interrupt_shadow(vcpu, 0);
4290
4291         /*
4292          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
4293          * actually changed, because vmx_set_cr0 refers to efer set above.
4294          *
4295          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
4296          * (KVM doesn't change it);
4297          */
4298         vcpu->arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4299         vmx_set_cr0(vcpu, vmcs12->host_cr0);
4300
4301         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
4302         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
4303         vmx_set_cr4(vcpu, vmcs12->host_cr4);
4304
4305         nested_ept_uninit_mmu_context(vcpu);
4306
4307         /*
4308          * Only PDPTE load can fail as the value of cr3 was checked on entry and
4309          * couldn't have changed.
4310          */
4311         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, true, &ignored))
4312                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
4313
4314         nested_vmx_transition_tlb_flush(vcpu, vmcs12, false);
4315
4316         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
4317         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
4318         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
4319         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
4320         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4321         vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
4322         vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
4323
4324         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
4325         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
4326                 vmcs_write64(GUEST_BNDCFGS, 0);
4327
4328         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4329                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
4330                 vcpu->arch.pat = vmcs12->host_ia32_pat;
4331         }
4332         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
4333                 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
4334                                          vmcs12->host_ia32_perf_global_ctrl));
4335
4336         /* Set L1 segment info according to Intel SDM
4337             27.5.2 Loading Host Segment and Descriptor-Table Registers */
4338         seg = (struct kvm_segment) {
4339                 .base = 0,
4340                 .limit = 0xFFFFFFFF,
4341                 .selector = vmcs12->host_cs_selector,
4342                 .type = 11,
4343                 .present = 1,
4344                 .s = 1,
4345                 .g = 1
4346         };
4347         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4348                 seg.l = 1;
4349         else
4350                 seg.db = 1;
4351         __vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
4352         seg = (struct kvm_segment) {
4353                 .base = 0,
4354                 .limit = 0xFFFFFFFF,
4355                 .type = 3,
4356                 .present = 1,
4357                 .s = 1,
4358                 .db = 1,
4359                 .g = 1
4360         };
4361         seg.selector = vmcs12->host_ds_selector;
4362         __vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
4363         seg.selector = vmcs12->host_es_selector;
4364         __vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
4365         seg.selector = vmcs12->host_ss_selector;
4366         __vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
4367         seg.selector = vmcs12->host_fs_selector;
4368         seg.base = vmcs12->host_fs_base;
4369         __vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
4370         seg.selector = vmcs12->host_gs_selector;
4371         seg.base = vmcs12->host_gs_base;
4372         __vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
4373         seg = (struct kvm_segment) {
4374                 .base = vmcs12->host_tr_base,
4375                 .limit = 0x67,
4376                 .selector = vmcs12->host_tr_selector,
4377                 .type = 11,
4378                 .present = 1
4379         };
4380         __vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
4381
4382         memset(&seg, 0, sizeof(seg));
4383         seg.unusable = 1;
4384         __vmx_set_segment(vcpu, &seg, VCPU_SREG_LDTR);
4385
4386         kvm_set_dr(vcpu, 7, 0x400);
4387         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4388
4389         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
4390                                 vmcs12->vm_exit_msr_load_count))
4391                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4392
4393         to_vmx(vcpu)->emulation_required = vmx_emulation_required(vcpu);
4394 }
4395
4396 static inline u64 nested_vmx_get_vmcs01_guest_efer(struct vcpu_vmx *vmx)
4397 {
4398         struct vmx_uret_msr *efer_msr;
4399         unsigned int i;
4400
4401         if (vm_entry_controls_get(vmx) & VM_ENTRY_LOAD_IA32_EFER)
4402                 return vmcs_read64(GUEST_IA32_EFER);
4403
4404         if (cpu_has_load_ia32_efer())
4405                 return host_efer;
4406
4407         for (i = 0; i < vmx->msr_autoload.guest.nr; ++i) {
4408                 if (vmx->msr_autoload.guest.val[i].index == MSR_EFER)
4409                         return vmx->msr_autoload.guest.val[i].value;
4410         }
4411
4412         efer_msr = vmx_find_uret_msr(vmx, MSR_EFER);
4413         if (efer_msr)
4414                 return efer_msr->data;
4415
4416         return host_efer;
4417 }
4418
4419 static void nested_vmx_restore_host_state(struct kvm_vcpu *vcpu)
4420 {
4421         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4422         struct vcpu_vmx *vmx = to_vmx(vcpu);
4423         struct vmx_msr_entry g, h;
4424         gpa_t gpa;
4425         u32 i, j;
4426
4427         vcpu->arch.pat = vmcs_read64(GUEST_IA32_PAT);
4428
4429         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
4430                 /*
4431                  * L1's host DR7 is lost if KVM_GUESTDBG_USE_HW_BP is set
4432                  * as vmcs01.GUEST_DR7 contains a userspace defined value
4433                  * and vcpu->arch.dr7 is not squirreled away before the
4434                  * nested VMENTER (not worth adding a variable in nested_vmx).
4435                  */
4436                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
4437                         kvm_set_dr(vcpu, 7, DR7_FIXED_1);
4438                 else
4439                         WARN_ON(kvm_set_dr(vcpu, 7, vmcs_readl(GUEST_DR7)));
4440         }
4441
4442         /*
4443          * Note that calling vmx_set_{efer,cr0,cr4} is important as they
4444          * handle a variety of side effects to KVM's software model.
4445          */
4446         vmx_set_efer(vcpu, nested_vmx_get_vmcs01_guest_efer(vmx));
4447
4448         vcpu->arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4449         vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW));
4450
4451         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
4452         vmx_set_cr4(vcpu, vmcs_readl(CR4_READ_SHADOW));
4453
4454         nested_ept_uninit_mmu_context(vcpu);
4455         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4456         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
4457
4458         /*
4459          * Use ept_save_pdptrs(vcpu) to load the MMU's cached PDPTRs
4460          * from vmcs01 (if necessary).  The PDPTRs are not loaded on
4461          * VMFail, like everything else we just need to ensure our
4462          * software model is up-to-date.
4463          */
4464         if (enable_ept && is_pae_paging(vcpu))
4465                 ept_save_pdptrs(vcpu);
4466
4467         kvm_mmu_reset_context(vcpu);
4468
4469         /*
4470          * This nasty bit of open coding is a compromise between blindly
4471          * loading L1's MSRs using the exit load lists (incorrect emulation
4472          * of VMFail), leaving the nested VM's MSRs in the software model
4473          * (incorrect behavior) and snapshotting the modified MSRs (too
4474          * expensive since the lists are unbound by hardware).  For each
4475          * MSR that was (prematurely) loaded from the nested VMEntry load
4476          * list, reload it from the exit load list if it exists and differs
4477          * from the guest value.  The intent is to stuff host state as
4478          * silently as possible, not to fully process the exit load list.
4479          */
4480         for (i = 0; i < vmcs12->vm_entry_msr_load_count; i++) {
4481                 gpa = vmcs12->vm_entry_msr_load_addr + (i * sizeof(g));
4482                 if (kvm_vcpu_read_guest(vcpu, gpa, &g, sizeof(g))) {
4483                         pr_debug_ratelimited(
4484                                 "%s read MSR index failed (%u, 0x%08llx)\n",
4485                                 __func__, i, gpa);
4486                         goto vmabort;
4487                 }
4488
4489                 for (j = 0; j < vmcs12->vm_exit_msr_load_count; j++) {
4490                         gpa = vmcs12->vm_exit_msr_load_addr + (j * sizeof(h));
4491                         if (kvm_vcpu_read_guest(vcpu, gpa, &h, sizeof(h))) {
4492                                 pr_debug_ratelimited(
4493                                         "%s read MSR failed (%u, 0x%08llx)\n",
4494                                         __func__, j, gpa);
4495                                 goto vmabort;
4496                         }
4497                         if (h.index != g.index)
4498                                 continue;
4499                         if (h.value == g.value)
4500                                 break;
4501
4502                         if (nested_vmx_load_msr_check(vcpu, &h)) {
4503                                 pr_debug_ratelimited(
4504                                         "%s check failed (%u, 0x%x, 0x%x)\n",
4505                                         __func__, j, h.index, h.reserved);
4506                                 goto vmabort;
4507                         }
4508
4509                         if (kvm_set_msr(vcpu, h.index, h.value)) {
4510                                 pr_debug_ratelimited(
4511                                         "%s WRMSR failed (%u, 0x%x, 0x%llx)\n",
4512                                         __func__, j, h.index, h.value);
4513                                 goto vmabort;
4514                         }
4515                 }
4516         }
4517
4518         return;
4519
4520 vmabort:
4521         nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4522 }
4523
4524 /*
4525  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
4526  * and modify vmcs12 to make it see what it would expect to see there if
4527  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
4528  */
4529 void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason,
4530                        u32 exit_intr_info, unsigned long exit_qualification)
4531 {
4532         struct vcpu_vmx *vmx = to_vmx(vcpu);
4533         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4534
4535         /* trying to cancel vmlaunch/vmresume is a bug */
4536         WARN_ON_ONCE(vmx->nested.nested_run_pending);
4537
4538         if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
4539                 /*
4540                  * KVM_REQ_GET_NESTED_STATE_PAGES is also used to map
4541                  * Enlightened VMCS after migration and we still need to
4542                  * do that when something is forcing L2->L1 exit prior to
4543                  * the first L2 run.
4544                  */
4545                 (void)nested_get_evmcs_page(vcpu);
4546         }
4547
4548         /* Service pending TLB flush requests for L2 before switching to L1. */
4549         kvm_service_local_tlb_flush_requests(vcpu);
4550
4551         /*
4552          * VCPU_EXREG_PDPTR will be clobbered in arch/x86/kvm/vmx/vmx.h between
4553          * now and the new vmentry.  Ensure that the VMCS02 PDPTR fields are
4554          * up-to-date before switching to L1.
4555          */
4556         if (enable_ept && is_pae_paging(vcpu))
4557                 vmx_ept_load_pdptrs(vcpu);
4558
4559         leave_guest_mode(vcpu);
4560
4561         if (nested_cpu_has_preemption_timer(vmcs12))
4562                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
4563
4564         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING)) {
4565                 vcpu->arch.tsc_offset = vcpu->arch.l1_tsc_offset;
4566                 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
4567                         vcpu->arch.tsc_scaling_ratio = vcpu->arch.l1_tsc_scaling_ratio;
4568         }
4569
4570         if (likely(!vmx->fail)) {
4571                 sync_vmcs02_to_vmcs12(vcpu, vmcs12);
4572
4573                 if (vm_exit_reason != -1)
4574                         prepare_vmcs12(vcpu, vmcs12, vm_exit_reason,
4575                                        exit_intr_info, exit_qualification);
4576
4577                 /*
4578                  * Must happen outside of sync_vmcs02_to_vmcs12() as it will
4579                  * also be used to capture vmcs12 cache as part of
4580                  * capturing nVMX state for snapshot (migration).
4581                  *
4582                  * Otherwise, this flush will dirty guest memory at a
4583                  * point it is already assumed by user-space to be
4584                  * immutable.
4585                  */
4586                 nested_flush_cached_shadow_vmcs12(vcpu, vmcs12);
4587         } else {
4588                 /*
4589                  * The only expected VM-instruction error is "VM entry with
4590                  * invalid control field(s)." Anything else indicates a
4591                  * problem with L0.  And we should never get here with a
4592                  * VMFail of any type if early consistency checks are enabled.
4593                  */
4594                 WARN_ON_ONCE(vmcs_read32(VM_INSTRUCTION_ERROR) !=
4595                              VMXERR_ENTRY_INVALID_CONTROL_FIELD);
4596                 WARN_ON_ONCE(nested_early_check);
4597         }
4598
4599         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
4600
4601         /* Update any VMCS fields that might have changed while L2 ran */
4602         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
4603         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
4604         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
4605         if (kvm_caps.has_tsc_control)
4606                 vmcs_write64(TSC_MULTIPLIER, vcpu->arch.tsc_scaling_ratio);
4607
4608         if (vmx->nested.l1_tpr_threshold != -1)
4609                 vmcs_write32(TPR_THRESHOLD, vmx->nested.l1_tpr_threshold);
4610
4611         if (vmx->nested.change_vmcs01_virtual_apic_mode) {
4612                 vmx->nested.change_vmcs01_virtual_apic_mode = false;
4613                 vmx_set_virtual_apic_mode(vcpu);
4614         }
4615
4616         if (vmx->nested.update_vmcs01_cpu_dirty_logging) {
4617                 vmx->nested.update_vmcs01_cpu_dirty_logging = false;
4618                 vmx_update_cpu_dirty_logging(vcpu);
4619         }
4620
4621         /* Unpin physical memory we referred to in vmcs02 */
4622         kvm_vcpu_unmap(vcpu, &vmx->nested.apic_access_page_map, false);
4623         kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true);
4624         kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true);
4625         vmx->nested.pi_desc = NULL;
4626
4627         if (vmx->nested.reload_vmcs01_apic_access_page) {
4628                 vmx->nested.reload_vmcs01_apic_access_page = false;
4629                 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4630         }
4631
4632         if (vmx->nested.update_vmcs01_apicv_status) {
4633                 vmx->nested.update_vmcs01_apicv_status = false;
4634                 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
4635         }
4636
4637         if ((vm_exit_reason != -1) &&
4638             (enable_shadow_vmcs || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)))
4639                 vmx->nested.need_vmcs12_to_shadow_sync = true;
4640
4641         /* in case we halted in L2 */
4642         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4643
4644         if (likely(!vmx->fail)) {
4645                 if ((u16)vm_exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
4646                     nested_exit_intr_ack_set(vcpu)) {
4647                         int irq = kvm_cpu_get_interrupt(vcpu);
4648                         WARN_ON(irq < 0);
4649                         vmcs12->vm_exit_intr_info = irq |
4650                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
4651                 }
4652
4653                 if (vm_exit_reason != -1)
4654                         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
4655                                                        vmcs12->exit_qualification,
4656                                                        vmcs12->idt_vectoring_info_field,
4657                                                        vmcs12->vm_exit_intr_info,
4658                                                        vmcs12->vm_exit_intr_error_code,
4659                                                        KVM_ISA_VMX);
4660
4661                 load_vmcs12_host_state(vcpu, vmcs12);
4662
4663                 return;
4664         }
4665
4666         /*
4667          * After an early L2 VM-entry failure, we're now back
4668          * in L1 which thinks it just finished a VMLAUNCH or
4669          * VMRESUME instruction, so we need to set the failure
4670          * flag and the VM-instruction error field of the VMCS
4671          * accordingly, and skip the emulated instruction.
4672          */
4673         (void)nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
4674
4675         /*
4676          * Restore L1's host state to KVM's software model.  We're here
4677          * because a consistency check was caught by hardware, which
4678          * means some amount of guest state has been propagated to KVM's
4679          * model and needs to be unwound to the host's state.
4680          */
4681         nested_vmx_restore_host_state(vcpu);
4682
4683         vmx->fail = 0;
4684 }
4685
4686 static void nested_vmx_triple_fault(struct kvm_vcpu *vcpu)
4687 {
4688         nested_vmx_vmexit(vcpu, EXIT_REASON_TRIPLE_FAULT, 0, 0);
4689 }
4690
4691 /*
4692  * Decode the memory-address operand of a vmx instruction, as recorded on an
4693  * exit caused by such an instruction (run by a guest hypervisor).
4694  * On success, returns 0. When the operand is invalid, returns 1 and throws
4695  * #UD, #GP, or #SS.
4696  */
4697 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification,
4698                         u32 vmx_instruction_info, bool wr, int len, gva_t *ret)
4699 {
4700         gva_t off;
4701         bool exn;
4702         struct kvm_segment s;
4703
4704         /*
4705          * According to Vol. 3B, "Information for VM Exits Due to Instruction
4706          * Execution", on an exit, vmx_instruction_info holds most of the
4707          * addressing components of the operand. Only the displacement part
4708          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4709          * For how an actual address is calculated from all these components,
4710          * refer to Vol. 1, "Operand Addressing".
4711          */
4712         int  scaling = vmx_instruction_info & 3;
4713         int  addr_size = (vmx_instruction_info >> 7) & 7;
4714         bool is_reg = vmx_instruction_info & (1u << 10);
4715         int  seg_reg = (vmx_instruction_info >> 15) & 7;
4716         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
4717         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4718         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
4719         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
4720
4721         if (is_reg) {
4722                 kvm_queue_exception(vcpu, UD_VECTOR);
4723                 return 1;
4724         }
4725
4726         /* Addr = segment_base + offset */
4727         /* offset = base + [index * scale] + displacement */
4728         off = exit_qualification; /* holds the displacement */
4729         if (addr_size == 1)
4730                 off = (gva_t)sign_extend64(off, 31);
4731         else if (addr_size == 0)
4732                 off = (gva_t)sign_extend64(off, 15);
4733         if (base_is_valid)
4734                 off += kvm_register_read(vcpu, base_reg);
4735         if (index_is_valid)
4736                 off += kvm_register_read(vcpu, index_reg) << scaling;
4737         vmx_get_segment(vcpu, &s, seg_reg);
4738
4739         /*
4740          * The effective address, i.e. @off, of a memory operand is truncated
4741          * based on the address size of the instruction.  Note that this is
4742          * the *effective address*, i.e. the address prior to accounting for
4743          * the segment's base.
4744          */
4745         if (addr_size == 1) /* 32 bit */
4746                 off &= 0xffffffff;
4747         else if (addr_size == 0) /* 16 bit */
4748                 off &= 0xffff;
4749
4750         /* Checks for #GP/#SS exceptions. */
4751         exn = false;
4752         if (is_long_mode(vcpu)) {
4753                 /*
4754                  * The virtual/linear address is never truncated in 64-bit
4755                  * mode, e.g. a 32-bit address size can yield a 64-bit virtual
4756                  * address when using FS/GS with a non-zero base.
4757                  */
4758                 if (seg_reg == VCPU_SREG_FS || seg_reg == VCPU_SREG_GS)
4759                         *ret = s.base + off;
4760                 else
4761                         *ret = off;
4762
4763                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
4764                  * non-canonical form. This is the only check on the memory
4765                  * destination for long mode!
4766                  */
4767                 exn = is_noncanonical_address(*ret, vcpu);
4768         } else {
4769                 /*
4770                  * When not in long mode, the virtual/linear address is
4771                  * unconditionally truncated to 32 bits regardless of the
4772                  * address size.
4773                  */
4774                 *ret = (s.base + off) & 0xffffffff;
4775
4776                 /* Protected mode: apply checks for segment validity in the
4777                  * following order:
4778                  * - segment type check (#GP(0) may be thrown)
4779                  * - usability check (#GP(0)/#SS(0))
4780                  * - limit check (#GP(0)/#SS(0))
4781                  */
4782                 if (wr)
4783                         /* #GP(0) if the destination operand is located in a
4784                          * read-only data segment or any code segment.
4785                          */
4786                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
4787                 else
4788                         /* #GP(0) if the source operand is located in an
4789                          * execute-only code segment
4790                          */
4791                         exn = ((s.type & 0xa) == 8);
4792                 if (exn) {
4793                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4794                         return 1;
4795                 }
4796                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
4797                  */
4798                 exn = (s.unusable != 0);
4799
4800                 /*
4801                  * Protected mode: #GP(0)/#SS(0) if the memory operand is
4802                  * outside the segment limit.  All CPUs that support VMX ignore
4803                  * limit checks for flat segments, i.e. segments with base==0,
4804                  * limit==0xffffffff and of type expand-up data or code.
4805                  */
4806                 if (!(s.base == 0 && s.limit == 0xffffffff &&
4807                      ((s.type & 8) || !(s.type & 4))))
4808                         exn = exn || ((u64)off + len - 1 > s.limit);
4809         }
4810         if (exn) {
4811                 kvm_queue_exception_e(vcpu,
4812                                       seg_reg == VCPU_SREG_SS ?
4813                                                 SS_VECTOR : GP_VECTOR,
4814                                       0);
4815                 return 1;
4816         }
4817
4818         return 0;
4819 }
4820
4821 void nested_vmx_pmu_refresh(struct kvm_vcpu *vcpu,
4822                             bool vcpu_has_perf_global_ctrl)
4823 {
4824         struct vcpu_vmx *vmx;
4825
4826         if (!nested_vmx_allowed(vcpu))
4827                 return;
4828
4829         vmx = to_vmx(vcpu);
4830         if (vcpu_has_perf_global_ctrl) {
4831                 vmx->nested.msrs.entry_ctls_high |=
4832                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
4833                 vmx->nested.msrs.exit_ctls_high |=
4834                                 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
4835         } else {
4836                 vmx->nested.msrs.entry_ctls_high &=
4837                                 ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
4838                 vmx->nested.msrs.exit_ctls_high &=
4839                                 ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
4840         }
4841 }
4842
4843 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer,
4844                                 int *ret)
4845 {
4846         gva_t gva;
4847         struct x86_exception e;
4848         int r;
4849
4850         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
4851                                 vmcs_read32(VMX_INSTRUCTION_INFO), false,
4852                                 sizeof(*vmpointer), &gva)) {
4853                 *ret = 1;
4854                 return -EINVAL;
4855         }
4856
4857         r = kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e);
4858         if (r != X86EMUL_CONTINUE) {
4859                 *ret = kvm_handle_memory_failure(vcpu, r, &e);
4860                 return -EINVAL;
4861         }
4862
4863         return 0;
4864 }
4865
4866 /*
4867  * Allocate a shadow VMCS and associate it with the currently loaded
4868  * VMCS, unless such a shadow VMCS already exists. The newly allocated
4869  * VMCS is also VMCLEARed, so that it is ready for use.
4870  */
4871 static struct vmcs *alloc_shadow_vmcs(struct kvm_vcpu *vcpu)
4872 {
4873         struct vcpu_vmx *vmx = to_vmx(vcpu);
4874         struct loaded_vmcs *loaded_vmcs = vmx->loaded_vmcs;
4875
4876         /*
4877          * KVM allocates a shadow VMCS only when L1 executes VMXON and frees it
4878          * when L1 executes VMXOFF or the vCPU is forced out of nested
4879          * operation.  VMXON faults if the CPU is already post-VMXON, so it
4880          * should be impossible to already have an allocated shadow VMCS.  KVM
4881          * doesn't support virtualization of VMCS shadowing, so vmcs01 should
4882          * always be the loaded VMCS.
4883          */
4884         if (WARN_ON(loaded_vmcs != &vmx->vmcs01 || loaded_vmcs->shadow_vmcs))
4885                 return loaded_vmcs->shadow_vmcs;
4886
4887         loaded_vmcs->shadow_vmcs = alloc_vmcs(true);
4888         if (loaded_vmcs->shadow_vmcs)
4889                 vmcs_clear(loaded_vmcs->shadow_vmcs);
4890
4891         return loaded_vmcs->shadow_vmcs;
4892 }
4893
4894 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
4895 {
4896         struct vcpu_vmx *vmx = to_vmx(vcpu);
4897         int r;
4898
4899         r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
4900         if (r < 0)
4901                 goto out_vmcs02;
4902
4903         vmx->nested.cached_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT);
4904         if (!vmx->nested.cached_vmcs12)
4905                 goto out_cached_vmcs12;
4906
4907         vmx->nested.shadow_vmcs12_cache.gpa = INVALID_GPA;
4908         vmx->nested.cached_shadow_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT);
4909         if (!vmx->nested.cached_shadow_vmcs12)
4910                 goto out_cached_shadow_vmcs12;
4911
4912         if (enable_shadow_vmcs && !alloc_shadow_vmcs(vcpu))
4913                 goto out_shadow_vmcs;
4914
4915         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
4916                      HRTIMER_MODE_ABS_PINNED);
4917         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
4918
4919         vmx->nested.vpid02 = allocate_vpid();
4920
4921         vmx->nested.vmcs02_initialized = false;
4922         vmx->nested.vmxon = true;
4923
4924         if (vmx_pt_mode_is_host_guest()) {
4925                 vmx->pt_desc.guest.ctl = 0;
4926                 pt_update_intercept_for_msr(vcpu);
4927         }
4928
4929         return 0;
4930
4931 out_shadow_vmcs:
4932         kfree(vmx->nested.cached_shadow_vmcs12);
4933
4934 out_cached_shadow_vmcs12:
4935         kfree(vmx->nested.cached_vmcs12);
4936
4937 out_cached_vmcs12:
4938         free_loaded_vmcs(&vmx->nested.vmcs02);
4939
4940 out_vmcs02:
4941         return -ENOMEM;
4942 }
4943
4944 /* Emulate the VMXON instruction. */
4945 static int handle_vmon(struct kvm_vcpu *vcpu)
4946 {
4947         int ret;
4948         gpa_t vmptr;
4949         uint32_t revision;
4950         struct vcpu_vmx *vmx = to_vmx(vcpu);
4951         const u64 VMXON_NEEDED_FEATURES = FEAT_CTL_LOCKED
4952                 | FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
4953
4954         /*
4955          * Note, KVM cannot rely on hardware to perform the CR0/CR4 #UD checks
4956          * that have higher priority than VM-Exit (see Intel SDM's pseudocode
4957          * for VMXON), as KVM must load valid CR0/CR4 values into hardware while
4958          * running the guest, i.e. KVM needs to check the _guest_ values.
4959          *
4960          * Rely on hardware for the other two pre-VM-Exit checks, !VM86 and
4961          * !COMPATIBILITY modes.  KVM may run the guest in VM86 to emulate Real
4962          * Mode, but KVM will never take the guest out of those modes.
4963          */
4964         if (!nested_host_cr0_valid(vcpu, kvm_read_cr0(vcpu)) ||
4965             !nested_host_cr4_valid(vcpu, kvm_read_cr4(vcpu))) {
4966                 kvm_queue_exception(vcpu, UD_VECTOR);
4967                 return 1;
4968         }
4969
4970         /*
4971          * CPL=0 and all other checks that are lower priority than VM-Exit must
4972          * be checked manually.
4973          */
4974         if (vmx_get_cpl(vcpu)) {
4975                 kvm_inject_gp(vcpu, 0);
4976                 return 1;
4977         }
4978
4979         if (vmx->nested.vmxon)
4980                 return nested_vmx_fail(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
4981
4982         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
4983                         != VMXON_NEEDED_FEATURES) {
4984                 kvm_inject_gp(vcpu, 0);
4985                 return 1;
4986         }
4987
4988         if (nested_vmx_get_vmptr(vcpu, &vmptr, &ret))
4989                 return ret;
4990
4991         /*
4992          * SDM 3: 24.11.5
4993          * The first 4 bytes of VMXON region contain the supported
4994          * VMCS revision identifier
4995          *
4996          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
4997          * which replaces physical address width with 32
4998          */
4999         if (!page_address_valid(vcpu, vmptr))
5000                 return nested_vmx_failInvalid(vcpu);
5001
5002         if (kvm_read_guest(vcpu->kvm, vmptr, &revision, sizeof(revision)) ||
5003             revision != VMCS12_REVISION)
5004                 return nested_vmx_failInvalid(vcpu);
5005
5006         vmx->nested.vmxon_ptr = vmptr;
5007         ret = enter_vmx_operation(vcpu);
5008         if (ret)
5009                 return ret;
5010
5011         return nested_vmx_succeed(vcpu);
5012 }
5013
5014 static inline void nested_release_vmcs12(struct kvm_vcpu *vcpu)
5015 {
5016         struct vcpu_vmx *vmx = to_vmx(vcpu);
5017
5018         if (vmx->nested.current_vmptr == INVALID_GPA)
5019                 return;
5020
5021         copy_vmcs02_to_vmcs12_rare(vcpu, get_vmcs12(vcpu));
5022
5023         if (enable_shadow_vmcs) {
5024                 /* copy to memory all shadowed fields in case
5025                    they were modified */
5026                 copy_shadow_to_vmcs12(vmx);
5027                 vmx_disable_shadow_vmcs(vmx);
5028         }
5029         vmx->nested.posted_intr_nv = -1;
5030
5031         /* Flush VMCS12 to guest memory */
5032         kvm_vcpu_write_guest_page(vcpu,
5033                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
5034                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
5035
5036         kvm_mmu_free_roots(vcpu->kvm, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
5037
5038         vmx->nested.current_vmptr = INVALID_GPA;
5039 }
5040
5041 /* Emulate the VMXOFF instruction */
5042 static int handle_vmoff(struct kvm_vcpu *vcpu)
5043 {
5044         if (!nested_vmx_check_permission(vcpu))
5045                 return 1;
5046
5047         free_nested(vcpu);
5048
5049         /* Process a latched INIT during time CPU was in VMX operation */
5050         kvm_make_request(KVM_REQ_EVENT, vcpu);
5051
5052         return nested_vmx_succeed(vcpu);
5053 }
5054
5055 /* Emulate the VMCLEAR instruction */
5056 static int handle_vmclear(struct kvm_vcpu *vcpu)
5057 {
5058         struct vcpu_vmx *vmx = to_vmx(vcpu);
5059         u32 zero = 0;
5060         gpa_t vmptr;
5061         u64 evmcs_gpa;
5062         int r;
5063
5064         if (!nested_vmx_check_permission(vcpu))
5065                 return 1;
5066
5067         if (nested_vmx_get_vmptr(vcpu, &vmptr, &r))
5068                 return r;
5069
5070         if (!page_address_valid(vcpu, vmptr))
5071                 return nested_vmx_fail(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5072
5073         if (vmptr == vmx->nested.vmxon_ptr)
5074                 return nested_vmx_fail(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
5075
5076         /*
5077          * When Enlightened VMEntry is enabled on the calling CPU we treat
5078          * memory area pointer by vmptr as Enlightened VMCS (as there's no good
5079          * way to distinguish it from VMCS12) and we must not corrupt it by
5080          * writing to the non-existent 'launch_state' field. The area doesn't
5081          * have to be the currently active EVMCS on the calling CPU and there's
5082          * nothing KVM has to do to transition it from 'active' to 'non-active'
5083          * state. It is possible that the area will stay mapped as
5084          * vmx->nested.hv_evmcs but this shouldn't be a problem.
5085          */
5086         if (likely(!vmx->nested.enlightened_vmcs_enabled ||
5087                    !nested_enlightened_vmentry(vcpu, &evmcs_gpa))) {
5088                 if (vmptr == vmx->nested.current_vmptr)
5089                         nested_release_vmcs12(vcpu);
5090
5091                 kvm_vcpu_write_guest(vcpu,
5092                                      vmptr + offsetof(struct vmcs12,
5093                                                       launch_state),
5094                                      &zero, sizeof(zero));
5095         } else if (vmx->nested.hv_evmcs && vmptr == vmx->nested.hv_evmcs_vmptr) {
5096                 nested_release_evmcs(vcpu);
5097         }
5098
5099         return nested_vmx_succeed(vcpu);
5100 }
5101
5102 /* Emulate the VMLAUNCH instruction */
5103 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5104 {
5105         return nested_vmx_run(vcpu, true);
5106 }
5107
5108 /* Emulate the VMRESUME instruction */
5109 static int handle_vmresume(struct kvm_vcpu *vcpu)
5110 {
5111
5112         return nested_vmx_run(vcpu, false);
5113 }
5114
5115 static int handle_vmread(struct kvm_vcpu *vcpu)
5116 {
5117         struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu)
5118                                                     : get_vmcs12(vcpu);
5119         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5120         u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5121         struct vcpu_vmx *vmx = to_vmx(vcpu);
5122         struct x86_exception e;
5123         unsigned long field;
5124         u64 value;
5125         gva_t gva = 0;
5126         short offset;
5127         int len, r;
5128
5129         if (!nested_vmx_check_permission(vcpu))
5130                 return 1;
5131
5132         /* Decode instruction info and find the field to read */
5133         field = kvm_register_read(vcpu, (((instr_info) >> 28) & 0xf));
5134
5135         if (!evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) {
5136                 /*
5137                  * In VMX non-root operation, when the VMCS-link pointer is INVALID_GPA,
5138                  * any VMREAD sets the ALU flags for VMfailInvalid.
5139                  */
5140                 if (vmx->nested.current_vmptr == INVALID_GPA ||
5141                     (is_guest_mode(vcpu) &&
5142                      get_vmcs12(vcpu)->vmcs_link_pointer == INVALID_GPA))
5143                         return nested_vmx_failInvalid(vcpu);
5144
5145                 offset = get_vmcs12_field_offset(field);
5146                 if (offset < 0)
5147                         return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5148
5149                 if (!is_guest_mode(vcpu) && is_vmcs12_ext_field(field))
5150                         copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
5151
5152                 /* Read the field, zero-extended to a u64 value */
5153                 value = vmcs12_read_any(vmcs12, field, offset);
5154         } else {
5155                 /*
5156                  * Hyper-V TLFS (as of 6.0b) explicitly states, that while an
5157                  * enlightened VMCS is active VMREAD/VMWRITE instructions are
5158                  * unsupported. Unfortunately, certain versions of Windows 11
5159                  * don't comply with this requirement which is not enforced in
5160                  * genuine Hyper-V. Allow VMREAD from an enlightened VMCS as a
5161                  * workaround, as misbehaving guests will panic on VM-Fail.
5162                  * Note, enlightened VMCS is incompatible with shadow VMCS so
5163                  * all VMREADs from L2 should go to L1.
5164                  */
5165                 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
5166                         return nested_vmx_failInvalid(vcpu);
5167
5168                 offset = evmcs_field_offset(field, NULL);
5169                 if (offset < 0)
5170                         return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5171
5172                 /* Read the field, zero-extended to a u64 value */
5173                 value = evmcs_read_any(vmx->nested.hv_evmcs, field, offset);
5174         }
5175
5176         /*
5177          * Now copy part of this value to register or memory, as requested.
5178          * Note that the number of bits actually copied is 32 or 64 depending
5179          * on the guest's mode (32 or 64 bit), not on the given field's length.
5180          */
5181         if (instr_info & BIT(10)) {
5182                 kvm_register_write(vcpu, (((instr_info) >> 3) & 0xf), value);
5183         } else {
5184                 len = is_64_bit_mode(vcpu) ? 8 : 4;
5185                 if (get_vmx_mem_address(vcpu, exit_qualification,
5186                                         instr_info, true, len, &gva))
5187                         return 1;
5188                 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
5189                 r = kvm_write_guest_virt_system(vcpu, gva, &value, len, &e);
5190                 if (r != X86EMUL_CONTINUE)
5191                         return kvm_handle_memory_failure(vcpu, r, &e);
5192         }
5193
5194         return nested_vmx_succeed(vcpu);
5195 }
5196
5197 static bool is_shadow_field_rw(unsigned long field)
5198 {
5199         switch (field) {
5200 #define SHADOW_FIELD_RW(x, y) case x:
5201 #include "vmcs_shadow_fields.h"
5202                 return true;
5203         default:
5204                 break;
5205         }
5206         return false;
5207 }
5208
5209 static bool is_shadow_field_ro(unsigned long field)
5210 {
5211         switch (field) {
5212 #define SHADOW_FIELD_RO(x, y) case x:
5213 #include "vmcs_shadow_fields.h"
5214                 return true;
5215         default:
5216                 break;
5217         }
5218         return false;
5219 }
5220
5221 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5222 {
5223         struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu)
5224                                                     : get_vmcs12(vcpu);
5225         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5226         u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5227         struct vcpu_vmx *vmx = to_vmx(vcpu);
5228         struct x86_exception e;
5229         unsigned long field;
5230         short offset;
5231         gva_t gva;
5232         int len, r;
5233
5234         /*
5235          * The value to write might be 32 or 64 bits, depending on L1's long
5236          * mode, and eventually we need to write that into a field of several
5237          * possible lengths. The code below first zero-extends the value to 64
5238          * bit (value), and then copies only the appropriate number of
5239          * bits into the vmcs12 field.
5240          */
5241         u64 value = 0;
5242
5243         if (!nested_vmx_check_permission(vcpu))
5244                 return 1;
5245
5246         /*
5247          * In VMX non-root operation, when the VMCS-link pointer is INVALID_GPA,
5248          * any VMWRITE sets the ALU flags for VMfailInvalid.
5249          */
5250         if (vmx->nested.current_vmptr == INVALID_GPA ||
5251             (is_guest_mode(vcpu) &&
5252              get_vmcs12(vcpu)->vmcs_link_pointer == INVALID_GPA))
5253                 return nested_vmx_failInvalid(vcpu);
5254
5255         if (instr_info & BIT(10))
5256                 value = kvm_register_read(vcpu, (((instr_info) >> 3) & 0xf));
5257         else {
5258                 len = is_64_bit_mode(vcpu) ? 8 : 4;
5259                 if (get_vmx_mem_address(vcpu, exit_qualification,
5260                                         instr_info, false, len, &gva))
5261                         return 1;
5262                 r = kvm_read_guest_virt(vcpu, gva, &value, len, &e);
5263                 if (r != X86EMUL_CONTINUE)
5264                         return kvm_handle_memory_failure(vcpu, r, &e);
5265         }
5266
5267         field = kvm_register_read(vcpu, (((instr_info) >> 28) & 0xf));
5268
5269         offset = get_vmcs12_field_offset(field);
5270         if (offset < 0)
5271                 return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5272
5273         /*
5274          * If the vCPU supports "VMWRITE to any supported field in the
5275          * VMCS," then the "read-only" fields are actually read/write.
5276          */
5277         if (vmcs_field_readonly(field) &&
5278             !nested_cpu_has_vmwrite_any_field(vcpu))
5279                 return nested_vmx_fail(vcpu, VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5280
5281         /*
5282          * Ensure vmcs12 is up-to-date before any VMWRITE that dirties
5283          * vmcs12, else we may crush a field or consume a stale value.
5284          */
5285         if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field))
5286                 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
5287
5288         /*
5289          * Some Intel CPUs intentionally drop the reserved bits of the AR byte
5290          * fields on VMWRITE.  Emulate this behavior to ensure consistent KVM
5291          * behavior regardless of the underlying hardware, e.g. if an AR_BYTE
5292          * field is intercepted for VMWRITE but not VMREAD (in L1), then VMREAD
5293          * from L1 will return a different value than VMREAD from L2 (L1 sees
5294          * the stripped down value, L2 sees the full value as stored by KVM).
5295          */
5296         if (field >= GUEST_ES_AR_BYTES && field <= GUEST_TR_AR_BYTES)
5297                 value &= 0x1f0ff;
5298
5299         vmcs12_write_any(vmcs12, field, offset, value);
5300
5301         /*
5302          * Do not track vmcs12 dirty-state if in guest-mode as we actually
5303          * dirty shadow vmcs12 instead of vmcs12.  Fields that can be updated
5304          * by L1 without a vmexit are always updated in the vmcs02, i.e. don't
5305          * "dirty" vmcs12, all others go down the prepare_vmcs02() slow path.
5306          */
5307         if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field)) {
5308                 /*
5309                  * L1 can read these fields without exiting, ensure the
5310                  * shadow VMCS is up-to-date.
5311                  */
5312                 if (enable_shadow_vmcs && is_shadow_field_ro(field)) {
5313                         preempt_disable();
5314                         vmcs_load(vmx->vmcs01.shadow_vmcs);
5315
5316                         __vmcs_writel(field, value);
5317
5318                         vmcs_clear(vmx->vmcs01.shadow_vmcs);
5319                         vmcs_load(vmx->loaded_vmcs->vmcs);
5320                         preempt_enable();
5321                 }
5322                 vmx->nested.dirty_vmcs12 = true;
5323         }
5324
5325         return nested_vmx_succeed(vcpu);
5326 }
5327
5328 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
5329 {
5330         vmx->nested.current_vmptr = vmptr;
5331         if (enable_shadow_vmcs) {
5332                 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
5333                 vmcs_write64(VMCS_LINK_POINTER,
5334                              __pa(vmx->vmcs01.shadow_vmcs));
5335                 vmx->nested.need_vmcs12_to_shadow_sync = true;
5336         }
5337         vmx->nested.dirty_vmcs12 = true;
5338         vmx->nested.force_msr_bitmap_recalc = true;
5339 }
5340
5341 /* Emulate the VMPTRLD instruction */
5342 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5343 {
5344         struct vcpu_vmx *vmx = to_vmx(vcpu);
5345         gpa_t vmptr;
5346         int r;
5347
5348         if (!nested_vmx_check_permission(vcpu))
5349                 return 1;
5350
5351         if (nested_vmx_get_vmptr(vcpu, &vmptr, &r))
5352                 return r;
5353
5354         if (!page_address_valid(vcpu, vmptr))
5355                 return nested_vmx_fail(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5356
5357         if (vmptr == vmx->nested.vmxon_ptr)
5358                 return nested_vmx_fail(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
5359
5360         /* Forbid normal VMPTRLD if Enlightened version was used */
5361         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
5362                 return 1;
5363
5364         if (vmx->nested.current_vmptr != vmptr) {
5365                 struct gfn_to_hva_cache *ghc = &vmx->nested.vmcs12_cache;
5366                 struct vmcs_hdr hdr;
5367
5368                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, vmptr, VMCS12_SIZE)) {
5369                         /*
5370                          * Reads from an unbacked page return all 1s,
5371                          * which means that the 32 bits located at the
5372                          * given physical address won't match the required
5373                          * VMCS12_REVISION identifier.
5374                          */
5375                         return nested_vmx_fail(vcpu,
5376                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5377                 }
5378
5379                 if (kvm_read_guest_offset_cached(vcpu->kvm, ghc, &hdr,
5380                                                  offsetof(struct vmcs12, hdr),
5381                                                  sizeof(hdr))) {
5382                         return nested_vmx_fail(vcpu,
5383                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5384                 }
5385
5386                 if (hdr.revision_id != VMCS12_REVISION ||
5387                     (hdr.shadow_vmcs &&
5388                      !nested_cpu_has_vmx_shadow_vmcs(vcpu))) {
5389                         return nested_vmx_fail(vcpu,
5390                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5391                 }
5392
5393                 nested_release_vmcs12(vcpu);
5394
5395                 /*
5396                  * Load VMCS12 from guest memory since it is not already
5397                  * cached.
5398                  */
5399                 if (kvm_read_guest_cached(vcpu->kvm, ghc, vmx->nested.cached_vmcs12,
5400                                           VMCS12_SIZE)) {
5401                         return nested_vmx_fail(vcpu,
5402                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5403                 }
5404
5405                 set_current_vmptr(vmx, vmptr);
5406         }
5407
5408         return nested_vmx_succeed(vcpu);
5409 }
5410
5411 /* Emulate the VMPTRST instruction */
5412 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5413 {
5414         unsigned long exit_qual = vmx_get_exit_qual(vcpu);
5415         u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5416         gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr;
5417         struct x86_exception e;
5418         gva_t gva;
5419         int r;
5420
5421         if (!nested_vmx_check_permission(vcpu))
5422                 return 1;
5423
5424         if (unlikely(evmptr_is_valid(to_vmx(vcpu)->nested.hv_evmcs_vmptr)))
5425                 return 1;
5426
5427         if (get_vmx_mem_address(vcpu, exit_qual, instr_info,
5428                                 true, sizeof(gpa_t), &gva))
5429                 return 1;
5430         /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
5431         r = kvm_write_guest_virt_system(vcpu, gva, (void *)&current_vmptr,
5432                                         sizeof(gpa_t), &e);
5433         if (r != X86EMUL_CONTINUE)
5434                 return kvm_handle_memory_failure(vcpu, r, &e);
5435
5436         return nested_vmx_succeed(vcpu);
5437 }
5438
5439 /* Emulate the INVEPT instruction */
5440 static int handle_invept(struct kvm_vcpu *vcpu)
5441 {
5442         struct vcpu_vmx *vmx = to_vmx(vcpu);
5443         u32 vmx_instruction_info, types;
5444         unsigned long type, roots_to_free;
5445         struct kvm_mmu *mmu;
5446         gva_t gva;
5447         struct x86_exception e;
5448         struct {
5449                 u64 eptp, gpa;
5450         } operand;
5451         int i, r, gpr_index;
5452
5453         if (!(vmx->nested.msrs.secondary_ctls_high &
5454               SECONDARY_EXEC_ENABLE_EPT) ||
5455             !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
5456                 kvm_queue_exception(vcpu, UD_VECTOR);
5457                 return 1;
5458         }
5459
5460         if (!nested_vmx_check_permission(vcpu))
5461                 return 1;
5462
5463         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5464         gpr_index = vmx_get_instr_info_reg2(vmx_instruction_info);
5465         type = kvm_register_read(vcpu, gpr_index);
5466
5467         types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
5468
5469         if (type >= 32 || !(types & (1 << type)))
5470                 return nested_vmx_fail(vcpu, VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5471
5472         /* According to the Intel VMX instruction reference, the memory
5473          * operand is read even if it isn't needed (e.g., for type==global)
5474          */
5475         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5476                         vmx_instruction_info, false, sizeof(operand), &gva))
5477                 return 1;
5478         r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
5479         if (r != X86EMUL_CONTINUE)
5480                 return kvm_handle_memory_failure(vcpu, r, &e);
5481
5482         /*
5483          * Nested EPT roots are always held through guest_mmu,
5484          * not root_mmu.
5485          */
5486         mmu = &vcpu->arch.guest_mmu;
5487
5488         switch (type) {
5489         case VMX_EPT_EXTENT_CONTEXT:
5490                 if (!nested_vmx_check_eptp(vcpu, operand.eptp))
5491                         return nested_vmx_fail(vcpu,
5492                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5493
5494                 roots_to_free = 0;
5495                 if (nested_ept_root_matches(mmu->root.hpa, mmu->root.pgd,
5496                                             operand.eptp))
5497                         roots_to_free |= KVM_MMU_ROOT_CURRENT;
5498
5499                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5500                         if (nested_ept_root_matches(mmu->prev_roots[i].hpa,
5501                                                     mmu->prev_roots[i].pgd,
5502                                                     operand.eptp))
5503                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5504                 }
5505                 break;
5506         case VMX_EPT_EXTENT_GLOBAL:
5507                 roots_to_free = KVM_MMU_ROOTS_ALL;
5508                 break;
5509         default:
5510                 BUG();
5511                 break;
5512         }
5513
5514         if (roots_to_free)
5515                 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
5516
5517         return nested_vmx_succeed(vcpu);
5518 }
5519
5520 static int handle_invvpid(struct kvm_vcpu *vcpu)
5521 {
5522         struct vcpu_vmx *vmx = to_vmx(vcpu);
5523         u32 vmx_instruction_info;
5524         unsigned long type, types;
5525         gva_t gva;
5526         struct x86_exception e;
5527         struct {
5528                 u64 vpid;
5529                 u64 gla;
5530         } operand;
5531         u16 vpid02;
5532         int r, gpr_index;
5533
5534         if (!(vmx->nested.msrs.secondary_ctls_high &
5535               SECONDARY_EXEC_ENABLE_VPID) ||
5536                         !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
5537                 kvm_queue_exception(vcpu, UD_VECTOR);
5538                 return 1;
5539         }
5540
5541         if (!nested_vmx_check_permission(vcpu))
5542                 return 1;
5543
5544         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5545         gpr_index = vmx_get_instr_info_reg2(vmx_instruction_info);
5546         type = kvm_register_read(vcpu, gpr_index);
5547
5548         types = (vmx->nested.msrs.vpid_caps &
5549                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
5550
5551         if (type >= 32 || !(types & (1 << type)))
5552                 return nested_vmx_fail(vcpu,
5553                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5554
5555         /* according to the intel vmx instruction reference, the memory
5556          * operand is read even if it isn't needed (e.g., for type==global)
5557          */
5558         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5559                         vmx_instruction_info, false, sizeof(operand), &gva))
5560                 return 1;
5561         r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
5562         if (r != X86EMUL_CONTINUE)
5563                 return kvm_handle_memory_failure(vcpu, r, &e);
5564
5565         if (operand.vpid >> 16)
5566                 return nested_vmx_fail(vcpu,
5567                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5568
5569         vpid02 = nested_get_vpid02(vcpu);
5570         switch (type) {
5571         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
5572                 if (!operand.vpid ||
5573                     is_noncanonical_address(operand.gla, vcpu))
5574                         return nested_vmx_fail(vcpu,
5575                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5576                 vpid_sync_vcpu_addr(vpid02, operand.gla);
5577                 break;
5578         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
5579         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
5580                 if (!operand.vpid)
5581                         return nested_vmx_fail(vcpu,
5582                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5583                 vpid_sync_context(vpid02);
5584                 break;
5585         case VMX_VPID_EXTENT_ALL_CONTEXT:
5586                 vpid_sync_context(vpid02);
5587                 break;
5588         default:
5589                 WARN_ON_ONCE(1);
5590                 return kvm_skip_emulated_instruction(vcpu);
5591         }
5592
5593         /*
5594          * Sync the shadow page tables if EPT is disabled, L1 is invalidating
5595          * linear mappings for L2 (tagged with L2's VPID).  Free all guest
5596          * roots as VPIDs are not tracked in the MMU role.
5597          *
5598          * Note, this operates on root_mmu, not guest_mmu, as L1 and L2 share
5599          * an MMU when EPT is disabled.
5600          *
5601          * TODO: sync only the affected SPTEs for INVDIVIDUAL_ADDR.
5602          */
5603         if (!enable_ept)
5604                 kvm_mmu_free_guest_mode_roots(vcpu->kvm, &vcpu->arch.root_mmu);
5605
5606         return nested_vmx_succeed(vcpu);
5607 }
5608
5609 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
5610                                      struct vmcs12 *vmcs12)
5611 {
5612         u32 index = kvm_rcx_read(vcpu);
5613         u64 new_eptp;
5614
5615         if (WARN_ON_ONCE(!nested_cpu_has_ept(vmcs12)))
5616                 return 1;
5617         if (index >= VMFUNC_EPTP_ENTRIES)
5618                 return 1;
5619
5620         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
5621                                      &new_eptp, index * 8, 8))
5622                 return 1;
5623
5624         /*
5625          * If the (L2) guest does a vmfunc to the currently
5626          * active ept pointer, we don't have to do anything else
5627          */
5628         if (vmcs12->ept_pointer != new_eptp) {
5629                 if (!nested_vmx_check_eptp(vcpu, new_eptp))
5630                         return 1;
5631
5632                 vmcs12->ept_pointer = new_eptp;
5633                 nested_ept_new_eptp(vcpu);
5634
5635                 if (!nested_cpu_has_vpid(vmcs12))
5636                         kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
5637         }
5638
5639         return 0;
5640 }
5641
5642 static int handle_vmfunc(struct kvm_vcpu *vcpu)
5643 {
5644         struct vcpu_vmx *vmx = to_vmx(vcpu);
5645         struct vmcs12 *vmcs12;
5646         u32 function = kvm_rax_read(vcpu);
5647
5648         /*
5649          * VMFUNC is only supported for nested guests, but we always enable the
5650          * secondary control for simplicity; for non-nested mode, fake that we
5651          * didn't by injecting #UD.
5652          */
5653         if (!is_guest_mode(vcpu)) {
5654                 kvm_queue_exception(vcpu, UD_VECTOR);
5655                 return 1;
5656         }
5657
5658         vmcs12 = get_vmcs12(vcpu);
5659
5660         /*
5661          * #UD on out-of-bounds function has priority over VM-Exit, and VMFUNC
5662          * is enabled in vmcs02 if and only if it's enabled in vmcs12.
5663          */
5664         if (WARN_ON_ONCE((function > 63) || !nested_cpu_has_vmfunc(vmcs12))) {
5665                 kvm_queue_exception(vcpu, UD_VECTOR);
5666                 return 1;
5667         }
5668
5669         if (!(vmcs12->vm_function_control & BIT_ULL(function)))
5670                 goto fail;
5671
5672         switch (function) {
5673         case 0:
5674                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
5675                         goto fail;
5676                 break;
5677         default:
5678                 goto fail;
5679         }
5680         return kvm_skip_emulated_instruction(vcpu);
5681
5682 fail:
5683         /*
5684          * This is effectively a reflected VM-Exit, as opposed to a synthesized
5685          * nested VM-Exit.  Pass the original exit reason, i.e. don't hardcode
5686          * EXIT_REASON_VMFUNC as the exit reason.
5687          */
5688         nested_vmx_vmexit(vcpu, vmx->exit_reason.full,
5689                           vmx_get_intr_info(vcpu),
5690                           vmx_get_exit_qual(vcpu));
5691         return 1;
5692 }
5693
5694 /*
5695  * Return true if an IO instruction with the specified port and size should cause
5696  * a VM-exit into L1.
5697  */
5698 bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port,
5699                                  int size)
5700 {
5701         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5702         gpa_t bitmap, last_bitmap;
5703         u8 b;
5704
5705         last_bitmap = INVALID_GPA;
5706         b = -1;
5707
5708         while (size > 0) {
5709                 if (port < 0x8000)
5710                         bitmap = vmcs12->io_bitmap_a;
5711                 else if (port < 0x10000)
5712                         bitmap = vmcs12->io_bitmap_b;
5713                 else
5714                         return true;
5715                 bitmap += (port & 0x7fff) / 8;
5716
5717                 if (last_bitmap != bitmap)
5718                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
5719                                 return true;
5720                 if (b & (1 << (port & 7)))
5721                         return true;
5722
5723                 port++;
5724                 size--;
5725                 last_bitmap = bitmap;
5726         }
5727
5728         return false;
5729 }
5730
5731 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5732                                        struct vmcs12 *vmcs12)
5733 {
5734         unsigned long exit_qualification;
5735         unsigned short port;
5736         int size;
5737
5738         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5739                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
5740
5741         exit_qualification = vmx_get_exit_qual(vcpu);
5742
5743         port = exit_qualification >> 16;
5744         size = (exit_qualification & 7) + 1;
5745
5746         return nested_vmx_check_io_bitmaps(vcpu, port, size);
5747 }
5748
5749 /*
5750  * Return 1 if we should exit from L2 to L1 to handle an MSR access,
5751  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5752  * disinterest in the current event (read or write a specific MSR) by using an
5753  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5754  */
5755 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5756                                         struct vmcs12 *vmcs12,
5757                                         union vmx_exit_reason exit_reason)
5758 {
5759         u32 msr_index = kvm_rcx_read(vcpu);
5760         gpa_t bitmap;
5761
5762         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
5763                 return true;
5764
5765         /*
5766          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5767          * for the four combinations of read/write and low/high MSR numbers.
5768          * First we need to figure out which of the four to use:
5769          */
5770         bitmap = vmcs12->msr_bitmap;
5771         if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
5772                 bitmap += 2048;
5773         if (msr_index >= 0xc0000000) {
5774                 msr_index -= 0xc0000000;
5775                 bitmap += 1024;
5776         }
5777
5778         /* Then read the msr_index'th bit from this bitmap: */
5779         if (msr_index < 1024*8) {
5780                 unsigned char b;
5781                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
5782                         return true;
5783                 return 1 & (b >> (msr_index & 7));
5784         } else
5785                 return true; /* let L1 handle the wrong parameter */
5786 }
5787
5788 /*
5789  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5790  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5791  * intercept (via guest_host_mask etc.) the current event.
5792  */
5793 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5794         struct vmcs12 *vmcs12)
5795 {
5796         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5797         int cr = exit_qualification & 15;
5798         int reg;
5799         unsigned long val;
5800
5801         switch ((exit_qualification >> 4) & 3) {
5802         case 0: /* mov to cr */
5803                 reg = (exit_qualification >> 8) & 15;
5804                 val = kvm_register_read(vcpu, reg);
5805                 switch (cr) {
5806                 case 0:
5807                         if (vmcs12->cr0_guest_host_mask &
5808                             (val ^ vmcs12->cr0_read_shadow))
5809                                 return true;
5810                         break;
5811                 case 3:
5812                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5813                                 return true;
5814                         break;
5815                 case 4:
5816                         if (vmcs12->cr4_guest_host_mask &
5817                             (vmcs12->cr4_read_shadow ^ val))
5818                                 return true;
5819                         break;
5820                 case 8:
5821                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5822                                 return true;
5823                         break;
5824                 }
5825                 break;
5826         case 2: /* clts */
5827                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5828                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5829                         return true;
5830                 break;
5831         case 1: /* mov from cr */
5832                 switch (cr) {
5833                 case 3:
5834                         if (vmcs12->cpu_based_vm_exec_control &
5835                             CPU_BASED_CR3_STORE_EXITING)
5836                                 return true;
5837                         break;
5838                 case 8:
5839                         if (vmcs12->cpu_based_vm_exec_control &
5840                             CPU_BASED_CR8_STORE_EXITING)
5841                                 return true;
5842                         break;
5843                 }
5844                 break;
5845         case 3: /* lmsw */
5846                 /*
5847                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5848                  * cr0. Other attempted changes are ignored, with no exit.
5849                  */
5850                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5851                 if (vmcs12->cr0_guest_host_mask & 0xe &
5852                     (val ^ vmcs12->cr0_read_shadow))
5853                         return true;
5854                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5855                     !(vmcs12->cr0_read_shadow & 0x1) &&
5856                     (val & 0x1))
5857                         return true;
5858                 break;
5859         }
5860         return false;
5861 }
5862
5863 static bool nested_vmx_exit_handled_encls(struct kvm_vcpu *vcpu,
5864                                           struct vmcs12 *vmcs12)
5865 {
5866         u32 encls_leaf;
5867
5868         if (!guest_cpuid_has(vcpu, X86_FEATURE_SGX) ||
5869             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENCLS_EXITING))
5870                 return false;
5871
5872         encls_leaf = kvm_rax_read(vcpu);
5873         if (encls_leaf > 62)
5874                 encls_leaf = 63;
5875         return vmcs12->encls_exiting_bitmap & BIT_ULL(encls_leaf);
5876 }
5877
5878 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu,
5879         struct vmcs12 *vmcs12, gpa_t bitmap)
5880 {
5881         u32 vmx_instruction_info;
5882         unsigned long field;
5883         u8 b;
5884
5885         if (!nested_cpu_has_shadow_vmcs(vmcs12))
5886                 return true;
5887
5888         /* Decode instruction info and find the field to access */
5889         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5890         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5891
5892         /* Out-of-range fields always cause a VM exit from L2 to L1 */
5893         if (field >> 15)
5894                 return true;
5895
5896         if (kvm_vcpu_read_guest(vcpu, bitmap + field/8, &b, 1))
5897                 return true;
5898
5899         return 1 & (b >> (field & 7));
5900 }
5901
5902 static bool nested_vmx_exit_handled_mtf(struct vmcs12 *vmcs12)
5903 {
5904         u32 entry_intr_info = vmcs12->vm_entry_intr_info_field;
5905
5906         if (nested_cpu_has_mtf(vmcs12))
5907                 return true;
5908
5909         /*
5910          * An MTF VM-exit may be injected into the guest by setting the
5911          * interruption-type to 7 (other event) and the vector field to 0. Such
5912          * is the case regardless of the 'monitor trap flag' VM-execution
5913          * control.
5914          */
5915         return entry_intr_info == (INTR_INFO_VALID_MASK
5916                                    | INTR_TYPE_OTHER_EVENT);
5917 }
5918
5919 /*
5920  * Return true if L0 wants to handle an exit from L2 regardless of whether or not
5921  * L1 wants the exit.  Only call this when in is_guest_mode (L2).
5922  */
5923 static bool nested_vmx_l0_wants_exit(struct kvm_vcpu *vcpu,
5924                                      union vmx_exit_reason exit_reason)
5925 {
5926         u32 intr_info;
5927
5928         switch ((u16)exit_reason.basic) {
5929         case EXIT_REASON_EXCEPTION_NMI:
5930                 intr_info = vmx_get_intr_info(vcpu);
5931                 if (is_nmi(intr_info))
5932                         return true;
5933                 else if (is_page_fault(intr_info))
5934                         return vcpu->arch.apf.host_apf_flags ||
5935                                vmx_need_pf_intercept(vcpu);
5936                 else if (is_debug(intr_info) &&
5937                          vcpu->guest_debug &
5938                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5939                         return true;
5940                 else if (is_breakpoint(intr_info) &&
5941                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5942                         return true;
5943                 else if (is_alignment_check(intr_info) &&
5944                          !vmx_guest_inject_ac(vcpu))
5945                         return true;
5946                 return false;
5947         case EXIT_REASON_EXTERNAL_INTERRUPT:
5948                 return true;
5949         case EXIT_REASON_MCE_DURING_VMENTRY:
5950                 return true;
5951         case EXIT_REASON_EPT_VIOLATION:
5952                 /*
5953                  * L0 always deals with the EPT violation. If nested EPT is
5954                  * used, and the nested mmu code discovers that the address is
5955                  * missing in the guest EPT table (EPT12), the EPT violation
5956                  * will be injected with nested_ept_inject_page_fault()
5957                  */
5958                 return true;
5959         case EXIT_REASON_EPT_MISCONFIG:
5960                 /*
5961                  * L2 never uses directly L1's EPT, but rather L0's own EPT
5962                  * table (shadow on EPT) or a merged EPT table that L0 built
5963                  * (EPT on EPT). So any problems with the structure of the
5964                  * table is L0's fault.
5965                  */
5966                 return true;
5967         case EXIT_REASON_PREEMPTION_TIMER:
5968                 return true;
5969         case EXIT_REASON_PML_FULL:
5970                 /*
5971                  * PML is emulated for an L1 VMM and should never be enabled in
5972                  * vmcs02, always "handle" PML_FULL by exiting to userspace.
5973                  */
5974                 return true;
5975         case EXIT_REASON_VMFUNC:
5976                 /* VM functions are emulated through L2->L0 vmexits. */
5977                 return true;
5978         case EXIT_REASON_BUS_LOCK:
5979                 /*
5980                  * At present, bus lock VM exit is never exposed to L1.
5981                  * Handle L2's bus locks in L0 directly.
5982                  */
5983                 return true;
5984         default:
5985                 break;
5986         }
5987         return false;
5988 }
5989
5990 /*
5991  * Return 1 if L1 wants to intercept an exit from L2.  Only call this when in
5992  * is_guest_mode (L2).
5993  */
5994 static bool nested_vmx_l1_wants_exit(struct kvm_vcpu *vcpu,
5995                                      union vmx_exit_reason exit_reason)
5996 {
5997         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5998         u32 intr_info;
5999
6000         switch ((u16)exit_reason.basic) {
6001         case EXIT_REASON_EXCEPTION_NMI:
6002                 intr_info = vmx_get_intr_info(vcpu);
6003                 if (is_nmi(intr_info))
6004                         return true;
6005                 else if (is_page_fault(intr_info))
6006                         return true;
6007                 return vmcs12->exception_bitmap &
6008                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6009         case EXIT_REASON_EXTERNAL_INTERRUPT:
6010                 return nested_exit_on_intr(vcpu);
6011         case EXIT_REASON_TRIPLE_FAULT:
6012                 return true;
6013         case EXIT_REASON_INTERRUPT_WINDOW:
6014                 return nested_cpu_has(vmcs12, CPU_BASED_INTR_WINDOW_EXITING);
6015         case EXIT_REASON_NMI_WINDOW:
6016                 return nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING);
6017         case EXIT_REASON_TASK_SWITCH:
6018                 return true;
6019         case EXIT_REASON_CPUID:
6020                 return true;
6021         case EXIT_REASON_HLT:
6022                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6023         case EXIT_REASON_INVD:
6024                 return true;
6025         case EXIT_REASON_INVLPG:
6026                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6027         case EXIT_REASON_RDPMC:
6028                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6029         case EXIT_REASON_RDRAND:
6030                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
6031         case EXIT_REASON_RDSEED:
6032                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
6033         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
6034                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6035         case EXIT_REASON_VMREAD:
6036                 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
6037                         vmcs12->vmread_bitmap);
6038         case EXIT_REASON_VMWRITE:
6039                 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
6040                         vmcs12->vmwrite_bitmap);
6041         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6042         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6043         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMRESUME:
6044         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6045         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
6046                 /*
6047                  * VMX instructions trap unconditionally. This allows L1 to
6048                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6049                  */
6050                 return true;
6051         case EXIT_REASON_CR_ACCESS:
6052                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6053         case EXIT_REASON_DR_ACCESS:
6054                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6055         case EXIT_REASON_IO_INSTRUCTION:
6056                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6057         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
6058                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
6059         case EXIT_REASON_MSR_READ:
6060         case EXIT_REASON_MSR_WRITE:
6061                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6062         case EXIT_REASON_INVALID_STATE:
6063                 return true;
6064         case EXIT_REASON_MWAIT_INSTRUCTION:
6065                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6066         case EXIT_REASON_MONITOR_TRAP_FLAG:
6067                 return nested_vmx_exit_handled_mtf(vmcs12);
6068         case EXIT_REASON_MONITOR_INSTRUCTION:
6069                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6070         case EXIT_REASON_PAUSE_INSTRUCTION:
6071                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6072                         nested_cpu_has2(vmcs12,
6073                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6074         case EXIT_REASON_MCE_DURING_VMENTRY:
6075                 return true;
6076         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6077                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
6078         case EXIT_REASON_APIC_ACCESS:
6079         case EXIT_REASON_APIC_WRITE:
6080         case EXIT_REASON_EOI_INDUCED:
6081                 /*
6082                  * The controls for "virtualize APIC accesses," "APIC-
6083                  * register virtualization," and "virtual-interrupt
6084                  * delivery" only come from vmcs12.
6085                  */
6086                 return true;
6087         case EXIT_REASON_INVPCID:
6088                 return
6089                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
6090                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6091         case EXIT_REASON_WBINVD:
6092                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6093         case EXIT_REASON_XSETBV:
6094                 return true;
6095         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
6096                 /*
6097                  * This should never happen, since it is not possible to
6098                  * set XSS to a non-zero value---neither in L1 nor in L2.
6099                  * If if it were, XSS would have to be checked against
6100                  * the XSS exit bitmap in vmcs12.
6101                  */
6102                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
6103         case EXIT_REASON_UMWAIT:
6104         case EXIT_REASON_TPAUSE:
6105                 return nested_cpu_has2(vmcs12,
6106                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE);
6107         case EXIT_REASON_ENCLS:
6108                 return nested_vmx_exit_handled_encls(vcpu, vmcs12);
6109         case EXIT_REASON_NOTIFY:
6110                 /* Notify VM exit is not exposed to L1 */
6111                 return false;
6112         default:
6113                 return true;
6114         }
6115 }
6116
6117 /*
6118  * Conditionally reflect a VM-Exit into L1.  Returns %true if the VM-Exit was
6119  * reflected into L1.
6120  */
6121 bool nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu)
6122 {
6123         struct vcpu_vmx *vmx = to_vmx(vcpu);
6124         union vmx_exit_reason exit_reason = vmx->exit_reason;
6125         unsigned long exit_qual;
6126         u32 exit_intr_info;
6127
6128         WARN_ON_ONCE(vmx->nested.nested_run_pending);
6129
6130         /*
6131          * Late nested VM-Fail shares the same flow as nested VM-Exit since KVM
6132          * has already loaded L2's state.
6133          */
6134         if (unlikely(vmx->fail)) {
6135                 trace_kvm_nested_vmenter_failed(
6136                         "hardware VM-instruction error: ",
6137                         vmcs_read32(VM_INSTRUCTION_ERROR));
6138                 exit_intr_info = 0;
6139                 exit_qual = 0;
6140                 goto reflect_vmexit;
6141         }
6142
6143         trace_kvm_nested_vmexit(vcpu, KVM_ISA_VMX);
6144
6145         /* If L0 (KVM) wants the exit, it trumps L1's desires. */
6146         if (nested_vmx_l0_wants_exit(vcpu, exit_reason))
6147                 return false;
6148
6149         /* If L1 doesn't want the exit, handle it in L0. */
6150         if (!nested_vmx_l1_wants_exit(vcpu, exit_reason))
6151                 return false;
6152
6153         /*
6154          * vmcs.VM_EXIT_INTR_INFO is only valid for EXCEPTION_NMI exits.  For
6155          * EXTERNAL_INTERRUPT, the value for vmcs12->vm_exit_intr_info would
6156          * need to be synthesized by querying the in-kernel LAPIC, but external
6157          * interrupts are never reflected to L1 so it's a non-issue.
6158          */
6159         exit_intr_info = vmx_get_intr_info(vcpu);
6160         if (is_exception_with_error_code(exit_intr_info)) {
6161                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6162
6163                 vmcs12->vm_exit_intr_error_code =
6164                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6165         }
6166         exit_qual = vmx_get_exit_qual(vcpu);
6167
6168 reflect_vmexit:
6169         nested_vmx_vmexit(vcpu, exit_reason.full, exit_intr_info, exit_qual);
6170         return true;
6171 }
6172
6173 static int vmx_get_nested_state(struct kvm_vcpu *vcpu,
6174                                 struct kvm_nested_state __user *user_kvm_nested_state,
6175                                 u32 user_data_size)
6176 {
6177         struct vcpu_vmx *vmx;
6178         struct vmcs12 *vmcs12;
6179         struct kvm_nested_state kvm_state = {
6180                 .flags = 0,
6181                 .format = KVM_STATE_NESTED_FORMAT_VMX,
6182                 .size = sizeof(kvm_state),
6183                 .hdr.vmx.flags = 0,
6184                 .hdr.vmx.vmxon_pa = INVALID_GPA,
6185                 .hdr.vmx.vmcs12_pa = INVALID_GPA,
6186                 .hdr.vmx.preemption_timer_deadline = 0,
6187         };
6188         struct kvm_vmx_nested_state_data __user *user_vmx_nested_state =
6189                 &user_kvm_nested_state->data.vmx[0];
6190
6191         if (!vcpu)
6192                 return kvm_state.size + sizeof(*user_vmx_nested_state);
6193
6194         vmx = to_vmx(vcpu);
6195         vmcs12 = get_vmcs12(vcpu);
6196
6197         if (nested_vmx_allowed(vcpu) &&
6198             (vmx->nested.vmxon || vmx->nested.smm.vmxon)) {
6199                 kvm_state.hdr.vmx.vmxon_pa = vmx->nested.vmxon_ptr;
6200                 kvm_state.hdr.vmx.vmcs12_pa = vmx->nested.current_vmptr;
6201
6202                 if (vmx_has_valid_vmcs12(vcpu)) {
6203                         kvm_state.size += sizeof(user_vmx_nested_state->vmcs12);
6204
6205                         /* 'hv_evmcs_vmptr' can also be EVMPTR_MAP_PENDING here */
6206                         if (vmx->nested.hv_evmcs_vmptr != EVMPTR_INVALID)
6207                                 kvm_state.flags |= KVM_STATE_NESTED_EVMCS;
6208
6209                         if (is_guest_mode(vcpu) &&
6210                             nested_cpu_has_shadow_vmcs(vmcs12) &&
6211                             vmcs12->vmcs_link_pointer != INVALID_GPA)
6212                                 kvm_state.size += sizeof(user_vmx_nested_state->shadow_vmcs12);
6213                 }
6214
6215                 if (vmx->nested.smm.vmxon)
6216                         kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_VMXON;
6217
6218                 if (vmx->nested.smm.guest_mode)
6219                         kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_GUEST_MODE;
6220
6221                 if (is_guest_mode(vcpu)) {
6222                         kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE;
6223
6224                         if (vmx->nested.nested_run_pending)
6225                                 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING;
6226
6227                         if (vmx->nested.mtf_pending)
6228                                 kvm_state.flags |= KVM_STATE_NESTED_MTF_PENDING;
6229
6230                         if (nested_cpu_has_preemption_timer(vmcs12) &&
6231                             vmx->nested.has_preemption_timer_deadline) {
6232                                 kvm_state.hdr.vmx.flags |=
6233                                         KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE;
6234                                 kvm_state.hdr.vmx.preemption_timer_deadline =
6235                                         vmx->nested.preemption_timer_deadline;
6236                         }
6237                 }
6238         }
6239
6240         if (user_data_size < kvm_state.size)
6241                 goto out;
6242
6243         if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state)))
6244                 return -EFAULT;
6245
6246         if (!vmx_has_valid_vmcs12(vcpu))
6247                 goto out;
6248
6249         /*
6250          * When running L2, the authoritative vmcs12 state is in the
6251          * vmcs02. When running L1, the authoritative vmcs12 state is
6252          * in the shadow or enlightened vmcs linked to vmcs01, unless
6253          * need_vmcs12_to_shadow_sync is set, in which case, the authoritative
6254          * vmcs12 state is in the vmcs12 already.
6255          */
6256         if (is_guest_mode(vcpu)) {
6257                 sync_vmcs02_to_vmcs12(vcpu, vmcs12);
6258                 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
6259         } else  {
6260                 copy_vmcs02_to_vmcs12_rare(vcpu, get_vmcs12(vcpu));
6261                 if (!vmx->nested.need_vmcs12_to_shadow_sync) {
6262                         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
6263                                 /*
6264                                  * L1 hypervisor is not obliged to keep eVMCS
6265                                  * clean fields data always up-to-date while
6266                                  * not in guest mode, 'hv_clean_fields' is only
6267                                  * supposed to be actual upon vmentry so we need
6268                                  * to ignore it here and do full copy.
6269                                  */
6270                                 copy_enlightened_to_vmcs12(vmx, 0);
6271                         else if (enable_shadow_vmcs)
6272                                 copy_shadow_to_vmcs12(vmx);
6273                 }
6274         }
6275
6276         BUILD_BUG_ON(sizeof(user_vmx_nested_state->vmcs12) < VMCS12_SIZE);
6277         BUILD_BUG_ON(sizeof(user_vmx_nested_state->shadow_vmcs12) < VMCS12_SIZE);
6278
6279         /*
6280          * Copy over the full allocated size of vmcs12 rather than just the size
6281          * of the struct.
6282          */
6283         if (copy_to_user(user_vmx_nested_state->vmcs12, vmcs12, VMCS12_SIZE))
6284                 return -EFAULT;
6285
6286         if (nested_cpu_has_shadow_vmcs(vmcs12) &&
6287             vmcs12->vmcs_link_pointer != INVALID_GPA) {
6288                 if (copy_to_user(user_vmx_nested_state->shadow_vmcs12,
6289                                  get_shadow_vmcs12(vcpu), VMCS12_SIZE))
6290                         return -EFAULT;
6291         }
6292 out:
6293         return kvm_state.size;
6294 }
6295
6296 /*
6297  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
6298  */
6299 void vmx_leave_nested(struct kvm_vcpu *vcpu)
6300 {
6301         if (is_guest_mode(vcpu)) {
6302                 to_vmx(vcpu)->nested.nested_run_pending = 0;
6303                 nested_vmx_vmexit(vcpu, -1, 0, 0);
6304         }
6305         free_nested(vcpu);
6306 }
6307
6308 static int vmx_set_nested_state(struct kvm_vcpu *vcpu,
6309                                 struct kvm_nested_state __user *user_kvm_nested_state,
6310                                 struct kvm_nested_state *kvm_state)
6311 {
6312         struct vcpu_vmx *vmx = to_vmx(vcpu);
6313         struct vmcs12 *vmcs12;
6314         enum vm_entry_failure_code ignored;
6315         struct kvm_vmx_nested_state_data __user *user_vmx_nested_state =
6316                 &user_kvm_nested_state->data.vmx[0];
6317         int ret;
6318
6319         if (kvm_state->format != KVM_STATE_NESTED_FORMAT_VMX)
6320                 return -EINVAL;
6321
6322         if (kvm_state->hdr.vmx.vmxon_pa == INVALID_GPA) {
6323                 if (kvm_state->hdr.vmx.smm.flags)
6324                         return -EINVAL;
6325
6326                 if (kvm_state->hdr.vmx.vmcs12_pa != INVALID_GPA)
6327                         return -EINVAL;
6328
6329                 /*
6330                  * KVM_STATE_NESTED_EVMCS used to signal that KVM should
6331                  * enable eVMCS capability on vCPU. However, since then
6332                  * code was changed such that flag signals vmcs12 should
6333                  * be copied into eVMCS in guest memory.
6334                  *
6335                  * To preserve backwards compatability, allow user
6336                  * to set this flag even when there is no VMXON region.
6337                  */
6338                 if (kvm_state->flags & ~KVM_STATE_NESTED_EVMCS)
6339                         return -EINVAL;
6340         } else {
6341                 if (!nested_vmx_allowed(vcpu))
6342                         return -EINVAL;
6343
6344                 if (!page_address_valid(vcpu, kvm_state->hdr.vmx.vmxon_pa))
6345                         return -EINVAL;
6346         }
6347
6348         if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
6349             (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
6350                 return -EINVAL;
6351
6352         if (kvm_state->hdr.vmx.smm.flags &
6353             ~(KVM_STATE_NESTED_SMM_GUEST_MODE | KVM_STATE_NESTED_SMM_VMXON))
6354                 return -EINVAL;
6355
6356         if (kvm_state->hdr.vmx.flags & ~KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE)
6357                 return -EINVAL;
6358
6359         /*
6360          * SMM temporarily disables VMX, so we cannot be in guest mode,
6361          * nor can VMLAUNCH/VMRESUME be pending.  Outside SMM, SMM flags
6362          * must be zero.
6363          */
6364         if (is_smm(vcpu) ?
6365                 (kvm_state->flags &
6366                  (KVM_STATE_NESTED_GUEST_MODE | KVM_STATE_NESTED_RUN_PENDING))
6367                 : kvm_state->hdr.vmx.smm.flags)
6368                 return -EINVAL;
6369
6370         if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
6371             !(kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON))
6372                 return -EINVAL;
6373
6374         if ((kvm_state->flags & KVM_STATE_NESTED_EVMCS) &&
6375                 (!nested_vmx_allowed(vcpu) || !vmx->nested.enlightened_vmcs_enabled))
6376                         return -EINVAL;
6377
6378         vmx_leave_nested(vcpu);
6379
6380         if (kvm_state->hdr.vmx.vmxon_pa == INVALID_GPA)
6381                 return 0;
6382
6383         vmx->nested.vmxon_ptr = kvm_state->hdr.vmx.vmxon_pa;
6384         ret = enter_vmx_operation(vcpu);
6385         if (ret)
6386                 return ret;
6387
6388         /* Empty 'VMXON' state is permitted if no VMCS loaded */
6389         if (kvm_state->size < sizeof(*kvm_state) + sizeof(*vmcs12)) {
6390                 /* See vmx_has_valid_vmcs12.  */
6391                 if ((kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE) ||
6392                     (kvm_state->flags & KVM_STATE_NESTED_EVMCS) ||
6393                     (kvm_state->hdr.vmx.vmcs12_pa != INVALID_GPA))
6394                         return -EINVAL;
6395                 else
6396                         return 0;
6397         }
6398
6399         if (kvm_state->hdr.vmx.vmcs12_pa != INVALID_GPA) {
6400                 if (kvm_state->hdr.vmx.vmcs12_pa == kvm_state->hdr.vmx.vmxon_pa ||
6401                     !page_address_valid(vcpu, kvm_state->hdr.vmx.vmcs12_pa))
6402                         return -EINVAL;
6403
6404                 set_current_vmptr(vmx, kvm_state->hdr.vmx.vmcs12_pa);
6405         } else if (kvm_state->flags & KVM_STATE_NESTED_EVMCS) {
6406                 /*
6407                  * nested_vmx_handle_enlightened_vmptrld() cannot be called
6408                  * directly from here as HV_X64_MSR_VP_ASSIST_PAGE may not be
6409                  * restored yet. EVMCS will be mapped from
6410                  * nested_get_vmcs12_pages().
6411                  */
6412                 vmx->nested.hv_evmcs_vmptr = EVMPTR_MAP_PENDING;
6413                 kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu);
6414         } else {
6415                 return -EINVAL;
6416         }
6417
6418         if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON) {
6419                 vmx->nested.smm.vmxon = true;
6420                 vmx->nested.vmxon = false;
6421
6422                 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE)
6423                         vmx->nested.smm.guest_mode = true;
6424         }
6425
6426         vmcs12 = get_vmcs12(vcpu);
6427         if (copy_from_user(vmcs12, user_vmx_nested_state->vmcs12, sizeof(*vmcs12)))
6428                 return -EFAULT;
6429
6430         if (vmcs12->hdr.revision_id != VMCS12_REVISION)
6431                 return -EINVAL;
6432
6433         if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
6434                 return 0;
6435
6436         vmx->nested.nested_run_pending =
6437                 !!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);
6438
6439         vmx->nested.mtf_pending =
6440                 !!(kvm_state->flags & KVM_STATE_NESTED_MTF_PENDING);
6441
6442         ret = -EINVAL;
6443         if (nested_cpu_has_shadow_vmcs(vmcs12) &&
6444             vmcs12->vmcs_link_pointer != INVALID_GPA) {
6445                 struct vmcs12 *shadow_vmcs12 = get_shadow_vmcs12(vcpu);
6446
6447                 if (kvm_state->size <
6448                     sizeof(*kvm_state) +
6449                     sizeof(user_vmx_nested_state->vmcs12) + sizeof(*shadow_vmcs12))
6450                         goto error_guest_mode;
6451
6452                 if (copy_from_user(shadow_vmcs12,
6453                                    user_vmx_nested_state->shadow_vmcs12,
6454                                    sizeof(*shadow_vmcs12))) {
6455                         ret = -EFAULT;
6456                         goto error_guest_mode;
6457                 }
6458
6459                 if (shadow_vmcs12->hdr.revision_id != VMCS12_REVISION ||
6460                     !shadow_vmcs12->hdr.shadow_vmcs)
6461                         goto error_guest_mode;
6462         }
6463
6464         vmx->nested.has_preemption_timer_deadline = false;
6465         if (kvm_state->hdr.vmx.flags & KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE) {
6466                 vmx->nested.has_preemption_timer_deadline = true;
6467                 vmx->nested.preemption_timer_deadline =
6468                         kvm_state->hdr.vmx.preemption_timer_deadline;
6469         }
6470
6471         if (nested_vmx_check_controls(vcpu, vmcs12) ||
6472             nested_vmx_check_host_state(vcpu, vmcs12) ||
6473             nested_vmx_check_guest_state(vcpu, vmcs12, &ignored))
6474                 goto error_guest_mode;
6475
6476         vmx->nested.dirty_vmcs12 = true;
6477         vmx->nested.force_msr_bitmap_recalc = true;
6478         ret = nested_vmx_enter_non_root_mode(vcpu, false);
6479         if (ret)
6480                 goto error_guest_mode;
6481
6482         return 0;
6483
6484 error_guest_mode:
6485         vmx->nested.nested_run_pending = 0;
6486         return ret;
6487 }
6488
6489 void nested_vmx_set_vmcs_shadowing_bitmap(void)
6490 {
6491         if (enable_shadow_vmcs) {
6492                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6493                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
6494         }
6495 }
6496
6497 /*
6498  * Indexing into the vmcs12 uses the VMCS encoding rotated left by 6.  Undo
6499  * that madness to get the encoding for comparison.
6500  */
6501 #define VMCS12_IDX_TO_ENC(idx) ((u16)(((u16)(idx) >> 6) | ((u16)(idx) << 10)))
6502
6503 static u64 nested_vmx_calc_vmcs_enum_msr(void)
6504 {
6505         /*
6506          * Note these are the so called "index" of the VMCS field encoding, not
6507          * the index into vmcs12.
6508          */
6509         unsigned int max_idx, idx;
6510         int i;
6511
6512         /*
6513          * For better or worse, KVM allows VMREAD/VMWRITE to all fields in
6514          * vmcs12, regardless of whether or not the associated feature is
6515          * exposed to L1.  Simply find the field with the highest index.
6516          */
6517         max_idx = 0;
6518         for (i = 0; i < nr_vmcs12_fields; i++) {
6519                 /* The vmcs12 table is very, very sparsely populated. */
6520                 if (!vmcs12_field_offsets[i])
6521                         continue;
6522
6523                 idx = vmcs_field_index(VMCS12_IDX_TO_ENC(i));
6524                 if (idx > max_idx)
6525                         max_idx = idx;
6526         }
6527
6528         return (u64)max_idx << VMCS_FIELD_INDEX_SHIFT;
6529 }
6530
6531 /*
6532  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
6533  * returned for the various VMX controls MSRs when nested VMX is enabled.
6534  * The same values should also be used to verify that vmcs12 control fields are
6535  * valid during nested entry from L1 to L2.
6536  * Each of these control msrs has a low and high 32-bit half: A low bit is on
6537  * if the corresponding bit in the (32-bit) control field *must* be on, and a
6538  * bit in the high half is on if the corresponding bit in the control field
6539  * may be on. See also vmx_control_verify().
6540  */
6541 void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps)
6542 {
6543         /*
6544          * Note that as a general rule, the high half of the MSRs (bits in
6545          * the control fields which may be 1) should be initialized by the
6546          * intersection of the underlying hardware's MSR (i.e., features which
6547          * can be supported) and the list of features we want to expose -
6548          * because they are known to be properly supported in our code.
6549          * Also, usually, the low half of the MSRs (bits which must be 1) can
6550          * be set to 0, meaning that L1 may turn off any of these bits. The
6551          * reason is that if one of these bits is necessary, it will appear
6552          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
6553          * fields of vmcs01 and vmcs02, will turn these bits off - and
6554          * nested_vmx_l1_wants_exit() will not pass related exits to L1.
6555          * These rules have exceptions below.
6556          */
6557
6558         /* pin-based controls */
6559         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
6560                 msrs->pinbased_ctls_low,
6561                 msrs->pinbased_ctls_high);
6562         msrs->pinbased_ctls_low |=
6563                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
6564         msrs->pinbased_ctls_high &=
6565                 PIN_BASED_EXT_INTR_MASK |
6566                 PIN_BASED_NMI_EXITING |
6567                 PIN_BASED_VIRTUAL_NMIS |
6568                 (enable_apicv ? PIN_BASED_POSTED_INTR : 0);
6569         msrs->pinbased_ctls_high |=
6570                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
6571                 PIN_BASED_VMX_PREEMPTION_TIMER;
6572
6573         /* exit controls */
6574         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
6575                 msrs->exit_ctls_low,
6576                 msrs->exit_ctls_high);
6577         msrs->exit_ctls_low =
6578                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
6579
6580         msrs->exit_ctls_high &=
6581 #ifdef CONFIG_X86_64
6582                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
6583 #endif
6584                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
6585                 VM_EXIT_CLEAR_BNDCFGS | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
6586         msrs->exit_ctls_high |=
6587                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
6588                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
6589                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
6590
6591         /* We support free control of debug control saving. */
6592         msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
6593
6594         /* entry controls */
6595         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
6596                 msrs->entry_ctls_low,
6597                 msrs->entry_ctls_high);
6598         msrs->entry_ctls_low =
6599                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
6600         msrs->entry_ctls_high &=
6601 #ifdef CONFIG_X86_64
6602                 VM_ENTRY_IA32E_MODE |
6603 #endif
6604                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS |
6605                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
6606         msrs->entry_ctls_high |=
6607                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
6608
6609         /* We support free control of debug control loading. */
6610         msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
6611
6612         /* cpu-based controls */
6613         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
6614                 msrs->procbased_ctls_low,
6615                 msrs->procbased_ctls_high);
6616         msrs->procbased_ctls_low =
6617                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
6618         msrs->procbased_ctls_high &=
6619                 CPU_BASED_INTR_WINDOW_EXITING |
6620                 CPU_BASED_NMI_WINDOW_EXITING | CPU_BASED_USE_TSC_OFFSETTING |
6621                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
6622                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
6623                 CPU_BASED_CR3_STORE_EXITING |
6624 #ifdef CONFIG_X86_64
6625                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
6626 #endif
6627                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
6628                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
6629                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
6630                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
6631                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
6632         /*
6633          * We can allow some features even when not supported by the
6634          * hardware. For example, L1 can specify an MSR bitmap - and we
6635          * can use it to avoid exits to L1 - even when L0 runs L2
6636          * without MSR bitmaps.
6637          */
6638         msrs->procbased_ctls_high |=
6639                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
6640                 CPU_BASED_USE_MSR_BITMAPS;
6641
6642         /* We support free control of CR3 access interception. */
6643         msrs->procbased_ctls_low &=
6644                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
6645
6646         /*
6647          * secondary cpu-based controls.  Do not include those that
6648          * depend on CPUID bits, they are added later by
6649          * vmx_vcpu_after_set_cpuid.
6650          */
6651         if (msrs->procbased_ctls_high & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
6652                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
6653                       msrs->secondary_ctls_low,
6654                       msrs->secondary_ctls_high);
6655
6656         msrs->secondary_ctls_low = 0;
6657         msrs->secondary_ctls_high &=
6658                 SECONDARY_EXEC_DESC |
6659                 SECONDARY_EXEC_ENABLE_RDTSCP |
6660                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6661                 SECONDARY_EXEC_WBINVD_EXITING |
6662                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
6663                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
6664                 SECONDARY_EXEC_RDRAND_EXITING |
6665                 SECONDARY_EXEC_ENABLE_INVPCID |
6666                 SECONDARY_EXEC_RDSEED_EXITING |
6667                 SECONDARY_EXEC_XSAVES |
6668                 SECONDARY_EXEC_TSC_SCALING;
6669
6670         /*
6671          * We can emulate "VMCS shadowing," even if the hardware
6672          * doesn't support it.
6673          */
6674         msrs->secondary_ctls_high |=
6675                 SECONDARY_EXEC_SHADOW_VMCS;
6676
6677         if (enable_ept) {
6678                 /* nested EPT: emulate EPT also to L1 */
6679                 msrs->secondary_ctls_high |=
6680                         SECONDARY_EXEC_ENABLE_EPT;
6681                 msrs->ept_caps =
6682                         VMX_EPT_PAGE_WALK_4_BIT |
6683                         VMX_EPT_PAGE_WALK_5_BIT |
6684                         VMX_EPTP_WB_BIT |
6685                         VMX_EPT_INVEPT_BIT |
6686                         VMX_EPT_EXECUTE_ONLY_BIT;
6687
6688                 msrs->ept_caps &= ept_caps;
6689                 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
6690                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
6691                         VMX_EPT_1GB_PAGE_BIT;
6692                 if (enable_ept_ad_bits) {
6693                         msrs->secondary_ctls_high |=
6694                                 SECONDARY_EXEC_ENABLE_PML;
6695                         msrs->ept_caps |= VMX_EPT_AD_BIT;
6696                 }
6697         }
6698
6699         if (cpu_has_vmx_vmfunc()) {
6700                 msrs->secondary_ctls_high |=
6701                         SECONDARY_EXEC_ENABLE_VMFUNC;
6702                 /*
6703                  * Advertise EPTP switching unconditionally
6704                  * since we emulate it
6705                  */
6706                 if (enable_ept)
6707                         msrs->vmfunc_controls =
6708                                 VMX_VMFUNC_EPTP_SWITCHING;
6709         }
6710
6711         /*
6712          * Old versions of KVM use the single-context version without
6713          * checking for support, so declare that it is supported even
6714          * though it is treated as global context.  The alternative is
6715          * not failing the single-context invvpid, and it is worse.
6716          */
6717         if (enable_vpid) {
6718                 msrs->secondary_ctls_high |=
6719                         SECONDARY_EXEC_ENABLE_VPID;
6720                 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
6721                         VMX_VPID_EXTENT_SUPPORTED_MASK;
6722         }
6723
6724         if (enable_unrestricted_guest)
6725                 msrs->secondary_ctls_high |=
6726                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
6727
6728         if (flexpriority_enabled)
6729                 msrs->secondary_ctls_high |=
6730                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6731
6732         if (enable_sgx)
6733                 msrs->secondary_ctls_high |= SECONDARY_EXEC_ENCLS_EXITING;
6734
6735         /* miscellaneous data */
6736         rdmsr(MSR_IA32_VMX_MISC,
6737                 msrs->misc_low,
6738                 msrs->misc_high);
6739         msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
6740         msrs->misc_low |=
6741                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
6742                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
6743                 VMX_MISC_ACTIVITY_HLT |
6744                 VMX_MISC_ACTIVITY_WAIT_SIPI;
6745         msrs->misc_high = 0;
6746
6747         /*
6748          * This MSR reports some information about VMX support. We
6749          * should return information about the VMX we emulate for the
6750          * guest, and the VMCS structure we give it - not about the
6751          * VMX support of the underlying hardware.
6752          */
6753         msrs->basic =
6754                 VMCS12_REVISION |
6755                 VMX_BASIC_TRUE_CTLS |
6756                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
6757                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
6758
6759         if (cpu_has_vmx_basic_inout())
6760                 msrs->basic |= VMX_BASIC_INOUT;
6761
6762         /*
6763          * These MSRs specify bits which the guest must keep fixed on
6764          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
6765          * We picked the standard core2 setting.
6766          */
6767 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
6768 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
6769         msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
6770         msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
6771
6772         /* These MSRs specify bits which the guest must keep fixed off. */
6773         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
6774         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
6775
6776         msrs->vmcs_enum = nested_vmx_calc_vmcs_enum_msr();
6777 }
6778
6779 void nested_vmx_hardware_unsetup(void)
6780 {
6781         int i;
6782
6783         if (enable_shadow_vmcs) {
6784                 for (i = 0; i < VMX_BITMAP_NR; i++)
6785                         free_page((unsigned long)vmx_bitmap[i]);
6786         }
6787 }
6788
6789 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *))
6790 {
6791         int i;
6792
6793         if (!cpu_has_vmx_shadow_vmcs())
6794                 enable_shadow_vmcs = 0;
6795         if (enable_shadow_vmcs) {
6796                 for (i = 0; i < VMX_BITMAP_NR; i++) {
6797                         /*
6798                          * The vmx_bitmap is not tied to a VM and so should
6799                          * not be charged to a memcg.
6800                          */
6801                         vmx_bitmap[i] = (unsigned long *)
6802                                 __get_free_page(GFP_KERNEL);
6803                         if (!vmx_bitmap[i]) {
6804                                 nested_vmx_hardware_unsetup();
6805                                 return -ENOMEM;
6806                         }
6807                 }
6808
6809                 init_vmcs_shadow_fields();
6810         }
6811
6812         exit_handlers[EXIT_REASON_VMCLEAR]      = handle_vmclear;
6813         exit_handlers[EXIT_REASON_VMLAUNCH]     = handle_vmlaunch;
6814         exit_handlers[EXIT_REASON_VMPTRLD]      = handle_vmptrld;
6815         exit_handlers[EXIT_REASON_VMPTRST]      = handle_vmptrst;
6816         exit_handlers[EXIT_REASON_VMREAD]       = handle_vmread;
6817         exit_handlers[EXIT_REASON_VMRESUME]     = handle_vmresume;
6818         exit_handlers[EXIT_REASON_VMWRITE]      = handle_vmwrite;
6819         exit_handlers[EXIT_REASON_VMOFF]        = handle_vmoff;
6820         exit_handlers[EXIT_REASON_VMON]         = handle_vmon;
6821         exit_handlers[EXIT_REASON_INVEPT]       = handle_invept;
6822         exit_handlers[EXIT_REASON_INVVPID]      = handle_invvpid;
6823         exit_handlers[EXIT_REASON_VMFUNC]       = handle_vmfunc;
6824
6825         return 0;
6826 }
6827
6828 struct kvm_x86_nested_ops vmx_nested_ops = {
6829         .leave_nested = vmx_leave_nested,
6830         .check_events = vmx_check_nested_events,
6831         .handle_page_fault_workaround = nested_vmx_handle_page_fault_workaround,
6832         .hv_timer_pending = nested_vmx_preemption_timer_pending,
6833         .triple_fault = nested_vmx_triple_fault,
6834         .get_state = vmx_get_nested_state,
6835         .set_state = vmx_set_nested_state,
6836         .get_nested_state_pages = vmx_get_nested_state_pages,
6837         .write_log_dirty = nested_vmx_write_pml_buffer,
6838         .enable_evmcs = nested_enable_evmcs,
6839         .get_evmcs_version = nested_get_evmcs_version,
6840 };