arch/x86/kvm/vmx/hyperv.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __KVM_X86_VMX_HYPERV_H
   3 #define __KVM_X86_VMX_HYPERV_H
   4
   5 #include <linux/jump_label.h>
   6
   7 #include <asm/hyperv-tlfs.h>
   8 #include <asm/mshyperv.h>
   9 #include <asm/vmx.h>
  10
  11 #include "../hyperv.h"
  12
  13 #include "capabilities.h"
  14 #include "vmcs.h"
  15 #include "vmcs12.h"
  16
  17 #define KVM_EVMCS_VERSION 1
  18
  19 /*
  20  * Enlightened VMCSv1 doesn't support these:
  21  *
  22  *      POSTED_INTR_NV                  = 0x00000002,
  23  *      GUEST_INTR_STATUS               = 0x00000810,
  24  *      APIC_ACCESS_ADDR                = 0x00002014,
  25  *      POSTED_INTR_DESC_ADDR           = 0x00002016,
  26  *      EOI_EXIT_BITMAP0                = 0x0000201c,
  27  *      EOI_EXIT_BITMAP1                = 0x0000201e,
  28  *      EOI_EXIT_BITMAP2                = 0x00002020,
  29  *      EOI_EXIT_BITMAP3                = 0x00002022,
  30  *      GUEST_PML_INDEX                 = 0x00000812,
  31  *      PML_ADDRESS                     = 0x0000200e,
  32  *      VM_FUNCTION_CONTROL             = 0x00002018,
  33  *      EPTP_LIST_ADDRESS               = 0x00002024,
  34  *      VMREAD_BITMAP                   = 0x00002026,
  35  *      VMWRITE_BITMAP                  = 0x00002028,
  36  *
  37  *      TSC_MULTIPLIER                  = 0x00002032,
  38  *      PLE_GAP                         = 0x00004020,
  39  *      PLE_WINDOW                      = 0x00004022,
  40  *      VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
  41  *
  42  * Currently unsupported in KVM:
  43  *      GUEST_IA32_RTIT_CTL             = 0x00002814,
  44  */
  45 #define EVMCS1_SUPPORTED_PINCTRL                                        \
  46         (PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |                          \
  47          PIN_BASED_EXT_INTR_MASK |                                      \
  48          PIN_BASED_NMI_EXITING |                                        \
  49          PIN_BASED_VIRTUAL_NMIS)
  50
  51 #define EVMCS1_SUPPORTED_EXEC_CTRL                                      \
  52         (CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |                          \
  53          CPU_BASED_HLT_EXITING |                                        \
  54          CPU_BASED_CR3_LOAD_EXITING |                                   \
  55          CPU_BASED_CR3_STORE_EXITING |                                  \
  56          CPU_BASED_UNCOND_IO_EXITING |                                  \
  57          CPU_BASED_MOV_DR_EXITING |                                     \
  58          CPU_BASED_USE_TSC_OFFSETTING |                                 \
  59          CPU_BASED_MWAIT_EXITING |                                      \
  60          CPU_BASED_MONITOR_EXITING |                                    \
  61          CPU_BASED_INVLPG_EXITING |                                     \
  62          CPU_BASED_RDPMC_EXITING |                                      \
  63          CPU_BASED_INTR_WINDOW_EXITING |                                \
  64          CPU_BASED_CR8_LOAD_EXITING |                                   \
  65          CPU_BASED_CR8_STORE_EXITING |                                  \
  66          CPU_BASED_RDTSC_EXITING |                                      \
  67          CPU_BASED_TPR_SHADOW |                                         \
  68          CPU_BASED_USE_IO_BITMAPS |                                     \
  69          CPU_BASED_MONITOR_TRAP_FLAG |                                  \
  70          CPU_BASED_USE_MSR_BITMAPS |                                    \
  71          CPU_BASED_NMI_WINDOW_EXITING |                                 \
  72          CPU_BASED_PAUSE_EXITING |                                      \
  73          CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
  74
  75 #define EVMCS1_SUPPORTED_2NDEXEC                                        \
  76         (SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |                        \
  77          SECONDARY_EXEC_WBINVD_EXITING |                                \
  78          SECONDARY_EXEC_ENABLE_VPID |                                   \
  79          SECONDARY_EXEC_ENABLE_EPT |                                    \
  80          SECONDARY_EXEC_UNRESTRICTED_GUEST |                            \
  81          SECONDARY_EXEC_DESC |                                          \
  82          SECONDARY_EXEC_ENABLE_RDTSCP |                                 \
  83          SECONDARY_EXEC_ENABLE_INVPCID |                                \
  84          SECONDARY_EXEC_ENABLE_XSAVES |                                 \
  85          SECONDARY_EXEC_RDSEED_EXITING |                                \
  86          SECONDARY_EXEC_RDRAND_EXITING |                                \
  87          SECONDARY_EXEC_TSC_SCALING |                                   \
  88          SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |                         \
  89          SECONDARY_EXEC_PT_USE_GPA |                                    \
  90          SECONDARY_EXEC_PT_CONCEAL_VMX |                                \
  91          SECONDARY_EXEC_BUS_LOCK_DETECTION |                            \
  92          SECONDARY_EXEC_NOTIFY_VM_EXITING |                             \
  93          SECONDARY_EXEC_ENCLS_EXITING)
  94
  95 #define EVMCS1_SUPPORTED_3RDEXEC (0ULL)
  96
  97 #define EVMCS1_SUPPORTED_VMEXIT_CTRL                                    \
  98         (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |                            \
  99          VM_EXIT_SAVE_DEBUG_CONTROLS |                                  \
 100          VM_EXIT_ACK_INTR_ON_EXIT |                                     \
 101          VM_EXIT_HOST_ADDR_SPACE_SIZE |                                 \
 102          VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |                           \
 103          VM_EXIT_SAVE_IA32_PAT |                                        \
 104          VM_EXIT_LOAD_IA32_PAT |                                        \
 105          VM_EXIT_SAVE_IA32_EFER |                                       \
 106          VM_EXIT_LOAD_IA32_EFER |                                       \
 107          VM_EXIT_CLEAR_BNDCFGS |                                        \
 108          VM_EXIT_PT_CONCEAL_PIP |                                       \
 109          VM_EXIT_CLEAR_IA32_RTIT_CTL)
 110
 111 #define EVMCS1_SUPPORTED_VMENTRY_CTRL                                   \
 112         (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |                           \
 113          VM_ENTRY_LOAD_DEBUG_CONTROLS |                                 \
 114          VM_ENTRY_IA32E_MODE |                                          \
 115          VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |                          \
 116          VM_ENTRY_LOAD_IA32_PAT |                                       \
 117          VM_ENTRY_LOAD_IA32_EFER |                                      \
 118          VM_ENTRY_LOAD_BNDCFGS |                                        \
 119          VM_ENTRY_PT_CONCEAL_PIP |                                      \
 120          VM_ENTRY_LOAD_IA32_RTIT_CTL)
 121
 122 #define EVMCS1_SUPPORTED_VMFUNC (0)
 123
 124 struct evmcs_field {
 125         u16 offset;
 126         u16 clean_field;
 127 };
 128
 129 extern const struct evmcs_field vmcs_field_to_evmcs_1[];
 130 extern const unsigned int nr_evmcs_1_fields;
 131
 132 static __always_inline int evmcs_field_offset(unsigned long field,
 133                                               u16 *clean_field)
 134 {
 135         unsigned int index = ROL16(field, 6);
 136         const struct evmcs_field *evmcs_field;
 137
 138         if (unlikely(index >= nr_evmcs_1_fields))
 139                 return -ENOENT;
 140
 141         evmcs_field = &vmcs_field_to_evmcs_1[index];
 142
 143         /*
 144          * Use offset=0 to detect holes in eVMCS. This offset belongs to
 145          * 'revision_id' but this field has no encoding and is supposed to
 146          * be accessed directly.
 147          */
 148         if (unlikely(!evmcs_field->offset))
 149                 return -ENOENT;
 150
 151         if (clean_field)
 152                 *clean_field = evmcs_field->clean_field;
 153
 154         return evmcs_field->offset;
 155 }
 156
 157 static inline u64 evmcs_read_any(struct hv_enlightened_vmcs *evmcs,
 158                                  unsigned long field, u16 offset)
 159 {
 160         /*
 161          * vmcs12_read_any() doesn't care whether the supplied structure
 162          * is 'struct vmcs12' or 'struct hv_enlightened_vmcs' as it takes
 163          * the exact offset of the required field, use it for convenience
 164          * here.
 165          */
 166         return vmcs12_read_any((void *)evmcs, field, offset);
 167 }
 168
 169 #define EVMPTR_INVALID (-1ULL)
 170 #define EVMPTR_MAP_PENDING (-2ULL)
 171
 172 static inline bool evmptr_is_valid(u64 evmptr)
 173 {
 174         return evmptr != EVMPTR_INVALID && evmptr != EVMPTR_MAP_PENDING;
 175 }
 176
 177 enum nested_evmptrld_status {
 178         EVMPTRLD_DISABLED,
 179         EVMPTRLD_SUCCEEDED,
 180         EVMPTRLD_VMFAIL,
 181         EVMPTRLD_ERROR,
 182 };
 183
 184 u64 nested_get_evmptr(struct kvm_vcpu *vcpu);
 185 uint16_t nested_get_evmcs_version(struct kvm_vcpu *vcpu);
 186 int nested_enable_evmcs(struct kvm_vcpu *vcpu,
 187                         uint16_t *vmcs_version);
 188 void nested_evmcs_filter_control_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata);
 189 int nested_evmcs_check_controls(struct vmcs12 *vmcs12);
 190 bool nested_evmcs_l2_tlb_flush_enabled(struct kvm_vcpu *vcpu);
 191 void vmx_hv_inject_synthetic_vmexit_post_tlb_flush(struct kvm_vcpu *vcpu);
 192
 193 #endif /* __KVM_X86_VMX_HYPERV_H */