1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Yaniv Kamay <yaniv@qumranet.com>
12 * Avi Kivity <avi@qumranet.com>
15 #define pr_fmt(fmt) "SVM: " fmt
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/hashtable.h>
36 #include <linux/frame.h>
37 #include <linux/psp-sev.h>
38 #include <linux/file.h>
39 #include <linux/pagemap.h>
40 #include <linux/swap.h>
41 #include <linux/rwsem.h>
44 #include <asm/perf_event.h>
45 #include <asm/tlbflush.h>
47 #include <asm/debugreg.h>
48 #include <asm/kvm_para.h>
49 #include <asm/irq_remapping.h>
50 #include <asm/spec-ctrl.h>
52 #include <asm/virtext.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
57 MODULE_AUTHOR("Qumranet");
58 MODULE_LICENSE("GPL");
60 static const struct x86_cpu_id svm_cpu_id[] = {
61 X86_FEATURE_MATCH(X86_FEATURE_SVM),
64 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
66 #define IOPM_ALLOC_ORDER 2
67 #define MSRPM_ALLOC_ORDER 1
69 #define SEG_TYPE_LDT 2
70 #define SEG_TYPE_BUSY_TSS16 3
72 #define SVM_FEATURE_LBRV (1 << 1)
73 #define SVM_FEATURE_SVML (1 << 2)
74 #define SVM_FEATURE_TSC_RATE (1 << 4)
75 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
76 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
77 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
78 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80 #define SVM_AVIC_DOORBELL 0xc001011b
82 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
83 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
84 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
86 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
88 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
89 #define TSC_RATIO_MIN 0x0000000000000001ULL
90 #define TSC_RATIO_MAX 0x000000ffffffffffULL
92 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
95 * 0xff is broadcast, so the max index allowed for physical APIC ID
96 * table is 0xfe. APIC IDs above 0xff are reserved.
98 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
100 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
101 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
102 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
104 /* AVIC GATAG is encoded using VM and VCPU IDs */
105 #define AVIC_VCPU_ID_BITS 8
106 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
108 #define AVIC_VM_ID_BITS 24
109 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
110 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
112 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
113 (y & AVIC_VCPU_ID_MASK))
114 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
115 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
117 static bool erratum_383_found __read_mostly;
119 static const u32 host_save_user_msrs[] = {
121 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
124 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
128 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
130 struct kvm_sev_info {
131 bool active; /* SEV enabled guest */
132 unsigned int asid; /* ASID used for this guest */
133 unsigned int handle; /* SEV firmware handle */
134 int fd; /* SEV device fd */
135 unsigned long pages_locked; /* Number of pages locked */
136 struct list_head regions_list; /* List of registered regions */
142 /* Struct members for AVIC */
144 struct page *avic_logical_id_table_page;
145 struct page *avic_physical_id_table_page;
146 struct hlist_node hnode;
148 struct kvm_sev_info sev_info;
153 struct nested_state {
159 /* These are the merged vectors */
162 /* gpa pointers to the real vectors */
166 /* A VMEXIT is required but not yet emulated */
169 /* cache for intercepts of the guest */
172 u32 intercept_exceptions;
175 /* Nested Paging related state */
179 #define MSRPM_OFFSETS 16
180 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
183 * Set osvw_len to higher value when updated Revision Guides
184 * are published and we know what the new status bits are
186 static uint64_t osvw_len = 4, osvw_status;
189 struct kvm_vcpu vcpu;
191 unsigned long vmcb_pa;
192 struct svm_cpu_data *svm_data;
193 uint64_t asid_generation;
194 uint64_t sysenter_esp;
195 uint64_t sysenter_eip;
202 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
212 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
213 * translated into the appropriate L2_CFG bits on the host to
214 * perform speculative control.
222 struct nested_state nested;
225 u64 nmi_singlestep_guest_rflags;
227 unsigned int3_injected;
228 unsigned long int3_rip;
230 /* cached guest cpuid flags for faster access */
231 bool nrips_enabled : 1;
235 struct page *avic_backing_page;
236 u64 *avic_physical_id_cache;
237 bool avic_is_running;
240 * Per-vcpu list of struct amd_svm_iommu_ir:
241 * This is used mainly to store interrupt remapping information used
242 * when update the vcpu affinity. This avoids the need to scan for
243 * IRTE and try to match ga_tag in the IOMMU driver.
245 struct list_head ir_list;
246 spinlock_t ir_list_lock;
248 /* which host CPU was used for running this vcpu */
249 unsigned int last_cpu;
253 * This is a wrapper of struct amd_iommu_ir_data.
255 struct amd_svm_iommu_ir {
256 struct list_head node; /* Used by SVM for per-vcpu ir_list */
257 void *data; /* Storing pointer to struct amd_ir_data */
260 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
261 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
262 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
264 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
265 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
266 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
267 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
269 static DEFINE_PER_CPU(u64, current_tsc_ratio);
270 #define TSC_RATIO_DEFAULT 0x0100000000ULL
272 #define MSR_INVALID 0xffffffffU
274 static const struct svm_direct_access_msrs {
275 u32 index; /* Index of the MSR */
276 bool always; /* True if intercept is always on */
277 } direct_access_msrs[] = {
278 { .index = MSR_STAR, .always = true },
279 { .index = MSR_IA32_SYSENTER_CS, .always = true },
281 { .index = MSR_GS_BASE, .always = true },
282 { .index = MSR_FS_BASE, .always = true },
283 { .index = MSR_KERNEL_GS_BASE, .always = true },
284 { .index = MSR_LSTAR, .always = true },
285 { .index = MSR_CSTAR, .always = true },
286 { .index = MSR_SYSCALL_MASK, .always = true },
288 { .index = MSR_IA32_SPEC_CTRL, .always = false },
289 { .index = MSR_IA32_PRED_CMD, .always = false },
290 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
291 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
292 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
293 { .index = MSR_IA32_LASTINTTOIP, .always = false },
294 { .index = MSR_INVALID, .always = false },
297 /* enable NPT for AMD64 and X86 with PAE */
298 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
299 static bool npt_enabled = true;
301 static bool npt_enabled;
305 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
306 * pause_filter_count: On processors that support Pause filtering(indicated
307 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
308 * count value. On VMRUN this value is loaded into an internal counter.
309 * Each time a pause instruction is executed, this counter is decremented
310 * until it reaches zero at which time a #VMEXIT is generated if pause
311 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
312 * Intercept Filtering for more details.
313 * This also indicate if ple logic enabled.
315 * pause_filter_thresh: In addition, some processor families support advanced
316 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
317 * the amount of time a guest is allowed to execute in a pause loop.
318 * In this mode, a 16-bit pause filter threshold field is added in the
319 * VMCB. The threshold value is a cycle count that is used to reset the
320 * pause counter. As with simple pause filtering, VMRUN loads the pause
321 * count value from VMCB into an internal counter. Then, on each pause
322 * instruction the hardware checks the elapsed number of cycles since
323 * the most recent pause instruction against the pause filter threshold.
324 * If the elapsed cycle count is greater than the pause filter threshold,
325 * then the internal pause count is reloaded from the VMCB and execution
326 * continues. If the elapsed cycle count is less than the pause filter
327 * threshold, then the internal pause count is decremented. If the count
328 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
329 * triggered. If advanced pause filtering is supported and pause filter
330 * threshold field is set to zero, the filter will operate in the simpler,
334 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
335 module_param(pause_filter_thresh, ushort, 0444);
337 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
338 module_param(pause_filter_count, ushort, 0444);
340 /* Default doubles per-vcpu window every exit. */
341 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
342 module_param(pause_filter_count_grow, ushort, 0444);
344 /* Default resets per-vcpu window every exit to pause_filter_count. */
345 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
346 module_param(pause_filter_count_shrink, ushort, 0444);
348 /* Default is to compute the maximum so we can never overflow. */
349 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
350 module_param(pause_filter_count_max, ushort, 0444);
352 /* allow nested paging (virtualized MMU) for all guests */
353 static int npt = true;
354 module_param(npt, int, S_IRUGO);
356 /* allow nested virtualization in KVM/SVM */
357 static int nested = true;
358 module_param(nested, int, S_IRUGO);
360 /* enable / disable AVIC */
362 #ifdef CONFIG_X86_LOCAL_APIC
363 module_param(avic, int, S_IRUGO);
366 /* enable/disable Next RIP Save */
367 static int nrips = true;
368 module_param(nrips, int, 0444);
370 /* enable/disable Virtual VMLOAD VMSAVE */
371 static int vls = true;
372 module_param(vls, int, 0444);
374 /* enable/disable Virtual GIF */
375 static int vgif = true;
376 module_param(vgif, int, 0444);
378 /* enable/disable SEV support */
379 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
380 module_param(sev, int, 0444);
382 static bool __read_mostly dump_invalid_vmcb = 0;
383 module_param(dump_invalid_vmcb, bool, 0644);
385 static u8 rsm_ins_bytes[] = "\x0f\xaa";
387 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
388 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
389 static void svm_complete_interrupts(struct vcpu_svm *svm);
391 static int nested_svm_exit_handled(struct vcpu_svm *svm);
392 static int nested_svm_intercept(struct vcpu_svm *svm);
393 static int nested_svm_vmexit(struct vcpu_svm *svm);
394 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
395 bool has_error_code, u32 error_code);
398 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
399 pause filter count */
400 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
401 VMCB_ASID, /* ASID */
402 VMCB_INTR, /* int_ctl, int_vector */
403 VMCB_NPT, /* npt_en, nCR3, gPAT */
404 VMCB_CR, /* CR0, CR3, CR4, EFER */
405 VMCB_DR, /* DR6, DR7 */
406 VMCB_DT, /* GDT, IDT */
407 VMCB_SEG, /* CS, DS, SS, ES, CPL */
408 VMCB_CR2, /* CR2 only */
409 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
410 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
411 * AVIC PHYSICAL_TABLE pointer,
412 * AVIC LOGICAL_TABLE pointer
417 /* TPR and CR2 are always written before VMRUN */
418 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
420 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
422 static int sev_flush_asids(void);
423 static DECLARE_RWSEM(sev_deactivate_lock);
424 static DEFINE_MUTEX(sev_bitmap_lock);
425 static unsigned int max_sev_asid;
426 static unsigned int min_sev_asid;
427 static unsigned long *sev_asid_bitmap;
428 static unsigned long *sev_reclaim_asid_bitmap;
429 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
432 struct list_head list;
433 unsigned long npages;
440 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
442 return container_of(kvm, struct kvm_svm, kvm);
445 static inline bool svm_sev_enabled(void)
447 return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
450 static inline bool sev_guest(struct kvm *kvm)
452 #ifdef CONFIG_KVM_AMD_SEV
453 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
461 static inline int sev_get_asid(struct kvm *kvm)
463 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
468 static inline void mark_all_dirty(struct vmcb *vmcb)
470 vmcb->control.clean = 0;
473 static inline void mark_all_clean(struct vmcb *vmcb)
475 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
476 & ~VMCB_ALWAYS_DIRTY_MASK;
479 static inline void mark_dirty(struct vmcb *vmcb, int bit)
481 vmcb->control.clean &= ~(1 << bit);
484 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
486 return container_of(vcpu, struct vcpu_svm, vcpu);
489 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
491 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
492 mark_dirty(svm->vmcb, VMCB_AVIC);
495 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
497 struct vcpu_svm *svm = to_svm(vcpu);
498 u64 *entry = svm->avic_physical_id_cache;
503 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
506 static void recalc_intercepts(struct vcpu_svm *svm)
508 struct vmcb_control_area *c, *h;
509 struct nested_state *g;
511 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
513 if (!is_guest_mode(&svm->vcpu))
516 c = &svm->vmcb->control;
517 h = &svm->nested.hsave->control;
520 c->intercept_cr = h->intercept_cr | g->intercept_cr;
521 c->intercept_dr = h->intercept_dr | g->intercept_dr;
522 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
523 c->intercept = h->intercept | g->intercept;
526 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
528 if (is_guest_mode(&svm->vcpu))
529 return svm->nested.hsave;
534 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
536 struct vmcb *vmcb = get_host_vmcb(svm);
538 vmcb->control.intercept_cr |= (1U << bit);
540 recalc_intercepts(svm);
543 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
545 struct vmcb *vmcb = get_host_vmcb(svm);
547 vmcb->control.intercept_cr &= ~(1U << bit);
549 recalc_intercepts(svm);
552 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
554 struct vmcb *vmcb = get_host_vmcb(svm);
556 return vmcb->control.intercept_cr & (1U << bit);
559 static inline void set_dr_intercepts(struct vcpu_svm *svm)
561 struct vmcb *vmcb = get_host_vmcb(svm);
563 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
564 | (1 << INTERCEPT_DR1_READ)
565 | (1 << INTERCEPT_DR2_READ)
566 | (1 << INTERCEPT_DR3_READ)
567 | (1 << INTERCEPT_DR4_READ)
568 | (1 << INTERCEPT_DR5_READ)
569 | (1 << INTERCEPT_DR6_READ)
570 | (1 << INTERCEPT_DR7_READ)
571 | (1 << INTERCEPT_DR0_WRITE)
572 | (1 << INTERCEPT_DR1_WRITE)
573 | (1 << INTERCEPT_DR2_WRITE)
574 | (1 << INTERCEPT_DR3_WRITE)
575 | (1 << INTERCEPT_DR4_WRITE)
576 | (1 << INTERCEPT_DR5_WRITE)
577 | (1 << INTERCEPT_DR6_WRITE)
578 | (1 << INTERCEPT_DR7_WRITE);
580 recalc_intercepts(svm);
583 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
585 struct vmcb *vmcb = get_host_vmcb(svm);
587 vmcb->control.intercept_dr = 0;
589 recalc_intercepts(svm);
592 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
594 struct vmcb *vmcb = get_host_vmcb(svm);
596 vmcb->control.intercept_exceptions |= (1U << bit);
598 recalc_intercepts(svm);
601 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
603 struct vmcb *vmcb = get_host_vmcb(svm);
605 vmcb->control.intercept_exceptions &= ~(1U << bit);
607 recalc_intercepts(svm);
610 static inline void set_intercept(struct vcpu_svm *svm, int bit)
612 struct vmcb *vmcb = get_host_vmcb(svm);
614 vmcb->control.intercept |= (1ULL << bit);
616 recalc_intercepts(svm);
619 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
621 struct vmcb *vmcb = get_host_vmcb(svm);
623 vmcb->control.intercept &= ~(1ULL << bit);
625 recalc_intercepts(svm);
628 static inline bool vgif_enabled(struct vcpu_svm *svm)
630 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
633 static inline void enable_gif(struct vcpu_svm *svm)
635 if (vgif_enabled(svm))
636 svm->vmcb->control.int_ctl |= V_GIF_MASK;
638 svm->vcpu.arch.hflags |= HF_GIF_MASK;
641 static inline void disable_gif(struct vcpu_svm *svm)
643 if (vgif_enabled(svm))
644 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
646 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
649 static inline bool gif_set(struct vcpu_svm *svm)
651 if (vgif_enabled(svm))
652 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
654 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
657 static unsigned long iopm_base;
659 struct kvm_ldttss_desc {
662 unsigned base1:8, type:5, dpl:2, p:1;
663 unsigned limit1:4, zero0:3, g:1, base2:8;
666 } __attribute__((packed));
668 struct svm_cpu_data {
675 struct kvm_ldttss_desc *tss_desc;
677 struct page *save_area;
678 struct vmcb *current_vmcb;
680 /* index = sev_asid, value = vmcb pointer */
681 struct vmcb **sev_vmcbs;
684 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
686 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
688 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
689 #define MSRS_RANGE_SIZE 2048
690 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
692 static u32 svm_msrpm_offset(u32 msr)
697 for (i = 0; i < NUM_MSR_MAPS; i++) {
698 if (msr < msrpm_ranges[i] ||
699 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
702 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
703 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
705 /* Now we have the u8 offset - but need the u32 offset */
709 /* MSR not in any range */
713 #define MAX_INST_SIZE 15
715 static inline void clgi(void)
717 asm volatile (__ex("clgi"));
720 static inline void stgi(void)
722 asm volatile (__ex("stgi"));
725 static inline void invlpga(unsigned long addr, u32 asid)
727 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
730 static int get_npt_level(struct kvm_vcpu *vcpu)
733 return PT64_ROOT_4LEVEL;
735 return PT32E_ROOT_LEVEL;
739 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
741 vcpu->arch.efer = efer;
744 /* Shadow paging assumes NX to be available. */
747 if (!(efer & EFER_LMA))
751 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
752 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
755 static int is_external_interrupt(u32 info)
757 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
758 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
761 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
763 struct vcpu_svm *svm = to_svm(vcpu);
766 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
767 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
771 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
773 struct vcpu_svm *svm = to_svm(vcpu);
776 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
778 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
782 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
784 struct vcpu_svm *svm = to_svm(vcpu);
786 if (nrips && svm->vmcb->control.next_rip != 0) {
787 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
788 svm->next_rip = svm->vmcb->control.next_rip;
791 if (!svm->next_rip) {
792 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
795 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
796 pr_err("%s: ip 0x%lx next 0x%llx\n",
797 __func__, kvm_rip_read(vcpu), svm->next_rip);
798 kvm_rip_write(vcpu, svm->next_rip);
800 svm_set_interrupt_shadow(vcpu, 0);
805 static void svm_queue_exception(struct kvm_vcpu *vcpu)
807 struct vcpu_svm *svm = to_svm(vcpu);
808 unsigned nr = vcpu->arch.exception.nr;
809 bool has_error_code = vcpu->arch.exception.has_error_code;
810 bool reinject = vcpu->arch.exception.injected;
811 u32 error_code = vcpu->arch.exception.error_code;
814 * If we are within a nested VM we'd better #VMEXIT and let the guest
815 * handle the exception
818 nested_svm_check_exception(svm, nr, has_error_code, error_code))
821 kvm_deliver_exception_payload(&svm->vcpu);
823 if (nr == BP_VECTOR && !nrips) {
824 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
827 * For guest debugging where we have to reinject #BP if some
828 * INT3 is guest-owned:
829 * Emulate nRIP by moving RIP forward. Will fail if injection
830 * raises a fault that is not intercepted. Still better than
831 * failing in all cases.
833 (void)skip_emulated_instruction(&svm->vcpu);
834 rip = kvm_rip_read(&svm->vcpu);
835 svm->int3_rip = rip + svm->vmcb->save.cs.base;
836 svm->int3_injected = rip - old_rip;
839 svm->vmcb->control.event_inj = nr
841 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
842 | SVM_EVTINJ_TYPE_EXEPT;
843 svm->vmcb->control.event_inj_err = error_code;
846 static void svm_init_erratum_383(void)
852 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
855 /* Use _safe variants to not break nested virtualization */
856 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
862 low = lower_32_bits(val);
863 high = upper_32_bits(val);
865 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
867 erratum_383_found = true;
870 static void svm_init_osvw(struct kvm_vcpu *vcpu)
873 * Guests should see errata 400 and 415 as fixed (assuming that
874 * HLT and IO instructions are intercepted).
876 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
877 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
880 * By increasing VCPU's osvw.length to 3 we are telling the guest that
881 * all osvw.status bits inside that length, including bit 0 (which is
882 * reserved for erratum 298), are valid. However, if host processor's
883 * osvw_len is 0 then osvw_status[0] carries no information. We need to
884 * be conservative here and therefore we tell the guest that erratum 298
885 * is present (because we really don't know).
887 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
888 vcpu->arch.osvw.status |= 1;
891 static int has_svm(void)
895 if (!cpu_has_svm(&msg)) {
896 printk(KERN_INFO "has_svm: %s\n", msg);
903 static void svm_hardware_disable(void)
905 /* Make sure we clean up behind us */
906 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
907 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
911 amd_pmu_disable_virt();
914 static int svm_hardware_enable(void)
917 struct svm_cpu_data *sd;
919 struct desc_struct *gdt;
920 int me = raw_smp_processor_id();
922 rdmsrl(MSR_EFER, efer);
923 if (efer & EFER_SVME)
927 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
930 sd = per_cpu(svm_data, me);
932 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
936 sd->asid_generation = 1;
937 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
938 sd->next_asid = sd->max_asid + 1;
939 sd->min_asid = max_sev_asid + 1;
941 gdt = get_current_gdt_rw();
942 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
944 wrmsrl(MSR_EFER, efer | EFER_SVME);
946 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
948 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
949 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
950 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
957 * Note that it is possible to have a system with mixed processor
958 * revisions and therefore different OSVW bits. If bits are not the same
959 * on different processors then choose the worst case (i.e. if erratum
960 * is present on one processor and not on another then assume that the
961 * erratum is present everywhere).
963 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
964 uint64_t len, status = 0;
967 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
969 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
973 osvw_status = osvw_len = 0;
977 osvw_status |= status;
978 osvw_status &= (1ULL << osvw_len) - 1;
981 osvw_status = osvw_len = 0;
983 svm_init_erratum_383();
985 amd_pmu_enable_virt();
990 static void svm_cpu_uninit(int cpu)
992 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
997 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
998 kfree(sd->sev_vmcbs);
999 __free_page(sd->save_area);
1003 static int svm_cpu_init(int cpu)
1005 struct svm_cpu_data *sd;
1008 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
1013 sd->save_area = alloc_page(GFP_KERNEL);
1017 if (svm_sev_enabled()) {
1019 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1026 per_cpu(svm_data, cpu) = sd;
1036 static bool valid_msr_intercept(u32 index)
1040 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1041 if (direct_access_msrs[i].index == index)
1047 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1054 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1055 to_svm(vcpu)->msrpm;
1057 offset = svm_msrpm_offset(msr);
1058 bit_write = 2 * (msr & 0x0f) + 1;
1059 tmp = msrpm[offset];
1061 BUG_ON(offset == MSR_INVALID);
1063 return !!test_bit(bit_write, &tmp);
1066 static void set_msr_interception(u32 *msrpm, unsigned msr,
1067 int read, int write)
1069 u8 bit_read, bit_write;
1074 * If this warning triggers extend the direct_access_msrs list at the
1075 * beginning of the file
1077 WARN_ON(!valid_msr_intercept(msr));
1079 offset = svm_msrpm_offset(msr);
1080 bit_read = 2 * (msr & 0x0f);
1081 bit_write = 2 * (msr & 0x0f) + 1;
1082 tmp = msrpm[offset];
1084 BUG_ON(offset == MSR_INVALID);
1086 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
1087 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1089 msrpm[offset] = tmp;
1092 static void svm_vcpu_init_msrpm(u32 *msrpm)
1096 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1098 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1099 if (!direct_access_msrs[i].always)
1102 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1106 static void add_msr_offset(u32 offset)
1110 for (i = 0; i < MSRPM_OFFSETS; ++i) {
1112 /* Offset already in list? */
1113 if (msrpm_offsets[i] == offset)
1116 /* Slot used by another offset? */
1117 if (msrpm_offsets[i] != MSR_INVALID)
1120 /* Add offset to list */
1121 msrpm_offsets[i] = offset;
1127 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1128 * increase MSRPM_OFFSETS in this case.
1133 static void init_msrpm_offsets(void)
1137 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1139 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1142 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1143 BUG_ON(offset == MSR_INVALID);
1145 add_msr_offset(offset);
1149 static void svm_enable_lbrv(struct vcpu_svm *svm)
1151 u32 *msrpm = svm->msrpm;
1153 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1154 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1155 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1156 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1157 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1160 static void svm_disable_lbrv(struct vcpu_svm *svm)
1162 u32 *msrpm = svm->msrpm;
1164 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1165 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1166 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1167 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1168 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1171 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1173 svm->nmi_singlestep = false;
1175 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1176 /* Clear our flags if they were not set by the guest */
1177 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1178 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1179 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1180 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1185 * This hash table is used to map VM_ID to a struct kvm_svm,
1186 * when handling AMD IOMMU GALOG notification to schedule in
1187 * a particular vCPU.
1189 #define SVM_VM_DATA_HASH_BITS 8
1190 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1191 static u32 next_vm_id = 0;
1192 static bool next_vm_id_wrapped = 0;
1193 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1196 * This function is called from IOMMU driver to notify
1197 * SVM to schedule in a particular vCPU of a particular VM.
1199 static int avic_ga_log_notifier(u32 ga_tag)
1201 unsigned long flags;
1202 struct kvm_svm *kvm_svm;
1203 struct kvm_vcpu *vcpu = NULL;
1204 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1205 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1207 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1209 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1210 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1211 if (kvm_svm->avic_vm_id != vm_id)
1213 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1216 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1219 * At this point, the IOMMU should have already set the pending
1220 * bit in the vAPIC backing page. So, we just need to schedule
1224 kvm_vcpu_wake_up(vcpu);
1229 static __init int sev_hardware_setup(void)
1231 struct sev_user_data_status *status;
1234 /* Maximum number of encrypted guests supported simultaneously */
1235 max_sev_asid = cpuid_ecx(0x8000001F);
1240 /* Minimum ASID value that should be used for SEV guest */
1241 min_sev_asid = cpuid_edx(0x8000001F);
1243 /* Initialize SEV ASID bitmaps */
1244 sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1245 if (!sev_asid_bitmap)
1248 sev_reclaim_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1249 if (!sev_reclaim_asid_bitmap)
1252 status = kmalloc(sizeof(*status), GFP_KERNEL);
1257 * Check SEV platform status.
1259 * PLATFORM_STATUS can be called in any state, if we failed to query
1260 * the PLATFORM status then either PSP firmware does not support SEV
1261 * feature or SEV firmware is dead.
1263 rc = sev_platform_status(status, NULL);
1267 pr_info("SEV supported\n");
1274 static void grow_ple_window(struct kvm_vcpu *vcpu)
1276 struct vcpu_svm *svm = to_svm(vcpu);
1277 struct vmcb_control_area *control = &svm->vmcb->control;
1278 int old = control->pause_filter_count;
1280 control->pause_filter_count = __grow_ple_window(old,
1282 pause_filter_count_grow,
1283 pause_filter_count_max);
1285 if (control->pause_filter_count != old) {
1286 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1287 trace_kvm_ple_window_update(vcpu->vcpu_id,
1288 control->pause_filter_count, old);
1292 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1294 struct vcpu_svm *svm = to_svm(vcpu);
1295 struct vmcb_control_area *control = &svm->vmcb->control;
1296 int old = control->pause_filter_count;
1298 control->pause_filter_count =
1299 __shrink_ple_window(old,
1301 pause_filter_count_shrink,
1302 pause_filter_count);
1303 if (control->pause_filter_count != old) {
1304 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1305 trace_kvm_ple_window_update(vcpu->vcpu_id,
1306 control->pause_filter_count, old);
1311 * The default MMIO mask is a single bit (excluding the present bit),
1312 * which could conflict with the memory encryption bit. Check for
1313 * memory encryption support and override the default MMIO mask if
1314 * memory encryption is enabled.
1316 static __init void svm_adjust_mmio_mask(void)
1318 unsigned int enc_bit, mask_bit;
1321 /* If there is no memory encryption support, use existing mask */
1322 if (cpuid_eax(0x80000000) < 0x8000001f)
1325 /* If memory encryption is not enabled, use existing mask */
1326 rdmsrl(MSR_K8_SYSCFG, msr);
1327 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
1330 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
1331 mask_bit = boot_cpu_data.x86_phys_bits;
1333 /* Increment the mask bit if it is the same as the encryption bit */
1334 if (enc_bit == mask_bit)
1338 * If the mask bit location is below 52, then some bits above the
1339 * physical addressing limit will always be reserved, so use the
1340 * rsvd_bits() function to generate the mask. This mask, along with
1341 * the present bit, will be used to generate a page fault with
1344 * If the mask bit location is 52 (or above), then clear the mask.
1346 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
1348 kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
1351 static __init int svm_hardware_setup(void)
1354 struct page *iopm_pages;
1358 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1363 iopm_va = page_address(iopm_pages);
1364 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1365 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1367 init_msrpm_offsets();
1369 if (boot_cpu_has(X86_FEATURE_NX))
1370 kvm_enable_efer_bits(EFER_NX);
1372 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1373 kvm_enable_efer_bits(EFER_FFXSR);
1375 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1376 kvm_has_tsc_control = true;
1377 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1378 kvm_tsc_scaling_ratio_frac_bits = 32;
1381 /* Check for pause filtering support */
1382 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1383 pause_filter_count = 0;
1384 pause_filter_thresh = 0;
1385 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1386 pause_filter_thresh = 0;
1390 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1391 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1395 if (boot_cpu_has(X86_FEATURE_SEV) &&
1396 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1397 r = sev_hardware_setup();
1405 svm_adjust_mmio_mask();
1407 for_each_possible_cpu(cpu) {
1408 r = svm_cpu_init(cpu);
1413 if (!boot_cpu_has(X86_FEATURE_NPT))
1414 npt_enabled = false;
1416 if (npt_enabled && !npt) {
1417 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1418 npt_enabled = false;
1422 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1428 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1434 !boot_cpu_has(X86_FEATURE_AVIC) ||
1435 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1438 pr_info("AVIC enabled\n");
1440 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1446 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1447 !IS_ENABLED(CONFIG_X86_64)) {
1450 pr_info("Virtual VMLOAD VMSAVE supported\n");
1455 if (!boot_cpu_has(X86_FEATURE_VGIF))
1458 pr_info("Virtual GIF supported\n");
1464 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1469 static __exit void svm_hardware_unsetup(void)
1473 if (svm_sev_enabled()) {
1474 bitmap_free(sev_asid_bitmap);
1475 bitmap_free(sev_reclaim_asid_bitmap);
1480 for_each_possible_cpu(cpu)
1481 svm_cpu_uninit(cpu);
1483 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1487 static void init_seg(struct vmcb_seg *seg)
1490 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1491 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1492 seg->limit = 0xffff;
1496 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1499 seg->attrib = SVM_SELECTOR_P_MASK | type;
1500 seg->limit = 0xffff;
1504 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1506 struct vcpu_svm *svm = to_svm(vcpu);
1508 if (is_guest_mode(vcpu))
1509 return svm->nested.hsave->control.tsc_offset;
1511 return vcpu->arch.tsc_offset;
1514 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1516 struct vcpu_svm *svm = to_svm(vcpu);
1517 u64 g_tsc_offset = 0;
1519 if (is_guest_mode(vcpu)) {
1520 /* Write L1's TSC offset. */
1521 g_tsc_offset = svm->vmcb->control.tsc_offset -
1522 svm->nested.hsave->control.tsc_offset;
1523 svm->nested.hsave->control.tsc_offset = offset;
1526 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1527 svm->vmcb->control.tsc_offset - g_tsc_offset,
1530 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1532 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1533 return svm->vmcb->control.tsc_offset;
1536 static void avic_init_vmcb(struct vcpu_svm *svm)
1538 struct vmcb *vmcb = svm->vmcb;
1539 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1540 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1541 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1542 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1544 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1545 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1546 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1547 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1548 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1551 static void init_vmcb(struct vcpu_svm *svm)
1553 struct vmcb_control_area *control = &svm->vmcb->control;
1554 struct vmcb_save_area *save = &svm->vmcb->save;
1556 svm->vcpu.arch.hflags = 0;
1558 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1559 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1560 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1561 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1562 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1563 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1564 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1565 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1567 set_dr_intercepts(svm);
1569 set_exception_intercept(svm, PF_VECTOR);
1570 set_exception_intercept(svm, UD_VECTOR);
1571 set_exception_intercept(svm, MC_VECTOR);
1572 set_exception_intercept(svm, AC_VECTOR);
1573 set_exception_intercept(svm, DB_VECTOR);
1575 * Guest access to VMware backdoor ports could legitimately
1576 * trigger #GP because of TSS I/O permission bitmap.
1577 * We intercept those #GP and allow access to them anyway
1580 if (enable_vmware_backdoor)
1581 set_exception_intercept(svm, GP_VECTOR);
1583 set_intercept(svm, INTERCEPT_INTR);
1584 set_intercept(svm, INTERCEPT_NMI);
1585 set_intercept(svm, INTERCEPT_SMI);
1586 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1587 set_intercept(svm, INTERCEPT_RDPMC);
1588 set_intercept(svm, INTERCEPT_CPUID);
1589 set_intercept(svm, INTERCEPT_INVD);
1590 set_intercept(svm, INTERCEPT_INVLPG);
1591 set_intercept(svm, INTERCEPT_INVLPGA);
1592 set_intercept(svm, INTERCEPT_IOIO_PROT);
1593 set_intercept(svm, INTERCEPT_MSR_PROT);
1594 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1595 set_intercept(svm, INTERCEPT_SHUTDOWN);
1596 set_intercept(svm, INTERCEPT_VMRUN);
1597 set_intercept(svm, INTERCEPT_VMMCALL);
1598 set_intercept(svm, INTERCEPT_VMLOAD);
1599 set_intercept(svm, INTERCEPT_VMSAVE);
1600 set_intercept(svm, INTERCEPT_STGI);
1601 set_intercept(svm, INTERCEPT_CLGI);
1602 set_intercept(svm, INTERCEPT_SKINIT);
1603 set_intercept(svm, INTERCEPT_WBINVD);
1604 set_intercept(svm, INTERCEPT_XSETBV);
1605 set_intercept(svm, INTERCEPT_RDPRU);
1606 set_intercept(svm, INTERCEPT_RSM);
1608 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1609 set_intercept(svm, INTERCEPT_MONITOR);
1610 set_intercept(svm, INTERCEPT_MWAIT);
1613 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1614 set_intercept(svm, INTERCEPT_HLT);
1616 control->iopm_base_pa = __sme_set(iopm_base);
1617 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1618 control->int_ctl = V_INTR_MASKING_MASK;
1620 init_seg(&save->es);
1621 init_seg(&save->ss);
1622 init_seg(&save->ds);
1623 init_seg(&save->fs);
1624 init_seg(&save->gs);
1626 save->cs.selector = 0xf000;
1627 save->cs.base = 0xffff0000;
1628 /* Executable/Readable Code Segment */
1629 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1630 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1631 save->cs.limit = 0xffff;
1633 save->gdtr.limit = 0xffff;
1634 save->idtr.limit = 0xffff;
1636 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1637 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1639 svm_set_efer(&svm->vcpu, 0);
1640 save->dr6 = 0xffff0ff0;
1641 kvm_set_rflags(&svm->vcpu, 2);
1642 save->rip = 0x0000fff0;
1643 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1646 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1647 * It also updates the guest-visible cr0 value.
1649 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1650 kvm_mmu_reset_context(&svm->vcpu);
1652 save->cr4 = X86_CR4_PAE;
1656 /* Setup VMCB for Nested Paging */
1657 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1658 clr_intercept(svm, INTERCEPT_INVLPG);
1659 clr_exception_intercept(svm, PF_VECTOR);
1660 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1661 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1662 save->g_pat = svm->vcpu.arch.pat;
1666 svm->asid_generation = 0;
1668 svm->nested.vmcb = 0;
1669 svm->vcpu.arch.hflags = 0;
1671 if (pause_filter_count) {
1672 control->pause_filter_count = pause_filter_count;
1673 if (pause_filter_thresh)
1674 control->pause_filter_thresh = pause_filter_thresh;
1675 set_intercept(svm, INTERCEPT_PAUSE);
1677 clr_intercept(svm, INTERCEPT_PAUSE);
1680 if (kvm_vcpu_apicv_active(&svm->vcpu))
1681 avic_init_vmcb(svm);
1684 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1685 * in VMCB and clear intercepts to avoid #VMEXIT.
1688 clr_intercept(svm, INTERCEPT_VMLOAD);
1689 clr_intercept(svm, INTERCEPT_VMSAVE);
1690 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1694 clr_intercept(svm, INTERCEPT_STGI);
1695 clr_intercept(svm, INTERCEPT_CLGI);
1696 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1699 if (sev_guest(svm->vcpu.kvm)) {
1700 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1701 clr_exception_intercept(svm, UD_VECTOR);
1704 mark_all_dirty(svm->vmcb);
1710 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1713 u64 *avic_physical_id_table;
1714 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1716 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1719 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1721 return &avic_physical_id_table[index];
1726 * AVIC hardware walks the nested page table to check permissions,
1727 * but does not use the SPA address specified in the leaf page
1728 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1729 * field of the VMCB. Therefore, we set up the
1730 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1732 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1734 struct kvm *kvm = vcpu->kvm;
1737 mutex_lock(&kvm->slots_lock);
1738 if (kvm->arch.apic_access_page_done)
1741 ret = __x86_set_memory_region(kvm,
1742 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1743 APIC_DEFAULT_PHYS_BASE,
1748 kvm->arch.apic_access_page_done = true;
1750 mutex_unlock(&kvm->slots_lock);
1754 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1757 u64 *entry, new_entry;
1758 int id = vcpu->vcpu_id;
1759 struct vcpu_svm *svm = to_svm(vcpu);
1761 ret = avic_init_access_page(vcpu);
1765 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1768 if (!svm->vcpu.arch.apic->regs)
1771 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1773 /* Setting AVIC backing page address in the phy APIC ID table */
1774 entry = avic_get_physical_id_entry(vcpu, id);
1778 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1779 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1780 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1781 WRITE_ONCE(*entry, new_entry);
1783 svm->avic_physical_id_cache = entry;
1788 static void sev_asid_free(int asid)
1790 struct svm_cpu_data *sd;
1793 mutex_lock(&sev_bitmap_lock);
1796 __set_bit(pos, sev_reclaim_asid_bitmap);
1798 for_each_possible_cpu(cpu) {
1799 sd = per_cpu(svm_data, cpu);
1800 sd->sev_vmcbs[pos] = NULL;
1803 mutex_unlock(&sev_bitmap_lock);
1806 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1808 struct sev_data_decommission *decommission;
1809 struct sev_data_deactivate *data;
1814 data = kzalloc(sizeof(*data), GFP_KERNEL);
1818 /* deactivate handle */
1819 data->handle = handle;
1821 /* Guard DEACTIVATE against WBINVD/DF_FLUSH used in ASID recycling */
1822 down_read(&sev_deactivate_lock);
1823 sev_guest_deactivate(data, NULL);
1824 up_read(&sev_deactivate_lock);
1828 decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1832 /* decommission handle */
1833 decommission->handle = handle;
1834 sev_guest_decommission(decommission, NULL);
1836 kfree(decommission);
1839 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1840 unsigned long ulen, unsigned long *n,
1843 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1844 unsigned long npages, npinned, size;
1845 unsigned long locked, lock_limit;
1846 struct page **pages;
1847 unsigned long first, last;
1849 if (ulen == 0 || uaddr + ulen < uaddr)
1852 /* Calculate number of pages. */
1853 first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1854 last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1855 npages = (last - first + 1);
1857 locked = sev->pages_locked + npages;
1858 lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1859 if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1860 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1864 /* Avoid using vmalloc for smaller buffers. */
1865 size = npages * sizeof(struct page *);
1866 if (size > PAGE_SIZE)
1867 pages = __vmalloc(size, GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1870 pages = kmalloc(size, GFP_KERNEL_ACCOUNT);
1875 /* Pin the user virtual address. */
1876 npinned = get_user_pages_fast(uaddr, npages, FOLL_WRITE, pages);
1877 if (npinned != npages) {
1878 pr_err("SEV: Failure locking %lu pages.\n", npages);
1883 sev->pages_locked = locked;
1889 release_pages(pages, npinned);
1895 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1896 unsigned long npages)
1898 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1900 release_pages(pages, npages);
1902 sev->pages_locked -= npages;
1905 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1907 uint8_t *page_virtual;
1910 if (npages == 0 || pages == NULL)
1913 for (i = 0; i < npages; i++) {
1914 page_virtual = kmap_atomic(pages[i]);
1915 clflush_cache_range(page_virtual, PAGE_SIZE);
1916 kunmap_atomic(page_virtual);
1920 static void __unregister_enc_region_locked(struct kvm *kvm,
1921 struct enc_region *region)
1924 * The guest may change the memory encryption attribute from C=0 -> C=1
1925 * or vice versa for this memory range. Lets make sure caches are
1926 * flushed to ensure that guest data gets written into memory with
1929 sev_clflush_pages(region->pages, region->npages);
1931 sev_unpin_memory(kvm, region->pages, region->npages);
1932 list_del(®ion->list);
1936 static struct kvm *svm_vm_alloc(void)
1938 struct kvm_svm *kvm_svm = __vmalloc(sizeof(struct kvm_svm),
1939 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1941 return &kvm_svm->kvm;
1944 static void svm_vm_free(struct kvm *kvm)
1946 vfree(to_kvm_svm(kvm));
1949 static void sev_vm_destroy(struct kvm *kvm)
1951 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1952 struct list_head *head = &sev->regions_list;
1953 struct list_head *pos, *q;
1955 if (!sev_guest(kvm))
1958 mutex_lock(&kvm->lock);
1961 * if userspace was terminated before unregistering the memory regions
1962 * then lets unpin all the registered memory.
1964 if (!list_empty(head)) {
1965 list_for_each_safe(pos, q, head) {
1966 __unregister_enc_region_locked(kvm,
1967 list_entry(pos, struct enc_region, list));
1971 mutex_unlock(&kvm->lock);
1973 sev_unbind_asid(kvm, sev->handle);
1974 sev_asid_free(sev->asid);
1977 static void avic_vm_destroy(struct kvm *kvm)
1979 unsigned long flags;
1980 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1985 if (kvm_svm->avic_logical_id_table_page)
1986 __free_page(kvm_svm->avic_logical_id_table_page);
1987 if (kvm_svm->avic_physical_id_table_page)
1988 __free_page(kvm_svm->avic_physical_id_table_page);
1990 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1991 hash_del(&kvm_svm->hnode);
1992 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1995 static void svm_vm_destroy(struct kvm *kvm)
1997 avic_vm_destroy(kvm);
1998 sev_vm_destroy(kvm);
2001 static int avic_vm_init(struct kvm *kvm)
2003 unsigned long flags;
2005 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
2007 struct page *p_page;
2008 struct page *l_page;
2014 /* Allocating physical APIC ID table (4KB) */
2015 p_page = alloc_page(GFP_KERNEL_ACCOUNT);
2019 kvm_svm->avic_physical_id_table_page = p_page;
2020 clear_page(page_address(p_page));
2022 /* Allocating logical APIC ID table (4KB) */
2023 l_page = alloc_page(GFP_KERNEL_ACCOUNT);
2027 kvm_svm->avic_logical_id_table_page = l_page;
2028 clear_page(page_address(l_page));
2030 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
2032 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
2033 if (vm_id == 0) { /* id is 1-based, zero is not okay */
2034 next_vm_id_wrapped = 1;
2037 /* Is it still in use? Only possible if wrapped at least once */
2038 if (next_vm_id_wrapped) {
2039 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
2040 if (k2->avic_vm_id == vm_id)
2044 kvm_svm->avic_vm_id = vm_id;
2045 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
2046 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
2051 avic_vm_destroy(kvm);
2055 static int svm_vm_init(struct kvm *kvm)
2058 int ret = avic_vm_init(kvm);
2063 kvm_apicv_init(kvm, avic && irqchip_split(kvm));
2068 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
2071 unsigned long flags;
2072 struct amd_svm_iommu_ir *ir;
2073 struct vcpu_svm *svm = to_svm(vcpu);
2075 if (!kvm_arch_has_assigned_device(vcpu->kvm))
2079 * Here, we go through the per-vcpu ir_list to update all existing
2080 * interrupt remapping table entry targeting this vcpu.
2082 spin_lock_irqsave(&svm->ir_list_lock, flags);
2084 if (list_empty(&svm->ir_list))
2087 list_for_each_entry(ir, &svm->ir_list, node) {
2088 ret = amd_iommu_update_ga(cpu, r, ir->data);
2093 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2097 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2100 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2101 int h_physical_id = kvm_cpu_get_apicid(cpu);
2102 struct vcpu_svm *svm = to_svm(vcpu);
2104 if (!kvm_vcpu_apicv_active(vcpu))
2108 * Since the host physical APIC id is 8 bits,
2109 * we can support host APIC ID upto 255.
2111 if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK))
2114 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2115 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2117 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2118 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2120 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2121 if (svm->avic_is_running)
2122 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2124 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2125 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2126 svm->avic_is_running);
2129 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2132 struct vcpu_svm *svm = to_svm(vcpu);
2134 if (!kvm_vcpu_apicv_active(vcpu))
2137 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2138 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2139 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2141 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2142 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2146 * This function is called during VCPU halt/unhalt.
2148 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2150 struct vcpu_svm *svm = to_svm(vcpu);
2152 svm->avic_is_running = is_run;
2154 avic_vcpu_load(vcpu, vcpu->cpu);
2156 avic_vcpu_put(vcpu);
2159 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2161 struct vcpu_svm *svm = to_svm(vcpu);
2165 vcpu->arch.microcode_version = 0x01000065;
2167 svm->virt_spec_ctrl = 0;
2170 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2171 MSR_IA32_APICBASE_ENABLE;
2172 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2173 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2177 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2178 kvm_rdx_write(vcpu, eax);
2180 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2181 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2184 static int avic_init_vcpu(struct vcpu_svm *svm)
2188 if (!kvm_vcpu_apicv_active(&svm->vcpu))
2191 ret = avic_init_backing_page(&svm->vcpu);
2195 INIT_LIST_HEAD(&svm->ir_list);
2196 spin_lock_init(&svm->ir_list_lock);
2197 svm->dfr_reg = APIC_DFR_FLAT;
2202 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
2204 struct vcpu_svm *svm;
2206 struct page *msrpm_pages;
2207 struct page *hsave_page;
2208 struct page *nested_msrpm_pages;
2211 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
2215 page = alloc_page(GFP_KERNEL_ACCOUNT);
2219 msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2223 nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2224 if (!nested_msrpm_pages)
2227 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
2231 err = avic_init_vcpu(svm);
2235 /* We initialize this flag to true to make sure that the is_running
2236 * bit would be set the first time the vcpu is loaded.
2238 svm->avic_is_running = true;
2240 svm->nested.hsave = page_address(hsave_page);
2242 svm->msrpm = page_address(msrpm_pages);
2243 svm_vcpu_init_msrpm(svm->msrpm);
2245 svm->nested.msrpm = page_address(nested_msrpm_pages);
2246 svm_vcpu_init_msrpm(svm->nested.msrpm);
2248 svm->vmcb = page_address(page);
2249 clear_page(svm->vmcb);
2250 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2251 svm->asid_generation = 0;
2254 svm_init_osvw(vcpu);
2259 __free_page(hsave_page);
2261 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2263 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2270 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2274 for_each_online_cpu(i)
2275 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2278 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2280 struct vcpu_svm *svm = to_svm(vcpu);
2283 * The vmcb page can be recycled, causing a false negative in
2284 * svm_vcpu_load(). So, ensure that no logical CPU has this
2285 * vmcb page recorded as its current vmcb.
2287 svm_clear_current_vmcb(svm->vmcb);
2289 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2290 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2291 __free_page(virt_to_page(svm->nested.hsave));
2292 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2295 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2297 struct vcpu_svm *svm = to_svm(vcpu);
2298 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2301 if (unlikely(cpu != vcpu->cpu)) {
2302 svm->asid_generation = 0;
2303 mark_all_dirty(svm->vmcb);
2306 #ifdef CONFIG_X86_64
2307 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2309 savesegment(fs, svm->host.fs);
2310 savesegment(gs, svm->host.gs);
2311 svm->host.ldt = kvm_read_ldt();
2313 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2314 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2316 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2317 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2318 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2319 __this_cpu_write(current_tsc_ratio, tsc_ratio);
2320 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2323 /* This assumes that the kernel never uses MSR_TSC_AUX */
2324 if (static_cpu_has(X86_FEATURE_RDTSCP))
2325 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2327 if (sd->current_vmcb != svm->vmcb) {
2328 sd->current_vmcb = svm->vmcb;
2329 indirect_branch_prediction_barrier();
2331 avic_vcpu_load(vcpu, cpu);
2334 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2336 struct vcpu_svm *svm = to_svm(vcpu);
2339 avic_vcpu_put(vcpu);
2341 ++vcpu->stat.host_state_reload;
2342 kvm_load_ldt(svm->host.ldt);
2343 #ifdef CONFIG_X86_64
2344 loadsegment(fs, svm->host.fs);
2345 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2346 load_gs_index(svm->host.gs);
2348 #ifdef CONFIG_X86_32_LAZY_GS
2349 loadsegment(gs, svm->host.gs);
2352 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2353 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2356 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2358 avic_set_running(vcpu, false);
2361 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2363 avic_set_running(vcpu, true);
2366 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2368 struct vcpu_svm *svm = to_svm(vcpu);
2369 unsigned long rflags = svm->vmcb->save.rflags;
2371 if (svm->nmi_singlestep) {
2372 /* Hide our flags if they were not set by the guest */
2373 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2374 rflags &= ~X86_EFLAGS_TF;
2375 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2376 rflags &= ~X86_EFLAGS_RF;
2381 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2383 if (to_svm(vcpu)->nmi_singlestep)
2384 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2387 * Any change of EFLAGS.VM is accompanied by a reload of SS
2388 * (caused by either a task switch or an inter-privilege IRET),
2389 * so we do not need to update the CPL here.
2391 to_svm(vcpu)->vmcb->save.rflags = rflags;
2394 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2397 case VCPU_EXREG_PDPTR:
2398 BUG_ON(!npt_enabled);
2399 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2406 static void svm_set_vintr(struct vcpu_svm *svm)
2408 set_intercept(svm, INTERCEPT_VINTR);
2411 static void svm_clear_vintr(struct vcpu_svm *svm)
2413 clr_intercept(svm, INTERCEPT_VINTR);
2416 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2418 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2421 case VCPU_SREG_CS: return &save->cs;
2422 case VCPU_SREG_DS: return &save->ds;
2423 case VCPU_SREG_ES: return &save->es;
2424 case VCPU_SREG_FS: return &save->fs;
2425 case VCPU_SREG_GS: return &save->gs;
2426 case VCPU_SREG_SS: return &save->ss;
2427 case VCPU_SREG_TR: return &save->tr;
2428 case VCPU_SREG_LDTR: return &save->ldtr;
2434 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2436 struct vmcb_seg *s = svm_seg(vcpu, seg);
2441 static void svm_get_segment(struct kvm_vcpu *vcpu,
2442 struct kvm_segment *var, int seg)
2444 struct vmcb_seg *s = svm_seg(vcpu, seg);
2446 var->base = s->base;
2447 var->limit = s->limit;
2448 var->selector = s->selector;
2449 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2450 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2451 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2452 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2453 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2454 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2455 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2458 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2459 * However, the SVM spec states that the G bit is not observed by the
2460 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2461 * So let's synthesize a legal G bit for all segments, this helps
2462 * running KVM nested. It also helps cross-vendor migration, because
2463 * Intel's vmentry has a check on the 'G' bit.
2465 var->g = s->limit > 0xfffff;
2468 * AMD's VMCB does not have an explicit unusable field, so emulate it
2469 * for cross vendor migration purposes by "not present"
2471 var->unusable = !var->present;
2476 * Work around a bug where the busy flag in the tr selector
2486 * The accessed bit must always be set in the segment
2487 * descriptor cache, although it can be cleared in the
2488 * descriptor, the cached bit always remains at 1. Since
2489 * Intel has a check on this, set it here to support
2490 * cross-vendor migration.
2497 * On AMD CPUs sometimes the DB bit in the segment
2498 * descriptor is left as 1, although the whole segment has
2499 * been made unusable. Clear it here to pass an Intel VMX
2500 * entry check when cross vendor migrating.
2504 /* This is symmetric with svm_set_segment() */
2505 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2510 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2512 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2517 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2519 struct vcpu_svm *svm = to_svm(vcpu);
2521 dt->size = svm->vmcb->save.idtr.limit;
2522 dt->address = svm->vmcb->save.idtr.base;
2525 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2527 struct vcpu_svm *svm = to_svm(vcpu);
2529 svm->vmcb->save.idtr.limit = dt->size;
2530 svm->vmcb->save.idtr.base = dt->address ;
2531 mark_dirty(svm->vmcb, VMCB_DT);
2534 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2536 struct vcpu_svm *svm = to_svm(vcpu);
2538 dt->size = svm->vmcb->save.gdtr.limit;
2539 dt->address = svm->vmcb->save.gdtr.base;
2542 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2544 struct vcpu_svm *svm = to_svm(vcpu);
2546 svm->vmcb->save.gdtr.limit = dt->size;
2547 svm->vmcb->save.gdtr.base = dt->address ;
2548 mark_dirty(svm->vmcb, VMCB_DT);
2551 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2555 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2559 static void update_cr0_intercept(struct vcpu_svm *svm)
2561 ulong gcr0 = svm->vcpu.arch.cr0;
2562 u64 *hcr0 = &svm->vmcb->save.cr0;
2564 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2565 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2567 mark_dirty(svm->vmcb, VMCB_CR);
2569 if (gcr0 == *hcr0) {
2570 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2571 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2573 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2574 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2578 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2580 struct vcpu_svm *svm = to_svm(vcpu);
2582 #ifdef CONFIG_X86_64
2583 if (vcpu->arch.efer & EFER_LME) {
2584 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2585 vcpu->arch.efer |= EFER_LMA;
2586 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2589 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2590 vcpu->arch.efer &= ~EFER_LMA;
2591 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2595 vcpu->arch.cr0 = cr0;
2598 cr0 |= X86_CR0_PG | X86_CR0_WP;
2601 * re-enable caching here because the QEMU bios
2602 * does not do it - this results in some delay at
2605 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2606 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2607 svm->vmcb->save.cr0 = cr0;
2608 mark_dirty(svm->vmcb, VMCB_CR);
2609 update_cr0_intercept(svm);
2612 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2614 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2615 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2617 if (cr4 & X86_CR4_VMXE)
2620 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2621 svm_flush_tlb(vcpu, true);
2623 vcpu->arch.cr4 = cr4;
2626 cr4 |= host_cr4_mce;
2627 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2628 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2632 static void svm_set_segment(struct kvm_vcpu *vcpu,
2633 struct kvm_segment *var, int seg)
2635 struct vcpu_svm *svm = to_svm(vcpu);
2636 struct vmcb_seg *s = svm_seg(vcpu, seg);
2638 s->base = var->base;
2639 s->limit = var->limit;
2640 s->selector = var->selector;
2641 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2642 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2643 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2644 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2645 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2646 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2647 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2648 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2651 * This is always accurate, except if SYSRET returned to a segment
2652 * with SS.DPL != 3. Intel does not have this quirk, and always
2653 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2654 * would entail passing the CPL to userspace and back.
2656 if (seg == VCPU_SREG_SS)
2657 /* This is symmetric with svm_get_segment() */
2658 svm->vmcb->save.cpl = (var->dpl & 3);
2660 mark_dirty(svm->vmcb, VMCB_SEG);
2663 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2665 struct vcpu_svm *svm = to_svm(vcpu);
2667 clr_exception_intercept(svm, BP_VECTOR);
2669 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2670 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2671 set_exception_intercept(svm, BP_VECTOR);
2673 vcpu->guest_debug = 0;
2676 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2678 if (sd->next_asid > sd->max_asid) {
2679 ++sd->asid_generation;
2680 sd->next_asid = sd->min_asid;
2681 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2684 svm->asid_generation = sd->asid_generation;
2685 svm->vmcb->control.asid = sd->next_asid++;
2687 mark_dirty(svm->vmcb, VMCB_ASID);
2690 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2692 return to_svm(vcpu)->vmcb->save.dr6;
2695 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2697 struct vcpu_svm *svm = to_svm(vcpu);
2699 svm->vmcb->save.dr6 = value;
2700 mark_dirty(svm->vmcb, VMCB_DR);
2703 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2705 struct vcpu_svm *svm = to_svm(vcpu);
2707 get_debugreg(vcpu->arch.db[0], 0);
2708 get_debugreg(vcpu->arch.db[1], 1);
2709 get_debugreg(vcpu->arch.db[2], 2);
2710 get_debugreg(vcpu->arch.db[3], 3);
2711 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2712 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2714 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2715 set_dr_intercepts(svm);
2718 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2720 struct vcpu_svm *svm = to_svm(vcpu);
2722 svm->vmcb->save.dr7 = value;
2723 mark_dirty(svm->vmcb, VMCB_DR);
2726 static int pf_interception(struct vcpu_svm *svm)
2728 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2729 u64 error_code = svm->vmcb->control.exit_info_1;
2731 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2732 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2733 svm->vmcb->control.insn_bytes : NULL,
2734 svm->vmcb->control.insn_len);
2737 static int npf_interception(struct vcpu_svm *svm)
2739 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2740 u64 error_code = svm->vmcb->control.exit_info_1;
2742 trace_kvm_page_fault(fault_address, error_code);
2743 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2744 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2745 svm->vmcb->control.insn_bytes : NULL,
2746 svm->vmcb->control.insn_len);
2749 static int db_interception(struct vcpu_svm *svm)
2751 struct kvm_run *kvm_run = svm->vcpu.run;
2752 struct kvm_vcpu *vcpu = &svm->vcpu;
2754 if (!(svm->vcpu.guest_debug &
2755 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2756 !svm->nmi_singlestep) {
2757 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2761 if (svm->nmi_singlestep) {
2762 disable_nmi_singlestep(svm);
2763 /* Make sure we check for pending NMIs upon entry */
2764 kvm_make_request(KVM_REQ_EVENT, vcpu);
2767 if (svm->vcpu.guest_debug &
2768 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2769 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2770 kvm_run->debug.arch.pc =
2771 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2772 kvm_run->debug.arch.exception = DB_VECTOR;
2779 static int bp_interception(struct vcpu_svm *svm)
2781 struct kvm_run *kvm_run = svm->vcpu.run;
2783 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2784 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2785 kvm_run->debug.arch.exception = BP_VECTOR;
2789 static int ud_interception(struct vcpu_svm *svm)
2791 return handle_ud(&svm->vcpu);
2794 static int ac_interception(struct vcpu_svm *svm)
2796 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2800 static int gp_interception(struct vcpu_svm *svm)
2802 struct kvm_vcpu *vcpu = &svm->vcpu;
2803 u32 error_code = svm->vmcb->control.exit_info_1;
2805 WARN_ON_ONCE(!enable_vmware_backdoor);
2808 * VMware backdoor emulation on #GP interception only handles IN{S},
2809 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
2812 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2815 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
2818 static bool is_erratum_383(void)
2823 if (!erratum_383_found)
2826 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2830 /* Bit 62 may or may not be set for this mce */
2831 value &= ~(1ULL << 62);
2833 if (value != 0xb600000000010015ULL)
2836 /* Clear MCi_STATUS registers */
2837 for (i = 0; i < 6; ++i)
2838 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2840 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2844 value &= ~(1ULL << 2);
2845 low = lower_32_bits(value);
2846 high = upper_32_bits(value);
2848 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2851 /* Flush tlb to evict multi-match entries */
2857 static void svm_handle_mce(struct vcpu_svm *svm)
2859 if (is_erratum_383()) {
2861 * Erratum 383 triggered. Guest state is corrupt so kill the
2864 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2866 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2872 * On an #MC intercept the MCE handler is not called automatically in
2873 * the host. So do it by hand here.
2877 /* not sure if we ever come back to this point */
2882 static int mc_interception(struct vcpu_svm *svm)
2887 static int shutdown_interception(struct vcpu_svm *svm)
2889 struct kvm_run *kvm_run = svm->vcpu.run;
2892 * VMCB is undefined after a SHUTDOWN intercept
2893 * so reinitialize it.
2895 clear_page(svm->vmcb);
2898 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2902 static int io_interception(struct vcpu_svm *svm)
2904 struct kvm_vcpu *vcpu = &svm->vcpu;
2905 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2906 int size, in, string;
2909 ++svm->vcpu.stat.io_exits;
2910 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2911 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2913 return kvm_emulate_instruction(vcpu, 0);
2915 port = io_info >> 16;
2916 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2917 svm->next_rip = svm->vmcb->control.exit_info_2;
2919 return kvm_fast_pio(&svm->vcpu, size, port, in);
2922 static int nmi_interception(struct vcpu_svm *svm)
2927 static int intr_interception(struct vcpu_svm *svm)
2929 ++svm->vcpu.stat.irq_exits;
2933 static int nop_on_interception(struct vcpu_svm *svm)
2938 static int halt_interception(struct vcpu_svm *svm)
2940 return kvm_emulate_halt(&svm->vcpu);
2943 static int vmmcall_interception(struct vcpu_svm *svm)
2945 return kvm_emulate_hypercall(&svm->vcpu);
2948 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2950 struct vcpu_svm *svm = to_svm(vcpu);
2952 return svm->nested.nested_cr3;
2955 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2957 struct vcpu_svm *svm = to_svm(vcpu);
2958 u64 cr3 = svm->nested.nested_cr3;
2962 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2963 offset_in_page(cr3) + index * 8, 8);
2969 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2972 struct vcpu_svm *svm = to_svm(vcpu);
2974 svm->vmcb->control.nested_cr3 = __sme_set(root);
2975 mark_dirty(svm->vmcb, VMCB_NPT);
2978 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2979 struct x86_exception *fault)
2981 struct vcpu_svm *svm = to_svm(vcpu);
2983 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2985 * TODO: track the cause of the nested page fault, and
2986 * correctly fill in the high bits of exit_info_1.
2988 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2989 svm->vmcb->control.exit_code_hi = 0;
2990 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2991 svm->vmcb->control.exit_info_2 = fault->address;
2994 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2995 svm->vmcb->control.exit_info_1 |= fault->error_code;
2998 * The present bit is always zero for page structure faults on real
3001 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
3002 svm->vmcb->control.exit_info_1 &= ~1;
3004 nested_svm_vmexit(svm);
3007 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
3009 WARN_ON(mmu_is_nested(vcpu));
3011 vcpu->arch.mmu = &vcpu->arch.guest_mmu;
3012 kvm_init_shadow_mmu(vcpu);
3013 vcpu->arch.mmu->set_cr3 = nested_svm_set_tdp_cr3;
3014 vcpu->arch.mmu->get_cr3 = nested_svm_get_tdp_cr3;
3015 vcpu->arch.mmu->get_pdptr = nested_svm_get_tdp_pdptr;
3016 vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
3017 vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
3018 reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
3019 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
3022 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
3024 vcpu->arch.mmu = &vcpu->arch.root_mmu;
3025 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
3028 static int nested_svm_check_permissions(struct vcpu_svm *svm)
3030 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
3031 !is_paging(&svm->vcpu)) {
3032 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3036 if (svm->vmcb->save.cpl) {
3037 kvm_inject_gp(&svm->vcpu, 0);
3044 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
3045 bool has_error_code, u32 error_code)
3049 if (!is_guest_mode(&svm->vcpu))
3052 vmexit = nested_svm_intercept(svm);
3053 if (vmexit != NESTED_EXIT_DONE)
3056 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
3057 svm->vmcb->control.exit_code_hi = 0;
3058 svm->vmcb->control.exit_info_1 = error_code;
3061 * EXITINFO2 is undefined for all exception intercepts other
3064 if (svm->vcpu.arch.exception.nested_apf)
3065 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3066 else if (svm->vcpu.arch.exception.has_payload)
3067 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
3069 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3071 svm->nested.exit_required = true;
3075 /* This function returns true if it is save to enable the irq window */
3076 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3078 if (!is_guest_mode(&svm->vcpu))
3081 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3084 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3088 * if vmexit was already requested (by intercepted exception
3089 * for instance) do not overwrite it with "external interrupt"
3092 if (svm->nested.exit_required)
3095 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
3096 svm->vmcb->control.exit_info_1 = 0;
3097 svm->vmcb->control.exit_info_2 = 0;
3099 if (svm->nested.intercept & 1ULL) {
3101 * The #vmexit can't be emulated here directly because this
3102 * code path runs with irqs and preemption disabled. A
3103 * #vmexit emulation might sleep. Only signal request for
3106 svm->nested.exit_required = true;
3107 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3114 /* This function returns true if it is save to enable the nmi window */
3115 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3117 if (!is_guest_mode(&svm->vcpu))
3120 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3123 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3124 svm->nested.exit_required = true;
3129 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3131 unsigned port, size, iopm_len;
3136 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3137 return NESTED_EXIT_HOST;
3139 port = svm->vmcb->control.exit_info_1 >> 16;
3140 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3141 SVM_IOIO_SIZE_SHIFT;
3142 gpa = svm->nested.vmcb_iopm + (port / 8);
3143 start_bit = port % 8;
3144 iopm_len = (start_bit + size > 8) ? 2 : 1;
3145 mask = (0xf >> (4 - size)) << start_bit;
3148 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3149 return NESTED_EXIT_DONE;
3151 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3154 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3156 u32 offset, msr, value;
3159 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3160 return NESTED_EXIT_HOST;
3162 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3163 offset = svm_msrpm_offset(msr);
3164 write = svm->vmcb->control.exit_info_1 & 1;
3165 mask = 1 << ((2 * (msr & 0xf)) + write);
3167 if (offset == MSR_INVALID)
3168 return NESTED_EXIT_DONE;
3170 /* Offset is in 32 bit units but need in 8 bit units */
3173 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3174 return NESTED_EXIT_DONE;
3176 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3179 /* DB exceptions for our internal use must not cause vmexit */
3180 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3184 /* if we're not singlestepping, it's not ours */
3185 if (!svm->nmi_singlestep)
3186 return NESTED_EXIT_DONE;
3188 /* if it's not a singlestep exception, it's not ours */
3189 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3190 return NESTED_EXIT_DONE;
3191 if (!(dr6 & DR6_BS))
3192 return NESTED_EXIT_DONE;
3194 /* if the guest is singlestepping, it should get the vmexit */
3195 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3196 disable_nmi_singlestep(svm);
3197 return NESTED_EXIT_DONE;
3200 /* it's ours, the nested hypervisor must not see this one */
3201 return NESTED_EXIT_HOST;
3204 static int nested_svm_exit_special(struct vcpu_svm *svm)
3206 u32 exit_code = svm->vmcb->control.exit_code;
3208 switch (exit_code) {
3211 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3212 return NESTED_EXIT_HOST;
3214 /* For now we are always handling NPFs when using them */
3216 return NESTED_EXIT_HOST;
3218 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3219 /* When we're shadowing, trap PFs, but not async PF */
3220 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3221 return NESTED_EXIT_HOST;
3227 return NESTED_EXIT_CONTINUE;
3231 * If this function returns true, this #vmexit was already handled
3233 static int nested_svm_intercept(struct vcpu_svm *svm)
3235 u32 exit_code = svm->vmcb->control.exit_code;
3236 int vmexit = NESTED_EXIT_HOST;
3238 switch (exit_code) {
3240 vmexit = nested_svm_exit_handled_msr(svm);
3243 vmexit = nested_svm_intercept_ioio(svm);
3245 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3246 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3247 if (svm->nested.intercept_cr & bit)
3248 vmexit = NESTED_EXIT_DONE;
3251 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3252 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3253 if (svm->nested.intercept_dr & bit)
3254 vmexit = NESTED_EXIT_DONE;
3257 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3258 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3259 if (svm->nested.intercept_exceptions & excp_bits) {
3260 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3261 vmexit = nested_svm_intercept_db(svm);
3263 vmexit = NESTED_EXIT_DONE;
3265 /* async page fault always cause vmexit */
3266 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3267 svm->vcpu.arch.exception.nested_apf != 0)
3268 vmexit = NESTED_EXIT_DONE;
3271 case SVM_EXIT_ERR: {
3272 vmexit = NESTED_EXIT_DONE;
3276 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3277 if (svm->nested.intercept & exit_bits)
3278 vmexit = NESTED_EXIT_DONE;
3285 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3289 vmexit = nested_svm_intercept(svm);
3291 if (vmexit == NESTED_EXIT_DONE)
3292 nested_svm_vmexit(svm);
3297 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3299 struct vmcb_control_area *dst = &dst_vmcb->control;
3300 struct vmcb_control_area *from = &from_vmcb->control;
3302 dst->intercept_cr = from->intercept_cr;
3303 dst->intercept_dr = from->intercept_dr;
3304 dst->intercept_exceptions = from->intercept_exceptions;
3305 dst->intercept = from->intercept;
3306 dst->iopm_base_pa = from->iopm_base_pa;
3307 dst->msrpm_base_pa = from->msrpm_base_pa;
3308 dst->tsc_offset = from->tsc_offset;
3309 dst->asid = from->asid;
3310 dst->tlb_ctl = from->tlb_ctl;
3311 dst->int_ctl = from->int_ctl;
3312 dst->int_vector = from->int_vector;
3313 dst->int_state = from->int_state;
3314 dst->exit_code = from->exit_code;
3315 dst->exit_code_hi = from->exit_code_hi;
3316 dst->exit_info_1 = from->exit_info_1;
3317 dst->exit_info_2 = from->exit_info_2;
3318 dst->exit_int_info = from->exit_int_info;
3319 dst->exit_int_info_err = from->exit_int_info_err;
3320 dst->nested_ctl = from->nested_ctl;
3321 dst->event_inj = from->event_inj;
3322 dst->event_inj_err = from->event_inj_err;
3323 dst->nested_cr3 = from->nested_cr3;
3324 dst->virt_ext = from->virt_ext;
3325 dst->pause_filter_count = from->pause_filter_count;
3326 dst->pause_filter_thresh = from->pause_filter_thresh;
3329 static int nested_svm_vmexit(struct vcpu_svm *svm)
3332 struct vmcb *nested_vmcb;
3333 struct vmcb *hsave = svm->nested.hsave;
3334 struct vmcb *vmcb = svm->vmcb;
3335 struct kvm_host_map map;
3337 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3338 vmcb->control.exit_info_1,
3339 vmcb->control.exit_info_2,
3340 vmcb->control.exit_int_info,
3341 vmcb->control.exit_int_info_err,
3344 rc = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->nested.vmcb), &map);
3347 kvm_inject_gp(&svm->vcpu, 0);
3351 nested_vmcb = map.hva;
3353 /* Exit Guest-Mode */
3354 leave_guest_mode(&svm->vcpu);
3355 svm->nested.vmcb = 0;
3357 /* Give the current vmcb to the guest */
3360 nested_vmcb->save.es = vmcb->save.es;
3361 nested_vmcb->save.cs = vmcb->save.cs;
3362 nested_vmcb->save.ss = vmcb->save.ss;
3363 nested_vmcb->save.ds = vmcb->save.ds;
3364 nested_vmcb->save.gdtr = vmcb->save.gdtr;
3365 nested_vmcb->save.idtr = vmcb->save.idtr;
3366 nested_vmcb->save.efer = svm->vcpu.arch.efer;
3367 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
3368 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
3369 nested_vmcb->save.cr2 = vmcb->save.cr2;
3370 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
3371 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3372 nested_vmcb->save.rip = vmcb->save.rip;
3373 nested_vmcb->save.rsp = vmcb->save.rsp;
3374 nested_vmcb->save.rax = vmcb->save.rax;
3375 nested_vmcb->save.dr7 = vmcb->save.dr7;
3376 nested_vmcb->save.dr6 = vmcb->save.dr6;
3377 nested_vmcb->save.cpl = vmcb->save.cpl;
3379 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
3380 nested_vmcb->control.int_vector = vmcb->control.int_vector;
3381 nested_vmcb->control.int_state = vmcb->control.int_state;
3382 nested_vmcb->control.exit_code = vmcb->control.exit_code;
3383 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
3384 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
3385 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
3386 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
3387 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3389 if (svm->nrips_enabled)
3390 nested_vmcb->control.next_rip = vmcb->control.next_rip;
3393 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3394 * to make sure that we do not lose injected events. So check event_inj
3395 * here and copy it to exit_int_info if it is valid.
3396 * Exit_int_info and event_inj can't be both valid because the case
3397 * below only happens on a VMRUN instruction intercept which has
3398 * no valid exit_int_info set.
3400 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3401 struct vmcb_control_area *nc = &nested_vmcb->control;
3403 nc->exit_int_info = vmcb->control.event_inj;
3404 nc->exit_int_info_err = vmcb->control.event_inj_err;
3407 nested_vmcb->control.tlb_ctl = 0;
3408 nested_vmcb->control.event_inj = 0;
3409 nested_vmcb->control.event_inj_err = 0;
3411 nested_vmcb->control.pause_filter_count =
3412 svm->vmcb->control.pause_filter_count;
3413 nested_vmcb->control.pause_filter_thresh =
3414 svm->vmcb->control.pause_filter_thresh;
3416 /* We always set V_INTR_MASKING and remember the old value in hflags */
3417 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3418 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3420 /* Restore the original control entries */
3421 copy_vmcb_control_area(vmcb, hsave);
3423 svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3424 kvm_clear_exception_queue(&svm->vcpu);
3425 kvm_clear_interrupt_queue(&svm->vcpu);
3427 svm->nested.nested_cr3 = 0;
3429 /* Restore selected save entries */
3430 svm->vmcb->save.es = hsave->save.es;
3431 svm->vmcb->save.cs = hsave->save.cs;
3432 svm->vmcb->save.ss = hsave->save.ss;
3433 svm->vmcb->save.ds = hsave->save.ds;
3434 svm->vmcb->save.gdtr = hsave->save.gdtr;
3435 svm->vmcb->save.idtr = hsave->save.idtr;
3436 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3437 svm_set_efer(&svm->vcpu, hsave->save.efer);
3438 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3439 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3441 svm->vmcb->save.cr3 = hsave->save.cr3;
3442 svm->vcpu.arch.cr3 = hsave->save.cr3;
3444 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3446 kvm_rax_write(&svm->vcpu, hsave->save.rax);
3447 kvm_rsp_write(&svm->vcpu, hsave->save.rsp);
3448 kvm_rip_write(&svm->vcpu, hsave->save.rip);
3449 svm->vmcb->save.dr7 = 0;
3450 svm->vmcb->save.cpl = 0;
3451 svm->vmcb->control.exit_int_info = 0;
3453 mark_all_dirty(svm->vmcb);
3455 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3457 nested_svm_uninit_mmu_context(&svm->vcpu);
3458 kvm_mmu_reset_context(&svm->vcpu);
3459 kvm_mmu_load(&svm->vcpu);
3462 * Drop what we picked up for L2 via svm_complete_interrupts() so it
3463 * doesn't end up in L1.
3465 svm->vcpu.arch.nmi_injected = false;
3466 kvm_clear_exception_queue(&svm->vcpu);
3467 kvm_clear_interrupt_queue(&svm->vcpu);
3472 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3475 * This function merges the msr permission bitmaps of kvm and the
3476 * nested vmcb. It is optimized in that it only merges the parts where
3477 * the kvm msr permission bitmap may contain zero bits
3481 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3484 for (i = 0; i < MSRPM_OFFSETS; i++) {
3488 if (msrpm_offsets[i] == 0xffffffff)
3491 p = msrpm_offsets[i];
3492 offset = svm->nested.vmcb_msrpm + (p * 4);
3494 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3497 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3500 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3505 static bool nested_vmcb_checks(struct vmcb *vmcb)
3507 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3510 if (vmcb->control.asid == 0)
3513 if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3520 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3521 struct vmcb *nested_vmcb, struct kvm_host_map *map)
3523 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3524 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3526 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3528 if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3529 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3530 nested_svm_init_mmu_context(&svm->vcpu);
3533 /* Load the nested guest state */
3534 svm->vmcb->save.es = nested_vmcb->save.es;
3535 svm->vmcb->save.cs = nested_vmcb->save.cs;
3536 svm->vmcb->save.ss = nested_vmcb->save.ss;
3537 svm->vmcb->save.ds = nested_vmcb->save.ds;
3538 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3539 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3540 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3541 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3542 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3543 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3545 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3546 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3548 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3550 /* Guest paging mode is active - reset mmu */
3551 kvm_mmu_reset_context(&svm->vcpu);
3553 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3554 kvm_rax_write(&svm->vcpu, nested_vmcb->save.rax);
3555 kvm_rsp_write(&svm->vcpu, nested_vmcb->save.rsp);
3556 kvm_rip_write(&svm->vcpu, nested_vmcb->save.rip);
3558 /* In case we don't even reach vcpu_run, the fields are not updated */
3559 svm->vmcb->save.rax = nested_vmcb->save.rax;
3560 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3561 svm->vmcb->save.rip = nested_vmcb->save.rip;
3562 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3563 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3564 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3566 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3567 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3569 /* cache intercepts */
3570 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3571 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3572 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3573 svm->nested.intercept = nested_vmcb->control.intercept;
3575 svm_flush_tlb(&svm->vcpu, true);
3576 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3577 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3578 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3580 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3582 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3583 /* We only want the cr8 intercept bits of the guest */
3584 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3585 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3588 /* We don't want to see VMMCALLs from a nested guest */
3589 clr_intercept(svm, INTERCEPT_VMMCALL);
3591 svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3592 svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3594 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3595 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3596 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3597 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3598 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3600 svm->vmcb->control.pause_filter_count =
3601 nested_vmcb->control.pause_filter_count;
3602 svm->vmcb->control.pause_filter_thresh =
3603 nested_vmcb->control.pause_filter_thresh;
3605 kvm_vcpu_unmap(&svm->vcpu, map, true);
3607 /* Enter Guest-Mode */
3608 enter_guest_mode(&svm->vcpu);
3611 * Merge guest and host intercepts - must be called with vcpu in
3612 * guest-mode to take affect here
3614 recalc_intercepts(svm);
3616 svm->nested.vmcb = vmcb_gpa;
3620 mark_all_dirty(svm->vmcb);
3623 static int nested_svm_vmrun(struct vcpu_svm *svm)
3626 struct vmcb *nested_vmcb;
3627 struct vmcb *hsave = svm->nested.hsave;
3628 struct vmcb *vmcb = svm->vmcb;
3629 struct kvm_host_map map;
3632 vmcb_gpa = svm->vmcb->save.rax;
3634 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb_gpa), &map);
3635 if (ret == -EINVAL) {
3636 kvm_inject_gp(&svm->vcpu, 0);
3639 return kvm_skip_emulated_instruction(&svm->vcpu);
3642 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3644 nested_vmcb = map.hva;
3646 if (!nested_vmcb_checks(nested_vmcb)) {
3647 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
3648 nested_vmcb->control.exit_code_hi = 0;
3649 nested_vmcb->control.exit_info_1 = 0;
3650 nested_vmcb->control.exit_info_2 = 0;
3652 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3657 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3658 nested_vmcb->save.rip,
3659 nested_vmcb->control.int_ctl,
3660 nested_vmcb->control.event_inj,
3661 nested_vmcb->control.nested_ctl);
3663 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3664 nested_vmcb->control.intercept_cr >> 16,
3665 nested_vmcb->control.intercept_exceptions,
3666 nested_vmcb->control.intercept);
3668 /* Clear internal status */
3669 kvm_clear_exception_queue(&svm->vcpu);
3670 kvm_clear_interrupt_queue(&svm->vcpu);
3673 * Save the old vmcb, so we don't need to pick what we save, but can
3674 * restore everything when a VMEXIT occurs
3676 hsave->save.es = vmcb->save.es;
3677 hsave->save.cs = vmcb->save.cs;
3678 hsave->save.ss = vmcb->save.ss;
3679 hsave->save.ds = vmcb->save.ds;
3680 hsave->save.gdtr = vmcb->save.gdtr;
3681 hsave->save.idtr = vmcb->save.idtr;
3682 hsave->save.efer = svm->vcpu.arch.efer;
3683 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
3684 hsave->save.cr4 = svm->vcpu.arch.cr4;
3685 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3686 hsave->save.rip = kvm_rip_read(&svm->vcpu);
3687 hsave->save.rsp = vmcb->save.rsp;
3688 hsave->save.rax = vmcb->save.rax;
3690 hsave->save.cr3 = vmcb->save.cr3;
3692 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
3694 copy_vmcb_control_area(hsave, vmcb);
3696 enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, &map);
3698 if (!nested_svm_vmrun_msrpm(svm)) {
3699 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3700 svm->vmcb->control.exit_code_hi = 0;
3701 svm->vmcb->control.exit_info_1 = 0;
3702 svm->vmcb->control.exit_info_2 = 0;
3704 nested_svm_vmexit(svm);
3710 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3712 to_vmcb->save.fs = from_vmcb->save.fs;
3713 to_vmcb->save.gs = from_vmcb->save.gs;
3714 to_vmcb->save.tr = from_vmcb->save.tr;
3715 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3716 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3717 to_vmcb->save.star = from_vmcb->save.star;
3718 to_vmcb->save.lstar = from_vmcb->save.lstar;
3719 to_vmcb->save.cstar = from_vmcb->save.cstar;
3720 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3721 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3722 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3723 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3726 static int vmload_interception(struct vcpu_svm *svm)
3728 struct vmcb *nested_vmcb;
3729 struct kvm_host_map map;
3732 if (nested_svm_check_permissions(svm))
3735 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3738 kvm_inject_gp(&svm->vcpu, 0);
3742 nested_vmcb = map.hva;
3744 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3746 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3747 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3752 static int vmsave_interception(struct vcpu_svm *svm)
3754 struct vmcb *nested_vmcb;
3755 struct kvm_host_map map;
3758 if (nested_svm_check_permissions(svm))
3761 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3764 kvm_inject_gp(&svm->vcpu, 0);
3768 nested_vmcb = map.hva;
3770 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3772 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3773 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3778 static int vmrun_interception(struct vcpu_svm *svm)
3780 if (nested_svm_check_permissions(svm))
3783 return nested_svm_vmrun(svm);
3786 static int stgi_interception(struct vcpu_svm *svm)
3790 if (nested_svm_check_permissions(svm))
3794 * If VGIF is enabled, the STGI intercept is only added to
3795 * detect the opening of the SMI/NMI window; remove it now.
3797 if (vgif_enabled(svm))
3798 clr_intercept(svm, INTERCEPT_STGI);
3800 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3801 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3808 static int clgi_interception(struct vcpu_svm *svm)
3812 if (nested_svm_check_permissions(svm))
3815 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3819 /* After a CLGI no interrupts should come */
3820 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3821 svm_clear_vintr(svm);
3822 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3823 mark_dirty(svm->vmcb, VMCB_INTR);
3829 static int invlpga_interception(struct vcpu_svm *svm)
3831 struct kvm_vcpu *vcpu = &svm->vcpu;
3833 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
3834 kvm_rax_read(&svm->vcpu));
3836 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3837 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
3839 return kvm_skip_emulated_instruction(&svm->vcpu);
3842 static int skinit_interception(struct vcpu_svm *svm)
3844 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
3846 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3850 static int wbinvd_interception(struct vcpu_svm *svm)
3852 return kvm_emulate_wbinvd(&svm->vcpu);
3855 static int xsetbv_interception(struct vcpu_svm *svm)
3857 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3858 u32 index = kvm_rcx_read(&svm->vcpu);
3860 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3861 return kvm_skip_emulated_instruction(&svm->vcpu);
3867 static int rdpru_interception(struct vcpu_svm *svm)
3869 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3873 static int task_switch_interception(struct vcpu_svm *svm)
3877 int int_type = svm->vmcb->control.exit_int_info &
3878 SVM_EXITINTINFO_TYPE_MASK;
3879 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3881 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3883 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3884 bool has_error_code = false;
3887 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3889 if (svm->vmcb->control.exit_info_2 &
3890 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3891 reason = TASK_SWITCH_IRET;
3892 else if (svm->vmcb->control.exit_info_2 &
3893 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3894 reason = TASK_SWITCH_JMP;
3896 reason = TASK_SWITCH_GATE;
3898 reason = TASK_SWITCH_CALL;
3900 if (reason == TASK_SWITCH_GATE) {
3902 case SVM_EXITINTINFO_TYPE_NMI:
3903 svm->vcpu.arch.nmi_injected = false;
3905 case SVM_EXITINTINFO_TYPE_EXEPT:
3906 if (svm->vmcb->control.exit_info_2 &
3907 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3908 has_error_code = true;
3910 (u32)svm->vmcb->control.exit_info_2;
3912 kvm_clear_exception_queue(&svm->vcpu);
3914 case SVM_EXITINTINFO_TYPE_INTR:
3915 kvm_clear_interrupt_queue(&svm->vcpu);
3922 if (reason != TASK_SWITCH_GATE ||
3923 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3924 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3925 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
3926 if (!skip_emulated_instruction(&svm->vcpu))
3930 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3933 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3934 has_error_code, error_code);
3937 static int cpuid_interception(struct vcpu_svm *svm)
3939 return kvm_emulate_cpuid(&svm->vcpu);
3942 static int iret_interception(struct vcpu_svm *svm)
3944 ++svm->vcpu.stat.nmi_window_exits;
3945 clr_intercept(svm, INTERCEPT_IRET);
3946 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3947 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3948 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3952 static int invlpg_interception(struct vcpu_svm *svm)
3954 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3955 return kvm_emulate_instruction(&svm->vcpu, 0);
3957 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3958 return kvm_skip_emulated_instruction(&svm->vcpu);
3961 static int emulate_on_interception(struct vcpu_svm *svm)
3963 return kvm_emulate_instruction(&svm->vcpu, 0);
3966 static int rsm_interception(struct vcpu_svm *svm)
3968 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
3971 static int rdpmc_interception(struct vcpu_svm *svm)
3976 return emulate_on_interception(svm);
3978 err = kvm_rdpmc(&svm->vcpu);
3979 return kvm_complete_insn_gp(&svm->vcpu, err);
3982 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3985 unsigned long cr0 = svm->vcpu.arch.cr0;
3989 intercept = svm->nested.intercept;
3991 if (!is_guest_mode(&svm->vcpu) ||
3992 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3995 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3996 val &= ~SVM_CR0_SELECTIVE_MASK;
3999 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4000 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
4006 #define CR_VALID (1ULL << 63)
4008 static int cr_interception(struct vcpu_svm *svm)
4014 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
4015 return emulate_on_interception(svm);
4017 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
4018 return emulate_on_interception(svm);
4020 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4021 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
4022 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
4024 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
4027 if (cr >= 16) { /* mov to cr */
4029 val = kvm_register_read(&svm->vcpu, reg);
4032 if (!check_selective_cr0_intercepted(svm, val))
4033 err = kvm_set_cr0(&svm->vcpu, val);
4039 err = kvm_set_cr3(&svm->vcpu, val);
4042 err = kvm_set_cr4(&svm->vcpu, val);
4045 err = kvm_set_cr8(&svm->vcpu, val);
4048 WARN(1, "unhandled write to CR%d", cr);
4049 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4052 } else { /* mov from cr */
4055 val = kvm_read_cr0(&svm->vcpu);
4058 val = svm->vcpu.arch.cr2;
4061 val = kvm_read_cr3(&svm->vcpu);
4064 val = kvm_read_cr4(&svm->vcpu);
4067 val = kvm_get_cr8(&svm->vcpu);
4070 WARN(1, "unhandled read from CR%d", cr);
4071 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4074 kvm_register_write(&svm->vcpu, reg, val);
4076 return kvm_complete_insn_gp(&svm->vcpu, err);
4079 static int dr_interception(struct vcpu_svm *svm)
4084 if (svm->vcpu.guest_debug == 0) {
4086 * No more DR vmexits; force a reload of the debug registers
4087 * and reenter on this instruction. The next vmexit will
4088 * retrieve the full state of the debug registers.
4090 clr_dr_intercepts(svm);
4091 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4095 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4096 return emulate_on_interception(svm);
4098 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4099 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4101 if (dr >= 16) { /* mov to DRn */
4102 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4104 val = kvm_register_read(&svm->vcpu, reg);
4105 kvm_set_dr(&svm->vcpu, dr - 16, val);
4107 if (!kvm_require_dr(&svm->vcpu, dr))
4109 kvm_get_dr(&svm->vcpu, dr, &val);
4110 kvm_register_write(&svm->vcpu, reg, val);
4113 return kvm_skip_emulated_instruction(&svm->vcpu);
4116 static int cr8_write_interception(struct vcpu_svm *svm)
4118 struct kvm_run *kvm_run = svm->vcpu.run;
4121 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4122 /* instruction emulation calls kvm_set_cr8() */
4123 r = cr_interception(svm);
4124 if (lapic_in_kernel(&svm->vcpu))
4126 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4128 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4132 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4136 switch (msr->index) {
4137 case MSR_F10H_DECFG:
4138 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4139 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4148 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4150 struct vcpu_svm *svm = to_svm(vcpu);
4152 switch (msr_info->index) {
4154 msr_info->data = svm->vmcb->save.star;
4156 #ifdef CONFIG_X86_64
4158 msr_info->data = svm->vmcb->save.lstar;
4161 msr_info->data = svm->vmcb->save.cstar;
4163 case MSR_KERNEL_GS_BASE:
4164 msr_info->data = svm->vmcb->save.kernel_gs_base;
4166 case MSR_SYSCALL_MASK:
4167 msr_info->data = svm->vmcb->save.sfmask;
4170 case MSR_IA32_SYSENTER_CS:
4171 msr_info->data = svm->vmcb->save.sysenter_cs;
4173 case MSR_IA32_SYSENTER_EIP:
4174 msr_info->data = svm->sysenter_eip;
4176 case MSR_IA32_SYSENTER_ESP:
4177 msr_info->data = svm->sysenter_esp;
4180 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4182 msr_info->data = svm->tsc_aux;
4185 * Nobody will change the following 5 values in the VMCB so we can
4186 * safely return them on rdmsr. They will always be 0 until LBRV is
4189 case MSR_IA32_DEBUGCTLMSR:
4190 msr_info->data = svm->vmcb->save.dbgctl;
4192 case MSR_IA32_LASTBRANCHFROMIP:
4193 msr_info->data = svm->vmcb->save.br_from;
4195 case MSR_IA32_LASTBRANCHTOIP:
4196 msr_info->data = svm->vmcb->save.br_to;
4198 case MSR_IA32_LASTINTFROMIP:
4199 msr_info->data = svm->vmcb->save.last_excp_from;
4201 case MSR_IA32_LASTINTTOIP:
4202 msr_info->data = svm->vmcb->save.last_excp_to;
4204 case MSR_VM_HSAVE_PA:
4205 msr_info->data = svm->nested.hsave_msr;
4208 msr_info->data = svm->nested.vm_cr_msr;
4210 case MSR_IA32_SPEC_CTRL:
4211 if (!msr_info->host_initiated &&
4212 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4213 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4216 msr_info->data = svm->spec_ctrl;
4218 case MSR_AMD64_VIRT_SPEC_CTRL:
4219 if (!msr_info->host_initiated &&
4220 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4223 msr_info->data = svm->virt_spec_ctrl;
4225 case MSR_F15H_IC_CFG: {
4229 family = guest_cpuid_family(vcpu);
4230 model = guest_cpuid_model(vcpu);
4232 if (family < 0 || model < 0)
4233 return kvm_get_msr_common(vcpu, msr_info);
4237 if (family == 0x15 &&
4238 (model >= 0x2 && model < 0x20))
4239 msr_info->data = 0x1E;
4242 case MSR_F10H_DECFG:
4243 msr_info->data = svm->msr_decfg;
4246 return kvm_get_msr_common(vcpu, msr_info);
4251 static int rdmsr_interception(struct vcpu_svm *svm)
4253 return kvm_emulate_rdmsr(&svm->vcpu);
4256 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4258 struct vcpu_svm *svm = to_svm(vcpu);
4259 int svm_dis, chg_mask;
4261 if (data & ~SVM_VM_CR_VALID_MASK)
4264 chg_mask = SVM_VM_CR_VALID_MASK;
4266 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4267 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4269 svm->nested.vm_cr_msr &= ~chg_mask;
4270 svm->nested.vm_cr_msr |= (data & chg_mask);
4272 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4274 /* check for svm_disable while efer.svme is set */
4275 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4281 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4283 struct vcpu_svm *svm = to_svm(vcpu);
4285 u32 ecx = msr->index;
4286 u64 data = msr->data;
4288 case MSR_IA32_CR_PAT:
4289 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4291 vcpu->arch.pat = data;
4292 svm->vmcb->save.g_pat = data;
4293 mark_dirty(svm->vmcb, VMCB_NPT);
4295 case MSR_IA32_SPEC_CTRL:
4296 if (!msr->host_initiated &&
4297 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4298 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4301 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
4304 svm->spec_ctrl = data;
4310 * When it's written (to non-zero) for the first time, pass
4314 * The handling of the MSR bitmap for L2 guests is done in
4315 * nested_svm_vmrun_msrpm.
4316 * We update the L1 MSR bit as well since it will end up
4317 * touching the MSR anyway now.
4319 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4321 case MSR_IA32_PRED_CMD:
4322 if (!msr->host_initiated &&
4323 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4326 if (data & ~PRED_CMD_IBPB)
4328 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
4333 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4334 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4336 case MSR_AMD64_VIRT_SPEC_CTRL:
4337 if (!msr->host_initiated &&
4338 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4341 if (data & ~SPEC_CTRL_SSBD)
4344 svm->virt_spec_ctrl = data;
4347 svm->vmcb->save.star = data;
4349 #ifdef CONFIG_X86_64
4351 svm->vmcb->save.lstar = data;
4354 svm->vmcb->save.cstar = data;
4356 case MSR_KERNEL_GS_BASE:
4357 svm->vmcb->save.kernel_gs_base = data;
4359 case MSR_SYSCALL_MASK:
4360 svm->vmcb->save.sfmask = data;
4363 case MSR_IA32_SYSENTER_CS:
4364 svm->vmcb->save.sysenter_cs = data;
4366 case MSR_IA32_SYSENTER_EIP:
4367 svm->sysenter_eip = data;
4368 svm->vmcb->save.sysenter_eip = data;
4370 case MSR_IA32_SYSENTER_ESP:
4371 svm->sysenter_esp = data;
4372 svm->vmcb->save.sysenter_esp = data;
4375 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4379 * This is rare, so we update the MSR here instead of using
4380 * direct_access_msrs. Doing that would require a rdmsr in
4383 svm->tsc_aux = data;
4384 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4386 case MSR_IA32_DEBUGCTLMSR:
4387 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4388 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4392 if (data & DEBUGCTL_RESERVED_BITS)
4395 svm->vmcb->save.dbgctl = data;
4396 mark_dirty(svm->vmcb, VMCB_LBR);
4397 if (data & (1ULL<<0))
4398 svm_enable_lbrv(svm);
4400 svm_disable_lbrv(svm);
4402 case MSR_VM_HSAVE_PA:
4403 svm->nested.hsave_msr = data;
4406 return svm_set_vm_cr(vcpu, data);
4408 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4410 case MSR_F10H_DECFG: {
4411 struct kvm_msr_entry msr_entry;
4413 msr_entry.index = msr->index;
4414 if (svm_get_msr_feature(&msr_entry))
4417 /* Check the supported bits */
4418 if (data & ~msr_entry.data)
4421 /* Don't allow the guest to change a bit, #GP */
4422 if (!msr->host_initiated && (data ^ msr_entry.data))
4425 svm->msr_decfg = data;
4428 case MSR_IA32_APICBASE:
4429 if (kvm_vcpu_apicv_active(vcpu))
4430 avic_update_vapic_bar(to_svm(vcpu), data);
4433 return kvm_set_msr_common(vcpu, msr);
4438 static int wrmsr_interception(struct vcpu_svm *svm)
4440 return kvm_emulate_wrmsr(&svm->vcpu);
4443 static int msr_interception(struct vcpu_svm *svm)
4445 if (svm->vmcb->control.exit_info_1)
4446 return wrmsr_interception(svm);
4448 return rdmsr_interception(svm);
4451 static int interrupt_window_interception(struct vcpu_svm *svm)
4453 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4454 svm_clear_vintr(svm);
4455 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4456 mark_dirty(svm->vmcb, VMCB_INTR);
4457 ++svm->vcpu.stat.irq_window_exits;
4461 static int pause_interception(struct vcpu_svm *svm)
4463 struct kvm_vcpu *vcpu = &svm->vcpu;
4464 bool in_kernel = (svm_get_cpl(vcpu) == 0);
4466 if (pause_filter_thresh)
4467 grow_ple_window(vcpu);
4469 kvm_vcpu_on_spin(vcpu, in_kernel);
4473 static int nop_interception(struct vcpu_svm *svm)
4475 return kvm_skip_emulated_instruction(&(svm->vcpu));
4478 static int monitor_interception(struct vcpu_svm *svm)
4480 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4481 return nop_interception(svm);
4484 static int mwait_interception(struct vcpu_svm *svm)
4486 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4487 return nop_interception(svm);
4490 enum avic_ipi_failure_cause {
4491 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4492 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4493 AVIC_IPI_FAILURE_INVALID_TARGET,
4494 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4497 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4499 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4500 u32 icrl = svm->vmcb->control.exit_info_1;
4501 u32 id = svm->vmcb->control.exit_info_2 >> 32;
4502 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4503 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4505 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4508 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4510 * AVIC hardware handles the generation of
4511 * IPIs when the specified Message Type is Fixed
4512 * (also known as fixed delivery mode) and
4513 * the Trigger Mode is edge-triggered. The hardware
4514 * also supports self and broadcast delivery modes
4515 * specified via the Destination Shorthand(DSH)
4516 * field of the ICRL. Logical and physical APIC ID
4517 * formats are supported. All other IPI types cause
4518 * a #VMEXIT, which needs to emulated.
4520 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4521 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4523 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4525 struct kvm_vcpu *vcpu;
4526 struct kvm *kvm = svm->vcpu.kvm;
4527 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4530 * At this point, we expect that the AVIC HW has already
4531 * set the appropriate IRR bits on the valid target
4532 * vcpus. So, we just need to kick the appropriate vcpu.
4534 kvm_for_each_vcpu(i, vcpu, kvm) {
4535 bool m = kvm_apic_match_dest(vcpu, apic,
4536 icrl & APIC_SHORT_MASK,
4537 GET_APIC_DEST_FIELD(icrh),
4538 icrl & APIC_DEST_MASK);
4540 if (m && !avic_vcpu_is_running(vcpu))
4541 kvm_vcpu_wake_up(vcpu);
4545 case AVIC_IPI_FAILURE_INVALID_TARGET:
4546 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
4547 index, svm->vcpu.vcpu_id, icrh, icrl);
4549 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4550 WARN_ONCE(1, "Invalid backing page\n");
4553 pr_err("Unknown IPI interception\n");
4559 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4561 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4563 u32 *logical_apic_id_table;
4564 int dlid = GET_APIC_LOGICAL_ID(ldr);
4569 if (flat) { /* flat */
4570 index = ffs(dlid) - 1;
4573 } else { /* cluster */
4574 int cluster = (dlid & 0xf0) >> 4;
4575 int apic = ffs(dlid & 0x0f) - 1;
4577 if ((apic < 0) || (apic > 7) ||
4580 index = (cluster << 2) + apic;
4583 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4585 return &logical_apic_id_table[index];
4588 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr)
4591 u32 *entry, new_entry;
4593 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4594 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4598 new_entry = READ_ONCE(*entry);
4599 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4600 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4601 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4602 WRITE_ONCE(*entry, new_entry);
4607 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu)
4609 struct vcpu_svm *svm = to_svm(vcpu);
4610 bool flat = svm->dfr_reg == APIC_DFR_FLAT;
4611 u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
4614 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry);
4617 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4620 struct vcpu_svm *svm = to_svm(vcpu);
4621 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4622 u32 id = kvm_xapic_id(vcpu->arch.apic);
4624 if (ldr == svm->ldr_reg)
4627 avic_invalidate_logical_id_entry(vcpu);
4630 ret = avic_ldr_write(vcpu, id, ldr);
4638 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4641 struct vcpu_svm *svm = to_svm(vcpu);
4642 u32 id = kvm_xapic_id(vcpu->arch.apic);
4644 if (vcpu->vcpu_id == id)
4647 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4648 new = avic_get_physical_id_entry(vcpu, id);
4652 /* We need to move physical_id_entry to new offset */
4655 to_svm(vcpu)->avic_physical_id_cache = new;
4658 * Also update the guest physical APIC ID in the logical
4659 * APIC ID table entry if already setup the LDR.
4662 avic_handle_ldr_update(vcpu);
4667 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4669 struct vcpu_svm *svm = to_svm(vcpu);
4670 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4672 if (svm->dfr_reg == dfr)
4675 avic_invalidate_logical_id_entry(vcpu);
4679 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4681 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4682 u32 offset = svm->vmcb->control.exit_info_1 &
4683 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4687 if (avic_handle_apic_id_update(&svm->vcpu))
4691 if (avic_handle_ldr_update(&svm->vcpu))
4695 avic_handle_dfr_update(&svm->vcpu);
4701 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4706 static bool is_avic_unaccelerated_access_trap(u32 offset)
4735 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4738 u32 offset = svm->vmcb->control.exit_info_1 &
4739 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4740 u32 vector = svm->vmcb->control.exit_info_2 &
4741 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4742 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4743 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4744 bool trap = is_avic_unaccelerated_access_trap(offset);
4746 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4747 trap, write, vector);
4750 WARN_ONCE(!write, "svm: Handling trap read.\n");
4751 ret = avic_unaccel_trap_write(svm);
4753 /* Handling Fault */
4754 ret = kvm_emulate_instruction(&svm->vcpu, 0);
4760 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4761 [SVM_EXIT_READ_CR0] = cr_interception,
4762 [SVM_EXIT_READ_CR3] = cr_interception,
4763 [SVM_EXIT_READ_CR4] = cr_interception,
4764 [SVM_EXIT_READ_CR8] = cr_interception,
4765 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4766 [SVM_EXIT_WRITE_CR0] = cr_interception,
4767 [SVM_EXIT_WRITE_CR3] = cr_interception,
4768 [SVM_EXIT_WRITE_CR4] = cr_interception,
4769 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4770 [SVM_EXIT_READ_DR0] = dr_interception,
4771 [SVM_EXIT_READ_DR1] = dr_interception,
4772 [SVM_EXIT_READ_DR2] = dr_interception,
4773 [SVM_EXIT_READ_DR3] = dr_interception,
4774 [SVM_EXIT_READ_DR4] = dr_interception,
4775 [SVM_EXIT_READ_DR5] = dr_interception,
4776 [SVM_EXIT_READ_DR6] = dr_interception,
4777 [SVM_EXIT_READ_DR7] = dr_interception,
4778 [SVM_EXIT_WRITE_DR0] = dr_interception,
4779 [SVM_EXIT_WRITE_DR1] = dr_interception,
4780 [SVM_EXIT_WRITE_DR2] = dr_interception,
4781 [SVM_EXIT_WRITE_DR3] = dr_interception,
4782 [SVM_EXIT_WRITE_DR4] = dr_interception,
4783 [SVM_EXIT_WRITE_DR5] = dr_interception,
4784 [SVM_EXIT_WRITE_DR6] = dr_interception,
4785 [SVM_EXIT_WRITE_DR7] = dr_interception,
4786 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4787 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4788 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4789 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4790 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4791 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4792 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
4793 [SVM_EXIT_INTR] = intr_interception,
4794 [SVM_EXIT_NMI] = nmi_interception,
4795 [SVM_EXIT_SMI] = nop_on_interception,
4796 [SVM_EXIT_INIT] = nop_on_interception,
4797 [SVM_EXIT_VINTR] = interrupt_window_interception,
4798 [SVM_EXIT_RDPMC] = rdpmc_interception,
4799 [SVM_EXIT_CPUID] = cpuid_interception,
4800 [SVM_EXIT_IRET] = iret_interception,
4801 [SVM_EXIT_INVD] = emulate_on_interception,
4802 [SVM_EXIT_PAUSE] = pause_interception,
4803 [SVM_EXIT_HLT] = halt_interception,
4804 [SVM_EXIT_INVLPG] = invlpg_interception,
4805 [SVM_EXIT_INVLPGA] = invlpga_interception,
4806 [SVM_EXIT_IOIO] = io_interception,
4807 [SVM_EXIT_MSR] = msr_interception,
4808 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4809 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4810 [SVM_EXIT_VMRUN] = vmrun_interception,
4811 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4812 [SVM_EXIT_VMLOAD] = vmload_interception,
4813 [SVM_EXIT_VMSAVE] = vmsave_interception,
4814 [SVM_EXIT_STGI] = stgi_interception,
4815 [SVM_EXIT_CLGI] = clgi_interception,
4816 [SVM_EXIT_SKINIT] = skinit_interception,
4817 [SVM_EXIT_WBINVD] = wbinvd_interception,
4818 [SVM_EXIT_MONITOR] = monitor_interception,
4819 [SVM_EXIT_MWAIT] = mwait_interception,
4820 [SVM_EXIT_XSETBV] = xsetbv_interception,
4821 [SVM_EXIT_RDPRU] = rdpru_interception,
4822 [SVM_EXIT_NPF] = npf_interception,
4823 [SVM_EXIT_RSM] = rsm_interception,
4824 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4825 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4828 static void dump_vmcb(struct kvm_vcpu *vcpu)
4830 struct vcpu_svm *svm = to_svm(vcpu);
4831 struct vmcb_control_area *control = &svm->vmcb->control;
4832 struct vmcb_save_area *save = &svm->vmcb->save;
4834 if (!dump_invalid_vmcb) {
4835 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
4839 pr_err("VMCB Control Area:\n");
4840 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4841 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4842 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4843 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4844 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4845 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4846 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4847 pr_err("%-20s%d\n", "pause filter threshold:",
4848 control->pause_filter_thresh);
4849 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4850 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4851 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4852 pr_err("%-20s%d\n", "asid:", control->asid);
4853 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4854 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4855 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4856 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4857 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4858 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4859 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4860 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4861 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4862 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4863 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4864 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4865 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4866 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4867 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4868 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4869 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4870 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4871 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4872 pr_err("VMCB State Save Area:\n");
4873 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4875 save->es.selector, save->es.attrib,
4876 save->es.limit, save->es.base);
4877 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4879 save->cs.selector, save->cs.attrib,
4880 save->cs.limit, save->cs.base);
4881 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4883 save->ss.selector, save->ss.attrib,
4884 save->ss.limit, save->ss.base);
4885 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4887 save->ds.selector, save->ds.attrib,
4888 save->ds.limit, save->ds.base);
4889 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4891 save->fs.selector, save->fs.attrib,
4892 save->fs.limit, save->fs.base);
4893 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4895 save->gs.selector, save->gs.attrib,
4896 save->gs.limit, save->gs.base);
4897 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4899 save->gdtr.selector, save->gdtr.attrib,
4900 save->gdtr.limit, save->gdtr.base);
4901 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4903 save->ldtr.selector, save->ldtr.attrib,
4904 save->ldtr.limit, save->ldtr.base);
4905 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4907 save->idtr.selector, save->idtr.attrib,
4908 save->idtr.limit, save->idtr.base);
4909 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4911 save->tr.selector, save->tr.attrib,
4912 save->tr.limit, save->tr.base);
4913 pr_err("cpl: %d efer: %016llx\n",
4914 save->cpl, save->efer);
4915 pr_err("%-15s %016llx %-13s %016llx\n",
4916 "cr0:", save->cr0, "cr2:", save->cr2);
4917 pr_err("%-15s %016llx %-13s %016llx\n",
4918 "cr3:", save->cr3, "cr4:", save->cr4);
4919 pr_err("%-15s %016llx %-13s %016llx\n",
4920 "dr6:", save->dr6, "dr7:", save->dr7);
4921 pr_err("%-15s %016llx %-13s %016llx\n",
4922 "rip:", save->rip, "rflags:", save->rflags);
4923 pr_err("%-15s %016llx %-13s %016llx\n",
4924 "rsp:", save->rsp, "rax:", save->rax);
4925 pr_err("%-15s %016llx %-13s %016llx\n",
4926 "star:", save->star, "lstar:", save->lstar);
4927 pr_err("%-15s %016llx %-13s %016llx\n",
4928 "cstar:", save->cstar, "sfmask:", save->sfmask);
4929 pr_err("%-15s %016llx %-13s %016llx\n",
4930 "kernel_gs_base:", save->kernel_gs_base,
4931 "sysenter_cs:", save->sysenter_cs);
4932 pr_err("%-15s %016llx %-13s %016llx\n",
4933 "sysenter_esp:", save->sysenter_esp,
4934 "sysenter_eip:", save->sysenter_eip);
4935 pr_err("%-15s %016llx %-13s %016llx\n",
4936 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4937 pr_err("%-15s %016llx %-13s %016llx\n",
4938 "br_from:", save->br_from, "br_to:", save->br_to);
4939 pr_err("%-15s %016llx %-13s %016llx\n",
4940 "excp_from:", save->last_excp_from,
4941 "excp_to:", save->last_excp_to);
4944 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4946 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4948 *info1 = control->exit_info_1;
4949 *info2 = control->exit_info_2;
4952 static int handle_exit(struct kvm_vcpu *vcpu,
4953 enum exit_fastpath_completion exit_fastpath)
4955 struct vcpu_svm *svm = to_svm(vcpu);
4956 struct kvm_run *kvm_run = vcpu->run;
4957 u32 exit_code = svm->vmcb->control.exit_code;
4959 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4961 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4962 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4964 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4966 if (unlikely(svm->nested.exit_required)) {
4967 nested_svm_vmexit(svm);
4968 svm->nested.exit_required = false;
4973 if (is_guest_mode(vcpu)) {
4976 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4977 svm->vmcb->control.exit_info_1,
4978 svm->vmcb->control.exit_info_2,
4979 svm->vmcb->control.exit_int_info,
4980 svm->vmcb->control.exit_int_info_err,
4983 vmexit = nested_svm_exit_special(svm);
4985 if (vmexit == NESTED_EXIT_CONTINUE)
4986 vmexit = nested_svm_exit_handled(svm);
4988 if (vmexit == NESTED_EXIT_DONE)
4992 svm_complete_interrupts(svm);
4994 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4995 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4996 kvm_run->fail_entry.hardware_entry_failure_reason
4997 = svm->vmcb->control.exit_code;
5002 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
5003 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
5004 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
5005 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
5006 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
5008 __func__, svm->vmcb->control.exit_int_info,
5011 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5012 kvm_skip_emulated_instruction(vcpu);
5014 } else if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
5015 || !svm_exit_handlers[exit_code]) {
5016 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
5018 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5019 vcpu->run->internal.suberror =
5020 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5021 vcpu->run->internal.ndata = 1;
5022 vcpu->run->internal.data[0] = exit_code;
5026 #ifdef CONFIG_RETPOLINE
5027 if (exit_code == SVM_EXIT_MSR)
5028 return msr_interception(svm);
5029 else if (exit_code == SVM_EXIT_VINTR)
5030 return interrupt_window_interception(svm);
5031 else if (exit_code == SVM_EXIT_INTR)
5032 return intr_interception(svm);
5033 else if (exit_code == SVM_EXIT_HLT)
5034 return halt_interception(svm);
5035 else if (exit_code == SVM_EXIT_NPF)
5036 return npf_interception(svm);
5038 return svm_exit_handlers[exit_code](svm);
5041 static void reload_tss(struct kvm_vcpu *vcpu)
5043 int cpu = raw_smp_processor_id();
5045 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5046 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5050 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5052 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5053 int asid = sev_get_asid(svm->vcpu.kvm);
5055 /* Assign the asid allocated with this SEV guest */
5056 svm->vmcb->control.asid = asid;
5061 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5062 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5064 if (sd->sev_vmcbs[asid] == svm->vmcb &&
5065 svm->last_cpu == cpu)
5068 svm->last_cpu = cpu;
5069 sd->sev_vmcbs[asid] = svm->vmcb;
5070 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5071 mark_dirty(svm->vmcb, VMCB_ASID);
5074 static void pre_svm_run(struct vcpu_svm *svm)
5076 int cpu = raw_smp_processor_id();
5078 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5080 if (sev_guest(svm->vcpu.kvm))
5081 return pre_sev_run(svm, cpu);
5083 /* FIXME: handle wraparound of asid_generation */
5084 if (svm->asid_generation != sd->asid_generation)
5088 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5090 struct vcpu_svm *svm = to_svm(vcpu);
5092 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5093 vcpu->arch.hflags |= HF_NMI_MASK;
5094 set_intercept(svm, INTERCEPT_IRET);
5095 ++vcpu->stat.nmi_injections;
5098 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5100 struct vmcb_control_area *control;
5102 /* The following fields are ignored when AVIC is enabled */
5103 control = &svm->vmcb->control;
5104 control->int_vector = irq;
5105 control->int_ctl &= ~V_INTR_PRIO_MASK;
5106 control->int_ctl |= V_IRQ_MASK |
5107 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5108 mark_dirty(svm->vmcb, VMCB_INTR);
5111 static void svm_set_irq(struct kvm_vcpu *vcpu)
5113 struct vcpu_svm *svm = to_svm(vcpu);
5115 BUG_ON(!(gif_set(svm)));
5117 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5118 ++vcpu->stat.irq_injections;
5120 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5121 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5124 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5126 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5129 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5131 struct vcpu_svm *svm = to_svm(vcpu);
5133 if (svm_nested_virtualize_tpr(vcpu))
5136 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5142 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5145 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5150 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5154 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5158 static int svm_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate)
5161 unsigned long flags;
5162 struct amd_svm_iommu_ir *ir;
5163 struct vcpu_svm *svm = to_svm(vcpu);
5165 if (!kvm_arch_has_assigned_device(vcpu->kvm))
5169 * Here, we go through the per-vcpu ir_list to update all existing
5170 * interrupt remapping table entry targeting this vcpu.
5172 spin_lock_irqsave(&svm->ir_list_lock, flags);
5174 if (list_empty(&svm->ir_list))
5177 list_for_each_entry(ir, &svm->ir_list, node) {
5179 ret = amd_iommu_activate_guest_mode(ir->data);
5181 ret = amd_iommu_deactivate_guest_mode(ir->data);
5186 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5190 /* Note: Currently only used by Hyper-V. */
5191 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5193 struct vcpu_svm *svm = to_svm(vcpu);
5194 struct vmcb *vmcb = svm->vmcb;
5195 bool activated = kvm_vcpu_apicv_active(vcpu);
5198 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
5200 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5201 mark_dirty(vmcb, VMCB_AVIC);
5203 svm_set_pi_irte_mode(vcpu, activated);
5206 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5211 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5213 kvm_lapic_set_irr(vec, vcpu->arch.apic);
5214 smp_mb__after_atomic();
5216 if (avic_vcpu_is_running(vcpu)) {
5217 int cpuid = vcpu->cpu;
5219 if (cpuid != get_cpu())
5220 wrmsrl(SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpuid));
5223 kvm_vcpu_wake_up(vcpu);
5226 static bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
5231 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5233 unsigned long flags;
5234 struct amd_svm_iommu_ir *cur;
5236 spin_lock_irqsave(&svm->ir_list_lock, flags);
5237 list_for_each_entry(cur, &svm->ir_list, node) {
5238 if (cur->data != pi->ir_data)
5240 list_del(&cur->node);
5244 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5247 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5250 unsigned long flags;
5251 struct amd_svm_iommu_ir *ir;
5254 * In some cases, the existing irte is updaed and re-set,
5255 * so we need to check here if it's already been * added
5258 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5259 struct kvm *kvm = svm->vcpu.kvm;
5260 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5261 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5262 struct vcpu_svm *prev_svm;
5269 prev_svm = to_svm(prev_vcpu);
5270 svm_ir_list_del(prev_svm, pi);
5274 * Allocating new amd_iommu_pi_data, which will get
5275 * add to the per-vcpu ir_list.
5277 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT);
5282 ir->data = pi->ir_data;
5284 spin_lock_irqsave(&svm->ir_list_lock, flags);
5285 list_add(&ir->node, &svm->ir_list);
5286 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5293 * The HW cannot support posting multicast/broadcast
5294 * interrupts to a vCPU. So, we still use legacy interrupt
5295 * remapping for these kind of interrupts.
5297 * For lowest-priority interrupts, we only support
5298 * those with single CPU as the destination, e.g. user
5299 * configures the interrupts via /proc/irq or uses
5300 * irqbalance to make the interrupts single-CPU.
5303 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5304 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5306 struct kvm_lapic_irq irq;
5307 struct kvm_vcpu *vcpu = NULL;
5309 kvm_set_msi_irq(kvm, e, &irq);
5311 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
5312 !kvm_irq_is_postable(&irq)) {
5313 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5314 __func__, irq.vector);
5318 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5320 *svm = to_svm(vcpu);
5321 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5322 vcpu_info->vector = irq.vector;
5328 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5331 * @host_irq: host irq of the interrupt
5332 * @guest_irq: gsi of the interrupt
5333 * @set: set or unset PI
5334 * returns 0 on success, < 0 on failure
5336 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5337 uint32_t guest_irq, bool set)
5339 struct kvm_kernel_irq_routing_entry *e;
5340 struct kvm_irq_routing_table *irq_rt;
5341 int idx, ret = -EINVAL;
5343 if (!kvm_arch_has_assigned_device(kvm) ||
5344 !irq_remapping_cap(IRQ_POSTING_CAP))
5347 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5348 __func__, host_irq, guest_irq, set);
5350 idx = srcu_read_lock(&kvm->irq_srcu);
5351 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5352 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5354 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5355 struct vcpu_data vcpu_info;
5356 struct vcpu_svm *svm = NULL;
5358 if (e->type != KVM_IRQ_ROUTING_MSI)
5362 * Here, we setup with legacy mode in the following cases:
5363 * 1. When cannot target interrupt to a specific vcpu.
5364 * 2. Unsetting posted interrupt.
5365 * 3. APIC virtialization is disabled for the vcpu.
5366 * 4. IRQ has incompatible delivery mode (SMI, INIT, etc)
5368 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5369 kvm_vcpu_apicv_active(&svm->vcpu)) {
5370 struct amd_iommu_pi_data pi;
5372 /* Try to enable guest_mode in IRTE */
5373 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5375 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5377 pi.is_guest_mode = true;
5378 pi.vcpu_data = &vcpu_info;
5379 ret = irq_set_vcpu_affinity(host_irq, &pi);
5382 * Here, we successfully setting up vcpu affinity in
5383 * IOMMU guest mode. Now, we need to store the posted
5384 * interrupt information in a per-vcpu ir_list so that
5385 * we can reference to them directly when we update vcpu
5386 * scheduling information in IOMMU irte.
5388 if (!ret && pi.is_guest_mode)
5389 svm_ir_list_add(svm, &pi);
5391 /* Use legacy mode in IRTE */
5392 struct amd_iommu_pi_data pi;
5395 * Here, pi is used to:
5396 * - Tell IOMMU to use legacy mode for this interrupt.
5397 * - Retrieve ga_tag of prior interrupt remapping data.
5399 pi.is_guest_mode = false;
5400 ret = irq_set_vcpu_affinity(host_irq, &pi);
5403 * Check if the posted interrupt was previously
5404 * setup with the guest_mode by checking if the ga_tag
5405 * was cached. If so, we need to clean up the per-vcpu
5408 if (!ret && pi.prev_ga_tag) {
5409 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5410 struct kvm_vcpu *vcpu;
5412 vcpu = kvm_get_vcpu_by_id(kvm, id);
5414 svm_ir_list_del(to_svm(vcpu), &pi);
5419 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5420 e->gsi, vcpu_info.vector,
5421 vcpu_info.pi_desc_addr, set);
5425 pr_err("%s: failed to update PI IRTE\n", __func__);
5432 srcu_read_unlock(&kvm->irq_srcu, idx);
5436 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5438 struct vcpu_svm *svm = to_svm(vcpu);
5439 struct vmcb *vmcb = svm->vmcb;
5441 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5442 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5443 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5448 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5450 struct vcpu_svm *svm = to_svm(vcpu);
5452 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5455 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5457 struct vcpu_svm *svm = to_svm(vcpu);
5460 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5461 set_intercept(svm, INTERCEPT_IRET);
5463 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5464 clr_intercept(svm, INTERCEPT_IRET);
5468 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5470 struct vcpu_svm *svm = to_svm(vcpu);
5471 struct vmcb *vmcb = svm->vmcb;
5474 if (!gif_set(svm) ||
5475 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5478 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5480 if (is_guest_mode(vcpu))
5481 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5486 static void enable_irq_window(struct kvm_vcpu *vcpu)
5488 struct vcpu_svm *svm = to_svm(vcpu);
5490 if (kvm_vcpu_apicv_active(vcpu))
5494 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5495 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5496 * get that intercept, this function will be called again though and
5497 * we'll get the vintr intercept. However, if the vGIF feature is
5498 * enabled, the STGI interception will not occur. Enable the irq
5499 * window under the assumption that the hardware will set the GIF.
5501 if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5503 svm_inject_irq(svm, 0x0);
5507 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5509 struct vcpu_svm *svm = to_svm(vcpu);
5511 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5513 return; /* IRET will cause a vm exit */
5515 if (!gif_set(svm)) {
5516 if (vgif_enabled(svm))
5517 set_intercept(svm, INTERCEPT_STGI);
5518 return; /* STGI will cause a vm exit */
5521 if (svm->nested.exit_required)
5522 return; /* we're not going to run the guest yet */
5525 * Something prevents NMI from been injected. Single step over possible
5526 * problem (IRET or exception injection or interrupt shadow)
5528 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5529 svm->nmi_singlestep = true;
5530 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5533 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5538 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5543 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5545 struct vcpu_svm *svm = to_svm(vcpu);
5547 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5548 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5550 svm->asid_generation--;
5553 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5555 struct vcpu_svm *svm = to_svm(vcpu);
5557 invlpga(gva, svm->vmcb->control.asid);
5560 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5564 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5566 struct vcpu_svm *svm = to_svm(vcpu);
5568 if (svm_nested_virtualize_tpr(vcpu))
5571 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5572 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5573 kvm_set_cr8(vcpu, cr8);
5577 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5579 struct vcpu_svm *svm = to_svm(vcpu);
5582 if (svm_nested_virtualize_tpr(vcpu) ||
5583 kvm_vcpu_apicv_active(vcpu))
5586 cr8 = kvm_get_cr8(vcpu);
5587 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5588 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5591 static void svm_complete_interrupts(struct vcpu_svm *svm)
5595 u32 exitintinfo = svm->vmcb->control.exit_int_info;
5596 unsigned int3_injected = svm->int3_injected;
5598 svm->int3_injected = 0;
5601 * If we've made progress since setting HF_IRET_MASK, we've
5602 * executed an IRET and can allow NMI injection.
5604 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5605 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5606 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5607 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5610 svm->vcpu.arch.nmi_injected = false;
5611 kvm_clear_exception_queue(&svm->vcpu);
5612 kvm_clear_interrupt_queue(&svm->vcpu);
5614 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5617 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5619 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5620 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5623 case SVM_EXITINTINFO_TYPE_NMI:
5624 svm->vcpu.arch.nmi_injected = true;
5626 case SVM_EXITINTINFO_TYPE_EXEPT:
5628 * In case of software exceptions, do not reinject the vector,
5629 * but re-execute the instruction instead. Rewind RIP first
5630 * if we emulated INT3 before.
5632 if (kvm_exception_is_soft(vector)) {
5633 if (vector == BP_VECTOR && int3_injected &&
5634 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5635 kvm_rip_write(&svm->vcpu,
5636 kvm_rip_read(&svm->vcpu) -
5640 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5641 u32 err = svm->vmcb->control.exit_int_info_err;
5642 kvm_requeue_exception_e(&svm->vcpu, vector, err);
5645 kvm_requeue_exception(&svm->vcpu, vector);
5647 case SVM_EXITINTINFO_TYPE_INTR:
5648 kvm_queue_interrupt(&svm->vcpu, vector, false);
5655 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5657 struct vcpu_svm *svm = to_svm(vcpu);
5658 struct vmcb_control_area *control = &svm->vmcb->control;
5660 control->exit_int_info = control->event_inj;
5661 control->exit_int_info_err = control->event_inj_err;
5662 control->event_inj = 0;
5663 svm_complete_interrupts(svm);
5666 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5668 struct vcpu_svm *svm = to_svm(vcpu);
5670 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5671 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5672 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5675 * A vmexit emulation is required before the vcpu can be executed
5678 if (unlikely(svm->nested.exit_required))
5682 * Disable singlestep if we're injecting an interrupt/exception.
5683 * We don't want our modified rflags to be pushed on the stack where
5684 * we might not be able to easily reset them if we disabled NMI
5687 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5689 * Event injection happens before external interrupts cause a
5690 * vmexit and interrupts are disabled here, so smp_send_reschedule
5691 * is enough to force an immediate vmexit.
5693 disable_nmi_singlestep(svm);
5694 smp_send_reschedule(vcpu->cpu);
5699 sync_lapic_to_cr8(vcpu);
5701 svm->vmcb->save.cr2 = vcpu->arch.cr2;
5704 kvm_load_guest_xsave_state(vcpu);
5706 if (lapic_in_kernel(vcpu) &&
5707 vcpu->arch.apic->lapic_timer.timer_advance_ns)
5708 kvm_wait_lapic_expire(vcpu);
5711 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5712 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5713 * is no need to worry about the conditional branch over the wrmsr
5714 * being speculatively taken.
5716 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5721 "push %%" _ASM_BP "; \n\t"
5722 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5723 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5724 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5725 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5726 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5727 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5728 #ifdef CONFIG_X86_64
5729 "mov %c[r8](%[svm]), %%r8 \n\t"
5730 "mov %c[r9](%[svm]), %%r9 \n\t"
5731 "mov %c[r10](%[svm]), %%r10 \n\t"
5732 "mov %c[r11](%[svm]), %%r11 \n\t"
5733 "mov %c[r12](%[svm]), %%r12 \n\t"
5734 "mov %c[r13](%[svm]), %%r13 \n\t"
5735 "mov %c[r14](%[svm]), %%r14 \n\t"
5736 "mov %c[r15](%[svm]), %%r15 \n\t"
5739 /* Enter guest mode */
5740 "push %%" _ASM_AX " \n\t"
5741 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5742 __ex("vmload %%" _ASM_AX) "\n\t"
5743 __ex("vmrun %%" _ASM_AX) "\n\t"
5744 __ex("vmsave %%" _ASM_AX) "\n\t"
5745 "pop %%" _ASM_AX " \n\t"
5747 /* Save guest registers, load host registers */
5748 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5749 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5750 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5751 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5752 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5753 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5754 #ifdef CONFIG_X86_64
5755 "mov %%r8, %c[r8](%[svm]) \n\t"
5756 "mov %%r9, %c[r9](%[svm]) \n\t"
5757 "mov %%r10, %c[r10](%[svm]) \n\t"
5758 "mov %%r11, %c[r11](%[svm]) \n\t"
5759 "mov %%r12, %c[r12](%[svm]) \n\t"
5760 "mov %%r13, %c[r13](%[svm]) \n\t"
5761 "mov %%r14, %c[r14](%[svm]) \n\t"
5762 "mov %%r15, %c[r15](%[svm]) \n\t"
5764 * Clear host registers marked as clobbered to prevent
5767 "xor %%r8d, %%r8d \n\t"
5768 "xor %%r9d, %%r9d \n\t"
5769 "xor %%r10d, %%r10d \n\t"
5770 "xor %%r11d, %%r11d \n\t"
5771 "xor %%r12d, %%r12d \n\t"
5772 "xor %%r13d, %%r13d \n\t"
5773 "xor %%r14d, %%r14d \n\t"
5774 "xor %%r15d, %%r15d \n\t"
5776 "xor %%ebx, %%ebx \n\t"
5777 "xor %%ecx, %%ecx \n\t"
5778 "xor %%edx, %%edx \n\t"
5779 "xor %%esi, %%esi \n\t"
5780 "xor %%edi, %%edi \n\t"
5784 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5785 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5786 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5787 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5788 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5789 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5790 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5791 #ifdef CONFIG_X86_64
5792 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5793 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5794 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5795 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5796 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5797 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5798 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5799 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5802 #ifdef CONFIG_X86_64
5803 , "rbx", "rcx", "rdx", "rsi", "rdi"
5804 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5806 , "ebx", "ecx", "edx", "esi", "edi"
5810 /* Eliminate branch target predictions from guest mode */
5813 #ifdef CONFIG_X86_64
5814 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5816 loadsegment(fs, svm->host.fs);
5817 #ifndef CONFIG_X86_32_LAZY_GS
5818 loadsegment(gs, svm->host.gs);
5823 * We do not use IBRS in the kernel. If this vCPU has used the
5824 * SPEC_CTRL MSR it may have left it on; save the value and
5825 * turn it off. This is much more efficient than blindly adding
5826 * it to the atomic save/restore list. Especially as the former
5827 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5829 * For non-nested case:
5830 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5834 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5837 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5838 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5842 local_irq_disable();
5844 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5846 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5847 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5848 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5849 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5851 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5852 kvm_before_interrupt(&svm->vcpu);
5854 kvm_load_host_xsave_state(vcpu);
5857 /* Any pending NMI will happen here */
5859 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5860 kvm_after_interrupt(&svm->vcpu);
5862 sync_cr8_to_lapic(vcpu);
5866 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5868 /* if exit due to PF check for async PF */
5869 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5870 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5873 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5874 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5878 * We need to handle MC intercepts here before the vcpu has a chance to
5879 * change the physical cpu
5881 if (unlikely(svm->vmcb->control.exit_code ==
5882 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5883 svm_handle_mce(svm);
5885 mark_all_clean(svm->vmcb);
5887 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5889 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5891 struct vcpu_svm *svm = to_svm(vcpu);
5893 svm->vmcb->save.cr3 = __sme_set(root);
5894 mark_dirty(svm->vmcb, VMCB_CR);
5897 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5899 struct vcpu_svm *svm = to_svm(vcpu);
5901 svm->vmcb->control.nested_cr3 = __sme_set(root);
5902 mark_dirty(svm->vmcb, VMCB_NPT);
5904 /* Also sync guest cr3 here in case we live migrate */
5905 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5906 mark_dirty(svm->vmcb, VMCB_CR);
5909 static int is_disabled(void)
5913 rdmsrl(MSR_VM_CR, vm_cr);
5914 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5921 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5924 * Patch in the VMMCALL instruction:
5926 hypercall[0] = 0x0f;
5927 hypercall[1] = 0x01;
5928 hypercall[2] = 0xd9;
5931 static int __init svm_check_processor_compat(void)
5936 static bool svm_cpu_has_accelerated_tpr(void)
5941 static bool svm_has_emulated_msr(int index)
5944 case MSR_IA32_MCG_EXT_CTL:
5945 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
5954 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5959 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5961 struct vcpu_svm *svm = to_svm(vcpu);
5963 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
5964 boot_cpu_has(X86_FEATURE_XSAVE) &&
5965 boot_cpu_has(X86_FEATURE_XSAVES);
5967 /* Update nrips enabled cache */
5968 svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5970 if (!kvm_vcpu_apicv_active(vcpu))
5973 guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5976 #define F feature_bit
5978 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5983 entry->ecx &= ~F(X2APIC);
5987 entry->ecx |= (1 << 2); /* Set SVM bit */
5990 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
5991 boot_cpu_has(X86_FEATURE_AMD_SSBD))
5992 entry->ebx |= F(VIRT_SSBD);
5995 entry->eax = 1; /* SVM revision 1 */
5996 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5997 ASID emulation to nested SVM */
5998 entry->ecx = 0; /* Reserved */
5999 entry->edx = 0; /* Per default do not support any
6000 additional features */
6002 /* Support next_rip if host supports it */
6003 if (boot_cpu_has(X86_FEATURE_NRIPS))
6004 entry->edx |= F(NRIPS);
6006 /* Support NPT for the guest if enabled */
6008 entry->edx |= F(NPT);
6013 static int svm_get_lpage_level(void)
6015 return PT_PDPE_LEVEL;
6018 static bool svm_rdtscp_supported(void)
6020 return boot_cpu_has(X86_FEATURE_RDTSCP);
6023 static bool svm_invpcid_supported(void)
6028 static bool svm_mpx_supported(void)
6033 static bool svm_xsaves_supported(void)
6035 return boot_cpu_has(X86_FEATURE_XSAVES);
6038 static bool svm_umip_emulated(void)
6043 static bool svm_pt_supported(void)
6048 static bool svm_has_wbinvd_exit(void)
6053 static bool svm_pku_supported(void)
6058 #define PRE_EX(exit) { .exit_code = (exit), \
6059 .stage = X86_ICPT_PRE_EXCEPT, }
6060 #define POST_EX(exit) { .exit_code = (exit), \
6061 .stage = X86_ICPT_POST_EXCEPT, }
6062 #define POST_MEM(exit) { .exit_code = (exit), \
6063 .stage = X86_ICPT_POST_MEMACCESS, }
6065 static const struct __x86_intercept {
6067 enum x86_intercept_stage stage;
6068 } x86_intercept_map[] = {
6069 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
6070 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
6071 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
6072 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
6073 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
6074 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
6075 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
6076 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
6077 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
6078 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
6079 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
6080 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
6081 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
6082 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
6083 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
6084 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
6085 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
6086 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
6087 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
6088 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
6089 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
6090 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
6091 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
6092 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
6093 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
6094 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
6095 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
6096 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
6097 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
6098 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
6099 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
6100 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
6101 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
6102 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
6103 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
6104 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
6105 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
6106 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
6107 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
6108 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
6109 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
6110 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
6111 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
6112 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
6113 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
6114 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
6115 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
6122 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6123 struct x86_instruction_info *info,
6124 enum x86_intercept_stage stage)
6126 struct vcpu_svm *svm = to_svm(vcpu);
6127 int vmexit, ret = X86EMUL_CONTINUE;
6128 struct __x86_intercept icpt_info;
6129 struct vmcb *vmcb = svm->vmcb;
6131 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6134 icpt_info = x86_intercept_map[info->intercept];
6136 if (stage != icpt_info.stage)
6139 switch (icpt_info.exit_code) {
6140 case SVM_EXIT_READ_CR0:
6141 if (info->intercept == x86_intercept_cr_read)
6142 icpt_info.exit_code += info->modrm_reg;
6144 case SVM_EXIT_WRITE_CR0: {
6145 unsigned long cr0, val;
6148 if (info->intercept == x86_intercept_cr_write)
6149 icpt_info.exit_code += info->modrm_reg;
6151 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6152 info->intercept == x86_intercept_clts)
6155 intercept = svm->nested.intercept;
6157 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6160 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6161 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
6163 if (info->intercept == x86_intercept_lmsw) {
6166 /* lmsw can't clear PE - catch this here */
6167 if (cr0 & X86_CR0_PE)
6172 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6176 case SVM_EXIT_READ_DR0:
6177 case SVM_EXIT_WRITE_DR0:
6178 icpt_info.exit_code += info->modrm_reg;
6181 if (info->intercept == x86_intercept_wrmsr)
6182 vmcb->control.exit_info_1 = 1;
6184 vmcb->control.exit_info_1 = 0;
6186 case SVM_EXIT_PAUSE:
6188 * We get this for NOP only, but pause
6189 * is rep not, check this here
6191 if (info->rep_prefix != REPE_PREFIX)
6194 case SVM_EXIT_IOIO: {
6198 if (info->intercept == x86_intercept_in ||
6199 info->intercept == x86_intercept_ins) {
6200 exit_info = ((info->src_val & 0xffff) << 16) |
6202 bytes = info->dst_bytes;
6204 exit_info = (info->dst_val & 0xffff) << 16;
6205 bytes = info->src_bytes;
6208 if (info->intercept == x86_intercept_outs ||
6209 info->intercept == x86_intercept_ins)
6210 exit_info |= SVM_IOIO_STR_MASK;
6212 if (info->rep_prefix)
6213 exit_info |= SVM_IOIO_REP_MASK;
6215 bytes = min(bytes, 4u);
6217 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6219 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6221 vmcb->control.exit_info_1 = exit_info;
6222 vmcb->control.exit_info_2 = info->next_rip;
6230 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6231 if (static_cpu_has(X86_FEATURE_NRIPS))
6232 vmcb->control.next_rip = info->next_rip;
6233 vmcb->control.exit_code = icpt_info.exit_code;
6234 vmexit = nested_svm_exit_handled(svm);
6236 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6243 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6244 enum exit_fastpath_completion *exit_fastpath)
6246 if (!is_guest_mode(vcpu) &&
6247 to_svm(vcpu)->vmcb->control.exit_code == EXIT_REASON_MSR_WRITE)
6248 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
6251 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6253 if (pause_filter_thresh)
6254 shrink_ple_window(vcpu);
6257 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6259 if (avic_handle_apic_id_update(vcpu) != 0)
6261 avic_handle_dfr_update(vcpu);
6262 avic_handle_ldr_update(vcpu);
6265 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6267 /* [63:9] are reserved. */
6268 vcpu->arch.mcg_cap &= 0x1ff;
6271 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6273 struct vcpu_svm *svm = to_svm(vcpu);
6275 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6279 if (is_guest_mode(&svm->vcpu) &&
6280 svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6281 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6282 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6283 svm->nested.exit_required = true;
6290 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6292 struct vcpu_svm *svm = to_svm(vcpu);
6295 if (is_guest_mode(vcpu)) {
6296 /* FED8h - SVM Guest */
6297 put_smstate(u64, smstate, 0x7ed8, 1);
6298 /* FEE0h - SVM Guest VMCB Physical Address */
6299 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6301 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6302 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6303 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6305 ret = nested_svm_vmexit(svm);
6312 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
6314 struct vcpu_svm *svm = to_svm(vcpu);
6315 struct vmcb *nested_vmcb;
6316 struct kvm_host_map map;
6320 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
6321 vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
6324 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
6326 nested_vmcb = map.hva;
6327 enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map);
6332 static int enable_smi_window(struct kvm_vcpu *vcpu)
6334 struct vcpu_svm *svm = to_svm(vcpu);
6336 if (!gif_set(svm)) {
6337 if (vgif_enabled(svm))
6338 set_intercept(svm, INTERCEPT_STGI);
6339 /* STGI will cause a vm exit */
6345 static int sev_flush_asids(void)
6350 * DEACTIVATE will clear the WBINVD indicator causing DF_FLUSH to fail,
6351 * so it must be guarded.
6353 down_write(&sev_deactivate_lock);
6355 wbinvd_on_all_cpus();
6356 ret = sev_guest_df_flush(&error);
6358 up_write(&sev_deactivate_lock);
6361 pr_err("SEV: DF_FLUSH failed, ret=%d, error=%#x\n", ret, error);
6366 /* Must be called with the sev_bitmap_lock held */
6367 static bool __sev_recycle_asids(void)
6371 /* Check if there are any ASIDs to reclaim before performing a flush */
6372 pos = find_next_bit(sev_reclaim_asid_bitmap,
6373 max_sev_asid, min_sev_asid - 1);
6374 if (pos >= max_sev_asid)
6377 if (sev_flush_asids())
6380 bitmap_xor(sev_asid_bitmap, sev_asid_bitmap, sev_reclaim_asid_bitmap,
6382 bitmap_zero(sev_reclaim_asid_bitmap, max_sev_asid);
6387 static int sev_asid_new(void)
6392 mutex_lock(&sev_bitmap_lock);
6395 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6398 pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6399 if (pos >= max_sev_asid) {
6400 if (retry && __sev_recycle_asids()) {
6404 mutex_unlock(&sev_bitmap_lock);
6408 __set_bit(pos, sev_asid_bitmap);
6410 mutex_unlock(&sev_bitmap_lock);
6415 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6417 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6421 if (unlikely(sev->active))
6424 asid = sev_asid_new();
6428 ret = sev_platform_init(&argp->error);
6434 INIT_LIST_HEAD(&sev->regions_list);
6439 sev_asid_free(asid);
6443 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6445 struct sev_data_activate *data;
6446 int asid = sev_get_asid(kvm);
6449 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6453 /* activate ASID on the given handle */
6454 data->handle = handle;
6456 ret = sev_guest_activate(data, error);
6462 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6471 ret = sev_issue_cmd_external_user(f.file, id, data, error);
6477 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6479 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6481 return __sev_issue_cmd(sev->fd, id, data, error);
6484 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6486 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6487 struct sev_data_launch_start *start;
6488 struct kvm_sev_launch_start params;
6489 void *dh_blob, *session_blob;
6490 int *error = &argp->error;
6493 if (!sev_guest(kvm))
6496 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6499 start = kzalloc(sizeof(*start), GFP_KERNEL_ACCOUNT);
6504 if (params.dh_uaddr) {
6505 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6506 if (IS_ERR(dh_blob)) {
6507 ret = PTR_ERR(dh_blob);
6511 start->dh_cert_address = __sme_set(__pa(dh_blob));
6512 start->dh_cert_len = params.dh_len;
6515 session_blob = NULL;
6516 if (params.session_uaddr) {
6517 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6518 if (IS_ERR(session_blob)) {
6519 ret = PTR_ERR(session_blob);
6523 start->session_address = __sme_set(__pa(session_blob));
6524 start->session_len = params.session_len;
6527 start->handle = params.handle;
6528 start->policy = params.policy;
6530 /* create memory encryption context */
6531 ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6533 goto e_free_session;
6535 /* Bind ASID to this guest */
6536 ret = sev_bind_asid(kvm, start->handle, error);
6538 goto e_free_session;
6540 /* return handle to userspace */
6541 params.handle = start->handle;
6542 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) {
6543 sev_unbind_asid(kvm, start->handle);
6545 goto e_free_session;
6548 sev->handle = start->handle;
6549 sev->fd = argp->sev_fd;
6552 kfree(session_blob);
6560 static unsigned long get_num_contig_pages(unsigned long idx,
6561 struct page **inpages, unsigned long npages)
6563 unsigned long paddr, next_paddr;
6564 unsigned long i = idx + 1, pages = 1;
6566 /* find the number of contiguous pages starting from idx */
6567 paddr = __sme_page_pa(inpages[idx]);
6568 while (i < npages) {
6569 next_paddr = __sme_page_pa(inpages[i++]);
6570 if ((paddr + PAGE_SIZE) == next_paddr) {
6581 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6583 unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i;
6584 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6585 struct kvm_sev_launch_update_data params;
6586 struct sev_data_launch_update_data *data;
6587 struct page **inpages;
6590 if (!sev_guest(kvm))
6593 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6596 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6600 vaddr = params.uaddr;
6602 vaddr_end = vaddr + size;
6604 /* Lock the user memory. */
6605 inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6612 * The LAUNCH_UPDATE command will perform in-place encryption of the
6613 * memory content (i.e it will write the same memory region with C=1).
6614 * It's possible that the cache may contain the data with C=0, i.e.,
6615 * unencrypted so invalidate it first.
6617 sev_clflush_pages(inpages, npages);
6619 for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6623 * If the user buffer is not page-aligned, calculate the offset
6626 offset = vaddr & (PAGE_SIZE - 1);
6628 /* Calculate the number of pages that can be encrypted in one go. */
6629 pages = get_num_contig_pages(i, inpages, npages);
6631 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6633 data->handle = sev->handle;
6635 data->address = __sme_page_pa(inpages[i]) + offset;
6636 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6641 next_vaddr = vaddr + len;
6645 /* content of memory is updated, mark pages dirty */
6646 for (i = 0; i < npages; i++) {
6647 set_page_dirty_lock(inpages[i]);
6648 mark_page_accessed(inpages[i]);
6650 /* unlock the user pages */
6651 sev_unpin_memory(kvm, inpages, npages);
6657 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6659 void __user *measure = (void __user *)(uintptr_t)argp->data;
6660 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6661 struct sev_data_launch_measure *data;
6662 struct kvm_sev_launch_measure params;
6663 void __user *p = NULL;
6667 if (!sev_guest(kvm))
6670 if (copy_from_user(¶ms, measure, sizeof(params)))
6673 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6677 /* User wants to query the blob length */
6681 p = (void __user *)(uintptr_t)params.uaddr;
6683 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6689 blob = kmalloc(params.len, GFP_KERNEL);
6693 data->address = __psp_pa(blob);
6694 data->len = params.len;
6698 data->handle = sev->handle;
6699 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6702 * If we query the session length, FW responded with expected data.
6711 if (copy_to_user(p, blob, params.len))
6716 params.len = data->len;
6717 if (copy_to_user(measure, ¶ms, sizeof(params)))
6726 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6728 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6729 struct sev_data_launch_finish *data;
6732 if (!sev_guest(kvm))
6735 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6739 data->handle = sev->handle;
6740 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6746 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6748 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6749 struct kvm_sev_guest_status params;
6750 struct sev_data_guest_status *data;
6753 if (!sev_guest(kvm))
6756 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6760 data->handle = sev->handle;
6761 ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6765 params.policy = data->policy;
6766 params.state = data->state;
6767 params.handle = data->handle;
6769 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params)))
6776 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6777 unsigned long dst, int size,
6778 int *error, bool enc)
6780 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6781 struct sev_data_dbg *data;
6784 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6788 data->handle = sev->handle;
6789 data->dst_addr = dst;
6790 data->src_addr = src;
6793 ret = sev_issue_cmd(kvm,
6794 enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6800 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6801 unsigned long dst_paddr, int sz, int *err)
6806 * Its safe to read more than we are asked, caller should ensure that
6807 * destination has enough space.
6809 src_paddr = round_down(src_paddr, 16);
6810 offset = src_paddr & 15;
6811 sz = round_up(sz + offset, 16);
6813 return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6816 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6817 unsigned long __user dst_uaddr,
6818 unsigned long dst_paddr,
6821 struct page *tpage = NULL;
6824 /* if inputs are not 16-byte then use intermediate buffer */
6825 if (!IS_ALIGNED(dst_paddr, 16) ||
6826 !IS_ALIGNED(paddr, 16) ||
6827 !IS_ALIGNED(size, 16)) {
6828 tpage = (void *)alloc_page(GFP_KERNEL);
6832 dst_paddr = __sme_page_pa(tpage);
6835 ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6840 offset = paddr & 15;
6841 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6842 page_address(tpage) + offset, size))
6853 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6854 unsigned long __user vaddr,
6855 unsigned long dst_paddr,
6856 unsigned long __user dst_vaddr,
6857 int size, int *error)
6859 struct page *src_tpage = NULL;
6860 struct page *dst_tpage = NULL;
6861 int ret, len = size;
6863 /* If source buffer is not aligned then use an intermediate buffer */
6864 if (!IS_ALIGNED(vaddr, 16)) {
6865 src_tpage = alloc_page(GFP_KERNEL);
6869 if (copy_from_user(page_address(src_tpage),
6870 (void __user *)(uintptr_t)vaddr, size)) {
6871 __free_page(src_tpage);
6875 paddr = __sme_page_pa(src_tpage);
6879 * If destination buffer or length is not aligned then do read-modify-write:
6880 * - decrypt destination in an intermediate buffer
6881 * - copy the source buffer in an intermediate buffer
6882 * - use the intermediate buffer as source buffer
6884 if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6887 dst_tpage = alloc_page(GFP_KERNEL);
6893 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6894 __sme_page_pa(dst_tpage), size, error);
6899 * If source is kernel buffer then use memcpy() otherwise
6902 dst_offset = dst_paddr & 15;
6905 memcpy(page_address(dst_tpage) + dst_offset,
6906 page_address(src_tpage), size);
6908 if (copy_from_user(page_address(dst_tpage) + dst_offset,
6909 (void __user *)(uintptr_t)vaddr, size)) {
6915 paddr = __sme_page_pa(dst_tpage);
6916 dst_paddr = round_down(dst_paddr, 16);
6917 len = round_up(size, 16);
6920 ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6924 __free_page(src_tpage);
6926 __free_page(dst_tpage);
6930 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6932 unsigned long vaddr, vaddr_end, next_vaddr;
6933 unsigned long dst_vaddr;
6934 struct page **src_p, **dst_p;
6935 struct kvm_sev_dbg debug;
6940 if (!sev_guest(kvm))
6943 if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6946 if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr)
6948 if (!debug.dst_uaddr)
6951 vaddr = debug.src_uaddr;
6953 vaddr_end = vaddr + size;
6954 dst_vaddr = debug.dst_uaddr;
6956 for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6957 int len, s_off, d_off;
6959 /* lock userspace source and destination page */
6960 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6964 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6966 sev_unpin_memory(kvm, src_p, n);
6971 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6972 * memory content (i.e it will write the same memory region with C=1).
6973 * It's possible that the cache may contain the data with C=0, i.e.,
6974 * unencrypted so invalidate it first.
6976 sev_clflush_pages(src_p, 1);
6977 sev_clflush_pages(dst_p, 1);
6980 * Since user buffer may not be page aligned, calculate the
6981 * offset within the page.
6983 s_off = vaddr & ~PAGE_MASK;
6984 d_off = dst_vaddr & ~PAGE_MASK;
6985 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6988 ret = __sev_dbg_decrypt_user(kvm,
6989 __sme_page_pa(src_p[0]) + s_off,
6991 __sme_page_pa(dst_p[0]) + d_off,
6994 ret = __sev_dbg_encrypt_user(kvm,
6995 __sme_page_pa(src_p[0]) + s_off,
6997 __sme_page_pa(dst_p[0]) + d_off,
7001 sev_unpin_memory(kvm, src_p, n);
7002 sev_unpin_memory(kvm, dst_p, n);
7007 next_vaddr = vaddr + len;
7008 dst_vaddr = dst_vaddr + len;
7015 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
7017 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7018 struct sev_data_launch_secret *data;
7019 struct kvm_sev_launch_secret params;
7020 struct page **pages;
7025 if (!sev_guest(kvm))
7028 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
7031 pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
7036 * The secret must be copied into contiguous memory region, lets verify
7037 * that userspace memory pages are contiguous before we issue command.
7039 if (get_num_contig_pages(0, pages, n) != n) {
7041 goto e_unpin_memory;
7045 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
7047 goto e_unpin_memory;
7049 offset = params.guest_uaddr & (PAGE_SIZE - 1);
7050 data->guest_address = __sme_page_pa(pages[0]) + offset;
7051 data->guest_len = params.guest_len;
7053 blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
7055 ret = PTR_ERR(blob);
7059 data->trans_address = __psp_pa(blob);
7060 data->trans_len = params.trans_len;
7062 hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
7067 data->hdr_address = __psp_pa(hdr);
7068 data->hdr_len = params.hdr_len;
7070 data->handle = sev->handle;
7071 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
7080 sev_unpin_memory(kvm, pages, n);
7084 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
7086 struct kvm_sev_cmd sev_cmd;
7089 if (!svm_sev_enabled())
7092 if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
7095 mutex_lock(&kvm->lock);
7097 switch (sev_cmd.id) {
7099 r = sev_guest_init(kvm, &sev_cmd);
7101 case KVM_SEV_LAUNCH_START:
7102 r = sev_launch_start(kvm, &sev_cmd);
7104 case KVM_SEV_LAUNCH_UPDATE_DATA:
7105 r = sev_launch_update_data(kvm, &sev_cmd);
7107 case KVM_SEV_LAUNCH_MEASURE:
7108 r = sev_launch_measure(kvm, &sev_cmd);
7110 case KVM_SEV_LAUNCH_FINISH:
7111 r = sev_launch_finish(kvm, &sev_cmd);
7113 case KVM_SEV_GUEST_STATUS:
7114 r = sev_guest_status(kvm, &sev_cmd);
7116 case KVM_SEV_DBG_DECRYPT:
7117 r = sev_dbg_crypt(kvm, &sev_cmd, true);
7119 case KVM_SEV_DBG_ENCRYPT:
7120 r = sev_dbg_crypt(kvm, &sev_cmd, false);
7122 case KVM_SEV_LAUNCH_SECRET:
7123 r = sev_launch_secret(kvm, &sev_cmd);
7130 if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
7134 mutex_unlock(&kvm->lock);
7138 static int svm_register_enc_region(struct kvm *kvm,
7139 struct kvm_enc_region *range)
7141 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7142 struct enc_region *region;
7145 if (!sev_guest(kvm))
7148 if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7151 region = kzalloc(sizeof(*region), GFP_KERNEL_ACCOUNT);
7155 region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1);
7156 if (!region->pages) {
7162 * The guest may change the memory encryption attribute from C=0 -> C=1
7163 * or vice versa for this memory range. Lets make sure caches are
7164 * flushed to ensure that guest data gets written into memory with
7167 sev_clflush_pages(region->pages, region->npages);
7169 region->uaddr = range->addr;
7170 region->size = range->size;
7172 mutex_lock(&kvm->lock);
7173 list_add_tail(®ion->list, &sev->regions_list);
7174 mutex_unlock(&kvm->lock);
7183 static struct enc_region *
7184 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7186 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7187 struct list_head *head = &sev->regions_list;
7188 struct enc_region *i;
7190 list_for_each_entry(i, head, list) {
7191 if (i->uaddr == range->addr &&
7192 i->size == range->size)
7200 static int svm_unregister_enc_region(struct kvm *kvm,
7201 struct kvm_enc_region *range)
7203 struct enc_region *region;
7206 mutex_lock(&kvm->lock);
7208 if (!sev_guest(kvm)) {
7213 region = find_enc_region(kvm, range);
7219 __unregister_enc_region_locked(kvm, region);
7221 mutex_unlock(&kvm->lock);
7225 mutex_unlock(&kvm->lock);
7229 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7231 unsigned long cr4 = kvm_read_cr4(vcpu);
7232 bool smep = cr4 & X86_CR4_SMEP;
7233 bool smap = cr4 & X86_CR4_SMAP;
7234 bool is_user = svm_get_cpl(vcpu) == 3;
7237 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
7240 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
7241 * possible that CPU microcode implementing DecodeAssist will fail
7242 * to read bytes of instruction which caused #NPF. In this case,
7243 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
7244 * return 0 instead of the correct guest instruction bytes.
7246 * This happens because CPU microcode reading instruction bytes
7247 * uses a special opcode which attempts to read data using CPL=0
7248 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
7249 * fault, it gives up and returns no instruction bytes.
7252 * We reach here in case CPU supports DecodeAssist, raised #NPF and
7253 * returned 0 in GuestIntrBytes field of the VMCB.
7254 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
7255 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
7256 * in case vCPU CPL==3 (Because otherwise guest would have triggered
7257 * a SMEP fault instead of #NPF).
7258 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
7259 * As most guests enable SMAP if they have also enabled SMEP, use above
7260 * logic in order to attempt minimize false-positive of detecting errata
7261 * while still preserving all cases semantic correctness.
7264 * To determine what instruction the guest was executing, the hypervisor
7265 * will have to decode the instruction at the instruction pointer.
7267 * In non SEV guest, hypervisor will be able to read the guest
7268 * memory to decode the instruction pointer when insn_len is zero
7269 * so we return true to indicate that decoding is possible.
7271 * But in the SEV guest, the guest memory is encrypted with the
7272 * guest specific key and hypervisor will not be able to decode the
7273 * instruction pointer so we will not able to workaround it. Lets
7274 * print the error and request to kill the guest.
7276 if (smap && (!smep || is_user)) {
7277 if (!sev_guest(vcpu->kvm))
7280 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
7281 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7287 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7289 struct vcpu_svm *svm = to_svm(vcpu);
7292 * TODO: Last condition latch INIT signals on vCPU when
7293 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
7294 * To properly emulate the INIT intercept, SVM should implement
7295 * kvm_x86_ops->check_nested_events() and call nested_svm_vmexit()
7296 * there if an INIT signal is pending.
7298 return !gif_set(svm) ||
7299 (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
7302 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7303 .cpu_has_kvm_support = has_svm,
7304 .disabled_by_bios = is_disabled,
7305 .hardware_setup = svm_hardware_setup,
7306 .hardware_unsetup = svm_hardware_unsetup,
7307 .check_processor_compatibility = svm_check_processor_compat,
7308 .hardware_enable = svm_hardware_enable,
7309 .hardware_disable = svm_hardware_disable,
7310 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7311 .has_emulated_msr = svm_has_emulated_msr,
7313 .vcpu_create = svm_create_vcpu,
7314 .vcpu_free = svm_free_vcpu,
7315 .vcpu_reset = svm_vcpu_reset,
7317 .vm_alloc = svm_vm_alloc,
7318 .vm_free = svm_vm_free,
7319 .vm_init = svm_vm_init,
7320 .vm_destroy = svm_vm_destroy,
7322 .prepare_guest_switch = svm_prepare_guest_switch,
7323 .vcpu_load = svm_vcpu_load,
7324 .vcpu_put = svm_vcpu_put,
7325 .vcpu_blocking = svm_vcpu_blocking,
7326 .vcpu_unblocking = svm_vcpu_unblocking,
7328 .update_bp_intercept = update_bp_intercept,
7329 .get_msr_feature = svm_get_msr_feature,
7330 .get_msr = svm_get_msr,
7331 .set_msr = svm_set_msr,
7332 .get_segment_base = svm_get_segment_base,
7333 .get_segment = svm_get_segment,
7334 .set_segment = svm_set_segment,
7335 .get_cpl = svm_get_cpl,
7336 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7337 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7338 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7339 .set_cr0 = svm_set_cr0,
7340 .set_cr3 = svm_set_cr3,
7341 .set_cr4 = svm_set_cr4,
7342 .set_efer = svm_set_efer,
7343 .get_idt = svm_get_idt,
7344 .set_idt = svm_set_idt,
7345 .get_gdt = svm_get_gdt,
7346 .set_gdt = svm_set_gdt,
7347 .get_dr6 = svm_get_dr6,
7348 .set_dr6 = svm_set_dr6,
7349 .set_dr7 = svm_set_dr7,
7350 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7351 .cache_reg = svm_cache_reg,
7352 .get_rflags = svm_get_rflags,
7353 .set_rflags = svm_set_rflags,
7355 .tlb_flush = svm_flush_tlb,
7356 .tlb_flush_gva = svm_flush_tlb_gva,
7358 .run = svm_vcpu_run,
7359 .handle_exit = handle_exit,
7360 .skip_emulated_instruction = skip_emulated_instruction,
7361 .set_interrupt_shadow = svm_set_interrupt_shadow,
7362 .get_interrupt_shadow = svm_get_interrupt_shadow,
7363 .patch_hypercall = svm_patch_hypercall,
7364 .set_irq = svm_set_irq,
7365 .set_nmi = svm_inject_nmi,
7366 .queue_exception = svm_queue_exception,
7367 .cancel_injection = svm_cancel_injection,
7368 .interrupt_allowed = svm_interrupt_allowed,
7369 .nmi_allowed = svm_nmi_allowed,
7370 .get_nmi_mask = svm_get_nmi_mask,
7371 .set_nmi_mask = svm_set_nmi_mask,
7372 .enable_nmi_window = enable_nmi_window,
7373 .enable_irq_window = enable_irq_window,
7374 .update_cr8_intercept = update_cr8_intercept,
7375 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7376 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7377 .load_eoi_exitmap = svm_load_eoi_exitmap,
7378 .hwapic_irr_update = svm_hwapic_irr_update,
7379 .hwapic_isr_update = svm_hwapic_isr_update,
7380 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7381 .apicv_post_state_restore = avic_post_state_restore,
7383 .set_tss_addr = svm_set_tss_addr,
7384 .set_identity_map_addr = svm_set_identity_map_addr,
7385 .get_tdp_level = get_npt_level,
7386 .get_mt_mask = svm_get_mt_mask,
7388 .get_exit_info = svm_get_exit_info,
7390 .get_lpage_level = svm_get_lpage_level,
7392 .cpuid_update = svm_cpuid_update,
7394 .rdtscp_supported = svm_rdtscp_supported,
7395 .invpcid_supported = svm_invpcid_supported,
7396 .mpx_supported = svm_mpx_supported,
7397 .xsaves_supported = svm_xsaves_supported,
7398 .umip_emulated = svm_umip_emulated,
7399 .pt_supported = svm_pt_supported,
7400 .pku_supported = svm_pku_supported,
7402 .set_supported_cpuid = svm_set_supported_cpuid,
7404 .has_wbinvd_exit = svm_has_wbinvd_exit,
7406 .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7407 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7409 .set_tdp_cr3 = set_tdp_cr3,
7411 .check_intercept = svm_check_intercept,
7412 .handle_exit_irqoff = svm_handle_exit_irqoff,
7414 .request_immediate_exit = __kvm_request_immediate_exit,
7416 .sched_in = svm_sched_in,
7418 .pmu_ops = &amd_pmu_ops,
7419 .deliver_posted_interrupt = svm_deliver_avic_intr,
7420 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
7421 .update_pi_irte = svm_update_pi_irte,
7422 .setup_mce = svm_setup_mce,
7424 .smi_allowed = svm_smi_allowed,
7425 .pre_enter_smm = svm_pre_enter_smm,
7426 .pre_leave_smm = svm_pre_leave_smm,
7427 .enable_smi_window = enable_smi_window,
7429 .mem_enc_op = svm_mem_enc_op,
7430 .mem_enc_reg_region = svm_register_enc_region,
7431 .mem_enc_unreg_region = svm_unregister_enc_region,
7433 .nested_enable_evmcs = NULL,
7434 .nested_get_evmcs_version = NULL,
7436 .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
7438 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
7441 static int __init svm_init(void)
7443 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7444 __alignof__(struct vcpu_svm), THIS_MODULE);
7447 static void __exit svm_exit(void)
7452 module_init(svm_init)
7453 module_exit(svm_exit)