2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
32 #include <asm/tlbflush.h>
34 #include <asm/kvm_para.h>
36 #include <asm/virtext.h>
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_TSC_RATE (1 << 4)
55 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
56 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
57 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
58 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
60 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
61 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
62 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
64 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
66 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
67 #define TSC_RATIO_MIN 0x0000000000000001ULL
68 #define TSC_RATIO_MAX 0x000000ffffffffffULL
70 static bool erratum_383_found __read_mostly;
72 static const u32 host_save_user_msrs[] = {
74 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
77 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
80 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
90 /* These are the merged vectors */
93 /* gpa pointers to the real vectors */
97 /* A VMEXIT is required but not yet emulated */
100 /* cache for intercepts of the guest */
103 u32 intercept_exceptions;
106 /* Nested Paging related state */
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
114 * Set osvw_len to higher value when updated Revision Guides
115 * are published and we know what the new status bits are
117 static uint64_t osvw_len = 4, osvw_status;
120 struct kvm_vcpu vcpu;
122 unsigned long vmcb_pa;
123 struct svm_cpu_data *svm_data;
124 uint64_t asid_generation;
125 uint64_t sysenter_esp;
126 uint64_t sysenter_eip;
130 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
142 struct nested_state nested;
146 unsigned int3_injected;
147 unsigned long int3_rip;
153 static DEFINE_PER_CPU(u64, current_tsc_ratio);
154 #define TSC_RATIO_DEFAULT 0x0100000000ULL
156 #define MSR_INVALID 0xffffffffU
158 static struct svm_direct_access_msrs {
159 u32 index; /* Index of the MSR */
160 bool always; /* True if intercept is always on */
161 } direct_access_msrs[] = {
162 { .index = MSR_STAR, .always = true },
163 { .index = MSR_IA32_SYSENTER_CS, .always = true },
165 { .index = MSR_GS_BASE, .always = true },
166 { .index = MSR_FS_BASE, .always = true },
167 { .index = MSR_KERNEL_GS_BASE, .always = true },
168 { .index = MSR_LSTAR, .always = true },
169 { .index = MSR_CSTAR, .always = true },
170 { .index = MSR_SYSCALL_MASK, .always = true },
172 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
173 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
174 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
175 { .index = MSR_IA32_LASTINTTOIP, .always = false },
176 { .index = MSR_INVALID, .always = false },
179 /* enable NPT for AMD64 and X86 with PAE */
180 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
181 static bool npt_enabled = true;
183 static bool npt_enabled;
186 /* allow nested paging (virtualized MMU) for all guests */
187 static int npt = true;
188 module_param(npt, int, S_IRUGO);
190 /* allow nested virtualization in KVM/SVM */
191 static int nested = true;
192 module_param(nested, int, S_IRUGO);
194 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
195 static void svm_complete_interrupts(struct vcpu_svm *svm);
197 static int nested_svm_exit_handled(struct vcpu_svm *svm);
198 static int nested_svm_intercept(struct vcpu_svm *svm);
199 static int nested_svm_vmexit(struct vcpu_svm *svm);
200 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
201 bool has_error_code, u32 error_code);
202 static u64 __scale_tsc(u64 ratio, u64 tsc);
205 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
206 pause filter count */
207 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
208 VMCB_ASID, /* ASID */
209 VMCB_INTR, /* int_ctl, int_vector */
210 VMCB_NPT, /* npt_en, nCR3, gPAT */
211 VMCB_CR, /* CR0, CR3, CR4, EFER */
212 VMCB_DR, /* DR6, DR7 */
213 VMCB_DT, /* GDT, IDT */
214 VMCB_SEG, /* CS, DS, SS, ES, CPL */
215 VMCB_CR2, /* CR2 only */
216 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
220 /* TPR and CR2 are always written before VMRUN */
221 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
223 static inline void mark_all_dirty(struct vmcb *vmcb)
225 vmcb->control.clean = 0;
228 static inline void mark_all_clean(struct vmcb *vmcb)
230 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
231 & ~VMCB_ALWAYS_DIRTY_MASK;
234 static inline void mark_dirty(struct vmcb *vmcb, int bit)
236 vmcb->control.clean &= ~(1 << bit);
239 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
241 return container_of(vcpu, struct vcpu_svm, vcpu);
244 static void recalc_intercepts(struct vcpu_svm *svm)
246 struct vmcb_control_area *c, *h;
247 struct nested_state *g;
249 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
251 if (!is_guest_mode(&svm->vcpu))
254 c = &svm->vmcb->control;
255 h = &svm->nested.hsave->control;
258 c->intercept_cr = h->intercept_cr | g->intercept_cr;
259 c->intercept_dr = h->intercept_dr | g->intercept_dr;
260 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
261 c->intercept = h->intercept | g->intercept;
264 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
266 if (is_guest_mode(&svm->vcpu))
267 return svm->nested.hsave;
272 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
274 struct vmcb *vmcb = get_host_vmcb(svm);
276 vmcb->control.intercept_cr |= (1U << bit);
278 recalc_intercepts(svm);
281 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
283 struct vmcb *vmcb = get_host_vmcb(svm);
285 vmcb->control.intercept_cr &= ~(1U << bit);
287 recalc_intercepts(svm);
290 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
292 struct vmcb *vmcb = get_host_vmcb(svm);
294 return vmcb->control.intercept_cr & (1U << bit);
297 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
299 struct vmcb *vmcb = get_host_vmcb(svm);
301 vmcb->control.intercept_dr |= (1U << bit);
303 recalc_intercepts(svm);
306 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
308 struct vmcb *vmcb = get_host_vmcb(svm);
310 vmcb->control.intercept_dr &= ~(1U << bit);
312 recalc_intercepts(svm);
315 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
317 struct vmcb *vmcb = get_host_vmcb(svm);
319 vmcb->control.intercept_exceptions |= (1U << bit);
321 recalc_intercepts(svm);
324 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
326 struct vmcb *vmcb = get_host_vmcb(svm);
328 vmcb->control.intercept_exceptions &= ~(1U << bit);
330 recalc_intercepts(svm);
333 static inline void set_intercept(struct vcpu_svm *svm, int bit)
335 struct vmcb *vmcb = get_host_vmcb(svm);
337 vmcb->control.intercept |= (1ULL << bit);
339 recalc_intercepts(svm);
342 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
344 struct vmcb *vmcb = get_host_vmcb(svm);
346 vmcb->control.intercept &= ~(1ULL << bit);
348 recalc_intercepts(svm);
351 static inline void enable_gif(struct vcpu_svm *svm)
353 svm->vcpu.arch.hflags |= HF_GIF_MASK;
356 static inline void disable_gif(struct vcpu_svm *svm)
358 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
361 static inline bool gif_set(struct vcpu_svm *svm)
363 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
366 static unsigned long iopm_base;
368 struct kvm_ldttss_desc {
371 unsigned base1:8, type:5, dpl:2, p:1;
372 unsigned limit1:4, zero0:3, g:1, base2:8;
375 } __attribute__((packed));
377 struct svm_cpu_data {
383 struct kvm_ldttss_desc *tss_desc;
385 struct page *save_area;
388 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
390 struct svm_init_data {
395 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
397 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
398 #define MSRS_RANGE_SIZE 2048
399 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
401 static u32 svm_msrpm_offset(u32 msr)
406 for (i = 0; i < NUM_MSR_MAPS; i++) {
407 if (msr < msrpm_ranges[i] ||
408 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
411 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
412 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
414 /* Now we have the u8 offset - but need the u32 offset */
418 /* MSR not in any range */
422 #define MAX_INST_SIZE 15
424 static inline void clgi(void)
426 asm volatile (__ex(SVM_CLGI));
429 static inline void stgi(void)
431 asm volatile (__ex(SVM_STGI));
434 static inline void invlpga(unsigned long addr, u32 asid)
436 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
439 static int get_npt_level(void)
442 return PT64_ROOT_LEVEL;
444 return PT32E_ROOT_LEVEL;
448 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
450 vcpu->arch.efer = efer;
451 if (!npt_enabled && !(efer & EFER_LMA))
454 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
455 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
458 static int is_external_interrupt(u32 info)
460 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
461 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
464 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
466 struct vcpu_svm *svm = to_svm(vcpu);
469 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
470 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
474 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
476 struct vcpu_svm *svm = to_svm(vcpu);
479 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
481 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
485 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
487 struct vcpu_svm *svm = to_svm(vcpu);
489 if (svm->vmcb->control.next_rip != 0)
490 svm->next_rip = svm->vmcb->control.next_rip;
492 if (!svm->next_rip) {
493 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
495 printk(KERN_DEBUG "%s: NOP\n", __func__);
498 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
499 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
500 __func__, kvm_rip_read(vcpu), svm->next_rip);
502 kvm_rip_write(vcpu, svm->next_rip);
503 svm_set_interrupt_shadow(vcpu, 0);
506 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
507 bool has_error_code, u32 error_code,
510 struct vcpu_svm *svm = to_svm(vcpu);
513 * If we are within a nested VM we'd better #VMEXIT and let the guest
514 * handle the exception
517 nested_svm_check_exception(svm, nr, has_error_code, error_code))
520 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
521 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
524 * For guest debugging where we have to reinject #BP if some
525 * INT3 is guest-owned:
526 * Emulate nRIP by moving RIP forward. Will fail if injection
527 * raises a fault that is not intercepted. Still better than
528 * failing in all cases.
530 skip_emulated_instruction(&svm->vcpu);
531 rip = kvm_rip_read(&svm->vcpu);
532 svm->int3_rip = rip + svm->vmcb->save.cs.base;
533 svm->int3_injected = rip - old_rip;
536 svm->vmcb->control.event_inj = nr
538 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
539 | SVM_EVTINJ_TYPE_EXEPT;
540 svm->vmcb->control.event_inj_err = error_code;
543 static void svm_init_erratum_383(void)
549 if (!cpu_has_amd_erratum(amd_erratum_383))
552 /* Use _safe variants to not break nested virtualization */
553 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
559 low = lower_32_bits(val);
560 high = upper_32_bits(val);
562 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
564 erratum_383_found = true;
567 static void svm_init_osvw(struct kvm_vcpu *vcpu)
570 * Guests should see errata 400 and 415 as fixed (assuming that
571 * HLT and IO instructions are intercepted).
573 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
574 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
577 * By increasing VCPU's osvw.length to 3 we are telling the guest that
578 * all osvw.status bits inside that length, including bit 0 (which is
579 * reserved for erratum 298), are valid. However, if host processor's
580 * osvw_len is 0 then osvw_status[0] carries no information. We need to
581 * be conservative here and therefore we tell the guest that erratum 298
582 * is present (because we really don't know).
584 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
585 vcpu->arch.osvw.status |= 1;
588 static int has_svm(void)
592 if (!cpu_has_svm(&msg)) {
593 printk(KERN_INFO "has_svm: %s\n", msg);
600 static void svm_hardware_disable(void *garbage)
602 /* Make sure we clean up behind us */
603 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
604 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
609 static int svm_hardware_enable(void *garbage)
612 struct svm_cpu_data *sd;
614 struct desc_ptr gdt_descr;
615 struct desc_struct *gdt;
616 int me = raw_smp_processor_id();
618 rdmsrl(MSR_EFER, efer);
619 if (efer & EFER_SVME)
623 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
627 sd = per_cpu(svm_data, me);
630 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
635 sd->asid_generation = 1;
636 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
637 sd->next_asid = sd->max_asid + 1;
639 native_store_gdt(&gdt_descr);
640 gdt = (struct desc_struct *)gdt_descr.address;
641 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
643 wrmsrl(MSR_EFER, efer | EFER_SVME);
645 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
647 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
648 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
649 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
656 * Note that it is possible to have a system with mixed processor
657 * revisions and therefore different OSVW bits. If bits are not the same
658 * on different processors then choose the worst case (i.e. if erratum
659 * is present on one processor and not on another then assume that the
660 * erratum is present everywhere).
662 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
663 uint64_t len, status = 0;
666 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
668 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
672 osvw_status = osvw_len = 0;
676 osvw_status |= status;
677 osvw_status &= (1ULL << osvw_len) - 1;
680 osvw_status = osvw_len = 0;
682 svm_init_erratum_383();
687 static void svm_cpu_uninit(int cpu)
689 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
694 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
695 __free_page(sd->save_area);
699 static int svm_cpu_init(int cpu)
701 struct svm_cpu_data *sd;
704 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
708 sd->save_area = alloc_page(GFP_KERNEL);
713 per_cpu(svm_data, cpu) = sd;
723 static bool valid_msr_intercept(u32 index)
727 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
728 if (direct_access_msrs[i].index == index)
734 static void set_msr_interception(u32 *msrpm, unsigned msr,
737 u8 bit_read, bit_write;
742 * If this warning triggers extend the direct_access_msrs list at the
743 * beginning of the file
745 WARN_ON(!valid_msr_intercept(msr));
747 offset = svm_msrpm_offset(msr);
748 bit_read = 2 * (msr & 0x0f);
749 bit_write = 2 * (msr & 0x0f) + 1;
752 BUG_ON(offset == MSR_INVALID);
754 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
755 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
760 static void svm_vcpu_init_msrpm(u32 *msrpm)
764 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
766 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
767 if (!direct_access_msrs[i].always)
770 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
774 static void add_msr_offset(u32 offset)
778 for (i = 0; i < MSRPM_OFFSETS; ++i) {
780 /* Offset already in list? */
781 if (msrpm_offsets[i] == offset)
784 /* Slot used by another offset? */
785 if (msrpm_offsets[i] != MSR_INVALID)
788 /* Add offset to list */
789 msrpm_offsets[i] = offset;
795 * If this BUG triggers the msrpm_offsets table has an overflow. Just
796 * increase MSRPM_OFFSETS in this case.
801 static void init_msrpm_offsets(void)
805 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
807 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
810 offset = svm_msrpm_offset(direct_access_msrs[i].index);
811 BUG_ON(offset == MSR_INVALID);
813 add_msr_offset(offset);
817 static void svm_enable_lbrv(struct vcpu_svm *svm)
819 u32 *msrpm = svm->msrpm;
821 svm->vmcb->control.lbr_ctl = 1;
822 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
823 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
824 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
825 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
828 static void svm_disable_lbrv(struct vcpu_svm *svm)
830 u32 *msrpm = svm->msrpm;
832 svm->vmcb->control.lbr_ctl = 0;
833 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
834 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
835 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
836 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
839 static __init int svm_hardware_setup(void)
842 struct page *iopm_pages;
846 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
851 iopm_va = page_address(iopm_pages);
852 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
853 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
855 init_msrpm_offsets();
857 if (boot_cpu_has(X86_FEATURE_NX))
858 kvm_enable_efer_bits(EFER_NX);
860 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
861 kvm_enable_efer_bits(EFER_FFXSR);
863 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
866 kvm_has_tsc_control = true;
869 * Make sure the user can only configure tsc_khz values that
870 * fit into a signed integer.
871 * A min value is not calculated needed because it will always
872 * be 1 on all machines and a value of 0 is used to disable
873 * tsc-scaling for the vcpu.
875 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
877 kvm_max_guest_tsc_khz = max;
881 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
882 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
885 for_each_possible_cpu(cpu) {
886 r = svm_cpu_init(cpu);
891 if (!boot_cpu_has(X86_FEATURE_NPT))
894 if (npt_enabled && !npt) {
895 printk(KERN_INFO "kvm: Nested Paging disabled\n");
900 printk(KERN_INFO "kvm: Nested Paging enabled\n");
908 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
913 static __exit void svm_hardware_unsetup(void)
917 for_each_possible_cpu(cpu)
920 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
924 static void init_seg(struct vmcb_seg *seg)
927 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
928 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
933 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
936 seg->attrib = SVM_SELECTOR_P_MASK | type;
941 static u64 __scale_tsc(u64 ratio, u64 tsc)
943 u64 mult, frac, _tsc;
946 frac = ratio & ((1ULL << 32) - 1);
950 _tsc += (tsc >> 32) * frac;
951 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
956 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
958 struct vcpu_svm *svm = to_svm(vcpu);
961 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
962 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
967 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
969 struct vcpu_svm *svm = to_svm(vcpu);
973 /* TSC scaling supported? */
974 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR))
977 /* TSC-Scaling disabled or guest TSC same frequency as host TSC? */
978 if (user_tsc_khz == 0) {
979 vcpu->arch.virtual_tsc_khz = 0;
980 svm->tsc_ratio = TSC_RATIO_DEFAULT;
986 /* TSC scaling required - calculate ratio */
988 do_div(ratio, tsc_khz);
990 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
991 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
995 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
996 svm->tsc_ratio = ratio;
999 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1001 struct vcpu_svm *svm = to_svm(vcpu);
1002 u64 g_tsc_offset = 0;
1004 if (is_guest_mode(vcpu)) {
1005 g_tsc_offset = svm->vmcb->control.tsc_offset -
1006 svm->nested.hsave->control.tsc_offset;
1007 svm->nested.hsave->control.tsc_offset = offset;
1010 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1012 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1015 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1017 struct vcpu_svm *svm = to_svm(vcpu);
1019 svm->vmcb->control.tsc_offset += adjustment;
1020 if (is_guest_mode(vcpu))
1021 svm->nested.hsave->control.tsc_offset += adjustment;
1022 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1025 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1029 tsc = svm_scale_tsc(vcpu, native_read_tsc());
1031 return target_tsc - tsc;
1034 static void init_vmcb(struct vcpu_svm *svm)
1036 struct vmcb_control_area *control = &svm->vmcb->control;
1037 struct vmcb_save_area *save = &svm->vmcb->save;
1039 svm->vcpu.fpu_active = 1;
1040 svm->vcpu.arch.hflags = 0;
1042 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1043 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1044 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1045 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1046 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1047 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1048 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1050 set_dr_intercept(svm, INTERCEPT_DR0_READ);
1051 set_dr_intercept(svm, INTERCEPT_DR1_READ);
1052 set_dr_intercept(svm, INTERCEPT_DR2_READ);
1053 set_dr_intercept(svm, INTERCEPT_DR3_READ);
1054 set_dr_intercept(svm, INTERCEPT_DR4_READ);
1055 set_dr_intercept(svm, INTERCEPT_DR5_READ);
1056 set_dr_intercept(svm, INTERCEPT_DR6_READ);
1057 set_dr_intercept(svm, INTERCEPT_DR7_READ);
1059 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1060 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1061 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1062 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1063 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1064 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1065 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1066 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1068 set_exception_intercept(svm, PF_VECTOR);
1069 set_exception_intercept(svm, UD_VECTOR);
1070 set_exception_intercept(svm, MC_VECTOR);
1072 set_intercept(svm, INTERCEPT_INTR);
1073 set_intercept(svm, INTERCEPT_NMI);
1074 set_intercept(svm, INTERCEPT_SMI);
1075 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1076 set_intercept(svm, INTERCEPT_RDPMC);
1077 set_intercept(svm, INTERCEPT_CPUID);
1078 set_intercept(svm, INTERCEPT_INVD);
1079 set_intercept(svm, INTERCEPT_HLT);
1080 set_intercept(svm, INTERCEPT_INVLPG);
1081 set_intercept(svm, INTERCEPT_INVLPGA);
1082 set_intercept(svm, INTERCEPT_IOIO_PROT);
1083 set_intercept(svm, INTERCEPT_MSR_PROT);
1084 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1085 set_intercept(svm, INTERCEPT_SHUTDOWN);
1086 set_intercept(svm, INTERCEPT_VMRUN);
1087 set_intercept(svm, INTERCEPT_VMMCALL);
1088 set_intercept(svm, INTERCEPT_VMLOAD);
1089 set_intercept(svm, INTERCEPT_VMSAVE);
1090 set_intercept(svm, INTERCEPT_STGI);
1091 set_intercept(svm, INTERCEPT_CLGI);
1092 set_intercept(svm, INTERCEPT_SKINIT);
1093 set_intercept(svm, INTERCEPT_WBINVD);
1094 set_intercept(svm, INTERCEPT_MONITOR);
1095 set_intercept(svm, INTERCEPT_MWAIT);
1096 set_intercept(svm, INTERCEPT_XSETBV);
1098 control->iopm_base_pa = iopm_base;
1099 control->msrpm_base_pa = __pa(svm->msrpm);
1100 control->int_ctl = V_INTR_MASKING_MASK;
1102 init_seg(&save->es);
1103 init_seg(&save->ss);
1104 init_seg(&save->ds);
1105 init_seg(&save->fs);
1106 init_seg(&save->gs);
1108 save->cs.selector = 0xf000;
1109 /* Executable/Readable Code Segment */
1110 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1111 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1112 save->cs.limit = 0xffff;
1114 * cs.base should really be 0xffff0000, but vmx can't handle that, so
1115 * be consistent with it.
1117 * Replace when we have real mode working for vmx.
1119 save->cs.base = 0xf0000;
1121 save->gdtr.limit = 0xffff;
1122 save->idtr.limit = 0xffff;
1124 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1125 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1127 svm_set_efer(&svm->vcpu, 0);
1128 save->dr6 = 0xffff0ff0;
1130 kvm_set_rflags(&svm->vcpu, 2);
1131 save->rip = 0x0000fff0;
1132 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1135 * This is the guest-visible cr0 value.
1136 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1138 svm->vcpu.arch.cr0 = 0;
1139 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1141 save->cr4 = X86_CR4_PAE;
1145 /* Setup VMCB for Nested Paging */
1146 control->nested_ctl = 1;
1147 clr_intercept(svm, INTERCEPT_INVLPG);
1148 clr_exception_intercept(svm, PF_VECTOR);
1149 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1150 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1151 save->g_pat = 0x0007040600070406ULL;
1155 svm->asid_generation = 0;
1157 svm->nested.vmcb = 0;
1158 svm->vcpu.arch.hflags = 0;
1160 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1161 control->pause_filter_count = 3000;
1162 set_intercept(svm, INTERCEPT_PAUSE);
1165 mark_all_dirty(svm->vmcb);
1170 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1172 struct vcpu_svm *svm = to_svm(vcpu);
1176 if (!kvm_vcpu_is_bsp(vcpu)) {
1177 kvm_rip_write(vcpu, 0);
1178 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1179 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1181 vcpu->arch.regs_avail = ~0;
1182 vcpu->arch.regs_dirty = ~0;
1187 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1189 struct vcpu_svm *svm;
1191 struct page *msrpm_pages;
1192 struct page *hsave_page;
1193 struct page *nested_msrpm_pages;
1196 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1202 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1204 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1209 page = alloc_page(GFP_KERNEL);
1213 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1217 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1218 if (!nested_msrpm_pages)
1221 hsave_page = alloc_page(GFP_KERNEL);
1225 svm->nested.hsave = page_address(hsave_page);
1227 svm->msrpm = page_address(msrpm_pages);
1228 svm_vcpu_init_msrpm(svm->msrpm);
1230 svm->nested.msrpm = page_address(nested_msrpm_pages);
1231 svm_vcpu_init_msrpm(svm->nested.msrpm);
1233 svm->vmcb = page_address(page);
1234 clear_page(svm->vmcb);
1235 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1236 svm->asid_generation = 0;
1238 kvm_write_tsc(&svm->vcpu, 0);
1240 err = fx_init(&svm->vcpu);
1244 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1245 if (kvm_vcpu_is_bsp(&svm->vcpu))
1246 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1248 svm_init_osvw(&svm->vcpu);
1253 __free_page(hsave_page);
1255 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1257 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1261 kvm_vcpu_uninit(&svm->vcpu);
1263 kmem_cache_free(kvm_vcpu_cache, svm);
1265 return ERR_PTR(err);
1268 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1270 struct vcpu_svm *svm = to_svm(vcpu);
1272 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1273 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1274 __free_page(virt_to_page(svm->nested.hsave));
1275 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1276 kvm_vcpu_uninit(vcpu);
1277 kmem_cache_free(kvm_vcpu_cache, svm);
1280 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1282 struct vcpu_svm *svm = to_svm(vcpu);
1285 if (unlikely(cpu != vcpu->cpu)) {
1286 svm->asid_generation = 0;
1287 mark_all_dirty(svm->vmcb);
1290 #ifdef CONFIG_X86_64
1291 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1293 savesegment(fs, svm->host.fs);
1294 savesegment(gs, svm->host.gs);
1295 svm->host.ldt = kvm_read_ldt();
1297 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1298 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1300 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1301 svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1302 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1303 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1307 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1309 struct vcpu_svm *svm = to_svm(vcpu);
1312 ++vcpu->stat.host_state_reload;
1313 kvm_load_ldt(svm->host.ldt);
1314 #ifdef CONFIG_X86_64
1315 loadsegment(fs, svm->host.fs);
1316 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1317 load_gs_index(svm->host.gs);
1319 #ifdef CONFIG_X86_32_LAZY_GS
1320 loadsegment(gs, svm->host.gs);
1323 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1324 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1327 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1329 return to_svm(vcpu)->vmcb->save.rflags;
1332 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1334 to_svm(vcpu)->vmcb->save.rflags = rflags;
1337 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1340 case VCPU_EXREG_PDPTR:
1341 BUG_ON(!npt_enabled);
1342 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1349 static void svm_set_vintr(struct vcpu_svm *svm)
1351 set_intercept(svm, INTERCEPT_VINTR);
1354 static void svm_clear_vintr(struct vcpu_svm *svm)
1356 clr_intercept(svm, INTERCEPT_VINTR);
1359 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1361 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1364 case VCPU_SREG_CS: return &save->cs;
1365 case VCPU_SREG_DS: return &save->ds;
1366 case VCPU_SREG_ES: return &save->es;
1367 case VCPU_SREG_FS: return &save->fs;
1368 case VCPU_SREG_GS: return &save->gs;
1369 case VCPU_SREG_SS: return &save->ss;
1370 case VCPU_SREG_TR: return &save->tr;
1371 case VCPU_SREG_LDTR: return &save->ldtr;
1377 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1379 struct vmcb_seg *s = svm_seg(vcpu, seg);
1384 static void svm_get_segment(struct kvm_vcpu *vcpu,
1385 struct kvm_segment *var, int seg)
1387 struct vmcb_seg *s = svm_seg(vcpu, seg);
1389 var->base = s->base;
1390 var->limit = s->limit;
1391 var->selector = s->selector;
1392 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1393 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1394 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1395 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1396 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1397 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1398 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1399 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1402 * AMD's VMCB does not have an explicit unusable field, so emulate it
1403 * for cross vendor migration purposes by "not present"
1405 var->unusable = !var->present || (var->type == 0);
1410 * SVM always stores 0 for the 'G' bit in the CS selector in
1411 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1412 * Intel's VMENTRY has a check on the 'G' bit.
1414 var->g = s->limit > 0xfffff;
1418 * Work around a bug where the busy flag in the tr selector
1428 * The accessed bit must always be set in the segment
1429 * descriptor cache, although it can be cleared in the
1430 * descriptor, the cached bit always remains at 1. Since
1431 * Intel has a check on this, set it here to support
1432 * cross-vendor migration.
1439 * On AMD CPUs sometimes the DB bit in the segment
1440 * descriptor is left as 1, although the whole segment has
1441 * been made unusable. Clear it here to pass an Intel VMX
1442 * entry check when cross vendor migrating.
1450 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1452 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1457 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1459 struct vcpu_svm *svm = to_svm(vcpu);
1461 dt->size = svm->vmcb->save.idtr.limit;
1462 dt->address = svm->vmcb->save.idtr.base;
1465 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1467 struct vcpu_svm *svm = to_svm(vcpu);
1469 svm->vmcb->save.idtr.limit = dt->size;
1470 svm->vmcb->save.idtr.base = dt->address ;
1471 mark_dirty(svm->vmcb, VMCB_DT);
1474 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1476 struct vcpu_svm *svm = to_svm(vcpu);
1478 dt->size = svm->vmcb->save.gdtr.limit;
1479 dt->address = svm->vmcb->save.gdtr.base;
1482 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1484 struct vcpu_svm *svm = to_svm(vcpu);
1486 svm->vmcb->save.gdtr.limit = dt->size;
1487 svm->vmcb->save.gdtr.base = dt->address ;
1488 mark_dirty(svm->vmcb, VMCB_DT);
1491 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1495 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1499 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1503 static void update_cr0_intercept(struct vcpu_svm *svm)
1505 ulong gcr0 = svm->vcpu.arch.cr0;
1506 u64 *hcr0 = &svm->vmcb->save.cr0;
1508 if (!svm->vcpu.fpu_active)
1509 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1511 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1512 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1514 mark_dirty(svm->vmcb, VMCB_CR);
1516 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1517 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1518 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1520 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1521 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1525 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1527 struct vcpu_svm *svm = to_svm(vcpu);
1529 #ifdef CONFIG_X86_64
1530 if (vcpu->arch.efer & EFER_LME) {
1531 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1532 vcpu->arch.efer |= EFER_LMA;
1533 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1536 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1537 vcpu->arch.efer &= ~EFER_LMA;
1538 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1542 vcpu->arch.cr0 = cr0;
1545 cr0 |= X86_CR0_PG | X86_CR0_WP;
1547 if (!vcpu->fpu_active)
1550 * re-enable caching here because the QEMU bios
1551 * does not do it - this results in some delay at
1554 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1555 svm->vmcb->save.cr0 = cr0;
1556 mark_dirty(svm->vmcb, VMCB_CR);
1557 update_cr0_intercept(svm);
1560 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1562 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1563 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1565 if (cr4 & X86_CR4_VMXE)
1568 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1569 svm_flush_tlb(vcpu);
1571 vcpu->arch.cr4 = cr4;
1574 cr4 |= host_cr4_mce;
1575 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1576 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1580 static void svm_set_segment(struct kvm_vcpu *vcpu,
1581 struct kvm_segment *var, int seg)
1583 struct vcpu_svm *svm = to_svm(vcpu);
1584 struct vmcb_seg *s = svm_seg(vcpu, seg);
1586 s->base = var->base;
1587 s->limit = var->limit;
1588 s->selector = var->selector;
1592 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1593 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1594 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1595 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1596 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1597 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1598 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1599 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1601 if (seg == VCPU_SREG_CS)
1603 = (svm->vmcb->save.cs.attrib
1604 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1606 mark_dirty(svm->vmcb, VMCB_SEG);
1609 static void update_db_intercept(struct kvm_vcpu *vcpu)
1611 struct vcpu_svm *svm = to_svm(vcpu);
1613 clr_exception_intercept(svm, DB_VECTOR);
1614 clr_exception_intercept(svm, BP_VECTOR);
1616 if (svm->nmi_singlestep)
1617 set_exception_intercept(svm, DB_VECTOR);
1619 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1620 if (vcpu->guest_debug &
1621 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1622 set_exception_intercept(svm, DB_VECTOR);
1623 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1624 set_exception_intercept(svm, BP_VECTOR);
1626 vcpu->guest_debug = 0;
1629 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1631 struct vcpu_svm *svm = to_svm(vcpu);
1633 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1634 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1636 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1638 mark_dirty(svm->vmcb, VMCB_DR);
1640 update_db_intercept(vcpu);
1643 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1645 if (sd->next_asid > sd->max_asid) {
1646 ++sd->asid_generation;
1648 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1651 svm->asid_generation = sd->asid_generation;
1652 svm->vmcb->control.asid = sd->next_asid++;
1654 mark_dirty(svm->vmcb, VMCB_ASID);
1657 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1659 struct vcpu_svm *svm = to_svm(vcpu);
1661 svm->vmcb->save.dr7 = value;
1662 mark_dirty(svm->vmcb, VMCB_DR);
1665 static int pf_interception(struct vcpu_svm *svm)
1667 u64 fault_address = svm->vmcb->control.exit_info_2;
1671 switch (svm->apf_reason) {
1673 error_code = svm->vmcb->control.exit_info_1;
1675 trace_kvm_page_fault(fault_address, error_code);
1676 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1677 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1678 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1679 svm->vmcb->control.insn_bytes,
1680 svm->vmcb->control.insn_len);
1682 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1683 svm->apf_reason = 0;
1684 local_irq_disable();
1685 kvm_async_pf_task_wait(fault_address);
1688 case KVM_PV_REASON_PAGE_READY:
1689 svm->apf_reason = 0;
1690 local_irq_disable();
1691 kvm_async_pf_task_wake(fault_address);
1698 static int db_interception(struct vcpu_svm *svm)
1700 struct kvm_run *kvm_run = svm->vcpu.run;
1702 if (!(svm->vcpu.guest_debug &
1703 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1704 !svm->nmi_singlestep) {
1705 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1709 if (svm->nmi_singlestep) {
1710 svm->nmi_singlestep = false;
1711 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1712 svm->vmcb->save.rflags &=
1713 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1714 update_db_intercept(&svm->vcpu);
1717 if (svm->vcpu.guest_debug &
1718 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1719 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1720 kvm_run->debug.arch.pc =
1721 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1722 kvm_run->debug.arch.exception = DB_VECTOR;
1729 static int bp_interception(struct vcpu_svm *svm)
1731 struct kvm_run *kvm_run = svm->vcpu.run;
1733 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1734 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1735 kvm_run->debug.arch.exception = BP_VECTOR;
1739 static int ud_interception(struct vcpu_svm *svm)
1743 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1744 if (er != EMULATE_DONE)
1745 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1749 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1751 struct vcpu_svm *svm = to_svm(vcpu);
1753 clr_exception_intercept(svm, NM_VECTOR);
1755 svm->vcpu.fpu_active = 1;
1756 update_cr0_intercept(svm);
1759 static int nm_interception(struct vcpu_svm *svm)
1761 svm_fpu_activate(&svm->vcpu);
1765 static bool is_erratum_383(void)
1770 if (!erratum_383_found)
1773 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1777 /* Bit 62 may or may not be set for this mce */
1778 value &= ~(1ULL << 62);
1780 if (value != 0xb600000000010015ULL)
1783 /* Clear MCi_STATUS registers */
1784 for (i = 0; i < 6; ++i)
1785 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1787 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1791 value &= ~(1ULL << 2);
1792 low = lower_32_bits(value);
1793 high = upper_32_bits(value);
1795 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1798 /* Flush tlb to evict multi-match entries */
1804 static void svm_handle_mce(struct vcpu_svm *svm)
1806 if (is_erratum_383()) {
1808 * Erratum 383 triggered. Guest state is corrupt so kill the
1811 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1813 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1819 * On an #MC intercept the MCE handler is not called automatically in
1820 * the host. So do it by hand here.
1824 /* not sure if we ever come back to this point */
1829 static int mc_interception(struct vcpu_svm *svm)
1834 static int shutdown_interception(struct vcpu_svm *svm)
1836 struct kvm_run *kvm_run = svm->vcpu.run;
1839 * VMCB is undefined after a SHUTDOWN intercept
1840 * so reinitialize it.
1842 clear_page(svm->vmcb);
1845 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1849 static int io_interception(struct vcpu_svm *svm)
1851 struct kvm_vcpu *vcpu = &svm->vcpu;
1852 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1853 int size, in, string;
1856 ++svm->vcpu.stat.io_exits;
1857 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1858 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1860 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1862 port = io_info >> 16;
1863 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1864 svm->next_rip = svm->vmcb->control.exit_info_2;
1865 skip_emulated_instruction(&svm->vcpu);
1867 return kvm_fast_pio_out(vcpu, size, port);
1870 static int nmi_interception(struct vcpu_svm *svm)
1875 static int intr_interception(struct vcpu_svm *svm)
1877 ++svm->vcpu.stat.irq_exits;
1881 static int nop_on_interception(struct vcpu_svm *svm)
1886 static int halt_interception(struct vcpu_svm *svm)
1888 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1889 skip_emulated_instruction(&svm->vcpu);
1890 return kvm_emulate_halt(&svm->vcpu);
1893 static int vmmcall_interception(struct vcpu_svm *svm)
1895 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1896 skip_emulated_instruction(&svm->vcpu);
1897 kvm_emulate_hypercall(&svm->vcpu);
1901 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1903 struct vcpu_svm *svm = to_svm(vcpu);
1905 return svm->nested.nested_cr3;
1908 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1910 struct vcpu_svm *svm = to_svm(vcpu);
1911 u64 cr3 = svm->nested.nested_cr3;
1915 ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1916 offset_in_page(cr3) + index * 8, 8);
1922 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1925 struct vcpu_svm *svm = to_svm(vcpu);
1927 svm->vmcb->control.nested_cr3 = root;
1928 mark_dirty(svm->vmcb, VMCB_NPT);
1929 svm_flush_tlb(vcpu);
1932 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1933 struct x86_exception *fault)
1935 struct vcpu_svm *svm = to_svm(vcpu);
1937 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1938 svm->vmcb->control.exit_code_hi = 0;
1939 svm->vmcb->control.exit_info_1 = fault->error_code;
1940 svm->vmcb->control.exit_info_2 = fault->address;
1942 nested_svm_vmexit(svm);
1945 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1949 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1951 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1952 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1953 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
1954 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1955 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1956 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1961 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1963 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1966 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1968 if (!(svm->vcpu.arch.efer & EFER_SVME)
1969 || !is_paging(&svm->vcpu)) {
1970 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1974 if (svm->vmcb->save.cpl) {
1975 kvm_inject_gp(&svm->vcpu, 0);
1982 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1983 bool has_error_code, u32 error_code)
1987 if (!is_guest_mode(&svm->vcpu))
1990 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1991 svm->vmcb->control.exit_code_hi = 0;
1992 svm->vmcb->control.exit_info_1 = error_code;
1993 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1995 vmexit = nested_svm_intercept(svm);
1996 if (vmexit == NESTED_EXIT_DONE)
1997 svm->nested.exit_required = true;
2002 /* This function returns true if it is save to enable the irq window */
2003 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2005 if (!is_guest_mode(&svm->vcpu))
2008 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2011 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2015 * if vmexit was already requested (by intercepted exception
2016 * for instance) do not overwrite it with "external interrupt"
2019 if (svm->nested.exit_required)
2022 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2023 svm->vmcb->control.exit_info_1 = 0;
2024 svm->vmcb->control.exit_info_2 = 0;
2026 if (svm->nested.intercept & 1ULL) {
2028 * The #vmexit can't be emulated here directly because this
2029 * code path runs with irqs and preemtion disabled. A
2030 * #vmexit emulation might sleep. Only signal request for
2033 svm->nested.exit_required = true;
2034 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2041 /* This function returns true if it is save to enable the nmi window */
2042 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2044 if (!is_guest_mode(&svm->vcpu))
2047 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2050 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2051 svm->nested.exit_required = true;
2056 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2062 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2063 if (is_error_page(page))
2071 kvm_release_page_clean(page);
2072 kvm_inject_gp(&svm->vcpu, 0);
2077 static void nested_svm_unmap(struct page *page)
2080 kvm_release_page_dirty(page);
2083 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2089 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2090 return NESTED_EXIT_HOST;
2092 port = svm->vmcb->control.exit_info_1 >> 16;
2093 gpa = svm->nested.vmcb_iopm + (port / 8);
2097 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2100 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2103 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2105 u32 offset, msr, value;
2108 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2109 return NESTED_EXIT_HOST;
2111 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2112 offset = svm_msrpm_offset(msr);
2113 write = svm->vmcb->control.exit_info_1 & 1;
2114 mask = 1 << ((2 * (msr & 0xf)) + write);
2116 if (offset == MSR_INVALID)
2117 return NESTED_EXIT_DONE;
2119 /* Offset is in 32 bit units but need in 8 bit units */
2122 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2123 return NESTED_EXIT_DONE;
2125 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2128 static int nested_svm_exit_special(struct vcpu_svm *svm)
2130 u32 exit_code = svm->vmcb->control.exit_code;
2132 switch (exit_code) {
2135 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2136 return NESTED_EXIT_HOST;
2138 /* For now we are always handling NPFs when using them */
2140 return NESTED_EXIT_HOST;
2142 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2143 /* When we're shadowing, trap PFs, but not async PF */
2144 if (!npt_enabled && svm->apf_reason == 0)
2145 return NESTED_EXIT_HOST;
2147 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2148 nm_interception(svm);
2154 return NESTED_EXIT_CONTINUE;
2158 * If this function returns true, this #vmexit was already handled
2160 static int nested_svm_intercept(struct vcpu_svm *svm)
2162 u32 exit_code = svm->vmcb->control.exit_code;
2163 int vmexit = NESTED_EXIT_HOST;
2165 switch (exit_code) {
2167 vmexit = nested_svm_exit_handled_msr(svm);
2170 vmexit = nested_svm_intercept_ioio(svm);
2172 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2173 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2174 if (svm->nested.intercept_cr & bit)
2175 vmexit = NESTED_EXIT_DONE;
2178 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2179 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2180 if (svm->nested.intercept_dr & bit)
2181 vmexit = NESTED_EXIT_DONE;
2184 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2185 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2186 if (svm->nested.intercept_exceptions & excp_bits)
2187 vmexit = NESTED_EXIT_DONE;
2188 /* async page fault always cause vmexit */
2189 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2190 svm->apf_reason != 0)
2191 vmexit = NESTED_EXIT_DONE;
2194 case SVM_EXIT_ERR: {
2195 vmexit = NESTED_EXIT_DONE;
2199 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2200 if (svm->nested.intercept & exit_bits)
2201 vmexit = NESTED_EXIT_DONE;
2208 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2212 vmexit = nested_svm_intercept(svm);
2214 if (vmexit == NESTED_EXIT_DONE)
2215 nested_svm_vmexit(svm);
2220 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2222 struct vmcb_control_area *dst = &dst_vmcb->control;
2223 struct vmcb_control_area *from = &from_vmcb->control;
2225 dst->intercept_cr = from->intercept_cr;
2226 dst->intercept_dr = from->intercept_dr;
2227 dst->intercept_exceptions = from->intercept_exceptions;
2228 dst->intercept = from->intercept;
2229 dst->iopm_base_pa = from->iopm_base_pa;
2230 dst->msrpm_base_pa = from->msrpm_base_pa;
2231 dst->tsc_offset = from->tsc_offset;
2232 dst->asid = from->asid;
2233 dst->tlb_ctl = from->tlb_ctl;
2234 dst->int_ctl = from->int_ctl;
2235 dst->int_vector = from->int_vector;
2236 dst->int_state = from->int_state;
2237 dst->exit_code = from->exit_code;
2238 dst->exit_code_hi = from->exit_code_hi;
2239 dst->exit_info_1 = from->exit_info_1;
2240 dst->exit_info_2 = from->exit_info_2;
2241 dst->exit_int_info = from->exit_int_info;
2242 dst->exit_int_info_err = from->exit_int_info_err;
2243 dst->nested_ctl = from->nested_ctl;
2244 dst->event_inj = from->event_inj;
2245 dst->event_inj_err = from->event_inj_err;
2246 dst->nested_cr3 = from->nested_cr3;
2247 dst->lbr_ctl = from->lbr_ctl;
2250 static int nested_svm_vmexit(struct vcpu_svm *svm)
2252 struct vmcb *nested_vmcb;
2253 struct vmcb *hsave = svm->nested.hsave;
2254 struct vmcb *vmcb = svm->vmcb;
2257 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2258 vmcb->control.exit_info_1,
2259 vmcb->control.exit_info_2,
2260 vmcb->control.exit_int_info,
2261 vmcb->control.exit_int_info_err,
2264 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2268 /* Exit Guest-Mode */
2269 leave_guest_mode(&svm->vcpu);
2270 svm->nested.vmcb = 0;
2272 /* Give the current vmcb to the guest */
2275 nested_vmcb->save.es = vmcb->save.es;
2276 nested_vmcb->save.cs = vmcb->save.cs;
2277 nested_vmcb->save.ss = vmcb->save.ss;
2278 nested_vmcb->save.ds = vmcb->save.ds;
2279 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2280 nested_vmcb->save.idtr = vmcb->save.idtr;
2281 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2282 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2283 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2284 nested_vmcb->save.cr2 = vmcb->save.cr2;
2285 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2286 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2287 nested_vmcb->save.rip = vmcb->save.rip;
2288 nested_vmcb->save.rsp = vmcb->save.rsp;
2289 nested_vmcb->save.rax = vmcb->save.rax;
2290 nested_vmcb->save.dr7 = vmcb->save.dr7;
2291 nested_vmcb->save.dr6 = vmcb->save.dr6;
2292 nested_vmcb->save.cpl = vmcb->save.cpl;
2294 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2295 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2296 nested_vmcb->control.int_state = vmcb->control.int_state;
2297 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2298 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2299 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2300 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2301 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2302 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2303 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2306 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2307 * to make sure that we do not lose injected events. So check event_inj
2308 * here and copy it to exit_int_info if it is valid.
2309 * Exit_int_info and event_inj can't be both valid because the case
2310 * below only happens on a VMRUN instruction intercept which has
2311 * no valid exit_int_info set.
2313 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2314 struct vmcb_control_area *nc = &nested_vmcb->control;
2316 nc->exit_int_info = vmcb->control.event_inj;
2317 nc->exit_int_info_err = vmcb->control.event_inj_err;
2320 nested_vmcb->control.tlb_ctl = 0;
2321 nested_vmcb->control.event_inj = 0;
2322 nested_vmcb->control.event_inj_err = 0;
2324 /* We always set V_INTR_MASKING and remember the old value in hflags */
2325 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2326 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2328 /* Restore the original control entries */
2329 copy_vmcb_control_area(vmcb, hsave);
2331 kvm_clear_exception_queue(&svm->vcpu);
2332 kvm_clear_interrupt_queue(&svm->vcpu);
2334 svm->nested.nested_cr3 = 0;
2336 /* Restore selected save entries */
2337 svm->vmcb->save.es = hsave->save.es;
2338 svm->vmcb->save.cs = hsave->save.cs;
2339 svm->vmcb->save.ss = hsave->save.ss;
2340 svm->vmcb->save.ds = hsave->save.ds;
2341 svm->vmcb->save.gdtr = hsave->save.gdtr;
2342 svm->vmcb->save.idtr = hsave->save.idtr;
2343 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2344 svm_set_efer(&svm->vcpu, hsave->save.efer);
2345 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2346 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2348 svm->vmcb->save.cr3 = hsave->save.cr3;
2349 svm->vcpu.arch.cr3 = hsave->save.cr3;
2351 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2353 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2354 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2355 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2356 svm->vmcb->save.dr7 = 0;
2357 svm->vmcb->save.cpl = 0;
2358 svm->vmcb->control.exit_int_info = 0;
2360 mark_all_dirty(svm->vmcb);
2362 nested_svm_unmap(page);
2364 nested_svm_uninit_mmu_context(&svm->vcpu);
2365 kvm_mmu_reset_context(&svm->vcpu);
2366 kvm_mmu_load(&svm->vcpu);
2371 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2374 * This function merges the msr permission bitmaps of kvm and the
2375 * nested vmcb. It is omptimized in that it only merges the parts where
2376 * the kvm msr permission bitmap may contain zero bits
2380 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2383 for (i = 0; i < MSRPM_OFFSETS; i++) {
2387 if (msrpm_offsets[i] == 0xffffffff)
2390 p = msrpm_offsets[i];
2391 offset = svm->nested.vmcb_msrpm + (p * 4);
2393 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2396 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2399 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2404 static bool nested_vmcb_checks(struct vmcb *vmcb)
2406 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2409 if (vmcb->control.asid == 0)
2412 if (vmcb->control.nested_ctl && !npt_enabled)
2418 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2420 struct vmcb *nested_vmcb;
2421 struct vmcb *hsave = svm->nested.hsave;
2422 struct vmcb *vmcb = svm->vmcb;
2426 vmcb_gpa = svm->vmcb->save.rax;
2428 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2432 if (!nested_vmcb_checks(nested_vmcb)) {
2433 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2434 nested_vmcb->control.exit_code_hi = 0;
2435 nested_vmcb->control.exit_info_1 = 0;
2436 nested_vmcb->control.exit_info_2 = 0;
2438 nested_svm_unmap(page);
2443 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2444 nested_vmcb->save.rip,
2445 nested_vmcb->control.int_ctl,
2446 nested_vmcb->control.event_inj,
2447 nested_vmcb->control.nested_ctl);
2449 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2450 nested_vmcb->control.intercept_cr >> 16,
2451 nested_vmcb->control.intercept_exceptions,
2452 nested_vmcb->control.intercept);
2454 /* Clear internal status */
2455 kvm_clear_exception_queue(&svm->vcpu);
2456 kvm_clear_interrupt_queue(&svm->vcpu);
2459 * Save the old vmcb, so we don't need to pick what we save, but can
2460 * restore everything when a VMEXIT occurs
2462 hsave->save.es = vmcb->save.es;
2463 hsave->save.cs = vmcb->save.cs;
2464 hsave->save.ss = vmcb->save.ss;
2465 hsave->save.ds = vmcb->save.ds;
2466 hsave->save.gdtr = vmcb->save.gdtr;
2467 hsave->save.idtr = vmcb->save.idtr;
2468 hsave->save.efer = svm->vcpu.arch.efer;
2469 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2470 hsave->save.cr4 = svm->vcpu.arch.cr4;
2471 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2472 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2473 hsave->save.rsp = vmcb->save.rsp;
2474 hsave->save.rax = vmcb->save.rax;
2476 hsave->save.cr3 = vmcb->save.cr3;
2478 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2480 copy_vmcb_control_area(hsave, vmcb);
2482 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2483 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2485 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2487 if (nested_vmcb->control.nested_ctl) {
2488 kvm_mmu_unload(&svm->vcpu);
2489 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2490 nested_svm_init_mmu_context(&svm->vcpu);
2493 /* Load the nested guest state */
2494 svm->vmcb->save.es = nested_vmcb->save.es;
2495 svm->vmcb->save.cs = nested_vmcb->save.cs;
2496 svm->vmcb->save.ss = nested_vmcb->save.ss;
2497 svm->vmcb->save.ds = nested_vmcb->save.ds;
2498 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2499 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2500 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2501 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2502 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2503 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2505 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2506 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2508 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2510 /* Guest paging mode is active - reset mmu */
2511 kvm_mmu_reset_context(&svm->vcpu);
2513 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2514 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2515 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2516 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2518 /* In case we don't even reach vcpu_run, the fields are not updated */
2519 svm->vmcb->save.rax = nested_vmcb->save.rax;
2520 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2521 svm->vmcb->save.rip = nested_vmcb->save.rip;
2522 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2523 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2524 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2526 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2527 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2529 /* cache intercepts */
2530 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2531 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2532 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2533 svm->nested.intercept = nested_vmcb->control.intercept;
2535 svm_flush_tlb(&svm->vcpu);
2536 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2537 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2538 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2540 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2542 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2543 /* We only want the cr8 intercept bits of the guest */
2544 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2545 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2548 /* We don't want to see VMMCALLs from a nested guest */
2549 clr_intercept(svm, INTERCEPT_VMMCALL);
2551 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2552 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2553 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2554 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2555 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2556 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2558 nested_svm_unmap(page);
2560 /* Enter Guest-Mode */
2561 enter_guest_mode(&svm->vcpu);
2564 * Merge guest and host intercepts - must be called with vcpu in
2565 * guest-mode to take affect here
2567 recalc_intercepts(svm);
2569 svm->nested.vmcb = vmcb_gpa;
2573 mark_all_dirty(svm->vmcb);
2578 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2580 to_vmcb->save.fs = from_vmcb->save.fs;
2581 to_vmcb->save.gs = from_vmcb->save.gs;
2582 to_vmcb->save.tr = from_vmcb->save.tr;
2583 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2584 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2585 to_vmcb->save.star = from_vmcb->save.star;
2586 to_vmcb->save.lstar = from_vmcb->save.lstar;
2587 to_vmcb->save.cstar = from_vmcb->save.cstar;
2588 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2589 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2590 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2591 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2594 static int vmload_interception(struct vcpu_svm *svm)
2596 struct vmcb *nested_vmcb;
2599 if (nested_svm_check_permissions(svm))
2602 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2606 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2607 skip_emulated_instruction(&svm->vcpu);
2609 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2610 nested_svm_unmap(page);
2615 static int vmsave_interception(struct vcpu_svm *svm)
2617 struct vmcb *nested_vmcb;
2620 if (nested_svm_check_permissions(svm))
2623 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2627 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2628 skip_emulated_instruction(&svm->vcpu);
2630 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2631 nested_svm_unmap(page);
2636 static int vmrun_interception(struct vcpu_svm *svm)
2638 if (nested_svm_check_permissions(svm))
2641 /* Save rip after vmrun instruction */
2642 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2644 if (!nested_svm_vmrun(svm))
2647 if (!nested_svm_vmrun_msrpm(svm))
2654 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2655 svm->vmcb->control.exit_code_hi = 0;
2656 svm->vmcb->control.exit_info_1 = 0;
2657 svm->vmcb->control.exit_info_2 = 0;
2659 nested_svm_vmexit(svm);
2664 static int stgi_interception(struct vcpu_svm *svm)
2666 if (nested_svm_check_permissions(svm))
2669 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2670 skip_emulated_instruction(&svm->vcpu);
2671 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2678 static int clgi_interception(struct vcpu_svm *svm)
2680 if (nested_svm_check_permissions(svm))
2683 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2684 skip_emulated_instruction(&svm->vcpu);
2688 /* After a CLGI no interrupts should come */
2689 svm_clear_vintr(svm);
2690 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2692 mark_dirty(svm->vmcb, VMCB_INTR);
2697 static int invlpga_interception(struct vcpu_svm *svm)
2699 struct kvm_vcpu *vcpu = &svm->vcpu;
2701 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2702 vcpu->arch.regs[VCPU_REGS_RAX]);
2704 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2705 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2707 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2708 skip_emulated_instruction(&svm->vcpu);
2712 static int skinit_interception(struct vcpu_svm *svm)
2714 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2716 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2720 static int xsetbv_interception(struct vcpu_svm *svm)
2722 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2723 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2725 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2726 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2727 skip_emulated_instruction(&svm->vcpu);
2733 static int invalid_op_interception(struct vcpu_svm *svm)
2735 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2739 static int task_switch_interception(struct vcpu_svm *svm)
2743 int int_type = svm->vmcb->control.exit_int_info &
2744 SVM_EXITINTINFO_TYPE_MASK;
2745 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2747 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2749 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2750 bool has_error_code = false;
2753 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2755 if (svm->vmcb->control.exit_info_2 &
2756 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2757 reason = TASK_SWITCH_IRET;
2758 else if (svm->vmcb->control.exit_info_2 &
2759 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2760 reason = TASK_SWITCH_JMP;
2762 reason = TASK_SWITCH_GATE;
2764 reason = TASK_SWITCH_CALL;
2766 if (reason == TASK_SWITCH_GATE) {
2768 case SVM_EXITINTINFO_TYPE_NMI:
2769 svm->vcpu.arch.nmi_injected = false;
2771 case SVM_EXITINTINFO_TYPE_EXEPT:
2772 if (svm->vmcb->control.exit_info_2 &
2773 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2774 has_error_code = true;
2776 (u32)svm->vmcb->control.exit_info_2;
2778 kvm_clear_exception_queue(&svm->vcpu);
2780 case SVM_EXITINTINFO_TYPE_INTR:
2781 kvm_clear_interrupt_queue(&svm->vcpu);
2788 if (reason != TASK_SWITCH_GATE ||
2789 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2790 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2791 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2792 skip_emulated_instruction(&svm->vcpu);
2794 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2795 has_error_code, error_code) == EMULATE_FAIL) {
2796 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2797 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2798 svm->vcpu.run->internal.ndata = 0;
2804 static int cpuid_interception(struct vcpu_svm *svm)
2806 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2807 kvm_emulate_cpuid(&svm->vcpu);
2811 static int iret_interception(struct vcpu_svm *svm)
2813 ++svm->vcpu.stat.nmi_window_exits;
2814 clr_intercept(svm, INTERCEPT_IRET);
2815 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2816 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2820 static int invlpg_interception(struct vcpu_svm *svm)
2822 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2823 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2825 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2826 skip_emulated_instruction(&svm->vcpu);
2830 static int emulate_on_interception(struct vcpu_svm *svm)
2832 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2835 static int rdpmc_interception(struct vcpu_svm *svm)
2839 if (!static_cpu_has(X86_FEATURE_NRIPS))
2840 return emulate_on_interception(svm);
2842 err = kvm_rdpmc(&svm->vcpu);
2843 kvm_complete_insn_gp(&svm->vcpu, err);
2848 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2850 unsigned long cr0 = svm->vcpu.arch.cr0;
2854 intercept = svm->nested.intercept;
2856 if (!is_guest_mode(&svm->vcpu) ||
2857 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2860 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2861 val &= ~SVM_CR0_SELECTIVE_MASK;
2864 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2865 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2871 #define CR_VALID (1ULL << 63)
2873 static int cr_interception(struct vcpu_svm *svm)
2879 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2880 return emulate_on_interception(svm);
2882 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2883 return emulate_on_interception(svm);
2885 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2886 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2889 if (cr >= 16) { /* mov to cr */
2891 val = kvm_register_read(&svm->vcpu, reg);
2894 if (!check_selective_cr0_intercepted(svm, val))
2895 err = kvm_set_cr0(&svm->vcpu, val);
2901 err = kvm_set_cr3(&svm->vcpu, val);
2904 err = kvm_set_cr4(&svm->vcpu, val);
2907 err = kvm_set_cr8(&svm->vcpu, val);
2910 WARN(1, "unhandled write to CR%d", cr);
2911 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2914 } else { /* mov from cr */
2917 val = kvm_read_cr0(&svm->vcpu);
2920 val = svm->vcpu.arch.cr2;
2923 val = kvm_read_cr3(&svm->vcpu);
2926 val = kvm_read_cr4(&svm->vcpu);
2929 val = kvm_get_cr8(&svm->vcpu);
2932 WARN(1, "unhandled read from CR%d", cr);
2933 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2936 kvm_register_write(&svm->vcpu, reg, val);
2938 kvm_complete_insn_gp(&svm->vcpu, err);
2943 static int dr_interception(struct vcpu_svm *svm)
2949 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2950 return emulate_on_interception(svm);
2952 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2953 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2955 if (dr >= 16) { /* mov to DRn */
2956 val = kvm_register_read(&svm->vcpu, reg);
2957 kvm_set_dr(&svm->vcpu, dr - 16, val);
2959 err = kvm_get_dr(&svm->vcpu, dr, &val);
2961 kvm_register_write(&svm->vcpu, reg, val);
2964 skip_emulated_instruction(&svm->vcpu);
2969 static int cr8_write_interception(struct vcpu_svm *svm)
2971 struct kvm_run *kvm_run = svm->vcpu.run;
2974 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2975 /* instruction emulation calls kvm_set_cr8() */
2976 r = cr_interception(svm);
2977 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2978 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2981 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2983 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2987 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu)
2989 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
2990 return vmcb->control.tsc_offset +
2991 svm_scale_tsc(vcpu, native_read_tsc());
2994 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2996 struct vcpu_svm *svm = to_svm(vcpu);
2999 case MSR_IA32_TSC: {
3000 *data = svm->vmcb->control.tsc_offset +
3001 svm_scale_tsc(vcpu, native_read_tsc());
3006 *data = svm->vmcb->save.star;
3008 #ifdef CONFIG_X86_64
3010 *data = svm->vmcb->save.lstar;
3013 *data = svm->vmcb->save.cstar;
3015 case MSR_KERNEL_GS_BASE:
3016 *data = svm->vmcb->save.kernel_gs_base;
3018 case MSR_SYSCALL_MASK:
3019 *data = svm->vmcb->save.sfmask;
3022 case MSR_IA32_SYSENTER_CS:
3023 *data = svm->vmcb->save.sysenter_cs;
3025 case MSR_IA32_SYSENTER_EIP:
3026 *data = svm->sysenter_eip;
3028 case MSR_IA32_SYSENTER_ESP:
3029 *data = svm->sysenter_esp;
3032 * Nobody will change the following 5 values in the VMCB so we can
3033 * safely return them on rdmsr. They will always be 0 until LBRV is
3036 case MSR_IA32_DEBUGCTLMSR:
3037 *data = svm->vmcb->save.dbgctl;
3039 case MSR_IA32_LASTBRANCHFROMIP:
3040 *data = svm->vmcb->save.br_from;
3042 case MSR_IA32_LASTBRANCHTOIP:
3043 *data = svm->vmcb->save.br_to;
3045 case MSR_IA32_LASTINTFROMIP:
3046 *data = svm->vmcb->save.last_excp_from;
3048 case MSR_IA32_LASTINTTOIP:
3049 *data = svm->vmcb->save.last_excp_to;
3051 case MSR_VM_HSAVE_PA:
3052 *data = svm->nested.hsave_msr;
3055 *data = svm->nested.vm_cr_msr;
3057 case MSR_IA32_UCODE_REV:
3061 return kvm_get_msr_common(vcpu, ecx, data);
3066 static int rdmsr_interception(struct vcpu_svm *svm)
3068 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3071 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3072 trace_kvm_msr_read_ex(ecx);
3073 kvm_inject_gp(&svm->vcpu, 0);
3075 trace_kvm_msr_read(ecx, data);
3077 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3078 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3079 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3080 skip_emulated_instruction(&svm->vcpu);
3085 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3087 struct vcpu_svm *svm = to_svm(vcpu);
3088 int svm_dis, chg_mask;
3090 if (data & ~SVM_VM_CR_VALID_MASK)
3093 chg_mask = SVM_VM_CR_VALID_MASK;
3095 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3096 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3098 svm->nested.vm_cr_msr &= ~chg_mask;
3099 svm->nested.vm_cr_msr |= (data & chg_mask);
3101 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3103 /* check for svm_disable while efer.svme is set */
3104 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3110 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
3112 struct vcpu_svm *svm = to_svm(vcpu);
3116 kvm_write_tsc(vcpu, data);
3119 svm->vmcb->save.star = data;
3121 #ifdef CONFIG_X86_64
3123 svm->vmcb->save.lstar = data;
3126 svm->vmcb->save.cstar = data;
3128 case MSR_KERNEL_GS_BASE:
3129 svm->vmcb->save.kernel_gs_base = data;
3131 case MSR_SYSCALL_MASK:
3132 svm->vmcb->save.sfmask = data;
3135 case MSR_IA32_SYSENTER_CS:
3136 svm->vmcb->save.sysenter_cs = data;
3138 case MSR_IA32_SYSENTER_EIP:
3139 svm->sysenter_eip = data;
3140 svm->vmcb->save.sysenter_eip = data;
3142 case MSR_IA32_SYSENTER_ESP:
3143 svm->sysenter_esp = data;
3144 svm->vmcb->save.sysenter_esp = data;
3146 case MSR_IA32_DEBUGCTLMSR:
3147 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3148 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3152 if (data & DEBUGCTL_RESERVED_BITS)
3155 svm->vmcb->save.dbgctl = data;
3156 mark_dirty(svm->vmcb, VMCB_LBR);
3157 if (data & (1ULL<<0))
3158 svm_enable_lbrv(svm);
3160 svm_disable_lbrv(svm);
3162 case MSR_VM_HSAVE_PA:
3163 svm->nested.hsave_msr = data;
3166 return svm_set_vm_cr(vcpu, data);
3168 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3171 return kvm_set_msr_common(vcpu, ecx, data);
3176 static int wrmsr_interception(struct vcpu_svm *svm)
3178 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3179 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3180 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3183 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3184 if (svm_set_msr(&svm->vcpu, ecx, data)) {
3185 trace_kvm_msr_write_ex(ecx, data);
3186 kvm_inject_gp(&svm->vcpu, 0);
3188 trace_kvm_msr_write(ecx, data);
3189 skip_emulated_instruction(&svm->vcpu);
3194 static int msr_interception(struct vcpu_svm *svm)
3196 if (svm->vmcb->control.exit_info_1)
3197 return wrmsr_interception(svm);
3199 return rdmsr_interception(svm);
3202 static int interrupt_window_interception(struct vcpu_svm *svm)
3204 struct kvm_run *kvm_run = svm->vcpu.run;
3206 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3207 svm_clear_vintr(svm);
3208 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3209 mark_dirty(svm->vmcb, VMCB_INTR);
3211 * If the user space waits to inject interrupts, exit as soon as
3214 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3215 kvm_run->request_interrupt_window &&
3216 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3217 ++svm->vcpu.stat.irq_window_exits;
3218 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3225 static int pause_interception(struct vcpu_svm *svm)
3227 kvm_vcpu_on_spin(&(svm->vcpu));
3231 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
3232 [SVM_EXIT_READ_CR0] = cr_interception,
3233 [SVM_EXIT_READ_CR3] = cr_interception,
3234 [SVM_EXIT_READ_CR4] = cr_interception,
3235 [SVM_EXIT_READ_CR8] = cr_interception,
3236 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3237 [SVM_EXIT_WRITE_CR0] = cr_interception,
3238 [SVM_EXIT_WRITE_CR3] = cr_interception,
3239 [SVM_EXIT_WRITE_CR4] = cr_interception,
3240 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3241 [SVM_EXIT_READ_DR0] = dr_interception,
3242 [SVM_EXIT_READ_DR1] = dr_interception,
3243 [SVM_EXIT_READ_DR2] = dr_interception,
3244 [SVM_EXIT_READ_DR3] = dr_interception,
3245 [SVM_EXIT_READ_DR4] = dr_interception,
3246 [SVM_EXIT_READ_DR5] = dr_interception,
3247 [SVM_EXIT_READ_DR6] = dr_interception,
3248 [SVM_EXIT_READ_DR7] = dr_interception,
3249 [SVM_EXIT_WRITE_DR0] = dr_interception,
3250 [SVM_EXIT_WRITE_DR1] = dr_interception,
3251 [SVM_EXIT_WRITE_DR2] = dr_interception,
3252 [SVM_EXIT_WRITE_DR3] = dr_interception,
3253 [SVM_EXIT_WRITE_DR4] = dr_interception,
3254 [SVM_EXIT_WRITE_DR5] = dr_interception,
3255 [SVM_EXIT_WRITE_DR6] = dr_interception,
3256 [SVM_EXIT_WRITE_DR7] = dr_interception,
3257 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3258 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3259 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3260 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3261 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3262 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3263 [SVM_EXIT_INTR] = intr_interception,
3264 [SVM_EXIT_NMI] = nmi_interception,
3265 [SVM_EXIT_SMI] = nop_on_interception,
3266 [SVM_EXIT_INIT] = nop_on_interception,
3267 [SVM_EXIT_VINTR] = interrupt_window_interception,
3268 [SVM_EXIT_RDPMC] = rdpmc_interception,
3269 [SVM_EXIT_CPUID] = cpuid_interception,
3270 [SVM_EXIT_IRET] = iret_interception,
3271 [SVM_EXIT_INVD] = emulate_on_interception,
3272 [SVM_EXIT_PAUSE] = pause_interception,
3273 [SVM_EXIT_HLT] = halt_interception,
3274 [SVM_EXIT_INVLPG] = invlpg_interception,
3275 [SVM_EXIT_INVLPGA] = invlpga_interception,
3276 [SVM_EXIT_IOIO] = io_interception,
3277 [SVM_EXIT_MSR] = msr_interception,
3278 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3279 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3280 [SVM_EXIT_VMRUN] = vmrun_interception,
3281 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3282 [SVM_EXIT_VMLOAD] = vmload_interception,
3283 [SVM_EXIT_VMSAVE] = vmsave_interception,
3284 [SVM_EXIT_STGI] = stgi_interception,
3285 [SVM_EXIT_CLGI] = clgi_interception,
3286 [SVM_EXIT_SKINIT] = skinit_interception,
3287 [SVM_EXIT_WBINVD] = emulate_on_interception,
3288 [SVM_EXIT_MONITOR] = invalid_op_interception,
3289 [SVM_EXIT_MWAIT] = invalid_op_interception,
3290 [SVM_EXIT_XSETBV] = xsetbv_interception,
3291 [SVM_EXIT_NPF] = pf_interception,
3294 static void dump_vmcb(struct kvm_vcpu *vcpu)
3296 struct vcpu_svm *svm = to_svm(vcpu);
3297 struct vmcb_control_area *control = &svm->vmcb->control;
3298 struct vmcb_save_area *save = &svm->vmcb->save;
3300 pr_err("VMCB Control Area:\n");
3301 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3302 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3303 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3304 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3305 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3306 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3307 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3308 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3309 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3310 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3311 pr_err("%-20s%d\n", "asid:", control->asid);
3312 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3313 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3314 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3315 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3316 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3317 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3318 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3319 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3320 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3321 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3322 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3323 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3324 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3325 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3326 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3327 pr_err("VMCB State Save Area:\n");
3328 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3330 save->es.selector, save->es.attrib,
3331 save->es.limit, save->es.base);
3332 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3334 save->cs.selector, save->cs.attrib,
3335 save->cs.limit, save->cs.base);
3336 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3338 save->ss.selector, save->ss.attrib,
3339 save->ss.limit, save->ss.base);
3340 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3342 save->ds.selector, save->ds.attrib,
3343 save->ds.limit, save->ds.base);
3344 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3346 save->fs.selector, save->fs.attrib,
3347 save->fs.limit, save->fs.base);
3348 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3350 save->gs.selector, save->gs.attrib,
3351 save->gs.limit, save->gs.base);
3352 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3354 save->gdtr.selector, save->gdtr.attrib,
3355 save->gdtr.limit, save->gdtr.base);
3356 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3358 save->ldtr.selector, save->ldtr.attrib,
3359 save->ldtr.limit, save->ldtr.base);
3360 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3362 save->idtr.selector, save->idtr.attrib,
3363 save->idtr.limit, save->idtr.base);
3364 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3366 save->tr.selector, save->tr.attrib,
3367 save->tr.limit, save->tr.base);
3368 pr_err("cpl: %d efer: %016llx\n",
3369 save->cpl, save->efer);
3370 pr_err("%-15s %016llx %-13s %016llx\n",
3371 "cr0:", save->cr0, "cr2:", save->cr2);
3372 pr_err("%-15s %016llx %-13s %016llx\n",
3373 "cr3:", save->cr3, "cr4:", save->cr4);
3374 pr_err("%-15s %016llx %-13s %016llx\n",
3375 "dr6:", save->dr6, "dr7:", save->dr7);
3376 pr_err("%-15s %016llx %-13s %016llx\n",
3377 "rip:", save->rip, "rflags:", save->rflags);
3378 pr_err("%-15s %016llx %-13s %016llx\n",
3379 "rsp:", save->rsp, "rax:", save->rax);
3380 pr_err("%-15s %016llx %-13s %016llx\n",
3381 "star:", save->star, "lstar:", save->lstar);
3382 pr_err("%-15s %016llx %-13s %016llx\n",
3383 "cstar:", save->cstar, "sfmask:", save->sfmask);
3384 pr_err("%-15s %016llx %-13s %016llx\n",
3385 "kernel_gs_base:", save->kernel_gs_base,
3386 "sysenter_cs:", save->sysenter_cs);
3387 pr_err("%-15s %016llx %-13s %016llx\n",
3388 "sysenter_esp:", save->sysenter_esp,
3389 "sysenter_eip:", save->sysenter_eip);
3390 pr_err("%-15s %016llx %-13s %016llx\n",
3391 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3392 pr_err("%-15s %016llx %-13s %016llx\n",
3393 "br_from:", save->br_from, "br_to:", save->br_to);
3394 pr_err("%-15s %016llx %-13s %016llx\n",
3395 "excp_from:", save->last_excp_from,
3396 "excp_to:", save->last_excp_to);
3399 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3401 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3403 *info1 = control->exit_info_1;
3404 *info2 = control->exit_info_2;
3407 static int handle_exit(struct kvm_vcpu *vcpu)
3409 struct vcpu_svm *svm = to_svm(vcpu);
3410 struct kvm_run *kvm_run = vcpu->run;
3411 u32 exit_code = svm->vmcb->control.exit_code;
3413 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3414 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3416 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3418 if (unlikely(svm->nested.exit_required)) {
3419 nested_svm_vmexit(svm);
3420 svm->nested.exit_required = false;
3425 if (is_guest_mode(vcpu)) {
3428 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3429 svm->vmcb->control.exit_info_1,
3430 svm->vmcb->control.exit_info_2,
3431 svm->vmcb->control.exit_int_info,
3432 svm->vmcb->control.exit_int_info_err,
3435 vmexit = nested_svm_exit_special(svm);
3437 if (vmexit == NESTED_EXIT_CONTINUE)
3438 vmexit = nested_svm_exit_handled(svm);
3440 if (vmexit == NESTED_EXIT_DONE)
3444 svm_complete_interrupts(svm);
3446 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3447 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3448 kvm_run->fail_entry.hardware_entry_failure_reason
3449 = svm->vmcb->control.exit_code;
3450 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3455 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3456 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3457 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3458 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3459 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3461 __func__, svm->vmcb->control.exit_int_info,
3464 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3465 || !svm_exit_handlers[exit_code]) {
3466 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3467 kvm_run->hw.hardware_exit_reason = exit_code;
3471 return svm_exit_handlers[exit_code](svm);
3474 static void reload_tss(struct kvm_vcpu *vcpu)
3476 int cpu = raw_smp_processor_id();
3478 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3479 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3483 static void pre_svm_run(struct vcpu_svm *svm)
3485 int cpu = raw_smp_processor_id();
3487 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3489 /* FIXME: handle wraparound of asid_generation */
3490 if (svm->asid_generation != sd->asid_generation)
3494 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3496 struct vcpu_svm *svm = to_svm(vcpu);
3498 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3499 vcpu->arch.hflags |= HF_NMI_MASK;
3500 set_intercept(svm, INTERCEPT_IRET);
3501 ++vcpu->stat.nmi_injections;
3504 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3506 struct vmcb_control_area *control;
3508 control = &svm->vmcb->control;
3509 control->int_vector = irq;
3510 control->int_ctl &= ~V_INTR_PRIO_MASK;
3511 control->int_ctl |= V_IRQ_MASK |
3512 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3513 mark_dirty(svm->vmcb, VMCB_INTR);
3516 static void svm_set_irq(struct kvm_vcpu *vcpu)
3518 struct vcpu_svm *svm = to_svm(vcpu);
3520 BUG_ON(!(gif_set(svm)));
3522 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3523 ++vcpu->stat.irq_injections;
3525 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3526 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3529 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3531 struct vcpu_svm *svm = to_svm(vcpu);
3533 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3540 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3543 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3545 struct vcpu_svm *svm = to_svm(vcpu);
3546 struct vmcb *vmcb = svm->vmcb;
3548 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3549 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3550 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3555 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3557 struct vcpu_svm *svm = to_svm(vcpu);
3559 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3562 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3564 struct vcpu_svm *svm = to_svm(vcpu);
3567 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3568 set_intercept(svm, INTERCEPT_IRET);
3570 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3571 clr_intercept(svm, INTERCEPT_IRET);
3575 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3577 struct vcpu_svm *svm = to_svm(vcpu);
3578 struct vmcb *vmcb = svm->vmcb;
3581 if (!gif_set(svm) ||
3582 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3585 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3587 if (is_guest_mode(vcpu))
3588 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3593 static void enable_irq_window(struct kvm_vcpu *vcpu)
3595 struct vcpu_svm *svm = to_svm(vcpu);
3598 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3599 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3600 * get that intercept, this function will be called again though and
3601 * we'll get the vintr intercept.
3603 if (gif_set(svm) && nested_svm_intr(svm)) {
3605 svm_inject_irq(svm, 0x0);
3609 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3611 struct vcpu_svm *svm = to_svm(vcpu);
3613 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3615 return; /* IRET will cause a vm exit */
3618 * Something prevents NMI from been injected. Single step over possible
3619 * problem (IRET or exception injection or interrupt shadow)
3621 svm->nmi_singlestep = true;
3622 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3623 update_db_intercept(vcpu);
3626 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3631 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3633 struct vcpu_svm *svm = to_svm(vcpu);
3635 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3636 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3638 svm->asid_generation--;
3641 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3645 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3647 struct vcpu_svm *svm = to_svm(vcpu);
3649 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3652 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3653 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3654 kvm_set_cr8(vcpu, cr8);
3658 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3660 struct vcpu_svm *svm = to_svm(vcpu);
3663 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3666 cr8 = kvm_get_cr8(vcpu);
3667 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3668 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3671 static void svm_complete_interrupts(struct vcpu_svm *svm)
3675 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3676 unsigned int3_injected = svm->int3_injected;
3678 svm->int3_injected = 0;
3681 * If we've made progress since setting HF_IRET_MASK, we've
3682 * executed an IRET and can allow NMI injection.
3684 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3685 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3686 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3687 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3690 svm->vcpu.arch.nmi_injected = false;
3691 kvm_clear_exception_queue(&svm->vcpu);
3692 kvm_clear_interrupt_queue(&svm->vcpu);
3694 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3697 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3699 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3700 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3703 case SVM_EXITINTINFO_TYPE_NMI:
3704 svm->vcpu.arch.nmi_injected = true;
3706 case SVM_EXITINTINFO_TYPE_EXEPT:
3708 * In case of software exceptions, do not reinject the vector,
3709 * but re-execute the instruction instead. Rewind RIP first
3710 * if we emulated INT3 before.
3712 if (kvm_exception_is_soft(vector)) {
3713 if (vector == BP_VECTOR && int3_injected &&
3714 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3715 kvm_rip_write(&svm->vcpu,
3716 kvm_rip_read(&svm->vcpu) -
3720 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3721 u32 err = svm->vmcb->control.exit_int_info_err;
3722 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3725 kvm_requeue_exception(&svm->vcpu, vector);
3727 case SVM_EXITINTINFO_TYPE_INTR:
3728 kvm_queue_interrupt(&svm->vcpu, vector, false);
3735 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3737 struct vcpu_svm *svm = to_svm(vcpu);
3738 struct vmcb_control_area *control = &svm->vmcb->control;
3740 control->exit_int_info = control->event_inj;
3741 control->exit_int_info_err = control->event_inj_err;
3742 control->event_inj = 0;
3743 svm_complete_interrupts(svm);
3746 #ifdef CONFIG_X86_64
3752 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3754 struct vcpu_svm *svm = to_svm(vcpu);
3756 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3757 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3758 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3761 * A vmexit emulation is required before the vcpu can be executed
3764 if (unlikely(svm->nested.exit_required))
3769 sync_lapic_to_cr8(vcpu);
3771 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3778 "push %%"R"bp; \n\t"
3779 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3780 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3781 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3782 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3783 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3784 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3785 #ifdef CONFIG_X86_64
3786 "mov %c[r8](%[svm]), %%r8 \n\t"
3787 "mov %c[r9](%[svm]), %%r9 \n\t"
3788 "mov %c[r10](%[svm]), %%r10 \n\t"
3789 "mov %c[r11](%[svm]), %%r11 \n\t"
3790 "mov %c[r12](%[svm]), %%r12 \n\t"
3791 "mov %c[r13](%[svm]), %%r13 \n\t"
3792 "mov %c[r14](%[svm]), %%r14 \n\t"
3793 "mov %c[r15](%[svm]), %%r15 \n\t"
3796 /* Enter guest mode */
3798 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3799 __ex(SVM_VMLOAD) "\n\t"
3800 __ex(SVM_VMRUN) "\n\t"
3801 __ex(SVM_VMSAVE) "\n\t"
3804 /* Save guest registers, load host registers */
3805 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3806 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3807 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3808 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3809 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3810 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3811 #ifdef CONFIG_X86_64
3812 "mov %%r8, %c[r8](%[svm]) \n\t"
3813 "mov %%r9, %c[r9](%[svm]) \n\t"
3814 "mov %%r10, %c[r10](%[svm]) \n\t"
3815 "mov %%r11, %c[r11](%[svm]) \n\t"
3816 "mov %%r12, %c[r12](%[svm]) \n\t"
3817 "mov %%r13, %c[r13](%[svm]) \n\t"
3818 "mov %%r14, %c[r14](%[svm]) \n\t"
3819 "mov %%r15, %c[r15](%[svm]) \n\t"
3824 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3825 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3826 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3827 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3828 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3829 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3830 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3831 #ifdef CONFIG_X86_64
3832 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3833 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3834 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3835 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3836 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3837 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3838 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3839 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3842 , R"bx", R"cx", R"dx", R"si", R"di"
3843 #ifdef CONFIG_X86_64
3844 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3848 #ifdef CONFIG_X86_64
3849 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3851 loadsegment(fs, svm->host.fs);
3852 #ifndef CONFIG_X86_32_LAZY_GS
3853 loadsegment(gs, svm->host.gs);
3859 local_irq_disable();
3861 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3862 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3863 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3864 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3866 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3868 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3869 kvm_before_handle_nmi(&svm->vcpu);
3873 /* Any pending NMI will happen here */
3875 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3876 kvm_after_handle_nmi(&svm->vcpu);
3878 sync_cr8_to_lapic(vcpu);
3882 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3884 /* if exit due to PF check for async PF */
3885 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3886 svm->apf_reason = kvm_read_and_reset_pf_reason();
3889 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3890 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3894 * We need to handle MC intercepts here before the vcpu has a chance to
3895 * change the physical cpu
3897 if (unlikely(svm->vmcb->control.exit_code ==
3898 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3899 svm_handle_mce(svm);
3901 mark_all_clean(svm->vmcb);
3906 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3908 struct vcpu_svm *svm = to_svm(vcpu);
3910 svm->vmcb->save.cr3 = root;
3911 mark_dirty(svm->vmcb, VMCB_CR);
3912 svm_flush_tlb(vcpu);
3915 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3917 struct vcpu_svm *svm = to_svm(vcpu);
3919 svm->vmcb->control.nested_cr3 = root;
3920 mark_dirty(svm->vmcb, VMCB_NPT);
3922 /* Also sync guest cr3 here in case we live migrate */
3923 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3924 mark_dirty(svm->vmcb, VMCB_CR);
3926 svm_flush_tlb(vcpu);
3929 static int is_disabled(void)
3933 rdmsrl(MSR_VM_CR, vm_cr);
3934 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3941 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3944 * Patch in the VMMCALL instruction:
3946 hypercall[0] = 0x0f;
3947 hypercall[1] = 0x01;
3948 hypercall[2] = 0xd9;
3951 static void svm_check_processor_compat(void *rtn)
3956 static bool svm_cpu_has_accelerated_tpr(void)
3961 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3966 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3970 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3975 entry->ecx |= (1 << 2); /* Set SVM bit */
3978 entry->eax = 1; /* SVM revision 1 */
3979 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3980 ASID emulation to nested SVM */
3981 entry->ecx = 0; /* Reserved */
3982 entry->edx = 0; /* Per default do not support any
3983 additional features */
3985 /* Support next_rip if host supports it */
3986 if (boot_cpu_has(X86_FEATURE_NRIPS))
3987 entry->edx |= SVM_FEATURE_NRIP;
3989 /* Support NPT for the guest if enabled */
3991 entry->edx |= SVM_FEATURE_NPT;
3997 static int svm_get_lpage_level(void)
3999 return PT_PDPE_LEVEL;
4002 static bool svm_rdtscp_supported(void)
4007 static bool svm_has_wbinvd_exit(void)
4012 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4014 struct vcpu_svm *svm = to_svm(vcpu);
4016 set_exception_intercept(svm, NM_VECTOR);
4017 update_cr0_intercept(svm);
4020 #define PRE_EX(exit) { .exit_code = (exit), \
4021 .stage = X86_ICPT_PRE_EXCEPT, }
4022 #define POST_EX(exit) { .exit_code = (exit), \
4023 .stage = X86_ICPT_POST_EXCEPT, }
4024 #define POST_MEM(exit) { .exit_code = (exit), \
4025 .stage = X86_ICPT_POST_MEMACCESS, }
4027 static struct __x86_intercept {
4029 enum x86_intercept_stage stage;
4030 } x86_intercept_map[] = {
4031 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4032 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4033 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4034 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4035 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4036 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4037 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4038 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4039 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4040 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4041 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4042 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4043 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4044 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4045 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4046 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4047 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4048 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4049 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4050 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4051 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4052 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4053 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4054 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4055 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4056 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4057 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4058 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4059 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4060 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4061 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4062 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4063 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4064 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4065 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4066 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4067 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4068 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4069 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4070 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4071 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4072 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4073 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4074 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4075 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4076 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4083 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4084 struct x86_instruction_info *info,
4085 enum x86_intercept_stage stage)
4087 struct vcpu_svm *svm = to_svm(vcpu);
4088 int vmexit, ret = X86EMUL_CONTINUE;
4089 struct __x86_intercept icpt_info;
4090 struct vmcb *vmcb = svm->vmcb;
4092 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4095 icpt_info = x86_intercept_map[info->intercept];
4097 if (stage != icpt_info.stage)
4100 switch (icpt_info.exit_code) {
4101 case SVM_EXIT_READ_CR0:
4102 if (info->intercept == x86_intercept_cr_read)
4103 icpt_info.exit_code += info->modrm_reg;
4105 case SVM_EXIT_WRITE_CR0: {
4106 unsigned long cr0, val;
4109 if (info->intercept == x86_intercept_cr_write)
4110 icpt_info.exit_code += info->modrm_reg;
4112 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4115 intercept = svm->nested.intercept;
4117 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4120 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4121 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4123 if (info->intercept == x86_intercept_lmsw) {
4126 /* lmsw can't clear PE - catch this here */
4127 if (cr0 & X86_CR0_PE)
4132 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4136 case SVM_EXIT_READ_DR0:
4137 case SVM_EXIT_WRITE_DR0:
4138 icpt_info.exit_code += info->modrm_reg;
4141 if (info->intercept == x86_intercept_wrmsr)
4142 vmcb->control.exit_info_1 = 1;
4144 vmcb->control.exit_info_1 = 0;
4146 case SVM_EXIT_PAUSE:
4148 * We get this for NOP only, but pause
4149 * is rep not, check this here
4151 if (info->rep_prefix != REPE_PREFIX)
4153 case SVM_EXIT_IOIO: {
4157 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4159 if (info->intercept == x86_intercept_in ||
4160 info->intercept == x86_intercept_ins) {
4161 exit_info |= SVM_IOIO_TYPE_MASK;
4162 bytes = info->src_bytes;
4164 bytes = info->dst_bytes;
4167 if (info->intercept == x86_intercept_outs ||
4168 info->intercept == x86_intercept_ins)
4169 exit_info |= SVM_IOIO_STR_MASK;
4171 if (info->rep_prefix)
4172 exit_info |= SVM_IOIO_REP_MASK;
4174 bytes = min(bytes, 4u);
4176 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4178 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4180 vmcb->control.exit_info_1 = exit_info;
4181 vmcb->control.exit_info_2 = info->next_rip;
4189 vmcb->control.next_rip = info->next_rip;
4190 vmcb->control.exit_code = icpt_info.exit_code;
4191 vmexit = nested_svm_exit_handled(svm);
4193 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4200 static struct kvm_x86_ops svm_x86_ops = {
4201 .cpu_has_kvm_support = has_svm,
4202 .disabled_by_bios = is_disabled,
4203 .hardware_setup = svm_hardware_setup,
4204 .hardware_unsetup = svm_hardware_unsetup,
4205 .check_processor_compatibility = svm_check_processor_compat,
4206 .hardware_enable = svm_hardware_enable,
4207 .hardware_disable = svm_hardware_disable,
4208 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4210 .vcpu_create = svm_create_vcpu,
4211 .vcpu_free = svm_free_vcpu,
4212 .vcpu_reset = svm_vcpu_reset,
4214 .prepare_guest_switch = svm_prepare_guest_switch,
4215 .vcpu_load = svm_vcpu_load,
4216 .vcpu_put = svm_vcpu_put,
4218 .set_guest_debug = svm_guest_debug,
4219 .get_msr = svm_get_msr,
4220 .set_msr = svm_set_msr,
4221 .get_segment_base = svm_get_segment_base,
4222 .get_segment = svm_get_segment,
4223 .set_segment = svm_set_segment,
4224 .get_cpl = svm_get_cpl,
4225 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4226 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4227 .decache_cr3 = svm_decache_cr3,
4228 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4229 .set_cr0 = svm_set_cr0,
4230 .set_cr3 = svm_set_cr3,
4231 .set_cr4 = svm_set_cr4,
4232 .set_efer = svm_set_efer,
4233 .get_idt = svm_get_idt,
4234 .set_idt = svm_set_idt,
4235 .get_gdt = svm_get_gdt,
4236 .set_gdt = svm_set_gdt,
4237 .set_dr7 = svm_set_dr7,
4238 .cache_reg = svm_cache_reg,
4239 .get_rflags = svm_get_rflags,
4240 .set_rflags = svm_set_rflags,
4241 .fpu_activate = svm_fpu_activate,
4242 .fpu_deactivate = svm_fpu_deactivate,
4244 .tlb_flush = svm_flush_tlb,
4246 .run = svm_vcpu_run,
4247 .handle_exit = handle_exit,
4248 .skip_emulated_instruction = skip_emulated_instruction,
4249 .set_interrupt_shadow = svm_set_interrupt_shadow,
4250 .get_interrupt_shadow = svm_get_interrupt_shadow,
4251 .patch_hypercall = svm_patch_hypercall,
4252 .set_irq = svm_set_irq,
4253 .set_nmi = svm_inject_nmi,
4254 .queue_exception = svm_queue_exception,
4255 .cancel_injection = svm_cancel_injection,
4256 .interrupt_allowed = svm_interrupt_allowed,
4257 .nmi_allowed = svm_nmi_allowed,
4258 .get_nmi_mask = svm_get_nmi_mask,
4259 .set_nmi_mask = svm_set_nmi_mask,
4260 .enable_nmi_window = enable_nmi_window,
4261 .enable_irq_window = enable_irq_window,
4262 .update_cr8_intercept = update_cr8_intercept,
4264 .set_tss_addr = svm_set_tss_addr,
4265 .get_tdp_level = get_npt_level,
4266 .get_mt_mask = svm_get_mt_mask,
4268 .get_exit_info = svm_get_exit_info,
4270 .get_lpage_level = svm_get_lpage_level,
4272 .cpuid_update = svm_cpuid_update,
4274 .rdtscp_supported = svm_rdtscp_supported,
4276 .set_supported_cpuid = svm_set_supported_cpuid,
4278 .has_wbinvd_exit = svm_has_wbinvd_exit,
4280 .set_tsc_khz = svm_set_tsc_khz,
4281 .write_tsc_offset = svm_write_tsc_offset,
4282 .adjust_tsc_offset = svm_adjust_tsc_offset,
4283 .compute_tsc_offset = svm_compute_tsc_offset,
4284 .read_l1_tsc = svm_read_l1_tsc,
4286 .set_tdp_cr3 = set_tdp_cr3,
4288 .check_intercept = svm_check_intercept,
4291 static int __init svm_init(void)
4293 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4294 __alignof__(struct vcpu_svm), THIS_MODULE);
4297 static void __exit svm_exit(void)
4302 module_init(svm_init)
4303 module_exit(svm_exit)