arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39 #include <linux/frame.h>
  40 #include <linux/psp-sev.h>
  41 #include <linux/file.h>
  42 #include <linux/pagemap.h>
  43 #include <linux/swap.h>
  44
  45 #include <asm/apic.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/desc.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kvm_para.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/spec-ctrl.h>
  53
  54 #include <asm/virtext.h>
  55 #include "trace.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id svm_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  67
  68 #define IOPM_ALLOC_ORDER 2
  69 #define MSRPM_ALLOC_ORDER 1
  70
  71 #define SEG_TYPE_LDT 2
  72 #define SEG_TYPE_BUSY_TSS16 3
  73
  74 #define SVM_FEATURE_NPT            (1 <<  0)
  75 #define SVM_FEATURE_LBRV           (1 <<  1)
  76 #define SVM_FEATURE_SVML           (1 <<  2)
  77 #define SVM_FEATURE_NRIP           (1 <<  3)
  78 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  79 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  80 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  81 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  82 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  83
  84 #define SVM_AVIC_DOORBELL       0xc001011b
  85
  86 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  87 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  88 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  89
  90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  91
  92 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  93 #define TSC_RATIO_MIN           0x0000000000000001ULL
  94 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  95
  96 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  97
  98 /*
  99  * 0xff is broadcast, so the max index allowed for physical APIC ID
 100  * table is 0xfe.  APIC IDs above 0xff are reserved.
 101  */
 102 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
 103
 104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
 105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 107
 108 /* AVIC GATAG is encoded using VM and VCPU IDs */
 109 #define AVIC_VCPU_ID_BITS               8
 110 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 111
 112 #define AVIC_VM_ID_BITS                 24
 113 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 114 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 115
 116 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 117                                                 (y & AVIC_VCPU_ID_MASK))
 118 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 119 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 120
 121 static bool erratum_383_found __read_mostly;
 122
 123 static const u32 host_save_user_msrs[] = {
 124 #ifdef CONFIG_X86_64
 125         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 126         MSR_FS_BASE,
 127 #endif
 128         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 129         MSR_TSC_AUX,
 130 };
 131
 132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 133
 134 struct kvm_sev_info {
 135         bool active;            /* SEV enabled guest */
 136         unsigned int asid;      /* ASID used for this guest */
 137         unsigned int handle;    /* SEV firmware handle */
 138         int fd;                 /* SEV device fd */
 139         unsigned long pages_locked; /* Number of pages locked */
 140         struct list_head regions_list;  /* List of registered regions */
 141 };
 142
 143 struct kvm_svm {
 144         struct kvm kvm;
 145
 146         /* Struct members for AVIC */
 147         u32 avic_vm_id;
 148         u32 ldr_mode;
 149         struct page *avic_logical_id_table_page;
 150         struct page *avic_physical_id_table_page;
 151         struct hlist_node hnode;
 152
 153         struct kvm_sev_info sev_info;
 154 };
 155
 156 struct kvm_vcpu;
 157
 158 struct nested_state {
 159         struct vmcb *hsave;
 160         u64 hsave_msr;
 161         u64 vm_cr_msr;
 162         u64 vmcb;
 163
 164         /* These are the merged vectors */
 165         u32 *msrpm;
 166
 167         /* gpa pointers to the real vectors */
 168         u64 vmcb_msrpm;
 169         u64 vmcb_iopm;
 170
 171         /* A VMEXIT is required but not yet emulated */
 172         bool exit_required;
 173
 174         /* cache for intercepts of the guest */
 175         u32 intercept_cr;
 176         u32 intercept_dr;
 177         u32 intercept_exceptions;
 178         u64 intercept;
 179
 180         /* Nested Paging related state */
 181         u64 nested_cr3;
 182 };
 183
 184 #define MSRPM_OFFSETS   16
 185 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 186
 187 /*
 188  * Set osvw_len to higher value when updated Revision Guides
 189  * are published and we know what the new status bits are
 190  */
 191 static uint64_t osvw_len = 4, osvw_status;
 192
 193 struct vcpu_svm {
 194         struct kvm_vcpu vcpu;
 195         struct vmcb *vmcb;
 196         unsigned long vmcb_pa;
 197         struct svm_cpu_data *svm_data;
 198         uint64_t asid_generation;
 199         uint64_t sysenter_esp;
 200         uint64_t sysenter_eip;
 201         uint64_t tsc_aux;
 202
 203         u64 msr_decfg;
 204
 205         u64 next_rip;
 206
 207         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 208         struct {
 209                 u16 fs;
 210                 u16 gs;
 211                 u16 ldt;
 212                 u64 gs_base;
 213         } host;
 214
 215         u64 spec_ctrl;
 216         /*
 217          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 218          * translated into the appropriate L2_CFG bits on the host to
 219          * perform speculative control.
 220          */
 221         u64 virt_spec_ctrl;
 222
 223         u32 *msrpm;
 224
 225         ulong nmi_iret_rip;
 226
 227         struct nested_state nested;
 228
 229         bool nmi_singlestep;
 230         u64 nmi_singlestep_guest_rflags;
 231
 232         unsigned int3_injected;
 233         unsigned long int3_rip;
 234
 235         /* cached guest cpuid flags for faster access */
 236         bool nrips_enabled      : 1;
 237
 238         u32 ldr_reg;
 239         struct page *avic_backing_page;
 240         u64 *avic_physical_id_cache;
 241         bool avic_is_running;
 242
 243         /*
 244          * Per-vcpu list of struct amd_svm_iommu_ir:
 245          * This is used mainly to store interrupt remapping information used
 246          * when update the vcpu affinity. This avoids the need to scan for
 247          * IRTE and try to match ga_tag in the IOMMU driver.
 248          */
 249         struct list_head ir_list;
 250         spinlock_t ir_list_lock;
 251
 252         /* which host CPU was used for running this vcpu */
 253         unsigned int last_cpu;
 254 };
 255
 256 /*
 257  * This is a wrapper of struct amd_iommu_ir_data.
 258  */
 259 struct amd_svm_iommu_ir {
 260         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 261         void *data;             /* Storing pointer to struct amd_ir_data */
 262 };
 263
 264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 265 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 266
 267 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 268 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 269 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 270 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 271
 272 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 273 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 274
 275 #define MSR_INVALID                     0xffffffffU
 276
 277 static const struct svm_direct_access_msrs {
 278         u32 index;   /* Index of the MSR */
 279         bool always; /* True if intercept is always on */
 280 } direct_access_msrs[] = {
 281         { .index = MSR_STAR,                            .always = true  },
 282         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 283 #ifdef CONFIG_X86_64
 284         { .index = MSR_GS_BASE,                         .always = true  },
 285         { .index = MSR_FS_BASE,                         .always = true  },
 286         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 287         { .index = MSR_LSTAR,                           .always = true  },
 288         { .index = MSR_CSTAR,                           .always = true  },
 289         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 290 #endif
 291         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 292         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 293         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 294         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 295         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 296         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 297         { .index = MSR_INVALID,                         .always = false },
 298 };
 299
 300 /* enable NPT for AMD64 and X86 with PAE */
 301 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 302 static bool npt_enabled = true;
 303 #else
 304 static bool npt_enabled;
 305 #endif
 306
 307 /*
 308  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 309  * pause_filter_count: On processors that support Pause filtering(indicated
 310  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 311  *      count value. On VMRUN this value is loaded into an internal counter.
 312  *      Each time a pause instruction is executed, this counter is decremented
 313  *      until it reaches zero at which time a #VMEXIT is generated if pause
 314  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 315  *      Intercept Filtering for more details.
 316  *      This also indicate if ple logic enabled.
 317  *
 318  * pause_filter_thresh: In addition, some processor families support advanced
 319  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 320  *      the amount of time a guest is allowed to execute in a pause loop.
 321  *      In this mode, a 16-bit pause filter threshold field is added in the
 322  *      VMCB. The threshold value is a cycle count that is used to reset the
 323  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 324  *      count value from VMCB into an internal counter. Then, on each pause
 325  *      instruction the hardware checks the elapsed number of cycles since
 326  *      the most recent pause instruction against the pause filter threshold.
 327  *      If the elapsed cycle count is greater than the pause filter threshold,
 328  *      then the internal pause count is reloaded from the VMCB and execution
 329  *      continues. If the elapsed cycle count is less than the pause filter
 330  *      threshold, then the internal pause count is decremented. If the count
 331  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 332  *      triggered. If advanced pause filtering is supported and pause filter
 333  *      threshold field is set to zero, the filter will operate in the simpler,
 334  *      count only mode.
 335  */
 336
 337 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 338 module_param(pause_filter_thresh, ushort, 0444);
 339
 340 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 341 module_param(pause_filter_count, ushort, 0444);
 342
 343 /* Default doubles per-vcpu window every exit. */
 344 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 345 module_param(pause_filter_count_grow, ushort, 0444);
 346
 347 /* Default resets per-vcpu window every exit to pause_filter_count. */
 348 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 349 module_param(pause_filter_count_shrink, ushort, 0444);
 350
 351 /* Default is to compute the maximum so we can never overflow. */
 352 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 353 module_param(pause_filter_count_max, ushort, 0444);
 354
 355 /* allow nested paging (virtualized MMU) for all guests */
 356 static int npt = true;
 357 module_param(npt, int, S_IRUGO);
 358
 359 /* allow nested virtualization in KVM/SVM */
 360 static int nested = true;
 361 module_param(nested, int, S_IRUGO);
 362
 363 /* enable / disable AVIC */
 364 static int avic;
 365 #ifdef CONFIG_X86_LOCAL_APIC
 366 module_param(avic, int, S_IRUGO);
 367 #endif
 368
 369 /* enable/disable Virtual VMLOAD VMSAVE */
 370 static int vls = true;
 371 module_param(vls, int, 0444);
 372
 373 /* enable/disable Virtual GIF */
 374 static int vgif = true;
 375 module_param(vgif, int, 0444);
 376
 377 /* enable/disable SEV support */
 378 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 379 module_param(sev, int, 0444);
 380
 381 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 382
 383 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 384 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
 385 static void svm_complete_interrupts(struct vcpu_svm *svm);
 386
 387 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 388 static int nested_svm_intercept(struct vcpu_svm *svm);
 389 static int nested_svm_vmexit(struct vcpu_svm *svm);
 390 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 391                                       bool has_error_code, u32 error_code);
 392
 393 enum {
 394         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 395                             pause filter count */
 396         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 397         VMCB_ASID,       /* ASID */
 398         VMCB_INTR,       /* int_ctl, int_vector */
 399         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 400         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 401         VMCB_DR,         /* DR6, DR7 */
 402         VMCB_DT,         /* GDT, IDT */
 403         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 404         VMCB_CR2,        /* CR2 only */
 405         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 406         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 407                           * AVIC PHYSICAL_TABLE pointer,
 408                           * AVIC LOGICAL_TABLE pointer
 409                           */
 410         VMCB_DIRTY_MAX,
 411 };
 412
 413 /* TPR and CR2 are always written before VMRUN */
 414 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 415
 416 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 417
 418 static unsigned int max_sev_asid;
 419 static unsigned int min_sev_asid;
 420 static unsigned long *sev_asid_bitmap;
 421 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
 422
 423 struct enc_region {
 424         struct list_head list;
 425         unsigned long npages;
 426         struct page **pages;
 427         unsigned long uaddr;
 428         unsigned long size;
 429 };
 430
 431
 432 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 433 {
 434         return container_of(kvm, struct kvm_svm, kvm);
 435 }
 436
 437 static inline bool svm_sev_enabled(void)
 438 {
 439         return max_sev_asid;
 440 }
 441
 442 static inline bool sev_guest(struct kvm *kvm)
 443 {
 444         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 445
 446         return sev->active;
 447 }
 448
 449 static inline int sev_get_asid(struct kvm *kvm)
 450 {
 451         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 452
 453         return sev->asid;
 454 }
 455
 456 static inline void mark_all_dirty(struct vmcb *vmcb)
 457 {
 458         vmcb->control.clean = 0;
 459 }
 460
 461 static inline void mark_all_clean(struct vmcb *vmcb)
 462 {
 463         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 464                                & ~VMCB_ALWAYS_DIRTY_MASK;
 465 }
 466
 467 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 468 {
 469         vmcb->control.clean &= ~(1 << bit);
 470 }
 471
 472 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 473 {
 474         return container_of(vcpu, struct vcpu_svm, vcpu);
 475 }
 476
 477 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 478 {
 479         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 480         mark_dirty(svm->vmcb, VMCB_AVIC);
 481 }
 482
 483 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 484 {
 485         struct vcpu_svm *svm = to_svm(vcpu);
 486         u64 *entry = svm->avic_physical_id_cache;
 487
 488         if (!entry)
 489                 return false;
 490
 491         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 492 }
 493
 494 static void recalc_intercepts(struct vcpu_svm *svm)
 495 {
 496         struct vmcb_control_area *c, *h;
 497         struct nested_state *g;
 498
 499         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 500
 501         if (!is_guest_mode(&svm->vcpu))
 502                 return;
 503
 504         c = &svm->vmcb->control;
 505         h = &svm->nested.hsave->control;
 506         g = &svm->nested;
 507
 508         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 509         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 510         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 511         c->intercept = h->intercept | g->intercept;
 512 }
 513
 514 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 515 {
 516         if (is_guest_mode(&svm->vcpu))
 517                 return svm->nested.hsave;
 518         else
 519                 return svm->vmcb;
 520 }
 521
 522 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 523 {
 524         struct vmcb *vmcb = get_host_vmcb(svm);
 525
 526         vmcb->control.intercept_cr |= (1U << bit);
 527
 528         recalc_intercepts(svm);
 529 }
 530
 531 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 532 {
 533         struct vmcb *vmcb = get_host_vmcb(svm);
 534
 535         vmcb->control.intercept_cr &= ~(1U << bit);
 536
 537         recalc_intercepts(svm);
 538 }
 539
 540 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 541 {
 542         struct vmcb *vmcb = get_host_vmcb(svm);
 543
 544         return vmcb->control.intercept_cr & (1U << bit);
 545 }
 546
 547 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 548 {
 549         struct vmcb *vmcb = get_host_vmcb(svm);
 550
 551         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 552                 | (1 << INTERCEPT_DR1_READ)
 553                 | (1 << INTERCEPT_DR2_READ)
 554                 | (1 << INTERCEPT_DR3_READ)
 555                 | (1 << INTERCEPT_DR4_READ)
 556                 | (1 << INTERCEPT_DR5_READ)
 557                 | (1 << INTERCEPT_DR6_READ)
 558                 | (1 << INTERCEPT_DR7_READ)
 559                 | (1 << INTERCEPT_DR0_WRITE)
 560                 | (1 << INTERCEPT_DR1_WRITE)
 561                 | (1 << INTERCEPT_DR2_WRITE)
 562                 | (1 << INTERCEPT_DR3_WRITE)
 563                 | (1 << INTERCEPT_DR4_WRITE)
 564                 | (1 << INTERCEPT_DR5_WRITE)
 565                 | (1 << INTERCEPT_DR6_WRITE)
 566                 | (1 << INTERCEPT_DR7_WRITE);
 567
 568         recalc_intercepts(svm);
 569 }
 570
 571 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 572 {
 573         struct vmcb *vmcb = get_host_vmcb(svm);
 574
 575         vmcb->control.intercept_dr = 0;
 576
 577         recalc_intercepts(svm);
 578 }
 579
 580 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 581 {
 582         struct vmcb *vmcb = get_host_vmcb(svm);
 583
 584         vmcb->control.intercept_exceptions |= (1U << bit);
 585
 586         recalc_intercepts(svm);
 587 }
 588
 589 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 590 {
 591         struct vmcb *vmcb = get_host_vmcb(svm);
 592
 593         vmcb->control.intercept_exceptions &= ~(1U << bit);
 594
 595         recalc_intercepts(svm);
 596 }
 597
 598 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 599 {
 600         struct vmcb *vmcb = get_host_vmcb(svm);
 601
 602         vmcb->control.intercept |= (1ULL << bit);
 603
 604         recalc_intercepts(svm);
 605 }
 606
 607 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 608 {
 609         struct vmcb *vmcb = get_host_vmcb(svm);
 610
 611         vmcb->control.intercept &= ~(1ULL << bit);
 612
 613         recalc_intercepts(svm);
 614 }
 615
 616 static inline bool vgif_enabled(struct vcpu_svm *svm)
 617 {
 618         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 619 }
 620
 621 static inline void enable_gif(struct vcpu_svm *svm)
 622 {
 623         if (vgif_enabled(svm))
 624                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 625         else
 626                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 627 }
 628
 629 static inline void disable_gif(struct vcpu_svm *svm)
 630 {
 631         if (vgif_enabled(svm))
 632                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 633         else
 634                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 635 }
 636
 637 static inline bool gif_set(struct vcpu_svm *svm)
 638 {
 639         if (vgif_enabled(svm))
 640                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 641         else
 642                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 643 }
 644
 645 static unsigned long iopm_base;
 646
 647 struct kvm_ldttss_desc {
 648         u16 limit0;
 649         u16 base0;
 650         unsigned base1:8, type:5, dpl:2, p:1;
 651         unsigned limit1:4, zero0:3, g:1, base2:8;
 652         u32 base3;
 653         u32 zero1;
 654 } __attribute__((packed));
 655
 656 struct svm_cpu_data {
 657         int cpu;
 658
 659         u64 asid_generation;
 660         u32 max_asid;
 661         u32 next_asid;
 662         u32 min_asid;
 663         struct kvm_ldttss_desc *tss_desc;
 664
 665         struct page *save_area;
 666         struct vmcb *current_vmcb;
 667
 668         /* index = sev_asid, value = vmcb pointer */
 669         struct vmcb **sev_vmcbs;
 670 };
 671
 672 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 673
 674 struct svm_init_data {
 675         int cpu;
 676         int r;
 677 };
 678
 679 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 680
 681 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 682 #define MSRS_RANGE_SIZE 2048
 683 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 684
 685 static u32 svm_msrpm_offset(u32 msr)
 686 {
 687         u32 offset;
 688         int i;
 689
 690         for (i = 0; i < NUM_MSR_MAPS; i++) {
 691                 if (msr < msrpm_ranges[i] ||
 692                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 693                         continue;
 694
 695                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 696                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 697
 698                 /* Now we have the u8 offset - but need the u32 offset */
 699                 return offset / 4;
 700         }
 701
 702         /* MSR not in any range */
 703         return MSR_INVALID;
 704 }
 705
 706 #define MAX_INST_SIZE 15
 707
 708 static inline void clgi(void)
 709 {
 710         asm volatile (__ex(SVM_CLGI));
 711 }
 712
 713 static inline void stgi(void)
 714 {
 715         asm volatile (__ex(SVM_STGI));
 716 }
 717
 718 static inline void invlpga(unsigned long addr, u32 asid)
 719 {
 720         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 721 }
 722
 723 static int get_npt_level(struct kvm_vcpu *vcpu)
 724 {
 725 #ifdef CONFIG_X86_64
 726         return PT64_ROOT_4LEVEL;
 727 #else
 728         return PT32E_ROOT_LEVEL;
 729 #endif
 730 }
 731
 732 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 733 {
 734         vcpu->arch.efer = efer;
 735         if (!npt_enabled && !(efer & EFER_LMA))
 736                 efer &= ~EFER_LME;
 737
 738         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 739         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 740 }
 741
 742 static int is_external_interrupt(u32 info)
 743 {
 744         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 745         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 746 }
 747
 748 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 749 {
 750         struct vcpu_svm *svm = to_svm(vcpu);
 751         u32 ret = 0;
 752
 753         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 754                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 755         return ret;
 756 }
 757
 758 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 759 {
 760         struct vcpu_svm *svm = to_svm(vcpu);
 761
 762         if (mask == 0)
 763                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 764         else
 765                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 766
 767 }
 768
 769 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 770 {
 771         struct vcpu_svm *svm = to_svm(vcpu);
 772
 773         if (svm->vmcb->control.next_rip != 0) {
 774                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 775                 svm->next_rip = svm->vmcb->control.next_rip;
 776         }
 777
 778         if (!svm->next_rip) {
 779                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 780                                 EMULATE_DONE)
 781                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 782                 return;
 783         }
 784         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 785                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 786                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 787
 788         kvm_rip_write(vcpu, svm->next_rip);
 789         svm_set_interrupt_shadow(vcpu, 0);
 790 }
 791
 792 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 793 {
 794         struct vcpu_svm *svm = to_svm(vcpu);
 795         unsigned nr = vcpu->arch.exception.nr;
 796         bool has_error_code = vcpu->arch.exception.has_error_code;
 797         bool reinject = vcpu->arch.exception.injected;
 798         u32 error_code = vcpu->arch.exception.error_code;
 799
 800         /*
 801          * If we are within a nested VM we'd better #VMEXIT and let the guest
 802          * handle the exception
 803          */
 804         if (!reinject &&
 805             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 806                 return;
 807
 808         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 809                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 810
 811                 /*
 812                  * For guest debugging where we have to reinject #BP if some
 813                  * INT3 is guest-owned:
 814                  * Emulate nRIP by moving RIP forward. Will fail if injection
 815                  * raises a fault that is not intercepted. Still better than
 816                  * failing in all cases.
 817                  */
 818                 skip_emulated_instruction(&svm->vcpu);
 819                 rip = kvm_rip_read(&svm->vcpu);
 820                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 821                 svm->int3_injected = rip - old_rip;
 822         }
 823
 824         svm->vmcb->control.event_inj = nr
 825                 | SVM_EVTINJ_VALID
 826                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 827                 | SVM_EVTINJ_TYPE_EXEPT;
 828         svm->vmcb->control.event_inj_err = error_code;
 829 }
 830
 831 static void svm_init_erratum_383(void)
 832 {
 833         u32 low, high;
 834         int err;
 835         u64 val;
 836
 837         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 838                 return;
 839
 840         /* Use _safe variants to not break nested virtualization */
 841         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 842         if (err)
 843                 return;
 844
 845         val |= (1ULL << 47);
 846
 847         low  = lower_32_bits(val);
 848         high = upper_32_bits(val);
 849
 850         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 851
 852         erratum_383_found = true;
 853 }
 854
 855 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 856 {
 857         /*
 858          * Guests should see errata 400 and 415 as fixed (assuming that
 859          * HLT and IO instructions are intercepted).
 860          */
 861         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 862         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 863
 864         /*
 865          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 866          * all osvw.status bits inside that length, including bit 0 (which is
 867          * reserved for erratum 298), are valid. However, if host processor's
 868          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 869          * be conservative here and therefore we tell the guest that erratum 298
 870          * is present (because we really don't know).
 871          */
 872         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 873                 vcpu->arch.osvw.status |= 1;
 874 }
 875
 876 static int has_svm(void)
 877 {
 878         const char *msg;
 879
 880         if (!cpu_has_svm(&msg)) {
 881                 printk(KERN_INFO "has_svm: %s\n", msg);
 882                 return 0;
 883         }
 884
 885         return 1;
 886 }
 887
 888 static void svm_hardware_disable(void)
 889 {
 890         /* Make sure we clean up behind us */
 891         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 892                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 893
 894         cpu_svm_disable();
 895
 896         amd_pmu_disable_virt();
 897 }
 898
 899 static int svm_hardware_enable(void)
 900 {
 901
 902         struct svm_cpu_data *sd;
 903         uint64_t efer;
 904         struct desc_struct *gdt;
 905         int me = raw_smp_processor_id();
 906
 907         rdmsrl(MSR_EFER, efer);
 908         if (efer & EFER_SVME)
 909                 return -EBUSY;
 910
 911         if (!has_svm()) {
 912                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 913                 return -EINVAL;
 914         }
 915         sd = per_cpu(svm_data, me);
 916         if (!sd) {
 917                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 918                 return -EINVAL;
 919         }
 920
 921         sd->asid_generation = 1;
 922         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 923         sd->next_asid = sd->max_asid + 1;
 924         sd->min_asid = max_sev_asid + 1;
 925
 926         gdt = get_current_gdt_rw();
 927         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 928
 929         wrmsrl(MSR_EFER, efer | EFER_SVME);
 930
 931         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 932
 933         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 934                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 935                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 936         }
 937
 938
 939         /*
 940          * Get OSVW bits.
 941          *
 942          * Note that it is possible to have a system with mixed processor
 943          * revisions and therefore different OSVW bits. If bits are not the same
 944          * on different processors then choose the worst case (i.e. if erratum
 945          * is present on one processor and not on another then assume that the
 946          * erratum is present everywhere).
 947          */
 948         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 949                 uint64_t len, status = 0;
 950                 int err;
 951
 952                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 953                 if (!err)
 954                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 955                                                       &err);
 956
 957                 if (err)
 958                         osvw_status = osvw_len = 0;
 959                 else {
 960                         if (len < osvw_len)
 961                                 osvw_len = len;
 962                         osvw_status |= status;
 963                         osvw_status &= (1ULL << osvw_len) - 1;
 964                 }
 965         } else
 966                 osvw_status = osvw_len = 0;
 967
 968         svm_init_erratum_383();
 969
 970         amd_pmu_enable_virt();
 971
 972         return 0;
 973 }
 974
 975 static void svm_cpu_uninit(int cpu)
 976 {
 977         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 978
 979         if (!sd)
 980                 return;
 981
 982         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 983         kfree(sd->sev_vmcbs);
 984         __free_page(sd->save_area);
 985         kfree(sd);
 986 }
 987
 988 static int svm_cpu_init(int cpu)
 989 {
 990         struct svm_cpu_data *sd;
 991         int r;
 992
 993         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 994         if (!sd)
 995                 return -ENOMEM;
 996         sd->cpu = cpu;
 997         r = -ENOMEM;
 998         sd->save_area = alloc_page(GFP_KERNEL);
 999         if (!sd->save_area)
1000                 goto err_1;
1001
1002         if (svm_sev_enabled()) {
1003                 r = -ENOMEM;
1004                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1005                                               sizeof(void *),
1006                                               GFP_KERNEL);
1007                 if (!sd->sev_vmcbs)
1008                         goto err_1;
1009         }
1010
1011         per_cpu(svm_data, cpu) = sd;
1012
1013         return 0;
1014
1015 err_1:
1016         kfree(sd);
1017         return r;
1018
1019 }
1020
1021 static bool valid_msr_intercept(u32 index)
1022 {
1023         int i;
1024
1025         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1026                 if (direct_access_msrs[i].index == index)
1027                         return true;
1028
1029         return false;
1030 }
1031
1032 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1033 {
1034         u8 bit_write;
1035         unsigned long tmp;
1036         u32 offset;
1037         u32 *msrpm;
1038
1039         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1040                                       to_svm(vcpu)->msrpm;
1041
1042         offset    = svm_msrpm_offset(msr);
1043         bit_write = 2 * (msr & 0x0f) + 1;
1044         tmp       = msrpm[offset];
1045
1046         BUG_ON(offset == MSR_INVALID);
1047
1048         return !!test_bit(bit_write,  &tmp);
1049 }
1050
1051 static void set_msr_interception(u32 *msrpm, unsigned msr,
1052                                  int read, int write)
1053 {
1054         u8 bit_read, bit_write;
1055         unsigned long tmp;
1056         u32 offset;
1057
1058         /*
1059          * If this warning triggers extend the direct_access_msrs list at the
1060          * beginning of the file
1061          */
1062         WARN_ON(!valid_msr_intercept(msr));
1063
1064         offset    = svm_msrpm_offset(msr);
1065         bit_read  = 2 * (msr & 0x0f);
1066         bit_write = 2 * (msr & 0x0f) + 1;
1067         tmp       = msrpm[offset];
1068
1069         BUG_ON(offset == MSR_INVALID);
1070
1071         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
1072         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1073
1074         msrpm[offset] = tmp;
1075 }
1076
1077 static void svm_vcpu_init_msrpm(u32 *msrpm)
1078 {
1079         int i;
1080
1081         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1082
1083         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1084                 if (!direct_access_msrs[i].always)
1085                         continue;
1086
1087                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1088         }
1089 }
1090
1091 static void add_msr_offset(u32 offset)
1092 {
1093         int i;
1094
1095         for (i = 0; i < MSRPM_OFFSETS; ++i) {
1096
1097                 /* Offset already in list? */
1098                 if (msrpm_offsets[i] == offset)
1099                         return;
1100
1101                 /* Slot used by another offset? */
1102                 if (msrpm_offsets[i] != MSR_INVALID)
1103                         continue;
1104
1105                 /* Add offset to list */
1106                 msrpm_offsets[i] = offset;
1107
1108                 return;
1109         }
1110
1111         /*
1112          * If this BUG triggers the msrpm_offsets table has an overflow. Just
1113          * increase MSRPM_OFFSETS in this case.
1114          */
1115         BUG();
1116 }
1117
1118 static void init_msrpm_offsets(void)
1119 {
1120         int i;
1121
1122         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1123
1124         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1125                 u32 offset;
1126
1127                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1128                 BUG_ON(offset == MSR_INVALID);
1129
1130                 add_msr_offset(offset);
1131         }
1132 }
1133
1134 static void svm_enable_lbrv(struct vcpu_svm *svm)
1135 {
1136         u32 *msrpm = svm->msrpm;
1137
1138         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1139         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1140         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1141         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1142         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1143 }
1144
1145 static void svm_disable_lbrv(struct vcpu_svm *svm)
1146 {
1147         u32 *msrpm = svm->msrpm;
1148
1149         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1150         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1151         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1152         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1153         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1154 }
1155
1156 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1157 {
1158         svm->nmi_singlestep = false;
1159
1160         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1161                 /* Clear our flags if they were not set by the guest */
1162                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1163                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1164                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1165                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1166         }
1167 }
1168
1169 /* Note:
1170  * This hash table is used to map VM_ID to a struct kvm_svm,
1171  * when handling AMD IOMMU GALOG notification to schedule in
1172  * a particular vCPU.
1173  */
1174 #define SVM_VM_DATA_HASH_BITS   8
1175 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1176 static u32 next_vm_id = 0;
1177 static bool next_vm_id_wrapped = 0;
1178 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1179
1180 /* Note:
1181  * This function is called from IOMMU driver to notify
1182  * SVM to schedule in a particular vCPU of a particular VM.
1183  */
1184 static int avic_ga_log_notifier(u32 ga_tag)
1185 {
1186         unsigned long flags;
1187         struct kvm_svm *kvm_svm;
1188         struct kvm_vcpu *vcpu = NULL;
1189         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1190         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1191
1192         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1193
1194         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1195         hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1196                 if (kvm_svm->avic_vm_id != vm_id)
1197                         continue;
1198                 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1199                 break;
1200         }
1201         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1202
1203         /* Note:
1204          * At this point, the IOMMU should have already set the pending
1205          * bit in the vAPIC backing page. So, we just need to schedule
1206          * in the vcpu.
1207          */
1208         if (vcpu)
1209                 kvm_vcpu_wake_up(vcpu);
1210
1211         return 0;
1212 }
1213
1214 static __init int sev_hardware_setup(void)
1215 {
1216         struct sev_user_data_status *status;
1217         int rc;
1218
1219         /* Maximum number of encrypted guests supported simultaneously */
1220         max_sev_asid = cpuid_ecx(0x8000001F);
1221
1222         if (!max_sev_asid)
1223                 return 1;
1224
1225         /* Minimum ASID value that should be used for SEV guest */
1226         min_sev_asid = cpuid_edx(0x8000001F);
1227
1228         /* Initialize SEV ASID bitmap */
1229         sev_asid_bitmap = kcalloc(BITS_TO_LONGS(max_sev_asid),
1230                                 sizeof(unsigned long), GFP_KERNEL);
1231         if (!sev_asid_bitmap)
1232                 return 1;
1233
1234         status = kmalloc(sizeof(*status), GFP_KERNEL);
1235         if (!status)
1236                 return 1;
1237
1238         /*
1239          * Check SEV platform status.
1240          *
1241          * PLATFORM_STATUS can be called in any state, if we failed to query
1242          * the PLATFORM status then either PSP firmware does not support SEV
1243          * feature or SEV firmware is dead.
1244          */
1245         rc = sev_platform_status(status, NULL);
1246         if (rc)
1247                 goto err;
1248
1249         pr_info("SEV supported\n");
1250
1251 err:
1252         kfree(status);
1253         return rc;
1254 }
1255
1256 static void grow_ple_window(struct kvm_vcpu *vcpu)
1257 {
1258         struct vcpu_svm *svm = to_svm(vcpu);
1259         struct vmcb_control_area *control = &svm->vmcb->control;
1260         int old = control->pause_filter_count;
1261
1262         control->pause_filter_count = __grow_ple_window(old,
1263                                                         pause_filter_count,
1264                                                         pause_filter_count_grow,
1265                                                         pause_filter_count_max);
1266
1267         if (control->pause_filter_count != old)
1268                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1269
1270         trace_kvm_ple_window_grow(vcpu->vcpu_id,
1271                                   control->pause_filter_count, old);
1272 }
1273
1274 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1275 {
1276         struct vcpu_svm *svm = to_svm(vcpu);
1277         struct vmcb_control_area *control = &svm->vmcb->control;
1278         int old = control->pause_filter_count;
1279
1280         control->pause_filter_count =
1281                                 __shrink_ple_window(old,
1282                                                     pause_filter_count,
1283                                                     pause_filter_count_shrink,
1284                                                     pause_filter_count);
1285         if (control->pause_filter_count != old)
1286                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1287
1288         trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1289                                     control->pause_filter_count, old);
1290 }
1291
1292 static __init int svm_hardware_setup(void)
1293 {
1294         int cpu;
1295         struct page *iopm_pages;
1296         void *iopm_va;
1297         int r;
1298
1299         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1300
1301         if (!iopm_pages)
1302                 return -ENOMEM;
1303
1304         iopm_va = page_address(iopm_pages);
1305         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1306         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1307
1308         init_msrpm_offsets();
1309
1310         if (boot_cpu_has(X86_FEATURE_NX))
1311                 kvm_enable_efer_bits(EFER_NX);
1312
1313         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1314                 kvm_enable_efer_bits(EFER_FFXSR);
1315
1316         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1317                 kvm_has_tsc_control = true;
1318                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1319                 kvm_tsc_scaling_ratio_frac_bits = 32;
1320         }
1321
1322         /* Check for pause filtering support */
1323         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1324                 pause_filter_count = 0;
1325                 pause_filter_thresh = 0;
1326         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1327                 pause_filter_thresh = 0;
1328         }
1329
1330         if (nested) {
1331                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1332                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1333         }
1334
1335         if (sev) {
1336                 if (boot_cpu_has(X86_FEATURE_SEV) &&
1337                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1338                         r = sev_hardware_setup();
1339                         if (r)
1340                                 sev = false;
1341                 } else {
1342                         sev = false;
1343                 }
1344         }
1345
1346         for_each_possible_cpu(cpu) {
1347                 r = svm_cpu_init(cpu);
1348                 if (r)
1349                         goto err;
1350         }
1351
1352         if (!boot_cpu_has(X86_FEATURE_NPT))
1353                 npt_enabled = false;
1354
1355         if (npt_enabled && !npt) {
1356                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1357                 npt_enabled = false;
1358         }
1359
1360         if (npt_enabled) {
1361                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1362                 kvm_enable_tdp();
1363         } else
1364                 kvm_disable_tdp();
1365
1366         if (avic) {
1367                 if (!npt_enabled ||
1368                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1369                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1370                         avic = false;
1371                 } else {
1372                         pr_info("AVIC enabled\n");
1373
1374                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1375                 }
1376         }
1377
1378         if (vls) {
1379                 if (!npt_enabled ||
1380                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1381                     !IS_ENABLED(CONFIG_X86_64)) {
1382                         vls = false;
1383                 } else {
1384                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1385                 }
1386         }
1387
1388         if (vgif) {
1389                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1390                         vgif = false;
1391                 else
1392                         pr_info("Virtual GIF supported\n");
1393         }
1394
1395         return 0;
1396
1397 err:
1398         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1399         iopm_base = 0;
1400         return r;
1401 }
1402
1403 static __exit void svm_hardware_unsetup(void)
1404 {
1405         int cpu;
1406
1407         if (svm_sev_enabled())
1408                 kfree(sev_asid_bitmap);
1409
1410         for_each_possible_cpu(cpu)
1411                 svm_cpu_uninit(cpu);
1412
1413         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1414         iopm_base = 0;
1415 }
1416
1417 static void init_seg(struct vmcb_seg *seg)
1418 {
1419         seg->selector = 0;
1420         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1421                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1422         seg->limit = 0xffff;
1423         seg->base = 0;
1424 }
1425
1426 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1427 {
1428         seg->selector = 0;
1429         seg->attrib = SVM_SELECTOR_P_MASK | type;
1430         seg->limit = 0xffff;
1431         seg->base = 0;
1432 }
1433
1434 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1435 {
1436         struct vcpu_svm *svm = to_svm(vcpu);
1437
1438         if (is_guest_mode(vcpu))
1439                 return svm->nested.hsave->control.tsc_offset;
1440
1441         return vcpu->arch.tsc_offset;
1442 }
1443
1444 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1445 {
1446         struct vcpu_svm *svm = to_svm(vcpu);
1447         u64 g_tsc_offset = 0;
1448
1449         if (is_guest_mode(vcpu)) {
1450                 /* Write L1's TSC offset.  */
1451                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1452                                svm->nested.hsave->control.tsc_offset;
1453                 svm->nested.hsave->control.tsc_offset = offset;
1454         } else
1455                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1456                                            svm->vmcb->control.tsc_offset,
1457                                            offset);
1458
1459         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1460
1461         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1462 }
1463
1464 static void avic_init_vmcb(struct vcpu_svm *svm)
1465 {
1466         struct vmcb *vmcb = svm->vmcb;
1467         struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1468         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1469         phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1470         phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1471
1472         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1473         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1474         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1475         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1476         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1477 }
1478
1479 static void init_vmcb(struct vcpu_svm *svm)
1480 {
1481         struct vmcb_control_area *control = &svm->vmcb->control;
1482         struct vmcb_save_area *save = &svm->vmcb->save;
1483
1484         svm->vcpu.arch.hflags = 0;
1485
1486         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1487         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1488         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1489         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1490         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1491         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1492         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1493                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1494
1495         set_dr_intercepts(svm);
1496
1497         set_exception_intercept(svm, PF_VECTOR);
1498         set_exception_intercept(svm, UD_VECTOR);
1499         set_exception_intercept(svm, MC_VECTOR);
1500         set_exception_intercept(svm, AC_VECTOR);
1501         set_exception_intercept(svm, DB_VECTOR);
1502         /*
1503          * Guest access to VMware backdoor ports could legitimately
1504          * trigger #GP because of TSS I/O permission bitmap.
1505          * We intercept those #GP and allow access to them anyway
1506          * as VMware does.
1507          */
1508         if (enable_vmware_backdoor)
1509                 set_exception_intercept(svm, GP_VECTOR);
1510
1511         set_intercept(svm, INTERCEPT_INTR);
1512         set_intercept(svm, INTERCEPT_NMI);
1513         set_intercept(svm, INTERCEPT_SMI);
1514         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1515         set_intercept(svm, INTERCEPT_RDPMC);
1516         set_intercept(svm, INTERCEPT_CPUID);
1517         set_intercept(svm, INTERCEPT_INVD);
1518         set_intercept(svm, INTERCEPT_INVLPG);
1519         set_intercept(svm, INTERCEPT_INVLPGA);
1520         set_intercept(svm, INTERCEPT_IOIO_PROT);
1521         set_intercept(svm, INTERCEPT_MSR_PROT);
1522         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1523         set_intercept(svm, INTERCEPT_SHUTDOWN);
1524         set_intercept(svm, INTERCEPT_VMRUN);
1525         set_intercept(svm, INTERCEPT_VMMCALL);
1526         set_intercept(svm, INTERCEPT_VMLOAD);
1527         set_intercept(svm, INTERCEPT_VMSAVE);
1528         set_intercept(svm, INTERCEPT_STGI);
1529         set_intercept(svm, INTERCEPT_CLGI);
1530         set_intercept(svm, INTERCEPT_SKINIT);
1531         set_intercept(svm, INTERCEPT_WBINVD);
1532         set_intercept(svm, INTERCEPT_XSETBV);
1533         set_intercept(svm, INTERCEPT_RSM);
1534
1535         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1536                 set_intercept(svm, INTERCEPT_MONITOR);
1537                 set_intercept(svm, INTERCEPT_MWAIT);
1538         }
1539
1540         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1541                 set_intercept(svm, INTERCEPT_HLT);
1542
1543         control->iopm_base_pa = __sme_set(iopm_base);
1544         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1545         control->int_ctl = V_INTR_MASKING_MASK;
1546
1547         init_seg(&save->es);
1548         init_seg(&save->ss);
1549         init_seg(&save->ds);
1550         init_seg(&save->fs);
1551         init_seg(&save->gs);
1552
1553         save->cs.selector = 0xf000;
1554         save->cs.base = 0xffff0000;
1555         /* Executable/Readable Code Segment */
1556         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1557                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1558         save->cs.limit = 0xffff;
1559
1560         save->gdtr.limit = 0xffff;
1561         save->idtr.limit = 0xffff;
1562
1563         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1564         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1565
1566         svm_set_efer(&svm->vcpu, 0);
1567         save->dr6 = 0xffff0ff0;
1568         kvm_set_rflags(&svm->vcpu, 2);
1569         save->rip = 0x0000fff0;
1570         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1571
1572         /*
1573          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1574          * It also updates the guest-visible cr0 value.
1575          */
1576         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1577         kvm_mmu_reset_context(&svm->vcpu);
1578
1579         save->cr4 = X86_CR4_PAE;
1580         /* rdx = ?? */
1581
1582         if (npt_enabled) {
1583                 /* Setup VMCB for Nested Paging */
1584                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1585                 clr_intercept(svm, INTERCEPT_INVLPG);
1586                 clr_exception_intercept(svm, PF_VECTOR);
1587                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1588                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1589                 save->g_pat = svm->vcpu.arch.pat;
1590                 save->cr3 = 0;
1591                 save->cr4 = 0;
1592         }
1593         svm->asid_generation = 0;
1594
1595         svm->nested.vmcb = 0;
1596         svm->vcpu.arch.hflags = 0;
1597
1598         if (pause_filter_count) {
1599                 control->pause_filter_count = pause_filter_count;
1600                 if (pause_filter_thresh)
1601                         control->pause_filter_thresh = pause_filter_thresh;
1602                 set_intercept(svm, INTERCEPT_PAUSE);
1603         } else {
1604                 clr_intercept(svm, INTERCEPT_PAUSE);
1605         }
1606
1607         if (kvm_vcpu_apicv_active(&svm->vcpu))
1608                 avic_init_vmcb(svm);
1609
1610         /*
1611          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1612          * in VMCB and clear intercepts to avoid #VMEXIT.
1613          */
1614         if (vls) {
1615                 clr_intercept(svm, INTERCEPT_VMLOAD);
1616                 clr_intercept(svm, INTERCEPT_VMSAVE);
1617                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1618         }
1619
1620         if (vgif) {
1621                 clr_intercept(svm, INTERCEPT_STGI);
1622                 clr_intercept(svm, INTERCEPT_CLGI);
1623                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1624         }
1625
1626         if (sev_guest(svm->vcpu.kvm)) {
1627                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1628                 clr_exception_intercept(svm, UD_VECTOR);
1629         }
1630
1631         mark_all_dirty(svm->vmcb);
1632
1633         enable_gif(svm);
1634
1635 }
1636
1637 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1638                                        unsigned int index)
1639 {
1640         u64 *avic_physical_id_table;
1641         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1642
1643         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1644                 return NULL;
1645
1646         avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1647
1648         return &avic_physical_id_table[index];
1649 }
1650
1651 /**
1652  * Note:
1653  * AVIC hardware walks the nested page table to check permissions,
1654  * but does not use the SPA address specified in the leaf page
1655  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1656  * field of the VMCB. Therefore, we set up the
1657  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1658  */
1659 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1660 {
1661         struct kvm *kvm = vcpu->kvm;
1662         int ret;
1663
1664         if (kvm->arch.apic_access_page_done)
1665                 return 0;
1666
1667         ret = x86_set_memory_region(kvm,
1668                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1669                                     APIC_DEFAULT_PHYS_BASE,
1670                                     PAGE_SIZE);
1671         if (ret)
1672                 return ret;
1673
1674         kvm->arch.apic_access_page_done = true;
1675         return 0;
1676 }
1677
1678 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1679 {
1680         int ret;
1681         u64 *entry, new_entry;
1682         int id = vcpu->vcpu_id;
1683         struct vcpu_svm *svm = to_svm(vcpu);
1684
1685         ret = avic_init_access_page(vcpu);
1686         if (ret)
1687                 return ret;
1688
1689         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1690                 return -EINVAL;
1691
1692         if (!svm->vcpu.arch.apic->regs)
1693                 return -EINVAL;
1694
1695         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1696
1697         /* Setting AVIC backing page address in the phy APIC ID table */
1698         entry = avic_get_physical_id_entry(vcpu, id);
1699         if (!entry)
1700                 return -EINVAL;
1701
1702         new_entry = READ_ONCE(*entry);
1703         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1704                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1705                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1706         WRITE_ONCE(*entry, new_entry);
1707
1708         svm->avic_physical_id_cache = entry;
1709
1710         return 0;
1711 }
1712
1713 static void __sev_asid_free(int asid)
1714 {
1715         struct svm_cpu_data *sd;
1716         int cpu, pos;
1717
1718         pos = asid - 1;
1719         clear_bit(pos, sev_asid_bitmap);
1720
1721         for_each_possible_cpu(cpu) {
1722                 sd = per_cpu(svm_data, cpu);
1723                 sd->sev_vmcbs[pos] = NULL;
1724         }
1725 }
1726
1727 static void sev_asid_free(struct kvm *kvm)
1728 {
1729         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1730
1731         __sev_asid_free(sev->asid);
1732 }
1733
1734 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1735 {
1736         struct sev_data_decommission *decommission;
1737         struct sev_data_deactivate *data;
1738
1739         if (!handle)
1740                 return;
1741
1742         data = kzalloc(sizeof(*data), GFP_KERNEL);
1743         if (!data)
1744                 return;
1745
1746         /* deactivate handle */
1747         data->handle = handle;
1748         sev_guest_deactivate(data, NULL);
1749
1750         wbinvd_on_all_cpus();
1751         sev_guest_df_flush(NULL);
1752         kfree(data);
1753
1754         decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1755         if (!decommission)
1756                 return;
1757
1758         /* decommission handle */
1759         decommission->handle = handle;
1760         sev_guest_decommission(decommission, NULL);
1761
1762         kfree(decommission);
1763 }
1764
1765 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1766                                     unsigned long ulen, unsigned long *n,
1767                                     int write)
1768 {
1769         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1770         unsigned long npages, npinned, size;
1771         unsigned long locked, lock_limit;
1772         struct page **pages;
1773         unsigned long first, last;
1774
1775         if (ulen == 0 || uaddr + ulen < uaddr)
1776                 return NULL;
1777
1778         /* Calculate number of pages. */
1779         first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1780         last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1781         npages = (last - first + 1);
1782
1783         locked = sev->pages_locked + npages;
1784         lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1785         if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1786                 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1787                 return NULL;
1788         }
1789
1790         /* Avoid using vmalloc for smaller buffers. */
1791         size = npages * sizeof(struct page *);
1792         if (size > PAGE_SIZE)
1793                 pages = vmalloc(size);
1794         else
1795                 pages = kmalloc(size, GFP_KERNEL);
1796
1797         if (!pages)
1798                 return NULL;
1799
1800         /* Pin the user virtual address. */
1801         npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages);
1802         if (npinned != npages) {
1803                 pr_err("SEV: Failure locking %lu pages.\n", npages);
1804                 goto err;
1805         }
1806
1807         *n = npages;
1808         sev->pages_locked = locked;
1809
1810         return pages;
1811
1812 err:
1813         if (npinned > 0)
1814                 release_pages(pages, npinned);
1815
1816         kvfree(pages);
1817         return NULL;
1818 }
1819
1820 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1821                              unsigned long npages)
1822 {
1823         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1824
1825         release_pages(pages, npages);
1826         kvfree(pages);
1827         sev->pages_locked -= npages;
1828 }
1829
1830 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1831 {
1832         uint8_t *page_virtual;
1833         unsigned long i;
1834
1835         if (npages == 0 || pages == NULL)
1836                 return;
1837
1838         for (i = 0; i < npages; i++) {
1839                 page_virtual = kmap_atomic(pages[i]);
1840                 clflush_cache_range(page_virtual, PAGE_SIZE);
1841                 kunmap_atomic(page_virtual);
1842         }
1843 }
1844
1845 static void __unregister_enc_region_locked(struct kvm *kvm,
1846                                            struct enc_region *region)
1847 {
1848         /*
1849          * The guest may change the memory encryption attribute from C=0 -> C=1
1850          * or vice versa for this memory range. Lets make sure caches are
1851          * flushed to ensure that guest data gets written into memory with
1852          * correct C-bit.
1853          */
1854         sev_clflush_pages(region->pages, region->npages);
1855
1856         sev_unpin_memory(kvm, region->pages, region->npages);
1857         list_del(&region->list);
1858         kfree(region);
1859 }
1860
1861 static struct kvm *svm_vm_alloc(void)
1862 {
1863         struct kvm_svm *kvm_svm = vzalloc(sizeof(struct kvm_svm));
1864         return &kvm_svm->kvm;
1865 }
1866
1867 static void svm_vm_free(struct kvm *kvm)
1868 {
1869         vfree(to_kvm_svm(kvm));
1870 }
1871
1872 static void sev_vm_destroy(struct kvm *kvm)
1873 {
1874         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1875         struct list_head *head = &sev->regions_list;
1876         struct list_head *pos, *q;
1877
1878         if (!sev_guest(kvm))
1879                 return;
1880
1881         mutex_lock(&kvm->lock);
1882
1883         /*
1884          * if userspace was terminated before unregistering the memory regions
1885          * then lets unpin all the registered memory.
1886          */
1887         if (!list_empty(head)) {
1888                 list_for_each_safe(pos, q, head) {
1889                         __unregister_enc_region_locked(kvm,
1890                                 list_entry(pos, struct enc_region, list));
1891                 }
1892         }
1893
1894         mutex_unlock(&kvm->lock);
1895
1896         sev_unbind_asid(kvm, sev->handle);
1897         sev_asid_free(kvm);
1898 }
1899
1900 static void avic_vm_destroy(struct kvm *kvm)
1901 {
1902         unsigned long flags;
1903         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1904
1905         if (!avic)
1906                 return;
1907
1908         if (kvm_svm->avic_logical_id_table_page)
1909                 __free_page(kvm_svm->avic_logical_id_table_page);
1910         if (kvm_svm->avic_physical_id_table_page)
1911                 __free_page(kvm_svm->avic_physical_id_table_page);
1912
1913         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1914         hash_del(&kvm_svm->hnode);
1915         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1916 }
1917
1918 static void svm_vm_destroy(struct kvm *kvm)
1919 {
1920         avic_vm_destroy(kvm);
1921         sev_vm_destroy(kvm);
1922 }
1923
1924 static int avic_vm_init(struct kvm *kvm)
1925 {
1926         unsigned long flags;
1927         int err = -ENOMEM;
1928         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1929         struct kvm_svm *k2;
1930         struct page *p_page;
1931         struct page *l_page;
1932         u32 vm_id;
1933
1934         if (!avic)
1935                 return 0;
1936
1937         /* Allocating physical APIC ID table (4KB) */
1938         p_page = alloc_page(GFP_KERNEL);
1939         if (!p_page)
1940                 goto free_avic;
1941
1942         kvm_svm->avic_physical_id_table_page = p_page;
1943         clear_page(page_address(p_page));
1944
1945         /* Allocating logical APIC ID table (4KB) */
1946         l_page = alloc_page(GFP_KERNEL);
1947         if (!l_page)
1948                 goto free_avic;
1949
1950         kvm_svm->avic_logical_id_table_page = l_page;
1951         clear_page(page_address(l_page));
1952
1953         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1954  again:
1955         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1956         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1957                 next_vm_id_wrapped = 1;
1958                 goto again;
1959         }
1960         /* Is it still in use? Only possible if wrapped at least once */
1961         if (next_vm_id_wrapped) {
1962                 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1963                         if (k2->avic_vm_id == vm_id)
1964                                 goto again;
1965                 }
1966         }
1967         kvm_svm->avic_vm_id = vm_id;
1968         hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1969         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1970
1971         return 0;
1972
1973 free_avic:
1974         avic_vm_destroy(kvm);
1975         return err;
1976 }
1977
1978 static inline int
1979 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1980 {
1981         int ret = 0;
1982         unsigned long flags;
1983         struct amd_svm_iommu_ir *ir;
1984         struct vcpu_svm *svm = to_svm(vcpu);
1985
1986         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1987                 return 0;
1988
1989         /*
1990          * Here, we go through the per-vcpu ir_list to update all existing
1991          * interrupt remapping table entry targeting this vcpu.
1992          */
1993         spin_lock_irqsave(&svm->ir_list_lock, flags);
1994
1995         if (list_empty(&svm->ir_list))
1996                 goto out;
1997
1998         list_for_each_entry(ir, &svm->ir_list, node) {
1999                 ret = amd_iommu_update_ga(cpu, r, ir->data);
2000                 if (ret)
2001                         break;
2002         }
2003 out:
2004         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2005         return ret;
2006 }
2007
2008 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2009 {
2010         u64 entry;
2011         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2012         int h_physical_id = kvm_cpu_get_apicid(cpu);
2013         struct vcpu_svm *svm = to_svm(vcpu);
2014
2015         if (!kvm_vcpu_apicv_active(vcpu))
2016                 return;
2017
2018         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
2019                 return;
2020
2021         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2022         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2023
2024         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2025         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2026
2027         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2028         if (svm->avic_is_running)
2029                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2030
2031         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2032         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2033                                         svm->avic_is_running);
2034 }
2035
2036 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2037 {
2038         u64 entry;
2039         struct vcpu_svm *svm = to_svm(vcpu);
2040
2041         if (!kvm_vcpu_apicv_active(vcpu))
2042                 return;
2043
2044         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2045         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2046                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2047
2048         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2049         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2050 }
2051
2052 /**
2053  * This function is called during VCPU halt/unhalt.
2054  */
2055 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2056 {
2057         struct vcpu_svm *svm = to_svm(vcpu);
2058
2059         svm->avic_is_running = is_run;
2060         if (is_run)
2061                 avic_vcpu_load(vcpu, vcpu->cpu);
2062         else
2063                 avic_vcpu_put(vcpu);
2064 }
2065
2066 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2067 {
2068         struct vcpu_svm *svm = to_svm(vcpu);
2069         u32 dummy;
2070         u32 eax = 1;
2071
2072         vcpu->arch.microcode_version = 0x01000065;
2073         svm->spec_ctrl = 0;
2074         svm->virt_spec_ctrl = 0;
2075
2076         if (!init_event) {
2077                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2078                                            MSR_IA32_APICBASE_ENABLE;
2079                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2080                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2081         }
2082         init_vmcb(svm);
2083
2084         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2085         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
2086
2087         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2088                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2089 }
2090
2091 static int avic_init_vcpu(struct vcpu_svm *svm)
2092 {
2093         int ret;
2094
2095         if (!kvm_vcpu_apicv_active(&svm->vcpu))
2096                 return 0;
2097
2098         ret = avic_init_backing_page(&svm->vcpu);
2099         if (ret)
2100                 return ret;
2101
2102         INIT_LIST_HEAD(&svm->ir_list);
2103         spin_lock_init(&svm->ir_list_lock);
2104
2105         return ret;
2106 }
2107
2108 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2109 {
2110         struct vcpu_svm *svm;
2111         struct page *page;
2112         struct page *msrpm_pages;
2113         struct page *hsave_page;
2114         struct page *nested_msrpm_pages;
2115         int err;
2116
2117         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2118         if (!svm) {
2119                 err = -ENOMEM;
2120                 goto out;
2121         }
2122
2123         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2124         if (err)
2125                 goto free_svm;
2126
2127         err = -ENOMEM;
2128         page = alloc_page(GFP_KERNEL);
2129         if (!page)
2130                 goto uninit;
2131
2132         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2133         if (!msrpm_pages)
2134                 goto free_page1;
2135
2136         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2137         if (!nested_msrpm_pages)
2138                 goto free_page2;
2139
2140         hsave_page = alloc_page(GFP_KERNEL);
2141         if (!hsave_page)
2142                 goto free_page3;
2143
2144         err = avic_init_vcpu(svm);
2145         if (err)
2146                 goto free_page4;
2147
2148         /* We initialize this flag to true to make sure that the is_running
2149          * bit would be set the first time the vcpu is loaded.
2150          */
2151         svm->avic_is_running = true;
2152
2153         svm->nested.hsave = page_address(hsave_page);
2154
2155         svm->msrpm = page_address(msrpm_pages);
2156         svm_vcpu_init_msrpm(svm->msrpm);
2157
2158         svm->nested.msrpm = page_address(nested_msrpm_pages);
2159         svm_vcpu_init_msrpm(svm->nested.msrpm);
2160
2161         svm->vmcb = page_address(page);
2162         clear_page(svm->vmcb);
2163         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2164         svm->asid_generation = 0;
2165         init_vmcb(svm);
2166
2167         svm_init_osvw(&svm->vcpu);
2168
2169         return &svm->vcpu;
2170
2171 free_page4:
2172         __free_page(hsave_page);
2173 free_page3:
2174         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2175 free_page2:
2176         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2177 free_page1:
2178         __free_page(page);
2179 uninit:
2180         kvm_vcpu_uninit(&svm->vcpu);
2181 free_svm:
2182         kmem_cache_free(kvm_vcpu_cache, svm);
2183 out:
2184         return ERR_PTR(err);
2185 }
2186
2187 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2188 {
2189         struct vcpu_svm *svm = to_svm(vcpu);
2190
2191         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2192         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2193         __free_page(virt_to_page(svm->nested.hsave));
2194         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2195         kvm_vcpu_uninit(vcpu);
2196         kmem_cache_free(kvm_vcpu_cache, svm);
2197         /*
2198          * The vmcb page can be recycled, causing a false negative in
2199          * svm_vcpu_load(). So do a full IBPB now.
2200          */
2201         indirect_branch_prediction_barrier();
2202 }
2203
2204 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2205 {
2206         struct vcpu_svm *svm = to_svm(vcpu);
2207         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2208         int i;
2209
2210         if (unlikely(cpu != vcpu->cpu)) {
2211                 svm->asid_generation = 0;
2212                 mark_all_dirty(svm->vmcb);
2213         }
2214
2215 #ifdef CONFIG_X86_64
2216         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2217 #endif
2218         savesegment(fs, svm->host.fs);
2219         savesegment(gs, svm->host.gs);
2220         svm->host.ldt = kvm_read_ldt();
2221
2222         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2223                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2224
2225         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2226                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2227                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2228                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
2229                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2230                 }
2231         }
2232         /* This assumes that the kernel never uses MSR_TSC_AUX */
2233         if (static_cpu_has(X86_FEATURE_RDTSCP))
2234                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2235
2236         if (sd->current_vmcb != svm->vmcb) {
2237                 sd->current_vmcb = svm->vmcb;
2238                 indirect_branch_prediction_barrier();
2239         }
2240         avic_vcpu_load(vcpu, cpu);
2241 }
2242
2243 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2244 {
2245         struct vcpu_svm *svm = to_svm(vcpu);
2246         int i;
2247
2248         avic_vcpu_put(vcpu);
2249
2250         ++vcpu->stat.host_state_reload;
2251         kvm_load_ldt(svm->host.ldt);
2252 #ifdef CONFIG_X86_64
2253         loadsegment(fs, svm->host.fs);
2254         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2255         load_gs_index(svm->host.gs);
2256 #else
2257 #ifdef CONFIG_X86_32_LAZY_GS
2258         loadsegment(gs, svm->host.gs);
2259 #endif
2260 #endif
2261         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2262                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2263 }
2264
2265 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2266 {
2267         avic_set_running(vcpu, false);
2268 }
2269
2270 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2271 {
2272         avic_set_running(vcpu, true);
2273 }
2274
2275 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2276 {
2277         struct vcpu_svm *svm = to_svm(vcpu);
2278         unsigned long rflags = svm->vmcb->save.rflags;
2279
2280         if (svm->nmi_singlestep) {
2281                 /* Hide our flags if they were not set by the guest */
2282                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2283                         rflags &= ~X86_EFLAGS_TF;
2284                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2285                         rflags &= ~X86_EFLAGS_RF;
2286         }
2287         return rflags;
2288 }
2289
2290 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2291 {
2292         if (to_svm(vcpu)->nmi_singlestep)
2293                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2294
2295        /*
2296         * Any change of EFLAGS.VM is accompanied by a reload of SS
2297         * (caused by either a task switch or an inter-privilege IRET),
2298         * so we do not need to update the CPL here.
2299         */
2300         to_svm(vcpu)->vmcb->save.rflags = rflags;
2301 }
2302
2303 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2304 {
2305         switch (reg) {
2306         case VCPU_EXREG_PDPTR:
2307                 BUG_ON(!npt_enabled);
2308                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2309                 break;
2310         default:
2311                 BUG();
2312         }
2313 }
2314
2315 static void svm_set_vintr(struct vcpu_svm *svm)
2316 {
2317         set_intercept(svm, INTERCEPT_VINTR);
2318 }
2319
2320 static void svm_clear_vintr(struct vcpu_svm *svm)
2321 {
2322         clr_intercept(svm, INTERCEPT_VINTR);
2323 }
2324
2325 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2326 {
2327         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2328
2329         switch (seg) {
2330         case VCPU_SREG_CS: return &save->cs;
2331         case VCPU_SREG_DS: return &save->ds;
2332         case VCPU_SREG_ES: return &save->es;
2333         case VCPU_SREG_FS: return &save->fs;
2334         case VCPU_SREG_GS: return &save->gs;
2335         case VCPU_SREG_SS: return &save->ss;
2336         case VCPU_SREG_TR: return &save->tr;
2337         case VCPU_SREG_LDTR: return &save->ldtr;
2338         }
2339         BUG();
2340         return NULL;
2341 }
2342
2343 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2344 {
2345         struct vmcb_seg *s = svm_seg(vcpu, seg);
2346
2347         return s->base;
2348 }
2349
2350 static void svm_get_segment(struct kvm_vcpu *vcpu,
2351                             struct kvm_segment *var, int seg)
2352 {
2353         struct vmcb_seg *s = svm_seg(vcpu, seg);
2354
2355         var->base = s->base;
2356         var->limit = s->limit;
2357         var->selector = s->selector;
2358         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2359         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2360         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2361         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2362         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2363         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2364         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2365
2366         /*
2367          * AMD CPUs circa 2014 track the G bit for all segments except CS.
2368          * However, the SVM spec states that the G bit is not observed by the
2369          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2370          * So let's synthesize a legal G bit for all segments, this helps
2371          * running KVM nested. It also helps cross-vendor migration, because
2372          * Intel's vmentry has a check on the 'G' bit.
2373          */
2374         var->g = s->limit > 0xfffff;
2375
2376         /*
2377          * AMD's VMCB does not have an explicit unusable field, so emulate it
2378          * for cross vendor migration purposes by "not present"
2379          */
2380         var->unusable = !var->present;
2381
2382         switch (seg) {
2383         case VCPU_SREG_TR:
2384                 /*
2385                  * Work around a bug where the busy flag in the tr selector
2386                  * isn't exposed
2387                  */
2388                 var->type |= 0x2;
2389                 break;
2390         case VCPU_SREG_DS:
2391         case VCPU_SREG_ES:
2392         case VCPU_SREG_FS:
2393         case VCPU_SREG_GS:
2394                 /*
2395                  * The accessed bit must always be set in the segment
2396                  * descriptor cache, although it can be cleared in the
2397                  * descriptor, the cached bit always remains at 1. Since
2398                  * Intel has a check on this, set it here to support
2399                  * cross-vendor migration.
2400                  */
2401                 if (!var->unusable)
2402                         var->type |= 0x1;
2403                 break;
2404         case VCPU_SREG_SS:
2405                 /*
2406                  * On AMD CPUs sometimes the DB bit in the segment
2407                  * descriptor is left as 1, although the whole segment has
2408                  * been made unusable. Clear it here to pass an Intel VMX
2409                  * entry check when cross vendor migrating.
2410                  */
2411                 if (var->unusable)
2412                         var->db = 0;
2413                 /* This is symmetric with svm_set_segment() */
2414                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2415                 break;
2416         }
2417 }
2418
2419 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2420 {
2421         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2422
2423         return save->cpl;
2424 }
2425
2426 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2427 {
2428         struct vcpu_svm *svm = to_svm(vcpu);
2429
2430         dt->size = svm->vmcb->save.idtr.limit;
2431         dt->address = svm->vmcb->save.idtr.base;
2432 }
2433
2434 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2435 {
2436         struct vcpu_svm *svm = to_svm(vcpu);
2437
2438         svm->vmcb->save.idtr.limit = dt->size;
2439         svm->vmcb->save.idtr.base = dt->address ;
2440         mark_dirty(svm->vmcb, VMCB_DT);
2441 }
2442
2443 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2444 {
2445         struct vcpu_svm *svm = to_svm(vcpu);
2446
2447         dt->size = svm->vmcb->save.gdtr.limit;
2448         dt->address = svm->vmcb->save.gdtr.base;
2449 }
2450
2451 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2452 {
2453         struct vcpu_svm *svm = to_svm(vcpu);
2454
2455         svm->vmcb->save.gdtr.limit = dt->size;
2456         svm->vmcb->save.gdtr.base = dt->address ;
2457         mark_dirty(svm->vmcb, VMCB_DT);
2458 }
2459
2460 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2461 {
2462 }
2463
2464 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2465 {
2466 }
2467
2468 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2469 {
2470 }
2471
2472 static void update_cr0_intercept(struct vcpu_svm *svm)
2473 {
2474         ulong gcr0 = svm->vcpu.arch.cr0;
2475         u64 *hcr0 = &svm->vmcb->save.cr0;
2476
2477         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2478                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2479
2480         mark_dirty(svm->vmcb, VMCB_CR);
2481
2482         if (gcr0 == *hcr0) {
2483                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2484                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2485         } else {
2486                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2487                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2488         }
2489 }
2490
2491 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2492 {
2493         struct vcpu_svm *svm = to_svm(vcpu);
2494
2495 #ifdef CONFIG_X86_64
2496         if (vcpu->arch.efer & EFER_LME) {
2497                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2498                         vcpu->arch.efer |= EFER_LMA;
2499                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2500                 }
2501
2502                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2503                         vcpu->arch.efer &= ~EFER_LMA;
2504                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2505                 }
2506         }
2507 #endif
2508         vcpu->arch.cr0 = cr0;
2509
2510         if (!npt_enabled)
2511                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2512
2513         /*
2514          * re-enable caching here because the QEMU bios
2515          * does not do it - this results in some delay at
2516          * reboot
2517          */
2518         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2519                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2520         svm->vmcb->save.cr0 = cr0;
2521         mark_dirty(svm->vmcb, VMCB_CR);
2522         update_cr0_intercept(svm);
2523 }
2524
2525 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2526 {
2527         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2528         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2529
2530         if (cr4 & X86_CR4_VMXE)
2531                 return 1;
2532
2533         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2534                 svm_flush_tlb(vcpu, true);
2535
2536         vcpu->arch.cr4 = cr4;
2537         if (!npt_enabled)
2538                 cr4 |= X86_CR4_PAE;
2539         cr4 |= host_cr4_mce;
2540         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2541         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2542         return 0;
2543 }
2544
2545 static void svm_set_segment(struct kvm_vcpu *vcpu,
2546                             struct kvm_segment *var, int seg)
2547 {
2548         struct vcpu_svm *svm = to_svm(vcpu);
2549         struct vmcb_seg *s = svm_seg(vcpu, seg);
2550
2551         s->base = var->base;
2552         s->limit = var->limit;
2553         s->selector = var->selector;
2554         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2555         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2556         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2557         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2558         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2559         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2560         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2561         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2562
2563         /*
2564          * This is always accurate, except if SYSRET returned to a segment
2565          * with SS.DPL != 3.  Intel does not have this quirk, and always
2566          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2567          * would entail passing the CPL to userspace and back.
2568          */
2569         if (seg == VCPU_SREG_SS)
2570                 /* This is symmetric with svm_get_segment() */
2571                 svm->vmcb->save.cpl = (var->dpl & 3);
2572
2573         mark_dirty(svm->vmcb, VMCB_SEG);
2574 }
2575
2576 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2577 {
2578         struct vcpu_svm *svm = to_svm(vcpu);
2579
2580         clr_exception_intercept(svm, BP_VECTOR);
2581
2582         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2583                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2584                         set_exception_intercept(svm, BP_VECTOR);
2585         } else
2586                 vcpu->guest_debug = 0;
2587 }
2588
2589 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2590 {
2591         if (sd->next_asid > sd->max_asid) {
2592                 ++sd->asid_generation;
2593                 sd->next_asid = sd->min_asid;
2594                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2595         }
2596
2597         svm->asid_generation = sd->asid_generation;
2598         svm->vmcb->control.asid = sd->next_asid++;
2599
2600         mark_dirty(svm->vmcb, VMCB_ASID);
2601 }
2602
2603 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2604 {
2605         return to_svm(vcpu)->vmcb->save.dr6;
2606 }
2607
2608 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2609 {
2610         struct vcpu_svm *svm = to_svm(vcpu);
2611
2612         svm->vmcb->save.dr6 = value;
2613         mark_dirty(svm->vmcb, VMCB_DR);
2614 }
2615
2616 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2617 {
2618         struct vcpu_svm *svm = to_svm(vcpu);
2619
2620         get_debugreg(vcpu->arch.db[0], 0);
2621         get_debugreg(vcpu->arch.db[1], 1);
2622         get_debugreg(vcpu->arch.db[2], 2);
2623         get_debugreg(vcpu->arch.db[3], 3);
2624         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2625         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2626
2627         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2628         set_dr_intercepts(svm);
2629 }
2630
2631 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2632 {
2633         struct vcpu_svm *svm = to_svm(vcpu);
2634
2635         svm->vmcb->save.dr7 = value;
2636         mark_dirty(svm->vmcb, VMCB_DR);
2637 }
2638
2639 static int pf_interception(struct vcpu_svm *svm)
2640 {
2641         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2642         u64 error_code = svm->vmcb->control.exit_info_1;
2643
2644         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2645                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2646                         svm->vmcb->control.insn_bytes : NULL,
2647                         svm->vmcb->control.insn_len);
2648 }
2649
2650 static int npf_interception(struct vcpu_svm *svm)
2651 {
2652         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2653         u64 error_code = svm->vmcb->control.exit_info_1;
2654
2655         trace_kvm_page_fault(fault_address, error_code);
2656         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2657                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2658                         svm->vmcb->control.insn_bytes : NULL,
2659                         svm->vmcb->control.insn_len);
2660 }
2661
2662 static int db_interception(struct vcpu_svm *svm)
2663 {
2664         struct kvm_run *kvm_run = svm->vcpu.run;
2665
2666         if (!(svm->vcpu.guest_debug &
2667               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2668                 !svm->nmi_singlestep) {
2669                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2670                 return 1;
2671         }
2672
2673         if (svm->nmi_singlestep) {
2674                 disable_nmi_singlestep(svm);
2675         }
2676
2677         if (svm->vcpu.guest_debug &
2678             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2679                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2680                 kvm_run->debug.arch.pc =
2681                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2682                 kvm_run->debug.arch.exception = DB_VECTOR;
2683                 return 0;
2684         }
2685
2686         return 1;
2687 }
2688
2689 static int bp_interception(struct vcpu_svm *svm)
2690 {
2691         struct kvm_run *kvm_run = svm->vcpu.run;
2692
2693         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2694         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2695         kvm_run->debug.arch.exception = BP_VECTOR;
2696         return 0;
2697 }
2698
2699 static int ud_interception(struct vcpu_svm *svm)
2700 {
2701         return handle_ud(&svm->vcpu);
2702 }
2703
2704 static int ac_interception(struct vcpu_svm *svm)
2705 {
2706         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2707         return 1;
2708 }
2709
2710 static int gp_interception(struct vcpu_svm *svm)
2711 {
2712         struct kvm_vcpu *vcpu = &svm->vcpu;
2713         u32 error_code = svm->vmcb->control.exit_info_1;
2714         int er;
2715
2716         WARN_ON_ONCE(!enable_vmware_backdoor);
2717
2718         er = emulate_instruction(vcpu,
2719                 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2720         if (er == EMULATE_USER_EXIT)
2721                 return 0;
2722         else if (er != EMULATE_DONE)
2723                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2724         return 1;
2725 }
2726
2727 static bool is_erratum_383(void)
2728 {
2729         int err, i;
2730         u64 value;
2731
2732         if (!erratum_383_found)
2733                 return false;
2734
2735         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2736         if (err)
2737                 return false;
2738
2739         /* Bit 62 may or may not be set for this mce */
2740         value &= ~(1ULL << 62);
2741
2742         if (value != 0xb600000000010015ULL)
2743                 return false;
2744
2745         /* Clear MCi_STATUS registers */
2746         for (i = 0; i < 6; ++i)
2747                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2748
2749         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2750         if (!err) {
2751                 u32 low, high;
2752
2753                 value &= ~(1ULL << 2);
2754                 low    = lower_32_bits(value);
2755                 high   = upper_32_bits(value);
2756
2757                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2758         }
2759
2760         /* Flush tlb to evict multi-match entries */
2761         __flush_tlb_all();
2762
2763         return true;
2764 }
2765
2766 static void svm_handle_mce(struct vcpu_svm *svm)
2767 {
2768         if (is_erratum_383()) {
2769                 /*
2770                  * Erratum 383 triggered. Guest state is corrupt so kill the
2771                  * guest.
2772                  */
2773                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2774
2775                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2776
2777                 return;
2778         }
2779
2780         /*
2781          * On an #MC intercept the MCE handler is not called automatically in
2782          * the host. So do it by hand here.
2783          */
2784         asm volatile (
2785                 "int $0x12\n");
2786         /* not sure if we ever come back to this point */
2787
2788         return;
2789 }
2790
2791 static int mc_interception(struct vcpu_svm *svm)
2792 {
2793         return 1;
2794 }
2795
2796 static int shutdown_interception(struct vcpu_svm *svm)
2797 {
2798         struct kvm_run *kvm_run = svm->vcpu.run;
2799
2800         /*
2801          * VMCB is undefined after a SHUTDOWN intercept
2802          * so reinitialize it.
2803          */
2804         clear_page(svm->vmcb);
2805         init_vmcb(svm);
2806
2807         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2808         return 0;
2809 }
2810
2811 static int io_interception(struct vcpu_svm *svm)
2812 {
2813         struct kvm_vcpu *vcpu = &svm->vcpu;
2814         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2815         int size, in, string;
2816         unsigned port;
2817
2818         ++svm->vcpu.stat.io_exits;
2819         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2820         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2821         if (string)
2822                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2823
2824         port = io_info >> 16;
2825         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2826         svm->next_rip = svm->vmcb->control.exit_info_2;
2827
2828         return kvm_fast_pio(&svm->vcpu, size, port, in);
2829 }
2830
2831 static int nmi_interception(struct vcpu_svm *svm)
2832 {
2833         return 1;
2834 }
2835
2836 static int intr_interception(struct vcpu_svm *svm)
2837 {
2838         ++svm->vcpu.stat.irq_exits;
2839         return 1;
2840 }
2841
2842 static int nop_on_interception(struct vcpu_svm *svm)
2843 {
2844         return 1;
2845 }
2846
2847 static int halt_interception(struct vcpu_svm *svm)
2848 {
2849         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2850         return kvm_emulate_halt(&svm->vcpu);
2851 }
2852
2853 static int vmmcall_interception(struct vcpu_svm *svm)
2854 {
2855         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2856         return kvm_emulate_hypercall(&svm->vcpu);
2857 }
2858
2859 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2860 {
2861         struct vcpu_svm *svm = to_svm(vcpu);
2862
2863         return svm->nested.nested_cr3;
2864 }
2865
2866 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2867 {
2868         struct vcpu_svm *svm = to_svm(vcpu);
2869         u64 cr3 = svm->nested.nested_cr3;
2870         u64 pdpte;
2871         int ret;
2872
2873         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2874                                        offset_in_page(cr3) + index * 8, 8);
2875         if (ret)
2876                 return 0;
2877         return pdpte;
2878 }
2879
2880 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2881                                    unsigned long root)
2882 {
2883         struct vcpu_svm *svm = to_svm(vcpu);
2884
2885         svm->vmcb->control.nested_cr3 = __sme_set(root);
2886         mark_dirty(svm->vmcb, VMCB_NPT);
2887 }
2888
2889 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2890                                        struct x86_exception *fault)
2891 {
2892         struct vcpu_svm *svm = to_svm(vcpu);
2893
2894         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2895                 /*
2896                  * TODO: track the cause of the nested page fault, and
2897                  * correctly fill in the high bits of exit_info_1.
2898                  */
2899                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2900                 svm->vmcb->control.exit_code_hi = 0;
2901                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2902                 svm->vmcb->control.exit_info_2 = fault->address;
2903         }
2904
2905         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2906         svm->vmcb->control.exit_info_1 |= fault->error_code;
2907
2908         /*
2909          * The present bit is always zero for page structure faults on real
2910          * hardware.
2911          */
2912         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2913                 svm->vmcb->control.exit_info_1 &= ~1;
2914
2915         nested_svm_vmexit(svm);
2916 }
2917
2918 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2919 {
2920         WARN_ON(mmu_is_nested(vcpu));
2921         kvm_init_shadow_mmu(vcpu);
2922         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2923         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2924         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2925         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2926         vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu);
2927         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2928         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2929 }
2930
2931 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2932 {
2933         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2934 }
2935
2936 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2937 {
2938         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2939             !is_paging(&svm->vcpu)) {
2940                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2941                 return 1;
2942         }
2943
2944         if (svm->vmcb->save.cpl) {
2945                 kvm_inject_gp(&svm->vcpu, 0);
2946                 return 1;
2947         }
2948
2949         return 0;
2950 }
2951
2952 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2953                                       bool has_error_code, u32 error_code)
2954 {
2955         int vmexit;
2956
2957         if (!is_guest_mode(&svm->vcpu))
2958                 return 0;
2959
2960         vmexit = nested_svm_intercept(svm);
2961         if (vmexit != NESTED_EXIT_DONE)
2962                 return 0;
2963
2964         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2965         svm->vmcb->control.exit_code_hi = 0;
2966         svm->vmcb->control.exit_info_1 = error_code;
2967
2968         /*
2969          * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2970          * The fix is to add the ancillary datum (CR2 or DR6) to structs
2971          * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2972          * written only when inject_pending_event runs (DR6 would written here
2973          * too).  This should be conditional on a new capability---if the
2974          * capability is disabled, kvm_multiple_exception would write the
2975          * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2976          */
2977         if (svm->vcpu.arch.exception.nested_apf)
2978                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2979         else
2980                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2981
2982         svm->nested.exit_required = true;
2983         return vmexit;
2984 }
2985
2986 /* This function returns true if it is save to enable the irq window */
2987 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2988 {
2989         if (!is_guest_mode(&svm->vcpu))
2990                 return true;
2991
2992         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2993                 return true;
2994
2995         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2996                 return false;
2997
2998         /*
2999          * if vmexit was already requested (by intercepted exception
3000          * for instance) do not overwrite it with "external interrupt"
3001          * vmexit.
3002          */
3003         if (svm->nested.exit_required)
3004                 return false;
3005
3006         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
3007         svm->vmcb->control.exit_info_1 = 0;
3008         svm->vmcb->control.exit_info_2 = 0;
3009
3010         if (svm->nested.intercept & 1ULL) {
3011                 /*
3012                  * The #vmexit can't be emulated here directly because this
3013                  * code path runs with irqs and preemption disabled. A
3014                  * #vmexit emulation might sleep. Only signal request for
3015                  * the #vmexit here.
3016                  */
3017                 svm->nested.exit_required = true;
3018                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3019                 return false;
3020         }
3021
3022         return true;
3023 }
3024
3025 /* This function returns true if it is save to enable the nmi window */
3026 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3027 {
3028         if (!is_guest_mode(&svm->vcpu))
3029                 return true;
3030
3031         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3032                 return true;
3033
3034         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3035         svm->nested.exit_required = true;
3036
3037         return false;
3038 }
3039
3040 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
3041 {
3042         struct page *page;
3043
3044         might_sleep();
3045
3046         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
3047         if (is_error_page(page))
3048                 goto error;
3049
3050         *_page = page;
3051
3052         return kmap(page);
3053
3054 error:
3055         kvm_inject_gp(&svm->vcpu, 0);
3056
3057         return NULL;
3058 }
3059
3060 static void nested_svm_unmap(struct page *page)
3061 {
3062         kunmap(page);
3063         kvm_release_page_dirty(page);
3064 }
3065
3066 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3067 {
3068         unsigned port, size, iopm_len;
3069         u16 val, mask;
3070         u8 start_bit;
3071         u64 gpa;
3072
3073         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3074                 return NESTED_EXIT_HOST;
3075
3076         port = svm->vmcb->control.exit_info_1 >> 16;
3077         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3078                 SVM_IOIO_SIZE_SHIFT;
3079         gpa  = svm->nested.vmcb_iopm + (port / 8);
3080         start_bit = port % 8;
3081         iopm_len = (start_bit + size > 8) ? 2 : 1;
3082         mask = (0xf >> (4 - size)) << start_bit;
3083         val = 0;
3084
3085         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3086                 return NESTED_EXIT_DONE;
3087
3088         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3089 }
3090
3091 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3092 {
3093         u32 offset, msr, value;
3094         int write, mask;
3095
3096         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3097                 return NESTED_EXIT_HOST;
3098
3099         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3100         offset = svm_msrpm_offset(msr);
3101         write  = svm->vmcb->control.exit_info_1 & 1;
3102         mask   = 1 << ((2 * (msr & 0xf)) + write);
3103
3104         if (offset == MSR_INVALID)
3105                 return NESTED_EXIT_DONE;
3106
3107         /* Offset is in 32 bit units but need in 8 bit units */
3108         offset *= 4;
3109
3110         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3111                 return NESTED_EXIT_DONE;
3112
3113         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3114 }
3115
3116 /* DB exceptions for our internal use must not cause vmexit */
3117 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3118 {
3119         unsigned long dr6;
3120
3121         /* if we're not singlestepping, it's not ours */
3122         if (!svm->nmi_singlestep)
3123                 return NESTED_EXIT_DONE;
3124
3125         /* if it's not a singlestep exception, it's not ours */
3126         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3127                 return NESTED_EXIT_DONE;
3128         if (!(dr6 & DR6_BS))
3129                 return NESTED_EXIT_DONE;
3130
3131         /* if the guest is singlestepping, it should get the vmexit */
3132         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3133                 disable_nmi_singlestep(svm);
3134                 return NESTED_EXIT_DONE;
3135         }
3136
3137         /* it's ours, the nested hypervisor must not see this one */
3138         return NESTED_EXIT_HOST;
3139 }
3140
3141 static int nested_svm_exit_special(struct vcpu_svm *svm)
3142 {
3143         u32 exit_code = svm->vmcb->control.exit_code;
3144
3145         switch (exit_code) {
3146         case SVM_EXIT_INTR:
3147         case SVM_EXIT_NMI:
3148         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3149                 return NESTED_EXIT_HOST;
3150         case SVM_EXIT_NPF:
3151                 /* For now we are always handling NPFs when using them */
3152                 if (npt_enabled)
3153                         return NESTED_EXIT_HOST;
3154                 break;
3155         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3156                 /* When we're shadowing, trap PFs, but not async PF */
3157                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3158                         return NESTED_EXIT_HOST;
3159                 break;
3160         default:
3161                 break;
3162         }
3163
3164         return NESTED_EXIT_CONTINUE;
3165 }
3166
3167 /*
3168  * If this function returns true, this #vmexit was already handled
3169  */
3170 static int nested_svm_intercept(struct vcpu_svm *svm)
3171 {
3172         u32 exit_code = svm->vmcb->control.exit_code;
3173         int vmexit = NESTED_EXIT_HOST;
3174
3175         switch (exit_code) {
3176         case SVM_EXIT_MSR:
3177                 vmexit = nested_svm_exit_handled_msr(svm);
3178                 break;
3179         case SVM_EXIT_IOIO:
3180                 vmexit = nested_svm_intercept_ioio(svm);
3181                 break;
3182         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3183                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3184                 if (svm->nested.intercept_cr & bit)
3185                         vmexit = NESTED_EXIT_DONE;
3186                 break;
3187         }
3188         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3189                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3190                 if (svm->nested.intercept_dr & bit)
3191                         vmexit = NESTED_EXIT_DONE;
3192                 break;
3193         }
3194         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3195                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3196                 if (svm->nested.intercept_exceptions & excp_bits) {
3197                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3198                                 vmexit = nested_svm_intercept_db(svm);
3199                         else
3200                                 vmexit = NESTED_EXIT_DONE;
3201                 }
3202                 /* async page fault always cause vmexit */
3203                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3204                          svm->vcpu.arch.exception.nested_apf != 0)
3205                         vmexit = NESTED_EXIT_DONE;
3206                 break;
3207         }
3208         case SVM_EXIT_ERR: {
3209                 vmexit = NESTED_EXIT_DONE;
3210                 break;
3211         }
3212         default: {
3213                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3214                 if (svm->nested.intercept & exit_bits)
3215                         vmexit = NESTED_EXIT_DONE;
3216         }
3217         }
3218
3219         return vmexit;
3220 }
3221
3222 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3223 {
3224         int vmexit;
3225
3226         vmexit = nested_svm_intercept(svm);
3227
3228         if (vmexit == NESTED_EXIT_DONE)
3229                 nested_svm_vmexit(svm);
3230
3231         return vmexit;
3232 }
3233
3234 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3235 {
3236         struct vmcb_control_area *dst  = &dst_vmcb->control;
3237         struct vmcb_control_area *from = &from_vmcb->control;
3238
3239         dst->intercept_cr         = from->intercept_cr;
3240         dst->intercept_dr         = from->intercept_dr;
3241         dst->intercept_exceptions = from->intercept_exceptions;
3242         dst->intercept            = from->intercept;
3243         dst->iopm_base_pa         = from->iopm_base_pa;
3244         dst->msrpm_base_pa        = from->msrpm_base_pa;
3245         dst->tsc_offset           = from->tsc_offset;
3246         dst->asid                 = from->asid;
3247         dst->tlb_ctl              = from->tlb_ctl;
3248         dst->int_ctl              = from->int_ctl;
3249         dst->int_vector           = from->int_vector;
3250         dst->int_state            = from->int_state;
3251         dst->exit_code            = from->exit_code;
3252         dst->exit_code_hi         = from->exit_code_hi;
3253         dst->exit_info_1          = from->exit_info_1;
3254         dst->exit_info_2          = from->exit_info_2;
3255         dst->exit_int_info        = from->exit_int_info;
3256         dst->exit_int_info_err    = from->exit_int_info_err;
3257         dst->nested_ctl           = from->nested_ctl;
3258         dst->event_inj            = from->event_inj;
3259         dst->event_inj_err        = from->event_inj_err;
3260         dst->nested_cr3           = from->nested_cr3;
3261         dst->virt_ext              = from->virt_ext;
3262 }
3263
3264 static int nested_svm_vmexit(struct vcpu_svm *svm)
3265 {
3266         struct vmcb *nested_vmcb;
3267         struct vmcb *hsave = svm->nested.hsave;
3268         struct vmcb *vmcb = svm->vmcb;
3269         struct page *page;
3270
3271         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3272                                        vmcb->control.exit_info_1,
3273                                        vmcb->control.exit_info_2,
3274                                        vmcb->control.exit_int_info,
3275                                        vmcb->control.exit_int_info_err,
3276                                        KVM_ISA_SVM);
3277
3278         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
3279         if (!nested_vmcb)
3280                 return 1;
3281
3282         /* Exit Guest-Mode */
3283         leave_guest_mode(&svm->vcpu);
3284         svm->nested.vmcb = 0;
3285
3286         /* Give the current vmcb to the guest */
3287         disable_gif(svm);
3288
3289         nested_vmcb->save.es     = vmcb->save.es;
3290         nested_vmcb->save.cs     = vmcb->save.cs;
3291         nested_vmcb->save.ss     = vmcb->save.ss;
3292         nested_vmcb->save.ds     = vmcb->save.ds;
3293         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
3294         nested_vmcb->save.idtr   = vmcb->save.idtr;
3295         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
3296         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
3297         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
3298         nested_vmcb->save.cr2    = vmcb->save.cr2;
3299         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
3300         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3301         nested_vmcb->save.rip    = vmcb->save.rip;
3302         nested_vmcb->save.rsp    = vmcb->save.rsp;
3303         nested_vmcb->save.rax    = vmcb->save.rax;
3304         nested_vmcb->save.dr7    = vmcb->save.dr7;
3305         nested_vmcb->save.dr6    = vmcb->save.dr6;
3306         nested_vmcb->save.cpl    = vmcb->save.cpl;
3307
3308         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
3309         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
3310         nested_vmcb->control.int_state         = vmcb->control.int_state;
3311         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
3312         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
3313         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
3314         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
3315         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
3316         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3317
3318         if (svm->nrips_enabled)
3319                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
3320
3321         /*
3322          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3323          * to make sure that we do not lose injected events. So check event_inj
3324          * here and copy it to exit_int_info if it is valid.
3325          * Exit_int_info and event_inj can't be both valid because the case
3326          * below only happens on a VMRUN instruction intercept which has
3327          * no valid exit_int_info set.
3328          */
3329         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3330                 struct vmcb_control_area *nc = &nested_vmcb->control;
3331
3332                 nc->exit_int_info     = vmcb->control.event_inj;
3333                 nc->exit_int_info_err = vmcb->control.event_inj_err;
3334         }
3335
3336         nested_vmcb->control.tlb_ctl           = 0;
3337         nested_vmcb->control.event_inj         = 0;
3338         nested_vmcb->control.event_inj_err     = 0;
3339
3340         /* We always set V_INTR_MASKING and remember the old value in hflags */
3341         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3342                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3343
3344         /* Restore the original control entries */
3345         copy_vmcb_control_area(vmcb, hsave);
3346
3347         svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3348         kvm_clear_exception_queue(&svm->vcpu);
3349         kvm_clear_interrupt_queue(&svm->vcpu);
3350
3351         svm->nested.nested_cr3 = 0;
3352
3353         /* Restore selected save entries */
3354         svm->vmcb->save.es = hsave->save.es;
3355         svm->vmcb->save.cs = hsave->save.cs;
3356         svm->vmcb->save.ss = hsave->save.ss;
3357         svm->vmcb->save.ds = hsave->save.ds;
3358         svm->vmcb->save.gdtr = hsave->save.gdtr;
3359         svm->vmcb->save.idtr = hsave->save.idtr;
3360         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3361         svm_set_efer(&svm->vcpu, hsave->save.efer);
3362         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3363         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3364         if (npt_enabled) {
3365                 svm->vmcb->save.cr3 = hsave->save.cr3;
3366                 svm->vcpu.arch.cr3 = hsave->save.cr3;
3367         } else {
3368                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3369         }
3370         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
3371         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
3372         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
3373         svm->vmcb->save.dr7 = 0;
3374         svm->vmcb->save.cpl = 0;
3375         svm->vmcb->control.exit_int_info = 0;
3376
3377         mark_all_dirty(svm->vmcb);
3378
3379         nested_svm_unmap(page);
3380
3381         nested_svm_uninit_mmu_context(&svm->vcpu);
3382         kvm_mmu_reset_context(&svm->vcpu);
3383         kvm_mmu_load(&svm->vcpu);
3384
3385         return 0;
3386 }
3387
3388 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3389 {
3390         /*
3391          * This function merges the msr permission bitmaps of kvm and the
3392          * nested vmcb. It is optimized in that it only merges the parts where
3393          * the kvm msr permission bitmap may contain zero bits
3394          */
3395         int i;
3396
3397         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3398                 return true;
3399
3400         for (i = 0; i < MSRPM_OFFSETS; i++) {
3401                 u32 value, p;
3402                 u64 offset;
3403
3404                 if (msrpm_offsets[i] == 0xffffffff)
3405                         break;
3406
3407                 p      = msrpm_offsets[i];
3408                 offset = svm->nested.vmcb_msrpm + (p * 4);
3409
3410                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3411                         return false;
3412
3413                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3414         }
3415
3416         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3417
3418         return true;
3419 }
3420
3421 static bool nested_vmcb_checks(struct vmcb *vmcb)
3422 {
3423         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3424                 return false;
3425
3426         if (vmcb->control.asid == 0)
3427                 return false;
3428
3429         if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3430             !npt_enabled)
3431                 return false;
3432
3433         return true;
3434 }
3435
3436 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3437                                  struct vmcb *nested_vmcb, struct page *page)
3438 {
3439         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3440                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3441         else
3442                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3443
3444         if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3445                 kvm_mmu_unload(&svm->vcpu);
3446                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3447                 nested_svm_init_mmu_context(&svm->vcpu);
3448         }
3449
3450         /* Load the nested guest state */
3451         svm->vmcb->save.es = nested_vmcb->save.es;
3452         svm->vmcb->save.cs = nested_vmcb->save.cs;
3453         svm->vmcb->save.ss = nested_vmcb->save.ss;
3454         svm->vmcb->save.ds = nested_vmcb->save.ds;
3455         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3456         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3457         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3458         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3459         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3460         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3461         if (npt_enabled) {
3462                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3463                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3464         } else
3465                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3466
3467         /* Guest paging mode is active - reset mmu */
3468         kvm_mmu_reset_context(&svm->vcpu);
3469
3470         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3471         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3472         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3473         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3474
3475         /* In case we don't even reach vcpu_run, the fields are not updated */
3476         svm->vmcb->save.rax = nested_vmcb->save.rax;
3477         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3478         svm->vmcb->save.rip = nested_vmcb->save.rip;
3479         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3480         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3481         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3482
3483         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3484         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
3485
3486         /* cache intercepts */
3487         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
3488         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
3489         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3490         svm->nested.intercept            = nested_vmcb->control.intercept;
3491
3492         svm_flush_tlb(&svm->vcpu, true);
3493         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3494         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3495                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3496         else
3497                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3498
3499         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3500                 /* We only want the cr8 intercept bits of the guest */
3501                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3502                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3503         }
3504
3505         /* We don't want to see VMMCALLs from a nested guest */
3506         clr_intercept(svm, INTERCEPT_VMMCALL);
3507
3508         svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3509         svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3510
3511         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3512         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3513         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3514         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3515         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3516
3517         nested_svm_unmap(page);
3518
3519         /* Enter Guest-Mode */
3520         enter_guest_mode(&svm->vcpu);
3521
3522         /*
3523          * Merge guest and host intercepts - must be called  with vcpu in
3524          * guest-mode to take affect here
3525          */
3526         recalc_intercepts(svm);
3527
3528         svm->nested.vmcb = vmcb_gpa;
3529
3530         enable_gif(svm);
3531
3532         mark_all_dirty(svm->vmcb);
3533 }
3534
3535 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3536 {
3537         struct vmcb *nested_vmcb;
3538         struct vmcb *hsave = svm->nested.hsave;
3539         struct vmcb *vmcb = svm->vmcb;
3540         struct page *page;
3541         u64 vmcb_gpa;
3542
3543         vmcb_gpa = svm->vmcb->save.rax;
3544
3545         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3546         if (!nested_vmcb)
3547                 return false;
3548
3549         if (!nested_vmcb_checks(nested_vmcb)) {
3550                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3551                 nested_vmcb->control.exit_code_hi = 0;
3552                 nested_vmcb->control.exit_info_1  = 0;
3553                 nested_vmcb->control.exit_info_2  = 0;
3554
3555                 nested_svm_unmap(page);
3556
3557                 return false;
3558         }
3559
3560         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3561                                nested_vmcb->save.rip,
3562                                nested_vmcb->control.int_ctl,
3563                                nested_vmcb->control.event_inj,
3564                                nested_vmcb->control.nested_ctl);
3565
3566         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3567                                     nested_vmcb->control.intercept_cr >> 16,
3568                                     nested_vmcb->control.intercept_exceptions,
3569                                     nested_vmcb->control.intercept);
3570
3571         /* Clear internal status */
3572         kvm_clear_exception_queue(&svm->vcpu);
3573         kvm_clear_interrupt_queue(&svm->vcpu);
3574
3575         /*
3576          * Save the old vmcb, so we don't need to pick what we save, but can
3577          * restore everything when a VMEXIT occurs
3578          */
3579         hsave->save.es     = vmcb->save.es;
3580         hsave->save.cs     = vmcb->save.cs;
3581         hsave->save.ss     = vmcb->save.ss;
3582         hsave->save.ds     = vmcb->save.ds;
3583         hsave->save.gdtr   = vmcb->save.gdtr;
3584         hsave->save.idtr   = vmcb->save.idtr;
3585         hsave->save.efer   = svm->vcpu.arch.efer;
3586         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3587         hsave->save.cr4    = svm->vcpu.arch.cr4;
3588         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3589         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3590         hsave->save.rsp    = vmcb->save.rsp;
3591         hsave->save.rax    = vmcb->save.rax;
3592         if (npt_enabled)
3593                 hsave->save.cr3    = vmcb->save.cr3;
3594         else
3595                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3596
3597         copy_vmcb_control_area(hsave, vmcb);
3598
3599         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3600
3601         return true;
3602 }
3603
3604 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3605 {
3606         to_vmcb->save.fs = from_vmcb->save.fs;
3607         to_vmcb->save.gs = from_vmcb->save.gs;
3608         to_vmcb->save.tr = from_vmcb->save.tr;
3609         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3610         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3611         to_vmcb->save.star = from_vmcb->save.star;
3612         to_vmcb->save.lstar = from_vmcb->save.lstar;
3613         to_vmcb->save.cstar = from_vmcb->save.cstar;
3614         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3615         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3616         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3617         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3618 }
3619
3620 static int vmload_interception(struct vcpu_svm *svm)
3621 {
3622         struct vmcb *nested_vmcb;
3623         struct page *page;
3624         int ret;
3625
3626         if (nested_svm_check_permissions(svm))
3627                 return 1;
3628
3629         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3630         if (!nested_vmcb)
3631                 return 1;
3632
3633         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3634         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3635
3636         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3637         nested_svm_unmap(page);
3638
3639         return ret;
3640 }
3641
3642 static int vmsave_interception(struct vcpu_svm *svm)
3643 {
3644         struct vmcb *nested_vmcb;
3645         struct page *page;
3646         int ret;
3647
3648         if (nested_svm_check_permissions(svm))
3649                 return 1;
3650
3651         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3652         if (!nested_vmcb)
3653                 return 1;
3654
3655         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3656         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3657
3658         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3659         nested_svm_unmap(page);
3660
3661         return ret;
3662 }
3663
3664 static int vmrun_interception(struct vcpu_svm *svm)
3665 {
3666         if (nested_svm_check_permissions(svm))
3667                 return 1;
3668
3669         /* Save rip after vmrun instruction */
3670         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3671
3672         if (!nested_svm_vmrun(svm))
3673                 return 1;
3674
3675         if (!nested_svm_vmrun_msrpm(svm))
3676                 goto failed;
3677
3678         return 1;
3679
3680 failed:
3681
3682         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3683         svm->vmcb->control.exit_code_hi = 0;
3684         svm->vmcb->control.exit_info_1  = 0;
3685         svm->vmcb->control.exit_info_2  = 0;
3686
3687         nested_svm_vmexit(svm);
3688
3689         return 1;
3690 }
3691
3692 static int stgi_interception(struct vcpu_svm *svm)
3693 {
3694         int ret;
3695
3696         if (nested_svm_check_permissions(svm))
3697                 return 1;
3698
3699         /*
3700          * If VGIF is enabled, the STGI intercept is only added to
3701          * detect the opening of the SMI/NMI window; remove it now.
3702          */
3703         if (vgif_enabled(svm))
3704                 clr_intercept(svm, INTERCEPT_STGI);
3705
3706         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3707         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3708         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3709
3710         enable_gif(svm);
3711
3712         return ret;
3713 }
3714
3715 static int clgi_interception(struct vcpu_svm *svm)
3716 {
3717         int ret;
3718
3719         if (nested_svm_check_permissions(svm))
3720                 return 1;
3721
3722         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3723         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3724
3725         disable_gif(svm);
3726
3727         /* After a CLGI no interrupts should come */
3728         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3729                 svm_clear_vintr(svm);
3730                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3731                 mark_dirty(svm->vmcb, VMCB_INTR);
3732         }
3733
3734         return ret;
3735 }
3736
3737 static int invlpga_interception(struct vcpu_svm *svm)
3738 {
3739         struct kvm_vcpu *vcpu = &svm->vcpu;
3740
3741         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3742                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3743
3744         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3745         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3746
3747         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3748         return kvm_skip_emulated_instruction(&svm->vcpu);
3749 }
3750
3751 static int skinit_interception(struct vcpu_svm *svm)
3752 {
3753         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3754
3755         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3756         return 1;
3757 }
3758
3759 static int wbinvd_interception(struct vcpu_svm *svm)
3760 {
3761         return kvm_emulate_wbinvd(&svm->vcpu);
3762 }
3763
3764 static int xsetbv_interception(struct vcpu_svm *svm)
3765 {
3766         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3767         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3768
3769         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3770                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3771                 return kvm_skip_emulated_instruction(&svm->vcpu);
3772         }
3773
3774         return 1;
3775 }
3776
3777 static int task_switch_interception(struct vcpu_svm *svm)
3778 {
3779         u16 tss_selector;
3780         int reason;
3781         int int_type = svm->vmcb->control.exit_int_info &
3782                 SVM_EXITINTINFO_TYPE_MASK;
3783         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3784         uint32_t type =
3785                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3786         uint32_t idt_v =
3787                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3788         bool has_error_code = false;
3789         u32 error_code = 0;
3790
3791         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3792
3793         if (svm->vmcb->control.exit_info_2 &
3794             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3795                 reason = TASK_SWITCH_IRET;
3796         else if (svm->vmcb->control.exit_info_2 &
3797                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3798                 reason = TASK_SWITCH_JMP;
3799         else if (idt_v)
3800                 reason = TASK_SWITCH_GATE;
3801         else
3802                 reason = TASK_SWITCH_CALL;
3803
3804         if (reason == TASK_SWITCH_GATE) {
3805                 switch (type) {
3806                 case SVM_EXITINTINFO_TYPE_NMI:
3807                         svm->vcpu.arch.nmi_injected = false;
3808                         break;
3809                 case SVM_EXITINTINFO_TYPE_EXEPT:
3810                         if (svm->vmcb->control.exit_info_2 &
3811                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3812                                 has_error_code = true;
3813                                 error_code =
3814                                         (u32)svm->vmcb->control.exit_info_2;
3815                         }
3816                         kvm_clear_exception_queue(&svm->vcpu);
3817                         break;
3818                 case SVM_EXITINTINFO_TYPE_INTR:
3819                         kvm_clear_interrupt_queue(&svm->vcpu);
3820                         break;
3821                 default:
3822                         break;
3823                 }
3824         }
3825
3826         if (reason != TASK_SWITCH_GATE ||
3827             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3828             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3829              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3830                 skip_emulated_instruction(&svm->vcpu);
3831
3832         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3833                 int_vec = -1;
3834
3835         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3836                                 has_error_code, error_code) == EMULATE_FAIL) {
3837                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3838                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3839                 svm->vcpu.run->internal.ndata = 0;
3840                 return 0;
3841         }
3842         return 1;
3843 }
3844
3845 static int cpuid_interception(struct vcpu_svm *svm)
3846 {
3847         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3848         return kvm_emulate_cpuid(&svm->vcpu);
3849 }
3850
3851 static int iret_interception(struct vcpu_svm *svm)
3852 {
3853         ++svm->vcpu.stat.nmi_window_exits;
3854         clr_intercept(svm, INTERCEPT_IRET);
3855         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3856         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3857         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3858         return 1;
3859 }
3860
3861 static int invlpg_interception(struct vcpu_svm *svm)
3862 {
3863         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3864                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3865
3866         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3867         return kvm_skip_emulated_instruction(&svm->vcpu);
3868 }
3869
3870 static int emulate_on_interception(struct vcpu_svm *svm)
3871 {
3872         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3873 }
3874
3875 static int rsm_interception(struct vcpu_svm *svm)
3876 {
3877         return x86_emulate_instruction(&svm->vcpu, 0, 0,
3878                                        rsm_ins_bytes, 2) == EMULATE_DONE;
3879 }
3880
3881 static int rdpmc_interception(struct vcpu_svm *svm)
3882 {
3883         int err;
3884
3885         if (!static_cpu_has(X86_FEATURE_NRIPS))
3886                 return emulate_on_interception(svm);
3887
3888         err = kvm_rdpmc(&svm->vcpu);
3889         return kvm_complete_insn_gp(&svm->vcpu, err);
3890 }
3891
3892 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3893                                             unsigned long val)
3894 {
3895         unsigned long cr0 = svm->vcpu.arch.cr0;
3896         bool ret = false;
3897         u64 intercept;
3898
3899         intercept = svm->nested.intercept;
3900
3901         if (!is_guest_mode(&svm->vcpu) ||
3902             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3903                 return false;
3904
3905         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3906         val &= ~SVM_CR0_SELECTIVE_MASK;
3907
3908         if (cr0 ^ val) {
3909                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3910                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3911         }
3912
3913         return ret;
3914 }
3915
3916 #define CR_VALID (1ULL << 63)
3917
3918 static int cr_interception(struct vcpu_svm *svm)
3919 {
3920         int reg, cr;
3921         unsigned long val;
3922         int err;
3923
3924         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3925                 return emulate_on_interception(svm);
3926
3927         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3928                 return emulate_on_interception(svm);
3929
3930         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3931         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3932                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3933         else
3934                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3935
3936         err = 0;
3937         if (cr >= 16) { /* mov to cr */
3938                 cr -= 16;
3939                 val = kvm_register_read(&svm->vcpu, reg);
3940                 switch (cr) {
3941                 case 0:
3942                         if (!check_selective_cr0_intercepted(svm, val))
3943                                 err = kvm_set_cr0(&svm->vcpu, val);
3944                         else
3945                                 return 1;
3946
3947                         break;
3948                 case 3:
3949                         err = kvm_set_cr3(&svm->vcpu, val);
3950                         break;
3951                 case 4:
3952                         err = kvm_set_cr4(&svm->vcpu, val);
3953                         break;
3954                 case 8:
3955                         err = kvm_set_cr8(&svm->vcpu, val);
3956                         break;
3957                 default:
3958                         WARN(1, "unhandled write to CR%d", cr);
3959                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3960                         return 1;
3961                 }
3962         } else { /* mov from cr */
3963                 switch (cr) {
3964                 case 0:
3965                         val = kvm_read_cr0(&svm->vcpu);
3966                         break;
3967                 case 2:
3968                         val = svm->vcpu.arch.cr2;
3969                         break;
3970                 case 3:
3971                         val = kvm_read_cr3(&svm->vcpu);
3972                         break;
3973                 case 4:
3974                         val = kvm_read_cr4(&svm->vcpu);
3975                         break;
3976                 case 8:
3977                         val = kvm_get_cr8(&svm->vcpu);
3978                         break;
3979                 default:
3980                         WARN(1, "unhandled read from CR%d", cr);
3981                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3982                         return 1;
3983                 }
3984                 kvm_register_write(&svm->vcpu, reg, val);
3985         }
3986         return kvm_complete_insn_gp(&svm->vcpu, err);
3987 }
3988
3989 static int dr_interception(struct vcpu_svm *svm)
3990 {
3991         int reg, dr;
3992         unsigned long val;
3993
3994         if (svm->vcpu.guest_debug == 0) {
3995                 /*
3996                  * No more DR vmexits; force a reload of the debug registers
3997                  * and reenter on this instruction.  The next vmexit will
3998                  * retrieve the full state of the debug registers.
3999                  */
4000                 clr_dr_intercepts(svm);
4001                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4002                 return 1;
4003         }
4004
4005         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4006                 return emulate_on_interception(svm);
4007
4008         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4009         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4010
4011         if (dr >= 16) { /* mov to DRn */
4012                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4013                         return 1;
4014                 val = kvm_register_read(&svm->vcpu, reg);
4015                 kvm_set_dr(&svm->vcpu, dr - 16, val);
4016         } else {
4017                 if (!kvm_require_dr(&svm->vcpu, dr))
4018                         return 1;
4019                 kvm_get_dr(&svm->vcpu, dr, &val);
4020                 kvm_register_write(&svm->vcpu, reg, val);
4021         }
4022
4023         return kvm_skip_emulated_instruction(&svm->vcpu);
4024 }
4025
4026 static int cr8_write_interception(struct vcpu_svm *svm)
4027 {
4028         struct kvm_run *kvm_run = svm->vcpu.run;
4029         int r;
4030
4031         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4032         /* instruction emulation calls kvm_set_cr8() */
4033         r = cr_interception(svm);
4034         if (lapic_in_kernel(&svm->vcpu))
4035                 return r;
4036         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4037                 return r;
4038         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4039         return 0;
4040 }
4041
4042 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4043 {
4044         msr->data = 0;
4045
4046         switch (msr->index) {
4047         case MSR_F10H_DECFG:
4048                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4049                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4050                 break;
4051         default:
4052                 return 1;
4053         }
4054
4055         return 0;
4056 }
4057
4058 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4059 {
4060         struct vcpu_svm *svm = to_svm(vcpu);
4061
4062         switch (msr_info->index) {
4063         case MSR_STAR:
4064                 msr_info->data = svm->vmcb->save.star;
4065                 break;
4066 #ifdef CONFIG_X86_64
4067         case MSR_LSTAR:
4068                 msr_info->data = svm->vmcb->save.lstar;
4069                 break;
4070         case MSR_CSTAR:
4071                 msr_info->data = svm->vmcb->save.cstar;
4072                 break;
4073         case MSR_KERNEL_GS_BASE:
4074                 msr_info->data = svm->vmcb->save.kernel_gs_base;
4075                 break;
4076         case MSR_SYSCALL_MASK:
4077                 msr_info->data = svm->vmcb->save.sfmask;
4078                 break;
4079 #endif
4080         case MSR_IA32_SYSENTER_CS:
4081                 msr_info->data = svm->vmcb->save.sysenter_cs;
4082                 break;
4083         case MSR_IA32_SYSENTER_EIP:
4084                 msr_info->data = svm->sysenter_eip;
4085                 break;
4086         case MSR_IA32_SYSENTER_ESP:
4087                 msr_info->data = svm->sysenter_esp;
4088                 break;
4089         case MSR_TSC_AUX:
4090                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4091                         return 1;
4092                 msr_info->data = svm->tsc_aux;
4093                 break;
4094         /*
4095          * Nobody will change the following 5 values in the VMCB so we can
4096          * safely return them on rdmsr. They will always be 0 until LBRV is
4097          * implemented.
4098          */
4099         case MSR_IA32_DEBUGCTLMSR:
4100                 msr_info->data = svm->vmcb->save.dbgctl;
4101                 break;
4102         case MSR_IA32_LASTBRANCHFROMIP:
4103                 msr_info->data = svm->vmcb->save.br_from;
4104                 break;
4105         case MSR_IA32_LASTBRANCHTOIP:
4106                 msr_info->data = svm->vmcb->save.br_to;
4107                 break;
4108         case MSR_IA32_LASTINTFROMIP:
4109                 msr_info->data = svm->vmcb->save.last_excp_from;
4110                 break;
4111         case MSR_IA32_LASTINTTOIP:
4112                 msr_info->data = svm->vmcb->save.last_excp_to;
4113                 break;
4114         case MSR_VM_HSAVE_PA:
4115                 msr_info->data = svm->nested.hsave_msr;
4116                 break;
4117         case MSR_VM_CR:
4118                 msr_info->data = svm->nested.vm_cr_msr;
4119                 break;
4120         case MSR_IA32_SPEC_CTRL:
4121                 if (!msr_info->host_initiated &&
4122                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4123                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4124                         return 1;
4125
4126                 msr_info->data = svm->spec_ctrl;
4127                 break;
4128         case MSR_AMD64_VIRT_SPEC_CTRL:
4129                 if (!msr_info->host_initiated &&
4130                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4131                         return 1;
4132
4133                 msr_info->data = svm->virt_spec_ctrl;
4134                 break;
4135         case MSR_F15H_IC_CFG: {
4136
4137                 int family, model;
4138
4139                 family = guest_cpuid_family(vcpu);
4140                 model  = guest_cpuid_model(vcpu);
4141
4142                 if (family < 0 || model < 0)
4143                         return kvm_get_msr_common(vcpu, msr_info);
4144
4145                 msr_info->data = 0;
4146
4147                 if (family == 0x15 &&
4148                     (model >= 0x2 && model < 0x20))
4149                         msr_info->data = 0x1E;
4150                 }
4151                 break;
4152         case MSR_F10H_DECFG:
4153                 msr_info->data = svm->msr_decfg;
4154                 break;
4155         default:
4156                 return kvm_get_msr_common(vcpu, msr_info);
4157         }
4158         return 0;
4159 }
4160
4161 static int rdmsr_interception(struct vcpu_svm *svm)
4162 {
4163         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4164         struct msr_data msr_info;
4165
4166         msr_info.index = ecx;
4167         msr_info.host_initiated = false;
4168         if (svm_get_msr(&svm->vcpu, &msr_info)) {
4169                 trace_kvm_msr_read_ex(ecx);
4170                 kvm_inject_gp(&svm->vcpu, 0);
4171                 return 1;
4172         } else {
4173                 trace_kvm_msr_read(ecx, msr_info.data);
4174
4175                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
4176                                    msr_info.data & 0xffffffff);
4177                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
4178                                    msr_info.data >> 32);
4179                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4180                 return kvm_skip_emulated_instruction(&svm->vcpu);
4181         }
4182 }
4183
4184 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4185 {
4186         struct vcpu_svm *svm = to_svm(vcpu);
4187         int svm_dis, chg_mask;
4188
4189         if (data & ~SVM_VM_CR_VALID_MASK)
4190                 return 1;
4191
4192         chg_mask = SVM_VM_CR_VALID_MASK;
4193
4194         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4195                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4196
4197         svm->nested.vm_cr_msr &= ~chg_mask;
4198         svm->nested.vm_cr_msr |= (data & chg_mask);
4199
4200         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4201
4202         /* check for svm_disable while efer.svme is set */
4203         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4204                 return 1;
4205
4206         return 0;
4207 }
4208
4209 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4210 {
4211         struct vcpu_svm *svm = to_svm(vcpu);
4212
4213         u32 ecx = msr->index;
4214         u64 data = msr->data;
4215         switch (ecx) {
4216         case MSR_IA32_CR_PAT:
4217                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4218                         return 1;
4219                 vcpu->arch.pat = data;
4220                 svm->vmcb->save.g_pat = data;
4221                 mark_dirty(svm->vmcb, VMCB_NPT);
4222                 break;
4223         case MSR_IA32_SPEC_CTRL:
4224                 if (!msr->host_initiated &&
4225                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4226                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4227                         return 1;
4228
4229                 /* The STIBP bit doesn't fault even if it's not advertised */
4230                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4231                         return 1;
4232
4233                 svm->spec_ctrl = data;
4234
4235                 if (!data)
4236                         break;
4237
4238                 /*
4239                  * For non-nested:
4240                  * When it's written (to non-zero) for the first time, pass
4241                  * it through.
4242                  *
4243                  * For nested:
4244                  * The handling of the MSR bitmap for L2 guests is done in
4245                  * nested_svm_vmrun_msrpm.
4246                  * We update the L1 MSR bit as well since it will end up
4247                  * touching the MSR anyway now.
4248                  */
4249                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4250                 break;
4251         case MSR_IA32_PRED_CMD:
4252                 if (!msr->host_initiated &&
4253                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4254                         return 1;
4255
4256                 if (data & ~PRED_CMD_IBPB)
4257                         return 1;
4258
4259                 if (!data)
4260                         break;
4261
4262                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4263                 if (is_guest_mode(vcpu))
4264                         break;
4265                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4266                 break;
4267         case MSR_AMD64_VIRT_SPEC_CTRL:
4268                 if (!msr->host_initiated &&
4269                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4270                         return 1;
4271
4272                 if (data & ~SPEC_CTRL_SSBD)
4273                         return 1;
4274
4275                 svm->virt_spec_ctrl = data;
4276                 break;
4277         case MSR_STAR:
4278                 svm->vmcb->save.star = data;
4279                 break;
4280 #ifdef CONFIG_X86_64
4281         case MSR_LSTAR:
4282                 svm->vmcb->save.lstar = data;
4283                 break;
4284         case MSR_CSTAR:
4285                 svm->vmcb->save.cstar = data;
4286                 break;
4287         case MSR_KERNEL_GS_BASE:
4288                 svm->vmcb->save.kernel_gs_base = data;
4289                 break;
4290         case MSR_SYSCALL_MASK:
4291                 svm->vmcb->save.sfmask = data;
4292                 break;
4293 #endif
4294         case MSR_IA32_SYSENTER_CS:
4295                 svm->vmcb->save.sysenter_cs = data;
4296                 break;
4297         case MSR_IA32_SYSENTER_EIP:
4298                 svm->sysenter_eip = data;
4299                 svm->vmcb->save.sysenter_eip = data;
4300                 break;
4301         case MSR_IA32_SYSENTER_ESP:
4302                 svm->sysenter_esp = data;
4303                 svm->vmcb->save.sysenter_esp = data;
4304                 break;
4305         case MSR_TSC_AUX:
4306                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4307                         return 1;
4308
4309                 /*
4310                  * This is rare, so we update the MSR here instead of using
4311                  * direct_access_msrs.  Doing that would require a rdmsr in
4312                  * svm_vcpu_put.
4313                  */
4314                 svm->tsc_aux = data;
4315                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4316                 break;
4317         case MSR_IA32_DEBUGCTLMSR:
4318                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4319                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4320                                     __func__, data);
4321                         break;
4322                 }
4323                 if (data & DEBUGCTL_RESERVED_BITS)
4324                         return 1;
4325
4326                 svm->vmcb->save.dbgctl = data;
4327                 mark_dirty(svm->vmcb, VMCB_LBR);
4328                 if (data & (1ULL<<0))
4329                         svm_enable_lbrv(svm);
4330                 else
4331                         svm_disable_lbrv(svm);
4332                 break;
4333         case MSR_VM_HSAVE_PA:
4334                 svm->nested.hsave_msr = data;
4335                 break;
4336         case MSR_VM_CR:
4337                 return svm_set_vm_cr(vcpu, data);
4338         case MSR_VM_IGNNE:
4339                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4340                 break;
4341         case MSR_F10H_DECFG: {
4342                 struct kvm_msr_entry msr_entry;
4343
4344                 msr_entry.index = msr->index;
4345                 if (svm_get_msr_feature(&msr_entry))
4346                         return 1;
4347
4348                 /* Check the supported bits */
4349                 if (data & ~msr_entry.data)
4350                         return 1;
4351
4352                 /* Don't allow the guest to change a bit, #GP */
4353                 if (!msr->host_initiated && (data ^ msr_entry.data))
4354                         return 1;
4355
4356                 svm->msr_decfg = data;
4357                 break;
4358         }
4359         case MSR_IA32_APICBASE:
4360                 if (kvm_vcpu_apicv_active(vcpu))
4361                         avic_update_vapic_bar(to_svm(vcpu), data);
4362                 /* Follow through */
4363         default:
4364                 return kvm_set_msr_common(vcpu, msr);
4365         }
4366         return 0;
4367 }
4368
4369 static int wrmsr_interception(struct vcpu_svm *svm)
4370 {
4371         struct msr_data msr;
4372         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4373         u64 data = kvm_read_edx_eax(&svm->vcpu);
4374
4375         msr.data = data;
4376         msr.index = ecx;
4377         msr.host_initiated = false;
4378
4379         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4380         if (kvm_set_msr(&svm->vcpu, &msr)) {
4381                 trace_kvm_msr_write_ex(ecx, data);
4382                 kvm_inject_gp(&svm->vcpu, 0);
4383                 return 1;
4384         } else {
4385                 trace_kvm_msr_write(ecx, data);
4386                 return kvm_skip_emulated_instruction(&svm->vcpu);
4387         }
4388 }
4389
4390 static int msr_interception(struct vcpu_svm *svm)
4391 {
4392         if (svm->vmcb->control.exit_info_1)
4393                 return wrmsr_interception(svm);
4394         else
4395                 return rdmsr_interception(svm);
4396 }
4397
4398 static int interrupt_window_interception(struct vcpu_svm *svm)
4399 {
4400         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4401         svm_clear_vintr(svm);
4402         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4403         mark_dirty(svm->vmcb, VMCB_INTR);
4404         ++svm->vcpu.stat.irq_window_exits;
4405         return 1;
4406 }
4407
4408 static int pause_interception(struct vcpu_svm *svm)
4409 {
4410         struct kvm_vcpu *vcpu = &svm->vcpu;
4411         bool in_kernel = (svm_get_cpl(vcpu) == 0);
4412
4413         if (pause_filter_thresh)
4414                 grow_ple_window(vcpu);
4415
4416         kvm_vcpu_on_spin(vcpu, in_kernel);
4417         return 1;
4418 }
4419
4420 static int nop_interception(struct vcpu_svm *svm)
4421 {
4422         return kvm_skip_emulated_instruction(&(svm->vcpu));
4423 }
4424
4425 static int monitor_interception(struct vcpu_svm *svm)
4426 {
4427         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4428         return nop_interception(svm);
4429 }
4430
4431 static int mwait_interception(struct vcpu_svm *svm)
4432 {
4433         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4434         return nop_interception(svm);
4435 }
4436
4437 enum avic_ipi_failure_cause {
4438         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4439         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4440         AVIC_IPI_FAILURE_INVALID_TARGET,
4441         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4442 };
4443
4444 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4445 {
4446         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4447         u32 icrl = svm->vmcb->control.exit_info_1;
4448         u32 id = svm->vmcb->control.exit_info_2 >> 32;
4449         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4450         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4451
4452         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4453
4454         switch (id) {
4455         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4456                 /*
4457                  * AVIC hardware handles the generation of
4458                  * IPIs when the specified Message Type is Fixed
4459                  * (also known as fixed delivery mode) and
4460                  * the Trigger Mode is edge-triggered. The hardware
4461                  * also supports self and broadcast delivery modes
4462                  * specified via the Destination Shorthand(DSH)
4463                  * field of the ICRL. Logical and physical APIC ID
4464                  * formats are supported. All other IPI types cause
4465                  * a #VMEXIT, which needs to emulated.
4466                  */
4467                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4468                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4469                 break;
4470         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4471                 int i;
4472                 struct kvm_vcpu *vcpu;
4473                 struct kvm *kvm = svm->vcpu.kvm;
4474                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4475
4476                 /*
4477                  * At this point, we expect that the AVIC HW has already
4478                  * set the appropriate IRR bits on the valid target
4479                  * vcpus. So, we just need to kick the appropriate vcpu.
4480                  */
4481                 kvm_for_each_vcpu(i, vcpu, kvm) {
4482                         bool m = kvm_apic_match_dest(vcpu, apic,
4483                                                      icrl & KVM_APIC_SHORT_MASK,
4484                                                      GET_APIC_DEST_FIELD(icrh),
4485                                                      icrl & KVM_APIC_DEST_MASK);
4486
4487                         if (m && !avic_vcpu_is_running(vcpu))
4488                                 kvm_vcpu_wake_up(vcpu);
4489                 }
4490                 break;
4491         }
4492         case AVIC_IPI_FAILURE_INVALID_TARGET:
4493                 break;
4494         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4495                 WARN_ONCE(1, "Invalid backing page\n");
4496                 break;
4497         default:
4498                 pr_err("Unknown IPI interception\n");
4499         }
4500
4501         return 1;
4502 }
4503
4504 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4505 {
4506         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4507         int index;
4508         u32 *logical_apic_id_table;
4509         int dlid = GET_APIC_LOGICAL_ID(ldr);
4510
4511         if (!dlid)
4512                 return NULL;
4513
4514         if (flat) { /* flat */
4515                 index = ffs(dlid) - 1;
4516                 if (index > 7)
4517                         return NULL;
4518         } else { /* cluster */
4519                 int cluster = (dlid & 0xf0) >> 4;
4520                 int apic = ffs(dlid & 0x0f) - 1;
4521
4522                 if ((apic < 0) || (apic > 7) ||
4523                     (cluster >= 0xf))
4524                         return NULL;
4525                 index = (cluster << 2) + apic;
4526         }
4527
4528         logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4529
4530         return &logical_apic_id_table[index];
4531 }
4532
4533 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
4534                           bool valid)
4535 {
4536         bool flat;
4537         u32 *entry, new_entry;
4538
4539         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4540         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4541         if (!entry)
4542                 return -EINVAL;
4543
4544         new_entry = READ_ONCE(*entry);
4545         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4546         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4547         if (valid)
4548                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4549         else
4550                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4551         WRITE_ONCE(*entry, new_entry);
4552
4553         return 0;
4554 }
4555
4556 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4557 {
4558         int ret;
4559         struct vcpu_svm *svm = to_svm(vcpu);
4560         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4561
4562         if (!ldr)
4563                 return 1;
4564
4565         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
4566         if (ret && svm->ldr_reg) {
4567                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
4568                 svm->ldr_reg = 0;
4569         } else {
4570                 svm->ldr_reg = ldr;
4571         }
4572         return ret;
4573 }
4574
4575 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4576 {
4577         u64 *old, *new;
4578         struct vcpu_svm *svm = to_svm(vcpu);
4579         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4580         u32 id = (apic_id_reg >> 24) & 0xff;
4581
4582         if (vcpu->vcpu_id == id)
4583                 return 0;
4584
4585         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4586         new = avic_get_physical_id_entry(vcpu, id);
4587         if (!new || !old)
4588                 return 1;
4589
4590         /* We need to move physical_id_entry to new offset */
4591         *new = *old;
4592         *old = 0ULL;
4593         to_svm(vcpu)->avic_physical_id_cache = new;
4594
4595         /*
4596          * Also update the guest physical APIC ID in the logical
4597          * APIC ID table entry if already setup the LDR.
4598          */
4599         if (svm->ldr_reg)
4600                 avic_handle_ldr_update(vcpu);
4601
4602         return 0;
4603 }
4604
4605 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4606 {
4607         struct vcpu_svm *svm = to_svm(vcpu);
4608         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4609         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4610         u32 mod = (dfr >> 28) & 0xf;
4611
4612         /*
4613          * We assume that all local APICs are using the same type.
4614          * If this changes, we need to flush the AVIC logical
4615          * APID id table.
4616          */
4617         if (kvm_svm->ldr_mode == mod)
4618                 return 0;
4619
4620         clear_page(page_address(kvm_svm->avic_logical_id_table_page));
4621         kvm_svm->ldr_mode = mod;
4622
4623         if (svm->ldr_reg)
4624                 avic_handle_ldr_update(vcpu);
4625         return 0;
4626 }
4627
4628 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4629 {
4630         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4631         u32 offset = svm->vmcb->control.exit_info_1 &
4632                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4633
4634         switch (offset) {
4635         case APIC_ID:
4636                 if (avic_handle_apic_id_update(&svm->vcpu))
4637                         return 0;
4638                 break;
4639         case APIC_LDR:
4640                 if (avic_handle_ldr_update(&svm->vcpu))
4641                         return 0;
4642                 break;
4643         case APIC_DFR:
4644                 avic_handle_dfr_update(&svm->vcpu);
4645                 break;
4646         default:
4647                 break;
4648         }
4649
4650         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4651
4652         return 1;
4653 }
4654
4655 static bool is_avic_unaccelerated_access_trap(u32 offset)
4656 {
4657         bool ret = false;
4658
4659         switch (offset) {
4660         case APIC_ID:
4661         case APIC_EOI:
4662         case APIC_RRR:
4663         case APIC_LDR:
4664         case APIC_DFR:
4665         case APIC_SPIV:
4666         case APIC_ESR:
4667         case APIC_ICR:
4668         case APIC_LVTT:
4669         case APIC_LVTTHMR:
4670         case APIC_LVTPC:
4671         case APIC_LVT0:
4672         case APIC_LVT1:
4673         case APIC_LVTERR:
4674         case APIC_TMICT:
4675         case APIC_TDCR:
4676                 ret = true;
4677                 break;
4678         default:
4679                 break;
4680         }
4681         return ret;
4682 }
4683
4684 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4685 {
4686         int ret = 0;
4687         u32 offset = svm->vmcb->control.exit_info_1 &
4688                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4689         u32 vector = svm->vmcb->control.exit_info_2 &
4690                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4691         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4692                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4693         bool trap = is_avic_unaccelerated_access_trap(offset);
4694
4695         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4696                                             trap, write, vector);
4697         if (trap) {
4698                 /* Handling Trap */
4699                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4700                 ret = avic_unaccel_trap_write(svm);
4701         } else {
4702                 /* Handling Fault */
4703                 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4704         }
4705
4706         return ret;
4707 }
4708
4709 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4710         [SVM_EXIT_READ_CR0]                     = cr_interception,
4711         [SVM_EXIT_READ_CR3]                     = cr_interception,
4712         [SVM_EXIT_READ_CR4]                     = cr_interception,
4713         [SVM_EXIT_READ_CR8]                     = cr_interception,
4714         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4715         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4716         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4717         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4718         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4719         [SVM_EXIT_READ_DR0]                     = dr_interception,
4720         [SVM_EXIT_READ_DR1]                     = dr_interception,
4721         [SVM_EXIT_READ_DR2]                     = dr_interception,
4722         [SVM_EXIT_READ_DR3]                     = dr_interception,
4723         [SVM_EXIT_READ_DR4]                     = dr_interception,
4724         [SVM_EXIT_READ_DR5]                     = dr_interception,
4725         [SVM_EXIT_READ_DR6]                     = dr_interception,
4726         [SVM_EXIT_READ_DR7]                     = dr_interception,
4727         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4728         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4729         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4730         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4731         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4732         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4733         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4734         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4735         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4736         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4737         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4738         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4739         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4740         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4741         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
4742         [SVM_EXIT_INTR]                         = intr_interception,
4743         [SVM_EXIT_NMI]                          = nmi_interception,
4744         [SVM_EXIT_SMI]                          = nop_on_interception,
4745         [SVM_EXIT_INIT]                         = nop_on_interception,
4746         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4747         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4748         [SVM_EXIT_CPUID]                        = cpuid_interception,
4749         [SVM_EXIT_IRET]                         = iret_interception,
4750         [SVM_EXIT_INVD]                         = emulate_on_interception,
4751         [SVM_EXIT_PAUSE]                        = pause_interception,
4752         [SVM_EXIT_HLT]                          = halt_interception,
4753         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4754         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4755         [SVM_EXIT_IOIO]                         = io_interception,
4756         [SVM_EXIT_MSR]                          = msr_interception,
4757         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4758         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4759         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4760         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4761         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4762         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4763         [SVM_EXIT_STGI]                         = stgi_interception,
4764         [SVM_EXIT_CLGI]                         = clgi_interception,
4765         [SVM_EXIT_SKINIT]                       = skinit_interception,
4766         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4767         [SVM_EXIT_MONITOR]                      = monitor_interception,
4768         [SVM_EXIT_MWAIT]                        = mwait_interception,
4769         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4770         [SVM_EXIT_NPF]                          = npf_interception,
4771         [SVM_EXIT_RSM]                          = rsm_interception,
4772         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4773         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4774 };
4775
4776 static void dump_vmcb(struct kvm_vcpu *vcpu)
4777 {
4778         struct vcpu_svm *svm = to_svm(vcpu);
4779         struct vmcb_control_area *control = &svm->vmcb->control;
4780         struct vmcb_save_area *save = &svm->vmcb->save;
4781
4782         pr_err("VMCB Control Area:\n");
4783         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4784         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4785         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4786         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4787         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4788         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4789         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4790         pr_err("%-20s%d\n", "pause filter threshold:",
4791                control->pause_filter_thresh);
4792         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4793         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4794         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4795         pr_err("%-20s%d\n", "asid:", control->asid);
4796         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4797         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4798         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4799         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4800         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4801         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4802         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4803         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4804         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4805         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4806         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4807         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4808         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4809         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4810         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4811         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4812         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4813         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4814         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4815         pr_err("VMCB State Save Area:\n");
4816         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4817                "es:",
4818                save->es.selector, save->es.attrib,
4819                save->es.limit, save->es.base);
4820         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4821                "cs:",
4822                save->cs.selector, save->cs.attrib,
4823                save->cs.limit, save->cs.base);
4824         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4825                "ss:",
4826                save->ss.selector, save->ss.attrib,
4827                save->ss.limit, save->ss.base);
4828         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4829                "ds:",
4830                save->ds.selector, save->ds.attrib,
4831                save->ds.limit, save->ds.base);
4832         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4833                "fs:",
4834                save->fs.selector, save->fs.attrib,
4835                save->fs.limit, save->fs.base);
4836         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4837                "gs:",
4838                save->gs.selector, save->gs.attrib,
4839                save->gs.limit, save->gs.base);
4840         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4841                "gdtr:",
4842                save->gdtr.selector, save->gdtr.attrib,
4843                save->gdtr.limit, save->gdtr.base);
4844         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4845                "ldtr:",
4846                save->ldtr.selector, save->ldtr.attrib,
4847                save->ldtr.limit, save->ldtr.base);
4848         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4849                "idtr:",
4850                save->idtr.selector, save->idtr.attrib,
4851                save->idtr.limit, save->idtr.base);
4852         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4853                "tr:",
4854                save->tr.selector, save->tr.attrib,
4855                save->tr.limit, save->tr.base);
4856         pr_err("cpl:            %d                efer:         %016llx\n",
4857                 save->cpl, save->efer);
4858         pr_err("%-15s %016llx %-13s %016llx\n",
4859                "cr0:", save->cr0, "cr2:", save->cr2);
4860         pr_err("%-15s %016llx %-13s %016llx\n",
4861                "cr3:", save->cr3, "cr4:", save->cr4);
4862         pr_err("%-15s %016llx %-13s %016llx\n",
4863                "dr6:", save->dr6, "dr7:", save->dr7);
4864         pr_err("%-15s %016llx %-13s %016llx\n",
4865                "rip:", save->rip, "rflags:", save->rflags);
4866         pr_err("%-15s %016llx %-13s %016llx\n",
4867                "rsp:", save->rsp, "rax:", save->rax);
4868         pr_err("%-15s %016llx %-13s %016llx\n",
4869                "star:", save->star, "lstar:", save->lstar);
4870         pr_err("%-15s %016llx %-13s %016llx\n",
4871                "cstar:", save->cstar, "sfmask:", save->sfmask);
4872         pr_err("%-15s %016llx %-13s %016llx\n",
4873                "kernel_gs_base:", save->kernel_gs_base,
4874                "sysenter_cs:", save->sysenter_cs);
4875         pr_err("%-15s %016llx %-13s %016llx\n",
4876                "sysenter_esp:", save->sysenter_esp,
4877                "sysenter_eip:", save->sysenter_eip);
4878         pr_err("%-15s %016llx %-13s %016llx\n",
4879                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4880         pr_err("%-15s %016llx %-13s %016llx\n",
4881                "br_from:", save->br_from, "br_to:", save->br_to);
4882         pr_err("%-15s %016llx %-13s %016llx\n",
4883                "excp_from:", save->last_excp_from,
4884                "excp_to:", save->last_excp_to);
4885 }
4886
4887 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4888 {
4889         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4890
4891         *info1 = control->exit_info_1;
4892         *info2 = control->exit_info_2;
4893 }
4894
4895 static int handle_exit(struct kvm_vcpu *vcpu)
4896 {
4897         struct vcpu_svm *svm = to_svm(vcpu);
4898         struct kvm_run *kvm_run = vcpu->run;
4899         u32 exit_code = svm->vmcb->control.exit_code;
4900
4901         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4902
4903         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4904                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4905         if (npt_enabled)
4906                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4907
4908         if (unlikely(svm->nested.exit_required)) {
4909                 nested_svm_vmexit(svm);
4910                 svm->nested.exit_required = false;
4911
4912                 return 1;
4913         }
4914
4915         if (is_guest_mode(vcpu)) {
4916                 int vmexit;
4917
4918                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4919                                         svm->vmcb->control.exit_info_1,
4920                                         svm->vmcb->control.exit_info_2,
4921                                         svm->vmcb->control.exit_int_info,
4922                                         svm->vmcb->control.exit_int_info_err,
4923                                         KVM_ISA_SVM);
4924
4925                 vmexit = nested_svm_exit_special(svm);
4926
4927                 if (vmexit == NESTED_EXIT_CONTINUE)
4928                         vmexit = nested_svm_exit_handled(svm);
4929
4930                 if (vmexit == NESTED_EXIT_DONE)
4931                         return 1;
4932         }
4933
4934         svm_complete_interrupts(svm);
4935
4936         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4937                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4938                 kvm_run->fail_entry.hardware_entry_failure_reason
4939                         = svm->vmcb->control.exit_code;
4940                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4941                 dump_vmcb(vcpu);
4942                 return 0;
4943         }
4944
4945         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4946             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4947             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4948             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4949                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4950                        "exit_code 0x%x\n",
4951                        __func__, svm->vmcb->control.exit_int_info,
4952                        exit_code);
4953
4954         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4955             || !svm_exit_handlers[exit_code]) {
4956                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4957                 kvm_queue_exception(vcpu, UD_VECTOR);
4958                 return 1;
4959         }
4960
4961         return svm_exit_handlers[exit_code](svm);
4962 }
4963
4964 static void reload_tss(struct kvm_vcpu *vcpu)
4965 {
4966         int cpu = raw_smp_processor_id();
4967
4968         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4969         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4970         load_TR_desc();
4971 }
4972
4973 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
4974 {
4975         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4976         int asid = sev_get_asid(svm->vcpu.kvm);
4977
4978         /* Assign the asid allocated with this SEV guest */
4979         svm->vmcb->control.asid = asid;
4980
4981         /*
4982          * Flush guest TLB:
4983          *
4984          * 1) when different VMCB for the same ASID is to be run on the same host CPU.
4985          * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
4986          */
4987         if (sd->sev_vmcbs[asid] == svm->vmcb &&
4988             svm->last_cpu == cpu)
4989                 return;
4990
4991         svm->last_cpu = cpu;
4992         sd->sev_vmcbs[asid] = svm->vmcb;
4993         svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4994         mark_dirty(svm->vmcb, VMCB_ASID);
4995 }
4996
4997 static void pre_svm_run(struct vcpu_svm *svm)
4998 {
4999         int cpu = raw_smp_processor_id();
5000
5001         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5002
5003         if (sev_guest(svm->vcpu.kvm))
5004                 return pre_sev_run(svm, cpu);
5005
5006         /* FIXME: handle wraparound of asid_generation */
5007         if (svm->asid_generation != sd->asid_generation)
5008                 new_asid(svm, sd);
5009 }
5010
5011 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5012 {
5013         struct vcpu_svm *svm = to_svm(vcpu);
5014
5015         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5016         vcpu->arch.hflags |= HF_NMI_MASK;
5017         set_intercept(svm, INTERCEPT_IRET);
5018         ++vcpu->stat.nmi_injections;
5019 }
5020
5021 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5022 {
5023         struct vmcb_control_area *control;
5024
5025         /* The following fields are ignored when AVIC is enabled */
5026         control = &svm->vmcb->control;
5027         control->int_vector = irq;
5028         control->int_ctl &= ~V_INTR_PRIO_MASK;
5029         control->int_ctl |= V_IRQ_MASK |
5030                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5031         mark_dirty(svm->vmcb, VMCB_INTR);
5032 }
5033
5034 static void svm_set_irq(struct kvm_vcpu *vcpu)
5035 {
5036         struct vcpu_svm *svm = to_svm(vcpu);
5037
5038         BUG_ON(!(gif_set(svm)));
5039
5040         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5041         ++vcpu->stat.irq_injections;
5042
5043         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5044                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5045 }
5046
5047 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5048 {
5049         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5050 }
5051
5052 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5053 {
5054         struct vcpu_svm *svm = to_svm(vcpu);
5055
5056         if (svm_nested_virtualize_tpr(vcpu) ||
5057             kvm_vcpu_apicv_active(vcpu))
5058                 return;
5059
5060         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5061
5062         if (irr == -1)
5063                 return;
5064
5065         if (tpr >= irr)
5066                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5067 }
5068
5069 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5070 {
5071         return;
5072 }
5073
5074 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5075 {
5076         return avic && irqchip_split(vcpu->kvm);
5077 }
5078
5079 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5080 {
5081 }
5082
5083 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5084 {
5085 }
5086
5087 /* Note: Currently only used by Hyper-V. */
5088 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5089 {
5090         struct vcpu_svm *svm = to_svm(vcpu);
5091         struct vmcb *vmcb = svm->vmcb;
5092
5093         if (!kvm_vcpu_apicv_active(&svm->vcpu))
5094                 return;
5095
5096         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5097         mark_dirty(vmcb, VMCB_INTR);
5098 }
5099
5100 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5101 {
5102         return;
5103 }
5104
5105 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5106 {
5107         kvm_lapic_set_irr(vec, vcpu->arch.apic);
5108         smp_mb__after_atomic();
5109
5110         if (avic_vcpu_is_running(vcpu))
5111                 wrmsrl(SVM_AVIC_DOORBELL,
5112                        kvm_cpu_get_apicid(vcpu->cpu));
5113         else
5114                 kvm_vcpu_wake_up(vcpu);
5115 }
5116
5117 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5118 {
5119         unsigned long flags;
5120         struct amd_svm_iommu_ir *cur;
5121
5122         spin_lock_irqsave(&svm->ir_list_lock, flags);
5123         list_for_each_entry(cur, &svm->ir_list, node) {
5124                 if (cur->data != pi->ir_data)
5125                         continue;
5126                 list_del(&cur->node);
5127                 kfree(cur);
5128                 break;
5129         }
5130         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5131 }
5132
5133 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5134 {
5135         int ret = 0;
5136         unsigned long flags;
5137         struct amd_svm_iommu_ir *ir;
5138
5139         /**
5140          * In some cases, the existing irte is updaed and re-set,
5141          * so we need to check here if it's already been * added
5142          * to the ir_list.
5143          */
5144         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5145                 struct kvm *kvm = svm->vcpu.kvm;
5146                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5147                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5148                 struct vcpu_svm *prev_svm;
5149
5150                 if (!prev_vcpu) {
5151                         ret = -EINVAL;
5152                         goto out;
5153                 }
5154
5155                 prev_svm = to_svm(prev_vcpu);
5156                 svm_ir_list_del(prev_svm, pi);
5157         }
5158
5159         /**
5160          * Allocating new amd_iommu_pi_data, which will get
5161          * add to the per-vcpu ir_list.
5162          */
5163         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
5164         if (!ir) {
5165                 ret = -ENOMEM;
5166                 goto out;
5167         }
5168         ir->data = pi->ir_data;
5169
5170         spin_lock_irqsave(&svm->ir_list_lock, flags);
5171         list_add(&ir->node, &svm->ir_list);
5172         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5173 out:
5174         return ret;
5175 }
5176
5177 /**
5178  * Note:
5179  * The HW cannot support posting multicast/broadcast
5180  * interrupts to a vCPU. So, we still use legacy interrupt
5181  * remapping for these kind of interrupts.
5182  *
5183  * For lowest-priority interrupts, we only support
5184  * those with single CPU as the destination, e.g. user
5185  * configures the interrupts via /proc/irq or uses
5186  * irqbalance to make the interrupts single-CPU.
5187  */
5188 static int
5189 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5190                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5191 {
5192         struct kvm_lapic_irq irq;
5193         struct kvm_vcpu *vcpu = NULL;
5194
5195         kvm_set_msi_irq(kvm, e, &irq);
5196
5197         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5198                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5199                          __func__, irq.vector);
5200                 return -1;
5201         }
5202
5203         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5204                  irq.vector);
5205         *svm = to_svm(vcpu);
5206         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5207         vcpu_info->vector = irq.vector;
5208
5209         return 0;
5210 }
5211
5212 /*
5213  * svm_update_pi_irte - set IRTE for Posted-Interrupts
5214  *
5215  * @kvm: kvm
5216  * @host_irq: host irq of the interrupt
5217  * @guest_irq: gsi of the interrupt
5218  * @set: set or unset PI
5219  * returns 0 on success, < 0 on failure
5220  */
5221 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5222                               uint32_t guest_irq, bool set)
5223 {
5224         struct kvm_kernel_irq_routing_entry *e;
5225         struct kvm_irq_routing_table *irq_rt;
5226         int idx, ret = -EINVAL;
5227
5228         if (!kvm_arch_has_assigned_device(kvm) ||
5229             !irq_remapping_cap(IRQ_POSTING_CAP))
5230                 return 0;
5231
5232         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5233                  __func__, host_irq, guest_irq, set);
5234
5235         idx = srcu_read_lock(&kvm->irq_srcu);
5236         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5237         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5238
5239         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5240                 struct vcpu_data vcpu_info;
5241                 struct vcpu_svm *svm = NULL;
5242
5243                 if (e->type != KVM_IRQ_ROUTING_MSI)
5244                         continue;
5245
5246                 /**
5247                  * Here, we setup with legacy mode in the following cases:
5248                  * 1. When cannot target interrupt to a specific vcpu.
5249                  * 2. Unsetting posted interrupt.
5250                  * 3. APIC virtialization is disabled for the vcpu.
5251                  */
5252                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5253                     kvm_vcpu_apicv_active(&svm->vcpu)) {
5254                         struct amd_iommu_pi_data pi;
5255
5256                         /* Try to enable guest_mode in IRTE */
5257                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5258                                             AVIC_HPA_MASK);
5259                         pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5260                                                      svm->vcpu.vcpu_id);
5261                         pi.is_guest_mode = true;
5262                         pi.vcpu_data = &vcpu_info;
5263                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5264
5265                         /**
5266                          * Here, we successfully setting up vcpu affinity in
5267                          * IOMMU guest mode. Now, we need to store the posted
5268                          * interrupt information in a per-vcpu ir_list so that
5269                          * we can reference to them directly when we update vcpu
5270                          * scheduling information in IOMMU irte.
5271                          */
5272                         if (!ret && pi.is_guest_mode)
5273                                 svm_ir_list_add(svm, &pi);
5274                 } else {
5275                         /* Use legacy mode in IRTE */
5276                         struct amd_iommu_pi_data pi;
5277
5278                         /**
5279                          * Here, pi is used to:
5280                          * - Tell IOMMU to use legacy mode for this interrupt.
5281                          * - Retrieve ga_tag of prior interrupt remapping data.
5282                          */
5283                         pi.is_guest_mode = false;
5284                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5285
5286                         /**
5287                          * Check if the posted interrupt was previously
5288                          * setup with the guest_mode by checking if the ga_tag
5289                          * was cached. If so, we need to clean up the per-vcpu
5290                          * ir_list.
5291                          */
5292                         if (!ret && pi.prev_ga_tag) {
5293                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5294                                 struct kvm_vcpu *vcpu;
5295
5296                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
5297                                 if (vcpu)
5298                                         svm_ir_list_del(to_svm(vcpu), &pi);
5299                         }
5300                 }
5301
5302                 if (!ret && svm) {
5303                         trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5304                                                  e->gsi, vcpu_info.vector,
5305                                                  vcpu_info.pi_desc_addr, set);
5306                 }
5307
5308                 if (ret < 0) {
5309                         pr_err("%s: failed to update PI IRTE\n", __func__);
5310                         goto out;
5311                 }
5312         }
5313
5314         ret = 0;
5315 out:
5316         srcu_read_unlock(&kvm->irq_srcu, idx);
5317         return ret;
5318 }
5319
5320 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5321 {
5322         struct vcpu_svm *svm = to_svm(vcpu);
5323         struct vmcb *vmcb = svm->vmcb;
5324         int ret;
5325         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5326               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5327         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5328
5329         return ret;
5330 }
5331
5332 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5333 {
5334         struct vcpu_svm *svm = to_svm(vcpu);
5335
5336         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5337 }
5338
5339 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5340 {
5341         struct vcpu_svm *svm = to_svm(vcpu);
5342
5343         if (masked) {
5344                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5345                 set_intercept(svm, INTERCEPT_IRET);
5346         } else {
5347                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5348                 clr_intercept(svm, INTERCEPT_IRET);
5349         }
5350 }
5351
5352 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5353 {
5354         struct vcpu_svm *svm = to_svm(vcpu);
5355         struct vmcb *vmcb = svm->vmcb;
5356         int ret;
5357
5358         if (!gif_set(svm) ||
5359              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5360                 return 0;
5361
5362         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5363
5364         if (is_guest_mode(vcpu))
5365                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5366
5367         return ret;
5368 }
5369
5370 static void enable_irq_window(struct kvm_vcpu *vcpu)
5371 {
5372         struct vcpu_svm *svm = to_svm(vcpu);
5373
5374         if (kvm_vcpu_apicv_active(vcpu))
5375                 return;
5376
5377         /*
5378          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5379          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
5380          * get that intercept, this function will be called again though and
5381          * we'll get the vintr intercept. However, if the vGIF feature is
5382          * enabled, the STGI interception will not occur. Enable the irq
5383          * window under the assumption that the hardware will set the GIF.
5384          */
5385         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5386                 svm_set_vintr(svm);
5387                 svm_inject_irq(svm, 0x0);
5388         }
5389 }
5390
5391 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5392 {
5393         struct vcpu_svm *svm = to_svm(vcpu);
5394
5395         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5396             == HF_NMI_MASK)
5397                 return; /* IRET will cause a vm exit */
5398
5399         if (!gif_set(svm)) {
5400                 if (vgif_enabled(svm))
5401                         set_intercept(svm, INTERCEPT_STGI);
5402                 return; /* STGI will cause a vm exit */
5403         }
5404
5405         if (svm->nested.exit_required)
5406                 return; /* we're not going to run the guest yet */
5407
5408         /*
5409          * Something prevents NMI from been injected. Single step over possible
5410          * problem (IRET or exception injection or interrupt shadow)
5411          */
5412         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5413         svm->nmi_singlestep = true;
5414         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5415 }
5416
5417 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5418 {
5419         return 0;
5420 }
5421
5422 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5423 {
5424         return 0;
5425 }
5426
5427 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5428 {
5429         struct vcpu_svm *svm = to_svm(vcpu);
5430
5431         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5432                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5433         else
5434                 svm->asid_generation--;
5435 }
5436
5437 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5438 {
5439         struct vcpu_svm *svm = to_svm(vcpu);
5440
5441         invlpga(gva, svm->vmcb->control.asid);
5442 }
5443
5444 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5445 {
5446 }
5447
5448 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5449 {
5450         struct vcpu_svm *svm = to_svm(vcpu);
5451
5452         if (svm_nested_virtualize_tpr(vcpu))
5453                 return;
5454
5455         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5456                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5457                 kvm_set_cr8(vcpu, cr8);
5458         }
5459 }
5460
5461 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5462 {
5463         struct vcpu_svm *svm = to_svm(vcpu);
5464         u64 cr8;
5465
5466         if (svm_nested_virtualize_tpr(vcpu) ||
5467             kvm_vcpu_apicv_active(vcpu))
5468                 return;
5469
5470         cr8 = kvm_get_cr8(vcpu);
5471         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5472         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5473 }
5474
5475 static void svm_complete_interrupts(struct vcpu_svm *svm)
5476 {
5477         u8 vector;
5478         int type;
5479         u32 exitintinfo = svm->vmcb->control.exit_int_info;
5480         unsigned int3_injected = svm->int3_injected;
5481
5482         svm->int3_injected = 0;
5483
5484         /*
5485          * If we've made progress since setting HF_IRET_MASK, we've
5486          * executed an IRET and can allow NMI injection.
5487          */
5488         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5489             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5490                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5491                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5492         }
5493
5494         svm->vcpu.arch.nmi_injected = false;
5495         kvm_clear_exception_queue(&svm->vcpu);
5496         kvm_clear_interrupt_queue(&svm->vcpu);
5497
5498         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5499                 return;
5500
5501         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5502
5503         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5504         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5505
5506         switch (type) {
5507         case SVM_EXITINTINFO_TYPE_NMI:
5508                 svm->vcpu.arch.nmi_injected = true;
5509                 break;
5510         case SVM_EXITINTINFO_TYPE_EXEPT:
5511                 /*
5512                  * In case of software exceptions, do not reinject the vector,
5513                  * but re-execute the instruction instead. Rewind RIP first
5514                  * if we emulated INT3 before.
5515                  */
5516                 if (kvm_exception_is_soft(vector)) {
5517                         if (vector == BP_VECTOR && int3_injected &&
5518                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5519                                 kvm_rip_write(&svm->vcpu,
5520                                               kvm_rip_read(&svm->vcpu) -
5521                                               int3_injected);
5522                         break;
5523                 }
5524                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5525                         u32 err = svm->vmcb->control.exit_int_info_err;
5526                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
5527
5528                 } else
5529                         kvm_requeue_exception(&svm->vcpu, vector);
5530                 break;
5531         case SVM_EXITINTINFO_TYPE_INTR:
5532                 kvm_queue_interrupt(&svm->vcpu, vector, false);
5533                 break;
5534         default:
5535                 break;
5536         }
5537 }
5538
5539 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5540 {
5541         struct vcpu_svm *svm = to_svm(vcpu);
5542         struct vmcb_control_area *control = &svm->vmcb->control;
5543
5544         control->exit_int_info = control->event_inj;
5545         control->exit_int_info_err = control->event_inj_err;
5546         control->event_inj = 0;
5547         svm_complete_interrupts(svm);
5548 }
5549
5550 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5551 {
5552         struct vcpu_svm *svm = to_svm(vcpu);
5553
5554         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5555         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5556         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5557
5558         /*
5559          * A vmexit emulation is required before the vcpu can be executed
5560          * again.
5561          */
5562         if (unlikely(svm->nested.exit_required))
5563                 return;
5564
5565         /*
5566          * Disable singlestep if we're injecting an interrupt/exception.
5567          * We don't want our modified rflags to be pushed on the stack where
5568          * we might not be able to easily reset them if we disabled NMI
5569          * singlestep later.
5570          */
5571         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5572                 /*
5573                  * Event injection happens before external interrupts cause a
5574                  * vmexit and interrupts are disabled here, so smp_send_reschedule
5575                  * is enough to force an immediate vmexit.
5576                  */
5577                 disable_nmi_singlestep(svm);
5578                 smp_send_reschedule(vcpu->cpu);
5579         }
5580
5581         pre_svm_run(svm);
5582
5583         sync_lapic_to_cr8(vcpu);
5584
5585         svm->vmcb->save.cr2 = vcpu->arch.cr2;
5586
5587         clgi();
5588
5589         /*
5590          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5591          * it's non-zero. Since vmentry is serialising on affected CPUs, there
5592          * is no need to worry about the conditional branch over the wrmsr
5593          * being speculatively taken.
5594          */
5595         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5596
5597         local_irq_enable();
5598
5599         asm volatile (
5600                 "push %%" _ASM_BP "; \n\t"
5601                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5602                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5603                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5604                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5605                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5606                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5607 #ifdef CONFIG_X86_64
5608                 "mov %c[r8](%[svm]),  %%r8  \n\t"
5609                 "mov %c[r9](%[svm]),  %%r9  \n\t"
5610                 "mov %c[r10](%[svm]), %%r10 \n\t"
5611                 "mov %c[r11](%[svm]), %%r11 \n\t"
5612                 "mov %c[r12](%[svm]), %%r12 \n\t"
5613                 "mov %c[r13](%[svm]), %%r13 \n\t"
5614                 "mov %c[r14](%[svm]), %%r14 \n\t"
5615                 "mov %c[r15](%[svm]), %%r15 \n\t"
5616 #endif
5617
5618                 /* Enter guest mode */
5619                 "push %%" _ASM_AX " \n\t"
5620                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5621                 __ex(SVM_VMLOAD) "\n\t"
5622                 __ex(SVM_VMRUN) "\n\t"
5623                 __ex(SVM_VMSAVE) "\n\t"
5624                 "pop %%" _ASM_AX " \n\t"
5625
5626                 /* Save guest registers, load host registers */
5627                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5628                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5629                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5630                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5631                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5632                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5633 #ifdef CONFIG_X86_64
5634                 "mov %%r8,  %c[r8](%[svm]) \n\t"
5635                 "mov %%r9,  %c[r9](%[svm]) \n\t"
5636                 "mov %%r10, %c[r10](%[svm]) \n\t"
5637                 "mov %%r11, %c[r11](%[svm]) \n\t"
5638                 "mov %%r12, %c[r12](%[svm]) \n\t"
5639                 "mov %%r13, %c[r13](%[svm]) \n\t"
5640                 "mov %%r14, %c[r14](%[svm]) \n\t"
5641                 "mov %%r15, %c[r15](%[svm]) \n\t"
5642 #endif
5643                 /*
5644                 * Clear host registers marked as clobbered to prevent
5645                 * speculative use.
5646                 */
5647                 "xor %%" _ASM_BX ", %%" _ASM_BX " \n\t"
5648                 "xor %%" _ASM_CX ", %%" _ASM_CX " \n\t"
5649                 "xor %%" _ASM_DX ", %%" _ASM_DX " \n\t"
5650                 "xor %%" _ASM_SI ", %%" _ASM_SI " \n\t"
5651                 "xor %%" _ASM_DI ", %%" _ASM_DI " \n\t"
5652 #ifdef CONFIG_X86_64
5653                 "xor %%r8, %%r8 \n\t"
5654                 "xor %%r9, %%r9 \n\t"
5655                 "xor %%r10, %%r10 \n\t"
5656                 "xor %%r11, %%r11 \n\t"
5657                 "xor %%r12, %%r12 \n\t"
5658                 "xor %%r13, %%r13 \n\t"
5659                 "xor %%r14, %%r14 \n\t"
5660                 "xor %%r15, %%r15 \n\t"
5661 #endif
5662                 "pop %%" _ASM_BP
5663                 :
5664                 : [svm]"a"(svm),
5665                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5666                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5667                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5668                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5669                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5670                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5671                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5672 #ifdef CONFIG_X86_64
5673                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5674                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5675                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5676                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5677                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5678                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5679                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5680                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5681 #endif
5682                 : "cc", "memory"
5683 #ifdef CONFIG_X86_64
5684                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5685                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5686 #else
5687                 , "ebx", "ecx", "edx", "esi", "edi"
5688 #endif
5689                 );
5690
5691         /* Eliminate branch target predictions from guest mode */
5692         vmexit_fill_RSB();
5693
5694 #ifdef CONFIG_X86_64
5695         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5696 #else
5697         loadsegment(fs, svm->host.fs);
5698 #ifndef CONFIG_X86_32_LAZY_GS
5699         loadsegment(gs, svm->host.gs);
5700 #endif
5701 #endif
5702
5703         /*
5704          * We do not use IBRS in the kernel. If this vCPU has used the
5705          * SPEC_CTRL MSR it may have left it on; save the value and
5706          * turn it off. This is much more efficient than blindly adding
5707          * it to the atomic save/restore list. Especially as the former
5708          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5709          *
5710          * For non-nested case:
5711          * If the L01 MSR bitmap does not intercept the MSR, then we need to
5712          * save it.
5713          *
5714          * For nested case:
5715          * If the L02 MSR bitmap does not intercept the MSR, then we need to
5716          * save it.
5717          */
5718         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5719                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5720
5721         reload_tss(vcpu);
5722
5723         local_irq_disable();
5724
5725         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5726
5727         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5728         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5729         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5730         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5731
5732         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5733                 kvm_before_interrupt(&svm->vcpu);
5734
5735         stgi();
5736
5737         /* Any pending NMI will happen here */
5738
5739         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5740                 kvm_after_interrupt(&svm->vcpu);
5741
5742         sync_cr8_to_lapic(vcpu);
5743
5744         svm->next_rip = 0;
5745
5746         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5747
5748         /* if exit due to PF check for async PF */
5749         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5750                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5751
5752         if (npt_enabled) {
5753                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5754                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5755         }
5756
5757         /*
5758          * We need to handle MC intercepts here before the vcpu has a chance to
5759          * change the physical cpu
5760          */
5761         if (unlikely(svm->vmcb->control.exit_code ==
5762                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5763                 svm_handle_mce(svm);
5764
5765         mark_all_clean(svm->vmcb);
5766 }
5767 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5768
5769 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5770 {
5771         struct vcpu_svm *svm = to_svm(vcpu);
5772
5773         svm->vmcb->save.cr3 = __sme_set(root);
5774         mark_dirty(svm->vmcb, VMCB_CR);
5775 }
5776
5777 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5778 {
5779         struct vcpu_svm *svm = to_svm(vcpu);
5780
5781         svm->vmcb->control.nested_cr3 = __sme_set(root);
5782         mark_dirty(svm->vmcb, VMCB_NPT);
5783
5784         /* Also sync guest cr3 here in case we live migrate */
5785         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5786         mark_dirty(svm->vmcb, VMCB_CR);
5787 }
5788
5789 static int is_disabled(void)
5790 {
5791         u64 vm_cr;
5792
5793         rdmsrl(MSR_VM_CR, vm_cr);
5794         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5795                 return 1;
5796
5797         return 0;
5798 }
5799
5800 static void
5801 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5802 {
5803         /*
5804          * Patch in the VMMCALL instruction:
5805          */
5806         hypercall[0] = 0x0f;
5807         hypercall[1] = 0x01;
5808         hypercall[2] = 0xd9;
5809 }
5810
5811 static void svm_check_processor_compat(void *rtn)
5812 {
5813         *(int *)rtn = 0;
5814 }
5815
5816 static bool svm_cpu_has_accelerated_tpr(void)
5817 {
5818         return false;
5819 }
5820
5821 static bool svm_has_emulated_msr(int index)
5822 {
5823         return true;
5824 }
5825
5826 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5827 {
5828         return 0;
5829 }
5830
5831 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5832 {
5833         struct vcpu_svm *svm = to_svm(vcpu);
5834
5835         /* Update nrips enabled cache */
5836         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5837
5838         if (!kvm_vcpu_apicv_active(vcpu))
5839                 return;
5840
5841         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5842 }
5843
5844 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5845 {
5846         switch (func) {
5847         case 0x1:
5848                 if (avic)
5849                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5850                 break;
5851         case 0x80000001:
5852                 if (nested)
5853                         entry->ecx |= (1 << 2); /* Set SVM bit */
5854                 break;
5855         case 0x8000000A:
5856                 entry->eax = 1; /* SVM revision 1 */
5857                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5858                                    ASID emulation to nested SVM */
5859                 entry->ecx = 0; /* Reserved */
5860                 entry->edx = 0; /* Per default do not support any
5861                                    additional features */
5862
5863                 /* Support next_rip if host supports it */
5864                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5865                         entry->edx |= SVM_FEATURE_NRIP;
5866
5867                 /* Support NPT for the guest if enabled */
5868                 if (npt_enabled)
5869                         entry->edx |= SVM_FEATURE_NPT;
5870
5871                 break;
5872         case 0x8000001F:
5873                 /* Support memory encryption cpuid if host supports it */
5874                 if (boot_cpu_has(X86_FEATURE_SEV))
5875                         cpuid(0x8000001f, &entry->eax, &entry->ebx,
5876                                 &entry->ecx, &entry->edx);
5877
5878         }
5879 }
5880
5881 static int svm_get_lpage_level(void)
5882 {
5883         return PT_PDPE_LEVEL;
5884 }
5885
5886 static bool svm_rdtscp_supported(void)
5887 {
5888         return boot_cpu_has(X86_FEATURE_RDTSCP);
5889 }
5890
5891 static bool svm_invpcid_supported(void)
5892 {
5893         return false;
5894 }
5895
5896 static bool svm_mpx_supported(void)
5897 {
5898         return false;
5899 }
5900
5901 static bool svm_xsaves_supported(void)
5902 {
5903         return false;
5904 }
5905
5906 static bool svm_umip_emulated(void)
5907 {
5908         return false;
5909 }
5910
5911 static bool svm_has_wbinvd_exit(void)
5912 {
5913         return true;
5914 }
5915
5916 #define PRE_EX(exit)  { .exit_code = (exit), \
5917                         .stage = X86_ICPT_PRE_EXCEPT, }
5918 #define POST_EX(exit) { .exit_code = (exit), \
5919                         .stage = X86_ICPT_POST_EXCEPT, }
5920 #define POST_MEM(exit) { .exit_code = (exit), \
5921                         .stage = X86_ICPT_POST_MEMACCESS, }
5922
5923 static const struct __x86_intercept {
5924         u32 exit_code;
5925         enum x86_intercept_stage stage;
5926 } x86_intercept_map[] = {
5927         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5928         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5929         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5930         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5931         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5932         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5933         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5934         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5935         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5936         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5937         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5938         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5939         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5940         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5941         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5942         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5943         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5944         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5945         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5946         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5947         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5948         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5949         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5950         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5951         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5952         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5953         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5954         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5955         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5956         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5957         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5958         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5959         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5960         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5961         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5962         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5963         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5964         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5965         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5966         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5967         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5968         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5969         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5970         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5971         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5972         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5973 };
5974
5975 #undef PRE_EX
5976 #undef POST_EX
5977 #undef POST_MEM
5978
5979 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5980                                struct x86_instruction_info *info,
5981                                enum x86_intercept_stage stage)
5982 {
5983         struct vcpu_svm *svm = to_svm(vcpu);
5984         int vmexit, ret = X86EMUL_CONTINUE;
5985         struct __x86_intercept icpt_info;
5986         struct vmcb *vmcb = svm->vmcb;
5987
5988         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5989                 goto out;
5990
5991         icpt_info = x86_intercept_map[info->intercept];
5992
5993         if (stage != icpt_info.stage)
5994                 goto out;
5995
5996         switch (icpt_info.exit_code) {
5997         case SVM_EXIT_READ_CR0:
5998                 if (info->intercept == x86_intercept_cr_read)
5999                         icpt_info.exit_code += info->modrm_reg;
6000                 break;
6001         case SVM_EXIT_WRITE_CR0: {
6002                 unsigned long cr0, val;
6003                 u64 intercept;
6004
6005                 if (info->intercept == x86_intercept_cr_write)
6006                         icpt_info.exit_code += info->modrm_reg;
6007
6008                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6009                     info->intercept == x86_intercept_clts)
6010                         break;
6011
6012                 intercept = svm->nested.intercept;
6013
6014                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6015                         break;
6016
6017                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6018                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
6019
6020                 if (info->intercept == x86_intercept_lmsw) {
6021                         cr0 &= 0xfUL;
6022                         val &= 0xfUL;
6023                         /* lmsw can't clear PE - catch this here */
6024                         if (cr0 & X86_CR0_PE)
6025                                 val |= X86_CR0_PE;
6026                 }
6027
6028                 if (cr0 ^ val)
6029                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6030
6031                 break;
6032         }
6033         case SVM_EXIT_READ_DR0:
6034         case SVM_EXIT_WRITE_DR0:
6035                 icpt_info.exit_code += info->modrm_reg;
6036                 break;
6037         case SVM_EXIT_MSR:
6038                 if (info->intercept == x86_intercept_wrmsr)
6039                         vmcb->control.exit_info_1 = 1;
6040                 else
6041                         vmcb->control.exit_info_1 = 0;
6042                 break;
6043         case SVM_EXIT_PAUSE:
6044                 /*
6045                  * We get this for NOP only, but pause
6046                  * is rep not, check this here
6047                  */
6048                 if (info->rep_prefix != REPE_PREFIX)
6049                         goto out;
6050                 break;
6051         case SVM_EXIT_IOIO: {
6052                 u64 exit_info;
6053                 u32 bytes;
6054
6055                 if (info->intercept == x86_intercept_in ||
6056                     info->intercept == x86_intercept_ins) {
6057                         exit_info = ((info->src_val & 0xffff) << 16) |
6058                                 SVM_IOIO_TYPE_MASK;
6059                         bytes = info->dst_bytes;
6060                 } else {
6061                         exit_info = (info->dst_val & 0xffff) << 16;
6062                         bytes = info->src_bytes;
6063                 }
6064
6065                 if (info->intercept == x86_intercept_outs ||
6066                     info->intercept == x86_intercept_ins)
6067                         exit_info |= SVM_IOIO_STR_MASK;
6068
6069                 if (info->rep_prefix)
6070                         exit_info |= SVM_IOIO_REP_MASK;
6071
6072                 bytes = min(bytes, 4u);
6073
6074                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6075
6076                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6077
6078                 vmcb->control.exit_info_1 = exit_info;
6079                 vmcb->control.exit_info_2 = info->next_rip;
6080
6081                 break;
6082         }
6083         default:
6084                 break;
6085         }
6086
6087         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6088         if (static_cpu_has(X86_FEATURE_NRIPS))
6089                 vmcb->control.next_rip  = info->next_rip;
6090         vmcb->control.exit_code = icpt_info.exit_code;
6091         vmexit = nested_svm_exit_handled(svm);
6092
6093         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6094                                            : X86EMUL_CONTINUE;
6095
6096 out:
6097         return ret;
6098 }
6099
6100 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6101 {
6102         local_irq_enable();
6103         /*
6104          * We must have an instruction with interrupts enabled, so
6105          * the timer interrupt isn't delayed by the interrupt shadow.
6106          */
6107         asm("nop");
6108         local_irq_disable();
6109 }
6110
6111 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6112 {
6113         if (pause_filter_thresh)
6114                 shrink_ple_window(vcpu);
6115 }
6116
6117 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6118 {
6119         if (avic_handle_apic_id_update(vcpu) != 0)
6120                 return;
6121         if (avic_handle_dfr_update(vcpu) != 0)
6122                 return;
6123         avic_handle_ldr_update(vcpu);
6124 }
6125
6126 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6127 {
6128         /* [63:9] are reserved. */
6129         vcpu->arch.mcg_cap &= 0x1ff;
6130 }
6131
6132 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6133 {
6134         struct vcpu_svm *svm = to_svm(vcpu);
6135
6136         /* Per APM Vol.2 15.22.2 "Response to SMI" */
6137         if (!gif_set(svm))
6138                 return 0;
6139
6140         if (is_guest_mode(&svm->vcpu) &&
6141             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6142                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6143                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6144                 svm->nested.exit_required = true;
6145                 return 0;
6146         }
6147
6148         return 1;
6149 }
6150
6151 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6152 {
6153         struct vcpu_svm *svm = to_svm(vcpu);
6154         int ret;
6155
6156         if (is_guest_mode(vcpu)) {
6157                 /* FED8h - SVM Guest */
6158                 put_smstate(u64, smstate, 0x7ed8, 1);
6159                 /* FEE0h - SVM Guest VMCB Physical Address */
6160                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6161
6162                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6163                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6164                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6165
6166                 ret = nested_svm_vmexit(svm);
6167                 if (ret)
6168                         return ret;
6169         }
6170         return 0;
6171 }
6172
6173 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
6174 {
6175         struct vcpu_svm *svm = to_svm(vcpu);
6176         struct vmcb *nested_vmcb;
6177         struct page *page;
6178         struct {
6179                 u64 guest;
6180                 u64 vmcb;
6181         } svm_state_save;
6182         int ret;
6183
6184         ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
6185                                   sizeof(svm_state_save));
6186         if (ret)
6187                 return ret;
6188
6189         if (svm_state_save.guest) {
6190                 vcpu->arch.hflags &= ~HF_SMM_MASK;
6191                 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
6192                 if (nested_vmcb)
6193                         enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
6194                 else
6195                         ret = 1;
6196                 vcpu->arch.hflags |= HF_SMM_MASK;
6197         }
6198         return ret;
6199 }
6200
6201 static int enable_smi_window(struct kvm_vcpu *vcpu)
6202 {
6203         struct vcpu_svm *svm = to_svm(vcpu);
6204
6205         if (!gif_set(svm)) {
6206                 if (vgif_enabled(svm))
6207                         set_intercept(svm, INTERCEPT_STGI);
6208                 /* STGI will cause a vm exit */
6209                 return 1;
6210         }
6211         return 0;
6212 }
6213
6214 static int sev_asid_new(void)
6215 {
6216         int pos;
6217
6218         /*
6219          * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6220          */
6221         pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6222         if (pos >= max_sev_asid)
6223                 return -EBUSY;
6224
6225         set_bit(pos, sev_asid_bitmap);
6226         return pos + 1;
6227 }
6228
6229 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6230 {
6231         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6232         int asid, ret;
6233
6234         ret = -EBUSY;
6235         asid = sev_asid_new();
6236         if (asid < 0)
6237                 return ret;
6238
6239         ret = sev_platform_init(&argp->error);
6240         if (ret)
6241                 goto e_free;
6242
6243         sev->active = true;
6244         sev->asid = asid;
6245         INIT_LIST_HEAD(&sev->regions_list);
6246
6247         return 0;
6248
6249 e_free:
6250         __sev_asid_free(asid);
6251         return ret;
6252 }
6253
6254 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6255 {
6256         struct sev_data_activate *data;
6257         int asid = sev_get_asid(kvm);
6258         int ret;
6259
6260         wbinvd_on_all_cpus();
6261
6262         ret = sev_guest_df_flush(error);
6263         if (ret)
6264                 return ret;
6265
6266         data = kzalloc(sizeof(*data), GFP_KERNEL);
6267         if (!data)
6268                 return -ENOMEM;
6269
6270         /* activate ASID on the given handle */
6271         data->handle = handle;
6272         data->asid   = asid;
6273         ret = sev_guest_activate(data, error);
6274         kfree(data);
6275
6276         return ret;
6277 }
6278
6279 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6280 {
6281         struct fd f;
6282         int ret;
6283
6284         f = fdget(fd);
6285         if (!f.file)
6286                 return -EBADF;
6287
6288         ret = sev_issue_cmd_external_user(f.file, id, data, error);
6289
6290         fdput(f);
6291         return ret;
6292 }
6293
6294 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6295 {
6296         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6297
6298         return __sev_issue_cmd(sev->fd, id, data, error);
6299 }
6300
6301 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6302 {
6303         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6304         struct sev_data_launch_start *start;
6305         struct kvm_sev_launch_start params;
6306         void *dh_blob, *session_blob;
6307         int *error = &argp->error;
6308         int ret;
6309
6310         if (!sev_guest(kvm))
6311                 return -ENOTTY;
6312
6313         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6314                 return -EFAULT;
6315
6316         start = kzalloc(sizeof(*start), GFP_KERNEL);
6317         if (!start)
6318                 return -ENOMEM;
6319
6320         dh_blob = NULL;
6321         if (params.dh_uaddr) {
6322                 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6323                 if (IS_ERR(dh_blob)) {
6324                         ret = PTR_ERR(dh_blob);
6325                         goto e_free;
6326                 }
6327
6328                 start->dh_cert_address = __sme_set(__pa(dh_blob));
6329                 start->dh_cert_len = params.dh_len;
6330         }
6331
6332         session_blob = NULL;
6333         if (params.session_uaddr) {
6334                 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6335                 if (IS_ERR(session_blob)) {
6336                         ret = PTR_ERR(session_blob);
6337                         goto e_free_dh;
6338                 }
6339
6340                 start->session_address = __sme_set(__pa(session_blob));
6341                 start->session_len = params.session_len;
6342         }
6343
6344         start->handle = params.handle;
6345         start->policy = params.policy;
6346
6347         /* create memory encryption context */
6348         ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6349         if (ret)
6350                 goto e_free_session;
6351
6352         /* Bind ASID to this guest */
6353         ret = sev_bind_asid(kvm, start->handle, error);
6354         if (ret)
6355                 goto e_free_session;
6356
6357         /* return handle to userspace */
6358         params.handle = start->handle;
6359         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params))) {
6360                 sev_unbind_asid(kvm, start->handle);
6361                 ret = -EFAULT;
6362                 goto e_free_session;
6363         }
6364
6365         sev->handle = start->handle;
6366         sev->fd = argp->sev_fd;
6367
6368 e_free_session:
6369         kfree(session_blob);
6370 e_free_dh:
6371         kfree(dh_blob);
6372 e_free:
6373         kfree(start);
6374         return ret;
6375 }
6376
6377 static int get_num_contig_pages(int idx, struct page **inpages,
6378                                 unsigned long npages)
6379 {
6380         unsigned long paddr, next_paddr;
6381         int i = idx + 1, pages = 1;
6382
6383         /* find the number of contiguous pages starting from idx */
6384         paddr = __sme_page_pa(inpages[idx]);
6385         while (i < npages) {
6386                 next_paddr = __sme_page_pa(inpages[i++]);
6387                 if ((paddr + PAGE_SIZE) == next_paddr) {
6388                         pages++;
6389                         paddr = next_paddr;
6390                         continue;
6391                 }
6392                 break;
6393         }
6394
6395         return pages;
6396 }
6397
6398 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6399 {
6400         unsigned long vaddr, vaddr_end, next_vaddr, npages, size;
6401         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6402         struct kvm_sev_launch_update_data params;
6403         struct sev_data_launch_update_data *data;
6404         struct page **inpages;
6405         int i, ret, pages;
6406
6407         if (!sev_guest(kvm))
6408                 return -ENOTTY;
6409
6410         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6411                 return -EFAULT;
6412
6413         data = kzalloc(sizeof(*data), GFP_KERNEL);
6414         if (!data)
6415                 return -ENOMEM;
6416
6417         vaddr = params.uaddr;
6418         size = params.len;
6419         vaddr_end = vaddr + size;
6420
6421         /* Lock the user memory. */
6422         inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6423         if (!inpages) {
6424                 ret = -ENOMEM;
6425                 goto e_free;
6426         }
6427
6428         /*
6429          * The LAUNCH_UPDATE command will perform in-place encryption of the
6430          * memory content (i.e it will write the same memory region with C=1).
6431          * It's possible that the cache may contain the data with C=0, i.e.,
6432          * unencrypted so invalidate it first.
6433          */
6434         sev_clflush_pages(inpages, npages);
6435
6436         for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6437                 int offset, len;
6438
6439                 /*
6440                  * If the user buffer is not page-aligned, calculate the offset
6441                  * within the page.
6442                  */
6443                 offset = vaddr & (PAGE_SIZE - 1);
6444
6445                 /* Calculate the number of pages that can be encrypted in one go. */
6446                 pages = get_num_contig_pages(i, inpages, npages);
6447
6448                 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6449
6450                 data->handle = sev->handle;
6451                 data->len = len;
6452                 data->address = __sme_page_pa(inpages[i]) + offset;
6453                 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6454                 if (ret)
6455                         goto e_unpin;
6456
6457                 size -= len;
6458                 next_vaddr = vaddr + len;
6459         }
6460
6461 e_unpin:
6462         /* content of memory is updated, mark pages dirty */
6463         for (i = 0; i < npages; i++) {
6464                 set_page_dirty_lock(inpages[i]);
6465                 mark_page_accessed(inpages[i]);
6466         }
6467         /* unlock the user pages */
6468         sev_unpin_memory(kvm, inpages, npages);
6469 e_free:
6470         kfree(data);
6471         return ret;
6472 }
6473
6474 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6475 {
6476         void __user *measure = (void __user *)(uintptr_t)argp->data;
6477         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6478         struct sev_data_launch_measure *data;
6479         struct kvm_sev_launch_measure params;
6480         void __user *p = NULL;
6481         void *blob = NULL;
6482         int ret;
6483
6484         if (!sev_guest(kvm))
6485                 return -ENOTTY;
6486
6487         if (copy_from_user(&params, measure, sizeof(params)))
6488                 return -EFAULT;
6489
6490         data = kzalloc(sizeof(*data), GFP_KERNEL);
6491         if (!data)
6492                 return -ENOMEM;
6493
6494         /* User wants to query the blob length */
6495         if (!params.len)
6496                 goto cmd;
6497
6498         p = (void __user *)(uintptr_t)params.uaddr;
6499         if (p) {
6500                 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6501                         ret = -EINVAL;
6502                         goto e_free;
6503                 }
6504
6505                 ret = -ENOMEM;
6506                 blob = kmalloc(params.len, GFP_KERNEL);
6507                 if (!blob)
6508                         goto e_free;
6509
6510                 data->address = __psp_pa(blob);
6511                 data->len = params.len;
6512         }
6513
6514 cmd:
6515         data->handle = sev->handle;
6516         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6517
6518         /*
6519          * If we query the session length, FW responded with expected data.
6520          */
6521         if (!params.len)
6522                 goto done;
6523
6524         if (ret)
6525                 goto e_free_blob;
6526
6527         if (blob) {
6528                 if (copy_to_user(p, blob, params.len))
6529                         ret = -EFAULT;
6530         }
6531
6532 done:
6533         params.len = data->len;
6534         if (copy_to_user(measure, &params, sizeof(params)))
6535                 ret = -EFAULT;
6536 e_free_blob:
6537         kfree(blob);
6538 e_free:
6539         kfree(data);
6540         return ret;
6541 }
6542
6543 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6544 {
6545         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6546         struct sev_data_launch_finish *data;
6547         int ret;
6548
6549         if (!sev_guest(kvm))
6550                 return -ENOTTY;
6551
6552         data = kzalloc(sizeof(*data), GFP_KERNEL);
6553         if (!data)
6554                 return -ENOMEM;
6555
6556         data->handle = sev->handle;
6557         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6558
6559         kfree(data);
6560         return ret;
6561 }
6562
6563 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6564 {
6565         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6566         struct kvm_sev_guest_status params;
6567         struct sev_data_guest_status *data;
6568         int ret;
6569
6570         if (!sev_guest(kvm))
6571                 return -ENOTTY;
6572
6573         data = kzalloc(sizeof(*data), GFP_KERNEL);
6574         if (!data)
6575                 return -ENOMEM;
6576
6577         data->handle = sev->handle;
6578         ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6579         if (ret)
6580                 goto e_free;
6581
6582         params.policy = data->policy;
6583         params.state = data->state;
6584         params.handle = data->handle;
6585
6586         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params)))
6587                 ret = -EFAULT;
6588 e_free:
6589         kfree(data);
6590         return ret;
6591 }
6592
6593 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6594                                unsigned long dst, int size,
6595                                int *error, bool enc)
6596 {
6597         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6598         struct sev_data_dbg *data;
6599         int ret;
6600
6601         data = kzalloc(sizeof(*data), GFP_KERNEL);
6602         if (!data)
6603                 return -ENOMEM;
6604
6605         data->handle = sev->handle;
6606         data->dst_addr = dst;
6607         data->src_addr = src;
6608         data->len = size;
6609
6610         ret = sev_issue_cmd(kvm,
6611                             enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6612                             data, error);
6613         kfree(data);
6614         return ret;
6615 }
6616
6617 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6618                              unsigned long dst_paddr, int sz, int *err)
6619 {
6620         int offset;
6621
6622         /*
6623          * Its safe to read more than we are asked, caller should ensure that
6624          * destination has enough space.
6625          */
6626         src_paddr = round_down(src_paddr, 16);
6627         offset = src_paddr & 15;
6628         sz = round_up(sz + offset, 16);
6629
6630         return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6631 }
6632
6633 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6634                                   unsigned long __user dst_uaddr,
6635                                   unsigned long dst_paddr,
6636                                   int size, int *err)
6637 {
6638         struct page *tpage = NULL;
6639         int ret, offset;
6640
6641         /* if inputs are not 16-byte then use intermediate buffer */
6642         if (!IS_ALIGNED(dst_paddr, 16) ||
6643             !IS_ALIGNED(paddr,     16) ||
6644             !IS_ALIGNED(size,      16)) {
6645                 tpage = (void *)alloc_page(GFP_KERNEL);
6646                 if (!tpage)
6647                         return -ENOMEM;
6648
6649                 dst_paddr = __sme_page_pa(tpage);
6650         }
6651
6652         ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6653         if (ret)
6654                 goto e_free;
6655
6656         if (tpage) {
6657                 offset = paddr & 15;
6658                 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6659                                  page_address(tpage) + offset, size))
6660                         ret = -EFAULT;
6661         }
6662
6663 e_free:
6664         if (tpage)
6665                 __free_page(tpage);
6666
6667         return ret;
6668 }
6669
6670 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6671                                   unsigned long __user vaddr,
6672                                   unsigned long dst_paddr,
6673                                   unsigned long __user dst_vaddr,
6674                                   int size, int *error)
6675 {
6676         struct page *src_tpage = NULL;
6677         struct page *dst_tpage = NULL;
6678         int ret, len = size;
6679
6680         /* If source buffer is not aligned then use an intermediate buffer */
6681         if (!IS_ALIGNED(vaddr, 16)) {
6682                 src_tpage = alloc_page(GFP_KERNEL);
6683                 if (!src_tpage)
6684                         return -ENOMEM;
6685
6686                 if (copy_from_user(page_address(src_tpage),
6687                                 (void __user *)(uintptr_t)vaddr, size)) {
6688                         __free_page(src_tpage);
6689                         return -EFAULT;
6690                 }
6691
6692                 paddr = __sme_page_pa(src_tpage);
6693         }
6694
6695         /*
6696          *  If destination buffer or length is not aligned then do read-modify-write:
6697          *   - decrypt destination in an intermediate buffer
6698          *   - copy the source buffer in an intermediate buffer
6699          *   - use the intermediate buffer as source buffer
6700          */
6701         if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6702                 int dst_offset;
6703
6704                 dst_tpage = alloc_page(GFP_KERNEL);
6705                 if (!dst_tpage) {
6706                         ret = -ENOMEM;
6707                         goto e_free;
6708                 }
6709
6710                 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6711                                         __sme_page_pa(dst_tpage), size, error);
6712                 if (ret)
6713                         goto e_free;
6714
6715                 /*
6716                  *  If source is kernel buffer then use memcpy() otherwise
6717                  *  copy_from_user().
6718                  */
6719                 dst_offset = dst_paddr & 15;
6720
6721                 if (src_tpage)
6722                         memcpy(page_address(dst_tpage) + dst_offset,
6723                                page_address(src_tpage), size);
6724                 else {
6725                         if (copy_from_user(page_address(dst_tpage) + dst_offset,
6726                                            (void __user *)(uintptr_t)vaddr, size)) {
6727                                 ret = -EFAULT;
6728                                 goto e_free;
6729                         }
6730                 }
6731
6732                 paddr = __sme_page_pa(dst_tpage);
6733                 dst_paddr = round_down(dst_paddr, 16);
6734                 len = round_up(size, 16);
6735         }
6736
6737         ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6738
6739 e_free:
6740         if (src_tpage)
6741                 __free_page(src_tpage);
6742         if (dst_tpage)
6743                 __free_page(dst_tpage);
6744         return ret;
6745 }
6746
6747 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6748 {
6749         unsigned long vaddr, vaddr_end, next_vaddr;
6750         unsigned long dst_vaddr, dst_vaddr_end;
6751         struct page **src_p, **dst_p;
6752         struct kvm_sev_dbg debug;
6753         unsigned long n;
6754         int ret, size;
6755
6756         if (!sev_guest(kvm))
6757                 return -ENOTTY;
6758
6759         if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6760                 return -EFAULT;
6761
6762         vaddr = debug.src_uaddr;
6763         size = debug.len;
6764         vaddr_end = vaddr + size;
6765         dst_vaddr = debug.dst_uaddr;
6766         dst_vaddr_end = dst_vaddr + size;
6767
6768         for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6769                 int len, s_off, d_off;
6770
6771                 /* lock userspace source and destination page */
6772                 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6773                 if (!src_p)
6774                         return -EFAULT;
6775
6776                 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6777                 if (!dst_p) {
6778                         sev_unpin_memory(kvm, src_p, n);
6779                         return -EFAULT;
6780                 }
6781
6782                 /*
6783                  * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6784                  * memory content (i.e it will write the same memory region with C=1).
6785                  * It's possible that the cache may contain the data with C=0, i.e.,
6786                  * unencrypted so invalidate it first.
6787                  */
6788                 sev_clflush_pages(src_p, 1);
6789                 sev_clflush_pages(dst_p, 1);
6790
6791                 /*
6792                  * Since user buffer may not be page aligned, calculate the
6793                  * offset within the page.
6794                  */
6795                 s_off = vaddr & ~PAGE_MASK;
6796                 d_off = dst_vaddr & ~PAGE_MASK;
6797                 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6798
6799                 if (dec)
6800                         ret = __sev_dbg_decrypt_user(kvm,
6801                                                      __sme_page_pa(src_p[0]) + s_off,
6802                                                      dst_vaddr,
6803                                                      __sme_page_pa(dst_p[0]) + d_off,
6804                                                      len, &argp->error);
6805                 else
6806                         ret = __sev_dbg_encrypt_user(kvm,
6807                                                      __sme_page_pa(src_p[0]) + s_off,
6808                                                      vaddr,
6809                                                      __sme_page_pa(dst_p[0]) + d_off,
6810                                                      dst_vaddr,
6811                                                      len, &argp->error);
6812
6813                 sev_unpin_memory(kvm, src_p, 1);
6814                 sev_unpin_memory(kvm, dst_p, 1);
6815
6816                 if (ret)
6817                         goto err;
6818
6819                 next_vaddr = vaddr + len;
6820                 dst_vaddr = dst_vaddr + len;
6821                 size -= len;
6822         }
6823 err:
6824         return ret;
6825 }
6826
6827 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6828 {
6829         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6830         struct sev_data_launch_secret *data;
6831         struct kvm_sev_launch_secret params;
6832         struct page **pages;
6833         void *blob, *hdr;
6834         unsigned long n;
6835         int ret, offset;
6836
6837         if (!sev_guest(kvm))
6838                 return -ENOTTY;
6839
6840         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6841                 return -EFAULT;
6842
6843         pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6844         if (!pages)
6845                 return -ENOMEM;
6846
6847         /*
6848          * The secret must be copied into contiguous memory region, lets verify
6849          * that userspace memory pages are contiguous before we issue command.
6850          */
6851         if (get_num_contig_pages(0, pages, n) != n) {
6852                 ret = -EINVAL;
6853                 goto e_unpin_memory;
6854         }
6855
6856         ret = -ENOMEM;
6857         data = kzalloc(sizeof(*data), GFP_KERNEL);
6858         if (!data)
6859                 goto e_unpin_memory;
6860
6861         offset = params.guest_uaddr & (PAGE_SIZE - 1);
6862         data->guest_address = __sme_page_pa(pages[0]) + offset;
6863         data->guest_len = params.guest_len;
6864
6865         blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6866         if (IS_ERR(blob)) {
6867                 ret = PTR_ERR(blob);
6868                 goto e_free;
6869         }
6870
6871         data->trans_address = __psp_pa(blob);
6872         data->trans_len = params.trans_len;
6873
6874         hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6875         if (IS_ERR(hdr)) {
6876                 ret = PTR_ERR(hdr);
6877                 goto e_free_blob;
6878         }
6879         data->hdr_address = __psp_pa(hdr);
6880         data->hdr_len = params.hdr_len;
6881
6882         data->handle = sev->handle;
6883         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6884
6885         kfree(hdr);
6886
6887 e_free_blob:
6888         kfree(blob);
6889 e_free:
6890         kfree(data);
6891 e_unpin_memory:
6892         sev_unpin_memory(kvm, pages, n);
6893         return ret;
6894 }
6895
6896 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6897 {
6898         struct kvm_sev_cmd sev_cmd;
6899         int r;
6900
6901         if (!svm_sev_enabled())
6902                 return -ENOTTY;
6903
6904         if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6905                 return -EFAULT;
6906
6907         mutex_lock(&kvm->lock);
6908
6909         switch (sev_cmd.id) {
6910         case KVM_SEV_INIT:
6911                 r = sev_guest_init(kvm, &sev_cmd);
6912                 break;
6913         case KVM_SEV_LAUNCH_START:
6914                 r = sev_launch_start(kvm, &sev_cmd);
6915                 break;
6916         case KVM_SEV_LAUNCH_UPDATE_DATA:
6917                 r = sev_launch_update_data(kvm, &sev_cmd);
6918                 break;
6919         case KVM_SEV_LAUNCH_MEASURE:
6920                 r = sev_launch_measure(kvm, &sev_cmd);
6921                 break;
6922         case KVM_SEV_LAUNCH_FINISH:
6923                 r = sev_launch_finish(kvm, &sev_cmd);
6924                 break;
6925         case KVM_SEV_GUEST_STATUS:
6926                 r = sev_guest_status(kvm, &sev_cmd);
6927                 break;
6928         case KVM_SEV_DBG_DECRYPT:
6929                 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6930                 break;
6931         case KVM_SEV_DBG_ENCRYPT:
6932                 r = sev_dbg_crypt(kvm, &sev_cmd, false);
6933                 break;
6934         case KVM_SEV_LAUNCH_SECRET:
6935                 r = sev_launch_secret(kvm, &sev_cmd);
6936                 break;
6937         default:
6938                 r = -EINVAL;
6939                 goto out;
6940         }
6941
6942         if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
6943                 r = -EFAULT;
6944
6945 out:
6946         mutex_unlock(&kvm->lock);
6947         return r;
6948 }
6949
6950 static int svm_register_enc_region(struct kvm *kvm,
6951                                    struct kvm_enc_region *range)
6952 {
6953         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6954         struct enc_region *region;
6955         int ret = 0;
6956
6957         if (!sev_guest(kvm))
6958                 return -ENOTTY;
6959
6960         if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
6961                 return -EINVAL;
6962
6963         region = kzalloc(sizeof(*region), GFP_KERNEL);
6964         if (!region)
6965                 return -ENOMEM;
6966
6967         region->pages = sev_pin_memory(kvm, range->addr, range->size, &region->npages, 1);
6968         if (!region->pages) {
6969                 ret = -ENOMEM;
6970                 goto e_free;
6971         }
6972
6973         /*
6974          * The guest may change the memory encryption attribute from C=0 -> C=1
6975          * or vice versa for this memory range. Lets make sure caches are
6976          * flushed to ensure that guest data gets written into memory with
6977          * correct C-bit.
6978          */
6979         sev_clflush_pages(region->pages, region->npages);
6980
6981         region->uaddr = range->addr;
6982         region->size = range->size;
6983
6984         mutex_lock(&kvm->lock);
6985         list_add_tail(&region->list, &sev->regions_list);
6986         mutex_unlock(&kvm->lock);
6987
6988         return ret;
6989
6990 e_free:
6991         kfree(region);
6992         return ret;
6993 }
6994
6995 static struct enc_region *
6996 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
6997 {
6998         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6999         struct list_head *head = &sev->regions_list;
7000         struct enc_region *i;
7001
7002         list_for_each_entry(i, head, list) {
7003                 if (i->uaddr == range->addr &&
7004                     i->size == range->size)
7005                         return i;
7006         }
7007
7008         return NULL;
7009 }
7010
7011
7012 static int svm_unregister_enc_region(struct kvm *kvm,
7013                                      struct kvm_enc_region *range)
7014 {
7015         struct enc_region *region;
7016         int ret;
7017
7018         mutex_lock(&kvm->lock);
7019
7020         if (!sev_guest(kvm)) {
7021                 ret = -ENOTTY;
7022                 goto failed;
7023         }
7024
7025         region = find_enc_region(kvm, range);
7026         if (!region) {
7027                 ret = -EINVAL;
7028                 goto failed;
7029         }
7030
7031         __unregister_enc_region_locked(kvm, region);
7032
7033         mutex_unlock(&kvm->lock);
7034         return 0;
7035
7036 failed:
7037         mutex_unlock(&kvm->lock);
7038         return ret;
7039 }
7040
7041 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7042         .cpu_has_kvm_support = has_svm,
7043         .disabled_by_bios = is_disabled,
7044         .hardware_setup = svm_hardware_setup,
7045         .hardware_unsetup = svm_hardware_unsetup,
7046         .check_processor_compatibility = svm_check_processor_compat,
7047         .hardware_enable = svm_hardware_enable,
7048         .hardware_disable = svm_hardware_disable,
7049         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7050         .has_emulated_msr = svm_has_emulated_msr,
7051
7052         .vcpu_create = svm_create_vcpu,
7053         .vcpu_free = svm_free_vcpu,
7054         .vcpu_reset = svm_vcpu_reset,
7055
7056         .vm_alloc = svm_vm_alloc,
7057         .vm_free = svm_vm_free,
7058         .vm_init = avic_vm_init,
7059         .vm_destroy = svm_vm_destroy,
7060
7061         .prepare_guest_switch = svm_prepare_guest_switch,
7062         .vcpu_load = svm_vcpu_load,
7063         .vcpu_put = svm_vcpu_put,
7064         .vcpu_blocking = svm_vcpu_blocking,
7065         .vcpu_unblocking = svm_vcpu_unblocking,
7066
7067         .update_bp_intercept = update_bp_intercept,
7068         .get_msr_feature = svm_get_msr_feature,
7069         .get_msr = svm_get_msr,
7070         .set_msr = svm_set_msr,
7071         .get_segment_base = svm_get_segment_base,
7072         .get_segment = svm_get_segment,
7073         .set_segment = svm_set_segment,
7074         .get_cpl = svm_get_cpl,
7075         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7076         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7077         .decache_cr3 = svm_decache_cr3,
7078         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7079         .set_cr0 = svm_set_cr0,
7080         .set_cr3 = svm_set_cr3,
7081         .set_cr4 = svm_set_cr4,
7082         .set_efer = svm_set_efer,
7083         .get_idt = svm_get_idt,
7084         .set_idt = svm_set_idt,
7085         .get_gdt = svm_get_gdt,
7086         .set_gdt = svm_set_gdt,
7087         .get_dr6 = svm_get_dr6,
7088         .set_dr6 = svm_set_dr6,
7089         .set_dr7 = svm_set_dr7,
7090         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7091         .cache_reg = svm_cache_reg,
7092         .get_rflags = svm_get_rflags,
7093         .set_rflags = svm_set_rflags,
7094
7095         .tlb_flush = svm_flush_tlb,
7096         .tlb_flush_gva = svm_flush_tlb_gva,
7097
7098         .run = svm_vcpu_run,
7099         .handle_exit = handle_exit,
7100         .skip_emulated_instruction = skip_emulated_instruction,
7101         .set_interrupt_shadow = svm_set_interrupt_shadow,
7102         .get_interrupt_shadow = svm_get_interrupt_shadow,
7103         .patch_hypercall = svm_patch_hypercall,
7104         .set_irq = svm_set_irq,
7105         .set_nmi = svm_inject_nmi,
7106         .queue_exception = svm_queue_exception,
7107         .cancel_injection = svm_cancel_injection,
7108         .interrupt_allowed = svm_interrupt_allowed,
7109         .nmi_allowed = svm_nmi_allowed,
7110         .get_nmi_mask = svm_get_nmi_mask,
7111         .set_nmi_mask = svm_set_nmi_mask,
7112         .enable_nmi_window = enable_nmi_window,
7113         .enable_irq_window = enable_irq_window,
7114         .update_cr8_intercept = update_cr8_intercept,
7115         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7116         .get_enable_apicv = svm_get_enable_apicv,
7117         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7118         .load_eoi_exitmap = svm_load_eoi_exitmap,
7119         .hwapic_irr_update = svm_hwapic_irr_update,
7120         .hwapic_isr_update = svm_hwapic_isr_update,
7121         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7122         .apicv_post_state_restore = avic_post_state_restore,
7123
7124         .set_tss_addr = svm_set_tss_addr,
7125         .set_identity_map_addr = svm_set_identity_map_addr,
7126         .get_tdp_level = get_npt_level,
7127         .get_mt_mask = svm_get_mt_mask,
7128
7129         .get_exit_info = svm_get_exit_info,
7130
7131         .get_lpage_level = svm_get_lpage_level,
7132
7133         .cpuid_update = svm_cpuid_update,
7134
7135         .rdtscp_supported = svm_rdtscp_supported,
7136         .invpcid_supported = svm_invpcid_supported,
7137         .mpx_supported = svm_mpx_supported,
7138         .xsaves_supported = svm_xsaves_supported,
7139         .umip_emulated = svm_umip_emulated,
7140
7141         .set_supported_cpuid = svm_set_supported_cpuid,
7142
7143         .has_wbinvd_exit = svm_has_wbinvd_exit,
7144
7145         .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7146         .write_tsc_offset = svm_write_tsc_offset,
7147
7148         .set_tdp_cr3 = set_tdp_cr3,
7149
7150         .check_intercept = svm_check_intercept,
7151         .handle_external_intr = svm_handle_external_intr,
7152
7153         .sched_in = svm_sched_in,
7154
7155         .pmu_ops = &amd_pmu_ops,
7156         .deliver_posted_interrupt = svm_deliver_avic_intr,
7157         .update_pi_irte = svm_update_pi_irte,
7158         .setup_mce = svm_setup_mce,
7159
7160         .smi_allowed = svm_smi_allowed,
7161         .pre_enter_smm = svm_pre_enter_smm,
7162         .pre_leave_smm = svm_pre_leave_smm,
7163         .enable_smi_window = enable_smi_window,
7164
7165         .mem_enc_op = svm_mem_enc_op,
7166         .mem_enc_reg_region = svm_register_enc_region,
7167         .mem_enc_unreg_region = svm_unregister_enc_region,
7168 };
7169
7170 static int __init svm_init(void)
7171 {
7172         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7173                         __alignof__(struct vcpu_svm), THIS_MODULE);
7174 }
7175
7176 static void __exit svm_exit(void)
7177 {
7178         kvm_exit();
7179 }
7180
7181 module_init(svm_init)
7182 module_exit(svm_exit)