arch/x86/kvm/svm/svm.h

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * AMD SVM support
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *   Avi Kivity   <avi@qumranet.com>
  13  */
  14
  15 #ifndef __SVM_SVM_H
  16 #define __SVM_SVM_H
  17
  18 #include <linux/kvm_types.h>
  19 #include <linux/kvm_host.h>
  20 #include <linux/bits.h>
  21
  22 #include <asm/svm.h>
  23
  24 static const u32 host_save_user_msrs[] = {
  25 #ifdef CONFIG_X86_64
  26         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  27         MSR_FS_BASE,
  28 #endif
  29         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  30         MSR_TSC_AUX,
  31 };
  32
  33 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  34
  35 #define MAX_DIRECT_ACCESS_MSRS  15
  36 #define MSRPM_OFFSETS   16
  37 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  38 extern bool npt_enabled;
  39
  40 enum {
  41         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
  42                             pause filter count */
  43         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
  44         VMCB_ASID,       /* ASID */
  45         VMCB_INTR,       /* int_ctl, int_vector */
  46         VMCB_NPT,        /* npt_en, nCR3, gPAT */
  47         VMCB_CR,         /* CR0, CR3, CR4, EFER */
  48         VMCB_DR,         /* DR6, DR7 */
  49         VMCB_DT,         /* GDT, IDT */
  50         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
  51         VMCB_CR2,        /* CR2 only */
  52         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
  53         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
  54                           * AVIC PHYSICAL_TABLE pointer,
  55                           * AVIC LOGICAL_TABLE pointer
  56                           */
  57         VMCB_DIRTY_MAX,
  58 };
  59
  60 /* TPR and CR2 are always written before VMRUN */
  61 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
  62
  63 struct kvm_sev_info {
  64         bool active;            /* SEV enabled guest */
  65         bool es_active;         /* SEV-ES enabled guest */
  66         unsigned int asid;      /* ASID used for this guest */
  67         unsigned int handle;    /* SEV firmware handle */
  68         int fd;                 /* SEV device fd */
  69         unsigned long pages_locked; /* Number of pages locked */
  70         struct list_head regions_list;  /* List of registered regions */
  71 };
  72
  73 struct kvm_svm {
  74         struct kvm kvm;
  75
  76         /* Struct members for AVIC */
  77         u32 avic_vm_id;
  78         struct page *avic_logical_id_table_page;
  79         struct page *avic_physical_id_table_page;
  80         struct hlist_node hnode;
  81
  82         struct kvm_sev_info sev_info;
  83 };
  84
  85 struct kvm_vcpu;
  86
  87 struct svm_nested_state {
  88         struct vmcb *hsave;
  89         u64 hsave_msr;
  90         u64 vm_cr_msr;
  91         u64 vmcb12_gpa;
  92
  93         /* These are the merged vectors */
  94         u32 *msrpm;
  95
  96         /* A VMRUN has started but has not yet been performed, so
  97          * we cannot inject a nested vmexit yet.  */
  98         bool nested_run_pending;
  99
 100         /* cache for control fields of the guest */
 101         struct vmcb_control_area ctl;
 102
 103         bool initialized;
 104 };
 105
 106 struct vcpu_svm {
 107         struct kvm_vcpu vcpu;
 108         struct vmcb *vmcb;
 109         unsigned long vmcb_pa;
 110         struct svm_cpu_data *svm_data;
 111         u32 asid;
 112         uint64_t asid_generation;
 113         uint64_t sysenter_esp;
 114         uint64_t sysenter_eip;
 115         uint64_t tsc_aux;
 116
 117         u64 msr_decfg;
 118
 119         u64 next_rip;
 120
 121         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 122         struct {
 123                 u16 fs;
 124                 u16 gs;
 125                 u16 ldt;
 126                 u64 gs_base;
 127         } host;
 128
 129         u64 spec_ctrl;
 130         /*
 131          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 132          * translated into the appropriate L2_CFG bits on the host to
 133          * perform speculative control.
 134          */
 135         u64 virt_spec_ctrl;
 136
 137         u32 *msrpm;
 138
 139         ulong nmi_iret_rip;
 140
 141         struct svm_nested_state nested;
 142
 143         bool nmi_singlestep;
 144         u64 nmi_singlestep_guest_rflags;
 145
 146         unsigned int3_injected;
 147         unsigned long int3_rip;
 148
 149         /* cached guest cpuid flags for faster access */
 150         bool nrips_enabled      : 1;
 151
 152         u32 ldr_reg;
 153         u32 dfr_reg;
 154         struct page *avic_backing_page;
 155         u64 *avic_physical_id_cache;
 156         bool avic_is_running;
 157
 158         /*
 159          * Per-vcpu list of struct amd_svm_iommu_ir:
 160          * This is used mainly to store interrupt remapping information used
 161          * when update the vcpu affinity. This avoids the need to scan for
 162          * IRTE and try to match ga_tag in the IOMMU driver.
 163          */
 164         struct list_head ir_list;
 165         spinlock_t ir_list_lock;
 166
 167         /* Save desired MSR intercept (read: pass-through) state */
 168         struct {
 169                 DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS);
 170                 DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS);
 171         } shadow_msr_intercept;
 172
 173         /* SEV-ES support */
 174         struct vmcb_save_area *vmsa;
 175         struct ghcb *ghcb;
 176         struct kvm_host_map ghcb_map;
 177
 178         /* SEV-ES scratch area support */
 179         void *ghcb_sa;
 180         u64 ghcb_sa_len;
 181         bool ghcb_sa_sync;
 182         bool ghcb_sa_free;
 183 };
 184
 185 struct svm_cpu_data {
 186         int cpu;
 187
 188         u64 asid_generation;
 189         u32 max_asid;
 190         u32 next_asid;
 191         u32 min_asid;
 192         struct kvm_ldttss_desc *tss_desc;
 193
 194         struct page *save_area;
 195         struct vmcb *current_vmcb;
 196
 197         /* index = sev_asid, value = vmcb pointer */
 198         struct vmcb **sev_vmcbs;
 199 };
 200
 201 DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);
 202
 203 void recalc_intercepts(struct vcpu_svm *svm);
 204
 205 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 206 {
 207         return container_of(kvm, struct kvm_svm, kvm);
 208 }
 209
 210 static inline bool sev_guest(struct kvm *kvm)
 211 {
 212 #ifdef CONFIG_KVM_AMD_SEV
 213         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 214
 215         return sev->active;
 216 #else
 217         return false;
 218 #endif
 219 }
 220
 221 static inline bool sev_es_guest(struct kvm *kvm)
 222 {
 223 #ifdef CONFIG_KVM_AMD_SEV
 224         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 225
 226         return sev_guest(kvm) && sev->es_active;
 227 #else
 228         return false;
 229 #endif
 230 }
 231
 232 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
 233 {
 234         vmcb->control.clean = 0;
 235 }
 236
 237 static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
 238 {
 239         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 240                                & ~VMCB_ALWAYS_DIRTY_MASK;
 241 }
 242
 243 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
 244 {
 245         vmcb->control.clean &= ~(1 << bit);
 246 }
 247
 248 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 249 {
 250         return container_of(vcpu, struct vcpu_svm, vcpu);
 251 }
 252
 253 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 254 {
 255         if (is_guest_mode(&svm->vcpu))
 256                 return svm->nested.hsave;
 257         else
 258                 return svm->vmcb;
 259 }
 260
 261 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit)
 262 {
 263         WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
 264         __set_bit(bit, (unsigned long *)&control->intercepts);
 265 }
 266
 267 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit)
 268 {
 269         WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
 270         __clear_bit(bit, (unsigned long *)&control->intercepts);
 271 }
 272
 273 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit)
 274 {
 275         WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
 276         return test_bit(bit, (unsigned long *)&control->intercepts);
 277 }
 278
 279 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 280 {
 281         struct vmcb *vmcb = get_host_vmcb(svm);
 282
 283         if (!sev_es_guest(svm->vcpu.kvm)) {
 284                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ);
 285                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ);
 286                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ);
 287                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ);
 288                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ);
 289                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ);
 290                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ);
 291                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE);
 292                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE);
 293                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE);
 294                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE);
 295                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE);
 296                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE);
 297                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE);
 298         }
 299
 300         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
 301         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
 302
 303         recalc_intercepts(svm);
 304 }
 305
 306 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 307 {
 308         struct vmcb *vmcb = get_host_vmcb(svm);
 309
 310         vmcb->control.intercepts[INTERCEPT_DR] = 0;
 311
 312         /* DR7 access must remain intercepted for an SEV-ES guest */
 313         if (sev_es_guest(svm->vcpu.kvm)) {
 314                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
 315                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
 316         }
 317
 318         recalc_intercepts(svm);
 319 }
 320
 321 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit)
 322 {
 323         struct vmcb *vmcb = get_host_vmcb(svm);
 324
 325         WARN_ON_ONCE(bit >= 32);
 326         vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
 327
 328         recalc_intercepts(svm);
 329 }
 330
 331 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit)
 332 {
 333         struct vmcb *vmcb = get_host_vmcb(svm);
 334
 335         WARN_ON_ONCE(bit >= 32);
 336         vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
 337
 338         recalc_intercepts(svm);
 339 }
 340
 341 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit)
 342 {
 343         struct vmcb *vmcb = get_host_vmcb(svm);
 344
 345         vmcb_set_intercept(&vmcb->control, bit);
 346
 347         recalc_intercepts(svm);
 348 }
 349
 350 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit)
 351 {
 352         struct vmcb *vmcb = get_host_vmcb(svm);
 353
 354         vmcb_clr_intercept(&vmcb->control, bit);
 355
 356         recalc_intercepts(svm);
 357 }
 358
 359 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit)
 360 {
 361         return vmcb_is_intercept(&svm->vmcb->control, bit);
 362 }
 363
 364 static inline bool vgif_enabled(struct vcpu_svm *svm)
 365 {
 366         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 367 }
 368
 369 static inline void enable_gif(struct vcpu_svm *svm)
 370 {
 371         if (vgif_enabled(svm))
 372                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 373         else
 374                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 375 }
 376
 377 static inline void disable_gif(struct vcpu_svm *svm)
 378 {
 379         if (vgif_enabled(svm))
 380                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 381         else
 382                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 383 }
 384
 385 static inline bool gif_set(struct vcpu_svm *svm)
 386 {
 387         if (vgif_enabled(svm))
 388                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 389         else
 390                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 391 }
 392
 393 /* svm.c */
 394 #define MSR_CR3_LEGACY_RESERVED_MASK            0xfe7U
 395 #define MSR_CR3_LEGACY_PAE_RESERVED_MASK        0x7U
 396 #define MSR_CR3_LONG_MBZ_MASK                   0xfff0000000000000U
 397 #define MSR_INVALID                             0xffffffffU
 398
 399 extern int sev;
 400 extern int sev_es;
 401 extern bool dump_invalid_vmcb;
 402
 403 u32 svm_msrpm_offset(u32 msr);
 404 u32 *svm_vcpu_alloc_msrpm(void);
 405 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm);
 406 void svm_vcpu_free_msrpm(u32 *msrpm);
 407
 408 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
 409 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 410 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
 411 void svm_flush_tlb(struct kvm_vcpu *vcpu);
 412 void disable_nmi_singlestep(struct vcpu_svm *svm);
 413 bool svm_smi_blocked(struct kvm_vcpu *vcpu);
 414 bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
 415 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
 416 void svm_set_gif(struct vcpu_svm *svm, bool value);
 417 int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code);
 418
 419 /* nested.c */
 420
 421 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
 422 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
 423 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
 424
 425 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu)
 426 {
 427         struct vcpu_svm *svm = to_svm(vcpu);
 428
 429         return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
 430 }
 431
 432 static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
 433 {
 434         return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SMI);
 435 }
 436
 437 static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
 438 {
 439         return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_INTR);
 440 }
 441
 442 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
 443 {
 444         return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_NMI);
 445 }
 446
 447 int enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
 448                          struct vmcb *nested_vmcb);
 449 void svm_leave_nested(struct vcpu_svm *svm);
 450 void svm_free_nested(struct vcpu_svm *svm);
 451 int svm_allocate_nested(struct vcpu_svm *svm);
 452 int nested_svm_vmrun(struct vcpu_svm *svm);
 453 void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb);
 454 int nested_svm_vmexit(struct vcpu_svm *svm);
 455 int nested_svm_exit_handled(struct vcpu_svm *svm);
 456 int nested_svm_check_permissions(struct vcpu_svm *svm);
 457 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 458                                bool has_error_code, u32 error_code);
 459 int nested_svm_exit_special(struct vcpu_svm *svm);
 460 void sync_nested_vmcb_control(struct vcpu_svm *svm);
 461
 462 extern struct kvm_x86_nested_ops svm_nested_ops;
 463
 464 /* avic.c */
 465
 466 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 467 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT                 31
 468 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 469
 470 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 471 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 472 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 473 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 474
 475 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 476
 477 extern int avic;
 478
 479 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 480 {
 481         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 482         vmcb_mark_dirty(svm->vmcb, VMCB_AVIC);
 483 }
 484
 485 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 486 {
 487         struct vcpu_svm *svm = to_svm(vcpu);
 488         u64 *entry = svm->avic_physical_id_cache;
 489
 490         if (!entry)
 491                 return false;
 492
 493         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 494 }
 495
 496 int avic_ga_log_notifier(u32 ga_tag);
 497 void avic_vm_destroy(struct kvm *kvm);
 498 int avic_vm_init(struct kvm *kvm);
 499 void avic_init_vmcb(struct vcpu_svm *svm);
 500 void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
 501 int avic_incomplete_ipi_interception(struct vcpu_svm *svm);
 502 int avic_unaccelerated_access_interception(struct vcpu_svm *svm);
 503 int avic_init_vcpu(struct vcpu_svm *svm);
 504 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 505 void avic_vcpu_put(struct kvm_vcpu *vcpu);
 506 void avic_post_state_restore(struct kvm_vcpu *vcpu);
 507 void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
 508 void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
 509 bool svm_check_apicv_inhibit_reasons(ulong bit);
 510 void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate);
 511 void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
 512 void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr);
 513 void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr);
 514 int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec);
 515 bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu);
 516 int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
 517                        uint32_t guest_irq, bool set);
 518 void svm_vcpu_blocking(struct kvm_vcpu *vcpu);
 519 void svm_vcpu_unblocking(struct kvm_vcpu *vcpu);
 520
 521 /* sev.c */
 522
 523 #define GHCB_VERSION_MAX                1ULL
 524 #define GHCB_VERSION_MIN                1ULL
 525
 526 #define GHCB_MSR_INFO_POS               0
 527 #define GHCB_MSR_INFO_MASK              (BIT_ULL(12) - 1)
 528
 529 #define GHCB_MSR_SEV_INFO_RESP          0x001
 530 #define GHCB_MSR_SEV_INFO_REQ           0x002
 531 #define GHCB_MSR_VER_MAX_POS            48
 532 #define GHCB_MSR_VER_MAX_MASK           0xffff
 533 #define GHCB_MSR_VER_MIN_POS            32
 534 #define GHCB_MSR_VER_MIN_MASK           0xffff
 535 #define GHCB_MSR_CBIT_POS               24
 536 #define GHCB_MSR_CBIT_MASK              0xff
 537 #define GHCB_MSR_SEV_INFO(_max, _min, _cbit)                            \
 538         ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) |   \
 539          (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) |   \
 540          (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) |        \
 541          GHCB_MSR_SEV_INFO_RESP)
 542
 543 #define GHCB_MSR_CPUID_REQ              0x004
 544 #define GHCB_MSR_CPUID_RESP             0x005
 545 #define GHCB_MSR_CPUID_FUNC_POS         32
 546 #define GHCB_MSR_CPUID_FUNC_MASK        0xffffffff
 547 #define GHCB_MSR_CPUID_VALUE_POS        32
 548 #define GHCB_MSR_CPUID_VALUE_MASK       0xffffffff
 549 #define GHCB_MSR_CPUID_REG_POS          30
 550 #define GHCB_MSR_CPUID_REG_MASK         0x3
 551
 552 #define GHCB_MSR_TERM_REQ               0x100
 553 #define GHCB_MSR_TERM_REASON_SET_POS    12
 554 #define GHCB_MSR_TERM_REASON_SET_MASK   0xf
 555 #define GHCB_MSR_TERM_REASON_POS        16
 556 #define GHCB_MSR_TERM_REASON_MASK       0xff
 557
 558 extern unsigned int max_sev_asid;
 559
 560 static inline bool svm_sev_enabled(void)
 561 {
 562         return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
 563 }
 564
 565 void sev_vm_destroy(struct kvm *kvm);
 566 int svm_mem_enc_op(struct kvm *kvm, void __user *argp);
 567 int svm_register_enc_region(struct kvm *kvm,
 568                             struct kvm_enc_region *range);
 569 int svm_unregister_enc_region(struct kvm *kvm,
 570                               struct kvm_enc_region *range);
 571 void pre_sev_run(struct vcpu_svm *svm, int cpu);
 572 void __init sev_hardware_setup(void);
 573 void sev_hardware_teardown(void);
 574 void sev_free_vcpu(struct kvm_vcpu *vcpu);
 575 int sev_handle_vmgexit(struct vcpu_svm *svm);
 576 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in);
 577
 578 #endif