arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/objtool.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/spec-ctrl.h>
  37 #include <asm/cpu_device_id.h>
  38 #include <asm/traps.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44 #include "svm_ops.h"
  45
  46 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  47
  48 MODULE_AUTHOR("Qumranet");
  49 MODULE_LICENSE("GPL");
  50
  51 #ifdef MODULE
  52 static const struct x86_cpu_id svm_cpu_id[] = {
  53         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  54         {}
  55 };
  56 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  57 #endif
  58
  59 #define SEG_TYPE_LDT 2
  60 #define SEG_TYPE_BUSY_TSS16 3
  61
  62 #define SVM_FEATURE_LBRV           (1 <<  1)
  63 #define SVM_FEATURE_SVML           (1 <<  2)
  64 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  65 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  66 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  67 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  68 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  69
  70 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  71
  72 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  73 #define TSC_RATIO_MIN           0x0000000000000001ULL
  74 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  75
  76 static bool erratum_383_found __read_mostly;
  77
  78 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  79
  80 /*
  81  * Set osvw_len to higher value when updated Revision Guides
  82  * are published and we know what the new status bits are
  83  */
  84 static uint64_t osvw_len = 4, osvw_status;
  85
  86 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  87 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  88
  89 static const struct svm_direct_access_msrs {
  90         u32 index;   /* Index of the MSR */
  91         bool always; /* True if intercept is initially cleared */
  92 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
  93         { .index = MSR_STAR,                            .always = true  },
  94         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  95         { .index = MSR_IA32_SYSENTER_EIP,               .always = false },
  96         { .index = MSR_IA32_SYSENTER_ESP,               .always = false },
  97 #ifdef CONFIG_X86_64
  98         { .index = MSR_GS_BASE,                         .always = true  },
  99         { .index = MSR_FS_BASE,                         .always = true  },
 100         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 101         { .index = MSR_LSTAR,                           .always = true  },
 102         { .index = MSR_CSTAR,                           .always = true  },
 103         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 104 #endif
 105         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 106         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 107         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 108         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 109         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 110         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 111         { .index = MSR_EFER,                            .always = false },
 112         { .index = MSR_IA32_CR_PAT,                     .always = false },
 113         { .index = MSR_AMD64_SEV_ES_GHCB,               .always = true  },
 114         { .index = MSR_INVALID,                         .always = false },
 115 };
 116
 117 /*
 118  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 119  * pause_filter_count: On processors that support Pause filtering(indicated
 120  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 121  *      count value. On VMRUN this value is loaded into an internal counter.
 122  *      Each time a pause instruction is executed, this counter is decremented
 123  *      until it reaches zero at which time a #VMEXIT is generated if pause
 124  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 125  *      Intercept Filtering for more details.
 126  *      This also indicate if ple logic enabled.
 127  *
 128  * pause_filter_thresh: In addition, some processor families support advanced
 129  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 130  *      the amount of time a guest is allowed to execute in a pause loop.
 131  *      In this mode, a 16-bit pause filter threshold field is added in the
 132  *      VMCB. The threshold value is a cycle count that is used to reset the
 133  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 134  *      count value from VMCB into an internal counter. Then, on each pause
 135  *      instruction the hardware checks the elapsed number of cycles since
 136  *      the most recent pause instruction against the pause filter threshold.
 137  *      If the elapsed cycle count is greater than the pause filter threshold,
 138  *      then the internal pause count is reloaded from the VMCB and execution
 139  *      continues. If the elapsed cycle count is less than the pause filter
 140  *      threshold, then the internal pause count is decremented. If the count
 141  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 142  *      triggered. If advanced pause filtering is supported and pause filter
 143  *      threshold field is set to zero, the filter will operate in the simpler,
 144  *      count only mode.
 145  */
 146
 147 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 148 module_param(pause_filter_thresh, ushort, 0444);
 149
 150 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 151 module_param(pause_filter_count, ushort, 0444);
 152
 153 /* Default doubles per-vcpu window every exit. */
 154 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 155 module_param(pause_filter_count_grow, ushort, 0444);
 156
 157 /* Default resets per-vcpu window every exit to pause_filter_count. */
 158 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 159 module_param(pause_filter_count_shrink, ushort, 0444);
 160
 161 /* Default is to compute the maximum so we can never overflow. */
 162 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(pause_filter_count_max, ushort, 0444);
 164
 165 /*
 166  * Use nested page tables by default.  Note, NPT may get forced off by
 167  * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
 168  */
 169 bool npt_enabled = true;
 170 module_param_named(npt, npt_enabled, bool, 0444);
 171
 172 /* allow nested virtualization in KVM/SVM */
 173 static int nested = true;
 174 module_param(nested, int, S_IRUGO);
 175
 176 /* enable/disable Next RIP Save */
 177 static int nrips = true;
 178 module_param(nrips, int, 0444);
 179
 180 /* enable/disable Virtual VMLOAD VMSAVE */
 181 static int vls = true;
 182 module_param(vls, int, 0444);
 183
 184 /* enable/disable Virtual GIF */
 185 static int vgif = true;
 186 module_param(vgif, int, 0444);
 187
 188 bool __read_mostly dump_invalid_vmcb;
 189 module_param(dump_invalid_vmcb, bool, 0644);
 190
 191 static bool svm_gp_erratum_intercept = true;
 192
 193 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 194
 195 static unsigned long iopm_base;
 196
 197 struct kvm_ldttss_desc {
 198         u16 limit0;
 199         u16 base0;
 200         unsigned base1:8, type:5, dpl:2, p:1;
 201         unsigned limit1:4, zero0:3, g:1, base2:8;
 202         u32 base3;
 203         u32 zero1;
 204 } __attribute__((packed));
 205
 206 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 207
 208 /*
 209  * Only MSR_TSC_AUX is switched via the user return hook.  EFER is switched via
 210  * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
 211  *
 212  * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
 213  * defer the restoration of TSC_AUX until the CPU returns to userspace.
 214  */
 215 static int tsc_aux_uret_slot __read_mostly = -1;
 216
 217 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 218
 219 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 220 #define MSRS_RANGE_SIZE 2048
 221 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 222
 223 u32 svm_msrpm_offset(u32 msr)
 224 {
 225         u32 offset;
 226         int i;
 227
 228         for (i = 0; i < NUM_MSR_MAPS; i++) {
 229                 if (msr < msrpm_ranges[i] ||
 230                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 231                         continue;
 232
 233                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 234                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 235
 236                 /* Now we have the u8 offset - but need the u32 offset */
 237                 return offset / 4;
 238         }
 239
 240         /* MSR not in any range */
 241         return MSR_INVALID;
 242 }
 243
 244 #define MAX_INST_SIZE 15
 245
 246 static int get_max_npt_level(void)
 247 {
 248 #ifdef CONFIG_X86_64
 249         return PT64_ROOT_4LEVEL;
 250 #else
 251         return PT32E_ROOT_LEVEL;
 252 #endif
 253 }
 254
 255 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 256 {
 257         struct vcpu_svm *svm = to_svm(vcpu);
 258         u64 old_efer = vcpu->arch.efer;
 259         vcpu->arch.efer = efer;
 260
 261         if (!npt_enabled) {
 262                 /* Shadow paging assumes NX to be available.  */
 263                 efer |= EFER_NX;
 264
 265                 if (!(efer & EFER_LMA))
 266                         efer &= ~EFER_LME;
 267         }
 268
 269         if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
 270                 if (!(efer & EFER_SVME)) {
 271                         svm_leave_nested(svm);
 272                         svm_set_gif(svm, true);
 273                         /* #GP intercept is still needed for vmware backdoor */
 274                         if (!enable_vmware_backdoor)
 275                                 clr_exception_intercept(svm, GP_VECTOR);
 276
 277                         /*
 278                          * Free the nested guest state, unless we are in SMM.
 279                          * In this case we will return to the nested guest
 280                          * as soon as we leave SMM.
 281                          */
 282                         if (!is_smm(vcpu))
 283                                 svm_free_nested(svm);
 284
 285                 } else {
 286                         int ret = svm_allocate_nested(svm);
 287
 288                         if (ret) {
 289                                 vcpu->arch.efer = old_efer;
 290                                 return ret;
 291                         }
 292
 293                         if (svm_gp_erratum_intercept)
 294                                 set_exception_intercept(svm, GP_VECTOR);
 295                 }
 296         }
 297
 298         svm->vmcb->save.efer = efer | EFER_SVME;
 299         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
 300         return 0;
 301 }
 302
 303 static int is_external_interrupt(u32 info)
 304 {
 305         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 306         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 307 }
 308
 309 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 310 {
 311         struct vcpu_svm *svm = to_svm(vcpu);
 312         u32 ret = 0;
 313
 314         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 315                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 316         return ret;
 317 }
 318
 319 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 320 {
 321         struct vcpu_svm *svm = to_svm(vcpu);
 322
 323         if (mask == 0)
 324                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 325         else
 326                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 327
 328 }
 329
 330 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 331 {
 332         struct vcpu_svm *svm = to_svm(vcpu);
 333
 334         /*
 335          * SEV-ES does not expose the next RIP. The RIP update is controlled by
 336          * the type of exit and the #VC handler in the guest.
 337          */
 338         if (sev_es_guest(vcpu->kvm))
 339                 goto done;
 340
 341         if (nrips && svm->vmcb->control.next_rip != 0) {
 342                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 343                 svm->next_rip = svm->vmcb->control.next_rip;
 344         }
 345
 346         if (!svm->next_rip) {
 347                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 348                         return 0;
 349         } else {
 350                 kvm_rip_write(vcpu, svm->next_rip);
 351         }
 352
 353 done:
 354         svm_set_interrupt_shadow(vcpu, 0);
 355
 356         return 1;
 357 }
 358
 359 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 360 {
 361         struct vcpu_svm *svm = to_svm(vcpu);
 362         unsigned nr = vcpu->arch.exception.nr;
 363         bool has_error_code = vcpu->arch.exception.has_error_code;
 364         u32 error_code = vcpu->arch.exception.error_code;
 365
 366         kvm_deliver_exception_payload(vcpu);
 367
 368         if (nr == BP_VECTOR && !nrips) {
 369                 unsigned long rip, old_rip = kvm_rip_read(vcpu);
 370
 371                 /*
 372                  * For guest debugging where we have to reinject #BP if some
 373                  * INT3 is guest-owned:
 374                  * Emulate nRIP by moving RIP forward. Will fail if injection
 375                  * raises a fault that is not intercepted. Still better than
 376                  * failing in all cases.
 377                  */
 378                 (void)skip_emulated_instruction(vcpu);
 379                 rip = kvm_rip_read(vcpu);
 380                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 381                 svm->int3_injected = rip - old_rip;
 382         }
 383
 384         svm->vmcb->control.event_inj = nr
 385                 | SVM_EVTINJ_VALID
 386                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 387                 | SVM_EVTINJ_TYPE_EXEPT;
 388         svm->vmcb->control.event_inj_err = error_code;
 389 }
 390
 391 static void svm_init_erratum_383(void)
 392 {
 393         u32 low, high;
 394         int err;
 395         u64 val;
 396
 397         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 398                 return;
 399
 400         /* Use _safe variants to not break nested virtualization */
 401         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 402         if (err)
 403                 return;
 404
 405         val |= (1ULL << 47);
 406
 407         low  = lower_32_bits(val);
 408         high = upper_32_bits(val);
 409
 410         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 411
 412         erratum_383_found = true;
 413 }
 414
 415 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 416 {
 417         /*
 418          * Guests should see errata 400 and 415 as fixed (assuming that
 419          * HLT and IO instructions are intercepted).
 420          */
 421         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 422         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 423
 424         /*
 425          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 426          * all osvw.status bits inside that length, including bit 0 (which is
 427          * reserved for erratum 298), are valid. However, if host processor's
 428          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 429          * be conservative here and therefore we tell the guest that erratum 298
 430          * is present (because we really don't know).
 431          */
 432         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 433                 vcpu->arch.osvw.status |= 1;
 434 }
 435
 436 static int has_svm(void)
 437 {
 438         const char *msg;
 439
 440         if (!cpu_has_svm(&msg)) {
 441                 printk(KERN_INFO "has_svm: %s\n", msg);
 442                 return 0;
 443         }
 444
 445         if (sev_active()) {
 446                 pr_info("KVM is unsupported when running as an SEV guest\n");
 447                 return 0;
 448         }
 449
 450         return 1;
 451 }
 452
 453 static void svm_hardware_disable(void)
 454 {
 455         /* Make sure we clean up behind us */
 456         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 457                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 458
 459         cpu_svm_disable();
 460
 461         amd_pmu_disable_virt();
 462 }
 463
 464 static int svm_hardware_enable(void)
 465 {
 466
 467         struct svm_cpu_data *sd;
 468         uint64_t efer;
 469         struct desc_struct *gdt;
 470         int me = raw_smp_processor_id();
 471
 472         rdmsrl(MSR_EFER, efer);
 473         if (efer & EFER_SVME)
 474                 return -EBUSY;
 475
 476         if (!has_svm()) {
 477                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 478                 return -EINVAL;
 479         }
 480         sd = per_cpu(svm_data, me);
 481         if (!sd) {
 482                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 483                 return -EINVAL;
 484         }
 485
 486         sd->asid_generation = 1;
 487         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 488         sd->next_asid = sd->max_asid + 1;
 489         sd->min_asid = max_sev_asid + 1;
 490
 491         gdt = get_current_gdt_rw();
 492         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 493
 494         wrmsrl(MSR_EFER, efer | EFER_SVME);
 495
 496         wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
 497
 498         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 499                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 500                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 501         }
 502
 503
 504         /*
 505          * Get OSVW bits.
 506          *
 507          * Note that it is possible to have a system with mixed processor
 508          * revisions and therefore different OSVW bits. If bits are not the same
 509          * on different processors then choose the worst case (i.e. if erratum
 510          * is present on one processor and not on another then assume that the
 511          * erratum is present everywhere).
 512          */
 513         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 514                 uint64_t len, status = 0;
 515                 int err;
 516
 517                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 518                 if (!err)
 519                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 520                                                       &err);
 521
 522                 if (err)
 523                         osvw_status = osvw_len = 0;
 524                 else {
 525                         if (len < osvw_len)
 526                                 osvw_len = len;
 527                         osvw_status |= status;
 528                         osvw_status &= (1ULL << osvw_len) - 1;
 529                 }
 530         } else
 531                 osvw_status = osvw_len = 0;
 532
 533         svm_init_erratum_383();
 534
 535         amd_pmu_enable_virt();
 536
 537         return 0;
 538 }
 539
 540 static void svm_cpu_uninit(int cpu)
 541 {
 542         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
 543
 544         if (!sd)
 545                 return;
 546
 547         per_cpu(svm_data, cpu) = NULL;
 548         kfree(sd->sev_vmcbs);
 549         __free_page(sd->save_area);
 550         kfree(sd);
 551 }
 552
 553 static int svm_cpu_init(int cpu)
 554 {
 555         struct svm_cpu_data *sd;
 556         int ret = -ENOMEM;
 557
 558         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 559         if (!sd)
 560                 return ret;
 561         sd->cpu = cpu;
 562         sd->save_area = alloc_page(GFP_KERNEL);
 563         if (!sd->save_area)
 564                 goto free_cpu_data;
 565
 566         clear_page(page_address(sd->save_area));
 567
 568         ret = sev_cpu_init(sd);
 569         if (ret)
 570                 goto free_save_area;
 571
 572         per_cpu(svm_data, cpu) = sd;
 573
 574         return 0;
 575
 576 free_save_area:
 577         __free_page(sd->save_area);
 578 free_cpu_data:
 579         kfree(sd);
 580         return ret;
 581
 582 }
 583
 584 static int direct_access_msr_slot(u32 msr)
 585 {
 586         u32 i;
 587
 588         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 589                 if (direct_access_msrs[i].index == msr)
 590                         return i;
 591
 592         return -ENOENT;
 593 }
 594
 595 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
 596                                      int write)
 597 {
 598         struct vcpu_svm *svm = to_svm(vcpu);
 599         int slot = direct_access_msr_slot(msr);
 600
 601         if (slot == -ENOENT)
 602                 return;
 603
 604         /* Set the shadow bitmaps to the desired intercept states */
 605         if (read)
 606                 set_bit(slot, svm->shadow_msr_intercept.read);
 607         else
 608                 clear_bit(slot, svm->shadow_msr_intercept.read);
 609
 610         if (write)
 611                 set_bit(slot, svm->shadow_msr_intercept.write);
 612         else
 613                 clear_bit(slot, svm->shadow_msr_intercept.write);
 614 }
 615
 616 static bool valid_msr_intercept(u32 index)
 617 {
 618         return direct_access_msr_slot(index) != -ENOENT;
 619 }
 620
 621 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 622 {
 623         u8 bit_write;
 624         unsigned long tmp;
 625         u32 offset;
 626         u32 *msrpm;
 627
 628         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 629                                       to_svm(vcpu)->msrpm;
 630
 631         offset    = svm_msrpm_offset(msr);
 632         bit_write = 2 * (msr & 0x0f) + 1;
 633         tmp       = msrpm[offset];
 634
 635         BUG_ON(offset == MSR_INVALID);
 636
 637         return !!test_bit(bit_write,  &tmp);
 638 }
 639
 640 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
 641                                         u32 msr, int read, int write)
 642 {
 643         u8 bit_read, bit_write;
 644         unsigned long tmp;
 645         u32 offset;
 646
 647         /*
 648          * If this warning triggers extend the direct_access_msrs list at the
 649          * beginning of the file
 650          */
 651         WARN_ON(!valid_msr_intercept(msr));
 652
 653         /* Enforce non allowed MSRs to trap */
 654         if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
 655                 read = 0;
 656
 657         if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
 658                 write = 0;
 659
 660         offset    = svm_msrpm_offset(msr);
 661         bit_read  = 2 * (msr & 0x0f);
 662         bit_write = 2 * (msr & 0x0f) + 1;
 663         tmp       = msrpm[offset];
 664
 665         BUG_ON(offset == MSR_INVALID);
 666
 667         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 668         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 669
 670         msrpm[offset] = tmp;
 671 }
 672
 673 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 674                           int read, int write)
 675 {
 676         set_shadow_msr_intercept(vcpu, msr, read, write);
 677         set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
 678 }
 679
 680 u32 *svm_vcpu_alloc_msrpm(void)
 681 {
 682         unsigned int order = get_order(MSRPM_SIZE);
 683         struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order);
 684         u32 *msrpm;
 685
 686         if (!pages)
 687                 return NULL;
 688
 689         msrpm = page_address(pages);
 690         memset(msrpm, 0xff, PAGE_SIZE * (1 << order));
 691
 692         return msrpm;
 693 }
 694
 695 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
 696 {
 697         int i;
 698
 699         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 700                 if (!direct_access_msrs[i].always)
 701                         continue;
 702                 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
 703         }
 704 }
 705
 706
 707 void svm_vcpu_free_msrpm(u32 *msrpm)
 708 {
 709         __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE));
 710 }
 711
 712 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
 713 {
 714         struct vcpu_svm *svm = to_svm(vcpu);
 715         u32 i;
 716
 717         /*
 718          * Set intercept permissions for all direct access MSRs again. They
 719          * will automatically get filtered through the MSR filter, so we are
 720          * back in sync after this.
 721          */
 722         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 723                 u32 msr = direct_access_msrs[i].index;
 724                 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
 725                 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
 726
 727                 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
 728         }
 729 }
 730
 731 static void add_msr_offset(u32 offset)
 732 {
 733         int i;
 734
 735         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 736
 737                 /* Offset already in list? */
 738                 if (msrpm_offsets[i] == offset)
 739                         return;
 740
 741                 /* Slot used by another offset? */
 742                 if (msrpm_offsets[i] != MSR_INVALID)
 743                         continue;
 744
 745                 /* Add offset to list */
 746                 msrpm_offsets[i] = offset;
 747
 748                 return;
 749         }
 750
 751         /*
 752          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 753          * increase MSRPM_OFFSETS in this case.
 754          */
 755         BUG();
 756 }
 757
 758 static void init_msrpm_offsets(void)
 759 {
 760         int i;
 761
 762         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 763
 764         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 765                 u32 offset;
 766
 767                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 768                 BUG_ON(offset == MSR_INVALID);
 769
 770                 add_msr_offset(offset);
 771         }
 772 }
 773
 774 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
 775 {
 776         struct vcpu_svm *svm = to_svm(vcpu);
 777
 778         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 779         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 780         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 781         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 782         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 783 }
 784
 785 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
 786 {
 787         struct vcpu_svm *svm = to_svm(vcpu);
 788
 789         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 790         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 791         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 792         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 793         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 794 }
 795
 796 void disable_nmi_singlestep(struct vcpu_svm *svm)
 797 {
 798         svm->nmi_singlestep = false;
 799
 800         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 801                 /* Clear our flags if they were not set by the guest */
 802                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 803                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 804                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 805                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 806         }
 807 }
 808
 809 static void grow_ple_window(struct kvm_vcpu *vcpu)
 810 {
 811         struct vcpu_svm *svm = to_svm(vcpu);
 812         struct vmcb_control_area *control = &svm->vmcb->control;
 813         int old = control->pause_filter_count;
 814
 815         control->pause_filter_count = __grow_ple_window(old,
 816                                                         pause_filter_count,
 817                                                         pause_filter_count_grow,
 818                                                         pause_filter_count_max);
 819
 820         if (control->pause_filter_count != old) {
 821                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 822                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 823                                             control->pause_filter_count, old);
 824         }
 825 }
 826
 827 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 828 {
 829         struct vcpu_svm *svm = to_svm(vcpu);
 830         struct vmcb_control_area *control = &svm->vmcb->control;
 831         int old = control->pause_filter_count;
 832
 833         control->pause_filter_count =
 834                                 __shrink_ple_window(old,
 835                                                     pause_filter_count,
 836                                                     pause_filter_count_shrink,
 837                                                     pause_filter_count);
 838         if (control->pause_filter_count != old) {
 839                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 840                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 841                                             control->pause_filter_count, old);
 842         }
 843 }
 844
 845 /*
 846  * The default MMIO mask is a single bit (excluding the present bit),
 847  * which could conflict with the memory encryption bit. Check for
 848  * memory encryption support and override the default MMIO mask if
 849  * memory encryption is enabled.
 850  */
 851 static __init void svm_adjust_mmio_mask(void)
 852 {
 853         unsigned int enc_bit, mask_bit;
 854         u64 msr, mask;
 855
 856         /* If there is no memory encryption support, use existing mask */
 857         if (cpuid_eax(0x80000000) < 0x8000001f)
 858                 return;
 859
 860         /* If memory encryption is not enabled, use existing mask */
 861         rdmsrl(MSR_K8_SYSCFG, msr);
 862         if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 863                 return;
 864
 865         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 866         mask_bit = boot_cpu_data.x86_phys_bits;
 867
 868         /* Increment the mask bit if it is the same as the encryption bit */
 869         if (enc_bit == mask_bit)
 870                 mask_bit++;
 871
 872         /*
 873          * If the mask bit location is below 52, then some bits above the
 874          * physical addressing limit will always be reserved, so use the
 875          * rsvd_bits() function to generate the mask. This mask, along with
 876          * the present bit, will be used to generate a page fault with
 877          * PFER.RSV = 1.
 878          *
 879          * If the mask bit location is 52 (or above), then clear the mask.
 880          */
 881         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 882
 883         kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
 884 }
 885
 886 static void svm_hardware_teardown(void)
 887 {
 888         int cpu;
 889
 890         sev_hardware_teardown();
 891
 892         for_each_possible_cpu(cpu)
 893                 svm_cpu_uninit(cpu);
 894
 895         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT),
 896         get_order(IOPM_SIZE));
 897         iopm_base = 0;
 898 }
 899
 900 static __init void svm_set_cpu_caps(void)
 901 {
 902         kvm_set_cpu_caps();
 903
 904         supported_xss = 0;
 905
 906         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 907         if (nested) {
 908                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 909
 910                 if (nrips)
 911                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 912
 913                 if (npt_enabled)
 914                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 915
 916                 /* Nested VM can receive #VMEXIT instead of triggering #GP */
 917                 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
 918         }
 919
 920         /* CPUID 0x80000008 */
 921         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 922             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 923                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 924
 925         /* CPUID 0x8000001F (SME/SEV features) */
 926         sev_set_cpu_caps();
 927 }
 928
 929 static __init int svm_hardware_setup(void)
 930 {
 931         int cpu;
 932         struct page *iopm_pages;
 933         void *iopm_va;
 934         int r;
 935         unsigned int order = get_order(IOPM_SIZE);
 936
 937         iopm_pages = alloc_pages(GFP_KERNEL, order);
 938
 939         if (!iopm_pages)
 940                 return -ENOMEM;
 941
 942         iopm_va = page_address(iopm_pages);
 943         memset(iopm_va, 0xff, PAGE_SIZE * (1 << order));
 944         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 945
 946         init_msrpm_offsets();
 947
 948         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 949
 950         if (boot_cpu_has(X86_FEATURE_NX))
 951                 kvm_enable_efer_bits(EFER_NX);
 952
 953         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 954                 kvm_enable_efer_bits(EFER_FFXSR);
 955
 956         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 957                 kvm_has_tsc_control = true;
 958                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 959                 kvm_tsc_scaling_ratio_frac_bits = 32;
 960         }
 961
 962         tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
 963
 964         /* Check for pause filtering support */
 965         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 966                 pause_filter_count = 0;
 967                 pause_filter_thresh = 0;
 968         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 969                 pause_filter_thresh = 0;
 970         }
 971
 972         if (nested) {
 973                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 974                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 975         }
 976
 977         /*
 978          * KVM's MMU doesn't support using 2-level paging for itself, and thus
 979          * NPT isn't supported if the host is using 2-level paging since host
 980          * CR4 is unchanged on VMRUN.
 981          */
 982         if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
 983                 npt_enabled = false;
 984
 985         if (!boot_cpu_has(X86_FEATURE_NPT))
 986                 npt_enabled = false;
 987
 988         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
 989         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
 990
 991         /* Note, SEV setup consumes npt_enabled. */
 992         sev_hardware_setup();
 993
 994         svm_adjust_mmio_mask();
 995
 996         for_each_possible_cpu(cpu) {
 997                 r = svm_cpu_init(cpu);
 998                 if (r)
 999                         goto err;
1000         }
1001
1002         if (nrips) {
1003                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1004                         nrips = false;
1005         }
1006
1007         if (avic) {
1008                 if (!npt_enabled ||
1009                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1010                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1011                         avic = false;
1012                 } else {
1013                         pr_info("AVIC enabled\n");
1014
1015                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1016                 }
1017         }
1018
1019         if (vls) {
1020                 if (!npt_enabled ||
1021                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1022                     !IS_ENABLED(CONFIG_X86_64)) {
1023                         vls = false;
1024                 } else {
1025                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1026                 }
1027         }
1028
1029         if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
1030                 svm_gp_erratum_intercept = false;
1031
1032         if (vgif) {
1033                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1034                         vgif = false;
1035                 else
1036                         pr_info("Virtual GIF supported\n");
1037         }
1038
1039         svm_set_cpu_caps();
1040
1041         /*
1042          * It seems that on AMD processors PTE's accessed bit is
1043          * being set by the CPU hardware before the NPF vmexit.
1044          * This is not expected behaviour and our tests fail because
1045          * of it.
1046          * A workaround here is to disable support for
1047          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1048          * In this case userspace can know if there is support using
1049          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1050          * it
1051          * If future AMD CPU models change the behaviour described above,
1052          * this variable can be changed accordingly
1053          */
1054         allow_smaller_maxphyaddr = !npt_enabled;
1055
1056         return 0;
1057
1058 err:
1059         svm_hardware_teardown();
1060         return r;
1061 }
1062
1063 static void init_seg(struct vmcb_seg *seg)
1064 {
1065         seg->selector = 0;
1066         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1067                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1068         seg->limit = 0xffff;
1069         seg->base = 0;
1070 }
1071
1072 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1073 {
1074         seg->selector = 0;
1075         seg->attrib = SVM_SELECTOR_P_MASK | type;
1076         seg->limit = 0xffff;
1077         seg->base = 0;
1078 }
1079
1080 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1081 {
1082         struct vcpu_svm *svm = to_svm(vcpu);
1083         u64 g_tsc_offset = 0;
1084
1085         if (is_guest_mode(vcpu)) {
1086                 /* Write L1's TSC offset.  */
1087                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1088                                svm->vmcb01.ptr->control.tsc_offset;
1089                 svm->vmcb01.ptr->control.tsc_offset = offset;
1090         }
1091
1092         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1093                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1094                                    offset);
1095
1096         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1097
1098         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1099         return svm->vmcb->control.tsc_offset;
1100 }
1101
1102 /* Evaluate instruction intercepts that depend on guest CPUID features. */
1103 static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu,
1104                                               struct vcpu_svm *svm)
1105 {
1106         /*
1107          * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1108          * roots, or if INVPCID is disabled in the guest to inject #UD.
1109          */
1110         if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1111                 if (!npt_enabled ||
1112                     !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1113                         svm_set_intercept(svm, INTERCEPT_INVPCID);
1114                 else
1115                         svm_clr_intercept(svm, INTERCEPT_INVPCID);
1116         }
1117
1118         if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) {
1119                 if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1120                         svm_clr_intercept(svm, INTERCEPT_RDTSCP);
1121                 else
1122                         svm_set_intercept(svm, INTERCEPT_RDTSCP);
1123         }
1124 }
1125
1126 static void init_vmcb(struct kvm_vcpu *vcpu)
1127 {
1128         struct vcpu_svm *svm = to_svm(vcpu);
1129         struct vmcb_control_area *control = &svm->vmcb->control;
1130         struct vmcb_save_area *save = &svm->vmcb->save;
1131
1132         vcpu->arch.hflags = 0;
1133
1134         svm_set_intercept(svm, INTERCEPT_CR0_READ);
1135         svm_set_intercept(svm, INTERCEPT_CR3_READ);
1136         svm_set_intercept(svm, INTERCEPT_CR4_READ);
1137         svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1138         svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1139         svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1140         if (!kvm_vcpu_apicv_active(vcpu))
1141                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1142
1143         set_dr_intercepts(svm);
1144
1145         set_exception_intercept(svm, PF_VECTOR);
1146         set_exception_intercept(svm, UD_VECTOR);
1147         set_exception_intercept(svm, MC_VECTOR);
1148         set_exception_intercept(svm, AC_VECTOR);
1149         set_exception_intercept(svm, DB_VECTOR);
1150         /*
1151          * Guest access to VMware backdoor ports could legitimately
1152          * trigger #GP because of TSS I/O permission bitmap.
1153          * We intercept those #GP and allow access to them anyway
1154          * as VMware does.
1155          */
1156         if (enable_vmware_backdoor)
1157                 set_exception_intercept(svm, GP_VECTOR);
1158
1159         svm_set_intercept(svm, INTERCEPT_INTR);
1160         svm_set_intercept(svm, INTERCEPT_NMI);
1161         svm_set_intercept(svm, INTERCEPT_SMI);
1162         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1163         svm_set_intercept(svm, INTERCEPT_RDPMC);
1164         svm_set_intercept(svm, INTERCEPT_CPUID);
1165         svm_set_intercept(svm, INTERCEPT_INVD);
1166         svm_set_intercept(svm, INTERCEPT_INVLPG);
1167         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1168         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1169         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1170         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1171         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1172         svm_set_intercept(svm, INTERCEPT_VMRUN);
1173         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1174         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1175         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1176         svm_set_intercept(svm, INTERCEPT_STGI);
1177         svm_set_intercept(svm, INTERCEPT_CLGI);
1178         svm_set_intercept(svm, INTERCEPT_SKINIT);
1179         svm_set_intercept(svm, INTERCEPT_WBINVD);
1180         svm_set_intercept(svm, INTERCEPT_XSETBV);
1181         svm_set_intercept(svm, INTERCEPT_RDPRU);
1182         svm_set_intercept(svm, INTERCEPT_RSM);
1183
1184         if (!kvm_mwait_in_guest(vcpu->kvm)) {
1185                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1186                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1187         }
1188
1189         if (!kvm_hlt_in_guest(vcpu->kvm))
1190                 svm_set_intercept(svm, INTERCEPT_HLT);
1191
1192         control->iopm_base_pa = __sme_set(iopm_base);
1193         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1194         control->int_ctl = V_INTR_MASKING_MASK;
1195
1196         init_seg(&save->es);
1197         init_seg(&save->ss);
1198         init_seg(&save->ds);
1199         init_seg(&save->fs);
1200         init_seg(&save->gs);
1201
1202         save->cs.selector = 0xf000;
1203         save->cs.base = 0xffff0000;
1204         /* Executable/Readable Code Segment */
1205         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1206                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1207         save->cs.limit = 0xffff;
1208
1209         save->gdtr.limit = 0xffff;
1210         save->idtr.limit = 0xffff;
1211
1212         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1213         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1214
1215         svm_set_cr4(vcpu, 0);
1216         svm_set_efer(vcpu, 0);
1217         save->dr6 = 0xffff0ff0;
1218         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
1219         save->rip = 0x0000fff0;
1220         vcpu->arch.regs[VCPU_REGS_RIP] = save->rip;
1221
1222         /*
1223          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1224          * It also updates the guest-visible cr0 value.
1225          */
1226         svm_set_cr0(vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1227         kvm_mmu_reset_context(vcpu);
1228
1229         save->cr4 = X86_CR4_PAE;
1230         /* rdx = ?? */
1231
1232         if (npt_enabled) {
1233                 /* Setup VMCB for Nested Paging */
1234                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1235                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1236                 clr_exception_intercept(svm, PF_VECTOR);
1237                 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1238                 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1239                 save->g_pat = vcpu->arch.pat;
1240                 save->cr3 = 0;
1241                 save->cr4 = 0;
1242         }
1243         svm->current_vmcb->asid_generation = 0;
1244         svm->asid = 0;
1245
1246         svm->nested.vmcb12_gpa = INVALID_GPA;
1247         svm->nested.last_vmcb12_gpa = INVALID_GPA;
1248         vcpu->arch.hflags = 0;
1249
1250         if (!kvm_pause_in_guest(vcpu->kvm)) {
1251                 control->pause_filter_count = pause_filter_count;
1252                 if (pause_filter_thresh)
1253                         control->pause_filter_thresh = pause_filter_thresh;
1254                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1255         } else {
1256                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1257         }
1258
1259         svm_recalc_instruction_intercepts(vcpu, svm);
1260
1261         /*
1262          * If the host supports V_SPEC_CTRL then disable the interception
1263          * of MSR_IA32_SPEC_CTRL.
1264          */
1265         if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
1266                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
1267
1268         if (kvm_vcpu_apicv_active(vcpu))
1269                 avic_init_vmcb(svm);
1270
1271         if (vgif) {
1272                 svm_clr_intercept(svm, INTERCEPT_STGI);
1273                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1274                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1275         }
1276
1277         if (sev_guest(vcpu->kvm)) {
1278                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1279                 clr_exception_intercept(svm, UD_VECTOR);
1280
1281                 if (sev_es_guest(vcpu->kvm)) {
1282                         /* Perform SEV-ES specific VMCB updates */
1283                         sev_es_init_vmcb(svm);
1284                 }
1285         }
1286
1287         vmcb_mark_all_dirty(svm->vmcb);
1288
1289         enable_gif(svm);
1290
1291 }
1292
1293 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1294 {
1295         struct vcpu_svm *svm = to_svm(vcpu);
1296         u32 dummy;
1297         u32 eax = 1;
1298
1299         svm->spec_ctrl = 0;
1300         svm->virt_spec_ctrl = 0;
1301
1302         if (!init_event) {
1303                 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1304                                        MSR_IA32_APICBASE_ENABLE;
1305                 if (kvm_vcpu_is_reset_bsp(vcpu))
1306                         vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
1307         }
1308         init_vmcb(vcpu);
1309
1310         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1311         kvm_rdx_write(vcpu, eax);
1312
1313         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1314                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1315 }
1316
1317 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb)
1318 {
1319         svm->current_vmcb = target_vmcb;
1320         svm->vmcb = target_vmcb->ptr;
1321 }
1322
1323 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1324 {
1325         struct vcpu_svm *svm;
1326         struct page *vmcb01_page;
1327         struct page *vmsa_page = NULL;
1328         int err;
1329
1330         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1331         svm = to_svm(vcpu);
1332
1333         err = -ENOMEM;
1334         vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1335         if (!vmcb01_page)
1336                 goto out;
1337
1338         if (sev_es_guest(vcpu->kvm)) {
1339                 /*
1340                  * SEV-ES guests require a separate VMSA page used to contain
1341                  * the encrypted register state of the guest.
1342                  */
1343                 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1344                 if (!vmsa_page)
1345                         goto error_free_vmcb_page;
1346
1347                 /*
1348                  * SEV-ES guests maintain an encrypted version of their FPU
1349                  * state which is restored and saved on VMRUN and VMEXIT.
1350                  * Free the fpu structure to prevent KVM from attempting to
1351                  * access the FPU state.
1352                  */
1353                 kvm_free_guest_fpu(vcpu);
1354         }
1355
1356         err = avic_init_vcpu(svm);
1357         if (err)
1358                 goto error_free_vmsa_page;
1359
1360         /* We initialize this flag to true to make sure that the is_running
1361          * bit would be set the first time the vcpu is loaded.
1362          */
1363         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1364                 svm->avic_is_running = true;
1365
1366         svm->msrpm = svm_vcpu_alloc_msrpm();
1367         if (!svm->msrpm) {
1368                 err = -ENOMEM;
1369                 goto error_free_vmsa_page;
1370         }
1371
1372         svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1373
1374         svm->vmcb01.ptr = page_address(vmcb01_page);
1375         svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT);
1376
1377         if (vmsa_page)
1378                 svm->vmsa = page_address(vmsa_page);
1379
1380         svm->guest_state_loaded = false;
1381
1382         svm_switch_vmcb(svm, &svm->vmcb01);
1383         init_vmcb(vcpu);
1384
1385         svm_init_osvw(vcpu);
1386         vcpu->arch.microcode_version = 0x01000065;
1387
1388         if (sev_es_guest(vcpu->kvm))
1389                 /* Perform SEV-ES specific VMCB creation updates */
1390                 sev_es_create_vcpu(svm);
1391
1392         return 0;
1393
1394 error_free_vmsa_page:
1395         if (vmsa_page)
1396                 __free_page(vmsa_page);
1397 error_free_vmcb_page:
1398         __free_page(vmcb01_page);
1399 out:
1400         return err;
1401 }
1402
1403 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1404 {
1405         int i;
1406
1407         for_each_online_cpu(i)
1408                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1409 }
1410
1411 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1412 {
1413         struct vcpu_svm *svm = to_svm(vcpu);
1414
1415         /*
1416          * The vmcb page can be recycled, causing a false negative in
1417          * svm_vcpu_load(). So, ensure that no logical CPU has this
1418          * vmcb page recorded as its current vmcb.
1419          */
1420         svm_clear_current_vmcb(svm->vmcb);
1421
1422         svm_free_nested(svm);
1423
1424         sev_free_vcpu(vcpu);
1425
1426         __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT));
1427         __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE));
1428 }
1429
1430 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1431 {
1432         struct vcpu_svm *svm = to_svm(vcpu);
1433         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1434
1435         if (svm->guest_state_loaded)
1436                 return;
1437
1438         /*
1439          * Save additional host state that will be restored on VMEXIT (sev-es)
1440          * or subsequent vmload of host save area.
1441          */
1442         if (sev_es_guest(vcpu->kvm)) {
1443                 sev_es_prepare_guest_switch(svm, vcpu->cpu);
1444         } else {
1445                 vmsave(__sme_page_pa(sd->save_area));
1446         }
1447
1448         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1449                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1450                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1451                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1452                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1453                 }
1454         }
1455
1456         if (likely(tsc_aux_uret_slot >= 0))
1457                 kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull);
1458
1459         svm->guest_state_loaded = true;
1460 }
1461
1462 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1463 {
1464         to_svm(vcpu)->guest_state_loaded = false;
1465 }
1466
1467 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1468 {
1469         struct vcpu_svm *svm = to_svm(vcpu);
1470         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1471
1472         if (sd->current_vmcb != svm->vmcb) {
1473                 sd->current_vmcb = svm->vmcb;
1474                 indirect_branch_prediction_barrier();
1475         }
1476         avic_vcpu_load(vcpu, cpu);
1477 }
1478
1479 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1480 {
1481         avic_vcpu_put(vcpu);
1482         svm_prepare_host_switch(vcpu);
1483
1484         ++vcpu->stat.host_state_reload;
1485 }
1486
1487 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1488 {
1489         struct vcpu_svm *svm = to_svm(vcpu);
1490         unsigned long rflags = svm->vmcb->save.rflags;
1491
1492         if (svm->nmi_singlestep) {
1493                 /* Hide our flags if they were not set by the guest */
1494                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1495                         rflags &= ~X86_EFLAGS_TF;
1496                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1497                         rflags &= ~X86_EFLAGS_RF;
1498         }
1499         return rflags;
1500 }
1501
1502 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1503 {
1504         if (to_svm(vcpu)->nmi_singlestep)
1505                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1506
1507        /*
1508         * Any change of EFLAGS.VM is accompanied by a reload of SS
1509         * (caused by either a task switch or an inter-privilege IRET),
1510         * so we do not need to update the CPL here.
1511         */
1512         to_svm(vcpu)->vmcb->save.rflags = rflags;
1513 }
1514
1515 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1516 {
1517         switch (reg) {
1518         case VCPU_EXREG_PDPTR:
1519                 BUG_ON(!npt_enabled);
1520                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1521                 break;
1522         default:
1523                 WARN_ON_ONCE(1);
1524         }
1525 }
1526
1527 static void svm_set_vintr(struct vcpu_svm *svm)
1528 {
1529         struct vmcb_control_area *control;
1530
1531         /* The following fields are ignored when AVIC is enabled */
1532         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1533         svm_set_intercept(svm, INTERCEPT_VINTR);
1534
1535         /*
1536          * This is just a dummy VINTR to actually cause a vmexit to happen.
1537          * Actual injection of virtual interrupts happens through EVENTINJ.
1538          */
1539         control = &svm->vmcb->control;
1540         control->int_vector = 0x0;
1541         control->int_ctl &= ~V_INTR_PRIO_MASK;
1542         control->int_ctl |= V_IRQ_MASK |
1543                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1544         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1545 }
1546
1547 static void svm_clear_vintr(struct vcpu_svm *svm)
1548 {
1549         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1550         svm_clr_intercept(svm, INTERCEPT_VINTR);
1551
1552         /* Drop int_ctl fields related to VINTR injection.  */
1553         svm->vmcb->control.int_ctl &= mask;
1554         if (is_guest_mode(&svm->vcpu)) {
1555                 svm->vmcb01.ptr->control.int_ctl &= mask;
1556
1557                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1558                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1559                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1560         }
1561
1562         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1563 }
1564
1565 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1566 {
1567         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1568         struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save;
1569
1570         switch (seg) {
1571         case VCPU_SREG_CS: return &save->cs;
1572         case VCPU_SREG_DS: return &save->ds;
1573         case VCPU_SREG_ES: return &save->es;
1574         case VCPU_SREG_FS: return &save01->fs;
1575         case VCPU_SREG_GS: return &save01->gs;
1576         case VCPU_SREG_SS: return &save->ss;
1577         case VCPU_SREG_TR: return &save01->tr;
1578         case VCPU_SREG_LDTR: return &save01->ldtr;
1579         }
1580         BUG();
1581         return NULL;
1582 }
1583
1584 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1585 {
1586         struct vmcb_seg *s = svm_seg(vcpu, seg);
1587
1588         return s->base;
1589 }
1590
1591 static void svm_get_segment(struct kvm_vcpu *vcpu,
1592                             struct kvm_segment *var, int seg)
1593 {
1594         struct vmcb_seg *s = svm_seg(vcpu, seg);
1595
1596         var->base = s->base;
1597         var->limit = s->limit;
1598         var->selector = s->selector;
1599         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1600         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1601         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1602         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1603         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1604         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1605         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1606
1607         /*
1608          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1609          * However, the SVM spec states that the G bit is not observed by the
1610          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1611          * So let's synthesize a legal G bit for all segments, this helps
1612          * running KVM nested. It also helps cross-vendor migration, because
1613          * Intel's vmentry has a check on the 'G' bit.
1614          */
1615         var->g = s->limit > 0xfffff;
1616
1617         /*
1618          * AMD's VMCB does not have an explicit unusable field, so emulate it
1619          * for cross vendor migration purposes by "not present"
1620          */
1621         var->unusable = !var->present;
1622
1623         switch (seg) {
1624         case VCPU_SREG_TR:
1625                 /*
1626                  * Work around a bug where the busy flag in the tr selector
1627                  * isn't exposed
1628                  */
1629                 var->type |= 0x2;
1630                 break;
1631         case VCPU_SREG_DS:
1632         case VCPU_SREG_ES:
1633         case VCPU_SREG_FS:
1634         case VCPU_SREG_GS:
1635                 /*
1636                  * The accessed bit must always be set in the segment
1637                  * descriptor cache, although it can be cleared in the
1638                  * descriptor, the cached bit always remains at 1. Since
1639                  * Intel has a check on this, set it here to support
1640                  * cross-vendor migration.
1641                  */
1642                 if (!var->unusable)
1643                         var->type |= 0x1;
1644                 break;
1645         case VCPU_SREG_SS:
1646                 /*
1647                  * On AMD CPUs sometimes the DB bit in the segment
1648                  * descriptor is left as 1, although the whole segment has
1649                  * been made unusable. Clear it here to pass an Intel VMX
1650                  * entry check when cross vendor migrating.
1651                  */
1652                 if (var->unusable)
1653                         var->db = 0;
1654                 /* This is symmetric with svm_set_segment() */
1655                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1656                 break;
1657         }
1658 }
1659
1660 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1661 {
1662         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1663
1664         return save->cpl;
1665 }
1666
1667 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1668 {
1669         struct vcpu_svm *svm = to_svm(vcpu);
1670
1671         dt->size = svm->vmcb->save.idtr.limit;
1672         dt->address = svm->vmcb->save.idtr.base;
1673 }
1674
1675 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1676 {
1677         struct vcpu_svm *svm = to_svm(vcpu);
1678
1679         svm->vmcb->save.idtr.limit = dt->size;
1680         svm->vmcb->save.idtr.base = dt->address ;
1681         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1682 }
1683
1684 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1685 {
1686         struct vcpu_svm *svm = to_svm(vcpu);
1687
1688         dt->size = svm->vmcb->save.gdtr.limit;
1689         dt->address = svm->vmcb->save.gdtr.base;
1690 }
1691
1692 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1693 {
1694         struct vcpu_svm *svm = to_svm(vcpu);
1695
1696         svm->vmcb->save.gdtr.limit = dt->size;
1697         svm->vmcb->save.gdtr.base = dt->address ;
1698         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1699 }
1700
1701 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1702 {
1703         struct vcpu_svm *svm = to_svm(vcpu);
1704         u64 hcr0 = cr0;
1705
1706 #ifdef CONFIG_X86_64
1707         if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1708                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1709                         vcpu->arch.efer |= EFER_LMA;
1710                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1711                 }
1712
1713                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1714                         vcpu->arch.efer &= ~EFER_LMA;
1715                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1716                 }
1717         }
1718 #endif
1719         vcpu->arch.cr0 = cr0;
1720
1721         if (!npt_enabled)
1722                 hcr0 |= X86_CR0_PG | X86_CR0_WP;
1723
1724         /*
1725          * re-enable caching here because the QEMU bios
1726          * does not do it - this results in some delay at
1727          * reboot
1728          */
1729         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1730                 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1731
1732         svm->vmcb->save.cr0 = hcr0;
1733         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1734
1735         /*
1736          * SEV-ES guests must always keep the CR intercepts cleared. CR
1737          * tracking is done using the CR write traps.
1738          */
1739         if (sev_es_guest(vcpu->kvm))
1740                 return;
1741
1742         if (hcr0 == cr0) {
1743                 /* Selective CR0 write remains on.  */
1744                 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1745                 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1746         } else {
1747                 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1748                 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1749         }
1750 }
1751
1752 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1753 {
1754         return true;
1755 }
1756
1757 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1758 {
1759         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1760         unsigned long old_cr4 = vcpu->arch.cr4;
1761
1762         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1763                 svm_flush_tlb(vcpu);
1764
1765         vcpu->arch.cr4 = cr4;
1766         if (!npt_enabled)
1767                 cr4 |= X86_CR4_PAE;
1768         cr4 |= host_cr4_mce;
1769         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1770         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1771
1772         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1773                 kvm_update_cpuid_runtime(vcpu);
1774 }
1775
1776 static void svm_set_segment(struct kvm_vcpu *vcpu,
1777                             struct kvm_segment *var, int seg)
1778 {
1779         struct vcpu_svm *svm = to_svm(vcpu);
1780         struct vmcb_seg *s = svm_seg(vcpu, seg);
1781
1782         s->base = var->base;
1783         s->limit = var->limit;
1784         s->selector = var->selector;
1785         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1786         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1787         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1788         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1789         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1790         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1791         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1792         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1793
1794         /*
1795          * This is always accurate, except if SYSRET returned to a segment
1796          * with SS.DPL != 3.  Intel does not have this quirk, and always
1797          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1798          * would entail passing the CPL to userspace and back.
1799          */
1800         if (seg == VCPU_SREG_SS)
1801                 /* This is symmetric with svm_get_segment() */
1802                 svm->vmcb->save.cpl = (var->dpl & 3);
1803
1804         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1805 }
1806
1807 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1808 {
1809         struct vcpu_svm *svm = to_svm(vcpu);
1810
1811         clr_exception_intercept(svm, BP_VECTOR);
1812
1813         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1814                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1815                         set_exception_intercept(svm, BP_VECTOR);
1816         }
1817 }
1818
1819 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1820 {
1821         if (sd->next_asid > sd->max_asid) {
1822                 ++sd->asid_generation;
1823                 sd->next_asid = sd->min_asid;
1824                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1825                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1826         }
1827
1828         svm->current_vmcb->asid_generation = sd->asid_generation;
1829         svm->asid = sd->next_asid++;
1830 }
1831
1832 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1833 {
1834         struct vmcb *vmcb = svm->vmcb;
1835
1836         if (svm->vcpu.arch.guest_state_protected)
1837                 return;
1838
1839         if (unlikely(value != vmcb->save.dr6)) {
1840                 vmcb->save.dr6 = value;
1841                 vmcb_mark_dirty(vmcb, VMCB_DR);
1842         }
1843 }
1844
1845 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1846 {
1847         struct vcpu_svm *svm = to_svm(vcpu);
1848
1849         if (vcpu->arch.guest_state_protected)
1850                 return;
1851
1852         get_debugreg(vcpu->arch.db[0], 0);
1853         get_debugreg(vcpu->arch.db[1], 1);
1854         get_debugreg(vcpu->arch.db[2], 2);
1855         get_debugreg(vcpu->arch.db[3], 3);
1856         /*
1857          * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1858          * because db_interception might need it.  We can do it before vmentry.
1859          */
1860         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1861         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1862         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1863         set_dr_intercepts(svm);
1864 }
1865
1866 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1867 {
1868         struct vcpu_svm *svm = to_svm(vcpu);
1869
1870         if (vcpu->arch.guest_state_protected)
1871                 return;
1872
1873         svm->vmcb->save.dr7 = value;
1874         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1875 }
1876
1877 static int pf_interception(struct kvm_vcpu *vcpu)
1878 {
1879         struct vcpu_svm *svm = to_svm(vcpu);
1880
1881         u64 fault_address = svm->vmcb->control.exit_info_2;
1882         u64 error_code = svm->vmcb->control.exit_info_1;
1883
1884         return kvm_handle_page_fault(vcpu, error_code, fault_address,
1885                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1886                         svm->vmcb->control.insn_bytes : NULL,
1887                         svm->vmcb->control.insn_len);
1888 }
1889
1890 static int npf_interception(struct kvm_vcpu *vcpu)
1891 {
1892         struct vcpu_svm *svm = to_svm(vcpu);
1893
1894         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1895         u64 error_code = svm->vmcb->control.exit_info_1;
1896
1897         trace_kvm_page_fault(fault_address, error_code);
1898         return kvm_mmu_page_fault(vcpu, fault_address, error_code,
1899                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1900                         svm->vmcb->control.insn_bytes : NULL,
1901                         svm->vmcb->control.insn_len);
1902 }
1903
1904 static int db_interception(struct kvm_vcpu *vcpu)
1905 {
1906         struct kvm_run *kvm_run = vcpu->run;
1907         struct vcpu_svm *svm = to_svm(vcpu);
1908
1909         if (!(vcpu->guest_debug &
1910               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1911                 !svm->nmi_singlestep) {
1912                 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
1913                 kvm_queue_exception_p(vcpu, DB_VECTOR, payload);
1914                 return 1;
1915         }
1916
1917         if (svm->nmi_singlestep) {
1918                 disable_nmi_singlestep(svm);
1919                 /* Make sure we check for pending NMIs upon entry */
1920                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1921         }
1922
1923         if (vcpu->guest_debug &
1924             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1925                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1926                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1927                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1928                 kvm_run->debug.arch.pc =
1929                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1930                 kvm_run->debug.arch.exception = DB_VECTOR;
1931                 return 0;
1932         }
1933
1934         return 1;
1935 }
1936
1937 static int bp_interception(struct kvm_vcpu *vcpu)
1938 {
1939         struct vcpu_svm *svm = to_svm(vcpu);
1940         struct kvm_run *kvm_run = vcpu->run;
1941
1942         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1943         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1944         kvm_run->debug.arch.exception = BP_VECTOR;
1945         return 0;
1946 }
1947
1948 static int ud_interception(struct kvm_vcpu *vcpu)
1949 {
1950         return handle_ud(vcpu);
1951 }
1952
1953 static int ac_interception(struct kvm_vcpu *vcpu)
1954 {
1955         kvm_queue_exception_e(vcpu, AC_VECTOR, 0);
1956         return 1;
1957 }
1958
1959 static bool is_erratum_383(void)
1960 {
1961         int err, i;
1962         u64 value;
1963
1964         if (!erratum_383_found)
1965                 return false;
1966
1967         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1968         if (err)
1969                 return false;
1970
1971         /* Bit 62 may or may not be set for this mce */
1972         value &= ~(1ULL << 62);
1973
1974         if (value != 0xb600000000010015ULL)
1975                 return false;
1976
1977         /* Clear MCi_STATUS registers */
1978         for (i = 0; i < 6; ++i)
1979                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1980
1981         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1982         if (!err) {
1983                 u32 low, high;
1984
1985                 value &= ~(1ULL << 2);
1986                 low    = lower_32_bits(value);
1987                 high   = upper_32_bits(value);
1988
1989                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1990         }
1991
1992         /* Flush tlb to evict multi-match entries */
1993         __flush_tlb_all();
1994
1995         return true;
1996 }
1997
1998 static void svm_handle_mce(struct kvm_vcpu *vcpu)
1999 {
2000         if (is_erratum_383()) {
2001                 /*
2002                  * Erratum 383 triggered. Guest state is corrupt so kill the
2003                  * guest.
2004                  */
2005                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2006
2007                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2008
2009                 return;
2010         }
2011
2012         /*
2013          * On an #MC intercept the MCE handler is not called automatically in
2014          * the host. So do it by hand here.
2015          */
2016         kvm_machine_check();
2017 }
2018
2019 static int mc_interception(struct kvm_vcpu *vcpu)
2020 {
2021         return 1;
2022 }
2023
2024 static int shutdown_interception(struct kvm_vcpu *vcpu)
2025 {
2026         struct kvm_run *kvm_run = vcpu->run;
2027         struct vcpu_svm *svm = to_svm(vcpu);
2028
2029         /*
2030          * The VM save area has already been encrypted so it
2031          * cannot be reinitialized - just terminate.
2032          */
2033         if (sev_es_guest(vcpu->kvm))
2034                 return -EINVAL;
2035
2036         /*
2037          * VMCB is undefined after a SHUTDOWN intercept
2038          * so reinitialize it.
2039          */
2040         clear_page(svm->vmcb);
2041         init_vmcb(vcpu);
2042
2043         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2044         return 0;
2045 }
2046
2047 static int io_interception(struct kvm_vcpu *vcpu)
2048 {
2049         struct vcpu_svm *svm = to_svm(vcpu);
2050         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2051         int size, in, string;
2052         unsigned port;
2053
2054         ++vcpu->stat.io_exits;
2055         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2056         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2057         port = io_info >> 16;
2058         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2059
2060         if (string) {
2061                 if (sev_es_guest(vcpu->kvm))
2062                         return sev_es_string_io(svm, size, port, in);
2063                 else
2064                         return kvm_emulate_instruction(vcpu, 0);
2065         }
2066
2067         svm->next_rip = svm->vmcb->control.exit_info_2;
2068
2069         return kvm_fast_pio(vcpu, size, port, in);
2070 }
2071
2072 static int nmi_interception(struct kvm_vcpu *vcpu)
2073 {
2074         return 1;
2075 }
2076
2077 static int intr_interception(struct kvm_vcpu *vcpu)
2078 {
2079         ++vcpu->stat.irq_exits;
2080         return 1;
2081 }
2082
2083 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload)
2084 {
2085         struct vcpu_svm *svm = to_svm(vcpu);
2086         struct vmcb *vmcb12;
2087         struct kvm_host_map map;
2088         int ret;
2089
2090         if (nested_svm_check_permissions(vcpu))
2091                 return 1;
2092
2093         ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2094         if (ret) {
2095                 if (ret == -EINVAL)
2096                         kvm_inject_gp(vcpu, 0);
2097                 return 1;
2098         }
2099
2100         vmcb12 = map.hva;
2101
2102         ret = kvm_skip_emulated_instruction(vcpu);
2103
2104         if (vmload) {
2105                 nested_svm_vmloadsave(vmcb12, svm->vmcb);
2106                 svm->sysenter_eip_hi = 0;
2107                 svm->sysenter_esp_hi = 0;
2108         } else
2109                 nested_svm_vmloadsave(svm->vmcb, vmcb12);
2110
2111         kvm_vcpu_unmap(vcpu, &map, true);
2112
2113         return ret;
2114 }
2115
2116 static int vmload_interception(struct kvm_vcpu *vcpu)
2117 {
2118         return vmload_vmsave_interception(vcpu, true);
2119 }
2120
2121 static int vmsave_interception(struct kvm_vcpu *vcpu)
2122 {
2123         return vmload_vmsave_interception(vcpu, false);
2124 }
2125
2126 static int vmrun_interception(struct kvm_vcpu *vcpu)
2127 {
2128         if (nested_svm_check_permissions(vcpu))
2129                 return 1;
2130
2131         return nested_svm_vmrun(vcpu);
2132 }
2133
2134 enum {
2135         NONE_SVM_INSTR,
2136         SVM_INSTR_VMRUN,
2137         SVM_INSTR_VMLOAD,
2138         SVM_INSTR_VMSAVE,
2139 };
2140
2141 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2142 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2143 {
2144         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2145
2146         if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2147                 return NONE_SVM_INSTR;
2148
2149         switch (ctxt->modrm) {
2150         case 0xd8: /* VMRUN */
2151                 return SVM_INSTR_VMRUN;
2152         case 0xda: /* VMLOAD */
2153                 return SVM_INSTR_VMLOAD;
2154         case 0xdb: /* VMSAVE */
2155                 return SVM_INSTR_VMSAVE;
2156         default:
2157                 break;
2158         }
2159
2160         return NONE_SVM_INSTR;
2161 }
2162
2163 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2164 {
2165         const int guest_mode_exit_codes[] = {
2166                 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2167                 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2168                 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2169         };
2170         int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = {
2171                 [SVM_INSTR_VMRUN] = vmrun_interception,
2172                 [SVM_INSTR_VMLOAD] = vmload_interception,
2173                 [SVM_INSTR_VMSAVE] = vmsave_interception,
2174         };
2175         struct vcpu_svm *svm = to_svm(vcpu);
2176         int ret;
2177
2178         if (is_guest_mode(vcpu)) {
2179                 /* Returns '1' or -errno on failure, '0' on success. */
2180                 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]);
2181                 if (ret)
2182                         return ret;
2183                 return 1;
2184         }
2185         return svm_instr_handlers[opcode](vcpu);
2186 }
2187
2188 /*
2189  * #GP handling code. Note that #GP can be triggered under the following two
2190  * cases:
2191  *   1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2192  *      some AMD CPUs when EAX of these instructions are in the reserved memory
2193  *      regions (e.g. SMM memory on host).
2194  *   2) VMware backdoor
2195  */
2196 static int gp_interception(struct kvm_vcpu *vcpu)
2197 {
2198         struct vcpu_svm *svm = to_svm(vcpu);
2199         u32 error_code = svm->vmcb->control.exit_info_1;
2200         int opcode;
2201
2202         /* Both #GP cases have zero error_code */
2203         if (error_code)
2204                 goto reinject;
2205
2206         /* Decode the instruction for usage later */
2207         if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2208                 goto reinject;
2209
2210         opcode = svm_instr_opcode(vcpu);
2211
2212         if (opcode == NONE_SVM_INSTR) {
2213                 if (!enable_vmware_backdoor)
2214                         goto reinject;
2215
2216                 /*
2217                  * VMware backdoor emulation on #GP interception only handles
2218                  * IN{S}, OUT{S}, and RDPMC.
2219                  */
2220                 if (!is_guest_mode(vcpu))
2221                         return kvm_emulate_instruction(vcpu,
2222                                 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2223         } else
2224                 return emulate_svm_instr(vcpu, opcode);
2225
2226 reinject:
2227         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2228         return 1;
2229 }
2230
2231 void svm_set_gif(struct vcpu_svm *svm, bool value)
2232 {
2233         if (value) {
2234                 /*
2235                  * If VGIF is enabled, the STGI intercept is only added to
2236                  * detect the opening of the SMI/NMI window; remove it now.
2237                  * Likewise, clear the VINTR intercept, we will set it
2238                  * again while processing KVM_REQ_EVENT if needed.
2239                  */
2240                 if (vgif_enabled(svm))
2241                         svm_clr_intercept(svm, INTERCEPT_STGI);
2242                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2243                         svm_clear_vintr(svm);
2244
2245                 enable_gif(svm);
2246                 if (svm->vcpu.arch.smi_pending ||
2247                     svm->vcpu.arch.nmi_pending ||
2248                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2249                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2250         } else {
2251                 disable_gif(svm);
2252
2253                 /*
2254                  * After a CLGI no interrupts should come.  But if vGIF is
2255                  * in use, we still rely on the VINTR intercept (rather than
2256                  * STGI) to detect an open interrupt window.
2257                 */
2258                 if (!vgif_enabled(svm))
2259                         svm_clear_vintr(svm);
2260         }
2261 }
2262
2263 static int stgi_interception(struct kvm_vcpu *vcpu)
2264 {
2265         int ret;
2266
2267         if (nested_svm_check_permissions(vcpu))
2268                 return 1;
2269
2270         ret = kvm_skip_emulated_instruction(vcpu);
2271         svm_set_gif(to_svm(vcpu), true);
2272         return ret;
2273 }
2274
2275 static int clgi_interception(struct kvm_vcpu *vcpu)
2276 {
2277         int ret;
2278
2279         if (nested_svm_check_permissions(vcpu))
2280                 return 1;
2281
2282         ret = kvm_skip_emulated_instruction(vcpu);
2283         svm_set_gif(to_svm(vcpu), false);
2284         return ret;
2285 }
2286
2287 static int invlpga_interception(struct kvm_vcpu *vcpu)
2288 {
2289         gva_t gva = kvm_rax_read(vcpu);
2290         u32 asid = kvm_rcx_read(vcpu);
2291
2292         /* FIXME: Handle an address size prefix. */
2293         if (!is_long_mode(vcpu))
2294                 gva = (u32)gva;
2295
2296         trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva);
2297
2298         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2299         kvm_mmu_invlpg(vcpu, gva);
2300
2301         return kvm_skip_emulated_instruction(vcpu);
2302 }
2303
2304 static int skinit_interception(struct kvm_vcpu *vcpu)
2305 {
2306         trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu));
2307
2308         kvm_queue_exception(vcpu, UD_VECTOR);
2309         return 1;
2310 }
2311
2312 static int task_switch_interception(struct kvm_vcpu *vcpu)
2313 {
2314         struct vcpu_svm *svm = to_svm(vcpu);
2315         u16 tss_selector;
2316         int reason;
2317         int int_type = svm->vmcb->control.exit_int_info &
2318                 SVM_EXITINTINFO_TYPE_MASK;
2319         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2320         uint32_t type =
2321                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2322         uint32_t idt_v =
2323                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2324         bool has_error_code = false;
2325         u32 error_code = 0;
2326
2327         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2328
2329         if (svm->vmcb->control.exit_info_2 &
2330             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2331                 reason = TASK_SWITCH_IRET;
2332         else if (svm->vmcb->control.exit_info_2 &
2333                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2334                 reason = TASK_SWITCH_JMP;
2335         else if (idt_v)
2336                 reason = TASK_SWITCH_GATE;
2337         else
2338                 reason = TASK_SWITCH_CALL;
2339
2340         if (reason == TASK_SWITCH_GATE) {
2341                 switch (type) {
2342                 case SVM_EXITINTINFO_TYPE_NMI:
2343                         vcpu->arch.nmi_injected = false;
2344                         break;
2345                 case SVM_EXITINTINFO_TYPE_EXEPT:
2346                         if (svm->vmcb->control.exit_info_2 &
2347                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2348                                 has_error_code = true;
2349                                 error_code =
2350                                         (u32)svm->vmcb->control.exit_info_2;
2351                         }
2352                         kvm_clear_exception_queue(vcpu);
2353                         break;
2354                 case SVM_EXITINTINFO_TYPE_INTR:
2355                         kvm_clear_interrupt_queue(vcpu);
2356                         break;
2357                 default:
2358                         break;
2359                 }
2360         }
2361
2362         if (reason != TASK_SWITCH_GATE ||
2363             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2364             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2365              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2366                 if (!skip_emulated_instruction(vcpu))
2367                         return 0;
2368         }
2369
2370         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2371                 int_vec = -1;
2372
2373         return kvm_task_switch(vcpu, tss_selector, int_vec, reason,
2374                                has_error_code, error_code);
2375 }
2376
2377 static int iret_interception(struct kvm_vcpu *vcpu)
2378 {
2379         struct vcpu_svm *svm = to_svm(vcpu);
2380
2381         ++vcpu->stat.nmi_window_exits;
2382         vcpu->arch.hflags |= HF_IRET_MASK;
2383         if (!sev_es_guest(vcpu->kvm)) {
2384                 svm_clr_intercept(svm, INTERCEPT_IRET);
2385                 svm->nmi_iret_rip = kvm_rip_read(vcpu);
2386         }
2387         kvm_make_request(KVM_REQ_EVENT, vcpu);
2388         return 1;
2389 }
2390
2391 static int invlpg_interception(struct kvm_vcpu *vcpu)
2392 {
2393         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2394                 return kvm_emulate_instruction(vcpu, 0);
2395
2396         kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
2397         return kvm_skip_emulated_instruction(vcpu);
2398 }
2399
2400 static int emulate_on_interception(struct kvm_vcpu *vcpu)
2401 {
2402         return kvm_emulate_instruction(vcpu, 0);
2403 }
2404
2405 static int rsm_interception(struct kvm_vcpu *vcpu)
2406 {
2407         return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2);
2408 }
2409
2410 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu,
2411                                             unsigned long val)
2412 {
2413         struct vcpu_svm *svm = to_svm(vcpu);
2414         unsigned long cr0 = vcpu->arch.cr0;
2415         bool ret = false;
2416
2417         if (!is_guest_mode(vcpu) ||
2418             (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2419                 return false;
2420
2421         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2422         val &= ~SVM_CR0_SELECTIVE_MASK;
2423
2424         if (cr0 ^ val) {
2425                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2426                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2427         }
2428
2429         return ret;
2430 }
2431
2432 #define CR_VALID (1ULL << 63)
2433
2434 static int cr_interception(struct kvm_vcpu *vcpu)
2435 {
2436         struct vcpu_svm *svm = to_svm(vcpu);
2437         int reg, cr;
2438         unsigned long val;
2439         int err;
2440
2441         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2442                 return emulate_on_interception(vcpu);
2443
2444         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2445                 return emulate_on_interception(vcpu);
2446
2447         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2448         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2449                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2450         else
2451                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2452
2453         err = 0;
2454         if (cr >= 16) { /* mov to cr */
2455                 cr -= 16;
2456                 val = kvm_register_read(vcpu, reg);
2457                 trace_kvm_cr_write(cr, val);
2458                 switch (cr) {
2459                 case 0:
2460                         if (!check_selective_cr0_intercepted(vcpu, val))
2461                                 err = kvm_set_cr0(vcpu, val);
2462                         else
2463                                 return 1;
2464
2465                         break;
2466                 case 3:
2467                         err = kvm_set_cr3(vcpu, val);
2468                         break;
2469                 case 4:
2470                         err = kvm_set_cr4(vcpu, val);
2471                         break;
2472                 case 8:
2473                         err = kvm_set_cr8(vcpu, val);
2474                         break;
2475                 default:
2476                         WARN(1, "unhandled write to CR%d", cr);
2477                         kvm_queue_exception(vcpu, UD_VECTOR);
2478                         return 1;
2479                 }
2480         } else { /* mov from cr */
2481                 switch (cr) {
2482                 case 0:
2483                         val = kvm_read_cr0(vcpu);
2484                         break;
2485                 case 2:
2486                         val = vcpu->arch.cr2;
2487                         break;
2488                 case 3:
2489                         val = kvm_read_cr3(vcpu);
2490                         break;
2491                 case 4:
2492                         val = kvm_read_cr4(vcpu);
2493                         break;
2494                 case 8:
2495                         val = kvm_get_cr8(vcpu);
2496                         break;
2497                 default:
2498                         WARN(1, "unhandled read from CR%d", cr);
2499                         kvm_queue_exception(vcpu, UD_VECTOR);
2500                         return 1;
2501                 }
2502                 kvm_register_write(vcpu, reg, val);
2503                 trace_kvm_cr_read(cr, val);
2504         }
2505         return kvm_complete_insn_gp(vcpu, err);
2506 }
2507
2508 static int cr_trap(struct kvm_vcpu *vcpu)
2509 {
2510         struct vcpu_svm *svm = to_svm(vcpu);
2511         unsigned long old_value, new_value;
2512         unsigned int cr;
2513         int ret = 0;
2514
2515         new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2516
2517         cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2518         switch (cr) {
2519         case 0:
2520                 old_value = kvm_read_cr0(vcpu);
2521                 svm_set_cr0(vcpu, new_value);
2522
2523                 kvm_post_set_cr0(vcpu, old_value, new_value);
2524                 break;
2525         case 4:
2526                 old_value = kvm_read_cr4(vcpu);
2527                 svm_set_cr4(vcpu, new_value);
2528
2529                 kvm_post_set_cr4(vcpu, old_value, new_value);
2530                 break;
2531         case 8:
2532                 ret = kvm_set_cr8(vcpu, new_value);
2533                 break;
2534         default:
2535                 WARN(1, "unhandled CR%d write trap", cr);
2536                 kvm_queue_exception(vcpu, UD_VECTOR);
2537                 return 1;
2538         }
2539
2540         return kvm_complete_insn_gp(vcpu, ret);
2541 }
2542
2543 static int dr_interception(struct kvm_vcpu *vcpu)
2544 {
2545         struct vcpu_svm *svm = to_svm(vcpu);
2546         int reg, dr;
2547         unsigned long val;
2548         int err = 0;
2549
2550         if (vcpu->guest_debug == 0) {
2551                 /*
2552                  * No more DR vmexits; force a reload of the debug registers
2553                  * and reenter on this instruction.  The next vmexit will
2554                  * retrieve the full state of the debug registers.
2555                  */
2556                 clr_dr_intercepts(svm);
2557                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2558                 return 1;
2559         }
2560
2561         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2562                 return emulate_on_interception(vcpu);
2563
2564         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2565         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2566         if (dr >= 16) { /* mov to DRn  */
2567                 dr -= 16;
2568                 val = kvm_register_read(vcpu, reg);
2569                 err = kvm_set_dr(vcpu, dr, val);
2570         } else {
2571                 kvm_get_dr(vcpu, dr, &val);
2572                 kvm_register_write(vcpu, reg, val);
2573         }
2574
2575         return kvm_complete_insn_gp(vcpu, err);
2576 }
2577
2578 static int cr8_write_interception(struct kvm_vcpu *vcpu)
2579 {
2580         int r;
2581
2582         u8 cr8_prev = kvm_get_cr8(vcpu);
2583         /* instruction emulation calls kvm_set_cr8() */
2584         r = cr_interception(vcpu);
2585         if (lapic_in_kernel(vcpu))
2586                 return r;
2587         if (cr8_prev <= kvm_get_cr8(vcpu))
2588                 return r;
2589         vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2590         return 0;
2591 }
2592
2593 static int efer_trap(struct kvm_vcpu *vcpu)
2594 {
2595         struct msr_data msr_info;
2596         int ret;
2597
2598         /*
2599          * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2600          * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2601          * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2602          * the guest doesn't have X86_FEATURE_SVM.
2603          */
2604         msr_info.host_initiated = false;
2605         msr_info.index = MSR_EFER;
2606         msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME;
2607         ret = kvm_set_msr_common(vcpu, &msr_info);
2608
2609         return kvm_complete_insn_gp(vcpu, ret);
2610 }
2611
2612 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2613 {
2614         msr->data = 0;
2615
2616         switch (msr->index) {
2617         case MSR_F10H_DECFG:
2618                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2619                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2620                 break;
2621         case MSR_IA32_PERF_CAPABILITIES:
2622                 return 0;
2623         default:
2624                 return KVM_MSR_RET_INVALID;
2625         }
2626
2627         return 0;
2628 }
2629
2630 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2631 {
2632         struct vcpu_svm *svm = to_svm(vcpu);
2633
2634         switch (msr_info->index) {
2635         case MSR_STAR:
2636                 msr_info->data = svm->vmcb01.ptr->save.star;
2637                 break;
2638 #ifdef CONFIG_X86_64
2639         case MSR_LSTAR:
2640                 msr_info->data = svm->vmcb01.ptr->save.lstar;
2641                 break;
2642         case MSR_CSTAR:
2643                 msr_info->data = svm->vmcb01.ptr->save.cstar;
2644                 break;
2645         case MSR_KERNEL_GS_BASE:
2646                 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2647                 break;
2648         case MSR_SYSCALL_MASK:
2649                 msr_info->data = svm->vmcb01.ptr->save.sfmask;
2650                 break;
2651 #endif
2652         case MSR_IA32_SYSENTER_CS:
2653                 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs;
2654                 break;
2655         case MSR_IA32_SYSENTER_EIP:
2656                 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip;
2657                 if (guest_cpuid_is_intel(vcpu))
2658                         msr_info->data |= (u64)svm->sysenter_eip_hi << 32;
2659                 break;
2660         case MSR_IA32_SYSENTER_ESP:
2661                 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp;
2662                 if (guest_cpuid_is_intel(vcpu))
2663                         msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
2664                 break;
2665         case MSR_TSC_AUX:
2666                 if (tsc_aux_uret_slot < 0)
2667                         return 1;
2668                 if (!msr_info->host_initiated &&
2669                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
2670                     !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
2671                         return 1;
2672                 msr_info->data = svm->tsc_aux;
2673                 break;
2674         /*
2675          * Nobody will change the following 5 values in the VMCB so we can
2676          * safely return them on rdmsr. They will always be 0 until LBRV is
2677          * implemented.
2678          */
2679         case MSR_IA32_DEBUGCTLMSR:
2680                 msr_info->data = svm->vmcb->save.dbgctl;
2681                 break;
2682         case MSR_IA32_LASTBRANCHFROMIP:
2683                 msr_info->data = svm->vmcb->save.br_from;
2684                 break;
2685         case MSR_IA32_LASTBRANCHTOIP:
2686                 msr_info->data = svm->vmcb->save.br_to;
2687                 break;
2688         case MSR_IA32_LASTINTFROMIP:
2689                 msr_info->data = svm->vmcb->save.last_excp_from;
2690                 break;
2691         case MSR_IA32_LASTINTTOIP:
2692                 msr_info->data = svm->vmcb->save.last_excp_to;
2693                 break;
2694         case MSR_VM_HSAVE_PA:
2695                 msr_info->data = svm->nested.hsave_msr;
2696                 break;
2697         case MSR_VM_CR:
2698                 msr_info->data = svm->nested.vm_cr_msr;
2699                 break;
2700         case MSR_IA32_SPEC_CTRL:
2701                 if (!msr_info->host_initiated &&
2702                     !guest_has_spec_ctrl_msr(vcpu))
2703                         return 1;
2704
2705                 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2706                         msr_info->data = svm->vmcb->save.spec_ctrl;
2707                 else
2708                         msr_info->data = svm->spec_ctrl;
2709                 break;
2710         case MSR_AMD64_VIRT_SPEC_CTRL:
2711                 if (!msr_info->host_initiated &&
2712                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2713                         return 1;
2714
2715                 msr_info->data = svm->virt_spec_ctrl;
2716                 break;
2717         case MSR_F15H_IC_CFG: {
2718
2719                 int family, model;
2720
2721                 family = guest_cpuid_family(vcpu);
2722                 model  = guest_cpuid_model(vcpu);
2723
2724                 if (family < 0 || model < 0)
2725                         return kvm_get_msr_common(vcpu, msr_info);
2726
2727                 msr_info->data = 0;
2728
2729                 if (family == 0x15 &&
2730                     (model >= 0x2 && model < 0x20))
2731                         msr_info->data = 0x1E;
2732                 }
2733                 break;
2734         case MSR_F10H_DECFG:
2735                 msr_info->data = svm->msr_decfg;
2736                 break;
2737         default:
2738                 return kvm_get_msr_common(vcpu, msr_info);
2739         }
2740         return 0;
2741 }
2742
2743 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2744 {
2745         struct vcpu_svm *svm = to_svm(vcpu);
2746         if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->ghcb))
2747                 return kvm_complete_insn_gp(vcpu, err);
2748
2749         ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2750         ghcb_set_sw_exit_info_2(svm->ghcb,
2751                                 X86_TRAP_GP |
2752                                 SVM_EVTINJ_TYPE_EXEPT |
2753                                 SVM_EVTINJ_VALID);
2754         return 1;
2755 }
2756
2757 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2758 {
2759         struct vcpu_svm *svm = to_svm(vcpu);
2760         int svm_dis, chg_mask;
2761
2762         if (data & ~SVM_VM_CR_VALID_MASK)
2763                 return 1;
2764
2765         chg_mask = SVM_VM_CR_VALID_MASK;
2766
2767         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2768                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2769
2770         svm->nested.vm_cr_msr &= ~chg_mask;
2771         svm->nested.vm_cr_msr |= (data & chg_mask);
2772
2773         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2774
2775         /* check for svm_disable while efer.svme is set */
2776         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2777                 return 1;
2778
2779         return 0;
2780 }
2781
2782 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2783 {
2784         struct vcpu_svm *svm = to_svm(vcpu);
2785         int r;
2786
2787         u32 ecx = msr->index;
2788         u64 data = msr->data;
2789         switch (ecx) {
2790         case MSR_IA32_CR_PAT:
2791                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2792                         return 1;
2793                 vcpu->arch.pat = data;
2794                 svm->vmcb01.ptr->save.g_pat = data;
2795                 if (is_guest_mode(vcpu))
2796                         nested_vmcb02_compute_g_pat(svm);
2797                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2798                 break;
2799         case MSR_IA32_SPEC_CTRL:
2800                 if (!msr->host_initiated &&
2801                     !guest_has_spec_ctrl_msr(vcpu))
2802                         return 1;
2803
2804                 if (kvm_spec_ctrl_test_value(data))
2805                         return 1;
2806
2807                 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2808                         svm->vmcb->save.spec_ctrl = data;
2809                 else
2810                         svm->spec_ctrl = data;
2811                 if (!data)
2812                         break;
2813
2814                 /*
2815                  * For non-nested:
2816                  * When it's written (to non-zero) for the first time, pass
2817                  * it through.
2818                  *
2819                  * For nested:
2820                  * The handling of the MSR bitmap for L2 guests is done in
2821                  * nested_svm_vmrun_msrpm.
2822                  * We update the L1 MSR bit as well since it will end up
2823                  * touching the MSR anyway now.
2824                  */
2825                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2826                 break;
2827         case MSR_IA32_PRED_CMD:
2828                 if (!msr->host_initiated &&
2829                     !guest_has_pred_cmd_msr(vcpu))
2830                         return 1;
2831
2832                 if (data & ~PRED_CMD_IBPB)
2833                         return 1;
2834                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2835                         return 1;
2836                 if (!data)
2837                         break;
2838
2839                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2840                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2841                 break;
2842         case MSR_AMD64_VIRT_SPEC_CTRL:
2843                 if (!msr->host_initiated &&
2844                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2845                         return 1;
2846
2847                 if (data & ~SPEC_CTRL_SSBD)
2848                         return 1;
2849
2850                 svm->virt_spec_ctrl = data;
2851                 break;
2852         case MSR_STAR:
2853                 svm->vmcb01.ptr->save.star = data;
2854                 break;
2855 #ifdef CONFIG_X86_64
2856         case MSR_LSTAR:
2857                 svm->vmcb01.ptr->save.lstar = data;
2858                 break;
2859         case MSR_CSTAR:
2860                 svm->vmcb01.ptr->save.cstar = data;
2861                 break;
2862         case MSR_KERNEL_GS_BASE:
2863                 svm->vmcb01.ptr->save.kernel_gs_base = data;
2864                 break;
2865         case MSR_SYSCALL_MASK:
2866                 svm->vmcb01.ptr->save.sfmask = data;
2867                 break;
2868 #endif
2869         case MSR_IA32_SYSENTER_CS:
2870                 svm->vmcb01.ptr->save.sysenter_cs = data;
2871                 break;
2872         case MSR_IA32_SYSENTER_EIP:
2873                 svm->vmcb01.ptr->save.sysenter_eip = (u32)data;
2874                 /*
2875                  * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
2876                  * when we spoof an Intel vendor ID (for cross vendor migration).
2877                  * In this case we use this intercept to track the high
2878                  * 32 bit part of these msrs to support Intel's
2879                  * implementation of SYSENTER/SYSEXIT.
2880                  */
2881                 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2882                 break;
2883         case MSR_IA32_SYSENTER_ESP:
2884                 svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
2885                 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2886                 break;
2887         case MSR_TSC_AUX:
2888                 if (tsc_aux_uret_slot < 0)
2889                         return 1;
2890
2891                 if (!msr->host_initiated &&
2892                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
2893                     !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
2894                         return 1;
2895
2896                 /*
2897                  * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
2898                  * incomplete and conflicting architectural behavior.  Current
2899                  * AMD CPUs completely ignore bits 63:32, i.e. they aren't
2900                  * reserved and always read as zeros.  Emulate AMD CPU behavior
2901                  * to avoid explosions if the vCPU is migrated from an AMD host
2902                  * to an Intel host.
2903                  */
2904                 data = (u32)data;
2905
2906                 /*
2907                  * TSC_AUX is usually changed only during boot and never read
2908                  * directly.  Intercept TSC_AUX instead of exposing it to the
2909                  * guest via direct_access_msrs, and switch it via user return.
2910                  */
2911                 preempt_disable();
2912                 r = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull);
2913                 preempt_enable();
2914                 if (r)
2915                         return 1;
2916
2917                 svm->tsc_aux = data;
2918                 break;
2919         case MSR_IA32_DEBUGCTLMSR:
2920                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2921                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2922                                     __func__, data);
2923                         break;
2924                 }
2925                 if (data & DEBUGCTL_RESERVED_BITS)
2926                         return 1;
2927
2928                 svm->vmcb->save.dbgctl = data;
2929                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2930                 if (data & (1ULL<<0))
2931                         svm_enable_lbrv(vcpu);
2932                 else
2933                         svm_disable_lbrv(vcpu);
2934                 break;
2935         case MSR_VM_HSAVE_PA:
2936                 svm->nested.hsave_msr = data;
2937                 break;
2938         case MSR_VM_CR:
2939                 return svm_set_vm_cr(vcpu, data);
2940         case MSR_VM_IGNNE:
2941                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2942                 break;
2943         case MSR_F10H_DECFG: {
2944                 struct kvm_msr_entry msr_entry;
2945
2946                 msr_entry.index = msr->index;
2947                 if (svm_get_msr_feature(&msr_entry))
2948                         return 1;
2949
2950                 /* Check the supported bits */
2951                 if (data & ~msr_entry.data)
2952                         return 1;
2953
2954                 /* Don't allow the guest to change a bit, #GP */
2955                 if (!msr->host_initiated && (data ^ msr_entry.data))
2956                         return 1;
2957
2958                 svm->msr_decfg = data;
2959                 break;
2960         }
2961         case MSR_IA32_APICBASE:
2962                 if (kvm_vcpu_apicv_active(vcpu))
2963                         avic_update_vapic_bar(to_svm(vcpu), data);
2964                 fallthrough;
2965         default:
2966                 return kvm_set_msr_common(vcpu, msr);
2967         }
2968         return 0;
2969 }
2970
2971 static int msr_interception(struct kvm_vcpu *vcpu)
2972 {
2973         if (to_svm(vcpu)->vmcb->control.exit_info_1)
2974                 return kvm_emulate_wrmsr(vcpu);
2975         else
2976                 return kvm_emulate_rdmsr(vcpu);
2977 }
2978
2979 static int interrupt_window_interception(struct kvm_vcpu *vcpu)
2980 {
2981         kvm_make_request(KVM_REQ_EVENT, vcpu);
2982         svm_clear_vintr(to_svm(vcpu));
2983
2984         /*
2985          * For AVIC, the only reason to end up here is ExtINTs.
2986          * In this case AVIC was temporarily disabled for
2987          * requesting the IRQ window and we have to re-enable it.
2988          */
2989         svm_toggle_avic_for_irq_window(vcpu, true);
2990
2991         ++vcpu->stat.irq_window_exits;
2992         return 1;
2993 }
2994
2995 static int pause_interception(struct kvm_vcpu *vcpu)
2996 {
2997         bool in_kernel;
2998
2999         /*
3000          * CPL is not made available for an SEV-ES guest, therefore
3001          * vcpu->arch.preempted_in_kernel can never be true.  Just
3002          * set in_kernel to false as well.
3003          */
3004         in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0;
3005
3006         if (!kvm_pause_in_guest(vcpu->kvm))
3007                 grow_ple_window(vcpu);
3008
3009         kvm_vcpu_on_spin(vcpu, in_kernel);
3010         return kvm_skip_emulated_instruction(vcpu);
3011 }
3012
3013 static int invpcid_interception(struct kvm_vcpu *vcpu)
3014 {
3015         struct vcpu_svm *svm = to_svm(vcpu);
3016         unsigned long type;
3017         gva_t gva;
3018
3019         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3020                 kvm_queue_exception(vcpu, UD_VECTOR);
3021                 return 1;
3022         }
3023
3024         /*
3025          * For an INVPCID intercept:
3026          * EXITINFO1 provides the linear address of the memory operand.
3027          * EXITINFO2 provides the contents of the register operand.
3028          */
3029         type = svm->vmcb->control.exit_info_2;
3030         gva = svm->vmcb->control.exit_info_1;
3031
3032         if (type > 3) {
3033                 kvm_inject_gp(vcpu, 0);
3034                 return 1;
3035         }
3036
3037         return kvm_handle_invpcid(vcpu, type, gva);
3038 }
3039
3040 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3041         [SVM_EXIT_READ_CR0]                     = cr_interception,
3042         [SVM_EXIT_READ_CR3]                     = cr_interception,
3043         [SVM_EXIT_READ_CR4]                     = cr_interception,
3044         [SVM_EXIT_READ_CR8]                     = cr_interception,
3045         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3046         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3047         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3048         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3049         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3050         [SVM_EXIT_READ_DR0]                     = dr_interception,
3051         [SVM_EXIT_READ_DR1]                     = dr_interception,
3052         [SVM_EXIT_READ_DR2]                     = dr_interception,
3053         [SVM_EXIT_READ_DR3]                     = dr_interception,
3054         [SVM_EXIT_READ_DR4]                     = dr_interception,
3055         [SVM_EXIT_READ_DR5]                     = dr_interception,
3056         [SVM_EXIT_READ_DR6]                     = dr_interception,
3057         [SVM_EXIT_READ_DR7]                     = dr_interception,
3058         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3059         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3060         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3061         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3062         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3063         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3064         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3065         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3066         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3067         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3068         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3069         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3070         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3071         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
3072         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
3073         [SVM_EXIT_INTR]                         = intr_interception,
3074         [SVM_EXIT_NMI]                          = nmi_interception,
3075         [SVM_EXIT_SMI]                          = kvm_emulate_as_nop,
3076         [SVM_EXIT_INIT]                         = kvm_emulate_as_nop,
3077         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3078         [SVM_EXIT_RDPMC]                        = kvm_emulate_rdpmc,
3079         [SVM_EXIT_CPUID]                        = kvm_emulate_cpuid,
3080         [SVM_EXIT_IRET]                         = iret_interception,
3081         [SVM_EXIT_INVD]                         = kvm_emulate_invd,
3082         [SVM_EXIT_PAUSE]                        = pause_interception,
3083         [SVM_EXIT_HLT]                          = kvm_emulate_halt,
3084         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3085         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3086         [SVM_EXIT_IOIO]                         = io_interception,
3087         [SVM_EXIT_MSR]                          = msr_interception,
3088         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3089         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3090         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3091         [SVM_EXIT_VMMCALL]                      = kvm_emulate_hypercall,
3092         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3093         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3094         [SVM_EXIT_STGI]                         = stgi_interception,
3095         [SVM_EXIT_CLGI]                         = clgi_interception,
3096         [SVM_EXIT_SKINIT]                       = skinit_interception,
3097         [SVM_EXIT_RDTSCP]                       = kvm_handle_invalid_op,
3098         [SVM_EXIT_WBINVD]                       = kvm_emulate_wbinvd,
3099         [SVM_EXIT_MONITOR]                      = kvm_emulate_monitor,
3100         [SVM_EXIT_MWAIT]                        = kvm_emulate_mwait,
3101         [SVM_EXIT_XSETBV]                       = kvm_emulate_xsetbv,
3102         [SVM_EXIT_RDPRU]                        = kvm_handle_invalid_op,
3103         [SVM_EXIT_EFER_WRITE_TRAP]              = efer_trap,
3104         [SVM_EXIT_CR0_WRITE_TRAP]               = cr_trap,
3105         [SVM_EXIT_CR4_WRITE_TRAP]               = cr_trap,
3106         [SVM_EXIT_CR8_WRITE_TRAP]               = cr_trap,
3107         [SVM_EXIT_INVPCID]                      = invpcid_interception,
3108         [SVM_EXIT_NPF]                          = npf_interception,
3109         [SVM_EXIT_RSM]                          = rsm_interception,
3110         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
3111         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
3112         [SVM_EXIT_VMGEXIT]                      = sev_handle_vmgexit,
3113 };
3114
3115 static void dump_vmcb(struct kvm_vcpu *vcpu)
3116 {
3117         struct vcpu_svm *svm = to_svm(vcpu);
3118         struct vmcb_control_area *control = &svm->vmcb->control;
3119         struct vmcb_save_area *save = &svm->vmcb->save;
3120         struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save;
3121
3122         if (!dump_invalid_vmcb) {
3123                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3124                 return;
3125         }
3126
3127         pr_err("VMCB Control Area:\n");
3128         pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3129         pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3130         pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3131         pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3132         pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3133         pr_err("%-20s%08x %08x\n", "intercepts:",
3134               control->intercepts[INTERCEPT_WORD3],
3135                control->intercepts[INTERCEPT_WORD4]);
3136         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3137         pr_err("%-20s%d\n", "pause filter threshold:",
3138                control->pause_filter_thresh);
3139         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3140         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3141         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3142         pr_err("%-20s%d\n", "asid:", control->asid);
3143         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3144         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3145         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3146         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3147         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3148         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3149         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3150         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3151         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3152         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3153         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3154         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3155         pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3156         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3157         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3158         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3159         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3160         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3161         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3162         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3163         pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3164         pr_err("VMCB State Save Area:\n");
3165         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3166                "es:",
3167                save->es.selector, save->es.attrib,
3168                save->es.limit, save->es.base);
3169         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3170                "cs:",
3171                save->cs.selector, save->cs.attrib,
3172                save->cs.limit, save->cs.base);
3173         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3174                "ss:",
3175                save->ss.selector, save->ss.attrib,
3176                save->ss.limit, save->ss.base);
3177         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3178                "ds:",
3179                save->ds.selector, save->ds.attrib,
3180                save->ds.limit, save->ds.base);
3181         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3182                "fs:",
3183                save01->fs.selector, save01->fs.attrib,
3184                save01->fs.limit, save01->fs.base);
3185         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3186                "gs:",
3187                save01->gs.selector, save01->gs.attrib,
3188                save01->gs.limit, save01->gs.base);
3189         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3190                "gdtr:",
3191                save->gdtr.selector, save->gdtr.attrib,
3192                save->gdtr.limit, save->gdtr.base);
3193         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3194                "ldtr:",
3195                save01->ldtr.selector, save01->ldtr.attrib,
3196                save01->ldtr.limit, save01->ldtr.base);
3197         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3198                "idtr:",
3199                save->idtr.selector, save->idtr.attrib,
3200                save->idtr.limit, save->idtr.base);
3201         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3202                "tr:",
3203                save01->tr.selector, save01->tr.attrib,
3204                save01->tr.limit, save01->tr.base);
3205         pr_err("cpl:            %d                efer:         %016llx\n",
3206                 save->cpl, save->efer);
3207         pr_err("%-15s %016llx %-13s %016llx\n",
3208                "cr0:", save->cr0, "cr2:", save->cr2);
3209         pr_err("%-15s %016llx %-13s %016llx\n",
3210                "cr3:", save->cr3, "cr4:", save->cr4);
3211         pr_err("%-15s %016llx %-13s %016llx\n",
3212                "dr6:", save->dr6, "dr7:", save->dr7);
3213         pr_err("%-15s %016llx %-13s %016llx\n",
3214                "rip:", save->rip, "rflags:", save->rflags);
3215         pr_err("%-15s %016llx %-13s %016llx\n",
3216                "rsp:", save->rsp, "rax:", save->rax);
3217         pr_err("%-15s %016llx %-13s %016llx\n",
3218                "star:", save01->star, "lstar:", save01->lstar);
3219         pr_err("%-15s %016llx %-13s %016llx\n",
3220                "cstar:", save01->cstar, "sfmask:", save01->sfmask);
3221         pr_err("%-15s %016llx %-13s %016llx\n",
3222                "kernel_gs_base:", save01->kernel_gs_base,
3223                "sysenter_cs:", save01->sysenter_cs);
3224         pr_err("%-15s %016llx %-13s %016llx\n",
3225                "sysenter_esp:", save01->sysenter_esp,
3226                "sysenter_eip:", save01->sysenter_eip);
3227         pr_err("%-15s %016llx %-13s %016llx\n",
3228                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3229         pr_err("%-15s %016llx %-13s %016llx\n",
3230                "br_from:", save->br_from, "br_to:", save->br_to);
3231         pr_err("%-15s %016llx %-13s %016llx\n",
3232                "excp_from:", save->last_excp_from,
3233                "excp_to:", save->last_excp_to);
3234 }
3235
3236 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3237 {
3238         if (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3239             svm_exit_handlers[exit_code])
3240                 return 0;
3241
3242         vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3243         dump_vmcb(vcpu);
3244         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3245         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3246         vcpu->run->internal.ndata = 2;
3247         vcpu->run->internal.data[0] = exit_code;
3248         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3249
3250         return -EINVAL;
3251 }
3252
3253 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code)
3254 {
3255         if (svm_handle_invalid_exit(vcpu, exit_code))
3256                 return 0;
3257
3258 #ifdef CONFIG_RETPOLINE
3259         if (exit_code == SVM_EXIT_MSR)
3260                 return msr_interception(vcpu);
3261         else if (exit_code == SVM_EXIT_VINTR)
3262                 return interrupt_window_interception(vcpu);
3263         else if (exit_code == SVM_EXIT_INTR)
3264                 return intr_interception(vcpu);
3265         else if (exit_code == SVM_EXIT_HLT)
3266                 return kvm_emulate_halt(vcpu);
3267         else if (exit_code == SVM_EXIT_NPF)
3268                 return npf_interception(vcpu);
3269 #endif
3270         return svm_exit_handlers[exit_code](vcpu);
3271 }
3272
3273 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3274                               u32 *intr_info, u32 *error_code)
3275 {
3276         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3277
3278         *info1 = control->exit_info_1;
3279         *info2 = control->exit_info_2;
3280         *intr_info = control->exit_int_info;
3281         if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3282             (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3283                 *error_code = control->exit_int_info_err;
3284         else
3285                 *error_code = 0;
3286 }
3287
3288 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3289 {
3290         struct vcpu_svm *svm = to_svm(vcpu);
3291         struct kvm_run *kvm_run = vcpu->run;
3292         u32 exit_code = svm->vmcb->control.exit_code;
3293
3294         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3295
3296         /* SEV-ES guests must use the CR write traps to track CR registers. */
3297         if (!sev_es_guest(vcpu->kvm)) {
3298                 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3299                         vcpu->arch.cr0 = svm->vmcb->save.cr0;
3300                 if (npt_enabled)
3301                         vcpu->arch.cr3 = svm->vmcb->save.cr3;
3302         }
3303
3304         if (is_guest_mode(vcpu)) {
3305                 int vmexit;
3306
3307                 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3308
3309                 vmexit = nested_svm_exit_special(svm);
3310
3311                 if (vmexit == NESTED_EXIT_CONTINUE)
3312                         vmexit = nested_svm_exit_handled(svm);
3313
3314                 if (vmexit == NESTED_EXIT_DONE)
3315                         return 1;
3316         }
3317
3318         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3319                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3320                 kvm_run->fail_entry.hardware_entry_failure_reason
3321                         = svm->vmcb->control.exit_code;
3322                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3323                 dump_vmcb(vcpu);
3324                 return 0;
3325         }
3326
3327         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3328             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3329             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3330             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3331                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3332                        "exit_code 0x%x\n",
3333                        __func__, svm->vmcb->control.exit_int_info,
3334                        exit_code);
3335
3336         if (exit_fastpath != EXIT_FASTPATH_NONE)
3337                 return 1;
3338
3339         return svm_invoke_exit_handler(vcpu, exit_code);
3340 }
3341
3342 static void reload_tss(struct kvm_vcpu *vcpu)
3343 {
3344         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3345
3346         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3347         load_TR_desc();
3348 }
3349
3350 static void pre_svm_run(struct kvm_vcpu *vcpu)
3351 {
3352         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3353         struct vcpu_svm *svm = to_svm(vcpu);
3354
3355         /*
3356          * If the previous vmrun of the vmcb occurred on a different physical
3357          * cpu, then mark the vmcb dirty and assign a new asid.  Hardware's
3358          * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3359          */
3360         if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) {
3361                 svm->current_vmcb->asid_generation = 0;
3362                 vmcb_mark_all_dirty(svm->vmcb);
3363                 svm->current_vmcb->cpu = vcpu->cpu;
3364         }
3365
3366         if (sev_guest(vcpu->kvm))
3367                 return pre_sev_run(svm, vcpu->cpu);
3368
3369         /* FIXME: handle wraparound of asid_generation */
3370         if (svm->current_vmcb->asid_generation != sd->asid_generation)
3371                 new_asid(svm, sd);
3372 }
3373
3374 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3375 {
3376         struct vcpu_svm *svm = to_svm(vcpu);
3377
3378         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3379         vcpu->arch.hflags |= HF_NMI_MASK;
3380         if (!sev_es_guest(vcpu->kvm))
3381                 svm_set_intercept(svm, INTERCEPT_IRET);
3382         ++vcpu->stat.nmi_injections;
3383 }
3384
3385 static void svm_set_irq(struct kvm_vcpu *vcpu)
3386 {
3387         struct vcpu_svm *svm = to_svm(vcpu);
3388
3389         BUG_ON(!(gif_set(svm)));
3390
3391         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3392         ++vcpu->stat.irq_injections;
3393
3394         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3395                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3396 }
3397
3398 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3399 {
3400         struct vcpu_svm *svm = to_svm(vcpu);
3401
3402         /*
3403          * SEV-ES guests must always keep the CR intercepts cleared. CR
3404          * tracking is done using the CR write traps.
3405          */
3406         if (sev_es_guest(vcpu->kvm))
3407                 return;
3408
3409         if (nested_svm_virtualize_tpr(vcpu))
3410                 return;
3411
3412         svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3413
3414         if (irr == -1)
3415                 return;
3416
3417         if (tpr >= irr)
3418                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3419 }
3420
3421 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3422 {
3423         struct vcpu_svm *svm = to_svm(vcpu);
3424         struct vmcb *vmcb = svm->vmcb;
3425         bool ret;
3426
3427         if (!gif_set(svm))
3428                 return true;
3429
3430         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3431                 return false;
3432
3433         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3434               (vcpu->arch.hflags & HF_NMI_MASK);
3435
3436         return ret;
3437 }
3438
3439 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3440 {
3441         struct vcpu_svm *svm = to_svm(vcpu);
3442         if (svm->nested.nested_run_pending)
3443                 return -EBUSY;
3444
3445         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3446         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3447                 return -EBUSY;
3448
3449         return !svm_nmi_blocked(vcpu);
3450 }
3451
3452 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3453 {
3454         return !!(vcpu->arch.hflags & HF_NMI_MASK);
3455 }
3456
3457 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3458 {
3459         struct vcpu_svm *svm = to_svm(vcpu);
3460
3461         if (masked) {
3462                 vcpu->arch.hflags |= HF_NMI_MASK;
3463                 if (!sev_es_guest(vcpu->kvm))
3464                         svm_set_intercept(svm, INTERCEPT_IRET);
3465         } else {
3466                 vcpu->arch.hflags &= ~HF_NMI_MASK;
3467                 if (!sev_es_guest(vcpu->kvm))
3468                         svm_clr_intercept(svm, INTERCEPT_IRET);
3469         }
3470 }
3471
3472 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3473 {
3474         struct vcpu_svm *svm = to_svm(vcpu);
3475         struct vmcb *vmcb = svm->vmcb;
3476
3477         if (!gif_set(svm))
3478                 return true;
3479
3480         if (sev_es_guest(vcpu->kvm)) {
3481                 /*
3482                  * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3483                  * bit to determine the state of the IF flag.
3484                  */
3485                 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3486                         return true;
3487         } else if (is_guest_mode(vcpu)) {
3488                 /* As long as interrupts are being delivered...  */
3489                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3490                     ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF)
3491                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3492                         return true;
3493
3494                 /* ... vmexits aren't blocked by the interrupt shadow  */
3495                 if (nested_exit_on_intr(svm))
3496                         return false;
3497         } else {
3498                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3499                         return true;
3500         }
3501
3502         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3503 }
3504
3505 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3506 {
3507         struct vcpu_svm *svm = to_svm(vcpu);
3508         if (svm->nested.nested_run_pending)
3509                 return -EBUSY;
3510
3511         /*
3512          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3513          * e.g. if the IRQ arrived asynchronously after checking nested events.
3514          */
3515         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3516                 return -EBUSY;
3517
3518         return !svm_interrupt_blocked(vcpu);
3519 }
3520
3521 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3522 {
3523         struct vcpu_svm *svm = to_svm(vcpu);
3524
3525         /*
3526          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3527          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3528          * get that intercept, this function will be called again though and
3529          * we'll get the vintr intercept. However, if the vGIF feature is
3530          * enabled, the STGI interception will not occur. Enable the irq
3531          * window under the assumption that the hardware will set the GIF.
3532          */
3533         if (vgif_enabled(svm) || gif_set(svm)) {
3534                 /*
3535                  * IRQ window is not needed when AVIC is enabled,
3536                  * unless we have pending ExtINT since it cannot be injected
3537                  * via AVIC. In such case, we need to temporarily disable AVIC,
3538                  * and fallback to injecting IRQ via V_IRQ.
3539                  */
3540                 svm_toggle_avic_for_irq_window(vcpu, false);
3541                 svm_set_vintr(svm);
3542         }
3543 }
3544
3545 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3546 {
3547         struct vcpu_svm *svm = to_svm(vcpu);
3548
3549         if ((vcpu->arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) == HF_NMI_MASK)
3550                 return; /* IRET will cause a vm exit */
3551
3552         if (!gif_set(svm)) {
3553                 if (vgif_enabled(svm))
3554                         svm_set_intercept(svm, INTERCEPT_STGI);
3555                 return; /* STGI will cause a vm exit */
3556         }
3557
3558         /*
3559          * Something prevents NMI from been injected. Single step over possible
3560          * problem (IRET or exception injection or interrupt shadow)
3561          */
3562         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3563         svm->nmi_singlestep = true;
3564         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3565 }
3566
3567 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3568 {
3569         return 0;
3570 }
3571
3572 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3573 {
3574         return 0;
3575 }
3576
3577 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3578 {
3579         struct vcpu_svm *svm = to_svm(vcpu);
3580
3581         /*
3582          * Flush only the current ASID even if the TLB flush was invoked via
3583          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3584          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3585          * unconditionally does a TLB flush on both nested VM-Enter and nested
3586          * VM-Exit (via kvm_mmu_reset_context()).
3587          */
3588         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3589                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3590         else
3591                 svm->current_vmcb->asid_generation--;
3592 }
3593
3594 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3595 {
3596         struct vcpu_svm *svm = to_svm(vcpu);
3597
3598         invlpga(gva, svm->vmcb->control.asid);
3599 }
3600
3601 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3602 {
3603         struct vcpu_svm *svm = to_svm(vcpu);
3604
3605         if (nested_svm_virtualize_tpr(vcpu))
3606                 return;
3607
3608         if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3609                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3610                 kvm_set_cr8(vcpu, cr8);
3611         }
3612 }
3613
3614 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3615 {
3616         struct vcpu_svm *svm = to_svm(vcpu);
3617         u64 cr8;
3618
3619         if (nested_svm_virtualize_tpr(vcpu) ||
3620             kvm_vcpu_apicv_active(vcpu))
3621                 return;
3622
3623         cr8 = kvm_get_cr8(vcpu);
3624         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3625         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3626 }
3627
3628 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
3629 {
3630         struct vcpu_svm *svm = to_svm(vcpu);
3631         u8 vector;
3632         int type;
3633         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3634         unsigned int3_injected = svm->int3_injected;
3635
3636         svm->int3_injected = 0;
3637
3638         /*
3639          * If we've made progress since setting HF_IRET_MASK, we've
3640          * executed an IRET and can allow NMI injection.
3641          */
3642         if ((vcpu->arch.hflags & HF_IRET_MASK) &&
3643             (sev_es_guest(vcpu->kvm) ||
3644              kvm_rip_read(vcpu) != svm->nmi_iret_rip)) {
3645                 vcpu->arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3646                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3647         }
3648
3649         vcpu->arch.nmi_injected = false;
3650         kvm_clear_exception_queue(vcpu);
3651         kvm_clear_interrupt_queue(vcpu);
3652
3653         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3654                 return;
3655
3656         kvm_make_request(KVM_REQ_EVENT, vcpu);
3657
3658         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3659         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3660
3661         switch (type) {
3662         case SVM_EXITINTINFO_TYPE_NMI:
3663                 vcpu->arch.nmi_injected = true;
3664                 break;
3665         case SVM_EXITINTINFO_TYPE_EXEPT:
3666                 /*
3667                  * Never re-inject a #VC exception.
3668                  */
3669                 if (vector == X86_TRAP_VC)
3670                         break;
3671
3672                 /*
3673                  * In case of software exceptions, do not reinject the vector,
3674                  * but re-execute the instruction instead. Rewind RIP first
3675                  * if we emulated INT3 before.
3676                  */
3677                 if (kvm_exception_is_soft(vector)) {
3678                         if (vector == BP_VECTOR && int3_injected &&
3679                             kvm_is_linear_rip(vcpu, svm->int3_rip))
3680                                 kvm_rip_write(vcpu,
3681                                               kvm_rip_read(vcpu) - int3_injected);
3682                         break;
3683                 }
3684                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3685                         u32 err = svm->vmcb->control.exit_int_info_err;
3686                         kvm_requeue_exception_e(vcpu, vector, err);
3687
3688                 } else
3689                         kvm_requeue_exception(vcpu, vector);
3690                 break;
3691         case SVM_EXITINTINFO_TYPE_INTR:
3692                 kvm_queue_interrupt(vcpu, vector, false);
3693                 break;
3694         default:
3695                 break;
3696         }
3697 }
3698
3699 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3700 {
3701         struct vcpu_svm *svm = to_svm(vcpu);
3702         struct vmcb_control_area *control = &svm->vmcb->control;
3703
3704         control->exit_int_info = control->event_inj;
3705         control->exit_int_info_err = control->event_inj_err;
3706         control->event_inj = 0;
3707         svm_complete_interrupts(vcpu);
3708 }
3709
3710 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3711 {
3712         if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3713             to_svm(vcpu)->vmcb->control.exit_info_1)
3714                 return handle_fastpath_set_msr_irqoff(vcpu);
3715
3716         return EXIT_FASTPATH_NONE;
3717 }
3718
3719 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
3720 {
3721         struct vcpu_svm *svm = to_svm(vcpu);
3722         unsigned long vmcb_pa = svm->current_vmcb->pa;
3723
3724         /*
3725          * VMENTER enables interrupts (host state), but the kernel state is
3726          * interrupts disabled when this is invoked. Also tell RCU about
3727          * it. This is the same logic as for exit_to_user_mode().
3728          *
3729          * This ensures that e.g. latency analysis on the host observes
3730          * guest mode as interrupt enabled.
3731          *
3732          * guest_enter_irqoff() informs context tracking about the
3733          * transition to guest mode and if enabled adjusts RCU state
3734          * accordingly.
3735          */
3736         instrumentation_begin();
3737         trace_hardirqs_on_prepare();
3738         lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3739         instrumentation_end();
3740
3741         guest_enter_irqoff();
3742         lockdep_hardirqs_on(CALLER_ADDR0);
3743
3744         if (sev_es_guest(vcpu->kvm)) {
3745                 __svm_sev_es_vcpu_run(vmcb_pa);
3746         } else {
3747                 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3748
3749                 /*
3750                  * Use a single vmcb (vmcb01 because it's always valid) for
3751                  * context switching guest state via VMLOAD/VMSAVE, that way
3752                  * the state doesn't need to be copied between vmcb01 and
3753                  * vmcb02 when switching vmcbs for nested virtualization.
3754                  */
3755                 vmload(svm->vmcb01.pa);
3756                 __svm_vcpu_run(vmcb_pa, (unsigned long *)&vcpu->arch.regs);
3757                 vmsave(svm->vmcb01.pa);
3758
3759                 vmload(__sme_page_pa(sd->save_area));
3760         }
3761
3762         /*
3763          * VMEXIT disables interrupts (host state), but tracing and lockdep
3764          * have them in state 'on' as recorded before entering guest mode.
3765          * Same as enter_from_user_mode().
3766          *
3767          * guest_exit_irqoff() restores host context and reinstates RCU if
3768          * enabled and required.
3769          *
3770          * This needs to be done before the below as native_read_msr()
3771          * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3772          * into world and some more.
3773          */
3774         lockdep_hardirqs_off(CALLER_ADDR0);
3775         guest_exit_irqoff();
3776
3777         instrumentation_begin();
3778         trace_hardirqs_off_finish();
3779         instrumentation_end();
3780 }
3781
3782 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3783 {
3784         struct vcpu_svm *svm = to_svm(vcpu);
3785
3786         trace_kvm_entry(vcpu);
3787
3788         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3789         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3790         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3791
3792         /*
3793          * Disable singlestep if we're injecting an interrupt/exception.
3794          * We don't want our modified rflags to be pushed on the stack where
3795          * we might not be able to easily reset them if we disabled NMI
3796          * singlestep later.
3797          */
3798         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3799                 /*
3800                  * Event injection happens before external interrupts cause a
3801                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3802                  * is enough to force an immediate vmexit.
3803                  */
3804                 disable_nmi_singlestep(svm);
3805                 smp_send_reschedule(vcpu->cpu);
3806         }
3807
3808         pre_svm_run(vcpu);
3809
3810         sync_lapic_to_cr8(vcpu);
3811
3812         if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3813                 svm->vmcb->control.asid = svm->asid;
3814                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3815         }
3816         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3817
3818         /*
3819          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3820          * of a #DB.
3821          */
3822         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3823                 svm_set_dr6(svm, vcpu->arch.dr6);
3824         else
3825                 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3826
3827         clgi();
3828         kvm_load_guest_xsave_state(vcpu);
3829
3830         kvm_wait_lapic_expire(vcpu);
3831
3832         /*
3833          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3834          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3835          * is no need to worry about the conditional branch over the wrmsr
3836          * being speculatively taken.
3837          */
3838         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3839                 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3840
3841         svm_vcpu_enter_exit(vcpu);
3842
3843         /*
3844          * We do not use IBRS in the kernel. If this vCPU has used the
3845          * SPEC_CTRL MSR it may have left it on; save the value and
3846          * turn it off. This is much more efficient than blindly adding
3847          * it to the atomic save/restore list. Especially as the former
3848          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3849          *
3850          * For non-nested case:
3851          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3852          * save it.
3853          *
3854          * For nested case:
3855          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3856          * save it.
3857          */
3858         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL) &&
3859             unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3860                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3861
3862         if (!sev_es_guest(vcpu->kvm))
3863                 reload_tss(vcpu);
3864
3865         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3866                 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3867
3868         if (!sev_es_guest(vcpu->kvm)) {
3869                 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3870                 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3871                 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3872                 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3873         }
3874
3875         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3876                 kvm_before_interrupt(vcpu);
3877
3878         kvm_load_host_xsave_state(vcpu);
3879         stgi();
3880
3881         /* Any pending NMI will happen here */
3882
3883         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3884                 kvm_after_interrupt(vcpu);
3885
3886         sync_cr8_to_lapic(vcpu);
3887
3888         svm->next_rip = 0;
3889         if (is_guest_mode(vcpu)) {
3890                 nested_sync_control_from_vmcb02(svm);
3891                 svm->nested.nested_run_pending = 0;
3892         }
3893
3894         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3895         vmcb_mark_all_clean(svm->vmcb);
3896
3897         /* if exit due to PF check for async PF */
3898         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3899                 vcpu->arch.apf.host_apf_flags =
3900                         kvm_read_and_reset_apf_flags();
3901
3902         if (npt_enabled) {
3903                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3904                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3905         }
3906
3907         /*
3908          * We need to handle MC intercepts here before the vcpu has a chance to
3909          * change the physical cpu
3910          */
3911         if (unlikely(svm->vmcb->control.exit_code ==
3912                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3913                 svm_handle_mce(vcpu);
3914
3915         svm_complete_interrupts(vcpu);
3916
3917         if (is_guest_mode(vcpu))
3918                 return EXIT_FASTPATH_NONE;
3919
3920         return svm_exit_handlers_fastpath(vcpu);
3921 }
3922
3923 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3924                              int root_level)
3925 {
3926         struct vcpu_svm *svm = to_svm(vcpu);
3927         unsigned long cr3;
3928
3929         if (npt_enabled) {
3930                 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa);
3931                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3932
3933                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3934                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3935                         return;
3936                 cr3 = vcpu->arch.cr3;
3937         } else if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3938                 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
3939         } else {
3940                 /* PCID in the guest should be impossible with a 32-bit MMU. */
3941                 WARN_ON_ONCE(kvm_get_active_pcid(vcpu));
3942                 cr3 = root_hpa;
3943         }
3944
3945         svm->vmcb->save.cr3 = cr3;
3946         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3947 }
3948
3949 static int is_disabled(void)
3950 {
3951         u64 vm_cr;
3952
3953         rdmsrl(MSR_VM_CR, vm_cr);
3954         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3955                 return 1;
3956
3957         return 0;
3958 }
3959
3960 static void
3961 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3962 {
3963         /*
3964          * Patch in the VMMCALL instruction:
3965          */
3966         hypercall[0] = 0x0f;
3967         hypercall[1] = 0x01;
3968         hypercall[2] = 0xd9;
3969 }
3970
3971 static int __init svm_check_processor_compat(void)
3972 {
3973         return 0;
3974 }
3975
3976 static bool svm_cpu_has_accelerated_tpr(void)
3977 {
3978         return false;
3979 }
3980
3981 /*
3982  * The kvm parameter can be NULL (module initialization, or invocation before
3983  * VM creation). Be sure to check the kvm parameter before using it.
3984  */
3985 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
3986 {
3987         switch (index) {
3988         case MSR_IA32_MCG_EXT_CTL:
3989         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3990                 return false;
3991         case MSR_IA32_SMBASE:
3992                 /* SEV-ES guests do not support SMM, so report false */
3993                 if (kvm && sev_es_guest(kvm))
3994                         return false;
3995                 break;
3996         default:
3997                 break;
3998         }
3999
4000         return true;
4001 }
4002
4003 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4004 {
4005         return 0;
4006 }
4007
4008 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
4009 {
4010         struct vcpu_svm *svm = to_svm(vcpu);
4011         struct kvm_cpuid_entry2 *best;
4012
4013         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4014                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
4015                                     boot_cpu_has(X86_FEATURE_XSAVES);
4016
4017         /* Update nrips enabled cache */
4018         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
4019                              guest_cpuid_has(vcpu, X86_FEATURE_NRIPS);
4020
4021         svm_recalc_instruction_intercepts(vcpu, svm);
4022
4023         /* For sev guests, the memory encryption bit is not reserved in CR3.  */
4024         if (sev_guest(vcpu->kvm)) {
4025                 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
4026                 if (best)
4027                         vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
4028         }
4029
4030         if (kvm_vcpu_apicv_active(vcpu)) {
4031                 /*
4032                  * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
4033                  * is exposed to the guest, disable AVIC.
4034                  */
4035                 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
4036                         kvm_request_apicv_update(vcpu->kvm, false,
4037                                                  APICV_INHIBIT_REASON_X2APIC);
4038
4039                 /*
4040                  * Currently, AVIC does not work with nested virtualization.
4041                  * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
4042                  */
4043                 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4044                         kvm_request_apicv_update(vcpu->kvm, false,
4045                                                  APICV_INHIBIT_REASON_NESTED);
4046         }
4047
4048         if (guest_cpuid_is_intel(vcpu)) {
4049                 /*
4050                  * We must intercept SYSENTER_EIP and SYSENTER_ESP
4051                  * accesses because the processor only stores 32 bits.
4052                  * For the same reason we cannot use virtual VMLOAD/VMSAVE.
4053                  */
4054                 svm_set_intercept(svm, INTERCEPT_VMLOAD);
4055                 svm_set_intercept(svm, INTERCEPT_VMSAVE);
4056                 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4057
4058                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0);
4059                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0);
4060         } else {
4061                 /*
4062                  * If hardware supports Virtual VMLOAD VMSAVE then enable it
4063                  * in VMCB and clear intercepts to avoid #VMEXIT.
4064                  */
4065                 if (vls) {
4066                         svm_clr_intercept(svm, INTERCEPT_VMLOAD);
4067                         svm_clr_intercept(svm, INTERCEPT_VMSAVE);
4068                         svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4069                 }
4070                 /* No need to intercept these MSRs */
4071                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
4072                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
4073         }
4074 }
4075
4076 static bool svm_has_wbinvd_exit(void)
4077 {
4078         return true;
4079 }
4080
4081 #define PRE_EX(exit)  { .exit_code = (exit), \
4082                         .stage = X86_ICPT_PRE_EXCEPT, }
4083 #define POST_EX(exit) { .exit_code = (exit), \
4084                         .stage = X86_ICPT_POST_EXCEPT, }
4085 #define POST_MEM(exit) { .exit_code = (exit), \
4086                         .stage = X86_ICPT_POST_MEMACCESS, }
4087
4088 static const struct __x86_intercept {
4089         u32 exit_code;
4090         enum x86_intercept_stage stage;
4091 } x86_intercept_map[] = {
4092         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4093         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4094         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4095         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4096         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4097         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4098         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4099         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4100         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4101         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4102         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4103         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4104         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4105         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4106         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4107         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4108         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4109         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4110         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4111         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4112         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4113         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4114         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4115         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4116         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4117         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4118         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4119         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4120         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4121         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4122         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4123         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4124         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4125         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4126         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4127         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4128         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4129         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4130         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4131         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4132         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4133         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4134         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4135         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4136         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4137         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4138         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
4139 };
4140
4141 #undef PRE_EX
4142 #undef POST_EX
4143 #undef POST_MEM
4144
4145 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4146                                struct x86_instruction_info *info,
4147                                enum x86_intercept_stage stage,
4148                                struct x86_exception *exception)
4149 {
4150         struct vcpu_svm *svm = to_svm(vcpu);
4151         int vmexit, ret = X86EMUL_CONTINUE;
4152         struct __x86_intercept icpt_info;
4153         struct vmcb *vmcb = svm->vmcb;
4154
4155         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4156                 goto out;
4157
4158         icpt_info = x86_intercept_map[info->intercept];
4159
4160         if (stage != icpt_info.stage)
4161                 goto out;
4162
4163         switch (icpt_info.exit_code) {
4164         case SVM_EXIT_READ_CR0:
4165                 if (info->intercept == x86_intercept_cr_read)
4166                         icpt_info.exit_code += info->modrm_reg;
4167                 break;
4168         case SVM_EXIT_WRITE_CR0: {
4169                 unsigned long cr0, val;
4170
4171                 if (info->intercept == x86_intercept_cr_write)
4172                         icpt_info.exit_code += info->modrm_reg;
4173
4174                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4175                     info->intercept == x86_intercept_clts)
4176                         break;
4177
4178                 if (!(vmcb_is_intercept(&svm->nested.ctl,
4179                                         INTERCEPT_SELECTIVE_CR0)))
4180                         break;
4181
4182                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4183                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4184
4185                 if (info->intercept == x86_intercept_lmsw) {
4186                         cr0 &= 0xfUL;
4187                         val &= 0xfUL;
4188                         /* lmsw can't clear PE - catch this here */
4189                         if (cr0 & X86_CR0_PE)
4190                                 val |= X86_CR0_PE;
4191                 }
4192
4193                 if (cr0 ^ val)
4194                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4195
4196                 break;
4197         }
4198         case SVM_EXIT_READ_DR0:
4199         case SVM_EXIT_WRITE_DR0:
4200                 icpt_info.exit_code += info->modrm_reg;
4201                 break;
4202         case SVM_EXIT_MSR:
4203                 if (info->intercept == x86_intercept_wrmsr)
4204                         vmcb->control.exit_info_1 = 1;
4205                 else
4206                         vmcb->control.exit_info_1 = 0;
4207                 break;
4208         case SVM_EXIT_PAUSE:
4209                 /*
4210                  * We get this for NOP only, but pause
4211                  * is rep not, check this here
4212                  */
4213                 if (info->rep_prefix != REPE_PREFIX)
4214                         goto out;
4215                 break;
4216         case SVM_EXIT_IOIO: {
4217                 u64 exit_info;
4218                 u32 bytes;
4219
4220                 if (info->intercept == x86_intercept_in ||
4221                     info->intercept == x86_intercept_ins) {
4222                         exit_info = ((info->src_val & 0xffff) << 16) |
4223                                 SVM_IOIO_TYPE_MASK;
4224                         bytes = info->dst_bytes;
4225                 } else {
4226                         exit_info = (info->dst_val & 0xffff) << 16;
4227                         bytes = info->src_bytes;
4228                 }
4229
4230                 if (info->intercept == x86_intercept_outs ||
4231                     info->intercept == x86_intercept_ins)
4232                         exit_info |= SVM_IOIO_STR_MASK;
4233
4234                 if (info->rep_prefix)
4235                         exit_info |= SVM_IOIO_REP_MASK;
4236
4237                 bytes = min(bytes, 4u);
4238
4239                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4240
4241                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4242
4243                 vmcb->control.exit_info_1 = exit_info;
4244                 vmcb->control.exit_info_2 = info->next_rip;
4245
4246                 break;
4247         }
4248         default:
4249                 break;
4250         }
4251
4252         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4253         if (static_cpu_has(X86_FEATURE_NRIPS))
4254                 vmcb->control.next_rip  = info->next_rip;
4255         vmcb->control.exit_code = icpt_info.exit_code;
4256         vmexit = nested_svm_exit_handled(svm);
4257
4258         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4259                                            : X86EMUL_CONTINUE;
4260
4261 out:
4262         return ret;
4263 }
4264
4265 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4266 {
4267 }
4268
4269 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4270 {
4271         if (!kvm_pause_in_guest(vcpu->kvm))
4272                 shrink_ple_window(vcpu);
4273 }
4274
4275 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4276 {
4277         /* [63:9] are reserved. */
4278         vcpu->arch.mcg_cap &= 0x1ff;
4279 }
4280
4281 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4282 {
4283         struct vcpu_svm *svm = to_svm(vcpu);
4284
4285         /* Per APM Vol.2 15.22.2 "Response to SMI" */
4286         if (!gif_set(svm))
4287                 return true;
4288
4289         return is_smm(vcpu);
4290 }
4291
4292 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4293 {
4294         struct vcpu_svm *svm = to_svm(vcpu);
4295         if (svm->nested.nested_run_pending)
4296                 return -EBUSY;
4297
4298         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
4299         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4300                 return -EBUSY;
4301
4302         return !svm_smi_blocked(vcpu);
4303 }
4304
4305 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4306 {
4307         struct vcpu_svm *svm = to_svm(vcpu);
4308         int ret;
4309
4310         if (is_guest_mode(vcpu)) {
4311                 /* FED8h - SVM Guest */
4312                 put_smstate(u64, smstate, 0x7ed8, 1);
4313                 /* FEE0h - SVM Guest VMCB Physical Address */
4314                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4315
4316                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4317                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4318                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4319
4320                 ret = nested_svm_vmexit(svm);
4321                 if (ret)
4322                         return ret;
4323         }
4324         return 0;
4325 }
4326
4327 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4328 {
4329         struct vcpu_svm *svm = to_svm(vcpu);
4330         struct kvm_host_map map;
4331         int ret = 0;
4332
4333         if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4334                 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4335                 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4336                 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4337
4338                 if (guest) {
4339                         if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4340                                 return 1;
4341
4342                         if (!(saved_efer & EFER_SVME))
4343                                 return 1;
4344
4345                         if (kvm_vcpu_map(vcpu,
4346                                          gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4347                                 return 1;
4348
4349                         if (svm_allocate_nested(svm))
4350                                 return 1;
4351
4352                         ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, map.hva);
4353                         kvm_vcpu_unmap(vcpu, &map, true);
4354                 }
4355         }
4356
4357         return ret;
4358 }
4359
4360 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4361 {
4362         struct vcpu_svm *svm = to_svm(vcpu);
4363
4364         if (!gif_set(svm)) {
4365                 if (vgif_enabled(svm))
4366                         svm_set_intercept(svm, INTERCEPT_STGI);
4367                 /* STGI will cause a vm exit */
4368         } else {
4369                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
4370         }
4371 }
4372
4373 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4374 {
4375         bool smep, smap, is_user;
4376         unsigned long cr4;
4377
4378         /*
4379          * When the guest is an SEV-ES guest, emulation is not possible.
4380          */
4381         if (sev_es_guest(vcpu->kvm))
4382                 return false;
4383
4384         /*
4385          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4386          *
4387          * Errata:
4388          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4389          * possible that CPU microcode implementing DecodeAssist will fail
4390          * to read bytes of instruction which caused #NPF. In this case,
4391          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4392          * return 0 instead of the correct guest instruction bytes.
4393          *
4394          * This happens because CPU microcode reading instruction bytes
4395          * uses a special opcode which attempts to read data using CPL=0
4396          * privileges. The microcode reads CS:RIP and if it hits a SMAP
4397          * fault, it gives up and returns no instruction bytes.
4398          *
4399          * Detection:
4400          * We reach here in case CPU supports DecodeAssist, raised #NPF and
4401          * returned 0 in GuestIntrBytes field of the VMCB.
4402          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4403          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4404          * in case vCPU CPL==3 (Because otherwise guest would have triggered
4405          * a SMEP fault instead of #NPF).
4406          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4407          * As most guests enable SMAP if they have also enabled SMEP, use above
4408          * logic in order to attempt minimize false-positive of detecting errata
4409          * while still preserving all cases semantic correctness.
4410          *
4411          * Workaround:
4412          * To determine what instruction the guest was executing, the hypervisor
4413          * will have to decode the instruction at the instruction pointer.
4414          *
4415          * In non SEV guest, hypervisor will be able to read the guest
4416          * memory to decode the instruction pointer when insn_len is zero
4417          * so we return true to indicate that decoding is possible.
4418          *
4419          * But in the SEV guest, the guest memory is encrypted with the
4420          * guest specific key and hypervisor will not be able to decode the
4421          * instruction pointer so we will not able to workaround it. Lets
4422          * print the error and request to kill the guest.
4423          */
4424         if (likely(!insn || insn_len))
4425                 return true;
4426
4427         /*
4428          * If RIP is invalid, go ahead with emulation which will cause an
4429          * internal error exit.
4430          */
4431         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4432                 return true;
4433
4434         cr4 = kvm_read_cr4(vcpu);
4435         smep = cr4 & X86_CR4_SMEP;
4436         smap = cr4 & X86_CR4_SMAP;
4437         is_user = svm_get_cpl(vcpu) == 3;
4438         if (smap && (!smep || is_user)) {
4439                 if (!sev_guest(vcpu->kvm))
4440                         return true;
4441
4442                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4443                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4444         }
4445
4446         return false;
4447 }
4448
4449 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4450 {
4451         struct vcpu_svm *svm = to_svm(vcpu);
4452
4453         /*
4454          * TODO: Last condition latch INIT signals on vCPU when
4455          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4456          * To properly emulate the INIT intercept,
4457          * svm_check_nested_events() should call nested_svm_vmexit()
4458          * if an INIT signal is pending.
4459          */
4460         return !gif_set(svm) ||
4461                    (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4462 }
4463
4464 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4465 {
4466         if (!sev_es_guest(vcpu->kvm))
4467                 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4468
4469         sev_vcpu_deliver_sipi_vector(vcpu, vector);
4470 }
4471
4472 static void svm_vm_destroy(struct kvm *kvm)
4473 {
4474         avic_vm_destroy(kvm);
4475         sev_vm_destroy(kvm);
4476 }
4477
4478 static int svm_vm_init(struct kvm *kvm)
4479 {
4480         if (!pause_filter_count || !pause_filter_thresh)
4481                 kvm->arch.pause_in_guest = true;
4482
4483         if (avic) {
4484                 int ret = avic_vm_init(kvm);
4485                 if (ret)
4486                         return ret;
4487         }
4488
4489         kvm_apicv_init(kvm, avic);
4490         return 0;
4491 }
4492
4493 static struct kvm_x86_ops svm_x86_ops __initdata = {
4494         .hardware_unsetup = svm_hardware_teardown,
4495         .hardware_enable = svm_hardware_enable,
4496         .hardware_disable = svm_hardware_disable,
4497         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4498         .has_emulated_msr = svm_has_emulated_msr,
4499
4500         .vcpu_create = svm_create_vcpu,
4501         .vcpu_free = svm_free_vcpu,
4502         .vcpu_reset = svm_vcpu_reset,
4503
4504         .vm_size = sizeof(struct kvm_svm),
4505         .vm_init = svm_vm_init,
4506         .vm_destroy = svm_vm_destroy,
4507
4508         .prepare_guest_switch = svm_prepare_guest_switch,
4509         .vcpu_load = svm_vcpu_load,
4510         .vcpu_put = svm_vcpu_put,
4511         .vcpu_blocking = svm_vcpu_blocking,
4512         .vcpu_unblocking = svm_vcpu_unblocking,
4513
4514         .update_exception_bitmap = svm_update_exception_bitmap,
4515         .get_msr_feature = svm_get_msr_feature,
4516         .get_msr = svm_get_msr,
4517         .set_msr = svm_set_msr,
4518         .get_segment_base = svm_get_segment_base,
4519         .get_segment = svm_get_segment,
4520         .set_segment = svm_set_segment,
4521         .get_cpl = svm_get_cpl,
4522         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4523         .set_cr0 = svm_set_cr0,
4524         .is_valid_cr4 = svm_is_valid_cr4,
4525         .set_cr4 = svm_set_cr4,
4526         .set_efer = svm_set_efer,
4527         .get_idt = svm_get_idt,
4528         .set_idt = svm_set_idt,
4529         .get_gdt = svm_get_gdt,
4530         .set_gdt = svm_set_gdt,
4531         .set_dr7 = svm_set_dr7,
4532         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4533         .cache_reg = svm_cache_reg,
4534         .get_rflags = svm_get_rflags,
4535         .set_rflags = svm_set_rflags,
4536
4537         .tlb_flush_all = svm_flush_tlb,
4538         .tlb_flush_current = svm_flush_tlb,
4539         .tlb_flush_gva = svm_flush_tlb_gva,
4540         .tlb_flush_guest = svm_flush_tlb,
4541
4542         .run = svm_vcpu_run,
4543         .handle_exit = handle_exit,
4544         .skip_emulated_instruction = skip_emulated_instruction,
4545         .update_emulated_instruction = NULL,
4546         .set_interrupt_shadow = svm_set_interrupt_shadow,
4547         .get_interrupt_shadow = svm_get_interrupt_shadow,
4548         .patch_hypercall = svm_patch_hypercall,
4549         .set_irq = svm_set_irq,
4550         .set_nmi = svm_inject_nmi,
4551         .queue_exception = svm_queue_exception,
4552         .cancel_injection = svm_cancel_injection,
4553         .interrupt_allowed = svm_interrupt_allowed,
4554         .nmi_allowed = svm_nmi_allowed,
4555         .get_nmi_mask = svm_get_nmi_mask,
4556         .set_nmi_mask = svm_set_nmi_mask,
4557         .enable_nmi_window = svm_enable_nmi_window,
4558         .enable_irq_window = svm_enable_irq_window,
4559         .update_cr8_intercept = svm_update_cr8_intercept,
4560         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4561         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4562         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4563         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4564         .load_eoi_exitmap = svm_load_eoi_exitmap,
4565         .hwapic_irr_update = svm_hwapic_irr_update,
4566         .hwapic_isr_update = svm_hwapic_isr_update,
4567         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4568         .apicv_post_state_restore = avic_post_state_restore,
4569
4570         .set_tss_addr = svm_set_tss_addr,
4571         .set_identity_map_addr = svm_set_identity_map_addr,
4572         .get_mt_mask = svm_get_mt_mask,
4573
4574         .get_exit_info = svm_get_exit_info,
4575
4576         .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4577
4578         .has_wbinvd_exit = svm_has_wbinvd_exit,
4579
4580         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4581
4582         .load_mmu_pgd = svm_load_mmu_pgd,
4583
4584         .check_intercept = svm_check_intercept,
4585         .handle_exit_irqoff = svm_handle_exit_irqoff,
4586
4587         .request_immediate_exit = __kvm_request_immediate_exit,
4588
4589         .sched_in = svm_sched_in,
4590
4591         .pmu_ops = &amd_pmu_ops,
4592         .nested_ops = &svm_nested_ops,
4593
4594         .deliver_posted_interrupt = svm_deliver_avic_intr,
4595         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4596         .update_pi_irte = svm_update_pi_irte,
4597         .setup_mce = svm_setup_mce,
4598
4599         .smi_allowed = svm_smi_allowed,
4600         .pre_enter_smm = svm_pre_enter_smm,
4601         .pre_leave_smm = svm_pre_leave_smm,
4602         .enable_smi_window = svm_enable_smi_window,
4603
4604         .mem_enc_op = svm_mem_enc_op,
4605         .mem_enc_reg_region = svm_register_enc_region,
4606         .mem_enc_unreg_region = svm_unregister_enc_region,
4607
4608         .vm_copy_enc_context_from = svm_vm_copy_asid_from,
4609
4610         .can_emulate_instruction = svm_can_emulate_instruction,
4611
4612         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4613
4614         .msr_filter_changed = svm_msr_filter_changed,
4615         .complete_emulated_msr = svm_complete_emulated_msr,
4616
4617         .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4618 };
4619
4620 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4621         .cpu_has_kvm_support = has_svm,
4622         .disabled_by_bios = is_disabled,
4623         .hardware_setup = svm_hardware_setup,
4624         .check_processor_compatibility = svm_check_processor_compat,
4625
4626         .runtime_ops = &svm_x86_ops,
4627 };
4628
4629 static int __init svm_init(void)
4630 {
4631         __unused_size_checks();
4632
4633         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4634                         __alignof__(struct vcpu_svm), THIS_MODULE);
4635 }
4636
4637 static void __exit svm_exit(void)
4638 {
4639         kvm_exit();
4640 }
4641
4642 module_init(svm_init)
4643 module_exit(svm_exit)