arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/objtool.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/spec-ctrl.h>
  37 #include <asm/cpu_device_id.h>
  38 #include <asm/traps.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44 #include "svm_ops.h"
  45
  46 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  47
  48 MODULE_AUTHOR("Qumranet");
  49 MODULE_LICENSE("GPL");
  50
  51 #ifdef MODULE
  52 static const struct x86_cpu_id svm_cpu_id[] = {
  53         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  54         {}
  55 };
  56 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  57 #endif
  58
  59 #define SEG_TYPE_LDT 2
  60 #define SEG_TYPE_BUSY_TSS16 3
  61
  62 #define SVM_FEATURE_LBRV           (1 <<  1)
  63 #define SVM_FEATURE_SVML           (1 <<  2)
  64 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  65 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  66 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  67 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  68 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  69
  70 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  71
  72 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  73 #define TSC_RATIO_MIN           0x0000000000000001ULL
  74 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  75
  76 static bool erratum_383_found __read_mostly;
  77
  78 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  79
  80 /*
  81  * Set osvw_len to higher value when updated Revision Guides
  82  * are published and we know what the new status bits are
  83  */
  84 static uint64_t osvw_len = 4, osvw_status;
  85
  86 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  87 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  88
  89 static const struct svm_direct_access_msrs {
  90         u32 index;   /* Index of the MSR */
  91         bool always; /* True if intercept is initially cleared */
  92 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
  93         { .index = MSR_STAR,                            .always = true  },
  94         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  95         { .index = MSR_IA32_SYSENTER_EIP,               .always = false },
  96         { .index = MSR_IA32_SYSENTER_ESP,               .always = false },
  97 #ifdef CONFIG_X86_64
  98         { .index = MSR_GS_BASE,                         .always = true  },
  99         { .index = MSR_FS_BASE,                         .always = true  },
 100         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 101         { .index = MSR_LSTAR,                           .always = true  },
 102         { .index = MSR_CSTAR,                           .always = true  },
 103         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 104 #endif
 105         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 106         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 107         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 108         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 109         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 110         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 111         { .index = MSR_EFER,                            .always = false },
 112         { .index = MSR_IA32_CR_PAT,                     .always = false },
 113         { .index = MSR_AMD64_SEV_ES_GHCB,               .always = true  },
 114         { .index = MSR_INVALID,                         .always = false },
 115 };
 116
 117 /*
 118  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 119  * pause_filter_count: On processors that support Pause filtering(indicated
 120  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 121  *      count value. On VMRUN this value is loaded into an internal counter.
 122  *      Each time a pause instruction is executed, this counter is decremented
 123  *      until it reaches zero at which time a #VMEXIT is generated if pause
 124  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 125  *      Intercept Filtering for more details.
 126  *      This also indicate if ple logic enabled.
 127  *
 128  * pause_filter_thresh: In addition, some processor families support advanced
 129  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 130  *      the amount of time a guest is allowed to execute in a pause loop.
 131  *      In this mode, a 16-bit pause filter threshold field is added in the
 132  *      VMCB. The threshold value is a cycle count that is used to reset the
 133  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 134  *      count value from VMCB into an internal counter. Then, on each pause
 135  *      instruction the hardware checks the elapsed number of cycles since
 136  *      the most recent pause instruction against the pause filter threshold.
 137  *      If the elapsed cycle count is greater than the pause filter threshold,
 138  *      then the internal pause count is reloaded from the VMCB and execution
 139  *      continues. If the elapsed cycle count is less than the pause filter
 140  *      threshold, then the internal pause count is decremented. If the count
 141  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 142  *      triggered. If advanced pause filtering is supported and pause filter
 143  *      threshold field is set to zero, the filter will operate in the simpler,
 144  *      count only mode.
 145  */
 146
 147 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 148 module_param(pause_filter_thresh, ushort, 0444);
 149
 150 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 151 module_param(pause_filter_count, ushort, 0444);
 152
 153 /* Default doubles per-vcpu window every exit. */
 154 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 155 module_param(pause_filter_count_grow, ushort, 0444);
 156
 157 /* Default resets per-vcpu window every exit to pause_filter_count. */
 158 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 159 module_param(pause_filter_count_shrink, ushort, 0444);
 160
 161 /* Default is to compute the maximum so we can never overflow. */
 162 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(pause_filter_count_max, ushort, 0444);
 164
 165 /*
 166  * Use nested page tables by default.  Note, NPT may get forced off by
 167  * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
 168  */
 169 bool npt_enabled = true;
 170 module_param_named(npt, npt_enabled, bool, 0444);
 171
 172 /* allow nested virtualization in KVM/SVM */
 173 static int nested = true;
 174 module_param(nested, int, S_IRUGO);
 175
 176 /* enable/disable Next RIP Save */
 177 static int nrips = true;
 178 module_param(nrips, int, 0444);
 179
 180 /* enable/disable Virtual VMLOAD VMSAVE */
 181 static int vls = true;
 182 module_param(vls, int, 0444);
 183
 184 /* enable/disable Virtual GIF */
 185 static int vgif = true;
 186 module_param(vgif, int, 0444);
 187
 188 /* enable/disable SEV support */
 189 int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 190 module_param(sev, int, 0444);
 191
 192 /* enable/disable SEV-ES support */
 193 int sev_es = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 194 module_param(sev_es, int, 0444);
 195
 196 bool __read_mostly dump_invalid_vmcb;
 197 module_param(dump_invalid_vmcb, bool, 0644);
 198
 199 static bool svm_gp_erratum_intercept = true;
 200
 201 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 202
 203 static unsigned long iopm_base;
 204
 205 struct kvm_ldttss_desc {
 206         u16 limit0;
 207         u16 base0;
 208         unsigned base1:8, type:5, dpl:2, p:1;
 209         unsigned limit1:4, zero0:3, g:1, base2:8;
 210         u32 base3;
 211         u32 zero1;
 212 } __attribute__((packed));
 213
 214 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 215
 216 /*
 217  * Only MSR_TSC_AUX is switched via the user return hook.  EFER is switched via
 218  * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
 219  *
 220  * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
 221  * defer the restoration of TSC_AUX until the CPU returns to userspace.
 222  */
 223 #define TSC_AUX_URET_SLOT       0
 224
 225 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 226
 227 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 228 #define MSRS_RANGE_SIZE 2048
 229 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 230
 231 u32 svm_msrpm_offset(u32 msr)
 232 {
 233         u32 offset;
 234         int i;
 235
 236         for (i = 0; i < NUM_MSR_MAPS; i++) {
 237                 if (msr < msrpm_ranges[i] ||
 238                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 239                         continue;
 240
 241                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 242                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 243
 244                 /* Now we have the u8 offset - but need the u32 offset */
 245                 return offset / 4;
 246         }
 247
 248         /* MSR not in any range */
 249         return MSR_INVALID;
 250 }
 251
 252 #define MAX_INST_SIZE 15
 253
 254 static int get_max_npt_level(void)
 255 {
 256 #ifdef CONFIG_X86_64
 257         return PT64_ROOT_4LEVEL;
 258 #else
 259         return PT32E_ROOT_LEVEL;
 260 #endif
 261 }
 262
 263 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 264 {
 265         struct vcpu_svm *svm = to_svm(vcpu);
 266         u64 old_efer = vcpu->arch.efer;
 267         vcpu->arch.efer = efer;
 268
 269         if (!npt_enabled) {
 270                 /* Shadow paging assumes NX to be available.  */
 271                 efer |= EFER_NX;
 272
 273                 if (!(efer & EFER_LMA))
 274                         efer &= ~EFER_LME;
 275         }
 276
 277         if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
 278                 if (!(efer & EFER_SVME)) {
 279                         svm_leave_nested(svm);
 280                         svm_set_gif(svm, true);
 281                         /* #GP intercept is still needed for vmware backdoor */
 282                         if (!enable_vmware_backdoor)
 283                                 clr_exception_intercept(svm, GP_VECTOR);
 284
 285                         /*
 286                          * Free the nested guest state, unless we are in SMM.
 287                          * In this case we will return to the nested guest
 288                          * as soon as we leave SMM.
 289                          */
 290                         if (!is_smm(vcpu))
 291                                 svm_free_nested(svm);
 292
 293                 } else {
 294                         int ret = svm_allocate_nested(svm);
 295
 296                         if (ret) {
 297                                 vcpu->arch.efer = old_efer;
 298                                 return ret;
 299                         }
 300
 301                         if (svm_gp_erratum_intercept)
 302                                 set_exception_intercept(svm, GP_VECTOR);
 303                 }
 304         }
 305
 306         svm->vmcb->save.efer = efer | EFER_SVME;
 307         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
 308         return 0;
 309 }
 310
 311 static int is_external_interrupt(u32 info)
 312 {
 313         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 314         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 315 }
 316
 317 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 318 {
 319         struct vcpu_svm *svm = to_svm(vcpu);
 320         u32 ret = 0;
 321
 322         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 323                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 324         return ret;
 325 }
 326
 327 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 328 {
 329         struct vcpu_svm *svm = to_svm(vcpu);
 330
 331         if (mask == 0)
 332                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 333         else
 334                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 335
 336 }
 337
 338 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 339 {
 340         struct vcpu_svm *svm = to_svm(vcpu);
 341
 342         /*
 343          * SEV-ES does not expose the next RIP. The RIP update is controlled by
 344          * the type of exit and the #VC handler in the guest.
 345          */
 346         if (sev_es_guest(vcpu->kvm))
 347                 goto done;
 348
 349         if (nrips && svm->vmcb->control.next_rip != 0) {
 350                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 351                 svm->next_rip = svm->vmcb->control.next_rip;
 352         }
 353
 354         if (!svm->next_rip) {
 355                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 356                         return 0;
 357         } else {
 358                 kvm_rip_write(vcpu, svm->next_rip);
 359         }
 360
 361 done:
 362         svm_set_interrupt_shadow(vcpu, 0);
 363
 364         return 1;
 365 }
 366
 367 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 368 {
 369         struct vcpu_svm *svm = to_svm(vcpu);
 370         unsigned nr = vcpu->arch.exception.nr;
 371         bool has_error_code = vcpu->arch.exception.has_error_code;
 372         u32 error_code = vcpu->arch.exception.error_code;
 373
 374         kvm_deliver_exception_payload(vcpu);
 375
 376         if (nr == BP_VECTOR && !nrips) {
 377                 unsigned long rip, old_rip = kvm_rip_read(vcpu);
 378
 379                 /*
 380                  * For guest debugging where we have to reinject #BP if some
 381                  * INT3 is guest-owned:
 382                  * Emulate nRIP by moving RIP forward. Will fail if injection
 383                  * raises a fault that is not intercepted. Still better than
 384                  * failing in all cases.
 385                  */
 386                 (void)skip_emulated_instruction(vcpu);
 387                 rip = kvm_rip_read(vcpu);
 388                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 389                 svm->int3_injected = rip - old_rip;
 390         }
 391
 392         svm->vmcb->control.event_inj = nr
 393                 | SVM_EVTINJ_VALID
 394                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 395                 | SVM_EVTINJ_TYPE_EXEPT;
 396         svm->vmcb->control.event_inj_err = error_code;
 397 }
 398
 399 static void svm_init_erratum_383(void)
 400 {
 401         u32 low, high;
 402         int err;
 403         u64 val;
 404
 405         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 406                 return;
 407
 408         /* Use _safe variants to not break nested virtualization */
 409         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 410         if (err)
 411                 return;
 412
 413         val |= (1ULL << 47);
 414
 415         low  = lower_32_bits(val);
 416         high = upper_32_bits(val);
 417
 418         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 419
 420         erratum_383_found = true;
 421 }
 422
 423 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 424 {
 425         /*
 426          * Guests should see errata 400 and 415 as fixed (assuming that
 427          * HLT and IO instructions are intercepted).
 428          */
 429         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 430         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 431
 432         /*
 433          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 434          * all osvw.status bits inside that length, including bit 0 (which is
 435          * reserved for erratum 298), are valid. However, if host processor's
 436          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 437          * be conservative here and therefore we tell the guest that erratum 298
 438          * is present (because we really don't know).
 439          */
 440         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 441                 vcpu->arch.osvw.status |= 1;
 442 }
 443
 444 static int has_svm(void)
 445 {
 446         const char *msg;
 447
 448         if (!cpu_has_svm(&msg)) {
 449                 printk(KERN_INFO "has_svm: %s\n", msg);
 450                 return 0;
 451         }
 452
 453         if (sev_active()) {
 454                 pr_info("KVM is unsupported when running as an SEV guest\n");
 455                 return 0;
 456         }
 457
 458         return 1;
 459 }
 460
 461 static void svm_hardware_disable(void)
 462 {
 463         /* Make sure we clean up behind us */
 464         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 465                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 466
 467         cpu_svm_disable();
 468
 469         amd_pmu_disable_virt();
 470 }
 471
 472 static int svm_hardware_enable(void)
 473 {
 474
 475         struct svm_cpu_data *sd;
 476         uint64_t efer;
 477         struct desc_struct *gdt;
 478         int me = raw_smp_processor_id();
 479
 480         rdmsrl(MSR_EFER, efer);
 481         if (efer & EFER_SVME)
 482                 return -EBUSY;
 483
 484         if (!has_svm()) {
 485                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 486                 return -EINVAL;
 487         }
 488         sd = per_cpu(svm_data, me);
 489         if (!sd) {
 490                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 491                 return -EINVAL;
 492         }
 493
 494         sd->asid_generation = 1;
 495         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 496         sd->next_asid = sd->max_asid + 1;
 497         sd->min_asid = max_sev_asid + 1;
 498
 499         gdt = get_current_gdt_rw();
 500         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 501
 502         wrmsrl(MSR_EFER, efer | EFER_SVME);
 503
 504         wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
 505
 506         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 507                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 508                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 509         }
 510
 511
 512         /*
 513          * Get OSVW bits.
 514          *
 515          * Note that it is possible to have a system with mixed processor
 516          * revisions and therefore different OSVW bits. If bits are not the same
 517          * on different processors then choose the worst case (i.e. if erratum
 518          * is present on one processor and not on another then assume that the
 519          * erratum is present everywhere).
 520          */
 521         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 522                 uint64_t len, status = 0;
 523                 int err;
 524
 525                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 526                 if (!err)
 527                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 528                                                       &err);
 529
 530                 if (err)
 531                         osvw_status = osvw_len = 0;
 532                 else {
 533                         if (len < osvw_len)
 534                                 osvw_len = len;
 535                         osvw_status |= status;
 536                         osvw_status &= (1ULL << osvw_len) - 1;
 537                 }
 538         } else
 539                 osvw_status = osvw_len = 0;
 540
 541         svm_init_erratum_383();
 542
 543         amd_pmu_enable_virt();
 544
 545         return 0;
 546 }
 547
 548 static void svm_cpu_uninit(int cpu)
 549 {
 550         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
 551
 552         if (!sd)
 553                 return;
 554
 555         per_cpu(svm_data, cpu) = NULL;
 556         kfree(sd->sev_vmcbs);
 557         __free_page(sd->save_area);
 558         kfree(sd);
 559 }
 560
 561 static int svm_cpu_init(int cpu)
 562 {
 563         struct svm_cpu_data *sd;
 564
 565         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 566         if (!sd)
 567                 return -ENOMEM;
 568         sd->cpu = cpu;
 569         sd->save_area = alloc_page(GFP_KERNEL);
 570         if (!sd->save_area)
 571                 goto free_cpu_data;
 572         clear_page(page_address(sd->save_area));
 573
 574         if (svm_sev_enabled()) {
 575                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
 576                                               sizeof(void *),
 577                                               GFP_KERNEL);
 578                 if (!sd->sev_vmcbs)
 579                         goto free_save_area;
 580         }
 581
 582         per_cpu(svm_data, cpu) = sd;
 583
 584         return 0;
 585
 586 free_save_area:
 587         __free_page(sd->save_area);
 588 free_cpu_data:
 589         kfree(sd);
 590         return -ENOMEM;
 591
 592 }
 593
 594 static int direct_access_msr_slot(u32 msr)
 595 {
 596         u32 i;
 597
 598         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 599                 if (direct_access_msrs[i].index == msr)
 600                         return i;
 601
 602         return -ENOENT;
 603 }
 604
 605 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
 606                                      int write)
 607 {
 608         struct vcpu_svm *svm = to_svm(vcpu);
 609         int slot = direct_access_msr_slot(msr);
 610
 611         if (slot == -ENOENT)
 612                 return;
 613
 614         /* Set the shadow bitmaps to the desired intercept states */
 615         if (read)
 616                 set_bit(slot, svm->shadow_msr_intercept.read);
 617         else
 618                 clear_bit(slot, svm->shadow_msr_intercept.read);
 619
 620         if (write)
 621                 set_bit(slot, svm->shadow_msr_intercept.write);
 622         else
 623                 clear_bit(slot, svm->shadow_msr_intercept.write);
 624 }
 625
 626 static bool valid_msr_intercept(u32 index)
 627 {
 628         return direct_access_msr_slot(index) != -ENOENT;
 629 }
 630
 631 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 632 {
 633         u8 bit_write;
 634         unsigned long tmp;
 635         u32 offset;
 636         u32 *msrpm;
 637
 638         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 639                                       to_svm(vcpu)->msrpm;
 640
 641         offset    = svm_msrpm_offset(msr);
 642         bit_write = 2 * (msr & 0x0f) + 1;
 643         tmp       = msrpm[offset];
 644
 645         BUG_ON(offset == MSR_INVALID);
 646
 647         return !!test_bit(bit_write,  &tmp);
 648 }
 649
 650 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
 651                                         u32 msr, int read, int write)
 652 {
 653         u8 bit_read, bit_write;
 654         unsigned long tmp;
 655         u32 offset;
 656
 657         /*
 658          * If this warning triggers extend the direct_access_msrs list at the
 659          * beginning of the file
 660          */
 661         WARN_ON(!valid_msr_intercept(msr));
 662
 663         /* Enforce non allowed MSRs to trap */
 664         if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
 665                 read = 0;
 666
 667         if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
 668                 write = 0;
 669
 670         offset    = svm_msrpm_offset(msr);
 671         bit_read  = 2 * (msr & 0x0f);
 672         bit_write = 2 * (msr & 0x0f) + 1;
 673         tmp       = msrpm[offset];
 674
 675         BUG_ON(offset == MSR_INVALID);
 676
 677         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 678         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 679
 680         msrpm[offset] = tmp;
 681 }
 682
 683 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 684                           int read, int write)
 685 {
 686         set_shadow_msr_intercept(vcpu, msr, read, write);
 687         set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
 688 }
 689
 690 u32 *svm_vcpu_alloc_msrpm(void)
 691 {
 692         unsigned int order = get_order(MSRPM_SIZE);
 693         struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order);
 694         u32 *msrpm;
 695
 696         if (!pages)
 697                 return NULL;
 698
 699         msrpm = page_address(pages);
 700         memset(msrpm, 0xff, PAGE_SIZE * (1 << order));
 701
 702         return msrpm;
 703 }
 704
 705 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
 706 {
 707         int i;
 708
 709         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 710                 if (!direct_access_msrs[i].always)
 711                         continue;
 712                 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
 713         }
 714 }
 715
 716
 717 void svm_vcpu_free_msrpm(u32 *msrpm)
 718 {
 719         __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE));
 720 }
 721
 722 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
 723 {
 724         struct vcpu_svm *svm = to_svm(vcpu);
 725         u32 i;
 726
 727         /*
 728          * Set intercept permissions for all direct access MSRs again. They
 729          * will automatically get filtered through the MSR filter, so we are
 730          * back in sync after this.
 731          */
 732         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 733                 u32 msr = direct_access_msrs[i].index;
 734                 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
 735                 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
 736
 737                 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
 738         }
 739 }
 740
 741 static void add_msr_offset(u32 offset)
 742 {
 743         int i;
 744
 745         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 746
 747                 /* Offset already in list? */
 748                 if (msrpm_offsets[i] == offset)
 749                         return;
 750
 751                 /* Slot used by another offset? */
 752                 if (msrpm_offsets[i] != MSR_INVALID)
 753                         continue;
 754
 755                 /* Add offset to list */
 756                 msrpm_offsets[i] = offset;
 757
 758                 return;
 759         }
 760
 761         /*
 762          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 763          * increase MSRPM_OFFSETS in this case.
 764          */
 765         BUG();
 766 }
 767
 768 static void init_msrpm_offsets(void)
 769 {
 770         int i;
 771
 772         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 773
 774         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 775                 u32 offset;
 776
 777                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 778                 BUG_ON(offset == MSR_INVALID);
 779
 780                 add_msr_offset(offset);
 781         }
 782 }
 783
 784 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
 785 {
 786         struct vcpu_svm *svm = to_svm(vcpu);
 787
 788         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 789         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 790         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 791         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 792         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 793 }
 794
 795 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
 796 {
 797         struct vcpu_svm *svm = to_svm(vcpu);
 798
 799         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 800         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 801         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 802         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 803         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 804 }
 805
 806 void disable_nmi_singlestep(struct vcpu_svm *svm)
 807 {
 808         svm->nmi_singlestep = false;
 809
 810         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 811                 /* Clear our flags if they were not set by the guest */
 812                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 813                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 814                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 815                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 816         }
 817 }
 818
 819 static void grow_ple_window(struct kvm_vcpu *vcpu)
 820 {
 821         struct vcpu_svm *svm = to_svm(vcpu);
 822         struct vmcb_control_area *control = &svm->vmcb->control;
 823         int old = control->pause_filter_count;
 824
 825         control->pause_filter_count = __grow_ple_window(old,
 826                                                         pause_filter_count,
 827                                                         pause_filter_count_grow,
 828                                                         pause_filter_count_max);
 829
 830         if (control->pause_filter_count != old) {
 831                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 832                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 833                                             control->pause_filter_count, old);
 834         }
 835 }
 836
 837 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 838 {
 839         struct vcpu_svm *svm = to_svm(vcpu);
 840         struct vmcb_control_area *control = &svm->vmcb->control;
 841         int old = control->pause_filter_count;
 842
 843         control->pause_filter_count =
 844                                 __shrink_ple_window(old,
 845                                                     pause_filter_count,
 846                                                     pause_filter_count_shrink,
 847                                                     pause_filter_count);
 848         if (control->pause_filter_count != old) {
 849                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 850                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 851                                             control->pause_filter_count, old);
 852         }
 853 }
 854
 855 /*
 856  * The default MMIO mask is a single bit (excluding the present bit),
 857  * which could conflict with the memory encryption bit. Check for
 858  * memory encryption support and override the default MMIO mask if
 859  * memory encryption is enabled.
 860  */
 861 static __init void svm_adjust_mmio_mask(void)
 862 {
 863         unsigned int enc_bit, mask_bit;
 864         u64 msr, mask;
 865
 866         /* If there is no memory encryption support, use existing mask */
 867         if (cpuid_eax(0x80000000) < 0x8000001f)
 868                 return;
 869
 870         /* If memory encryption is not enabled, use existing mask */
 871         rdmsrl(MSR_K8_SYSCFG, msr);
 872         if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 873                 return;
 874
 875         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 876         mask_bit = boot_cpu_data.x86_phys_bits;
 877
 878         /* Increment the mask bit if it is the same as the encryption bit */
 879         if (enc_bit == mask_bit)
 880                 mask_bit++;
 881
 882         /*
 883          * If the mask bit location is below 52, then some bits above the
 884          * physical addressing limit will always be reserved, so use the
 885          * rsvd_bits() function to generate the mask. This mask, along with
 886          * the present bit, will be used to generate a page fault with
 887          * PFER.RSV = 1.
 888          *
 889          * If the mask bit location is 52 (or above), then clear the mask.
 890          */
 891         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 892
 893         kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
 894 }
 895
 896 static void svm_hardware_teardown(void)
 897 {
 898         int cpu;
 899
 900         if (svm_sev_enabled())
 901                 sev_hardware_teardown();
 902
 903         for_each_possible_cpu(cpu)
 904                 svm_cpu_uninit(cpu);
 905
 906         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT),
 907         get_order(IOPM_SIZE));
 908         iopm_base = 0;
 909 }
 910
 911 static __init void svm_set_cpu_caps(void)
 912 {
 913         kvm_set_cpu_caps();
 914
 915         supported_xss = 0;
 916
 917         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 918         if (nested) {
 919                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 920
 921                 if (nrips)
 922                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 923
 924                 if (npt_enabled)
 925                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 926
 927                 /* Nested VM can receive #VMEXIT instead of triggering #GP */
 928                 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
 929         }
 930
 931         /* CPUID 0x80000008 */
 932         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 933             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 934                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 935 }
 936
 937 static __init int svm_hardware_setup(void)
 938 {
 939         int cpu;
 940         struct page *iopm_pages;
 941         void *iopm_va;
 942         int r;
 943         unsigned int order = get_order(IOPM_SIZE);
 944
 945         iopm_pages = alloc_pages(GFP_KERNEL, order);
 946
 947         if (!iopm_pages)
 948                 return -ENOMEM;
 949
 950         iopm_va = page_address(iopm_pages);
 951         memset(iopm_va, 0xff, PAGE_SIZE * (1 << order));
 952         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 953
 954         init_msrpm_offsets();
 955
 956         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 957
 958         if (boot_cpu_has(X86_FEATURE_NX))
 959                 kvm_enable_efer_bits(EFER_NX);
 960
 961         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 962                 kvm_enable_efer_bits(EFER_FFXSR);
 963
 964         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 965                 kvm_has_tsc_control = true;
 966                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 967                 kvm_tsc_scaling_ratio_frac_bits = 32;
 968         }
 969
 970         if (boot_cpu_has(X86_FEATURE_RDTSCP))
 971                 kvm_define_user_return_msr(TSC_AUX_URET_SLOT, MSR_TSC_AUX);
 972
 973         /* Check for pause filtering support */
 974         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 975                 pause_filter_count = 0;
 976                 pause_filter_thresh = 0;
 977         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 978                 pause_filter_thresh = 0;
 979         }
 980
 981         if (nested) {
 982                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 983                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 984         }
 985
 986         if (IS_ENABLED(CONFIG_KVM_AMD_SEV) && sev) {
 987                 sev_hardware_setup();
 988         } else {
 989                 sev = false;
 990                 sev_es = false;
 991         }
 992
 993         svm_adjust_mmio_mask();
 994
 995         for_each_possible_cpu(cpu) {
 996                 r = svm_cpu_init(cpu);
 997                 if (r)
 998                         goto err;
 999         }
1000
1001         /*
1002          * KVM's MMU doesn't support using 2-level paging for itself, and thus
1003          * NPT isn't supported if the host is using 2-level paging since host
1004          * CR4 is unchanged on VMRUN.
1005          */
1006         if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
1007                 npt_enabled = false;
1008
1009         if (!boot_cpu_has(X86_FEATURE_NPT))
1010                 npt_enabled = false;
1011
1012         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
1013         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
1014
1015         if (nrips) {
1016                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1017                         nrips = false;
1018         }
1019
1020         if (avic) {
1021                 if (!npt_enabled ||
1022                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1023                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1024                         avic = false;
1025                 } else {
1026                         pr_info("AVIC enabled\n");
1027
1028                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1029                 }
1030         }
1031
1032         if (vls) {
1033                 if (!npt_enabled ||
1034                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1035                     !IS_ENABLED(CONFIG_X86_64)) {
1036                         vls = false;
1037                 } else {
1038                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1039                 }
1040         }
1041
1042         if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
1043                 svm_gp_erratum_intercept = false;
1044
1045         if (vgif) {
1046                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1047                         vgif = false;
1048                 else
1049                         pr_info("Virtual GIF supported\n");
1050         }
1051
1052         svm_set_cpu_caps();
1053
1054         /*
1055          * It seems that on AMD processors PTE's accessed bit is
1056          * being set by the CPU hardware before the NPF vmexit.
1057          * This is not expected behaviour and our tests fail because
1058          * of it.
1059          * A workaround here is to disable support for
1060          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1061          * In this case userspace can know if there is support using
1062          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1063          * it
1064          * If future AMD CPU models change the behaviour described above,
1065          * this variable can be changed accordingly
1066          */
1067         allow_smaller_maxphyaddr = !npt_enabled;
1068
1069         return 0;
1070
1071 err:
1072         svm_hardware_teardown();
1073         return r;
1074 }
1075
1076 static void init_seg(struct vmcb_seg *seg)
1077 {
1078         seg->selector = 0;
1079         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1080                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1081         seg->limit = 0xffff;
1082         seg->base = 0;
1083 }
1084
1085 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1086 {
1087         seg->selector = 0;
1088         seg->attrib = SVM_SELECTOR_P_MASK | type;
1089         seg->limit = 0xffff;
1090         seg->base = 0;
1091 }
1092
1093 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1094 {
1095         struct vcpu_svm *svm = to_svm(vcpu);
1096         u64 g_tsc_offset = 0;
1097
1098         if (is_guest_mode(vcpu)) {
1099                 /* Write L1's TSC offset.  */
1100                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1101                                svm->vmcb01.ptr->control.tsc_offset;
1102                 svm->vmcb01.ptr->control.tsc_offset = offset;
1103         }
1104
1105         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1106                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1107                                    offset);
1108
1109         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1110
1111         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1112         return svm->vmcb->control.tsc_offset;
1113 }
1114
1115 static void svm_check_invpcid(struct vcpu_svm *svm)
1116 {
1117         /*
1118          * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1119          * roots, or if INVPCID is disabled in the guest to inject #UD.
1120          */
1121         if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1122                 if (!npt_enabled ||
1123                     !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1124                         svm_set_intercept(svm, INTERCEPT_INVPCID);
1125                 else
1126                         svm_clr_intercept(svm, INTERCEPT_INVPCID);
1127         }
1128 }
1129
1130 static void init_vmcb(struct kvm_vcpu *vcpu)
1131 {
1132         struct vcpu_svm *svm = to_svm(vcpu);
1133         struct vmcb_control_area *control = &svm->vmcb->control;
1134         struct vmcb_save_area *save = &svm->vmcb->save;
1135
1136         vcpu->arch.hflags = 0;
1137
1138         svm_set_intercept(svm, INTERCEPT_CR0_READ);
1139         svm_set_intercept(svm, INTERCEPT_CR3_READ);
1140         svm_set_intercept(svm, INTERCEPT_CR4_READ);
1141         svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1142         svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1143         svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1144         if (!kvm_vcpu_apicv_active(vcpu))
1145                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1146
1147         set_dr_intercepts(svm);
1148
1149         set_exception_intercept(svm, PF_VECTOR);
1150         set_exception_intercept(svm, UD_VECTOR);
1151         set_exception_intercept(svm, MC_VECTOR);
1152         set_exception_intercept(svm, AC_VECTOR);
1153         set_exception_intercept(svm, DB_VECTOR);
1154         /*
1155          * Guest access to VMware backdoor ports could legitimately
1156          * trigger #GP because of TSS I/O permission bitmap.
1157          * We intercept those #GP and allow access to them anyway
1158          * as VMware does.
1159          */
1160         if (enable_vmware_backdoor)
1161                 set_exception_intercept(svm, GP_VECTOR);
1162
1163         svm_set_intercept(svm, INTERCEPT_INTR);
1164         svm_set_intercept(svm, INTERCEPT_NMI);
1165         svm_set_intercept(svm, INTERCEPT_SMI);
1166         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1167         svm_set_intercept(svm, INTERCEPT_RDPMC);
1168         svm_set_intercept(svm, INTERCEPT_CPUID);
1169         svm_set_intercept(svm, INTERCEPT_INVD);
1170         svm_set_intercept(svm, INTERCEPT_INVLPG);
1171         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1172         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1173         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1174         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1175         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1176         svm_set_intercept(svm, INTERCEPT_VMRUN);
1177         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1178         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1179         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1180         svm_set_intercept(svm, INTERCEPT_STGI);
1181         svm_set_intercept(svm, INTERCEPT_CLGI);
1182         svm_set_intercept(svm, INTERCEPT_SKINIT);
1183         svm_set_intercept(svm, INTERCEPT_WBINVD);
1184         svm_set_intercept(svm, INTERCEPT_XSETBV);
1185         svm_set_intercept(svm, INTERCEPT_RDPRU);
1186         svm_set_intercept(svm, INTERCEPT_RSM);
1187
1188         if (!kvm_mwait_in_guest(vcpu->kvm)) {
1189                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1190                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1191         }
1192
1193         if (!kvm_hlt_in_guest(vcpu->kvm))
1194                 svm_set_intercept(svm, INTERCEPT_HLT);
1195
1196         control->iopm_base_pa = __sme_set(iopm_base);
1197         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1198         control->int_ctl = V_INTR_MASKING_MASK;
1199
1200         init_seg(&save->es);
1201         init_seg(&save->ss);
1202         init_seg(&save->ds);
1203         init_seg(&save->fs);
1204         init_seg(&save->gs);
1205
1206         save->cs.selector = 0xf000;
1207         save->cs.base = 0xffff0000;
1208         /* Executable/Readable Code Segment */
1209         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1210                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1211         save->cs.limit = 0xffff;
1212
1213         save->gdtr.limit = 0xffff;
1214         save->idtr.limit = 0xffff;
1215
1216         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1217         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1218
1219         svm_set_cr4(vcpu, 0);
1220         svm_set_efer(vcpu, 0);
1221         save->dr6 = 0xffff0ff0;
1222         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
1223         save->rip = 0x0000fff0;
1224         vcpu->arch.regs[VCPU_REGS_RIP] = save->rip;
1225
1226         /*
1227          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1228          * It also updates the guest-visible cr0 value.
1229          */
1230         svm_set_cr0(vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1231         kvm_mmu_reset_context(vcpu);
1232
1233         save->cr4 = X86_CR4_PAE;
1234         /* rdx = ?? */
1235
1236         if (npt_enabled) {
1237                 /* Setup VMCB for Nested Paging */
1238                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1239                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1240                 clr_exception_intercept(svm, PF_VECTOR);
1241                 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1242                 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1243                 save->g_pat = vcpu->arch.pat;
1244                 save->cr3 = 0;
1245                 save->cr4 = 0;
1246         }
1247         svm->current_vmcb->asid_generation = 0;
1248         svm->asid = 0;
1249
1250         svm->nested.vmcb12_gpa = 0;
1251         svm->nested.last_vmcb12_gpa = 0;
1252         vcpu->arch.hflags = 0;
1253
1254         if (!kvm_pause_in_guest(vcpu->kvm)) {
1255                 control->pause_filter_count = pause_filter_count;
1256                 if (pause_filter_thresh)
1257                         control->pause_filter_thresh = pause_filter_thresh;
1258                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1259         } else {
1260                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1261         }
1262
1263         svm_check_invpcid(svm);
1264
1265         /*
1266          * If the host supports V_SPEC_CTRL then disable the interception
1267          * of MSR_IA32_SPEC_CTRL.
1268          */
1269         if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
1270                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
1271
1272         if (kvm_vcpu_apicv_active(vcpu))
1273                 avic_init_vmcb(svm);
1274
1275         if (vgif) {
1276                 svm_clr_intercept(svm, INTERCEPT_STGI);
1277                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1278                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1279         }
1280
1281         if (sev_guest(vcpu->kvm)) {
1282                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1283                 clr_exception_intercept(svm, UD_VECTOR);
1284
1285                 if (sev_es_guest(vcpu->kvm)) {
1286                         /* Perform SEV-ES specific VMCB updates */
1287                         sev_es_init_vmcb(svm);
1288                 }
1289         }
1290
1291         vmcb_mark_all_dirty(svm->vmcb);
1292
1293         enable_gif(svm);
1294
1295 }
1296
1297 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1298 {
1299         struct vcpu_svm *svm = to_svm(vcpu);
1300         u32 dummy;
1301         u32 eax = 1;
1302
1303         svm->spec_ctrl = 0;
1304         svm->virt_spec_ctrl = 0;
1305
1306         if (!init_event) {
1307                 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1308                                        MSR_IA32_APICBASE_ENABLE;
1309                 if (kvm_vcpu_is_reset_bsp(vcpu))
1310                         vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
1311         }
1312         init_vmcb(vcpu);
1313
1314         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1315         kvm_rdx_write(vcpu, eax);
1316
1317         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1318                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1319 }
1320
1321 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb)
1322 {
1323         svm->current_vmcb = target_vmcb;
1324         svm->vmcb = target_vmcb->ptr;
1325 }
1326
1327 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1328 {
1329         struct vcpu_svm *svm;
1330         struct page *vmcb01_page;
1331         struct page *vmsa_page = NULL;
1332         int err;
1333
1334         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1335         svm = to_svm(vcpu);
1336
1337         err = -ENOMEM;
1338         vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1339         if (!vmcb01_page)
1340                 goto out;
1341
1342         if (sev_es_guest(vcpu->kvm)) {
1343                 /*
1344                  * SEV-ES guests require a separate VMSA page used to contain
1345                  * the encrypted register state of the guest.
1346                  */
1347                 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1348                 if (!vmsa_page)
1349                         goto error_free_vmcb_page;
1350
1351                 /*
1352                  * SEV-ES guests maintain an encrypted version of their FPU
1353                  * state which is restored and saved on VMRUN and VMEXIT.
1354                  * Free the fpu structure to prevent KVM from attempting to
1355                  * access the FPU state.
1356                  */
1357                 kvm_free_guest_fpu(vcpu);
1358         }
1359
1360         err = avic_init_vcpu(svm);
1361         if (err)
1362                 goto error_free_vmsa_page;
1363
1364         /* We initialize this flag to true to make sure that the is_running
1365          * bit would be set the first time the vcpu is loaded.
1366          */
1367         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1368                 svm->avic_is_running = true;
1369
1370         svm->msrpm = svm_vcpu_alloc_msrpm();
1371         if (!svm->msrpm) {
1372                 err = -ENOMEM;
1373                 goto error_free_vmsa_page;
1374         }
1375
1376         svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1377
1378         svm->vmcb01.ptr = page_address(vmcb01_page);
1379         svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT);
1380
1381         if (vmsa_page)
1382                 svm->vmsa = page_address(vmsa_page);
1383
1384         svm->guest_state_loaded = false;
1385
1386         svm_switch_vmcb(svm, &svm->vmcb01);
1387         init_vmcb(vcpu);
1388
1389         svm_init_osvw(vcpu);
1390         vcpu->arch.microcode_version = 0x01000065;
1391
1392         if (sev_es_guest(vcpu->kvm))
1393                 /* Perform SEV-ES specific VMCB creation updates */
1394                 sev_es_create_vcpu(svm);
1395
1396         return 0;
1397
1398 error_free_vmsa_page:
1399         if (vmsa_page)
1400                 __free_page(vmsa_page);
1401 error_free_vmcb_page:
1402         __free_page(vmcb01_page);
1403 out:
1404         return err;
1405 }
1406
1407 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1408 {
1409         int i;
1410
1411         for_each_online_cpu(i)
1412                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1413 }
1414
1415 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1416 {
1417         struct vcpu_svm *svm = to_svm(vcpu);
1418
1419         /*
1420          * The vmcb page can be recycled, causing a false negative in
1421          * svm_vcpu_load(). So, ensure that no logical CPU has this
1422          * vmcb page recorded as its current vmcb.
1423          */
1424         svm_clear_current_vmcb(svm->vmcb);
1425
1426         svm_free_nested(svm);
1427
1428         sev_free_vcpu(vcpu);
1429
1430         __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT));
1431         __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE));
1432 }
1433
1434 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1435 {
1436         struct vcpu_svm *svm = to_svm(vcpu);
1437         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1438
1439         if (svm->guest_state_loaded)
1440                 return;
1441
1442         /*
1443          * Save additional host state that will be restored on VMEXIT (sev-es)
1444          * or subsequent vmload of host save area.
1445          */
1446         if (sev_es_guest(vcpu->kvm)) {
1447                 sev_es_prepare_guest_switch(svm, vcpu->cpu);
1448         } else {
1449                 vmsave(__sme_page_pa(sd->save_area));
1450         }
1451
1452         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1453                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1454                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1455                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1456                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1457                 }
1458         }
1459
1460         if (static_cpu_has(X86_FEATURE_RDTSCP))
1461                 kvm_set_user_return_msr(TSC_AUX_URET_SLOT, svm->tsc_aux, -1ull);
1462
1463         svm->guest_state_loaded = true;
1464 }
1465
1466 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1467 {
1468         to_svm(vcpu)->guest_state_loaded = false;
1469 }
1470
1471 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1472 {
1473         struct vcpu_svm *svm = to_svm(vcpu);
1474         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1475
1476         if (sd->current_vmcb != svm->vmcb) {
1477                 sd->current_vmcb = svm->vmcb;
1478                 indirect_branch_prediction_barrier();
1479         }
1480         avic_vcpu_load(vcpu, cpu);
1481 }
1482
1483 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1484 {
1485         avic_vcpu_put(vcpu);
1486         svm_prepare_host_switch(vcpu);
1487
1488         ++vcpu->stat.host_state_reload;
1489 }
1490
1491 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1492 {
1493         struct vcpu_svm *svm = to_svm(vcpu);
1494         unsigned long rflags = svm->vmcb->save.rflags;
1495
1496         if (svm->nmi_singlestep) {
1497                 /* Hide our flags if they were not set by the guest */
1498                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1499                         rflags &= ~X86_EFLAGS_TF;
1500                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1501                         rflags &= ~X86_EFLAGS_RF;
1502         }
1503         return rflags;
1504 }
1505
1506 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1507 {
1508         if (to_svm(vcpu)->nmi_singlestep)
1509                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1510
1511        /*
1512         * Any change of EFLAGS.VM is accompanied by a reload of SS
1513         * (caused by either a task switch or an inter-privilege IRET),
1514         * so we do not need to update the CPL here.
1515         */
1516         to_svm(vcpu)->vmcb->save.rflags = rflags;
1517 }
1518
1519 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1520 {
1521         switch (reg) {
1522         case VCPU_EXREG_PDPTR:
1523                 BUG_ON(!npt_enabled);
1524                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1525                 break;
1526         default:
1527                 WARN_ON_ONCE(1);
1528         }
1529 }
1530
1531 static void svm_set_vintr(struct vcpu_svm *svm)
1532 {
1533         struct vmcb_control_area *control;
1534
1535         /* The following fields are ignored when AVIC is enabled */
1536         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1537         svm_set_intercept(svm, INTERCEPT_VINTR);
1538
1539         /*
1540          * This is just a dummy VINTR to actually cause a vmexit to happen.
1541          * Actual injection of virtual interrupts happens through EVENTINJ.
1542          */
1543         control = &svm->vmcb->control;
1544         control->int_vector = 0x0;
1545         control->int_ctl &= ~V_INTR_PRIO_MASK;
1546         control->int_ctl |= V_IRQ_MASK |
1547                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1548         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1549 }
1550
1551 static void svm_clear_vintr(struct vcpu_svm *svm)
1552 {
1553         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1554         svm_clr_intercept(svm, INTERCEPT_VINTR);
1555
1556         /* Drop int_ctl fields related to VINTR injection.  */
1557         svm->vmcb->control.int_ctl &= mask;
1558         if (is_guest_mode(&svm->vcpu)) {
1559                 svm->vmcb01.ptr->control.int_ctl &= mask;
1560
1561                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1562                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1563                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1564         }
1565
1566         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1567 }
1568
1569 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1570 {
1571         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1572         struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save;
1573
1574         switch (seg) {
1575         case VCPU_SREG_CS: return &save->cs;
1576         case VCPU_SREG_DS: return &save->ds;
1577         case VCPU_SREG_ES: return &save->es;
1578         case VCPU_SREG_FS: return &save01->fs;
1579         case VCPU_SREG_GS: return &save01->gs;
1580         case VCPU_SREG_SS: return &save->ss;
1581         case VCPU_SREG_TR: return &save01->tr;
1582         case VCPU_SREG_LDTR: return &save01->ldtr;
1583         }
1584         BUG();
1585         return NULL;
1586 }
1587
1588 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1589 {
1590         struct vmcb_seg *s = svm_seg(vcpu, seg);
1591
1592         return s->base;
1593 }
1594
1595 static void svm_get_segment(struct kvm_vcpu *vcpu,
1596                             struct kvm_segment *var, int seg)
1597 {
1598         struct vmcb_seg *s = svm_seg(vcpu, seg);
1599
1600         var->base = s->base;
1601         var->limit = s->limit;
1602         var->selector = s->selector;
1603         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1604         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1605         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1606         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1607         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1608         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1609         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1610
1611         /*
1612          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1613          * However, the SVM spec states that the G bit is not observed by the
1614          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1615          * So let's synthesize a legal G bit for all segments, this helps
1616          * running KVM nested. It also helps cross-vendor migration, because
1617          * Intel's vmentry has a check on the 'G' bit.
1618          */
1619         var->g = s->limit > 0xfffff;
1620
1621         /*
1622          * AMD's VMCB does not have an explicit unusable field, so emulate it
1623          * for cross vendor migration purposes by "not present"
1624          */
1625         var->unusable = !var->present;
1626
1627         switch (seg) {
1628         case VCPU_SREG_TR:
1629                 /*
1630                  * Work around a bug where the busy flag in the tr selector
1631                  * isn't exposed
1632                  */
1633                 var->type |= 0x2;
1634                 break;
1635         case VCPU_SREG_DS:
1636         case VCPU_SREG_ES:
1637         case VCPU_SREG_FS:
1638         case VCPU_SREG_GS:
1639                 /*
1640                  * The accessed bit must always be set in the segment
1641                  * descriptor cache, although it can be cleared in the
1642                  * descriptor, the cached bit always remains at 1. Since
1643                  * Intel has a check on this, set it here to support
1644                  * cross-vendor migration.
1645                  */
1646                 if (!var->unusable)
1647                         var->type |= 0x1;
1648                 break;
1649         case VCPU_SREG_SS:
1650                 /*
1651                  * On AMD CPUs sometimes the DB bit in the segment
1652                  * descriptor is left as 1, although the whole segment has
1653                  * been made unusable. Clear it here to pass an Intel VMX
1654                  * entry check when cross vendor migrating.
1655                  */
1656                 if (var->unusable)
1657                         var->db = 0;
1658                 /* This is symmetric with svm_set_segment() */
1659                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1660                 break;
1661         }
1662 }
1663
1664 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1665 {
1666         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1667
1668         return save->cpl;
1669 }
1670
1671 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1672 {
1673         struct vcpu_svm *svm = to_svm(vcpu);
1674
1675         dt->size = svm->vmcb->save.idtr.limit;
1676         dt->address = svm->vmcb->save.idtr.base;
1677 }
1678
1679 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1680 {
1681         struct vcpu_svm *svm = to_svm(vcpu);
1682
1683         svm->vmcb->save.idtr.limit = dt->size;
1684         svm->vmcb->save.idtr.base = dt->address ;
1685         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1686 }
1687
1688 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1689 {
1690         struct vcpu_svm *svm = to_svm(vcpu);
1691
1692         dt->size = svm->vmcb->save.gdtr.limit;
1693         dt->address = svm->vmcb->save.gdtr.base;
1694 }
1695
1696 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1697 {
1698         struct vcpu_svm *svm = to_svm(vcpu);
1699
1700         svm->vmcb->save.gdtr.limit = dt->size;
1701         svm->vmcb->save.gdtr.base = dt->address ;
1702         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1703 }
1704
1705 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1706 {
1707         struct vcpu_svm *svm = to_svm(vcpu);
1708         u64 hcr0 = cr0;
1709
1710 #ifdef CONFIG_X86_64
1711         if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1712                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1713                         vcpu->arch.efer |= EFER_LMA;
1714                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1715                 }
1716
1717                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1718                         vcpu->arch.efer &= ~EFER_LMA;
1719                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1720                 }
1721         }
1722 #endif
1723         vcpu->arch.cr0 = cr0;
1724
1725         if (!npt_enabled)
1726                 hcr0 |= X86_CR0_PG | X86_CR0_WP;
1727
1728         /*
1729          * re-enable caching here because the QEMU bios
1730          * does not do it - this results in some delay at
1731          * reboot
1732          */
1733         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1734                 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1735
1736         svm->vmcb->save.cr0 = hcr0;
1737         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1738
1739         /*
1740          * SEV-ES guests must always keep the CR intercepts cleared. CR
1741          * tracking is done using the CR write traps.
1742          */
1743         if (sev_es_guest(vcpu->kvm))
1744                 return;
1745
1746         if (hcr0 == cr0) {
1747                 /* Selective CR0 write remains on.  */
1748                 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1749                 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1750         } else {
1751                 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1752                 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1753         }
1754 }
1755
1756 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1757 {
1758         return true;
1759 }
1760
1761 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1762 {
1763         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1764         unsigned long old_cr4 = vcpu->arch.cr4;
1765
1766         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1767                 svm_flush_tlb(vcpu);
1768
1769         vcpu->arch.cr4 = cr4;
1770         if (!npt_enabled)
1771                 cr4 |= X86_CR4_PAE;
1772         cr4 |= host_cr4_mce;
1773         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1774         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1775
1776         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1777                 kvm_update_cpuid_runtime(vcpu);
1778 }
1779
1780 static void svm_set_segment(struct kvm_vcpu *vcpu,
1781                             struct kvm_segment *var, int seg)
1782 {
1783         struct vcpu_svm *svm = to_svm(vcpu);
1784         struct vmcb_seg *s = svm_seg(vcpu, seg);
1785
1786         s->base = var->base;
1787         s->limit = var->limit;
1788         s->selector = var->selector;
1789         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1790         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1791         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1792         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1793         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1794         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1795         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1796         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1797
1798         /*
1799          * This is always accurate, except if SYSRET returned to a segment
1800          * with SS.DPL != 3.  Intel does not have this quirk, and always
1801          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1802          * would entail passing the CPL to userspace and back.
1803          */
1804         if (seg == VCPU_SREG_SS)
1805                 /* This is symmetric with svm_get_segment() */
1806                 svm->vmcb->save.cpl = (var->dpl & 3);
1807
1808         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1809 }
1810
1811 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1812 {
1813         struct vcpu_svm *svm = to_svm(vcpu);
1814
1815         clr_exception_intercept(svm, BP_VECTOR);
1816
1817         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1818                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1819                         set_exception_intercept(svm, BP_VECTOR);
1820         }
1821 }
1822
1823 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1824 {
1825         if (sd->next_asid > sd->max_asid) {
1826                 ++sd->asid_generation;
1827                 sd->next_asid = sd->min_asid;
1828                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1829                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1830         }
1831
1832         svm->current_vmcb->asid_generation = sd->asid_generation;
1833         svm->asid = sd->next_asid++;
1834 }
1835
1836 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1837 {
1838         struct vmcb *vmcb = svm->vmcb;
1839
1840         if (svm->vcpu.arch.guest_state_protected)
1841                 return;
1842
1843         if (unlikely(value != vmcb->save.dr6)) {
1844                 vmcb->save.dr6 = value;
1845                 vmcb_mark_dirty(vmcb, VMCB_DR);
1846         }
1847 }
1848
1849 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1850 {
1851         struct vcpu_svm *svm = to_svm(vcpu);
1852
1853         if (vcpu->arch.guest_state_protected)
1854                 return;
1855
1856         get_debugreg(vcpu->arch.db[0], 0);
1857         get_debugreg(vcpu->arch.db[1], 1);
1858         get_debugreg(vcpu->arch.db[2], 2);
1859         get_debugreg(vcpu->arch.db[3], 3);
1860         /*
1861          * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1862          * because db_interception might need it.  We can do it before vmentry.
1863          */
1864         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1865         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1866         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1867         set_dr_intercepts(svm);
1868 }
1869
1870 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1871 {
1872         struct vcpu_svm *svm = to_svm(vcpu);
1873
1874         if (vcpu->arch.guest_state_protected)
1875                 return;
1876
1877         svm->vmcb->save.dr7 = value;
1878         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1879 }
1880
1881 static int pf_interception(struct kvm_vcpu *vcpu)
1882 {
1883         struct vcpu_svm *svm = to_svm(vcpu);
1884
1885         u64 fault_address = svm->vmcb->control.exit_info_2;
1886         u64 error_code = svm->vmcb->control.exit_info_1;
1887
1888         return kvm_handle_page_fault(vcpu, error_code, fault_address,
1889                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1890                         svm->vmcb->control.insn_bytes : NULL,
1891                         svm->vmcb->control.insn_len);
1892 }
1893
1894 static int npf_interception(struct kvm_vcpu *vcpu)
1895 {
1896         struct vcpu_svm *svm = to_svm(vcpu);
1897
1898         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1899         u64 error_code = svm->vmcb->control.exit_info_1;
1900
1901         trace_kvm_page_fault(fault_address, error_code);
1902         return kvm_mmu_page_fault(vcpu, fault_address, error_code,
1903                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1904                         svm->vmcb->control.insn_bytes : NULL,
1905                         svm->vmcb->control.insn_len);
1906 }
1907
1908 static int db_interception(struct kvm_vcpu *vcpu)
1909 {
1910         struct kvm_run *kvm_run = vcpu->run;
1911         struct vcpu_svm *svm = to_svm(vcpu);
1912
1913         if (!(vcpu->guest_debug &
1914               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1915                 !svm->nmi_singlestep) {
1916                 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
1917                 kvm_queue_exception_p(vcpu, DB_VECTOR, payload);
1918                 return 1;
1919         }
1920
1921         if (svm->nmi_singlestep) {
1922                 disable_nmi_singlestep(svm);
1923                 /* Make sure we check for pending NMIs upon entry */
1924                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1925         }
1926
1927         if (vcpu->guest_debug &
1928             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1929                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1930                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1931                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1932                 kvm_run->debug.arch.pc =
1933                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1934                 kvm_run->debug.arch.exception = DB_VECTOR;
1935                 return 0;
1936         }
1937
1938         return 1;
1939 }
1940
1941 static int bp_interception(struct kvm_vcpu *vcpu)
1942 {
1943         struct vcpu_svm *svm = to_svm(vcpu);
1944         struct kvm_run *kvm_run = vcpu->run;
1945
1946         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1947         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1948         kvm_run->debug.arch.exception = BP_VECTOR;
1949         return 0;
1950 }
1951
1952 static int ud_interception(struct kvm_vcpu *vcpu)
1953 {
1954         return handle_ud(vcpu);
1955 }
1956
1957 static int ac_interception(struct kvm_vcpu *vcpu)
1958 {
1959         kvm_queue_exception_e(vcpu, AC_VECTOR, 0);
1960         return 1;
1961 }
1962
1963 static bool is_erratum_383(void)
1964 {
1965         int err, i;
1966         u64 value;
1967
1968         if (!erratum_383_found)
1969                 return false;
1970
1971         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1972         if (err)
1973                 return false;
1974
1975         /* Bit 62 may or may not be set for this mce */
1976         value &= ~(1ULL << 62);
1977
1978         if (value != 0xb600000000010015ULL)
1979                 return false;
1980
1981         /* Clear MCi_STATUS registers */
1982         for (i = 0; i < 6; ++i)
1983                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1984
1985         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1986         if (!err) {
1987                 u32 low, high;
1988
1989                 value &= ~(1ULL << 2);
1990                 low    = lower_32_bits(value);
1991                 high   = upper_32_bits(value);
1992
1993                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1994         }
1995
1996         /* Flush tlb to evict multi-match entries */
1997         __flush_tlb_all();
1998
1999         return true;
2000 }
2001
2002 static void svm_handle_mce(struct kvm_vcpu *vcpu)
2003 {
2004         if (is_erratum_383()) {
2005                 /*
2006                  * Erratum 383 triggered. Guest state is corrupt so kill the
2007                  * guest.
2008                  */
2009                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2010
2011                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2012
2013                 return;
2014         }
2015
2016         /*
2017          * On an #MC intercept the MCE handler is not called automatically in
2018          * the host. So do it by hand here.
2019          */
2020         kvm_machine_check();
2021 }
2022
2023 static int mc_interception(struct kvm_vcpu *vcpu)
2024 {
2025         return 1;
2026 }
2027
2028 static int shutdown_interception(struct kvm_vcpu *vcpu)
2029 {
2030         struct kvm_run *kvm_run = vcpu->run;
2031         struct vcpu_svm *svm = to_svm(vcpu);
2032
2033         /*
2034          * The VM save area has already been encrypted so it
2035          * cannot be reinitialized - just terminate.
2036          */
2037         if (sev_es_guest(vcpu->kvm))
2038                 return -EINVAL;
2039
2040         /*
2041          * VMCB is undefined after a SHUTDOWN intercept
2042          * so reinitialize it.
2043          */
2044         clear_page(svm->vmcb);
2045         init_vmcb(vcpu);
2046
2047         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2048         return 0;
2049 }
2050
2051 static int io_interception(struct kvm_vcpu *vcpu)
2052 {
2053         struct vcpu_svm *svm = to_svm(vcpu);
2054         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2055         int size, in, string;
2056         unsigned port;
2057
2058         ++vcpu->stat.io_exits;
2059         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2060         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2061         port = io_info >> 16;
2062         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2063
2064         if (string) {
2065                 if (sev_es_guest(vcpu->kvm))
2066                         return sev_es_string_io(svm, size, port, in);
2067                 else
2068                         return kvm_emulate_instruction(vcpu, 0);
2069         }
2070
2071         svm->next_rip = svm->vmcb->control.exit_info_2;
2072
2073         return kvm_fast_pio(vcpu, size, port, in);
2074 }
2075
2076 static int nmi_interception(struct kvm_vcpu *vcpu)
2077 {
2078         return 1;
2079 }
2080
2081 static int intr_interception(struct kvm_vcpu *vcpu)
2082 {
2083         ++vcpu->stat.irq_exits;
2084         return 1;
2085 }
2086
2087 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload)
2088 {
2089         struct vcpu_svm *svm = to_svm(vcpu);
2090         struct vmcb *vmcb12;
2091         struct kvm_host_map map;
2092         int ret;
2093
2094         if (nested_svm_check_permissions(vcpu))
2095                 return 1;
2096
2097         ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2098         if (ret) {
2099                 if (ret == -EINVAL)
2100                         kvm_inject_gp(vcpu, 0);
2101                 return 1;
2102         }
2103
2104         vmcb12 = map.hva;
2105
2106         ret = kvm_skip_emulated_instruction(vcpu);
2107
2108         if (vmload) {
2109                 nested_svm_vmloadsave(vmcb12, svm->vmcb);
2110                 svm->sysenter_eip_hi = 0;
2111                 svm->sysenter_esp_hi = 0;
2112         } else
2113                 nested_svm_vmloadsave(svm->vmcb, vmcb12);
2114
2115         kvm_vcpu_unmap(vcpu, &map, true);
2116
2117         return ret;
2118 }
2119
2120 static int vmload_interception(struct kvm_vcpu *vcpu)
2121 {
2122         return vmload_vmsave_interception(vcpu, true);
2123 }
2124
2125 static int vmsave_interception(struct kvm_vcpu *vcpu)
2126 {
2127         return vmload_vmsave_interception(vcpu, false);
2128 }
2129
2130 static int vmrun_interception(struct kvm_vcpu *vcpu)
2131 {
2132         if (nested_svm_check_permissions(vcpu))
2133                 return 1;
2134
2135         return nested_svm_vmrun(vcpu);
2136 }
2137
2138 enum {
2139         NONE_SVM_INSTR,
2140         SVM_INSTR_VMRUN,
2141         SVM_INSTR_VMLOAD,
2142         SVM_INSTR_VMSAVE,
2143 };
2144
2145 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2146 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2147 {
2148         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2149
2150         if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2151                 return NONE_SVM_INSTR;
2152
2153         switch (ctxt->modrm) {
2154         case 0xd8: /* VMRUN */
2155                 return SVM_INSTR_VMRUN;
2156         case 0xda: /* VMLOAD */
2157                 return SVM_INSTR_VMLOAD;
2158         case 0xdb: /* VMSAVE */
2159                 return SVM_INSTR_VMSAVE;
2160         default:
2161                 break;
2162         }
2163
2164         return NONE_SVM_INSTR;
2165 }
2166
2167 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2168 {
2169         const int guest_mode_exit_codes[] = {
2170                 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2171                 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2172                 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2173         };
2174         int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = {
2175                 [SVM_INSTR_VMRUN] = vmrun_interception,
2176                 [SVM_INSTR_VMLOAD] = vmload_interception,
2177                 [SVM_INSTR_VMSAVE] = vmsave_interception,
2178         };
2179         struct vcpu_svm *svm = to_svm(vcpu);
2180         int ret;
2181
2182         if (is_guest_mode(vcpu)) {
2183                 /* Returns '1' or -errno on failure, '0' on success. */
2184                 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]);
2185                 if (ret)
2186                         return ret;
2187                 return 1;
2188         }
2189         return svm_instr_handlers[opcode](vcpu);
2190 }
2191
2192 /*
2193  * #GP handling code. Note that #GP can be triggered under the following two
2194  * cases:
2195  *   1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2196  *      some AMD CPUs when EAX of these instructions are in the reserved memory
2197  *      regions (e.g. SMM memory on host).
2198  *   2) VMware backdoor
2199  */
2200 static int gp_interception(struct kvm_vcpu *vcpu)
2201 {
2202         struct vcpu_svm *svm = to_svm(vcpu);
2203         u32 error_code = svm->vmcb->control.exit_info_1;
2204         int opcode;
2205
2206         /* Both #GP cases have zero error_code */
2207         if (error_code)
2208                 goto reinject;
2209
2210         /* Decode the instruction for usage later */
2211         if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2212                 goto reinject;
2213
2214         opcode = svm_instr_opcode(vcpu);
2215
2216         if (opcode == NONE_SVM_INSTR) {
2217                 if (!enable_vmware_backdoor)
2218                         goto reinject;
2219
2220                 /*
2221                  * VMware backdoor emulation on #GP interception only handles
2222                  * IN{S}, OUT{S}, and RDPMC.
2223                  */
2224                 if (!is_guest_mode(vcpu))
2225                         return kvm_emulate_instruction(vcpu,
2226                                 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2227         } else
2228                 return emulate_svm_instr(vcpu, opcode);
2229
2230 reinject:
2231         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2232         return 1;
2233 }
2234
2235 void svm_set_gif(struct vcpu_svm *svm, bool value)
2236 {
2237         if (value) {
2238                 /*
2239                  * If VGIF is enabled, the STGI intercept is only added to
2240                  * detect the opening of the SMI/NMI window; remove it now.
2241                  * Likewise, clear the VINTR intercept, we will set it
2242                  * again while processing KVM_REQ_EVENT if needed.
2243                  */
2244                 if (vgif_enabled(svm))
2245                         svm_clr_intercept(svm, INTERCEPT_STGI);
2246                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2247                         svm_clear_vintr(svm);
2248
2249                 enable_gif(svm);
2250                 if (svm->vcpu.arch.smi_pending ||
2251                     svm->vcpu.arch.nmi_pending ||
2252                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2253                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2254         } else {
2255                 disable_gif(svm);
2256
2257                 /*
2258                  * After a CLGI no interrupts should come.  But if vGIF is
2259                  * in use, we still rely on the VINTR intercept (rather than
2260                  * STGI) to detect an open interrupt window.
2261                 */
2262                 if (!vgif_enabled(svm))
2263                         svm_clear_vintr(svm);
2264         }
2265 }
2266
2267 static int stgi_interception(struct kvm_vcpu *vcpu)
2268 {
2269         int ret;
2270
2271         if (nested_svm_check_permissions(vcpu))
2272                 return 1;
2273
2274         ret = kvm_skip_emulated_instruction(vcpu);
2275         svm_set_gif(to_svm(vcpu), true);
2276         return ret;
2277 }
2278
2279 static int clgi_interception(struct kvm_vcpu *vcpu)
2280 {
2281         int ret;
2282
2283         if (nested_svm_check_permissions(vcpu))
2284                 return 1;
2285
2286         ret = kvm_skip_emulated_instruction(vcpu);
2287         svm_set_gif(to_svm(vcpu), false);
2288         return ret;
2289 }
2290
2291 static int invlpga_interception(struct kvm_vcpu *vcpu)
2292 {
2293         trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, kvm_rcx_read(vcpu),
2294                           kvm_rax_read(vcpu));
2295
2296         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2297         kvm_mmu_invlpg(vcpu, kvm_rax_read(vcpu));
2298
2299         return kvm_skip_emulated_instruction(vcpu);
2300 }
2301
2302 static int skinit_interception(struct kvm_vcpu *vcpu)
2303 {
2304         trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu));
2305
2306         kvm_queue_exception(vcpu, UD_VECTOR);
2307         return 1;
2308 }
2309
2310 static int task_switch_interception(struct kvm_vcpu *vcpu)
2311 {
2312         struct vcpu_svm *svm = to_svm(vcpu);
2313         u16 tss_selector;
2314         int reason;
2315         int int_type = svm->vmcb->control.exit_int_info &
2316                 SVM_EXITINTINFO_TYPE_MASK;
2317         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2318         uint32_t type =
2319                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2320         uint32_t idt_v =
2321                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2322         bool has_error_code = false;
2323         u32 error_code = 0;
2324
2325         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2326
2327         if (svm->vmcb->control.exit_info_2 &
2328             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2329                 reason = TASK_SWITCH_IRET;
2330         else if (svm->vmcb->control.exit_info_2 &
2331                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2332                 reason = TASK_SWITCH_JMP;
2333         else if (idt_v)
2334                 reason = TASK_SWITCH_GATE;
2335         else
2336                 reason = TASK_SWITCH_CALL;
2337
2338         if (reason == TASK_SWITCH_GATE) {
2339                 switch (type) {
2340                 case SVM_EXITINTINFO_TYPE_NMI:
2341                         vcpu->arch.nmi_injected = false;
2342                         break;
2343                 case SVM_EXITINTINFO_TYPE_EXEPT:
2344                         if (svm->vmcb->control.exit_info_2 &
2345                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2346                                 has_error_code = true;
2347                                 error_code =
2348                                         (u32)svm->vmcb->control.exit_info_2;
2349                         }
2350                         kvm_clear_exception_queue(vcpu);
2351                         break;
2352                 case SVM_EXITINTINFO_TYPE_INTR:
2353                         kvm_clear_interrupt_queue(vcpu);
2354                         break;
2355                 default:
2356                         break;
2357                 }
2358         }
2359
2360         if (reason != TASK_SWITCH_GATE ||
2361             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2362             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2363              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2364                 if (!skip_emulated_instruction(vcpu))
2365                         return 0;
2366         }
2367
2368         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2369                 int_vec = -1;
2370
2371         return kvm_task_switch(vcpu, tss_selector, int_vec, reason,
2372                                has_error_code, error_code);
2373 }
2374
2375 static int iret_interception(struct kvm_vcpu *vcpu)
2376 {
2377         struct vcpu_svm *svm = to_svm(vcpu);
2378
2379         ++vcpu->stat.nmi_window_exits;
2380         vcpu->arch.hflags |= HF_IRET_MASK;
2381         if (!sev_es_guest(vcpu->kvm)) {
2382                 svm_clr_intercept(svm, INTERCEPT_IRET);
2383                 svm->nmi_iret_rip = kvm_rip_read(vcpu);
2384         }
2385         kvm_make_request(KVM_REQ_EVENT, vcpu);
2386         return 1;
2387 }
2388
2389 static int invlpg_interception(struct kvm_vcpu *vcpu)
2390 {
2391         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2392                 return kvm_emulate_instruction(vcpu, 0);
2393
2394         kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
2395         return kvm_skip_emulated_instruction(vcpu);
2396 }
2397
2398 static int emulate_on_interception(struct kvm_vcpu *vcpu)
2399 {
2400         return kvm_emulate_instruction(vcpu, 0);
2401 }
2402
2403 static int rsm_interception(struct kvm_vcpu *vcpu)
2404 {
2405         return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2);
2406 }
2407
2408 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu,
2409                                             unsigned long val)
2410 {
2411         struct vcpu_svm *svm = to_svm(vcpu);
2412         unsigned long cr0 = vcpu->arch.cr0;
2413         bool ret = false;
2414
2415         if (!is_guest_mode(vcpu) ||
2416             (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2417                 return false;
2418
2419         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2420         val &= ~SVM_CR0_SELECTIVE_MASK;
2421
2422         if (cr0 ^ val) {
2423                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2424                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2425         }
2426
2427         return ret;
2428 }
2429
2430 #define CR_VALID (1ULL << 63)
2431
2432 static int cr_interception(struct kvm_vcpu *vcpu)
2433 {
2434         struct vcpu_svm *svm = to_svm(vcpu);
2435         int reg, cr;
2436         unsigned long val;
2437         int err;
2438
2439         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2440                 return emulate_on_interception(vcpu);
2441
2442         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2443                 return emulate_on_interception(vcpu);
2444
2445         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2446         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2447                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2448         else
2449                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2450
2451         err = 0;
2452         if (cr >= 16) { /* mov to cr */
2453                 cr -= 16;
2454                 val = kvm_register_read(vcpu, reg);
2455                 trace_kvm_cr_write(cr, val);
2456                 switch (cr) {
2457                 case 0:
2458                         if (!check_selective_cr0_intercepted(vcpu, val))
2459                                 err = kvm_set_cr0(vcpu, val);
2460                         else
2461                                 return 1;
2462
2463                         break;
2464                 case 3:
2465                         err = kvm_set_cr3(vcpu, val);
2466                         break;
2467                 case 4:
2468                         err = kvm_set_cr4(vcpu, val);
2469                         break;
2470                 case 8:
2471                         err = kvm_set_cr8(vcpu, val);
2472                         break;
2473                 default:
2474                         WARN(1, "unhandled write to CR%d", cr);
2475                         kvm_queue_exception(vcpu, UD_VECTOR);
2476                         return 1;
2477                 }
2478         } else { /* mov from cr */
2479                 switch (cr) {
2480                 case 0:
2481                         val = kvm_read_cr0(vcpu);
2482                         break;
2483                 case 2:
2484                         val = vcpu->arch.cr2;
2485                         break;
2486                 case 3:
2487                         val = kvm_read_cr3(vcpu);
2488                         break;
2489                 case 4:
2490                         val = kvm_read_cr4(vcpu);
2491                         break;
2492                 case 8:
2493                         val = kvm_get_cr8(vcpu);
2494                         break;
2495                 default:
2496                         WARN(1, "unhandled read from CR%d", cr);
2497                         kvm_queue_exception(vcpu, UD_VECTOR);
2498                         return 1;
2499                 }
2500                 kvm_register_write(vcpu, reg, val);
2501                 trace_kvm_cr_read(cr, val);
2502         }
2503         return kvm_complete_insn_gp(vcpu, err);
2504 }
2505
2506 static int cr_trap(struct kvm_vcpu *vcpu)
2507 {
2508         struct vcpu_svm *svm = to_svm(vcpu);
2509         unsigned long old_value, new_value;
2510         unsigned int cr;
2511         int ret = 0;
2512
2513         new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2514
2515         cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2516         switch (cr) {
2517         case 0:
2518                 old_value = kvm_read_cr0(vcpu);
2519                 svm_set_cr0(vcpu, new_value);
2520
2521                 kvm_post_set_cr0(vcpu, old_value, new_value);
2522                 break;
2523         case 4:
2524                 old_value = kvm_read_cr4(vcpu);
2525                 svm_set_cr4(vcpu, new_value);
2526
2527                 kvm_post_set_cr4(vcpu, old_value, new_value);
2528                 break;
2529         case 8:
2530                 ret = kvm_set_cr8(vcpu, new_value);
2531                 break;
2532         default:
2533                 WARN(1, "unhandled CR%d write trap", cr);
2534                 kvm_queue_exception(vcpu, UD_VECTOR);
2535                 return 1;
2536         }
2537
2538         return kvm_complete_insn_gp(vcpu, ret);
2539 }
2540
2541 static int dr_interception(struct kvm_vcpu *vcpu)
2542 {
2543         struct vcpu_svm *svm = to_svm(vcpu);
2544         int reg, dr;
2545         unsigned long val;
2546         int err = 0;
2547
2548         if (vcpu->guest_debug == 0) {
2549                 /*
2550                  * No more DR vmexits; force a reload of the debug registers
2551                  * and reenter on this instruction.  The next vmexit will
2552                  * retrieve the full state of the debug registers.
2553                  */
2554                 clr_dr_intercepts(svm);
2555                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2556                 return 1;
2557         }
2558
2559         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2560                 return emulate_on_interception(vcpu);
2561
2562         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2563         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2564         if (dr >= 16) { /* mov to DRn  */
2565                 dr -= 16;
2566                 val = kvm_register_read(vcpu, reg);
2567                 err = kvm_set_dr(vcpu, dr, val);
2568         } else {
2569                 kvm_get_dr(vcpu, dr, &val);
2570                 kvm_register_write(vcpu, reg, val);
2571         }
2572
2573         return kvm_complete_insn_gp(vcpu, err);
2574 }
2575
2576 static int cr8_write_interception(struct kvm_vcpu *vcpu)
2577 {
2578         int r;
2579
2580         u8 cr8_prev = kvm_get_cr8(vcpu);
2581         /* instruction emulation calls kvm_set_cr8() */
2582         r = cr_interception(vcpu);
2583         if (lapic_in_kernel(vcpu))
2584                 return r;
2585         if (cr8_prev <= kvm_get_cr8(vcpu))
2586                 return r;
2587         vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2588         return 0;
2589 }
2590
2591 static int efer_trap(struct kvm_vcpu *vcpu)
2592 {
2593         struct msr_data msr_info;
2594         int ret;
2595
2596         /*
2597          * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2598          * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2599          * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2600          * the guest doesn't have X86_FEATURE_SVM.
2601          */
2602         msr_info.host_initiated = false;
2603         msr_info.index = MSR_EFER;
2604         msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME;
2605         ret = kvm_set_msr_common(vcpu, &msr_info);
2606
2607         return kvm_complete_insn_gp(vcpu, ret);
2608 }
2609
2610 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2611 {
2612         msr->data = 0;
2613
2614         switch (msr->index) {
2615         case MSR_F10H_DECFG:
2616                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2617                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2618                 break;
2619         case MSR_IA32_PERF_CAPABILITIES:
2620                 return 0;
2621         default:
2622                 return KVM_MSR_RET_INVALID;
2623         }
2624
2625         return 0;
2626 }
2627
2628 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2629 {
2630         struct vcpu_svm *svm = to_svm(vcpu);
2631
2632         switch (msr_info->index) {
2633         case MSR_STAR:
2634                 msr_info->data = svm->vmcb01.ptr->save.star;
2635                 break;
2636 #ifdef CONFIG_X86_64
2637         case MSR_LSTAR:
2638                 msr_info->data = svm->vmcb01.ptr->save.lstar;
2639                 break;
2640         case MSR_CSTAR:
2641                 msr_info->data = svm->vmcb01.ptr->save.cstar;
2642                 break;
2643         case MSR_KERNEL_GS_BASE:
2644                 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2645                 break;
2646         case MSR_SYSCALL_MASK:
2647                 msr_info->data = svm->vmcb01.ptr->save.sfmask;
2648                 break;
2649 #endif
2650         case MSR_IA32_SYSENTER_CS:
2651                 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs;
2652                 break;
2653         case MSR_IA32_SYSENTER_EIP:
2654                 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip;
2655                 if (guest_cpuid_is_intel(vcpu))
2656                         msr_info->data |= (u64)svm->sysenter_eip_hi << 32;
2657                 break;
2658         case MSR_IA32_SYSENTER_ESP:
2659                 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp;
2660                 if (guest_cpuid_is_intel(vcpu))
2661                         msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
2662                 break;
2663         case MSR_TSC_AUX:
2664                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2665                         return 1;
2666                 if (!msr_info->host_initiated &&
2667                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2668                         return 1;
2669                 msr_info->data = svm->tsc_aux;
2670                 break;
2671         /*
2672          * Nobody will change the following 5 values in the VMCB so we can
2673          * safely return them on rdmsr. They will always be 0 until LBRV is
2674          * implemented.
2675          */
2676         case MSR_IA32_DEBUGCTLMSR:
2677                 msr_info->data = svm->vmcb->save.dbgctl;
2678                 break;
2679         case MSR_IA32_LASTBRANCHFROMIP:
2680                 msr_info->data = svm->vmcb->save.br_from;
2681                 break;
2682         case MSR_IA32_LASTBRANCHTOIP:
2683                 msr_info->data = svm->vmcb->save.br_to;
2684                 break;
2685         case MSR_IA32_LASTINTFROMIP:
2686                 msr_info->data = svm->vmcb->save.last_excp_from;
2687                 break;
2688         case MSR_IA32_LASTINTTOIP:
2689                 msr_info->data = svm->vmcb->save.last_excp_to;
2690                 break;
2691         case MSR_VM_HSAVE_PA:
2692                 msr_info->data = svm->nested.hsave_msr;
2693                 break;
2694         case MSR_VM_CR:
2695                 msr_info->data = svm->nested.vm_cr_msr;
2696                 break;
2697         case MSR_IA32_SPEC_CTRL:
2698                 if (!msr_info->host_initiated &&
2699                     !guest_has_spec_ctrl_msr(vcpu))
2700                         return 1;
2701
2702                 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2703                         msr_info->data = svm->vmcb->save.spec_ctrl;
2704                 else
2705                         msr_info->data = svm->spec_ctrl;
2706                 break;
2707         case MSR_AMD64_VIRT_SPEC_CTRL:
2708                 if (!msr_info->host_initiated &&
2709                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2710                         return 1;
2711
2712                 msr_info->data = svm->virt_spec_ctrl;
2713                 break;
2714         case MSR_F15H_IC_CFG: {
2715
2716                 int family, model;
2717
2718                 family = guest_cpuid_family(vcpu);
2719                 model  = guest_cpuid_model(vcpu);
2720
2721                 if (family < 0 || model < 0)
2722                         return kvm_get_msr_common(vcpu, msr_info);
2723
2724                 msr_info->data = 0;
2725
2726                 if (family == 0x15 &&
2727                     (model >= 0x2 && model < 0x20))
2728                         msr_info->data = 0x1E;
2729                 }
2730                 break;
2731         case MSR_F10H_DECFG:
2732                 msr_info->data = svm->msr_decfg;
2733                 break;
2734         default:
2735                 return kvm_get_msr_common(vcpu, msr_info);
2736         }
2737         return 0;
2738 }
2739
2740 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2741 {
2742         struct vcpu_svm *svm = to_svm(vcpu);
2743         if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->ghcb))
2744                 return kvm_complete_insn_gp(vcpu, err);
2745
2746         ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2747         ghcb_set_sw_exit_info_2(svm->ghcb,
2748                                 X86_TRAP_GP |
2749                                 SVM_EVTINJ_TYPE_EXEPT |
2750                                 SVM_EVTINJ_VALID);
2751         return 1;
2752 }
2753
2754 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2755 {
2756         struct vcpu_svm *svm = to_svm(vcpu);
2757         int svm_dis, chg_mask;
2758
2759         if (data & ~SVM_VM_CR_VALID_MASK)
2760                 return 1;
2761
2762         chg_mask = SVM_VM_CR_VALID_MASK;
2763
2764         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2765                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2766
2767         svm->nested.vm_cr_msr &= ~chg_mask;
2768         svm->nested.vm_cr_msr |= (data & chg_mask);
2769
2770         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2771
2772         /* check for svm_disable while efer.svme is set */
2773         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2774                 return 1;
2775
2776         return 0;
2777 }
2778
2779 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2780 {
2781         struct vcpu_svm *svm = to_svm(vcpu);
2782         int r;
2783
2784         u32 ecx = msr->index;
2785         u64 data = msr->data;
2786         switch (ecx) {
2787         case MSR_IA32_CR_PAT:
2788                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2789                         return 1;
2790                 vcpu->arch.pat = data;
2791                 svm->vmcb01.ptr->save.g_pat = data;
2792                 if (is_guest_mode(vcpu))
2793                         nested_vmcb02_compute_g_pat(svm);
2794                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2795                 break;
2796         case MSR_IA32_SPEC_CTRL:
2797                 if (!msr->host_initiated &&
2798                     !guest_has_spec_ctrl_msr(vcpu))
2799                         return 1;
2800
2801                 if (kvm_spec_ctrl_test_value(data))
2802                         return 1;
2803
2804                 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2805                         svm->vmcb->save.spec_ctrl = data;
2806                 else
2807                         svm->spec_ctrl = data;
2808                 if (!data)
2809                         break;
2810
2811                 /*
2812                  * For non-nested:
2813                  * When it's written (to non-zero) for the first time, pass
2814                  * it through.
2815                  *
2816                  * For nested:
2817                  * The handling of the MSR bitmap for L2 guests is done in
2818                  * nested_svm_vmrun_msrpm.
2819                  * We update the L1 MSR bit as well since it will end up
2820                  * touching the MSR anyway now.
2821                  */
2822                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2823                 break;
2824         case MSR_IA32_PRED_CMD:
2825                 if (!msr->host_initiated &&
2826                     !guest_has_pred_cmd_msr(vcpu))
2827                         return 1;
2828
2829                 if (data & ~PRED_CMD_IBPB)
2830                         return 1;
2831                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2832                         return 1;
2833                 if (!data)
2834                         break;
2835
2836                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2837                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2838                 break;
2839         case MSR_AMD64_VIRT_SPEC_CTRL:
2840                 if (!msr->host_initiated &&
2841                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2842                         return 1;
2843
2844                 if (data & ~SPEC_CTRL_SSBD)
2845                         return 1;
2846
2847                 svm->virt_spec_ctrl = data;
2848                 break;
2849         case MSR_STAR:
2850                 svm->vmcb01.ptr->save.star = data;
2851                 break;
2852 #ifdef CONFIG_X86_64
2853         case MSR_LSTAR:
2854                 svm->vmcb01.ptr->save.lstar = data;
2855                 break;
2856         case MSR_CSTAR:
2857                 svm->vmcb01.ptr->save.cstar = data;
2858                 break;
2859         case MSR_KERNEL_GS_BASE:
2860                 svm->vmcb01.ptr->save.kernel_gs_base = data;
2861                 break;
2862         case MSR_SYSCALL_MASK:
2863                 svm->vmcb01.ptr->save.sfmask = data;
2864                 break;
2865 #endif
2866         case MSR_IA32_SYSENTER_CS:
2867                 svm->vmcb01.ptr->save.sysenter_cs = data;
2868                 break;
2869         case MSR_IA32_SYSENTER_EIP:
2870                 svm->vmcb01.ptr->save.sysenter_eip = (u32)data;
2871                 /*
2872                  * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
2873                  * when we spoof an Intel vendor ID (for cross vendor migration).
2874                  * In this case we use this intercept to track the high
2875                  * 32 bit part of these msrs to support Intel's
2876                  * implementation of SYSENTER/SYSEXIT.
2877                  */
2878                 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2879                 break;
2880         case MSR_IA32_SYSENTER_ESP:
2881                 svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
2882                 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2883                 break;
2884         case MSR_TSC_AUX:
2885                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2886                         return 1;
2887
2888                 if (!msr->host_initiated &&
2889                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2890                         return 1;
2891
2892                 /*
2893                  * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
2894                  * incomplete and conflicting architectural behavior.  Current
2895                  * AMD CPUs completely ignore bits 63:32, i.e. they aren't
2896                  * reserved and always read as zeros.  Emulate AMD CPU behavior
2897                  * to avoid explosions if the vCPU is migrated from an AMD host
2898                  * to an Intel host.
2899                  */
2900                 data = (u32)data;
2901
2902                 /*
2903                  * TSC_AUX is usually changed only during boot and never read
2904                  * directly.  Intercept TSC_AUX instead of exposing it to the
2905                  * guest via direct_access_msrs, and switch it via user return.
2906                  */
2907                 preempt_disable();
2908                 r = kvm_set_user_return_msr(TSC_AUX_URET_SLOT, data, -1ull);
2909                 preempt_enable();
2910                 if (r)
2911                         return 1;
2912
2913                 svm->tsc_aux = data;
2914                 break;
2915         case MSR_IA32_DEBUGCTLMSR:
2916                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2917                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2918                                     __func__, data);
2919                         break;
2920                 }
2921                 if (data & DEBUGCTL_RESERVED_BITS)
2922                         return 1;
2923
2924                 svm->vmcb->save.dbgctl = data;
2925                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2926                 if (data & (1ULL<<0))
2927                         svm_enable_lbrv(vcpu);
2928                 else
2929                         svm_disable_lbrv(vcpu);
2930                 break;
2931         case MSR_VM_HSAVE_PA:
2932                 svm->nested.hsave_msr = data;
2933                 break;
2934         case MSR_VM_CR:
2935                 return svm_set_vm_cr(vcpu, data);
2936         case MSR_VM_IGNNE:
2937                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2938                 break;
2939         case MSR_F10H_DECFG: {
2940                 struct kvm_msr_entry msr_entry;
2941
2942                 msr_entry.index = msr->index;
2943                 if (svm_get_msr_feature(&msr_entry))
2944                         return 1;
2945
2946                 /* Check the supported bits */
2947                 if (data & ~msr_entry.data)
2948                         return 1;
2949
2950                 /* Don't allow the guest to change a bit, #GP */
2951                 if (!msr->host_initiated && (data ^ msr_entry.data))
2952                         return 1;
2953
2954                 svm->msr_decfg = data;
2955                 break;
2956         }
2957         case MSR_IA32_APICBASE:
2958                 if (kvm_vcpu_apicv_active(vcpu))
2959                         avic_update_vapic_bar(to_svm(vcpu), data);
2960                 fallthrough;
2961         default:
2962                 return kvm_set_msr_common(vcpu, msr);
2963         }
2964         return 0;
2965 }
2966
2967 static int msr_interception(struct kvm_vcpu *vcpu)
2968 {
2969         if (to_svm(vcpu)->vmcb->control.exit_info_1)
2970                 return kvm_emulate_wrmsr(vcpu);
2971         else
2972                 return kvm_emulate_rdmsr(vcpu);
2973 }
2974
2975 static int interrupt_window_interception(struct kvm_vcpu *vcpu)
2976 {
2977         kvm_make_request(KVM_REQ_EVENT, vcpu);
2978         svm_clear_vintr(to_svm(vcpu));
2979
2980         /*
2981          * For AVIC, the only reason to end up here is ExtINTs.
2982          * In this case AVIC was temporarily disabled for
2983          * requesting the IRQ window and we have to re-enable it.
2984          */
2985         svm_toggle_avic_for_irq_window(vcpu, true);
2986
2987         ++vcpu->stat.irq_window_exits;
2988         return 1;
2989 }
2990
2991 static int pause_interception(struct kvm_vcpu *vcpu)
2992 {
2993         bool in_kernel;
2994
2995         /*
2996          * CPL is not made available for an SEV-ES guest, therefore
2997          * vcpu->arch.preempted_in_kernel can never be true.  Just
2998          * set in_kernel to false as well.
2999          */
3000         in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0;
3001
3002         if (!kvm_pause_in_guest(vcpu->kvm))
3003                 grow_ple_window(vcpu);
3004
3005         kvm_vcpu_on_spin(vcpu, in_kernel);
3006         return kvm_skip_emulated_instruction(vcpu);
3007 }
3008
3009 static int invpcid_interception(struct kvm_vcpu *vcpu)
3010 {
3011         struct vcpu_svm *svm = to_svm(vcpu);
3012         unsigned long type;
3013         gva_t gva;
3014
3015         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3016                 kvm_queue_exception(vcpu, UD_VECTOR);
3017                 return 1;
3018         }
3019
3020         /*
3021          * For an INVPCID intercept:
3022          * EXITINFO1 provides the linear address of the memory operand.
3023          * EXITINFO2 provides the contents of the register operand.
3024          */
3025         type = svm->vmcb->control.exit_info_2;
3026         gva = svm->vmcb->control.exit_info_1;
3027
3028         if (type > 3) {
3029                 kvm_inject_gp(vcpu, 0);
3030                 return 1;
3031         }
3032
3033         return kvm_handle_invpcid(vcpu, type, gva);
3034 }
3035
3036 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3037         [SVM_EXIT_READ_CR0]                     = cr_interception,
3038         [SVM_EXIT_READ_CR3]                     = cr_interception,
3039         [SVM_EXIT_READ_CR4]                     = cr_interception,
3040         [SVM_EXIT_READ_CR8]                     = cr_interception,
3041         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3042         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3043         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3044         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3045         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3046         [SVM_EXIT_READ_DR0]                     = dr_interception,
3047         [SVM_EXIT_READ_DR1]                     = dr_interception,
3048         [SVM_EXIT_READ_DR2]                     = dr_interception,
3049         [SVM_EXIT_READ_DR3]                     = dr_interception,
3050         [SVM_EXIT_READ_DR4]                     = dr_interception,
3051         [SVM_EXIT_READ_DR5]                     = dr_interception,
3052         [SVM_EXIT_READ_DR6]                     = dr_interception,
3053         [SVM_EXIT_READ_DR7]                     = dr_interception,
3054         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3055         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3056         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3057         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3058         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3059         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3060         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3061         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3062         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3063         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3064         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3065         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3066         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3067         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
3068         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
3069         [SVM_EXIT_INTR]                         = intr_interception,
3070         [SVM_EXIT_NMI]                          = nmi_interception,
3071         [SVM_EXIT_SMI]                          = kvm_emulate_as_nop,
3072         [SVM_EXIT_INIT]                         = kvm_emulate_as_nop,
3073         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3074         [SVM_EXIT_RDPMC]                        = kvm_emulate_rdpmc,
3075         [SVM_EXIT_CPUID]                        = kvm_emulate_cpuid,
3076         [SVM_EXIT_IRET]                         = iret_interception,
3077         [SVM_EXIT_INVD]                         = kvm_emulate_invd,
3078         [SVM_EXIT_PAUSE]                        = pause_interception,
3079         [SVM_EXIT_HLT]                          = kvm_emulate_halt,
3080         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3081         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3082         [SVM_EXIT_IOIO]                         = io_interception,
3083         [SVM_EXIT_MSR]                          = msr_interception,
3084         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3085         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3086         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3087         [SVM_EXIT_VMMCALL]                      = kvm_emulate_hypercall,
3088         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3089         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3090         [SVM_EXIT_STGI]                         = stgi_interception,
3091         [SVM_EXIT_CLGI]                         = clgi_interception,
3092         [SVM_EXIT_SKINIT]                       = skinit_interception,
3093         [SVM_EXIT_WBINVD]                       = kvm_emulate_wbinvd,
3094         [SVM_EXIT_MONITOR]                      = kvm_emulate_monitor,
3095         [SVM_EXIT_MWAIT]                        = kvm_emulate_mwait,
3096         [SVM_EXIT_XSETBV]                       = kvm_emulate_xsetbv,
3097         [SVM_EXIT_RDPRU]                        = kvm_handle_invalid_op,
3098         [SVM_EXIT_EFER_WRITE_TRAP]              = efer_trap,
3099         [SVM_EXIT_CR0_WRITE_TRAP]               = cr_trap,
3100         [SVM_EXIT_CR4_WRITE_TRAP]               = cr_trap,
3101         [SVM_EXIT_CR8_WRITE_TRAP]               = cr_trap,
3102         [SVM_EXIT_INVPCID]                      = invpcid_interception,
3103         [SVM_EXIT_NPF]                          = npf_interception,
3104         [SVM_EXIT_RSM]                          = rsm_interception,
3105         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
3106         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
3107         [SVM_EXIT_VMGEXIT]                      = sev_handle_vmgexit,
3108 };
3109
3110 static void dump_vmcb(struct kvm_vcpu *vcpu)
3111 {
3112         struct vcpu_svm *svm = to_svm(vcpu);
3113         struct vmcb_control_area *control = &svm->vmcb->control;
3114         struct vmcb_save_area *save = &svm->vmcb->save;
3115         struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save;
3116
3117         if (!dump_invalid_vmcb) {
3118                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3119                 return;
3120         }
3121
3122         pr_err("VMCB Control Area:\n");
3123         pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3124         pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3125         pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3126         pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3127         pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3128         pr_err("%-20s%08x %08x\n", "intercepts:",
3129               control->intercepts[INTERCEPT_WORD3],
3130                control->intercepts[INTERCEPT_WORD4]);
3131         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3132         pr_err("%-20s%d\n", "pause filter threshold:",
3133                control->pause_filter_thresh);
3134         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3135         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3136         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3137         pr_err("%-20s%d\n", "asid:", control->asid);
3138         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3139         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3140         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3141         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3142         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3143         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3144         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3145         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3146         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3147         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3148         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3149         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3150         pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3151         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3152         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3153         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3154         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3155         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3156         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3157         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3158         pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3159         pr_err("VMCB State Save Area:\n");
3160         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3161                "es:",
3162                save->es.selector, save->es.attrib,
3163                save->es.limit, save->es.base);
3164         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3165                "cs:",
3166                save->cs.selector, save->cs.attrib,
3167                save->cs.limit, save->cs.base);
3168         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3169                "ss:",
3170                save->ss.selector, save->ss.attrib,
3171                save->ss.limit, save->ss.base);
3172         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3173                "ds:",
3174                save->ds.selector, save->ds.attrib,
3175                save->ds.limit, save->ds.base);
3176         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3177                "fs:",
3178                save01->fs.selector, save01->fs.attrib,
3179                save01->fs.limit, save01->fs.base);
3180         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3181                "gs:",
3182                save01->gs.selector, save01->gs.attrib,
3183                save01->gs.limit, save01->gs.base);
3184         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3185                "gdtr:",
3186                save->gdtr.selector, save->gdtr.attrib,
3187                save->gdtr.limit, save->gdtr.base);
3188         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3189                "ldtr:",
3190                save01->ldtr.selector, save01->ldtr.attrib,
3191                save01->ldtr.limit, save01->ldtr.base);
3192         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3193                "idtr:",
3194                save->idtr.selector, save->idtr.attrib,
3195                save->idtr.limit, save->idtr.base);
3196         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3197                "tr:",
3198                save01->tr.selector, save01->tr.attrib,
3199                save01->tr.limit, save01->tr.base);
3200         pr_err("cpl:            %d                efer:         %016llx\n",
3201                 save->cpl, save->efer);
3202         pr_err("%-15s %016llx %-13s %016llx\n",
3203                "cr0:", save->cr0, "cr2:", save->cr2);
3204         pr_err("%-15s %016llx %-13s %016llx\n",
3205                "cr3:", save->cr3, "cr4:", save->cr4);
3206         pr_err("%-15s %016llx %-13s %016llx\n",
3207                "dr6:", save->dr6, "dr7:", save->dr7);
3208         pr_err("%-15s %016llx %-13s %016llx\n",
3209                "rip:", save->rip, "rflags:", save->rflags);
3210         pr_err("%-15s %016llx %-13s %016llx\n",
3211                "rsp:", save->rsp, "rax:", save->rax);
3212         pr_err("%-15s %016llx %-13s %016llx\n",
3213                "star:", save01->star, "lstar:", save01->lstar);
3214         pr_err("%-15s %016llx %-13s %016llx\n",
3215                "cstar:", save01->cstar, "sfmask:", save01->sfmask);
3216         pr_err("%-15s %016llx %-13s %016llx\n",
3217                "kernel_gs_base:", save01->kernel_gs_base,
3218                "sysenter_cs:", save01->sysenter_cs);
3219         pr_err("%-15s %016llx %-13s %016llx\n",
3220                "sysenter_esp:", save01->sysenter_esp,
3221                "sysenter_eip:", save01->sysenter_eip);
3222         pr_err("%-15s %016llx %-13s %016llx\n",
3223                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3224         pr_err("%-15s %016llx %-13s %016llx\n",
3225                "br_from:", save->br_from, "br_to:", save->br_to);
3226         pr_err("%-15s %016llx %-13s %016llx\n",
3227                "excp_from:", save->last_excp_from,
3228                "excp_to:", save->last_excp_to);
3229 }
3230
3231 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3232 {
3233         if (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3234             svm_exit_handlers[exit_code])
3235                 return 0;
3236
3237         vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3238         dump_vmcb(vcpu);
3239         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3240         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3241         vcpu->run->internal.ndata = 2;
3242         vcpu->run->internal.data[0] = exit_code;
3243         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3244
3245         return -EINVAL;
3246 }
3247
3248 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code)
3249 {
3250         if (svm_handle_invalid_exit(vcpu, exit_code))
3251                 return 0;
3252
3253 #ifdef CONFIG_RETPOLINE
3254         if (exit_code == SVM_EXIT_MSR)
3255                 return msr_interception(vcpu);
3256         else if (exit_code == SVM_EXIT_VINTR)
3257                 return interrupt_window_interception(vcpu);
3258         else if (exit_code == SVM_EXIT_INTR)
3259                 return intr_interception(vcpu);
3260         else if (exit_code == SVM_EXIT_HLT)
3261                 return kvm_emulate_halt(vcpu);
3262         else if (exit_code == SVM_EXIT_NPF)
3263                 return npf_interception(vcpu);
3264 #endif
3265         return svm_exit_handlers[exit_code](vcpu);
3266 }
3267
3268 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3269                               u32 *intr_info, u32 *error_code)
3270 {
3271         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3272
3273         *info1 = control->exit_info_1;
3274         *info2 = control->exit_info_2;
3275         *intr_info = control->exit_int_info;
3276         if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3277             (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3278                 *error_code = control->exit_int_info_err;
3279         else
3280                 *error_code = 0;
3281 }
3282
3283 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3284 {
3285         struct vcpu_svm *svm = to_svm(vcpu);
3286         struct kvm_run *kvm_run = vcpu->run;
3287         u32 exit_code = svm->vmcb->control.exit_code;
3288
3289         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3290
3291         /* SEV-ES guests must use the CR write traps to track CR registers. */
3292         if (!sev_es_guest(vcpu->kvm)) {
3293                 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3294                         vcpu->arch.cr0 = svm->vmcb->save.cr0;
3295                 if (npt_enabled)
3296                         vcpu->arch.cr3 = svm->vmcb->save.cr3;
3297         }
3298
3299         if (is_guest_mode(vcpu)) {
3300                 int vmexit;
3301
3302                 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3303
3304                 vmexit = nested_svm_exit_special(svm);
3305
3306                 if (vmexit == NESTED_EXIT_CONTINUE)
3307                         vmexit = nested_svm_exit_handled(svm);
3308
3309                 if (vmexit == NESTED_EXIT_DONE)
3310                         return 1;
3311         }
3312
3313         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3314                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3315                 kvm_run->fail_entry.hardware_entry_failure_reason
3316                         = svm->vmcb->control.exit_code;
3317                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3318                 dump_vmcb(vcpu);
3319                 return 0;
3320         }
3321
3322         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3323             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3324             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3325             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3326                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3327                        "exit_code 0x%x\n",
3328                        __func__, svm->vmcb->control.exit_int_info,
3329                        exit_code);
3330
3331         if (exit_fastpath != EXIT_FASTPATH_NONE)
3332                 return 1;
3333
3334         return svm_invoke_exit_handler(vcpu, exit_code);
3335 }
3336
3337 static void reload_tss(struct kvm_vcpu *vcpu)
3338 {
3339         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3340
3341         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3342         load_TR_desc();
3343 }
3344
3345 static void pre_svm_run(struct kvm_vcpu *vcpu)
3346 {
3347         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3348         struct vcpu_svm *svm = to_svm(vcpu);
3349
3350         /*
3351          * If the previous vmrun of the vmcb occurred on a different physical
3352          * cpu, then mark the vmcb dirty and assign a new asid.  Hardware's
3353          * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3354          */
3355         if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) {
3356                 svm->current_vmcb->asid_generation = 0;
3357                 vmcb_mark_all_dirty(svm->vmcb);
3358                 svm->current_vmcb->cpu = vcpu->cpu;
3359         }
3360
3361         if (sev_guest(vcpu->kvm))
3362                 return pre_sev_run(svm, vcpu->cpu);
3363
3364         /* FIXME: handle wraparound of asid_generation */
3365         if (svm->current_vmcb->asid_generation != sd->asid_generation)
3366                 new_asid(svm, sd);
3367 }
3368
3369 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3370 {
3371         struct vcpu_svm *svm = to_svm(vcpu);
3372
3373         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3374         vcpu->arch.hflags |= HF_NMI_MASK;
3375         if (!sev_es_guest(vcpu->kvm))
3376                 svm_set_intercept(svm, INTERCEPT_IRET);
3377         ++vcpu->stat.nmi_injections;
3378 }
3379
3380 static void svm_set_irq(struct kvm_vcpu *vcpu)
3381 {
3382         struct vcpu_svm *svm = to_svm(vcpu);
3383
3384         BUG_ON(!(gif_set(svm)));
3385
3386         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3387         ++vcpu->stat.irq_injections;
3388
3389         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3390                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3391 }
3392
3393 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3394 {
3395         struct vcpu_svm *svm = to_svm(vcpu);
3396
3397         /*
3398          * SEV-ES guests must always keep the CR intercepts cleared. CR
3399          * tracking is done using the CR write traps.
3400          */
3401         if (sev_es_guest(vcpu->kvm))
3402                 return;
3403
3404         if (nested_svm_virtualize_tpr(vcpu))
3405                 return;
3406
3407         svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3408
3409         if (irr == -1)
3410                 return;
3411
3412         if (tpr >= irr)
3413                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3414 }
3415
3416 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3417 {
3418         struct vcpu_svm *svm = to_svm(vcpu);
3419         struct vmcb *vmcb = svm->vmcb;
3420         bool ret;
3421
3422         if (!gif_set(svm))
3423                 return true;
3424
3425         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3426                 return false;
3427
3428         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3429               (vcpu->arch.hflags & HF_NMI_MASK);
3430
3431         return ret;
3432 }
3433
3434 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3435 {
3436         struct vcpu_svm *svm = to_svm(vcpu);
3437         if (svm->nested.nested_run_pending)
3438                 return -EBUSY;
3439
3440         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3441         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3442                 return -EBUSY;
3443
3444         return !svm_nmi_blocked(vcpu);
3445 }
3446
3447 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3448 {
3449         return !!(vcpu->arch.hflags & HF_NMI_MASK);
3450 }
3451
3452 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3453 {
3454         struct vcpu_svm *svm = to_svm(vcpu);
3455
3456         if (masked) {
3457                 vcpu->arch.hflags |= HF_NMI_MASK;
3458                 if (!sev_es_guest(vcpu->kvm))
3459                         svm_set_intercept(svm, INTERCEPT_IRET);
3460         } else {
3461                 vcpu->arch.hflags &= ~HF_NMI_MASK;
3462                 if (!sev_es_guest(vcpu->kvm))
3463                         svm_clr_intercept(svm, INTERCEPT_IRET);
3464         }
3465 }
3466
3467 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3468 {
3469         struct vcpu_svm *svm = to_svm(vcpu);
3470         struct vmcb *vmcb = svm->vmcb;
3471
3472         if (!gif_set(svm))
3473                 return true;
3474
3475         if (sev_es_guest(vcpu->kvm)) {
3476                 /*
3477                  * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3478                  * bit to determine the state of the IF flag.
3479                  */
3480                 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3481                         return true;
3482         } else if (is_guest_mode(vcpu)) {
3483                 /* As long as interrupts are being delivered...  */
3484                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3485                     ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF)
3486                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3487                         return true;
3488
3489                 /* ... vmexits aren't blocked by the interrupt shadow  */
3490                 if (nested_exit_on_intr(svm))
3491                         return false;
3492         } else {
3493                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3494                         return true;
3495         }
3496
3497         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3498 }
3499
3500 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3501 {
3502         struct vcpu_svm *svm = to_svm(vcpu);
3503         if (svm->nested.nested_run_pending)
3504                 return -EBUSY;
3505
3506         /*
3507          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3508          * e.g. if the IRQ arrived asynchronously after checking nested events.
3509          */
3510         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3511                 return -EBUSY;
3512
3513         return !svm_interrupt_blocked(vcpu);
3514 }
3515
3516 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3517 {
3518         struct vcpu_svm *svm = to_svm(vcpu);
3519
3520         /*
3521          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3522          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3523          * get that intercept, this function will be called again though and
3524          * we'll get the vintr intercept. However, if the vGIF feature is
3525          * enabled, the STGI interception will not occur. Enable the irq
3526          * window under the assumption that the hardware will set the GIF.
3527          */
3528         if (vgif_enabled(svm) || gif_set(svm)) {
3529                 /*
3530                  * IRQ window is not needed when AVIC is enabled,
3531                  * unless we have pending ExtINT since it cannot be injected
3532                  * via AVIC. In such case, we need to temporarily disable AVIC,
3533                  * and fallback to injecting IRQ via V_IRQ.
3534                  */
3535                 svm_toggle_avic_for_irq_window(vcpu, false);
3536                 svm_set_vintr(svm);
3537         }
3538 }
3539
3540 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3541 {
3542         struct vcpu_svm *svm = to_svm(vcpu);
3543
3544         if ((vcpu->arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) == HF_NMI_MASK)
3545                 return; /* IRET will cause a vm exit */
3546
3547         if (!gif_set(svm)) {
3548                 if (vgif_enabled(svm))
3549                         svm_set_intercept(svm, INTERCEPT_STGI);
3550                 return; /* STGI will cause a vm exit */
3551         }
3552
3553         /*
3554          * Something prevents NMI from been injected. Single step over possible
3555          * problem (IRET or exception injection or interrupt shadow)
3556          */
3557         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3558         svm->nmi_singlestep = true;
3559         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3560 }
3561
3562 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3563 {
3564         return 0;
3565 }
3566
3567 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3568 {
3569         return 0;
3570 }
3571
3572 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3573 {
3574         struct vcpu_svm *svm = to_svm(vcpu);
3575
3576         /*
3577          * Flush only the current ASID even if the TLB flush was invoked via
3578          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3579          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3580          * unconditionally does a TLB flush on both nested VM-Enter and nested
3581          * VM-Exit (via kvm_mmu_reset_context()).
3582          */
3583         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3584                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3585         else
3586                 svm->current_vmcb->asid_generation--;
3587 }
3588
3589 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3590 {
3591         struct vcpu_svm *svm = to_svm(vcpu);
3592
3593         invlpga(gva, svm->vmcb->control.asid);
3594 }
3595
3596 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3597 {
3598         struct vcpu_svm *svm = to_svm(vcpu);
3599
3600         if (nested_svm_virtualize_tpr(vcpu))
3601                 return;
3602
3603         if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3604                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3605                 kvm_set_cr8(vcpu, cr8);
3606         }
3607 }
3608
3609 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3610 {
3611         struct vcpu_svm *svm = to_svm(vcpu);
3612         u64 cr8;
3613
3614         if (nested_svm_virtualize_tpr(vcpu) ||
3615             kvm_vcpu_apicv_active(vcpu))
3616                 return;
3617
3618         cr8 = kvm_get_cr8(vcpu);
3619         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3620         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3621 }
3622
3623 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
3624 {
3625         struct vcpu_svm *svm = to_svm(vcpu);
3626         u8 vector;
3627         int type;
3628         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3629         unsigned int3_injected = svm->int3_injected;
3630
3631         svm->int3_injected = 0;
3632
3633         /*
3634          * If we've made progress since setting HF_IRET_MASK, we've
3635          * executed an IRET and can allow NMI injection.
3636          */
3637         if ((vcpu->arch.hflags & HF_IRET_MASK) &&
3638             (sev_es_guest(vcpu->kvm) ||
3639              kvm_rip_read(vcpu) != svm->nmi_iret_rip)) {
3640                 vcpu->arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3641                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3642         }
3643
3644         vcpu->arch.nmi_injected = false;
3645         kvm_clear_exception_queue(vcpu);
3646         kvm_clear_interrupt_queue(vcpu);
3647
3648         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3649                 return;
3650
3651         kvm_make_request(KVM_REQ_EVENT, vcpu);
3652
3653         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3654         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3655
3656         switch (type) {
3657         case SVM_EXITINTINFO_TYPE_NMI:
3658                 vcpu->arch.nmi_injected = true;
3659                 break;
3660         case SVM_EXITINTINFO_TYPE_EXEPT:
3661                 /*
3662                  * Never re-inject a #VC exception.
3663                  */
3664                 if (vector == X86_TRAP_VC)
3665                         break;
3666
3667                 /*
3668                  * In case of software exceptions, do not reinject the vector,
3669                  * but re-execute the instruction instead. Rewind RIP first
3670                  * if we emulated INT3 before.
3671                  */
3672                 if (kvm_exception_is_soft(vector)) {
3673                         if (vector == BP_VECTOR && int3_injected &&
3674                             kvm_is_linear_rip(vcpu, svm->int3_rip))
3675                                 kvm_rip_write(vcpu,
3676                                               kvm_rip_read(vcpu) - int3_injected);
3677                         break;
3678                 }
3679                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3680                         u32 err = svm->vmcb->control.exit_int_info_err;
3681                         kvm_requeue_exception_e(vcpu, vector, err);
3682
3683                 } else
3684                         kvm_requeue_exception(vcpu, vector);
3685                 break;
3686         case SVM_EXITINTINFO_TYPE_INTR:
3687                 kvm_queue_interrupt(vcpu, vector, false);
3688                 break;
3689         default:
3690                 break;
3691         }
3692 }
3693
3694 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3695 {
3696         struct vcpu_svm *svm = to_svm(vcpu);
3697         struct vmcb_control_area *control = &svm->vmcb->control;
3698
3699         control->exit_int_info = control->event_inj;
3700         control->exit_int_info_err = control->event_inj_err;
3701         control->event_inj = 0;
3702         svm_complete_interrupts(vcpu);
3703 }
3704
3705 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3706 {
3707         if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3708             to_svm(vcpu)->vmcb->control.exit_info_1)
3709                 return handle_fastpath_set_msr_irqoff(vcpu);
3710
3711         return EXIT_FASTPATH_NONE;
3712 }
3713
3714 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
3715 {
3716         struct vcpu_svm *svm = to_svm(vcpu);
3717         unsigned long vmcb_pa = svm->current_vmcb->pa;
3718
3719         /*
3720          * VMENTER enables interrupts (host state), but the kernel state is
3721          * interrupts disabled when this is invoked. Also tell RCU about
3722          * it. This is the same logic as for exit_to_user_mode().
3723          *
3724          * This ensures that e.g. latency analysis on the host observes
3725          * guest mode as interrupt enabled.
3726          *
3727          * guest_enter_irqoff() informs context tracking about the
3728          * transition to guest mode and if enabled adjusts RCU state
3729          * accordingly.
3730          */
3731         instrumentation_begin();
3732         trace_hardirqs_on_prepare();
3733         lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3734         instrumentation_end();
3735
3736         guest_enter_irqoff();
3737         lockdep_hardirqs_on(CALLER_ADDR0);
3738
3739         if (sev_es_guest(vcpu->kvm)) {
3740                 __svm_sev_es_vcpu_run(vmcb_pa);
3741         } else {
3742                 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3743
3744                 /*
3745                  * Use a single vmcb (vmcb01 because it's always valid) for
3746                  * context switching guest state via VMLOAD/VMSAVE, that way
3747                  * the state doesn't need to be copied between vmcb01 and
3748                  * vmcb02 when switching vmcbs for nested virtualization.
3749                  */
3750                 vmload(svm->vmcb01.pa);
3751                 __svm_vcpu_run(vmcb_pa, (unsigned long *)&vcpu->arch.regs);
3752                 vmsave(svm->vmcb01.pa);
3753
3754                 vmload(__sme_page_pa(sd->save_area));
3755         }
3756
3757         /*
3758          * VMEXIT disables interrupts (host state), but tracing and lockdep
3759          * have them in state 'on' as recorded before entering guest mode.
3760          * Same as enter_from_user_mode().
3761          *
3762          * guest_exit_irqoff() restores host context and reinstates RCU if
3763          * enabled and required.
3764          *
3765          * This needs to be done before the below as native_read_msr()
3766          * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3767          * into world and some more.
3768          */
3769         lockdep_hardirqs_off(CALLER_ADDR0);
3770         guest_exit_irqoff();
3771
3772         instrumentation_begin();
3773         trace_hardirqs_off_finish();
3774         instrumentation_end();
3775 }
3776
3777 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3778 {
3779         struct vcpu_svm *svm = to_svm(vcpu);
3780
3781         trace_kvm_entry(vcpu);
3782
3783         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3784         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3785         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3786
3787         /*
3788          * Disable singlestep if we're injecting an interrupt/exception.
3789          * We don't want our modified rflags to be pushed on the stack where
3790          * we might not be able to easily reset them if we disabled NMI
3791          * singlestep later.
3792          */
3793         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3794                 /*
3795                  * Event injection happens before external interrupts cause a
3796                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3797                  * is enough to force an immediate vmexit.
3798                  */
3799                 disable_nmi_singlestep(svm);
3800                 smp_send_reschedule(vcpu->cpu);
3801         }
3802
3803         pre_svm_run(vcpu);
3804
3805         sync_lapic_to_cr8(vcpu);
3806
3807         if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3808                 svm->vmcb->control.asid = svm->asid;
3809                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3810         }
3811         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3812
3813         /*
3814          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3815          * of a #DB.
3816          */
3817         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3818                 svm_set_dr6(svm, vcpu->arch.dr6);
3819         else
3820                 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3821
3822         clgi();
3823         kvm_load_guest_xsave_state(vcpu);
3824
3825         kvm_wait_lapic_expire(vcpu);
3826
3827         /*
3828          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3829          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3830          * is no need to worry about the conditional branch over the wrmsr
3831          * being speculatively taken.
3832          */
3833         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3834                 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3835
3836         svm_vcpu_enter_exit(vcpu);
3837
3838         /*
3839          * We do not use IBRS in the kernel. If this vCPU has used the
3840          * SPEC_CTRL MSR it may have left it on; save the value and
3841          * turn it off. This is much more efficient than blindly adding
3842          * it to the atomic save/restore list. Especially as the former
3843          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3844          *
3845          * For non-nested case:
3846          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3847          * save it.
3848          *
3849          * For nested case:
3850          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3851          * save it.
3852          */
3853         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL) &&
3854             unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3855                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3856
3857         if (!sev_es_guest(vcpu->kvm))
3858                 reload_tss(vcpu);
3859
3860         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3861                 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3862
3863         if (!sev_es_guest(vcpu->kvm)) {
3864                 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3865                 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3866                 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3867                 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3868         }
3869
3870         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3871                 kvm_before_interrupt(vcpu);
3872
3873         kvm_load_host_xsave_state(vcpu);
3874         stgi();
3875
3876         /* Any pending NMI will happen here */
3877
3878         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3879                 kvm_after_interrupt(vcpu);
3880
3881         sync_cr8_to_lapic(vcpu);
3882
3883         svm->next_rip = 0;
3884         if (is_guest_mode(vcpu)) {
3885                 nested_sync_control_from_vmcb02(svm);
3886                 svm->nested.nested_run_pending = 0;
3887         }
3888
3889         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3890         vmcb_mark_all_clean(svm->vmcb);
3891
3892         /* if exit due to PF check for async PF */
3893         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3894                 vcpu->arch.apf.host_apf_flags =
3895                         kvm_read_and_reset_apf_flags();
3896
3897         if (npt_enabled) {
3898                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3899                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3900         }
3901
3902         /*
3903          * We need to handle MC intercepts here before the vcpu has a chance to
3904          * change the physical cpu
3905          */
3906         if (unlikely(svm->vmcb->control.exit_code ==
3907                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3908                 svm_handle_mce(vcpu);
3909
3910         svm_complete_interrupts(vcpu);
3911
3912         if (is_guest_mode(vcpu))
3913                 return EXIT_FASTPATH_NONE;
3914
3915         return svm_exit_handlers_fastpath(vcpu);
3916 }
3917
3918 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3919                              int root_level)
3920 {
3921         struct vcpu_svm *svm = to_svm(vcpu);
3922         unsigned long cr3;
3923
3924         if (npt_enabled) {
3925                 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa);
3926                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3927
3928                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3929                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3930                         return;
3931                 cr3 = vcpu->arch.cr3;
3932         } else if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3933                 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
3934         } else {
3935                 /* PCID in the guest should be impossible with a 32-bit MMU. */
3936                 WARN_ON_ONCE(kvm_get_active_pcid(vcpu));
3937                 cr3 = root_hpa;
3938         }
3939
3940         svm->vmcb->save.cr3 = cr3;
3941         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3942 }
3943
3944 static int is_disabled(void)
3945 {
3946         u64 vm_cr;
3947
3948         rdmsrl(MSR_VM_CR, vm_cr);
3949         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3950                 return 1;
3951
3952         return 0;
3953 }
3954
3955 static void
3956 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3957 {
3958         /*
3959          * Patch in the VMMCALL instruction:
3960          */
3961         hypercall[0] = 0x0f;
3962         hypercall[1] = 0x01;
3963         hypercall[2] = 0xd9;
3964 }
3965
3966 static int __init svm_check_processor_compat(void)
3967 {
3968         return 0;
3969 }
3970
3971 static bool svm_cpu_has_accelerated_tpr(void)
3972 {
3973         return false;
3974 }
3975
3976 /*
3977  * The kvm parameter can be NULL (module initialization, or invocation before
3978  * VM creation). Be sure to check the kvm parameter before using it.
3979  */
3980 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
3981 {
3982         switch (index) {
3983         case MSR_IA32_MCG_EXT_CTL:
3984         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3985                 return false;
3986         case MSR_IA32_SMBASE:
3987                 /* SEV-ES guests do not support SMM, so report false */
3988                 if (kvm && sev_es_guest(kvm))
3989                         return false;
3990                 break;
3991         default:
3992                 break;
3993         }
3994
3995         return true;
3996 }
3997
3998 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3999 {
4000         return 0;
4001 }
4002
4003 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
4004 {
4005         struct vcpu_svm *svm = to_svm(vcpu);
4006         struct kvm_cpuid_entry2 *best;
4007
4008         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4009                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
4010                                     boot_cpu_has(X86_FEATURE_XSAVES);
4011
4012         /* Update nrips enabled cache */
4013         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
4014                              guest_cpuid_has(vcpu, X86_FEATURE_NRIPS);
4015
4016         /* Check again if INVPCID interception if required */
4017         svm_check_invpcid(svm);
4018
4019         /* For sev guests, the memory encryption bit is not reserved in CR3.  */
4020         if (sev_guest(vcpu->kvm)) {
4021                 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
4022                 if (best)
4023                         vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
4024         }
4025
4026         if (kvm_vcpu_apicv_active(vcpu)) {
4027                 /*
4028                  * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
4029                  * is exposed to the guest, disable AVIC.
4030                  */
4031                 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
4032                         kvm_request_apicv_update(vcpu->kvm, false,
4033                                                  APICV_INHIBIT_REASON_X2APIC);
4034
4035                 /*
4036                  * Currently, AVIC does not work with nested virtualization.
4037                  * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
4038                  */
4039                 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4040                         kvm_request_apicv_update(vcpu->kvm, false,
4041                                                  APICV_INHIBIT_REASON_NESTED);
4042         }
4043
4044         if (guest_cpuid_is_intel(vcpu)) {
4045                 /*
4046                  * We must intercept SYSENTER_EIP and SYSENTER_ESP
4047                  * accesses because the processor only stores 32 bits.
4048                  * For the same reason we cannot use virtual VMLOAD/VMSAVE.
4049                  */
4050                 svm_set_intercept(svm, INTERCEPT_VMLOAD);
4051                 svm_set_intercept(svm, INTERCEPT_VMSAVE);
4052                 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4053
4054                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0);
4055                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0);
4056         } else {
4057                 /*
4058                  * If hardware supports Virtual VMLOAD VMSAVE then enable it
4059                  * in VMCB and clear intercepts to avoid #VMEXIT.
4060                  */
4061                 if (vls) {
4062                         svm_clr_intercept(svm, INTERCEPT_VMLOAD);
4063                         svm_clr_intercept(svm, INTERCEPT_VMSAVE);
4064                         svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4065                 }
4066                 /* No need to intercept these MSRs */
4067                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
4068                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
4069         }
4070 }
4071
4072 static bool svm_has_wbinvd_exit(void)
4073 {
4074         return true;
4075 }
4076
4077 #define PRE_EX(exit)  { .exit_code = (exit), \
4078                         .stage = X86_ICPT_PRE_EXCEPT, }
4079 #define POST_EX(exit) { .exit_code = (exit), \
4080                         .stage = X86_ICPT_POST_EXCEPT, }
4081 #define POST_MEM(exit) { .exit_code = (exit), \
4082                         .stage = X86_ICPT_POST_MEMACCESS, }
4083
4084 static const struct __x86_intercept {
4085         u32 exit_code;
4086         enum x86_intercept_stage stage;
4087 } x86_intercept_map[] = {
4088         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4089         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4090         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4091         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4092         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4093         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4094         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4095         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4096         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4097         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4098         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4099         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4100         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4101         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4102         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4103         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4104         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4105         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4106         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4107         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4108         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4109         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4110         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4111         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4112         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4113         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4114         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4115         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4116         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4117         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4118         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4119         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4120         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4121         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4122         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4123         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4124         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4125         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4126         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4127         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4128         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4129         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4130         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4131         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4132         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4133         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4134         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
4135 };
4136
4137 #undef PRE_EX
4138 #undef POST_EX
4139 #undef POST_MEM
4140
4141 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4142                                struct x86_instruction_info *info,
4143                                enum x86_intercept_stage stage,
4144                                struct x86_exception *exception)
4145 {
4146         struct vcpu_svm *svm = to_svm(vcpu);
4147         int vmexit, ret = X86EMUL_CONTINUE;
4148         struct __x86_intercept icpt_info;
4149         struct vmcb *vmcb = svm->vmcb;
4150
4151         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4152                 goto out;
4153
4154         icpt_info = x86_intercept_map[info->intercept];
4155
4156         if (stage != icpt_info.stage)
4157                 goto out;
4158
4159         switch (icpt_info.exit_code) {
4160         case SVM_EXIT_READ_CR0:
4161                 if (info->intercept == x86_intercept_cr_read)
4162                         icpt_info.exit_code += info->modrm_reg;
4163                 break;
4164         case SVM_EXIT_WRITE_CR0: {
4165                 unsigned long cr0, val;
4166
4167                 if (info->intercept == x86_intercept_cr_write)
4168                         icpt_info.exit_code += info->modrm_reg;
4169
4170                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4171                     info->intercept == x86_intercept_clts)
4172                         break;
4173
4174                 if (!(vmcb_is_intercept(&svm->nested.ctl,
4175                                         INTERCEPT_SELECTIVE_CR0)))
4176                         break;
4177
4178                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4179                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4180
4181                 if (info->intercept == x86_intercept_lmsw) {
4182                         cr0 &= 0xfUL;
4183                         val &= 0xfUL;
4184                         /* lmsw can't clear PE - catch this here */
4185                         if (cr0 & X86_CR0_PE)
4186                                 val |= X86_CR0_PE;
4187                 }
4188
4189                 if (cr0 ^ val)
4190                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4191
4192                 break;
4193         }
4194         case SVM_EXIT_READ_DR0:
4195         case SVM_EXIT_WRITE_DR0:
4196                 icpt_info.exit_code += info->modrm_reg;
4197                 break;
4198         case SVM_EXIT_MSR:
4199                 if (info->intercept == x86_intercept_wrmsr)
4200                         vmcb->control.exit_info_1 = 1;
4201                 else
4202                         vmcb->control.exit_info_1 = 0;
4203                 break;
4204         case SVM_EXIT_PAUSE:
4205                 /*
4206                  * We get this for NOP only, but pause
4207                  * is rep not, check this here
4208                  */
4209                 if (info->rep_prefix != REPE_PREFIX)
4210                         goto out;
4211                 break;
4212         case SVM_EXIT_IOIO: {
4213                 u64 exit_info;
4214                 u32 bytes;
4215
4216                 if (info->intercept == x86_intercept_in ||
4217                     info->intercept == x86_intercept_ins) {
4218                         exit_info = ((info->src_val & 0xffff) << 16) |
4219                                 SVM_IOIO_TYPE_MASK;
4220                         bytes = info->dst_bytes;
4221                 } else {
4222                         exit_info = (info->dst_val & 0xffff) << 16;
4223                         bytes = info->src_bytes;
4224                 }
4225
4226                 if (info->intercept == x86_intercept_outs ||
4227                     info->intercept == x86_intercept_ins)
4228                         exit_info |= SVM_IOIO_STR_MASK;
4229
4230                 if (info->rep_prefix)
4231                         exit_info |= SVM_IOIO_REP_MASK;
4232
4233                 bytes = min(bytes, 4u);
4234
4235                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4236
4237                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4238
4239                 vmcb->control.exit_info_1 = exit_info;
4240                 vmcb->control.exit_info_2 = info->next_rip;
4241
4242                 break;
4243         }
4244         default:
4245                 break;
4246         }
4247
4248         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4249         if (static_cpu_has(X86_FEATURE_NRIPS))
4250                 vmcb->control.next_rip  = info->next_rip;
4251         vmcb->control.exit_code = icpt_info.exit_code;
4252         vmexit = nested_svm_exit_handled(svm);
4253
4254         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4255                                            : X86EMUL_CONTINUE;
4256
4257 out:
4258         return ret;
4259 }
4260
4261 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4262 {
4263 }
4264
4265 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4266 {
4267         if (!kvm_pause_in_guest(vcpu->kvm))
4268                 shrink_ple_window(vcpu);
4269 }
4270
4271 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4272 {
4273         /* [63:9] are reserved. */
4274         vcpu->arch.mcg_cap &= 0x1ff;
4275 }
4276
4277 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4278 {
4279         struct vcpu_svm *svm = to_svm(vcpu);
4280
4281         /* Per APM Vol.2 15.22.2 "Response to SMI" */
4282         if (!gif_set(svm))
4283                 return true;
4284
4285         return is_smm(vcpu);
4286 }
4287
4288 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4289 {
4290         struct vcpu_svm *svm = to_svm(vcpu);
4291         if (svm->nested.nested_run_pending)
4292                 return -EBUSY;
4293
4294         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
4295         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4296                 return -EBUSY;
4297
4298         return !svm_smi_blocked(vcpu);
4299 }
4300
4301 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4302 {
4303         struct vcpu_svm *svm = to_svm(vcpu);
4304         int ret;
4305
4306         if (is_guest_mode(vcpu)) {
4307                 /* FED8h - SVM Guest */
4308                 put_smstate(u64, smstate, 0x7ed8, 1);
4309                 /* FEE0h - SVM Guest VMCB Physical Address */
4310                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4311
4312                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4313                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4314                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4315
4316                 ret = nested_svm_vmexit(svm);
4317                 if (ret)
4318                         return ret;
4319         }
4320         return 0;
4321 }
4322
4323 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4324 {
4325         struct vcpu_svm *svm = to_svm(vcpu);
4326         struct kvm_host_map map;
4327         int ret = 0;
4328
4329         if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4330                 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4331                 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4332                 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4333
4334                 if (guest) {
4335                         if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4336                                 return 1;
4337
4338                         if (!(saved_efer & EFER_SVME))
4339                                 return 1;
4340
4341                         if (kvm_vcpu_map(vcpu,
4342                                          gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4343                                 return 1;
4344
4345                         if (svm_allocate_nested(svm))
4346                                 return 1;
4347
4348                         ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, map.hva);
4349                         kvm_vcpu_unmap(vcpu, &map, true);
4350                 }
4351         }
4352
4353         return ret;
4354 }
4355
4356 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4357 {
4358         struct vcpu_svm *svm = to_svm(vcpu);
4359
4360         if (!gif_set(svm)) {
4361                 if (vgif_enabled(svm))
4362                         svm_set_intercept(svm, INTERCEPT_STGI);
4363                 /* STGI will cause a vm exit */
4364         } else {
4365                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
4366         }
4367 }
4368
4369 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4370 {
4371         bool smep, smap, is_user;
4372         unsigned long cr4;
4373
4374         /*
4375          * When the guest is an SEV-ES guest, emulation is not possible.
4376          */
4377         if (sev_es_guest(vcpu->kvm))
4378                 return false;
4379
4380         /*
4381          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4382          *
4383          * Errata:
4384          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4385          * possible that CPU microcode implementing DecodeAssist will fail
4386          * to read bytes of instruction which caused #NPF. In this case,
4387          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4388          * return 0 instead of the correct guest instruction bytes.
4389          *
4390          * This happens because CPU microcode reading instruction bytes
4391          * uses a special opcode which attempts to read data using CPL=0
4392          * priviledges. The microcode reads CS:RIP and if it hits a SMAP
4393          * fault, it gives up and returns no instruction bytes.
4394          *
4395          * Detection:
4396          * We reach here in case CPU supports DecodeAssist, raised #NPF and
4397          * returned 0 in GuestIntrBytes field of the VMCB.
4398          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4399          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4400          * in case vCPU CPL==3 (Because otherwise guest would have triggered
4401          * a SMEP fault instead of #NPF).
4402          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4403          * As most guests enable SMAP if they have also enabled SMEP, use above
4404          * logic in order to attempt minimize false-positive of detecting errata
4405          * while still preserving all cases semantic correctness.
4406          *
4407          * Workaround:
4408          * To determine what instruction the guest was executing, the hypervisor
4409          * will have to decode the instruction at the instruction pointer.
4410          *
4411          * In non SEV guest, hypervisor will be able to read the guest
4412          * memory to decode the instruction pointer when insn_len is zero
4413          * so we return true to indicate that decoding is possible.
4414          *
4415          * But in the SEV guest, the guest memory is encrypted with the
4416          * guest specific key and hypervisor will not be able to decode the
4417          * instruction pointer so we will not able to workaround it. Lets
4418          * print the error and request to kill the guest.
4419          */
4420         if (likely(!insn || insn_len))
4421                 return true;
4422
4423         /*
4424          * If RIP is invalid, go ahead with emulation which will cause an
4425          * internal error exit.
4426          */
4427         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4428                 return true;
4429
4430         cr4 = kvm_read_cr4(vcpu);
4431         smep = cr4 & X86_CR4_SMEP;
4432         smap = cr4 & X86_CR4_SMAP;
4433         is_user = svm_get_cpl(vcpu) == 3;
4434         if (smap && (!smep || is_user)) {
4435                 if (!sev_guest(vcpu->kvm))
4436                         return true;
4437
4438                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4439                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4440         }
4441
4442         return false;
4443 }
4444
4445 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4446 {
4447         struct vcpu_svm *svm = to_svm(vcpu);
4448
4449         /*
4450          * TODO: Last condition latch INIT signals on vCPU when
4451          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4452          * To properly emulate the INIT intercept,
4453          * svm_check_nested_events() should call nested_svm_vmexit()
4454          * if an INIT signal is pending.
4455          */
4456         return !gif_set(svm) ||
4457                    (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4458 }
4459
4460 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4461 {
4462         if (!sev_es_guest(vcpu->kvm))
4463                 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4464
4465         sev_vcpu_deliver_sipi_vector(vcpu, vector);
4466 }
4467
4468 static void svm_vm_destroy(struct kvm *kvm)
4469 {
4470         avic_vm_destroy(kvm);
4471         sev_vm_destroy(kvm);
4472 }
4473
4474 static int svm_vm_init(struct kvm *kvm)
4475 {
4476         if (!pause_filter_count || !pause_filter_thresh)
4477                 kvm->arch.pause_in_guest = true;
4478
4479         if (avic) {
4480                 int ret = avic_vm_init(kvm);
4481                 if (ret)
4482                         return ret;
4483         }
4484
4485         kvm_apicv_init(kvm, avic);
4486         return 0;
4487 }
4488
4489 static struct kvm_x86_ops svm_x86_ops __initdata = {
4490         .hardware_unsetup = svm_hardware_teardown,
4491         .hardware_enable = svm_hardware_enable,
4492         .hardware_disable = svm_hardware_disable,
4493         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4494         .has_emulated_msr = svm_has_emulated_msr,
4495
4496         .vcpu_create = svm_create_vcpu,
4497         .vcpu_free = svm_free_vcpu,
4498         .vcpu_reset = svm_vcpu_reset,
4499
4500         .vm_size = sizeof(struct kvm_svm),
4501         .vm_init = svm_vm_init,
4502         .vm_destroy = svm_vm_destroy,
4503
4504         .prepare_guest_switch = svm_prepare_guest_switch,
4505         .vcpu_load = svm_vcpu_load,
4506         .vcpu_put = svm_vcpu_put,
4507         .vcpu_blocking = svm_vcpu_blocking,
4508         .vcpu_unblocking = svm_vcpu_unblocking,
4509
4510         .update_exception_bitmap = svm_update_exception_bitmap,
4511         .get_msr_feature = svm_get_msr_feature,
4512         .get_msr = svm_get_msr,
4513         .set_msr = svm_set_msr,
4514         .get_segment_base = svm_get_segment_base,
4515         .get_segment = svm_get_segment,
4516         .set_segment = svm_set_segment,
4517         .get_cpl = svm_get_cpl,
4518         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4519         .set_cr0 = svm_set_cr0,
4520         .is_valid_cr4 = svm_is_valid_cr4,
4521         .set_cr4 = svm_set_cr4,
4522         .set_efer = svm_set_efer,
4523         .get_idt = svm_get_idt,
4524         .set_idt = svm_set_idt,
4525         .get_gdt = svm_get_gdt,
4526         .set_gdt = svm_set_gdt,
4527         .set_dr7 = svm_set_dr7,
4528         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4529         .cache_reg = svm_cache_reg,
4530         .get_rflags = svm_get_rflags,
4531         .set_rflags = svm_set_rflags,
4532
4533         .tlb_flush_all = svm_flush_tlb,
4534         .tlb_flush_current = svm_flush_tlb,
4535         .tlb_flush_gva = svm_flush_tlb_gva,
4536         .tlb_flush_guest = svm_flush_tlb,
4537
4538         .run = svm_vcpu_run,
4539         .handle_exit = handle_exit,
4540         .skip_emulated_instruction = skip_emulated_instruction,
4541         .update_emulated_instruction = NULL,
4542         .set_interrupt_shadow = svm_set_interrupt_shadow,
4543         .get_interrupt_shadow = svm_get_interrupt_shadow,
4544         .patch_hypercall = svm_patch_hypercall,
4545         .set_irq = svm_set_irq,
4546         .set_nmi = svm_inject_nmi,
4547         .queue_exception = svm_queue_exception,
4548         .cancel_injection = svm_cancel_injection,
4549         .interrupt_allowed = svm_interrupt_allowed,
4550         .nmi_allowed = svm_nmi_allowed,
4551         .get_nmi_mask = svm_get_nmi_mask,
4552         .set_nmi_mask = svm_set_nmi_mask,
4553         .enable_nmi_window = svm_enable_nmi_window,
4554         .enable_irq_window = svm_enable_irq_window,
4555         .update_cr8_intercept = svm_update_cr8_intercept,
4556         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4557         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4558         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4559         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4560         .load_eoi_exitmap = svm_load_eoi_exitmap,
4561         .hwapic_irr_update = svm_hwapic_irr_update,
4562         .hwapic_isr_update = svm_hwapic_isr_update,
4563         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4564         .apicv_post_state_restore = avic_post_state_restore,
4565
4566         .set_tss_addr = svm_set_tss_addr,
4567         .set_identity_map_addr = svm_set_identity_map_addr,
4568         .get_mt_mask = svm_get_mt_mask,
4569
4570         .get_exit_info = svm_get_exit_info,
4571
4572         .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4573
4574         .has_wbinvd_exit = svm_has_wbinvd_exit,
4575
4576         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4577
4578         .load_mmu_pgd = svm_load_mmu_pgd,
4579
4580         .check_intercept = svm_check_intercept,
4581         .handle_exit_irqoff = svm_handle_exit_irqoff,
4582
4583         .request_immediate_exit = __kvm_request_immediate_exit,
4584
4585         .sched_in = svm_sched_in,
4586
4587         .pmu_ops = &amd_pmu_ops,
4588         .nested_ops = &svm_nested_ops,
4589
4590         .deliver_posted_interrupt = svm_deliver_avic_intr,
4591         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4592         .update_pi_irte = svm_update_pi_irte,
4593         .setup_mce = svm_setup_mce,
4594
4595         .smi_allowed = svm_smi_allowed,
4596         .pre_enter_smm = svm_pre_enter_smm,
4597         .pre_leave_smm = svm_pre_leave_smm,
4598         .enable_smi_window = svm_enable_smi_window,
4599
4600         .mem_enc_op = svm_mem_enc_op,
4601         .mem_enc_reg_region = svm_register_enc_region,
4602         .mem_enc_unreg_region = svm_unregister_enc_region,
4603
4604         .vm_copy_enc_context_from = svm_vm_copy_asid_from,
4605
4606         .can_emulate_instruction = svm_can_emulate_instruction,
4607
4608         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4609
4610         .msr_filter_changed = svm_msr_filter_changed,
4611         .complete_emulated_msr = svm_complete_emulated_msr,
4612
4613         .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4614 };
4615
4616 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4617         .cpu_has_kvm_support = has_svm,
4618         .disabled_by_bios = is_disabled,
4619         .hardware_setup = svm_hardware_setup,
4620         .check_processor_compatibility = svm_check_processor_compat,
4621
4622         .runtime_ops = &svm_x86_ops,
4623 };
4624
4625 static int __init svm_init(void)
4626 {
4627         __unused_size_checks();
4628
4629         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4630                         __alignof__(struct vcpu_svm), THIS_MODULE);
4631 }
4632
4633 static void __exit svm_exit(void)
4634 {
4635         kvm_exit();
4636 }
4637
4638 module_init(svm_init)
4639 module_exit(svm_exit)