arch/x86/kvm/pmu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine -- Performance Monitoring Unit support
   4  *
   5  * Copyright 2015 Red Hat, Inc. and/or its affiliates.
   6  *
   7  * Authors:
   8  *   Avi Kivity   <avi@redhat.com>
   9  *   Gleb Natapov <gleb@redhat.com>
  10  *   Wei Huang    <wei@redhat.com>
  11  */
  12
  13 #include <linux/types.h>
  14 #include <linux/kvm_host.h>
  15 #include <linux/perf_event.h>
  16 #include <linux/bsearch.h>
  17 #include <linux/sort.h>
  18 #include <asm/perf_event.h>
  19 #include "x86.h"
  20 #include "cpuid.h"
  21 #include "lapic.h"
  22 #include "pmu.h"
  23
  24 /* This is enough to filter the vast majority of currently defined events. */
  25 #define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300
  26
  27 /* NOTE:
  28  * - Each perf counter is defined as "struct kvm_pmc";
  29  * - There are two types of perf counters: general purpose (gp) and fixed.
  30  *   gp counters are stored in gp_counters[] and fixed counters are stored
  31  *   in fixed_counters[] respectively. Both of them are part of "struct
  32  *   kvm_pmu";
  33  * - pmu.c understands the difference between gp counters and fixed counters.
  34  *   However AMD doesn't support fixed-counters;
  35  * - There are three types of index to access perf counters (PMC):
  36  *     1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD
  37  *        has MSR_K7_PERFCTRn.
  38  *     2. MSR Index (named idx): This normally is used by RDPMC instruction.
  39  *        For instance AMD RDPMC instruction uses 0000_0003h in ECX to access
  40  *        C001_0007h (MSR_K7_PERCTR3). Intel has a similar mechanism, except
  41  *        that it also supports fixed counters. idx can be used to as index to
  42  *        gp and fixed counters.
  43  *     3. Global PMC Index (named pmc): pmc is an index specific to PMU
  44  *        code. Each pmc, stored in kvm_pmc.idx field, is unique across
  45  *        all perf counters (both gp and fixed). The mapping relationship
  46  *        between pmc and perf counters is as the following:
  47  *        * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters
  48  *                 [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed
  49  *        * AMD:   [0 .. AMD64_NUM_COUNTERS-1] <=> gp counters
  50  */
  51
  52 static void kvm_pmi_trigger_fn(struct irq_work *irq_work)
  53 {
  54         struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work);
  55         struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
  56
  57         kvm_pmu_deliver_pmi(vcpu);
  58 }
  59
  60 static inline void __kvm_perf_overflow(struct kvm_pmc *pmc, bool in_pmi)
  61 {
  62         struct kvm_pmu *pmu = pmc_to_pmu(pmc);
  63
  64         /* Ignore counters that have been reprogrammed already. */
  65         if (test_and_set_bit(pmc->idx, pmu->reprogram_pmi))
  66                 return;
  67
  68         __set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
  69         kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
  70
  71         if (!pmc->intr)
  72                 return;
  73
  74         /*
  75          * Inject PMI. If vcpu was in a guest mode during NMI PMI
  76          * can be ejected on a guest mode re-entry. Otherwise we can't
  77          * be sure that vcpu wasn't executing hlt instruction at the
  78          * time of vmexit and is not going to re-enter guest mode until
  79          * woken up. So we should wake it, but this is impossible from
  80          * NMI context. Do it from irq work instead.
  81          */
  82         if (in_pmi && !kvm_handling_nmi_from_guest(pmc->vcpu))
  83                 irq_work_queue(&pmc_to_pmu(pmc)->irq_work);
  84         else
  85                 kvm_make_request(KVM_REQ_PMI, pmc->vcpu);
  86 }
  87
  88 static void kvm_perf_overflow(struct perf_event *perf_event,
  89                               struct perf_sample_data *data,
  90                               struct pt_regs *regs)
  91 {
  92         struct kvm_pmc *pmc = perf_event->overflow_handler_context;
  93
  94         __kvm_perf_overflow(pmc, true);
  95 }
  96
  97 static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
  98                                   u64 config, bool exclude_user,
  99                                   bool exclude_kernel, bool intr)
 100 {
 101         struct perf_event *event;
 102         struct perf_event_attr attr = {
 103                 .type = type,
 104                 .size = sizeof(attr),
 105                 .pinned = true,
 106                 .exclude_idle = true,
 107                 .exclude_host = 1,
 108                 .exclude_user = exclude_user,
 109                 .exclude_kernel = exclude_kernel,
 110                 .config = config,
 111         };
 112
 113         if (type == PERF_TYPE_HARDWARE && config >= PERF_COUNT_HW_MAX)
 114                 return;
 115
 116         attr.sample_period = get_sample_period(pmc, pmc->counter);
 117
 118         if ((attr.config & HSW_IN_TX_CHECKPOINTED) &&
 119             guest_cpuid_is_intel(pmc->vcpu)) {
 120                 /*
 121                  * HSW_IN_TX_CHECKPOINTED is not supported with nonzero
 122                  * period. Just clear the sample period so at least
 123                  * allocating the counter doesn't fail.
 124                  */
 125                 attr.sample_period = 0;
 126         }
 127
 128         event = perf_event_create_kernel_counter(&attr, -1, current,
 129                                                  kvm_perf_overflow, pmc);
 130         if (IS_ERR(event)) {
 131                 pr_debug_ratelimited("kvm_pmu: event creation failed %ld for pmc->idx = %d\n",
 132                             PTR_ERR(event), pmc->idx);
 133                 return;
 134         }
 135
 136         pmc->perf_event = event;
 137         pmc_to_pmu(pmc)->event_count++;
 138         clear_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi);
 139         pmc->is_paused = false;
 140         pmc->intr = intr;
 141 }
 142
 143 static void pmc_pause_counter(struct kvm_pmc *pmc)
 144 {
 145         u64 counter = pmc->counter;
 146
 147         if (!pmc->perf_event || pmc->is_paused)
 148                 return;
 149
 150         /* update counter, reset event value to avoid redundant accumulation */
 151         counter += perf_event_pause(pmc->perf_event, true);
 152         pmc->counter = counter & pmc_bitmask(pmc);
 153         pmc->is_paused = true;
 154 }
 155
 156 static bool pmc_resume_counter(struct kvm_pmc *pmc)
 157 {
 158         if (!pmc->perf_event)
 159                 return false;
 160
 161         /* recalibrate sample period and check if it's accepted by perf core */
 162         if (perf_event_period(pmc->perf_event,
 163                               get_sample_period(pmc, pmc->counter)))
 164                 return false;
 165
 166         /* reuse perf_event to serve as pmc_reprogram_counter() does*/
 167         perf_event_enable(pmc->perf_event);
 168         pmc->is_paused = false;
 169
 170         clear_bit(pmc->idx, (unsigned long *)&pmc_to_pmu(pmc)->reprogram_pmi);
 171         return true;
 172 }
 173
 174 static int cmp_u64(const void *a, const void *b)
 175 {
 176         return *(__u64 *)a - *(__u64 *)b;
 177 }
 178
 179 void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
 180 {
 181         u64 config;
 182         u32 type = PERF_TYPE_RAW;
 183         struct kvm *kvm = pmc->vcpu->kvm;
 184         struct kvm_pmu_event_filter *filter;
 185         struct kvm_pmu *pmu = vcpu_to_pmu(pmc->vcpu);
 186         bool allow_event = true;
 187
 188         if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
 189                 printk_once("kvm pmu: pin control bit is ignored\n");
 190
 191         pmc->eventsel = eventsel;
 192
 193         pmc_pause_counter(pmc);
 194
 195         if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc))
 196                 return;
 197
 198         filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu);
 199         if (filter) {
 200                 __u64 key = eventsel & AMD64_RAW_EVENT_MASK_NB;
 201
 202                 if (bsearch(&key, filter->events, filter->nevents,
 203                             sizeof(__u64), cmp_u64))
 204                         allow_event = filter->action == KVM_PMU_EVENT_ALLOW;
 205                 else
 206                         allow_event = filter->action == KVM_PMU_EVENT_DENY;
 207         }
 208         if (!allow_event)
 209                 return;
 210
 211         if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE |
 212                           ARCH_PERFMON_EVENTSEL_INV |
 213                           ARCH_PERFMON_EVENTSEL_CMASK |
 214                           HSW_IN_TX |
 215                           HSW_IN_TX_CHECKPOINTED))) {
 216                 config = kvm_x86_ops.pmu_ops->pmc_perf_hw_id(pmc);
 217                 if (config != PERF_COUNT_HW_MAX)
 218                         type = PERF_TYPE_HARDWARE;
 219         }
 220
 221         if (type == PERF_TYPE_RAW)
 222                 config = eventsel & pmu->raw_event_mask;
 223
 224         if (pmc->current_config == eventsel && pmc_resume_counter(pmc))
 225                 return;
 226
 227         pmc_release_perf_event(pmc);
 228
 229         pmc->current_config = eventsel;
 230         pmc_reprogram_counter(pmc, type, config,
 231                               !(eventsel & ARCH_PERFMON_EVENTSEL_USR),
 232                               !(eventsel & ARCH_PERFMON_EVENTSEL_OS),
 233                               eventsel & ARCH_PERFMON_EVENTSEL_INT);
 234 }
 235 EXPORT_SYMBOL_GPL(reprogram_gp_counter);
 236
 237 void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int idx)
 238 {
 239         unsigned en_field = ctrl & 0x3;
 240         bool pmi = ctrl & 0x8;
 241         struct kvm_pmu_event_filter *filter;
 242         struct kvm *kvm = pmc->vcpu->kvm;
 243
 244         pmc_pause_counter(pmc);
 245
 246         if (!en_field || !pmc_is_enabled(pmc))
 247                 return;
 248
 249         filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu);
 250         if (filter) {
 251                 if (filter->action == KVM_PMU_EVENT_DENY &&
 252                     test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
 253                         return;
 254                 if (filter->action == KVM_PMU_EVENT_ALLOW &&
 255                     !test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
 256                         return;
 257         }
 258
 259         if (pmc->current_config == (u64)ctrl && pmc_resume_counter(pmc))
 260                 return;
 261
 262         pmc_release_perf_event(pmc);
 263
 264         pmc->current_config = (u64)ctrl;
 265         pmc_reprogram_counter(pmc, PERF_TYPE_HARDWARE,
 266                               kvm_x86_ops.pmu_ops->pmc_perf_hw_id(pmc),
 267                               !(en_field & 0x2), /* exclude user */
 268                               !(en_field & 0x1), /* exclude kernel */
 269                               pmi);
 270 }
 271 EXPORT_SYMBOL_GPL(reprogram_fixed_counter);
 272
 273 void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx)
 274 {
 275         struct kvm_pmc *pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, pmc_idx);
 276
 277         if (!pmc)
 278                 return;
 279
 280         if (pmc_is_gp(pmc))
 281                 reprogram_gp_counter(pmc, pmc->eventsel);
 282         else {
 283                 int idx = pmc_idx - INTEL_PMC_IDX_FIXED;
 284                 u8 ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx);
 285
 286                 reprogram_fixed_counter(pmc, ctrl, idx);
 287         }
 288 }
 289 EXPORT_SYMBOL_GPL(reprogram_counter);
 290
 291 void kvm_pmu_handle_event(struct kvm_vcpu *vcpu)
 292 {
 293         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 294         int bit;
 295
 296         for_each_set_bit(bit, pmu->reprogram_pmi, X86_PMC_IDX_MAX) {
 297                 struct kvm_pmc *pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, bit);
 298
 299                 if (unlikely(!pmc || !pmc->perf_event)) {
 300                         clear_bit(bit, pmu->reprogram_pmi);
 301                         continue;
 302                 }
 303
 304                 reprogram_counter(pmu, bit);
 305         }
 306
 307         /*
 308          * Unused perf_events are only released if the corresponding MSRs
 309          * weren't accessed during the last vCPU time slice. kvm_arch_sched_in
 310          * triggers KVM_REQ_PMU if cleanup is needed.
 311          */
 312         if (unlikely(pmu->need_cleanup))
 313                 kvm_pmu_cleanup(vcpu);
 314 }
 315
 316 /* check if idx is a valid index to access PMU */
 317 bool kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
 318 {
 319         return kvm_x86_ops.pmu_ops->is_valid_rdpmc_ecx(vcpu, idx);
 320 }
 321
 322 bool is_vmware_backdoor_pmc(u32 pmc_idx)
 323 {
 324         switch (pmc_idx) {
 325         case VMWARE_BACKDOOR_PMC_HOST_TSC:
 326         case VMWARE_BACKDOOR_PMC_REAL_TIME:
 327         case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
 328                 return true;
 329         }
 330         return false;
 331 }
 332
 333 static int kvm_pmu_rdpmc_vmware(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
 334 {
 335         u64 ctr_val;
 336
 337         switch (idx) {
 338         case VMWARE_BACKDOOR_PMC_HOST_TSC:
 339                 ctr_val = rdtsc();
 340                 break;
 341         case VMWARE_BACKDOOR_PMC_REAL_TIME:
 342                 ctr_val = ktime_get_boottime_ns();
 343                 break;
 344         case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
 345                 ctr_val = ktime_get_boottime_ns() +
 346                         vcpu->kvm->arch.kvmclock_offset;
 347                 break;
 348         default:
 349                 return 1;
 350         }
 351
 352         *data = ctr_val;
 353         return 0;
 354 }
 355
 356 int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
 357 {
 358         bool fast_mode = idx & (1u << 31);
 359         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 360         struct kvm_pmc *pmc;
 361         u64 mask = fast_mode ? ~0u : ~0ull;
 362
 363         if (!pmu->version)
 364                 return 1;
 365
 366         if (is_vmware_backdoor_pmc(idx))
 367                 return kvm_pmu_rdpmc_vmware(vcpu, idx, data);
 368
 369         pmc = kvm_x86_ops.pmu_ops->rdpmc_ecx_to_pmc(vcpu, idx, &mask);
 370         if (!pmc)
 371                 return 1;
 372
 373         if (!(kvm_read_cr4(vcpu) & X86_CR4_PCE) &&
 374             (static_call(kvm_x86_get_cpl)(vcpu) != 0) &&
 375             (kvm_read_cr0(vcpu) & X86_CR0_PE))
 376                 return 1;
 377
 378         *data = pmc_read_counter(pmc) & mask;
 379         return 0;
 380 }
 381
 382 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
 383 {
 384         if (lapic_in_kernel(vcpu)) {
 385                 if (kvm_x86_ops.pmu_ops->deliver_pmi)
 386                         kvm_x86_ops.pmu_ops->deliver_pmi(vcpu);
 387                 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC);
 388         }
 389 }
 390
 391 bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
 392 {
 393         return kvm_x86_ops.pmu_ops->msr_idx_to_pmc(vcpu, msr) ||
 394                 kvm_x86_ops.pmu_ops->is_valid_msr(vcpu, msr);
 395 }
 396
 397 static void kvm_pmu_mark_pmc_in_use(struct kvm_vcpu *vcpu, u32 msr)
 398 {
 399         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 400         struct kvm_pmc *pmc = kvm_x86_ops.pmu_ops->msr_idx_to_pmc(vcpu, msr);
 401
 402         if (pmc)
 403                 __set_bit(pmc->idx, pmu->pmc_in_use);
 404 }
 405
 406 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 407 {
 408         return kvm_x86_ops.pmu_ops->get_msr(vcpu, msr_info);
 409 }
 410
 411 int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 412 {
 413         kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index);
 414         return kvm_x86_ops.pmu_ops->set_msr(vcpu, msr_info);
 415 }
 416
 417 /* refresh PMU settings. This function generally is called when underlying
 418  * settings are changed (such as changes of PMU CPUID by guest VMs), which
 419  * should rarely happen.
 420  */
 421 void kvm_pmu_refresh(struct kvm_vcpu *vcpu)
 422 {
 423         kvm_x86_ops.pmu_ops->refresh(vcpu);
 424 }
 425
 426 void kvm_pmu_reset(struct kvm_vcpu *vcpu)
 427 {
 428         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 429
 430         irq_work_sync(&pmu->irq_work);
 431         kvm_x86_ops.pmu_ops->reset(vcpu);
 432 }
 433
 434 void kvm_pmu_init(struct kvm_vcpu *vcpu)
 435 {
 436         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 437
 438         memset(pmu, 0, sizeof(*pmu));
 439         kvm_x86_ops.pmu_ops->init(vcpu);
 440         init_irq_work(&pmu->irq_work, kvm_pmi_trigger_fn);
 441         pmu->event_count = 0;
 442         pmu->need_cleanup = false;
 443         kvm_pmu_refresh(vcpu);
 444 }
 445
 446 static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc)
 447 {
 448         struct kvm_pmu *pmu = pmc_to_pmu(pmc);
 449
 450         if (pmc_is_fixed(pmc))
 451                 return fixed_ctrl_field(pmu->fixed_ctr_ctrl,
 452                         pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3;
 453
 454         return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE;
 455 }
 456
 457 /* Release perf_events for vPMCs that have been unused for a full time slice.  */
 458 void kvm_pmu_cleanup(struct kvm_vcpu *vcpu)
 459 {
 460         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 461         struct kvm_pmc *pmc = NULL;
 462         DECLARE_BITMAP(bitmask, X86_PMC_IDX_MAX);
 463         int i;
 464
 465         pmu->need_cleanup = false;
 466
 467         bitmap_andnot(bitmask, pmu->all_valid_pmc_idx,
 468                       pmu->pmc_in_use, X86_PMC_IDX_MAX);
 469
 470         for_each_set_bit(i, bitmask, X86_PMC_IDX_MAX) {
 471                 pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, i);
 472
 473                 if (pmc && pmc->perf_event && !pmc_speculative_in_use(pmc))
 474                         pmc_stop_counter(pmc);
 475         }
 476
 477         if (kvm_x86_ops.pmu_ops->cleanup)
 478                 kvm_x86_ops.pmu_ops->cleanup(vcpu);
 479
 480         bitmap_zero(pmu->pmc_in_use, X86_PMC_IDX_MAX);
 481 }
 482
 483 void kvm_pmu_destroy(struct kvm_vcpu *vcpu)
 484 {
 485         kvm_pmu_reset(vcpu);
 486 }
 487
 488 static void kvm_pmu_incr_counter(struct kvm_pmc *pmc)
 489 {
 490         struct kvm_pmu *pmu = pmc_to_pmu(pmc);
 491         u64 prev_count;
 492
 493         prev_count = pmc->counter;
 494         pmc->counter = (pmc->counter + 1) & pmc_bitmask(pmc);
 495
 496         reprogram_counter(pmu, pmc->idx);
 497         if (pmc->counter < prev_count)
 498                 __kvm_perf_overflow(pmc, false);
 499 }
 500
 501 static inline bool eventsel_match_perf_hw_id(struct kvm_pmc *pmc,
 502         unsigned int perf_hw_id)
 503 {
 504         u64 old_eventsel = pmc->eventsel;
 505         unsigned int config;
 506
 507         pmc->eventsel &= (ARCH_PERFMON_EVENTSEL_EVENT | ARCH_PERFMON_EVENTSEL_UMASK);
 508         config = kvm_x86_ops.pmu_ops->pmc_perf_hw_id(pmc);
 509         pmc->eventsel = old_eventsel;
 510         return config == perf_hw_id;
 511 }
 512
 513 static inline bool cpl_is_matched(struct kvm_pmc *pmc)
 514 {
 515         bool select_os, select_user;
 516         u64 config = pmc->current_config;
 517
 518         if (pmc_is_gp(pmc)) {
 519                 select_os = config & ARCH_PERFMON_EVENTSEL_OS;
 520                 select_user = config & ARCH_PERFMON_EVENTSEL_USR;
 521         } else {
 522                 select_os = config & 0x1;
 523                 select_user = config & 0x2;
 524         }
 525
 526         return (static_call(kvm_x86_get_cpl)(pmc->vcpu) == 0) ? select_os : select_user;
 527 }
 528
 529 void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id)
 530 {
 531         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 532         struct kvm_pmc *pmc;
 533         int i;
 534
 535         for_each_set_bit(i, pmu->all_valid_pmc_idx, X86_PMC_IDX_MAX) {
 536                 pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, i);
 537
 538                 if (!pmc || !pmc_is_enabled(pmc) || !pmc_speculative_in_use(pmc))
 539                         continue;
 540
 541                 /* Ignore checks for edge detect, pin control, invert and CMASK bits */
 542                 if (eventsel_match_perf_hw_id(pmc, perf_hw_id) && cpl_is_matched(pmc))
 543                         kvm_pmu_incr_counter(pmc);
 544         }
 545 }
 546 EXPORT_SYMBOL_GPL(kvm_pmu_trigger_event);
 547
 548 int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp)
 549 {
 550         struct kvm_pmu_event_filter tmp, *filter;
 551         size_t size;
 552         int r;
 553
 554         if (copy_from_user(&tmp, argp, sizeof(tmp)))
 555                 return -EFAULT;
 556
 557         if (tmp.action != KVM_PMU_EVENT_ALLOW &&
 558             tmp.action != KVM_PMU_EVENT_DENY)
 559                 return -EINVAL;
 560
 561         if (tmp.flags != 0)
 562                 return -EINVAL;
 563
 564         if (tmp.nevents > KVM_PMU_EVENT_FILTER_MAX_EVENTS)
 565                 return -E2BIG;
 566
 567         size = struct_size(filter, events, tmp.nevents);
 568         filter = kmalloc(size, GFP_KERNEL_ACCOUNT);
 569         if (!filter)
 570                 return -ENOMEM;
 571
 572         r = -EFAULT;
 573         if (copy_from_user(filter, argp, size))
 574                 goto cleanup;
 575
 576         /* Ensure nevents can't be changed between the user copies. */
 577         *filter = tmp;
 578
 579         /*
 580          * Sort the in-kernel list so that we can search it with bsearch.
 581          */
 582         sort(&filter->events, filter->nevents, sizeof(__u64), cmp_u64, NULL);
 583
 584         mutex_lock(&kvm->lock);
 585         filter = rcu_replace_pointer(kvm->arch.pmu_event_filter, filter,
 586                                      mutex_is_locked(&kvm->lock));
 587         mutex_unlock(&kvm->lock);
 588
 589         synchronize_srcu_expedited(&kvm->srcu);
 590         r = 0;
 591 cleanup:
 592         kfree(filter);
 593         return r;
 594 }