2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/uaccess.h>
40 #include <linux/hash.h>
43 #include <asm/cmpxchg.h>
46 #include <asm/kvm_page_track.h>
49 * When setting this variable to true it enables Two-Dimensional-Paging
50 * where the hardware walks 2 page tables:
51 * 1. the guest-virtual to guest-physical
52 * 2. while doing 1. it walks guest-physical to host-physical
53 * If the hardware supports that we don't need to do shadow paging.
55 bool tdp_enabled = false;
59 AUDIT_POST_PAGE_FAULT,
70 module_param(dbg, bool, 0644);
72 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
73 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
74 #define MMU_WARN_ON(x) WARN_ON(x)
76 #define pgprintk(x...) do { } while (0)
77 #define rmap_printk(x...) do { } while (0)
78 #define MMU_WARN_ON(x) do { } while (0)
81 #define PTE_PREFETCH_NUM 8
83 #define PT_FIRST_AVAIL_BITS_SHIFT 10
84 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
86 #define PT64_LEVEL_BITS 9
88 #define PT64_LEVEL_SHIFT(level) \
89 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
91 #define PT64_INDEX(address, level)\
92 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
95 #define PT32_LEVEL_BITS 10
97 #define PT32_LEVEL_SHIFT(level) \
98 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
100 #define PT32_LVL_OFFSET_MASK(level) \
101 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
102 * PT32_LEVEL_BITS))) - 1))
104 #define PT32_INDEX(address, level)\
105 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
108 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
109 #define PT64_DIR_BASE_ADDR_MASK \
110 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
111 #define PT64_LVL_ADDR_MASK(level) \
112 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
113 * PT64_LEVEL_BITS))) - 1))
114 #define PT64_LVL_OFFSET_MASK(level) \
115 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
116 * PT64_LEVEL_BITS))) - 1))
118 #define PT32_BASE_ADDR_MASK PAGE_MASK
119 #define PT32_DIR_BASE_ADDR_MASK \
120 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
121 #define PT32_LVL_ADDR_MASK(level) \
122 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT32_LEVEL_BITS))) - 1))
125 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
126 | shadow_x_mask | shadow_nx_mask)
128 #define ACC_EXEC_MASK 1
129 #define ACC_WRITE_MASK PT_WRITABLE_MASK
130 #define ACC_USER_MASK PT_USER_MASK
131 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
133 #include <trace/events/kvm.h>
135 #define CREATE_TRACE_POINTS
136 #include "mmutrace.h"
138 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
139 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
141 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
143 /* make pte_list_desc fit well in cache line */
144 #define PTE_LIST_EXT 3
146 struct pte_list_desc {
147 u64 *sptes[PTE_LIST_EXT];
148 struct pte_list_desc *more;
151 struct kvm_shadow_walk_iterator {
159 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
160 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
161 shadow_walk_okay(&(_walker)); \
162 shadow_walk_next(&(_walker)))
164 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
165 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
166 shadow_walk_okay(&(_walker)) && \
167 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
168 __shadow_walk_next(&(_walker), spte))
170 static struct kmem_cache *pte_list_desc_cache;
171 static struct kmem_cache *mmu_page_header_cache;
172 static struct percpu_counter kvm_total_used_mmu_pages;
174 static u64 __read_mostly shadow_nx_mask;
175 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
176 static u64 __read_mostly shadow_user_mask;
177 static u64 __read_mostly shadow_accessed_mask;
178 static u64 __read_mostly shadow_dirty_mask;
179 static u64 __read_mostly shadow_mmio_mask;
180 static u64 __read_mostly shadow_present_mask;
182 static void mmu_spte_set(u64 *sptep, u64 spte);
183 static void mmu_free_roots(struct kvm_vcpu *vcpu);
185 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
187 shadow_mmio_mask = mmio_mask;
189 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
192 * the low bit of the generation number is always presumed to be zero.
193 * This disables mmio caching during memslot updates. The concept is
194 * similar to a seqcount but instead of retrying the access we just punt
195 * and ignore the cache.
197 * spte bits 3-11 are used as bits 1-9 of the generation number,
198 * the bits 52-61 are used as bits 10-19 of the generation number.
200 #define MMIO_SPTE_GEN_LOW_SHIFT 2
201 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
203 #define MMIO_GEN_SHIFT 20
204 #define MMIO_GEN_LOW_SHIFT 10
205 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
206 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
208 static u64 generation_mmio_spte_mask(unsigned int gen)
212 WARN_ON(gen & ~MMIO_GEN_MASK);
214 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
215 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
219 static unsigned int get_mmio_spte_generation(u64 spte)
223 spte &= ~shadow_mmio_mask;
225 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
226 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
230 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
232 return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
235 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
238 unsigned int gen = kvm_current_mmio_generation(vcpu);
239 u64 mask = generation_mmio_spte_mask(gen);
241 access &= ACC_WRITE_MASK | ACC_USER_MASK;
242 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
244 trace_mark_mmio_spte(sptep, gfn, access, gen);
245 mmu_spte_set(sptep, mask);
248 static bool is_mmio_spte(u64 spte)
250 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
253 static gfn_t get_mmio_spte_gfn(u64 spte)
255 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
256 return (spte & ~mask) >> PAGE_SHIFT;
259 static unsigned get_mmio_spte_access(u64 spte)
261 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
262 return (spte & ~mask) & ~PAGE_MASK;
265 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
266 kvm_pfn_t pfn, unsigned access)
268 if (unlikely(is_noslot_pfn(pfn))) {
269 mark_mmio_spte(vcpu, sptep, gfn, access);
276 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
278 unsigned int kvm_gen, spte_gen;
280 kvm_gen = kvm_current_mmio_generation(vcpu);
281 spte_gen = get_mmio_spte_generation(spte);
283 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
284 return likely(kvm_gen == spte_gen);
287 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
288 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask)
290 shadow_user_mask = user_mask;
291 shadow_accessed_mask = accessed_mask;
292 shadow_dirty_mask = dirty_mask;
293 shadow_nx_mask = nx_mask;
294 shadow_x_mask = x_mask;
295 shadow_present_mask = p_mask;
297 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
299 static int is_cpuid_PSE36(void)
304 static int is_nx(struct kvm_vcpu *vcpu)
306 return vcpu->arch.efer & EFER_NX;
309 static int is_shadow_present_pte(u64 pte)
311 return (pte & 0xFFFFFFFFull) && !is_mmio_spte(pte);
314 static int is_large_pte(u64 pte)
316 return pte & PT_PAGE_SIZE_MASK;
319 static int is_last_spte(u64 pte, int level)
321 if (level == PT_PAGE_TABLE_LEVEL)
323 if (is_large_pte(pte))
328 static kvm_pfn_t spte_to_pfn(u64 pte)
330 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
333 static gfn_t pse36_gfn_delta(u32 gpte)
335 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
337 return (gpte & PT32_DIR_PSE36_MASK) << shift;
341 static void __set_spte(u64 *sptep, u64 spte)
343 WRITE_ONCE(*sptep, spte);
346 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
348 WRITE_ONCE(*sptep, spte);
351 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
353 return xchg(sptep, spte);
356 static u64 __get_spte_lockless(u64 *sptep)
358 return ACCESS_ONCE(*sptep);
369 static void count_spte_clear(u64 *sptep, u64 spte)
371 struct kvm_mmu_page *sp = page_header(__pa(sptep));
373 if (is_shadow_present_pte(spte))
376 /* Ensure the spte is completely set before we increase the count */
378 sp->clear_spte_count++;
381 static void __set_spte(u64 *sptep, u64 spte)
383 union split_spte *ssptep, sspte;
385 ssptep = (union split_spte *)sptep;
386 sspte = (union split_spte)spte;
388 ssptep->spte_high = sspte.spte_high;
391 * If we map the spte from nonpresent to present, We should store
392 * the high bits firstly, then set present bit, so cpu can not
393 * fetch this spte while we are setting the spte.
397 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
400 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
402 union split_spte *ssptep, sspte;
404 ssptep = (union split_spte *)sptep;
405 sspte = (union split_spte)spte;
407 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
410 * If we map the spte from present to nonpresent, we should clear
411 * present bit firstly to avoid vcpu fetch the old high bits.
415 ssptep->spte_high = sspte.spte_high;
416 count_spte_clear(sptep, spte);
419 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
421 union split_spte *ssptep, sspte, orig;
423 ssptep = (union split_spte *)sptep;
424 sspte = (union split_spte)spte;
426 /* xchg acts as a barrier before the setting of the high bits */
427 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
428 orig.spte_high = ssptep->spte_high;
429 ssptep->spte_high = sspte.spte_high;
430 count_spte_clear(sptep, spte);
436 * The idea using the light way get the spte on x86_32 guest is from
437 * gup_get_pte(arch/x86/mm/gup.c).
439 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
440 * coalesces them and we are running out of the MMU lock. Therefore
441 * we need to protect against in-progress updates of the spte.
443 * Reading the spte while an update is in progress may get the old value
444 * for the high part of the spte. The race is fine for a present->non-present
445 * change (because the high part of the spte is ignored for non-present spte),
446 * but for a present->present change we must reread the spte.
448 * All such changes are done in two steps (present->non-present and
449 * non-present->present), hence it is enough to count the number of
450 * present->non-present updates: if it changed while reading the spte,
451 * we might have hit the race. This is done using clear_spte_count.
453 static u64 __get_spte_lockless(u64 *sptep)
455 struct kvm_mmu_page *sp = page_header(__pa(sptep));
456 union split_spte spte, *orig = (union split_spte *)sptep;
460 count = sp->clear_spte_count;
463 spte.spte_low = orig->spte_low;
466 spte.spte_high = orig->spte_high;
469 if (unlikely(spte.spte_low != orig->spte_low ||
470 count != sp->clear_spte_count))
477 static bool spte_is_locklessly_modifiable(u64 spte)
479 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
480 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
483 static bool spte_has_volatile_bits(u64 spte)
486 * Always atomically update spte if it can be updated
487 * out of mmu-lock, it can ensure dirty bit is not lost,
488 * also, it can help us to get a stable is_writable_pte()
489 * to ensure tlb flush is not missed.
491 if (spte_is_locklessly_modifiable(spte))
494 if (!shadow_accessed_mask)
497 if (!is_shadow_present_pte(spte))
500 if ((spte & shadow_accessed_mask) &&
501 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
507 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
509 return (old_spte & bit_mask) && !(new_spte & bit_mask);
512 static bool spte_is_bit_changed(u64 old_spte, u64 new_spte, u64 bit_mask)
514 return (old_spte & bit_mask) != (new_spte & bit_mask);
517 /* Rules for using mmu_spte_set:
518 * Set the sptep from nonpresent to present.
519 * Note: the sptep being assigned *must* be either not present
520 * or in a state where the hardware will not attempt to update
523 static void mmu_spte_set(u64 *sptep, u64 new_spte)
525 WARN_ON(is_shadow_present_pte(*sptep));
526 __set_spte(sptep, new_spte);
529 /* Rules for using mmu_spte_update:
530 * Update the state bits, it means the mapped pfn is not changed.
532 * Whenever we overwrite a writable spte with a read-only one we
533 * should flush remote TLBs. Otherwise rmap_write_protect
534 * will find a read-only spte, even though the writable spte
535 * might be cached on a CPU's TLB, the return value indicates this
538 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
540 u64 old_spte = *sptep;
543 WARN_ON(!is_shadow_present_pte(new_spte));
545 if (!is_shadow_present_pte(old_spte)) {
546 mmu_spte_set(sptep, new_spte);
550 if (!spte_has_volatile_bits(old_spte))
551 __update_clear_spte_fast(sptep, new_spte);
553 old_spte = __update_clear_spte_slow(sptep, new_spte);
556 * For the spte updated out of mmu-lock is safe, since
557 * we always atomically update it, see the comments in
558 * spte_has_volatile_bits().
560 if (spte_is_locklessly_modifiable(old_spte) &&
561 !is_writable_pte(new_spte))
564 if (!shadow_accessed_mask) {
566 * We don't set page dirty when dropping non-writable spte.
567 * So do it now if the new spte is becoming non-writable.
570 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
575 * Flush TLB when accessed/dirty bits are changed in the page tables,
576 * to guarantee consistency between TLB and page tables.
578 if (spte_is_bit_changed(old_spte, new_spte,
579 shadow_accessed_mask | shadow_dirty_mask))
582 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
583 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
584 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
585 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
591 * Rules for using mmu_spte_clear_track_bits:
592 * It sets the sptep from present to nonpresent, and track the
593 * state bits, it is used to clear the last level sptep.
595 static int mmu_spte_clear_track_bits(u64 *sptep)
598 u64 old_spte = *sptep;
600 if (!spte_has_volatile_bits(old_spte))
601 __update_clear_spte_fast(sptep, 0ull);
603 old_spte = __update_clear_spte_slow(sptep, 0ull);
605 if (!is_shadow_present_pte(old_spte))
608 pfn = spte_to_pfn(old_spte);
611 * KVM does not hold the refcount of the page used by
612 * kvm mmu, before reclaiming the page, we should
613 * unmap it from mmu first.
615 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
617 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
618 kvm_set_pfn_accessed(pfn);
619 if (old_spte & (shadow_dirty_mask ? shadow_dirty_mask :
621 kvm_set_pfn_dirty(pfn);
626 * Rules for using mmu_spte_clear_no_track:
627 * Directly clear spte without caring the state bits of sptep,
628 * it is used to set the upper level spte.
630 static void mmu_spte_clear_no_track(u64 *sptep)
632 __update_clear_spte_fast(sptep, 0ull);
635 static u64 mmu_spte_get_lockless(u64 *sptep)
637 return __get_spte_lockless(sptep);
640 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
643 * Prevent page table teardown by making any free-er wait during
644 * kvm_flush_remote_tlbs() IPI to all active vcpus.
649 * Make sure a following spte read is not reordered ahead of the write
652 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
655 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
658 * Make sure the write to vcpu->mode is not reordered in front of
659 * reads to sptes. If it does, kvm_commit_zap_page() can see us
660 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
662 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
666 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
667 struct kmem_cache *base_cache, int min)
671 if (cache->nobjs >= min)
673 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
674 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
677 cache->objects[cache->nobjs++] = obj;
682 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
687 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
688 struct kmem_cache *cache)
691 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
694 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
699 if (cache->nobjs >= min)
701 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
702 page = (void *)__get_free_page(GFP_KERNEL);
705 cache->objects[cache->nobjs++] = page;
710 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
713 free_page((unsigned long)mc->objects[--mc->nobjs]);
716 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
720 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
721 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
724 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
727 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
728 mmu_page_header_cache, 4);
733 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
735 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
736 pte_list_desc_cache);
737 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
738 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
739 mmu_page_header_cache);
742 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
747 p = mc->objects[--mc->nobjs];
751 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
753 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
756 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
758 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
761 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
763 if (!sp->role.direct)
764 return sp->gfns[index];
766 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
769 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
772 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
774 sp->gfns[index] = gfn;
778 * Return the pointer to the large page information for a given gfn,
779 * handling slots that are not large page aligned.
781 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
782 struct kvm_memory_slot *slot,
787 idx = gfn_to_index(gfn, slot->base_gfn, level);
788 return &slot->arch.lpage_info[level - 2][idx];
791 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
792 gfn_t gfn, int count)
794 struct kvm_lpage_info *linfo;
797 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
798 linfo = lpage_info_slot(gfn, slot, i);
799 linfo->disallow_lpage += count;
800 WARN_ON(linfo->disallow_lpage < 0);
804 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
806 update_gfn_disallow_lpage_count(slot, gfn, 1);
809 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
811 update_gfn_disallow_lpage_count(slot, gfn, -1);
814 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
816 struct kvm_memslots *slots;
817 struct kvm_memory_slot *slot;
820 kvm->arch.indirect_shadow_pages++;
822 slots = kvm_memslots_for_spte_role(kvm, sp->role);
823 slot = __gfn_to_memslot(slots, gfn);
825 /* the non-leaf shadow pages are keeping readonly. */
826 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
827 return kvm_slot_page_track_add_page(kvm, slot, gfn,
828 KVM_PAGE_TRACK_WRITE);
830 kvm_mmu_gfn_disallow_lpage(slot, gfn);
833 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
835 struct kvm_memslots *slots;
836 struct kvm_memory_slot *slot;
839 kvm->arch.indirect_shadow_pages--;
841 slots = kvm_memslots_for_spte_role(kvm, sp->role);
842 slot = __gfn_to_memslot(slots, gfn);
843 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
844 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
845 KVM_PAGE_TRACK_WRITE);
847 kvm_mmu_gfn_allow_lpage(slot, gfn);
850 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
851 struct kvm_memory_slot *slot)
853 struct kvm_lpage_info *linfo;
856 linfo = lpage_info_slot(gfn, slot, level);
857 return !!linfo->disallow_lpage;
863 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
866 struct kvm_memory_slot *slot;
868 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
869 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
872 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
874 unsigned long page_size;
877 page_size = kvm_host_page_size(kvm, gfn);
879 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
880 if (page_size >= KVM_HPAGE_SIZE(i))
889 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
892 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
894 if (no_dirty_log && slot->dirty_bitmap)
900 static struct kvm_memory_slot *
901 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
904 struct kvm_memory_slot *slot;
906 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
907 if (!memslot_valid_for_gpte(slot, no_dirty_log))
913 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
914 bool *force_pt_level)
916 int host_level, level, max_level;
917 struct kvm_memory_slot *slot;
919 if (unlikely(*force_pt_level))
920 return PT_PAGE_TABLE_LEVEL;
922 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
923 *force_pt_level = !memslot_valid_for_gpte(slot, true);
924 if (unlikely(*force_pt_level))
925 return PT_PAGE_TABLE_LEVEL;
927 host_level = host_mapping_level(vcpu->kvm, large_gfn);
929 if (host_level == PT_PAGE_TABLE_LEVEL)
932 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
934 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
935 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
942 * About rmap_head encoding:
944 * If the bit zero of rmap_head->val is clear, then it points to the only spte
945 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
946 * pte_list_desc containing more mappings.
950 * Returns the number of pointers in the rmap chain, not counting the new one.
952 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
953 struct kvm_rmap_head *rmap_head)
955 struct pte_list_desc *desc;
958 if (!rmap_head->val) {
959 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
960 rmap_head->val = (unsigned long)spte;
961 } else if (!(rmap_head->val & 1)) {
962 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
963 desc = mmu_alloc_pte_list_desc(vcpu);
964 desc->sptes[0] = (u64 *)rmap_head->val;
965 desc->sptes[1] = spte;
966 rmap_head->val = (unsigned long)desc | 1;
969 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
970 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
971 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
973 count += PTE_LIST_EXT;
975 if (desc->sptes[PTE_LIST_EXT-1]) {
976 desc->more = mmu_alloc_pte_list_desc(vcpu);
979 for (i = 0; desc->sptes[i]; ++i)
981 desc->sptes[i] = spte;
987 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
988 struct pte_list_desc *desc, int i,
989 struct pte_list_desc *prev_desc)
993 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
995 desc->sptes[i] = desc->sptes[j];
996 desc->sptes[j] = NULL;
999 if (!prev_desc && !desc->more)
1000 rmap_head->val = (unsigned long)desc->sptes[0];
1003 prev_desc->more = desc->more;
1005 rmap_head->val = (unsigned long)desc->more | 1;
1006 mmu_free_pte_list_desc(desc);
1009 static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1011 struct pte_list_desc *desc;
1012 struct pte_list_desc *prev_desc;
1015 if (!rmap_head->val) {
1016 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
1018 } else if (!(rmap_head->val & 1)) {
1019 rmap_printk("pte_list_remove: %p 1->0\n", spte);
1020 if ((u64 *)rmap_head->val != spte) {
1021 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
1026 rmap_printk("pte_list_remove: %p many->many\n", spte);
1027 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1030 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1031 if (desc->sptes[i] == spte) {
1032 pte_list_desc_remove_entry(rmap_head,
1033 desc, i, prev_desc);
1040 pr_err("pte_list_remove: %p many->many\n", spte);
1045 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1046 struct kvm_memory_slot *slot)
1050 idx = gfn_to_index(gfn, slot->base_gfn, level);
1051 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1054 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1055 struct kvm_mmu_page *sp)
1057 struct kvm_memslots *slots;
1058 struct kvm_memory_slot *slot;
1060 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1061 slot = __gfn_to_memslot(slots, gfn);
1062 return __gfn_to_rmap(gfn, sp->role.level, slot);
1065 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1067 struct kvm_mmu_memory_cache *cache;
1069 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1070 return mmu_memory_cache_free_objects(cache);
1073 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1075 struct kvm_mmu_page *sp;
1076 struct kvm_rmap_head *rmap_head;
1078 sp = page_header(__pa(spte));
1079 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1080 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1081 return pte_list_add(vcpu, spte, rmap_head);
1084 static void rmap_remove(struct kvm *kvm, u64 *spte)
1086 struct kvm_mmu_page *sp;
1088 struct kvm_rmap_head *rmap_head;
1090 sp = page_header(__pa(spte));
1091 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1092 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1093 pte_list_remove(spte, rmap_head);
1097 * Used by the following functions to iterate through the sptes linked by a
1098 * rmap. All fields are private and not assumed to be used outside.
1100 struct rmap_iterator {
1101 /* private fields */
1102 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1103 int pos; /* index of the sptep */
1107 * Iteration must be started by this function. This should also be used after
1108 * removing/dropping sptes from the rmap link because in such cases the
1109 * information in the itererator may not be valid.
1111 * Returns sptep if found, NULL otherwise.
1113 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1114 struct rmap_iterator *iter)
1118 if (!rmap_head->val)
1121 if (!(rmap_head->val & 1)) {
1123 sptep = (u64 *)rmap_head->val;
1127 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1129 sptep = iter->desc->sptes[iter->pos];
1131 BUG_ON(!is_shadow_present_pte(*sptep));
1136 * Must be used with a valid iterator: e.g. after rmap_get_first().
1138 * Returns sptep if found, NULL otherwise.
1140 static u64 *rmap_get_next(struct rmap_iterator *iter)
1145 if (iter->pos < PTE_LIST_EXT - 1) {
1147 sptep = iter->desc->sptes[iter->pos];
1152 iter->desc = iter->desc->more;
1156 /* desc->sptes[0] cannot be NULL */
1157 sptep = iter->desc->sptes[iter->pos];
1164 BUG_ON(!is_shadow_present_pte(*sptep));
1168 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1169 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1170 _spte_; _spte_ = rmap_get_next(_iter_))
1172 static void drop_spte(struct kvm *kvm, u64 *sptep)
1174 if (mmu_spte_clear_track_bits(sptep))
1175 rmap_remove(kvm, sptep);
1179 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1181 if (is_large_pte(*sptep)) {
1182 WARN_ON(page_header(__pa(sptep))->role.level ==
1183 PT_PAGE_TABLE_LEVEL);
1184 drop_spte(kvm, sptep);
1192 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1194 if (__drop_large_spte(vcpu->kvm, sptep))
1195 kvm_flush_remote_tlbs(vcpu->kvm);
1199 * Write-protect on the specified @sptep, @pt_protect indicates whether
1200 * spte write-protection is caused by protecting shadow page table.
1202 * Note: write protection is difference between dirty logging and spte
1204 * - for dirty logging, the spte can be set to writable at anytime if
1205 * its dirty bitmap is properly set.
1206 * - for spte protection, the spte can be writable only after unsync-ing
1209 * Return true if tlb need be flushed.
1211 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1215 if (!is_writable_pte(spte) &&
1216 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1219 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1222 spte &= ~SPTE_MMU_WRITEABLE;
1223 spte = spte & ~PT_WRITABLE_MASK;
1225 return mmu_spte_update(sptep, spte);
1228 static bool __rmap_write_protect(struct kvm *kvm,
1229 struct kvm_rmap_head *rmap_head,
1233 struct rmap_iterator iter;
1236 for_each_rmap_spte(rmap_head, &iter, sptep)
1237 flush |= spte_write_protect(sptep, pt_protect);
1242 static bool spte_clear_dirty(u64 *sptep)
1246 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1248 spte &= ~shadow_dirty_mask;
1250 return mmu_spte_update(sptep, spte);
1253 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1256 struct rmap_iterator iter;
1259 for_each_rmap_spte(rmap_head, &iter, sptep)
1260 flush |= spte_clear_dirty(sptep);
1265 static bool spte_set_dirty(u64 *sptep)
1269 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1271 spte |= shadow_dirty_mask;
1273 return mmu_spte_update(sptep, spte);
1276 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1279 struct rmap_iterator iter;
1282 for_each_rmap_spte(rmap_head, &iter, sptep)
1283 flush |= spte_set_dirty(sptep);
1289 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1290 * @kvm: kvm instance
1291 * @slot: slot to protect
1292 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1293 * @mask: indicates which pages we should protect
1295 * Used when we do not need to care about huge page mappings: e.g. during dirty
1296 * logging we do not have any such mappings.
1298 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1299 struct kvm_memory_slot *slot,
1300 gfn_t gfn_offset, unsigned long mask)
1302 struct kvm_rmap_head *rmap_head;
1305 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1306 PT_PAGE_TABLE_LEVEL, slot);
1307 __rmap_write_protect(kvm, rmap_head, false);
1309 /* clear the first set bit */
1315 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages
1316 * @kvm: kvm instance
1317 * @slot: slot to clear D-bit
1318 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1319 * @mask: indicates which pages we should clear D-bit
1321 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1323 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1324 struct kvm_memory_slot *slot,
1325 gfn_t gfn_offset, unsigned long mask)
1327 struct kvm_rmap_head *rmap_head;
1330 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1331 PT_PAGE_TABLE_LEVEL, slot);
1332 __rmap_clear_dirty(kvm, rmap_head);
1334 /* clear the first set bit */
1338 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1341 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1344 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1345 * enable dirty logging for them.
1347 * Used when we do not need to care about huge page mappings: e.g. during dirty
1348 * logging we do not have any such mappings.
1350 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1351 struct kvm_memory_slot *slot,
1352 gfn_t gfn_offset, unsigned long mask)
1354 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1355 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1358 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1361 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1362 struct kvm_memory_slot *slot, u64 gfn)
1364 struct kvm_rmap_head *rmap_head;
1366 bool write_protected = false;
1368 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1369 rmap_head = __gfn_to_rmap(gfn, i, slot);
1370 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1373 return write_protected;
1376 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1378 struct kvm_memory_slot *slot;
1380 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1381 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1384 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1387 struct rmap_iterator iter;
1390 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1391 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1393 drop_spte(kvm, sptep);
1400 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1401 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1404 return kvm_zap_rmapp(kvm, rmap_head);
1407 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1408 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1412 struct rmap_iterator iter;
1415 pte_t *ptep = (pte_t *)data;
1418 WARN_ON(pte_huge(*ptep));
1419 new_pfn = pte_pfn(*ptep);
1422 for_each_rmap_spte(rmap_head, &iter, sptep) {
1423 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1424 sptep, *sptep, gfn, level);
1428 if (pte_write(*ptep)) {
1429 drop_spte(kvm, sptep);
1432 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1433 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1435 new_spte &= ~PT_WRITABLE_MASK;
1436 new_spte &= ~SPTE_HOST_WRITEABLE;
1437 new_spte &= ~shadow_accessed_mask;
1439 mmu_spte_clear_track_bits(sptep);
1440 mmu_spte_set(sptep, new_spte);
1445 kvm_flush_remote_tlbs(kvm);
1450 struct slot_rmap_walk_iterator {
1452 struct kvm_memory_slot *slot;
1458 /* output fields. */
1460 struct kvm_rmap_head *rmap;
1463 /* private field. */
1464 struct kvm_rmap_head *end_rmap;
1468 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1470 iterator->level = level;
1471 iterator->gfn = iterator->start_gfn;
1472 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1473 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1478 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1479 struct kvm_memory_slot *slot, int start_level,
1480 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1482 iterator->slot = slot;
1483 iterator->start_level = start_level;
1484 iterator->end_level = end_level;
1485 iterator->start_gfn = start_gfn;
1486 iterator->end_gfn = end_gfn;
1488 rmap_walk_init_level(iterator, iterator->start_level);
1491 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1493 return !!iterator->rmap;
1496 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1498 if (++iterator->rmap <= iterator->end_rmap) {
1499 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1503 if (++iterator->level > iterator->end_level) {
1504 iterator->rmap = NULL;
1508 rmap_walk_init_level(iterator, iterator->level);
1511 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1512 _start_gfn, _end_gfn, _iter_) \
1513 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1514 _end_level_, _start_gfn, _end_gfn); \
1515 slot_rmap_walk_okay(_iter_); \
1516 slot_rmap_walk_next(_iter_))
1518 static int kvm_handle_hva_range(struct kvm *kvm,
1519 unsigned long start,
1522 int (*handler)(struct kvm *kvm,
1523 struct kvm_rmap_head *rmap_head,
1524 struct kvm_memory_slot *slot,
1527 unsigned long data))
1529 struct kvm_memslots *slots;
1530 struct kvm_memory_slot *memslot;
1531 struct slot_rmap_walk_iterator iterator;
1535 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1536 slots = __kvm_memslots(kvm, i);
1537 kvm_for_each_memslot(memslot, slots) {
1538 unsigned long hva_start, hva_end;
1539 gfn_t gfn_start, gfn_end;
1541 hva_start = max(start, memslot->userspace_addr);
1542 hva_end = min(end, memslot->userspace_addr +
1543 (memslot->npages << PAGE_SHIFT));
1544 if (hva_start >= hva_end)
1547 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1548 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1550 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1551 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1553 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1554 PT_MAX_HUGEPAGE_LEVEL,
1555 gfn_start, gfn_end - 1,
1557 ret |= handler(kvm, iterator.rmap, memslot,
1558 iterator.gfn, iterator.level, data);
1565 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1567 int (*handler)(struct kvm *kvm,
1568 struct kvm_rmap_head *rmap_head,
1569 struct kvm_memory_slot *slot,
1570 gfn_t gfn, int level,
1571 unsigned long data))
1573 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1576 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1578 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1581 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1583 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1586 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1588 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1591 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1592 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1596 struct rmap_iterator uninitialized_var(iter);
1599 BUG_ON(!shadow_accessed_mask);
1601 for_each_rmap_spte(rmap_head, &iter, sptep) {
1602 if (*sptep & shadow_accessed_mask) {
1604 clear_bit((ffs(shadow_accessed_mask) - 1),
1605 (unsigned long *)sptep);
1609 trace_kvm_age_page(gfn, level, slot, young);
1613 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1614 struct kvm_memory_slot *slot, gfn_t gfn,
1615 int level, unsigned long data)
1618 struct rmap_iterator iter;
1622 * If there's no access bit in the secondary pte set by the
1623 * hardware it's up to gup-fast/gup to set the access bit in
1624 * the primary pte or in the page structure.
1626 if (!shadow_accessed_mask)
1629 for_each_rmap_spte(rmap_head, &iter, sptep) {
1630 if (*sptep & shadow_accessed_mask) {
1639 #define RMAP_RECYCLE_THRESHOLD 1000
1641 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1643 struct kvm_rmap_head *rmap_head;
1644 struct kvm_mmu_page *sp;
1646 sp = page_header(__pa(spte));
1648 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1650 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1651 kvm_flush_remote_tlbs(vcpu->kvm);
1654 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1657 * In case of absence of EPT Access and Dirty Bits supports,
1658 * emulate the accessed bit for EPT, by checking if this page has
1659 * an EPT mapping, and clearing it if it does. On the next access,
1660 * a new EPT mapping will be established.
1661 * This has some overhead, but not as much as the cost of swapping
1662 * out actively used pages or breaking up actively used hugepages.
1664 if (!shadow_accessed_mask)
1665 return kvm_handle_hva_range(kvm, start, end, 0,
1668 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1671 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1673 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1677 static int is_empty_shadow_page(u64 *spt)
1682 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1683 if (is_shadow_present_pte(*pos)) {
1684 printk(KERN_ERR "%s: %p %llx\n", __func__,
1693 * This value is the sum of all of the kvm instances's
1694 * kvm->arch.n_used_mmu_pages values. We need a global,
1695 * aggregate version in order to make the slab shrinker
1698 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1700 kvm->arch.n_used_mmu_pages += nr;
1701 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1704 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1706 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1707 hlist_del(&sp->hash_link);
1708 list_del(&sp->link);
1709 free_page((unsigned long)sp->spt);
1710 if (!sp->role.direct)
1711 free_page((unsigned long)sp->gfns);
1712 kmem_cache_free(mmu_page_header_cache, sp);
1715 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1717 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1720 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1721 struct kvm_mmu_page *sp, u64 *parent_pte)
1726 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1729 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1732 pte_list_remove(parent_pte, &sp->parent_ptes);
1735 static void drop_parent_pte(struct kvm_mmu_page *sp,
1738 mmu_page_remove_parent_pte(sp, parent_pte);
1739 mmu_spte_clear_no_track(parent_pte);
1742 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1744 struct kvm_mmu_page *sp;
1746 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1747 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1749 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1750 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1753 * The active_mmu_pages list is the FIFO list, do not move the
1754 * page until it is zapped. kvm_zap_obsolete_pages depends on
1755 * this feature. See the comments in kvm_zap_obsolete_pages().
1757 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1758 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1762 static void mark_unsync(u64 *spte);
1763 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1766 struct rmap_iterator iter;
1768 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1773 static void mark_unsync(u64 *spte)
1775 struct kvm_mmu_page *sp;
1778 sp = page_header(__pa(spte));
1779 index = spte - sp->spt;
1780 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1782 if (sp->unsync_children++)
1784 kvm_mmu_mark_parents_unsync(sp);
1787 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1788 struct kvm_mmu_page *sp)
1793 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1797 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1798 struct kvm_mmu_page *sp, u64 *spte,
1804 #define KVM_PAGE_ARRAY_NR 16
1806 struct kvm_mmu_pages {
1807 struct mmu_page_and_offset {
1808 struct kvm_mmu_page *sp;
1810 } page[KVM_PAGE_ARRAY_NR];
1814 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1820 for (i=0; i < pvec->nr; i++)
1821 if (pvec->page[i].sp == sp)
1824 pvec->page[pvec->nr].sp = sp;
1825 pvec->page[pvec->nr].idx = idx;
1827 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1830 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1832 --sp->unsync_children;
1833 WARN_ON((int)sp->unsync_children < 0);
1834 __clear_bit(idx, sp->unsync_child_bitmap);
1837 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1838 struct kvm_mmu_pages *pvec)
1840 int i, ret, nr_unsync_leaf = 0;
1842 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1843 struct kvm_mmu_page *child;
1844 u64 ent = sp->spt[i];
1846 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1847 clear_unsync_child_bit(sp, i);
1851 child = page_header(ent & PT64_BASE_ADDR_MASK);
1853 if (child->unsync_children) {
1854 if (mmu_pages_add(pvec, child, i))
1857 ret = __mmu_unsync_walk(child, pvec);
1859 clear_unsync_child_bit(sp, i);
1861 } else if (ret > 0) {
1862 nr_unsync_leaf += ret;
1865 } else if (child->unsync) {
1867 if (mmu_pages_add(pvec, child, i))
1870 clear_unsync_child_bit(sp, i);
1873 return nr_unsync_leaf;
1876 #define INVALID_INDEX (-1)
1878 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1879 struct kvm_mmu_pages *pvec)
1882 if (!sp->unsync_children)
1885 mmu_pages_add(pvec, sp, INVALID_INDEX);
1886 return __mmu_unsync_walk(sp, pvec);
1889 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1891 WARN_ON(!sp->unsync);
1892 trace_kvm_mmu_sync_page(sp);
1894 --kvm->stat.mmu_unsync;
1897 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1898 struct list_head *invalid_list);
1899 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1900 struct list_head *invalid_list);
1903 * NOTE: we should pay more attention on the zapped-obsolete page
1904 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1905 * since it has been deleted from active_mmu_pages but still can be found
1908 * for_each_valid_sp() has skipped that kind of pages.
1910 #define for_each_valid_sp(_kvm, _sp, _gfn) \
1911 hlist_for_each_entry(_sp, \
1912 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1913 if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \
1916 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1917 for_each_valid_sp(_kvm, _sp, _gfn) \
1918 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1920 /* @sp->gfn should be write-protected at the call site */
1921 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1922 struct list_head *invalid_list)
1924 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1925 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1929 if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) {
1930 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1937 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1938 struct list_head *invalid_list,
1939 bool remote_flush, bool local_flush)
1941 if (!list_empty(invalid_list)) {
1942 kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list);
1947 kvm_flush_remote_tlbs(vcpu->kvm);
1948 else if (local_flush)
1949 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1952 #ifdef CONFIG_KVM_MMU_AUDIT
1953 #include "mmu_audit.c"
1955 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1956 static void mmu_audit_disable(void) { }
1959 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1961 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1964 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1965 struct list_head *invalid_list)
1967 kvm_unlink_unsync_page(vcpu->kvm, sp);
1968 return __kvm_sync_page(vcpu, sp, invalid_list);
1971 /* @gfn should be write-protected at the call site */
1972 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
1973 struct list_head *invalid_list)
1975 struct kvm_mmu_page *s;
1978 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1982 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1983 ret |= kvm_sync_page(vcpu, s, invalid_list);
1989 struct mmu_page_path {
1990 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL];
1991 unsigned int idx[PT64_ROOT_LEVEL];
1994 #define for_each_sp(pvec, sp, parents, i) \
1995 for (i = mmu_pages_first(&pvec, &parents); \
1996 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1997 i = mmu_pages_next(&pvec, &parents, i))
1999 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2000 struct mmu_page_path *parents,
2005 for (n = i+1; n < pvec->nr; n++) {
2006 struct kvm_mmu_page *sp = pvec->page[n].sp;
2007 unsigned idx = pvec->page[n].idx;
2008 int level = sp->role.level;
2010 parents->idx[level-1] = idx;
2011 if (level == PT_PAGE_TABLE_LEVEL)
2014 parents->parent[level-2] = sp;
2020 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2021 struct mmu_page_path *parents)
2023 struct kvm_mmu_page *sp;
2029 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2031 sp = pvec->page[0].sp;
2032 level = sp->role.level;
2033 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2035 parents->parent[level-2] = sp;
2037 /* Also set up a sentinel. Further entries in pvec are all
2038 * children of sp, so this element is never overwritten.
2040 parents->parent[level-1] = NULL;
2041 return mmu_pages_next(pvec, parents, 0);
2044 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2046 struct kvm_mmu_page *sp;
2047 unsigned int level = 0;
2050 unsigned int idx = parents->idx[level];
2051 sp = parents->parent[level];
2055 WARN_ON(idx == INVALID_INDEX);
2056 clear_unsync_child_bit(sp, idx);
2058 } while (!sp->unsync_children);
2061 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2062 struct kvm_mmu_page *parent)
2065 struct kvm_mmu_page *sp;
2066 struct mmu_page_path parents;
2067 struct kvm_mmu_pages pages;
2068 LIST_HEAD(invalid_list);
2071 while (mmu_unsync_walk(parent, &pages)) {
2072 bool protected = false;
2074 for_each_sp(pages, sp, parents, i)
2075 protected |= rmap_write_protect(vcpu, sp->gfn);
2078 kvm_flush_remote_tlbs(vcpu->kvm);
2082 for_each_sp(pages, sp, parents, i) {
2083 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2084 mmu_pages_clear_parents(&parents);
2086 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2087 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2088 cond_resched_lock(&vcpu->kvm->mmu_lock);
2093 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2096 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2098 atomic_set(&sp->write_flooding_count, 0);
2101 static void clear_sp_write_flooding_count(u64 *spte)
2103 struct kvm_mmu_page *sp = page_header(__pa(spte));
2105 __clear_sp_write_flooding_count(sp);
2108 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2115 union kvm_mmu_page_role role;
2117 struct kvm_mmu_page *sp;
2118 bool need_sync = false;
2121 LIST_HEAD(invalid_list);
2123 role = vcpu->arch.mmu.base_role;
2125 role.direct = direct;
2128 role.access = access;
2129 if (!vcpu->arch.mmu.direct_map
2130 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2131 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2132 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2133 role.quadrant = quadrant;
2135 for_each_valid_sp(vcpu->kvm, sp, gfn) {
2136 if (sp->gfn != gfn) {
2141 if (!need_sync && sp->unsync)
2144 if (sp->role.word != role.word)
2148 /* The page is good, but __kvm_sync_page might still end
2149 * up zapping it. If so, break in order to rebuild it.
2151 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2154 WARN_ON(!list_empty(&invalid_list));
2155 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2158 if (sp->unsync_children)
2159 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2161 __clear_sp_write_flooding_count(sp);
2162 trace_kvm_mmu_get_page(sp, false);
2166 ++vcpu->kvm->stat.mmu_cache_miss;
2168 sp = kvm_mmu_alloc_page(vcpu, direct);
2172 hlist_add_head(&sp->hash_link,
2173 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2176 * we should do write protection before syncing pages
2177 * otherwise the content of the synced shadow page may
2178 * be inconsistent with guest page table.
2180 account_shadowed(vcpu->kvm, sp);
2181 if (level == PT_PAGE_TABLE_LEVEL &&
2182 rmap_write_protect(vcpu, gfn))
2183 kvm_flush_remote_tlbs(vcpu->kvm);
2185 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2186 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2188 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2189 clear_page(sp->spt);
2190 trace_kvm_mmu_get_page(sp, true);
2192 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2194 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2195 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2199 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2200 struct kvm_vcpu *vcpu, u64 addr)
2202 iterator->addr = addr;
2203 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2204 iterator->level = vcpu->arch.mmu.shadow_root_level;
2206 if (iterator->level == PT64_ROOT_LEVEL &&
2207 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2208 !vcpu->arch.mmu.direct_map)
2211 if (iterator->level == PT32E_ROOT_LEVEL) {
2212 iterator->shadow_addr
2213 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2214 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2216 if (!iterator->shadow_addr)
2217 iterator->level = 0;
2221 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2223 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2226 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2227 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2231 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2234 if (is_last_spte(spte, iterator->level)) {
2235 iterator->level = 0;
2239 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2243 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2245 return __shadow_walk_next(iterator, *iterator->sptep);
2248 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2249 struct kvm_mmu_page *sp)
2253 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2255 spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2256 shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
2258 mmu_spte_set(sptep, spte);
2260 mmu_page_add_parent_pte(vcpu, sp, sptep);
2262 if (sp->unsync_children || sp->unsync)
2266 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2267 unsigned direct_access)
2269 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2270 struct kvm_mmu_page *child;
2273 * For the direct sp, if the guest pte's dirty bit
2274 * changed form clean to dirty, it will corrupt the
2275 * sp's access: allow writable in the read-only sp,
2276 * so we should update the spte at this point to get
2277 * a new sp with the correct access.
2279 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2280 if (child->role.access == direct_access)
2283 drop_parent_pte(child, sptep);
2284 kvm_flush_remote_tlbs(vcpu->kvm);
2288 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2292 struct kvm_mmu_page *child;
2295 if (is_shadow_present_pte(pte)) {
2296 if (is_last_spte(pte, sp->role.level)) {
2297 drop_spte(kvm, spte);
2298 if (is_large_pte(pte))
2301 child = page_header(pte & PT64_BASE_ADDR_MASK);
2302 drop_parent_pte(child, spte);
2307 if (is_mmio_spte(pte))
2308 mmu_spte_clear_no_track(spte);
2313 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2314 struct kvm_mmu_page *sp)
2318 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2319 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2322 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2325 struct rmap_iterator iter;
2327 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2328 drop_parent_pte(sp, sptep);
2331 static int mmu_zap_unsync_children(struct kvm *kvm,
2332 struct kvm_mmu_page *parent,
2333 struct list_head *invalid_list)
2336 struct mmu_page_path parents;
2337 struct kvm_mmu_pages pages;
2339 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2342 while (mmu_unsync_walk(parent, &pages)) {
2343 struct kvm_mmu_page *sp;
2345 for_each_sp(pages, sp, parents, i) {
2346 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2347 mmu_pages_clear_parents(&parents);
2355 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2356 struct list_head *invalid_list)
2360 trace_kvm_mmu_prepare_zap_page(sp);
2361 ++kvm->stat.mmu_shadow_zapped;
2362 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2363 kvm_mmu_page_unlink_children(kvm, sp);
2364 kvm_mmu_unlink_parents(kvm, sp);
2366 if (!sp->role.invalid && !sp->role.direct)
2367 unaccount_shadowed(kvm, sp);
2370 kvm_unlink_unsync_page(kvm, sp);
2371 if (!sp->root_count) {
2374 list_move(&sp->link, invalid_list);
2375 kvm_mod_used_mmu_pages(kvm, -1);
2377 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2380 * The obsolete pages can not be used on any vcpus.
2381 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2383 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2384 kvm_reload_remote_mmus(kvm);
2387 sp->role.invalid = 1;
2391 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2392 struct list_head *invalid_list)
2394 struct kvm_mmu_page *sp, *nsp;
2396 if (list_empty(invalid_list))
2400 * We need to make sure everyone sees our modifications to
2401 * the page tables and see changes to vcpu->mode here. The barrier
2402 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2403 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2405 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2406 * guest mode and/or lockless shadow page table walks.
2408 kvm_flush_remote_tlbs(kvm);
2410 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2411 WARN_ON(!sp->role.invalid || sp->root_count);
2412 kvm_mmu_free_page(sp);
2416 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2417 struct list_head *invalid_list)
2419 struct kvm_mmu_page *sp;
2421 if (list_empty(&kvm->arch.active_mmu_pages))
2424 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2425 struct kvm_mmu_page, link);
2426 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2432 * Changing the number of mmu pages allocated to the vm
2433 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2435 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2437 LIST_HEAD(invalid_list);
2439 spin_lock(&kvm->mmu_lock);
2441 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2442 /* Need to free some mmu pages to achieve the goal. */
2443 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2444 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2447 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2448 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2451 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2453 spin_unlock(&kvm->mmu_lock);
2456 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2458 struct kvm_mmu_page *sp;
2459 LIST_HEAD(invalid_list);
2462 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2464 spin_lock(&kvm->mmu_lock);
2465 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2466 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2469 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2471 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2472 spin_unlock(&kvm->mmu_lock);
2476 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2478 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2480 trace_kvm_mmu_unsync_page(sp);
2481 ++vcpu->kvm->stat.mmu_unsync;
2484 kvm_mmu_mark_parents_unsync(sp);
2487 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2490 struct kvm_mmu_page *sp;
2492 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2495 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2502 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2503 kvm_unsync_page(vcpu, sp);
2509 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2512 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn));
2517 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2518 unsigned pte_access, int level,
2519 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2520 bool can_unsync, bool host_writable)
2525 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2529 * For the EPT case, shadow_present_mask is 0 if hardware
2530 * supports exec-only page table entries. In that case,
2531 * ACC_USER_MASK and shadow_user_mask are used to represent
2532 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2534 spte |= shadow_present_mask;
2536 spte |= shadow_accessed_mask;
2538 if (pte_access & ACC_EXEC_MASK)
2539 spte |= shadow_x_mask;
2541 spte |= shadow_nx_mask;
2543 if (pte_access & ACC_USER_MASK)
2544 spte |= shadow_user_mask;
2546 if (level > PT_PAGE_TABLE_LEVEL)
2547 spte |= PT_PAGE_SIZE_MASK;
2549 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2550 kvm_is_mmio_pfn(pfn));
2553 spte |= SPTE_HOST_WRITEABLE;
2555 pte_access &= ~ACC_WRITE_MASK;
2557 spte |= (u64)pfn << PAGE_SHIFT;
2559 if (pte_access & ACC_WRITE_MASK) {
2562 * Other vcpu creates new sp in the window between
2563 * mapping_level() and acquiring mmu-lock. We can
2564 * allow guest to retry the access, the mapping can
2565 * be fixed if guest refault.
2567 if (level > PT_PAGE_TABLE_LEVEL &&
2568 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2571 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2574 * Optimization: for pte sync, if spte was writable the hash
2575 * lookup is unnecessary (and expensive). Write protection
2576 * is responsibility of mmu_get_page / kvm_sync_page.
2577 * Same reasoning can be applied to dirty page accounting.
2579 if (!can_unsync && is_writable_pte(*sptep))
2582 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2583 pgprintk("%s: found shadow page for %llx, marking ro\n",
2586 pte_access &= ~ACC_WRITE_MASK;
2587 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2591 if (pte_access & ACC_WRITE_MASK) {
2592 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2593 spte |= shadow_dirty_mask;
2597 if (mmu_spte_update(sptep, spte))
2598 kvm_flush_remote_tlbs(vcpu->kvm);
2603 static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2604 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2605 bool speculative, bool host_writable)
2607 int was_rmapped = 0;
2609 bool emulate = false;
2611 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2612 *sptep, write_fault, gfn);
2614 if (is_shadow_present_pte(*sptep)) {
2616 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2617 * the parent of the now unreachable PTE.
2619 if (level > PT_PAGE_TABLE_LEVEL &&
2620 !is_large_pte(*sptep)) {
2621 struct kvm_mmu_page *child;
2624 child = page_header(pte & PT64_BASE_ADDR_MASK);
2625 drop_parent_pte(child, sptep);
2626 kvm_flush_remote_tlbs(vcpu->kvm);
2627 } else if (pfn != spte_to_pfn(*sptep)) {
2628 pgprintk("hfn old %llx new %llx\n",
2629 spte_to_pfn(*sptep), pfn);
2630 drop_spte(vcpu->kvm, sptep);
2631 kvm_flush_remote_tlbs(vcpu->kvm);
2636 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2637 true, host_writable)) {
2640 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2643 if (unlikely(is_mmio_spte(*sptep)))
2646 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2647 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2648 is_large_pte(*sptep)? "2MB" : "4kB",
2649 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2651 if (!was_rmapped && is_large_pte(*sptep))
2652 ++vcpu->kvm->stat.lpages;
2654 if (is_shadow_present_pte(*sptep)) {
2656 rmap_count = rmap_add(vcpu, sptep, gfn);
2657 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2658 rmap_recycle(vcpu, sptep, gfn);
2662 kvm_release_pfn_clean(pfn);
2667 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2670 struct kvm_memory_slot *slot;
2672 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2674 return KVM_PFN_ERR_FAULT;
2676 return gfn_to_pfn_memslot_atomic(slot, gfn);
2679 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2680 struct kvm_mmu_page *sp,
2681 u64 *start, u64 *end)
2683 struct page *pages[PTE_PREFETCH_NUM];
2684 struct kvm_memory_slot *slot;
2685 unsigned access = sp->role.access;
2689 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2690 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2694 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2698 for (i = 0; i < ret; i++, gfn++, start++)
2699 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
2700 page_to_pfn(pages[i]), true, true);
2705 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2706 struct kvm_mmu_page *sp, u64 *sptep)
2708 u64 *spte, *start = NULL;
2711 WARN_ON(!sp->role.direct);
2713 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2716 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2717 if (is_shadow_present_pte(*spte) || spte == sptep) {
2720 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2728 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2730 struct kvm_mmu_page *sp;
2733 * Since it's no accessed bit on EPT, it's no way to
2734 * distinguish between actually accessed translations
2735 * and prefetched, so disable pte prefetch if EPT is
2738 if (!shadow_accessed_mask)
2741 sp = page_header(__pa(sptep));
2742 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2745 __direct_pte_prefetch(vcpu, sp, sptep);
2748 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
2749 int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
2751 struct kvm_shadow_walk_iterator iterator;
2752 struct kvm_mmu_page *sp;
2756 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2759 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2760 if (iterator.level == level) {
2761 emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2762 write, level, gfn, pfn, prefault,
2764 direct_pte_prefetch(vcpu, iterator.sptep);
2765 ++vcpu->stat.pf_fixed;
2769 drop_large_spte(vcpu, iterator.sptep);
2770 if (!is_shadow_present_pte(*iterator.sptep)) {
2771 u64 base_addr = iterator.addr;
2773 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2774 pseudo_gfn = base_addr >> PAGE_SHIFT;
2775 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2776 iterator.level - 1, 1, ACC_ALL);
2778 link_shadow_page(vcpu, iterator.sptep, sp);
2784 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2788 info.si_signo = SIGBUS;
2790 info.si_code = BUS_MCEERR_AR;
2791 info.si_addr = (void __user *)address;
2792 info.si_addr_lsb = PAGE_SHIFT;
2794 send_sig_info(SIGBUS, &info, tsk);
2797 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2800 * Do not cache the mmio info caused by writing the readonly gfn
2801 * into the spte otherwise read access on readonly gfn also can
2802 * caused mmio page fault and treat it as mmio access.
2803 * Return 1 to tell kvm to emulate it.
2805 if (pfn == KVM_PFN_ERR_RO_FAULT)
2808 if (pfn == KVM_PFN_ERR_HWPOISON) {
2809 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2816 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2817 gfn_t *gfnp, kvm_pfn_t *pfnp,
2820 kvm_pfn_t pfn = *pfnp;
2822 int level = *levelp;
2825 * Check if it's a transparent hugepage. If this would be an
2826 * hugetlbfs page, level wouldn't be set to
2827 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2830 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
2831 level == PT_PAGE_TABLE_LEVEL &&
2832 PageTransCompoundMap(pfn_to_page(pfn)) &&
2833 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
2836 * mmu_notifier_retry was successful and we hold the
2837 * mmu_lock here, so the pmd can't become splitting
2838 * from under us, and in turn
2839 * __split_huge_page_refcount() can't run from under
2840 * us and we can safely transfer the refcount from
2841 * PG_tail to PG_head as we switch the pfn to tail to
2844 *levelp = level = PT_DIRECTORY_LEVEL;
2845 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2846 VM_BUG_ON((gfn & mask) != (pfn & mask));
2850 kvm_release_pfn_clean(pfn);
2858 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2859 kvm_pfn_t pfn, unsigned access, int *ret_val)
2861 /* The pfn is invalid, report the error! */
2862 if (unlikely(is_error_pfn(pfn))) {
2863 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2867 if (unlikely(is_noslot_pfn(pfn)))
2868 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2873 static bool page_fault_can_be_fast(u32 error_code)
2876 * Do not fix the mmio spte with invalid generation number which
2877 * need to be updated by slow page fault path.
2879 if (unlikely(error_code & PFERR_RSVD_MASK))
2883 * #PF can be fast only if the shadow page table is present and it
2884 * is caused by write-protect, that means we just need change the
2885 * W bit of the spte which can be done out of mmu-lock.
2887 if (!(error_code & PFERR_PRESENT_MASK) ||
2888 !(error_code & PFERR_WRITE_MASK))
2895 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2896 u64 *sptep, u64 spte)
2900 WARN_ON(!sp->role.direct);
2903 * The gfn of direct spte is stable since it is calculated
2906 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2909 * Theoretically we could also set dirty bit (and flush TLB) here in
2910 * order to eliminate unnecessary PML logging. See comments in
2911 * set_spte. But fast_page_fault is very unlikely to happen with PML
2912 * enabled, so we do not do this. This might result in the same GPA
2913 * to be logged in PML buffer again when the write really happens, and
2914 * eventually to be called by mark_page_dirty twice. But it's also no
2915 * harm. This also avoids the TLB flush needed after setting dirty bit
2916 * so non-PML cases won't be impacted.
2918 * Compare with set_spte where instead shadow_dirty_mask is set.
2920 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2921 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2928 * - true: let the vcpu to access on the same address again.
2929 * - false: let the real page fault path to fix it.
2931 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2934 struct kvm_shadow_walk_iterator iterator;
2935 struct kvm_mmu_page *sp;
2939 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2942 if (!page_fault_can_be_fast(error_code))
2945 walk_shadow_page_lockless_begin(vcpu);
2946 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2947 if (!is_shadow_present_pte(spte) || iterator.level < level)
2951 * If the mapping has been changed, let the vcpu fault on the
2952 * same address again.
2954 if (!is_shadow_present_pte(spte)) {
2959 sp = page_header(__pa(iterator.sptep));
2960 if (!is_last_spte(spte, sp->role.level))
2964 * Check if it is a spurious fault caused by TLB lazily flushed.
2966 * Need not check the access of upper level table entries since
2967 * they are always ACC_ALL.
2969 if (is_writable_pte(spte)) {
2975 * Currently, to simplify the code, only the spte write-protected
2976 * by dirty-log can be fast fixed.
2978 if (!spte_is_locklessly_modifiable(spte))
2982 * Do not fix write-permission on the large spte since we only dirty
2983 * the first page into the dirty-bitmap in fast_pf_fix_direct_spte()
2984 * that means other pages are missed if its slot is dirty-logged.
2986 * Instead, we let the slow page fault path create a normal spte to
2989 * See the comments in kvm_arch_commit_memory_region().
2991 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2995 * Currently, fast page fault only works for direct mapping since
2996 * the gfn is not stable for indirect shadow page.
2997 * See Documentation/virtual/kvm/locking.txt to get more detail.
2999 ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte);
3001 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
3003 walk_shadow_page_lockless_end(vcpu);
3008 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3009 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
3010 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
3012 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3013 gfn_t gfn, bool prefault)
3017 bool force_pt_level = false;
3019 unsigned long mmu_seq;
3020 bool map_writable, write = error_code & PFERR_WRITE_MASK;
3022 level = mapping_level(vcpu, gfn, &force_pt_level);
3023 if (likely(!force_pt_level)) {
3025 * This path builds a PAE pagetable - so we can map
3026 * 2mb pages at maximum. Therefore check if the level
3027 * is larger than that.
3029 if (level > PT_DIRECTORY_LEVEL)
3030 level = PT_DIRECTORY_LEVEL;
3032 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3035 if (fast_page_fault(vcpu, v, level, error_code))
3038 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3041 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3044 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3047 spin_lock(&vcpu->kvm->mmu_lock);
3048 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3050 make_mmu_pages_available(vcpu);
3051 if (likely(!force_pt_level))
3052 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3053 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3054 spin_unlock(&vcpu->kvm->mmu_lock);
3059 spin_unlock(&vcpu->kvm->mmu_lock);
3060 kvm_release_pfn_clean(pfn);
3065 static void mmu_free_roots(struct kvm_vcpu *vcpu)
3068 struct kvm_mmu_page *sp;
3069 LIST_HEAD(invalid_list);
3071 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3074 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
3075 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
3076 vcpu->arch.mmu.direct_map)) {
3077 hpa_t root = vcpu->arch.mmu.root_hpa;
3079 spin_lock(&vcpu->kvm->mmu_lock);
3080 sp = page_header(root);
3082 if (!sp->root_count && sp->role.invalid) {
3083 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3084 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3086 spin_unlock(&vcpu->kvm->mmu_lock);
3087 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3091 spin_lock(&vcpu->kvm->mmu_lock);
3092 for (i = 0; i < 4; ++i) {
3093 hpa_t root = vcpu->arch.mmu.pae_root[i];
3096 root &= PT64_BASE_ADDR_MASK;
3097 sp = page_header(root);
3099 if (!sp->root_count && sp->role.invalid)
3100 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3103 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3105 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3106 spin_unlock(&vcpu->kvm->mmu_lock);
3107 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3110 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3114 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3115 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3122 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3124 struct kvm_mmu_page *sp;
3127 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3128 spin_lock(&vcpu->kvm->mmu_lock);
3129 make_mmu_pages_available(vcpu);
3130 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL);
3132 spin_unlock(&vcpu->kvm->mmu_lock);
3133 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3134 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3135 for (i = 0; i < 4; ++i) {
3136 hpa_t root = vcpu->arch.mmu.pae_root[i];
3138 MMU_WARN_ON(VALID_PAGE(root));
3139 spin_lock(&vcpu->kvm->mmu_lock);
3140 make_mmu_pages_available(vcpu);
3141 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3142 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3143 root = __pa(sp->spt);
3145 spin_unlock(&vcpu->kvm->mmu_lock);
3146 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3148 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3155 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3157 struct kvm_mmu_page *sp;
3162 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3164 if (mmu_check_root(vcpu, root_gfn))
3168 * Do we shadow a long mode page table? If so we need to
3169 * write-protect the guests page table root.
3171 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3172 hpa_t root = vcpu->arch.mmu.root_hpa;
3174 MMU_WARN_ON(VALID_PAGE(root));
3176 spin_lock(&vcpu->kvm->mmu_lock);
3177 make_mmu_pages_available(vcpu);
3178 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3180 root = __pa(sp->spt);
3182 spin_unlock(&vcpu->kvm->mmu_lock);
3183 vcpu->arch.mmu.root_hpa = root;
3188 * We shadow a 32 bit page table. This may be a legacy 2-level
3189 * or a PAE 3-level page table. In either case we need to be aware that
3190 * the shadow page table may be a PAE or a long mode page table.
3192 pm_mask = PT_PRESENT_MASK;
3193 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3194 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3196 for (i = 0; i < 4; ++i) {
3197 hpa_t root = vcpu->arch.mmu.pae_root[i];
3199 MMU_WARN_ON(VALID_PAGE(root));
3200 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3201 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3202 if (!(pdptr & PT_PRESENT_MASK)) {
3203 vcpu->arch.mmu.pae_root[i] = 0;
3206 root_gfn = pdptr >> PAGE_SHIFT;
3207 if (mmu_check_root(vcpu, root_gfn))
3210 spin_lock(&vcpu->kvm->mmu_lock);
3211 make_mmu_pages_available(vcpu);
3212 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3214 root = __pa(sp->spt);
3216 spin_unlock(&vcpu->kvm->mmu_lock);
3218 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3220 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3223 * If we shadow a 32 bit page table with a long mode page
3224 * table we enter this path.
3226 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3227 if (vcpu->arch.mmu.lm_root == NULL) {
3229 * The additional page necessary for this is only
3230 * allocated on demand.
3235 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3236 if (lm_root == NULL)
3239 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3241 vcpu->arch.mmu.lm_root = lm_root;
3244 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3250 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3252 if (vcpu->arch.mmu.direct_map)
3253 return mmu_alloc_direct_roots(vcpu);
3255 return mmu_alloc_shadow_roots(vcpu);
3258 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3261 struct kvm_mmu_page *sp;
3263 if (vcpu->arch.mmu.direct_map)
3266 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3269 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3270 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3271 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3272 hpa_t root = vcpu->arch.mmu.root_hpa;
3273 sp = page_header(root);
3274 mmu_sync_children(vcpu, sp);
3275 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3278 for (i = 0; i < 4; ++i) {
3279 hpa_t root = vcpu->arch.mmu.pae_root[i];
3281 if (root && VALID_PAGE(root)) {
3282 root &= PT64_BASE_ADDR_MASK;
3283 sp = page_header(root);
3284 mmu_sync_children(vcpu, sp);
3287 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3290 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3292 spin_lock(&vcpu->kvm->mmu_lock);
3293 mmu_sync_roots(vcpu);
3294 spin_unlock(&vcpu->kvm->mmu_lock);
3296 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3298 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3299 u32 access, struct x86_exception *exception)
3302 exception->error_code = 0;
3306 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3308 struct x86_exception *exception)
3311 exception->error_code = 0;
3312 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3316 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3318 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3320 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3321 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3324 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3326 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3329 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3331 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3334 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3337 return vcpu_match_mmio_gpa(vcpu, addr);
3339 return vcpu_match_mmio_gva(vcpu, addr);
3342 /* return true if reserved bit is detected on spte. */
3344 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3346 struct kvm_shadow_walk_iterator iterator;
3347 u64 sptes[PT64_ROOT_LEVEL], spte = 0ull;
3349 bool reserved = false;
3351 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3354 walk_shadow_page_lockless_begin(vcpu);
3356 for (shadow_walk_init(&iterator, vcpu, addr),
3357 leaf = root = iterator.level;
3358 shadow_walk_okay(&iterator);
3359 __shadow_walk_next(&iterator, spte)) {
3360 spte = mmu_spte_get_lockless(iterator.sptep);
3362 sptes[leaf - 1] = spte;
3365 if (!is_shadow_present_pte(spte))
3368 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
3372 walk_shadow_page_lockless_end(vcpu);
3375 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3377 while (root > leaf) {
3378 pr_err("------ spte 0x%llx level %d.\n",
3379 sptes[root - 1], root);
3388 int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3393 if (mmio_info_in_cache(vcpu, addr, direct))
3394 return RET_MMIO_PF_EMULATE;
3396 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3397 if (WARN_ON(reserved))
3398 return RET_MMIO_PF_BUG;
3400 if (is_mmio_spte(spte)) {
3401 gfn_t gfn = get_mmio_spte_gfn(spte);
3402 unsigned access = get_mmio_spte_access(spte);
3404 if (!check_mmio_spte(vcpu, spte))
3405 return RET_MMIO_PF_INVALID;
3410 trace_handle_mmio_page_fault(addr, gfn, access);
3411 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3412 return RET_MMIO_PF_EMULATE;
3416 * If the page table is zapped by other cpus, let CPU fault again on
3419 return RET_MMIO_PF_RETRY;
3421 EXPORT_SYMBOL_GPL(handle_mmio_page_fault);
3423 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3424 u32 error_code, gfn_t gfn)
3426 if (unlikely(error_code & PFERR_RSVD_MASK))
3429 if (!(error_code & PFERR_PRESENT_MASK) ||
3430 !(error_code & PFERR_WRITE_MASK))
3434 * guest is writing the page which is write tracked which can
3435 * not be fixed by page fault handler.
3437 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3443 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3445 struct kvm_shadow_walk_iterator iterator;
3448 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3451 walk_shadow_page_lockless_begin(vcpu);
3452 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3453 clear_sp_write_flooding_count(iterator.sptep);
3454 if (!is_shadow_present_pte(spte))
3457 walk_shadow_page_lockless_end(vcpu);
3460 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3461 u32 error_code, bool prefault)
3463 gfn_t gfn = gva >> PAGE_SHIFT;
3466 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3468 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3471 r = mmu_topup_memory_caches(vcpu);
3475 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3478 return nonpaging_map(vcpu, gva & PAGE_MASK,
3479 error_code, gfn, prefault);
3482 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3484 struct kvm_arch_async_pf arch;
3486 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3488 arch.direct_map = vcpu->arch.mmu.direct_map;
3489 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3491 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3494 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3496 if (unlikely(!lapic_in_kernel(vcpu) ||
3497 kvm_event_needs_reinjection(vcpu)))
3500 return kvm_x86_ops->interrupt_allowed(vcpu);
3503 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3504 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
3506 struct kvm_memory_slot *slot;
3509 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3511 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3513 return false; /* *pfn has correct page already */
3515 if (!prefault && can_do_async_pf(vcpu)) {
3516 trace_kvm_try_async_get_page(gva, gfn);
3517 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3518 trace_kvm_async_pf_doublefault(gva, gfn);
3519 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3521 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3525 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3530 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
3532 int page_num = KVM_PAGES_PER_HPAGE(level);
3534 gfn &= ~(page_num - 1);
3536 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
3539 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3545 bool force_pt_level;
3546 gfn_t gfn = gpa >> PAGE_SHIFT;
3547 unsigned long mmu_seq;
3548 int write = error_code & PFERR_WRITE_MASK;
3551 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3553 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3556 r = mmu_topup_memory_caches(vcpu);
3560 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
3561 PT_DIRECTORY_LEVEL);
3562 level = mapping_level(vcpu, gfn, &force_pt_level);
3563 if (likely(!force_pt_level)) {
3564 if (level > PT_DIRECTORY_LEVEL &&
3565 !check_hugepage_cache_consistency(vcpu, gfn, level))
3566 level = PT_DIRECTORY_LEVEL;
3567 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3570 if (fast_page_fault(vcpu, gpa, level, error_code))
3573 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3576 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3579 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3582 spin_lock(&vcpu->kvm->mmu_lock);
3583 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3585 make_mmu_pages_available(vcpu);
3586 if (likely(!force_pt_level))
3587 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3588 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3589 spin_unlock(&vcpu->kvm->mmu_lock);
3594 spin_unlock(&vcpu->kvm->mmu_lock);
3595 kvm_release_pfn_clean(pfn);
3599 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3600 struct kvm_mmu *context)
3602 context->page_fault = nonpaging_page_fault;
3603 context->gva_to_gpa = nonpaging_gva_to_gpa;
3604 context->sync_page = nonpaging_sync_page;
3605 context->invlpg = nonpaging_invlpg;
3606 context->update_pte = nonpaging_update_pte;
3607 context->root_level = 0;
3608 context->shadow_root_level = PT32E_ROOT_LEVEL;
3609 context->root_hpa = INVALID_PAGE;
3610 context->direct_map = true;
3611 context->nx = false;
3614 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3616 mmu_free_roots(vcpu);
3619 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3621 return kvm_read_cr3(vcpu);
3624 static void inject_page_fault(struct kvm_vcpu *vcpu,
3625 struct x86_exception *fault)
3627 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3630 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3631 unsigned access, int *nr_present)
3633 if (unlikely(is_mmio_spte(*sptep))) {
3634 if (gfn != get_mmio_spte_gfn(*sptep)) {
3635 mmu_spte_clear_no_track(sptep);
3640 mark_mmio_spte(vcpu, sptep, gfn, access);
3647 static inline bool is_last_gpte(struct kvm_mmu *mmu,
3648 unsigned level, unsigned gpte)
3651 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
3652 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3653 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3655 gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
3658 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3659 * If it is clear, there are no large pages at this level, so clear
3660 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3662 gpte &= level - mmu->last_nonleaf_level;
3664 return gpte & PT_PAGE_SIZE_MASK;
3667 #define PTTYPE_EPT 18 /* arbitrary */
3668 #define PTTYPE PTTYPE_EPT
3669 #include "paging_tmpl.h"
3673 #include "paging_tmpl.h"
3677 #include "paging_tmpl.h"
3681 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3682 struct rsvd_bits_validate *rsvd_check,
3683 int maxphyaddr, int level, bool nx, bool gbpages,
3686 u64 exb_bit_rsvd = 0;
3687 u64 gbpages_bit_rsvd = 0;
3688 u64 nonleaf_bit8_rsvd = 0;
3690 rsvd_check->bad_mt_xwr = 0;
3693 exb_bit_rsvd = rsvd_bits(63, 63);
3695 gbpages_bit_rsvd = rsvd_bits(7, 7);
3698 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3699 * leaf entries) on AMD CPUs only.
3702 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3705 case PT32_ROOT_LEVEL:
3706 /* no rsvd bits for 2 level 4K page table entries */
3707 rsvd_check->rsvd_bits_mask[0][1] = 0;
3708 rsvd_check->rsvd_bits_mask[0][0] = 0;
3709 rsvd_check->rsvd_bits_mask[1][0] =
3710 rsvd_check->rsvd_bits_mask[0][0];
3713 rsvd_check->rsvd_bits_mask[1][1] = 0;
3717 if (is_cpuid_PSE36())
3718 /* 36bits PSE 4MB page */
3719 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3721 /* 32 bits PSE 4MB page */
3722 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3724 case PT32E_ROOT_LEVEL:
3725 rsvd_check->rsvd_bits_mask[0][2] =
3726 rsvd_bits(maxphyaddr, 63) |
3727 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3728 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3729 rsvd_bits(maxphyaddr, 62); /* PDE */
3730 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3731 rsvd_bits(maxphyaddr, 62); /* PTE */
3732 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3733 rsvd_bits(maxphyaddr, 62) |
3734 rsvd_bits(13, 20); /* large page */
3735 rsvd_check->rsvd_bits_mask[1][0] =
3736 rsvd_check->rsvd_bits_mask[0][0];
3738 case PT64_ROOT_LEVEL:
3739 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3740 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3741 rsvd_bits(maxphyaddr, 51);
3742 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3743 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
3744 rsvd_bits(maxphyaddr, 51);
3745 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3746 rsvd_bits(maxphyaddr, 51);
3747 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3748 rsvd_bits(maxphyaddr, 51);
3749 rsvd_check->rsvd_bits_mask[1][3] =
3750 rsvd_check->rsvd_bits_mask[0][3];
3751 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3752 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3754 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3755 rsvd_bits(maxphyaddr, 51) |
3756 rsvd_bits(13, 20); /* large page */
3757 rsvd_check->rsvd_bits_mask[1][0] =
3758 rsvd_check->rsvd_bits_mask[0][0];
3763 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3764 struct kvm_mmu *context)
3766 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
3767 cpuid_maxphyaddr(vcpu), context->root_level,
3768 context->nx, guest_cpuid_has_gbpages(vcpu),
3769 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
3773 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
3774 int maxphyaddr, bool execonly)
3778 rsvd_check->rsvd_bits_mask[0][3] =
3779 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3780 rsvd_check->rsvd_bits_mask[0][2] =
3781 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3782 rsvd_check->rsvd_bits_mask[0][1] =
3783 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3784 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3787 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
3788 rsvd_check->rsvd_bits_mask[1][2] =
3789 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
3790 rsvd_check->rsvd_bits_mask[1][1] =
3791 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
3792 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
3794 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
3795 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
3796 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
3797 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
3798 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
3800 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
3801 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
3803 rsvd_check->bad_mt_xwr = bad_mt_xwr;
3806 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
3807 struct kvm_mmu *context, bool execonly)
3809 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
3810 cpuid_maxphyaddr(vcpu), execonly);
3814 * the page table on host is the shadow page table for the page
3815 * table in guest or amd nested guest, its mmu features completely
3816 * follow the features in guest.
3819 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3821 bool uses_nx = context->nx || context->base_role.smep_andnot_wp;
3824 * Passing "true" to the last argument is okay; it adds a check
3825 * on bit 8 of the SPTEs which KVM doesn't use anyway.
3827 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3828 boot_cpu_data.x86_phys_bits,
3829 context->shadow_root_level, uses_nx,
3830 guest_cpuid_has_gbpages(vcpu), is_pse(vcpu),
3833 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
3835 static inline bool boot_cpu_is_amd(void)
3837 WARN_ON_ONCE(!tdp_enabled);
3838 return shadow_x_mask == 0;
3842 * the direct page table on host, use as much mmu features as
3843 * possible, however, kvm currently does not do execution-protection.
3846 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3847 struct kvm_mmu *context)
3849 if (boot_cpu_is_amd())
3850 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3851 boot_cpu_data.x86_phys_bits,
3852 context->shadow_root_level, false,
3853 boot_cpu_has(X86_FEATURE_GBPAGES),
3856 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3857 boot_cpu_data.x86_phys_bits,
3863 * as the comments in reset_shadow_zero_bits_mask() except it
3864 * is the shadow page table for intel nested guest.
3867 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3868 struct kvm_mmu *context, bool execonly)
3870 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3871 boot_cpu_data.x86_phys_bits, execonly);
3874 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
3875 struct kvm_mmu *mmu, bool ept)
3877 unsigned bit, byte, pfec;
3879 bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
3881 cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3882 cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3883 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3886 wf = pfec & PFERR_WRITE_MASK;
3887 uf = pfec & PFERR_USER_MASK;
3888 ff = pfec & PFERR_FETCH_MASK;
3890 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
3891 * subject to SMAP restrictions, and cleared otherwise. The
3892 * bit is only meaningful if the SMAP bit is set in CR4.
3894 smapf = !(pfec & PFERR_RSVD_MASK);
3895 for (bit = 0; bit < 8; ++bit) {
3896 x = bit & ACC_EXEC_MASK;
3897 w = bit & ACC_WRITE_MASK;
3898 u = bit & ACC_USER_MASK;
3901 /* Not really needed: !nx will cause pte.nx to fault */
3903 /* Allow supervisor writes if !cr0.wp */
3904 w |= !is_write_protection(vcpu) && !uf;
3905 /* Disallow supervisor fetches of user code if cr4.smep */
3906 x &= !(cr4_smep && u && !uf);
3909 * SMAP:kernel-mode data accesses from user-mode
3910 * mappings should fault. A fault is considered
3911 * as a SMAP violation if all of the following
3912 * conditions are ture:
3913 * - X86_CR4_SMAP is set in CR4
3914 * - An user page is accessed
3915 * - Page fault in kernel mode
3916 * - if CPL = 3 or X86_EFLAGS_AC is clear
3918 * Here, we cover the first three conditions.
3919 * The fourth is computed dynamically in
3920 * permission_fault() and is in smapf.
3922 * Also, SMAP does not affect instruction
3923 * fetches, add the !ff check here to make it
3926 smap = cr4_smap && u && !uf && !ff;
3929 fault = (ff && !x) || (uf && !u) || (wf && !w) ||
3931 map |= fault << bit;
3933 mmu->permissions[byte] = map;
3938 * PKU is an additional mechanism by which the paging controls access to
3939 * user-mode addresses based on the value in the PKRU register. Protection
3940 * key violations are reported through a bit in the page fault error code.
3941 * Unlike other bits of the error code, the PK bit is not known at the
3942 * call site of e.g. gva_to_gpa; it must be computed directly in
3943 * permission_fault based on two bits of PKRU, on some machine state (CR4,
3944 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
3946 * In particular the following conditions come from the error code, the
3947 * page tables and the machine state:
3948 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
3949 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
3950 * - PK is always zero if U=0 in the page tables
3951 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
3953 * The PKRU bitmask caches the result of these four conditions. The error
3954 * code (minus the P bit) and the page table's U bit form an index into the
3955 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
3956 * with the two bits of the PKRU register corresponding to the protection key.
3957 * For the first three conditions above the bits will be 00, thus masking
3958 * away both AD and WD. For all reads or if the last condition holds, WD
3959 * only will be masked away.
3961 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3972 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
3973 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
3978 wp = is_write_protection(vcpu);
3980 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
3981 unsigned pfec, pkey_bits;
3982 bool check_pkey, check_write, ff, uf, wf, pte_user;
3985 ff = pfec & PFERR_FETCH_MASK;
3986 uf = pfec & PFERR_USER_MASK;
3987 wf = pfec & PFERR_WRITE_MASK;
3989 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
3990 pte_user = pfec & PFERR_RSVD_MASK;
3993 * Only need to check the access which is not an
3994 * instruction fetch and is to a user page.
3996 check_pkey = (!ff && pte_user);
3998 * write access is controlled by PKRU if it is a
3999 * user access or CR0.WP = 1.
4001 check_write = check_pkey && wf && (uf || wp);
4003 /* PKRU.AD stops both read and write access. */
4004 pkey_bits = !!check_pkey;
4005 /* PKRU.WD stops write access. */
4006 pkey_bits |= (!!check_write) << 1;
4008 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4012 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4014 unsigned root_level = mmu->root_level;
4016 mmu->last_nonleaf_level = root_level;
4017 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4018 mmu->last_nonleaf_level++;
4021 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4022 struct kvm_mmu *context,
4025 context->nx = is_nx(vcpu);
4026 context->root_level = level;
4028 reset_rsvds_bits_mask(vcpu, context);
4029 update_permission_bitmask(vcpu, context, false);
4030 update_pkru_bitmask(vcpu, context, false);
4031 update_last_nonleaf_level(vcpu, context);
4033 MMU_WARN_ON(!is_pae(vcpu));
4034 context->page_fault = paging64_page_fault;
4035 context->gva_to_gpa = paging64_gva_to_gpa;
4036 context->sync_page = paging64_sync_page;
4037 context->invlpg = paging64_invlpg;
4038 context->update_pte = paging64_update_pte;
4039 context->shadow_root_level = level;
4040 context->root_hpa = INVALID_PAGE;
4041 context->direct_map = false;
4044 static void paging64_init_context(struct kvm_vcpu *vcpu,
4045 struct kvm_mmu *context)
4047 paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
4050 static void paging32_init_context(struct kvm_vcpu *vcpu,
4051 struct kvm_mmu *context)
4053 context->nx = false;
4054 context->root_level = PT32_ROOT_LEVEL;
4056 reset_rsvds_bits_mask(vcpu, context);
4057 update_permission_bitmask(vcpu, context, false);
4058 update_pkru_bitmask(vcpu, context, false);
4059 update_last_nonleaf_level(vcpu, context);
4061 context->page_fault = paging32_page_fault;
4062 context->gva_to_gpa = paging32_gva_to_gpa;
4063 context->sync_page = paging32_sync_page;
4064 context->invlpg = paging32_invlpg;
4065 context->update_pte = paging32_update_pte;
4066 context->shadow_root_level = PT32E_ROOT_LEVEL;
4067 context->root_hpa = INVALID_PAGE;
4068 context->direct_map = false;
4071 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4072 struct kvm_mmu *context)
4074 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4077 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4079 struct kvm_mmu *context = &vcpu->arch.mmu;
4081 context->base_role.word = 0;
4082 context->base_role.smm = is_smm(vcpu);
4083 context->page_fault = tdp_page_fault;
4084 context->sync_page = nonpaging_sync_page;
4085 context->invlpg = nonpaging_invlpg;
4086 context->update_pte = nonpaging_update_pte;
4087 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4088 context->root_hpa = INVALID_PAGE;
4089 context->direct_map = true;
4090 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
4091 context->get_cr3 = get_cr3;
4092 context->get_pdptr = kvm_pdptr_read;
4093 context->inject_page_fault = kvm_inject_page_fault;
4095 if (!is_paging(vcpu)) {
4096 context->nx = false;
4097 context->gva_to_gpa = nonpaging_gva_to_gpa;
4098 context->root_level = 0;
4099 } else if (is_long_mode(vcpu)) {
4100 context->nx = is_nx(vcpu);
4101 context->root_level = PT64_ROOT_LEVEL;
4102 reset_rsvds_bits_mask(vcpu, context);
4103 context->gva_to_gpa = paging64_gva_to_gpa;
4104 } else if (is_pae(vcpu)) {
4105 context->nx = is_nx(vcpu);
4106 context->root_level = PT32E_ROOT_LEVEL;
4107 reset_rsvds_bits_mask(vcpu, context);
4108 context->gva_to_gpa = paging64_gva_to_gpa;
4110 context->nx = false;
4111 context->root_level = PT32_ROOT_LEVEL;
4112 reset_rsvds_bits_mask(vcpu, context);
4113 context->gva_to_gpa = paging32_gva_to_gpa;
4116 update_permission_bitmask(vcpu, context, false);
4117 update_pkru_bitmask(vcpu, context, false);
4118 update_last_nonleaf_level(vcpu, context);
4119 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4122 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4124 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4125 bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4126 struct kvm_mmu *context = &vcpu->arch.mmu;
4128 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4130 if (!is_paging(vcpu))
4131 nonpaging_init_context(vcpu, context);
4132 else if (is_long_mode(vcpu))
4133 paging64_init_context(vcpu, context);
4134 else if (is_pae(vcpu))
4135 paging32E_init_context(vcpu, context);
4137 paging32_init_context(vcpu, context);
4139 context->base_role.nxe = is_nx(vcpu);
4140 context->base_role.cr4_pae = !!is_pae(vcpu);
4141 context->base_role.cr0_wp = is_write_protection(vcpu);
4142 context->base_role.smep_andnot_wp
4143 = smep && !is_write_protection(vcpu);
4144 context->base_role.smap_andnot_wp
4145 = smap && !is_write_protection(vcpu);
4146 context->base_role.smm = is_smm(vcpu);
4147 reset_shadow_zero_bits_mask(vcpu, context);
4149 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4151 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly)
4153 struct kvm_mmu *context = &vcpu->arch.mmu;
4155 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4157 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4160 context->page_fault = ept_page_fault;
4161 context->gva_to_gpa = ept_gva_to_gpa;
4162 context->sync_page = ept_sync_page;
4163 context->invlpg = ept_invlpg;
4164 context->update_pte = ept_update_pte;
4165 context->root_level = context->shadow_root_level;
4166 context->root_hpa = INVALID_PAGE;
4167 context->direct_map = false;
4169 update_permission_bitmask(vcpu, context, true);
4170 update_pkru_bitmask(vcpu, context, true);
4171 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4172 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4174 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4176 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4178 struct kvm_mmu *context = &vcpu->arch.mmu;
4180 kvm_init_shadow_mmu(vcpu);
4181 context->set_cr3 = kvm_x86_ops->set_cr3;
4182 context->get_cr3 = get_cr3;
4183 context->get_pdptr = kvm_pdptr_read;
4184 context->inject_page_fault = kvm_inject_page_fault;
4187 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4189 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4191 g_context->get_cr3 = get_cr3;
4192 g_context->get_pdptr = kvm_pdptr_read;
4193 g_context->inject_page_fault = kvm_inject_page_fault;
4196 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4197 * L1's nested page tables (e.g. EPT12). The nested translation
4198 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4199 * L2's page tables as the first level of translation and L1's
4200 * nested page tables as the second level of translation. Basically
4201 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4203 if (!is_paging(vcpu)) {
4204 g_context->nx = false;
4205 g_context->root_level = 0;
4206 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4207 } else if (is_long_mode(vcpu)) {
4208 g_context->nx = is_nx(vcpu);
4209 g_context->root_level = PT64_ROOT_LEVEL;
4210 reset_rsvds_bits_mask(vcpu, g_context);
4211 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4212 } else if (is_pae(vcpu)) {
4213 g_context->nx = is_nx(vcpu);
4214 g_context->root_level = PT32E_ROOT_LEVEL;
4215 reset_rsvds_bits_mask(vcpu, g_context);
4216 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4218 g_context->nx = false;
4219 g_context->root_level = PT32_ROOT_LEVEL;
4220 reset_rsvds_bits_mask(vcpu, g_context);
4221 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4224 update_permission_bitmask(vcpu, g_context, false);
4225 update_pkru_bitmask(vcpu, g_context, false);
4226 update_last_nonleaf_level(vcpu, g_context);
4229 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
4231 if (mmu_is_nested(vcpu))
4232 init_kvm_nested_mmu(vcpu);
4233 else if (tdp_enabled)
4234 init_kvm_tdp_mmu(vcpu);
4236 init_kvm_softmmu(vcpu);
4239 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4241 kvm_mmu_unload(vcpu);
4244 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4246 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4250 r = mmu_topup_memory_caches(vcpu);
4253 r = mmu_alloc_roots(vcpu);
4254 kvm_mmu_sync_roots(vcpu);
4257 /* set_cr3() should ensure TLB has been flushed */
4258 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
4262 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4264 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4266 mmu_free_roots(vcpu);
4267 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4269 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4271 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4272 struct kvm_mmu_page *sp, u64 *spte,
4275 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4276 ++vcpu->kvm->stat.mmu_pde_zapped;
4280 ++vcpu->kvm->stat.mmu_pte_updated;
4281 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4284 static bool need_remote_flush(u64 old, u64 new)
4286 if (!is_shadow_present_pte(old))
4288 if (!is_shadow_present_pte(new))
4290 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4292 old ^= shadow_nx_mask;
4293 new ^= shadow_nx_mask;
4294 return (old & ~new & PT64_PERM_MASK) != 0;
4297 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4298 const u8 *new, int *bytes)
4304 * Assume that the pte write on a page table of the same type
4305 * as the current vcpu paging mode since we update the sptes only
4306 * when they have the same mode.
4308 if (is_pae(vcpu) && *bytes == 4) {
4309 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4312 r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8);
4315 new = (const u8 *)&gentry;
4320 gentry = *(const u32 *)new;
4323 gentry = *(const u64 *)new;
4334 * If we're seeing too many writes to a page, it may no longer be a page table,
4335 * or we may be forking, in which case it is better to unmap the page.
4337 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4340 * Skip write-flooding detected for the sp whose level is 1, because
4341 * it can become unsync, then the guest page is not write-protected.
4343 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4346 atomic_inc(&sp->write_flooding_count);
4347 return atomic_read(&sp->write_flooding_count) >= 3;
4351 * Misaligned accesses are too much trouble to fix up; also, they usually
4352 * indicate a page is not used as a page table.
4354 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4357 unsigned offset, pte_size, misaligned;
4359 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4360 gpa, bytes, sp->role.word);
4362 offset = offset_in_page(gpa);
4363 pte_size = sp->role.cr4_pae ? 8 : 4;
4366 * Sometimes, the OS only writes the last one bytes to update status
4367 * bits, for example, in linux, andb instruction is used in clear_bit().
4369 if (!(offset & (pte_size - 1)) && bytes == 1)
4372 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4373 misaligned |= bytes < 4;
4378 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4380 unsigned page_offset, quadrant;
4384 page_offset = offset_in_page(gpa);
4385 level = sp->role.level;
4387 if (!sp->role.cr4_pae) {
4388 page_offset <<= 1; /* 32->64 */
4390 * A 32-bit pde maps 4MB while the shadow pdes map
4391 * only 2MB. So we need to double the offset again
4392 * and zap two pdes instead of one.
4394 if (level == PT32_ROOT_LEVEL) {
4395 page_offset &= ~7; /* kill rounding error */
4399 quadrant = page_offset >> PAGE_SHIFT;
4400 page_offset &= ~PAGE_MASK;
4401 if (quadrant != sp->role.quadrant)
4405 spte = &sp->spt[page_offset / sizeof(*spte)];
4409 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4410 const u8 *new, int bytes,
4411 struct kvm_page_track_notifier_node *node)
4413 gfn_t gfn = gpa >> PAGE_SHIFT;
4414 struct kvm_mmu_page *sp;
4415 LIST_HEAD(invalid_list);
4416 u64 entry, gentry, *spte;
4418 bool remote_flush, local_flush;
4419 union kvm_mmu_page_role mask = { };
4424 mask.smep_andnot_wp = 1;
4425 mask.smap_andnot_wp = 1;
4429 * If we don't have indirect shadow pages, it means no page is
4430 * write-protected, so we can exit simply.
4432 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4435 remote_flush = local_flush = false;
4437 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4439 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4442 * No need to care whether allocation memory is successful
4443 * or not since pte prefetch is skiped if it does not have
4444 * enough objects in the cache.
4446 mmu_topup_memory_caches(vcpu);
4448 spin_lock(&vcpu->kvm->mmu_lock);
4449 ++vcpu->kvm->stat.mmu_pte_write;
4450 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4452 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4453 if (detect_write_misaligned(sp, gpa, bytes) ||
4454 detect_write_flooding(sp)) {
4455 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4456 ++vcpu->kvm->stat.mmu_flooded;
4460 spte = get_written_sptes(sp, gpa, &npte);
4467 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4469 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4470 & mask.word) && rmap_can_add(vcpu))
4471 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4472 if (need_remote_flush(entry, *spte))
4473 remote_flush = true;
4477 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
4478 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4479 spin_unlock(&vcpu->kvm->mmu_lock);
4482 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4487 if (vcpu->arch.mmu.direct_map)
4490 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4492 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4496 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4498 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4500 LIST_HEAD(invalid_list);
4502 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4505 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4506 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4509 ++vcpu->kvm->stat.mmu_recycled;
4511 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4514 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
4515 void *insn, int insn_len)
4517 int r, emulation_type = EMULTYPE_RETRY;
4518 enum emulation_result er;
4519 bool direct = vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu);
4521 if (unlikely(error_code & PFERR_RSVD_MASK)) {
4522 r = handle_mmio_page_fault(vcpu, cr2, direct);
4523 if (r == RET_MMIO_PF_EMULATE) {
4527 if (r == RET_MMIO_PF_RETRY)
4533 r = vcpu->arch.mmu.page_fault(vcpu, cr2, lower_32_bits(error_code),
4541 * Before emulating the instruction, check if the error code
4542 * was due to a RO violation while translating the guest page.
4543 * This can occur when using nested virtualization with nested
4544 * paging in both guests. If true, we simply unprotect the page
4545 * and resume the guest.
4547 * Note: AMD only (since it supports the PFERR_GUEST_PAGE_MASK used
4548 * in PFERR_NEXT_GUEST_PAGE)
4550 if (error_code == PFERR_NESTED_GUEST_PAGE) {
4551 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2));
4555 if (mmio_info_in_cache(vcpu, cr2, direct))
4558 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4563 case EMULATE_USER_EXIT:
4564 ++vcpu->stat.mmio_exits;
4572 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4574 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4576 vcpu->arch.mmu.invlpg(vcpu, gva);
4577 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4578 ++vcpu->stat.invlpg;
4580 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4582 void kvm_enable_tdp(void)
4586 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4588 void kvm_disable_tdp(void)
4590 tdp_enabled = false;
4592 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4594 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4596 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4597 if (vcpu->arch.mmu.lm_root != NULL)
4598 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4601 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4607 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4608 * Therefore we need to allocate shadow page tables in the first
4609 * 4GB of memory, which happens to fit the DMA32 zone.
4611 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4615 vcpu->arch.mmu.pae_root = page_address(page);
4616 for (i = 0; i < 4; ++i)
4617 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4622 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4624 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4625 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4626 vcpu->arch.mmu.translate_gpa = translate_gpa;
4627 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4629 return alloc_mmu_pages(vcpu);
4632 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4634 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4639 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
4640 struct kvm_memory_slot *slot,
4641 struct kvm_page_track_notifier_node *node)
4643 kvm_mmu_invalidate_zap_all_pages(kvm);
4646 void kvm_mmu_init_vm(struct kvm *kvm)
4648 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4650 node->track_write = kvm_mmu_pte_write;
4651 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
4652 kvm_page_track_register_notifier(kvm, node);
4655 void kvm_mmu_uninit_vm(struct kvm *kvm)
4657 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4659 kvm_page_track_unregister_notifier(kvm, node);
4662 /* The return value indicates if tlb flush on all vcpus is needed. */
4663 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
4665 /* The caller should hold mmu-lock before calling this function. */
4667 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
4668 slot_level_handler fn, int start_level, int end_level,
4669 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
4671 struct slot_rmap_walk_iterator iterator;
4674 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
4675 end_gfn, &iterator) {
4677 flush |= fn(kvm, iterator.rmap);
4679 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4680 if (flush && lock_flush_tlb) {
4681 kvm_flush_remote_tlbs(kvm);
4684 cond_resched_lock(&kvm->mmu_lock);
4688 if (flush && lock_flush_tlb) {
4689 kvm_flush_remote_tlbs(kvm);
4697 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4698 slot_level_handler fn, int start_level, int end_level,
4699 bool lock_flush_tlb)
4701 return slot_handle_level_range(kvm, memslot, fn, start_level,
4702 end_level, memslot->base_gfn,
4703 memslot->base_gfn + memslot->npages - 1,
4708 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4709 slot_level_handler fn, bool lock_flush_tlb)
4711 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4712 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4716 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4717 slot_level_handler fn, bool lock_flush_tlb)
4719 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
4720 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4724 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
4725 slot_level_handler fn, bool lock_flush_tlb)
4727 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4728 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
4731 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
4733 struct kvm_memslots *slots;
4734 struct kvm_memory_slot *memslot;
4737 spin_lock(&kvm->mmu_lock);
4738 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
4739 slots = __kvm_memslots(kvm, i);
4740 kvm_for_each_memslot(memslot, slots) {
4743 start = max(gfn_start, memslot->base_gfn);
4744 end = min(gfn_end, memslot->base_gfn + memslot->npages);
4748 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
4749 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
4750 start, end - 1, true);
4754 spin_unlock(&kvm->mmu_lock);
4757 static bool slot_rmap_write_protect(struct kvm *kvm,
4758 struct kvm_rmap_head *rmap_head)
4760 return __rmap_write_protect(kvm, rmap_head, false);
4763 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
4764 struct kvm_memory_slot *memslot)
4768 spin_lock(&kvm->mmu_lock);
4769 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
4771 spin_unlock(&kvm->mmu_lock);
4774 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4775 * which do tlb flush out of mmu-lock should be serialized by
4776 * kvm->slots_lock otherwise tlb flush would be missed.
4778 lockdep_assert_held(&kvm->slots_lock);
4781 * We can flush all the TLBs out of the mmu lock without TLB
4782 * corruption since we just change the spte from writable to
4783 * readonly so that we only need to care the case of changing
4784 * spte from present to present (changing the spte from present
4785 * to nonpresent will flush all the TLBs immediately), in other
4786 * words, the only case we care is mmu_spte_update() where we
4787 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
4788 * instead of PT_WRITABLE_MASK, that means it does not depend
4789 * on PT_WRITABLE_MASK anymore.
4792 kvm_flush_remote_tlbs(kvm);
4795 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
4796 struct kvm_rmap_head *rmap_head)
4799 struct rmap_iterator iter;
4800 int need_tlb_flush = 0;
4802 struct kvm_mmu_page *sp;
4805 for_each_rmap_spte(rmap_head, &iter, sptep) {
4806 sp = page_header(__pa(sptep));
4807 pfn = spte_to_pfn(*sptep);
4810 * We cannot do huge page mapping for indirect shadow pages,
4811 * which are found on the last rmap (level = 1) when not using
4812 * tdp; such shadow pages are synced with the page table in
4813 * the guest, and the guest page table is using 4K page size
4814 * mapping if the indirect sp has level = 1.
4816 if (sp->role.direct &&
4817 !kvm_is_reserved_pfn(pfn) &&
4818 PageTransCompoundMap(pfn_to_page(pfn))) {
4819 drop_spte(kvm, sptep);
4825 return need_tlb_flush;
4828 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
4829 const struct kvm_memory_slot *memslot)
4831 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
4832 spin_lock(&kvm->mmu_lock);
4833 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
4834 kvm_mmu_zap_collapsible_spte, true);
4835 spin_unlock(&kvm->mmu_lock);
4838 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
4839 struct kvm_memory_slot *memslot)
4843 spin_lock(&kvm->mmu_lock);
4844 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
4845 spin_unlock(&kvm->mmu_lock);
4847 lockdep_assert_held(&kvm->slots_lock);
4850 * It's also safe to flush TLBs out of mmu lock here as currently this
4851 * function is only used for dirty logging, in which case flushing TLB
4852 * out of mmu lock also guarantees no dirty pages will be lost in
4856 kvm_flush_remote_tlbs(kvm);
4858 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
4860 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
4861 struct kvm_memory_slot *memslot)
4865 spin_lock(&kvm->mmu_lock);
4866 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
4868 spin_unlock(&kvm->mmu_lock);
4870 /* see kvm_mmu_slot_remove_write_access */
4871 lockdep_assert_held(&kvm->slots_lock);
4874 kvm_flush_remote_tlbs(kvm);
4876 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
4878 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
4879 struct kvm_memory_slot *memslot)
4883 spin_lock(&kvm->mmu_lock);
4884 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
4885 spin_unlock(&kvm->mmu_lock);
4887 lockdep_assert_held(&kvm->slots_lock);
4889 /* see kvm_mmu_slot_leaf_clear_dirty */
4891 kvm_flush_remote_tlbs(kvm);
4893 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
4895 #define BATCH_ZAP_PAGES 10
4896 static void kvm_zap_obsolete_pages(struct kvm *kvm)
4898 struct kvm_mmu_page *sp, *node;
4902 list_for_each_entry_safe_reverse(sp, node,
4903 &kvm->arch.active_mmu_pages, link) {
4907 * No obsolete page exists before new created page since
4908 * active_mmu_pages is the FIFO list.
4910 if (!is_obsolete_sp(kvm, sp))
4914 * Since we are reversely walking the list and the invalid
4915 * list will be moved to the head, skip the invalid page
4916 * can help us to avoid the infinity list walking.
4918 if (sp->role.invalid)
4922 * Need not flush tlb since we only zap the sp with invalid
4923 * generation number.
4925 if (batch >= BATCH_ZAP_PAGES &&
4926 cond_resched_lock(&kvm->mmu_lock)) {
4931 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4932 &kvm->arch.zapped_obsolete_pages);
4940 * Should flush tlb before free page tables since lockless-walking
4941 * may use the pages.
4943 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4947 * Fast invalidate all shadow pages and use lock-break technique
4948 * to zap obsolete pages.
4950 * It's required when memslot is being deleted or VM is being
4951 * destroyed, in these cases, we should ensure that KVM MMU does
4952 * not use any resource of the being-deleted slot or all slots
4953 * after calling the function.
4955 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4957 spin_lock(&kvm->mmu_lock);
4958 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4959 kvm->arch.mmu_valid_gen++;
4962 * Notify all vcpus to reload its shadow page table
4963 * and flush TLB. Then all vcpus will switch to new
4964 * shadow page table with the new mmu_valid_gen.
4966 * Note: we should do this under the protection of
4967 * mmu-lock, otherwise, vcpu would purge shadow page
4968 * but miss tlb flush.
4970 kvm_reload_remote_mmus(kvm);
4972 kvm_zap_obsolete_pages(kvm);
4973 spin_unlock(&kvm->mmu_lock);
4976 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4978 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4981 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots)
4984 * The very rare case: if the generation-number is round,
4985 * zap all shadow pages.
4987 if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) {
4988 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
4989 kvm_mmu_invalidate_zap_all_pages(kvm);
4993 static unsigned long
4994 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
4997 int nr_to_scan = sc->nr_to_scan;
4998 unsigned long freed = 0;
5000 spin_lock(&kvm_lock);
5002 list_for_each_entry(kvm, &vm_list, vm_list) {
5004 LIST_HEAD(invalid_list);
5007 * Never scan more than sc->nr_to_scan VM instances.
5008 * Will not hit this condition practically since we do not try
5009 * to shrink more than one VM and it is very unlikely to see
5010 * !n_used_mmu_pages so many times.
5015 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5016 * here. We may skip a VM instance errorneosly, but we do not
5017 * want to shrink a VM that only started to populate its MMU
5020 if (!kvm->arch.n_used_mmu_pages &&
5021 !kvm_has_zapped_obsolete_pages(kvm))
5024 idx = srcu_read_lock(&kvm->srcu);
5025 spin_lock(&kvm->mmu_lock);
5027 if (kvm_has_zapped_obsolete_pages(kvm)) {
5028 kvm_mmu_commit_zap_page(kvm,
5029 &kvm->arch.zapped_obsolete_pages);
5033 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
5035 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5038 spin_unlock(&kvm->mmu_lock);
5039 srcu_read_unlock(&kvm->srcu, idx);
5042 * unfair on small ones
5043 * per-vm shrinkers cry out
5044 * sadness comes quickly
5046 list_move_tail(&kvm->vm_list, &vm_list);
5050 spin_unlock(&kvm_lock);
5054 static unsigned long
5055 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5057 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5060 static struct shrinker mmu_shrinker = {
5061 .count_objects = mmu_shrink_count,
5062 .scan_objects = mmu_shrink_scan,
5063 .seeks = DEFAULT_SEEKS * 10,
5066 static void mmu_destroy_caches(void)
5068 if (pte_list_desc_cache)
5069 kmem_cache_destroy(pte_list_desc_cache);
5070 if (mmu_page_header_cache)
5071 kmem_cache_destroy(mmu_page_header_cache);
5074 int kvm_mmu_module_init(void)
5076 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5077 sizeof(struct pte_list_desc),
5079 if (!pte_list_desc_cache)
5082 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5083 sizeof(struct kvm_mmu_page),
5085 if (!mmu_page_header_cache)
5088 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5091 register_shrinker(&mmu_shrinker);
5096 mmu_destroy_caches();
5101 * Caculate mmu pages needed for kvm.
5103 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
5105 unsigned int nr_mmu_pages;
5106 unsigned int nr_pages = 0;
5107 struct kvm_memslots *slots;
5108 struct kvm_memory_slot *memslot;
5111 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5112 slots = __kvm_memslots(kvm, i);
5114 kvm_for_each_memslot(memslot, slots)
5115 nr_pages += memslot->npages;
5118 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5119 nr_mmu_pages = max(nr_mmu_pages,
5120 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
5122 return nr_mmu_pages;
5125 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5127 kvm_mmu_unload(vcpu);
5128 free_mmu_pages(vcpu);
5129 mmu_free_memory_caches(vcpu);
5132 void kvm_mmu_module_exit(void)
5134 mmu_destroy_caches();
5135 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5136 unregister_shrinker(&mmu_shrinker);
5137 mmu_audit_disable();