1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
51 #include <asm/set_memory.h>
53 #include <asm/kvm_page_track.h>
58 extern bool itlb_multihit_kvm_mitigation;
60 int __read_mostly nx_huge_pages = -1;
61 static uint __read_mostly nx_huge_pages_recovery_period_ms;
62 #ifdef CONFIG_PREEMPT_RT
63 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
64 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
66 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
69 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
70 static int set_nx_huge_pages_recovery_param(const char *val, const struct kernel_param *kp);
72 static const struct kernel_param_ops nx_huge_pages_ops = {
73 .set = set_nx_huge_pages,
74 .get = param_get_bool,
77 static const struct kernel_param_ops nx_huge_pages_recovery_param_ops = {
78 .set = set_nx_huge_pages_recovery_param,
79 .get = param_get_uint,
82 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
83 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
84 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_param_ops,
85 &nx_huge_pages_recovery_ratio, 0644);
86 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
87 module_param_cb(nx_huge_pages_recovery_period_ms, &nx_huge_pages_recovery_param_ops,
88 &nx_huge_pages_recovery_period_ms, 0644);
89 __MODULE_PARM_TYPE(nx_huge_pages_recovery_period_ms, "uint");
91 static bool __read_mostly force_flush_and_sync_on_reuse;
92 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
95 * When setting this variable to true it enables Two-Dimensional-Paging
96 * where the hardware walks 2 page tables:
97 * 1. the guest-virtual to guest-physical
98 * 2. while doing 1. it walks guest-physical to host-physical
99 * If the hardware supports that we don't need to do shadow paging.
101 bool tdp_enabled = false;
103 static int max_huge_page_level __read_mostly;
104 static int tdp_root_level __read_mostly;
105 static int max_tdp_level __read_mostly;
108 AUDIT_PRE_PAGE_FAULT,
109 AUDIT_POST_PAGE_FAULT,
111 AUDIT_POST_PTE_WRITE,
118 module_param(dbg, bool, 0644);
121 #define PTE_PREFETCH_NUM 8
123 #define PT32_LEVEL_BITS 10
125 #define PT32_LEVEL_SHIFT(level) \
126 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
128 #define PT32_LVL_OFFSET_MASK(level) \
129 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
130 * PT32_LEVEL_BITS))) - 1))
132 #define PT32_INDEX(address, level)\
133 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
136 #define PT32_BASE_ADDR_MASK PAGE_MASK
137 #define PT32_DIR_BASE_ADDR_MASK \
138 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
139 #define PT32_LVL_ADDR_MASK(level) \
140 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
141 * PT32_LEVEL_BITS))) - 1))
143 #include <trace/events/kvm.h>
145 /* make pte_list_desc fit well in cache lines */
146 #define PTE_LIST_EXT 14
149 * Slight optimization of cacheline layout, by putting `more' and `spte_count'
150 * at the start; then accessing it will only use one single cacheline for
151 * either full (entries==PTE_LIST_EXT) case or entries<=6.
153 struct pte_list_desc {
154 struct pte_list_desc *more;
156 * Stores number of entries stored in the pte_list_desc. No need to be
157 * u64 but just for easier alignment. When PTE_LIST_EXT, means full.
160 u64 *sptes[PTE_LIST_EXT];
163 struct kvm_shadow_walk_iterator {
171 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
172 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
174 shadow_walk_okay(&(_walker)); \
175 shadow_walk_next(&(_walker)))
177 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
178 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
179 shadow_walk_okay(&(_walker)); \
180 shadow_walk_next(&(_walker)))
182 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
183 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
184 shadow_walk_okay(&(_walker)) && \
185 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
186 __shadow_walk_next(&(_walker), spte))
188 static struct kmem_cache *pte_list_desc_cache;
189 struct kmem_cache *mmu_page_header_cache;
190 static struct percpu_counter kvm_total_used_mmu_pages;
192 static void mmu_spte_set(u64 *sptep, u64 spte);
193 static union kvm_mmu_page_role
194 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
196 struct kvm_mmu_role_regs {
197 const unsigned long cr0;
198 const unsigned long cr4;
202 #define CREATE_TRACE_POINTS
203 #include "mmutrace.h"
206 * Yes, lot's of underscores. They're a hint that you probably shouldn't be
207 * reading from the role_regs. Once the mmu_role is constructed, it becomes
208 * the single source of truth for the MMU's state.
210 #define BUILD_MMU_ROLE_REGS_ACCESSOR(reg, name, flag) \
211 static inline bool __maybe_unused ____is_##reg##_##name(struct kvm_mmu_role_regs *regs)\
213 return !!(regs->reg & flag); \
215 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, pg, X86_CR0_PG);
216 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, wp, X86_CR0_WP);
217 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pse, X86_CR4_PSE);
218 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pae, X86_CR4_PAE);
219 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smep, X86_CR4_SMEP);
220 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smap, X86_CR4_SMAP);
221 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pke, X86_CR4_PKE);
222 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, la57, X86_CR4_LA57);
223 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, nx, EFER_NX);
224 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, lma, EFER_LMA);
227 * The MMU itself (with a valid role) is the single source of truth for the
228 * MMU. Do not use the regs used to build the MMU/role, nor the vCPU. The
229 * regs don't account for dependencies, e.g. clearing CR4 bits if CR0.PG=1,
230 * and the vCPU may be incorrect/irrelevant.
232 #define BUILD_MMU_ROLE_ACCESSOR(base_or_ext, reg, name) \
233 static inline bool __maybe_unused is_##reg##_##name(struct kvm_mmu *mmu) \
235 return !!(mmu->mmu_role. base_or_ext . reg##_##name); \
237 BUILD_MMU_ROLE_ACCESSOR(ext, cr0, pg);
238 BUILD_MMU_ROLE_ACCESSOR(base, cr0, wp);
239 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pse);
240 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pae);
241 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smep);
242 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smap);
243 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pke);
244 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, la57);
245 BUILD_MMU_ROLE_ACCESSOR(base, efer, nx);
247 static struct kvm_mmu_role_regs vcpu_to_role_regs(struct kvm_vcpu *vcpu)
249 struct kvm_mmu_role_regs regs = {
250 .cr0 = kvm_read_cr0_bits(vcpu, KVM_MMU_CR0_ROLE_BITS),
251 .cr4 = kvm_read_cr4_bits(vcpu, KVM_MMU_CR4_ROLE_BITS),
252 .efer = vcpu->arch.efer,
258 static int role_regs_to_root_level(struct kvm_mmu_role_regs *regs)
260 if (!____is_cr0_pg(regs))
262 else if (____is_efer_lma(regs))
263 return ____is_cr4_la57(regs) ? PT64_ROOT_5LEVEL :
265 else if (____is_cr4_pae(regs))
266 return PT32E_ROOT_LEVEL;
268 return PT32_ROOT_LEVEL;
271 static inline bool kvm_available_flush_tlb_with_range(void)
273 return kvm_x86_ops.tlb_remote_flush_with_range;
276 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
277 struct kvm_tlb_range *range)
281 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
282 ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range);
285 kvm_flush_remote_tlbs(kvm);
288 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
289 u64 start_gfn, u64 pages)
291 struct kvm_tlb_range range;
293 range.start_gfn = start_gfn;
296 kvm_flush_remote_tlbs_with_range(kvm, &range);
299 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
302 u64 spte = make_mmio_spte(vcpu, gfn, access);
304 trace_mark_mmio_spte(sptep, gfn, spte);
305 mmu_spte_set(sptep, spte);
308 static gfn_t get_mmio_spte_gfn(u64 spte)
310 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
312 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)
313 & shadow_nonpresent_or_rsvd_mask;
315 return gpa >> PAGE_SHIFT;
318 static unsigned get_mmio_spte_access(u64 spte)
320 return spte & shadow_mmio_access_mask;
323 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
325 u64 kvm_gen, spte_gen, gen;
327 gen = kvm_vcpu_memslots(vcpu)->generation;
328 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
331 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
332 spte_gen = get_mmio_spte_generation(spte);
334 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
335 return likely(kvm_gen == spte_gen);
338 static int is_cpuid_PSE36(void)
343 static gfn_t pse36_gfn_delta(u32 gpte)
345 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
347 return (gpte & PT32_DIR_PSE36_MASK) << shift;
351 static void __set_spte(u64 *sptep, u64 spte)
353 WRITE_ONCE(*sptep, spte);
356 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
358 WRITE_ONCE(*sptep, spte);
361 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
363 return xchg(sptep, spte);
366 static u64 __get_spte_lockless(u64 *sptep)
368 return READ_ONCE(*sptep);
379 static void count_spte_clear(u64 *sptep, u64 spte)
381 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
383 if (is_shadow_present_pte(spte))
386 /* Ensure the spte is completely set before we increase the count */
388 sp->clear_spte_count++;
391 static void __set_spte(u64 *sptep, u64 spte)
393 union split_spte *ssptep, sspte;
395 ssptep = (union split_spte *)sptep;
396 sspte = (union split_spte)spte;
398 ssptep->spte_high = sspte.spte_high;
401 * If we map the spte from nonpresent to present, We should store
402 * the high bits firstly, then set present bit, so cpu can not
403 * fetch this spte while we are setting the spte.
407 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
410 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
412 union split_spte *ssptep, sspte;
414 ssptep = (union split_spte *)sptep;
415 sspte = (union split_spte)spte;
417 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
420 * If we map the spte from present to nonpresent, we should clear
421 * present bit firstly to avoid vcpu fetch the old high bits.
425 ssptep->spte_high = sspte.spte_high;
426 count_spte_clear(sptep, spte);
429 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
431 union split_spte *ssptep, sspte, orig;
433 ssptep = (union split_spte *)sptep;
434 sspte = (union split_spte)spte;
436 /* xchg acts as a barrier before the setting of the high bits */
437 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
438 orig.spte_high = ssptep->spte_high;
439 ssptep->spte_high = sspte.spte_high;
440 count_spte_clear(sptep, spte);
446 * The idea using the light way get the spte on x86_32 guest is from
447 * gup_get_pte (mm/gup.c).
449 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
450 * coalesces them and we are running out of the MMU lock. Therefore
451 * we need to protect against in-progress updates of the spte.
453 * Reading the spte while an update is in progress may get the old value
454 * for the high part of the spte. The race is fine for a present->non-present
455 * change (because the high part of the spte is ignored for non-present spte),
456 * but for a present->present change we must reread the spte.
458 * All such changes are done in two steps (present->non-present and
459 * non-present->present), hence it is enough to count the number of
460 * present->non-present updates: if it changed while reading the spte,
461 * we might have hit the race. This is done using clear_spte_count.
463 static u64 __get_spte_lockless(u64 *sptep)
465 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
466 union split_spte spte, *orig = (union split_spte *)sptep;
470 count = sp->clear_spte_count;
473 spte.spte_low = orig->spte_low;
476 spte.spte_high = orig->spte_high;
479 if (unlikely(spte.spte_low != orig->spte_low ||
480 count != sp->clear_spte_count))
487 static bool spte_has_volatile_bits(u64 spte)
489 if (!is_shadow_present_pte(spte))
493 * Always atomically update spte if it can be updated
494 * out of mmu-lock, it can ensure dirty bit is not lost,
495 * also, it can help us to get a stable is_writable_pte()
496 * to ensure tlb flush is not missed.
498 if (spte_can_locklessly_be_made_writable(spte) ||
499 is_access_track_spte(spte))
502 if (spte_ad_enabled(spte)) {
503 if ((spte & shadow_accessed_mask) == 0 ||
504 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
511 /* Rules for using mmu_spte_set:
512 * Set the sptep from nonpresent to present.
513 * Note: the sptep being assigned *must* be either not present
514 * or in a state where the hardware will not attempt to update
517 static void mmu_spte_set(u64 *sptep, u64 new_spte)
519 WARN_ON(is_shadow_present_pte(*sptep));
520 __set_spte(sptep, new_spte);
524 * Update the SPTE (excluding the PFN), but do not track changes in its
525 * accessed/dirty status.
527 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
529 u64 old_spte = *sptep;
531 WARN_ON(!is_shadow_present_pte(new_spte));
533 if (!is_shadow_present_pte(old_spte)) {
534 mmu_spte_set(sptep, new_spte);
538 if (!spte_has_volatile_bits(old_spte))
539 __update_clear_spte_fast(sptep, new_spte);
541 old_spte = __update_clear_spte_slow(sptep, new_spte);
543 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
548 /* Rules for using mmu_spte_update:
549 * Update the state bits, it means the mapped pfn is not changed.
551 * Whenever we overwrite a writable spte with a read-only one we
552 * should flush remote TLBs. Otherwise rmap_write_protect
553 * will find a read-only spte, even though the writable spte
554 * might be cached on a CPU's TLB, the return value indicates this
557 * Returns true if the TLB needs to be flushed
559 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
562 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
564 if (!is_shadow_present_pte(old_spte))
568 * For the spte updated out of mmu-lock is safe, since
569 * we always atomically update it, see the comments in
570 * spte_has_volatile_bits().
572 if (spte_can_locklessly_be_made_writable(old_spte) &&
573 !is_writable_pte(new_spte))
577 * Flush TLB when accessed/dirty states are changed in the page tables,
578 * to guarantee consistency between TLB and page tables.
581 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
583 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
586 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
588 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
595 * Rules for using mmu_spte_clear_track_bits:
596 * It sets the sptep from present to nonpresent, and track the
597 * state bits, it is used to clear the last level sptep.
598 * Returns the old PTE.
600 static int mmu_spte_clear_track_bits(struct kvm *kvm, u64 *sptep)
603 u64 old_spte = *sptep;
604 int level = sptep_to_sp(sptep)->role.level;
606 if (!spte_has_volatile_bits(old_spte))
607 __update_clear_spte_fast(sptep, 0ull);
609 old_spte = __update_clear_spte_slow(sptep, 0ull);
611 if (!is_shadow_present_pte(old_spte))
614 kvm_update_page_stats(kvm, level, -1);
616 pfn = spte_to_pfn(old_spte);
619 * KVM does not hold the refcount of the page used by
620 * kvm mmu, before reclaiming the page, we should
621 * unmap it from mmu first.
623 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
625 if (is_accessed_spte(old_spte))
626 kvm_set_pfn_accessed(pfn);
628 if (is_dirty_spte(old_spte))
629 kvm_set_pfn_dirty(pfn);
635 * Rules for using mmu_spte_clear_no_track:
636 * Directly clear spte without caring the state bits of sptep,
637 * it is used to set the upper level spte.
639 static void mmu_spte_clear_no_track(u64 *sptep)
641 __update_clear_spte_fast(sptep, 0ull);
644 static u64 mmu_spte_get_lockless(u64 *sptep)
646 return __get_spte_lockless(sptep);
649 /* Restore an acc-track PTE back to a regular PTE */
650 static u64 restore_acc_track_spte(u64 spte)
653 u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
654 & SHADOW_ACC_TRACK_SAVED_BITS_MASK;
656 WARN_ON_ONCE(spte_ad_enabled(spte));
657 WARN_ON_ONCE(!is_access_track_spte(spte));
659 new_spte &= ~shadow_acc_track_mask;
660 new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
661 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
662 new_spte |= saved_bits;
667 /* Returns the Accessed status of the PTE and resets it at the same time. */
668 static bool mmu_spte_age(u64 *sptep)
670 u64 spte = mmu_spte_get_lockless(sptep);
672 if (!is_accessed_spte(spte))
675 if (spte_ad_enabled(spte)) {
676 clear_bit((ffs(shadow_accessed_mask) - 1),
677 (unsigned long *)sptep);
680 * Capture the dirty status of the page, so that it doesn't get
681 * lost when the SPTE is marked for access tracking.
683 if (is_writable_pte(spte))
684 kvm_set_pfn_dirty(spte_to_pfn(spte));
686 spte = mark_spte_for_access_track(spte);
687 mmu_spte_update_no_track(sptep, spte);
693 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
695 if (is_tdp_mmu(vcpu->arch.mmu)) {
696 kvm_tdp_mmu_walk_lockless_begin();
699 * Prevent page table teardown by making any free-er wait during
700 * kvm_flush_remote_tlbs() IPI to all active vcpus.
705 * Make sure a following spte read is not reordered ahead of the write
708 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
712 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
714 if (is_tdp_mmu(vcpu->arch.mmu)) {
715 kvm_tdp_mmu_walk_lockless_end();
718 * Make sure the write to vcpu->mode is not reordered in front of
719 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
720 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
722 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
727 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
731 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
732 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
733 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
736 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
737 PT64_ROOT_MAX_LEVEL);
740 if (maybe_indirect) {
741 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
742 PT64_ROOT_MAX_LEVEL);
746 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
747 PT64_ROOT_MAX_LEVEL);
750 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
752 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
753 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
754 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
755 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
758 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
760 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
763 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
765 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
768 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
770 if (!sp->role.direct)
771 return sp->gfns[index];
773 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
776 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
778 if (!sp->role.direct) {
779 sp->gfns[index] = gfn;
783 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
784 pr_err_ratelimited("gfn mismatch under direct page %llx "
785 "(expected %llx, got %llx)\n",
787 kvm_mmu_page_get_gfn(sp, index), gfn);
791 * Return the pointer to the large page information for a given gfn,
792 * handling slots that are not large page aligned.
794 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
795 const struct kvm_memory_slot *slot, int level)
799 idx = gfn_to_index(gfn, slot->base_gfn, level);
800 return &slot->arch.lpage_info[level - 2][idx];
803 static void update_gfn_disallow_lpage_count(const struct kvm_memory_slot *slot,
804 gfn_t gfn, int count)
806 struct kvm_lpage_info *linfo;
809 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
810 linfo = lpage_info_slot(gfn, slot, i);
811 linfo->disallow_lpage += count;
812 WARN_ON(linfo->disallow_lpage < 0);
816 void kvm_mmu_gfn_disallow_lpage(const struct kvm_memory_slot *slot, gfn_t gfn)
818 update_gfn_disallow_lpage_count(slot, gfn, 1);
821 void kvm_mmu_gfn_allow_lpage(const struct kvm_memory_slot *slot, gfn_t gfn)
823 update_gfn_disallow_lpage_count(slot, gfn, -1);
826 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
828 struct kvm_memslots *slots;
829 struct kvm_memory_slot *slot;
832 kvm->arch.indirect_shadow_pages++;
834 slots = kvm_memslots_for_spte_role(kvm, sp->role);
835 slot = __gfn_to_memslot(slots, gfn);
837 /* the non-leaf shadow pages are keeping readonly. */
838 if (sp->role.level > PG_LEVEL_4K)
839 return kvm_slot_page_track_add_page(kvm, slot, gfn,
840 KVM_PAGE_TRACK_WRITE);
842 kvm_mmu_gfn_disallow_lpage(slot, gfn);
845 void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
847 if (sp->lpage_disallowed)
850 ++kvm->stat.nx_lpage_splits;
851 list_add_tail(&sp->lpage_disallowed_link,
852 &kvm->arch.lpage_disallowed_mmu_pages);
853 sp->lpage_disallowed = true;
856 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
858 struct kvm_memslots *slots;
859 struct kvm_memory_slot *slot;
862 kvm->arch.indirect_shadow_pages--;
864 slots = kvm_memslots_for_spte_role(kvm, sp->role);
865 slot = __gfn_to_memslot(slots, gfn);
866 if (sp->role.level > PG_LEVEL_4K)
867 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
868 KVM_PAGE_TRACK_WRITE);
870 kvm_mmu_gfn_allow_lpage(slot, gfn);
873 void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
875 --kvm->stat.nx_lpage_splits;
876 sp->lpage_disallowed = false;
877 list_del(&sp->lpage_disallowed_link);
880 static struct kvm_memory_slot *
881 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
884 struct kvm_memory_slot *slot;
886 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
887 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
889 if (no_dirty_log && kvm_slot_dirty_track_enabled(slot))
896 * About rmap_head encoding:
898 * If the bit zero of rmap_head->val is clear, then it points to the only spte
899 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
900 * pte_list_desc containing more mappings.
904 * Returns the number of pointers in the rmap chain, not counting the new one.
906 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
907 struct kvm_rmap_head *rmap_head)
909 struct pte_list_desc *desc;
912 if (!rmap_head->val) {
913 rmap_printk("%p %llx 0->1\n", spte, *spte);
914 rmap_head->val = (unsigned long)spte;
915 } else if (!(rmap_head->val & 1)) {
916 rmap_printk("%p %llx 1->many\n", spte, *spte);
917 desc = mmu_alloc_pte_list_desc(vcpu);
918 desc->sptes[0] = (u64 *)rmap_head->val;
919 desc->sptes[1] = spte;
920 desc->spte_count = 2;
921 rmap_head->val = (unsigned long)desc | 1;
924 rmap_printk("%p %llx many->many\n", spte, *spte);
925 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
926 while (desc->spte_count == PTE_LIST_EXT) {
927 count += PTE_LIST_EXT;
929 desc->more = mmu_alloc_pte_list_desc(vcpu);
931 desc->spte_count = 0;
936 count += desc->spte_count;
937 desc->sptes[desc->spte_count++] = spte;
943 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
944 struct pte_list_desc *desc, int i,
945 struct pte_list_desc *prev_desc)
947 int j = desc->spte_count - 1;
949 desc->sptes[i] = desc->sptes[j];
950 desc->sptes[j] = NULL;
952 if (desc->spte_count)
954 if (!prev_desc && !desc->more)
958 prev_desc->more = desc->more;
960 rmap_head->val = (unsigned long)desc->more | 1;
961 mmu_free_pte_list_desc(desc);
964 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
966 struct pte_list_desc *desc;
967 struct pte_list_desc *prev_desc;
970 if (!rmap_head->val) {
971 pr_err("%s: %p 0->BUG\n", __func__, spte);
973 } else if (!(rmap_head->val & 1)) {
974 rmap_printk("%p 1->0\n", spte);
975 if ((u64 *)rmap_head->val != spte) {
976 pr_err("%s: %p 1->BUG\n", __func__, spte);
981 rmap_printk("%p many->many\n", spte);
982 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
985 for (i = 0; i < desc->spte_count; ++i) {
986 if (desc->sptes[i] == spte) {
987 pte_list_desc_remove_entry(rmap_head,
995 pr_err("%s: %p many->many\n", __func__, spte);
1000 static void pte_list_remove(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1003 mmu_spte_clear_track_bits(kvm, sptep);
1004 __pte_list_remove(sptep, rmap_head);
1007 /* Return true if rmap existed, false otherwise */
1008 static bool pte_list_destroy(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1010 struct pte_list_desc *desc, *next;
1013 if (!rmap_head->val)
1016 if (!(rmap_head->val & 1)) {
1017 mmu_spte_clear_track_bits(kvm, (u64 *)rmap_head->val);
1021 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1023 for (; desc; desc = next) {
1024 for (i = 0; i < desc->spte_count; i++)
1025 mmu_spte_clear_track_bits(kvm, desc->sptes[i]);
1027 mmu_free_pte_list_desc(desc);
1030 /* rmap_head is meaningless now, remember to reset it */
1035 unsigned int pte_list_count(struct kvm_rmap_head *rmap_head)
1037 struct pte_list_desc *desc;
1038 unsigned int count = 0;
1040 if (!rmap_head->val)
1042 else if (!(rmap_head->val & 1))
1045 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1048 count += desc->spte_count;
1055 static struct kvm_rmap_head *gfn_to_rmap(gfn_t gfn, int level,
1056 const struct kvm_memory_slot *slot)
1060 idx = gfn_to_index(gfn, slot->base_gfn, level);
1061 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
1064 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1066 struct kvm_mmu_memory_cache *mc;
1068 mc = &vcpu->arch.mmu_pte_list_desc_cache;
1069 return kvm_mmu_memory_cache_nr_free_objects(mc);
1072 static void rmap_remove(struct kvm *kvm, u64 *spte)
1074 struct kvm_memslots *slots;
1075 struct kvm_memory_slot *slot;
1076 struct kvm_mmu_page *sp;
1078 struct kvm_rmap_head *rmap_head;
1080 sp = sptep_to_sp(spte);
1081 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1084 * Unlike rmap_add, rmap_remove does not run in the context of a vCPU
1085 * so we have to determine which memslots to use based on context
1086 * information in sp->role.
1088 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1090 slot = __gfn_to_memslot(slots, gfn);
1091 rmap_head = gfn_to_rmap(gfn, sp->role.level, slot);
1093 __pte_list_remove(spte, rmap_head);
1097 * Used by the following functions to iterate through the sptes linked by a
1098 * rmap. All fields are private and not assumed to be used outside.
1100 struct rmap_iterator {
1101 /* private fields */
1102 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1103 int pos; /* index of the sptep */
1107 * Iteration must be started by this function. This should also be used after
1108 * removing/dropping sptes from the rmap link because in such cases the
1109 * information in the iterator may not be valid.
1111 * Returns sptep if found, NULL otherwise.
1113 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1114 struct rmap_iterator *iter)
1118 if (!rmap_head->val)
1121 if (!(rmap_head->val & 1)) {
1123 sptep = (u64 *)rmap_head->val;
1127 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1129 sptep = iter->desc->sptes[iter->pos];
1131 BUG_ON(!is_shadow_present_pte(*sptep));
1136 * Must be used with a valid iterator: e.g. after rmap_get_first().
1138 * Returns sptep if found, NULL otherwise.
1140 static u64 *rmap_get_next(struct rmap_iterator *iter)
1145 if (iter->pos < PTE_LIST_EXT - 1) {
1147 sptep = iter->desc->sptes[iter->pos];
1152 iter->desc = iter->desc->more;
1156 /* desc->sptes[0] cannot be NULL */
1157 sptep = iter->desc->sptes[iter->pos];
1164 BUG_ON(!is_shadow_present_pte(*sptep));
1168 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1169 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1170 _spte_; _spte_ = rmap_get_next(_iter_))
1172 static void drop_spte(struct kvm *kvm, u64 *sptep)
1174 u64 old_spte = mmu_spte_clear_track_bits(kvm, sptep);
1176 if (is_shadow_present_pte(old_spte))
1177 rmap_remove(kvm, sptep);
1181 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1183 if (is_large_pte(*sptep)) {
1184 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1185 drop_spte(kvm, sptep);
1192 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1194 if (__drop_large_spte(vcpu->kvm, sptep)) {
1195 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1197 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1198 KVM_PAGES_PER_HPAGE(sp->role.level));
1203 * Write-protect on the specified @sptep, @pt_protect indicates whether
1204 * spte write-protection is caused by protecting shadow page table.
1206 * Note: write protection is difference between dirty logging and spte
1208 * - for dirty logging, the spte can be set to writable at anytime if
1209 * its dirty bitmap is properly set.
1210 * - for spte protection, the spte can be writable only after unsync-ing
1213 * Return true if tlb need be flushed.
1215 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1219 if (!is_writable_pte(spte) &&
1220 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1223 rmap_printk("spte %p %llx\n", sptep, *sptep);
1226 spte &= ~shadow_mmu_writable_mask;
1227 spte = spte & ~PT_WRITABLE_MASK;
1229 return mmu_spte_update(sptep, spte);
1232 static bool __rmap_write_protect(struct kvm *kvm,
1233 struct kvm_rmap_head *rmap_head,
1237 struct rmap_iterator iter;
1240 for_each_rmap_spte(rmap_head, &iter, sptep)
1241 flush |= spte_write_protect(sptep, pt_protect);
1246 static bool spte_clear_dirty(u64 *sptep)
1250 rmap_printk("spte %p %llx\n", sptep, *sptep);
1252 MMU_WARN_ON(!spte_ad_enabled(spte));
1253 spte &= ~shadow_dirty_mask;
1254 return mmu_spte_update(sptep, spte);
1257 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1259 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1260 (unsigned long *)sptep);
1261 if (was_writable && !spte_ad_enabled(*sptep))
1262 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1264 return was_writable;
1268 * Gets the GFN ready for another round of dirty logging by clearing the
1269 * - D bit on ad-enabled SPTEs, and
1270 * - W bit on ad-disabled SPTEs.
1271 * Returns true iff any D or W bits were cleared.
1273 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1274 const struct kvm_memory_slot *slot)
1277 struct rmap_iterator iter;
1280 for_each_rmap_spte(rmap_head, &iter, sptep)
1281 if (spte_ad_need_write_protect(*sptep))
1282 flush |= spte_wrprot_for_clear_dirty(sptep);
1284 flush |= spte_clear_dirty(sptep);
1290 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1291 * @kvm: kvm instance
1292 * @slot: slot to protect
1293 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1294 * @mask: indicates which pages we should protect
1296 * Used when we do not need to care about huge page mappings.
1298 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1299 struct kvm_memory_slot *slot,
1300 gfn_t gfn_offset, unsigned long mask)
1302 struct kvm_rmap_head *rmap_head;
1304 if (is_tdp_mmu_enabled(kvm))
1305 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1306 slot->base_gfn + gfn_offset, mask, true);
1308 if (!kvm_memslots_have_rmaps(kvm))
1312 rmap_head = gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1314 __rmap_write_protect(kvm, rmap_head, false);
1316 /* clear the first set bit */
1322 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1323 * protect the page if the D-bit isn't supported.
1324 * @kvm: kvm instance
1325 * @slot: slot to clear D-bit
1326 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1327 * @mask: indicates which pages we should clear D-bit
1329 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1331 static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1332 struct kvm_memory_slot *slot,
1333 gfn_t gfn_offset, unsigned long mask)
1335 struct kvm_rmap_head *rmap_head;
1337 if (is_tdp_mmu_enabled(kvm))
1338 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1339 slot->base_gfn + gfn_offset, mask, false);
1341 if (!kvm_memslots_have_rmaps(kvm))
1345 rmap_head = gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1347 __rmap_clear_dirty(kvm, rmap_head, slot);
1349 /* clear the first set bit */
1355 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1358 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1359 * enable dirty logging for them.
1361 * We need to care about huge page mappings: e.g. during dirty logging we may
1362 * have such mappings.
1364 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1365 struct kvm_memory_slot *slot,
1366 gfn_t gfn_offset, unsigned long mask)
1369 * Huge pages are NOT write protected when we start dirty logging in
1370 * initially-all-set mode; must write protect them here so that they
1371 * are split to 4K on the first write.
1373 * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn
1374 * of memslot has no such restriction, so the range can cross two large
1377 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) {
1378 gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask);
1379 gfn_t end = slot->base_gfn + gfn_offset + __fls(mask);
1381 kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M);
1383 /* Cross two large pages? */
1384 if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) !=
1385 ALIGN(end << PAGE_SHIFT, PMD_SIZE))
1386 kvm_mmu_slot_gfn_write_protect(kvm, slot, end,
1390 /* Now handle 4K PTEs. */
1391 if (kvm_x86_ops.cpu_dirty_log_size)
1392 kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask);
1394 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1397 int kvm_cpu_dirty_log_size(void)
1399 return kvm_x86_ops.cpu_dirty_log_size;
1402 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1403 struct kvm_memory_slot *slot, u64 gfn,
1406 struct kvm_rmap_head *rmap_head;
1408 bool write_protected = false;
1410 if (kvm_memslots_have_rmaps(kvm)) {
1411 for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1412 rmap_head = gfn_to_rmap(gfn, i, slot);
1413 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1417 if (is_tdp_mmu_enabled(kvm))
1419 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level);
1421 return write_protected;
1424 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1426 struct kvm_memory_slot *slot;
1428 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1429 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K);
1432 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1433 const struct kvm_memory_slot *slot)
1435 return pte_list_destroy(kvm, rmap_head);
1438 static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1439 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1442 return kvm_zap_rmapp(kvm, rmap_head, slot);
1445 static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1446 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1450 struct rmap_iterator iter;
1451 bool need_flush = false;
1455 WARN_ON(pte_huge(pte));
1456 new_pfn = pte_pfn(pte);
1459 for_each_rmap_spte(rmap_head, &iter, sptep) {
1460 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1461 sptep, *sptep, gfn, level);
1465 if (pte_write(pte)) {
1466 pte_list_remove(kvm, rmap_head, sptep);
1469 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1472 mmu_spte_clear_track_bits(kvm, sptep);
1473 mmu_spte_set(sptep, new_spte);
1477 if (need_flush && kvm_available_flush_tlb_with_range()) {
1478 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1485 struct slot_rmap_walk_iterator {
1487 const struct kvm_memory_slot *slot;
1493 /* output fields. */
1495 struct kvm_rmap_head *rmap;
1498 /* private field. */
1499 struct kvm_rmap_head *end_rmap;
1503 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1505 iterator->level = level;
1506 iterator->gfn = iterator->start_gfn;
1507 iterator->rmap = gfn_to_rmap(iterator->gfn, level, iterator->slot);
1508 iterator->end_rmap = gfn_to_rmap(iterator->end_gfn, level, iterator->slot);
1512 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1513 const struct kvm_memory_slot *slot, int start_level,
1514 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1516 iterator->slot = slot;
1517 iterator->start_level = start_level;
1518 iterator->end_level = end_level;
1519 iterator->start_gfn = start_gfn;
1520 iterator->end_gfn = end_gfn;
1522 rmap_walk_init_level(iterator, iterator->start_level);
1525 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1527 return !!iterator->rmap;
1530 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1532 if (++iterator->rmap <= iterator->end_rmap) {
1533 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1537 if (++iterator->level > iterator->end_level) {
1538 iterator->rmap = NULL;
1542 rmap_walk_init_level(iterator, iterator->level);
1545 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1546 _start_gfn, _end_gfn, _iter_) \
1547 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1548 _end_level_, _start_gfn, _end_gfn); \
1549 slot_rmap_walk_okay(_iter_); \
1550 slot_rmap_walk_next(_iter_))
1552 typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1553 struct kvm_memory_slot *slot, gfn_t gfn,
1554 int level, pte_t pte);
1556 static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm,
1557 struct kvm_gfn_range *range,
1558 rmap_handler_t handler)
1560 struct slot_rmap_walk_iterator iterator;
1563 for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL,
1564 range->start, range->end - 1, &iterator)
1565 ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn,
1566 iterator.level, range->pte);
1571 bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range)
1575 if (kvm_memslots_have_rmaps(kvm))
1576 flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp);
1578 if (is_tdp_mmu_enabled(kvm))
1579 flush = kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush);
1584 bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1588 if (kvm_memslots_have_rmaps(kvm))
1589 flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp);
1591 if (is_tdp_mmu_enabled(kvm))
1592 flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range);
1597 static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1598 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1602 struct rmap_iterator iter;
1605 for_each_rmap_spte(rmap_head, &iter, sptep)
1606 young |= mmu_spte_age(sptep);
1611 static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1612 struct kvm_memory_slot *slot, gfn_t gfn,
1613 int level, pte_t unused)
1616 struct rmap_iterator iter;
1618 for_each_rmap_spte(rmap_head, &iter, sptep)
1619 if (is_accessed_spte(*sptep))
1624 #define RMAP_RECYCLE_THRESHOLD 1000
1626 static void rmap_add(struct kvm_vcpu *vcpu, struct kvm_memory_slot *slot,
1627 u64 *spte, gfn_t gfn)
1629 struct kvm_mmu_page *sp;
1630 struct kvm_rmap_head *rmap_head;
1633 sp = sptep_to_sp(spte);
1634 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1635 rmap_head = gfn_to_rmap(gfn, sp->role.level, slot);
1636 rmap_count = pte_list_add(vcpu, spte, rmap_head);
1638 if (rmap_count > RMAP_RECYCLE_THRESHOLD) {
1639 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0));
1640 kvm_flush_remote_tlbs_with_address(
1641 vcpu->kvm, sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level));
1645 bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1649 if (kvm_memslots_have_rmaps(kvm))
1650 young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp);
1652 if (is_tdp_mmu_enabled(kvm))
1653 young |= kvm_tdp_mmu_age_gfn_range(kvm, range);
1658 bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1662 if (kvm_memslots_have_rmaps(kvm))
1663 young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp);
1665 if (is_tdp_mmu_enabled(kvm))
1666 young |= kvm_tdp_mmu_test_age_gfn(kvm, range);
1672 static int is_empty_shadow_page(u64 *spt)
1677 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1678 if (is_shadow_present_pte(*pos)) {
1679 printk(KERN_ERR "%s: %p %llx\n", __func__,
1688 * This value is the sum of all of the kvm instances's
1689 * kvm->arch.n_used_mmu_pages values. We need a global,
1690 * aggregate version in order to make the slab shrinker
1693 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, long nr)
1695 kvm->arch.n_used_mmu_pages += nr;
1696 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1699 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1701 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1702 hlist_del(&sp->hash_link);
1703 list_del(&sp->link);
1704 free_page((unsigned long)sp->spt);
1705 if (!sp->role.direct)
1706 free_page((unsigned long)sp->gfns);
1707 kmem_cache_free(mmu_page_header_cache, sp);
1710 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1712 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1715 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1716 struct kvm_mmu_page *sp, u64 *parent_pte)
1721 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1724 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1727 __pte_list_remove(parent_pte, &sp->parent_ptes);
1730 static void drop_parent_pte(struct kvm_mmu_page *sp,
1733 mmu_page_remove_parent_pte(sp, parent_pte);
1734 mmu_spte_clear_no_track(parent_pte);
1737 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1739 struct kvm_mmu_page *sp;
1741 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1742 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1744 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1745 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1748 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1749 * depends on valid pages being added to the head of the list. See
1750 * comments in kvm_zap_obsolete_pages().
1752 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1753 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1754 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1758 static void mark_unsync(u64 *spte);
1759 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1762 struct rmap_iterator iter;
1764 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1769 static void mark_unsync(u64 *spte)
1771 struct kvm_mmu_page *sp;
1774 sp = sptep_to_sp(spte);
1775 index = spte - sp->spt;
1776 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1778 if (sp->unsync_children++)
1780 kvm_mmu_mark_parents_unsync(sp);
1783 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1784 struct kvm_mmu_page *sp)
1789 #define KVM_PAGE_ARRAY_NR 16
1791 struct kvm_mmu_pages {
1792 struct mmu_page_and_offset {
1793 struct kvm_mmu_page *sp;
1795 } page[KVM_PAGE_ARRAY_NR];
1799 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1805 for (i=0; i < pvec->nr; i++)
1806 if (pvec->page[i].sp == sp)
1809 pvec->page[pvec->nr].sp = sp;
1810 pvec->page[pvec->nr].idx = idx;
1812 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1815 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1817 --sp->unsync_children;
1818 WARN_ON((int)sp->unsync_children < 0);
1819 __clear_bit(idx, sp->unsync_child_bitmap);
1822 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1823 struct kvm_mmu_pages *pvec)
1825 int i, ret, nr_unsync_leaf = 0;
1827 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1828 struct kvm_mmu_page *child;
1829 u64 ent = sp->spt[i];
1831 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1832 clear_unsync_child_bit(sp, i);
1836 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1838 if (child->unsync_children) {
1839 if (mmu_pages_add(pvec, child, i))
1842 ret = __mmu_unsync_walk(child, pvec);
1844 clear_unsync_child_bit(sp, i);
1846 } else if (ret > 0) {
1847 nr_unsync_leaf += ret;
1850 } else if (child->unsync) {
1852 if (mmu_pages_add(pvec, child, i))
1855 clear_unsync_child_bit(sp, i);
1858 return nr_unsync_leaf;
1861 #define INVALID_INDEX (-1)
1863 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1864 struct kvm_mmu_pages *pvec)
1867 if (!sp->unsync_children)
1870 mmu_pages_add(pvec, sp, INVALID_INDEX);
1871 return __mmu_unsync_walk(sp, pvec);
1874 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1876 WARN_ON(!sp->unsync);
1877 trace_kvm_mmu_sync_page(sp);
1879 --kvm->stat.mmu_unsync;
1882 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1883 struct list_head *invalid_list);
1884 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1885 struct list_head *invalid_list);
1887 #define for_each_valid_sp(_kvm, _sp, _list) \
1888 hlist_for_each_entry(_sp, _list, hash_link) \
1889 if (is_obsolete_sp((_kvm), (_sp))) { \
1892 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1893 for_each_valid_sp(_kvm, _sp, \
1894 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1895 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1897 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1898 struct list_head *invalid_list)
1900 int ret = vcpu->arch.mmu->sync_page(vcpu, sp);
1903 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1910 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1911 struct list_head *invalid_list,
1914 if (!remote_flush && list_empty(invalid_list))
1917 if (!list_empty(invalid_list))
1918 kvm_mmu_commit_zap_page(kvm, invalid_list);
1920 kvm_flush_remote_tlbs(kvm);
1924 #ifdef CONFIG_KVM_MMU_AUDIT
1925 #include "mmu_audit.c"
1927 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1928 static void mmu_audit_disable(void) { }
1931 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1933 if (sp->role.invalid)
1936 /* TDP MMU pages due not use the MMU generation. */
1937 return !sp->tdp_mmu_page &&
1938 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1941 struct mmu_page_path {
1942 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1943 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1946 #define for_each_sp(pvec, sp, parents, i) \
1947 for (i = mmu_pages_first(&pvec, &parents); \
1948 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1949 i = mmu_pages_next(&pvec, &parents, i))
1951 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1952 struct mmu_page_path *parents,
1957 for (n = i+1; n < pvec->nr; n++) {
1958 struct kvm_mmu_page *sp = pvec->page[n].sp;
1959 unsigned idx = pvec->page[n].idx;
1960 int level = sp->role.level;
1962 parents->idx[level-1] = idx;
1963 if (level == PG_LEVEL_4K)
1966 parents->parent[level-2] = sp;
1972 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1973 struct mmu_page_path *parents)
1975 struct kvm_mmu_page *sp;
1981 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1983 sp = pvec->page[0].sp;
1984 level = sp->role.level;
1985 WARN_ON(level == PG_LEVEL_4K);
1987 parents->parent[level-2] = sp;
1989 /* Also set up a sentinel. Further entries in pvec are all
1990 * children of sp, so this element is never overwritten.
1992 parents->parent[level-1] = NULL;
1993 return mmu_pages_next(pvec, parents, 0);
1996 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1998 struct kvm_mmu_page *sp;
1999 unsigned int level = 0;
2002 unsigned int idx = parents->idx[level];
2003 sp = parents->parent[level];
2007 WARN_ON(idx == INVALID_INDEX);
2008 clear_unsync_child_bit(sp, idx);
2010 } while (!sp->unsync_children);
2013 static int mmu_sync_children(struct kvm_vcpu *vcpu,
2014 struct kvm_mmu_page *parent, bool can_yield)
2017 struct kvm_mmu_page *sp;
2018 struct mmu_page_path parents;
2019 struct kvm_mmu_pages pages;
2020 LIST_HEAD(invalid_list);
2023 while (mmu_unsync_walk(parent, &pages)) {
2024 bool protected = false;
2026 for_each_sp(pages, sp, parents, i)
2027 protected |= rmap_write_protect(vcpu, sp->gfn);
2030 kvm_mmu_remote_flush_or_zap(vcpu->kvm, &invalid_list, true);
2034 for_each_sp(pages, sp, parents, i) {
2035 kvm_unlink_unsync_page(vcpu->kvm, sp);
2036 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2037 mmu_pages_clear_parents(&parents);
2039 if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) {
2040 kvm_mmu_remote_flush_or_zap(vcpu->kvm, &invalid_list, flush);
2042 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2046 cond_resched_rwlock_write(&vcpu->kvm->mmu_lock);
2051 kvm_mmu_remote_flush_or_zap(vcpu->kvm, &invalid_list, flush);
2055 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2057 atomic_set(&sp->write_flooding_count, 0);
2060 static void clear_sp_write_flooding_count(u64 *spte)
2062 __clear_sp_write_flooding_count(sptep_to_sp(spte));
2065 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2070 unsigned int access)
2072 bool direct_mmu = vcpu->arch.mmu->direct_map;
2073 union kvm_mmu_page_role role;
2074 struct hlist_head *sp_list;
2076 struct kvm_mmu_page *sp;
2078 LIST_HEAD(invalid_list);
2080 role = vcpu->arch.mmu->mmu_role.base;
2082 role.direct = direct;
2083 role.access = access;
2084 if (role.has_4_byte_gpte) {
2085 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2086 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2087 role.quadrant = quadrant;
2090 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2091 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2092 if (sp->gfn != gfn) {
2097 if (sp->role.word != role.word) {
2099 * If the guest is creating an upper-level page, zap
2100 * unsync pages for the same gfn. While it's possible
2101 * the guest is using recursive page tables, in all
2102 * likelihood the guest has stopped using the unsync
2103 * page and is installing a completely unrelated page.
2104 * Unsync pages must not be left as is, because the new
2105 * upper-level page will be write-protected.
2107 if (level > PG_LEVEL_4K && sp->unsync)
2108 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2114 goto trace_get_page;
2118 * The page is good, but is stale. kvm_sync_page does
2119 * get the latest guest state, but (unlike mmu_unsync_children)
2120 * it doesn't write-protect the page or mark it synchronized!
2121 * This way the validity of the mapping is ensured, but the
2122 * overhead of write protection is not incurred until the
2123 * guest invalidates the TLB mapping. This allows multiple
2124 * SPs for a single gfn to be unsync.
2126 * If the sync fails, the page is zapped. If so, break
2127 * in order to rebuild it.
2129 if (!kvm_sync_page(vcpu, sp, &invalid_list))
2132 WARN_ON(!list_empty(&invalid_list));
2133 kvm_flush_remote_tlbs(vcpu->kvm);
2136 __clear_sp_write_flooding_count(sp);
2139 trace_kvm_mmu_get_page(sp, false);
2143 ++vcpu->kvm->stat.mmu_cache_miss;
2145 sp = kvm_mmu_alloc_page(vcpu, direct);
2149 hlist_add_head(&sp->hash_link, sp_list);
2151 account_shadowed(vcpu->kvm, sp);
2152 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2153 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2155 trace_kvm_mmu_get_page(sp, true);
2157 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2159 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2160 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2164 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2165 struct kvm_vcpu *vcpu, hpa_t root,
2168 iterator->addr = addr;
2169 iterator->shadow_addr = root;
2170 iterator->level = vcpu->arch.mmu->shadow_root_level;
2172 if (iterator->level >= PT64_ROOT_4LEVEL &&
2173 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2174 !vcpu->arch.mmu->direct_map)
2175 iterator->level = PT32E_ROOT_LEVEL;
2177 if (iterator->level == PT32E_ROOT_LEVEL) {
2179 * prev_root is currently only used for 64-bit hosts. So only
2180 * the active root_hpa is valid here.
2182 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2184 iterator->shadow_addr
2185 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2186 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2188 if (!iterator->shadow_addr)
2189 iterator->level = 0;
2193 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2194 struct kvm_vcpu *vcpu, u64 addr)
2196 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2200 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2202 if (iterator->level < PG_LEVEL_4K)
2205 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2206 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2210 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2213 if (!is_shadow_present_pte(spte) || is_last_spte(spte, iterator->level)) {
2214 iterator->level = 0;
2218 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2222 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2224 __shadow_walk_next(iterator, *iterator->sptep);
2227 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2228 struct kvm_mmu_page *sp)
2232 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2234 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2236 mmu_spte_set(sptep, spte);
2238 mmu_page_add_parent_pte(vcpu, sp, sptep);
2240 if (sp->unsync_children || sp->unsync)
2244 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2245 unsigned direct_access)
2247 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2248 struct kvm_mmu_page *child;
2251 * For the direct sp, if the guest pte's dirty bit
2252 * changed form clean to dirty, it will corrupt the
2253 * sp's access: allow writable in the read-only sp,
2254 * so we should update the spte at this point to get
2255 * a new sp with the correct access.
2257 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2258 if (child->role.access == direct_access)
2261 drop_parent_pte(child, sptep);
2262 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2266 /* Returns the number of zapped non-leaf child shadow pages. */
2267 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2268 u64 *spte, struct list_head *invalid_list)
2271 struct kvm_mmu_page *child;
2274 if (is_shadow_present_pte(pte)) {
2275 if (is_last_spte(pte, sp->role.level)) {
2276 drop_spte(kvm, spte);
2278 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2279 drop_parent_pte(child, spte);
2282 * Recursively zap nested TDP SPs, parentless SPs are
2283 * unlikely to be used again in the near future. This
2284 * avoids retaining a large number of stale nested SPs.
2286 if (tdp_enabled && invalid_list &&
2287 child->role.guest_mode && !child->parent_ptes.val)
2288 return kvm_mmu_prepare_zap_page(kvm, child,
2291 } else if (is_mmio_spte(pte)) {
2292 mmu_spte_clear_no_track(spte);
2297 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2298 struct kvm_mmu_page *sp,
2299 struct list_head *invalid_list)
2304 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2305 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2310 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2313 struct rmap_iterator iter;
2315 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2316 drop_parent_pte(sp, sptep);
2319 static int mmu_zap_unsync_children(struct kvm *kvm,
2320 struct kvm_mmu_page *parent,
2321 struct list_head *invalid_list)
2324 struct mmu_page_path parents;
2325 struct kvm_mmu_pages pages;
2327 if (parent->role.level == PG_LEVEL_4K)
2330 while (mmu_unsync_walk(parent, &pages)) {
2331 struct kvm_mmu_page *sp;
2333 for_each_sp(pages, sp, parents, i) {
2334 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2335 mmu_pages_clear_parents(&parents);
2343 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2344 struct kvm_mmu_page *sp,
2345 struct list_head *invalid_list,
2350 trace_kvm_mmu_prepare_zap_page(sp);
2351 ++kvm->stat.mmu_shadow_zapped;
2352 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2353 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2354 kvm_mmu_unlink_parents(kvm, sp);
2356 /* Zapping children means active_mmu_pages has become unstable. */
2357 list_unstable = *nr_zapped;
2359 if (!sp->role.invalid && !sp->role.direct)
2360 unaccount_shadowed(kvm, sp);
2363 kvm_unlink_unsync_page(kvm, sp);
2364 if (!sp->root_count) {
2369 * Already invalid pages (previously active roots) are not on
2370 * the active page list. See list_del() in the "else" case of
2373 if (sp->role.invalid)
2374 list_add(&sp->link, invalid_list);
2376 list_move(&sp->link, invalid_list);
2377 kvm_mod_used_mmu_pages(kvm, -1);
2380 * Remove the active root from the active page list, the root
2381 * will be explicitly freed when the root_count hits zero.
2383 list_del(&sp->link);
2386 * Obsolete pages cannot be used on any vCPUs, see the comment
2387 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2388 * treats invalid shadow pages as being obsolete.
2390 if (!is_obsolete_sp(kvm, sp))
2391 kvm_reload_remote_mmus(kvm);
2394 if (sp->lpage_disallowed)
2395 unaccount_huge_nx_page(kvm, sp);
2397 sp->role.invalid = 1;
2398 return list_unstable;
2401 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2402 struct list_head *invalid_list)
2406 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2410 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2411 struct list_head *invalid_list)
2413 struct kvm_mmu_page *sp, *nsp;
2415 if (list_empty(invalid_list))
2419 * We need to make sure everyone sees our modifications to
2420 * the page tables and see changes to vcpu->mode here. The barrier
2421 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2422 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2424 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2425 * guest mode and/or lockless shadow page table walks.
2427 kvm_flush_remote_tlbs(kvm);
2429 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2430 WARN_ON(!sp->role.invalid || sp->root_count);
2431 kvm_mmu_free_page(sp);
2435 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2436 unsigned long nr_to_zap)
2438 unsigned long total_zapped = 0;
2439 struct kvm_mmu_page *sp, *tmp;
2440 LIST_HEAD(invalid_list);
2444 if (list_empty(&kvm->arch.active_mmu_pages))
2448 list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2450 * Don't zap active root pages, the page itself can't be freed
2451 * and zapping it will just force vCPUs to realloc and reload.
2456 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2458 total_zapped += nr_zapped;
2459 if (total_zapped >= nr_to_zap)
2466 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2468 kvm->stat.mmu_recycled += total_zapped;
2469 return total_zapped;
2472 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2474 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2475 return kvm->arch.n_max_mmu_pages -
2476 kvm->arch.n_used_mmu_pages;
2481 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2483 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2485 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2488 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2491 * Note, this check is intentionally soft, it only guarantees that one
2492 * page is available, while the caller may end up allocating as many as
2493 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2494 * exceeding the (arbitrary by default) limit will not harm the host,
2495 * being too aggressive may unnecessarily kill the guest, and getting an
2496 * exact count is far more trouble than it's worth, especially in the
2499 if (!kvm_mmu_available_pages(vcpu->kvm))
2505 * Changing the number of mmu pages allocated to the vm
2506 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2508 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2510 write_lock(&kvm->mmu_lock);
2512 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2513 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2516 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2519 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2521 write_unlock(&kvm->mmu_lock);
2524 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2526 struct kvm_mmu_page *sp;
2527 LIST_HEAD(invalid_list);
2530 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2532 write_lock(&kvm->mmu_lock);
2533 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2534 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2537 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2539 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2540 write_unlock(&kvm->mmu_lock);
2545 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2550 if (vcpu->arch.mmu->direct_map)
2553 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2555 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2560 static void kvm_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2562 trace_kvm_mmu_unsync_page(sp);
2563 ++kvm->stat.mmu_unsync;
2566 kvm_mmu_mark_parents_unsync(sp);
2570 * Attempt to unsync any shadow pages that can be reached by the specified gfn,
2571 * KVM is creating a writable mapping for said gfn. Returns 0 if all pages
2572 * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must
2573 * be write-protected.
2575 int mmu_try_to_unsync_pages(struct kvm *kvm, const struct kvm_memory_slot *slot,
2576 gfn_t gfn, bool can_unsync, bool prefetch)
2578 struct kvm_mmu_page *sp;
2579 bool locked = false;
2582 * Force write-protection if the page is being tracked. Note, the page
2583 * track machinery is used to write-protect upper-level shadow pages,
2584 * i.e. this guards the role.level == 4K assertion below!
2586 if (kvm_slot_page_track_is_active(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE))
2590 * The page is not write-tracked, mark existing shadow pages unsync
2591 * unless KVM is synchronizing an unsync SP (can_unsync = false). In
2592 * that case, KVM must complete emulation of the guest TLB flush before
2593 * allowing shadow pages to become unsync (writable by the guest).
2595 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2606 * TDP MMU page faults require an additional spinlock as they
2607 * run with mmu_lock held for read, not write, and the unsync
2608 * logic is not thread safe. Take the spinklock regardless of
2609 * the MMU type to avoid extra conditionals/parameters, there's
2610 * no meaningful penalty if mmu_lock is held for write.
2614 spin_lock(&kvm->arch.mmu_unsync_pages_lock);
2617 * Recheck after taking the spinlock, a different vCPU
2618 * may have since marked the page unsync. A false
2619 * positive on the unprotected check above is not
2620 * possible as clearing sp->unsync _must_ hold mmu_lock
2621 * for write, i.e. unsync cannot transition from 0->1
2622 * while this CPU holds mmu_lock for read (or write).
2624 if (READ_ONCE(sp->unsync))
2628 WARN_ON(sp->role.level != PG_LEVEL_4K);
2629 kvm_unsync_page(kvm, sp);
2632 spin_unlock(&kvm->arch.mmu_unsync_pages_lock);
2635 * We need to ensure that the marking of unsync pages is visible
2636 * before the SPTE is updated to allow writes because
2637 * kvm_mmu_sync_roots() checks the unsync flags without holding
2638 * the MMU lock and so can race with this. If the SPTE was updated
2639 * before the page had been marked as unsync-ed, something like the
2640 * following could happen:
2643 * ---------------------------------------------------------------------
2644 * 1.2 Host updates SPTE
2646 * 2.1 Guest writes a GPTE for GVA X.
2647 * (GPTE being in the guest page table shadowed
2648 * by the SP from CPU 1.)
2649 * This reads SPTE during the page table walk.
2650 * Since SPTE.W is read as 1, there is no
2653 * 2.2 Guest issues TLB flush.
2654 * That causes a VM Exit.
2656 * 2.3 Walking of unsync pages sees sp->unsync is
2657 * false and skips the page.
2659 * 2.4 Guest accesses GVA X.
2660 * Since the mapping in the SP was not updated,
2661 * so the old mapping for GVA X incorrectly
2665 * (sp->unsync = true)
2667 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2668 * the situation in 2.4 does not arise. It pairs with the read barrier
2669 * in is_unsync_root(), placed between 2.1's load of SPTE.W and 2.3.
2676 static int mmu_set_spte(struct kvm_vcpu *vcpu, struct kvm_memory_slot *slot,
2677 u64 *sptep, unsigned int pte_access, gfn_t gfn,
2678 kvm_pfn_t pfn, struct kvm_page_fault *fault)
2680 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
2681 int level = sp->role.level;
2682 int was_rmapped = 0;
2683 int ret = RET_PF_FIXED;
2688 /* Prefetching always gets a writable pfn. */
2689 bool host_writable = !fault || fault->map_writable;
2690 bool prefetch = !fault || fault->prefetch;
2691 bool write_fault = fault && fault->write;
2693 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2694 *sptep, write_fault, gfn);
2696 if (unlikely(is_noslot_pfn(pfn))) {
2697 mark_mmio_spte(vcpu, sptep, gfn, pte_access);
2698 return RET_PF_EMULATE;
2701 if (is_shadow_present_pte(*sptep)) {
2703 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2704 * the parent of the now unreachable PTE.
2706 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2707 struct kvm_mmu_page *child;
2710 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2711 drop_parent_pte(child, sptep);
2713 } else if (pfn != spte_to_pfn(*sptep)) {
2714 pgprintk("hfn old %llx new %llx\n",
2715 spte_to_pfn(*sptep), pfn);
2716 drop_spte(vcpu->kvm, sptep);
2722 wrprot = make_spte(vcpu, sp, slot, pte_access, gfn, pfn, *sptep, prefetch,
2723 true, host_writable, &spte);
2725 if (*sptep == spte) {
2726 ret = RET_PF_SPURIOUS;
2728 trace_kvm_mmu_set_spte(level, gfn, sptep);
2729 flush |= mmu_spte_update(sptep, spte);
2734 ret = RET_PF_EMULATE;
2738 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2739 KVM_PAGES_PER_HPAGE(level));
2741 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2744 WARN_ON_ONCE(ret == RET_PF_SPURIOUS);
2745 kvm_update_page_stats(vcpu->kvm, level, 1);
2746 rmap_add(vcpu, slot, sptep, gfn);
2752 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2753 struct kvm_mmu_page *sp,
2754 u64 *start, u64 *end)
2756 struct page *pages[PTE_PREFETCH_NUM];
2757 struct kvm_memory_slot *slot;
2758 unsigned int access = sp->role.access;
2762 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2763 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2767 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2771 for (i = 0; i < ret; i++, gfn++, start++) {
2772 mmu_set_spte(vcpu, slot, start, access, gfn,
2773 page_to_pfn(pages[i]), NULL);
2780 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2781 struct kvm_mmu_page *sp, u64 *sptep)
2783 u64 *spte, *start = NULL;
2786 WARN_ON(!sp->role.direct);
2788 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2791 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2792 if (is_shadow_present_pte(*spte) || spte == sptep) {
2795 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2802 direct_pte_prefetch_many(vcpu, sp, start, spte);
2805 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2807 struct kvm_mmu_page *sp;
2809 sp = sptep_to_sp(sptep);
2812 * Without accessed bits, there's no way to distinguish between
2813 * actually accessed translations and prefetched, so disable pte
2814 * prefetch if accessed bits aren't available.
2816 if (sp_ad_disabled(sp))
2819 if (sp->role.level > PG_LEVEL_4K)
2823 * If addresses are being invalidated, skip prefetching to avoid
2824 * accidentally prefetching those addresses.
2826 if (unlikely(vcpu->kvm->mmu_notifier_count))
2829 __direct_pte_prefetch(vcpu, sp, sptep);
2832 static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
2833 const struct kvm_memory_slot *slot)
2839 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2843 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2844 * is not solely for performance, it's also necessary to avoid the
2845 * "writable" check in __gfn_to_hva_many(), which will always fail on
2846 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2847 * page fault steps have already verified the guest isn't writing a
2848 * read-only memslot.
2850 hva = __gfn_to_hva_memslot(slot, gfn);
2852 pte = lookup_address_in_mm(kvm->mm, hva, &level);
2859 int kvm_mmu_max_mapping_level(struct kvm *kvm,
2860 const struct kvm_memory_slot *slot, gfn_t gfn,
2861 kvm_pfn_t pfn, int max_level)
2863 struct kvm_lpage_info *linfo;
2866 max_level = min(max_level, max_huge_page_level);
2867 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2868 linfo = lpage_info_slot(gfn, slot, max_level);
2869 if (!linfo->disallow_lpage)
2873 if (max_level == PG_LEVEL_4K)
2876 host_level = host_pfn_mapping_level(kvm, gfn, pfn, slot);
2877 return min(host_level, max_level);
2880 void kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
2882 struct kvm_memory_slot *slot = fault->slot;
2885 fault->huge_page_disallowed = fault->exec && fault->nx_huge_page_workaround_enabled;
2887 if (unlikely(fault->max_level == PG_LEVEL_4K))
2890 if (is_error_noslot_pfn(fault->pfn) || kvm_is_reserved_pfn(fault->pfn))
2893 if (kvm_slot_dirty_track_enabled(slot))
2897 * Enforce the iTLB multihit workaround after capturing the requested
2898 * level, which will be used to do precise, accurate accounting.
2900 fault->req_level = kvm_mmu_max_mapping_level(vcpu->kvm, slot,
2901 fault->gfn, fault->pfn,
2903 if (fault->req_level == PG_LEVEL_4K || fault->huge_page_disallowed)
2907 * mmu_notifier_retry() was successful and mmu_lock is held, so
2908 * the pmd can't be split from under us.
2910 fault->goal_level = fault->req_level;
2911 mask = KVM_PAGES_PER_HPAGE(fault->goal_level) - 1;
2912 VM_BUG_ON((fault->gfn & mask) != (fault->pfn & mask));
2913 fault->pfn &= ~mask;
2916 void disallowed_hugepage_adjust(struct kvm_page_fault *fault, u64 spte, int cur_level)
2918 if (cur_level > PG_LEVEL_4K &&
2919 cur_level == fault->goal_level &&
2920 is_shadow_present_pte(spte) &&
2921 !is_large_pte(spte)) {
2923 * A small SPTE exists for this pfn, but FNAME(fetch)
2924 * and __direct_map would like to create a large PTE
2925 * instead: just force them to go down another level,
2926 * patching back for them into pfn the next 9 bits of
2929 u64 page_mask = KVM_PAGES_PER_HPAGE(cur_level) -
2930 KVM_PAGES_PER_HPAGE(cur_level - 1);
2931 fault->pfn |= fault->gfn & page_mask;
2932 fault->goal_level--;
2936 static int __direct_map(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
2938 struct kvm_shadow_walk_iterator it;
2939 struct kvm_mmu_page *sp;
2941 gfn_t base_gfn = fault->gfn;
2943 kvm_mmu_hugepage_adjust(vcpu, fault);
2945 trace_kvm_mmu_spte_requested(fault);
2946 for_each_shadow_entry(vcpu, fault->addr, it) {
2948 * We cannot overwrite existing page tables with an NX
2949 * large page, as the leaf could be executable.
2951 if (fault->nx_huge_page_workaround_enabled)
2952 disallowed_hugepage_adjust(fault, *it.sptep, it.level);
2954 base_gfn = fault->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2955 if (it.level == fault->goal_level)
2958 drop_large_spte(vcpu, it.sptep);
2959 if (is_shadow_present_pte(*it.sptep))
2962 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2963 it.level - 1, true, ACC_ALL);
2965 link_shadow_page(vcpu, it.sptep, sp);
2966 if (fault->is_tdp && fault->huge_page_disallowed &&
2967 fault->req_level >= it.level)
2968 account_huge_nx_page(vcpu->kvm, sp);
2971 if (WARN_ON_ONCE(it.level != fault->goal_level))
2974 ret = mmu_set_spte(vcpu, fault->slot, it.sptep, ACC_ALL,
2975 base_gfn, fault->pfn, fault);
2976 if (ret == RET_PF_SPURIOUS)
2979 direct_pte_prefetch(vcpu, it.sptep);
2980 ++vcpu->stat.pf_fixed;
2984 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2986 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2989 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2992 * Do not cache the mmio info caused by writing the readonly gfn
2993 * into the spte otherwise read access on readonly gfn also can
2994 * caused mmio page fault and treat it as mmio access.
2996 if (pfn == KVM_PFN_ERR_RO_FAULT)
2997 return RET_PF_EMULATE;
2999 if (pfn == KVM_PFN_ERR_HWPOISON) {
3000 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3001 return RET_PF_RETRY;
3007 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault,
3008 unsigned int access, int *ret_val)
3010 /* The pfn is invalid, report the error! */
3011 if (unlikely(is_error_pfn(fault->pfn))) {
3012 *ret_val = kvm_handle_bad_page(vcpu, fault->gfn, fault->pfn);
3016 if (unlikely(!fault->slot)) {
3017 gva_t gva = fault->is_tdp ? 0 : fault->addr;
3019 vcpu_cache_mmio_info(vcpu, gva, fault->gfn,
3020 access & shadow_mmio_access_mask);
3022 * If MMIO caching is disabled, emulate immediately without
3023 * touching the shadow page tables as attempting to install an
3024 * MMIO SPTE will just be an expensive nop.
3026 if (unlikely(!shadow_mmio_value)) {
3027 *ret_val = RET_PF_EMULATE;
3035 static bool page_fault_can_be_fast(struct kvm_page_fault *fault)
3038 * Do not fix the mmio spte with invalid generation number which
3039 * need to be updated by slow page fault path.
3044 /* See if the page fault is due to an NX violation */
3045 if (unlikely(fault->exec && fault->present))
3049 * #PF can be fast if:
3050 * 1. The shadow page table entry is not present, which could mean that
3051 * the fault is potentially caused by access tracking (if enabled).
3052 * 2. The shadow page table entry is present and the fault
3053 * is caused by write-protect, that means we just need change the W
3054 * bit of the spte which can be done out of mmu-lock.
3056 * However, if access tracking is disabled we know that a non-present
3057 * page must be a genuine page fault where we have to create a new SPTE.
3058 * So, if access tracking is disabled, we return true only for write
3059 * accesses to a present page.
3062 return shadow_acc_track_mask != 0 || (fault->write && fault->present);
3066 * Returns true if the SPTE was fixed successfully. Otherwise,
3067 * someone else modified the SPTE from its original value.
3070 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault,
3071 u64 *sptep, u64 old_spte, u64 new_spte)
3074 * Theoretically we could also set dirty bit (and flush TLB) here in
3075 * order to eliminate unnecessary PML logging. See comments in
3076 * set_spte. But fast_page_fault is very unlikely to happen with PML
3077 * enabled, so we do not do this. This might result in the same GPA
3078 * to be logged in PML buffer again when the write really happens, and
3079 * eventually to be called by mark_page_dirty twice. But it's also no
3080 * harm. This also avoids the TLB flush needed after setting dirty bit
3081 * so non-PML cases won't be impacted.
3083 * Compare with set_spte where instead shadow_dirty_mask is set.
3085 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3088 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte))
3089 mark_page_dirty_in_slot(vcpu->kvm, fault->slot, fault->gfn);
3094 static bool is_access_allowed(struct kvm_page_fault *fault, u64 spte)
3097 return is_executable_pte(spte);
3100 return is_writable_pte(spte);
3102 /* Fault was on Read access */
3103 return spte & PT_PRESENT_MASK;
3107 * Returns the last level spte pointer of the shadow page walk for the given
3108 * gpa, and sets *spte to the spte value. This spte may be non-preset. If no
3109 * walk could be performed, returns NULL and *spte does not contain valid data.
3112 * - Must be called between walk_shadow_page_lockless_{begin,end}.
3113 * - The returned sptep must not be used after walk_shadow_page_lockless_end.
3115 static u64 *fast_pf_get_last_sptep(struct kvm_vcpu *vcpu, gpa_t gpa, u64 *spte)
3117 struct kvm_shadow_walk_iterator iterator;
3121 for_each_shadow_entry_lockless(vcpu, gpa, iterator, old_spte) {
3122 sptep = iterator.sptep;
3130 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3132 static int fast_page_fault(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
3134 struct kvm_mmu_page *sp;
3135 int ret = RET_PF_INVALID;
3138 uint retry_count = 0;
3140 if (!page_fault_can_be_fast(fault))
3143 walk_shadow_page_lockless_begin(vcpu);
3148 if (is_tdp_mmu(vcpu->arch.mmu))
3149 sptep = kvm_tdp_mmu_fast_pf_get_last_sptep(vcpu, fault->addr, &spte);
3151 sptep = fast_pf_get_last_sptep(vcpu, fault->addr, &spte);
3153 if (!is_shadow_present_pte(spte))
3156 sp = sptep_to_sp(sptep);
3157 if (!is_last_spte(spte, sp->role.level))
3161 * Check whether the memory access that caused the fault would
3162 * still cause it if it were to be performed right now. If not,
3163 * then this is a spurious fault caused by TLB lazily flushed,
3164 * or some other CPU has already fixed the PTE after the
3165 * current CPU took the fault.
3167 * Need not check the access of upper level table entries since
3168 * they are always ACC_ALL.
3170 if (is_access_allowed(fault, spte)) {
3171 ret = RET_PF_SPURIOUS;
3177 if (is_access_track_spte(spte))
3178 new_spte = restore_acc_track_spte(new_spte);
3181 * Currently, to simplify the code, write-protection can
3182 * be removed in the fast path only if the SPTE was
3183 * write-protected for dirty-logging or access tracking.
3186 spte_can_locklessly_be_made_writable(spte)) {
3187 new_spte |= PT_WRITABLE_MASK;
3190 * Do not fix write-permission on the large spte when
3191 * dirty logging is enabled. Since we only dirty the
3192 * first page into the dirty-bitmap in
3193 * fast_pf_fix_direct_spte(), other pages are missed
3194 * if its slot has dirty logging enabled.
3196 * Instead, we let the slow page fault path create a
3197 * normal spte to fix the access.
3199 if (sp->role.level > PG_LEVEL_4K &&
3200 kvm_slot_dirty_track_enabled(fault->slot))
3204 /* Verify that the fault can be handled in the fast path */
3205 if (new_spte == spte ||
3206 !is_access_allowed(fault, new_spte))
3210 * Currently, fast page fault only works for direct mapping
3211 * since the gfn is not stable for indirect shadow page. See
3212 * Documentation/virt/kvm/locking.rst to get more detail.
3214 if (fast_pf_fix_direct_spte(vcpu, fault, sptep, spte, new_spte)) {
3219 if (++retry_count > 4) {
3220 printk_once(KERN_WARNING
3221 "kvm: Fast #PF retrying more than 4 times.\n");
3227 trace_fast_page_fault(vcpu, fault, sptep, spte, ret);
3228 walk_shadow_page_lockless_end(vcpu);
3233 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3234 struct list_head *invalid_list)
3236 struct kvm_mmu_page *sp;
3238 if (!VALID_PAGE(*root_hpa))
3241 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3243 if (is_tdp_mmu_page(sp))
3244 kvm_tdp_mmu_put_root(kvm, sp, false);
3245 else if (!--sp->root_count && sp->role.invalid)
3246 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3248 *root_hpa = INVALID_PAGE;
3251 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3252 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3253 ulong roots_to_free)
3255 struct kvm *kvm = vcpu->kvm;
3257 LIST_HEAD(invalid_list);
3258 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3260 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3262 /* Before acquiring the MMU lock, see if we need to do any real work. */
3263 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3264 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3265 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3266 VALID_PAGE(mmu->prev_roots[i].hpa))
3269 if (i == KVM_MMU_NUM_PREV_ROOTS)
3273 write_lock(&kvm->mmu_lock);
3275 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3276 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3277 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3280 if (free_active_root) {
3281 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3282 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3283 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3284 } else if (mmu->pae_root) {
3285 for (i = 0; i < 4; ++i) {
3286 if (!IS_VALID_PAE_ROOT(mmu->pae_root[i]))
3289 mmu_free_root_page(kvm, &mmu->pae_root[i],
3291 mmu->pae_root[i] = INVALID_PAE_ROOT;
3294 mmu->root_hpa = INVALID_PAGE;
3298 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3299 write_unlock(&kvm->mmu_lock);
3301 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3303 void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3305 unsigned long roots_to_free = 0;
3310 * This should not be called while L2 is active, L2 can't invalidate
3311 * _only_ its own roots, e.g. INVVPID unconditionally exits.
3313 WARN_ON_ONCE(mmu->mmu_role.base.guest_mode);
3315 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3316 root_hpa = mmu->prev_roots[i].hpa;
3317 if (!VALID_PAGE(root_hpa))
3320 if (!to_shadow_page(root_hpa) ||
3321 to_shadow_page(root_hpa)->role.guest_mode)
3322 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
3325 kvm_mmu_free_roots(vcpu, mmu, roots_to_free);
3327 EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots);
3330 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3334 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3335 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3342 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3343 u8 level, bool direct)
3345 struct kvm_mmu_page *sp;
3347 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3350 return __pa(sp->spt);
3353 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3355 struct kvm_mmu *mmu = vcpu->arch.mmu;
3356 u8 shadow_root_level = mmu->shadow_root_level;
3361 write_lock(&vcpu->kvm->mmu_lock);
3362 r = make_mmu_pages_available(vcpu);
3366 if (is_tdp_mmu_enabled(vcpu->kvm)) {
3367 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3368 mmu->root_hpa = root;
3369 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3370 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true);
3371 mmu->root_hpa = root;
3372 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3373 if (WARN_ON_ONCE(!mmu->pae_root)) {
3378 for (i = 0; i < 4; ++i) {
3379 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3381 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3382 i << 30, PT32_ROOT_LEVEL, true);
3383 mmu->pae_root[i] = root | PT_PRESENT_MASK |
3386 mmu->root_hpa = __pa(mmu->pae_root);
3388 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level);
3393 /* root_pgd is ignored for direct MMUs. */
3396 write_unlock(&vcpu->kvm->mmu_lock);
3400 static int mmu_first_shadow_root_alloc(struct kvm *kvm)
3402 struct kvm_memslots *slots;
3403 struct kvm_memory_slot *slot;
3407 * Check if this is the first shadow root being allocated before
3410 if (kvm_shadow_root_allocated(kvm))
3413 mutex_lock(&kvm->slots_arch_lock);
3415 /* Recheck, under the lock, whether this is the first shadow root. */
3416 if (kvm_shadow_root_allocated(kvm))
3420 * Check if anything actually needs to be allocated, e.g. all metadata
3421 * will be allocated upfront if TDP is disabled.
3423 if (kvm_memslots_have_rmaps(kvm) &&
3424 kvm_page_track_write_tracking_enabled(kvm))
3427 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
3428 slots = __kvm_memslots(kvm, i);
3429 kvm_for_each_memslot(slot, bkt, slots) {
3431 * Both of these functions are no-ops if the target is
3432 * already allocated, so unconditionally calling both
3433 * is safe. Intentionally do NOT free allocations on
3434 * failure to avoid having to track which allocations
3435 * were made now versus when the memslot was created.
3436 * The metadata is guaranteed to be freed when the slot
3437 * is freed, and will be kept/used if userspace retries
3438 * KVM_RUN instead of killing the VM.
3440 r = memslot_rmap_alloc(slot, slot->npages);
3443 r = kvm_page_track_write_tracking_alloc(slot);
3450 * Ensure that shadow_root_allocated becomes true strictly after
3451 * all the related pointers are set.
3454 smp_store_release(&kvm->arch.shadow_root_allocated, true);
3457 mutex_unlock(&kvm->slots_arch_lock);
3461 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3463 struct kvm_mmu *mmu = vcpu->arch.mmu;
3464 u64 pdptrs[4], pm_mask;
3465 gfn_t root_gfn, root_pgd;
3470 root_pgd = mmu->get_guest_pgd(vcpu);
3471 root_gfn = root_pgd >> PAGE_SHIFT;
3473 if (mmu_check_root(vcpu, root_gfn))
3477 * On SVM, reading PDPTRs might access guest memory, which might fault
3478 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3480 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3481 for (i = 0; i < 4; ++i) {
3482 pdptrs[i] = mmu->get_pdptr(vcpu, i);
3483 if (!(pdptrs[i] & PT_PRESENT_MASK))
3486 if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT))
3491 r = mmu_first_shadow_root_alloc(vcpu->kvm);
3495 write_lock(&vcpu->kvm->mmu_lock);
3496 r = make_mmu_pages_available(vcpu);
3501 * Do we shadow a long mode page table? If so we need to
3502 * write-protect the guests page table root.
3504 if (mmu->root_level >= PT64_ROOT_4LEVEL) {
3505 root = mmu_alloc_root(vcpu, root_gfn, 0,
3506 mmu->shadow_root_level, false);
3507 mmu->root_hpa = root;
3511 if (WARN_ON_ONCE(!mmu->pae_root)) {
3517 * We shadow a 32 bit page table. This may be a legacy 2-level
3518 * or a PAE 3-level page table. In either case we need to be aware that
3519 * the shadow page table may be a PAE or a long mode page table.
3521 pm_mask = PT_PRESENT_MASK | shadow_me_mask;
3522 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3523 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3525 if (WARN_ON_ONCE(!mmu->pml4_root)) {
3529 mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask;
3531 if (mmu->shadow_root_level == PT64_ROOT_5LEVEL) {
3532 if (WARN_ON_ONCE(!mmu->pml5_root)) {
3536 mmu->pml5_root[0] = __pa(mmu->pml4_root) | pm_mask;
3540 for (i = 0; i < 4; ++i) {
3541 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3543 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3544 if (!(pdptrs[i] & PT_PRESENT_MASK)) {
3545 mmu->pae_root[i] = INVALID_PAE_ROOT;
3548 root_gfn = pdptrs[i] >> PAGE_SHIFT;
3551 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3552 PT32_ROOT_LEVEL, false);
3553 mmu->pae_root[i] = root | pm_mask;
3556 if (mmu->shadow_root_level == PT64_ROOT_5LEVEL)
3557 mmu->root_hpa = __pa(mmu->pml5_root);
3558 else if (mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3559 mmu->root_hpa = __pa(mmu->pml4_root);
3561 mmu->root_hpa = __pa(mmu->pae_root);
3564 mmu->root_pgd = root_pgd;
3566 write_unlock(&vcpu->kvm->mmu_lock);
3571 static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu)
3573 struct kvm_mmu *mmu = vcpu->arch.mmu;
3574 bool need_pml5 = mmu->shadow_root_level > PT64_ROOT_4LEVEL;
3575 u64 *pml5_root = NULL;
3576 u64 *pml4_root = NULL;
3580 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3581 * tables are allocated and initialized at root creation as there is no
3582 * equivalent level in the guest's NPT to shadow. Allocate the tables
3583 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
3585 if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL ||
3586 mmu->shadow_root_level < PT64_ROOT_4LEVEL)
3590 * NPT, the only paging mode that uses this horror, uses a fixed number
3591 * of levels for the shadow page tables, e.g. all MMUs are 4-level or
3592 * all MMus are 5-level. Thus, this can safely require that pml5_root
3593 * is allocated if the other roots are valid and pml5 is needed, as any
3594 * prior MMU would also have required pml5.
3596 if (mmu->pae_root && mmu->pml4_root && (!need_pml5 || mmu->pml5_root))
3600 * The special roots should always be allocated in concert. Yell and
3601 * bail if KVM ends up in a state where only one of the roots is valid.
3603 if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root ||
3604 (need_pml5 && mmu->pml5_root)))
3608 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3609 * doesn't need to be decrypted.
3611 pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3615 #ifdef CONFIG_X86_64
3616 pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3621 pml5_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3627 mmu->pae_root = pae_root;
3628 mmu->pml4_root = pml4_root;
3629 mmu->pml5_root = pml5_root;
3633 #ifdef CONFIG_X86_64
3635 free_page((unsigned long)pml4_root);
3637 free_page((unsigned long)pae_root);
3642 static bool is_unsync_root(hpa_t root)
3644 struct kvm_mmu_page *sp;
3646 if (!VALID_PAGE(root))
3650 * The read barrier orders the CPU's read of SPTE.W during the page table
3651 * walk before the reads of sp->unsync/sp->unsync_children here.
3653 * Even if another CPU was marking the SP as unsync-ed simultaneously,
3654 * any guest page table changes are not guaranteed to be visible anyway
3655 * until this VCPU issues a TLB flush strictly after those changes are
3656 * made. We only need to ensure that the other CPU sets these flags
3657 * before any actual changes to the page tables are made. The comments
3658 * in mmu_try_to_unsync_pages() describe what could go wrong if this
3659 * requirement isn't satisfied.
3662 sp = to_shadow_page(root);
3663 if (sp->unsync || sp->unsync_children)
3669 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3672 struct kvm_mmu_page *sp;
3674 if (vcpu->arch.mmu->direct_map)
3677 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3680 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3682 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3683 hpa_t root = vcpu->arch.mmu->root_hpa;
3684 sp = to_shadow_page(root);
3686 if (!is_unsync_root(root))
3689 write_lock(&vcpu->kvm->mmu_lock);
3690 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3692 mmu_sync_children(vcpu, sp, true);
3694 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3695 write_unlock(&vcpu->kvm->mmu_lock);
3699 write_lock(&vcpu->kvm->mmu_lock);
3700 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3702 for (i = 0; i < 4; ++i) {
3703 hpa_t root = vcpu->arch.mmu->pae_root[i];
3705 if (IS_VALID_PAE_ROOT(root)) {
3706 root &= PT64_BASE_ADDR_MASK;
3707 sp = to_shadow_page(root);
3708 mmu_sync_children(vcpu, sp, true);
3712 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3713 write_unlock(&vcpu->kvm->mmu_lock);
3716 void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu)
3718 unsigned long roots_to_free = 0;
3721 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3722 if (is_unsync_root(vcpu->arch.mmu->prev_roots[i].hpa))
3723 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
3725 /* sync prev_roots by simply freeing them */
3726 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
3729 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3730 gpa_t vaddr, u32 access,
3731 struct x86_exception *exception)
3734 exception->error_code = 0;
3735 return kvm_translate_gpa(vcpu, mmu, vaddr, access, exception);
3738 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3741 * A nested guest cannot use the MMIO cache if it is using nested
3742 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3744 if (mmu_is_nested(vcpu))
3748 return vcpu_match_mmio_gpa(vcpu, addr);
3750 return vcpu_match_mmio_gva(vcpu, addr);
3754 * Return the level of the lowest level SPTE added to sptes.
3755 * That SPTE may be non-present.
3757 * Must be called between walk_shadow_page_lockless_{begin,end}.
3759 static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
3761 struct kvm_shadow_walk_iterator iterator;
3765 for (shadow_walk_init(&iterator, vcpu, addr),
3766 *root_level = iterator.level;
3767 shadow_walk_okay(&iterator);
3768 __shadow_walk_next(&iterator, spte)) {
3769 leaf = iterator.level;
3770 spte = mmu_spte_get_lockless(iterator.sptep);
3778 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3779 static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3781 u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
3782 struct rsvd_bits_validate *rsvd_check;
3783 int root, leaf, level;
3784 bool reserved = false;
3786 walk_shadow_page_lockless_begin(vcpu);
3788 if (is_tdp_mmu(vcpu->arch.mmu))
3789 leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
3791 leaf = get_walk(vcpu, addr, sptes, &root);
3793 walk_shadow_page_lockless_end(vcpu);
3795 if (unlikely(leaf < 0)) {
3800 *sptep = sptes[leaf];
3803 * Skip reserved bits checks on the terminal leaf if it's not a valid
3804 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3805 * design, always have reserved bits set. The purpose of the checks is
3806 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3808 if (!is_shadow_present_pte(sptes[leaf]))
3811 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3813 for (level = root; level >= leaf; level--)
3814 reserved |= is_rsvd_spte(rsvd_check, sptes[level], level);
3817 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
3819 for (level = root; level >= leaf; level--)
3820 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3821 sptes[level], level,
3822 get_rsvd_bits(rsvd_check, sptes[level], level));
3828 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3833 if (mmio_info_in_cache(vcpu, addr, direct))
3834 return RET_PF_EMULATE;
3836 reserved = get_mmio_spte(vcpu, addr, &spte);
3837 if (WARN_ON(reserved))
3840 if (is_mmio_spte(spte)) {
3841 gfn_t gfn = get_mmio_spte_gfn(spte);
3842 unsigned int access = get_mmio_spte_access(spte);
3844 if (!check_mmio_spte(vcpu, spte))
3845 return RET_PF_INVALID;
3850 trace_handle_mmio_page_fault(addr, gfn, access);
3851 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3852 return RET_PF_EMULATE;
3856 * If the page table is zapped by other cpus, let CPU fault again on
3859 return RET_PF_RETRY;
3862 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3863 struct kvm_page_fault *fault)
3865 if (unlikely(fault->rsvd))
3868 if (!fault->present || !fault->write)
3872 * guest is writing the page which is write tracked which can
3873 * not be fixed by page fault handler.
3875 if (kvm_slot_page_track_is_active(vcpu->kvm, fault->slot, fault->gfn, KVM_PAGE_TRACK_WRITE))
3881 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3883 struct kvm_shadow_walk_iterator iterator;
3886 walk_shadow_page_lockless_begin(vcpu);
3887 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3888 clear_sp_write_flooding_count(iterator.sptep);
3889 walk_shadow_page_lockless_end(vcpu);
3892 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3895 struct kvm_arch_async_pf arch;
3897 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3899 arch.direct_map = vcpu->arch.mmu->direct_map;
3900 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3902 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3903 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3906 static bool kvm_faultin_pfn(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault, int *r)
3908 struct kvm_memory_slot *slot = fault->slot;
3912 * Retry the page fault if the gfn hit a memslot that is being deleted
3913 * or moved. This ensures any existing SPTEs for the old memslot will
3914 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3916 if (slot && (slot->flags & KVM_MEMSLOT_INVALID))
3919 if (!kvm_is_visible_memslot(slot)) {
3920 /* Don't expose private memslots to L2. */
3921 if (is_guest_mode(vcpu)) {
3923 fault->pfn = KVM_PFN_NOSLOT;
3924 fault->map_writable = false;
3928 * If the APIC access page exists but is disabled, go directly
3929 * to emulation without caching the MMIO access or creating a
3930 * MMIO SPTE. That way the cache doesn't need to be purged
3931 * when the AVIC is re-enabled.
3933 if (slot && slot->id == APIC_ACCESS_PAGE_PRIVATE_MEMSLOT &&
3934 !kvm_apicv_activated(vcpu->kvm)) {
3935 *r = RET_PF_EMULATE;
3941 fault->pfn = __gfn_to_pfn_memslot(slot, fault->gfn, false, &async,
3942 fault->write, &fault->map_writable,
3945 return false; /* *pfn has correct page already */
3947 if (!fault->prefetch && kvm_can_do_async_pf(vcpu)) {
3948 trace_kvm_try_async_get_page(fault->addr, fault->gfn);
3949 if (kvm_find_async_pf_gfn(vcpu, fault->gfn)) {
3950 trace_kvm_async_pf_doublefault(fault->addr, fault->gfn);
3951 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3953 } else if (kvm_arch_setup_async_pf(vcpu, fault->addr, fault->gfn))
3957 fault->pfn = __gfn_to_pfn_memslot(slot, fault->gfn, false, NULL,
3958 fault->write, &fault->map_writable,
3968 * Returns true if the page fault is stale and needs to be retried, i.e. if the
3969 * root was invalidated by a memslot update or a relevant mmu_notifier fired.
3971 static bool is_page_fault_stale(struct kvm_vcpu *vcpu,
3972 struct kvm_page_fault *fault, int mmu_seq)
3974 struct kvm_mmu_page *sp = to_shadow_page(vcpu->arch.mmu->root_hpa);
3976 /* Special roots, e.g. pae_root, are not backed by shadow pages. */
3977 if (sp && is_obsolete_sp(vcpu->kvm, sp))
3981 * Roots without an associated shadow page are considered invalid if
3982 * there is a pending request to free obsolete roots. The request is
3983 * only a hint that the current root _may_ be obsolete and needs to be
3984 * reloaded, e.g. if the guest frees a PGD that KVM is tracking as a
3985 * previous root, then __kvm_mmu_prepare_zap_page() signals all vCPUs
3986 * to reload even if no vCPU is actively using the root.
3988 if (!sp && kvm_test_request(KVM_REQ_MMU_RELOAD, vcpu))
3991 return fault->slot &&
3992 mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, fault->hva);
3995 static int direct_page_fault(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
3997 bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu);
3999 unsigned long mmu_seq;
4002 fault->gfn = fault->addr >> PAGE_SHIFT;
4003 fault->slot = kvm_vcpu_gfn_to_memslot(vcpu, fault->gfn);
4005 if (page_fault_handle_page_track(vcpu, fault))
4006 return RET_PF_EMULATE;
4008 r = fast_page_fault(vcpu, fault);
4009 if (r != RET_PF_INVALID)
4012 r = mmu_topup_memory_caches(vcpu, false);
4016 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4019 if (kvm_faultin_pfn(vcpu, fault, &r))
4022 if (handle_abnormal_pfn(vcpu, fault, ACC_ALL, &r))
4027 if (is_tdp_mmu_fault)
4028 read_lock(&vcpu->kvm->mmu_lock);
4030 write_lock(&vcpu->kvm->mmu_lock);
4032 if (is_page_fault_stale(vcpu, fault, mmu_seq))
4035 r = make_mmu_pages_available(vcpu);
4039 if (is_tdp_mmu_fault)
4040 r = kvm_tdp_mmu_map(vcpu, fault);
4042 r = __direct_map(vcpu, fault);
4045 if (is_tdp_mmu_fault)
4046 read_unlock(&vcpu->kvm->mmu_lock);
4048 write_unlock(&vcpu->kvm->mmu_lock);
4049 kvm_release_pfn_clean(fault->pfn);
4053 static int nonpaging_page_fault(struct kvm_vcpu *vcpu,
4054 struct kvm_page_fault *fault)
4056 pgprintk("%s: gva %lx error %x\n", __func__, fault->addr, fault->error_code);
4058 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
4059 fault->max_level = PG_LEVEL_2M;
4060 return direct_page_fault(vcpu, fault);
4063 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
4064 u64 fault_address, char *insn, int insn_len)
4067 u32 flags = vcpu->arch.apf.host_apf_flags;
4069 #ifndef CONFIG_X86_64
4070 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
4071 if (WARN_ON_ONCE(fault_address >> 32))
4075 vcpu->arch.l1tf_flush_l1d = true;
4077 trace_kvm_page_fault(fault_address, error_code);
4079 if (kvm_event_needs_reinjection(vcpu))
4080 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
4081 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
4083 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
4084 vcpu->arch.apf.host_apf_flags = 0;
4085 local_irq_disable();
4086 kvm_async_pf_task_wait_schedule(fault_address);
4089 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
4094 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
4096 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
4098 while (fault->max_level > PG_LEVEL_4K) {
4099 int page_num = KVM_PAGES_PER_HPAGE(fault->max_level);
4100 gfn_t base = (fault->addr >> PAGE_SHIFT) & ~(page_num - 1);
4102 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
4108 return direct_page_fault(vcpu, fault);
4111 static void nonpaging_init_context(struct kvm_mmu *context)
4113 context->page_fault = nonpaging_page_fault;
4114 context->gva_to_gpa = nonpaging_gva_to_gpa;
4115 context->sync_page = nonpaging_sync_page;
4116 context->invlpg = NULL;
4117 context->direct_map = true;
4120 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
4121 union kvm_mmu_page_role role)
4123 return (role.direct || pgd == root->pgd) &&
4124 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
4125 role.word == to_shadow_page(root->hpa)->role.word;
4129 * Find out if a previously cached root matching the new pgd/role is available.
4130 * The current root is also inserted into the cache.
4131 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4133 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4134 * false is returned. This root should now be freed by the caller.
4136 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4137 union kvm_mmu_page_role new_role)
4140 struct kvm_mmu_root_info root;
4141 struct kvm_mmu *mmu = vcpu->arch.mmu;
4143 root.pgd = mmu->root_pgd;
4144 root.hpa = mmu->root_hpa;
4146 if (is_root_usable(&root, new_pgd, new_role))
4149 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4150 swap(root, mmu->prev_roots[i]);
4152 if (is_root_usable(&root, new_pgd, new_role))
4156 mmu->root_hpa = root.hpa;
4157 mmu->root_pgd = root.pgd;
4159 return i < KVM_MMU_NUM_PREV_ROOTS;
4162 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4163 union kvm_mmu_page_role new_role)
4165 struct kvm_mmu *mmu = vcpu->arch.mmu;
4168 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4169 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4170 * later if necessary.
4172 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4173 mmu->root_level >= PT64_ROOT_4LEVEL)
4174 return cached_root_available(vcpu, new_pgd, new_role);
4179 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4180 union kvm_mmu_page_role new_role)
4182 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
4183 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
4188 * It's possible that the cached previous root page is obsolete because
4189 * of a change in the MMU generation number. However, changing the
4190 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
4191 * free the root set here and allocate a new one.
4193 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
4195 if (force_flush_and_sync_on_reuse) {
4196 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4197 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
4201 * The last MMIO access's GVA and GPA are cached in the VCPU. When
4202 * switching to a new CR3, that GVA->GPA mapping may no longer be
4203 * valid. So clear any cached MMIO info even when we don't need to sync
4204 * the shadow page tables.
4206 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4209 * If this is a direct root page, it doesn't have a write flooding
4210 * count. Otherwise, clear the write flooding count.
4212 if (!new_role.direct)
4213 __clear_sp_write_flooding_count(
4214 to_shadow_page(vcpu->arch.mmu->root_hpa));
4217 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd)
4219 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu));
4221 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
4223 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4225 return kvm_read_cr3(vcpu);
4228 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4229 unsigned int access)
4231 if (unlikely(is_mmio_spte(*sptep))) {
4232 if (gfn != get_mmio_spte_gfn(*sptep)) {
4233 mmu_spte_clear_no_track(sptep);
4237 mark_mmio_spte(vcpu, sptep, gfn, access);
4244 #define PTTYPE_EPT 18 /* arbitrary */
4245 #define PTTYPE PTTYPE_EPT
4246 #include "paging_tmpl.h"
4250 #include "paging_tmpl.h"
4254 #include "paging_tmpl.h"
4258 __reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check,
4259 u64 pa_bits_rsvd, int level, bool nx, bool gbpages,
4262 u64 gbpages_bit_rsvd = 0;
4263 u64 nonleaf_bit8_rsvd = 0;
4266 rsvd_check->bad_mt_xwr = 0;
4269 gbpages_bit_rsvd = rsvd_bits(7, 7);
4271 if (level == PT32E_ROOT_LEVEL)
4272 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62);
4274 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4276 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4278 high_bits_rsvd |= rsvd_bits(63, 63);
4281 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4282 * leaf entries) on AMD CPUs only.
4285 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4288 case PT32_ROOT_LEVEL:
4289 /* no rsvd bits for 2 level 4K page table entries */
4290 rsvd_check->rsvd_bits_mask[0][1] = 0;
4291 rsvd_check->rsvd_bits_mask[0][0] = 0;
4292 rsvd_check->rsvd_bits_mask[1][0] =
4293 rsvd_check->rsvd_bits_mask[0][0];
4296 rsvd_check->rsvd_bits_mask[1][1] = 0;
4300 if (is_cpuid_PSE36())
4301 /* 36bits PSE 4MB page */
4302 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4304 /* 32 bits PSE 4MB page */
4305 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4307 case PT32E_ROOT_LEVEL:
4308 rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
4311 rsvd_bits(1, 2); /* PDPTE */
4312 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
4313 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
4314 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4315 rsvd_bits(13, 20); /* large page */
4316 rsvd_check->rsvd_bits_mask[1][0] =
4317 rsvd_check->rsvd_bits_mask[0][0];
4319 case PT64_ROOT_5LEVEL:
4320 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd |
4323 rsvd_check->rsvd_bits_mask[1][4] =
4324 rsvd_check->rsvd_bits_mask[0][4];
4326 case PT64_ROOT_4LEVEL:
4327 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd |
4330 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd |
4332 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd;
4333 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4334 rsvd_check->rsvd_bits_mask[1][3] =
4335 rsvd_check->rsvd_bits_mask[0][3];
4336 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd |
4339 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4340 rsvd_bits(13, 20); /* large page */
4341 rsvd_check->rsvd_bits_mask[1][0] =
4342 rsvd_check->rsvd_bits_mask[0][0];
4347 static bool guest_can_use_gbpages(struct kvm_vcpu *vcpu)
4350 * If TDP is enabled, let the guest use GBPAGES if they're supported in
4351 * hardware. The hardware page walker doesn't let KVM disable GBPAGES,
4352 * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA
4353 * walk for performance and complexity reasons. Not to mention KVM
4354 * _can't_ solve the problem because GVA->GPA walks aren't visible to
4355 * KVM once a TDP translation is installed. Mimic hardware behavior so
4356 * that KVM's is at least consistent, i.e. doesn't randomly inject #PF.
4358 return tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) :
4359 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES);
4362 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4363 struct kvm_mmu *context)
4365 __reset_rsvds_bits_mask(&context->guest_rsvd_check,
4366 vcpu->arch.reserved_gpa_bits,
4367 context->root_level, is_efer_nx(context),
4368 guest_can_use_gbpages(vcpu),
4369 is_cr4_pse(context),
4370 guest_cpuid_is_amd_or_hygon(vcpu));
4374 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4375 u64 pa_bits_rsvd, bool execonly, int huge_page_level)
4377 u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4378 u64 large_1g_rsvd = 0, large_2m_rsvd = 0;
4381 if (huge_page_level < PG_LEVEL_1G)
4382 large_1g_rsvd = rsvd_bits(7, 7);
4383 if (huge_page_level < PG_LEVEL_2M)
4384 large_2m_rsvd = rsvd_bits(7, 7);
4386 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
4387 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
4388 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6) | large_1g_rsvd;
4389 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6) | large_2m_rsvd;
4390 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4393 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4394 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4395 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29) | large_1g_rsvd;
4396 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20) | large_2m_rsvd;
4397 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4399 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4400 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4401 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4402 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4403 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4405 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4406 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4408 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4411 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4412 struct kvm_mmu *context, bool execonly, int huge_page_level)
4414 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4415 vcpu->arch.reserved_gpa_bits, execonly,
4419 static inline u64 reserved_hpa_bits(void)
4421 return rsvd_bits(shadow_phys_bits, 63);
4425 * the page table on host is the shadow page table for the page
4426 * table in guest or amd nested guest, its mmu features completely
4427 * follow the features in guest.
4429 static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4430 struct kvm_mmu *context)
4433 * KVM uses NX when TDP is disabled to handle a variety of scenarios,
4434 * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
4435 * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
4436 * The iTLB multi-hit workaround can be toggled at any time, so assume
4437 * NX can be used by any non-nested shadow MMU to avoid having to reset
4438 * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
4440 bool uses_nx = is_efer_nx(context) || !tdp_enabled;
4442 /* @amd adds a check on bit of SPTEs, which KVM shouldn't use anyways. */
4444 /* KVM doesn't use 2-level page tables for the shadow MMU. */
4445 bool is_pse = false;
4446 struct rsvd_bits_validate *shadow_zero_check;
4449 WARN_ON_ONCE(context->shadow_root_level < PT32E_ROOT_LEVEL);
4451 shadow_zero_check = &context->shadow_zero_check;
4452 __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
4453 context->shadow_root_level, uses_nx,
4454 guest_can_use_gbpages(vcpu), is_pse, is_amd);
4456 if (!shadow_me_mask)
4459 for (i = context->shadow_root_level; --i >= 0;) {
4460 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4461 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4466 static inline bool boot_cpu_is_amd(void)
4468 WARN_ON_ONCE(!tdp_enabled);
4469 return shadow_x_mask == 0;
4473 * the direct page table on host, use as much mmu features as
4474 * possible, however, kvm currently does not do execution-protection.
4477 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4478 struct kvm_mmu *context)
4480 struct rsvd_bits_validate *shadow_zero_check;
4483 shadow_zero_check = &context->shadow_zero_check;
4485 if (boot_cpu_is_amd())
4486 __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
4487 context->shadow_root_level, false,
4488 boot_cpu_has(X86_FEATURE_GBPAGES),
4491 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4492 reserved_hpa_bits(), false,
4493 max_huge_page_level);
4495 if (!shadow_me_mask)
4498 for (i = context->shadow_root_level; --i >= 0;) {
4499 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4500 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4505 * as the comments in reset_shadow_zero_bits_mask() except it
4506 * is the shadow page table for intel nested guest.
4509 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4510 struct kvm_mmu *context, bool execonly)
4512 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4513 reserved_hpa_bits(), execonly,
4514 max_huge_page_level);
4517 #define BYTE_MASK(access) \
4518 ((1 & (access) ? 2 : 0) | \
4519 (2 & (access) ? 4 : 0) | \
4520 (3 & (access) ? 8 : 0) | \
4521 (4 & (access) ? 16 : 0) | \
4522 (5 & (access) ? 32 : 0) | \
4523 (6 & (access) ? 64 : 0) | \
4524 (7 & (access) ? 128 : 0))
4527 static void update_permission_bitmask(struct kvm_mmu *mmu, bool ept)
4531 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4532 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4533 const u8 u = BYTE_MASK(ACC_USER_MASK);
4535 bool cr4_smep = is_cr4_smep(mmu);
4536 bool cr4_smap = is_cr4_smap(mmu);
4537 bool cr0_wp = is_cr0_wp(mmu);
4538 bool efer_nx = is_efer_nx(mmu);
4540 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4541 unsigned pfec = byte << 1;
4544 * Each "*f" variable has a 1 bit for each UWX value
4545 * that causes a fault with the given PFEC.
4548 /* Faults from writes to non-writable pages */
4549 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4550 /* Faults from user mode accesses to supervisor pages */
4551 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4552 /* Faults from fetches of non-executable pages*/
4553 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4554 /* Faults from kernel mode fetches of user pages */
4556 /* Faults from kernel mode accesses of user pages */
4560 /* Faults from kernel mode accesses to user pages */
4561 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4563 /* Not really needed: !nx will cause pte.nx to fault */
4567 /* Allow supervisor writes if !cr0.wp */
4569 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4571 /* Disallow supervisor fetches of user code if cr4.smep */
4573 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4576 * SMAP:kernel-mode data accesses from user-mode
4577 * mappings should fault. A fault is considered
4578 * as a SMAP violation if all of the following
4579 * conditions are true:
4580 * - X86_CR4_SMAP is set in CR4
4581 * - A user page is accessed
4582 * - The access is not a fetch
4583 * - Page fault in kernel mode
4584 * - if CPL = 3 or X86_EFLAGS_AC is clear
4586 * Here, we cover the first three conditions.
4587 * The fourth is computed dynamically in permission_fault();
4588 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4589 * *not* subject to SMAP restrictions.
4592 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4595 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4600 * PKU is an additional mechanism by which the paging controls access to
4601 * user-mode addresses based on the value in the PKRU register. Protection
4602 * key violations are reported through a bit in the page fault error code.
4603 * Unlike other bits of the error code, the PK bit is not known at the
4604 * call site of e.g. gva_to_gpa; it must be computed directly in
4605 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4606 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4608 * In particular the following conditions come from the error code, the
4609 * page tables and the machine state:
4610 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4611 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4612 * - PK is always zero if U=0 in the page tables
4613 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4615 * The PKRU bitmask caches the result of these four conditions. The error
4616 * code (minus the P bit) and the page table's U bit form an index into the
4617 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4618 * with the two bits of the PKRU register corresponding to the protection key.
4619 * For the first three conditions above the bits will be 00, thus masking
4620 * away both AD and WD. For all reads or if the last condition holds, WD
4621 * only will be masked away.
4623 static void update_pkru_bitmask(struct kvm_mmu *mmu)
4630 if (!is_cr4_pke(mmu))
4633 wp = is_cr0_wp(mmu);
4635 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4636 unsigned pfec, pkey_bits;
4637 bool check_pkey, check_write, ff, uf, wf, pte_user;
4640 ff = pfec & PFERR_FETCH_MASK;
4641 uf = pfec & PFERR_USER_MASK;
4642 wf = pfec & PFERR_WRITE_MASK;
4644 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4645 pte_user = pfec & PFERR_RSVD_MASK;
4648 * Only need to check the access which is not an
4649 * instruction fetch and is to a user page.
4651 check_pkey = (!ff && pte_user);
4653 * write access is controlled by PKRU if it is a
4654 * user access or CR0.WP = 1.
4656 check_write = check_pkey && wf && (uf || wp);
4658 /* PKRU.AD stops both read and write access. */
4659 pkey_bits = !!check_pkey;
4660 /* PKRU.WD stops write access. */
4661 pkey_bits |= (!!check_write) << 1;
4663 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4667 static void reset_guest_paging_metadata(struct kvm_vcpu *vcpu,
4668 struct kvm_mmu *mmu)
4670 if (!is_cr0_pg(mmu))
4673 reset_rsvds_bits_mask(vcpu, mmu);
4674 update_permission_bitmask(mmu, false);
4675 update_pkru_bitmask(mmu);
4678 static void paging64_init_context(struct kvm_mmu *context)
4680 context->page_fault = paging64_page_fault;
4681 context->gva_to_gpa = paging64_gva_to_gpa;
4682 context->sync_page = paging64_sync_page;
4683 context->invlpg = paging64_invlpg;
4684 context->direct_map = false;
4687 static void paging32_init_context(struct kvm_mmu *context)
4689 context->page_fault = paging32_page_fault;
4690 context->gva_to_gpa = paging32_gva_to_gpa;
4691 context->sync_page = paging32_sync_page;
4692 context->invlpg = paging32_invlpg;
4693 context->direct_map = false;
4696 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu,
4697 struct kvm_mmu_role_regs *regs)
4699 union kvm_mmu_extended_role ext = {0};
4701 if (____is_cr0_pg(regs)) {
4703 ext.cr4_pae = ____is_cr4_pae(regs);
4704 ext.cr4_smep = ____is_cr4_smep(regs);
4705 ext.cr4_smap = ____is_cr4_smap(regs);
4706 ext.cr4_pse = ____is_cr4_pse(regs);
4708 /* PKEY and LA57 are active iff long mode is active. */
4709 ext.cr4_pke = ____is_efer_lma(regs) && ____is_cr4_pke(regs);
4710 ext.cr4_la57 = ____is_efer_lma(regs) && ____is_cr4_la57(regs);
4711 ext.efer_lma = ____is_efer_lma(regs);
4719 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4720 struct kvm_mmu_role_regs *regs,
4723 union kvm_mmu_role role = {0};
4725 role.base.access = ACC_ALL;
4726 if (____is_cr0_pg(regs)) {
4727 role.base.efer_nx = ____is_efer_nx(regs);
4728 role.base.cr0_wp = ____is_cr0_wp(regs);
4730 role.base.smm = is_smm(vcpu);
4731 role.base.guest_mode = is_guest_mode(vcpu);
4736 role.ext = kvm_calc_mmu_role_ext(vcpu, regs);
4741 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4743 /* tdp_root_level is architecture forced level, use it if nonzero */
4745 return tdp_root_level;
4747 /* Use 5-level TDP if and only if it's useful/necessary. */
4748 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4751 return max_tdp_level;
4754 static union kvm_mmu_role
4755 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu,
4756 struct kvm_mmu_role_regs *regs, bool base_only)
4758 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
4760 role.base.ad_disabled = (shadow_accessed_mask == 0);
4761 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4762 role.base.direct = true;
4763 role.base.has_4_byte_gpte = false;
4768 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4770 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4771 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4772 union kvm_mmu_role new_role =
4773 kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, false);
4775 if (new_role.as_u64 == context->mmu_role.as_u64)
4778 context->mmu_role.as_u64 = new_role.as_u64;
4779 context->page_fault = kvm_tdp_page_fault;
4780 context->sync_page = nonpaging_sync_page;
4781 context->invlpg = NULL;
4782 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4783 context->direct_map = true;
4784 context->get_guest_pgd = get_cr3;
4785 context->get_pdptr = kvm_pdptr_read;
4786 context->inject_page_fault = kvm_inject_page_fault;
4787 context->root_level = role_regs_to_root_level(®s);
4789 if (!is_cr0_pg(context))
4790 context->gva_to_gpa = nonpaging_gva_to_gpa;
4791 else if (is_cr4_pae(context))
4792 context->gva_to_gpa = paging64_gva_to_gpa;
4794 context->gva_to_gpa = paging32_gva_to_gpa;
4796 reset_guest_paging_metadata(vcpu, context);
4797 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4800 static union kvm_mmu_role
4801 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu,
4802 struct kvm_mmu_role_regs *regs, bool base_only)
4804 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
4806 role.base.smep_andnot_wp = role.ext.cr4_smep && !____is_cr0_wp(regs);
4807 role.base.smap_andnot_wp = role.ext.cr4_smap && !____is_cr0_wp(regs);
4808 role.base.has_4_byte_gpte = ____is_cr0_pg(regs) && !____is_cr4_pae(regs);
4813 static union kvm_mmu_role
4814 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu,
4815 struct kvm_mmu_role_regs *regs, bool base_only)
4817 union kvm_mmu_role role =
4818 kvm_calc_shadow_root_page_role_common(vcpu, regs, base_only);
4820 role.base.direct = !____is_cr0_pg(regs);
4822 if (!____is_efer_lma(regs))
4823 role.base.level = PT32E_ROOT_LEVEL;
4824 else if (____is_cr4_la57(regs))
4825 role.base.level = PT64_ROOT_5LEVEL;
4827 role.base.level = PT64_ROOT_4LEVEL;
4832 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4833 struct kvm_mmu_role_regs *regs,
4834 union kvm_mmu_role new_role)
4836 if (new_role.as_u64 == context->mmu_role.as_u64)
4839 context->mmu_role.as_u64 = new_role.as_u64;
4841 if (!is_cr0_pg(context))
4842 nonpaging_init_context(context);
4843 else if (is_cr4_pae(context))
4844 paging64_init_context(context);
4846 paging32_init_context(context);
4847 context->root_level = role_regs_to_root_level(regs);
4849 reset_guest_paging_metadata(vcpu, context);
4850 context->shadow_root_level = new_role.base.level;
4852 reset_shadow_zero_bits_mask(vcpu, context);
4855 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu,
4856 struct kvm_mmu_role_regs *regs)
4858 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4859 union kvm_mmu_role new_role =
4860 kvm_calc_shadow_mmu_root_page_role(vcpu, regs, false);
4862 shadow_mmu_init_context(vcpu, context, regs, new_role);
4865 static union kvm_mmu_role
4866 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu,
4867 struct kvm_mmu_role_regs *regs)
4869 union kvm_mmu_role role =
4870 kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
4872 role.base.direct = false;
4873 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4878 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
4879 unsigned long cr4, u64 efer, gpa_t nested_cr3)
4881 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4882 struct kvm_mmu_role_regs regs = {
4884 .cr4 = cr4 & ~X86_CR4_PKE,
4887 union kvm_mmu_role new_role;
4889 new_role = kvm_calc_shadow_npt_root_page_role(vcpu, ®s);
4891 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base);
4893 shadow_mmu_init_context(vcpu, context, ®s, new_role);
4895 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4897 static union kvm_mmu_role
4898 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4899 bool execonly, u8 level)
4901 union kvm_mmu_role role = {0};
4903 /* SMM flag is inherited from root_mmu */
4904 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4906 role.base.level = level;
4907 role.base.has_4_byte_gpte = false;
4908 role.base.direct = false;
4909 role.base.ad_disabled = !accessed_dirty;
4910 role.base.guest_mode = true;
4911 role.base.access = ACC_ALL;
4913 /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */
4915 role.ext.execonly = execonly;
4921 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4922 int huge_page_level, bool accessed_dirty,
4925 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4926 u8 level = vmx_eptp_page_walk_level(new_eptp);
4927 union kvm_mmu_role new_role =
4928 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4931 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base);
4933 if (new_role.as_u64 == context->mmu_role.as_u64)
4936 context->mmu_role.as_u64 = new_role.as_u64;
4938 context->shadow_root_level = level;
4940 context->ept_ad = accessed_dirty;
4941 context->page_fault = ept_page_fault;
4942 context->gva_to_gpa = ept_gva_to_gpa;
4943 context->sync_page = ept_sync_page;
4944 context->invlpg = ept_invlpg;
4945 context->root_level = level;
4946 context->direct_map = false;
4948 update_permission_bitmask(context, true);
4949 context->pkru_mask = 0;
4950 reset_rsvds_bits_mask_ept(vcpu, context, execonly, huge_page_level);
4951 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4953 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4955 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4957 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4958 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4960 kvm_init_shadow_mmu(vcpu, ®s);
4962 context->get_guest_pgd = get_cr3;
4963 context->get_pdptr = kvm_pdptr_read;
4964 context->inject_page_fault = kvm_inject_page_fault;
4967 static union kvm_mmu_role
4968 kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu, struct kvm_mmu_role_regs *regs)
4970 union kvm_mmu_role role;
4972 role = kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
4975 * Nested MMUs are used only for walking L2's gva->gpa, they never have
4976 * shadow pages of their own and so "direct" has no meaning. Set it
4977 * to "true" to try to detect bogus usage of the nested MMU.
4979 role.base.direct = true;
4980 role.base.level = role_regs_to_root_level(regs);
4984 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4986 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4987 union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu, ®s);
4988 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4990 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4993 g_context->mmu_role.as_u64 = new_role.as_u64;
4994 g_context->get_guest_pgd = get_cr3;
4995 g_context->get_pdptr = kvm_pdptr_read;
4996 g_context->inject_page_fault = kvm_inject_page_fault;
4997 g_context->root_level = new_role.base.level;
5000 * L2 page tables are never shadowed, so there is no need to sync
5003 g_context->invlpg = NULL;
5006 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
5007 * L1's nested page tables (e.g. EPT12). The nested translation
5008 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
5009 * L2's page tables as the first level of translation and L1's
5010 * nested page tables as the second level of translation. Basically
5011 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
5013 if (!is_paging(vcpu))
5014 g_context->gva_to_gpa = nonpaging_gva_to_gpa;
5015 else if (is_long_mode(vcpu))
5016 g_context->gva_to_gpa = paging64_gva_to_gpa;
5017 else if (is_pae(vcpu))
5018 g_context->gva_to_gpa = paging64_gva_to_gpa;
5020 g_context->gva_to_gpa = paging32_gva_to_gpa;
5022 reset_guest_paging_metadata(vcpu, g_context);
5025 void kvm_init_mmu(struct kvm_vcpu *vcpu)
5027 if (mmu_is_nested(vcpu))
5028 init_kvm_nested_mmu(vcpu);
5029 else if (tdp_enabled)
5030 init_kvm_tdp_mmu(vcpu);
5032 init_kvm_softmmu(vcpu);
5034 EXPORT_SYMBOL_GPL(kvm_init_mmu);
5036 static union kvm_mmu_page_role
5037 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
5039 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
5040 union kvm_mmu_role role;
5043 role = kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, true);
5045 role = kvm_calc_shadow_mmu_root_page_role(vcpu, ®s, true);
5050 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu)
5053 * Invalidate all MMU roles to force them to reinitialize as CPUID
5054 * information is factored into reserved bit calculations.
5056 * Correctly handling multiple vCPU models with respect to paging and
5057 * physical address properties) in a single VM would require tracking
5058 * all relevant CPUID information in kvm_mmu_page_role. That is very
5059 * undesirable as it would increase the memory requirements for
5060 * gfn_track (see struct kvm_mmu_page_role comments). For now that
5061 * problem is swept under the rug; KVM's CPUID API is horrific and
5062 * it's all but impossible to solve it without introducing a new API.
5064 vcpu->arch.root_mmu.mmu_role.ext.valid = 0;
5065 vcpu->arch.guest_mmu.mmu_role.ext.valid = 0;
5066 vcpu->arch.nested_mmu.mmu_role.ext.valid = 0;
5067 kvm_mmu_reset_context(vcpu);
5070 * Changing guest CPUID after KVM_RUN is forbidden, see the comment in
5071 * kvm_arch_vcpu_ioctl().
5073 KVM_BUG_ON(vcpu->arch.last_vmentry_cpu != -1, vcpu->kvm);
5076 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
5078 kvm_mmu_unload(vcpu);
5081 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
5083 int kvm_mmu_load(struct kvm_vcpu *vcpu)
5087 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
5090 r = mmu_alloc_special_roots(vcpu);
5093 if (vcpu->arch.mmu->direct_map)
5094 r = mmu_alloc_direct_roots(vcpu);
5096 r = mmu_alloc_shadow_roots(vcpu);
5100 kvm_mmu_sync_roots(vcpu);
5102 kvm_mmu_load_pgd(vcpu);
5103 static_call(kvm_x86_tlb_flush_current)(vcpu);
5108 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
5110 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
5111 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
5112 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
5113 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
5116 static bool need_remote_flush(u64 old, u64 new)
5118 if (!is_shadow_present_pte(old))
5120 if (!is_shadow_present_pte(new))
5122 if ((old ^ new) & PT64_BASE_ADDR_MASK)
5124 old ^= shadow_nx_mask;
5125 new ^= shadow_nx_mask;
5126 return (old & ~new & PT64_PERM_MASK) != 0;
5129 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
5136 * Assume that the pte write on a page table of the same type
5137 * as the current vcpu paging mode since we update the sptes only
5138 * when they have the same mode.
5140 if (is_pae(vcpu) && *bytes == 4) {
5141 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5146 if (*bytes == 4 || *bytes == 8) {
5147 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5156 * If we're seeing too many writes to a page, it may no longer be a page table,
5157 * or we may be forking, in which case it is better to unmap the page.
5159 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5162 * Skip write-flooding detected for the sp whose level is 1, because
5163 * it can become unsync, then the guest page is not write-protected.
5165 if (sp->role.level == PG_LEVEL_4K)
5168 atomic_inc(&sp->write_flooding_count);
5169 return atomic_read(&sp->write_flooding_count) >= 3;
5173 * Misaligned accesses are too much trouble to fix up; also, they usually
5174 * indicate a page is not used as a page table.
5176 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5179 unsigned offset, pte_size, misaligned;
5181 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5182 gpa, bytes, sp->role.word);
5184 offset = offset_in_page(gpa);
5185 pte_size = sp->role.has_4_byte_gpte ? 4 : 8;
5188 * Sometimes, the OS only writes the last one bytes to update status
5189 * bits, for example, in linux, andb instruction is used in clear_bit().
5191 if (!(offset & (pte_size - 1)) && bytes == 1)
5194 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5195 misaligned |= bytes < 4;
5200 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5202 unsigned page_offset, quadrant;
5206 page_offset = offset_in_page(gpa);
5207 level = sp->role.level;
5209 if (sp->role.has_4_byte_gpte) {
5210 page_offset <<= 1; /* 32->64 */
5212 * A 32-bit pde maps 4MB while the shadow pdes map
5213 * only 2MB. So we need to double the offset again
5214 * and zap two pdes instead of one.
5216 if (level == PT32_ROOT_LEVEL) {
5217 page_offset &= ~7; /* kill rounding error */
5221 quadrant = page_offset >> PAGE_SHIFT;
5222 page_offset &= ~PAGE_MASK;
5223 if (quadrant != sp->role.quadrant)
5227 spte = &sp->spt[page_offset / sizeof(*spte)];
5231 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5232 const u8 *new, int bytes,
5233 struct kvm_page_track_notifier_node *node)
5235 gfn_t gfn = gpa >> PAGE_SHIFT;
5236 struct kvm_mmu_page *sp;
5237 LIST_HEAD(invalid_list);
5238 u64 entry, gentry, *spte;
5243 * If we don't have indirect shadow pages, it means no page is
5244 * write-protected, so we can exit simply.
5246 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5249 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5252 * No need to care whether allocation memory is successful
5253 * or not since pte prefetch is skipped if it does not have
5254 * enough objects in the cache.
5256 mmu_topup_memory_caches(vcpu, true);
5258 write_lock(&vcpu->kvm->mmu_lock);
5260 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5262 ++vcpu->kvm->stat.mmu_pte_write;
5263 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5265 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5266 if (detect_write_misaligned(sp, gpa, bytes) ||
5267 detect_write_flooding(sp)) {
5268 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5269 ++vcpu->kvm->stat.mmu_flooded;
5273 spte = get_written_sptes(sp, gpa, &npte);
5279 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
5280 if (gentry && sp->role.level != PG_LEVEL_4K)
5281 ++vcpu->kvm->stat.mmu_pde_zapped;
5282 if (need_remote_flush(entry, *spte))
5287 kvm_mmu_remote_flush_or_zap(vcpu->kvm, &invalid_list, flush);
5288 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5289 write_unlock(&vcpu->kvm->mmu_lock);
5292 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5293 void *insn, int insn_len)
5295 int r, emulation_type = EMULTYPE_PF;
5296 bool direct = vcpu->arch.mmu->direct_map;
5298 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5299 return RET_PF_RETRY;
5302 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5303 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5304 if (r == RET_PF_EMULATE)
5308 if (r == RET_PF_INVALID) {
5309 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5310 lower_32_bits(error_code), false);
5311 if (KVM_BUG_ON(r == RET_PF_INVALID, vcpu->kvm))
5317 if (r != RET_PF_EMULATE)
5321 * Before emulating the instruction, check if the error code
5322 * was due to a RO violation while translating the guest page.
5323 * This can occur when using nested virtualization with nested
5324 * paging in both guests. If true, we simply unprotect the page
5325 * and resume the guest.
5327 if (vcpu->arch.mmu->direct_map &&
5328 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5329 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5334 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5335 * optimistically try to just unprotect the page and let the processor
5336 * re-execute the instruction that caused the page fault. Do not allow
5337 * retrying MMIO emulation, as it's not only pointless but could also
5338 * cause us to enter an infinite loop because the processor will keep
5339 * faulting on the non-existent MMIO address. Retrying an instruction
5340 * from a nested guest is also pointless and dangerous as we are only
5341 * explicitly shadowing L1's page tables, i.e. unprotecting something
5342 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5344 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5345 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5347 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5350 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5352 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5353 gva_t gva, hpa_t root_hpa)
5357 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5358 if (mmu != &vcpu->arch.guest_mmu) {
5359 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5360 if (is_noncanonical_address(gva, vcpu))
5363 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5369 if (root_hpa == INVALID_PAGE) {
5370 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5373 * INVLPG is required to invalidate any global mappings for the VA,
5374 * irrespective of PCID. Since it would take us roughly similar amount
5375 * of work to determine whether any of the prev_root mappings of the VA
5376 * is marked global, or to just sync it blindly, so we might as well
5377 * just always sync it.
5379 * Mappings not reachable via the current cr3 or the prev_roots will be
5380 * synced when switching to that cr3, so nothing needs to be done here
5383 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5384 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5385 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5387 mmu->invlpg(vcpu, gva, root_hpa);
5391 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5393 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.walk_mmu, gva, INVALID_PAGE);
5394 ++vcpu->stat.invlpg;
5396 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5399 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5401 struct kvm_mmu *mmu = vcpu->arch.mmu;
5402 bool tlb_flush = false;
5405 if (pcid == kvm_get_active_pcid(vcpu)) {
5406 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5410 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5411 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5412 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5413 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5419 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5421 ++vcpu->stat.invlpg;
5424 * Mappings not reachable via the current cr3 or the prev_roots will be
5425 * synced when switching to that cr3, so nothing needs to be done here
5430 void kvm_configure_mmu(bool enable_tdp, int tdp_forced_root_level,
5431 int tdp_max_root_level, int tdp_huge_page_level)
5433 tdp_enabled = enable_tdp;
5434 tdp_root_level = tdp_forced_root_level;
5435 max_tdp_level = tdp_max_root_level;
5438 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5439 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5440 * the kernel is not. But, KVM never creates a page size greater than
5441 * what is used by the kernel for any given HVA, i.e. the kernel's
5442 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5445 max_huge_page_level = tdp_huge_page_level;
5446 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5447 max_huge_page_level = PG_LEVEL_1G;
5449 max_huge_page_level = PG_LEVEL_2M;
5451 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5453 /* The return value indicates if tlb flush on all vcpus is needed. */
5454 typedef bool (*slot_level_handler) (struct kvm *kvm,
5455 struct kvm_rmap_head *rmap_head,
5456 const struct kvm_memory_slot *slot);
5458 /* The caller should hold mmu-lock before calling this function. */
5459 static __always_inline bool
5460 slot_handle_level_range(struct kvm *kvm, const struct kvm_memory_slot *memslot,
5461 slot_level_handler fn, int start_level, int end_level,
5462 gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield,
5465 struct slot_rmap_walk_iterator iterator;
5467 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5468 end_gfn, &iterator) {
5470 flush |= fn(kvm, iterator.rmap, memslot);
5472 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
5473 if (flush && flush_on_yield) {
5474 kvm_flush_remote_tlbs_with_address(kvm,
5476 iterator.gfn - start_gfn + 1);
5479 cond_resched_rwlock_write(&kvm->mmu_lock);
5486 static __always_inline bool
5487 slot_handle_level(struct kvm *kvm, const struct kvm_memory_slot *memslot,
5488 slot_level_handler fn, int start_level, int end_level,
5489 bool flush_on_yield)
5491 return slot_handle_level_range(kvm, memslot, fn, start_level,
5492 end_level, memslot->base_gfn,
5493 memslot->base_gfn + memslot->npages - 1,
5494 flush_on_yield, false);
5497 static __always_inline bool
5498 slot_handle_level_4k(struct kvm *kvm, const struct kvm_memory_slot *memslot,
5499 slot_level_handler fn, bool flush_on_yield)
5501 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5502 PG_LEVEL_4K, flush_on_yield);
5505 static void free_mmu_pages(struct kvm_mmu *mmu)
5507 if (!tdp_enabled && mmu->pae_root)
5508 set_memory_encrypted((unsigned long)mmu->pae_root, 1);
5509 free_page((unsigned long)mmu->pae_root);
5510 free_page((unsigned long)mmu->pml4_root);
5511 free_page((unsigned long)mmu->pml5_root);
5514 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5519 mmu->root_hpa = INVALID_PAGE;
5521 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5522 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5524 /* vcpu->arch.guest_mmu isn't used when !tdp_enabled. */
5525 if (!tdp_enabled && mmu == &vcpu->arch.guest_mmu)
5529 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5530 * while the PDP table is a per-vCPU construct that's allocated at MMU
5531 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5532 * x86_64. Therefore we need to allocate the PDP table in the first
5533 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5534 * generally doesn't use PAE paging and can skip allocating the PDP
5535 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5536 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5537 * KVM; that horror is handled on-demand by mmu_alloc_special_roots().
5539 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5542 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5546 mmu->pae_root = page_address(page);
5549 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5550 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5551 * that KVM's writes and the CPU's reads get along. Note, this is
5552 * only necessary when using shadow paging, as 64-bit NPT can get at
5553 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5554 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5557 set_memory_decrypted((unsigned long)mmu->pae_root, 1);
5559 WARN_ON_ONCE(shadow_me_mask);
5561 for (i = 0; i < 4; ++i)
5562 mmu->pae_root[i] = INVALID_PAE_ROOT;
5567 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5571 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5572 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5574 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5575 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5577 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5579 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5580 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5582 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5586 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5588 goto fail_allocate_root;
5592 free_mmu_pages(&vcpu->arch.guest_mmu);
5596 #define BATCH_ZAP_PAGES 10
5597 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5599 struct kvm_mmu_page *sp, *node;
5600 int nr_zapped, batch = 0;
5603 list_for_each_entry_safe_reverse(sp, node,
5604 &kvm->arch.active_mmu_pages, link) {
5606 * No obsolete valid page exists before a newly created page
5607 * since active_mmu_pages is a FIFO list.
5609 if (!is_obsolete_sp(kvm, sp))
5613 * Invalid pages should never land back on the list of active
5614 * pages. Skip the bogus page, otherwise we'll get stuck in an
5615 * infinite loop if the page gets put back on the list (again).
5617 if (WARN_ON(sp->role.invalid))
5621 * No need to flush the TLB since we're only zapping shadow
5622 * pages with an obsolete generation number and all vCPUS have
5623 * loaded a new root, i.e. the shadow pages being zapped cannot
5624 * be in active use by the guest.
5626 if (batch >= BATCH_ZAP_PAGES &&
5627 cond_resched_rwlock_write(&kvm->mmu_lock)) {
5632 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5633 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5640 * Trigger a remote TLB flush before freeing the page tables to ensure
5641 * KVM is not in the middle of a lockless shadow page table walk, which
5642 * may reference the pages.
5644 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5648 * Fast invalidate all shadow pages and use lock-break technique
5649 * to zap obsolete pages.
5651 * It's required when memslot is being deleted or VM is being
5652 * destroyed, in these cases, we should ensure that KVM MMU does
5653 * not use any resource of the being-deleted slot or all slots
5654 * after calling the function.
5656 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5658 lockdep_assert_held(&kvm->slots_lock);
5660 write_lock(&kvm->mmu_lock);
5661 trace_kvm_mmu_zap_all_fast(kvm);
5664 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5665 * held for the entire duration of zapping obsolete pages, it's
5666 * impossible for there to be multiple invalid generations associated
5667 * with *valid* shadow pages at any given time, i.e. there is exactly
5668 * one valid generation and (at most) one invalid generation.
5670 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5672 /* In order to ensure all threads see this change when
5673 * handling the MMU reload signal, this must happen in the
5674 * same critical section as kvm_reload_remote_mmus, and
5675 * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages
5676 * could drop the MMU lock and yield.
5678 if (is_tdp_mmu_enabled(kvm))
5679 kvm_tdp_mmu_invalidate_all_roots(kvm);
5682 * Notify all vcpus to reload its shadow page table and flush TLB.
5683 * Then all vcpus will switch to new shadow page table with the new
5686 * Note: we need to do this under the protection of mmu_lock,
5687 * otherwise, vcpu would purge shadow page but miss tlb flush.
5689 kvm_reload_remote_mmus(kvm);
5691 kvm_zap_obsolete_pages(kvm);
5693 write_unlock(&kvm->mmu_lock);
5695 if (is_tdp_mmu_enabled(kvm)) {
5696 read_lock(&kvm->mmu_lock);
5697 kvm_tdp_mmu_zap_invalidated_roots(kvm);
5698 read_unlock(&kvm->mmu_lock);
5702 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5704 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5707 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5708 struct kvm_memory_slot *slot,
5709 struct kvm_page_track_notifier_node *node)
5711 kvm_mmu_zap_all_fast(kvm);
5714 void kvm_mmu_init_vm(struct kvm *kvm)
5716 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5718 spin_lock_init(&kvm->arch.mmu_unsync_pages_lock);
5720 kvm_mmu_init_tdp_mmu(kvm);
5722 node->track_write = kvm_mmu_pte_write;
5723 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5724 kvm_page_track_register_notifier(kvm, node);
5727 void kvm_mmu_uninit_vm(struct kvm *kvm)
5729 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5731 kvm_page_track_unregister_notifier(kvm, node);
5733 kvm_mmu_uninit_tdp_mmu(kvm);
5736 static bool __kvm_zap_rmaps(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5738 const struct kvm_memory_slot *memslot;
5739 struct kvm_memslots *slots;
5740 struct kvm_memslot_iter iter;
5745 if (!kvm_memslots_have_rmaps(kvm))
5748 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5749 slots = __kvm_memslots(kvm, i);
5751 kvm_for_each_memslot_in_gfn_range(&iter, slots, gfn_start, gfn_end) {
5752 memslot = iter.slot;
5753 start = max(gfn_start, memslot->base_gfn);
5754 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5755 if (WARN_ON_ONCE(start >= end))
5758 flush = slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5760 PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL,
5761 start, end - 1, true, flush);
5769 * Invalidate (zap) SPTEs that cover GFNs from gfn_start and up to gfn_end
5770 * (not including it)
5772 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5777 if (WARN_ON_ONCE(gfn_end <= gfn_start))
5780 write_lock(&kvm->mmu_lock);
5782 kvm_inc_notifier_count(kvm, gfn_start, gfn_end);
5784 flush = __kvm_zap_rmaps(kvm, gfn_start, gfn_end);
5786 if (is_tdp_mmu_enabled(kvm)) {
5787 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++)
5788 flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start,
5793 kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
5794 gfn_end - gfn_start);
5796 kvm_dec_notifier_count(kvm, gfn_start, gfn_end);
5798 write_unlock(&kvm->mmu_lock);
5801 static bool slot_rmap_write_protect(struct kvm *kvm,
5802 struct kvm_rmap_head *rmap_head,
5803 const struct kvm_memory_slot *slot)
5805 return __rmap_write_protect(kvm, rmap_head, false);
5808 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5809 const struct kvm_memory_slot *memslot,
5814 if (kvm_memslots_have_rmaps(kvm)) {
5815 write_lock(&kvm->mmu_lock);
5816 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5817 start_level, KVM_MAX_HUGEPAGE_LEVEL,
5819 write_unlock(&kvm->mmu_lock);
5822 if (is_tdp_mmu_enabled(kvm)) {
5823 read_lock(&kvm->mmu_lock);
5824 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level);
5825 read_unlock(&kvm->mmu_lock);
5829 * Flush TLBs if any SPTEs had to be write-protected to ensure that
5830 * guest writes are reflected in the dirty bitmap before the memslot
5831 * update completes, i.e. before enabling dirty logging is visible to
5834 * Perform the TLB flush outside the mmu_lock to reduce the amount of
5835 * time the lock is held. However, this does mean that another CPU can
5836 * now grab mmu_lock and encounter a write-protected SPTE while CPUs
5837 * still have a writable mapping for the associated GFN in their TLB.
5839 * This is safe but requires KVM to be careful when making decisions
5840 * based on the write-protection status of an SPTE. Specifically, KVM
5841 * also write-protects SPTEs to monitor changes to guest page tables
5842 * during shadow paging, and must guarantee no CPUs can write to those
5843 * page before the lock is dropped. As mentioned in the previous
5844 * paragraph, a write-protected SPTE is no guarantee that CPU cannot
5845 * perform writes. So to determine if a TLB flush is truly required, KVM
5846 * will clear a separate software-only bit (MMU-writable) and skip the
5847 * flush if-and-only-if this bit was already clear.
5849 * See DEFAULT_SPTE_MMU_WRITEABLE for more details.
5852 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5855 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5856 struct kvm_rmap_head *rmap_head,
5857 const struct kvm_memory_slot *slot)
5860 struct rmap_iterator iter;
5861 int need_tlb_flush = 0;
5863 struct kvm_mmu_page *sp;
5866 for_each_rmap_spte(rmap_head, &iter, sptep) {
5867 sp = sptep_to_sp(sptep);
5868 pfn = spte_to_pfn(*sptep);
5871 * We cannot do huge page mapping for indirect shadow pages,
5872 * which are found on the last rmap (level = 1) when not using
5873 * tdp; such shadow pages are synced with the page table in
5874 * the guest, and the guest page table is using 4K page size
5875 * mapping if the indirect sp has level = 1.
5877 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5878 sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn,
5879 pfn, PG_LEVEL_NUM)) {
5880 pte_list_remove(kvm, rmap_head, sptep);
5882 if (kvm_available_flush_tlb_with_range())
5883 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5884 KVM_PAGES_PER_HPAGE(sp->role.level));
5892 return need_tlb_flush;
5895 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5896 const struct kvm_memory_slot *slot)
5898 if (kvm_memslots_have_rmaps(kvm)) {
5899 write_lock(&kvm->mmu_lock);
5901 * Zap only 4k SPTEs since the legacy MMU only supports dirty
5902 * logging at a 4k granularity and never creates collapsible
5903 * 2m SPTEs during dirty logging.
5905 if (slot_handle_level_4k(kvm, slot, kvm_mmu_zap_collapsible_spte, true))
5906 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5907 write_unlock(&kvm->mmu_lock);
5910 if (is_tdp_mmu_enabled(kvm)) {
5911 read_lock(&kvm->mmu_lock);
5912 kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot);
5913 read_unlock(&kvm->mmu_lock);
5917 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5918 const struct kvm_memory_slot *memslot)
5921 * All current use cases for flushing the TLBs for a specific memslot
5922 * related to dirty logging, and many do the TLB flush out of mmu_lock.
5923 * The interaction between the various operations on memslot must be
5924 * serialized by slots_locks to ensure the TLB flush from one operation
5925 * is observed by any other operation on the same memslot.
5927 lockdep_assert_held(&kvm->slots_lock);
5928 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5932 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5933 const struct kvm_memory_slot *memslot)
5937 if (kvm_memslots_have_rmaps(kvm)) {
5938 write_lock(&kvm->mmu_lock);
5940 * Clear dirty bits only on 4k SPTEs since the legacy MMU only
5941 * support dirty logging at a 4k granularity.
5943 flush = slot_handle_level_4k(kvm, memslot, __rmap_clear_dirty, false);
5944 write_unlock(&kvm->mmu_lock);
5947 if (is_tdp_mmu_enabled(kvm)) {
5948 read_lock(&kvm->mmu_lock);
5949 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5950 read_unlock(&kvm->mmu_lock);
5954 * It's also safe to flush TLBs out of mmu lock here as currently this
5955 * function is only used for dirty logging, in which case flushing TLB
5956 * out of mmu lock also guarantees no dirty pages will be lost in
5960 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5963 void kvm_mmu_zap_all(struct kvm *kvm)
5965 struct kvm_mmu_page *sp, *node;
5966 LIST_HEAD(invalid_list);
5969 write_lock(&kvm->mmu_lock);
5971 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5972 if (WARN_ON(sp->role.invalid))
5974 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5976 if (cond_resched_rwlock_write(&kvm->mmu_lock))
5980 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5982 if (is_tdp_mmu_enabled(kvm))
5983 kvm_tdp_mmu_zap_all(kvm);
5985 write_unlock(&kvm->mmu_lock);
5988 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5990 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5992 gen &= MMIO_SPTE_GEN_MASK;
5995 * Generation numbers are incremented in multiples of the number of
5996 * address spaces in order to provide unique generations across all
5997 * address spaces. Strip what is effectively the address space
5998 * modifier prior to checking for a wrap of the MMIO generation so
5999 * that a wrap in any address space is detected.
6001 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
6004 * The very rare case: if the MMIO generation number has wrapped,
6005 * zap all shadow pages.
6007 if (unlikely(gen == 0)) {
6008 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
6009 kvm_mmu_zap_all_fast(kvm);
6013 static unsigned long
6014 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
6017 int nr_to_scan = sc->nr_to_scan;
6018 unsigned long freed = 0;
6020 mutex_lock(&kvm_lock);
6022 list_for_each_entry(kvm, &vm_list, vm_list) {
6024 LIST_HEAD(invalid_list);
6027 * Never scan more than sc->nr_to_scan VM instances.
6028 * Will not hit this condition practically since we do not try
6029 * to shrink more than one VM and it is very unlikely to see
6030 * !n_used_mmu_pages so many times.
6035 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
6036 * here. We may skip a VM instance errorneosly, but we do not
6037 * want to shrink a VM that only started to populate its MMU
6040 if (!kvm->arch.n_used_mmu_pages &&
6041 !kvm_has_zapped_obsolete_pages(kvm))
6044 idx = srcu_read_lock(&kvm->srcu);
6045 write_lock(&kvm->mmu_lock);
6047 if (kvm_has_zapped_obsolete_pages(kvm)) {
6048 kvm_mmu_commit_zap_page(kvm,
6049 &kvm->arch.zapped_obsolete_pages);
6053 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
6056 write_unlock(&kvm->mmu_lock);
6057 srcu_read_unlock(&kvm->srcu, idx);
6060 * unfair on small ones
6061 * per-vm shrinkers cry out
6062 * sadness comes quickly
6064 list_move_tail(&kvm->vm_list, &vm_list);
6068 mutex_unlock(&kvm_lock);
6072 static unsigned long
6073 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
6075 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
6078 static struct shrinker mmu_shrinker = {
6079 .count_objects = mmu_shrink_count,
6080 .scan_objects = mmu_shrink_scan,
6081 .seeks = DEFAULT_SEEKS * 10,
6084 static void mmu_destroy_caches(void)
6086 kmem_cache_destroy(pte_list_desc_cache);
6087 kmem_cache_destroy(mmu_page_header_cache);
6090 static bool get_nx_auto_mode(void)
6092 /* Return true when CPU has the bug, and mitigations are ON */
6093 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
6096 static void __set_nx_huge_pages(bool val)
6098 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
6101 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
6103 bool old_val = nx_huge_pages;
6106 /* In "auto" mode deploy workaround only if CPU has the bug. */
6107 if (sysfs_streq(val, "off"))
6109 else if (sysfs_streq(val, "force"))
6111 else if (sysfs_streq(val, "auto"))
6112 new_val = get_nx_auto_mode();
6113 else if (strtobool(val, &new_val) < 0)
6116 __set_nx_huge_pages(new_val);
6118 if (new_val != old_val) {
6121 mutex_lock(&kvm_lock);
6123 list_for_each_entry(kvm, &vm_list, vm_list) {
6124 mutex_lock(&kvm->slots_lock);
6125 kvm_mmu_zap_all_fast(kvm);
6126 mutex_unlock(&kvm->slots_lock);
6128 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6130 mutex_unlock(&kvm_lock);
6136 int kvm_mmu_module_init(void)
6140 if (nx_huge_pages == -1)
6141 __set_nx_huge_pages(get_nx_auto_mode());
6144 * MMU roles use union aliasing which is, generally speaking, an
6145 * undefined behavior. However, we supposedly know how compilers behave
6146 * and the current status quo is unlikely to change. Guardians below are
6147 * supposed to let us know if the assumption becomes false.
6149 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
6150 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
6151 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
6153 kvm_mmu_reset_all_pte_masks();
6155 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
6156 sizeof(struct pte_list_desc),
6157 0, SLAB_ACCOUNT, NULL);
6158 if (!pte_list_desc_cache)
6161 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
6162 sizeof(struct kvm_mmu_page),
6163 0, SLAB_ACCOUNT, NULL);
6164 if (!mmu_page_header_cache)
6167 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
6170 ret = register_shrinker(&mmu_shrinker);
6177 mmu_destroy_caches();
6181 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6183 kvm_mmu_unload(vcpu);
6184 free_mmu_pages(&vcpu->arch.root_mmu);
6185 free_mmu_pages(&vcpu->arch.guest_mmu);
6186 mmu_free_memory_caches(vcpu);
6189 void kvm_mmu_module_exit(void)
6191 mmu_destroy_caches();
6192 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6193 unregister_shrinker(&mmu_shrinker);
6194 mmu_audit_disable();
6198 * Calculate the effective recovery period, accounting for '0' meaning "let KVM
6199 * select a halving time of 1 hour". Returns true if recovery is enabled.
6201 static bool calc_nx_huge_pages_recovery_period(uint *period)
6204 * Use READ_ONCE to get the params, this may be called outside of the
6205 * param setters, e.g. by the kthread to compute its next timeout.
6207 bool enabled = READ_ONCE(nx_huge_pages);
6208 uint ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6210 if (!enabled || !ratio)
6213 *period = READ_ONCE(nx_huge_pages_recovery_period_ms);
6215 /* Make sure the period is not less than one second. */
6216 ratio = min(ratio, 3600u);
6217 *period = 60 * 60 * 1000 / ratio;
6222 static int set_nx_huge_pages_recovery_param(const char *val, const struct kernel_param *kp)
6224 bool was_recovery_enabled, is_recovery_enabled;
6225 uint old_period, new_period;
6228 was_recovery_enabled = calc_nx_huge_pages_recovery_period(&old_period);
6230 err = param_set_uint(val, kp);
6234 is_recovery_enabled = calc_nx_huge_pages_recovery_period(&new_period);
6236 if (is_recovery_enabled &&
6237 (!was_recovery_enabled || old_period > new_period)) {
6240 mutex_lock(&kvm_lock);
6242 list_for_each_entry(kvm, &vm_list, vm_list)
6243 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6245 mutex_unlock(&kvm_lock);
6251 static void kvm_recover_nx_lpages(struct kvm *kvm)
6253 unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits;
6255 struct kvm_mmu_page *sp;
6257 LIST_HEAD(invalid_list);
6261 rcu_idx = srcu_read_lock(&kvm->srcu);
6262 write_lock(&kvm->mmu_lock);
6264 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6265 to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0;
6266 for ( ; to_zap; --to_zap) {
6267 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
6271 * We use a separate list instead of just using active_mmu_pages
6272 * because the number of lpage_disallowed pages is expected to
6273 * be relatively small compared to the total.
6275 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6276 struct kvm_mmu_page,
6277 lpage_disallowed_link);
6278 WARN_ON_ONCE(!sp->lpage_disallowed);
6279 if (is_tdp_mmu_page(sp)) {
6280 flush |= kvm_tdp_mmu_zap_sp(kvm, sp);
6282 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6283 WARN_ON_ONCE(sp->lpage_disallowed);
6286 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
6287 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6288 cond_resched_rwlock_write(&kvm->mmu_lock);
6292 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6294 write_unlock(&kvm->mmu_lock);
6295 srcu_read_unlock(&kvm->srcu, rcu_idx);
6298 static long get_nx_lpage_recovery_timeout(u64 start_time)
6303 enabled = calc_nx_huge_pages_recovery_period(&period);
6305 return enabled ? start_time + msecs_to_jiffies(period) - get_jiffies_64()
6306 : MAX_SCHEDULE_TIMEOUT;
6309 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6312 long remaining_time;
6315 start_time = get_jiffies_64();
6316 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6318 set_current_state(TASK_INTERRUPTIBLE);
6319 while (!kthread_should_stop() && remaining_time > 0) {
6320 schedule_timeout(remaining_time);
6321 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6322 set_current_state(TASK_INTERRUPTIBLE);
6325 set_current_state(TASK_RUNNING);
6327 if (kthread_should_stop())
6330 kvm_recover_nx_lpages(kvm);
6334 int kvm_mmu_post_init_vm(struct kvm *kvm)
6338 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6339 "kvm-nx-lpage-recovery",
6340 &kvm->arch.nx_lpage_recovery_thread);
6342 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6347 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6349 if (kvm->arch.nx_lpage_recovery_thread)
6350 kthread_stop(kvm->arch.nx_lpage_recovery_thread);