1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
51 #include <asm/set_memory.h>
53 #include <asm/kvm_page_track.h>
56 extern bool itlb_multihit_kvm_mitigation;
58 int __read_mostly nx_huge_pages = -1;
59 #ifdef CONFIG_PREEMPT_RT
60 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
61 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
63 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
66 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
67 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops nx_huge_pages_ops = {
70 .set = set_nx_huge_pages,
71 .get = param_get_bool,
74 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
75 .set = set_nx_huge_pages_recovery_ratio,
76 .get = param_get_uint,
79 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
80 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
81 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
82 &nx_huge_pages_recovery_ratio, 0644);
83 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
85 static bool __read_mostly force_flush_and_sync_on_reuse;
86 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
89 * When setting this variable to true it enables Two-Dimensional-Paging
90 * where the hardware walks 2 page tables:
91 * 1. the guest-virtual to guest-physical
92 * 2. while doing 1. it walks guest-physical to host-physical
93 * If the hardware supports that we don't need to do shadow paging.
95 bool tdp_enabled = false;
97 static int max_huge_page_level __read_mostly;
98 static int max_tdp_level __read_mostly;
101 AUDIT_PRE_PAGE_FAULT,
102 AUDIT_POST_PAGE_FAULT,
104 AUDIT_POST_PTE_WRITE,
111 module_param(dbg, bool, 0644);
114 #define PTE_PREFETCH_NUM 8
116 #define PT32_LEVEL_BITS 10
118 #define PT32_LEVEL_SHIFT(level) \
119 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
121 #define PT32_LVL_OFFSET_MASK(level) \
122 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT32_LEVEL_BITS))) - 1))
125 #define PT32_INDEX(address, level)\
126 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
129 #define PT32_BASE_ADDR_MASK PAGE_MASK
130 #define PT32_DIR_BASE_ADDR_MASK \
131 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
132 #define PT32_LVL_ADDR_MASK(level) \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
134 * PT32_LEVEL_BITS))) - 1))
136 #include <trace/events/kvm.h>
138 /* make pte_list_desc fit well in cache line */
139 #define PTE_LIST_EXT 3
141 struct pte_list_desc {
142 u64 *sptes[PTE_LIST_EXT];
143 struct pte_list_desc *more;
146 struct kvm_shadow_walk_iterator {
154 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
155 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
157 shadow_walk_okay(&(_walker)); \
158 shadow_walk_next(&(_walker)))
160 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
161 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
162 shadow_walk_okay(&(_walker)); \
163 shadow_walk_next(&(_walker)))
165 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
166 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
167 shadow_walk_okay(&(_walker)) && \
168 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
169 __shadow_walk_next(&(_walker), spte))
171 static struct kmem_cache *pte_list_desc_cache;
172 struct kmem_cache *mmu_page_header_cache;
173 static struct percpu_counter kvm_total_used_mmu_pages;
175 static void mmu_spte_set(u64 *sptep, u64 spte);
176 static union kvm_mmu_page_role
177 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
179 #define CREATE_TRACE_POINTS
180 #include "mmutrace.h"
183 static inline bool kvm_available_flush_tlb_with_range(void)
185 return kvm_x86_ops.tlb_remote_flush_with_range;
188 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
189 struct kvm_tlb_range *range)
193 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
194 ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range);
197 kvm_flush_remote_tlbs(kvm);
200 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
201 u64 start_gfn, u64 pages)
203 struct kvm_tlb_range range;
205 range.start_gfn = start_gfn;
208 kvm_flush_remote_tlbs_with_range(kvm, &range);
211 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
214 u64 spte = make_mmio_spte(vcpu, gfn, access);
216 trace_mark_mmio_spte(sptep, gfn, spte);
217 mmu_spte_set(sptep, spte);
220 static gfn_t get_mmio_spte_gfn(u64 spte)
222 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
224 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)
225 & shadow_nonpresent_or_rsvd_mask;
227 return gpa >> PAGE_SHIFT;
230 static unsigned get_mmio_spte_access(u64 spte)
232 return spte & shadow_mmio_access_mask;
235 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
237 u64 kvm_gen, spte_gen, gen;
239 gen = kvm_vcpu_memslots(vcpu)->generation;
240 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
243 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
244 spte_gen = get_mmio_spte_generation(spte);
246 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
247 return likely(kvm_gen == spte_gen);
250 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
251 struct x86_exception *exception)
253 /* Check if guest physical address doesn't exceed guest maximum */
254 if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) {
255 exception->error_code |= PFERR_RSVD_MASK;
262 static int is_cpuid_PSE36(void)
267 static int is_nx(struct kvm_vcpu *vcpu)
269 return vcpu->arch.efer & EFER_NX;
272 static gfn_t pse36_gfn_delta(u32 gpte)
274 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
276 return (gpte & PT32_DIR_PSE36_MASK) << shift;
280 static void __set_spte(u64 *sptep, u64 spte)
282 WRITE_ONCE(*sptep, spte);
285 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
287 WRITE_ONCE(*sptep, spte);
290 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
292 return xchg(sptep, spte);
295 static u64 __get_spte_lockless(u64 *sptep)
297 return READ_ONCE(*sptep);
308 static void count_spte_clear(u64 *sptep, u64 spte)
310 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
312 if (is_shadow_present_pte(spte))
315 /* Ensure the spte is completely set before we increase the count */
317 sp->clear_spte_count++;
320 static void __set_spte(u64 *sptep, u64 spte)
322 union split_spte *ssptep, sspte;
324 ssptep = (union split_spte *)sptep;
325 sspte = (union split_spte)spte;
327 ssptep->spte_high = sspte.spte_high;
330 * If we map the spte from nonpresent to present, We should store
331 * the high bits firstly, then set present bit, so cpu can not
332 * fetch this spte while we are setting the spte.
336 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
339 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
341 union split_spte *ssptep, sspte;
343 ssptep = (union split_spte *)sptep;
344 sspte = (union split_spte)spte;
346 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
349 * If we map the spte from present to nonpresent, we should clear
350 * present bit firstly to avoid vcpu fetch the old high bits.
354 ssptep->spte_high = sspte.spte_high;
355 count_spte_clear(sptep, spte);
358 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
360 union split_spte *ssptep, sspte, orig;
362 ssptep = (union split_spte *)sptep;
363 sspte = (union split_spte)spte;
365 /* xchg acts as a barrier before the setting of the high bits */
366 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
367 orig.spte_high = ssptep->spte_high;
368 ssptep->spte_high = sspte.spte_high;
369 count_spte_clear(sptep, spte);
375 * The idea using the light way get the spte on x86_32 guest is from
376 * gup_get_pte (mm/gup.c).
378 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
379 * coalesces them and we are running out of the MMU lock. Therefore
380 * we need to protect against in-progress updates of the spte.
382 * Reading the spte while an update is in progress may get the old value
383 * for the high part of the spte. The race is fine for a present->non-present
384 * change (because the high part of the spte is ignored for non-present spte),
385 * but for a present->present change we must reread the spte.
387 * All such changes are done in two steps (present->non-present and
388 * non-present->present), hence it is enough to count the number of
389 * present->non-present updates: if it changed while reading the spte,
390 * we might have hit the race. This is done using clear_spte_count.
392 static u64 __get_spte_lockless(u64 *sptep)
394 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
395 union split_spte spte, *orig = (union split_spte *)sptep;
399 count = sp->clear_spte_count;
402 spte.spte_low = orig->spte_low;
405 spte.spte_high = orig->spte_high;
408 if (unlikely(spte.spte_low != orig->spte_low ||
409 count != sp->clear_spte_count))
416 static bool spte_has_volatile_bits(u64 spte)
418 if (!is_shadow_present_pte(spte))
422 * Always atomically update spte if it can be updated
423 * out of mmu-lock, it can ensure dirty bit is not lost,
424 * also, it can help us to get a stable is_writable_pte()
425 * to ensure tlb flush is not missed.
427 if (spte_can_locklessly_be_made_writable(spte) ||
428 is_access_track_spte(spte))
431 if (spte_ad_enabled(spte)) {
432 if ((spte & shadow_accessed_mask) == 0 ||
433 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
440 /* Rules for using mmu_spte_set:
441 * Set the sptep from nonpresent to present.
442 * Note: the sptep being assigned *must* be either not present
443 * or in a state where the hardware will not attempt to update
446 static void mmu_spte_set(u64 *sptep, u64 new_spte)
448 WARN_ON(is_shadow_present_pte(*sptep));
449 __set_spte(sptep, new_spte);
453 * Update the SPTE (excluding the PFN), but do not track changes in its
454 * accessed/dirty status.
456 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
458 u64 old_spte = *sptep;
460 WARN_ON(!is_shadow_present_pte(new_spte));
462 if (!is_shadow_present_pte(old_spte)) {
463 mmu_spte_set(sptep, new_spte);
467 if (!spte_has_volatile_bits(old_spte))
468 __update_clear_spte_fast(sptep, new_spte);
470 old_spte = __update_clear_spte_slow(sptep, new_spte);
472 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
477 /* Rules for using mmu_spte_update:
478 * Update the state bits, it means the mapped pfn is not changed.
480 * Whenever we overwrite a writable spte with a read-only one we
481 * should flush remote TLBs. Otherwise rmap_write_protect
482 * will find a read-only spte, even though the writable spte
483 * might be cached on a CPU's TLB, the return value indicates this
486 * Returns true if the TLB needs to be flushed
488 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
491 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
493 if (!is_shadow_present_pte(old_spte))
497 * For the spte updated out of mmu-lock is safe, since
498 * we always atomically update it, see the comments in
499 * spte_has_volatile_bits().
501 if (spte_can_locklessly_be_made_writable(old_spte) &&
502 !is_writable_pte(new_spte))
506 * Flush TLB when accessed/dirty states are changed in the page tables,
507 * to guarantee consistency between TLB and page tables.
510 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
512 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
515 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
517 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
524 * Rules for using mmu_spte_clear_track_bits:
525 * It sets the sptep from present to nonpresent, and track the
526 * state bits, it is used to clear the last level sptep.
527 * Returns non-zero if the PTE was previously valid.
529 static int mmu_spte_clear_track_bits(u64 *sptep)
532 u64 old_spte = *sptep;
534 if (!spte_has_volatile_bits(old_spte))
535 __update_clear_spte_fast(sptep, 0ull);
537 old_spte = __update_clear_spte_slow(sptep, 0ull);
539 if (!is_shadow_present_pte(old_spte))
542 pfn = spte_to_pfn(old_spte);
545 * KVM does not hold the refcount of the page used by
546 * kvm mmu, before reclaiming the page, we should
547 * unmap it from mmu first.
549 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
551 if (is_accessed_spte(old_spte))
552 kvm_set_pfn_accessed(pfn);
554 if (is_dirty_spte(old_spte))
555 kvm_set_pfn_dirty(pfn);
561 * Rules for using mmu_spte_clear_no_track:
562 * Directly clear spte without caring the state bits of sptep,
563 * it is used to set the upper level spte.
565 static void mmu_spte_clear_no_track(u64 *sptep)
567 __update_clear_spte_fast(sptep, 0ull);
570 static u64 mmu_spte_get_lockless(u64 *sptep)
572 return __get_spte_lockless(sptep);
575 /* Restore an acc-track PTE back to a regular PTE */
576 static u64 restore_acc_track_spte(u64 spte)
579 u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
580 & SHADOW_ACC_TRACK_SAVED_BITS_MASK;
582 WARN_ON_ONCE(spte_ad_enabled(spte));
583 WARN_ON_ONCE(!is_access_track_spte(spte));
585 new_spte &= ~shadow_acc_track_mask;
586 new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
587 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
588 new_spte |= saved_bits;
593 /* Returns the Accessed status of the PTE and resets it at the same time. */
594 static bool mmu_spte_age(u64 *sptep)
596 u64 spte = mmu_spte_get_lockless(sptep);
598 if (!is_accessed_spte(spte))
601 if (spte_ad_enabled(spte)) {
602 clear_bit((ffs(shadow_accessed_mask) - 1),
603 (unsigned long *)sptep);
606 * Capture the dirty status of the page, so that it doesn't get
607 * lost when the SPTE is marked for access tracking.
609 if (is_writable_pte(spte))
610 kvm_set_pfn_dirty(spte_to_pfn(spte));
612 spte = mark_spte_for_access_track(spte);
613 mmu_spte_update_no_track(sptep, spte);
619 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
622 * Prevent page table teardown by making any free-er wait during
623 * kvm_flush_remote_tlbs() IPI to all active vcpus.
628 * Make sure a following spte read is not reordered ahead of the write
631 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
634 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
637 * Make sure the write to vcpu->mode is not reordered in front of
638 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
639 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
641 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
645 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
649 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
650 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
651 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
654 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
655 PT64_ROOT_MAX_LEVEL);
658 if (maybe_indirect) {
659 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
660 PT64_ROOT_MAX_LEVEL);
664 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
665 PT64_ROOT_MAX_LEVEL);
668 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
670 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
671 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
672 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
673 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
676 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
678 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
681 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
683 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
686 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
688 if (!sp->role.direct)
689 return sp->gfns[index];
691 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
694 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
696 if (!sp->role.direct) {
697 sp->gfns[index] = gfn;
701 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
702 pr_err_ratelimited("gfn mismatch under direct page %llx "
703 "(expected %llx, got %llx)\n",
705 kvm_mmu_page_get_gfn(sp, index), gfn);
709 * Return the pointer to the large page information for a given gfn,
710 * handling slots that are not large page aligned.
712 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
713 const struct kvm_memory_slot *slot, int level)
717 idx = gfn_to_index(gfn, slot->base_gfn, level);
718 return &slot->arch.lpage_info[level - 2][idx];
721 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
722 gfn_t gfn, int count)
724 struct kvm_lpage_info *linfo;
727 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
728 linfo = lpage_info_slot(gfn, slot, i);
729 linfo->disallow_lpage += count;
730 WARN_ON(linfo->disallow_lpage < 0);
734 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
736 update_gfn_disallow_lpage_count(slot, gfn, 1);
739 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
741 update_gfn_disallow_lpage_count(slot, gfn, -1);
744 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
746 struct kvm_memslots *slots;
747 struct kvm_memory_slot *slot;
750 kvm->arch.indirect_shadow_pages++;
752 slots = kvm_memslots_for_spte_role(kvm, sp->role);
753 slot = __gfn_to_memslot(slots, gfn);
755 /* the non-leaf shadow pages are keeping readonly. */
756 if (sp->role.level > PG_LEVEL_4K)
757 return kvm_slot_page_track_add_page(kvm, slot, gfn,
758 KVM_PAGE_TRACK_WRITE);
760 kvm_mmu_gfn_disallow_lpage(slot, gfn);
763 void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
765 if (sp->lpage_disallowed)
768 ++kvm->stat.nx_lpage_splits;
769 list_add_tail(&sp->lpage_disallowed_link,
770 &kvm->arch.lpage_disallowed_mmu_pages);
771 sp->lpage_disallowed = true;
774 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
776 struct kvm_memslots *slots;
777 struct kvm_memory_slot *slot;
780 kvm->arch.indirect_shadow_pages--;
782 slots = kvm_memslots_for_spte_role(kvm, sp->role);
783 slot = __gfn_to_memslot(slots, gfn);
784 if (sp->role.level > PG_LEVEL_4K)
785 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
786 KVM_PAGE_TRACK_WRITE);
788 kvm_mmu_gfn_allow_lpage(slot, gfn);
791 void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
793 --kvm->stat.nx_lpage_splits;
794 sp->lpage_disallowed = false;
795 list_del(&sp->lpage_disallowed_link);
798 static struct kvm_memory_slot *
799 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
802 struct kvm_memory_slot *slot;
804 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
805 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
807 if (no_dirty_log && kvm_slot_dirty_track_enabled(slot))
814 * About rmap_head encoding:
816 * If the bit zero of rmap_head->val is clear, then it points to the only spte
817 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
818 * pte_list_desc containing more mappings.
822 * Returns the number of pointers in the rmap chain, not counting the new one.
824 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
825 struct kvm_rmap_head *rmap_head)
827 struct pte_list_desc *desc;
830 if (!rmap_head->val) {
831 rmap_printk("%p %llx 0->1\n", spte, *spte);
832 rmap_head->val = (unsigned long)spte;
833 } else if (!(rmap_head->val & 1)) {
834 rmap_printk("%p %llx 1->many\n", spte, *spte);
835 desc = mmu_alloc_pte_list_desc(vcpu);
836 desc->sptes[0] = (u64 *)rmap_head->val;
837 desc->sptes[1] = spte;
838 rmap_head->val = (unsigned long)desc | 1;
841 rmap_printk("%p %llx many->many\n", spte, *spte);
842 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
843 while (desc->sptes[PTE_LIST_EXT-1]) {
844 count += PTE_LIST_EXT;
847 desc->more = mmu_alloc_pte_list_desc(vcpu);
853 for (i = 0; desc->sptes[i]; ++i)
855 desc->sptes[i] = spte;
861 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
862 struct pte_list_desc *desc, int i,
863 struct pte_list_desc *prev_desc)
867 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
869 desc->sptes[i] = desc->sptes[j];
870 desc->sptes[j] = NULL;
873 if (!prev_desc && !desc->more)
877 prev_desc->more = desc->more;
879 rmap_head->val = (unsigned long)desc->more | 1;
880 mmu_free_pte_list_desc(desc);
883 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
885 struct pte_list_desc *desc;
886 struct pte_list_desc *prev_desc;
889 if (!rmap_head->val) {
890 pr_err("%s: %p 0->BUG\n", __func__, spte);
892 } else if (!(rmap_head->val & 1)) {
893 rmap_printk("%p 1->0\n", spte);
894 if ((u64 *)rmap_head->val != spte) {
895 pr_err("%s: %p 1->BUG\n", __func__, spte);
900 rmap_printk("%p many->many\n", spte);
901 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
904 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
905 if (desc->sptes[i] == spte) {
906 pte_list_desc_remove_entry(rmap_head,
914 pr_err("%s: %p many->many\n", __func__, spte);
919 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
921 mmu_spte_clear_track_bits(sptep);
922 __pte_list_remove(sptep, rmap_head);
925 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
926 struct kvm_memory_slot *slot)
930 idx = gfn_to_index(gfn, slot->base_gfn, level);
931 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
934 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
935 struct kvm_mmu_page *sp)
937 struct kvm_memslots *slots;
938 struct kvm_memory_slot *slot;
940 slots = kvm_memslots_for_spte_role(kvm, sp->role);
941 slot = __gfn_to_memslot(slots, gfn);
942 return __gfn_to_rmap(gfn, sp->role.level, slot);
945 static bool rmap_can_add(struct kvm_vcpu *vcpu)
947 struct kvm_mmu_memory_cache *mc;
949 mc = &vcpu->arch.mmu_pte_list_desc_cache;
950 return kvm_mmu_memory_cache_nr_free_objects(mc);
953 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
955 struct kvm_mmu_page *sp;
956 struct kvm_rmap_head *rmap_head;
958 sp = sptep_to_sp(spte);
959 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
960 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
961 return pte_list_add(vcpu, spte, rmap_head);
964 static void rmap_remove(struct kvm *kvm, u64 *spte)
966 struct kvm_mmu_page *sp;
968 struct kvm_rmap_head *rmap_head;
970 sp = sptep_to_sp(spte);
971 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
972 rmap_head = gfn_to_rmap(kvm, gfn, sp);
973 __pte_list_remove(spte, rmap_head);
977 * Used by the following functions to iterate through the sptes linked by a
978 * rmap. All fields are private and not assumed to be used outside.
980 struct rmap_iterator {
982 struct pte_list_desc *desc; /* holds the sptep if not NULL */
983 int pos; /* index of the sptep */
987 * Iteration must be started by this function. This should also be used after
988 * removing/dropping sptes from the rmap link because in such cases the
989 * information in the iterator may not be valid.
991 * Returns sptep if found, NULL otherwise.
993 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
994 struct rmap_iterator *iter)
1001 if (!(rmap_head->val & 1)) {
1003 sptep = (u64 *)rmap_head->val;
1007 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1009 sptep = iter->desc->sptes[iter->pos];
1011 BUG_ON(!is_shadow_present_pte(*sptep));
1016 * Must be used with a valid iterator: e.g. after rmap_get_first().
1018 * Returns sptep if found, NULL otherwise.
1020 static u64 *rmap_get_next(struct rmap_iterator *iter)
1025 if (iter->pos < PTE_LIST_EXT - 1) {
1027 sptep = iter->desc->sptes[iter->pos];
1032 iter->desc = iter->desc->more;
1036 /* desc->sptes[0] cannot be NULL */
1037 sptep = iter->desc->sptes[iter->pos];
1044 BUG_ON(!is_shadow_present_pte(*sptep));
1048 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1049 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1050 _spte_; _spte_ = rmap_get_next(_iter_))
1052 static void drop_spte(struct kvm *kvm, u64 *sptep)
1054 if (mmu_spte_clear_track_bits(sptep))
1055 rmap_remove(kvm, sptep);
1059 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1061 if (is_large_pte(*sptep)) {
1062 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1063 drop_spte(kvm, sptep);
1071 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1073 if (__drop_large_spte(vcpu->kvm, sptep)) {
1074 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1076 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1077 KVM_PAGES_PER_HPAGE(sp->role.level));
1082 * Write-protect on the specified @sptep, @pt_protect indicates whether
1083 * spte write-protection is caused by protecting shadow page table.
1085 * Note: write protection is difference between dirty logging and spte
1087 * - for dirty logging, the spte can be set to writable at anytime if
1088 * its dirty bitmap is properly set.
1089 * - for spte protection, the spte can be writable only after unsync-ing
1092 * Return true if tlb need be flushed.
1094 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1098 if (!is_writable_pte(spte) &&
1099 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1102 rmap_printk("spte %p %llx\n", sptep, *sptep);
1105 spte &= ~shadow_mmu_writable_mask;
1106 spte = spte & ~PT_WRITABLE_MASK;
1108 return mmu_spte_update(sptep, spte);
1111 static bool __rmap_write_protect(struct kvm *kvm,
1112 struct kvm_rmap_head *rmap_head,
1116 struct rmap_iterator iter;
1119 for_each_rmap_spte(rmap_head, &iter, sptep)
1120 flush |= spte_write_protect(sptep, pt_protect);
1125 static bool spte_clear_dirty(u64 *sptep)
1129 rmap_printk("spte %p %llx\n", sptep, *sptep);
1131 MMU_WARN_ON(!spte_ad_enabled(spte));
1132 spte &= ~shadow_dirty_mask;
1133 return mmu_spte_update(sptep, spte);
1136 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1138 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1139 (unsigned long *)sptep);
1140 if (was_writable && !spte_ad_enabled(*sptep))
1141 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1143 return was_writable;
1147 * Gets the GFN ready for another round of dirty logging by clearing the
1148 * - D bit on ad-enabled SPTEs, and
1149 * - W bit on ad-disabled SPTEs.
1150 * Returns true iff any D or W bits were cleared.
1152 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1153 struct kvm_memory_slot *slot)
1156 struct rmap_iterator iter;
1159 for_each_rmap_spte(rmap_head, &iter, sptep)
1160 if (spte_ad_need_write_protect(*sptep))
1161 flush |= spte_wrprot_for_clear_dirty(sptep);
1163 flush |= spte_clear_dirty(sptep);
1169 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1170 * @kvm: kvm instance
1171 * @slot: slot to protect
1172 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1173 * @mask: indicates which pages we should protect
1175 * Used when we do not need to care about huge page mappings.
1177 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1178 struct kvm_memory_slot *slot,
1179 gfn_t gfn_offset, unsigned long mask)
1181 struct kvm_rmap_head *rmap_head;
1183 if (is_tdp_mmu_enabled(kvm))
1184 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1185 slot->base_gfn + gfn_offset, mask, true);
1187 if (!kvm_memslots_have_rmaps(kvm))
1191 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1193 __rmap_write_protect(kvm, rmap_head, false);
1195 /* clear the first set bit */
1201 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1202 * protect the page if the D-bit isn't supported.
1203 * @kvm: kvm instance
1204 * @slot: slot to clear D-bit
1205 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1206 * @mask: indicates which pages we should clear D-bit
1208 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1210 static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1211 struct kvm_memory_slot *slot,
1212 gfn_t gfn_offset, unsigned long mask)
1214 struct kvm_rmap_head *rmap_head;
1216 if (is_tdp_mmu_enabled(kvm))
1217 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1218 slot->base_gfn + gfn_offset, mask, false);
1220 if (!kvm_memslots_have_rmaps(kvm))
1224 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1226 __rmap_clear_dirty(kvm, rmap_head, slot);
1228 /* clear the first set bit */
1234 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1237 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1238 * enable dirty logging for them.
1240 * We need to care about huge page mappings: e.g. during dirty logging we may
1241 * have such mappings.
1243 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1244 struct kvm_memory_slot *slot,
1245 gfn_t gfn_offset, unsigned long mask)
1248 * Huge pages are NOT write protected when we start dirty logging in
1249 * initially-all-set mode; must write protect them here so that they
1250 * are split to 4K on the first write.
1252 * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn
1253 * of memslot has no such restriction, so the range can cross two large
1256 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) {
1257 gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask);
1258 gfn_t end = slot->base_gfn + gfn_offset + __fls(mask);
1260 kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M);
1262 /* Cross two large pages? */
1263 if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) !=
1264 ALIGN(end << PAGE_SHIFT, PMD_SIZE))
1265 kvm_mmu_slot_gfn_write_protect(kvm, slot, end,
1269 /* Now handle 4K PTEs. */
1270 if (kvm_x86_ops.cpu_dirty_log_size)
1271 kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask);
1273 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1276 int kvm_cpu_dirty_log_size(void)
1278 return kvm_x86_ops.cpu_dirty_log_size;
1281 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1282 struct kvm_memory_slot *slot, u64 gfn,
1285 struct kvm_rmap_head *rmap_head;
1287 bool write_protected = false;
1289 if (kvm_memslots_have_rmaps(kvm)) {
1290 for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1291 rmap_head = __gfn_to_rmap(gfn, i, slot);
1292 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1296 if (is_tdp_mmu_enabled(kvm))
1298 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level);
1300 return write_protected;
1303 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1305 struct kvm_memory_slot *slot;
1307 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1308 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K);
1311 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1312 struct kvm_memory_slot *slot)
1315 struct rmap_iterator iter;
1318 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1319 rmap_printk("spte %p %llx.\n", sptep, *sptep);
1321 pte_list_remove(rmap_head, sptep);
1328 static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1329 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1332 return kvm_zap_rmapp(kvm, rmap_head, slot);
1335 static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1336 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1340 struct rmap_iterator iter;
1345 WARN_ON(pte_huge(pte));
1346 new_pfn = pte_pfn(pte);
1349 for_each_rmap_spte(rmap_head, &iter, sptep) {
1350 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1351 sptep, *sptep, gfn, level);
1355 if (pte_write(pte)) {
1356 pte_list_remove(rmap_head, sptep);
1359 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1362 mmu_spte_clear_track_bits(sptep);
1363 mmu_spte_set(sptep, new_spte);
1367 if (need_flush && kvm_available_flush_tlb_with_range()) {
1368 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1375 struct slot_rmap_walk_iterator {
1377 struct kvm_memory_slot *slot;
1383 /* output fields. */
1385 struct kvm_rmap_head *rmap;
1388 /* private field. */
1389 struct kvm_rmap_head *end_rmap;
1393 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1395 iterator->level = level;
1396 iterator->gfn = iterator->start_gfn;
1397 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1398 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1403 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1404 struct kvm_memory_slot *slot, int start_level,
1405 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1407 iterator->slot = slot;
1408 iterator->start_level = start_level;
1409 iterator->end_level = end_level;
1410 iterator->start_gfn = start_gfn;
1411 iterator->end_gfn = end_gfn;
1413 rmap_walk_init_level(iterator, iterator->start_level);
1416 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1418 return !!iterator->rmap;
1421 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1423 if (++iterator->rmap <= iterator->end_rmap) {
1424 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1428 if (++iterator->level > iterator->end_level) {
1429 iterator->rmap = NULL;
1433 rmap_walk_init_level(iterator, iterator->level);
1436 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1437 _start_gfn, _end_gfn, _iter_) \
1438 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1439 _end_level_, _start_gfn, _end_gfn); \
1440 slot_rmap_walk_okay(_iter_); \
1441 slot_rmap_walk_next(_iter_))
1443 typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1444 struct kvm_memory_slot *slot, gfn_t gfn,
1445 int level, pte_t pte);
1447 static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm,
1448 struct kvm_gfn_range *range,
1449 rmap_handler_t handler)
1451 struct slot_rmap_walk_iterator iterator;
1454 for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL,
1455 range->start, range->end - 1, &iterator)
1456 ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn,
1457 iterator.level, range->pte);
1462 bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range)
1466 if (kvm_memslots_have_rmaps(kvm))
1467 flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp);
1469 if (is_tdp_mmu_enabled(kvm))
1470 flush |= kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush);
1475 bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1479 if (kvm_memslots_have_rmaps(kvm))
1480 flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp);
1482 if (is_tdp_mmu_enabled(kvm))
1483 flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range);
1488 static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1489 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1493 struct rmap_iterator iter;
1496 for_each_rmap_spte(rmap_head, &iter, sptep)
1497 young |= mmu_spte_age(sptep);
1502 static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1503 struct kvm_memory_slot *slot, gfn_t gfn,
1504 int level, pte_t unused)
1507 struct rmap_iterator iter;
1509 for_each_rmap_spte(rmap_head, &iter, sptep)
1510 if (is_accessed_spte(*sptep))
1515 #define RMAP_RECYCLE_THRESHOLD 1000
1517 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1519 struct kvm_rmap_head *rmap_head;
1520 struct kvm_mmu_page *sp;
1522 sp = sptep_to_sp(spte);
1524 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1526 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0));
1527 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1528 KVM_PAGES_PER_HPAGE(sp->role.level));
1531 bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1535 if (kvm_memslots_have_rmaps(kvm))
1536 young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp);
1538 if (is_tdp_mmu_enabled(kvm))
1539 young |= kvm_tdp_mmu_age_gfn_range(kvm, range);
1544 bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1548 if (kvm_memslots_have_rmaps(kvm))
1549 young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp);
1551 if (is_tdp_mmu_enabled(kvm))
1552 young |= kvm_tdp_mmu_test_age_gfn(kvm, range);
1558 static int is_empty_shadow_page(u64 *spt)
1563 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1564 if (is_shadow_present_pte(*pos)) {
1565 printk(KERN_ERR "%s: %p %llx\n", __func__,
1574 * This value is the sum of all of the kvm instances's
1575 * kvm->arch.n_used_mmu_pages values. We need a global,
1576 * aggregate version in order to make the slab shrinker
1579 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
1581 kvm->arch.n_used_mmu_pages += nr;
1582 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1585 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1587 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1588 hlist_del(&sp->hash_link);
1589 list_del(&sp->link);
1590 free_page((unsigned long)sp->spt);
1591 if (!sp->role.direct)
1592 free_page((unsigned long)sp->gfns);
1593 kmem_cache_free(mmu_page_header_cache, sp);
1596 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1598 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1601 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1602 struct kvm_mmu_page *sp, u64 *parent_pte)
1607 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1610 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1613 __pte_list_remove(parent_pte, &sp->parent_ptes);
1616 static void drop_parent_pte(struct kvm_mmu_page *sp,
1619 mmu_page_remove_parent_pte(sp, parent_pte);
1620 mmu_spte_clear_no_track(parent_pte);
1623 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1625 struct kvm_mmu_page *sp;
1627 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1628 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1630 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1631 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1634 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1635 * depends on valid pages being added to the head of the list. See
1636 * comments in kvm_zap_obsolete_pages().
1638 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1639 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1640 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1644 static void mark_unsync(u64 *spte);
1645 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1648 struct rmap_iterator iter;
1650 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1655 static void mark_unsync(u64 *spte)
1657 struct kvm_mmu_page *sp;
1660 sp = sptep_to_sp(spte);
1661 index = spte - sp->spt;
1662 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1664 if (sp->unsync_children++)
1666 kvm_mmu_mark_parents_unsync(sp);
1669 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1670 struct kvm_mmu_page *sp)
1675 #define KVM_PAGE_ARRAY_NR 16
1677 struct kvm_mmu_pages {
1678 struct mmu_page_and_offset {
1679 struct kvm_mmu_page *sp;
1681 } page[KVM_PAGE_ARRAY_NR];
1685 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1691 for (i=0; i < pvec->nr; i++)
1692 if (pvec->page[i].sp == sp)
1695 pvec->page[pvec->nr].sp = sp;
1696 pvec->page[pvec->nr].idx = idx;
1698 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1701 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1703 --sp->unsync_children;
1704 WARN_ON((int)sp->unsync_children < 0);
1705 __clear_bit(idx, sp->unsync_child_bitmap);
1708 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1709 struct kvm_mmu_pages *pvec)
1711 int i, ret, nr_unsync_leaf = 0;
1713 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1714 struct kvm_mmu_page *child;
1715 u64 ent = sp->spt[i];
1717 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1718 clear_unsync_child_bit(sp, i);
1722 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1724 if (child->unsync_children) {
1725 if (mmu_pages_add(pvec, child, i))
1728 ret = __mmu_unsync_walk(child, pvec);
1730 clear_unsync_child_bit(sp, i);
1732 } else if (ret > 0) {
1733 nr_unsync_leaf += ret;
1736 } else if (child->unsync) {
1738 if (mmu_pages_add(pvec, child, i))
1741 clear_unsync_child_bit(sp, i);
1744 return nr_unsync_leaf;
1747 #define INVALID_INDEX (-1)
1749 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1750 struct kvm_mmu_pages *pvec)
1753 if (!sp->unsync_children)
1756 mmu_pages_add(pvec, sp, INVALID_INDEX);
1757 return __mmu_unsync_walk(sp, pvec);
1760 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1762 WARN_ON(!sp->unsync);
1763 trace_kvm_mmu_sync_page(sp);
1765 --kvm->stat.mmu_unsync;
1768 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1769 struct list_head *invalid_list);
1770 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1771 struct list_head *invalid_list);
1773 #define for_each_valid_sp(_kvm, _sp, _list) \
1774 hlist_for_each_entry(_sp, _list, hash_link) \
1775 if (is_obsolete_sp((_kvm), (_sp))) { \
1778 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1779 for_each_valid_sp(_kvm, _sp, \
1780 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1781 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1783 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1784 struct list_head *invalid_list)
1786 if (vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
1787 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1794 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1795 struct list_head *invalid_list,
1798 if (!remote_flush && list_empty(invalid_list))
1801 if (!list_empty(invalid_list))
1802 kvm_mmu_commit_zap_page(kvm, invalid_list);
1804 kvm_flush_remote_tlbs(kvm);
1808 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1809 struct list_head *invalid_list,
1810 bool remote_flush, bool local_flush)
1812 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
1816 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1819 #ifdef CONFIG_KVM_MMU_AUDIT
1820 #include "mmu_audit.c"
1822 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1823 static void mmu_audit_disable(void) { }
1826 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1828 return sp->role.invalid ||
1829 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1832 struct mmu_page_path {
1833 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1834 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1837 #define for_each_sp(pvec, sp, parents, i) \
1838 for (i = mmu_pages_first(&pvec, &parents); \
1839 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1840 i = mmu_pages_next(&pvec, &parents, i))
1842 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1843 struct mmu_page_path *parents,
1848 for (n = i+1; n < pvec->nr; n++) {
1849 struct kvm_mmu_page *sp = pvec->page[n].sp;
1850 unsigned idx = pvec->page[n].idx;
1851 int level = sp->role.level;
1853 parents->idx[level-1] = idx;
1854 if (level == PG_LEVEL_4K)
1857 parents->parent[level-2] = sp;
1863 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1864 struct mmu_page_path *parents)
1866 struct kvm_mmu_page *sp;
1872 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1874 sp = pvec->page[0].sp;
1875 level = sp->role.level;
1876 WARN_ON(level == PG_LEVEL_4K);
1878 parents->parent[level-2] = sp;
1880 /* Also set up a sentinel. Further entries in pvec are all
1881 * children of sp, so this element is never overwritten.
1883 parents->parent[level-1] = NULL;
1884 return mmu_pages_next(pvec, parents, 0);
1887 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1889 struct kvm_mmu_page *sp;
1890 unsigned int level = 0;
1893 unsigned int idx = parents->idx[level];
1894 sp = parents->parent[level];
1898 WARN_ON(idx == INVALID_INDEX);
1899 clear_unsync_child_bit(sp, idx);
1901 } while (!sp->unsync_children);
1904 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1905 struct kvm_mmu_page *parent)
1908 struct kvm_mmu_page *sp;
1909 struct mmu_page_path parents;
1910 struct kvm_mmu_pages pages;
1911 LIST_HEAD(invalid_list);
1914 while (mmu_unsync_walk(parent, &pages)) {
1915 bool protected = false;
1917 for_each_sp(pages, sp, parents, i)
1918 protected |= rmap_write_protect(vcpu, sp->gfn);
1921 kvm_flush_remote_tlbs(vcpu->kvm);
1925 for_each_sp(pages, sp, parents, i) {
1926 kvm_unlink_unsync_page(vcpu->kvm, sp);
1927 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
1928 mmu_pages_clear_parents(&parents);
1930 if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) {
1931 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1932 cond_resched_rwlock_write(&vcpu->kvm->mmu_lock);
1937 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1940 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1942 atomic_set(&sp->write_flooding_count, 0);
1945 static void clear_sp_write_flooding_count(u64 *spte)
1947 __clear_sp_write_flooding_count(sptep_to_sp(spte));
1950 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1955 unsigned int access)
1957 bool direct_mmu = vcpu->arch.mmu->direct_map;
1958 union kvm_mmu_page_role role;
1959 struct hlist_head *sp_list;
1961 struct kvm_mmu_page *sp;
1963 LIST_HEAD(invalid_list);
1965 role = vcpu->arch.mmu->mmu_role.base;
1967 role.direct = direct;
1969 role.gpte_is_8_bytes = true;
1970 role.access = access;
1971 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
1972 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1973 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1974 role.quadrant = quadrant;
1977 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
1978 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
1979 if (sp->gfn != gfn) {
1984 if (sp->role.word != role.word) {
1986 * If the guest is creating an upper-level page, zap
1987 * unsync pages for the same gfn. While it's possible
1988 * the guest is using recursive page tables, in all
1989 * likelihood the guest has stopped using the unsync
1990 * page and is installing a completely unrelated page.
1991 * Unsync pages must not be left as is, because the new
1992 * upper-level page will be write-protected.
1994 if (level > PG_LEVEL_4K && sp->unsync)
1995 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2001 goto trace_get_page;
2005 * The page is good, but is stale. kvm_sync_page does
2006 * get the latest guest state, but (unlike mmu_unsync_children)
2007 * it doesn't write-protect the page or mark it synchronized!
2008 * This way the validity of the mapping is ensured, but the
2009 * overhead of write protection is not incurred until the
2010 * guest invalidates the TLB mapping. This allows multiple
2011 * SPs for a single gfn to be unsync.
2013 * If the sync fails, the page is zapped. If so, break
2014 * in order to rebuild it.
2016 if (!kvm_sync_page(vcpu, sp, &invalid_list))
2019 WARN_ON(!list_empty(&invalid_list));
2020 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2023 if (sp->unsync_children)
2024 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2026 __clear_sp_write_flooding_count(sp);
2029 trace_kvm_mmu_get_page(sp, false);
2033 ++vcpu->kvm->stat.mmu_cache_miss;
2035 sp = kvm_mmu_alloc_page(vcpu, direct);
2039 hlist_add_head(&sp->hash_link, sp_list);
2041 account_shadowed(vcpu->kvm, sp);
2042 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2043 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2045 trace_kvm_mmu_get_page(sp, true);
2047 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2049 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2050 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2054 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2055 struct kvm_vcpu *vcpu, hpa_t root,
2058 iterator->addr = addr;
2059 iterator->shadow_addr = root;
2060 iterator->level = vcpu->arch.mmu->shadow_root_level;
2062 if (iterator->level == PT64_ROOT_4LEVEL &&
2063 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2064 !vcpu->arch.mmu->direct_map)
2067 if (iterator->level == PT32E_ROOT_LEVEL) {
2069 * prev_root is currently only used for 64-bit hosts. So only
2070 * the active root_hpa is valid here.
2072 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2074 iterator->shadow_addr
2075 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2076 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2078 if (!iterator->shadow_addr)
2079 iterator->level = 0;
2083 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2084 struct kvm_vcpu *vcpu, u64 addr)
2086 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2090 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2092 if (iterator->level < PG_LEVEL_4K)
2095 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2096 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2100 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2103 if (is_last_spte(spte, iterator->level)) {
2104 iterator->level = 0;
2108 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2112 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2114 __shadow_walk_next(iterator, *iterator->sptep);
2117 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2118 struct kvm_mmu_page *sp)
2122 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2124 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2126 mmu_spte_set(sptep, spte);
2128 mmu_page_add_parent_pte(vcpu, sp, sptep);
2130 if (sp->unsync_children || sp->unsync)
2134 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2135 unsigned direct_access)
2137 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2138 struct kvm_mmu_page *child;
2141 * For the direct sp, if the guest pte's dirty bit
2142 * changed form clean to dirty, it will corrupt the
2143 * sp's access: allow writable in the read-only sp,
2144 * so we should update the spte at this point to get
2145 * a new sp with the correct access.
2147 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2148 if (child->role.access == direct_access)
2151 drop_parent_pte(child, sptep);
2152 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2156 /* Returns the number of zapped non-leaf child shadow pages. */
2157 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2158 u64 *spte, struct list_head *invalid_list)
2161 struct kvm_mmu_page *child;
2164 if (is_shadow_present_pte(pte)) {
2165 if (is_last_spte(pte, sp->role.level)) {
2166 drop_spte(kvm, spte);
2167 if (is_large_pte(pte))
2170 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2171 drop_parent_pte(child, spte);
2174 * Recursively zap nested TDP SPs, parentless SPs are
2175 * unlikely to be used again in the near future. This
2176 * avoids retaining a large number of stale nested SPs.
2178 if (tdp_enabled && invalid_list &&
2179 child->role.guest_mode && !child->parent_ptes.val)
2180 return kvm_mmu_prepare_zap_page(kvm, child,
2183 } else if (is_mmio_spte(pte)) {
2184 mmu_spte_clear_no_track(spte);
2189 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2190 struct kvm_mmu_page *sp,
2191 struct list_head *invalid_list)
2196 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2197 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2202 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2205 struct rmap_iterator iter;
2207 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2208 drop_parent_pte(sp, sptep);
2211 static int mmu_zap_unsync_children(struct kvm *kvm,
2212 struct kvm_mmu_page *parent,
2213 struct list_head *invalid_list)
2216 struct mmu_page_path parents;
2217 struct kvm_mmu_pages pages;
2219 if (parent->role.level == PG_LEVEL_4K)
2222 while (mmu_unsync_walk(parent, &pages)) {
2223 struct kvm_mmu_page *sp;
2225 for_each_sp(pages, sp, parents, i) {
2226 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2227 mmu_pages_clear_parents(&parents);
2235 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2236 struct kvm_mmu_page *sp,
2237 struct list_head *invalid_list,
2242 trace_kvm_mmu_prepare_zap_page(sp);
2243 ++kvm->stat.mmu_shadow_zapped;
2244 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2245 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2246 kvm_mmu_unlink_parents(kvm, sp);
2248 /* Zapping children means active_mmu_pages has become unstable. */
2249 list_unstable = *nr_zapped;
2251 if (!sp->role.invalid && !sp->role.direct)
2252 unaccount_shadowed(kvm, sp);
2255 kvm_unlink_unsync_page(kvm, sp);
2256 if (!sp->root_count) {
2261 * Already invalid pages (previously active roots) are not on
2262 * the active page list. See list_del() in the "else" case of
2265 if (sp->role.invalid)
2266 list_add(&sp->link, invalid_list);
2268 list_move(&sp->link, invalid_list);
2269 kvm_mod_used_mmu_pages(kvm, -1);
2272 * Remove the active root from the active page list, the root
2273 * will be explicitly freed when the root_count hits zero.
2275 list_del(&sp->link);
2278 * Obsolete pages cannot be used on any vCPUs, see the comment
2279 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2280 * treats invalid shadow pages as being obsolete.
2282 if (!is_obsolete_sp(kvm, sp))
2283 kvm_reload_remote_mmus(kvm);
2286 if (sp->lpage_disallowed)
2287 unaccount_huge_nx_page(kvm, sp);
2289 sp->role.invalid = 1;
2290 return list_unstable;
2293 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2294 struct list_head *invalid_list)
2298 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2302 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2303 struct list_head *invalid_list)
2305 struct kvm_mmu_page *sp, *nsp;
2307 if (list_empty(invalid_list))
2311 * We need to make sure everyone sees our modifications to
2312 * the page tables and see changes to vcpu->mode here. The barrier
2313 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2314 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2316 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2317 * guest mode and/or lockless shadow page table walks.
2319 kvm_flush_remote_tlbs(kvm);
2321 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2322 WARN_ON(!sp->role.invalid || sp->root_count);
2323 kvm_mmu_free_page(sp);
2327 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2328 unsigned long nr_to_zap)
2330 unsigned long total_zapped = 0;
2331 struct kvm_mmu_page *sp, *tmp;
2332 LIST_HEAD(invalid_list);
2336 if (list_empty(&kvm->arch.active_mmu_pages))
2340 list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2342 * Don't zap active root pages, the page itself can't be freed
2343 * and zapping it will just force vCPUs to realloc and reload.
2348 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2350 total_zapped += nr_zapped;
2351 if (total_zapped >= nr_to_zap)
2358 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2360 kvm->stat.mmu_recycled += total_zapped;
2361 return total_zapped;
2364 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2366 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2367 return kvm->arch.n_max_mmu_pages -
2368 kvm->arch.n_used_mmu_pages;
2373 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2375 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2377 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2380 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2383 * Note, this check is intentionally soft, it only guarantees that one
2384 * page is available, while the caller may end up allocating as many as
2385 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2386 * exceeding the (arbitrary by default) limit will not harm the host,
2387 * being too agressive may unnecessarily kill the guest, and getting an
2388 * exact count is far more trouble than it's worth, especially in the
2391 if (!kvm_mmu_available_pages(vcpu->kvm))
2397 * Changing the number of mmu pages allocated to the vm
2398 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2400 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2402 write_lock(&kvm->mmu_lock);
2404 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2405 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2408 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2411 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2413 write_unlock(&kvm->mmu_lock);
2416 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2418 struct kvm_mmu_page *sp;
2419 LIST_HEAD(invalid_list);
2422 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2424 write_lock(&kvm->mmu_lock);
2425 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2426 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2429 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2431 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2432 write_unlock(&kvm->mmu_lock);
2437 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2442 if (vcpu->arch.mmu->direct_map)
2445 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2447 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2452 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2454 trace_kvm_mmu_unsync_page(sp);
2455 ++vcpu->kvm->stat.mmu_unsync;
2458 kvm_mmu_mark_parents_unsync(sp);
2462 * Attempt to unsync any shadow pages that can be reached by the specified gfn,
2463 * KVM is creating a writable mapping for said gfn. Returns 0 if all pages
2464 * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must
2465 * be write-protected.
2467 int mmu_try_to_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, bool can_unsync)
2469 struct kvm_mmu_page *sp;
2472 * Force write-protection if the page is being tracked. Note, the page
2473 * track machinery is used to write-protect upper-level shadow pages,
2474 * i.e. this guards the role.level == 4K assertion below!
2476 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2480 * The page is not write-tracked, mark existing shadow pages unsync
2481 * unless KVM is synchronizing an unsync SP (can_unsync = false). In
2482 * that case, KVM must complete emulation of the guest TLB flush before
2483 * allowing shadow pages to become unsync (writable by the guest).
2485 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2492 WARN_ON(sp->role.level != PG_LEVEL_4K);
2493 kvm_unsync_page(vcpu, sp);
2497 * We need to ensure that the marking of unsync pages is visible
2498 * before the SPTE is updated to allow writes because
2499 * kvm_mmu_sync_roots() checks the unsync flags without holding
2500 * the MMU lock and so can race with this. If the SPTE was updated
2501 * before the page had been marked as unsync-ed, something like the
2502 * following could happen:
2505 * ---------------------------------------------------------------------
2506 * 1.2 Host updates SPTE
2508 * 2.1 Guest writes a GPTE for GVA X.
2509 * (GPTE being in the guest page table shadowed
2510 * by the SP from CPU 1.)
2511 * This reads SPTE during the page table walk.
2512 * Since SPTE.W is read as 1, there is no
2515 * 2.2 Guest issues TLB flush.
2516 * That causes a VM Exit.
2518 * 2.3 Walking of unsync pages sees sp->unsync is
2519 * false and skips the page.
2521 * 2.4 Guest accesses GVA X.
2522 * Since the mapping in the SP was not updated,
2523 * so the old mapping for GVA X incorrectly
2527 * (sp->unsync = true)
2529 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2530 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2531 * pairs with this write barrier.
2538 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2539 unsigned int pte_access, int level,
2540 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2541 bool can_unsync, bool host_writable)
2544 struct kvm_mmu_page *sp;
2547 sp = sptep_to_sp(sptep);
2549 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2550 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2552 if (spte & PT_WRITABLE_MASK)
2553 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2556 ret |= SET_SPTE_SPURIOUS;
2557 else if (mmu_spte_update(sptep, spte))
2558 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2562 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2563 unsigned int pte_access, bool write_fault, int level,
2564 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2567 int was_rmapped = 0;
2570 int ret = RET_PF_FIXED;
2573 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2574 *sptep, write_fault, gfn);
2576 if (unlikely(is_noslot_pfn(pfn))) {
2577 mark_mmio_spte(vcpu, sptep, gfn, pte_access);
2578 return RET_PF_EMULATE;
2581 if (is_shadow_present_pte(*sptep)) {
2583 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2584 * the parent of the now unreachable PTE.
2586 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2587 struct kvm_mmu_page *child;
2590 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2591 drop_parent_pte(child, sptep);
2593 } else if (pfn != spte_to_pfn(*sptep)) {
2594 pgprintk("hfn old %llx new %llx\n",
2595 spte_to_pfn(*sptep), pfn);
2596 drop_spte(vcpu->kvm, sptep);
2602 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2603 speculative, true, host_writable);
2604 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2606 ret = RET_PF_EMULATE;
2607 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2610 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2611 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2612 KVM_PAGES_PER_HPAGE(level));
2615 * The fault is fully spurious if and only if the new SPTE and old SPTE
2616 * are identical, and emulation is not required.
2618 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2619 WARN_ON_ONCE(!was_rmapped);
2620 return RET_PF_SPURIOUS;
2623 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2624 trace_kvm_mmu_set_spte(level, gfn, sptep);
2625 if (!was_rmapped && is_large_pte(*sptep))
2626 ++vcpu->kvm->stat.lpages;
2628 if (is_shadow_present_pte(*sptep)) {
2630 rmap_count = rmap_add(vcpu, sptep, gfn);
2631 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2632 rmap_recycle(vcpu, sptep, gfn);
2639 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2642 struct kvm_memory_slot *slot;
2644 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2646 return KVM_PFN_ERR_FAULT;
2648 return gfn_to_pfn_memslot_atomic(slot, gfn);
2651 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2652 struct kvm_mmu_page *sp,
2653 u64 *start, u64 *end)
2655 struct page *pages[PTE_PREFETCH_NUM];
2656 struct kvm_memory_slot *slot;
2657 unsigned int access = sp->role.access;
2661 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2662 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2666 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2670 for (i = 0; i < ret; i++, gfn++, start++) {
2671 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2672 page_to_pfn(pages[i]), true, true);
2679 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2680 struct kvm_mmu_page *sp, u64 *sptep)
2682 u64 *spte, *start = NULL;
2685 WARN_ON(!sp->role.direct);
2687 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2690 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2691 if (is_shadow_present_pte(*spte) || spte == sptep) {
2694 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2702 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2704 struct kvm_mmu_page *sp;
2706 sp = sptep_to_sp(sptep);
2709 * Without accessed bits, there's no way to distinguish between
2710 * actually accessed translations and prefetched, so disable pte
2711 * prefetch if accessed bits aren't available.
2713 if (sp_ad_disabled(sp))
2716 if (sp->role.level > PG_LEVEL_4K)
2720 * If addresses are being invalidated, skip prefetching to avoid
2721 * accidentally prefetching those addresses.
2723 if (unlikely(vcpu->kvm->mmu_notifier_count))
2726 __direct_pte_prefetch(vcpu, sp, sptep);
2729 static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
2730 const struct kvm_memory_slot *slot)
2736 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2740 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2741 * is not solely for performance, it's also necessary to avoid the
2742 * "writable" check in __gfn_to_hva_many(), which will always fail on
2743 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2744 * page fault steps have already verified the guest isn't writing a
2745 * read-only memslot.
2747 hva = __gfn_to_hva_memslot(slot, gfn);
2749 pte = lookup_address_in_mm(kvm->mm, hva, &level);
2756 int kvm_mmu_max_mapping_level(struct kvm *kvm,
2757 const struct kvm_memory_slot *slot, gfn_t gfn,
2758 kvm_pfn_t pfn, int max_level)
2760 struct kvm_lpage_info *linfo;
2762 max_level = min(max_level, max_huge_page_level);
2763 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2764 linfo = lpage_info_slot(gfn, slot, max_level);
2765 if (!linfo->disallow_lpage)
2769 if (max_level == PG_LEVEL_4K)
2772 return host_pfn_mapping_level(kvm, gfn, pfn, slot);
2775 int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2776 int max_level, kvm_pfn_t *pfnp,
2777 bool huge_page_disallowed, int *req_level)
2779 struct kvm_memory_slot *slot;
2780 kvm_pfn_t pfn = *pfnp;
2784 *req_level = PG_LEVEL_4K;
2786 if (unlikely(max_level == PG_LEVEL_4K))
2789 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
2792 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2796 level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level);
2797 if (level == PG_LEVEL_4K)
2800 *req_level = level = min(level, max_level);
2803 * Enforce the iTLB multihit workaround after capturing the requested
2804 * level, which will be used to do precise, accurate accounting.
2806 if (huge_page_disallowed)
2810 * mmu_notifier_retry() was successful and mmu_lock is held, so
2811 * the pmd can't be split from under us.
2813 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2814 VM_BUG_ON((gfn & mask) != (pfn & mask));
2815 *pfnp = pfn & ~mask;
2820 void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2821 kvm_pfn_t *pfnp, int *goal_levelp)
2823 int level = *goal_levelp;
2825 if (cur_level == level && level > PG_LEVEL_4K &&
2826 is_shadow_present_pte(spte) &&
2827 !is_large_pte(spte)) {
2829 * A small SPTE exists for this pfn, but FNAME(fetch)
2830 * and __direct_map would like to create a large PTE
2831 * instead: just force them to go down another level,
2832 * patching back for them into pfn the next 9 bits of
2835 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2836 KVM_PAGES_PER_HPAGE(level - 1);
2837 *pfnp |= gfn & page_mask;
2842 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
2843 int map_writable, int max_level, kvm_pfn_t pfn,
2844 bool prefault, bool is_tdp)
2846 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2847 bool write = error_code & PFERR_WRITE_MASK;
2848 bool exec = error_code & PFERR_FETCH_MASK;
2849 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
2850 struct kvm_shadow_walk_iterator it;
2851 struct kvm_mmu_page *sp;
2852 int level, req_level, ret;
2853 gfn_t gfn = gpa >> PAGE_SHIFT;
2854 gfn_t base_gfn = gfn;
2856 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2857 huge_page_disallowed, &req_level);
2859 trace_kvm_mmu_spte_requested(gpa, level, pfn);
2860 for_each_shadow_entry(vcpu, gpa, it) {
2862 * We cannot overwrite existing page tables with an NX
2863 * large page, as the leaf could be executable.
2865 if (nx_huge_page_workaround_enabled)
2866 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
2869 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2870 if (it.level == level)
2873 drop_large_spte(vcpu, it.sptep);
2874 if (!is_shadow_present_pte(*it.sptep)) {
2875 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2876 it.level - 1, true, ACC_ALL);
2878 link_shadow_page(vcpu, it.sptep, sp);
2879 if (is_tdp && huge_page_disallowed &&
2880 req_level >= it.level)
2881 account_huge_nx_page(vcpu->kvm, sp);
2885 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2886 write, level, base_gfn, pfn, prefault,
2888 if (ret == RET_PF_SPURIOUS)
2891 direct_pte_prefetch(vcpu, it.sptep);
2892 ++vcpu->stat.pf_fixed;
2896 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2898 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2901 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2904 * Do not cache the mmio info caused by writing the readonly gfn
2905 * into the spte otherwise read access on readonly gfn also can
2906 * caused mmio page fault and treat it as mmio access.
2908 if (pfn == KVM_PFN_ERR_RO_FAULT)
2909 return RET_PF_EMULATE;
2911 if (pfn == KVM_PFN_ERR_HWPOISON) {
2912 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2913 return RET_PF_RETRY;
2919 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2920 kvm_pfn_t pfn, unsigned int access,
2923 /* The pfn is invalid, report the error! */
2924 if (unlikely(is_error_pfn(pfn))) {
2925 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2929 if (unlikely(is_noslot_pfn(pfn))) {
2930 vcpu_cache_mmio_info(vcpu, gva, gfn,
2931 access & shadow_mmio_access_mask);
2933 * If MMIO caching is disabled, emulate immediately without
2934 * touching the shadow page tables as attempting to install an
2935 * MMIO SPTE will just be an expensive nop.
2937 if (unlikely(!shadow_mmio_value)) {
2938 *ret_val = RET_PF_EMULATE;
2946 static bool page_fault_can_be_fast(u32 error_code)
2949 * Do not fix the mmio spte with invalid generation number which
2950 * need to be updated by slow page fault path.
2952 if (unlikely(error_code & PFERR_RSVD_MASK))
2955 /* See if the page fault is due to an NX violation */
2956 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
2957 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
2961 * #PF can be fast if:
2962 * 1. The shadow page table entry is not present, which could mean that
2963 * the fault is potentially caused by access tracking (if enabled).
2964 * 2. The shadow page table entry is present and the fault
2965 * is caused by write-protect, that means we just need change the W
2966 * bit of the spte which can be done out of mmu-lock.
2968 * However, if access tracking is disabled we know that a non-present
2969 * page must be a genuine page fault where we have to create a new SPTE.
2970 * So, if access tracking is disabled, we return true only for write
2971 * accesses to a present page.
2974 return shadow_acc_track_mask != 0 ||
2975 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
2976 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
2980 * Returns true if the SPTE was fixed successfully. Otherwise,
2981 * someone else modified the SPTE from its original value.
2984 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2985 u64 *sptep, u64 old_spte, u64 new_spte)
2989 WARN_ON(!sp->role.direct);
2992 * Theoretically we could also set dirty bit (and flush TLB) here in
2993 * order to eliminate unnecessary PML logging. See comments in
2994 * set_spte. But fast_page_fault is very unlikely to happen with PML
2995 * enabled, so we do not do this. This might result in the same GPA
2996 * to be logged in PML buffer again when the write really happens, and
2997 * eventually to be called by mark_page_dirty twice. But it's also no
2998 * harm. This also avoids the TLB flush needed after setting dirty bit
2999 * so non-PML cases won't be impacted.
3001 * Compare with set_spte where instead shadow_dirty_mask is set.
3003 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3006 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3008 * The gfn of direct spte is stable since it is
3009 * calculated by sp->gfn.
3011 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3012 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3018 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3020 if (fault_err_code & PFERR_FETCH_MASK)
3021 return is_executable_pte(spte);
3023 if (fault_err_code & PFERR_WRITE_MASK)
3024 return is_writable_pte(spte);
3026 /* Fault was on Read access */
3027 return spte & PT_PRESENT_MASK;
3031 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3033 static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3036 struct kvm_shadow_walk_iterator iterator;
3037 struct kvm_mmu_page *sp;
3038 int ret = RET_PF_INVALID;
3040 uint retry_count = 0;
3042 if (!page_fault_can_be_fast(error_code))
3045 walk_shadow_page_lockless_begin(vcpu);
3050 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3051 if (!is_shadow_present_pte(spte))
3054 if (!is_shadow_present_pte(spte))
3057 sp = sptep_to_sp(iterator.sptep);
3058 if (!is_last_spte(spte, sp->role.level))
3062 * Check whether the memory access that caused the fault would
3063 * still cause it if it were to be performed right now. If not,
3064 * then this is a spurious fault caused by TLB lazily flushed,
3065 * or some other CPU has already fixed the PTE after the
3066 * current CPU took the fault.
3068 * Need not check the access of upper level table entries since
3069 * they are always ACC_ALL.
3071 if (is_access_allowed(error_code, spte)) {
3072 ret = RET_PF_SPURIOUS;
3078 if (is_access_track_spte(spte))
3079 new_spte = restore_acc_track_spte(new_spte);
3082 * Currently, to simplify the code, write-protection can
3083 * be removed in the fast path only if the SPTE was
3084 * write-protected for dirty-logging or access tracking.
3086 if ((error_code & PFERR_WRITE_MASK) &&
3087 spte_can_locklessly_be_made_writable(spte)) {
3088 new_spte |= PT_WRITABLE_MASK;
3091 * Do not fix write-permission on the large spte. Since
3092 * we only dirty the first page into the dirty-bitmap in
3093 * fast_pf_fix_direct_spte(), other pages are missed
3094 * if its slot has dirty logging enabled.
3096 * Instead, we let the slow page fault path create a
3097 * normal spte to fix the access.
3099 * See the comments in kvm_arch_commit_memory_region().
3101 if (sp->role.level > PG_LEVEL_4K)
3105 /* Verify that the fault can be handled in the fast path */
3106 if (new_spte == spte ||
3107 !is_access_allowed(error_code, new_spte))
3111 * Currently, fast page fault only works for direct mapping
3112 * since the gfn is not stable for indirect shadow page. See
3113 * Documentation/virt/kvm/locking.rst to get more detail.
3115 if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte,
3121 if (++retry_count > 4) {
3122 printk_once(KERN_WARNING
3123 "kvm: Fast #PF retrying more than 4 times.\n");
3129 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3131 walk_shadow_page_lockless_end(vcpu);
3136 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3137 struct list_head *invalid_list)
3139 struct kvm_mmu_page *sp;
3141 if (!VALID_PAGE(*root_hpa))
3144 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3146 if (is_tdp_mmu_page(sp))
3147 kvm_tdp_mmu_put_root(kvm, sp, false);
3148 else if (!--sp->root_count && sp->role.invalid)
3149 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3151 *root_hpa = INVALID_PAGE;
3154 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3155 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3156 ulong roots_to_free)
3158 struct kvm *kvm = vcpu->kvm;
3160 LIST_HEAD(invalid_list);
3161 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3163 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3165 /* Before acquiring the MMU lock, see if we need to do any real work. */
3166 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3167 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3168 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3169 VALID_PAGE(mmu->prev_roots[i].hpa))
3172 if (i == KVM_MMU_NUM_PREV_ROOTS)
3176 write_lock(&kvm->mmu_lock);
3178 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3179 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3180 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3183 if (free_active_root) {
3184 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3185 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3186 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3187 } else if (mmu->pae_root) {
3188 for (i = 0; i < 4; ++i) {
3189 if (!IS_VALID_PAE_ROOT(mmu->pae_root[i]))
3192 mmu_free_root_page(kvm, &mmu->pae_root[i],
3194 mmu->pae_root[i] = INVALID_PAE_ROOT;
3197 mmu->root_hpa = INVALID_PAGE;
3201 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3202 write_unlock(&kvm->mmu_lock);
3204 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3206 void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3208 unsigned long roots_to_free = 0;
3213 * This should not be called while L2 is active, L2 can't invalidate
3214 * _only_ its own roots, e.g. INVVPID unconditionally exits.
3216 WARN_ON_ONCE(mmu->mmu_role.base.guest_mode);
3218 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3219 root_hpa = mmu->prev_roots[i].hpa;
3220 if (!VALID_PAGE(root_hpa))
3223 if (!to_shadow_page(root_hpa) ||
3224 to_shadow_page(root_hpa)->role.guest_mode)
3225 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
3228 kvm_mmu_free_roots(vcpu, mmu, roots_to_free);
3230 EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots);
3233 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3237 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3238 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3245 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3246 u8 level, bool direct)
3248 struct kvm_mmu_page *sp;
3250 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3253 return __pa(sp->spt);
3256 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3258 struct kvm_mmu *mmu = vcpu->arch.mmu;
3259 u8 shadow_root_level = mmu->shadow_root_level;
3264 write_lock(&vcpu->kvm->mmu_lock);
3265 r = make_mmu_pages_available(vcpu);
3269 if (is_tdp_mmu_enabled(vcpu->kvm)) {
3270 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3271 mmu->root_hpa = root;
3272 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3273 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true);
3274 mmu->root_hpa = root;
3275 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3276 if (WARN_ON_ONCE(!mmu->pae_root)) {
3281 for (i = 0; i < 4; ++i) {
3282 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3284 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3285 i << 30, PT32_ROOT_LEVEL, true);
3286 mmu->pae_root[i] = root | PT_PRESENT_MASK |
3289 mmu->root_hpa = __pa(mmu->pae_root);
3291 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level);
3296 /* root_pgd is ignored for direct MMUs. */
3299 write_unlock(&vcpu->kvm->mmu_lock);
3303 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3305 struct kvm_mmu *mmu = vcpu->arch.mmu;
3306 u64 pdptrs[4], pm_mask;
3307 gfn_t root_gfn, root_pgd;
3312 root_pgd = mmu->get_guest_pgd(vcpu);
3313 root_gfn = root_pgd >> PAGE_SHIFT;
3315 if (mmu_check_root(vcpu, root_gfn))
3319 * On SVM, reading PDPTRs might access guest memory, which might fault
3320 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3322 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3323 for (i = 0; i < 4; ++i) {
3324 pdptrs[i] = mmu->get_pdptr(vcpu, i);
3325 if (!(pdptrs[i] & PT_PRESENT_MASK))
3328 if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT))
3333 r = alloc_all_memslots_rmaps(vcpu->kvm);
3337 write_lock(&vcpu->kvm->mmu_lock);
3338 r = make_mmu_pages_available(vcpu);
3343 * Do we shadow a long mode page table? If so we need to
3344 * write-protect the guests page table root.
3346 if (mmu->root_level >= PT64_ROOT_4LEVEL) {
3347 root = mmu_alloc_root(vcpu, root_gfn, 0,
3348 mmu->shadow_root_level, false);
3349 mmu->root_hpa = root;
3353 if (WARN_ON_ONCE(!mmu->pae_root)) {
3359 * We shadow a 32 bit page table. This may be a legacy 2-level
3360 * or a PAE 3-level page table. In either case we need to be aware that
3361 * the shadow page table may be a PAE or a long mode page table.
3363 pm_mask = PT_PRESENT_MASK | shadow_me_mask;
3364 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3365 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3367 if (WARN_ON_ONCE(!mmu->pml4_root)) {
3372 mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask;
3375 for (i = 0; i < 4; ++i) {
3376 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3378 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3379 if (!(pdptrs[i] & PT_PRESENT_MASK)) {
3380 mmu->pae_root[i] = INVALID_PAE_ROOT;
3383 root_gfn = pdptrs[i] >> PAGE_SHIFT;
3386 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3387 PT32_ROOT_LEVEL, false);
3388 mmu->pae_root[i] = root | pm_mask;
3391 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3392 mmu->root_hpa = __pa(mmu->pml4_root);
3394 mmu->root_hpa = __pa(mmu->pae_root);
3397 mmu->root_pgd = root_pgd;
3399 write_unlock(&vcpu->kvm->mmu_lock);
3404 static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu)
3406 struct kvm_mmu *mmu = vcpu->arch.mmu;
3407 u64 *pml4_root, *pae_root;
3410 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3411 * tables are allocated and initialized at root creation as there is no
3412 * equivalent level in the guest's NPT to shadow. Allocate the tables
3413 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
3415 if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL ||
3416 mmu->shadow_root_level < PT64_ROOT_4LEVEL)
3420 * This mess only works with 4-level paging and needs to be updated to
3421 * work with 5-level paging.
3423 if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL))
3426 if (mmu->pae_root && mmu->pml4_root)
3430 * The special roots should always be allocated in concert. Yell and
3431 * bail if KVM ends up in a state where only one of the roots is valid.
3433 if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root))
3437 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3438 * doesn't need to be decrypted.
3440 pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3444 pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3446 free_page((unsigned long)pae_root);
3450 mmu->pae_root = pae_root;
3451 mmu->pml4_root = pml4_root;
3456 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3459 struct kvm_mmu_page *sp;
3461 if (vcpu->arch.mmu->direct_map)
3464 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3467 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3469 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3470 hpa_t root = vcpu->arch.mmu->root_hpa;
3471 sp = to_shadow_page(root);
3474 * Even if another CPU was marking the SP as unsync-ed
3475 * simultaneously, any guest page table changes are not
3476 * guaranteed to be visible anyway until this VCPU issues a TLB
3477 * flush strictly after those changes are made. We only need to
3478 * ensure that the other CPU sets these flags before any actual
3479 * changes to the page tables are made. The comments in
3480 * mmu_try_to_unsync_pages() describe what could go wrong if
3481 * this requirement isn't satisfied.
3483 if (!smp_load_acquire(&sp->unsync) &&
3484 !smp_load_acquire(&sp->unsync_children))
3487 write_lock(&vcpu->kvm->mmu_lock);
3488 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3490 mmu_sync_children(vcpu, sp);
3492 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3493 write_unlock(&vcpu->kvm->mmu_lock);
3497 write_lock(&vcpu->kvm->mmu_lock);
3498 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3500 for (i = 0; i < 4; ++i) {
3501 hpa_t root = vcpu->arch.mmu->pae_root[i];
3503 if (IS_VALID_PAE_ROOT(root)) {
3504 root &= PT64_BASE_ADDR_MASK;
3505 sp = to_shadow_page(root);
3506 mmu_sync_children(vcpu, sp);
3510 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3511 write_unlock(&vcpu->kvm->mmu_lock);
3514 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3515 u32 access, struct x86_exception *exception)
3518 exception->error_code = 0;
3522 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3524 struct x86_exception *exception)
3527 exception->error_code = 0;
3528 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3532 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3534 int bit7 = (pte >> 7) & 1;
3536 return pte & rsvd_check->rsvd_bits_mask[bit7][level-1];
3539 static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte)
3541 return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
3544 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3547 * A nested guest cannot use the MMIO cache if it is using nested
3548 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3550 if (mmu_is_nested(vcpu))
3554 return vcpu_match_mmio_gpa(vcpu, addr);
3556 return vcpu_match_mmio_gva(vcpu, addr);
3560 * Return the level of the lowest level SPTE added to sptes.
3561 * That SPTE may be non-present.
3563 static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
3565 struct kvm_shadow_walk_iterator iterator;
3569 walk_shadow_page_lockless_begin(vcpu);
3571 for (shadow_walk_init(&iterator, vcpu, addr),
3572 *root_level = iterator.level;
3573 shadow_walk_okay(&iterator);
3574 __shadow_walk_next(&iterator, spte)) {
3575 leaf = iterator.level;
3576 spte = mmu_spte_get_lockless(iterator.sptep);
3580 if (!is_shadow_present_pte(spte))
3584 walk_shadow_page_lockless_end(vcpu);
3589 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3590 static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3592 u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
3593 struct rsvd_bits_validate *rsvd_check;
3594 int root, leaf, level;
3595 bool reserved = false;
3597 if (is_tdp_mmu(vcpu->arch.mmu))
3598 leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
3600 leaf = get_walk(vcpu, addr, sptes, &root);
3602 if (unlikely(leaf < 0)) {
3607 *sptep = sptes[leaf];
3610 * Skip reserved bits checks on the terminal leaf if it's not a valid
3611 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3612 * design, always have reserved bits set. The purpose of the checks is
3613 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3615 if (!is_shadow_present_pte(sptes[leaf]))
3618 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3620 for (level = root; level >= leaf; level--)
3622 * Use a bitwise-OR instead of a logical-OR to aggregate the
3623 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3624 * adding a Jcc in the loop.
3626 reserved |= __is_bad_mt_xwr(rsvd_check, sptes[level]) |
3627 __is_rsvd_bits_set(rsvd_check, sptes[level], level);
3630 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
3632 for (level = root; level >= leaf; level--)
3633 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3634 sptes[level], level,
3635 rsvd_check->rsvd_bits_mask[(sptes[level] >> 7) & 1][level-1]);
3641 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3646 if (mmio_info_in_cache(vcpu, addr, direct))
3647 return RET_PF_EMULATE;
3649 reserved = get_mmio_spte(vcpu, addr, &spte);
3650 if (WARN_ON(reserved))
3653 if (is_mmio_spte(spte)) {
3654 gfn_t gfn = get_mmio_spte_gfn(spte);
3655 unsigned int access = get_mmio_spte_access(spte);
3657 if (!check_mmio_spte(vcpu, spte))
3658 return RET_PF_INVALID;
3663 trace_handle_mmio_page_fault(addr, gfn, access);
3664 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3665 return RET_PF_EMULATE;
3669 * If the page table is zapped by other cpus, let CPU fault again on
3672 return RET_PF_RETRY;
3675 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3676 u32 error_code, gfn_t gfn)
3678 if (unlikely(error_code & PFERR_RSVD_MASK))
3681 if (!(error_code & PFERR_PRESENT_MASK) ||
3682 !(error_code & PFERR_WRITE_MASK))
3686 * guest is writing the page which is write tracked which can
3687 * not be fixed by page fault handler.
3689 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3695 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3697 struct kvm_shadow_walk_iterator iterator;
3700 walk_shadow_page_lockless_begin(vcpu);
3701 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3702 clear_sp_write_flooding_count(iterator.sptep);
3703 if (!is_shadow_present_pte(spte))
3706 walk_shadow_page_lockless_end(vcpu);
3709 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3712 struct kvm_arch_async_pf arch;
3714 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3716 arch.direct_map = vcpu->arch.mmu->direct_map;
3717 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3719 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3720 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3723 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3724 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva,
3725 bool write, bool *writable)
3727 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3731 * Retry the page fault if the gfn hit a memslot that is being deleted
3732 * or moved. This ensures any existing SPTEs for the old memslot will
3733 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3735 if (slot && (slot->flags & KVM_MEMSLOT_INVALID))
3738 /* Don't expose private memslots to L2. */
3739 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3740 *pfn = KVM_PFN_NOSLOT;
3746 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async,
3747 write, writable, hva);
3749 return false; /* *pfn has correct page already */
3751 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3752 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
3753 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3754 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
3755 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3757 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
3761 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL,
3762 write, writable, hva);
3766 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3767 bool prefault, int max_level, bool is_tdp)
3769 bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu);
3770 bool write = error_code & PFERR_WRITE_MASK;
3773 gfn_t gfn = gpa >> PAGE_SHIFT;
3774 unsigned long mmu_seq;
3779 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3780 return RET_PF_EMULATE;
3782 if (!is_tdp_mmu_fault) {
3783 r = fast_page_fault(vcpu, gpa, error_code);
3784 if (r != RET_PF_INVALID)
3788 r = mmu_topup_memory_caches(vcpu, false);
3792 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3795 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, &hva,
3796 write, &map_writable))
3797 return RET_PF_RETRY;
3799 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
3804 if (is_tdp_mmu_fault)
3805 read_lock(&vcpu->kvm->mmu_lock);
3807 write_lock(&vcpu->kvm->mmu_lock);
3809 if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva))
3811 r = make_mmu_pages_available(vcpu);
3815 if (is_tdp_mmu_fault)
3816 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
3819 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
3823 if (is_tdp_mmu_fault)
3824 read_unlock(&vcpu->kvm->mmu_lock);
3826 write_unlock(&vcpu->kvm->mmu_lock);
3827 kvm_release_pfn_clean(pfn);
3831 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
3832 u32 error_code, bool prefault)
3834 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
3836 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3837 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3838 PG_LEVEL_2M, false);
3841 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3842 u64 fault_address, char *insn, int insn_len)
3845 u32 flags = vcpu->arch.apf.host_apf_flags;
3847 #ifndef CONFIG_X86_64
3848 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3849 if (WARN_ON_ONCE(fault_address >> 32))
3853 vcpu->arch.l1tf_flush_l1d = true;
3855 trace_kvm_page_fault(fault_address, error_code);
3857 if (kvm_event_needs_reinjection(vcpu))
3858 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3859 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3861 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
3862 vcpu->arch.apf.host_apf_flags = 0;
3863 local_irq_disable();
3864 kvm_async_pf_task_wait_schedule(fault_address);
3867 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
3872 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3874 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3879 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3880 max_level > PG_LEVEL_4K;
3882 int page_num = KVM_PAGES_PER_HPAGE(max_level);
3883 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
3885 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
3889 return direct_page_fault(vcpu, gpa, error_code, prefault,
3893 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3894 struct kvm_mmu *context)
3896 context->page_fault = nonpaging_page_fault;
3897 context->gva_to_gpa = nonpaging_gva_to_gpa;
3898 context->sync_page = nonpaging_sync_page;
3899 context->invlpg = NULL;
3900 context->root_level = 0;
3901 context->shadow_root_level = PT32E_ROOT_LEVEL;
3902 context->direct_map = true;
3903 context->nx = false;
3906 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
3907 union kvm_mmu_page_role role)
3909 return (role.direct || pgd == root->pgd) &&
3910 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
3911 role.word == to_shadow_page(root->hpa)->role.word;
3915 * Find out if a previously cached root matching the new pgd/role is available.
3916 * The current root is also inserted into the cache.
3917 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3919 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3920 * false is returned. This root should now be freed by the caller.
3922 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3923 union kvm_mmu_page_role new_role)
3926 struct kvm_mmu_root_info root;
3927 struct kvm_mmu *mmu = vcpu->arch.mmu;
3929 root.pgd = mmu->root_pgd;
3930 root.hpa = mmu->root_hpa;
3932 if (is_root_usable(&root, new_pgd, new_role))
3935 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3936 swap(root, mmu->prev_roots[i]);
3938 if (is_root_usable(&root, new_pgd, new_role))
3942 mmu->root_hpa = root.hpa;
3943 mmu->root_pgd = root.pgd;
3945 return i < KVM_MMU_NUM_PREV_ROOTS;
3948 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3949 union kvm_mmu_page_role new_role)
3951 struct kvm_mmu *mmu = vcpu->arch.mmu;
3954 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
3955 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
3956 * later if necessary.
3958 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3959 mmu->root_level >= PT64_ROOT_4LEVEL)
3960 return cached_root_available(vcpu, new_pgd, new_role);
3965 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3966 union kvm_mmu_page_role new_role)
3968 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
3969 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
3974 * It's possible that the cached previous root page is obsolete because
3975 * of a change in the MMU generation number. However, changing the
3976 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
3977 * free the root set here and allocate a new one.
3979 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
3981 if (force_flush_and_sync_on_reuse) {
3982 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
3983 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3987 * The last MMIO access's GVA and GPA are cached in the VCPU. When
3988 * switching to a new CR3, that GVA->GPA mapping may no longer be
3989 * valid. So clear any cached MMIO info even when we don't need to sync
3990 * the shadow page tables.
3992 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3995 * If this is a direct root page, it doesn't have a write flooding
3996 * count. Otherwise, clear the write flooding count.
3998 if (!new_role.direct)
3999 __clear_sp_write_flooding_count(
4000 to_shadow_page(vcpu->arch.mmu->root_hpa));
4003 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd)
4005 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu));
4007 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
4009 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4011 return kvm_read_cr3(vcpu);
4014 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4015 unsigned int access, int *nr_present)
4017 if (unlikely(is_mmio_spte(*sptep))) {
4018 if (gfn != get_mmio_spte_gfn(*sptep)) {
4019 mmu_spte_clear_no_track(sptep);
4024 mark_mmio_spte(vcpu, sptep, gfn, access);
4031 static inline bool is_last_gpte(struct kvm_mmu *mmu,
4032 unsigned level, unsigned gpte)
4035 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4036 * If it is clear, there are no large pages at this level, so clear
4037 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4039 gpte &= level - mmu->last_nonleaf_level;
4042 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
4043 * iff level <= PG_LEVEL_4K, which for our purpose means
4044 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
4046 gpte |= level - PG_LEVEL_4K - 1;
4048 return gpte & PT_PAGE_SIZE_MASK;
4051 #define PTTYPE_EPT 18 /* arbitrary */
4052 #define PTTYPE PTTYPE_EPT
4053 #include "paging_tmpl.h"
4057 #include "paging_tmpl.h"
4061 #include "paging_tmpl.h"
4065 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4066 struct rsvd_bits_validate *rsvd_check,
4067 u64 pa_bits_rsvd, int level, bool nx, bool gbpages,
4070 u64 gbpages_bit_rsvd = 0;
4071 u64 nonleaf_bit8_rsvd = 0;
4074 rsvd_check->bad_mt_xwr = 0;
4077 gbpages_bit_rsvd = rsvd_bits(7, 7);
4079 if (level == PT32E_ROOT_LEVEL)
4080 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62);
4082 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4084 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4086 high_bits_rsvd |= rsvd_bits(63, 63);
4089 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4090 * leaf entries) on AMD CPUs only.
4093 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4096 case PT32_ROOT_LEVEL:
4097 /* no rsvd bits for 2 level 4K page table entries */
4098 rsvd_check->rsvd_bits_mask[0][1] = 0;
4099 rsvd_check->rsvd_bits_mask[0][0] = 0;
4100 rsvd_check->rsvd_bits_mask[1][0] =
4101 rsvd_check->rsvd_bits_mask[0][0];
4104 rsvd_check->rsvd_bits_mask[1][1] = 0;
4108 if (is_cpuid_PSE36())
4109 /* 36bits PSE 4MB page */
4110 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4112 /* 32 bits PSE 4MB page */
4113 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4115 case PT32E_ROOT_LEVEL:
4116 rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
4119 rsvd_bits(1, 2); /* PDPTE */
4120 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
4121 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
4122 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4123 rsvd_bits(13, 20); /* large page */
4124 rsvd_check->rsvd_bits_mask[1][0] =
4125 rsvd_check->rsvd_bits_mask[0][0];
4127 case PT64_ROOT_5LEVEL:
4128 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd |
4131 rsvd_check->rsvd_bits_mask[1][4] =
4132 rsvd_check->rsvd_bits_mask[0][4];
4134 case PT64_ROOT_4LEVEL:
4135 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd |
4138 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd |
4140 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd;
4141 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4142 rsvd_check->rsvd_bits_mask[1][3] =
4143 rsvd_check->rsvd_bits_mask[0][3];
4144 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd |
4147 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4148 rsvd_bits(13, 20); /* large page */
4149 rsvd_check->rsvd_bits_mask[1][0] =
4150 rsvd_check->rsvd_bits_mask[0][0];
4155 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4156 struct kvm_mmu *context)
4158 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4159 vcpu->arch.reserved_gpa_bits,
4160 context->root_level, context->nx,
4161 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4163 guest_cpuid_is_amd_or_hygon(vcpu));
4167 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4168 u64 pa_bits_rsvd, bool execonly)
4170 u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4173 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
4174 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
4175 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6);
4176 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6);
4177 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4180 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4181 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4182 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29);
4183 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20);
4184 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4186 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4187 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4188 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4189 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4190 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4192 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4193 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4195 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4198 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4199 struct kvm_mmu *context, bool execonly)
4201 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4202 vcpu->arch.reserved_gpa_bits, execonly);
4205 static inline u64 reserved_hpa_bits(void)
4207 return rsvd_bits(shadow_phys_bits, 63);
4211 * the page table on host is the shadow page table for the page
4212 * table in guest or amd nested guest, its mmu features completely
4213 * follow the features in guest.
4216 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4219 * KVM uses NX when TDP is disabled to handle a variety of scenarios,
4220 * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
4221 * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
4222 * The iTLB multi-hit workaround can be toggled at any time, so assume
4223 * NX can be used by any non-nested shadow MMU to avoid having to reset
4224 * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
4226 bool uses_nx = context->nx || !tdp_enabled ||
4227 context->mmu_role.base.smep_andnot_wp;
4228 struct rsvd_bits_validate *shadow_zero_check;
4232 * Passing "true" to the last argument is okay; it adds a check
4233 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4235 shadow_zero_check = &context->shadow_zero_check;
4236 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4237 reserved_hpa_bits(),
4238 context->shadow_root_level, uses_nx,
4239 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4240 is_pse(vcpu), true);
4242 if (!shadow_me_mask)
4245 for (i = context->shadow_root_level; --i >= 0;) {
4246 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4247 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4251 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4253 static inline bool boot_cpu_is_amd(void)
4255 WARN_ON_ONCE(!tdp_enabled);
4256 return shadow_x_mask == 0;
4260 * the direct page table on host, use as much mmu features as
4261 * possible, however, kvm currently does not do execution-protection.
4264 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4265 struct kvm_mmu *context)
4267 struct rsvd_bits_validate *shadow_zero_check;
4270 shadow_zero_check = &context->shadow_zero_check;
4272 if (boot_cpu_is_amd())
4273 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4274 reserved_hpa_bits(),
4275 context->shadow_root_level, false,
4276 boot_cpu_has(X86_FEATURE_GBPAGES),
4279 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4280 reserved_hpa_bits(), false);
4282 if (!shadow_me_mask)
4285 for (i = context->shadow_root_level; --i >= 0;) {
4286 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4287 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4292 * as the comments in reset_shadow_zero_bits_mask() except it
4293 * is the shadow page table for intel nested guest.
4296 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4297 struct kvm_mmu *context, bool execonly)
4299 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4300 reserved_hpa_bits(), execonly);
4303 #define BYTE_MASK(access) \
4304 ((1 & (access) ? 2 : 0) | \
4305 (2 & (access) ? 4 : 0) | \
4306 (3 & (access) ? 8 : 0) | \
4307 (4 & (access) ? 16 : 0) | \
4308 (5 & (access) ? 32 : 0) | \
4309 (6 & (access) ? 64 : 0) | \
4310 (7 & (access) ? 128 : 0))
4313 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4314 struct kvm_mmu *mmu, bool ept)
4318 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4319 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4320 const u8 u = BYTE_MASK(ACC_USER_MASK);
4322 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4323 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4324 bool cr0_wp = is_write_protection(vcpu);
4326 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4327 unsigned pfec = byte << 1;
4330 * Each "*f" variable has a 1 bit for each UWX value
4331 * that causes a fault with the given PFEC.
4334 /* Faults from writes to non-writable pages */
4335 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4336 /* Faults from user mode accesses to supervisor pages */
4337 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4338 /* Faults from fetches of non-executable pages*/
4339 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4340 /* Faults from kernel mode fetches of user pages */
4342 /* Faults from kernel mode accesses of user pages */
4346 /* Faults from kernel mode accesses to user pages */
4347 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4349 /* Not really needed: !nx will cause pte.nx to fault */
4353 /* Allow supervisor writes if !cr0.wp */
4355 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4357 /* Disallow supervisor fetches of user code if cr4.smep */
4359 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4362 * SMAP:kernel-mode data accesses from user-mode
4363 * mappings should fault. A fault is considered
4364 * as a SMAP violation if all of the following
4365 * conditions are true:
4366 * - X86_CR4_SMAP is set in CR4
4367 * - A user page is accessed
4368 * - The access is not a fetch
4369 * - Page fault in kernel mode
4370 * - if CPL = 3 or X86_EFLAGS_AC is clear
4372 * Here, we cover the first three conditions.
4373 * The fourth is computed dynamically in permission_fault();
4374 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4375 * *not* subject to SMAP restrictions.
4378 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4381 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4386 * PKU is an additional mechanism by which the paging controls access to
4387 * user-mode addresses based on the value in the PKRU register. Protection
4388 * key violations are reported through a bit in the page fault error code.
4389 * Unlike other bits of the error code, the PK bit is not known at the
4390 * call site of e.g. gva_to_gpa; it must be computed directly in
4391 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4392 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4394 * In particular the following conditions come from the error code, the
4395 * page tables and the machine state:
4396 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4397 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4398 * - PK is always zero if U=0 in the page tables
4399 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4401 * The PKRU bitmask caches the result of these four conditions. The error
4402 * code (minus the P bit) and the page table's U bit form an index into the
4403 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4404 * with the two bits of the PKRU register corresponding to the protection key.
4405 * For the first three conditions above the bits will be 00, thus masking
4406 * away both AD and WD. For all reads or if the last condition holds, WD
4407 * only will be masked away.
4409 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4420 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4421 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4426 wp = is_write_protection(vcpu);
4428 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4429 unsigned pfec, pkey_bits;
4430 bool check_pkey, check_write, ff, uf, wf, pte_user;
4433 ff = pfec & PFERR_FETCH_MASK;
4434 uf = pfec & PFERR_USER_MASK;
4435 wf = pfec & PFERR_WRITE_MASK;
4437 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4438 pte_user = pfec & PFERR_RSVD_MASK;
4441 * Only need to check the access which is not an
4442 * instruction fetch and is to a user page.
4444 check_pkey = (!ff && pte_user);
4446 * write access is controlled by PKRU if it is a
4447 * user access or CR0.WP = 1.
4449 check_write = check_pkey && wf && (uf || wp);
4451 /* PKRU.AD stops both read and write access. */
4452 pkey_bits = !!check_pkey;
4453 /* PKRU.WD stops write access. */
4454 pkey_bits |= (!!check_write) << 1;
4456 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4460 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4462 unsigned root_level = mmu->root_level;
4464 mmu->last_nonleaf_level = root_level;
4465 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4466 mmu->last_nonleaf_level++;
4469 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4470 struct kvm_mmu *context,
4473 context->nx = is_nx(vcpu);
4474 context->root_level = level;
4476 reset_rsvds_bits_mask(vcpu, context);
4477 update_permission_bitmask(vcpu, context, false);
4478 update_pkru_bitmask(vcpu, context, false);
4479 update_last_nonleaf_level(vcpu, context);
4481 MMU_WARN_ON(!is_pae(vcpu));
4482 context->page_fault = paging64_page_fault;
4483 context->gva_to_gpa = paging64_gva_to_gpa;
4484 context->sync_page = paging64_sync_page;
4485 context->invlpg = paging64_invlpg;
4486 context->shadow_root_level = level;
4487 context->direct_map = false;
4490 static void paging64_init_context(struct kvm_vcpu *vcpu,
4491 struct kvm_mmu *context)
4493 int root_level = is_la57_mode(vcpu) ?
4494 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4496 paging64_init_context_common(vcpu, context, root_level);
4499 static void paging32_init_context(struct kvm_vcpu *vcpu,
4500 struct kvm_mmu *context)
4502 context->nx = false;
4503 context->root_level = PT32_ROOT_LEVEL;
4505 reset_rsvds_bits_mask(vcpu, context);
4506 update_permission_bitmask(vcpu, context, false);
4507 update_pkru_bitmask(vcpu, context, false);
4508 update_last_nonleaf_level(vcpu, context);
4510 context->page_fault = paging32_page_fault;
4511 context->gva_to_gpa = paging32_gva_to_gpa;
4512 context->sync_page = paging32_sync_page;
4513 context->invlpg = paging32_invlpg;
4514 context->shadow_root_level = PT32E_ROOT_LEVEL;
4515 context->direct_map = false;
4518 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4519 struct kvm_mmu *context)
4521 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4524 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4526 union kvm_mmu_extended_role ext = {0};
4528 ext.cr0_pg = !!is_paging(vcpu);
4529 ext.cr4_pae = !!is_pae(vcpu);
4530 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4531 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4532 ext.cr4_pse = !!is_pse(vcpu);
4533 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4534 ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
4541 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4544 union kvm_mmu_role role = {0};
4546 role.base.access = ACC_ALL;
4547 role.base.nxe = !!is_nx(vcpu);
4548 role.base.cr0_wp = is_write_protection(vcpu);
4549 role.base.smm = is_smm(vcpu);
4550 role.base.guest_mode = is_guest_mode(vcpu);
4555 role.ext = kvm_calc_mmu_role_ext(vcpu);
4560 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4562 /* Use 5-level TDP if and only if it's useful/necessary. */
4563 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4566 return max_tdp_level;
4569 static union kvm_mmu_role
4570 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4572 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4574 role.base.ad_disabled = (shadow_accessed_mask == 0);
4575 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4576 role.base.direct = true;
4577 role.base.gpte_is_8_bytes = true;
4582 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4584 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4585 union kvm_mmu_role new_role =
4586 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
4588 if (new_role.as_u64 == context->mmu_role.as_u64)
4591 context->mmu_role.as_u64 = new_role.as_u64;
4592 context->page_fault = kvm_tdp_page_fault;
4593 context->sync_page = nonpaging_sync_page;
4594 context->invlpg = NULL;
4595 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4596 context->direct_map = true;
4597 context->get_guest_pgd = get_cr3;
4598 context->get_pdptr = kvm_pdptr_read;
4599 context->inject_page_fault = kvm_inject_page_fault;
4601 if (!is_paging(vcpu)) {
4602 context->nx = false;
4603 context->gva_to_gpa = nonpaging_gva_to_gpa;
4604 context->root_level = 0;
4605 } else if (is_long_mode(vcpu)) {
4606 context->nx = is_nx(vcpu);
4607 context->root_level = is_la57_mode(vcpu) ?
4608 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4609 reset_rsvds_bits_mask(vcpu, context);
4610 context->gva_to_gpa = paging64_gva_to_gpa;
4611 } else if (is_pae(vcpu)) {
4612 context->nx = is_nx(vcpu);
4613 context->root_level = PT32E_ROOT_LEVEL;
4614 reset_rsvds_bits_mask(vcpu, context);
4615 context->gva_to_gpa = paging64_gva_to_gpa;
4617 context->nx = false;
4618 context->root_level = PT32_ROOT_LEVEL;
4619 reset_rsvds_bits_mask(vcpu, context);
4620 context->gva_to_gpa = paging32_gva_to_gpa;
4623 update_permission_bitmask(vcpu, context, false);
4624 update_pkru_bitmask(vcpu, context, false);
4625 update_last_nonleaf_level(vcpu, context);
4626 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4629 static union kvm_mmu_role
4630 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, bool base_only)
4632 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4634 role.base.smep_andnot_wp = role.ext.cr4_smep &&
4635 !is_write_protection(vcpu);
4636 role.base.smap_andnot_wp = role.ext.cr4_smap &&
4637 !is_write_protection(vcpu);
4638 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
4643 static union kvm_mmu_role
4644 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4646 union kvm_mmu_role role =
4647 kvm_calc_shadow_root_page_role_common(vcpu, base_only);
4649 role.base.direct = !is_paging(vcpu);
4651 if (!is_long_mode(vcpu))
4652 role.base.level = PT32E_ROOT_LEVEL;
4653 else if (is_la57_mode(vcpu))
4654 role.base.level = PT64_ROOT_5LEVEL;
4656 role.base.level = PT64_ROOT_4LEVEL;
4661 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4662 u32 cr0, u32 cr4, u32 efer,
4663 union kvm_mmu_role new_role)
4665 if (!(cr0 & X86_CR0_PG))
4666 nonpaging_init_context(vcpu, context);
4667 else if (efer & EFER_LMA)
4668 paging64_init_context(vcpu, context);
4669 else if (cr4 & X86_CR4_PAE)
4670 paging32E_init_context(vcpu, context);
4672 paging32_init_context(vcpu, context);
4674 context->mmu_role.as_u64 = new_role.as_u64;
4675 reset_shadow_zero_bits_mask(vcpu, context);
4678 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer)
4680 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4681 union kvm_mmu_role new_role =
4682 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4684 if (new_role.as_u64 != context->mmu_role.as_u64)
4685 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4688 static union kvm_mmu_role
4689 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu)
4691 union kvm_mmu_role role =
4692 kvm_calc_shadow_root_page_role_common(vcpu, false);
4694 role.base.direct = false;
4695 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4700 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer,
4703 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4704 union kvm_mmu_role new_role = kvm_calc_shadow_npt_root_page_role(vcpu);
4706 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base);
4708 if (new_role.as_u64 != context->mmu_role.as_u64) {
4709 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4712 * Override the level set by the common init helper, nested TDP
4713 * always uses the host's TDP configuration.
4715 context->shadow_root_level = new_role.base.level;
4718 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4720 static union kvm_mmu_role
4721 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4722 bool execonly, u8 level)
4724 union kvm_mmu_role role = {0};
4726 /* SMM flag is inherited from root_mmu */
4727 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4729 role.base.level = level;
4730 role.base.gpte_is_8_bytes = true;
4731 role.base.direct = false;
4732 role.base.ad_disabled = !accessed_dirty;
4733 role.base.guest_mode = true;
4734 role.base.access = ACC_ALL;
4736 role.ext = kvm_calc_mmu_role_ext(vcpu);
4737 role.ext.execonly = execonly;
4742 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4743 bool accessed_dirty, gpa_t new_eptp)
4745 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4746 u8 level = vmx_eptp_page_walk_level(new_eptp);
4747 union kvm_mmu_role new_role =
4748 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4751 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base);
4753 if (new_role.as_u64 == context->mmu_role.as_u64)
4756 context->shadow_root_level = level;
4759 context->ept_ad = accessed_dirty;
4760 context->page_fault = ept_page_fault;
4761 context->gva_to_gpa = ept_gva_to_gpa;
4762 context->sync_page = ept_sync_page;
4763 context->invlpg = ept_invlpg;
4764 context->root_level = level;
4765 context->direct_map = false;
4766 context->mmu_role.as_u64 = new_role.as_u64;
4768 update_permission_bitmask(vcpu, context, true);
4769 update_pkru_bitmask(vcpu, context, true);
4770 update_last_nonleaf_level(vcpu, context);
4771 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4772 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4774 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4776 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4778 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4780 kvm_init_shadow_mmu(vcpu,
4781 kvm_read_cr0_bits(vcpu, X86_CR0_PG),
4782 kvm_read_cr4_bits(vcpu, X86_CR4_PAE),
4785 context->get_guest_pgd = get_cr3;
4786 context->get_pdptr = kvm_pdptr_read;
4787 context->inject_page_fault = kvm_inject_page_fault;
4790 static union kvm_mmu_role kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu)
4792 union kvm_mmu_role role = kvm_calc_shadow_root_page_role_common(vcpu, false);
4795 * Nested MMUs are used only for walking L2's gva->gpa, they never have
4796 * shadow pages of their own and so "direct" has no meaning. Set it
4797 * to "true" to try to detect bogus usage of the nested MMU.
4799 role.base.direct = true;
4801 if (!is_paging(vcpu))
4802 role.base.level = 0;
4803 else if (is_long_mode(vcpu))
4804 role.base.level = is_la57_mode(vcpu) ? PT64_ROOT_5LEVEL :
4806 else if (is_pae(vcpu))
4807 role.base.level = PT32E_ROOT_LEVEL;
4809 role.base.level = PT32_ROOT_LEVEL;
4814 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4816 union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu);
4817 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4819 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4822 g_context->mmu_role.as_u64 = new_role.as_u64;
4823 g_context->get_guest_pgd = get_cr3;
4824 g_context->get_pdptr = kvm_pdptr_read;
4825 g_context->inject_page_fault = kvm_inject_page_fault;
4828 * L2 page tables are never shadowed, so there is no need to sync
4831 g_context->invlpg = NULL;
4834 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4835 * L1's nested page tables (e.g. EPT12). The nested translation
4836 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4837 * L2's page tables as the first level of translation and L1's
4838 * nested page tables as the second level of translation. Basically
4839 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4841 if (!is_paging(vcpu)) {
4842 g_context->nx = false;
4843 g_context->root_level = 0;
4844 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4845 } else if (is_long_mode(vcpu)) {
4846 g_context->nx = is_nx(vcpu);
4847 g_context->root_level = is_la57_mode(vcpu) ?
4848 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4849 reset_rsvds_bits_mask(vcpu, g_context);
4850 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4851 } else if (is_pae(vcpu)) {
4852 g_context->nx = is_nx(vcpu);
4853 g_context->root_level = PT32E_ROOT_LEVEL;
4854 reset_rsvds_bits_mask(vcpu, g_context);
4855 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4857 g_context->nx = false;
4858 g_context->root_level = PT32_ROOT_LEVEL;
4859 reset_rsvds_bits_mask(vcpu, g_context);
4860 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4863 update_permission_bitmask(vcpu, g_context, false);
4864 update_pkru_bitmask(vcpu, g_context, false);
4865 update_last_nonleaf_level(vcpu, g_context);
4868 void kvm_init_mmu(struct kvm_vcpu *vcpu)
4870 if (mmu_is_nested(vcpu))
4871 init_kvm_nested_mmu(vcpu);
4872 else if (tdp_enabled)
4873 init_kvm_tdp_mmu(vcpu);
4875 init_kvm_softmmu(vcpu);
4877 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4879 static union kvm_mmu_page_role
4880 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4882 union kvm_mmu_role role;
4885 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
4887 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
4892 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu)
4895 * Invalidate all MMU roles to force them to reinitialize as CPUID
4896 * information is factored into reserved bit calculations.
4898 vcpu->arch.root_mmu.mmu_role.ext.valid = 0;
4899 vcpu->arch.guest_mmu.mmu_role.ext.valid = 0;
4900 vcpu->arch.nested_mmu.mmu_role.ext.valid = 0;
4901 kvm_mmu_reset_context(vcpu);
4904 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
4905 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
4906 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
4907 * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise
4908 * sweep the problem under the rug.
4910 * KVM's horrific CPUID ABI makes the problem all but impossible to
4911 * solve, as correctly handling multiple vCPU models (with respect to
4912 * paging and physical address properties) in a single VM would require
4913 * tracking all relevant CPUID information in kvm_mmu_page_role. That
4914 * is very undesirable as it would double the memory requirements for
4915 * gfn_track (see struct kvm_mmu_page_role comments), and in practice
4916 * no sane VMM mucks with the core vCPU model on the fly.
4918 if (vcpu->arch.last_vmentry_cpu != -1) {
4919 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n");
4920 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n");
4924 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4926 kvm_mmu_unload(vcpu);
4929 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4931 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4935 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
4938 r = mmu_alloc_special_roots(vcpu);
4941 if (vcpu->arch.mmu->direct_map)
4942 r = mmu_alloc_direct_roots(vcpu);
4944 r = mmu_alloc_shadow_roots(vcpu);
4948 kvm_mmu_sync_roots(vcpu);
4950 kvm_mmu_load_pgd(vcpu);
4951 static_call(kvm_x86_tlb_flush_current)(vcpu);
4956 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4958 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
4959 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
4960 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4961 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
4964 static bool need_remote_flush(u64 old, u64 new)
4966 if (!is_shadow_present_pte(old))
4968 if (!is_shadow_present_pte(new))
4970 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4972 old ^= shadow_nx_mask;
4973 new ^= shadow_nx_mask;
4974 return (old & ~new & PT64_PERM_MASK) != 0;
4977 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4984 * Assume that the pte write on a page table of the same type
4985 * as the current vcpu paging mode since we update the sptes only
4986 * when they have the same mode.
4988 if (is_pae(vcpu) && *bytes == 4) {
4989 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4994 if (*bytes == 4 || *bytes == 8) {
4995 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5004 * If we're seeing too many writes to a page, it may no longer be a page table,
5005 * or we may be forking, in which case it is better to unmap the page.
5007 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5010 * Skip write-flooding detected for the sp whose level is 1, because
5011 * it can become unsync, then the guest page is not write-protected.
5013 if (sp->role.level == PG_LEVEL_4K)
5016 atomic_inc(&sp->write_flooding_count);
5017 return atomic_read(&sp->write_flooding_count) >= 3;
5021 * Misaligned accesses are too much trouble to fix up; also, they usually
5022 * indicate a page is not used as a page table.
5024 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5027 unsigned offset, pte_size, misaligned;
5029 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5030 gpa, bytes, sp->role.word);
5032 offset = offset_in_page(gpa);
5033 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5036 * Sometimes, the OS only writes the last one bytes to update status
5037 * bits, for example, in linux, andb instruction is used in clear_bit().
5039 if (!(offset & (pte_size - 1)) && bytes == 1)
5042 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5043 misaligned |= bytes < 4;
5048 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5050 unsigned page_offset, quadrant;
5054 page_offset = offset_in_page(gpa);
5055 level = sp->role.level;
5057 if (!sp->role.gpte_is_8_bytes) {
5058 page_offset <<= 1; /* 32->64 */
5060 * A 32-bit pde maps 4MB while the shadow pdes map
5061 * only 2MB. So we need to double the offset again
5062 * and zap two pdes instead of one.
5064 if (level == PT32_ROOT_LEVEL) {
5065 page_offset &= ~7; /* kill rounding error */
5069 quadrant = page_offset >> PAGE_SHIFT;
5070 page_offset &= ~PAGE_MASK;
5071 if (quadrant != sp->role.quadrant)
5075 spte = &sp->spt[page_offset / sizeof(*spte)];
5079 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5080 const u8 *new, int bytes,
5081 struct kvm_page_track_notifier_node *node)
5083 gfn_t gfn = gpa >> PAGE_SHIFT;
5084 struct kvm_mmu_page *sp;
5085 LIST_HEAD(invalid_list);
5086 u64 entry, gentry, *spte;
5088 bool remote_flush, local_flush;
5091 * If we don't have indirect shadow pages, it means no page is
5092 * write-protected, so we can exit simply.
5094 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5097 remote_flush = local_flush = false;
5099 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5102 * No need to care whether allocation memory is successful
5103 * or not since pte prefetch is skipped if it does not have
5104 * enough objects in the cache.
5106 mmu_topup_memory_caches(vcpu, true);
5108 write_lock(&vcpu->kvm->mmu_lock);
5110 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5112 ++vcpu->kvm->stat.mmu_pte_write;
5113 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5115 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5116 if (detect_write_misaligned(sp, gpa, bytes) ||
5117 detect_write_flooding(sp)) {
5118 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5119 ++vcpu->kvm->stat.mmu_flooded;
5123 spte = get_written_sptes(sp, gpa, &npte);
5130 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
5131 if (gentry && sp->role.level != PG_LEVEL_4K)
5132 ++vcpu->kvm->stat.mmu_pde_zapped;
5133 if (need_remote_flush(entry, *spte))
5134 remote_flush = true;
5138 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5139 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5140 write_unlock(&vcpu->kvm->mmu_lock);
5143 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5144 void *insn, int insn_len)
5146 int r, emulation_type = EMULTYPE_PF;
5147 bool direct = vcpu->arch.mmu->direct_map;
5149 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5150 return RET_PF_RETRY;
5153 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5154 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5155 if (r == RET_PF_EMULATE)
5159 if (r == RET_PF_INVALID) {
5160 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5161 lower_32_bits(error_code), false);
5162 if (WARN_ON_ONCE(r == RET_PF_INVALID))
5168 if (r != RET_PF_EMULATE)
5172 * Before emulating the instruction, check if the error code
5173 * was due to a RO violation while translating the guest page.
5174 * This can occur when using nested virtualization with nested
5175 * paging in both guests. If true, we simply unprotect the page
5176 * and resume the guest.
5178 if (vcpu->arch.mmu->direct_map &&
5179 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5180 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5185 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5186 * optimistically try to just unprotect the page and let the processor
5187 * re-execute the instruction that caused the page fault. Do not allow
5188 * retrying MMIO emulation, as it's not only pointless but could also
5189 * cause us to enter an infinite loop because the processor will keep
5190 * faulting on the non-existent MMIO address. Retrying an instruction
5191 * from a nested guest is also pointless and dangerous as we are only
5192 * explicitly shadowing L1's page tables, i.e. unprotecting something
5193 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5195 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5196 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5198 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5201 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5203 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5204 gva_t gva, hpa_t root_hpa)
5208 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5209 if (mmu != &vcpu->arch.guest_mmu) {
5210 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5211 if (is_noncanonical_address(gva, vcpu))
5214 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5220 if (root_hpa == INVALID_PAGE) {
5221 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5224 * INVLPG is required to invalidate any global mappings for the VA,
5225 * irrespective of PCID. Since it would take us roughly similar amount
5226 * of work to determine whether any of the prev_root mappings of the VA
5227 * is marked global, or to just sync it blindly, so we might as well
5228 * just always sync it.
5230 * Mappings not reachable via the current cr3 or the prev_roots will be
5231 * synced when switching to that cr3, so nothing needs to be done here
5234 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5235 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5236 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5238 mmu->invlpg(vcpu, gva, root_hpa);
5242 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5244 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
5245 ++vcpu->stat.invlpg;
5247 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5250 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5252 struct kvm_mmu *mmu = vcpu->arch.mmu;
5253 bool tlb_flush = false;
5256 if (pcid == kvm_get_active_pcid(vcpu)) {
5257 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5261 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5262 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5263 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5264 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5270 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5272 ++vcpu->stat.invlpg;
5275 * Mappings not reachable via the current cr3 or the prev_roots will be
5276 * synced when switching to that cr3, so nothing needs to be done here
5281 void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
5282 int tdp_huge_page_level)
5284 tdp_enabled = enable_tdp;
5285 max_tdp_level = tdp_max_root_level;
5288 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5289 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5290 * the kernel is not. But, KVM never creates a page size greater than
5291 * what is used by the kernel for any given HVA, i.e. the kernel's
5292 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5295 max_huge_page_level = tdp_huge_page_level;
5296 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5297 max_huge_page_level = PG_LEVEL_1G;
5299 max_huge_page_level = PG_LEVEL_2M;
5301 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5303 /* The return value indicates if tlb flush on all vcpus is needed. */
5304 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head,
5305 struct kvm_memory_slot *slot);
5307 /* The caller should hold mmu-lock before calling this function. */
5308 static __always_inline bool
5309 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5310 slot_level_handler fn, int start_level, int end_level,
5311 gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield,
5314 struct slot_rmap_walk_iterator iterator;
5316 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5317 end_gfn, &iterator) {
5319 flush |= fn(kvm, iterator.rmap, memslot);
5321 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
5322 if (flush && flush_on_yield) {
5323 kvm_flush_remote_tlbs_with_address(kvm,
5325 iterator.gfn - start_gfn + 1);
5328 cond_resched_rwlock_write(&kvm->mmu_lock);
5335 static __always_inline bool
5336 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5337 slot_level_handler fn, int start_level, int end_level,
5338 bool flush_on_yield)
5340 return slot_handle_level_range(kvm, memslot, fn, start_level,
5341 end_level, memslot->base_gfn,
5342 memslot->base_gfn + memslot->npages - 1,
5343 flush_on_yield, false);
5346 static __always_inline bool
5347 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5348 slot_level_handler fn, bool flush_on_yield)
5350 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5351 PG_LEVEL_4K, flush_on_yield);
5354 static void free_mmu_pages(struct kvm_mmu *mmu)
5356 if (!tdp_enabled && mmu->pae_root)
5357 set_memory_encrypted((unsigned long)mmu->pae_root, 1);
5358 free_page((unsigned long)mmu->pae_root);
5359 free_page((unsigned long)mmu->pml4_root);
5362 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5367 mmu->root_hpa = INVALID_PAGE;
5369 mmu->translate_gpa = translate_gpa;
5370 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5371 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5374 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5375 * while the PDP table is a per-vCPU construct that's allocated at MMU
5376 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5377 * x86_64. Therefore we need to allocate the PDP table in the first
5378 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5379 * generally doesn't use PAE paging and can skip allocating the PDP
5380 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5381 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5382 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
5384 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5387 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5391 mmu->pae_root = page_address(page);
5394 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5395 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5396 * that KVM's writes and the CPU's reads get along. Note, this is
5397 * only necessary when using shadow paging, as 64-bit NPT can get at
5398 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5399 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5402 set_memory_decrypted((unsigned long)mmu->pae_root, 1);
5404 WARN_ON_ONCE(shadow_me_mask);
5406 for (i = 0; i < 4; ++i)
5407 mmu->pae_root[i] = INVALID_PAE_ROOT;
5412 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5416 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5417 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5419 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5420 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5422 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5424 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5425 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5427 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5429 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5433 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5435 goto fail_allocate_root;
5439 free_mmu_pages(&vcpu->arch.guest_mmu);
5443 #define BATCH_ZAP_PAGES 10
5444 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5446 struct kvm_mmu_page *sp, *node;
5447 int nr_zapped, batch = 0;
5450 list_for_each_entry_safe_reverse(sp, node,
5451 &kvm->arch.active_mmu_pages, link) {
5453 * No obsolete valid page exists before a newly created page
5454 * since active_mmu_pages is a FIFO list.
5456 if (!is_obsolete_sp(kvm, sp))
5460 * Invalid pages should never land back on the list of active
5461 * pages. Skip the bogus page, otherwise we'll get stuck in an
5462 * infinite loop if the page gets put back on the list (again).
5464 if (WARN_ON(sp->role.invalid))
5468 * No need to flush the TLB since we're only zapping shadow
5469 * pages with an obsolete generation number and all vCPUS have
5470 * loaded a new root, i.e. the shadow pages being zapped cannot
5471 * be in active use by the guest.
5473 if (batch >= BATCH_ZAP_PAGES &&
5474 cond_resched_rwlock_write(&kvm->mmu_lock)) {
5479 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5480 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5487 * Trigger a remote TLB flush before freeing the page tables to ensure
5488 * KVM is not in the middle of a lockless shadow page table walk, which
5489 * may reference the pages.
5491 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5495 * Fast invalidate all shadow pages and use lock-break technique
5496 * to zap obsolete pages.
5498 * It's required when memslot is being deleted or VM is being
5499 * destroyed, in these cases, we should ensure that KVM MMU does
5500 * not use any resource of the being-deleted slot or all slots
5501 * after calling the function.
5503 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5505 lockdep_assert_held(&kvm->slots_lock);
5507 write_lock(&kvm->mmu_lock);
5508 trace_kvm_mmu_zap_all_fast(kvm);
5511 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5512 * held for the entire duration of zapping obsolete pages, it's
5513 * impossible for there to be multiple invalid generations associated
5514 * with *valid* shadow pages at any given time, i.e. there is exactly
5515 * one valid generation and (at most) one invalid generation.
5517 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5519 /* In order to ensure all threads see this change when
5520 * handling the MMU reload signal, this must happen in the
5521 * same critical section as kvm_reload_remote_mmus, and
5522 * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages
5523 * could drop the MMU lock and yield.
5525 if (is_tdp_mmu_enabled(kvm))
5526 kvm_tdp_mmu_invalidate_all_roots(kvm);
5529 * Notify all vcpus to reload its shadow page table and flush TLB.
5530 * Then all vcpus will switch to new shadow page table with the new
5533 * Note: we need to do this under the protection of mmu_lock,
5534 * otherwise, vcpu would purge shadow page but miss tlb flush.
5536 kvm_reload_remote_mmus(kvm);
5538 kvm_zap_obsolete_pages(kvm);
5540 write_unlock(&kvm->mmu_lock);
5542 if (is_tdp_mmu_enabled(kvm)) {
5543 read_lock(&kvm->mmu_lock);
5544 kvm_tdp_mmu_zap_invalidated_roots(kvm);
5545 read_unlock(&kvm->mmu_lock);
5549 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5551 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5554 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5555 struct kvm_memory_slot *slot,
5556 struct kvm_page_track_notifier_node *node)
5558 kvm_mmu_zap_all_fast(kvm);
5561 void kvm_mmu_init_vm(struct kvm *kvm)
5563 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5565 if (!kvm_mmu_init_tdp_mmu(kvm))
5567 * No smp_load/store wrappers needed here as we are in
5568 * VM init and there cannot be any memslots / other threads
5569 * accessing this struct kvm yet.
5571 kvm->arch.memslots_have_rmaps = true;
5573 node->track_write = kvm_mmu_pte_write;
5574 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5575 kvm_page_track_register_notifier(kvm, node);
5578 void kvm_mmu_uninit_vm(struct kvm *kvm)
5580 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5582 kvm_page_track_unregister_notifier(kvm, node);
5584 kvm_mmu_uninit_tdp_mmu(kvm);
5587 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5589 struct kvm_memslots *slots;
5590 struct kvm_memory_slot *memslot;
5594 if (kvm_memslots_have_rmaps(kvm)) {
5595 write_lock(&kvm->mmu_lock);
5596 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5597 slots = __kvm_memslots(kvm, i);
5598 kvm_for_each_memslot(memslot, slots) {
5601 start = max(gfn_start, memslot->base_gfn);
5602 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5606 flush = slot_handle_level_range(kvm, memslot,
5607 kvm_zap_rmapp, PG_LEVEL_4K,
5608 KVM_MAX_HUGEPAGE_LEVEL, start,
5609 end - 1, true, flush);
5613 kvm_flush_remote_tlbs_with_address(kvm, gfn_start, gfn_end);
5614 write_unlock(&kvm->mmu_lock);
5617 if (is_tdp_mmu_enabled(kvm)) {
5620 read_lock(&kvm->mmu_lock);
5621 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++)
5622 flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start,
5623 gfn_end, flush, true);
5625 kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
5628 read_unlock(&kvm->mmu_lock);
5632 static bool slot_rmap_write_protect(struct kvm *kvm,
5633 struct kvm_rmap_head *rmap_head,
5634 struct kvm_memory_slot *slot)
5636 return __rmap_write_protect(kvm, rmap_head, false);
5639 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5640 struct kvm_memory_slot *memslot,
5645 if (kvm_memslots_have_rmaps(kvm)) {
5646 write_lock(&kvm->mmu_lock);
5647 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5648 start_level, KVM_MAX_HUGEPAGE_LEVEL,
5650 write_unlock(&kvm->mmu_lock);
5653 if (is_tdp_mmu_enabled(kvm)) {
5654 read_lock(&kvm->mmu_lock);
5655 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level);
5656 read_unlock(&kvm->mmu_lock);
5660 * We can flush all the TLBs out of the mmu lock without TLB
5661 * corruption since we just change the spte from writable to
5662 * readonly so that we only need to care the case of changing
5663 * spte from present to present (changing the spte from present
5664 * to nonpresent will flush all the TLBs immediately), in other
5665 * words, the only case we care is mmu_spte_update() where we
5666 * have checked Host-writable | MMU-writable instead of
5667 * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK
5671 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5674 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5675 struct kvm_rmap_head *rmap_head,
5676 struct kvm_memory_slot *slot)
5679 struct rmap_iterator iter;
5680 int need_tlb_flush = 0;
5682 struct kvm_mmu_page *sp;
5685 for_each_rmap_spte(rmap_head, &iter, sptep) {
5686 sp = sptep_to_sp(sptep);
5687 pfn = spte_to_pfn(*sptep);
5690 * We cannot do huge page mapping for indirect shadow pages,
5691 * which are found on the last rmap (level = 1) when not using
5692 * tdp; such shadow pages are synced with the page table in
5693 * the guest, and the guest page table is using 4K page size
5694 * mapping if the indirect sp has level = 1.
5696 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5697 sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn,
5698 pfn, PG_LEVEL_NUM)) {
5699 pte_list_remove(rmap_head, sptep);
5701 if (kvm_available_flush_tlb_with_range())
5702 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5703 KVM_PAGES_PER_HPAGE(sp->role.level));
5711 return need_tlb_flush;
5714 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5715 const struct kvm_memory_slot *memslot)
5717 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5718 struct kvm_memory_slot *slot = (struct kvm_memory_slot *)memslot;
5721 if (kvm_memslots_have_rmaps(kvm)) {
5722 write_lock(&kvm->mmu_lock);
5723 flush = slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true);
5725 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5726 write_unlock(&kvm->mmu_lock);
5729 if (is_tdp_mmu_enabled(kvm)) {
5730 read_lock(&kvm->mmu_lock);
5731 flush = kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot, flush);
5733 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5734 read_unlock(&kvm->mmu_lock);
5738 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5739 const struct kvm_memory_slot *memslot)
5742 * All current use cases for flushing the TLBs for a specific memslot
5743 * related to dirty logging, and many do the TLB flush out of mmu_lock.
5744 * The interaction between the various operations on memslot must be
5745 * serialized by slots_locks to ensure the TLB flush from one operation
5746 * is observed by any other operation on the same memslot.
5748 lockdep_assert_held(&kvm->slots_lock);
5749 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5753 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5754 struct kvm_memory_slot *memslot)
5758 if (kvm_memslots_have_rmaps(kvm)) {
5759 write_lock(&kvm->mmu_lock);
5760 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty,
5762 write_unlock(&kvm->mmu_lock);
5765 if (is_tdp_mmu_enabled(kvm)) {
5766 read_lock(&kvm->mmu_lock);
5767 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5768 read_unlock(&kvm->mmu_lock);
5772 * It's also safe to flush TLBs out of mmu lock here as currently this
5773 * function is only used for dirty logging, in which case flushing TLB
5774 * out of mmu lock also guarantees no dirty pages will be lost in
5778 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5781 void kvm_mmu_zap_all(struct kvm *kvm)
5783 struct kvm_mmu_page *sp, *node;
5784 LIST_HEAD(invalid_list);
5787 write_lock(&kvm->mmu_lock);
5789 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5790 if (WARN_ON(sp->role.invalid))
5792 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5794 if (cond_resched_rwlock_write(&kvm->mmu_lock))
5798 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5800 if (is_tdp_mmu_enabled(kvm))
5801 kvm_tdp_mmu_zap_all(kvm);
5803 write_unlock(&kvm->mmu_lock);
5806 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5808 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5810 gen &= MMIO_SPTE_GEN_MASK;
5813 * Generation numbers are incremented in multiples of the number of
5814 * address spaces in order to provide unique generations across all
5815 * address spaces. Strip what is effectively the address space
5816 * modifier prior to checking for a wrap of the MMIO generation so
5817 * that a wrap in any address space is detected.
5819 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5822 * The very rare case: if the MMIO generation number has wrapped,
5823 * zap all shadow pages.
5825 if (unlikely(gen == 0)) {
5826 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5827 kvm_mmu_zap_all_fast(kvm);
5831 static unsigned long
5832 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5835 int nr_to_scan = sc->nr_to_scan;
5836 unsigned long freed = 0;
5838 mutex_lock(&kvm_lock);
5840 list_for_each_entry(kvm, &vm_list, vm_list) {
5842 LIST_HEAD(invalid_list);
5845 * Never scan more than sc->nr_to_scan VM instances.
5846 * Will not hit this condition practically since we do not try
5847 * to shrink more than one VM and it is very unlikely to see
5848 * !n_used_mmu_pages so many times.
5853 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5854 * here. We may skip a VM instance errorneosly, but we do not
5855 * want to shrink a VM that only started to populate its MMU
5858 if (!kvm->arch.n_used_mmu_pages &&
5859 !kvm_has_zapped_obsolete_pages(kvm))
5862 idx = srcu_read_lock(&kvm->srcu);
5863 write_lock(&kvm->mmu_lock);
5865 if (kvm_has_zapped_obsolete_pages(kvm)) {
5866 kvm_mmu_commit_zap_page(kvm,
5867 &kvm->arch.zapped_obsolete_pages);
5871 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
5874 write_unlock(&kvm->mmu_lock);
5875 srcu_read_unlock(&kvm->srcu, idx);
5878 * unfair on small ones
5879 * per-vm shrinkers cry out
5880 * sadness comes quickly
5882 list_move_tail(&kvm->vm_list, &vm_list);
5886 mutex_unlock(&kvm_lock);
5890 static unsigned long
5891 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5893 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5896 static struct shrinker mmu_shrinker = {
5897 .count_objects = mmu_shrink_count,
5898 .scan_objects = mmu_shrink_scan,
5899 .seeks = DEFAULT_SEEKS * 10,
5902 static void mmu_destroy_caches(void)
5904 kmem_cache_destroy(pte_list_desc_cache);
5905 kmem_cache_destroy(mmu_page_header_cache);
5908 static bool get_nx_auto_mode(void)
5910 /* Return true when CPU has the bug, and mitigations are ON */
5911 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5914 static void __set_nx_huge_pages(bool val)
5916 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5919 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5921 bool old_val = nx_huge_pages;
5924 /* In "auto" mode deploy workaround only if CPU has the bug. */
5925 if (sysfs_streq(val, "off"))
5927 else if (sysfs_streq(val, "force"))
5929 else if (sysfs_streq(val, "auto"))
5930 new_val = get_nx_auto_mode();
5931 else if (strtobool(val, &new_val) < 0)
5934 __set_nx_huge_pages(new_val);
5936 if (new_val != old_val) {
5939 mutex_lock(&kvm_lock);
5941 list_for_each_entry(kvm, &vm_list, vm_list) {
5942 mutex_lock(&kvm->slots_lock);
5943 kvm_mmu_zap_all_fast(kvm);
5944 mutex_unlock(&kvm->slots_lock);
5946 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5948 mutex_unlock(&kvm_lock);
5954 int kvm_mmu_module_init(void)
5958 if (nx_huge_pages == -1)
5959 __set_nx_huge_pages(get_nx_auto_mode());
5962 * MMU roles use union aliasing which is, generally speaking, an
5963 * undefined behavior. However, we supposedly know how compilers behave
5964 * and the current status quo is unlikely to change. Guardians below are
5965 * supposed to let us know if the assumption becomes false.
5967 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
5968 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
5969 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
5971 kvm_mmu_reset_all_pte_masks();
5973 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5974 sizeof(struct pte_list_desc),
5975 0, SLAB_ACCOUNT, NULL);
5976 if (!pte_list_desc_cache)
5979 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5980 sizeof(struct kvm_mmu_page),
5981 0, SLAB_ACCOUNT, NULL);
5982 if (!mmu_page_header_cache)
5985 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5988 ret = register_shrinker(&mmu_shrinker);
5995 mmu_destroy_caches();
6000 * Calculate mmu pages needed for kvm.
6002 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
6004 unsigned long nr_mmu_pages;
6005 unsigned long nr_pages = 0;
6006 struct kvm_memslots *slots;
6007 struct kvm_memory_slot *memslot;
6010 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6011 slots = __kvm_memslots(kvm, i);
6013 kvm_for_each_memslot(memslot, slots)
6014 nr_pages += memslot->npages;
6017 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
6018 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
6020 return nr_mmu_pages;
6023 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6025 kvm_mmu_unload(vcpu);
6026 free_mmu_pages(&vcpu->arch.root_mmu);
6027 free_mmu_pages(&vcpu->arch.guest_mmu);
6028 mmu_free_memory_caches(vcpu);
6031 void kvm_mmu_module_exit(void)
6033 mmu_destroy_caches();
6034 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6035 unregister_shrinker(&mmu_shrinker);
6036 mmu_audit_disable();
6039 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
6041 unsigned int old_val;
6044 old_val = nx_huge_pages_recovery_ratio;
6045 err = param_set_uint(val, kp);
6049 if (READ_ONCE(nx_huge_pages) &&
6050 !old_val && nx_huge_pages_recovery_ratio) {
6053 mutex_lock(&kvm_lock);
6055 list_for_each_entry(kvm, &vm_list, vm_list)
6056 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6058 mutex_unlock(&kvm_lock);
6064 static void kvm_recover_nx_lpages(struct kvm *kvm)
6066 unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits;
6068 struct kvm_mmu_page *sp;
6070 LIST_HEAD(invalid_list);
6074 rcu_idx = srcu_read_lock(&kvm->srcu);
6075 write_lock(&kvm->mmu_lock);
6077 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6078 to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0;
6079 for ( ; to_zap; --to_zap) {
6080 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
6084 * We use a separate list instead of just using active_mmu_pages
6085 * because the number of lpage_disallowed pages is expected to
6086 * be relatively small compared to the total.
6088 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6089 struct kvm_mmu_page,
6090 lpage_disallowed_link);
6091 WARN_ON_ONCE(!sp->lpage_disallowed);
6092 if (is_tdp_mmu_page(sp)) {
6093 flush |= kvm_tdp_mmu_zap_sp(kvm, sp);
6095 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6096 WARN_ON_ONCE(sp->lpage_disallowed);
6099 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
6100 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6101 cond_resched_rwlock_write(&kvm->mmu_lock);
6105 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6107 write_unlock(&kvm->mmu_lock);
6108 srcu_read_unlock(&kvm->srcu, rcu_idx);
6111 static long get_nx_lpage_recovery_timeout(u64 start_time)
6113 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6114 ? start_time + 60 * HZ - get_jiffies_64()
6115 : MAX_SCHEDULE_TIMEOUT;
6118 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6121 long remaining_time;
6124 start_time = get_jiffies_64();
6125 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6127 set_current_state(TASK_INTERRUPTIBLE);
6128 while (!kthread_should_stop() && remaining_time > 0) {
6129 schedule_timeout(remaining_time);
6130 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6131 set_current_state(TASK_INTERRUPTIBLE);
6134 set_current_state(TASK_RUNNING);
6136 if (kthread_should_stop())
6139 kvm_recover_nx_lpages(kvm);
6143 int kvm_mmu_post_init_vm(struct kvm *kvm)
6147 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6148 "kvm-nx-lpage-recovery",
6149 &kvm->arch.nx_lpage_recovery_thread);
6151 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6156 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6158 if (kvm->arch.nx_lpage_recovery_thread)
6159 kthread_stop(kvm->arch.nx_lpage_recovery_thread);