1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "kvm_cache_regs.h"
24 #include <linux/kvm_host.h>
25 #include <linux/types.h>
26 #include <linux/string.h>
28 #include <linux/highmem.h>
29 #include <linux/moduleparam.h>
30 #include <linux/export.h>
31 #include <linux/swap.h>
32 #include <linux/hugetlb.h>
33 #include <linux/compiler.h>
34 #include <linux/srcu.h>
35 #include <linux/slab.h>
36 #include <linux/sched/signal.h>
37 #include <linux/uaccess.h>
38 #include <linux/hash.h>
39 #include <linux/kern_levels.h>
40 #include <linux/kthread.h>
44 #include <asm/cmpxchg.h>
45 #include <asm/e820/api.h>
48 #include <asm/kvm_page_track.h>
51 extern bool itlb_multihit_kvm_mitigation;
53 static int __read_mostly nx_huge_pages = -1;
54 #ifdef CONFIG_PREEMPT_RT
55 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
56 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
58 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
61 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
62 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
64 static struct kernel_param_ops nx_huge_pages_ops = {
65 .set = set_nx_huge_pages,
66 .get = param_get_bool,
69 static struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
70 .set = set_nx_huge_pages_recovery_ratio,
71 .get = param_get_uint,
74 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
75 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
76 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
77 &nx_huge_pages_recovery_ratio, 0644);
78 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
81 * When setting this variable to true it enables Two-Dimensional-Paging
82 * where the hardware walks 2 page tables:
83 * 1. the guest-virtual to guest-physical
84 * 2. while doing 1. it walks guest-physical to host-physical
85 * If the hardware supports that we don't need to do shadow paging.
87 bool tdp_enabled = false;
91 AUDIT_POST_PAGE_FAULT,
102 module_param(dbg, bool, 0644);
104 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
105 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
106 #define MMU_WARN_ON(x) WARN_ON(x)
108 #define pgprintk(x...) do { } while (0)
109 #define rmap_printk(x...) do { } while (0)
110 #define MMU_WARN_ON(x) do { } while (0)
113 #define PTE_PREFETCH_NUM 8
115 #define PT_FIRST_AVAIL_BITS_SHIFT 10
116 #define PT64_SECOND_AVAIL_BITS_SHIFT 54
119 * The mask used to denote special SPTEs, which can be either MMIO SPTEs or
120 * Access Tracking SPTEs.
122 #define SPTE_SPECIAL_MASK (3ULL << 52)
123 #define SPTE_AD_ENABLED_MASK (0ULL << 52)
124 #define SPTE_AD_DISABLED_MASK (1ULL << 52)
125 #define SPTE_AD_WRPROT_ONLY_MASK (2ULL << 52)
126 #define SPTE_MMIO_MASK (3ULL << 52)
128 #define PT64_LEVEL_BITS 9
130 #define PT64_LEVEL_SHIFT(level) \
131 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
133 #define PT64_INDEX(address, level)\
134 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
137 #define PT32_LEVEL_BITS 10
139 #define PT32_LEVEL_SHIFT(level) \
140 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
142 #define PT32_LVL_OFFSET_MASK(level) \
143 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
144 * PT32_LEVEL_BITS))) - 1))
146 #define PT32_INDEX(address, level)\
147 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
150 #ifdef CONFIG_DYNAMIC_PHYSICAL_MASK
151 #define PT64_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1))
153 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
155 #define PT64_LVL_ADDR_MASK(level) \
156 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
157 * PT64_LEVEL_BITS))) - 1))
158 #define PT64_LVL_OFFSET_MASK(level) \
159 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
160 * PT64_LEVEL_BITS))) - 1))
162 #define PT32_BASE_ADDR_MASK PAGE_MASK
163 #define PT32_DIR_BASE_ADDR_MASK \
164 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
165 #define PT32_LVL_ADDR_MASK(level) \
166 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
167 * PT32_LEVEL_BITS))) - 1))
169 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
170 | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
172 #define ACC_EXEC_MASK 1
173 #define ACC_WRITE_MASK PT_WRITABLE_MASK
174 #define ACC_USER_MASK PT_USER_MASK
175 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
177 /* The mask for the R/X bits in EPT PTEs */
178 #define PT64_EPT_READABLE_MASK 0x1ull
179 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
181 #include <trace/events/kvm.h>
183 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
184 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
186 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
188 /* make pte_list_desc fit well in cache line */
189 #define PTE_LIST_EXT 3
192 * Return values of handle_mmio_page_fault and mmu.page_fault:
193 * RET_PF_RETRY: let CPU fault again on the address.
194 * RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
196 * For handle_mmio_page_fault only:
197 * RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
205 struct pte_list_desc {
206 u64 *sptes[PTE_LIST_EXT];
207 struct pte_list_desc *more;
210 struct kvm_shadow_walk_iterator {
218 static const union kvm_mmu_page_role mmu_base_role_mask = {
220 .gpte_is_8_bytes = 1,
229 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
230 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
232 shadow_walk_okay(&(_walker)); \
233 shadow_walk_next(&(_walker)))
235 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
236 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
237 shadow_walk_okay(&(_walker)); \
238 shadow_walk_next(&(_walker)))
240 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
241 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
242 shadow_walk_okay(&(_walker)) && \
243 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
244 __shadow_walk_next(&(_walker), spte))
246 static struct kmem_cache *pte_list_desc_cache;
247 static struct kmem_cache *mmu_page_header_cache;
248 static struct percpu_counter kvm_total_used_mmu_pages;
250 static u64 __read_mostly shadow_nx_mask;
251 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
252 static u64 __read_mostly shadow_user_mask;
253 static u64 __read_mostly shadow_accessed_mask;
254 static u64 __read_mostly shadow_dirty_mask;
255 static u64 __read_mostly shadow_mmio_mask;
256 static u64 __read_mostly shadow_mmio_value;
257 static u64 __read_mostly shadow_mmio_access_mask;
258 static u64 __read_mostly shadow_present_mask;
259 static u64 __read_mostly shadow_me_mask;
262 * SPTEs used by MMUs without A/D bits are marked with SPTE_AD_DISABLED_MASK;
263 * shadow_acc_track_mask is the set of bits to be cleared in non-accessed
266 static u64 __read_mostly shadow_acc_track_mask;
269 * The mask/shift to use for saving the original R/X bits when marking the PTE
270 * as not-present for access tracking purposes. We do not save the W bit as the
271 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
272 * restored only when a write is attempted to the page.
274 static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
275 PT64_EPT_EXECUTABLE_MASK;
276 static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
279 * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order
280 * to guard against L1TF attacks.
282 static u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
285 * The number of high-order 1 bits to use in the mask above.
287 static const u64 shadow_nonpresent_or_rsvd_mask_len = 5;
290 * In some cases, we need to preserve the GFN of a non-present or reserved
291 * SPTE when we usurp the upper five bits of the physical address space to
292 * defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll
293 * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask
294 * left into the reserved bits, i.e. the GFN in the SPTE will be split into
295 * high and low parts. This mask covers the lower bits of the GFN.
297 static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
300 * The number of non-reserved physical address bits irrespective of features
301 * that repurpose legal bits, e.g. MKTME.
303 static u8 __read_mostly shadow_phys_bits;
305 static void mmu_spte_set(u64 *sptep, u64 spte);
306 static bool is_executable_pte(u64 spte);
307 static union kvm_mmu_page_role
308 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
310 #define CREATE_TRACE_POINTS
311 #include "mmutrace.h"
314 static inline bool kvm_available_flush_tlb_with_range(void)
316 return kvm_x86_ops->tlb_remote_flush_with_range;
319 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
320 struct kvm_tlb_range *range)
324 if (range && kvm_x86_ops->tlb_remote_flush_with_range)
325 ret = kvm_x86_ops->tlb_remote_flush_with_range(kvm, range);
328 kvm_flush_remote_tlbs(kvm);
331 static void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
332 u64 start_gfn, u64 pages)
334 struct kvm_tlb_range range;
336 range.start_gfn = start_gfn;
339 kvm_flush_remote_tlbs_with_range(kvm, &range);
342 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value, u64 access_mask)
344 BUG_ON((u64)(unsigned)access_mask != access_mask);
345 BUG_ON((mmio_mask & mmio_value) != mmio_value);
346 shadow_mmio_value = mmio_value | SPTE_MMIO_MASK;
347 shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK;
348 shadow_mmio_access_mask = access_mask;
350 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
352 static bool is_mmio_spte(u64 spte)
354 return (spte & shadow_mmio_mask) == shadow_mmio_value;
357 static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
359 return sp->role.ad_disabled;
362 static inline bool kvm_vcpu_ad_need_write_protect(struct kvm_vcpu *vcpu)
365 * When using the EPT page-modification log, the GPAs in the log
366 * would come from L2 rather than L1. Therefore, we need to rely
367 * on write protection to record dirty pages. This also bypasses
368 * PML, since writes now result in a vmexit.
370 return vcpu->arch.mmu == &vcpu->arch.guest_mmu;
373 static inline bool spte_ad_enabled(u64 spte)
375 MMU_WARN_ON(is_mmio_spte(spte));
376 return (spte & SPTE_SPECIAL_MASK) != SPTE_AD_DISABLED_MASK;
379 static inline bool spte_ad_need_write_protect(u64 spte)
381 MMU_WARN_ON(is_mmio_spte(spte));
382 return (spte & SPTE_SPECIAL_MASK) != SPTE_AD_ENABLED_MASK;
385 static bool is_nx_huge_page_enabled(void)
387 return READ_ONCE(nx_huge_pages);
390 static inline u64 spte_shadow_accessed_mask(u64 spte)
392 MMU_WARN_ON(is_mmio_spte(spte));
393 return spte_ad_enabled(spte) ? shadow_accessed_mask : 0;
396 static inline u64 spte_shadow_dirty_mask(u64 spte)
398 MMU_WARN_ON(is_mmio_spte(spte));
399 return spte_ad_enabled(spte) ? shadow_dirty_mask : 0;
402 static inline bool is_access_track_spte(u64 spte)
404 return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0;
408 * Due to limited space in PTEs, the MMIO generation is a 19 bit subset of
409 * the memslots generation and is derived as follows:
411 * Bits 0-8 of the MMIO generation are propagated to spte bits 3-11
412 * Bits 9-18 of the MMIO generation are propagated to spte bits 52-61
414 * The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not included in
415 * the MMIO generation number, as doing so would require stealing a bit from
416 * the "real" generation number and thus effectively halve the maximum number
417 * of MMIO generations that can be handled before encountering a wrap (which
418 * requires a full MMU zap). The flag is instead explicitly queried when
419 * checking for MMIO spte cache hits.
421 #define MMIO_SPTE_GEN_MASK GENMASK_ULL(18, 0)
423 #define MMIO_SPTE_GEN_LOW_START 3
424 #define MMIO_SPTE_GEN_LOW_END 11
425 #define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \
426 MMIO_SPTE_GEN_LOW_START)
428 #define MMIO_SPTE_GEN_HIGH_START 52
429 #define MMIO_SPTE_GEN_HIGH_END 61
430 #define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \
431 MMIO_SPTE_GEN_HIGH_START)
432 static u64 generation_mmio_spte_mask(u64 gen)
436 WARN_ON(gen & ~MMIO_SPTE_GEN_MASK);
438 mask = (gen << MMIO_SPTE_GEN_LOW_START) & MMIO_SPTE_GEN_LOW_MASK;
439 mask |= (gen << MMIO_SPTE_GEN_HIGH_START) & MMIO_SPTE_GEN_HIGH_MASK;
443 static u64 get_mmio_spte_generation(u64 spte)
447 spte &= ~shadow_mmio_mask;
449 gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_START;
450 gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_START;
454 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
457 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK;
458 u64 mask = generation_mmio_spte_mask(gen);
459 u64 gpa = gfn << PAGE_SHIFT;
461 access &= shadow_mmio_access_mask;
462 mask |= shadow_mmio_value | access;
463 mask |= gpa | shadow_nonpresent_or_rsvd_mask;
464 mask |= (gpa & shadow_nonpresent_or_rsvd_mask)
465 << shadow_nonpresent_or_rsvd_mask_len;
467 trace_mark_mmio_spte(sptep, gfn, access, gen);
468 mmu_spte_set(sptep, mask);
471 static gfn_t get_mmio_spte_gfn(u64 spte)
473 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
475 gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len)
476 & shadow_nonpresent_or_rsvd_mask;
478 return gpa >> PAGE_SHIFT;
481 static unsigned get_mmio_spte_access(u64 spte)
483 return spte & shadow_mmio_access_mask;
486 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
487 kvm_pfn_t pfn, unsigned access)
489 if (unlikely(is_noslot_pfn(pfn))) {
490 mark_mmio_spte(vcpu, sptep, gfn, access);
497 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
499 u64 kvm_gen, spte_gen, gen;
501 gen = kvm_vcpu_memslots(vcpu)->generation;
502 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
505 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
506 spte_gen = get_mmio_spte_generation(spte);
508 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
509 return likely(kvm_gen == spte_gen);
513 * Sets the shadow PTE masks used by the MMU.
516 * - Setting either @accessed_mask or @dirty_mask requires setting both
517 * - At least one of @accessed_mask or @acc_track_mask must be set
519 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
520 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
521 u64 acc_track_mask, u64 me_mask)
523 BUG_ON(!dirty_mask != !accessed_mask);
524 BUG_ON(!accessed_mask && !acc_track_mask);
525 BUG_ON(acc_track_mask & SPTE_SPECIAL_MASK);
527 shadow_user_mask = user_mask;
528 shadow_accessed_mask = accessed_mask;
529 shadow_dirty_mask = dirty_mask;
530 shadow_nx_mask = nx_mask;
531 shadow_x_mask = x_mask;
532 shadow_present_mask = p_mask;
533 shadow_acc_track_mask = acc_track_mask;
534 shadow_me_mask = me_mask;
536 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
538 static u8 kvm_get_shadow_phys_bits(void)
541 * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected
542 * in CPU detection code, but the processor treats those reduced bits as
543 * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at
544 * the physical address bits reported by CPUID.
546 if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008))
547 return cpuid_eax(0x80000008) & 0xff;
550 * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with
551 * custom CPUID. Proceed with whatever the kernel found since these features
552 * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008).
554 return boot_cpu_data.x86_phys_bits;
557 static void kvm_mmu_reset_all_pte_masks(void)
561 shadow_user_mask = 0;
562 shadow_accessed_mask = 0;
563 shadow_dirty_mask = 0;
566 shadow_mmio_mask = 0;
567 shadow_present_mask = 0;
568 shadow_acc_track_mask = 0;
570 shadow_phys_bits = kvm_get_shadow_phys_bits();
573 * If the CPU has 46 or less physical address bits, then set an
574 * appropriate mask to guard against L1TF attacks. Otherwise, it is
575 * assumed that the CPU is not vulnerable to L1TF.
577 * Some Intel CPUs address the L1 cache using more PA bits than are
578 * reported by CPUID. Use the PA width of the L1 cache when possible
579 * to achieve more effective mitigation, e.g. if system RAM overlaps
580 * the most significant bits of legal physical address space.
582 shadow_nonpresent_or_rsvd_mask = 0;
583 low_phys_bits = boot_cpu_data.x86_cache_bits;
584 if (boot_cpu_data.x86_cache_bits <
585 52 - shadow_nonpresent_or_rsvd_mask_len) {
586 shadow_nonpresent_or_rsvd_mask =
587 rsvd_bits(boot_cpu_data.x86_cache_bits -
588 shadow_nonpresent_or_rsvd_mask_len,
589 boot_cpu_data.x86_cache_bits - 1);
590 low_phys_bits -= shadow_nonpresent_or_rsvd_mask_len;
592 WARN_ON_ONCE(boot_cpu_has_bug(X86_BUG_L1TF));
594 shadow_nonpresent_or_rsvd_lower_gfn_mask =
595 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);
598 static int is_cpuid_PSE36(void)
603 static int is_nx(struct kvm_vcpu *vcpu)
605 return vcpu->arch.efer & EFER_NX;
608 static int is_shadow_present_pte(u64 pte)
610 return (pte != 0) && !is_mmio_spte(pte);
613 static int is_large_pte(u64 pte)
615 return pte & PT_PAGE_SIZE_MASK;
618 static int is_last_spte(u64 pte, int level)
620 if (level == PT_PAGE_TABLE_LEVEL)
622 if (is_large_pte(pte))
627 static bool is_executable_pte(u64 spte)
629 return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
632 static kvm_pfn_t spte_to_pfn(u64 pte)
634 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
637 static gfn_t pse36_gfn_delta(u32 gpte)
639 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
641 return (gpte & PT32_DIR_PSE36_MASK) << shift;
645 static void __set_spte(u64 *sptep, u64 spte)
647 WRITE_ONCE(*sptep, spte);
650 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
652 WRITE_ONCE(*sptep, spte);
655 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
657 return xchg(sptep, spte);
660 static u64 __get_spte_lockless(u64 *sptep)
662 return READ_ONCE(*sptep);
673 static void count_spte_clear(u64 *sptep, u64 spte)
675 struct kvm_mmu_page *sp = page_header(__pa(sptep));
677 if (is_shadow_present_pte(spte))
680 /* Ensure the spte is completely set before we increase the count */
682 sp->clear_spte_count++;
685 static void __set_spte(u64 *sptep, u64 spte)
687 union split_spte *ssptep, sspte;
689 ssptep = (union split_spte *)sptep;
690 sspte = (union split_spte)spte;
692 ssptep->spte_high = sspte.spte_high;
695 * If we map the spte from nonpresent to present, We should store
696 * the high bits firstly, then set present bit, so cpu can not
697 * fetch this spte while we are setting the spte.
701 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
704 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
706 union split_spte *ssptep, sspte;
708 ssptep = (union split_spte *)sptep;
709 sspte = (union split_spte)spte;
711 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
714 * If we map the spte from present to nonpresent, we should clear
715 * present bit firstly to avoid vcpu fetch the old high bits.
719 ssptep->spte_high = sspte.spte_high;
720 count_spte_clear(sptep, spte);
723 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
725 union split_spte *ssptep, sspte, orig;
727 ssptep = (union split_spte *)sptep;
728 sspte = (union split_spte)spte;
730 /* xchg acts as a barrier before the setting of the high bits */
731 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
732 orig.spte_high = ssptep->spte_high;
733 ssptep->spte_high = sspte.spte_high;
734 count_spte_clear(sptep, spte);
740 * The idea using the light way get the spte on x86_32 guest is from
741 * gup_get_pte (mm/gup.c).
743 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
744 * coalesces them and we are running out of the MMU lock. Therefore
745 * we need to protect against in-progress updates of the spte.
747 * Reading the spte while an update is in progress may get the old value
748 * for the high part of the spte. The race is fine for a present->non-present
749 * change (because the high part of the spte is ignored for non-present spte),
750 * but for a present->present change we must reread the spte.
752 * All such changes are done in two steps (present->non-present and
753 * non-present->present), hence it is enough to count the number of
754 * present->non-present updates: if it changed while reading the spte,
755 * we might have hit the race. This is done using clear_spte_count.
757 static u64 __get_spte_lockless(u64 *sptep)
759 struct kvm_mmu_page *sp = page_header(__pa(sptep));
760 union split_spte spte, *orig = (union split_spte *)sptep;
764 count = sp->clear_spte_count;
767 spte.spte_low = orig->spte_low;
770 spte.spte_high = orig->spte_high;
773 if (unlikely(spte.spte_low != orig->spte_low ||
774 count != sp->clear_spte_count))
781 static bool spte_can_locklessly_be_made_writable(u64 spte)
783 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
784 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
787 static bool spte_has_volatile_bits(u64 spte)
789 if (!is_shadow_present_pte(spte))
793 * Always atomically update spte if it can be updated
794 * out of mmu-lock, it can ensure dirty bit is not lost,
795 * also, it can help us to get a stable is_writable_pte()
796 * to ensure tlb flush is not missed.
798 if (spte_can_locklessly_be_made_writable(spte) ||
799 is_access_track_spte(spte))
802 if (spte_ad_enabled(spte)) {
803 if ((spte & shadow_accessed_mask) == 0 ||
804 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
811 static bool is_accessed_spte(u64 spte)
813 u64 accessed_mask = spte_shadow_accessed_mask(spte);
815 return accessed_mask ? spte & accessed_mask
816 : !is_access_track_spte(spte);
819 static bool is_dirty_spte(u64 spte)
821 u64 dirty_mask = spte_shadow_dirty_mask(spte);
823 return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK;
826 /* Rules for using mmu_spte_set:
827 * Set the sptep from nonpresent to present.
828 * Note: the sptep being assigned *must* be either not present
829 * or in a state where the hardware will not attempt to update
832 static void mmu_spte_set(u64 *sptep, u64 new_spte)
834 WARN_ON(is_shadow_present_pte(*sptep));
835 __set_spte(sptep, new_spte);
839 * Update the SPTE (excluding the PFN), but do not track changes in its
840 * accessed/dirty status.
842 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
844 u64 old_spte = *sptep;
846 WARN_ON(!is_shadow_present_pte(new_spte));
848 if (!is_shadow_present_pte(old_spte)) {
849 mmu_spte_set(sptep, new_spte);
853 if (!spte_has_volatile_bits(old_spte))
854 __update_clear_spte_fast(sptep, new_spte);
856 old_spte = __update_clear_spte_slow(sptep, new_spte);
858 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
863 /* Rules for using mmu_spte_update:
864 * Update the state bits, it means the mapped pfn is not changed.
866 * Whenever we overwrite a writable spte with a read-only one we
867 * should flush remote TLBs. Otherwise rmap_write_protect
868 * will find a read-only spte, even though the writable spte
869 * might be cached on a CPU's TLB, the return value indicates this
872 * Returns true if the TLB needs to be flushed
874 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
877 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
879 if (!is_shadow_present_pte(old_spte))
883 * For the spte updated out of mmu-lock is safe, since
884 * we always atomically update it, see the comments in
885 * spte_has_volatile_bits().
887 if (spte_can_locklessly_be_made_writable(old_spte) &&
888 !is_writable_pte(new_spte))
892 * Flush TLB when accessed/dirty states are changed in the page tables,
893 * to guarantee consistency between TLB and page tables.
896 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
898 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
901 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
903 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
910 * Rules for using mmu_spte_clear_track_bits:
911 * It sets the sptep from present to nonpresent, and track the
912 * state bits, it is used to clear the last level sptep.
913 * Returns non-zero if the PTE was previously valid.
915 static int mmu_spte_clear_track_bits(u64 *sptep)
918 u64 old_spte = *sptep;
920 if (!spte_has_volatile_bits(old_spte))
921 __update_clear_spte_fast(sptep, 0ull);
923 old_spte = __update_clear_spte_slow(sptep, 0ull);
925 if (!is_shadow_present_pte(old_spte))
928 pfn = spte_to_pfn(old_spte);
931 * KVM does not hold the refcount of the page used by
932 * kvm mmu, before reclaiming the page, we should
933 * unmap it from mmu first.
935 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
937 if (is_accessed_spte(old_spte))
938 kvm_set_pfn_accessed(pfn);
940 if (is_dirty_spte(old_spte))
941 kvm_set_pfn_dirty(pfn);
947 * Rules for using mmu_spte_clear_no_track:
948 * Directly clear spte without caring the state bits of sptep,
949 * it is used to set the upper level spte.
951 static void mmu_spte_clear_no_track(u64 *sptep)
953 __update_clear_spte_fast(sptep, 0ull);
956 static u64 mmu_spte_get_lockless(u64 *sptep)
958 return __get_spte_lockless(sptep);
961 static u64 mark_spte_for_access_track(u64 spte)
963 if (spte_ad_enabled(spte))
964 return spte & ~shadow_accessed_mask;
966 if (is_access_track_spte(spte))
970 * Making an Access Tracking PTE will result in removal of write access
971 * from the PTE. So, verify that we will be able to restore the write
972 * access in the fast page fault path later on.
974 WARN_ONCE((spte & PT_WRITABLE_MASK) &&
975 !spte_can_locklessly_be_made_writable(spte),
976 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
978 WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
979 shadow_acc_track_saved_bits_shift),
980 "kvm: Access Tracking saved bit locations are not zero\n");
982 spte |= (spte & shadow_acc_track_saved_bits_mask) <<
983 shadow_acc_track_saved_bits_shift;
984 spte &= ~shadow_acc_track_mask;
989 /* Restore an acc-track PTE back to a regular PTE */
990 static u64 restore_acc_track_spte(u64 spte)
993 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
994 & shadow_acc_track_saved_bits_mask;
996 WARN_ON_ONCE(spte_ad_enabled(spte));
997 WARN_ON_ONCE(!is_access_track_spte(spte));
999 new_spte &= ~shadow_acc_track_mask;
1000 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
1001 shadow_acc_track_saved_bits_shift);
1002 new_spte |= saved_bits;
1007 /* Returns the Accessed status of the PTE and resets it at the same time. */
1008 static bool mmu_spte_age(u64 *sptep)
1010 u64 spte = mmu_spte_get_lockless(sptep);
1012 if (!is_accessed_spte(spte))
1015 if (spte_ad_enabled(spte)) {
1016 clear_bit((ffs(shadow_accessed_mask) - 1),
1017 (unsigned long *)sptep);
1020 * Capture the dirty status of the page, so that it doesn't get
1021 * lost when the SPTE is marked for access tracking.
1023 if (is_writable_pte(spte))
1024 kvm_set_pfn_dirty(spte_to_pfn(spte));
1026 spte = mark_spte_for_access_track(spte);
1027 mmu_spte_update_no_track(sptep, spte);
1033 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
1036 * Prevent page table teardown by making any free-er wait during
1037 * kvm_flush_remote_tlbs() IPI to all active vcpus.
1039 local_irq_disable();
1042 * Make sure a following spte read is not reordered ahead of the write
1045 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
1048 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
1051 * Make sure the write to vcpu->mode is not reordered in front of
1052 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
1053 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
1055 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
1059 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
1060 struct kmem_cache *base_cache, int min)
1064 if (cache->nobjs >= min)
1066 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
1067 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL_ACCOUNT);
1069 return cache->nobjs >= min ? 0 : -ENOMEM;
1070 cache->objects[cache->nobjs++] = obj;
1075 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
1077 return cache->nobjs;
1080 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
1081 struct kmem_cache *cache)
1084 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
1087 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
1092 if (cache->nobjs >= min)
1094 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
1095 page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT);
1097 return cache->nobjs >= min ? 0 : -ENOMEM;
1098 cache->objects[cache->nobjs++] = page;
1103 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
1106 free_page((unsigned long)mc->objects[--mc->nobjs]);
1109 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
1113 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
1114 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
1117 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
1120 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
1121 mmu_page_header_cache, 4);
1126 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
1128 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
1129 pte_list_desc_cache);
1130 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
1131 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
1132 mmu_page_header_cache);
1135 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
1140 p = mc->objects[--mc->nobjs];
1144 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
1146 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
1149 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
1151 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
1154 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
1156 if (!sp->role.direct)
1157 return sp->gfns[index];
1159 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
1162 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
1164 if (!sp->role.direct) {
1165 sp->gfns[index] = gfn;
1169 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
1170 pr_err_ratelimited("gfn mismatch under direct page %llx "
1171 "(expected %llx, got %llx)\n",
1173 kvm_mmu_page_get_gfn(sp, index), gfn);
1177 * Return the pointer to the large page information for a given gfn,
1178 * handling slots that are not large page aligned.
1180 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
1181 struct kvm_memory_slot *slot,
1186 idx = gfn_to_index(gfn, slot->base_gfn, level);
1187 return &slot->arch.lpage_info[level - 2][idx];
1190 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
1191 gfn_t gfn, int count)
1193 struct kvm_lpage_info *linfo;
1196 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1197 linfo = lpage_info_slot(gfn, slot, i);
1198 linfo->disallow_lpage += count;
1199 WARN_ON(linfo->disallow_lpage < 0);
1203 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1205 update_gfn_disallow_lpage_count(slot, gfn, 1);
1208 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1210 update_gfn_disallow_lpage_count(slot, gfn, -1);
1213 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1215 struct kvm_memslots *slots;
1216 struct kvm_memory_slot *slot;
1219 kvm->arch.indirect_shadow_pages++;
1221 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1222 slot = __gfn_to_memslot(slots, gfn);
1224 /* the non-leaf shadow pages are keeping readonly. */
1225 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1226 return kvm_slot_page_track_add_page(kvm, slot, gfn,
1227 KVM_PAGE_TRACK_WRITE);
1229 kvm_mmu_gfn_disallow_lpage(slot, gfn);
1232 static void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1234 if (sp->lpage_disallowed)
1237 ++kvm->stat.nx_lpage_splits;
1238 list_add_tail(&sp->lpage_disallowed_link,
1239 &kvm->arch.lpage_disallowed_mmu_pages);
1240 sp->lpage_disallowed = true;
1243 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1245 struct kvm_memslots *slots;
1246 struct kvm_memory_slot *slot;
1249 kvm->arch.indirect_shadow_pages--;
1251 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1252 slot = __gfn_to_memslot(slots, gfn);
1253 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1254 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
1255 KVM_PAGE_TRACK_WRITE);
1257 kvm_mmu_gfn_allow_lpage(slot, gfn);
1260 static void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1262 --kvm->stat.nx_lpage_splits;
1263 sp->lpage_disallowed = false;
1264 list_del(&sp->lpage_disallowed_link);
1267 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
1268 struct kvm_memory_slot *slot)
1270 struct kvm_lpage_info *linfo;
1273 linfo = lpage_info_slot(gfn, slot, level);
1274 return !!linfo->disallow_lpage;
1280 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
1283 struct kvm_memory_slot *slot;
1285 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1286 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
1289 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
1291 unsigned long page_size;
1294 page_size = kvm_host_page_size(kvm, gfn);
1296 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1297 if (page_size >= KVM_HPAGE_SIZE(i))
1306 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
1309 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
1311 if (no_dirty_log && slot->dirty_bitmap)
1317 static struct kvm_memory_slot *
1318 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
1321 struct kvm_memory_slot *slot;
1323 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1324 if (!memslot_valid_for_gpte(slot, no_dirty_log))
1330 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
1333 int host_level, max_level = *max_levelp;
1334 struct kvm_memory_slot *slot;
1336 if (unlikely(max_level == PT_PAGE_TABLE_LEVEL))
1337 return PT_PAGE_TABLE_LEVEL;
1339 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
1340 if (!memslot_valid_for_gpte(slot, true)) {
1341 *max_levelp = PT_PAGE_TABLE_LEVEL;
1342 return PT_PAGE_TABLE_LEVEL;
1345 host_level = host_mapping_level(vcpu->kvm, large_gfn);
1347 if (host_level == PT_PAGE_TABLE_LEVEL)
1350 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
1351 for ( ; max_level > PT_PAGE_TABLE_LEVEL; max_level--) {
1352 if (!__mmu_gfn_lpage_is_disallowed(large_gfn, max_level, slot))
1360 * About rmap_head encoding:
1362 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1363 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1364 * pte_list_desc containing more mappings.
1368 * Returns the number of pointers in the rmap chain, not counting the new one.
1370 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
1371 struct kvm_rmap_head *rmap_head)
1373 struct pte_list_desc *desc;
1376 if (!rmap_head->val) {
1377 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
1378 rmap_head->val = (unsigned long)spte;
1379 } else if (!(rmap_head->val & 1)) {
1380 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
1381 desc = mmu_alloc_pte_list_desc(vcpu);
1382 desc->sptes[0] = (u64 *)rmap_head->val;
1383 desc->sptes[1] = spte;
1384 rmap_head->val = (unsigned long)desc | 1;
1387 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
1388 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1389 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
1391 count += PTE_LIST_EXT;
1393 if (desc->sptes[PTE_LIST_EXT-1]) {
1394 desc->more = mmu_alloc_pte_list_desc(vcpu);
1397 for (i = 0; desc->sptes[i]; ++i)
1399 desc->sptes[i] = spte;
1405 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
1406 struct pte_list_desc *desc, int i,
1407 struct pte_list_desc *prev_desc)
1411 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
1413 desc->sptes[i] = desc->sptes[j];
1414 desc->sptes[j] = NULL;
1417 if (!prev_desc && !desc->more)
1421 prev_desc->more = desc->more;
1423 rmap_head->val = (unsigned long)desc->more | 1;
1424 mmu_free_pte_list_desc(desc);
1427 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1429 struct pte_list_desc *desc;
1430 struct pte_list_desc *prev_desc;
1433 if (!rmap_head->val) {
1434 pr_err("%s: %p 0->BUG\n", __func__, spte);
1436 } else if (!(rmap_head->val & 1)) {
1437 rmap_printk("%s: %p 1->0\n", __func__, spte);
1438 if ((u64 *)rmap_head->val != spte) {
1439 pr_err("%s: %p 1->BUG\n", __func__, spte);
1444 rmap_printk("%s: %p many->many\n", __func__, spte);
1445 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1448 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1449 if (desc->sptes[i] == spte) {
1450 pte_list_desc_remove_entry(rmap_head,
1451 desc, i, prev_desc);
1458 pr_err("%s: %p many->many\n", __func__, spte);
1463 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
1465 mmu_spte_clear_track_bits(sptep);
1466 __pte_list_remove(sptep, rmap_head);
1469 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1470 struct kvm_memory_slot *slot)
1474 idx = gfn_to_index(gfn, slot->base_gfn, level);
1475 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1478 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1479 struct kvm_mmu_page *sp)
1481 struct kvm_memslots *slots;
1482 struct kvm_memory_slot *slot;
1484 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1485 slot = __gfn_to_memslot(slots, gfn);
1486 return __gfn_to_rmap(gfn, sp->role.level, slot);
1489 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1491 struct kvm_mmu_memory_cache *cache;
1493 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1494 return mmu_memory_cache_free_objects(cache);
1497 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1499 struct kvm_mmu_page *sp;
1500 struct kvm_rmap_head *rmap_head;
1502 sp = page_header(__pa(spte));
1503 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1504 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1505 return pte_list_add(vcpu, spte, rmap_head);
1508 static void rmap_remove(struct kvm *kvm, u64 *spte)
1510 struct kvm_mmu_page *sp;
1512 struct kvm_rmap_head *rmap_head;
1514 sp = page_header(__pa(spte));
1515 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1516 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1517 __pte_list_remove(spte, rmap_head);
1521 * Used by the following functions to iterate through the sptes linked by a
1522 * rmap. All fields are private and not assumed to be used outside.
1524 struct rmap_iterator {
1525 /* private fields */
1526 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1527 int pos; /* index of the sptep */
1531 * Iteration must be started by this function. This should also be used after
1532 * removing/dropping sptes from the rmap link because in such cases the
1533 * information in the iterator may not be valid.
1535 * Returns sptep if found, NULL otherwise.
1537 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1538 struct rmap_iterator *iter)
1542 if (!rmap_head->val)
1545 if (!(rmap_head->val & 1)) {
1547 sptep = (u64 *)rmap_head->val;
1551 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1553 sptep = iter->desc->sptes[iter->pos];
1555 BUG_ON(!is_shadow_present_pte(*sptep));
1560 * Must be used with a valid iterator: e.g. after rmap_get_first().
1562 * Returns sptep if found, NULL otherwise.
1564 static u64 *rmap_get_next(struct rmap_iterator *iter)
1569 if (iter->pos < PTE_LIST_EXT - 1) {
1571 sptep = iter->desc->sptes[iter->pos];
1576 iter->desc = iter->desc->more;
1580 /* desc->sptes[0] cannot be NULL */
1581 sptep = iter->desc->sptes[iter->pos];
1588 BUG_ON(!is_shadow_present_pte(*sptep));
1592 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1593 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1594 _spte_; _spte_ = rmap_get_next(_iter_))
1596 static void drop_spte(struct kvm *kvm, u64 *sptep)
1598 if (mmu_spte_clear_track_bits(sptep))
1599 rmap_remove(kvm, sptep);
1603 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1605 if (is_large_pte(*sptep)) {
1606 WARN_ON(page_header(__pa(sptep))->role.level ==
1607 PT_PAGE_TABLE_LEVEL);
1608 drop_spte(kvm, sptep);
1616 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1618 if (__drop_large_spte(vcpu->kvm, sptep)) {
1619 struct kvm_mmu_page *sp = page_header(__pa(sptep));
1621 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1622 KVM_PAGES_PER_HPAGE(sp->role.level));
1627 * Write-protect on the specified @sptep, @pt_protect indicates whether
1628 * spte write-protection is caused by protecting shadow page table.
1630 * Note: write protection is difference between dirty logging and spte
1632 * - for dirty logging, the spte can be set to writable at anytime if
1633 * its dirty bitmap is properly set.
1634 * - for spte protection, the spte can be writable only after unsync-ing
1637 * Return true if tlb need be flushed.
1639 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1643 if (!is_writable_pte(spte) &&
1644 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1647 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1650 spte &= ~SPTE_MMU_WRITEABLE;
1651 spte = spte & ~PT_WRITABLE_MASK;
1653 return mmu_spte_update(sptep, spte);
1656 static bool __rmap_write_protect(struct kvm *kvm,
1657 struct kvm_rmap_head *rmap_head,
1661 struct rmap_iterator iter;
1664 for_each_rmap_spte(rmap_head, &iter, sptep)
1665 flush |= spte_write_protect(sptep, pt_protect);
1670 static bool spte_clear_dirty(u64 *sptep)
1674 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1676 MMU_WARN_ON(!spte_ad_enabled(spte));
1677 spte &= ~shadow_dirty_mask;
1678 return mmu_spte_update(sptep, spte);
1681 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1683 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1684 (unsigned long *)sptep);
1685 if (was_writable && !spte_ad_enabled(*sptep))
1686 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1688 return was_writable;
1692 * Gets the GFN ready for another round of dirty logging by clearing the
1693 * - D bit on ad-enabled SPTEs, and
1694 * - W bit on ad-disabled SPTEs.
1695 * Returns true iff any D or W bits were cleared.
1697 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1700 struct rmap_iterator iter;
1703 for_each_rmap_spte(rmap_head, &iter, sptep)
1704 if (spte_ad_need_write_protect(*sptep))
1705 flush |= spte_wrprot_for_clear_dirty(sptep);
1707 flush |= spte_clear_dirty(sptep);
1712 static bool spte_set_dirty(u64 *sptep)
1716 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1719 * Similar to the !kvm_x86_ops->slot_disable_log_dirty case,
1720 * do not bother adding back write access to pages marked
1721 * SPTE_AD_WRPROT_ONLY_MASK.
1723 spte |= shadow_dirty_mask;
1725 return mmu_spte_update(sptep, spte);
1728 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1731 struct rmap_iterator iter;
1734 for_each_rmap_spte(rmap_head, &iter, sptep)
1735 if (spte_ad_enabled(*sptep))
1736 flush |= spte_set_dirty(sptep);
1742 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1743 * @kvm: kvm instance
1744 * @slot: slot to protect
1745 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1746 * @mask: indicates which pages we should protect
1748 * Used when we do not need to care about huge page mappings: e.g. during dirty
1749 * logging we do not have any such mappings.
1751 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1752 struct kvm_memory_slot *slot,
1753 gfn_t gfn_offset, unsigned long mask)
1755 struct kvm_rmap_head *rmap_head;
1758 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1759 PT_PAGE_TABLE_LEVEL, slot);
1760 __rmap_write_protect(kvm, rmap_head, false);
1762 /* clear the first set bit */
1768 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1769 * protect the page if the D-bit isn't supported.
1770 * @kvm: kvm instance
1771 * @slot: slot to clear D-bit
1772 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1773 * @mask: indicates which pages we should clear D-bit
1775 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1777 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1778 struct kvm_memory_slot *slot,
1779 gfn_t gfn_offset, unsigned long mask)
1781 struct kvm_rmap_head *rmap_head;
1784 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1785 PT_PAGE_TABLE_LEVEL, slot);
1786 __rmap_clear_dirty(kvm, rmap_head);
1788 /* clear the first set bit */
1792 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1795 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1798 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1799 * enable dirty logging for them.
1801 * Used when we do not need to care about huge page mappings: e.g. during dirty
1802 * logging we do not have any such mappings.
1804 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1805 struct kvm_memory_slot *slot,
1806 gfn_t gfn_offset, unsigned long mask)
1808 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1809 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1812 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1816 * kvm_arch_write_log_dirty - emulate dirty page logging
1817 * @vcpu: Guest mode vcpu
1819 * Emulate arch specific page modification logging for the
1822 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu)
1824 if (kvm_x86_ops->write_log_dirty)
1825 return kvm_x86_ops->write_log_dirty(vcpu);
1830 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1831 struct kvm_memory_slot *slot, u64 gfn)
1833 struct kvm_rmap_head *rmap_head;
1835 bool write_protected = false;
1837 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1838 rmap_head = __gfn_to_rmap(gfn, i, slot);
1839 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1842 return write_protected;
1845 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1847 struct kvm_memory_slot *slot;
1849 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1850 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1853 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1856 struct rmap_iterator iter;
1859 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1860 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1862 pte_list_remove(rmap_head, sptep);
1869 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1870 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1873 return kvm_zap_rmapp(kvm, rmap_head);
1876 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1877 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1881 struct rmap_iterator iter;
1884 pte_t *ptep = (pte_t *)data;
1887 WARN_ON(pte_huge(*ptep));
1888 new_pfn = pte_pfn(*ptep);
1891 for_each_rmap_spte(rmap_head, &iter, sptep) {
1892 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1893 sptep, *sptep, gfn, level);
1897 if (pte_write(*ptep)) {
1898 pte_list_remove(rmap_head, sptep);
1901 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1902 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1904 new_spte &= ~PT_WRITABLE_MASK;
1905 new_spte &= ~SPTE_HOST_WRITEABLE;
1907 new_spte = mark_spte_for_access_track(new_spte);
1909 mmu_spte_clear_track_bits(sptep);
1910 mmu_spte_set(sptep, new_spte);
1914 if (need_flush && kvm_available_flush_tlb_with_range()) {
1915 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1922 struct slot_rmap_walk_iterator {
1924 struct kvm_memory_slot *slot;
1930 /* output fields. */
1932 struct kvm_rmap_head *rmap;
1935 /* private field. */
1936 struct kvm_rmap_head *end_rmap;
1940 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1942 iterator->level = level;
1943 iterator->gfn = iterator->start_gfn;
1944 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1945 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1950 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1951 struct kvm_memory_slot *slot, int start_level,
1952 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1954 iterator->slot = slot;
1955 iterator->start_level = start_level;
1956 iterator->end_level = end_level;
1957 iterator->start_gfn = start_gfn;
1958 iterator->end_gfn = end_gfn;
1960 rmap_walk_init_level(iterator, iterator->start_level);
1963 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1965 return !!iterator->rmap;
1968 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1970 if (++iterator->rmap <= iterator->end_rmap) {
1971 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1975 if (++iterator->level > iterator->end_level) {
1976 iterator->rmap = NULL;
1980 rmap_walk_init_level(iterator, iterator->level);
1983 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1984 _start_gfn, _end_gfn, _iter_) \
1985 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1986 _end_level_, _start_gfn, _end_gfn); \
1987 slot_rmap_walk_okay(_iter_); \
1988 slot_rmap_walk_next(_iter_))
1990 static int kvm_handle_hva_range(struct kvm *kvm,
1991 unsigned long start,
1994 int (*handler)(struct kvm *kvm,
1995 struct kvm_rmap_head *rmap_head,
1996 struct kvm_memory_slot *slot,
1999 unsigned long data))
2001 struct kvm_memslots *slots;
2002 struct kvm_memory_slot *memslot;
2003 struct slot_rmap_walk_iterator iterator;
2007 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
2008 slots = __kvm_memslots(kvm, i);
2009 kvm_for_each_memslot(memslot, slots) {
2010 unsigned long hva_start, hva_end;
2011 gfn_t gfn_start, gfn_end;
2013 hva_start = max(start, memslot->userspace_addr);
2014 hva_end = min(end, memslot->userspace_addr +
2015 (memslot->npages << PAGE_SHIFT));
2016 if (hva_start >= hva_end)
2019 * {gfn(page) | page intersects with [hva_start, hva_end)} =
2020 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
2022 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
2023 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
2025 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
2026 PT_MAX_HUGEPAGE_LEVEL,
2027 gfn_start, gfn_end - 1,
2029 ret |= handler(kvm, iterator.rmap, memslot,
2030 iterator.gfn, iterator.level, data);
2037 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
2039 int (*handler)(struct kvm *kvm,
2040 struct kvm_rmap_head *rmap_head,
2041 struct kvm_memory_slot *slot,
2042 gfn_t gfn, int level,
2043 unsigned long data))
2045 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
2048 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
2050 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
2053 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
2055 return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
2058 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
2059 struct kvm_memory_slot *slot, gfn_t gfn, int level,
2063 struct rmap_iterator uninitialized_var(iter);
2066 for_each_rmap_spte(rmap_head, &iter, sptep)
2067 young |= mmu_spte_age(sptep);
2069 trace_kvm_age_page(gfn, level, slot, young);
2073 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
2074 struct kvm_memory_slot *slot, gfn_t gfn,
2075 int level, unsigned long data)
2078 struct rmap_iterator iter;
2080 for_each_rmap_spte(rmap_head, &iter, sptep)
2081 if (is_accessed_spte(*sptep))
2086 #define RMAP_RECYCLE_THRESHOLD 1000
2088 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
2090 struct kvm_rmap_head *rmap_head;
2091 struct kvm_mmu_page *sp;
2093 sp = page_header(__pa(spte));
2095 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
2097 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
2098 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
2099 KVM_PAGES_PER_HPAGE(sp->role.level));
2102 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
2104 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
2107 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
2109 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
2113 static int is_empty_shadow_page(u64 *spt)
2118 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
2119 if (is_shadow_present_pte(*pos)) {
2120 printk(KERN_ERR "%s: %p %llx\n", __func__,
2129 * This value is the sum of all of the kvm instances's
2130 * kvm->arch.n_used_mmu_pages values. We need a global,
2131 * aggregate version in order to make the slab shrinker
2134 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
2136 kvm->arch.n_used_mmu_pages += nr;
2137 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
2140 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
2142 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
2143 hlist_del(&sp->hash_link);
2144 list_del(&sp->link);
2145 free_page((unsigned long)sp->spt);
2146 if (!sp->role.direct)
2147 free_page((unsigned long)sp->gfns);
2148 kmem_cache_free(mmu_page_header_cache, sp);
2151 static unsigned kvm_page_table_hashfn(gfn_t gfn)
2153 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
2156 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
2157 struct kvm_mmu_page *sp, u64 *parent_pte)
2162 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
2165 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
2168 __pte_list_remove(parent_pte, &sp->parent_ptes);
2171 static void drop_parent_pte(struct kvm_mmu_page *sp,
2174 mmu_page_remove_parent_pte(sp, parent_pte);
2175 mmu_spte_clear_no_track(parent_pte);
2178 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
2180 struct kvm_mmu_page *sp;
2182 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
2183 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2185 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2186 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
2189 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
2190 * depends on valid pages being added to the head of the list. See
2191 * comments in kvm_zap_obsolete_pages().
2193 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2194 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
2195 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
2199 static void mark_unsync(u64 *spte);
2200 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
2203 struct rmap_iterator iter;
2205 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
2210 static void mark_unsync(u64 *spte)
2212 struct kvm_mmu_page *sp;
2215 sp = page_header(__pa(spte));
2216 index = spte - sp->spt;
2217 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
2219 if (sp->unsync_children++)
2221 kvm_mmu_mark_parents_unsync(sp);
2224 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
2225 struct kvm_mmu_page *sp)
2230 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root)
2234 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
2235 struct kvm_mmu_page *sp, u64 *spte,
2241 #define KVM_PAGE_ARRAY_NR 16
2243 struct kvm_mmu_pages {
2244 struct mmu_page_and_offset {
2245 struct kvm_mmu_page *sp;
2247 } page[KVM_PAGE_ARRAY_NR];
2251 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
2257 for (i=0; i < pvec->nr; i++)
2258 if (pvec->page[i].sp == sp)
2261 pvec->page[pvec->nr].sp = sp;
2262 pvec->page[pvec->nr].idx = idx;
2264 return (pvec->nr == KVM_PAGE_ARRAY_NR);
2267 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
2269 --sp->unsync_children;
2270 WARN_ON((int)sp->unsync_children < 0);
2271 __clear_bit(idx, sp->unsync_child_bitmap);
2274 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
2275 struct kvm_mmu_pages *pvec)
2277 int i, ret, nr_unsync_leaf = 0;
2279 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
2280 struct kvm_mmu_page *child;
2281 u64 ent = sp->spt[i];
2283 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
2284 clear_unsync_child_bit(sp, i);
2288 child = page_header(ent & PT64_BASE_ADDR_MASK);
2290 if (child->unsync_children) {
2291 if (mmu_pages_add(pvec, child, i))
2294 ret = __mmu_unsync_walk(child, pvec);
2296 clear_unsync_child_bit(sp, i);
2298 } else if (ret > 0) {
2299 nr_unsync_leaf += ret;
2302 } else if (child->unsync) {
2304 if (mmu_pages_add(pvec, child, i))
2307 clear_unsync_child_bit(sp, i);
2310 return nr_unsync_leaf;
2313 #define INVALID_INDEX (-1)
2315 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
2316 struct kvm_mmu_pages *pvec)
2319 if (!sp->unsync_children)
2322 mmu_pages_add(pvec, sp, INVALID_INDEX);
2323 return __mmu_unsync_walk(sp, pvec);
2326 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2328 WARN_ON(!sp->unsync);
2329 trace_kvm_mmu_sync_page(sp);
2331 --kvm->stat.mmu_unsync;
2334 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2335 struct list_head *invalid_list);
2336 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2337 struct list_head *invalid_list);
2340 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2341 hlist_for_each_entry(_sp, \
2342 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2343 if (is_obsolete_sp((_kvm), (_sp))) { \
2346 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2347 for_each_valid_sp(_kvm, _sp, _gfn) \
2348 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2350 static inline bool is_ept_sp(struct kvm_mmu_page *sp)
2352 return sp->role.cr0_wp && sp->role.smap_andnot_wp;
2355 /* @sp->gfn should be write-protected at the call site */
2356 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2357 struct list_head *invalid_list)
2359 if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) ||
2360 vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
2361 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2368 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
2369 struct list_head *invalid_list,
2372 if (!remote_flush && list_empty(invalid_list))
2375 if (!list_empty(invalid_list))
2376 kvm_mmu_commit_zap_page(kvm, invalid_list);
2378 kvm_flush_remote_tlbs(kvm);
2382 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
2383 struct list_head *invalid_list,
2384 bool remote_flush, bool local_flush)
2386 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
2390 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2393 #ifdef CONFIG_KVM_MMU_AUDIT
2394 #include "mmu_audit.c"
2396 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
2397 static void mmu_audit_disable(void) { }
2400 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2402 return sp->role.invalid ||
2403 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2406 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2407 struct list_head *invalid_list)
2409 kvm_unlink_unsync_page(vcpu->kvm, sp);
2410 return __kvm_sync_page(vcpu, sp, invalid_list);
2413 /* @gfn should be write-protected at the call site */
2414 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
2415 struct list_head *invalid_list)
2417 struct kvm_mmu_page *s;
2420 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2424 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2425 ret |= kvm_sync_page(vcpu, s, invalid_list);
2431 struct mmu_page_path {
2432 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
2433 unsigned int idx[PT64_ROOT_MAX_LEVEL];
2436 #define for_each_sp(pvec, sp, parents, i) \
2437 for (i = mmu_pages_first(&pvec, &parents); \
2438 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2439 i = mmu_pages_next(&pvec, &parents, i))
2441 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2442 struct mmu_page_path *parents,
2447 for (n = i+1; n < pvec->nr; n++) {
2448 struct kvm_mmu_page *sp = pvec->page[n].sp;
2449 unsigned idx = pvec->page[n].idx;
2450 int level = sp->role.level;
2452 parents->idx[level-1] = idx;
2453 if (level == PT_PAGE_TABLE_LEVEL)
2456 parents->parent[level-2] = sp;
2462 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2463 struct mmu_page_path *parents)
2465 struct kvm_mmu_page *sp;
2471 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2473 sp = pvec->page[0].sp;
2474 level = sp->role.level;
2475 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2477 parents->parent[level-2] = sp;
2479 /* Also set up a sentinel. Further entries in pvec are all
2480 * children of sp, so this element is never overwritten.
2482 parents->parent[level-1] = NULL;
2483 return mmu_pages_next(pvec, parents, 0);
2486 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2488 struct kvm_mmu_page *sp;
2489 unsigned int level = 0;
2492 unsigned int idx = parents->idx[level];
2493 sp = parents->parent[level];
2497 WARN_ON(idx == INVALID_INDEX);
2498 clear_unsync_child_bit(sp, idx);
2500 } while (!sp->unsync_children);
2503 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2504 struct kvm_mmu_page *parent)
2507 struct kvm_mmu_page *sp;
2508 struct mmu_page_path parents;
2509 struct kvm_mmu_pages pages;
2510 LIST_HEAD(invalid_list);
2513 while (mmu_unsync_walk(parent, &pages)) {
2514 bool protected = false;
2516 for_each_sp(pages, sp, parents, i)
2517 protected |= rmap_write_protect(vcpu, sp->gfn);
2520 kvm_flush_remote_tlbs(vcpu->kvm);
2524 for_each_sp(pages, sp, parents, i) {
2525 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2526 mmu_pages_clear_parents(&parents);
2528 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2529 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2530 cond_resched_lock(&vcpu->kvm->mmu_lock);
2535 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2538 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2540 atomic_set(&sp->write_flooding_count, 0);
2543 static void clear_sp_write_flooding_count(u64 *spte)
2545 struct kvm_mmu_page *sp = page_header(__pa(spte));
2547 __clear_sp_write_flooding_count(sp);
2550 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2557 union kvm_mmu_page_role role;
2559 struct kvm_mmu_page *sp;
2560 bool need_sync = false;
2563 LIST_HEAD(invalid_list);
2565 role = vcpu->arch.mmu->mmu_role.base;
2567 role.direct = direct;
2569 role.gpte_is_8_bytes = true;
2570 role.access = access;
2571 if (!vcpu->arch.mmu->direct_map
2572 && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2573 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2574 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2575 role.quadrant = quadrant;
2577 for_each_valid_sp(vcpu->kvm, sp, gfn) {
2578 if (sp->gfn != gfn) {
2583 if (!need_sync && sp->unsync)
2586 if (sp->role.word != role.word)
2590 /* The page is good, but __kvm_sync_page might still end
2591 * up zapping it. If so, break in order to rebuild it.
2593 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2596 WARN_ON(!list_empty(&invalid_list));
2597 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2600 if (sp->unsync_children)
2601 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2603 __clear_sp_write_flooding_count(sp);
2604 trace_kvm_mmu_get_page(sp, false);
2608 ++vcpu->kvm->stat.mmu_cache_miss;
2610 sp = kvm_mmu_alloc_page(vcpu, direct);
2614 hlist_add_head(&sp->hash_link,
2615 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2618 * we should do write protection before syncing pages
2619 * otherwise the content of the synced shadow page may
2620 * be inconsistent with guest page table.
2622 account_shadowed(vcpu->kvm, sp);
2623 if (level == PT_PAGE_TABLE_LEVEL &&
2624 rmap_write_protect(vcpu, gfn))
2625 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2627 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2628 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2630 clear_page(sp->spt);
2631 trace_kvm_mmu_get_page(sp, true);
2633 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2635 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2636 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2640 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2641 struct kvm_vcpu *vcpu, hpa_t root,
2644 iterator->addr = addr;
2645 iterator->shadow_addr = root;
2646 iterator->level = vcpu->arch.mmu->shadow_root_level;
2648 if (iterator->level == PT64_ROOT_4LEVEL &&
2649 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2650 !vcpu->arch.mmu->direct_map)
2653 if (iterator->level == PT32E_ROOT_LEVEL) {
2655 * prev_root is currently only used for 64-bit hosts. So only
2656 * the active root_hpa is valid here.
2658 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2660 iterator->shadow_addr
2661 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2662 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2664 if (!iterator->shadow_addr)
2665 iterator->level = 0;
2669 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2670 struct kvm_vcpu *vcpu, u64 addr)
2672 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2676 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2678 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2681 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2682 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2686 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2689 if (is_last_spte(spte, iterator->level)) {
2690 iterator->level = 0;
2694 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2698 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2700 __shadow_walk_next(iterator, *iterator->sptep);
2703 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2704 struct kvm_mmu_page *sp)
2708 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2710 spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2711 shadow_user_mask | shadow_x_mask | shadow_me_mask;
2713 if (sp_ad_disabled(sp))
2714 spte |= SPTE_AD_DISABLED_MASK;
2716 spte |= shadow_accessed_mask;
2718 mmu_spte_set(sptep, spte);
2720 mmu_page_add_parent_pte(vcpu, sp, sptep);
2722 if (sp->unsync_children || sp->unsync)
2726 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2727 unsigned direct_access)
2729 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2730 struct kvm_mmu_page *child;
2733 * For the direct sp, if the guest pte's dirty bit
2734 * changed form clean to dirty, it will corrupt the
2735 * sp's access: allow writable in the read-only sp,
2736 * so we should update the spte at this point to get
2737 * a new sp with the correct access.
2739 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2740 if (child->role.access == direct_access)
2743 drop_parent_pte(child, sptep);
2744 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2748 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2752 struct kvm_mmu_page *child;
2755 if (is_shadow_present_pte(pte)) {
2756 if (is_last_spte(pte, sp->role.level)) {
2757 drop_spte(kvm, spte);
2758 if (is_large_pte(pte))
2761 child = page_header(pte & PT64_BASE_ADDR_MASK);
2762 drop_parent_pte(child, spte);
2767 if (is_mmio_spte(pte))
2768 mmu_spte_clear_no_track(spte);
2773 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2774 struct kvm_mmu_page *sp)
2778 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2779 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2782 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2785 struct rmap_iterator iter;
2787 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2788 drop_parent_pte(sp, sptep);
2791 static int mmu_zap_unsync_children(struct kvm *kvm,
2792 struct kvm_mmu_page *parent,
2793 struct list_head *invalid_list)
2796 struct mmu_page_path parents;
2797 struct kvm_mmu_pages pages;
2799 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2802 while (mmu_unsync_walk(parent, &pages)) {
2803 struct kvm_mmu_page *sp;
2805 for_each_sp(pages, sp, parents, i) {
2806 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2807 mmu_pages_clear_parents(&parents);
2815 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2816 struct kvm_mmu_page *sp,
2817 struct list_head *invalid_list,
2822 trace_kvm_mmu_prepare_zap_page(sp);
2823 ++kvm->stat.mmu_shadow_zapped;
2824 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2825 kvm_mmu_page_unlink_children(kvm, sp);
2826 kvm_mmu_unlink_parents(kvm, sp);
2828 /* Zapping children means active_mmu_pages has become unstable. */
2829 list_unstable = *nr_zapped;
2831 if (!sp->role.invalid && !sp->role.direct)
2832 unaccount_shadowed(kvm, sp);
2835 kvm_unlink_unsync_page(kvm, sp);
2836 if (!sp->root_count) {
2839 list_move(&sp->link, invalid_list);
2840 kvm_mod_used_mmu_pages(kvm, -1);
2842 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2845 * Obsolete pages cannot be used on any vCPUs, see the comment
2846 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2847 * treats invalid shadow pages as being obsolete.
2849 if (!is_obsolete_sp(kvm, sp))
2850 kvm_reload_remote_mmus(kvm);
2853 if (sp->lpage_disallowed)
2854 unaccount_huge_nx_page(kvm, sp);
2856 sp->role.invalid = 1;
2857 return list_unstable;
2860 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2861 struct list_head *invalid_list)
2865 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2869 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2870 struct list_head *invalid_list)
2872 struct kvm_mmu_page *sp, *nsp;
2874 if (list_empty(invalid_list))
2878 * We need to make sure everyone sees our modifications to
2879 * the page tables and see changes to vcpu->mode here. The barrier
2880 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2881 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2883 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2884 * guest mode and/or lockless shadow page table walks.
2886 kvm_flush_remote_tlbs(kvm);
2888 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2889 WARN_ON(!sp->role.invalid || sp->root_count);
2890 kvm_mmu_free_page(sp);
2894 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2895 struct list_head *invalid_list)
2897 struct kvm_mmu_page *sp;
2899 if (list_empty(&kvm->arch.active_mmu_pages))
2902 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2903 struct kvm_mmu_page, link);
2904 return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2907 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2909 LIST_HEAD(invalid_list);
2911 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
2914 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
2915 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
2918 ++vcpu->kvm->stat.mmu_recycled;
2920 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2922 if (!kvm_mmu_available_pages(vcpu->kvm))
2928 * Changing the number of mmu pages allocated to the vm
2929 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2931 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2933 LIST_HEAD(invalid_list);
2935 spin_lock(&kvm->mmu_lock);
2937 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2938 /* Need to free some mmu pages to achieve the goal. */
2939 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2940 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2943 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2944 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2947 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2949 spin_unlock(&kvm->mmu_lock);
2952 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2954 struct kvm_mmu_page *sp;
2955 LIST_HEAD(invalid_list);
2958 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2960 spin_lock(&kvm->mmu_lock);
2961 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2962 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2965 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2967 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2968 spin_unlock(&kvm->mmu_lock);
2972 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2974 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2976 trace_kvm_mmu_unsync_page(sp);
2977 ++vcpu->kvm->stat.mmu_unsync;
2980 kvm_mmu_mark_parents_unsync(sp);
2983 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2986 struct kvm_mmu_page *sp;
2988 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2991 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2998 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2999 kvm_unsync_page(vcpu, sp);
3003 * We need to ensure that the marking of unsync pages is visible
3004 * before the SPTE is updated to allow writes because
3005 * kvm_mmu_sync_roots() checks the unsync flags without holding
3006 * the MMU lock and so can race with this. If the SPTE was updated
3007 * before the page had been marked as unsync-ed, something like the
3008 * following could happen:
3011 * ---------------------------------------------------------------------
3012 * 1.2 Host updates SPTE
3014 * 2.1 Guest writes a GPTE for GVA X.
3015 * (GPTE being in the guest page table shadowed
3016 * by the SP from CPU 1.)
3017 * This reads SPTE during the page table walk.
3018 * Since SPTE.W is read as 1, there is no
3021 * 2.2 Guest issues TLB flush.
3022 * That causes a VM Exit.
3024 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
3025 * Since it is false, so it just returns.
3027 * 2.4 Guest accesses GVA X.
3028 * Since the mapping in the SP was not updated,
3029 * so the old mapping for GVA X incorrectly
3033 * (sp->unsync = true)
3035 * The write barrier below ensures that 1.1 happens before 1.2 and thus
3036 * the situation in 2.4 does not arise. The implicit barrier in 2.2
3037 * pairs with this write barrier.
3044 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
3047 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) &&
3049 * Some reserved pages, such as those from NVDIMM
3050 * DAX devices, are not for MMIO, and can be mapped
3051 * with cached memory type for better performance.
3052 * However, the above check misconceives those pages
3053 * as MMIO, and results in KVM mapping them with UC
3054 * memory type, which would hurt the performance.
3055 * Therefore, we check the host memory type in addition
3056 * and only treat UC/UC-/WC pages as MMIO.
3058 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn));
3060 return !e820__mapped_raw_any(pfn_to_hpa(pfn),
3061 pfn_to_hpa(pfn + 1) - 1,
3065 /* Bits which may be returned by set_spte() */
3066 #define SET_SPTE_WRITE_PROTECTED_PT BIT(0)
3067 #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1)
3069 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
3070 unsigned pte_access, int level,
3071 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
3072 bool can_unsync, bool host_writable)
3076 struct kvm_mmu_page *sp;
3078 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
3081 sp = page_header(__pa(sptep));
3082 if (sp_ad_disabled(sp))
3083 spte |= SPTE_AD_DISABLED_MASK;
3084 else if (kvm_vcpu_ad_need_write_protect(vcpu))
3085 spte |= SPTE_AD_WRPROT_ONLY_MASK;
3088 * For the EPT case, shadow_present_mask is 0 if hardware
3089 * supports exec-only page table entries. In that case,
3090 * ACC_USER_MASK and shadow_user_mask are used to represent
3091 * read access. See FNAME(gpte_access) in paging_tmpl.h.
3093 spte |= shadow_present_mask;
3095 spte |= spte_shadow_accessed_mask(spte);
3097 if (level > PT_PAGE_TABLE_LEVEL && (pte_access & ACC_EXEC_MASK) &&
3098 is_nx_huge_page_enabled()) {
3099 pte_access &= ~ACC_EXEC_MASK;
3102 if (pte_access & ACC_EXEC_MASK)
3103 spte |= shadow_x_mask;
3105 spte |= shadow_nx_mask;
3107 if (pte_access & ACC_USER_MASK)
3108 spte |= shadow_user_mask;
3110 if (level > PT_PAGE_TABLE_LEVEL)
3111 spte |= PT_PAGE_SIZE_MASK;
3113 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
3114 kvm_is_mmio_pfn(pfn));
3117 spte |= SPTE_HOST_WRITEABLE;
3119 pte_access &= ~ACC_WRITE_MASK;
3121 if (!kvm_is_mmio_pfn(pfn))
3122 spte |= shadow_me_mask;
3124 spte |= (u64)pfn << PAGE_SHIFT;
3126 if (pte_access & ACC_WRITE_MASK) {
3129 * Other vcpu creates new sp in the window between
3130 * mapping_level() and acquiring mmu-lock. We can
3131 * allow guest to retry the access, the mapping can
3132 * be fixed if guest refault.
3134 if (level > PT_PAGE_TABLE_LEVEL &&
3135 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
3138 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
3141 * Optimization: for pte sync, if spte was writable the hash
3142 * lookup is unnecessary (and expensive). Write protection
3143 * is responsibility of mmu_get_page / kvm_sync_page.
3144 * Same reasoning can be applied to dirty page accounting.
3146 if (!can_unsync && is_writable_pte(*sptep))
3149 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
3150 pgprintk("%s: found shadow page for %llx, marking ro\n",
3152 ret |= SET_SPTE_WRITE_PROTECTED_PT;
3153 pte_access &= ~ACC_WRITE_MASK;
3154 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
3158 if (pte_access & ACC_WRITE_MASK) {
3159 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3160 spte |= spte_shadow_dirty_mask(spte);
3164 spte = mark_spte_for_access_track(spte);
3167 if (mmu_spte_update(sptep, spte))
3168 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
3173 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
3174 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
3175 bool speculative, bool host_writable)
3177 int was_rmapped = 0;
3180 int ret = RET_PF_RETRY;
3183 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
3184 *sptep, write_fault, gfn);
3186 if (is_shadow_present_pte(*sptep)) {
3188 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
3189 * the parent of the now unreachable PTE.
3191 if (level > PT_PAGE_TABLE_LEVEL &&
3192 !is_large_pte(*sptep)) {
3193 struct kvm_mmu_page *child;
3196 child = page_header(pte & PT64_BASE_ADDR_MASK);
3197 drop_parent_pte(child, sptep);
3199 } else if (pfn != spte_to_pfn(*sptep)) {
3200 pgprintk("hfn old %llx new %llx\n",
3201 spte_to_pfn(*sptep), pfn);
3202 drop_spte(vcpu->kvm, sptep);
3208 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
3209 speculative, true, host_writable);
3210 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
3212 ret = RET_PF_EMULATE;
3213 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3216 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
3217 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
3218 KVM_PAGES_PER_HPAGE(level));
3220 if (unlikely(is_mmio_spte(*sptep)))
3221 ret = RET_PF_EMULATE;
3223 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
3224 trace_kvm_mmu_set_spte(level, gfn, sptep);
3225 if (!was_rmapped && is_large_pte(*sptep))
3226 ++vcpu->kvm->stat.lpages;
3228 if (is_shadow_present_pte(*sptep)) {
3230 rmap_count = rmap_add(vcpu, sptep, gfn);
3231 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
3232 rmap_recycle(vcpu, sptep, gfn);
3239 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
3242 struct kvm_memory_slot *slot;
3244 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
3246 return KVM_PFN_ERR_FAULT;
3248 return gfn_to_pfn_memslot_atomic(slot, gfn);
3251 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
3252 struct kvm_mmu_page *sp,
3253 u64 *start, u64 *end)
3255 struct page *pages[PTE_PREFETCH_NUM];
3256 struct kvm_memory_slot *slot;
3257 unsigned access = sp->role.access;
3261 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
3262 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
3266 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
3270 for (i = 0; i < ret; i++, gfn++, start++) {
3271 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
3272 page_to_pfn(pages[i]), true, true);
3279 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
3280 struct kvm_mmu_page *sp, u64 *sptep)
3282 u64 *spte, *start = NULL;
3285 WARN_ON(!sp->role.direct);
3287 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
3290 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
3291 if (is_shadow_present_pte(*spte) || spte == sptep) {
3294 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
3302 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
3304 struct kvm_mmu_page *sp;
3306 sp = page_header(__pa(sptep));
3309 * Without accessed bits, there's no way to distinguish between
3310 * actually accessed translations and prefetched, so disable pte
3311 * prefetch if accessed bits aren't available.
3313 if (sp_ad_disabled(sp))
3316 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3319 __direct_pte_prefetch(vcpu, sp, sptep);
3322 static void disallowed_hugepage_adjust(struct kvm_shadow_walk_iterator it,
3323 gfn_t gfn, kvm_pfn_t *pfnp, int *levelp)
3325 int level = *levelp;
3326 u64 spte = *it.sptep;
3328 if (it.level == level && level > PT_PAGE_TABLE_LEVEL &&
3329 is_nx_huge_page_enabled() &&
3330 is_shadow_present_pte(spte) &&
3331 !is_large_pte(spte)) {
3333 * A small SPTE exists for this pfn, but FNAME(fetch)
3334 * and __direct_map would like to create a large PTE
3335 * instead: just force them to go down another level,
3336 * patching back for them into pfn the next 9 bits of
3339 u64 page_mask = KVM_PAGES_PER_HPAGE(level) - KVM_PAGES_PER_HPAGE(level - 1);
3340 *pfnp |= gfn & page_mask;
3345 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, int write,
3346 int map_writable, int level, kvm_pfn_t pfn,
3347 bool prefault, bool lpage_disallowed)
3349 struct kvm_shadow_walk_iterator it;
3350 struct kvm_mmu_page *sp;
3352 gfn_t gfn = gpa >> PAGE_SHIFT;
3353 gfn_t base_gfn = gfn;
3355 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3356 return RET_PF_RETRY;
3358 trace_kvm_mmu_spte_requested(gpa, level, pfn);
3359 for_each_shadow_entry(vcpu, gpa, it) {
3361 * We cannot overwrite existing page tables with an NX
3362 * large page, as the leaf could be executable.
3364 disallowed_hugepage_adjust(it, gfn, &pfn, &level);
3366 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
3367 if (it.level == level)
3370 drop_large_spte(vcpu, it.sptep);
3371 if (!is_shadow_present_pte(*it.sptep)) {
3372 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
3373 it.level - 1, true, ACC_ALL);
3375 link_shadow_page(vcpu, it.sptep, sp);
3376 if (lpage_disallowed)
3377 account_huge_nx_page(vcpu->kvm, sp);
3381 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
3382 write, level, base_gfn, pfn, prefault,
3384 direct_pte_prefetch(vcpu, it.sptep);
3385 ++vcpu->stat.pf_fixed;
3389 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
3391 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
3394 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
3397 * Do not cache the mmio info caused by writing the readonly gfn
3398 * into the spte otherwise read access on readonly gfn also can
3399 * caused mmio page fault and treat it as mmio access.
3401 if (pfn == KVM_PFN_ERR_RO_FAULT)
3402 return RET_PF_EMULATE;
3404 if (pfn == KVM_PFN_ERR_HWPOISON) {
3405 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3406 return RET_PF_RETRY;
3412 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
3413 gfn_t gfn, kvm_pfn_t *pfnp,
3416 kvm_pfn_t pfn = *pfnp;
3417 int level = *levelp;
3420 * Check if it's a transparent hugepage. If this would be an
3421 * hugetlbfs page, level wouldn't be set to
3422 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
3425 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
3426 !kvm_is_zone_device_pfn(pfn) && level == PT_PAGE_TABLE_LEVEL &&
3427 PageTransCompoundMap(pfn_to_page(pfn)) &&
3428 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
3431 * mmu_notifier_retry was successful and we hold the
3432 * mmu_lock here, so the pmd can't become splitting
3433 * from under us, and in turn
3434 * __split_huge_page_refcount() can't run from under
3435 * us and we can safely transfer the refcount from
3436 * PG_tail to PG_head as we switch the pfn to tail to
3439 *levelp = level = PT_DIRECTORY_LEVEL;
3440 mask = KVM_PAGES_PER_HPAGE(level) - 1;
3441 VM_BUG_ON((gfn & mask) != (pfn & mask));
3443 kvm_release_pfn_clean(pfn);
3451 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
3452 kvm_pfn_t pfn, unsigned access, int *ret_val)
3454 /* The pfn is invalid, report the error! */
3455 if (unlikely(is_error_pfn(pfn))) {
3456 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
3460 if (unlikely(is_noslot_pfn(pfn)))
3461 vcpu_cache_mmio_info(vcpu, gva, gfn,
3462 access & shadow_mmio_access_mask);
3467 static bool page_fault_can_be_fast(u32 error_code)
3470 * Do not fix the mmio spte with invalid generation number which
3471 * need to be updated by slow page fault path.
3473 if (unlikely(error_code & PFERR_RSVD_MASK))
3476 /* See if the page fault is due to an NX violation */
3477 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3478 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3482 * #PF can be fast if:
3483 * 1. The shadow page table entry is not present, which could mean that
3484 * the fault is potentially caused by access tracking (if enabled).
3485 * 2. The shadow page table entry is present and the fault
3486 * is caused by write-protect, that means we just need change the W
3487 * bit of the spte which can be done out of mmu-lock.
3489 * However, if access tracking is disabled we know that a non-present
3490 * page must be a genuine page fault where we have to create a new SPTE.
3491 * So, if access tracking is disabled, we return true only for write
3492 * accesses to a present page.
3495 return shadow_acc_track_mask != 0 ||
3496 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3497 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3501 * Returns true if the SPTE was fixed successfully. Otherwise,
3502 * someone else modified the SPTE from its original value.
3505 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3506 u64 *sptep, u64 old_spte, u64 new_spte)
3510 WARN_ON(!sp->role.direct);
3513 * Theoretically we could also set dirty bit (and flush TLB) here in
3514 * order to eliminate unnecessary PML logging. See comments in
3515 * set_spte. But fast_page_fault is very unlikely to happen with PML
3516 * enabled, so we do not do this. This might result in the same GPA
3517 * to be logged in PML buffer again when the write really happens, and
3518 * eventually to be called by mark_page_dirty twice. But it's also no
3519 * harm. This also avoids the TLB flush needed after setting dirty bit
3520 * so non-PML cases won't be impacted.
3522 * Compare with set_spte where instead shadow_dirty_mask is set.
3524 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3527 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3529 * The gfn of direct spte is stable since it is
3530 * calculated by sp->gfn.
3532 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3533 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3539 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3541 if (fault_err_code & PFERR_FETCH_MASK)
3542 return is_executable_pte(spte);
3544 if (fault_err_code & PFERR_WRITE_MASK)
3545 return is_writable_pte(spte);
3547 /* Fault was on Read access */
3548 return spte & PT_PRESENT_MASK;
3553 * - true: let the vcpu to access on the same address again.
3554 * - false: let the real page fault path to fix it.
3556 static bool fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, int level,
3559 struct kvm_shadow_walk_iterator iterator;
3560 struct kvm_mmu_page *sp;
3561 bool fault_handled = false;
3563 uint retry_count = 0;
3565 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3568 if (!page_fault_can_be_fast(error_code))
3571 walk_shadow_page_lockless_begin(vcpu);
3576 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3577 if (!is_shadow_present_pte(spte) ||
3578 iterator.level < level)
3581 sp = page_header(__pa(iterator.sptep));
3582 if (!is_last_spte(spte, sp->role.level))
3586 * Check whether the memory access that caused the fault would
3587 * still cause it if it were to be performed right now. If not,
3588 * then this is a spurious fault caused by TLB lazily flushed,
3589 * or some other CPU has already fixed the PTE after the
3590 * current CPU took the fault.
3592 * Need not check the access of upper level table entries since
3593 * they are always ACC_ALL.
3595 if (is_access_allowed(error_code, spte)) {
3596 fault_handled = true;
3602 if (is_access_track_spte(spte))
3603 new_spte = restore_acc_track_spte(new_spte);
3606 * Currently, to simplify the code, write-protection can
3607 * be removed in the fast path only if the SPTE was
3608 * write-protected for dirty-logging or access tracking.
3610 if ((error_code & PFERR_WRITE_MASK) &&
3611 spte_can_locklessly_be_made_writable(spte))
3613 new_spte |= PT_WRITABLE_MASK;
3616 * Do not fix write-permission on the large spte. Since
3617 * we only dirty the first page into the dirty-bitmap in
3618 * fast_pf_fix_direct_spte(), other pages are missed
3619 * if its slot has dirty logging enabled.
3621 * Instead, we let the slow page fault path create a
3622 * normal spte to fix the access.
3624 * See the comments in kvm_arch_commit_memory_region().
3626 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3630 /* Verify that the fault can be handled in the fast path */
3631 if (new_spte == spte ||
3632 !is_access_allowed(error_code, new_spte))
3636 * Currently, fast page fault only works for direct mapping
3637 * since the gfn is not stable for indirect shadow page. See
3638 * Documentation/virt/kvm/locking.txt to get more detail.
3640 fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
3641 iterator.sptep, spte,
3646 if (++retry_count > 4) {
3647 printk_once(KERN_WARNING
3648 "kvm: Fast #PF retrying more than 4 times.\n");
3654 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3655 spte, fault_handled);
3656 walk_shadow_page_lockless_end(vcpu);
3658 return fault_handled;
3661 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3662 struct list_head *invalid_list)
3664 struct kvm_mmu_page *sp;
3666 if (!VALID_PAGE(*root_hpa))
3669 sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK);
3671 if (!sp->root_count && sp->role.invalid)
3672 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3674 *root_hpa = INVALID_PAGE;
3677 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3678 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3679 ulong roots_to_free)
3682 LIST_HEAD(invalid_list);
3683 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3685 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3687 /* Before acquiring the MMU lock, see if we need to do any real work. */
3688 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3689 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3690 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3691 VALID_PAGE(mmu->prev_roots[i].hpa))
3694 if (i == KVM_MMU_NUM_PREV_ROOTS)
3698 spin_lock(&vcpu->kvm->mmu_lock);
3700 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3701 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3702 mmu_free_root_page(vcpu->kvm, &mmu->prev_roots[i].hpa,
3705 if (free_active_root) {
3706 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3707 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3708 mmu_free_root_page(vcpu->kvm, &mmu->root_hpa,
3711 for (i = 0; i < 4; ++i)
3712 if (mmu->pae_root[i] != 0)
3713 mmu_free_root_page(vcpu->kvm,
3716 mmu->root_hpa = INVALID_PAGE;
3721 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3722 spin_unlock(&vcpu->kvm->mmu_lock);
3724 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3726 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3730 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3731 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3738 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3740 struct kvm_mmu_page *sp;
3743 if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3744 spin_lock(&vcpu->kvm->mmu_lock);
3745 if(make_mmu_pages_available(vcpu) < 0) {
3746 spin_unlock(&vcpu->kvm->mmu_lock);
3749 sp = kvm_mmu_get_page(vcpu, 0, 0,
3750 vcpu->arch.mmu->shadow_root_level, 1, ACC_ALL);
3752 spin_unlock(&vcpu->kvm->mmu_lock);
3753 vcpu->arch.mmu->root_hpa = __pa(sp->spt);
3754 } else if (vcpu->arch.mmu->shadow_root_level == PT32E_ROOT_LEVEL) {
3755 for (i = 0; i < 4; ++i) {
3756 hpa_t root = vcpu->arch.mmu->pae_root[i];
3758 MMU_WARN_ON(VALID_PAGE(root));
3759 spin_lock(&vcpu->kvm->mmu_lock);
3760 if (make_mmu_pages_available(vcpu) < 0) {
3761 spin_unlock(&vcpu->kvm->mmu_lock);
3764 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3765 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3766 root = __pa(sp->spt);
3768 spin_unlock(&vcpu->kvm->mmu_lock);
3769 vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK;
3771 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3774 vcpu->arch.mmu->root_cr3 = vcpu->arch.mmu->get_cr3(vcpu);
3779 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3781 struct kvm_mmu_page *sp;
3783 gfn_t root_gfn, root_cr3;
3786 root_cr3 = vcpu->arch.mmu->get_cr3(vcpu);
3787 root_gfn = root_cr3 >> PAGE_SHIFT;
3789 if (mmu_check_root(vcpu, root_gfn))
3793 * Do we shadow a long mode page table? If so we need to
3794 * write-protect the guests page table root.
3796 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3797 hpa_t root = vcpu->arch.mmu->root_hpa;
3799 MMU_WARN_ON(VALID_PAGE(root));
3801 spin_lock(&vcpu->kvm->mmu_lock);
3802 if (make_mmu_pages_available(vcpu) < 0) {
3803 spin_unlock(&vcpu->kvm->mmu_lock);
3806 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
3807 vcpu->arch.mmu->shadow_root_level, 0, ACC_ALL);
3808 root = __pa(sp->spt);
3810 spin_unlock(&vcpu->kvm->mmu_lock);
3811 vcpu->arch.mmu->root_hpa = root;
3816 * We shadow a 32 bit page table. This may be a legacy 2-level
3817 * or a PAE 3-level page table. In either case we need to be aware that
3818 * the shadow page table may be a PAE or a long mode page table.
3820 pm_mask = PT_PRESENT_MASK;
3821 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3822 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3824 for (i = 0; i < 4; ++i) {
3825 hpa_t root = vcpu->arch.mmu->pae_root[i];
3827 MMU_WARN_ON(VALID_PAGE(root));
3828 if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) {
3829 pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i);
3830 if (!(pdptr & PT_PRESENT_MASK)) {
3831 vcpu->arch.mmu->pae_root[i] = 0;
3834 root_gfn = pdptr >> PAGE_SHIFT;
3835 if (mmu_check_root(vcpu, root_gfn))
3838 spin_lock(&vcpu->kvm->mmu_lock);
3839 if (make_mmu_pages_available(vcpu) < 0) {
3840 spin_unlock(&vcpu->kvm->mmu_lock);
3843 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3845 root = __pa(sp->spt);
3847 spin_unlock(&vcpu->kvm->mmu_lock);
3849 vcpu->arch.mmu->pae_root[i] = root | pm_mask;
3851 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3854 * If we shadow a 32 bit page table with a long mode page
3855 * table we enter this path.
3857 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3858 if (vcpu->arch.mmu->lm_root == NULL) {
3860 * The additional page necessary for this is only
3861 * allocated on demand.
3866 lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3867 if (lm_root == NULL)
3870 lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask;
3872 vcpu->arch.mmu->lm_root = lm_root;
3875 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root);
3879 vcpu->arch.mmu->root_cr3 = root_cr3;
3884 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3886 if (vcpu->arch.mmu->direct_map)
3887 return mmu_alloc_direct_roots(vcpu);
3889 return mmu_alloc_shadow_roots(vcpu);
3892 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3895 struct kvm_mmu_page *sp;
3897 if (vcpu->arch.mmu->direct_map)
3900 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3903 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3905 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3906 hpa_t root = vcpu->arch.mmu->root_hpa;
3907 sp = page_header(root);
3910 * Even if another CPU was marking the SP as unsync-ed
3911 * simultaneously, any guest page table changes are not
3912 * guaranteed to be visible anyway until this VCPU issues a TLB
3913 * flush strictly after those changes are made. We only need to
3914 * ensure that the other CPU sets these flags before any actual
3915 * changes to the page tables are made. The comments in
3916 * mmu_need_write_protect() describe what could go wrong if this
3917 * requirement isn't satisfied.
3919 if (!smp_load_acquire(&sp->unsync) &&
3920 !smp_load_acquire(&sp->unsync_children))
3923 spin_lock(&vcpu->kvm->mmu_lock);
3924 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3926 mmu_sync_children(vcpu, sp);
3928 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3929 spin_unlock(&vcpu->kvm->mmu_lock);
3933 spin_lock(&vcpu->kvm->mmu_lock);
3934 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3936 for (i = 0; i < 4; ++i) {
3937 hpa_t root = vcpu->arch.mmu->pae_root[i];
3939 if (root && VALID_PAGE(root)) {
3940 root &= PT64_BASE_ADDR_MASK;
3941 sp = page_header(root);
3942 mmu_sync_children(vcpu, sp);
3946 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3947 spin_unlock(&vcpu->kvm->mmu_lock);
3949 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3951 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3952 u32 access, struct x86_exception *exception)
3955 exception->error_code = 0;
3959 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3961 struct x86_exception *exception)
3964 exception->error_code = 0;
3965 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3969 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3971 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3973 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3974 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3977 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3979 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3982 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3984 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3987 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3990 * A nested guest cannot use the MMIO cache if it is using nested
3991 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3993 if (mmu_is_nested(vcpu))
3997 return vcpu_match_mmio_gpa(vcpu, addr);
3999 return vcpu_match_mmio_gva(vcpu, addr);
4002 /* return true if reserved bit is detected on spte. */
4004 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
4006 struct kvm_shadow_walk_iterator iterator;
4007 u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull;
4009 bool reserved = false;
4011 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
4014 walk_shadow_page_lockless_begin(vcpu);
4016 for (shadow_walk_init(&iterator, vcpu, addr),
4017 leaf = root = iterator.level;
4018 shadow_walk_okay(&iterator);
4019 __shadow_walk_next(&iterator, spte)) {
4020 spte = mmu_spte_get_lockless(iterator.sptep);
4022 sptes[leaf - 1] = spte;
4025 if (!is_shadow_present_pte(spte))
4028 reserved |= is_shadow_zero_bits_set(vcpu->arch.mmu, spte,
4032 walk_shadow_page_lockless_end(vcpu);
4035 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
4037 while (root > leaf) {
4038 pr_err("------ spte 0x%llx level %d.\n",
4039 sptes[root - 1], root);
4048 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
4053 if (mmio_info_in_cache(vcpu, addr, direct))
4054 return RET_PF_EMULATE;
4056 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
4057 if (WARN_ON(reserved))
4060 if (is_mmio_spte(spte)) {
4061 gfn_t gfn = get_mmio_spte_gfn(spte);
4062 unsigned access = get_mmio_spte_access(spte);
4064 if (!check_mmio_spte(vcpu, spte))
4065 return RET_PF_INVALID;
4070 trace_handle_mmio_page_fault(addr, gfn, access);
4071 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
4072 return RET_PF_EMULATE;
4076 * If the page table is zapped by other cpus, let CPU fault again on
4079 return RET_PF_RETRY;
4082 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
4083 u32 error_code, gfn_t gfn)
4085 if (unlikely(error_code & PFERR_RSVD_MASK))
4088 if (!(error_code & PFERR_PRESENT_MASK) ||
4089 !(error_code & PFERR_WRITE_MASK))
4093 * guest is writing the page which is write tracked which can
4094 * not be fixed by page fault handler.
4096 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
4102 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
4104 struct kvm_shadow_walk_iterator iterator;
4107 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
4110 walk_shadow_page_lockless_begin(vcpu);
4111 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4112 clear_sp_write_flooding_count(iterator.sptep);
4113 if (!is_shadow_present_pte(spte))
4116 walk_shadow_page_lockless_end(vcpu);
4119 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
4122 struct kvm_arch_async_pf arch;
4124 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
4126 arch.direct_map = vcpu->arch.mmu->direct_map;
4127 arch.cr3 = vcpu->arch.mmu->get_cr3(vcpu);
4129 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
4130 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
4133 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
4134 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, bool write,
4137 struct kvm_memory_slot *slot;
4141 * Don't expose private memslots to L2.
4143 if (is_guest_mode(vcpu) && !kvm_is_visible_gfn(vcpu->kvm, gfn)) {
4144 *pfn = KVM_PFN_NOSLOT;
4148 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
4150 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
4152 return false; /* *pfn has correct page already */
4154 if (!prefault && kvm_can_do_async_pf(vcpu)) {
4155 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
4156 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
4157 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
4158 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
4160 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
4164 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
4168 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
4169 u32 error_code, bool prefault)
4174 unsigned long mmu_seq;
4175 gfn_t gfn = gpa >> PAGE_SHIFT;
4176 bool write = error_code & PFERR_WRITE_MASK;
4178 bool exec = error_code & PFERR_FETCH_MASK;
4179 bool lpage_disallowed = exec && is_nx_huge_page_enabled();
4182 /* Note, paging is disabled, ergo gva == gpa. */
4183 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
4187 if (page_fault_handle_page_track(vcpu, error_code, gfn))
4188 return RET_PF_EMULATE;
4190 r = mmu_topup_memory_caches(vcpu);
4194 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa));
4196 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
4197 max_level = lpage_disallowed ? PT_PAGE_TABLE_LEVEL : PT_DIRECTORY_LEVEL;
4199 level = mapping_level(vcpu, gfn, &max_level);
4200 if (level > PT_PAGE_TABLE_LEVEL)
4201 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
4203 if (fast_page_fault(vcpu, gpa, level, error_code))
4204 return RET_PF_RETRY;
4206 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4209 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
4210 return RET_PF_RETRY;
4212 if (handle_abnormal_pfn(vcpu, gpa, gfn, pfn, ACC_ALL, &r))
4216 spin_lock(&vcpu->kvm->mmu_lock);
4217 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
4219 if (make_mmu_pages_available(vcpu) < 0)
4221 if (likely(max_level > PT_PAGE_TABLE_LEVEL))
4222 transparent_hugepage_adjust(vcpu, gfn, &pfn, &level);
4223 r = __direct_map(vcpu, gpa, write, map_writable, level, pfn,
4226 spin_unlock(&vcpu->kvm->mmu_lock);
4227 kvm_release_pfn_clean(pfn);
4231 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
4232 u64 fault_address, char *insn, int insn_len)
4236 #ifndef CONFIG_X86_64
4237 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
4238 if (WARN_ON_ONCE(fault_address >> 32))
4242 vcpu->arch.l1tf_flush_l1d = true;
4243 switch (vcpu->arch.apf.host_apf_reason) {
4245 trace_kvm_page_fault(fault_address, error_code);
4247 if (kvm_event_needs_reinjection(vcpu))
4248 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
4249 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
4252 case KVM_PV_REASON_PAGE_NOT_PRESENT:
4253 vcpu->arch.apf.host_apf_reason = 0;
4254 local_irq_disable();
4255 kvm_async_pf_task_wait(fault_address, 0);
4258 case KVM_PV_REASON_PAGE_READY:
4259 vcpu->arch.apf.host_apf_reason = 0;
4260 local_irq_disable();
4261 kvm_async_pf_task_wake(fault_address);
4267 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
4269 static int tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
4275 gfn_t gfn = gpa >> PAGE_SHIFT;
4276 unsigned long mmu_seq;
4277 int write = error_code & PFERR_WRITE_MASK;
4279 bool lpage_disallowed = (error_code & PFERR_FETCH_MASK) &&
4280 is_nx_huge_page_enabled();
4283 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa));
4285 if (page_fault_handle_page_track(vcpu, error_code, gfn))
4286 return RET_PF_EMULATE;
4288 r = mmu_topup_memory_caches(vcpu);
4292 for (max_level = PT_MAX_HUGEPAGE_LEVEL;
4293 max_level > PT_PAGE_TABLE_LEVEL;
4295 int page_num = KVM_PAGES_PER_HPAGE(max_level);
4296 gfn_t base = gfn & ~(page_num - 1);
4298 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
4302 if (lpage_disallowed)
4303 max_level = PT_PAGE_TABLE_LEVEL;
4305 level = mapping_level(vcpu, gfn, &max_level);
4306 if (level > PT_PAGE_TABLE_LEVEL)
4307 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
4309 if (fast_page_fault(vcpu, gpa, level, error_code))
4310 return RET_PF_RETRY;
4312 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4315 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
4316 return RET_PF_RETRY;
4318 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
4322 spin_lock(&vcpu->kvm->mmu_lock);
4323 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
4325 if (make_mmu_pages_available(vcpu) < 0)
4327 if (likely(max_level > PT_PAGE_TABLE_LEVEL))
4328 transparent_hugepage_adjust(vcpu, gfn, &pfn, &level);
4329 r = __direct_map(vcpu, gpa, write, map_writable, level, pfn,
4330 prefault, lpage_disallowed);
4332 spin_unlock(&vcpu->kvm->mmu_lock);
4333 kvm_release_pfn_clean(pfn);
4337 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
4338 struct kvm_mmu *context)
4340 context->page_fault = nonpaging_page_fault;
4341 context->gva_to_gpa = nonpaging_gva_to_gpa;
4342 context->sync_page = nonpaging_sync_page;
4343 context->invlpg = nonpaging_invlpg;
4344 context->update_pte = nonpaging_update_pte;
4345 context->root_level = 0;
4346 context->shadow_root_level = PT32E_ROOT_LEVEL;
4347 context->direct_map = true;
4348 context->nx = false;
4352 * Find out if a previously cached root matching the new CR3/role is available.
4353 * The current root is also inserted into the cache.
4354 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4356 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4357 * false is returned. This root should now be freed by the caller.
4359 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4360 union kvm_mmu_page_role new_role)
4363 struct kvm_mmu_root_info root;
4364 struct kvm_mmu *mmu = vcpu->arch.mmu;
4366 root.cr3 = mmu->root_cr3;
4367 root.hpa = mmu->root_hpa;
4369 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4370 swap(root, mmu->prev_roots[i]);
4372 if (new_cr3 == root.cr3 && VALID_PAGE(root.hpa) &&
4373 page_header(root.hpa) != NULL &&
4374 new_role.word == page_header(root.hpa)->role.word)
4378 mmu->root_hpa = root.hpa;
4379 mmu->root_cr3 = root.cr3;
4381 return i < KVM_MMU_NUM_PREV_ROOTS;
4384 static bool fast_cr3_switch(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4385 union kvm_mmu_page_role new_role,
4386 bool skip_tlb_flush)
4388 struct kvm_mmu *mmu = vcpu->arch.mmu;
4391 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4392 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4393 * later if necessary.
4395 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4396 mmu->root_level >= PT64_ROOT_4LEVEL) {
4397 if (mmu_check_root(vcpu, new_cr3 >> PAGE_SHIFT))
4400 if (cached_root_available(vcpu, new_cr3, new_role)) {
4402 * It is possible that the cached previous root page is
4403 * obsolete because of a change in the MMU generation
4404 * number. However, changing the generation number is
4405 * accompanied by KVM_REQ_MMU_RELOAD, which will free
4406 * the root set here and allocate a new one.
4408 kvm_make_request(KVM_REQ_LOAD_CR3, vcpu);
4409 if (!skip_tlb_flush) {
4410 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4411 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4415 * The last MMIO access's GVA and GPA are cached in the
4416 * VCPU. When switching to a new CR3, that GVA->GPA
4417 * mapping may no longer be valid. So clear any cached
4418 * MMIO info even when we don't need to sync the shadow
4421 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4423 __clear_sp_write_flooding_count(
4424 page_header(mmu->root_hpa));
4433 static void __kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4434 union kvm_mmu_page_role new_role,
4435 bool skip_tlb_flush)
4437 if (!fast_cr3_switch(vcpu, new_cr3, new_role, skip_tlb_flush))
4438 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu,
4439 KVM_MMU_ROOT_CURRENT);
4442 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush)
4444 __kvm_mmu_new_cr3(vcpu, new_cr3, kvm_mmu_calc_root_page_role(vcpu),
4447 EXPORT_SYMBOL_GPL(kvm_mmu_new_cr3);
4449 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4451 return kvm_read_cr3(vcpu);
4454 static void inject_page_fault(struct kvm_vcpu *vcpu,
4455 struct x86_exception *fault)
4457 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
4460 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4461 unsigned access, int *nr_present)
4463 if (unlikely(is_mmio_spte(*sptep))) {
4464 if (gfn != get_mmio_spte_gfn(*sptep)) {
4465 mmu_spte_clear_no_track(sptep);
4470 mark_mmio_spte(vcpu, sptep, gfn, access);
4477 static inline bool is_last_gpte(struct kvm_mmu *mmu,
4478 unsigned level, unsigned gpte)
4481 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4482 * If it is clear, there are no large pages at this level, so clear
4483 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4485 gpte &= level - mmu->last_nonleaf_level;
4488 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
4489 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
4490 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
4492 gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
4494 return gpte & PT_PAGE_SIZE_MASK;
4497 #define PTTYPE_EPT 18 /* arbitrary */
4498 #define PTTYPE PTTYPE_EPT
4499 #include "paging_tmpl.h"
4503 #include "paging_tmpl.h"
4507 #include "paging_tmpl.h"
4511 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4512 struct rsvd_bits_validate *rsvd_check,
4513 int maxphyaddr, int level, bool nx, bool gbpages,
4516 u64 exb_bit_rsvd = 0;
4517 u64 gbpages_bit_rsvd = 0;
4518 u64 nonleaf_bit8_rsvd = 0;
4520 rsvd_check->bad_mt_xwr = 0;
4523 exb_bit_rsvd = rsvd_bits(63, 63);
4525 gbpages_bit_rsvd = rsvd_bits(7, 7);
4528 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4529 * leaf entries) on AMD CPUs only.
4532 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4535 case PT32_ROOT_LEVEL:
4536 /* no rsvd bits for 2 level 4K page table entries */
4537 rsvd_check->rsvd_bits_mask[0][1] = 0;
4538 rsvd_check->rsvd_bits_mask[0][0] = 0;
4539 rsvd_check->rsvd_bits_mask[1][0] =
4540 rsvd_check->rsvd_bits_mask[0][0];
4543 rsvd_check->rsvd_bits_mask[1][1] = 0;
4547 if (is_cpuid_PSE36())
4548 /* 36bits PSE 4MB page */
4549 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4551 /* 32 bits PSE 4MB page */
4552 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4554 case PT32E_ROOT_LEVEL:
4555 rsvd_check->rsvd_bits_mask[0][2] =
4556 rsvd_bits(maxphyaddr, 63) |
4557 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
4558 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4559 rsvd_bits(maxphyaddr, 62); /* PDE */
4560 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4561 rsvd_bits(maxphyaddr, 62); /* PTE */
4562 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4563 rsvd_bits(maxphyaddr, 62) |
4564 rsvd_bits(13, 20); /* large page */
4565 rsvd_check->rsvd_bits_mask[1][0] =
4566 rsvd_check->rsvd_bits_mask[0][0];
4568 case PT64_ROOT_5LEVEL:
4569 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
4570 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4571 rsvd_bits(maxphyaddr, 51);
4572 rsvd_check->rsvd_bits_mask[1][4] =
4573 rsvd_check->rsvd_bits_mask[0][4];
4575 case PT64_ROOT_4LEVEL:
4576 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4577 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4578 rsvd_bits(maxphyaddr, 51);
4579 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
4580 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
4581 rsvd_bits(maxphyaddr, 51);
4582 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4583 rsvd_bits(maxphyaddr, 51);
4584 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4585 rsvd_bits(maxphyaddr, 51);
4586 rsvd_check->rsvd_bits_mask[1][3] =
4587 rsvd_check->rsvd_bits_mask[0][3];
4588 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
4589 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
4591 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4592 rsvd_bits(maxphyaddr, 51) |
4593 rsvd_bits(13, 20); /* large page */
4594 rsvd_check->rsvd_bits_mask[1][0] =
4595 rsvd_check->rsvd_bits_mask[0][0];
4600 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4601 struct kvm_mmu *context)
4603 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4604 cpuid_maxphyaddr(vcpu), context->root_level,
4606 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4607 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
4611 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4612 int maxphyaddr, bool execonly)
4616 rsvd_check->rsvd_bits_mask[0][4] =
4617 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4618 rsvd_check->rsvd_bits_mask[0][3] =
4619 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4620 rsvd_check->rsvd_bits_mask[0][2] =
4621 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4622 rsvd_check->rsvd_bits_mask[0][1] =
4623 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4624 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4627 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4628 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4629 rsvd_check->rsvd_bits_mask[1][2] =
4630 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4631 rsvd_check->rsvd_bits_mask[1][1] =
4632 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4633 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4635 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4636 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4637 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4638 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4639 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4641 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4642 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4644 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4647 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4648 struct kvm_mmu *context, bool execonly)
4650 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4651 cpuid_maxphyaddr(vcpu), execonly);
4655 * the page table on host is the shadow page table for the page
4656 * table in guest or amd nested guest, its mmu features completely
4657 * follow the features in guest.
4660 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4662 bool uses_nx = context->nx ||
4663 context->mmu_role.base.smep_andnot_wp;
4664 struct rsvd_bits_validate *shadow_zero_check;
4668 * Passing "true" to the last argument is okay; it adds a check
4669 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4671 shadow_zero_check = &context->shadow_zero_check;
4672 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4674 context->shadow_root_level, uses_nx,
4675 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4676 is_pse(vcpu), true);
4678 if (!shadow_me_mask)
4681 for (i = context->shadow_root_level; --i >= 0;) {
4682 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4683 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4687 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4689 static inline bool boot_cpu_is_amd(void)
4691 WARN_ON_ONCE(!tdp_enabled);
4692 return shadow_x_mask == 0;
4696 * the direct page table on host, use as much mmu features as
4697 * possible, however, kvm currently does not do execution-protection.
4700 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4701 struct kvm_mmu *context)
4703 struct rsvd_bits_validate *shadow_zero_check;
4706 shadow_zero_check = &context->shadow_zero_check;
4708 if (boot_cpu_is_amd())
4709 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4711 context->shadow_root_level, false,
4712 boot_cpu_has(X86_FEATURE_GBPAGES),
4715 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4719 if (!shadow_me_mask)
4722 for (i = context->shadow_root_level; --i >= 0;) {
4723 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4724 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4729 * as the comments in reset_shadow_zero_bits_mask() except it
4730 * is the shadow page table for intel nested guest.
4733 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4734 struct kvm_mmu *context, bool execonly)
4736 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4737 shadow_phys_bits, execonly);
4740 #define BYTE_MASK(access) \
4741 ((1 & (access) ? 2 : 0) | \
4742 (2 & (access) ? 4 : 0) | \
4743 (3 & (access) ? 8 : 0) | \
4744 (4 & (access) ? 16 : 0) | \
4745 (5 & (access) ? 32 : 0) | \
4746 (6 & (access) ? 64 : 0) | \
4747 (7 & (access) ? 128 : 0))
4750 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4751 struct kvm_mmu *mmu, bool ept)
4755 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4756 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4757 const u8 u = BYTE_MASK(ACC_USER_MASK);
4759 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4760 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4761 bool cr0_wp = is_write_protection(vcpu);
4763 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4764 unsigned pfec = byte << 1;
4767 * Each "*f" variable has a 1 bit for each UWX value
4768 * that causes a fault with the given PFEC.
4771 /* Faults from writes to non-writable pages */
4772 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4773 /* Faults from user mode accesses to supervisor pages */
4774 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4775 /* Faults from fetches of non-executable pages*/
4776 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4777 /* Faults from kernel mode fetches of user pages */
4779 /* Faults from kernel mode accesses of user pages */
4783 /* Faults from kernel mode accesses to user pages */
4784 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4786 /* Not really needed: !nx will cause pte.nx to fault */
4790 /* Allow supervisor writes if !cr0.wp */
4792 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4794 /* Disallow supervisor fetches of user code if cr4.smep */
4796 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4799 * SMAP:kernel-mode data accesses from user-mode
4800 * mappings should fault. A fault is considered
4801 * as a SMAP violation if all of the following
4802 * conditions are true:
4803 * - X86_CR4_SMAP is set in CR4
4804 * - A user page is accessed
4805 * - The access is not a fetch
4806 * - Page fault in kernel mode
4807 * - if CPL = 3 or X86_EFLAGS_AC is clear
4809 * Here, we cover the first three conditions.
4810 * The fourth is computed dynamically in permission_fault();
4811 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4812 * *not* subject to SMAP restrictions.
4815 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4818 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4823 * PKU is an additional mechanism by which the paging controls access to
4824 * user-mode addresses based on the value in the PKRU register. Protection
4825 * key violations are reported through a bit in the page fault error code.
4826 * Unlike other bits of the error code, the PK bit is not known at the
4827 * call site of e.g. gva_to_gpa; it must be computed directly in
4828 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4829 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4831 * In particular the following conditions come from the error code, the
4832 * page tables and the machine state:
4833 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4834 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4835 * - PK is always zero if U=0 in the page tables
4836 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4838 * The PKRU bitmask caches the result of these four conditions. The error
4839 * code (minus the P bit) and the page table's U bit form an index into the
4840 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4841 * with the two bits of the PKRU register corresponding to the protection key.
4842 * For the first three conditions above the bits will be 00, thus masking
4843 * away both AD and WD. For all reads or if the last condition holds, WD
4844 * only will be masked away.
4846 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4857 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4858 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4863 wp = is_write_protection(vcpu);
4865 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4866 unsigned pfec, pkey_bits;
4867 bool check_pkey, check_write, ff, uf, wf, pte_user;
4870 ff = pfec & PFERR_FETCH_MASK;
4871 uf = pfec & PFERR_USER_MASK;
4872 wf = pfec & PFERR_WRITE_MASK;
4874 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4875 pte_user = pfec & PFERR_RSVD_MASK;
4878 * Only need to check the access which is not an
4879 * instruction fetch and is to a user page.
4881 check_pkey = (!ff && pte_user);
4883 * write access is controlled by PKRU if it is a
4884 * user access or CR0.WP = 1.
4886 check_write = check_pkey && wf && (uf || wp);
4888 /* PKRU.AD stops both read and write access. */
4889 pkey_bits = !!check_pkey;
4890 /* PKRU.WD stops write access. */
4891 pkey_bits |= (!!check_write) << 1;
4893 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4897 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4899 unsigned root_level = mmu->root_level;
4901 mmu->last_nonleaf_level = root_level;
4902 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4903 mmu->last_nonleaf_level++;
4906 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4907 struct kvm_mmu *context,
4910 context->nx = is_nx(vcpu);
4911 context->root_level = level;
4913 reset_rsvds_bits_mask(vcpu, context);
4914 update_permission_bitmask(vcpu, context, false);
4915 update_pkru_bitmask(vcpu, context, false);
4916 update_last_nonleaf_level(vcpu, context);
4918 MMU_WARN_ON(!is_pae(vcpu));
4919 context->page_fault = paging64_page_fault;
4920 context->gva_to_gpa = paging64_gva_to_gpa;
4921 context->sync_page = paging64_sync_page;
4922 context->invlpg = paging64_invlpg;
4923 context->update_pte = paging64_update_pte;
4924 context->shadow_root_level = level;
4925 context->direct_map = false;
4928 static void paging64_init_context(struct kvm_vcpu *vcpu,
4929 struct kvm_mmu *context)
4931 int root_level = is_la57_mode(vcpu) ?
4932 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4934 paging64_init_context_common(vcpu, context, root_level);
4937 static void paging32_init_context(struct kvm_vcpu *vcpu,
4938 struct kvm_mmu *context)
4940 context->nx = false;
4941 context->root_level = PT32_ROOT_LEVEL;
4943 reset_rsvds_bits_mask(vcpu, context);
4944 update_permission_bitmask(vcpu, context, false);
4945 update_pkru_bitmask(vcpu, context, false);
4946 update_last_nonleaf_level(vcpu, context);
4948 context->page_fault = paging32_page_fault;
4949 context->gva_to_gpa = paging32_gva_to_gpa;
4950 context->sync_page = paging32_sync_page;
4951 context->invlpg = paging32_invlpg;
4952 context->update_pte = paging32_update_pte;
4953 context->shadow_root_level = PT32E_ROOT_LEVEL;
4954 context->direct_map = false;
4957 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4958 struct kvm_mmu *context)
4960 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4963 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4965 union kvm_mmu_extended_role ext = {0};
4967 ext.cr0_pg = !!is_paging(vcpu);
4968 ext.cr4_pae = !!is_pae(vcpu);
4969 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4970 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4971 ext.cr4_pse = !!is_pse(vcpu);
4972 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4973 ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
4974 ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
4981 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4984 union kvm_mmu_role role = {0};
4986 role.base.access = ACC_ALL;
4987 role.base.nxe = !!is_nx(vcpu);
4988 role.base.cr0_wp = is_write_protection(vcpu);
4989 role.base.smm = is_smm(vcpu);
4990 role.base.guest_mode = is_guest_mode(vcpu);
4995 role.ext = kvm_calc_mmu_role_ext(vcpu);
5000 static union kvm_mmu_role
5001 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
5003 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
5005 role.base.ad_disabled = (shadow_accessed_mask == 0);
5006 role.base.level = kvm_x86_ops->get_tdp_level(vcpu);
5007 role.base.direct = true;
5008 role.base.gpte_is_8_bytes = true;
5013 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
5015 struct kvm_mmu *context = vcpu->arch.mmu;
5016 union kvm_mmu_role new_role =
5017 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
5019 new_role.base.word &= mmu_base_role_mask.word;
5020 if (new_role.as_u64 == context->mmu_role.as_u64)
5023 context->mmu_role.as_u64 = new_role.as_u64;
5024 context->page_fault = tdp_page_fault;
5025 context->sync_page = nonpaging_sync_page;
5026 context->invlpg = nonpaging_invlpg;
5027 context->update_pte = nonpaging_update_pte;
5028 context->shadow_root_level = kvm_x86_ops->get_tdp_level(vcpu);
5029 context->direct_map = true;
5030 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
5031 context->get_cr3 = get_cr3;
5032 context->get_pdptr = kvm_pdptr_read;
5033 context->inject_page_fault = kvm_inject_page_fault;
5035 if (!is_paging(vcpu)) {
5036 context->nx = false;
5037 context->gva_to_gpa = nonpaging_gva_to_gpa;
5038 context->root_level = 0;
5039 } else if (is_long_mode(vcpu)) {
5040 context->nx = is_nx(vcpu);
5041 context->root_level = is_la57_mode(vcpu) ?
5042 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
5043 reset_rsvds_bits_mask(vcpu, context);
5044 context->gva_to_gpa = paging64_gva_to_gpa;
5045 } else if (is_pae(vcpu)) {
5046 context->nx = is_nx(vcpu);
5047 context->root_level = PT32E_ROOT_LEVEL;
5048 reset_rsvds_bits_mask(vcpu, context);
5049 context->gva_to_gpa = paging64_gva_to_gpa;
5051 context->nx = false;
5052 context->root_level = PT32_ROOT_LEVEL;
5053 reset_rsvds_bits_mask(vcpu, context);
5054 context->gva_to_gpa = paging32_gva_to_gpa;
5057 update_permission_bitmask(vcpu, context, false);
5058 update_pkru_bitmask(vcpu, context, false);
5059 update_last_nonleaf_level(vcpu, context);
5060 reset_tdp_shadow_zero_bits_mask(vcpu, context);
5063 static union kvm_mmu_role
5064 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
5066 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
5068 role.base.smep_andnot_wp = role.ext.cr4_smep &&
5069 !is_write_protection(vcpu);
5070 role.base.smap_andnot_wp = role.ext.cr4_smap &&
5071 !is_write_protection(vcpu);
5072 role.base.direct = !is_paging(vcpu);
5073 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
5075 if (!is_long_mode(vcpu))
5076 role.base.level = PT32E_ROOT_LEVEL;
5077 else if (is_la57_mode(vcpu))
5078 role.base.level = PT64_ROOT_5LEVEL;
5080 role.base.level = PT64_ROOT_4LEVEL;
5085 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
5087 struct kvm_mmu *context = vcpu->arch.mmu;
5088 union kvm_mmu_role new_role =
5089 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
5091 new_role.base.word &= mmu_base_role_mask.word;
5092 if (new_role.as_u64 == context->mmu_role.as_u64)
5095 if (!is_paging(vcpu))
5096 nonpaging_init_context(vcpu, context);
5097 else if (is_long_mode(vcpu))
5098 paging64_init_context(vcpu, context);
5099 else if (is_pae(vcpu))
5100 paging32E_init_context(vcpu, context);
5102 paging32_init_context(vcpu, context);
5104 context->mmu_role.as_u64 = new_role.as_u64;
5105 reset_shadow_zero_bits_mask(vcpu, context);
5107 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
5109 static union kvm_mmu_role
5110 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
5113 union kvm_mmu_role role = {0};
5115 /* SMM flag is inherited from root_mmu */
5116 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
5118 role.base.level = PT64_ROOT_4LEVEL;
5119 role.base.gpte_is_8_bytes = true;
5120 role.base.direct = false;
5121 role.base.ad_disabled = !accessed_dirty;
5122 role.base.guest_mode = true;
5123 role.base.access = ACC_ALL;
5126 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
5127 * SMAP variation to denote shadow EPT entries.
5129 role.base.cr0_wp = true;
5130 role.base.smap_andnot_wp = true;
5132 role.ext = kvm_calc_mmu_role_ext(vcpu);
5133 role.ext.execonly = execonly;
5138 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
5139 bool accessed_dirty, gpa_t new_eptp)
5141 struct kvm_mmu *context = vcpu->arch.mmu;
5142 union kvm_mmu_role new_role =
5143 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
5146 __kvm_mmu_new_cr3(vcpu, new_eptp, new_role.base, false);
5148 new_role.base.word &= mmu_base_role_mask.word;
5149 if (new_role.as_u64 == context->mmu_role.as_u64)
5152 context->shadow_root_level = PT64_ROOT_4LEVEL;
5155 context->ept_ad = accessed_dirty;
5156 context->page_fault = ept_page_fault;
5157 context->gva_to_gpa = ept_gva_to_gpa;
5158 context->sync_page = ept_sync_page;
5159 context->invlpg = ept_invlpg;
5160 context->update_pte = ept_update_pte;
5161 context->root_level = PT64_ROOT_4LEVEL;
5162 context->direct_map = false;
5163 context->mmu_role.as_u64 = new_role.as_u64;
5165 update_permission_bitmask(vcpu, context, true);
5166 update_pkru_bitmask(vcpu, context, true);
5167 update_last_nonleaf_level(vcpu, context);
5168 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
5169 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
5171 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
5173 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
5175 struct kvm_mmu *context = vcpu->arch.mmu;
5177 kvm_init_shadow_mmu(vcpu);
5178 context->set_cr3 = kvm_x86_ops->set_cr3;
5179 context->get_cr3 = get_cr3;
5180 context->get_pdptr = kvm_pdptr_read;
5181 context->inject_page_fault = kvm_inject_page_fault;
5184 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
5186 union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false);
5187 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
5189 new_role.base.word &= mmu_base_role_mask.word;
5190 if (new_role.as_u64 == g_context->mmu_role.as_u64)
5193 g_context->mmu_role.as_u64 = new_role.as_u64;
5194 g_context->get_cr3 = get_cr3;
5195 g_context->get_pdptr = kvm_pdptr_read;
5196 g_context->inject_page_fault = kvm_inject_page_fault;
5199 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
5200 * L1's nested page tables (e.g. EPT12). The nested translation
5201 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
5202 * L2's page tables as the first level of translation and L1's
5203 * nested page tables as the second level of translation. Basically
5204 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
5206 if (!is_paging(vcpu)) {
5207 g_context->nx = false;
5208 g_context->root_level = 0;
5209 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
5210 } else if (is_long_mode(vcpu)) {
5211 g_context->nx = is_nx(vcpu);
5212 g_context->root_level = is_la57_mode(vcpu) ?
5213 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
5214 reset_rsvds_bits_mask(vcpu, g_context);
5215 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5216 } else if (is_pae(vcpu)) {
5217 g_context->nx = is_nx(vcpu);
5218 g_context->root_level = PT32E_ROOT_LEVEL;
5219 reset_rsvds_bits_mask(vcpu, g_context);
5220 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5222 g_context->nx = false;
5223 g_context->root_level = PT32_ROOT_LEVEL;
5224 reset_rsvds_bits_mask(vcpu, g_context);
5225 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
5228 update_permission_bitmask(vcpu, g_context, false);
5229 update_pkru_bitmask(vcpu, g_context, false);
5230 update_last_nonleaf_level(vcpu, g_context);
5233 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
5238 vcpu->arch.mmu->root_hpa = INVALID_PAGE;
5240 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5241 vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5244 if (mmu_is_nested(vcpu))
5245 init_kvm_nested_mmu(vcpu);
5246 else if (tdp_enabled)
5247 init_kvm_tdp_mmu(vcpu);
5249 init_kvm_softmmu(vcpu);
5251 EXPORT_SYMBOL_GPL(kvm_init_mmu);
5253 static union kvm_mmu_page_role
5254 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
5256 union kvm_mmu_role role;
5259 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
5261 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
5266 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
5268 kvm_mmu_unload(vcpu);
5269 kvm_init_mmu(vcpu, true);
5271 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
5273 int kvm_mmu_load(struct kvm_vcpu *vcpu)
5277 r = mmu_topup_memory_caches(vcpu);
5280 r = mmu_alloc_roots(vcpu);
5281 kvm_mmu_sync_roots(vcpu);
5284 kvm_mmu_load_cr3(vcpu);
5285 kvm_x86_ops->tlb_flush(vcpu, true);
5289 EXPORT_SYMBOL_GPL(kvm_mmu_load);
5291 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
5293 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
5294 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
5295 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
5296 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
5298 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
5300 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
5301 struct kvm_mmu_page *sp, u64 *spte,
5304 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
5305 ++vcpu->kvm->stat.mmu_pde_zapped;
5309 ++vcpu->kvm->stat.mmu_pte_updated;
5310 vcpu->arch.mmu->update_pte(vcpu, sp, spte, new);
5313 static bool need_remote_flush(u64 old, u64 new)
5315 if (!is_shadow_present_pte(old))
5317 if (!is_shadow_present_pte(new))
5319 if ((old ^ new) & PT64_BASE_ADDR_MASK)
5321 old ^= shadow_nx_mask;
5322 new ^= shadow_nx_mask;
5323 return (old & ~new & PT64_PERM_MASK) != 0;
5326 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
5333 * Assume that the pte write on a page table of the same type
5334 * as the current vcpu paging mode since we update the sptes only
5335 * when they have the same mode.
5337 if (is_pae(vcpu) && *bytes == 4) {
5338 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5343 if (*bytes == 4 || *bytes == 8) {
5344 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5353 * If we're seeing too many writes to a page, it may no longer be a page table,
5354 * or we may be forking, in which case it is better to unmap the page.
5356 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5359 * Skip write-flooding detected for the sp whose level is 1, because
5360 * it can become unsync, then the guest page is not write-protected.
5362 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
5365 atomic_inc(&sp->write_flooding_count);
5366 return atomic_read(&sp->write_flooding_count) >= 3;
5370 * Misaligned accesses are too much trouble to fix up; also, they usually
5371 * indicate a page is not used as a page table.
5373 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5376 unsigned offset, pte_size, misaligned;
5378 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5379 gpa, bytes, sp->role.word);
5381 offset = offset_in_page(gpa);
5382 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5385 * Sometimes, the OS only writes the last one bytes to update status
5386 * bits, for example, in linux, andb instruction is used in clear_bit().
5388 if (!(offset & (pte_size - 1)) && bytes == 1)
5391 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5392 misaligned |= bytes < 4;
5397 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5399 unsigned page_offset, quadrant;
5403 page_offset = offset_in_page(gpa);
5404 level = sp->role.level;
5406 if (!sp->role.gpte_is_8_bytes) {
5407 page_offset <<= 1; /* 32->64 */
5409 * A 32-bit pde maps 4MB while the shadow pdes map
5410 * only 2MB. So we need to double the offset again
5411 * and zap two pdes instead of one.
5413 if (level == PT32_ROOT_LEVEL) {
5414 page_offset &= ~7; /* kill rounding error */
5418 quadrant = page_offset >> PAGE_SHIFT;
5419 page_offset &= ~PAGE_MASK;
5420 if (quadrant != sp->role.quadrant)
5424 spte = &sp->spt[page_offset / sizeof(*spte)];
5428 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5429 const u8 *new, int bytes,
5430 struct kvm_page_track_notifier_node *node)
5432 gfn_t gfn = gpa >> PAGE_SHIFT;
5433 struct kvm_mmu_page *sp;
5434 LIST_HEAD(invalid_list);
5435 u64 entry, gentry, *spte;
5437 bool remote_flush, local_flush;
5440 * If we don't have indirect shadow pages, it means no page is
5441 * write-protected, so we can exit simply.
5443 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5446 remote_flush = local_flush = false;
5448 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5451 * No need to care whether allocation memory is successful
5452 * or not since pte prefetch is skiped if it does not have
5453 * enough objects in the cache.
5455 mmu_topup_memory_caches(vcpu);
5457 spin_lock(&vcpu->kvm->mmu_lock);
5459 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5461 ++vcpu->kvm->stat.mmu_pte_write;
5462 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5464 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5465 if (detect_write_misaligned(sp, gpa, bytes) ||
5466 detect_write_flooding(sp)) {
5467 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5468 ++vcpu->kvm->stat.mmu_flooded;
5472 spte = get_written_sptes(sp, gpa, &npte);
5478 u32 base_role = vcpu->arch.mmu->mmu_role.base.word;
5481 mmu_page_zap_pte(vcpu->kvm, sp, spte);
5483 !((sp->role.word ^ base_role)
5484 & mmu_base_role_mask.word) && rmap_can_add(vcpu))
5485 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
5486 if (need_remote_flush(entry, *spte))
5487 remote_flush = true;
5491 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5492 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5493 spin_unlock(&vcpu->kvm->mmu_lock);
5496 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
5501 if (vcpu->arch.mmu->direct_map)
5504 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
5506 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
5510 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
5512 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5513 void *insn, int insn_len)
5515 int r, emulation_type = 0;
5516 bool direct = vcpu->arch.mmu->direct_map;
5518 /* With shadow page tables, fault_address contains a GVA or nGPA. */
5519 if (vcpu->arch.mmu->direct_map) {
5520 vcpu->arch.gpa_available = true;
5521 vcpu->arch.gpa_val = cr2_or_gpa;
5525 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5526 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5527 if (r == RET_PF_EMULATE)
5531 if (r == RET_PF_INVALID) {
5532 r = vcpu->arch.mmu->page_fault(vcpu, cr2_or_gpa,
5533 lower_32_bits(error_code),
5535 WARN_ON(r == RET_PF_INVALID);
5538 if (r == RET_PF_RETRY)
5544 * Before emulating the instruction, check if the error code
5545 * was due to a RO violation while translating the guest page.
5546 * This can occur when using nested virtualization with nested
5547 * paging in both guests. If true, we simply unprotect the page
5548 * and resume the guest.
5550 if (vcpu->arch.mmu->direct_map &&
5551 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5552 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5557 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5558 * optimistically try to just unprotect the page and let the processor
5559 * re-execute the instruction that caused the page fault. Do not allow
5560 * retrying MMIO emulation, as it's not only pointless but could also
5561 * cause us to enter an infinite loop because the processor will keep
5562 * faulting on the non-existent MMIO address. Retrying an instruction
5563 * from a nested guest is also pointless and dangerous as we are only
5564 * explicitly shadowing L1's page tables, i.e. unprotecting something
5565 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5567 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5568 emulation_type = EMULTYPE_ALLOW_RETRY;
5571 * On AMD platforms, under certain conditions insn_len may be zero on #NPF.
5572 * This can happen if a guest gets a page-fault on data access but the HW
5573 * table walker is not able to read the instruction page (e.g instruction
5574 * page is not present in memory). In those cases we simply restart the
5575 * guest, with the exception of AMD Erratum 1096 which is unrecoverable.
5577 if (unlikely(insn && !insn_len)) {
5578 if (!kvm_x86_ops->need_emulation_on_page_fault(vcpu))
5582 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5585 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5587 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5589 struct kvm_mmu *mmu = vcpu->arch.mmu;
5592 /* INVLPG on a * non-canonical address is a NOP according to the SDM. */
5593 if (is_noncanonical_address(gva, vcpu))
5596 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5599 * INVLPG is required to invalidate any global mappings for the VA,
5600 * irrespective of PCID. Since it would take us roughly similar amount
5601 * of work to determine whether any of the prev_root mappings of the VA
5602 * is marked global, or to just sync it blindly, so we might as well
5603 * just always sync it.
5605 * Mappings not reachable via the current cr3 or the prev_roots will be
5606 * synced when switching to that cr3, so nothing needs to be done here
5609 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5610 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5611 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5613 kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5614 ++vcpu->stat.invlpg;
5616 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5618 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5620 struct kvm_mmu *mmu = vcpu->arch.mmu;
5621 bool tlb_flush = false;
5624 if (pcid == kvm_get_active_pcid(vcpu)) {
5625 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5629 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5630 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5631 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].cr3)) {
5632 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5638 kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5640 ++vcpu->stat.invlpg;
5643 * Mappings not reachable via the current cr3 or the prev_roots will be
5644 * synced when switching to that cr3, so nothing needs to be done here
5648 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva);
5650 void kvm_enable_tdp(void)
5654 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
5656 void kvm_disable_tdp(void)
5658 tdp_enabled = false;
5660 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
5663 /* The return value indicates if tlb flush on all vcpus is needed. */
5664 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5666 /* The caller should hold mmu-lock before calling this function. */
5667 static __always_inline bool
5668 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5669 slot_level_handler fn, int start_level, int end_level,
5670 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5672 struct slot_rmap_walk_iterator iterator;
5675 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5676 end_gfn, &iterator) {
5678 flush |= fn(kvm, iterator.rmap);
5680 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5681 if (flush && lock_flush_tlb) {
5682 kvm_flush_remote_tlbs_with_address(kvm,
5684 iterator.gfn - start_gfn + 1);
5687 cond_resched_lock(&kvm->mmu_lock);
5691 if (flush && lock_flush_tlb) {
5692 kvm_flush_remote_tlbs_with_address(kvm, start_gfn,
5693 end_gfn - start_gfn + 1);
5700 static __always_inline bool
5701 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5702 slot_level_handler fn, int start_level, int end_level,
5703 bool lock_flush_tlb)
5705 return slot_handle_level_range(kvm, memslot, fn, start_level,
5706 end_level, memslot->base_gfn,
5707 memslot->base_gfn + memslot->npages - 1,
5711 static __always_inline bool
5712 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5713 slot_level_handler fn, bool lock_flush_tlb)
5715 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5716 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5719 static __always_inline bool
5720 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5721 slot_level_handler fn, bool lock_flush_tlb)
5723 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
5724 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5727 static __always_inline bool
5728 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5729 slot_level_handler fn, bool lock_flush_tlb)
5731 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5732 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
5735 static void free_mmu_pages(struct kvm_mmu *mmu)
5737 free_page((unsigned long)mmu->pae_root);
5738 free_page((unsigned long)mmu->lm_root);
5741 static int alloc_mmu_pages(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5747 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5748 * while the PDP table is a per-vCPU construct that's allocated at MMU
5749 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5750 * x86_64. Therefore we need to allocate the PDP table in the first
5751 * 4GB of memory, which happens to fit the DMA32 zone. Except for
5752 * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can
5753 * skip allocating the PDP table.
5755 if (tdp_enabled && kvm_x86_ops->get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5758 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5762 mmu->pae_root = page_address(page);
5763 for (i = 0; i < 4; ++i)
5764 mmu->pae_root[i] = INVALID_PAGE;
5769 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5774 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5775 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5777 vcpu->arch.root_mmu.root_hpa = INVALID_PAGE;
5778 vcpu->arch.root_mmu.root_cr3 = 0;
5779 vcpu->arch.root_mmu.translate_gpa = translate_gpa;
5780 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5781 vcpu->arch.root_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5783 vcpu->arch.guest_mmu.root_hpa = INVALID_PAGE;
5784 vcpu->arch.guest_mmu.root_cr3 = 0;
5785 vcpu->arch.guest_mmu.translate_gpa = translate_gpa;
5786 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5787 vcpu->arch.guest_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5789 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5791 ret = alloc_mmu_pages(vcpu, &vcpu->arch.guest_mmu);
5795 ret = alloc_mmu_pages(vcpu, &vcpu->arch.root_mmu);
5797 goto fail_allocate_root;
5801 free_mmu_pages(&vcpu->arch.guest_mmu);
5805 #define BATCH_ZAP_PAGES 10
5806 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5808 struct kvm_mmu_page *sp, *node;
5809 int nr_zapped, batch = 0;
5812 list_for_each_entry_safe_reverse(sp, node,
5813 &kvm->arch.active_mmu_pages, link) {
5815 * No obsolete valid page exists before a newly created page
5816 * since active_mmu_pages is a FIFO list.
5818 if (!is_obsolete_sp(kvm, sp))
5822 * Skip invalid pages with a non-zero root count, zapping pages
5823 * with a non-zero root count will never succeed, i.e. the page
5824 * will get thrown back on active_mmu_pages and we'll get stuck
5825 * in an infinite loop.
5827 if (sp->role.invalid && sp->root_count)
5831 * No need to flush the TLB since we're only zapping shadow
5832 * pages with an obsolete generation number and all vCPUS have
5833 * loaded a new root, i.e. the shadow pages being zapped cannot
5834 * be in active use by the guest.
5836 if (batch >= BATCH_ZAP_PAGES &&
5837 cond_resched_lock(&kvm->mmu_lock)) {
5842 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5843 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5850 * Trigger a remote TLB flush before freeing the page tables to ensure
5851 * KVM is not in the middle of a lockless shadow page table walk, which
5852 * may reference the pages.
5854 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5858 * Fast invalidate all shadow pages and use lock-break technique
5859 * to zap obsolete pages.
5861 * It's required when memslot is being deleted or VM is being
5862 * destroyed, in these cases, we should ensure that KVM MMU does
5863 * not use any resource of the being-deleted slot or all slots
5864 * after calling the function.
5866 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5868 lockdep_assert_held(&kvm->slots_lock);
5870 spin_lock(&kvm->mmu_lock);
5871 trace_kvm_mmu_zap_all_fast(kvm);
5874 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5875 * held for the entire duration of zapping obsolete pages, it's
5876 * impossible for there to be multiple invalid generations associated
5877 * with *valid* shadow pages at any given time, i.e. there is exactly
5878 * one valid generation and (at most) one invalid generation.
5880 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5883 * Notify all vcpus to reload its shadow page table and flush TLB.
5884 * Then all vcpus will switch to new shadow page table with the new
5887 * Note: we need to do this under the protection of mmu_lock,
5888 * otherwise, vcpu would purge shadow page but miss tlb flush.
5890 kvm_reload_remote_mmus(kvm);
5892 kvm_zap_obsolete_pages(kvm);
5893 spin_unlock(&kvm->mmu_lock);
5896 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5898 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5901 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5902 struct kvm_memory_slot *slot,
5903 struct kvm_page_track_notifier_node *node)
5905 kvm_mmu_zap_all_fast(kvm);
5908 void kvm_mmu_init_vm(struct kvm *kvm)
5910 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5912 node->track_write = kvm_mmu_pte_write;
5913 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5914 kvm_page_track_register_notifier(kvm, node);
5917 void kvm_mmu_uninit_vm(struct kvm *kvm)
5919 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5921 kvm_page_track_unregister_notifier(kvm, node);
5924 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5926 struct kvm_memslots *slots;
5927 struct kvm_memory_slot *memslot;
5930 spin_lock(&kvm->mmu_lock);
5931 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5932 slots = __kvm_memslots(kvm, i);
5933 kvm_for_each_memslot(memslot, slots) {
5936 start = max(gfn_start, memslot->base_gfn);
5937 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5941 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5942 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
5943 start, end - 1, true);
5947 spin_unlock(&kvm->mmu_lock);
5950 static bool slot_rmap_write_protect(struct kvm *kvm,
5951 struct kvm_rmap_head *rmap_head)
5953 return __rmap_write_protect(kvm, rmap_head, false);
5956 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5957 struct kvm_memory_slot *memslot)
5961 spin_lock(&kvm->mmu_lock);
5962 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
5964 spin_unlock(&kvm->mmu_lock);
5967 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
5968 * which do tlb flush out of mmu-lock should be serialized by
5969 * kvm->slots_lock otherwise tlb flush would be missed.
5971 lockdep_assert_held(&kvm->slots_lock);
5974 * We can flush all the TLBs out of the mmu lock without TLB
5975 * corruption since we just change the spte from writable to
5976 * readonly so that we only need to care the case of changing
5977 * spte from present to present (changing the spte from present
5978 * to nonpresent will flush all the TLBs immediately), in other
5979 * words, the only case we care is mmu_spte_update() where we
5980 * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5981 * instead of PT_WRITABLE_MASK, that means it does not depend
5982 * on PT_WRITABLE_MASK anymore.
5985 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5989 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5990 struct kvm_rmap_head *rmap_head)
5993 struct rmap_iterator iter;
5994 int need_tlb_flush = 0;
5996 struct kvm_mmu_page *sp;
5999 for_each_rmap_spte(rmap_head, &iter, sptep) {
6000 sp = page_header(__pa(sptep));
6001 pfn = spte_to_pfn(*sptep);
6004 * We cannot do huge page mapping for indirect shadow pages,
6005 * which are found on the last rmap (level = 1) when not using
6006 * tdp; such shadow pages are synced with the page table in
6007 * the guest, and the guest page table is using 4K page size
6008 * mapping if the indirect sp has level = 1.
6010 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
6011 !kvm_is_zone_device_pfn(pfn) &&
6012 PageTransCompoundMap(pfn_to_page(pfn))) {
6013 pte_list_remove(rmap_head, sptep);
6015 if (kvm_available_flush_tlb_with_range())
6016 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
6017 KVM_PAGES_PER_HPAGE(sp->role.level));
6025 return need_tlb_flush;
6028 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
6029 const struct kvm_memory_slot *memslot)
6031 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
6032 spin_lock(&kvm->mmu_lock);
6033 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
6034 kvm_mmu_zap_collapsible_spte, true);
6035 spin_unlock(&kvm->mmu_lock);
6038 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
6039 struct kvm_memory_slot *memslot)
6043 spin_lock(&kvm->mmu_lock);
6044 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
6045 spin_unlock(&kvm->mmu_lock);
6047 lockdep_assert_held(&kvm->slots_lock);
6050 * It's also safe to flush TLBs out of mmu lock here as currently this
6051 * function is only used for dirty logging, in which case flushing TLB
6052 * out of mmu lock also guarantees no dirty pages will be lost in
6056 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
6059 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
6061 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
6062 struct kvm_memory_slot *memslot)
6066 spin_lock(&kvm->mmu_lock);
6067 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
6069 spin_unlock(&kvm->mmu_lock);
6071 /* see kvm_mmu_slot_remove_write_access */
6072 lockdep_assert_held(&kvm->slots_lock);
6075 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
6078 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
6080 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
6081 struct kvm_memory_slot *memslot)
6085 spin_lock(&kvm->mmu_lock);
6086 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
6087 spin_unlock(&kvm->mmu_lock);
6089 lockdep_assert_held(&kvm->slots_lock);
6091 /* see kvm_mmu_slot_leaf_clear_dirty */
6093 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
6096 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
6098 void kvm_mmu_zap_all(struct kvm *kvm)
6100 struct kvm_mmu_page *sp, *node;
6101 LIST_HEAD(invalid_list);
6104 spin_lock(&kvm->mmu_lock);
6106 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
6107 if (sp->role.invalid && sp->root_count)
6109 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
6111 if (cond_resched_lock(&kvm->mmu_lock))
6115 kvm_mmu_commit_zap_page(kvm, &invalid_list);
6116 spin_unlock(&kvm->mmu_lock);
6119 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
6121 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
6123 gen &= MMIO_SPTE_GEN_MASK;
6126 * Generation numbers are incremented in multiples of the number of
6127 * address spaces in order to provide unique generations across all
6128 * address spaces. Strip what is effectively the address space
6129 * modifier prior to checking for a wrap of the MMIO generation so
6130 * that a wrap in any address space is detected.
6132 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
6135 * The very rare case: if the MMIO generation number has wrapped,
6136 * zap all shadow pages.
6138 if (unlikely(gen == 0)) {
6139 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
6140 kvm_mmu_zap_all_fast(kvm);
6144 static unsigned long
6145 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
6148 int nr_to_scan = sc->nr_to_scan;
6149 unsigned long freed = 0;
6151 mutex_lock(&kvm_lock);
6153 list_for_each_entry(kvm, &vm_list, vm_list) {
6155 LIST_HEAD(invalid_list);
6158 * Never scan more than sc->nr_to_scan VM instances.
6159 * Will not hit this condition practically since we do not try
6160 * to shrink more than one VM and it is very unlikely to see
6161 * !n_used_mmu_pages so many times.
6166 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
6167 * here. We may skip a VM instance errorneosly, but we do not
6168 * want to shrink a VM that only started to populate its MMU
6171 if (!kvm->arch.n_used_mmu_pages &&
6172 !kvm_has_zapped_obsolete_pages(kvm))
6175 idx = srcu_read_lock(&kvm->srcu);
6176 spin_lock(&kvm->mmu_lock);
6178 if (kvm_has_zapped_obsolete_pages(kvm)) {
6179 kvm_mmu_commit_zap_page(kvm,
6180 &kvm->arch.zapped_obsolete_pages);
6184 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
6186 kvm_mmu_commit_zap_page(kvm, &invalid_list);
6189 spin_unlock(&kvm->mmu_lock);
6190 srcu_read_unlock(&kvm->srcu, idx);
6193 * unfair on small ones
6194 * per-vm shrinkers cry out
6195 * sadness comes quickly
6197 list_move_tail(&kvm->vm_list, &vm_list);
6201 mutex_unlock(&kvm_lock);
6205 static unsigned long
6206 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
6208 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
6211 static struct shrinker mmu_shrinker = {
6212 .count_objects = mmu_shrink_count,
6213 .scan_objects = mmu_shrink_scan,
6214 .seeks = DEFAULT_SEEKS * 10,
6217 static void mmu_destroy_caches(void)
6219 kmem_cache_destroy(pte_list_desc_cache);
6220 kmem_cache_destroy(mmu_page_header_cache);
6223 static void kvm_set_mmio_spte_mask(void)
6228 * Set the reserved bits and the present bit of an paging-structure
6229 * entry to generate page fault with PFER.RSV = 1.
6233 * Mask the uppermost physical address bit, which would be reserved as
6234 * long as the supported physical address width is less than 52.
6238 /* Set the present bit. */
6242 * If reserved bit is not supported, clear the present bit to disable
6245 if (IS_ENABLED(CONFIG_X86_64) && shadow_phys_bits == 52)
6248 kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK);
6251 static bool get_nx_auto_mode(void)
6253 /* Return true when CPU has the bug, and mitigations are ON */
6254 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
6257 static void __set_nx_huge_pages(bool val)
6259 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
6262 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
6264 bool old_val = nx_huge_pages;
6267 /* In "auto" mode deploy workaround only if CPU has the bug. */
6268 if (sysfs_streq(val, "off"))
6270 else if (sysfs_streq(val, "force"))
6272 else if (sysfs_streq(val, "auto"))
6273 new_val = get_nx_auto_mode();
6274 else if (strtobool(val, &new_val) < 0)
6277 __set_nx_huge_pages(new_val);
6279 if (new_val != old_val) {
6282 mutex_lock(&kvm_lock);
6284 list_for_each_entry(kvm, &vm_list, vm_list) {
6285 mutex_lock(&kvm->slots_lock);
6286 kvm_mmu_zap_all_fast(kvm);
6287 mutex_unlock(&kvm->slots_lock);
6289 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6291 mutex_unlock(&kvm_lock);
6297 int kvm_mmu_module_init(void)
6301 if (nx_huge_pages == -1)
6302 __set_nx_huge_pages(get_nx_auto_mode());
6305 * MMU roles use union aliasing which is, generally speaking, an
6306 * undefined behavior. However, we supposedly know how compilers behave
6307 * and the current status quo is unlikely to change. Guardians below are
6308 * supposed to let us know if the assumption becomes false.
6310 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
6311 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
6312 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
6314 kvm_mmu_reset_all_pte_masks();
6316 kvm_set_mmio_spte_mask();
6318 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
6319 sizeof(struct pte_list_desc),
6320 0, SLAB_ACCOUNT, NULL);
6321 if (!pte_list_desc_cache)
6324 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
6325 sizeof(struct kvm_mmu_page),
6326 0, SLAB_ACCOUNT, NULL);
6327 if (!mmu_page_header_cache)
6330 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
6333 ret = register_shrinker(&mmu_shrinker);
6340 mmu_destroy_caches();
6345 * Calculate mmu pages needed for kvm.
6347 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
6349 unsigned long nr_mmu_pages;
6350 unsigned long nr_pages = 0;
6351 struct kvm_memslots *slots;
6352 struct kvm_memory_slot *memslot;
6355 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6356 slots = __kvm_memslots(kvm, i);
6358 kvm_for_each_memslot(memslot, slots)
6359 nr_pages += memslot->npages;
6362 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
6363 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
6365 return nr_mmu_pages;
6368 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6370 kvm_mmu_unload(vcpu);
6371 free_mmu_pages(&vcpu->arch.root_mmu);
6372 free_mmu_pages(&vcpu->arch.guest_mmu);
6373 mmu_free_memory_caches(vcpu);
6376 void kvm_mmu_module_exit(void)
6378 mmu_destroy_caches();
6379 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6380 unregister_shrinker(&mmu_shrinker);
6381 mmu_audit_disable();
6384 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
6386 unsigned int old_val;
6389 old_val = nx_huge_pages_recovery_ratio;
6390 err = param_set_uint(val, kp);
6394 if (READ_ONCE(nx_huge_pages) &&
6395 !old_val && nx_huge_pages_recovery_ratio) {
6398 mutex_lock(&kvm_lock);
6400 list_for_each_entry(kvm, &vm_list, vm_list)
6401 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6403 mutex_unlock(&kvm_lock);
6409 static void kvm_recover_nx_lpages(struct kvm *kvm)
6412 struct kvm_mmu_page *sp;
6414 LIST_HEAD(invalid_list);
6417 rcu_idx = srcu_read_lock(&kvm->srcu);
6418 spin_lock(&kvm->mmu_lock);
6420 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6421 to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0;
6422 while (to_zap && !list_empty(&kvm->arch.lpage_disallowed_mmu_pages)) {
6424 * We use a separate list instead of just using active_mmu_pages
6425 * because the number of lpage_disallowed pages is expected to
6426 * be relatively small compared to the total.
6428 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6429 struct kvm_mmu_page,
6430 lpage_disallowed_link);
6431 WARN_ON_ONCE(!sp->lpage_disallowed);
6432 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6433 WARN_ON_ONCE(sp->lpage_disallowed);
6435 if (!--to_zap || need_resched() || spin_needbreak(&kvm->mmu_lock)) {
6436 kvm_mmu_commit_zap_page(kvm, &invalid_list);
6438 cond_resched_lock(&kvm->mmu_lock);
6442 spin_unlock(&kvm->mmu_lock);
6443 srcu_read_unlock(&kvm->srcu, rcu_idx);
6446 static long get_nx_lpage_recovery_timeout(u64 start_time)
6448 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6449 ? start_time + 60 * HZ - get_jiffies_64()
6450 : MAX_SCHEDULE_TIMEOUT;
6453 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6456 long remaining_time;
6459 start_time = get_jiffies_64();
6460 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6462 set_current_state(TASK_INTERRUPTIBLE);
6463 while (!kthread_should_stop() && remaining_time > 0) {
6464 schedule_timeout(remaining_time);
6465 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6466 set_current_state(TASK_INTERRUPTIBLE);
6469 set_current_state(TASK_RUNNING);
6471 if (kthread_should_stop())
6474 kvm_recover_nx_lpages(kvm);
6478 int kvm_mmu_post_init_vm(struct kvm *kvm)
6482 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6483 "kvm-nx-lpage-recovery",
6484 &kvm->arch.nx_lpage_recovery_thread);
6486 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6491 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6493 if (kvm->arch.nx_lpage_recovery_thread)
6494 kthread_stop(kvm->arch.nx_lpage_recovery_thread);