1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
51 #include <asm/set_memory.h>
53 #include <asm/kvm_page_track.h>
56 extern bool itlb_multihit_kvm_mitigation;
58 static int __read_mostly nx_huge_pages = -1;
59 #ifdef CONFIG_PREEMPT_RT
60 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
61 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
63 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
66 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
67 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops nx_huge_pages_ops = {
70 .set = set_nx_huge_pages,
71 .get = param_get_bool,
74 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
75 .set = set_nx_huge_pages_recovery_ratio,
76 .get = param_get_uint,
79 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
80 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
81 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
82 &nx_huge_pages_recovery_ratio, 0644);
83 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
85 static bool __read_mostly force_flush_and_sync_on_reuse;
86 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
89 * When setting this variable to true it enables Two-Dimensional-Paging
90 * where the hardware walks 2 page tables:
91 * 1. the guest-virtual to guest-physical
92 * 2. while doing 1. it walks guest-physical to host-physical
93 * If the hardware supports that we don't need to do shadow paging.
95 bool tdp_enabled = false;
97 static int max_huge_page_level __read_mostly;
98 static int max_tdp_level __read_mostly;
101 AUDIT_PRE_PAGE_FAULT,
102 AUDIT_POST_PAGE_FAULT,
104 AUDIT_POST_PTE_WRITE,
111 module_param(dbg, bool, 0644);
114 #define PTE_PREFETCH_NUM 8
116 #define PT32_LEVEL_BITS 10
118 #define PT32_LEVEL_SHIFT(level) \
119 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
121 #define PT32_LVL_OFFSET_MASK(level) \
122 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT32_LEVEL_BITS))) - 1))
125 #define PT32_INDEX(address, level)\
126 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
129 #define PT32_BASE_ADDR_MASK PAGE_MASK
130 #define PT32_DIR_BASE_ADDR_MASK \
131 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
132 #define PT32_LVL_ADDR_MASK(level) \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
134 * PT32_LEVEL_BITS))) - 1))
136 #include <trace/events/kvm.h>
138 /* make pte_list_desc fit well in cache line */
139 #define PTE_LIST_EXT 3
141 struct pte_list_desc {
142 u64 *sptes[PTE_LIST_EXT];
143 struct pte_list_desc *more;
146 struct kvm_shadow_walk_iterator {
154 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
155 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
157 shadow_walk_okay(&(_walker)); \
158 shadow_walk_next(&(_walker)))
160 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
161 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
162 shadow_walk_okay(&(_walker)); \
163 shadow_walk_next(&(_walker)))
165 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
166 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
167 shadow_walk_okay(&(_walker)) && \
168 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
169 __shadow_walk_next(&(_walker), spte))
171 static struct kmem_cache *pte_list_desc_cache;
172 struct kmem_cache *mmu_page_header_cache;
173 static struct percpu_counter kvm_total_used_mmu_pages;
175 static void mmu_spte_set(u64 *sptep, u64 spte);
176 static union kvm_mmu_page_role
177 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
179 #define CREATE_TRACE_POINTS
180 #include "mmutrace.h"
183 static inline bool kvm_available_flush_tlb_with_range(void)
185 return kvm_x86_ops.tlb_remote_flush_with_range;
188 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
189 struct kvm_tlb_range *range)
193 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
194 ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range);
197 kvm_flush_remote_tlbs(kvm);
200 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
201 u64 start_gfn, u64 pages)
203 struct kvm_tlb_range range;
205 range.start_gfn = start_gfn;
208 kvm_flush_remote_tlbs_with_range(kvm, &range);
211 bool is_nx_huge_page_enabled(void)
213 return READ_ONCE(nx_huge_pages);
216 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
219 u64 spte = make_mmio_spte(vcpu, gfn, access);
221 trace_mark_mmio_spte(sptep, gfn, spte);
222 mmu_spte_set(sptep, spte);
225 static gfn_t get_mmio_spte_gfn(u64 spte)
227 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
229 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)
230 & shadow_nonpresent_or_rsvd_mask;
232 return gpa >> PAGE_SHIFT;
235 static unsigned get_mmio_spte_access(u64 spte)
237 return spte & shadow_mmio_access_mask;
240 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
242 u64 kvm_gen, spte_gen, gen;
244 gen = kvm_vcpu_memslots(vcpu)->generation;
245 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
248 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
249 spte_gen = get_mmio_spte_generation(spte);
251 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
252 return likely(kvm_gen == spte_gen);
255 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
256 struct x86_exception *exception)
258 /* Check if guest physical address doesn't exceed guest maximum */
259 if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) {
260 exception->error_code |= PFERR_RSVD_MASK;
267 static int is_cpuid_PSE36(void)
272 static int is_nx(struct kvm_vcpu *vcpu)
274 return vcpu->arch.efer & EFER_NX;
277 static gfn_t pse36_gfn_delta(u32 gpte)
279 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
281 return (gpte & PT32_DIR_PSE36_MASK) << shift;
285 static void __set_spte(u64 *sptep, u64 spte)
287 WRITE_ONCE(*sptep, spte);
290 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
292 WRITE_ONCE(*sptep, spte);
295 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
297 return xchg(sptep, spte);
300 static u64 __get_spte_lockless(u64 *sptep)
302 return READ_ONCE(*sptep);
313 static void count_spte_clear(u64 *sptep, u64 spte)
315 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
317 if (is_shadow_present_pte(spte))
320 /* Ensure the spte is completely set before we increase the count */
322 sp->clear_spte_count++;
325 static void __set_spte(u64 *sptep, u64 spte)
327 union split_spte *ssptep, sspte;
329 ssptep = (union split_spte *)sptep;
330 sspte = (union split_spte)spte;
332 ssptep->spte_high = sspte.spte_high;
335 * If we map the spte from nonpresent to present, We should store
336 * the high bits firstly, then set present bit, so cpu can not
337 * fetch this spte while we are setting the spte.
341 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
344 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
346 union split_spte *ssptep, sspte;
348 ssptep = (union split_spte *)sptep;
349 sspte = (union split_spte)spte;
351 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
354 * If we map the spte from present to nonpresent, we should clear
355 * present bit firstly to avoid vcpu fetch the old high bits.
359 ssptep->spte_high = sspte.spte_high;
360 count_spte_clear(sptep, spte);
363 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
365 union split_spte *ssptep, sspte, orig;
367 ssptep = (union split_spte *)sptep;
368 sspte = (union split_spte)spte;
370 /* xchg acts as a barrier before the setting of the high bits */
371 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
372 orig.spte_high = ssptep->spte_high;
373 ssptep->spte_high = sspte.spte_high;
374 count_spte_clear(sptep, spte);
380 * The idea using the light way get the spte on x86_32 guest is from
381 * gup_get_pte (mm/gup.c).
383 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
384 * coalesces them and we are running out of the MMU lock. Therefore
385 * we need to protect against in-progress updates of the spte.
387 * Reading the spte while an update is in progress may get the old value
388 * for the high part of the spte. The race is fine for a present->non-present
389 * change (because the high part of the spte is ignored for non-present spte),
390 * but for a present->present change we must reread the spte.
392 * All such changes are done in two steps (present->non-present and
393 * non-present->present), hence it is enough to count the number of
394 * present->non-present updates: if it changed while reading the spte,
395 * we might have hit the race. This is done using clear_spte_count.
397 static u64 __get_spte_lockless(u64 *sptep)
399 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
400 union split_spte spte, *orig = (union split_spte *)sptep;
404 count = sp->clear_spte_count;
407 spte.spte_low = orig->spte_low;
410 spte.spte_high = orig->spte_high;
413 if (unlikely(spte.spte_low != orig->spte_low ||
414 count != sp->clear_spte_count))
421 static bool spte_has_volatile_bits(u64 spte)
423 if (!is_shadow_present_pte(spte))
427 * Always atomically update spte if it can be updated
428 * out of mmu-lock, it can ensure dirty bit is not lost,
429 * also, it can help us to get a stable is_writable_pte()
430 * to ensure tlb flush is not missed.
432 if (spte_can_locklessly_be_made_writable(spte) ||
433 is_access_track_spte(spte))
436 if (spte_ad_enabled(spte)) {
437 if ((spte & shadow_accessed_mask) == 0 ||
438 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
445 /* Rules for using mmu_spte_set:
446 * Set the sptep from nonpresent to present.
447 * Note: the sptep being assigned *must* be either not present
448 * or in a state where the hardware will not attempt to update
451 static void mmu_spte_set(u64 *sptep, u64 new_spte)
453 WARN_ON(is_shadow_present_pte(*sptep));
454 __set_spte(sptep, new_spte);
458 * Update the SPTE (excluding the PFN), but do not track changes in its
459 * accessed/dirty status.
461 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
463 u64 old_spte = *sptep;
465 WARN_ON(!is_shadow_present_pte(new_spte));
467 if (!is_shadow_present_pte(old_spte)) {
468 mmu_spte_set(sptep, new_spte);
472 if (!spte_has_volatile_bits(old_spte))
473 __update_clear_spte_fast(sptep, new_spte);
475 old_spte = __update_clear_spte_slow(sptep, new_spte);
477 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
482 /* Rules for using mmu_spte_update:
483 * Update the state bits, it means the mapped pfn is not changed.
485 * Whenever we overwrite a writable spte with a read-only one we
486 * should flush remote TLBs. Otherwise rmap_write_protect
487 * will find a read-only spte, even though the writable spte
488 * might be cached on a CPU's TLB, the return value indicates this
491 * Returns true if the TLB needs to be flushed
493 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
496 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
498 if (!is_shadow_present_pte(old_spte))
502 * For the spte updated out of mmu-lock is safe, since
503 * we always atomically update it, see the comments in
504 * spte_has_volatile_bits().
506 if (spte_can_locklessly_be_made_writable(old_spte) &&
507 !is_writable_pte(new_spte))
511 * Flush TLB when accessed/dirty states are changed in the page tables,
512 * to guarantee consistency between TLB and page tables.
515 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
517 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
520 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
522 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
529 * Rules for using mmu_spte_clear_track_bits:
530 * It sets the sptep from present to nonpresent, and track the
531 * state bits, it is used to clear the last level sptep.
532 * Returns non-zero if the PTE was previously valid.
534 static int mmu_spte_clear_track_bits(u64 *sptep)
537 u64 old_spte = *sptep;
539 if (!spte_has_volatile_bits(old_spte))
540 __update_clear_spte_fast(sptep, 0ull);
542 old_spte = __update_clear_spte_slow(sptep, 0ull);
544 if (!is_shadow_present_pte(old_spte))
547 pfn = spte_to_pfn(old_spte);
550 * KVM does not hold the refcount of the page used by
551 * kvm mmu, before reclaiming the page, we should
552 * unmap it from mmu first.
554 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
556 if (is_accessed_spte(old_spte))
557 kvm_set_pfn_accessed(pfn);
559 if (is_dirty_spte(old_spte))
560 kvm_set_pfn_dirty(pfn);
566 * Rules for using mmu_spte_clear_no_track:
567 * Directly clear spte without caring the state bits of sptep,
568 * it is used to set the upper level spte.
570 static void mmu_spte_clear_no_track(u64 *sptep)
572 __update_clear_spte_fast(sptep, 0ull);
575 static u64 mmu_spte_get_lockless(u64 *sptep)
577 return __get_spte_lockless(sptep);
580 /* Restore an acc-track PTE back to a regular PTE */
581 static u64 restore_acc_track_spte(u64 spte)
584 u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
585 & SHADOW_ACC_TRACK_SAVED_BITS_MASK;
587 WARN_ON_ONCE(spte_ad_enabled(spte));
588 WARN_ON_ONCE(!is_access_track_spte(spte));
590 new_spte &= ~shadow_acc_track_mask;
591 new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
592 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
593 new_spte |= saved_bits;
598 /* Returns the Accessed status of the PTE and resets it at the same time. */
599 static bool mmu_spte_age(u64 *sptep)
601 u64 spte = mmu_spte_get_lockless(sptep);
603 if (!is_accessed_spte(spte))
606 if (spte_ad_enabled(spte)) {
607 clear_bit((ffs(shadow_accessed_mask) - 1),
608 (unsigned long *)sptep);
611 * Capture the dirty status of the page, so that it doesn't get
612 * lost when the SPTE is marked for access tracking.
614 if (is_writable_pte(spte))
615 kvm_set_pfn_dirty(spte_to_pfn(spte));
617 spte = mark_spte_for_access_track(spte);
618 mmu_spte_update_no_track(sptep, spte);
624 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
627 * Prevent page table teardown by making any free-er wait during
628 * kvm_flush_remote_tlbs() IPI to all active vcpus.
633 * Make sure a following spte read is not reordered ahead of the write
636 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
639 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
642 * Make sure the write to vcpu->mode is not reordered in front of
643 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
644 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
646 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
650 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
654 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
655 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
656 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
659 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
660 PT64_ROOT_MAX_LEVEL);
663 if (maybe_indirect) {
664 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
665 PT64_ROOT_MAX_LEVEL);
669 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
670 PT64_ROOT_MAX_LEVEL);
673 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
675 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
676 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
677 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
678 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
681 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
683 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
686 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
688 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
691 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
693 if (!sp->role.direct)
694 return sp->gfns[index];
696 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
699 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
701 if (!sp->role.direct) {
702 sp->gfns[index] = gfn;
706 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
707 pr_err_ratelimited("gfn mismatch under direct page %llx "
708 "(expected %llx, got %llx)\n",
710 kvm_mmu_page_get_gfn(sp, index), gfn);
714 * Return the pointer to the large page information for a given gfn,
715 * handling slots that are not large page aligned.
717 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
718 struct kvm_memory_slot *slot,
723 idx = gfn_to_index(gfn, slot->base_gfn, level);
724 return &slot->arch.lpage_info[level - 2][idx];
727 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
728 gfn_t gfn, int count)
730 struct kvm_lpage_info *linfo;
733 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
734 linfo = lpage_info_slot(gfn, slot, i);
735 linfo->disallow_lpage += count;
736 WARN_ON(linfo->disallow_lpage < 0);
740 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
742 update_gfn_disallow_lpage_count(slot, gfn, 1);
745 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
747 update_gfn_disallow_lpage_count(slot, gfn, -1);
750 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
752 struct kvm_memslots *slots;
753 struct kvm_memory_slot *slot;
756 kvm->arch.indirect_shadow_pages++;
758 slots = kvm_memslots_for_spte_role(kvm, sp->role);
759 slot = __gfn_to_memslot(slots, gfn);
761 /* the non-leaf shadow pages are keeping readonly. */
762 if (sp->role.level > PG_LEVEL_4K)
763 return kvm_slot_page_track_add_page(kvm, slot, gfn,
764 KVM_PAGE_TRACK_WRITE);
766 kvm_mmu_gfn_disallow_lpage(slot, gfn);
769 void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
771 if (sp->lpage_disallowed)
774 ++kvm->stat.nx_lpage_splits;
775 list_add_tail(&sp->lpage_disallowed_link,
776 &kvm->arch.lpage_disallowed_mmu_pages);
777 sp->lpage_disallowed = true;
780 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
782 struct kvm_memslots *slots;
783 struct kvm_memory_slot *slot;
786 kvm->arch.indirect_shadow_pages--;
788 slots = kvm_memslots_for_spte_role(kvm, sp->role);
789 slot = __gfn_to_memslot(slots, gfn);
790 if (sp->role.level > PG_LEVEL_4K)
791 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
792 KVM_PAGE_TRACK_WRITE);
794 kvm_mmu_gfn_allow_lpage(slot, gfn);
797 void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
799 --kvm->stat.nx_lpage_splits;
800 sp->lpage_disallowed = false;
801 list_del(&sp->lpage_disallowed_link);
804 static struct kvm_memory_slot *
805 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
808 struct kvm_memory_slot *slot;
810 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
811 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
813 if (no_dirty_log && kvm_slot_dirty_track_enabled(slot))
820 * About rmap_head encoding:
822 * If the bit zero of rmap_head->val is clear, then it points to the only spte
823 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
824 * pte_list_desc containing more mappings.
828 * Returns the number of pointers in the rmap chain, not counting the new one.
830 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
831 struct kvm_rmap_head *rmap_head)
833 struct pte_list_desc *desc;
836 if (!rmap_head->val) {
837 rmap_printk("%p %llx 0->1\n", spte, *spte);
838 rmap_head->val = (unsigned long)spte;
839 } else if (!(rmap_head->val & 1)) {
840 rmap_printk("%p %llx 1->many\n", spte, *spte);
841 desc = mmu_alloc_pte_list_desc(vcpu);
842 desc->sptes[0] = (u64 *)rmap_head->val;
843 desc->sptes[1] = spte;
844 rmap_head->val = (unsigned long)desc | 1;
847 rmap_printk("%p %llx many->many\n", spte, *spte);
848 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
849 while (desc->sptes[PTE_LIST_EXT-1]) {
850 count += PTE_LIST_EXT;
853 desc->more = mmu_alloc_pte_list_desc(vcpu);
859 for (i = 0; desc->sptes[i]; ++i)
861 desc->sptes[i] = spte;
867 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
868 struct pte_list_desc *desc, int i,
869 struct pte_list_desc *prev_desc)
873 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
875 desc->sptes[i] = desc->sptes[j];
876 desc->sptes[j] = NULL;
879 if (!prev_desc && !desc->more)
883 prev_desc->more = desc->more;
885 rmap_head->val = (unsigned long)desc->more | 1;
886 mmu_free_pte_list_desc(desc);
889 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
891 struct pte_list_desc *desc;
892 struct pte_list_desc *prev_desc;
895 if (!rmap_head->val) {
896 pr_err("%s: %p 0->BUG\n", __func__, spte);
898 } else if (!(rmap_head->val & 1)) {
899 rmap_printk("%p 1->0\n", spte);
900 if ((u64 *)rmap_head->val != spte) {
901 pr_err("%s: %p 1->BUG\n", __func__, spte);
906 rmap_printk("%p many->many\n", spte);
907 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
910 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
911 if (desc->sptes[i] == spte) {
912 pte_list_desc_remove_entry(rmap_head,
920 pr_err("%s: %p many->many\n", __func__, spte);
925 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
927 mmu_spte_clear_track_bits(sptep);
928 __pte_list_remove(sptep, rmap_head);
931 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
932 struct kvm_memory_slot *slot)
936 idx = gfn_to_index(gfn, slot->base_gfn, level);
937 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
940 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
941 struct kvm_mmu_page *sp)
943 struct kvm_memslots *slots;
944 struct kvm_memory_slot *slot;
946 slots = kvm_memslots_for_spte_role(kvm, sp->role);
947 slot = __gfn_to_memslot(slots, gfn);
948 return __gfn_to_rmap(gfn, sp->role.level, slot);
951 static bool rmap_can_add(struct kvm_vcpu *vcpu)
953 struct kvm_mmu_memory_cache *mc;
955 mc = &vcpu->arch.mmu_pte_list_desc_cache;
956 return kvm_mmu_memory_cache_nr_free_objects(mc);
959 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
961 struct kvm_mmu_page *sp;
962 struct kvm_rmap_head *rmap_head;
964 sp = sptep_to_sp(spte);
965 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
966 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
967 return pte_list_add(vcpu, spte, rmap_head);
970 static void rmap_remove(struct kvm *kvm, u64 *spte)
972 struct kvm_mmu_page *sp;
974 struct kvm_rmap_head *rmap_head;
976 sp = sptep_to_sp(spte);
977 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
978 rmap_head = gfn_to_rmap(kvm, gfn, sp);
979 __pte_list_remove(spte, rmap_head);
983 * Used by the following functions to iterate through the sptes linked by a
984 * rmap. All fields are private and not assumed to be used outside.
986 struct rmap_iterator {
988 struct pte_list_desc *desc; /* holds the sptep if not NULL */
989 int pos; /* index of the sptep */
993 * Iteration must be started by this function. This should also be used after
994 * removing/dropping sptes from the rmap link because in such cases the
995 * information in the iterator may not be valid.
997 * Returns sptep if found, NULL otherwise.
999 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1000 struct rmap_iterator *iter)
1004 if (!rmap_head->val)
1007 if (!(rmap_head->val & 1)) {
1009 sptep = (u64 *)rmap_head->val;
1013 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1015 sptep = iter->desc->sptes[iter->pos];
1017 BUG_ON(!is_shadow_present_pte(*sptep));
1022 * Must be used with a valid iterator: e.g. after rmap_get_first().
1024 * Returns sptep if found, NULL otherwise.
1026 static u64 *rmap_get_next(struct rmap_iterator *iter)
1031 if (iter->pos < PTE_LIST_EXT - 1) {
1033 sptep = iter->desc->sptes[iter->pos];
1038 iter->desc = iter->desc->more;
1042 /* desc->sptes[0] cannot be NULL */
1043 sptep = iter->desc->sptes[iter->pos];
1050 BUG_ON(!is_shadow_present_pte(*sptep));
1054 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1055 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1056 _spte_; _spte_ = rmap_get_next(_iter_))
1058 static void drop_spte(struct kvm *kvm, u64 *sptep)
1060 if (mmu_spte_clear_track_bits(sptep))
1061 rmap_remove(kvm, sptep);
1065 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1067 if (is_large_pte(*sptep)) {
1068 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1069 drop_spte(kvm, sptep);
1077 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1079 if (__drop_large_spte(vcpu->kvm, sptep)) {
1080 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1082 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1083 KVM_PAGES_PER_HPAGE(sp->role.level));
1088 * Write-protect on the specified @sptep, @pt_protect indicates whether
1089 * spte write-protection is caused by protecting shadow page table.
1091 * Note: write protection is difference between dirty logging and spte
1093 * - for dirty logging, the spte can be set to writable at anytime if
1094 * its dirty bitmap is properly set.
1095 * - for spte protection, the spte can be writable only after unsync-ing
1098 * Return true if tlb need be flushed.
1100 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1104 if (!is_writable_pte(spte) &&
1105 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1108 rmap_printk("spte %p %llx\n", sptep, *sptep);
1111 spte &= ~shadow_mmu_writable_mask;
1112 spte = spte & ~PT_WRITABLE_MASK;
1114 return mmu_spte_update(sptep, spte);
1117 static bool __rmap_write_protect(struct kvm *kvm,
1118 struct kvm_rmap_head *rmap_head,
1122 struct rmap_iterator iter;
1125 for_each_rmap_spte(rmap_head, &iter, sptep)
1126 flush |= spte_write_protect(sptep, pt_protect);
1131 static bool spte_clear_dirty(u64 *sptep)
1135 rmap_printk("spte %p %llx\n", sptep, *sptep);
1137 MMU_WARN_ON(!spte_ad_enabled(spte));
1138 spte &= ~shadow_dirty_mask;
1139 return mmu_spte_update(sptep, spte);
1142 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1144 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1145 (unsigned long *)sptep);
1146 if (was_writable && !spte_ad_enabled(*sptep))
1147 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1149 return was_writable;
1153 * Gets the GFN ready for another round of dirty logging by clearing the
1154 * - D bit on ad-enabled SPTEs, and
1155 * - W bit on ad-disabled SPTEs.
1156 * Returns true iff any D or W bits were cleared.
1158 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1159 struct kvm_memory_slot *slot)
1162 struct rmap_iterator iter;
1165 for_each_rmap_spte(rmap_head, &iter, sptep)
1166 if (spte_ad_need_write_protect(*sptep))
1167 flush |= spte_wrprot_for_clear_dirty(sptep);
1169 flush |= spte_clear_dirty(sptep);
1175 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1176 * @kvm: kvm instance
1177 * @slot: slot to protect
1178 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1179 * @mask: indicates which pages we should protect
1181 * Used when we do not need to care about huge page mappings: e.g. during dirty
1182 * logging we do not have any such mappings.
1184 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1185 struct kvm_memory_slot *slot,
1186 gfn_t gfn_offset, unsigned long mask)
1188 struct kvm_rmap_head *rmap_head;
1190 if (is_tdp_mmu_enabled(kvm))
1191 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1192 slot->base_gfn + gfn_offset, mask, true);
1194 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1196 __rmap_write_protect(kvm, rmap_head, false);
1198 /* clear the first set bit */
1204 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1205 * protect the page if the D-bit isn't supported.
1206 * @kvm: kvm instance
1207 * @slot: slot to clear D-bit
1208 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1209 * @mask: indicates which pages we should clear D-bit
1211 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1213 static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1214 struct kvm_memory_slot *slot,
1215 gfn_t gfn_offset, unsigned long mask)
1217 struct kvm_rmap_head *rmap_head;
1219 if (is_tdp_mmu_enabled(kvm))
1220 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1221 slot->base_gfn + gfn_offset, mask, false);
1223 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1225 __rmap_clear_dirty(kvm, rmap_head, slot);
1227 /* clear the first set bit */
1233 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1236 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1237 * enable dirty logging for them.
1239 * Used when we do not need to care about huge page mappings: e.g. during dirty
1240 * logging we do not have any such mappings.
1242 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1243 struct kvm_memory_slot *slot,
1244 gfn_t gfn_offset, unsigned long mask)
1246 if (kvm_x86_ops.cpu_dirty_log_size)
1247 kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask);
1249 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1252 int kvm_cpu_dirty_log_size(void)
1254 return kvm_x86_ops.cpu_dirty_log_size;
1257 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1258 struct kvm_memory_slot *slot, u64 gfn)
1260 struct kvm_rmap_head *rmap_head;
1262 bool write_protected = false;
1264 for (i = PG_LEVEL_4K; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1265 rmap_head = __gfn_to_rmap(gfn, i, slot);
1266 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1269 if (is_tdp_mmu_enabled(kvm))
1271 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn);
1273 return write_protected;
1276 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1278 struct kvm_memory_slot *slot;
1280 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1281 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1284 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1285 struct kvm_memory_slot *slot)
1288 struct rmap_iterator iter;
1291 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1292 rmap_printk("spte %p %llx.\n", sptep, *sptep);
1294 pte_list_remove(rmap_head, sptep);
1301 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1302 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1305 return kvm_zap_rmapp(kvm, rmap_head, slot);
1308 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1309 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1313 struct rmap_iterator iter;
1316 pte_t *ptep = (pte_t *)data;
1319 WARN_ON(pte_huge(*ptep));
1320 new_pfn = pte_pfn(*ptep);
1323 for_each_rmap_spte(rmap_head, &iter, sptep) {
1324 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1325 sptep, *sptep, gfn, level);
1329 if (pte_write(*ptep)) {
1330 pte_list_remove(rmap_head, sptep);
1333 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1336 mmu_spte_clear_track_bits(sptep);
1337 mmu_spte_set(sptep, new_spte);
1341 if (need_flush && kvm_available_flush_tlb_with_range()) {
1342 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1349 struct slot_rmap_walk_iterator {
1351 struct kvm_memory_slot *slot;
1357 /* output fields. */
1359 struct kvm_rmap_head *rmap;
1362 /* private field. */
1363 struct kvm_rmap_head *end_rmap;
1367 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1369 iterator->level = level;
1370 iterator->gfn = iterator->start_gfn;
1371 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1372 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1377 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1378 struct kvm_memory_slot *slot, int start_level,
1379 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1381 iterator->slot = slot;
1382 iterator->start_level = start_level;
1383 iterator->end_level = end_level;
1384 iterator->start_gfn = start_gfn;
1385 iterator->end_gfn = end_gfn;
1387 rmap_walk_init_level(iterator, iterator->start_level);
1390 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1392 return !!iterator->rmap;
1395 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1397 if (++iterator->rmap <= iterator->end_rmap) {
1398 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1402 if (++iterator->level > iterator->end_level) {
1403 iterator->rmap = NULL;
1407 rmap_walk_init_level(iterator, iterator->level);
1410 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1411 _start_gfn, _end_gfn, _iter_) \
1412 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1413 _end_level_, _start_gfn, _end_gfn); \
1414 slot_rmap_walk_okay(_iter_); \
1415 slot_rmap_walk_next(_iter_))
1417 typedef int (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1418 struct kvm_memory_slot *slot, gfn_t gfn,
1419 int level, unsigned long data);
1421 static __always_inline int kvm_handle_hva_range(struct kvm *kvm,
1422 unsigned long start,
1425 rmap_handler_t handler)
1427 struct kvm_memslots *slots;
1428 struct kvm_memory_slot *memslot;
1429 struct slot_rmap_walk_iterator iterator;
1433 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1434 slots = __kvm_memslots(kvm, i);
1435 kvm_for_each_memslot(memslot, slots) {
1436 unsigned long hva_start, hva_end;
1437 gfn_t gfn_start, gfn_end;
1439 hva_start = max(start, memslot->userspace_addr);
1440 hva_end = min(end, memslot->userspace_addr +
1441 (memslot->npages << PAGE_SHIFT));
1442 if (hva_start >= hva_end)
1445 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1446 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1448 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1449 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1451 for_each_slot_rmap_range(memslot, PG_LEVEL_4K,
1452 KVM_MAX_HUGEPAGE_LEVEL,
1453 gfn_start, gfn_end - 1,
1455 ret |= handler(kvm, iterator.rmap, memslot,
1456 iterator.gfn, iterator.level, data);
1463 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1464 unsigned long data, rmap_handler_t handler)
1466 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1469 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end,
1474 r = kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1476 if (is_tdp_mmu_enabled(kvm))
1477 r |= kvm_tdp_mmu_zap_hva_range(kvm, start, end);
1482 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1486 r = kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1488 if (is_tdp_mmu_enabled(kvm))
1489 r |= kvm_tdp_mmu_set_spte_hva(kvm, hva, &pte);
1494 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1495 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1499 struct rmap_iterator iter;
1502 for_each_rmap_spte(rmap_head, &iter, sptep)
1503 young |= mmu_spte_age(sptep);
1508 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1509 struct kvm_memory_slot *slot, gfn_t gfn,
1510 int level, unsigned long data)
1513 struct rmap_iterator iter;
1515 for_each_rmap_spte(rmap_head, &iter, sptep)
1516 if (is_accessed_spte(*sptep))
1521 #define RMAP_RECYCLE_THRESHOLD 1000
1523 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1525 struct kvm_rmap_head *rmap_head;
1526 struct kvm_mmu_page *sp;
1528 sp = sptep_to_sp(spte);
1530 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1532 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1533 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1534 KVM_PAGES_PER_HPAGE(sp->role.level));
1537 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1541 young = kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1542 if (is_tdp_mmu_enabled(kvm))
1543 young |= kvm_tdp_mmu_age_hva_range(kvm, start, end);
1548 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1552 young = kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1553 if (is_tdp_mmu_enabled(kvm))
1554 young |= kvm_tdp_mmu_test_age_hva(kvm, hva);
1560 static int is_empty_shadow_page(u64 *spt)
1565 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1566 if (is_shadow_present_pte(*pos)) {
1567 printk(KERN_ERR "%s: %p %llx\n", __func__,
1576 * This value is the sum of all of the kvm instances's
1577 * kvm->arch.n_used_mmu_pages values. We need a global,
1578 * aggregate version in order to make the slab shrinker
1581 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
1583 kvm->arch.n_used_mmu_pages += nr;
1584 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1587 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1589 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1590 hlist_del(&sp->hash_link);
1591 list_del(&sp->link);
1592 free_page((unsigned long)sp->spt);
1593 if (!sp->role.direct)
1594 free_page((unsigned long)sp->gfns);
1595 kmem_cache_free(mmu_page_header_cache, sp);
1598 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1600 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1603 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1604 struct kvm_mmu_page *sp, u64 *parent_pte)
1609 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1612 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1615 __pte_list_remove(parent_pte, &sp->parent_ptes);
1618 static void drop_parent_pte(struct kvm_mmu_page *sp,
1621 mmu_page_remove_parent_pte(sp, parent_pte);
1622 mmu_spte_clear_no_track(parent_pte);
1625 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1627 struct kvm_mmu_page *sp;
1629 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1630 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1632 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1633 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1636 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1637 * depends on valid pages being added to the head of the list. See
1638 * comments in kvm_zap_obsolete_pages().
1640 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1641 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1642 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1646 static void mark_unsync(u64 *spte);
1647 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1650 struct rmap_iterator iter;
1652 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1657 static void mark_unsync(u64 *spte)
1659 struct kvm_mmu_page *sp;
1662 sp = sptep_to_sp(spte);
1663 index = spte - sp->spt;
1664 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1666 if (sp->unsync_children++)
1668 kvm_mmu_mark_parents_unsync(sp);
1671 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1672 struct kvm_mmu_page *sp)
1677 #define KVM_PAGE_ARRAY_NR 16
1679 struct kvm_mmu_pages {
1680 struct mmu_page_and_offset {
1681 struct kvm_mmu_page *sp;
1683 } page[KVM_PAGE_ARRAY_NR];
1687 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1693 for (i=0; i < pvec->nr; i++)
1694 if (pvec->page[i].sp == sp)
1697 pvec->page[pvec->nr].sp = sp;
1698 pvec->page[pvec->nr].idx = idx;
1700 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1703 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1705 --sp->unsync_children;
1706 WARN_ON((int)sp->unsync_children < 0);
1707 __clear_bit(idx, sp->unsync_child_bitmap);
1710 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1711 struct kvm_mmu_pages *pvec)
1713 int i, ret, nr_unsync_leaf = 0;
1715 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1716 struct kvm_mmu_page *child;
1717 u64 ent = sp->spt[i];
1719 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1720 clear_unsync_child_bit(sp, i);
1724 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1726 if (child->unsync_children) {
1727 if (mmu_pages_add(pvec, child, i))
1730 ret = __mmu_unsync_walk(child, pvec);
1732 clear_unsync_child_bit(sp, i);
1734 } else if (ret > 0) {
1735 nr_unsync_leaf += ret;
1738 } else if (child->unsync) {
1740 if (mmu_pages_add(pvec, child, i))
1743 clear_unsync_child_bit(sp, i);
1746 return nr_unsync_leaf;
1749 #define INVALID_INDEX (-1)
1751 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1752 struct kvm_mmu_pages *pvec)
1755 if (!sp->unsync_children)
1758 mmu_pages_add(pvec, sp, INVALID_INDEX);
1759 return __mmu_unsync_walk(sp, pvec);
1762 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1764 WARN_ON(!sp->unsync);
1765 trace_kvm_mmu_sync_page(sp);
1767 --kvm->stat.mmu_unsync;
1770 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1771 struct list_head *invalid_list);
1772 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1773 struct list_head *invalid_list);
1775 #define for_each_valid_sp(_kvm, _sp, _list) \
1776 hlist_for_each_entry(_sp, _list, hash_link) \
1777 if (is_obsolete_sp((_kvm), (_sp))) { \
1780 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1781 for_each_valid_sp(_kvm, _sp, \
1782 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1783 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1785 static inline bool is_ept_sp(struct kvm_mmu_page *sp)
1787 return sp->role.cr0_wp && sp->role.smap_andnot_wp;
1790 /* @sp->gfn should be write-protected at the call site */
1791 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1792 struct list_head *invalid_list)
1794 if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) ||
1795 vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
1796 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1803 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1804 struct list_head *invalid_list,
1807 if (!remote_flush && list_empty(invalid_list))
1810 if (!list_empty(invalid_list))
1811 kvm_mmu_commit_zap_page(kvm, invalid_list);
1813 kvm_flush_remote_tlbs(kvm);
1817 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1818 struct list_head *invalid_list,
1819 bool remote_flush, bool local_flush)
1821 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
1825 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1828 #ifdef CONFIG_KVM_MMU_AUDIT
1829 #include "mmu_audit.c"
1831 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1832 static void mmu_audit_disable(void) { }
1835 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1837 return sp->role.invalid ||
1838 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1841 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1842 struct list_head *invalid_list)
1844 kvm_unlink_unsync_page(vcpu->kvm, sp);
1845 return __kvm_sync_page(vcpu, sp, invalid_list);
1848 /* @gfn should be write-protected at the call site */
1849 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
1850 struct list_head *invalid_list)
1852 struct kvm_mmu_page *s;
1855 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1859 WARN_ON(s->role.level != PG_LEVEL_4K);
1860 ret |= kvm_sync_page(vcpu, s, invalid_list);
1866 struct mmu_page_path {
1867 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1868 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1871 #define for_each_sp(pvec, sp, parents, i) \
1872 for (i = mmu_pages_first(&pvec, &parents); \
1873 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1874 i = mmu_pages_next(&pvec, &parents, i))
1876 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1877 struct mmu_page_path *parents,
1882 for (n = i+1; n < pvec->nr; n++) {
1883 struct kvm_mmu_page *sp = pvec->page[n].sp;
1884 unsigned idx = pvec->page[n].idx;
1885 int level = sp->role.level;
1887 parents->idx[level-1] = idx;
1888 if (level == PG_LEVEL_4K)
1891 parents->parent[level-2] = sp;
1897 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1898 struct mmu_page_path *parents)
1900 struct kvm_mmu_page *sp;
1906 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1908 sp = pvec->page[0].sp;
1909 level = sp->role.level;
1910 WARN_ON(level == PG_LEVEL_4K);
1912 parents->parent[level-2] = sp;
1914 /* Also set up a sentinel. Further entries in pvec are all
1915 * children of sp, so this element is never overwritten.
1917 parents->parent[level-1] = NULL;
1918 return mmu_pages_next(pvec, parents, 0);
1921 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1923 struct kvm_mmu_page *sp;
1924 unsigned int level = 0;
1927 unsigned int idx = parents->idx[level];
1928 sp = parents->parent[level];
1932 WARN_ON(idx == INVALID_INDEX);
1933 clear_unsync_child_bit(sp, idx);
1935 } while (!sp->unsync_children);
1938 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1939 struct kvm_mmu_page *parent)
1942 struct kvm_mmu_page *sp;
1943 struct mmu_page_path parents;
1944 struct kvm_mmu_pages pages;
1945 LIST_HEAD(invalid_list);
1948 while (mmu_unsync_walk(parent, &pages)) {
1949 bool protected = false;
1951 for_each_sp(pages, sp, parents, i)
1952 protected |= rmap_write_protect(vcpu, sp->gfn);
1955 kvm_flush_remote_tlbs(vcpu->kvm);
1959 for_each_sp(pages, sp, parents, i) {
1960 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
1961 mmu_pages_clear_parents(&parents);
1963 if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) {
1964 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1965 cond_resched_rwlock_write(&vcpu->kvm->mmu_lock);
1970 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1973 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1975 atomic_set(&sp->write_flooding_count, 0);
1978 static void clear_sp_write_flooding_count(u64 *spte)
1980 __clear_sp_write_flooding_count(sptep_to_sp(spte));
1983 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1988 unsigned int access)
1990 bool direct_mmu = vcpu->arch.mmu->direct_map;
1991 union kvm_mmu_page_role role;
1992 struct hlist_head *sp_list;
1994 struct kvm_mmu_page *sp;
1995 bool need_sync = false;
1998 LIST_HEAD(invalid_list);
2000 role = vcpu->arch.mmu->mmu_role.base;
2002 role.direct = direct;
2004 role.gpte_is_8_bytes = true;
2005 role.access = access;
2006 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2007 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2008 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2009 role.quadrant = quadrant;
2012 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2013 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2014 if (sp->gfn != gfn) {
2019 if (!need_sync && sp->unsync)
2022 if (sp->role.word != role.word)
2026 goto trace_get_page;
2029 /* The page is good, but __kvm_sync_page might still end
2030 * up zapping it. If so, break in order to rebuild it.
2032 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2035 WARN_ON(!list_empty(&invalid_list));
2036 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2039 if (sp->unsync_children)
2040 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2042 __clear_sp_write_flooding_count(sp);
2045 trace_kvm_mmu_get_page(sp, false);
2049 ++vcpu->kvm->stat.mmu_cache_miss;
2051 sp = kvm_mmu_alloc_page(vcpu, direct);
2055 hlist_add_head(&sp->hash_link, sp_list);
2058 * we should do write protection before syncing pages
2059 * otherwise the content of the synced shadow page may
2060 * be inconsistent with guest page table.
2062 account_shadowed(vcpu->kvm, sp);
2063 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2064 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2066 if (level > PG_LEVEL_4K && need_sync)
2067 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2069 trace_kvm_mmu_get_page(sp, true);
2071 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2073 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2074 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2078 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2079 struct kvm_vcpu *vcpu, hpa_t root,
2082 iterator->addr = addr;
2083 iterator->shadow_addr = root;
2084 iterator->level = vcpu->arch.mmu->shadow_root_level;
2086 if (iterator->level == PT64_ROOT_4LEVEL &&
2087 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2088 !vcpu->arch.mmu->direct_map)
2091 if (iterator->level == PT32E_ROOT_LEVEL) {
2093 * prev_root is currently only used for 64-bit hosts. So only
2094 * the active root_hpa is valid here.
2096 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2098 iterator->shadow_addr
2099 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2100 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2102 if (!iterator->shadow_addr)
2103 iterator->level = 0;
2107 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2108 struct kvm_vcpu *vcpu, u64 addr)
2110 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2114 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2116 if (iterator->level < PG_LEVEL_4K)
2119 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2120 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2124 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2127 if (is_last_spte(spte, iterator->level)) {
2128 iterator->level = 0;
2132 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2136 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2138 __shadow_walk_next(iterator, *iterator->sptep);
2141 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2142 struct kvm_mmu_page *sp)
2146 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2148 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2150 mmu_spte_set(sptep, spte);
2152 mmu_page_add_parent_pte(vcpu, sp, sptep);
2154 if (sp->unsync_children || sp->unsync)
2158 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2159 unsigned direct_access)
2161 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2162 struct kvm_mmu_page *child;
2165 * For the direct sp, if the guest pte's dirty bit
2166 * changed form clean to dirty, it will corrupt the
2167 * sp's access: allow writable in the read-only sp,
2168 * so we should update the spte at this point to get
2169 * a new sp with the correct access.
2171 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2172 if (child->role.access == direct_access)
2175 drop_parent_pte(child, sptep);
2176 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2180 /* Returns the number of zapped non-leaf child shadow pages. */
2181 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2182 u64 *spte, struct list_head *invalid_list)
2185 struct kvm_mmu_page *child;
2188 if (is_shadow_present_pte(pte)) {
2189 if (is_last_spte(pte, sp->role.level)) {
2190 drop_spte(kvm, spte);
2191 if (is_large_pte(pte))
2194 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2195 drop_parent_pte(child, spte);
2198 * Recursively zap nested TDP SPs, parentless SPs are
2199 * unlikely to be used again in the near future. This
2200 * avoids retaining a large number of stale nested SPs.
2202 if (tdp_enabled && invalid_list &&
2203 child->role.guest_mode && !child->parent_ptes.val)
2204 return kvm_mmu_prepare_zap_page(kvm, child,
2207 } else if (is_mmio_spte(pte)) {
2208 mmu_spte_clear_no_track(spte);
2213 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2214 struct kvm_mmu_page *sp,
2215 struct list_head *invalid_list)
2220 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2221 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2226 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2229 struct rmap_iterator iter;
2231 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2232 drop_parent_pte(sp, sptep);
2235 static int mmu_zap_unsync_children(struct kvm *kvm,
2236 struct kvm_mmu_page *parent,
2237 struct list_head *invalid_list)
2240 struct mmu_page_path parents;
2241 struct kvm_mmu_pages pages;
2243 if (parent->role.level == PG_LEVEL_4K)
2246 while (mmu_unsync_walk(parent, &pages)) {
2247 struct kvm_mmu_page *sp;
2249 for_each_sp(pages, sp, parents, i) {
2250 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2251 mmu_pages_clear_parents(&parents);
2259 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2260 struct kvm_mmu_page *sp,
2261 struct list_head *invalid_list,
2266 trace_kvm_mmu_prepare_zap_page(sp);
2267 ++kvm->stat.mmu_shadow_zapped;
2268 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2269 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2270 kvm_mmu_unlink_parents(kvm, sp);
2272 /* Zapping children means active_mmu_pages has become unstable. */
2273 list_unstable = *nr_zapped;
2275 if (!sp->role.invalid && !sp->role.direct)
2276 unaccount_shadowed(kvm, sp);
2279 kvm_unlink_unsync_page(kvm, sp);
2280 if (!sp->root_count) {
2285 * Already invalid pages (previously active roots) are not on
2286 * the active page list. See list_del() in the "else" case of
2289 if (sp->role.invalid)
2290 list_add(&sp->link, invalid_list);
2292 list_move(&sp->link, invalid_list);
2293 kvm_mod_used_mmu_pages(kvm, -1);
2296 * Remove the active root from the active page list, the root
2297 * will be explicitly freed when the root_count hits zero.
2299 list_del(&sp->link);
2302 * Obsolete pages cannot be used on any vCPUs, see the comment
2303 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2304 * treats invalid shadow pages as being obsolete.
2306 if (!is_obsolete_sp(kvm, sp))
2307 kvm_reload_remote_mmus(kvm);
2310 if (sp->lpage_disallowed)
2311 unaccount_huge_nx_page(kvm, sp);
2313 sp->role.invalid = 1;
2314 return list_unstable;
2317 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2318 struct list_head *invalid_list)
2322 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2326 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2327 struct list_head *invalid_list)
2329 struct kvm_mmu_page *sp, *nsp;
2331 if (list_empty(invalid_list))
2335 * We need to make sure everyone sees our modifications to
2336 * the page tables and see changes to vcpu->mode here. The barrier
2337 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2338 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2340 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2341 * guest mode and/or lockless shadow page table walks.
2343 kvm_flush_remote_tlbs(kvm);
2345 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2346 WARN_ON(!sp->role.invalid || sp->root_count);
2347 kvm_mmu_free_page(sp);
2351 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2352 unsigned long nr_to_zap)
2354 unsigned long total_zapped = 0;
2355 struct kvm_mmu_page *sp, *tmp;
2356 LIST_HEAD(invalid_list);
2360 if (list_empty(&kvm->arch.active_mmu_pages))
2364 list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2366 * Don't zap active root pages, the page itself can't be freed
2367 * and zapping it will just force vCPUs to realloc and reload.
2372 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2374 total_zapped += nr_zapped;
2375 if (total_zapped >= nr_to_zap)
2382 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2384 kvm->stat.mmu_recycled += total_zapped;
2385 return total_zapped;
2388 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2390 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2391 return kvm->arch.n_max_mmu_pages -
2392 kvm->arch.n_used_mmu_pages;
2397 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2399 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2401 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2404 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2407 * Note, this check is intentionally soft, it only guarantees that one
2408 * page is available, while the caller may end up allocating as many as
2409 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2410 * exceeding the (arbitrary by default) limit will not harm the host,
2411 * being too agressive may unnecessarily kill the guest, and getting an
2412 * exact count is far more trouble than it's worth, especially in the
2415 if (!kvm_mmu_available_pages(vcpu->kvm))
2421 * Changing the number of mmu pages allocated to the vm
2422 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2424 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2426 write_lock(&kvm->mmu_lock);
2428 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2429 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2432 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2435 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2437 write_unlock(&kvm->mmu_lock);
2440 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2442 struct kvm_mmu_page *sp;
2443 LIST_HEAD(invalid_list);
2446 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2448 write_lock(&kvm->mmu_lock);
2449 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2450 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2453 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2455 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2456 write_unlock(&kvm->mmu_lock);
2461 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2466 if (vcpu->arch.mmu->direct_map)
2469 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2471 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2476 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2478 trace_kvm_mmu_unsync_page(sp);
2479 ++vcpu->kvm->stat.mmu_unsync;
2482 kvm_mmu_mark_parents_unsync(sp);
2485 bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2488 struct kvm_mmu_page *sp;
2490 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2493 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2500 WARN_ON(sp->role.level != PG_LEVEL_4K);
2501 kvm_unsync_page(vcpu, sp);
2505 * We need to ensure that the marking of unsync pages is visible
2506 * before the SPTE is updated to allow writes because
2507 * kvm_mmu_sync_roots() checks the unsync flags without holding
2508 * the MMU lock and so can race with this. If the SPTE was updated
2509 * before the page had been marked as unsync-ed, something like the
2510 * following could happen:
2513 * ---------------------------------------------------------------------
2514 * 1.2 Host updates SPTE
2516 * 2.1 Guest writes a GPTE for GVA X.
2517 * (GPTE being in the guest page table shadowed
2518 * by the SP from CPU 1.)
2519 * This reads SPTE during the page table walk.
2520 * Since SPTE.W is read as 1, there is no
2523 * 2.2 Guest issues TLB flush.
2524 * That causes a VM Exit.
2526 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2527 * Since it is false, so it just returns.
2529 * 2.4 Guest accesses GVA X.
2530 * Since the mapping in the SP was not updated,
2531 * so the old mapping for GVA X incorrectly
2535 * (sp->unsync = true)
2537 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2538 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2539 * pairs with this write barrier.
2546 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2547 unsigned int pte_access, int level,
2548 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2549 bool can_unsync, bool host_writable)
2552 struct kvm_mmu_page *sp;
2555 sp = sptep_to_sp(sptep);
2557 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2558 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2560 if (spte & PT_WRITABLE_MASK)
2561 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2564 ret |= SET_SPTE_SPURIOUS;
2565 else if (mmu_spte_update(sptep, spte))
2566 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2570 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2571 unsigned int pte_access, bool write_fault, int level,
2572 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2575 int was_rmapped = 0;
2578 int ret = RET_PF_FIXED;
2581 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2582 *sptep, write_fault, gfn);
2584 if (unlikely(is_noslot_pfn(pfn))) {
2585 mark_mmio_spte(vcpu, sptep, gfn, pte_access);
2586 return RET_PF_EMULATE;
2589 if (is_shadow_present_pte(*sptep)) {
2591 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2592 * the parent of the now unreachable PTE.
2594 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2595 struct kvm_mmu_page *child;
2598 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2599 drop_parent_pte(child, sptep);
2601 } else if (pfn != spte_to_pfn(*sptep)) {
2602 pgprintk("hfn old %llx new %llx\n",
2603 spte_to_pfn(*sptep), pfn);
2604 drop_spte(vcpu->kvm, sptep);
2610 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2611 speculative, true, host_writable);
2612 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2614 ret = RET_PF_EMULATE;
2615 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2618 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2619 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2620 KVM_PAGES_PER_HPAGE(level));
2623 * The fault is fully spurious if and only if the new SPTE and old SPTE
2624 * are identical, and emulation is not required.
2626 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2627 WARN_ON_ONCE(!was_rmapped);
2628 return RET_PF_SPURIOUS;
2631 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2632 trace_kvm_mmu_set_spte(level, gfn, sptep);
2633 if (!was_rmapped && is_large_pte(*sptep))
2634 ++vcpu->kvm->stat.lpages;
2636 if (is_shadow_present_pte(*sptep)) {
2638 rmap_count = rmap_add(vcpu, sptep, gfn);
2639 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2640 rmap_recycle(vcpu, sptep, gfn);
2647 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2650 struct kvm_memory_slot *slot;
2652 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2654 return KVM_PFN_ERR_FAULT;
2656 return gfn_to_pfn_memslot_atomic(slot, gfn);
2659 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2660 struct kvm_mmu_page *sp,
2661 u64 *start, u64 *end)
2663 struct page *pages[PTE_PREFETCH_NUM];
2664 struct kvm_memory_slot *slot;
2665 unsigned int access = sp->role.access;
2669 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2670 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2674 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2678 for (i = 0; i < ret; i++, gfn++, start++) {
2679 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2680 page_to_pfn(pages[i]), true, true);
2687 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2688 struct kvm_mmu_page *sp, u64 *sptep)
2690 u64 *spte, *start = NULL;
2693 WARN_ON(!sp->role.direct);
2695 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2698 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2699 if (is_shadow_present_pte(*spte) || spte == sptep) {
2702 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2710 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2712 struct kvm_mmu_page *sp;
2714 sp = sptep_to_sp(sptep);
2717 * Without accessed bits, there's no way to distinguish between
2718 * actually accessed translations and prefetched, so disable pte
2719 * prefetch if accessed bits aren't available.
2721 if (sp_ad_disabled(sp))
2724 if (sp->role.level > PG_LEVEL_4K)
2728 * If addresses are being invalidated, skip prefetching to avoid
2729 * accidentally prefetching those addresses.
2731 if (unlikely(vcpu->kvm->mmu_notifier_count))
2734 __direct_pte_prefetch(vcpu, sp, sptep);
2737 static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
2738 struct kvm_memory_slot *slot)
2744 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2748 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2749 * is not solely for performance, it's also necessary to avoid the
2750 * "writable" check in __gfn_to_hva_many(), which will always fail on
2751 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2752 * page fault steps have already verified the guest isn't writing a
2753 * read-only memslot.
2755 hva = __gfn_to_hva_memslot(slot, gfn);
2757 pte = lookup_address_in_mm(kvm->mm, hva, &level);
2764 int kvm_mmu_max_mapping_level(struct kvm *kvm, struct kvm_memory_slot *slot,
2765 gfn_t gfn, kvm_pfn_t pfn, int max_level)
2767 struct kvm_lpage_info *linfo;
2769 max_level = min(max_level, max_huge_page_level);
2770 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2771 linfo = lpage_info_slot(gfn, slot, max_level);
2772 if (!linfo->disallow_lpage)
2776 if (max_level == PG_LEVEL_4K)
2779 return host_pfn_mapping_level(kvm, gfn, pfn, slot);
2782 int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2783 int max_level, kvm_pfn_t *pfnp,
2784 bool huge_page_disallowed, int *req_level)
2786 struct kvm_memory_slot *slot;
2787 kvm_pfn_t pfn = *pfnp;
2791 *req_level = PG_LEVEL_4K;
2793 if (unlikely(max_level == PG_LEVEL_4K))
2796 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
2799 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2803 level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level);
2804 if (level == PG_LEVEL_4K)
2807 *req_level = level = min(level, max_level);
2810 * Enforce the iTLB multihit workaround after capturing the requested
2811 * level, which will be used to do precise, accurate accounting.
2813 if (huge_page_disallowed)
2817 * mmu_notifier_retry() was successful and mmu_lock is held, so
2818 * the pmd can't be split from under us.
2820 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2821 VM_BUG_ON((gfn & mask) != (pfn & mask));
2822 *pfnp = pfn & ~mask;
2827 void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2828 kvm_pfn_t *pfnp, int *goal_levelp)
2830 int level = *goal_levelp;
2832 if (cur_level == level && level > PG_LEVEL_4K &&
2833 is_shadow_present_pte(spte) &&
2834 !is_large_pte(spte)) {
2836 * A small SPTE exists for this pfn, but FNAME(fetch)
2837 * and __direct_map would like to create a large PTE
2838 * instead: just force them to go down another level,
2839 * patching back for them into pfn the next 9 bits of
2842 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2843 KVM_PAGES_PER_HPAGE(level - 1);
2844 *pfnp |= gfn & page_mask;
2849 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
2850 int map_writable, int max_level, kvm_pfn_t pfn,
2851 bool prefault, bool is_tdp)
2853 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2854 bool write = error_code & PFERR_WRITE_MASK;
2855 bool exec = error_code & PFERR_FETCH_MASK;
2856 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
2857 struct kvm_shadow_walk_iterator it;
2858 struct kvm_mmu_page *sp;
2859 int level, req_level, ret;
2860 gfn_t gfn = gpa >> PAGE_SHIFT;
2861 gfn_t base_gfn = gfn;
2863 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
2864 return RET_PF_RETRY;
2866 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2867 huge_page_disallowed, &req_level);
2869 trace_kvm_mmu_spte_requested(gpa, level, pfn);
2870 for_each_shadow_entry(vcpu, gpa, it) {
2872 * We cannot overwrite existing page tables with an NX
2873 * large page, as the leaf could be executable.
2875 if (nx_huge_page_workaround_enabled)
2876 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
2879 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2880 if (it.level == level)
2883 drop_large_spte(vcpu, it.sptep);
2884 if (!is_shadow_present_pte(*it.sptep)) {
2885 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2886 it.level - 1, true, ACC_ALL);
2888 link_shadow_page(vcpu, it.sptep, sp);
2889 if (is_tdp && huge_page_disallowed &&
2890 req_level >= it.level)
2891 account_huge_nx_page(vcpu->kvm, sp);
2895 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2896 write, level, base_gfn, pfn, prefault,
2898 if (ret == RET_PF_SPURIOUS)
2901 direct_pte_prefetch(vcpu, it.sptep);
2902 ++vcpu->stat.pf_fixed;
2906 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2908 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2911 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2914 * Do not cache the mmio info caused by writing the readonly gfn
2915 * into the spte otherwise read access on readonly gfn also can
2916 * caused mmio page fault and treat it as mmio access.
2918 if (pfn == KVM_PFN_ERR_RO_FAULT)
2919 return RET_PF_EMULATE;
2921 if (pfn == KVM_PFN_ERR_HWPOISON) {
2922 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2923 return RET_PF_RETRY;
2929 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2930 kvm_pfn_t pfn, unsigned int access,
2933 /* The pfn is invalid, report the error! */
2934 if (unlikely(is_error_pfn(pfn))) {
2935 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2939 if (unlikely(is_noslot_pfn(pfn))) {
2940 vcpu_cache_mmio_info(vcpu, gva, gfn,
2941 access & shadow_mmio_access_mask);
2943 * If MMIO caching is disabled, emulate immediately without
2944 * touching the shadow page tables as attempting to install an
2945 * MMIO SPTE will just be an expensive nop.
2947 if (unlikely(!shadow_mmio_value)) {
2948 *ret_val = RET_PF_EMULATE;
2956 static bool page_fault_can_be_fast(u32 error_code)
2959 * Do not fix the mmio spte with invalid generation number which
2960 * need to be updated by slow page fault path.
2962 if (unlikely(error_code & PFERR_RSVD_MASK))
2965 /* See if the page fault is due to an NX violation */
2966 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
2967 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
2971 * #PF can be fast if:
2972 * 1. The shadow page table entry is not present, which could mean that
2973 * the fault is potentially caused by access tracking (if enabled).
2974 * 2. The shadow page table entry is present and the fault
2975 * is caused by write-protect, that means we just need change the W
2976 * bit of the spte which can be done out of mmu-lock.
2978 * However, if access tracking is disabled we know that a non-present
2979 * page must be a genuine page fault where we have to create a new SPTE.
2980 * So, if access tracking is disabled, we return true only for write
2981 * accesses to a present page.
2984 return shadow_acc_track_mask != 0 ||
2985 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
2986 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
2990 * Returns true if the SPTE was fixed successfully. Otherwise,
2991 * someone else modified the SPTE from its original value.
2994 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2995 u64 *sptep, u64 old_spte, u64 new_spte)
2999 WARN_ON(!sp->role.direct);
3002 * Theoretically we could also set dirty bit (and flush TLB) here in
3003 * order to eliminate unnecessary PML logging. See comments in
3004 * set_spte. But fast_page_fault is very unlikely to happen with PML
3005 * enabled, so we do not do this. This might result in the same GPA
3006 * to be logged in PML buffer again when the write really happens, and
3007 * eventually to be called by mark_page_dirty twice. But it's also no
3008 * harm. This also avoids the TLB flush needed after setting dirty bit
3009 * so non-PML cases won't be impacted.
3011 * Compare with set_spte where instead shadow_dirty_mask is set.
3013 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3016 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3018 * The gfn of direct spte is stable since it is
3019 * calculated by sp->gfn.
3021 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3022 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3028 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3030 if (fault_err_code & PFERR_FETCH_MASK)
3031 return is_executable_pte(spte);
3033 if (fault_err_code & PFERR_WRITE_MASK)
3034 return is_writable_pte(spte);
3036 /* Fault was on Read access */
3037 return spte & PT_PRESENT_MASK;
3041 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3043 static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3046 struct kvm_shadow_walk_iterator iterator;
3047 struct kvm_mmu_page *sp;
3048 int ret = RET_PF_INVALID;
3050 uint retry_count = 0;
3052 if (!page_fault_can_be_fast(error_code))
3055 walk_shadow_page_lockless_begin(vcpu);
3060 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3061 if (!is_shadow_present_pte(spte))
3064 if (!is_shadow_present_pte(spte))
3067 sp = sptep_to_sp(iterator.sptep);
3068 if (!is_last_spte(spte, sp->role.level))
3072 * Check whether the memory access that caused the fault would
3073 * still cause it if it were to be performed right now. If not,
3074 * then this is a spurious fault caused by TLB lazily flushed,
3075 * or some other CPU has already fixed the PTE after the
3076 * current CPU took the fault.
3078 * Need not check the access of upper level table entries since
3079 * they are always ACC_ALL.
3081 if (is_access_allowed(error_code, spte)) {
3082 ret = RET_PF_SPURIOUS;
3088 if (is_access_track_spte(spte))
3089 new_spte = restore_acc_track_spte(new_spte);
3092 * Currently, to simplify the code, write-protection can
3093 * be removed in the fast path only if the SPTE was
3094 * write-protected for dirty-logging or access tracking.
3096 if ((error_code & PFERR_WRITE_MASK) &&
3097 spte_can_locklessly_be_made_writable(spte)) {
3098 new_spte |= PT_WRITABLE_MASK;
3101 * Do not fix write-permission on the large spte. Since
3102 * we only dirty the first page into the dirty-bitmap in
3103 * fast_pf_fix_direct_spte(), other pages are missed
3104 * if its slot has dirty logging enabled.
3106 * Instead, we let the slow page fault path create a
3107 * normal spte to fix the access.
3109 * See the comments in kvm_arch_commit_memory_region().
3111 if (sp->role.level > PG_LEVEL_4K)
3115 /* Verify that the fault can be handled in the fast path */
3116 if (new_spte == spte ||
3117 !is_access_allowed(error_code, new_spte))
3121 * Currently, fast page fault only works for direct mapping
3122 * since the gfn is not stable for indirect shadow page. See
3123 * Documentation/virt/kvm/locking.rst to get more detail.
3125 if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte,
3131 if (++retry_count > 4) {
3132 printk_once(KERN_WARNING
3133 "kvm: Fast #PF retrying more than 4 times.\n");
3139 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3141 walk_shadow_page_lockless_end(vcpu);
3146 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3147 struct list_head *invalid_list)
3149 struct kvm_mmu_page *sp;
3151 if (!VALID_PAGE(*root_hpa))
3154 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3156 if (kvm_mmu_put_root(kvm, sp)) {
3157 if (is_tdp_mmu_page(sp))
3158 kvm_tdp_mmu_free_root(kvm, sp);
3159 else if (sp->role.invalid)
3160 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3163 *root_hpa = INVALID_PAGE;
3166 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3167 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3168 ulong roots_to_free)
3170 struct kvm *kvm = vcpu->kvm;
3172 LIST_HEAD(invalid_list);
3173 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3175 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3177 /* Before acquiring the MMU lock, see if we need to do any real work. */
3178 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3179 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3180 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3181 VALID_PAGE(mmu->prev_roots[i].hpa))
3184 if (i == KVM_MMU_NUM_PREV_ROOTS)
3188 write_lock(&kvm->mmu_lock);
3190 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3191 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3192 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3195 if (free_active_root) {
3196 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3197 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3198 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3199 } else if (mmu->pae_root) {
3200 for (i = 0; i < 4; ++i) {
3201 if (!IS_VALID_PAE_ROOT(mmu->pae_root[i]))
3204 mmu_free_root_page(kvm, &mmu->pae_root[i],
3206 mmu->pae_root[i] = INVALID_PAE_ROOT;
3209 mmu->root_hpa = INVALID_PAGE;
3213 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3214 write_unlock(&kvm->mmu_lock);
3216 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3218 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3222 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3223 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3230 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3231 u8 level, bool direct)
3233 struct kvm_mmu_page *sp;
3235 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3238 return __pa(sp->spt);
3241 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3243 struct kvm_mmu *mmu = vcpu->arch.mmu;
3244 u8 shadow_root_level = mmu->shadow_root_level;
3249 write_lock(&vcpu->kvm->mmu_lock);
3250 r = make_mmu_pages_available(vcpu);
3254 if (is_tdp_mmu_enabled(vcpu->kvm)) {
3255 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3256 mmu->root_hpa = root;
3257 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3258 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true);
3259 mmu->root_hpa = root;
3260 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3261 if (WARN_ON_ONCE(!mmu->pae_root)) {
3266 for (i = 0; i < 4; ++i) {
3267 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3269 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3270 i << 30, PT32_ROOT_LEVEL, true);
3271 mmu->pae_root[i] = root | PT_PRESENT_MASK |
3274 mmu->root_hpa = __pa(mmu->pae_root);
3276 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level);
3281 /* root_pgd is ignored for direct MMUs. */
3284 write_unlock(&vcpu->kvm->mmu_lock);
3288 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3290 struct kvm_mmu *mmu = vcpu->arch.mmu;
3291 u64 pdptrs[4], pm_mask;
3292 gfn_t root_gfn, root_pgd;
3297 root_pgd = mmu->get_guest_pgd(vcpu);
3298 root_gfn = root_pgd >> PAGE_SHIFT;
3300 if (mmu_check_root(vcpu, root_gfn))
3304 * On SVM, reading PDPTRs might access guest memory, which might fault
3305 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3307 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3308 for (i = 0; i < 4; ++i) {
3309 pdptrs[i] = mmu->get_pdptr(vcpu, i);
3310 if (!(pdptrs[i] & PT_PRESENT_MASK))
3313 if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT))
3318 write_lock(&vcpu->kvm->mmu_lock);
3319 r = make_mmu_pages_available(vcpu);
3324 * Do we shadow a long mode page table? If so we need to
3325 * write-protect the guests page table root.
3327 if (mmu->root_level >= PT64_ROOT_4LEVEL) {
3328 root = mmu_alloc_root(vcpu, root_gfn, 0,
3329 mmu->shadow_root_level, false);
3330 mmu->root_hpa = root;
3334 if (WARN_ON_ONCE(!mmu->pae_root)) {
3340 * We shadow a 32 bit page table. This may be a legacy 2-level
3341 * or a PAE 3-level page table. In either case we need to be aware that
3342 * the shadow page table may be a PAE or a long mode page table.
3344 pm_mask = PT_PRESENT_MASK | shadow_me_mask;
3345 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3346 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3348 if (WARN_ON_ONCE(!mmu->lm_root)) {
3353 mmu->lm_root[0] = __pa(mmu->pae_root) | pm_mask;
3356 for (i = 0; i < 4; ++i) {
3357 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3359 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3360 if (!(pdptrs[i] & PT_PRESENT_MASK)) {
3361 mmu->pae_root[i] = INVALID_PAE_ROOT;
3364 root_gfn = pdptrs[i] >> PAGE_SHIFT;
3367 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3368 PT32_ROOT_LEVEL, false);
3369 mmu->pae_root[i] = root | pm_mask;
3372 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3373 mmu->root_hpa = __pa(mmu->lm_root);
3375 mmu->root_hpa = __pa(mmu->pae_root);
3378 mmu->root_pgd = root_pgd;
3380 write_unlock(&vcpu->kvm->mmu_lock);
3385 static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu)
3387 struct kvm_mmu *mmu = vcpu->arch.mmu;
3388 u64 *lm_root, *pae_root;
3391 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3392 * tables are allocated and initialized at root creation as there is no
3393 * equivalent level in the guest's NPT to shadow. Allocate the tables
3394 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
3396 if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL ||
3397 mmu->shadow_root_level < PT64_ROOT_4LEVEL)
3401 * This mess only works with 4-level paging and needs to be updated to
3402 * work with 5-level paging.
3404 if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL))
3407 if (mmu->pae_root && mmu->lm_root)
3411 * The special roots should always be allocated in concert. Yell and
3412 * bail if KVM ends up in a state where only one of the roots is valid.
3414 if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->lm_root))
3418 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3419 * doesn't need to be decrypted.
3421 pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3425 lm_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3427 free_page((unsigned long)pae_root);
3431 mmu->pae_root = pae_root;
3432 mmu->lm_root = lm_root;
3437 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3440 struct kvm_mmu_page *sp;
3442 if (vcpu->arch.mmu->direct_map)
3445 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3448 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3450 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3451 hpa_t root = vcpu->arch.mmu->root_hpa;
3452 sp = to_shadow_page(root);
3455 * Even if another CPU was marking the SP as unsync-ed
3456 * simultaneously, any guest page table changes are not
3457 * guaranteed to be visible anyway until this VCPU issues a TLB
3458 * flush strictly after those changes are made. We only need to
3459 * ensure that the other CPU sets these flags before any actual
3460 * changes to the page tables are made. The comments in
3461 * mmu_need_write_protect() describe what could go wrong if this
3462 * requirement isn't satisfied.
3464 if (!smp_load_acquire(&sp->unsync) &&
3465 !smp_load_acquire(&sp->unsync_children))
3468 write_lock(&vcpu->kvm->mmu_lock);
3469 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3471 mmu_sync_children(vcpu, sp);
3473 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3474 write_unlock(&vcpu->kvm->mmu_lock);
3478 write_lock(&vcpu->kvm->mmu_lock);
3479 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3481 for (i = 0; i < 4; ++i) {
3482 hpa_t root = vcpu->arch.mmu->pae_root[i];
3484 if (IS_VALID_PAE_ROOT(root)) {
3485 root &= PT64_BASE_ADDR_MASK;
3486 sp = to_shadow_page(root);
3487 mmu_sync_children(vcpu, sp);
3491 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3492 write_unlock(&vcpu->kvm->mmu_lock);
3495 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3496 u32 access, struct x86_exception *exception)
3499 exception->error_code = 0;
3503 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3505 struct x86_exception *exception)
3508 exception->error_code = 0;
3509 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3513 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3515 int bit7 = (pte >> 7) & 1;
3517 return pte & rsvd_check->rsvd_bits_mask[bit7][level-1];
3520 static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte)
3522 return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
3525 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3528 * A nested guest cannot use the MMIO cache if it is using nested
3529 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3531 if (mmu_is_nested(vcpu))
3535 return vcpu_match_mmio_gpa(vcpu, addr);
3537 return vcpu_match_mmio_gva(vcpu, addr);
3541 * Return the level of the lowest level SPTE added to sptes.
3542 * That SPTE may be non-present.
3544 static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
3546 struct kvm_shadow_walk_iterator iterator;
3550 walk_shadow_page_lockless_begin(vcpu);
3552 for (shadow_walk_init(&iterator, vcpu, addr),
3553 *root_level = iterator.level;
3554 shadow_walk_okay(&iterator);
3555 __shadow_walk_next(&iterator, spte)) {
3556 leaf = iterator.level;
3557 spte = mmu_spte_get_lockless(iterator.sptep);
3561 if (!is_shadow_present_pte(spte))
3565 walk_shadow_page_lockless_end(vcpu);
3570 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3571 static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3573 u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
3574 struct rsvd_bits_validate *rsvd_check;
3575 int root, leaf, level;
3576 bool reserved = false;
3578 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) {
3583 if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
3584 leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
3586 leaf = get_walk(vcpu, addr, sptes, &root);
3588 if (unlikely(leaf < 0)) {
3593 *sptep = sptes[leaf];
3596 * Skip reserved bits checks on the terminal leaf if it's not a valid
3597 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3598 * design, always have reserved bits set. The purpose of the checks is
3599 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3601 if (!is_shadow_present_pte(sptes[leaf]))
3604 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3606 for (level = root; level >= leaf; level--)
3608 * Use a bitwise-OR instead of a logical-OR to aggregate the
3609 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3610 * adding a Jcc in the loop.
3612 reserved |= __is_bad_mt_xwr(rsvd_check, sptes[level]) |
3613 __is_rsvd_bits_set(rsvd_check, sptes[level], level);
3616 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
3618 for (level = root; level >= leaf; level--)
3619 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3620 sptes[level], level,
3621 rsvd_check->rsvd_bits_mask[(sptes[level] >> 7) & 1][level-1]);
3627 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3632 if (mmio_info_in_cache(vcpu, addr, direct))
3633 return RET_PF_EMULATE;
3635 reserved = get_mmio_spte(vcpu, addr, &spte);
3636 if (WARN_ON(reserved))
3639 if (is_mmio_spte(spte)) {
3640 gfn_t gfn = get_mmio_spte_gfn(spte);
3641 unsigned int access = get_mmio_spte_access(spte);
3643 if (!check_mmio_spte(vcpu, spte))
3644 return RET_PF_INVALID;
3649 trace_handle_mmio_page_fault(addr, gfn, access);
3650 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3651 return RET_PF_EMULATE;
3655 * If the page table is zapped by other cpus, let CPU fault again on
3658 return RET_PF_RETRY;
3661 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3662 u32 error_code, gfn_t gfn)
3664 if (unlikely(error_code & PFERR_RSVD_MASK))
3667 if (!(error_code & PFERR_PRESENT_MASK) ||
3668 !(error_code & PFERR_WRITE_MASK))
3672 * guest is writing the page which is write tracked which can
3673 * not be fixed by page fault handler.
3675 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3681 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3683 struct kvm_shadow_walk_iterator iterator;
3686 walk_shadow_page_lockless_begin(vcpu);
3687 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3688 clear_sp_write_flooding_count(iterator.sptep);
3689 if (!is_shadow_present_pte(spte))
3692 walk_shadow_page_lockless_end(vcpu);
3695 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3698 struct kvm_arch_async_pf arch;
3700 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3702 arch.direct_map = vcpu->arch.mmu->direct_map;
3703 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3705 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3706 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3709 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3710 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva,
3711 bool write, bool *writable)
3713 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3717 * Retry the page fault if the gfn hit a memslot that is being deleted
3718 * or moved. This ensures any existing SPTEs for the old memslot will
3719 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3721 if (slot && (slot->flags & KVM_MEMSLOT_INVALID))
3724 /* Don't expose private memslots to L2. */
3725 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3726 *pfn = KVM_PFN_NOSLOT;
3732 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async,
3733 write, writable, hva);
3735 return false; /* *pfn has correct page already */
3737 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3738 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
3739 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3740 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
3741 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3743 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
3747 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL,
3748 write, writable, hva);
3752 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3753 bool prefault, int max_level, bool is_tdp)
3755 bool write = error_code & PFERR_WRITE_MASK;
3758 gfn_t gfn = gpa >> PAGE_SHIFT;
3759 unsigned long mmu_seq;
3764 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3765 return RET_PF_EMULATE;
3767 if (!is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) {
3768 r = fast_page_fault(vcpu, gpa, error_code);
3769 if (r != RET_PF_INVALID)
3773 r = mmu_topup_memory_caches(vcpu, false);
3777 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3780 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, &hva,
3781 write, &map_writable))
3782 return RET_PF_RETRY;
3784 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
3789 if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
3790 read_lock(&vcpu->kvm->mmu_lock);
3792 write_lock(&vcpu->kvm->mmu_lock);
3794 if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva))
3796 r = make_mmu_pages_available(vcpu);
3800 if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
3801 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
3804 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
3808 if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
3809 read_unlock(&vcpu->kvm->mmu_lock);
3811 write_unlock(&vcpu->kvm->mmu_lock);
3812 kvm_release_pfn_clean(pfn);
3816 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
3817 u32 error_code, bool prefault)
3819 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
3821 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3822 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3823 PG_LEVEL_2M, false);
3826 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3827 u64 fault_address, char *insn, int insn_len)
3830 u32 flags = vcpu->arch.apf.host_apf_flags;
3832 #ifndef CONFIG_X86_64
3833 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3834 if (WARN_ON_ONCE(fault_address >> 32))
3838 vcpu->arch.l1tf_flush_l1d = true;
3840 trace_kvm_page_fault(fault_address, error_code);
3842 if (kvm_event_needs_reinjection(vcpu))
3843 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3844 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3846 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
3847 vcpu->arch.apf.host_apf_flags = 0;
3848 local_irq_disable();
3849 kvm_async_pf_task_wait_schedule(fault_address);
3852 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
3857 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3859 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3864 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3865 max_level > PG_LEVEL_4K;
3867 int page_num = KVM_PAGES_PER_HPAGE(max_level);
3868 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
3870 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
3874 return direct_page_fault(vcpu, gpa, error_code, prefault,
3878 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3879 struct kvm_mmu *context)
3881 context->page_fault = nonpaging_page_fault;
3882 context->gva_to_gpa = nonpaging_gva_to_gpa;
3883 context->sync_page = nonpaging_sync_page;
3884 context->invlpg = NULL;
3885 context->root_level = 0;
3886 context->shadow_root_level = PT32E_ROOT_LEVEL;
3887 context->direct_map = true;
3888 context->nx = false;
3891 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
3892 union kvm_mmu_page_role role)
3894 return (role.direct || pgd == root->pgd) &&
3895 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
3896 role.word == to_shadow_page(root->hpa)->role.word;
3900 * Find out if a previously cached root matching the new pgd/role is available.
3901 * The current root is also inserted into the cache.
3902 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3904 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3905 * false is returned. This root should now be freed by the caller.
3907 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3908 union kvm_mmu_page_role new_role)
3911 struct kvm_mmu_root_info root;
3912 struct kvm_mmu *mmu = vcpu->arch.mmu;
3914 root.pgd = mmu->root_pgd;
3915 root.hpa = mmu->root_hpa;
3917 if (is_root_usable(&root, new_pgd, new_role))
3920 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3921 swap(root, mmu->prev_roots[i]);
3923 if (is_root_usable(&root, new_pgd, new_role))
3927 mmu->root_hpa = root.hpa;
3928 mmu->root_pgd = root.pgd;
3930 return i < KVM_MMU_NUM_PREV_ROOTS;
3933 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3934 union kvm_mmu_page_role new_role)
3936 struct kvm_mmu *mmu = vcpu->arch.mmu;
3939 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
3940 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
3941 * later if necessary.
3943 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3944 mmu->root_level >= PT64_ROOT_4LEVEL)
3945 return cached_root_available(vcpu, new_pgd, new_role);
3950 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3951 union kvm_mmu_page_role new_role,
3952 bool skip_tlb_flush, bool skip_mmu_sync)
3954 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
3955 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
3960 * It's possible that the cached previous root page is obsolete because
3961 * of a change in the MMU generation number. However, changing the
3962 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
3963 * free the root set here and allocate a new one.
3965 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
3967 if (!skip_mmu_sync || force_flush_and_sync_on_reuse)
3968 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
3969 if (!skip_tlb_flush || force_flush_and_sync_on_reuse)
3970 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3973 * The last MMIO access's GVA and GPA are cached in the VCPU. When
3974 * switching to a new CR3, that GVA->GPA mapping may no longer be
3975 * valid. So clear any cached MMIO info even when we don't need to sync
3976 * the shadow page tables.
3978 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3981 * If this is a direct root page, it doesn't have a write flooding
3982 * count. Otherwise, clear the write flooding count.
3984 if (!new_role.direct)
3985 __clear_sp_write_flooding_count(
3986 to_shadow_page(vcpu->arch.mmu->root_hpa));
3989 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush,
3992 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu),
3993 skip_tlb_flush, skip_mmu_sync);
3995 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
3997 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3999 return kvm_read_cr3(vcpu);
4002 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4003 unsigned int access, int *nr_present)
4005 if (unlikely(is_mmio_spte(*sptep))) {
4006 if (gfn != get_mmio_spte_gfn(*sptep)) {
4007 mmu_spte_clear_no_track(sptep);
4012 mark_mmio_spte(vcpu, sptep, gfn, access);
4019 static inline bool is_last_gpte(struct kvm_mmu *mmu,
4020 unsigned level, unsigned gpte)
4023 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4024 * If it is clear, there are no large pages at this level, so clear
4025 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4027 gpte &= level - mmu->last_nonleaf_level;
4030 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
4031 * iff level <= PG_LEVEL_4K, which for our purpose means
4032 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
4034 gpte |= level - PG_LEVEL_4K - 1;
4036 return gpte & PT_PAGE_SIZE_MASK;
4039 #define PTTYPE_EPT 18 /* arbitrary */
4040 #define PTTYPE PTTYPE_EPT
4041 #include "paging_tmpl.h"
4045 #include "paging_tmpl.h"
4049 #include "paging_tmpl.h"
4053 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4054 struct rsvd_bits_validate *rsvd_check,
4055 u64 pa_bits_rsvd, int level, bool nx, bool gbpages,
4058 u64 gbpages_bit_rsvd = 0;
4059 u64 nonleaf_bit8_rsvd = 0;
4062 rsvd_check->bad_mt_xwr = 0;
4065 gbpages_bit_rsvd = rsvd_bits(7, 7);
4067 if (level == PT32E_ROOT_LEVEL)
4068 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62);
4070 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4072 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4074 high_bits_rsvd |= rsvd_bits(63, 63);
4077 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4078 * leaf entries) on AMD CPUs only.
4081 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4084 case PT32_ROOT_LEVEL:
4085 /* no rsvd bits for 2 level 4K page table entries */
4086 rsvd_check->rsvd_bits_mask[0][1] = 0;
4087 rsvd_check->rsvd_bits_mask[0][0] = 0;
4088 rsvd_check->rsvd_bits_mask[1][0] =
4089 rsvd_check->rsvd_bits_mask[0][0];
4092 rsvd_check->rsvd_bits_mask[1][1] = 0;
4096 if (is_cpuid_PSE36())
4097 /* 36bits PSE 4MB page */
4098 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4100 /* 32 bits PSE 4MB page */
4101 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4103 case PT32E_ROOT_LEVEL:
4104 rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
4107 rsvd_bits(1, 2); /* PDPTE */
4108 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
4109 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
4110 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4111 rsvd_bits(13, 20); /* large page */
4112 rsvd_check->rsvd_bits_mask[1][0] =
4113 rsvd_check->rsvd_bits_mask[0][0];
4115 case PT64_ROOT_5LEVEL:
4116 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd |
4119 rsvd_check->rsvd_bits_mask[1][4] =
4120 rsvd_check->rsvd_bits_mask[0][4];
4122 case PT64_ROOT_4LEVEL:
4123 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd |
4126 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd |
4128 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd;
4129 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4130 rsvd_check->rsvd_bits_mask[1][3] =
4131 rsvd_check->rsvd_bits_mask[0][3];
4132 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd |
4135 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4136 rsvd_bits(13, 20); /* large page */
4137 rsvd_check->rsvd_bits_mask[1][0] =
4138 rsvd_check->rsvd_bits_mask[0][0];
4143 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4144 struct kvm_mmu *context)
4146 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4147 vcpu->arch.reserved_gpa_bits,
4148 context->root_level, context->nx,
4149 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4151 guest_cpuid_is_amd_or_hygon(vcpu));
4155 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4156 u64 pa_bits_rsvd, bool execonly)
4158 u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4161 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
4162 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
4163 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6);
4164 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6);
4165 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4168 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4169 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4170 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29);
4171 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20);
4172 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4174 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4175 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4176 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4177 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4178 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4180 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4181 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4183 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4186 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4187 struct kvm_mmu *context, bool execonly)
4189 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4190 vcpu->arch.reserved_gpa_bits, execonly);
4193 static inline u64 reserved_hpa_bits(void)
4195 return rsvd_bits(shadow_phys_bits, 63);
4199 * the page table on host is the shadow page table for the page
4200 * table in guest or amd nested guest, its mmu features completely
4201 * follow the features in guest.
4204 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4206 bool uses_nx = context->nx ||
4207 context->mmu_role.base.smep_andnot_wp;
4208 struct rsvd_bits_validate *shadow_zero_check;
4212 * Passing "true" to the last argument is okay; it adds a check
4213 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4215 shadow_zero_check = &context->shadow_zero_check;
4216 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4217 reserved_hpa_bits(),
4218 context->shadow_root_level, uses_nx,
4219 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4220 is_pse(vcpu), true);
4222 if (!shadow_me_mask)
4225 for (i = context->shadow_root_level; --i >= 0;) {
4226 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4227 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4231 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4233 static inline bool boot_cpu_is_amd(void)
4235 WARN_ON_ONCE(!tdp_enabled);
4236 return shadow_x_mask == 0;
4240 * the direct page table on host, use as much mmu features as
4241 * possible, however, kvm currently does not do execution-protection.
4244 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4245 struct kvm_mmu *context)
4247 struct rsvd_bits_validate *shadow_zero_check;
4250 shadow_zero_check = &context->shadow_zero_check;
4252 if (boot_cpu_is_amd())
4253 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4254 reserved_hpa_bits(),
4255 context->shadow_root_level, false,
4256 boot_cpu_has(X86_FEATURE_GBPAGES),
4259 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4260 reserved_hpa_bits(), false);
4262 if (!shadow_me_mask)
4265 for (i = context->shadow_root_level; --i >= 0;) {
4266 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4267 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4272 * as the comments in reset_shadow_zero_bits_mask() except it
4273 * is the shadow page table for intel nested guest.
4276 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4277 struct kvm_mmu *context, bool execonly)
4279 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4280 reserved_hpa_bits(), execonly);
4283 #define BYTE_MASK(access) \
4284 ((1 & (access) ? 2 : 0) | \
4285 (2 & (access) ? 4 : 0) | \
4286 (3 & (access) ? 8 : 0) | \
4287 (4 & (access) ? 16 : 0) | \
4288 (5 & (access) ? 32 : 0) | \
4289 (6 & (access) ? 64 : 0) | \
4290 (7 & (access) ? 128 : 0))
4293 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4294 struct kvm_mmu *mmu, bool ept)
4298 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4299 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4300 const u8 u = BYTE_MASK(ACC_USER_MASK);
4302 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4303 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4304 bool cr0_wp = is_write_protection(vcpu);
4306 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4307 unsigned pfec = byte << 1;
4310 * Each "*f" variable has a 1 bit for each UWX value
4311 * that causes a fault with the given PFEC.
4314 /* Faults from writes to non-writable pages */
4315 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4316 /* Faults from user mode accesses to supervisor pages */
4317 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4318 /* Faults from fetches of non-executable pages*/
4319 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4320 /* Faults from kernel mode fetches of user pages */
4322 /* Faults from kernel mode accesses of user pages */
4326 /* Faults from kernel mode accesses to user pages */
4327 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4329 /* Not really needed: !nx will cause pte.nx to fault */
4333 /* Allow supervisor writes if !cr0.wp */
4335 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4337 /* Disallow supervisor fetches of user code if cr4.smep */
4339 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4342 * SMAP:kernel-mode data accesses from user-mode
4343 * mappings should fault. A fault is considered
4344 * as a SMAP violation if all of the following
4345 * conditions are true:
4346 * - X86_CR4_SMAP is set in CR4
4347 * - A user page is accessed
4348 * - The access is not a fetch
4349 * - Page fault in kernel mode
4350 * - if CPL = 3 or X86_EFLAGS_AC is clear
4352 * Here, we cover the first three conditions.
4353 * The fourth is computed dynamically in permission_fault();
4354 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4355 * *not* subject to SMAP restrictions.
4358 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4361 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4366 * PKU is an additional mechanism by which the paging controls access to
4367 * user-mode addresses based on the value in the PKRU register. Protection
4368 * key violations are reported through a bit in the page fault error code.
4369 * Unlike other bits of the error code, the PK bit is not known at the
4370 * call site of e.g. gva_to_gpa; it must be computed directly in
4371 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4372 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4374 * In particular the following conditions come from the error code, the
4375 * page tables and the machine state:
4376 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4377 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4378 * - PK is always zero if U=0 in the page tables
4379 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4381 * The PKRU bitmask caches the result of these four conditions. The error
4382 * code (minus the P bit) and the page table's U bit form an index into the
4383 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4384 * with the two bits of the PKRU register corresponding to the protection key.
4385 * For the first three conditions above the bits will be 00, thus masking
4386 * away both AD and WD. For all reads or if the last condition holds, WD
4387 * only will be masked away.
4389 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4400 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4401 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4406 wp = is_write_protection(vcpu);
4408 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4409 unsigned pfec, pkey_bits;
4410 bool check_pkey, check_write, ff, uf, wf, pte_user;
4413 ff = pfec & PFERR_FETCH_MASK;
4414 uf = pfec & PFERR_USER_MASK;
4415 wf = pfec & PFERR_WRITE_MASK;
4417 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4418 pte_user = pfec & PFERR_RSVD_MASK;
4421 * Only need to check the access which is not an
4422 * instruction fetch and is to a user page.
4424 check_pkey = (!ff && pte_user);
4426 * write access is controlled by PKRU if it is a
4427 * user access or CR0.WP = 1.
4429 check_write = check_pkey && wf && (uf || wp);
4431 /* PKRU.AD stops both read and write access. */
4432 pkey_bits = !!check_pkey;
4433 /* PKRU.WD stops write access. */
4434 pkey_bits |= (!!check_write) << 1;
4436 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4440 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4442 unsigned root_level = mmu->root_level;
4444 mmu->last_nonleaf_level = root_level;
4445 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4446 mmu->last_nonleaf_level++;
4449 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4450 struct kvm_mmu *context,
4453 context->nx = is_nx(vcpu);
4454 context->root_level = level;
4456 reset_rsvds_bits_mask(vcpu, context);
4457 update_permission_bitmask(vcpu, context, false);
4458 update_pkru_bitmask(vcpu, context, false);
4459 update_last_nonleaf_level(vcpu, context);
4461 MMU_WARN_ON(!is_pae(vcpu));
4462 context->page_fault = paging64_page_fault;
4463 context->gva_to_gpa = paging64_gva_to_gpa;
4464 context->sync_page = paging64_sync_page;
4465 context->invlpg = paging64_invlpg;
4466 context->shadow_root_level = level;
4467 context->direct_map = false;
4470 static void paging64_init_context(struct kvm_vcpu *vcpu,
4471 struct kvm_mmu *context)
4473 int root_level = is_la57_mode(vcpu) ?
4474 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4476 paging64_init_context_common(vcpu, context, root_level);
4479 static void paging32_init_context(struct kvm_vcpu *vcpu,
4480 struct kvm_mmu *context)
4482 context->nx = false;
4483 context->root_level = PT32_ROOT_LEVEL;
4485 reset_rsvds_bits_mask(vcpu, context);
4486 update_permission_bitmask(vcpu, context, false);
4487 update_pkru_bitmask(vcpu, context, false);
4488 update_last_nonleaf_level(vcpu, context);
4490 context->page_fault = paging32_page_fault;
4491 context->gva_to_gpa = paging32_gva_to_gpa;
4492 context->sync_page = paging32_sync_page;
4493 context->invlpg = paging32_invlpg;
4494 context->shadow_root_level = PT32E_ROOT_LEVEL;
4495 context->direct_map = false;
4498 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4499 struct kvm_mmu *context)
4501 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4504 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4506 union kvm_mmu_extended_role ext = {0};
4508 ext.cr0_pg = !!is_paging(vcpu);
4509 ext.cr4_pae = !!is_pae(vcpu);
4510 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4511 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4512 ext.cr4_pse = !!is_pse(vcpu);
4513 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4514 ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
4521 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4524 union kvm_mmu_role role = {0};
4526 role.base.access = ACC_ALL;
4527 role.base.nxe = !!is_nx(vcpu);
4528 role.base.cr0_wp = is_write_protection(vcpu);
4529 role.base.smm = is_smm(vcpu);
4530 role.base.guest_mode = is_guest_mode(vcpu);
4535 role.ext = kvm_calc_mmu_role_ext(vcpu);
4540 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4542 /* Use 5-level TDP if and only if it's useful/necessary. */
4543 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4546 return max_tdp_level;
4549 static union kvm_mmu_role
4550 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4552 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4554 role.base.ad_disabled = (shadow_accessed_mask == 0);
4555 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4556 role.base.direct = true;
4557 role.base.gpte_is_8_bytes = true;
4562 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4564 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4565 union kvm_mmu_role new_role =
4566 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
4568 if (new_role.as_u64 == context->mmu_role.as_u64)
4571 context->mmu_role.as_u64 = new_role.as_u64;
4572 context->page_fault = kvm_tdp_page_fault;
4573 context->sync_page = nonpaging_sync_page;
4574 context->invlpg = NULL;
4575 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4576 context->direct_map = true;
4577 context->get_guest_pgd = get_cr3;
4578 context->get_pdptr = kvm_pdptr_read;
4579 context->inject_page_fault = kvm_inject_page_fault;
4581 if (!is_paging(vcpu)) {
4582 context->nx = false;
4583 context->gva_to_gpa = nonpaging_gva_to_gpa;
4584 context->root_level = 0;
4585 } else if (is_long_mode(vcpu)) {
4586 context->nx = is_nx(vcpu);
4587 context->root_level = is_la57_mode(vcpu) ?
4588 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4589 reset_rsvds_bits_mask(vcpu, context);
4590 context->gva_to_gpa = paging64_gva_to_gpa;
4591 } else if (is_pae(vcpu)) {
4592 context->nx = is_nx(vcpu);
4593 context->root_level = PT32E_ROOT_LEVEL;
4594 reset_rsvds_bits_mask(vcpu, context);
4595 context->gva_to_gpa = paging64_gva_to_gpa;
4597 context->nx = false;
4598 context->root_level = PT32_ROOT_LEVEL;
4599 reset_rsvds_bits_mask(vcpu, context);
4600 context->gva_to_gpa = paging32_gva_to_gpa;
4603 update_permission_bitmask(vcpu, context, false);
4604 update_pkru_bitmask(vcpu, context, false);
4605 update_last_nonleaf_level(vcpu, context);
4606 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4609 static union kvm_mmu_role
4610 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, bool base_only)
4612 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4614 role.base.smep_andnot_wp = role.ext.cr4_smep &&
4615 !is_write_protection(vcpu);
4616 role.base.smap_andnot_wp = role.ext.cr4_smap &&
4617 !is_write_protection(vcpu);
4618 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
4623 static union kvm_mmu_role
4624 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4626 union kvm_mmu_role role =
4627 kvm_calc_shadow_root_page_role_common(vcpu, base_only);
4629 role.base.direct = !is_paging(vcpu);
4631 if (!is_long_mode(vcpu))
4632 role.base.level = PT32E_ROOT_LEVEL;
4633 else if (is_la57_mode(vcpu))
4634 role.base.level = PT64_ROOT_5LEVEL;
4636 role.base.level = PT64_ROOT_4LEVEL;
4641 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4642 u32 cr0, u32 cr4, u32 efer,
4643 union kvm_mmu_role new_role)
4645 if (!(cr0 & X86_CR0_PG))
4646 nonpaging_init_context(vcpu, context);
4647 else if (efer & EFER_LMA)
4648 paging64_init_context(vcpu, context);
4649 else if (cr4 & X86_CR4_PAE)
4650 paging32E_init_context(vcpu, context);
4652 paging32_init_context(vcpu, context);
4654 context->mmu_role.as_u64 = new_role.as_u64;
4655 reset_shadow_zero_bits_mask(vcpu, context);
4658 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer)
4660 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4661 union kvm_mmu_role new_role =
4662 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4664 if (new_role.as_u64 != context->mmu_role.as_u64)
4665 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4668 static union kvm_mmu_role
4669 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu)
4671 union kvm_mmu_role role =
4672 kvm_calc_shadow_root_page_role_common(vcpu, false);
4674 role.base.direct = false;
4675 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4680 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer,
4683 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4684 union kvm_mmu_role new_role = kvm_calc_shadow_npt_root_page_role(vcpu);
4686 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base, false, false);
4688 if (new_role.as_u64 != context->mmu_role.as_u64) {
4689 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4692 * Override the level set by the common init helper, nested TDP
4693 * always uses the host's TDP configuration.
4695 context->shadow_root_level = new_role.base.level;
4698 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4700 static union kvm_mmu_role
4701 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4702 bool execonly, u8 level)
4704 union kvm_mmu_role role = {0};
4706 /* SMM flag is inherited from root_mmu */
4707 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4709 role.base.level = level;
4710 role.base.gpte_is_8_bytes = true;
4711 role.base.direct = false;
4712 role.base.ad_disabled = !accessed_dirty;
4713 role.base.guest_mode = true;
4714 role.base.access = ACC_ALL;
4717 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
4718 * SMAP variation to denote shadow EPT entries.
4720 role.base.cr0_wp = true;
4721 role.base.smap_andnot_wp = true;
4723 role.ext = kvm_calc_mmu_role_ext(vcpu);
4724 role.ext.execonly = execonly;
4729 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4730 bool accessed_dirty, gpa_t new_eptp)
4732 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4733 u8 level = vmx_eptp_page_walk_level(new_eptp);
4734 union kvm_mmu_role new_role =
4735 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4738 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base, true, true);
4740 if (new_role.as_u64 == context->mmu_role.as_u64)
4743 context->shadow_root_level = level;
4746 context->ept_ad = accessed_dirty;
4747 context->page_fault = ept_page_fault;
4748 context->gva_to_gpa = ept_gva_to_gpa;
4749 context->sync_page = ept_sync_page;
4750 context->invlpg = ept_invlpg;
4751 context->root_level = level;
4752 context->direct_map = false;
4753 context->mmu_role.as_u64 = new_role.as_u64;
4755 update_permission_bitmask(vcpu, context, true);
4756 update_pkru_bitmask(vcpu, context, true);
4757 update_last_nonleaf_level(vcpu, context);
4758 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4759 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4761 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4763 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4765 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4767 kvm_init_shadow_mmu(vcpu,
4768 kvm_read_cr0_bits(vcpu, X86_CR0_PG),
4769 kvm_read_cr4_bits(vcpu, X86_CR4_PAE),
4772 context->get_guest_pgd = get_cr3;
4773 context->get_pdptr = kvm_pdptr_read;
4774 context->inject_page_fault = kvm_inject_page_fault;
4777 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4779 union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false);
4780 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4782 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4785 g_context->mmu_role.as_u64 = new_role.as_u64;
4786 g_context->get_guest_pgd = get_cr3;
4787 g_context->get_pdptr = kvm_pdptr_read;
4788 g_context->inject_page_fault = kvm_inject_page_fault;
4791 * L2 page tables are never shadowed, so there is no need to sync
4794 g_context->invlpg = NULL;
4797 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4798 * L1's nested page tables (e.g. EPT12). The nested translation
4799 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4800 * L2's page tables as the first level of translation and L1's
4801 * nested page tables as the second level of translation. Basically
4802 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4804 if (!is_paging(vcpu)) {
4805 g_context->nx = false;
4806 g_context->root_level = 0;
4807 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4808 } else if (is_long_mode(vcpu)) {
4809 g_context->nx = is_nx(vcpu);
4810 g_context->root_level = is_la57_mode(vcpu) ?
4811 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4812 reset_rsvds_bits_mask(vcpu, g_context);
4813 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4814 } else if (is_pae(vcpu)) {
4815 g_context->nx = is_nx(vcpu);
4816 g_context->root_level = PT32E_ROOT_LEVEL;
4817 reset_rsvds_bits_mask(vcpu, g_context);
4818 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4820 g_context->nx = false;
4821 g_context->root_level = PT32_ROOT_LEVEL;
4822 reset_rsvds_bits_mask(vcpu, g_context);
4823 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4826 update_permission_bitmask(vcpu, g_context, false);
4827 update_pkru_bitmask(vcpu, g_context, false);
4828 update_last_nonleaf_level(vcpu, g_context);
4831 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
4836 vcpu->arch.mmu->root_hpa = INVALID_PAGE;
4838 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
4839 vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
4842 if (mmu_is_nested(vcpu))
4843 init_kvm_nested_mmu(vcpu);
4844 else if (tdp_enabled)
4845 init_kvm_tdp_mmu(vcpu);
4847 init_kvm_softmmu(vcpu);
4849 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4851 static union kvm_mmu_page_role
4852 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4854 union kvm_mmu_role role;
4857 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
4859 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
4864 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4866 kvm_mmu_unload(vcpu);
4867 kvm_init_mmu(vcpu, true);
4869 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4871 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4875 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
4878 r = mmu_alloc_special_roots(vcpu);
4881 if (vcpu->arch.mmu->direct_map)
4882 r = mmu_alloc_direct_roots(vcpu);
4884 r = mmu_alloc_shadow_roots(vcpu);
4888 kvm_mmu_sync_roots(vcpu);
4890 kvm_mmu_load_pgd(vcpu);
4891 static_call(kvm_x86_tlb_flush_current)(vcpu);
4896 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4898 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
4899 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
4900 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4901 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
4904 static bool need_remote_flush(u64 old, u64 new)
4906 if (!is_shadow_present_pte(old))
4908 if (!is_shadow_present_pte(new))
4910 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4912 old ^= shadow_nx_mask;
4913 new ^= shadow_nx_mask;
4914 return (old & ~new & PT64_PERM_MASK) != 0;
4917 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4924 * Assume that the pte write on a page table of the same type
4925 * as the current vcpu paging mode since we update the sptes only
4926 * when they have the same mode.
4928 if (is_pae(vcpu) && *bytes == 4) {
4929 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4934 if (*bytes == 4 || *bytes == 8) {
4935 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
4944 * If we're seeing too many writes to a page, it may no longer be a page table,
4945 * or we may be forking, in which case it is better to unmap the page.
4947 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4950 * Skip write-flooding detected for the sp whose level is 1, because
4951 * it can become unsync, then the guest page is not write-protected.
4953 if (sp->role.level == PG_LEVEL_4K)
4956 atomic_inc(&sp->write_flooding_count);
4957 return atomic_read(&sp->write_flooding_count) >= 3;
4961 * Misaligned accesses are too much trouble to fix up; also, they usually
4962 * indicate a page is not used as a page table.
4964 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4967 unsigned offset, pte_size, misaligned;
4969 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4970 gpa, bytes, sp->role.word);
4972 offset = offset_in_page(gpa);
4973 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
4976 * Sometimes, the OS only writes the last one bytes to update status
4977 * bits, for example, in linux, andb instruction is used in clear_bit().
4979 if (!(offset & (pte_size - 1)) && bytes == 1)
4982 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4983 misaligned |= bytes < 4;
4988 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4990 unsigned page_offset, quadrant;
4994 page_offset = offset_in_page(gpa);
4995 level = sp->role.level;
4997 if (!sp->role.gpte_is_8_bytes) {
4998 page_offset <<= 1; /* 32->64 */
5000 * A 32-bit pde maps 4MB while the shadow pdes map
5001 * only 2MB. So we need to double the offset again
5002 * and zap two pdes instead of one.
5004 if (level == PT32_ROOT_LEVEL) {
5005 page_offset &= ~7; /* kill rounding error */
5009 quadrant = page_offset >> PAGE_SHIFT;
5010 page_offset &= ~PAGE_MASK;
5011 if (quadrant != sp->role.quadrant)
5015 spte = &sp->spt[page_offset / sizeof(*spte)];
5019 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5020 const u8 *new, int bytes,
5021 struct kvm_page_track_notifier_node *node)
5023 gfn_t gfn = gpa >> PAGE_SHIFT;
5024 struct kvm_mmu_page *sp;
5025 LIST_HEAD(invalid_list);
5026 u64 entry, gentry, *spte;
5028 bool remote_flush, local_flush;
5031 * If we don't have indirect shadow pages, it means no page is
5032 * write-protected, so we can exit simply.
5034 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5037 remote_flush = local_flush = false;
5039 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5042 * No need to care whether allocation memory is successful
5043 * or not since pte prefetch is skiped if it does not have
5044 * enough objects in the cache.
5046 mmu_topup_memory_caches(vcpu, true);
5048 write_lock(&vcpu->kvm->mmu_lock);
5050 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5052 ++vcpu->kvm->stat.mmu_pte_write;
5053 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5055 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5056 if (detect_write_misaligned(sp, gpa, bytes) ||
5057 detect_write_flooding(sp)) {
5058 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5059 ++vcpu->kvm->stat.mmu_flooded;
5063 spte = get_written_sptes(sp, gpa, &npte);
5070 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
5071 if (gentry && sp->role.level != PG_LEVEL_4K)
5072 ++vcpu->kvm->stat.mmu_pde_zapped;
5073 if (need_remote_flush(entry, *spte))
5074 remote_flush = true;
5078 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5079 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5080 write_unlock(&vcpu->kvm->mmu_lock);
5083 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5084 void *insn, int insn_len)
5086 int r, emulation_type = EMULTYPE_PF;
5087 bool direct = vcpu->arch.mmu->direct_map;
5089 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5090 return RET_PF_RETRY;
5093 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5094 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5095 if (r == RET_PF_EMULATE)
5099 if (r == RET_PF_INVALID) {
5100 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5101 lower_32_bits(error_code), false);
5102 if (WARN_ON_ONCE(r == RET_PF_INVALID))
5108 if (r != RET_PF_EMULATE)
5112 * Before emulating the instruction, check if the error code
5113 * was due to a RO violation while translating the guest page.
5114 * This can occur when using nested virtualization with nested
5115 * paging in both guests. If true, we simply unprotect the page
5116 * and resume the guest.
5118 if (vcpu->arch.mmu->direct_map &&
5119 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5120 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5125 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5126 * optimistically try to just unprotect the page and let the processor
5127 * re-execute the instruction that caused the page fault. Do not allow
5128 * retrying MMIO emulation, as it's not only pointless but could also
5129 * cause us to enter an infinite loop because the processor will keep
5130 * faulting on the non-existent MMIO address. Retrying an instruction
5131 * from a nested guest is also pointless and dangerous as we are only
5132 * explicitly shadowing L1's page tables, i.e. unprotecting something
5133 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5135 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5136 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5138 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5141 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5143 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5144 gva_t gva, hpa_t root_hpa)
5148 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5149 if (mmu != &vcpu->arch.guest_mmu) {
5150 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5151 if (is_noncanonical_address(gva, vcpu))
5154 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5160 if (root_hpa == INVALID_PAGE) {
5161 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5164 * INVLPG is required to invalidate any global mappings for the VA,
5165 * irrespective of PCID. Since it would take us roughly similar amount
5166 * of work to determine whether any of the prev_root mappings of the VA
5167 * is marked global, or to just sync it blindly, so we might as well
5168 * just always sync it.
5170 * Mappings not reachable via the current cr3 or the prev_roots will be
5171 * synced when switching to that cr3, so nothing needs to be done here
5174 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5175 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5176 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5178 mmu->invlpg(vcpu, gva, root_hpa);
5182 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5184 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
5185 ++vcpu->stat.invlpg;
5187 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5190 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5192 struct kvm_mmu *mmu = vcpu->arch.mmu;
5193 bool tlb_flush = false;
5196 if (pcid == kvm_get_active_pcid(vcpu)) {
5197 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5201 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5202 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5203 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5204 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5210 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5212 ++vcpu->stat.invlpg;
5215 * Mappings not reachable via the current cr3 or the prev_roots will be
5216 * synced when switching to that cr3, so nothing needs to be done here
5221 void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
5222 int tdp_huge_page_level)
5224 tdp_enabled = enable_tdp;
5225 max_tdp_level = tdp_max_root_level;
5228 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5229 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5230 * the kernel is not. But, KVM never creates a page size greater than
5231 * what is used by the kernel for any given HVA, i.e. the kernel's
5232 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5235 max_huge_page_level = tdp_huge_page_level;
5236 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5237 max_huge_page_level = PG_LEVEL_1G;
5239 max_huge_page_level = PG_LEVEL_2M;
5241 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5243 /* The return value indicates if tlb flush on all vcpus is needed. */
5244 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head,
5245 struct kvm_memory_slot *slot);
5247 /* The caller should hold mmu-lock before calling this function. */
5248 static __always_inline bool
5249 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5250 slot_level_handler fn, int start_level, int end_level,
5251 gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield,
5254 struct slot_rmap_walk_iterator iterator;
5256 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5257 end_gfn, &iterator) {
5259 flush |= fn(kvm, iterator.rmap, memslot);
5261 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
5262 if (flush && flush_on_yield) {
5263 kvm_flush_remote_tlbs_with_address(kvm,
5265 iterator.gfn - start_gfn + 1);
5268 cond_resched_rwlock_write(&kvm->mmu_lock);
5275 static __always_inline bool
5276 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5277 slot_level_handler fn, int start_level, int end_level,
5278 bool flush_on_yield)
5280 return slot_handle_level_range(kvm, memslot, fn, start_level,
5281 end_level, memslot->base_gfn,
5282 memslot->base_gfn + memslot->npages - 1,
5283 flush_on_yield, false);
5286 static __always_inline bool
5287 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5288 slot_level_handler fn, bool flush_on_yield)
5290 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5291 PG_LEVEL_4K, flush_on_yield);
5294 static void free_mmu_pages(struct kvm_mmu *mmu)
5296 if (!tdp_enabled && mmu->pae_root)
5297 set_memory_encrypted((unsigned long)mmu->pae_root, 1);
5298 free_page((unsigned long)mmu->pae_root);
5299 free_page((unsigned long)mmu->lm_root);
5302 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5307 mmu->root_hpa = INVALID_PAGE;
5309 mmu->translate_gpa = translate_gpa;
5310 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5311 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5314 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5315 * while the PDP table is a per-vCPU construct that's allocated at MMU
5316 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5317 * x86_64. Therefore we need to allocate the PDP table in the first
5318 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5319 * generally doesn't use PAE paging and can skip allocating the PDP
5320 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5321 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5322 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
5324 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5327 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5331 mmu->pae_root = page_address(page);
5334 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5335 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5336 * that KVM's writes and the CPU's reads get along. Note, this is
5337 * only necessary when using shadow paging, as 64-bit NPT can get at
5338 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5339 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5342 set_memory_decrypted((unsigned long)mmu->pae_root, 1);
5344 WARN_ON_ONCE(shadow_me_mask);
5346 for (i = 0; i < 4; ++i)
5347 mmu->pae_root[i] = INVALID_PAE_ROOT;
5352 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5356 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5357 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5359 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5360 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5362 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5364 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5365 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5367 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5369 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5373 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5375 goto fail_allocate_root;
5379 free_mmu_pages(&vcpu->arch.guest_mmu);
5383 #define BATCH_ZAP_PAGES 10
5384 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5386 struct kvm_mmu_page *sp, *node;
5387 int nr_zapped, batch = 0;
5390 list_for_each_entry_safe_reverse(sp, node,
5391 &kvm->arch.active_mmu_pages, link) {
5393 * No obsolete valid page exists before a newly created page
5394 * since active_mmu_pages is a FIFO list.
5396 if (!is_obsolete_sp(kvm, sp))
5400 * Invalid pages should never land back on the list of active
5401 * pages. Skip the bogus page, otherwise we'll get stuck in an
5402 * infinite loop if the page gets put back on the list (again).
5404 if (WARN_ON(sp->role.invalid))
5408 * No need to flush the TLB since we're only zapping shadow
5409 * pages with an obsolete generation number and all vCPUS have
5410 * loaded a new root, i.e. the shadow pages being zapped cannot
5411 * be in active use by the guest.
5413 if (batch >= BATCH_ZAP_PAGES &&
5414 cond_resched_rwlock_write(&kvm->mmu_lock)) {
5419 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5420 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5427 * Trigger a remote TLB flush before freeing the page tables to ensure
5428 * KVM is not in the middle of a lockless shadow page table walk, which
5429 * may reference the pages.
5431 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5435 * Fast invalidate all shadow pages and use lock-break technique
5436 * to zap obsolete pages.
5438 * It's required when memslot is being deleted or VM is being
5439 * destroyed, in these cases, we should ensure that KVM MMU does
5440 * not use any resource of the being-deleted slot or all slots
5441 * after calling the function.
5443 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5445 lockdep_assert_held(&kvm->slots_lock);
5447 write_lock(&kvm->mmu_lock);
5448 trace_kvm_mmu_zap_all_fast(kvm);
5451 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5452 * held for the entire duration of zapping obsolete pages, it's
5453 * impossible for there to be multiple invalid generations associated
5454 * with *valid* shadow pages at any given time, i.e. there is exactly
5455 * one valid generation and (at most) one invalid generation.
5457 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5460 * Notify all vcpus to reload its shadow page table and flush TLB.
5461 * Then all vcpus will switch to new shadow page table with the new
5464 * Note: we need to do this under the protection of mmu_lock,
5465 * otherwise, vcpu would purge shadow page but miss tlb flush.
5467 kvm_reload_remote_mmus(kvm);
5469 kvm_zap_obsolete_pages(kvm);
5471 if (is_tdp_mmu_enabled(kvm))
5472 kvm_tdp_mmu_zap_all(kvm);
5474 write_unlock(&kvm->mmu_lock);
5477 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5479 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5482 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5483 struct kvm_memory_slot *slot,
5484 struct kvm_page_track_notifier_node *node)
5486 kvm_mmu_zap_all_fast(kvm);
5489 void kvm_mmu_init_vm(struct kvm *kvm)
5491 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5493 kvm_mmu_init_tdp_mmu(kvm);
5495 node->track_write = kvm_mmu_pte_write;
5496 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5497 kvm_page_track_register_notifier(kvm, node);
5500 void kvm_mmu_uninit_vm(struct kvm *kvm)
5502 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5504 kvm_page_track_unregister_notifier(kvm, node);
5506 kvm_mmu_uninit_tdp_mmu(kvm);
5509 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5511 struct kvm_memslots *slots;
5512 struct kvm_memory_slot *memslot;
5516 write_lock(&kvm->mmu_lock);
5517 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5518 slots = __kvm_memslots(kvm, i);
5519 kvm_for_each_memslot(memslot, slots) {
5522 start = max(gfn_start, memslot->base_gfn);
5523 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5527 flush = slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5529 KVM_MAX_HUGEPAGE_LEVEL,
5530 start, end - 1, true, flush);
5534 if (is_tdp_mmu_enabled(kvm)) {
5535 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++)
5536 flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start,
5541 kvm_flush_remote_tlbs_with_address(kvm, gfn_start, gfn_end);
5543 write_unlock(&kvm->mmu_lock);
5546 static bool slot_rmap_write_protect(struct kvm *kvm,
5547 struct kvm_rmap_head *rmap_head,
5548 struct kvm_memory_slot *slot)
5550 return __rmap_write_protect(kvm, rmap_head, false);
5553 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5554 struct kvm_memory_slot *memslot,
5559 write_lock(&kvm->mmu_lock);
5560 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5561 start_level, KVM_MAX_HUGEPAGE_LEVEL, false);
5562 if (is_tdp_mmu_enabled(kvm))
5563 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level);
5564 write_unlock(&kvm->mmu_lock);
5567 * We can flush all the TLBs out of the mmu lock without TLB
5568 * corruption since we just change the spte from writable to
5569 * readonly so that we only need to care the case of changing
5570 * spte from present to present (changing the spte from present
5571 * to nonpresent will flush all the TLBs immediately), in other
5572 * words, the only case we care is mmu_spte_update() where we
5573 * have checked Host-writable | MMU-writable instead of
5574 * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK
5578 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5581 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5582 struct kvm_rmap_head *rmap_head,
5583 struct kvm_memory_slot *slot)
5586 struct rmap_iterator iter;
5587 int need_tlb_flush = 0;
5589 struct kvm_mmu_page *sp;
5592 for_each_rmap_spte(rmap_head, &iter, sptep) {
5593 sp = sptep_to_sp(sptep);
5594 pfn = spte_to_pfn(*sptep);
5597 * We cannot do huge page mapping for indirect shadow pages,
5598 * which are found on the last rmap (level = 1) when not using
5599 * tdp; such shadow pages are synced with the page table in
5600 * the guest, and the guest page table is using 4K page size
5601 * mapping if the indirect sp has level = 1.
5603 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5604 sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn,
5605 pfn, PG_LEVEL_NUM)) {
5606 pte_list_remove(rmap_head, sptep);
5608 if (kvm_available_flush_tlb_with_range())
5609 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5610 KVM_PAGES_PER_HPAGE(sp->role.level));
5618 return need_tlb_flush;
5621 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5622 const struct kvm_memory_slot *memslot)
5624 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5625 struct kvm_memory_slot *slot = (struct kvm_memory_slot *)memslot;
5628 write_lock(&kvm->mmu_lock);
5629 flush = slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true);
5631 if (is_tdp_mmu_enabled(kvm))
5632 flush = kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot, flush);
5635 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5637 write_unlock(&kvm->mmu_lock);
5640 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5641 struct kvm_memory_slot *memslot)
5644 * All current use cases for flushing the TLBs for a specific memslot
5645 * related to dirty logging, and many do the TLB flush out of mmu_lock.
5646 * The interaction between the various operations on memslot must be
5647 * serialized by slots_locks to ensure the TLB flush from one operation
5648 * is observed by any other operation on the same memslot.
5650 lockdep_assert_held(&kvm->slots_lock);
5651 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5655 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5656 struct kvm_memory_slot *memslot)
5660 write_lock(&kvm->mmu_lock);
5661 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5662 if (is_tdp_mmu_enabled(kvm))
5663 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5664 write_unlock(&kvm->mmu_lock);
5667 * It's also safe to flush TLBs out of mmu lock here as currently this
5668 * function is only used for dirty logging, in which case flushing TLB
5669 * out of mmu lock also guarantees no dirty pages will be lost in
5673 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5676 void kvm_mmu_zap_all(struct kvm *kvm)
5678 struct kvm_mmu_page *sp, *node;
5679 LIST_HEAD(invalid_list);
5682 write_lock(&kvm->mmu_lock);
5684 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5685 if (WARN_ON(sp->role.invalid))
5687 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5689 if (cond_resched_rwlock_write(&kvm->mmu_lock))
5693 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5695 if (is_tdp_mmu_enabled(kvm))
5696 kvm_tdp_mmu_zap_all(kvm);
5698 write_unlock(&kvm->mmu_lock);
5701 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5703 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5705 gen &= MMIO_SPTE_GEN_MASK;
5708 * Generation numbers are incremented in multiples of the number of
5709 * address spaces in order to provide unique generations across all
5710 * address spaces. Strip what is effectively the address space
5711 * modifier prior to checking for a wrap of the MMIO generation so
5712 * that a wrap in any address space is detected.
5714 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5717 * The very rare case: if the MMIO generation number has wrapped,
5718 * zap all shadow pages.
5720 if (unlikely(gen == 0)) {
5721 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5722 kvm_mmu_zap_all_fast(kvm);
5726 static unsigned long
5727 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5730 int nr_to_scan = sc->nr_to_scan;
5731 unsigned long freed = 0;
5733 mutex_lock(&kvm_lock);
5735 list_for_each_entry(kvm, &vm_list, vm_list) {
5737 LIST_HEAD(invalid_list);
5740 * Never scan more than sc->nr_to_scan VM instances.
5741 * Will not hit this condition practically since we do not try
5742 * to shrink more than one VM and it is very unlikely to see
5743 * !n_used_mmu_pages so many times.
5748 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5749 * here. We may skip a VM instance errorneosly, but we do not
5750 * want to shrink a VM that only started to populate its MMU
5753 if (!kvm->arch.n_used_mmu_pages &&
5754 !kvm_has_zapped_obsolete_pages(kvm))
5757 idx = srcu_read_lock(&kvm->srcu);
5758 write_lock(&kvm->mmu_lock);
5760 if (kvm_has_zapped_obsolete_pages(kvm)) {
5761 kvm_mmu_commit_zap_page(kvm,
5762 &kvm->arch.zapped_obsolete_pages);
5766 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
5769 write_unlock(&kvm->mmu_lock);
5770 srcu_read_unlock(&kvm->srcu, idx);
5773 * unfair on small ones
5774 * per-vm shrinkers cry out
5775 * sadness comes quickly
5777 list_move_tail(&kvm->vm_list, &vm_list);
5781 mutex_unlock(&kvm_lock);
5785 static unsigned long
5786 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5788 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5791 static struct shrinker mmu_shrinker = {
5792 .count_objects = mmu_shrink_count,
5793 .scan_objects = mmu_shrink_scan,
5794 .seeks = DEFAULT_SEEKS * 10,
5797 static void mmu_destroy_caches(void)
5799 kmem_cache_destroy(pte_list_desc_cache);
5800 kmem_cache_destroy(mmu_page_header_cache);
5803 static bool get_nx_auto_mode(void)
5805 /* Return true when CPU has the bug, and mitigations are ON */
5806 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5809 static void __set_nx_huge_pages(bool val)
5811 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5814 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5816 bool old_val = nx_huge_pages;
5819 /* In "auto" mode deploy workaround only if CPU has the bug. */
5820 if (sysfs_streq(val, "off"))
5822 else if (sysfs_streq(val, "force"))
5824 else if (sysfs_streq(val, "auto"))
5825 new_val = get_nx_auto_mode();
5826 else if (strtobool(val, &new_val) < 0)
5829 __set_nx_huge_pages(new_val);
5831 if (new_val != old_val) {
5834 mutex_lock(&kvm_lock);
5836 list_for_each_entry(kvm, &vm_list, vm_list) {
5837 mutex_lock(&kvm->slots_lock);
5838 kvm_mmu_zap_all_fast(kvm);
5839 mutex_unlock(&kvm->slots_lock);
5841 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5843 mutex_unlock(&kvm_lock);
5849 int kvm_mmu_module_init(void)
5853 if (nx_huge_pages == -1)
5854 __set_nx_huge_pages(get_nx_auto_mode());
5857 * MMU roles use union aliasing which is, generally speaking, an
5858 * undefined behavior. However, we supposedly know how compilers behave
5859 * and the current status quo is unlikely to change. Guardians below are
5860 * supposed to let us know if the assumption becomes false.
5862 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
5863 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
5864 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
5866 kvm_mmu_reset_all_pte_masks();
5868 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5869 sizeof(struct pte_list_desc),
5870 0, SLAB_ACCOUNT, NULL);
5871 if (!pte_list_desc_cache)
5874 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5875 sizeof(struct kvm_mmu_page),
5876 0, SLAB_ACCOUNT, NULL);
5877 if (!mmu_page_header_cache)
5880 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5883 ret = register_shrinker(&mmu_shrinker);
5890 mmu_destroy_caches();
5895 * Calculate mmu pages needed for kvm.
5897 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
5899 unsigned long nr_mmu_pages;
5900 unsigned long nr_pages = 0;
5901 struct kvm_memslots *slots;
5902 struct kvm_memory_slot *memslot;
5905 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5906 slots = __kvm_memslots(kvm, i);
5908 kvm_for_each_memslot(memslot, slots)
5909 nr_pages += memslot->npages;
5912 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5913 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
5915 return nr_mmu_pages;
5918 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5920 kvm_mmu_unload(vcpu);
5921 free_mmu_pages(&vcpu->arch.root_mmu);
5922 free_mmu_pages(&vcpu->arch.guest_mmu);
5923 mmu_free_memory_caches(vcpu);
5926 void kvm_mmu_module_exit(void)
5928 mmu_destroy_caches();
5929 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5930 unregister_shrinker(&mmu_shrinker);
5931 mmu_audit_disable();
5934 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
5936 unsigned int old_val;
5939 old_val = nx_huge_pages_recovery_ratio;
5940 err = param_set_uint(val, kp);
5944 if (READ_ONCE(nx_huge_pages) &&
5945 !old_val && nx_huge_pages_recovery_ratio) {
5948 mutex_lock(&kvm_lock);
5950 list_for_each_entry(kvm, &vm_list, vm_list)
5951 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5953 mutex_unlock(&kvm_lock);
5959 static void kvm_recover_nx_lpages(struct kvm *kvm)
5962 struct kvm_mmu_page *sp;
5964 LIST_HEAD(invalid_list);
5968 rcu_idx = srcu_read_lock(&kvm->srcu);
5969 write_lock(&kvm->mmu_lock);
5971 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
5972 to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0;
5973 for ( ; to_zap; --to_zap) {
5974 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
5978 * We use a separate list instead of just using active_mmu_pages
5979 * because the number of lpage_disallowed pages is expected to
5980 * be relatively small compared to the total.
5982 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
5983 struct kvm_mmu_page,
5984 lpage_disallowed_link);
5985 WARN_ON_ONCE(!sp->lpage_disallowed);
5986 if (is_tdp_mmu_page(sp)) {
5987 flush = kvm_tdp_mmu_zap_sp(kvm, sp);
5989 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
5990 WARN_ON_ONCE(sp->lpage_disallowed);
5993 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
5994 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
5995 cond_resched_rwlock_write(&kvm->mmu_lock);
5999 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6001 write_unlock(&kvm->mmu_lock);
6002 srcu_read_unlock(&kvm->srcu, rcu_idx);
6005 static long get_nx_lpage_recovery_timeout(u64 start_time)
6007 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6008 ? start_time + 60 * HZ - get_jiffies_64()
6009 : MAX_SCHEDULE_TIMEOUT;
6012 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6015 long remaining_time;
6018 start_time = get_jiffies_64();
6019 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6021 set_current_state(TASK_INTERRUPTIBLE);
6022 while (!kthread_should_stop() && remaining_time > 0) {
6023 schedule_timeout(remaining_time);
6024 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6025 set_current_state(TASK_INTERRUPTIBLE);
6028 set_current_state(TASK_RUNNING);
6030 if (kthread_should_stop())
6033 kvm_recover_nx_lpages(kvm);
6037 int kvm_mmu_post_init_vm(struct kvm *kvm)
6041 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6042 "kvm-nx-lpage-recovery",
6043 &kvm->arch.nx_lpage_recovery_thread);
6045 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6050 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6052 if (kvm->arch.nx_lpage_recovery_thread)
6053 kthread_stop(kvm->arch.nx_lpage_recovery_thread);