1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
22 #include "kvm_cache_regs.h"
23 #include "kvm_emulate.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/moduleparam.h>
32 #include <linux/export.h>
33 #include <linux/swap.h>
34 #include <linux/hugetlb.h>
35 #include <linux/compiler.h>
36 #include <linux/srcu.h>
37 #include <linux/slab.h>
38 #include <linux/sched/signal.h>
39 #include <linux/uaccess.h>
40 #include <linux/hash.h>
41 #include <linux/kern_levels.h>
42 #include <linux/kthread.h>
45 #include <asm/memtype.h>
46 #include <asm/cmpxchg.h>
47 #include <asm/e820/api.h>
50 #include <asm/kvm_page_track.h>
53 extern bool itlb_multihit_kvm_mitigation;
55 static int __read_mostly nx_huge_pages = -1;
56 #ifdef CONFIG_PREEMPT_RT
57 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
58 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
60 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
63 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
64 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
66 static struct kernel_param_ops nx_huge_pages_ops = {
67 .set = set_nx_huge_pages,
68 .get = param_get_bool,
71 static struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
72 .set = set_nx_huge_pages_recovery_ratio,
73 .get = param_get_uint,
76 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
77 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
78 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
79 &nx_huge_pages_recovery_ratio, 0644);
80 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
82 static bool __read_mostly force_flush_and_sync_on_reuse;
83 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
86 * When setting this variable to true it enables Two-Dimensional-Paging
87 * where the hardware walks 2 page tables:
88 * 1. the guest-virtual to guest-physical
89 * 2. while doing 1. it walks guest-physical to host-physical
90 * If the hardware supports that we don't need to do shadow paging.
92 bool tdp_enabled = false;
94 static int max_page_level __read_mostly;
98 AUDIT_POST_PAGE_FAULT,
100 AUDIT_POST_PTE_WRITE,
109 module_param(dbg, bool, 0644);
111 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
112 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
113 #define MMU_WARN_ON(x) WARN_ON(x)
115 #define pgprintk(x...) do { } while (0)
116 #define rmap_printk(x...) do { } while (0)
117 #define MMU_WARN_ON(x) do { } while (0)
120 #define PTE_PREFETCH_NUM 8
122 #define PT_FIRST_AVAIL_BITS_SHIFT 10
123 #define PT64_SECOND_AVAIL_BITS_SHIFT 54
126 * The mask used to denote special SPTEs, which can be either MMIO SPTEs or
127 * Access Tracking SPTEs.
129 #define SPTE_SPECIAL_MASK (3ULL << 52)
130 #define SPTE_AD_ENABLED_MASK (0ULL << 52)
131 #define SPTE_AD_DISABLED_MASK (1ULL << 52)
132 #define SPTE_AD_WRPROT_ONLY_MASK (2ULL << 52)
133 #define SPTE_MMIO_MASK (3ULL << 52)
135 #define PT64_LEVEL_BITS 9
137 #define PT64_LEVEL_SHIFT(level) \
138 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
140 #define PT64_INDEX(address, level)\
141 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
144 #define PT32_LEVEL_BITS 10
146 #define PT32_LEVEL_SHIFT(level) \
147 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
149 #define PT32_LVL_OFFSET_MASK(level) \
150 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
151 * PT32_LEVEL_BITS))) - 1))
153 #define PT32_INDEX(address, level)\
154 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
157 #ifdef CONFIG_DYNAMIC_PHYSICAL_MASK
158 #define PT64_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1))
160 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
162 #define PT64_LVL_ADDR_MASK(level) \
163 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
164 * PT64_LEVEL_BITS))) - 1))
165 #define PT64_LVL_OFFSET_MASK(level) \
166 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
167 * PT64_LEVEL_BITS))) - 1))
169 #define PT32_BASE_ADDR_MASK PAGE_MASK
170 #define PT32_DIR_BASE_ADDR_MASK \
171 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
172 #define PT32_LVL_ADDR_MASK(level) \
173 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
174 * PT32_LEVEL_BITS))) - 1))
176 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
177 | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
179 #define ACC_EXEC_MASK 1
180 #define ACC_WRITE_MASK PT_WRITABLE_MASK
181 #define ACC_USER_MASK PT_USER_MASK
182 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
184 /* The mask for the R/X bits in EPT PTEs */
185 #define PT64_EPT_READABLE_MASK 0x1ull
186 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
188 #include <trace/events/kvm.h>
190 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
191 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
193 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
195 /* make pte_list_desc fit well in cache line */
196 #define PTE_LIST_EXT 3
199 * Return values of handle_mmio_page_fault and mmu.page_fault:
200 * RET_PF_RETRY: let CPU fault again on the address.
201 * RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
203 * For handle_mmio_page_fault only:
204 * RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
212 struct pte_list_desc {
213 u64 *sptes[PTE_LIST_EXT];
214 struct pte_list_desc *more;
217 struct kvm_shadow_walk_iterator {
225 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
226 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
228 shadow_walk_okay(&(_walker)); \
229 shadow_walk_next(&(_walker)))
231 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
232 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
233 shadow_walk_okay(&(_walker)); \
234 shadow_walk_next(&(_walker)))
236 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
237 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
238 shadow_walk_okay(&(_walker)) && \
239 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
240 __shadow_walk_next(&(_walker), spte))
242 static struct kmem_cache *pte_list_desc_cache;
243 static struct kmem_cache *mmu_page_header_cache;
244 static struct percpu_counter kvm_total_used_mmu_pages;
246 static u64 __read_mostly shadow_nx_mask;
247 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
248 static u64 __read_mostly shadow_user_mask;
249 static u64 __read_mostly shadow_accessed_mask;
250 static u64 __read_mostly shadow_dirty_mask;
251 static u64 __read_mostly shadow_mmio_value;
252 static u64 __read_mostly shadow_mmio_access_mask;
253 static u64 __read_mostly shadow_present_mask;
254 static u64 __read_mostly shadow_me_mask;
257 * SPTEs used by MMUs without A/D bits are marked with SPTE_AD_DISABLED_MASK;
258 * shadow_acc_track_mask is the set of bits to be cleared in non-accessed
261 static u64 __read_mostly shadow_acc_track_mask;
264 * The mask/shift to use for saving the original R/X bits when marking the PTE
265 * as not-present for access tracking purposes. We do not save the W bit as the
266 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
267 * restored only when a write is attempted to the page.
269 static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
270 PT64_EPT_EXECUTABLE_MASK;
271 static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
274 * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order
275 * to guard against L1TF attacks.
277 static u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
280 * The number of high-order 1 bits to use in the mask above.
282 static const u64 shadow_nonpresent_or_rsvd_mask_len = 5;
285 * In some cases, we need to preserve the GFN of a non-present or reserved
286 * SPTE when we usurp the upper five bits of the physical address space to
287 * defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll
288 * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask
289 * left into the reserved bits, i.e. the GFN in the SPTE will be split into
290 * high and low parts. This mask covers the lower bits of the GFN.
292 static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
295 * The number of non-reserved physical address bits irrespective of features
296 * that repurpose legal bits, e.g. MKTME.
298 static u8 __read_mostly shadow_phys_bits;
300 static void mmu_spte_set(u64 *sptep, u64 spte);
301 static bool is_executable_pte(u64 spte);
302 static union kvm_mmu_page_role
303 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
305 #define CREATE_TRACE_POINTS
306 #include "mmutrace.h"
309 static inline bool kvm_available_flush_tlb_with_range(void)
311 return kvm_x86_ops.tlb_remote_flush_with_range;
314 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
315 struct kvm_tlb_range *range)
319 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
320 ret = kvm_x86_ops.tlb_remote_flush_with_range(kvm, range);
323 kvm_flush_remote_tlbs(kvm);
326 static void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
327 u64 start_gfn, u64 pages)
329 struct kvm_tlb_range range;
331 range.start_gfn = start_gfn;
334 kvm_flush_remote_tlbs_with_range(kvm, &range);
337 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 access_mask)
339 BUG_ON((u64)(unsigned)access_mask != access_mask);
340 WARN_ON(mmio_value & (shadow_nonpresent_or_rsvd_mask << shadow_nonpresent_or_rsvd_mask_len));
341 WARN_ON(mmio_value & shadow_nonpresent_or_rsvd_lower_gfn_mask);
342 shadow_mmio_value = mmio_value | SPTE_MMIO_MASK;
343 shadow_mmio_access_mask = access_mask;
345 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
347 static bool is_mmio_spte(u64 spte)
349 return (spte & SPTE_SPECIAL_MASK) == SPTE_MMIO_MASK;
352 static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
354 return sp->role.ad_disabled;
357 static inline bool kvm_vcpu_ad_need_write_protect(struct kvm_vcpu *vcpu)
360 * When using the EPT page-modification log, the GPAs in the log
361 * would come from L2 rather than L1. Therefore, we need to rely
362 * on write protection to record dirty pages. This also bypasses
363 * PML, since writes now result in a vmexit.
365 return vcpu->arch.mmu == &vcpu->arch.guest_mmu;
368 static inline bool spte_ad_enabled(u64 spte)
370 MMU_WARN_ON(is_mmio_spte(spte));
371 return (spte & SPTE_SPECIAL_MASK) != SPTE_AD_DISABLED_MASK;
374 static inline bool spte_ad_need_write_protect(u64 spte)
376 MMU_WARN_ON(is_mmio_spte(spte));
377 return (spte & SPTE_SPECIAL_MASK) != SPTE_AD_ENABLED_MASK;
380 static bool is_nx_huge_page_enabled(void)
382 return READ_ONCE(nx_huge_pages);
385 static inline u64 spte_shadow_accessed_mask(u64 spte)
387 MMU_WARN_ON(is_mmio_spte(spte));
388 return spte_ad_enabled(spte) ? shadow_accessed_mask : 0;
391 static inline u64 spte_shadow_dirty_mask(u64 spte)
393 MMU_WARN_ON(is_mmio_spte(spte));
394 return spte_ad_enabled(spte) ? shadow_dirty_mask : 0;
397 static inline bool is_access_track_spte(u64 spte)
399 return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0;
403 * Due to limited space in PTEs, the MMIO generation is a 19 bit subset of
404 * the memslots generation and is derived as follows:
406 * Bits 0-8 of the MMIO generation are propagated to spte bits 3-11
407 * Bits 9-18 of the MMIO generation are propagated to spte bits 52-61
409 * The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not included in
410 * the MMIO generation number, as doing so would require stealing a bit from
411 * the "real" generation number and thus effectively halve the maximum number
412 * of MMIO generations that can be handled before encountering a wrap (which
413 * requires a full MMU zap). The flag is instead explicitly queried when
414 * checking for MMIO spte cache hits.
416 #define MMIO_SPTE_GEN_MASK GENMASK_ULL(17, 0)
418 #define MMIO_SPTE_GEN_LOW_START 3
419 #define MMIO_SPTE_GEN_LOW_END 11
420 #define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \
421 MMIO_SPTE_GEN_LOW_START)
423 #define MMIO_SPTE_GEN_HIGH_START PT64_SECOND_AVAIL_BITS_SHIFT
424 #define MMIO_SPTE_GEN_HIGH_END 62
425 #define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \
426 MMIO_SPTE_GEN_HIGH_START)
428 static u64 generation_mmio_spte_mask(u64 gen)
432 WARN_ON(gen & ~MMIO_SPTE_GEN_MASK);
433 BUILD_BUG_ON((MMIO_SPTE_GEN_HIGH_MASK | MMIO_SPTE_GEN_LOW_MASK) & SPTE_SPECIAL_MASK);
435 mask = (gen << MMIO_SPTE_GEN_LOW_START) & MMIO_SPTE_GEN_LOW_MASK;
436 mask |= (gen << MMIO_SPTE_GEN_HIGH_START) & MMIO_SPTE_GEN_HIGH_MASK;
440 static u64 get_mmio_spte_generation(u64 spte)
444 gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_START;
445 gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_START;
449 static u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access)
452 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK;
453 u64 mask = generation_mmio_spte_mask(gen);
454 u64 gpa = gfn << PAGE_SHIFT;
456 access &= shadow_mmio_access_mask;
457 mask |= shadow_mmio_value | access;
458 mask |= gpa | shadow_nonpresent_or_rsvd_mask;
459 mask |= (gpa & shadow_nonpresent_or_rsvd_mask)
460 << shadow_nonpresent_or_rsvd_mask_len;
465 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
468 u64 mask = make_mmio_spte(vcpu, gfn, access);
469 unsigned int gen = get_mmio_spte_generation(mask);
471 access = mask & ACC_ALL;
473 trace_mark_mmio_spte(sptep, gfn, access, gen);
474 mmu_spte_set(sptep, mask);
477 static gfn_t get_mmio_spte_gfn(u64 spte)
479 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
481 gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len)
482 & shadow_nonpresent_or_rsvd_mask;
484 return gpa >> PAGE_SHIFT;
487 static unsigned get_mmio_spte_access(u64 spte)
489 return spte & shadow_mmio_access_mask;
492 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
493 kvm_pfn_t pfn, unsigned int access)
495 if (unlikely(is_noslot_pfn(pfn))) {
496 mark_mmio_spte(vcpu, sptep, gfn, access);
503 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
505 u64 kvm_gen, spte_gen, gen;
507 gen = kvm_vcpu_memslots(vcpu)->generation;
508 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
511 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
512 spte_gen = get_mmio_spte_generation(spte);
514 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
515 return likely(kvm_gen == spte_gen);
519 * Sets the shadow PTE masks used by the MMU.
522 * - Setting either @accessed_mask or @dirty_mask requires setting both
523 * - At least one of @accessed_mask or @acc_track_mask must be set
525 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
526 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
527 u64 acc_track_mask, u64 me_mask)
529 BUG_ON(!dirty_mask != !accessed_mask);
530 BUG_ON(!accessed_mask && !acc_track_mask);
531 BUG_ON(acc_track_mask & SPTE_SPECIAL_MASK);
533 shadow_user_mask = user_mask;
534 shadow_accessed_mask = accessed_mask;
535 shadow_dirty_mask = dirty_mask;
536 shadow_nx_mask = nx_mask;
537 shadow_x_mask = x_mask;
538 shadow_present_mask = p_mask;
539 shadow_acc_track_mask = acc_track_mask;
540 shadow_me_mask = me_mask;
542 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
544 static u8 kvm_get_shadow_phys_bits(void)
547 * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected
548 * in CPU detection code, but the processor treats those reduced bits as
549 * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at
550 * the physical address bits reported by CPUID.
552 if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008))
553 return cpuid_eax(0x80000008) & 0xff;
556 * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with
557 * custom CPUID. Proceed with whatever the kernel found since these features
558 * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008).
560 return boot_cpu_data.x86_phys_bits;
563 static void kvm_mmu_reset_all_pte_masks(void)
567 shadow_user_mask = 0;
568 shadow_accessed_mask = 0;
569 shadow_dirty_mask = 0;
572 shadow_present_mask = 0;
573 shadow_acc_track_mask = 0;
575 shadow_phys_bits = kvm_get_shadow_phys_bits();
578 * If the CPU has 46 or less physical address bits, then set an
579 * appropriate mask to guard against L1TF attacks. Otherwise, it is
580 * assumed that the CPU is not vulnerable to L1TF.
582 * Some Intel CPUs address the L1 cache using more PA bits than are
583 * reported by CPUID. Use the PA width of the L1 cache when possible
584 * to achieve more effective mitigation, e.g. if system RAM overlaps
585 * the most significant bits of legal physical address space.
587 shadow_nonpresent_or_rsvd_mask = 0;
588 low_phys_bits = boot_cpu_data.x86_phys_bits;
589 if (boot_cpu_has_bug(X86_BUG_L1TF) &&
590 !WARN_ON_ONCE(boot_cpu_data.x86_cache_bits >=
591 52 - shadow_nonpresent_or_rsvd_mask_len)) {
592 low_phys_bits = boot_cpu_data.x86_cache_bits
593 - shadow_nonpresent_or_rsvd_mask_len;
594 shadow_nonpresent_or_rsvd_mask =
595 rsvd_bits(low_phys_bits, boot_cpu_data.x86_cache_bits - 1);
598 shadow_nonpresent_or_rsvd_lower_gfn_mask =
599 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);
602 static int is_cpuid_PSE36(void)
607 static int is_nx(struct kvm_vcpu *vcpu)
609 return vcpu->arch.efer & EFER_NX;
612 static int is_shadow_present_pte(u64 pte)
614 return (pte != 0) && !is_mmio_spte(pte);
617 static int is_large_pte(u64 pte)
619 return pte & PT_PAGE_SIZE_MASK;
622 static int is_last_spte(u64 pte, int level)
624 if (level == PG_LEVEL_4K)
626 if (is_large_pte(pte))
631 static bool is_executable_pte(u64 spte)
633 return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
636 static kvm_pfn_t spte_to_pfn(u64 pte)
638 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
641 static gfn_t pse36_gfn_delta(u32 gpte)
643 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
645 return (gpte & PT32_DIR_PSE36_MASK) << shift;
649 static void __set_spte(u64 *sptep, u64 spte)
651 WRITE_ONCE(*sptep, spte);
654 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
656 WRITE_ONCE(*sptep, spte);
659 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
661 return xchg(sptep, spte);
664 static u64 __get_spte_lockless(u64 *sptep)
666 return READ_ONCE(*sptep);
677 static void count_spte_clear(u64 *sptep, u64 spte)
679 struct kvm_mmu_page *sp = page_header(__pa(sptep));
681 if (is_shadow_present_pte(spte))
684 /* Ensure the spte is completely set before we increase the count */
686 sp->clear_spte_count++;
689 static void __set_spte(u64 *sptep, u64 spte)
691 union split_spte *ssptep, sspte;
693 ssptep = (union split_spte *)sptep;
694 sspte = (union split_spte)spte;
696 ssptep->spte_high = sspte.spte_high;
699 * If we map the spte from nonpresent to present, We should store
700 * the high bits firstly, then set present bit, so cpu can not
701 * fetch this spte while we are setting the spte.
705 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
708 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
710 union split_spte *ssptep, sspte;
712 ssptep = (union split_spte *)sptep;
713 sspte = (union split_spte)spte;
715 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
718 * If we map the spte from present to nonpresent, we should clear
719 * present bit firstly to avoid vcpu fetch the old high bits.
723 ssptep->spte_high = sspte.spte_high;
724 count_spte_clear(sptep, spte);
727 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
729 union split_spte *ssptep, sspte, orig;
731 ssptep = (union split_spte *)sptep;
732 sspte = (union split_spte)spte;
734 /* xchg acts as a barrier before the setting of the high bits */
735 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
736 orig.spte_high = ssptep->spte_high;
737 ssptep->spte_high = sspte.spte_high;
738 count_spte_clear(sptep, spte);
744 * The idea using the light way get the spte on x86_32 guest is from
745 * gup_get_pte (mm/gup.c).
747 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
748 * coalesces them and we are running out of the MMU lock. Therefore
749 * we need to protect against in-progress updates of the spte.
751 * Reading the spte while an update is in progress may get the old value
752 * for the high part of the spte. The race is fine for a present->non-present
753 * change (because the high part of the spte is ignored for non-present spte),
754 * but for a present->present change we must reread the spte.
756 * All such changes are done in two steps (present->non-present and
757 * non-present->present), hence it is enough to count the number of
758 * present->non-present updates: if it changed while reading the spte,
759 * we might have hit the race. This is done using clear_spte_count.
761 static u64 __get_spte_lockless(u64 *sptep)
763 struct kvm_mmu_page *sp = page_header(__pa(sptep));
764 union split_spte spte, *orig = (union split_spte *)sptep;
768 count = sp->clear_spte_count;
771 spte.spte_low = orig->spte_low;
774 spte.spte_high = orig->spte_high;
777 if (unlikely(spte.spte_low != orig->spte_low ||
778 count != sp->clear_spte_count))
785 static bool spte_can_locklessly_be_made_writable(u64 spte)
787 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
788 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
791 static bool spte_has_volatile_bits(u64 spte)
793 if (!is_shadow_present_pte(spte))
797 * Always atomically update spte if it can be updated
798 * out of mmu-lock, it can ensure dirty bit is not lost,
799 * also, it can help us to get a stable is_writable_pte()
800 * to ensure tlb flush is not missed.
802 if (spte_can_locklessly_be_made_writable(spte) ||
803 is_access_track_spte(spte))
806 if (spte_ad_enabled(spte)) {
807 if ((spte & shadow_accessed_mask) == 0 ||
808 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
815 static bool is_accessed_spte(u64 spte)
817 u64 accessed_mask = spte_shadow_accessed_mask(spte);
819 return accessed_mask ? spte & accessed_mask
820 : !is_access_track_spte(spte);
823 static bool is_dirty_spte(u64 spte)
825 u64 dirty_mask = spte_shadow_dirty_mask(spte);
827 return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK;
830 /* Rules for using mmu_spte_set:
831 * Set the sptep from nonpresent to present.
832 * Note: the sptep being assigned *must* be either not present
833 * or in a state where the hardware will not attempt to update
836 static void mmu_spte_set(u64 *sptep, u64 new_spte)
838 WARN_ON(is_shadow_present_pte(*sptep));
839 __set_spte(sptep, new_spte);
843 * Update the SPTE (excluding the PFN), but do not track changes in its
844 * accessed/dirty status.
846 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
848 u64 old_spte = *sptep;
850 WARN_ON(!is_shadow_present_pte(new_spte));
852 if (!is_shadow_present_pte(old_spte)) {
853 mmu_spte_set(sptep, new_spte);
857 if (!spte_has_volatile_bits(old_spte))
858 __update_clear_spte_fast(sptep, new_spte);
860 old_spte = __update_clear_spte_slow(sptep, new_spte);
862 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
867 /* Rules for using mmu_spte_update:
868 * Update the state bits, it means the mapped pfn is not changed.
870 * Whenever we overwrite a writable spte with a read-only one we
871 * should flush remote TLBs. Otherwise rmap_write_protect
872 * will find a read-only spte, even though the writable spte
873 * might be cached on a CPU's TLB, the return value indicates this
876 * Returns true if the TLB needs to be flushed
878 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
881 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
883 if (!is_shadow_present_pte(old_spte))
887 * For the spte updated out of mmu-lock is safe, since
888 * we always atomically update it, see the comments in
889 * spte_has_volatile_bits().
891 if (spte_can_locklessly_be_made_writable(old_spte) &&
892 !is_writable_pte(new_spte))
896 * Flush TLB when accessed/dirty states are changed in the page tables,
897 * to guarantee consistency between TLB and page tables.
900 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
902 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
905 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
907 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
914 * Rules for using mmu_spte_clear_track_bits:
915 * It sets the sptep from present to nonpresent, and track the
916 * state bits, it is used to clear the last level sptep.
917 * Returns non-zero if the PTE was previously valid.
919 static int mmu_spte_clear_track_bits(u64 *sptep)
922 u64 old_spte = *sptep;
924 if (!spte_has_volatile_bits(old_spte))
925 __update_clear_spte_fast(sptep, 0ull);
927 old_spte = __update_clear_spte_slow(sptep, 0ull);
929 if (!is_shadow_present_pte(old_spte))
932 pfn = spte_to_pfn(old_spte);
935 * KVM does not hold the refcount of the page used by
936 * kvm mmu, before reclaiming the page, we should
937 * unmap it from mmu first.
939 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
941 if (is_accessed_spte(old_spte))
942 kvm_set_pfn_accessed(pfn);
944 if (is_dirty_spte(old_spte))
945 kvm_set_pfn_dirty(pfn);
951 * Rules for using mmu_spte_clear_no_track:
952 * Directly clear spte without caring the state bits of sptep,
953 * it is used to set the upper level spte.
955 static void mmu_spte_clear_no_track(u64 *sptep)
957 __update_clear_spte_fast(sptep, 0ull);
960 static u64 mmu_spte_get_lockless(u64 *sptep)
962 return __get_spte_lockless(sptep);
965 static u64 mark_spte_for_access_track(u64 spte)
967 if (spte_ad_enabled(spte))
968 return spte & ~shadow_accessed_mask;
970 if (is_access_track_spte(spte))
974 * Making an Access Tracking PTE will result in removal of write access
975 * from the PTE. So, verify that we will be able to restore the write
976 * access in the fast page fault path later on.
978 WARN_ONCE((spte & PT_WRITABLE_MASK) &&
979 !spte_can_locklessly_be_made_writable(spte),
980 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
982 WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
983 shadow_acc_track_saved_bits_shift),
984 "kvm: Access Tracking saved bit locations are not zero\n");
986 spte |= (spte & shadow_acc_track_saved_bits_mask) <<
987 shadow_acc_track_saved_bits_shift;
988 spte &= ~shadow_acc_track_mask;
993 /* Restore an acc-track PTE back to a regular PTE */
994 static u64 restore_acc_track_spte(u64 spte)
997 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
998 & shadow_acc_track_saved_bits_mask;
1000 WARN_ON_ONCE(spte_ad_enabled(spte));
1001 WARN_ON_ONCE(!is_access_track_spte(spte));
1003 new_spte &= ~shadow_acc_track_mask;
1004 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
1005 shadow_acc_track_saved_bits_shift);
1006 new_spte |= saved_bits;
1011 /* Returns the Accessed status of the PTE and resets it at the same time. */
1012 static bool mmu_spte_age(u64 *sptep)
1014 u64 spte = mmu_spte_get_lockless(sptep);
1016 if (!is_accessed_spte(spte))
1019 if (spte_ad_enabled(spte)) {
1020 clear_bit((ffs(shadow_accessed_mask) - 1),
1021 (unsigned long *)sptep);
1024 * Capture the dirty status of the page, so that it doesn't get
1025 * lost when the SPTE is marked for access tracking.
1027 if (is_writable_pte(spte))
1028 kvm_set_pfn_dirty(spte_to_pfn(spte));
1030 spte = mark_spte_for_access_track(spte);
1031 mmu_spte_update_no_track(sptep, spte);
1037 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
1040 * Prevent page table teardown by making any free-er wait during
1041 * kvm_flush_remote_tlbs() IPI to all active vcpus.
1043 local_irq_disable();
1046 * Make sure a following spte read is not reordered ahead of the write
1049 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
1052 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
1055 * Make sure the write to vcpu->mode is not reordered in front of
1056 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
1057 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
1059 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
1063 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
1064 struct kmem_cache *base_cache, int min)
1068 if (cache->nobjs >= min)
1070 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
1071 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL_ACCOUNT);
1073 return cache->nobjs >= min ? 0 : -ENOMEM;
1074 cache->objects[cache->nobjs++] = obj;
1079 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
1081 return cache->nobjs;
1084 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
1085 struct kmem_cache *cache)
1088 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
1091 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
1096 if (cache->nobjs >= min)
1098 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
1099 page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT);
1101 return cache->nobjs >= min ? 0 : -ENOMEM;
1102 cache->objects[cache->nobjs++] = page;
1107 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
1110 free_page((unsigned long)mc->objects[--mc->nobjs]);
1113 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
1117 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
1118 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
1121 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
1124 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
1125 mmu_page_header_cache, 4);
1130 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
1132 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
1133 pte_list_desc_cache);
1134 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
1135 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
1136 mmu_page_header_cache);
1139 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
1144 p = mc->objects[--mc->nobjs];
1148 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
1150 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
1153 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
1155 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
1158 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
1160 if (!sp->role.direct)
1161 return sp->gfns[index];
1163 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
1166 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
1168 if (!sp->role.direct) {
1169 sp->gfns[index] = gfn;
1173 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
1174 pr_err_ratelimited("gfn mismatch under direct page %llx "
1175 "(expected %llx, got %llx)\n",
1177 kvm_mmu_page_get_gfn(sp, index), gfn);
1181 * Return the pointer to the large page information for a given gfn,
1182 * handling slots that are not large page aligned.
1184 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
1185 struct kvm_memory_slot *slot,
1190 idx = gfn_to_index(gfn, slot->base_gfn, level);
1191 return &slot->arch.lpage_info[level - 2][idx];
1194 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
1195 gfn_t gfn, int count)
1197 struct kvm_lpage_info *linfo;
1200 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1201 linfo = lpage_info_slot(gfn, slot, i);
1202 linfo->disallow_lpage += count;
1203 WARN_ON(linfo->disallow_lpage < 0);
1207 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1209 update_gfn_disallow_lpage_count(slot, gfn, 1);
1212 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1214 update_gfn_disallow_lpage_count(slot, gfn, -1);
1217 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1219 struct kvm_memslots *slots;
1220 struct kvm_memory_slot *slot;
1223 kvm->arch.indirect_shadow_pages++;
1225 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1226 slot = __gfn_to_memslot(slots, gfn);
1228 /* the non-leaf shadow pages are keeping readonly. */
1229 if (sp->role.level > PG_LEVEL_4K)
1230 return kvm_slot_page_track_add_page(kvm, slot, gfn,
1231 KVM_PAGE_TRACK_WRITE);
1233 kvm_mmu_gfn_disallow_lpage(slot, gfn);
1236 static void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1238 if (sp->lpage_disallowed)
1241 ++kvm->stat.nx_lpage_splits;
1242 list_add_tail(&sp->lpage_disallowed_link,
1243 &kvm->arch.lpage_disallowed_mmu_pages);
1244 sp->lpage_disallowed = true;
1247 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1249 struct kvm_memslots *slots;
1250 struct kvm_memory_slot *slot;
1253 kvm->arch.indirect_shadow_pages--;
1255 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1256 slot = __gfn_to_memslot(slots, gfn);
1257 if (sp->role.level > PG_LEVEL_4K)
1258 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
1259 KVM_PAGE_TRACK_WRITE);
1261 kvm_mmu_gfn_allow_lpage(slot, gfn);
1264 static void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1266 --kvm->stat.nx_lpage_splits;
1267 sp->lpage_disallowed = false;
1268 list_del(&sp->lpage_disallowed_link);
1271 static struct kvm_memory_slot *
1272 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
1275 struct kvm_memory_slot *slot;
1277 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1278 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
1280 if (no_dirty_log && slot->dirty_bitmap)
1287 * About rmap_head encoding:
1289 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1290 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1291 * pte_list_desc containing more mappings.
1295 * Returns the number of pointers in the rmap chain, not counting the new one.
1297 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
1298 struct kvm_rmap_head *rmap_head)
1300 struct pte_list_desc *desc;
1303 if (!rmap_head->val) {
1304 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
1305 rmap_head->val = (unsigned long)spte;
1306 } else if (!(rmap_head->val & 1)) {
1307 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
1308 desc = mmu_alloc_pte_list_desc(vcpu);
1309 desc->sptes[0] = (u64 *)rmap_head->val;
1310 desc->sptes[1] = spte;
1311 rmap_head->val = (unsigned long)desc | 1;
1314 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
1315 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1316 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
1318 count += PTE_LIST_EXT;
1320 if (desc->sptes[PTE_LIST_EXT-1]) {
1321 desc->more = mmu_alloc_pte_list_desc(vcpu);
1324 for (i = 0; desc->sptes[i]; ++i)
1326 desc->sptes[i] = spte;
1332 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
1333 struct pte_list_desc *desc, int i,
1334 struct pte_list_desc *prev_desc)
1338 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
1340 desc->sptes[i] = desc->sptes[j];
1341 desc->sptes[j] = NULL;
1344 if (!prev_desc && !desc->more)
1348 prev_desc->more = desc->more;
1350 rmap_head->val = (unsigned long)desc->more | 1;
1351 mmu_free_pte_list_desc(desc);
1354 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1356 struct pte_list_desc *desc;
1357 struct pte_list_desc *prev_desc;
1360 if (!rmap_head->val) {
1361 pr_err("%s: %p 0->BUG\n", __func__, spte);
1363 } else if (!(rmap_head->val & 1)) {
1364 rmap_printk("%s: %p 1->0\n", __func__, spte);
1365 if ((u64 *)rmap_head->val != spte) {
1366 pr_err("%s: %p 1->BUG\n", __func__, spte);
1371 rmap_printk("%s: %p many->many\n", __func__, spte);
1372 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1375 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1376 if (desc->sptes[i] == spte) {
1377 pte_list_desc_remove_entry(rmap_head,
1378 desc, i, prev_desc);
1385 pr_err("%s: %p many->many\n", __func__, spte);
1390 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
1392 mmu_spte_clear_track_bits(sptep);
1393 __pte_list_remove(sptep, rmap_head);
1396 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1397 struct kvm_memory_slot *slot)
1401 idx = gfn_to_index(gfn, slot->base_gfn, level);
1402 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
1405 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1406 struct kvm_mmu_page *sp)
1408 struct kvm_memslots *slots;
1409 struct kvm_memory_slot *slot;
1411 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1412 slot = __gfn_to_memslot(slots, gfn);
1413 return __gfn_to_rmap(gfn, sp->role.level, slot);
1416 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1418 struct kvm_mmu_memory_cache *cache;
1420 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1421 return mmu_memory_cache_free_objects(cache);
1424 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1426 struct kvm_mmu_page *sp;
1427 struct kvm_rmap_head *rmap_head;
1429 sp = page_header(__pa(spte));
1430 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1431 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1432 return pte_list_add(vcpu, spte, rmap_head);
1435 static void rmap_remove(struct kvm *kvm, u64 *spte)
1437 struct kvm_mmu_page *sp;
1439 struct kvm_rmap_head *rmap_head;
1441 sp = page_header(__pa(spte));
1442 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1443 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1444 __pte_list_remove(spte, rmap_head);
1448 * Used by the following functions to iterate through the sptes linked by a
1449 * rmap. All fields are private and not assumed to be used outside.
1451 struct rmap_iterator {
1452 /* private fields */
1453 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1454 int pos; /* index of the sptep */
1458 * Iteration must be started by this function. This should also be used after
1459 * removing/dropping sptes from the rmap link because in such cases the
1460 * information in the iterator may not be valid.
1462 * Returns sptep if found, NULL otherwise.
1464 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1465 struct rmap_iterator *iter)
1469 if (!rmap_head->val)
1472 if (!(rmap_head->val & 1)) {
1474 sptep = (u64 *)rmap_head->val;
1478 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1480 sptep = iter->desc->sptes[iter->pos];
1482 BUG_ON(!is_shadow_present_pte(*sptep));
1487 * Must be used with a valid iterator: e.g. after rmap_get_first().
1489 * Returns sptep if found, NULL otherwise.
1491 static u64 *rmap_get_next(struct rmap_iterator *iter)
1496 if (iter->pos < PTE_LIST_EXT - 1) {
1498 sptep = iter->desc->sptes[iter->pos];
1503 iter->desc = iter->desc->more;
1507 /* desc->sptes[0] cannot be NULL */
1508 sptep = iter->desc->sptes[iter->pos];
1515 BUG_ON(!is_shadow_present_pte(*sptep));
1519 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1520 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1521 _spte_; _spte_ = rmap_get_next(_iter_))
1523 static void drop_spte(struct kvm *kvm, u64 *sptep)
1525 if (mmu_spte_clear_track_bits(sptep))
1526 rmap_remove(kvm, sptep);
1530 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1532 if (is_large_pte(*sptep)) {
1533 WARN_ON(page_header(__pa(sptep))->role.level == PG_LEVEL_4K);
1534 drop_spte(kvm, sptep);
1542 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1544 if (__drop_large_spte(vcpu->kvm, sptep)) {
1545 struct kvm_mmu_page *sp = page_header(__pa(sptep));
1547 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1548 KVM_PAGES_PER_HPAGE(sp->role.level));
1553 * Write-protect on the specified @sptep, @pt_protect indicates whether
1554 * spte write-protection is caused by protecting shadow page table.
1556 * Note: write protection is difference between dirty logging and spte
1558 * - for dirty logging, the spte can be set to writable at anytime if
1559 * its dirty bitmap is properly set.
1560 * - for spte protection, the spte can be writable only after unsync-ing
1563 * Return true if tlb need be flushed.
1565 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1569 if (!is_writable_pte(spte) &&
1570 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1573 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1576 spte &= ~SPTE_MMU_WRITEABLE;
1577 spte = spte & ~PT_WRITABLE_MASK;
1579 return mmu_spte_update(sptep, spte);
1582 static bool __rmap_write_protect(struct kvm *kvm,
1583 struct kvm_rmap_head *rmap_head,
1587 struct rmap_iterator iter;
1590 for_each_rmap_spte(rmap_head, &iter, sptep)
1591 flush |= spte_write_protect(sptep, pt_protect);
1596 static bool spte_clear_dirty(u64 *sptep)
1600 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1602 MMU_WARN_ON(!spte_ad_enabled(spte));
1603 spte &= ~shadow_dirty_mask;
1604 return mmu_spte_update(sptep, spte);
1607 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1609 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1610 (unsigned long *)sptep);
1611 if (was_writable && !spte_ad_enabled(*sptep))
1612 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1614 return was_writable;
1618 * Gets the GFN ready for another round of dirty logging by clearing the
1619 * - D bit on ad-enabled SPTEs, and
1620 * - W bit on ad-disabled SPTEs.
1621 * Returns true iff any D or W bits were cleared.
1623 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1626 struct rmap_iterator iter;
1629 for_each_rmap_spte(rmap_head, &iter, sptep)
1630 if (spte_ad_need_write_protect(*sptep))
1631 flush |= spte_wrprot_for_clear_dirty(sptep);
1633 flush |= spte_clear_dirty(sptep);
1638 static bool spte_set_dirty(u64 *sptep)
1642 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1645 * Similar to the !kvm_x86_ops.slot_disable_log_dirty case,
1646 * do not bother adding back write access to pages marked
1647 * SPTE_AD_WRPROT_ONLY_MASK.
1649 spte |= shadow_dirty_mask;
1651 return mmu_spte_update(sptep, spte);
1654 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1657 struct rmap_iterator iter;
1660 for_each_rmap_spte(rmap_head, &iter, sptep)
1661 if (spte_ad_enabled(*sptep))
1662 flush |= spte_set_dirty(sptep);
1668 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1669 * @kvm: kvm instance
1670 * @slot: slot to protect
1671 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1672 * @mask: indicates which pages we should protect
1674 * Used when we do not need to care about huge page mappings: e.g. during dirty
1675 * logging we do not have any such mappings.
1677 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1678 struct kvm_memory_slot *slot,
1679 gfn_t gfn_offset, unsigned long mask)
1681 struct kvm_rmap_head *rmap_head;
1684 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1686 __rmap_write_protect(kvm, rmap_head, false);
1688 /* clear the first set bit */
1694 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1695 * protect the page if the D-bit isn't supported.
1696 * @kvm: kvm instance
1697 * @slot: slot to clear D-bit
1698 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1699 * @mask: indicates which pages we should clear D-bit
1701 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1703 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1704 struct kvm_memory_slot *slot,
1705 gfn_t gfn_offset, unsigned long mask)
1707 struct kvm_rmap_head *rmap_head;
1710 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1712 __rmap_clear_dirty(kvm, rmap_head);
1714 /* clear the first set bit */
1718 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1721 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1724 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1725 * enable dirty logging for them.
1727 * Used when we do not need to care about huge page mappings: e.g. during dirty
1728 * logging we do not have any such mappings.
1730 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1731 struct kvm_memory_slot *slot,
1732 gfn_t gfn_offset, unsigned long mask)
1734 if (kvm_x86_ops.enable_log_dirty_pt_masked)
1735 kvm_x86_ops.enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1738 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1741 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1742 struct kvm_memory_slot *slot, u64 gfn)
1744 struct kvm_rmap_head *rmap_head;
1746 bool write_protected = false;
1748 for (i = PG_LEVEL_4K; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1749 rmap_head = __gfn_to_rmap(gfn, i, slot);
1750 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1753 return write_protected;
1756 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1758 struct kvm_memory_slot *slot;
1760 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1761 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1764 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1767 struct rmap_iterator iter;
1770 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1771 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1773 pte_list_remove(rmap_head, sptep);
1780 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1781 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1784 return kvm_zap_rmapp(kvm, rmap_head);
1787 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1788 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1792 struct rmap_iterator iter;
1795 pte_t *ptep = (pte_t *)data;
1798 WARN_ON(pte_huge(*ptep));
1799 new_pfn = pte_pfn(*ptep);
1802 for_each_rmap_spte(rmap_head, &iter, sptep) {
1803 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1804 sptep, *sptep, gfn, level);
1808 if (pte_write(*ptep)) {
1809 pte_list_remove(rmap_head, sptep);
1812 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1813 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1815 new_spte &= ~PT_WRITABLE_MASK;
1816 new_spte &= ~SPTE_HOST_WRITEABLE;
1818 new_spte = mark_spte_for_access_track(new_spte);
1820 mmu_spte_clear_track_bits(sptep);
1821 mmu_spte_set(sptep, new_spte);
1825 if (need_flush && kvm_available_flush_tlb_with_range()) {
1826 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1833 struct slot_rmap_walk_iterator {
1835 struct kvm_memory_slot *slot;
1841 /* output fields. */
1843 struct kvm_rmap_head *rmap;
1846 /* private field. */
1847 struct kvm_rmap_head *end_rmap;
1851 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1853 iterator->level = level;
1854 iterator->gfn = iterator->start_gfn;
1855 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1856 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1861 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1862 struct kvm_memory_slot *slot, int start_level,
1863 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1865 iterator->slot = slot;
1866 iterator->start_level = start_level;
1867 iterator->end_level = end_level;
1868 iterator->start_gfn = start_gfn;
1869 iterator->end_gfn = end_gfn;
1871 rmap_walk_init_level(iterator, iterator->start_level);
1874 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1876 return !!iterator->rmap;
1879 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1881 if (++iterator->rmap <= iterator->end_rmap) {
1882 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1886 if (++iterator->level > iterator->end_level) {
1887 iterator->rmap = NULL;
1891 rmap_walk_init_level(iterator, iterator->level);
1894 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1895 _start_gfn, _end_gfn, _iter_) \
1896 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1897 _end_level_, _start_gfn, _end_gfn); \
1898 slot_rmap_walk_okay(_iter_); \
1899 slot_rmap_walk_next(_iter_))
1901 static int kvm_handle_hva_range(struct kvm *kvm,
1902 unsigned long start,
1905 int (*handler)(struct kvm *kvm,
1906 struct kvm_rmap_head *rmap_head,
1907 struct kvm_memory_slot *slot,
1910 unsigned long data))
1912 struct kvm_memslots *slots;
1913 struct kvm_memory_slot *memslot;
1914 struct slot_rmap_walk_iterator iterator;
1918 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1919 slots = __kvm_memslots(kvm, i);
1920 kvm_for_each_memslot(memslot, slots) {
1921 unsigned long hva_start, hva_end;
1922 gfn_t gfn_start, gfn_end;
1924 hva_start = max(start, memslot->userspace_addr);
1925 hva_end = min(end, memslot->userspace_addr +
1926 (memslot->npages << PAGE_SHIFT));
1927 if (hva_start >= hva_end)
1930 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1931 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1933 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1934 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1936 for_each_slot_rmap_range(memslot, PG_LEVEL_4K,
1937 KVM_MAX_HUGEPAGE_LEVEL,
1938 gfn_start, gfn_end - 1,
1940 ret |= handler(kvm, iterator.rmap, memslot,
1941 iterator.gfn, iterator.level, data);
1948 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1950 int (*handler)(struct kvm *kvm,
1951 struct kvm_rmap_head *rmap_head,
1952 struct kvm_memory_slot *slot,
1953 gfn_t gfn, int level,
1954 unsigned long data))
1956 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1959 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1961 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1964 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1966 return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1969 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1970 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1974 struct rmap_iterator uninitialized_var(iter);
1977 for_each_rmap_spte(rmap_head, &iter, sptep)
1978 young |= mmu_spte_age(sptep);
1980 trace_kvm_age_page(gfn, level, slot, young);
1984 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1985 struct kvm_memory_slot *slot, gfn_t gfn,
1986 int level, unsigned long data)
1989 struct rmap_iterator iter;
1991 for_each_rmap_spte(rmap_head, &iter, sptep)
1992 if (is_accessed_spte(*sptep))
1997 #define RMAP_RECYCLE_THRESHOLD 1000
1999 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
2001 struct kvm_rmap_head *rmap_head;
2002 struct kvm_mmu_page *sp;
2004 sp = page_header(__pa(spte));
2006 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
2008 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
2009 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
2010 KVM_PAGES_PER_HPAGE(sp->role.level));
2013 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
2015 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
2018 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
2020 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
2024 static int is_empty_shadow_page(u64 *spt)
2029 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
2030 if (is_shadow_present_pte(*pos)) {
2031 printk(KERN_ERR "%s: %p %llx\n", __func__,
2040 * This value is the sum of all of the kvm instances's
2041 * kvm->arch.n_used_mmu_pages values. We need a global,
2042 * aggregate version in order to make the slab shrinker
2045 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
2047 kvm->arch.n_used_mmu_pages += nr;
2048 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
2051 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
2053 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
2054 hlist_del(&sp->hash_link);
2055 list_del(&sp->link);
2056 free_page((unsigned long)sp->spt);
2057 if (!sp->role.direct)
2058 free_page((unsigned long)sp->gfns);
2059 kmem_cache_free(mmu_page_header_cache, sp);
2062 static unsigned kvm_page_table_hashfn(gfn_t gfn)
2064 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
2067 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
2068 struct kvm_mmu_page *sp, u64 *parent_pte)
2073 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
2076 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
2079 __pte_list_remove(parent_pte, &sp->parent_ptes);
2082 static void drop_parent_pte(struct kvm_mmu_page *sp,
2085 mmu_page_remove_parent_pte(sp, parent_pte);
2086 mmu_spte_clear_no_track(parent_pte);
2089 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
2091 struct kvm_mmu_page *sp;
2093 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
2094 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2096 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2097 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
2100 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
2101 * depends on valid pages being added to the head of the list. See
2102 * comments in kvm_zap_obsolete_pages().
2104 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2105 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
2106 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
2110 static void mark_unsync(u64 *spte);
2111 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
2114 struct rmap_iterator iter;
2116 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
2121 static void mark_unsync(u64 *spte)
2123 struct kvm_mmu_page *sp;
2126 sp = page_header(__pa(spte));
2127 index = spte - sp->spt;
2128 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
2130 if (sp->unsync_children++)
2132 kvm_mmu_mark_parents_unsync(sp);
2135 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
2136 struct kvm_mmu_page *sp)
2141 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
2142 struct kvm_mmu_page *sp, u64 *spte,
2148 #define KVM_PAGE_ARRAY_NR 16
2150 struct kvm_mmu_pages {
2151 struct mmu_page_and_offset {
2152 struct kvm_mmu_page *sp;
2154 } page[KVM_PAGE_ARRAY_NR];
2158 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
2164 for (i=0; i < pvec->nr; i++)
2165 if (pvec->page[i].sp == sp)
2168 pvec->page[pvec->nr].sp = sp;
2169 pvec->page[pvec->nr].idx = idx;
2171 return (pvec->nr == KVM_PAGE_ARRAY_NR);
2174 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
2176 --sp->unsync_children;
2177 WARN_ON((int)sp->unsync_children < 0);
2178 __clear_bit(idx, sp->unsync_child_bitmap);
2181 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
2182 struct kvm_mmu_pages *pvec)
2184 int i, ret, nr_unsync_leaf = 0;
2186 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
2187 struct kvm_mmu_page *child;
2188 u64 ent = sp->spt[i];
2190 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
2191 clear_unsync_child_bit(sp, i);
2195 child = page_header(ent & PT64_BASE_ADDR_MASK);
2197 if (child->unsync_children) {
2198 if (mmu_pages_add(pvec, child, i))
2201 ret = __mmu_unsync_walk(child, pvec);
2203 clear_unsync_child_bit(sp, i);
2205 } else if (ret > 0) {
2206 nr_unsync_leaf += ret;
2209 } else if (child->unsync) {
2211 if (mmu_pages_add(pvec, child, i))
2214 clear_unsync_child_bit(sp, i);
2217 return nr_unsync_leaf;
2220 #define INVALID_INDEX (-1)
2222 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
2223 struct kvm_mmu_pages *pvec)
2226 if (!sp->unsync_children)
2229 mmu_pages_add(pvec, sp, INVALID_INDEX);
2230 return __mmu_unsync_walk(sp, pvec);
2233 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2235 WARN_ON(!sp->unsync);
2236 trace_kvm_mmu_sync_page(sp);
2238 --kvm->stat.mmu_unsync;
2241 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2242 struct list_head *invalid_list);
2243 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2244 struct list_head *invalid_list);
2246 #define for_each_valid_sp(_kvm, _sp, _list) \
2247 hlist_for_each_entry(_sp, _list, hash_link) \
2248 if (is_obsolete_sp((_kvm), (_sp))) { \
2251 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2252 for_each_valid_sp(_kvm, _sp, \
2253 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
2254 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2256 static inline bool is_ept_sp(struct kvm_mmu_page *sp)
2258 return sp->role.cr0_wp && sp->role.smap_andnot_wp;
2261 /* @sp->gfn should be write-protected at the call site */
2262 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2263 struct list_head *invalid_list)
2265 if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) ||
2266 vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
2267 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2274 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
2275 struct list_head *invalid_list,
2278 if (!remote_flush && list_empty(invalid_list))
2281 if (!list_empty(invalid_list))
2282 kvm_mmu_commit_zap_page(kvm, invalid_list);
2284 kvm_flush_remote_tlbs(kvm);
2288 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
2289 struct list_head *invalid_list,
2290 bool remote_flush, bool local_flush)
2292 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
2296 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2299 #ifdef CONFIG_KVM_MMU_AUDIT
2300 #include "mmu_audit.c"
2302 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
2303 static void mmu_audit_disable(void) { }
2306 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2308 return sp->role.invalid ||
2309 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2312 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2313 struct list_head *invalid_list)
2315 kvm_unlink_unsync_page(vcpu->kvm, sp);
2316 return __kvm_sync_page(vcpu, sp, invalid_list);
2319 /* @gfn should be write-protected at the call site */
2320 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
2321 struct list_head *invalid_list)
2323 struct kvm_mmu_page *s;
2326 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2330 WARN_ON(s->role.level != PG_LEVEL_4K);
2331 ret |= kvm_sync_page(vcpu, s, invalid_list);
2337 struct mmu_page_path {
2338 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
2339 unsigned int idx[PT64_ROOT_MAX_LEVEL];
2342 #define for_each_sp(pvec, sp, parents, i) \
2343 for (i = mmu_pages_first(&pvec, &parents); \
2344 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2345 i = mmu_pages_next(&pvec, &parents, i))
2347 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2348 struct mmu_page_path *parents,
2353 for (n = i+1; n < pvec->nr; n++) {
2354 struct kvm_mmu_page *sp = pvec->page[n].sp;
2355 unsigned idx = pvec->page[n].idx;
2356 int level = sp->role.level;
2358 parents->idx[level-1] = idx;
2359 if (level == PG_LEVEL_4K)
2362 parents->parent[level-2] = sp;
2368 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2369 struct mmu_page_path *parents)
2371 struct kvm_mmu_page *sp;
2377 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2379 sp = pvec->page[0].sp;
2380 level = sp->role.level;
2381 WARN_ON(level == PG_LEVEL_4K);
2383 parents->parent[level-2] = sp;
2385 /* Also set up a sentinel. Further entries in pvec are all
2386 * children of sp, so this element is never overwritten.
2388 parents->parent[level-1] = NULL;
2389 return mmu_pages_next(pvec, parents, 0);
2392 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2394 struct kvm_mmu_page *sp;
2395 unsigned int level = 0;
2398 unsigned int idx = parents->idx[level];
2399 sp = parents->parent[level];
2403 WARN_ON(idx == INVALID_INDEX);
2404 clear_unsync_child_bit(sp, idx);
2406 } while (!sp->unsync_children);
2409 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2410 struct kvm_mmu_page *parent)
2413 struct kvm_mmu_page *sp;
2414 struct mmu_page_path parents;
2415 struct kvm_mmu_pages pages;
2416 LIST_HEAD(invalid_list);
2419 while (mmu_unsync_walk(parent, &pages)) {
2420 bool protected = false;
2422 for_each_sp(pages, sp, parents, i)
2423 protected |= rmap_write_protect(vcpu, sp->gfn);
2426 kvm_flush_remote_tlbs(vcpu->kvm);
2430 for_each_sp(pages, sp, parents, i) {
2431 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2432 mmu_pages_clear_parents(&parents);
2434 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2435 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2436 cond_resched_lock(&vcpu->kvm->mmu_lock);
2441 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2444 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2446 atomic_set(&sp->write_flooding_count, 0);
2449 static void clear_sp_write_flooding_count(u64 *spte)
2451 struct kvm_mmu_page *sp = page_header(__pa(spte));
2453 __clear_sp_write_flooding_count(sp);
2456 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2461 unsigned int access)
2463 bool direct_mmu = vcpu->arch.mmu->direct_map;
2464 union kvm_mmu_page_role role;
2465 struct hlist_head *sp_list;
2467 struct kvm_mmu_page *sp;
2468 bool need_sync = false;
2471 LIST_HEAD(invalid_list);
2473 role = vcpu->arch.mmu->mmu_role.base;
2475 role.direct = direct;
2477 role.gpte_is_8_bytes = true;
2478 role.access = access;
2479 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2480 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2481 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2482 role.quadrant = quadrant;
2485 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2486 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2487 if (sp->gfn != gfn) {
2492 if (!need_sync && sp->unsync)
2495 if (sp->role.word != role.word)
2499 goto trace_get_page;
2502 /* The page is good, but __kvm_sync_page might still end
2503 * up zapping it. If so, break in order to rebuild it.
2505 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2508 WARN_ON(!list_empty(&invalid_list));
2509 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2512 if (sp->unsync_children)
2513 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2515 __clear_sp_write_flooding_count(sp);
2518 trace_kvm_mmu_get_page(sp, false);
2522 ++vcpu->kvm->stat.mmu_cache_miss;
2524 sp = kvm_mmu_alloc_page(vcpu, direct);
2528 hlist_add_head(&sp->hash_link, sp_list);
2531 * we should do write protection before syncing pages
2532 * otherwise the content of the synced shadow page may
2533 * be inconsistent with guest page table.
2535 account_shadowed(vcpu->kvm, sp);
2536 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2537 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2539 if (level > PG_LEVEL_4K && need_sync)
2540 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2542 clear_page(sp->spt);
2543 trace_kvm_mmu_get_page(sp, true);
2545 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2547 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2548 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2552 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2553 struct kvm_vcpu *vcpu, hpa_t root,
2556 iterator->addr = addr;
2557 iterator->shadow_addr = root;
2558 iterator->level = vcpu->arch.mmu->shadow_root_level;
2560 if (iterator->level == PT64_ROOT_4LEVEL &&
2561 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2562 !vcpu->arch.mmu->direct_map)
2565 if (iterator->level == PT32E_ROOT_LEVEL) {
2567 * prev_root is currently only used for 64-bit hosts. So only
2568 * the active root_hpa is valid here.
2570 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2572 iterator->shadow_addr
2573 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2574 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2576 if (!iterator->shadow_addr)
2577 iterator->level = 0;
2581 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2582 struct kvm_vcpu *vcpu, u64 addr)
2584 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2588 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2590 if (iterator->level < PG_LEVEL_4K)
2593 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2594 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2598 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2601 if (is_last_spte(spte, iterator->level)) {
2602 iterator->level = 0;
2606 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2610 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2612 __shadow_walk_next(iterator, *iterator->sptep);
2615 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2616 struct kvm_mmu_page *sp)
2620 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2622 spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2623 shadow_user_mask | shadow_x_mask | shadow_me_mask;
2625 if (sp_ad_disabled(sp))
2626 spte |= SPTE_AD_DISABLED_MASK;
2628 spte |= shadow_accessed_mask;
2630 mmu_spte_set(sptep, spte);
2632 mmu_page_add_parent_pte(vcpu, sp, sptep);
2634 if (sp->unsync_children || sp->unsync)
2638 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2639 unsigned direct_access)
2641 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2642 struct kvm_mmu_page *child;
2645 * For the direct sp, if the guest pte's dirty bit
2646 * changed form clean to dirty, it will corrupt the
2647 * sp's access: allow writable in the read-only sp,
2648 * so we should update the spte at this point to get
2649 * a new sp with the correct access.
2651 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2652 if (child->role.access == direct_access)
2655 drop_parent_pte(child, sptep);
2656 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2660 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2664 struct kvm_mmu_page *child;
2667 if (is_shadow_present_pte(pte)) {
2668 if (is_last_spte(pte, sp->role.level)) {
2669 drop_spte(kvm, spte);
2670 if (is_large_pte(pte))
2673 child = page_header(pte & PT64_BASE_ADDR_MASK);
2674 drop_parent_pte(child, spte);
2679 if (is_mmio_spte(pte))
2680 mmu_spte_clear_no_track(spte);
2685 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2686 struct kvm_mmu_page *sp)
2690 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2691 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2694 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2697 struct rmap_iterator iter;
2699 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2700 drop_parent_pte(sp, sptep);
2703 static int mmu_zap_unsync_children(struct kvm *kvm,
2704 struct kvm_mmu_page *parent,
2705 struct list_head *invalid_list)
2708 struct mmu_page_path parents;
2709 struct kvm_mmu_pages pages;
2711 if (parent->role.level == PG_LEVEL_4K)
2714 while (mmu_unsync_walk(parent, &pages)) {
2715 struct kvm_mmu_page *sp;
2717 for_each_sp(pages, sp, parents, i) {
2718 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2719 mmu_pages_clear_parents(&parents);
2727 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2728 struct kvm_mmu_page *sp,
2729 struct list_head *invalid_list,
2734 trace_kvm_mmu_prepare_zap_page(sp);
2735 ++kvm->stat.mmu_shadow_zapped;
2736 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2737 kvm_mmu_page_unlink_children(kvm, sp);
2738 kvm_mmu_unlink_parents(kvm, sp);
2740 /* Zapping children means active_mmu_pages has become unstable. */
2741 list_unstable = *nr_zapped;
2743 if (!sp->role.invalid && !sp->role.direct)
2744 unaccount_shadowed(kvm, sp);
2747 kvm_unlink_unsync_page(kvm, sp);
2748 if (!sp->root_count) {
2753 * Already invalid pages (previously active roots) are not on
2754 * the active page list. See list_del() in the "else" case of
2757 if (sp->role.invalid)
2758 list_add(&sp->link, invalid_list);
2760 list_move(&sp->link, invalid_list);
2761 kvm_mod_used_mmu_pages(kvm, -1);
2764 * Remove the active root from the active page list, the root
2765 * will be explicitly freed when the root_count hits zero.
2767 list_del(&sp->link);
2770 * Obsolete pages cannot be used on any vCPUs, see the comment
2771 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2772 * treats invalid shadow pages as being obsolete.
2774 if (!is_obsolete_sp(kvm, sp))
2775 kvm_reload_remote_mmus(kvm);
2778 if (sp->lpage_disallowed)
2779 unaccount_huge_nx_page(kvm, sp);
2781 sp->role.invalid = 1;
2782 return list_unstable;
2785 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2786 struct list_head *invalid_list)
2790 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2794 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2795 struct list_head *invalid_list)
2797 struct kvm_mmu_page *sp, *nsp;
2799 if (list_empty(invalid_list))
2803 * We need to make sure everyone sees our modifications to
2804 * the page tables and see changes to vcpu->mode here. The barrier
2805 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2806 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2808 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2809 * guest mode and/or lockless shadow page table walks.
2811 kvm_flush_remote_tlbs(kvm);
2813 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2814 WARN_ON(!sp->role.invalid || sp->root_count);
2815 kvm_mmu_free_page(sp);
2819 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2820 unsigned long nr_to_zap)
2822 unsigned long total_zapped = 0;
2823 struct kvm_mmu_page *sp, *tmp;
2824 LIST_HEAD(invalid_list);
2828 if (list_empty(&kvm->arch.active_mmu_pages))
2832 list_for_each_entry_safe(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2834 * Don't zap active root pages, the page itself can't be freed
2835 * and zapping it will just force vCPUs to realloc and reload.
2840 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2842 total_zapped += nr_zapped;
2843 if (total_zapped >= nr_to_zap)
2850 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2852 kvm->stat.mmu_recycled += total_zapped;
2853 return total_zapped;
2856 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2858 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2860 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2863 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2865 if (!kvm_mmu_available_pages(vcpu->kvm))
2871 * Changing the number of mmu pages allocated to the vm
2872 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2874 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2876 spin_lock(&kvm->mmu_lock);
2878 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2879 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2882 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2885 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2887 spin_unlock(&kvm->mmu_lock);
2890 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2892 struct kvm_mmu_page *sp;
2893 LIST_HEAD(invalid_list);
2896 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2898 spin_lock(&kvm->mmu_lock);
2899 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2900 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2903 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2905 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2906 spin_unlock(&kvm->mmu_lock);
2910 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2912 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2914 trace_kvm_mmu_unsync_page(sp);
2915 ++vcpu->kvm->stat.mmu_unsync;
2918 kvm_mmu_mark_parents_unsync(sp);
2921 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2924 struct kvm_mmu_page *sp;
2926 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2929 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2936 WARN_ON(sp->role.level != PG_LEVEL_4K);
2937 kvm_unsync_page(vcpu, sp);
2941 * We need to ensure that the marking of unsync pages is visible
2942 * before the SPTE is updated to allow writes because
2943 * kvm_mmu_sync_roots() checks the unsync flags without holding
2944 * the MMU lock and so can race with this. If the SPTE was updated
2945 * before the page had been marked as unsync-ed, something like the
2946 * following could happen:
2949 * ---------------------------------------------------------------------
2950 * 1.2 Host updates SPTE
2952 * 2.1 Guest writes a GPTE for GVA X.
2953 * (GPTE being in the guest page table shadowed
2954 * by the SP from CPU 1.)
2955 * This reads SPTE during the page table walk.
2956 * Since SPTE.W is read as 1, there is no
2959 * 2.2 Guest issues TLB flush.
2960 * That causes a VM Exit.
2962 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2963 * Since it is false, so it just returns.
2965 * 2.4 Guest accesses GVA X.
2966 * Since the mapping in the SP was not updated,
2967 * so the old mapping for GVA X incorrectly
2971 * (sp->unsync = true)
2973 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2974 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2975 * pairs with this write barrier.
2982 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2985 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) &&
2987 * Some reserved pages, such as those from NVDIMM
2988 * DAX devices, are not for MMIO, and can be mapped
2989 * with cached memory type for better performance.
2990 * However, the above check misconceives those pages
2991 * as MMIO, and results in KVM mapping them with UC
2992 * memory type, which would hurt the performance.
2993 * Therefore, we check the host memory type in addition
2994 * and only treat UC/UC-/WC pages as MMIO.
2996 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn));
2998 return !e820__mapped_raw_any(pfn_to_hpa(pfn),
2999 pfn_to_hpa(pfn + 1) - 1,
3003 /* Bits which may be returned by set_spte() */
3004 #define SET_SPTE_WRITE_PROTECTED_PT BIT(0)
3005 #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1)
3007 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
3008 unsigned int pte_access, int level,
3009 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
3010 bool can_unsync, bool host_writable)
3014 struct kvm_mmu_page *sp;
3016 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
3019 sp = page_header(__pa(sptep));
3020 if (sp_ad_disabled(sp))
3021 spte |= SPTE_AD_DISABLED_MASK;
3022 else if (kvm_vcpu_ad_need_write_protect(vcpu))
3023 spte |= SPTE_AD_WRPROT_ONLY_MASK;
3026 * For the EPT case, shadow_present_mask is 0 if hardware
3027 * supports exec-only page table entries. In that case,
3028 * ACC_USER_MASK and shadow_user_mask are used to represent
3029 * read access. See FNAME(gpte_access) in paging_tmpl.h.
3031 spte |= shadow_present_mask;
3033 spte |= spte_shadow_accessed_mask(spte);
3035 if (level > PG_LEVEL_4K && (pte_access & ACC_EXEC_MASK) &&
3036 is_nx_huge_page_enabled()) {
3037 pte_access &= ~ACC_EXEC_MASK;
3040 if (pte_access & ACC_EXEC_MASK)
3041 spte |= shadow_x_mask;
3043 spte |= shadow_nx_mask;
3045 if (pte_access & ACC_USER_MASK)
3046 spte |= shadow_user_mask;
3048 if (level > PG_LEVEL_4K)
3049 spte |= PT_PAGE_SIZE_MASK;
3051 spte |= kvm_x86_ops.get_mt_mask(vcpu, gfn,
3052 kvm_is_mmio_pfn(pfn));
3055 spte |= SPTE_HOST_WRITEABLE;
3057 pte_access &= ~ACC_WRITE_MASK;
3059 if (!kvm_is_mmio_pfn(pfn))
3060 spte |= shadow_me_mask;
3062 spte |= (u64)pfn << PAGE_SHIFT;
3064 if (pte_access & ACC_WRITE_MASK) {
3065 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
3068 * Optimization: for pte sync, if spte was writable the hash
3069 * lookup is unnecessary (and expensive). Write protection
3070 * is responsibility of mmu_get_page / kvm_sync_page.
3071 * Same reasoning can be applied to dirty page accounting.
3073 if (!can_unsync && is_writable_pte(*sptep))
3076 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
3077 pgprintk("%s: found shadow page for %llx, marking ro\n",
3079 ret |= SET_SPTE_WRITE_PROTECTED_PT;
3080 pte_access &= ~ACC_WRITE_MASK;
3081 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
3085 if (pte_access & ACC_WRITE_MASK) {
3086 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3087 spte |= spte_shadow_dirty_mask(spte);
3091 spte = mark_spte_for_access_track(spte);
3094 if (mmu_spte_update(sptep, spte))
3095 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
3099 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
3100 unsigned int pte_access, int write_fault, int level,
3101 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
3104 int was_rmapped = 0;
3107 int ret = RET_PF_RETRY;
3110 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
3111 *sptep, write_fault, gfn);
3113 if (is_shadow_present_pte(*sptep)) {
3115 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
3116 * the parent of the now unreachable PTE.
3118 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
3119 struct kvm_mmu_page *child;
3122 child = page_header(pte & PT64_BASE_ADDR_MASK);
3123 drop_parent_pte(child, sptep);
3125 } else if (pfn != spte_to_pfn(*sptep)) {
3126 pgprintk("hfn old %llx new %llx\n",
3127 spte_to_pfn(*sptep), pfn);
3128 drop_spte(vcpu->kvm, sptep);
3134 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
3135 speculative, true, host_writable);
3136 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
3138 ret = RET_PF_EMULATE;
3139 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3142 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
3143 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
3144 KVM_PAGES_PER_HPAGE(level));
3146 if (unlikely(is_mmio_spte(*sptep)))
3147 ret = RET_PF_EMULATE;
3149 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
3150 trace_kvm_mmu_set_spte(level, gfn, sptep);
3151 if (!was_rmapped && is_large_pte(*sptep))
3152 ++vcpu->kvm->stat.lpages;
3154 if (is_shadow_present_pte(*sptep)) {
3156 rmap_count = rmap_add(vcpu, sptep, gfn);
3157 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
3158 rmap_recycle(vcpu, sptep, gfn);
3165 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
3168 struct kvm_memory_slot *slot;
3170 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
3172 return KVM_PFN_ERR_FAULT;
3174 return gfn_to_pfn_memslot_atomic(slot, gfn);
3177 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
3178 struct kvm_mmu_page *sp,
3179 u64 *start, u64 *end)
3181 struct page *pages[PTE_PREFETCH_NUM];
3182 struct kvm_memory_slot *slot;
3183 unsigned int access = sp->role.access;
3187 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
3188 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
3192 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
3196 for (i = 0; i < ret; i++, gfn++, start++) {
3197 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
3198 page_to_pfn(pages[i]), true, true);
3205 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
3206 struct kvm_mmu_page *sp, u64 *sptep)
3208 u64 *spte, *start = NULL;
3211 WARN_ON(!sp->role.direct);
3213 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
3216 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
3217 if (is_shadow_present_pte(*spte) || spte == sptep) {
3220 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
3228 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
3230 struct kvm_mmu_page *sp;
3232 sp = page_header(__pa(sptep));
3235 * Without accessed bits, there's no way to distinguish between
3236 * actually accessed translations and prefetched, so disable pte
3237 * prefetch if accessed bits aren't available.
3239 if (sp_ad_disabled(sp))
3242 if (sp->role.level > PG_LEVEL_4K)
3245 __direct_pte_prefetch(vcpu, sp, sptep);
3248 static int host_pfn_mapping_level(struct kvm_vcpu *vcpu, gfn_t gfn,
3249 kvm_pfn_t pfn, struct kvm_memory_slot *slot)
3255 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
3259 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
3260 * is not solely for performance, it's also necessary to avoid the
3261 * "writable" check in __gfn_to_hva_many(), which will always fail on
3262 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
3263 * page fault steps have already verified the guest isn't writing a
3264 * read-only memslot.
3266 hva = __gfn_to_hva_memslot(slot, gfn);
3268 pte = lookup_address_in_mm(vcpu->kvm->mm, hva, &level);
3275 static int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
3276 int max_level, kvm_pfn_t *pfnp)
3278 struct kvm_memory_slot *slot;
3279 struct kvm_lpage_info *linfo;
3280 kvm_pfn_t pfn = *pfnp;
3284 if (unlikely(max_level == PG_LEVEL_4K))
3287 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
3290 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
3294 max_level = min(max_level, max_page_level);
3295 for ( ; max_level > PG_LEVEL_4K; max_level--) {
3296 linfo = lpage_info_slot(gfn, slot, max_level);
3297 if (!linfo->disallow_lpage)
3301 if (max_level == PG_LEVEL_4K)
3304 level = host_pfn_mapping_level(vcpu, gfn, pfn, slot);
3305 if (level == PG_LEVEL_4K)
3308 level = min(level, max_level);
3311 * mmu_notifier_retry() was successful and mmu_lock is held, so
3312 * the pmd can't be split from under us.
3314 mask = KVM_PAGES_PER_HPAGE(level) - 1;
3315 VM_BUG_ON((gfn & mask) != (pfn & mask));
3316 *pfnp = pfn & ~mask;
3321 static void disallowed_hugepage_adjust(struct kvm_shadow_walk_iterator it,
3322 gfn_t gfn, kvm_pfn_t *pfnp, int *levelp)
3324 int level = *levelp;
3325 u64 spte = *it.sptep;
3327 if (it.level == level && level > PG_LEVEL_4K &&
3328 is_nx_huge_page_enabled() &&
3329 is_shadow_present_pte(spte) &&
3330 !is_large_pte(spte)) {
3332 * A small SPTE exists for this pfn, but FNAME(fetch)
3333 * and __direct_map would like to create a large PTE
3334 * instead: just force them to go down another level,
3335 * patching back for them into pfn the next 9 bits of
3338 u64 page_mask = KVM_PAGES_PER_HPAGE(level) - KVM_PAGES_PER_HPAGE(level - 1);
3339 *pfnp |= gfn & page_mask;
3344 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, int write,
3345 int map_writable, int max_level, kvm_pfn_t pfn,
3346 bool prefault, bool account_disallowed_nx_lpage)
3348 struct kvm_shadow_walk_iterator it;
3349 struct kvm_mmu_page *sp;
3351 gfn_t gfn = gpa >> PAGE_SHIFT;
3352 gfn_t base_gfn = gfn;
3354 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
3355 return RET_PF_RETRY;
3357 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn);
3359 trace_kvm_mmu_spte_requested(gpa, level, pfn);
3360 for_each_shadow_entry(vcpu, gpa, it) {
3362 * We cannot overwrite existing page tables with an NX
3363 * large page, as the leaf could be executable.
3365 disallowed_hugepage_adjust(it, gfn, &pfn, &level);
3367 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
3368 if (it.level == level)
3371 drop_large_spte(vcpu, it.sptep);
3372 if (!is_shadow_present_pte(*it.sptep)) {
3373 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
3374 it.level - 1, true, ACC_ALL);
3376 link_shadow_page(vcpu, it.sptep, sp);
3377 if (account_disallowed_nx_lpage)
3378 account_huge_nx_page(vcpu->kvm, sp);
3382 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
3383 write, level, base_gfn, pfn, prefault,
3385 direct_pte_prefetch(vcpu, it.sptep);
3386 ++vcpu->stat.pf_fixed;
3390 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
3392 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
3395 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
3398 * Do not cache the mmio info caused by writing the readonly gfn
3399 * into the spte otherwise read access on readonly gfn also can
3400 * caused mmio page fault and treat it as mmio access.
3402 if (pfn == KVM_PFN_ERR_RO_FAULT)
3403 return RET_PF_EMULATE;
3405 if (pfn == KVM_PFN_ERR_HWPOISON) {
3406 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3407 return RET_PF_RETRY;
3413 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
3414 kvm_pfn_t pfn, unsigned int access,
3417 /* The pfn is invalid, report the error! */
3418 if (unlikely(is_error_pfn(pfn))) {
3419 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
3423 if (unlikely(is_noslot_pfn(pfn)))
3424 vcpu_cache_mmio_info(vcpu, gva, gfn,
3425 access & shadow_mmio_access_mask);
3430 static bool page_fault_can_be_fast(u32 error_code)
3433 * Do not fix the mmio spte with invalid generation number which
3434 * need to be updated by slow page fault path.
3436 if (unlikely(error_code & PFERR_RSVD_MASK))
3439 /* See if the page fault is due to an NX violation */
3440 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3441 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3445 * #PF can be fast if:
3446 * 1. The shadow page table entry is not present, which could mean that
3447 * the fault is potentially caused by access tracking (if enabled).
3448 * 2. The shadow page table entry is present and the fault
3449 * is caused by write-protect, that means we just need change the W
3450 * bit of the spte which can be done out of mmu-lock.
3452 * However, if access tracking is disabled we know that a non-present
3453 * page must be a genuine page fault where we have to create a new SPTE.
3454 * So, if access tracking is disabled, we return true only for write
3455 * accesses to a present page.
3458 return shadow_acc_track_mask != 0 ||
3459 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3460 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3464 * Returns true if the SPTE was fixed successfully. Otherwise,
3465 * someone else modified the SPTE from its original value.
3468 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3469 u64 *sptep, u64 old_spte, u64 new_spte)
3473 WARN_ON(!sp->role.direct);
3476 * Theoretically we could also set dirty bit (and flush TLB) here in
3477 * order to eliminate unnecessary PML logging. See comments in
3478 * set_spte. But fast_page_fault is very unlikely to happen with PML
3479 * enabled, so we do not do this. This might result in the same GPA
3480 * to be logged in PML buffer again when the write really happens, and
3481 * eventually to be called by mark_page_dirty twice. But it's also no
3482 * harm. This also avoids the TLB flush needed after setting dirty bit
3483 * so non-PML cases won't be impacted.
3485 * Compare with set_spte where instead shadow_dirty_mask is set.
3487 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3490 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3492 * The gfn of direct spte is stable since it is
3493 * calculated by sp->gfn.
3495 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3496 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3502 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3504 if (fault_err_code & PFERR_FETCH_MASK)
3505 return is_executable_pte(spte);
3507 if (fault_err_code & PFERR_WRITE_MASK)
3508 return is_writable_pte(spte);
3510 /* Fault was on Read access */
3511 return spte & PT_PRESENT_MASK;
3516 * - true: let the vcpu to access on the same address again.
3517 * - false: let the real page fault path to fix it.
3519 static bool fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3522 struct kvm_shadow_walk_iterator iterator;
3523 struct kvm_mmu_page *sp;
3524 bool fault_handled = false;
3526 uint retry_count = 0;
3528 if (!page_fault_can_be_fast(error_code))
3531 walk_shadow_page_lockless_begin(vcpu);
3536 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3537 if (!is_shadow_present_pte(spte))
3540 sp = page_header(__pa(iterator.sptep));
3541 if (!is_last_spte(spte, sp->role.level))
3545 * Check whether the memory access that caused the fault would
3546 * still cause it if it were to be performed right now. If not,
3547 * then this is a spurious fault caused by TLB lazily flushed,
3548 * or some other CPU has already fixed the PTE after the
3549 * current CPU took the fault.
3551 * Need not check the access of upper level table entries since
3552 * they are always ACC_ALL.
3554 if (is_access_allowed(error_code, spte)) {
3555 fault_handled = true;
3561 if (is_access_track_spte(spte))
3562 new_spte = restore_acc_track_spte(new_spte);
3565 * Currently, to simplify the code, write-protection can
3566 * be removed in the fast path only if the SPTE was
3567 * write-protected for dirty-logging or access tracking.
3569 if ((error_code & PFERR_WRITE_MASK) &&
3570 spte_can_locklessly_be_made_writable(spte)) {
3571 new_spte |= PT_WRITABLE_MASK;
3574 * Do not fix write-permission on the large spte. Since
3575 * we only dirty the first page into the dirty-bitmap in
3576 * fast_pf_fix_direct_spte(), other pages are missed
3577 * if its slot has dirty logging enabled.
3579 * Instead, we let the slow page fault path create a
3580 * normal spte to fix the access.
3582 * See the comments in kvm_arch_commit_memory_region().
3584 if (sp->role.level > PG_LEVEL_4K)
3588 /* Verify that the fault can be handled in the fast path */
3589 if (new_spte == spte ||
3590 !is_access_allowed(error_code, new_spte))
3594 * Currently, fast page fault only works for direct mapping
3595 * since the gfn is not stable for indirect shadow page. See
3596 * Documentation/virt/kvm/locking.rst to get more detail.
3598 fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
3599 iterator.sptep, spte,
3604 if (++retry_count > 4) {
3605 printk_once(KERN_WARNING
3606 "kvm: Fast #PF retrying more than 4 times.\n");
3612 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3613 spte, fault_handled);
3614 walk_shadow_page_lockless_end(vcpu);
3616 return fault_handled;
3619 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3620 struct list_head *invalid_list)
3622 struct kvm_mmu_page *sp;
3624 if (!VALID_PAGE(*root_hpa))
3627 sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK);
3629 if (!sp->root_count && sp->role.invalid)
3630 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3632 *root_hpa = INVALID_PAGE;
3635 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3636 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3637 ulong roots_to_free)
3640 LIST_HEAD(invalid_list);
3641 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3643 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3645 /* Before acquiring the MMU lock, see if we need to do any real work. */
3646 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3647 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3648 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3649 VALID_PAGE(mmu->prev_roots[i].hpa))
3652 if (i == KVM_MMU_NUM_PREV_ROOTS)
3656 spin_lock(&vcpu->kvm->mmu_lock);
3658 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3659 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3660 mmu_free_root_page(vcpu->kvm, &mmu->prev_roots[i].hpa,
3663 if (free_active_root) {
3664 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3665 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3666 mmu_free_root_page(vcpu->kvm, &mmu->root_hpa,
3669 for (i = 0; i < 4; ++i)
3670 if (mmu->pae_root[i] != 0)
3671 mmu_free_root_page(vcpu->kvm,
3674 mmu->root_hpa = INVALID_PAGE;
3679 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3680 spin_unlock(&vcpu->kvm->mmu_lock);
3682 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3684 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3688 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3689 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3696 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3697 u8 level, bool direct)
3699 struct kvm_mmu_page *sp;
3701 spin_lock(&vcpu->kvm->mmu_lock);
3703 if (make_mmu_pages_available(vcpu)) {
3704 spin_unlock(&vcpu->kvm->mmu_lock);
3705 return INVALID_PAGE;
3707 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3710 spin_unlock(&vcpu->kvm->mmu_lock);
3711 return __pa(sp->spt);
3714 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3716 u8 shadow_root_level = vcpu->arch.mmu->shadow_root_level;
3720 if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3721 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true);
3722 if (!VALID_PAGE(root))
3724 vcpu->arch.mmu->root_hpa = root;
3725 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3726 for (i = 0; i < 4; ++i) {
3727 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
3729 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3730 i << 30, PT32_ROOT_LEVEL, true);
3731 if (!VALID_PAGE(root))
3733 vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK;
3735 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3739 /* root_pgd is ignored for direct MMUs. */
3740 vcpu->arch.mmu->root_pgd = 0;
3745 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3748 gfn_t root_gfn, root_pgd;
3752 root_pgd = vcpu->arch.mmu->get_guest_pgd(vcpu);
3753 root_gfn = root_pgd >> PAGE_SHIFT;
3755 if (mmu_check_root(vcpu, root_gfn))
3759 * Do we shadow a long mode page table? If so we need to
3760 * write-protect the guests page table root.
3762 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3763 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->root_hpa));
3765 root = mmu_alloc_root(vcpu, root_gfn, 0,
3766 vcpu->arch.mmu->shadow_root_level, false);
3767 if (!VALID_PAGE(root))
3769 vcpu->arch.mmu->root_hpa = root;
3774 * We shadow a 32 bit page table. This may be a legacy 2-level
3775 * or a PAE 3-level page table. In either case we need to be aware that
3776 * the shadow page table may be a PAE or a long mode page table.
3778 pm_mask = PT_PRESENT_MASK;
3779 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3780 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3782 for (i = 0; i < 4; ++i) {
3783 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
3784 if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) {
3785 pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i);
3786 if (!(pdptr & PT_PRESENT_MASK)) {
3787 vcpu->arch.mmu->pae_root[i] = 0;
3790 root_gfn = pdptr >> PAGE_SHIFT;
3791 if (mmu_check_root(vcpu, root_gfn))
3795 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3796 PT32_ROOT_LEVEL, false);
3797 if (!VALID_PAGE(root))
3799 vcpu->arch.mmu->pae_root[i] = root | pm_mask;
3801 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3804 * If we shadow a 32 bit page table with a long mode page
3805 * table we enter this path.
3807 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3808 if (vcpu->arch.mmu->lm_root == NULL) {
3810 * The additional page necessary for this is only
3811 * allocated on demand.
3816 lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3817 if (lm_root == NULL)
3820 lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask;
3822 vcpu->arch.mmu->lm_root = lm_root;
3825 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root);
3829 vcpu->arch.mmu->root_pgd = root_pgd;
3834 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3836 if (vcpu->arch.mmu->direct_map)
3837 return mmu_alloc_direct_roots(vcpu);
3839 return mmu_alloc_shadow_roots(vcpu);
3842 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3845 struct kvm_mmu_page *sp;
3847 if (vcpu->arch.mmu->direct_map)
3850 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3853 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3855 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3856 hpa_t root = vcpu->arch.mmu->root_hpa;
3857 sp = page_header(root);
3860 * Even if another CPU was marking the SP as unsync-ed
3861 * simultaneously, any guest page table changes are not
3862 * guaranteed to be visible anyway until this VCPU issues a TLB
3863 * flush strictly after those changes are made. We only need to
3864 * ensure that the other CPU sets these flags before any actual
3865 * changes to the page tables are made. The comments in
3866 * mmu_need_write_protect() describe what could go wrong if this
3867 * requirement isn't satisfied.
3869 if (!smp_load_acquire(&sp->unsync) &&
3870 !smp_load_acquire(&sp->unsync_children))
3873 spin_lock(&vcpu->kvm->mmu_lock);
3874 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3876 mmu_sync_children(vcpu, sp);
3878 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3879 spin_unlock(&vcpu->kvm->mmu_lock);
3883 spin_lock(&vcpu->kvm->mmu_lock);
3884 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3886 for (i = 0; i < 4; ++i) {
3887 hpa_t root = vcpu->arch.mmu->pae_root[i];
3889 if (root && VALID_PAGE(root)) {
3890 root &= PT64_BASE_ADDR_MASK;
3891 sp = page_header(root);
3892 mmu_sync_children(vcpu, sp);
3896 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3897 spin_unlock(&vcpu->kvm->mmu_lock);
3899 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3901 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3902 u32 access, struct x86_exception *exception)
3905 exception->error_code = 0;
3909 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3911 struct x86_exception *exception)
3914 exception->error_code = 0;
3915 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3919 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3921 int bit7 = (pte >> 7) & 1;
3923 return pte & rsvd_check->rsvd_bits_mask[bit7][level-1];
3926 static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte)
3928 return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
3931 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3934 * A nested guest cannot use the MMIO cache if it is using nested
3935 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3937 if (mmu_is_nested(vcpu))
3941 return vcpu_match_mmio_gpa(vcpu, addr);
3943 return vcpu_match_mmio_gva(vcpu, addr);
3946 /* return true if reserved bit is detected on spte. */
3948 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3950 struct kvm_shadow_walk_iterator iterator;
3951 u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull;
3952 struct rsvd_bits_validate *rsvd_check;
3954 bool reserved = false;
3956 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3958 walk_shadow_page_lockless_begin(vcpu);
3960 for (shadow_walk_init(&iterator, vcpu, addr),
3961 leaf = root = iterator.level;
3962 shadow_walk_okay(&iterator);
3963 __shadow_walk_next(&iterator, spte)) {
3964 spte = mmu_spte_get_lockless(iterator.sptep);
3966 sptes[leaf - 1] = spte;
3969 if (!is_shadow_present_pte(spte))
3973 * Use a bitwise-OR instead of a logical-OR to aggregate the
3974 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3975 * adding a Jcc in the loop.
3977 reserved |= __is_bad_mt_xwr(rsvd_check, spte) |
3978 __is_rsvd_bits_set(rsvd_check, spte, iterator.level);
3981 walk_shadow_page_lockless_end(vcpu);
3984 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3986 while (root > leaf) {
3987 pr_err("------ spte 0x%llx level %d.\n",
3988 sptes[root - 1], root);
3997 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
4002 if (mmio_info_in_cache(vcpu, addr, direct))
4003 return RET_PF_EMULATE;
4005 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
4006 if (WARN_ON(reserved))
4009 if (is_mmio_spte(spte)) {
4010 gfn_t gfn = get_mmio_spte_gfn(spte);
4011 unsigned int access = get_mmio_spte_access(spte);
4013 if (!check_mmio_spte(vcpu, spte))
4014 return RET_PF_INVALID;
4019 trace_handle_mmio_page_fault(addr, gfn, access);
4020 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
4021 return RET_PF_EMULATE;
4025 * If the page table is zapped by other cpus, let CPU fault again on
4028 return RET_PF_RETRY;
4031 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
4032 u32 error_code, gfn_t gfn)
4034 if (unlikely(error_code & PFERR_RSVD_MASK))
4037 if (!(error_code & PFERR_PRESENT_MASK) ||
4038 !(error_code & PFERR_WRITE_MASK))
4042 * guest is writing the page which is write tracked which can
4043 * not be fixed by page fault handler.
4045 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
4051 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
4053 struct kvm_shadow_walk_iterator iterator;
4056 walk_shadow_page_lockless_begin(vcpu);
4057 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4058 clear_sp_write_flooding_count(iterator.sptep);
4059 if (!is_shadow_present_pte(spte))
4062 walk_shadow_page_lockless_end(vcpu);
4065 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
4068 struct kvm_arch_async_pf arch;
4070 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
4072 arch.direct_map = vcpu->arch.mmu->direct_map;
4073 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
4075 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
4076 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
4079 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
4080 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, bool write,
4083 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
4086 /* Don't expose private memslots to L2. */
4087 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
4088 *pfn = KVM_PFN_NOSLOT;
4094 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
4096 return false; /* *pfn has correct page already */
4098 if (!prefault && kvm_can_do_async_pf(vcpu)) {
4099 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
4100 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
4101 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
4102 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
4104 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
4108 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
4112 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
4113 bool prefault, int max_level, bool is_tdp)
4115 bool write = error_code & PFERR_WRITE_MASK;
4116 bool exec = error_code & PFERR_FETCH_MASK;
4117 bool lpage_disallowed = exec && is_nx_huge_page_enabled();
4120 gfn_t gfn = gpa >> PAGE_SHIFT;
4121 unsigned long mmu_seq;
4125 if (page_fault_handle_page_track(vcpu, error_code, gfn))
4126 return RET_PF_EMULATE;
4128 r = mmu_topup_memory_caches(vcpu);
4132 if (lpage_disallowed)
4133 max_level = PG_LEVEL_4K;
4135 if (fast_page_fault(vcpu, gpa, error_code))
4136 return RET_PF_RETRY;
4138 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4141 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
4142 return RET_PF_RETRY;
4144 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
4148 spin_lock(&vcpu->kvm->mmu_lock);
4149 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
4151 if (make_mmu_pages_available(vcpu) < 0)
4153 r = __direct_map(vcpu, gpa, write, map_writable, max_level, pfn,
4154 prefault, is_tdp && lpage_disallowed);
4157 spin_unlock(&vcpu->kvm->mmu_lock);
4158 kvm_release_pfn_clean(pfn);
4162 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
4163 u32 error_code, bool prefault)
4165 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
4167 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
4168 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
4169 PG_LEVEL_2M, false);
4172 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
4173 u64 fault_address, char *insn, int insn_len)
4176 u32 flags = vcpu->arch.apf.host_apf_flags;
4178 #ifndef CONFIG_X86_64
4179 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
4180 if (WARN_ON_ONCE(fault_address >> 32))
4184 vcpu->arch.l1tf_flush_l1d = true;
4186 trace_kvm_page_fault(fault_address, error_code);
4188 if (kvm_event_needs_reinjection(vcpu))
4189 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
4190 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
4192 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
4193 vcpu->arch.apf.host_apf_flags = 0;
4194 local_irq_disable();
4195 kvm_async_pf_task_wait_schedule(fault_address);
4198 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
4203 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
4205 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
4210 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
4211 max_level > PG_LEVEL_4K;
4213 int page_num = KVM_PAGES_PER_HPAGE(max_level);
4214 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
4216 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
4220 return direct_page_fault(vcpu, gpa, error_code, prefault,
4224 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
4225 struct kvm_mmu *context)
4227 context->page_fault = nonpaging_page_fault;
4228 context->gva_to_gpa = nonpaging_gva_to_gpa;
4229 context->sync_page = nonpaging_sync_page;
4230 context->invlpg = NULL;
4231 context->update_pte = nonpaging_update_pte;
4232 context->root_level = 0;
4233 context->shadow_root_level = PT32E_ROOT_LEVEL;
4234 context->direct_map = true;
4235 context->nx = false;
4238 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
4239 union kvm_mmu_page_role role)
4241 return (role.direct || pgd == root->pgd) &&
4242 VALID_PAGE(root->hpa) && page_header(root->hpa) &&
4243 role.word == page_header(root->hpa)->role.word;
4247 * Find out if a previously cached root matching the new pgd/role is available.
4248 * The current root is also inserted into the cache.
4249 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4251 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4252 * false is returned. This root should now be freed by the caller.
4254 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4255 union kvm_mmu_page_role new_role)
4258 struct kvm_mmu_root_info root;
4259 struct kvm_mmu *mmu = vcpu->arch.mmu;
4261 root.pgd = mmu->root_pgd;
4262 root.hpa = mmu->root_hpa;
4264 if (is_root_usable(&root, new_pgd, new_role))
4267 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4268 swap(root, mmu->prev_roots[i]);
4270 if (is_root_usable(&root, new_pgd, new_role))
4274 mmu->root_hpa = root.hpa;
4275 mmu->root_pgd = root.pgd;
4277 return i < KVM_MMU_NUM_PREV_ROOTS;
4280 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4281 union kvm_mmu_page_role new_role)
4283 struct kvm_mmu *mmu = vcpu->arch.mmu;
4286 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4287 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4288 * later if necessary.
4290 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4291 mmu->root_level >= PT64_ROOT_4LEVEL)
4292 return !mmu_check_root(vcpu, new_pgd >> PAGE_SHIFT) &&
4293 cached_root_available(vcpu, new_pgd, new_role);
4298 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4299 union kvm_mmu_page_role new_role,
4300 bool skip_tlb_flush, bool skip_mmu_sync)
4302 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
4303 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
4308 * It's possible that the cached previous root page is obsolete because
4309 * of a change in the MMU generation number. However, changing the
4310 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
4311 * free the root set here and allocate a new one.
4313 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
4315 if (!skip_mmu_sync || force_flush_and_sync_on_reuse)
4316 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4317 if (!skip_tlb_flush || force_flush_and_sync_on_reuse)
4318 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
4321 * The last MMIO access's GVA and GPA are cached in the VCPU. When
4322 * switching to a new CR3, that GVA->GPA mapping may no longer be
4323 * valid. So clear any cached MMIO info even when we don't need to sync
4324 * the shadow page tables.
4326 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4328 __clear_sp_write_flooding_count(page_header(vcpu->arch.mmu->root_hpa));
4331 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush,
4334 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu),
4335 skip_tlb_flush, skip_mmu_sync);
4337 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
4339 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4341 return kvm_read_cr3(vcpu);
4344 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4345 unsigned int access, int *nr_present)
4347 if (unlikely(is_mmio_spte(*sptep))) {
4348 if (gfn != get_mmio_spte_gfn(*sptep)) {
4349 mmu_spte_clear_no_track(sptep);
4354 mark_mmio_spte(vcpu, sptep, gfn, access);
4361 static inline bool is_last_gpte(struct kvm_mmu *mmu,
4362 unsigned level, unsigned gpte)
4365 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4366 * If it is clear, there are no large pages at this level, so clear
4367 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4369 gpte &= level - mmu->last_nonleaf_level;
4372 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
4373 * iff level <= PG_LEVEL_4K, which for our purpose means
4374 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
4376 gpte |= level - PG_LEVEL_4K - 1;
4378 return gpte & PT_PAGE_SIZE_MASK;
4381 #define PTTYPE_EPT 18 /* arbitrary */
4382 #define PTTYPE PTTYPE_EPT
4383 #include "paging_tmpl.h"
4387 #include "paging_tmpl.h"
4391 #include "paging_tmpl.h"
4395 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4396 struct rsvd_bits_validate *rsvd_check,
4397 int maxphyaddr, int level, bool nx, bool gbpages,
4400 u64 exb_bit_rsvd = 0;
4401 u64 gbpages_bit_rsvd = 0;
4402 u64 nonleaf_bit8_rsvd = 0;
4404 rsvd_check->bad_mt_xwr = 0;
4407 exb_bit_rsvd = rsvd_bits(63, 63);
4409 gbpages_bit_rsvd = rsvd_bits(7, 7);
4412 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4413 * leaf entries) on AMD CPUs only.
4416 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4419 case PT32_ROOT_LEVEL:
4420 /* no rsvd bits for 2 level 4K page table entries */
4421 rsvd_check->rsvd_bits_mask[0][1] = 0;
4422 rsvd_check->rsvd_bits_mask[0][0] = 0;
4423 rsvd_check->rsvd_bits_mask[1][0] =
4424 rsvd_check->rsvd_bits_mask[0][0];
4427 rsvd_check->rsvd_bits_mask[1][1] = 0;
4431 if (is_cpuid_PSE36())
4432 /* 36bits PSE 4MB page */
4433 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4435 /* 32 bits PSE 4MB page */
4436 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4438 case PT32E_ROOT_LEVEL:
4439 rsvd_check->rsvd_bits_mask[0][2] =
4440 rsvd_bits(maxphyaddr, 63) |
4441 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
4442 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4443 rsvd_bits(maxphyaddr, 62); /* PDE */
4444 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4445 rsvd_bits(maxphyaddr, 62); /* PTE */
4446 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4447 rsvd_bits(maxphyaddr, 62) |
4448 rsvd_bits(13, 20); /* large page */
4449 rsvd_check->rsvd_bits_mask[1][0] =
4450 rsvd_check->rsvd_bits_mask[0][0];
4452 case PT64_ROOT_5LEVEL:
4453 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
4454 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4455 rsvd_bits(maxphyaddr, 51);
4456 rsvd_check->rsvd_bits_mask[1][4] =
4457 rsvd_check->rsvd_bits_mask[0][4];
4459 case PT64_ROOT_4LEVEL:
4460 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4461 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4462 rsvd_bits(maxphyaddr, 51);
4463 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
4465 rsvd_bits(maxphyaddr, 51);
4466 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4467 rsvd_bits(maxphyaddr, 51);
4468 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4469 rsvd_bits(maxphyaddr, 51);
4470 rsvd_check->rsvd_bits_mask[1][3] =
4471 rsvd_check->rsvd_bits_mask[0][3];
4472 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
4473 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
4475 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4476 rsvd_bits(maxphyaddr, 51) |
4477 rsvd_bits(13, 20); /* large page */
4478 rsvd_check->rsvd_bits_mask[1][0] =
4479 rsvd_check->rsvd_bits_mask[0][0];
4484 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4485 struct kvm_mmu *context)
4487 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4488 cpuid_maxphyaddr(vcpu), context->root_level,
4490 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4492 guest_cpuid_is_amd_or_hygon(vcpu));
4496 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4497 int maxphyaddr, bool execonly)
4501 rsvd_check->rsvd_bits_mask[0][4] =
4502 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4503 rsvd_check->rsvd_bits_mask[0][3] =
4504 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4505 rsvd_check->rsvd_bits_mask[0][2] =
4506 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4507 rsvd_check->rsvd_bits_mask[0][1] =
4508 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4509 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4512 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4513 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4514 rsvd_check->rsvd_bits_mask[1][2] =
4515 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4516 rsvd_check->rsvd_bits_mask[1][1] =
4517 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4518 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4520 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4521 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4522 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4523 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4524 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4526 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4527 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4529 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4532 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4533 struct kvm_mmu *context, bool execonly)
4535 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4536 cpuid_maxphyaddr(vcpu), execonly);
4540 * the page table on host is the shadow page table for the page
4541 * table in guest or amd nested guest, its mmu features completely
4542 * follow the features in guest.
4545 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4547 bool uses_nx = context->nx ||
4548 context->mmu_role.base.smep_andnot_wp;
4549 struct rsvd_bits_validate *shadow_zero_check;
4553 * Passing "true" to the last argument is okay; it adds a check
4554 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4556 shadow_zero_check = &context->shadow_zero_check;
4557 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4559 context->shadow_root_level, uses_nx,
4560 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4561 is_pse(vcpu), true);
4563 if (!shadow_me_mask)
4566 for (i = context->shadow_root_level; --i >= 0;) {
4567 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4568 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4572 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4574 static inline bool boot_cpu_is_amd(void)
4576 WARN_ON_ONCE(!tdp_enabled);
4577 return shadow_x_mask == 0;
4581 * the direct page table on host, use as much mmu features as
4582 * possible, however, kvm currently does not do execution-protection.
4585 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4586 struct kvm_mmu *context)
4588 struct rsvd_bits_validate *shadow_zero_check;
4591 shadow_zero_check = &context->shadow_zero_check;
4593 if (boot_cpu_is_amd())
4594 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4596 context->shadow_root_level, false,
4597 boot_cpu_has(X86_FEATURE_GBPAGES),
4600 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4604 if (!shadow_me_mask)
4607 for (i = context->shadow_root_level; --i >= 0;) {
4608 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4609 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4614 * as the comments in reset_shadow_zero_bits_mask() except it
4615 * is the shadow page table for intel nested guest.
4618 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4619 struct kvm_mmu *context, bool execonly)
4621 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4622 shadow_phys_bits, execonly);
4625 #define BYTE_MASK(access) \
4626 ((1 & (access) ? 2 : 0) | \
4627 (2 & (access) ? 4 : 0) | \
4628 (3 & (access) ? 8 : 0) | \
4629 (4 & (access) ? 16 : 0) | \
4630 (5 & (access) ? 32 : 0) | \
4631 (6 & (access) ? 64 : 0) | \
4632 (7 & (access) ? 128 : 0))
4635 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4636 struct kvm_mmu *mmu, bool ept)
4640 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4641 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4642 const u8 u = BYTE_MASK(ACC_USER_MASK);
4644 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4645 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4646 bool cr0_wp = is_write_protection(vcpu);
4648 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4649 unsigned pfec = byte << 1;
4652 * Each "*f" variable has a 1 bit for each UWX value
4653 * that causes a fault with the given PFEC.
4656 /* Faults from writes to non-writable pages */
4657 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4658 /* Faults from user mode accesses to supervisor pages */
4659 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4660 /* Faults from fetches of non-executable pages*/
4661 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4662 /* Faults from kernel mode fetches of user pages */
4664 /* Faults from kernel mode accesses of user pages */
4668 /* Faults from kernel mode accesses to user pages */
4669 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4671 /* Not really needed: !nx will cause pte.nx to fault */
4675 /* Allow supervisor writes if !cr0.wp */
4677 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4679 /* Disallow supervisor fetches of user code if cr4.smep */
4681 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4684 * SMAP:kernel-mode data accesses from user-mode
4685 * mappings should fault. A fault is considered
4686 * as a SMAP violation if all of the following
4687 * conditions are true:
4688 * - X86_CR4_SMAP is set in CR4
4689 * - A user page is accessed
4690 * - The access is not a fetch
4691 * - Page fault in kernel mode
4692 * - if CPL = 3 or X86_EFLAGS_AC is clear
4694 * Here, we cover the first three conditions.
4695 * The fourth is computed dynamically in permission_fault();
4696 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4697 * *not* subject to SMAP restrictions.
4700 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4703 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4708 * PKU is an additional mechanism by which the paging controls access to
4709 * user-mode addresses based on the value in the PKRU register. Protection
4710 * key violations are reported through a bit in the page fault error code.
4711 * Unlike other bits of the error code, the PK bit is not known at the
4712 * call site of e.g. gva_to_gpa; it must be computed directly in
4713 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4714 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4716 * In particular the following conditions come from the error code, the
4717 * page tables and the machine state:
4718 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4719 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4720 * - PK is always zero if U=0 in the page tables
4721 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4723 * The PKRU bitmask caches the result of these four conditions. The error
4724 * code (minus the P bit) and the page table's U bit form an index into the
4725 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4726 * with the two bits of the PKRU register corresponding to the protection key.
4727 * For the first three conditions above the bits will be 00, thus masking
4728 * away both AD and WD. For all reads or if the last condition holds, WD
4729 * only will be masked away.
4731 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4742 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4743 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4748 wp = is_write_protection(vcpu);
4750 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4751 unsigned pfec, pkey_bits;
4752 bool check_pkey, check_write, ff, uf, wf, pte_user;
4755 ff = pfec & PFERR_FETCH_MASK;
4756 uf = pfec & PFERR_USER_MASK;
4757 wf = pfec & PFERR_WRITE_MASK;
4759 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4760 pte_user = pfec & PFERR_RSVD_MASK;
4763 * Only need to check the access which is not an
4764 * instruction fetch and is to a user page.
4766 check_pkey = (!ff && pte_user);
4768 * write access is controlled by PKRU if it is a
4769 * user access or CR0.WP = 1.
4771 check_write = check_pkey && wf && (uf || wp);
4773 /* PKRU.AD stops both read and write access. */
4774 pkey_bits = !!check_pkey;
4775 /* PKRU.WD stops write access. */
4776 pkey_bits |= (!!check_write) << 1;
4778 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4782 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4784 unsigned root_level = mmu->root_level;
4786 mmu->last_nonleaf_level = root_level;
4787 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4788 mmu->last_nonleaf_level++;
4791 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4792 struct kvm_mmu *context,
4795 context->nx = is_nx(vcpu);
4796 context->root_level = level;
4798 reset_rsvds_bits_mask(vcpu, context);
4799 update_permission_bitmask(vcpu, context, false);
4800 update_pkru_bitmask(vcpu, context, false);
4801 update_last_nonleaf_level(vcpu, context);
4803 MMU_WARN_ON(!is_pae(vcpu));
4804 context->page_fault = paging64_page_fault;
4805 context->gva_to_gpa = paging64_gva_to_gpa;
4806 context->sync_page = paging64_sync_page;
4807 context->invlpg = paging64_invlpg;
4808 context->update_pte = paging64_update_pte;
4809 context->shadow_root_level = level;
4810 context->direct_map = false;
4813 static void paging64_init_context(struct kvm_vcpu *vcpu,
4814 struct kvm_mmu *context)
4816 int root_level = is_la57_mode(vcpu) ?
4817 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4819 paging64_init_context_common(vcpu, context, root_level);
4822 static void paging32_init_context(struct kvm_vcpu *vcpu,
4823 struct kvm_mmu *context)
4825 context->nx = false;
4826 context->root_level = PT32_ROOT_LEVEL;
4828 reset_rsvds_bits_mask(vcpu, context);
4829 update_permission_bitmask(vcpu, context, false);
4830 update_pkru_bitmask(vcpu, context, false);
4831 update_last_nonleaf_level(vcpu, context);
4833 context->page_fault = paging32_page_fault;
4834 context->gva_to_gpa = paging32_gva_to_gpa;
4835 context->sync_page = paging32_sync_page;
4836 context->invlpg = paging32_invlpg;
4837 context->update_pte = paging32_update_pte;
4838 context->shadow_root_level = PT32E_ROOT_LEVEL;
4839 context->direct_map = false;
4842 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4843 struct kvm_mmu *context)
4845 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4848 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4850 union kvm_mmu_extended_role ext = {0};
4852 ext.cr0_pg = !!is_paging(vcpu);
4853 ext.cr4_pae = !!is_pae(vcpu);
4854 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4855 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4856 ext.cr4_pse = !!is_pse(vcpu);
4857 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4858 ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
4865 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4868 union kvm_mmu_role role = {0};
4870 role.base.access = ACC_ALL;
4871 role.base.nxe = !!is_nx(vcpu);
4872 role.base.cr0_wp = is_write_protection(vcpu);
4873 role.base.smm = is_smm(vcpu);
4874 role.base.guest_mode = is_guest_mode(vcpu);
4879 role.ext = kvm_calc_mmu_role_ext(vcpu);
4884 static union kvm_mmu_role
4885 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4887 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4889 role.base.ad_disabled = (shadow_accessed_mask == 0);
4890 role.base.level = vcpu->arch.tdp_level;
4891 role.base.direct = true;
4892 role.base.gpte_is_8_bytes = true;
4897 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4899 struct kvm_mmu *context = vcpu->arch.mmu;
4900 union kvm_mmu_role new_role =
4901 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
4903 if (new_role.as_u64 == context->mmu_role.as_u64)
4906 context->mmu_role.as_u64 = new_role.as_u64;
4907 context->page_fault = kvm_tdp_page_fault;
4908 context->sync_page = nonpaging_sync_page;
4909 context->invlpg = NULL;
4910 context->update_pte = nonpaging_update_pte;
4911 context->shadow_root_level = vcpu->arch.tdp_level;
4912 context->direct_map = true;
4913 context->get_guest_pgd = get_cr3;
4914 context->get_pdptr = kvm_pdptr_read;
4915 context->inject_page_fault = kvm_inject_page_fault;
4917 if (!is_paging(vcpu)) {
4918 context->nx = false;
4919 context->gva_to_gpa = nonpaging_gva_to_gpa;
4920 context->root_level = 0;
4921 } else if (is_long_mode(vcpu)) {
4922 context->nx = is_nx(vcpu);
4923 context->root_level = is_la57_mode(vcpu) ?
4924 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4925 reset_rsvds_bits_mask(vcpu, context);
4926 context->gva_to_gpa = paging64_gva_to_gpa;
4927 } else if (is_pae(vcpu)) {
4928 context->nx = is_nx(vcpu);
4929 context->root_level = PT32E_ROOT_LEVEL;
4930 reset_rsvds_bits_mask(vcpu, context);
4931 context->gva_to_gpa = paging64_gva_to_gpa;
4933 context->nx = false;
4934 context->root_level = PT32_ROOT_LEVEL;
4935 reset_rsvds_bits_mask(vcpu, context);
4936 context->gva_to_gpa = paging32_gva_to_gpa;
4939 update_permission_bitmask(vcpu, context, false);
4940 update_pkru_bitmask(vcpu, context, false);
4941 update_last_nonleaf_level(vcpu, context);
4942 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4945 static union kvm_mmu_role
4946 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4948 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4950 role.base.smep_andnot_wp = role.ext.cr4_smep &&
4951 !is_write_protection(vcpu);
4952 role.base.smap_andnot_wp = role.ext.cr4_smap &&
4953 !is_write_protection(vcpu);
4954 role.base.direct = !is_paging(vcpu);
4955 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
4957 if (!is_long_mode(vcpu))
4958 role.base.level = PT32E_ROOT_LEVEL;
4959 else if (is_la57_mode(vcpu))
4960 role.base.level = PT64_ROOT_5LEVEL;
4962 role.base.level = PT64_ROOT_4LEVEL;
4967 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer)
4969 struct kvm_mmu *context = vcpu->arch.mmu;
4970 union kvm_mmu_role new_role =
4971 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4973 if (new_role.as_u64 == context->mmu_role.as_u64)
4976 if (!(cr0 & X86_CR0_PG))
4977 nonpaging_init_context(vcpu, context);
4978 else if (efer & EFER_LMA)
4979 paging64_init_context(vcpu, context);
4980 else if (cr4 & X86_CR4_PAE)
4981 paging32E_init_context(vcpu, context);
4983 paging32_init_context(vcpu, context);
4985 context->mmu_role.as_u64 = new_role.as_u64;
4986 reset_shadow_zero_bits_mask(vcpu, context);
4988 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4990 static union kvm_mmu_role
4991 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4992 bool execonly, u8 level)
4994 union kvm_mmu_role role = {0};
4996 /* SMM flag is inherited from root_mmu */
4997 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4999 role.base.level = level;
5000 role.base.gpte_is_8_bytes = true;
5001 role.base.direct = false;
5002 role.base.ad_disabled = !accessed_dirty;
5003 role.base.guest_mode = true;
5004 role.base.access = ACC_ALL;
5007 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
5008 * SMAP variation to denote shadow EPT entries.
5010 role.base.cr0_wp = true;
5011 role.base.smap_andnot_wp = true;
5013 role.ext = kvm_calc_mmu_role_ext(vcpu);
5014 role.ext.execonly = execonly;
5019 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
5020 bool accessed_dirty, gpa_t new_eptp)
5022 struct kvm_mmu *context = vcpu->arch.mmu;
5023 u8 level = vmx_eptp_page_walk_level(new_eptp);
5024 union kvm_mmu_role new_role =
5025 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
5028 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base, true, true);
5030 if (new_role.as_u64 == context->mmu_role.as_u64)
5033 context->shadow_root_level = level;
5036 context->ept_ad = accessed_dirty;
5037 context->page_fault = ept_page_fault;
5038 context->gva_to_gpa = ept_gva_to_gpa;
5039 context->sync_page = ept_sync_page;
5040 context->invlpg = ept_invlpg;
5041 context->update_pte = ept_update_pte;
5042 context->root_level = level;
5043 context->direct_map = false;
5044 context->mmu_role.as_u64 = new_role.as_u64;
5046 update_permission_bitmask(vcpu, context, true);
5047 update_pkru_bitmask(vcpu, context, true);
5048 update_last_nonleaf_level(vcpu, context);
5049 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
5050 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
5052 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
5054 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
5056 struct kvm_mmu *context = vcpu->arch.mmu;
5058 kvm_init_shadow_mmu(vcpu,
5059 kvm_read_cr0_bits(vcpu, X86_CR0_PG),
5060 kvm_read_cr4_bits(vcpu, X86_CR4_PAE),
5063 context->get_guest_pgd = get_cr3;
5064 context->get_pdptr = kvm_pdptr_read;
5065 context->inject_page_fault = kvm_inject_page_fault;
5068 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
5070 union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false);
5071 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
5073 if (new_role.as_u64 == g_context->mmu_role.as_u64)
5076 g_context->mmu_role.as_u64 = new_role.as_u64;
5077 g_context->get_guest_pgd = get_cr3;
5078 g_context->get_pdptr = kvm_pdptr_read;
5079 g_context->inject_page_fault = kvm_inject_page_fault;
5082 * L2 page tables are never shadowed, so there is no need to sync
5085 g_context->invlpg = NULL;
5088 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
5089 * L1's nested page tables (e.g. EPT12). The nested translation
5090 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
5091 * L2's page tables as the first level of translation and L1's
5092 * nested page tables as the second level of translation. Basically
5093 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
5095 if (!is_paging(vcpu)) {
5096 g_context->nx = false;
5097 g_context->root_level = 0;
5098 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
5099 } else if (is_long_mode(vcpu)) {
5100 g_context->nx = is_nx(vcpu);
5101 g_context->root_level = is_la57_mode(vcpu) ?
5102 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
5103 reset_rsvds_bits_mask(vcpu, g_context);
5104 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5105 } else if (is_pae(vcpu)) {
5106 g_context->nx = is_nx(vcpu);
5107 g_context->root_level = PT32E_ROOT_LEVEL;
5108 reset_rsvds_bits_mask(vcpu, g_context);
5109 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5111 g_context->nx = false;
5112 g_context->root_level = PT32_ROOT_LEVEL;
5113 reset_rsvds_bits_mask(vcpu, g_context);
5114 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
5117 update_permission_bitmask(vcpu, g_context, false);
5118 update_pkru_bitmask(vcpu, g_context, false);
5119 update_last_nonleaf_level(vcpu, g_context);
5122 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
5127 vcpu->arch.mmu->root_hpa = INVALID_PAGE;
5129 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5130 vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5133 if (mmu_is_nested(vcpu))
5134 init_kvm_nested_mmu(vcpu);
5135 else if (tdp_enabled)
5136 init_kvm_tdp_mmu(vcpu);
5138 init_kvm_softmmu(vcpu);
5140 EXPORT_SYMBOL_GPL(kvm_init_mmu);
5142 static union kvm_mmu_page_role
5143 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
5145 union kvm_mmu_role role;
5148 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
5150 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
5155 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
5157 kvm_mmu_unload(vcpu);
5158 kvm_init_mmu(vcpu, true);
5160 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
5162 int kvm_mmu_load(struct kvm_vcpu *vcpu)
5166 r = mmu_topup_memory_caches(vcpu);
5169 r = mmu_alloc_roots(vcpu);
5170 kvm_mmu_sync_roots(vcpu);
5173 kvm_mmu_load_pgd(vcpu);
5174 kvm_x86_ops.tlb_flush_current(vcpu);
5178 EXPORT_SYMBOL_GPL(kvm_mmu_load);
5180 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
5182 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
5183 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
5184 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
5185 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
5187 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
5189 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
5190 struct kvm_mmu_page *sp, u64 *spte,
5193 if (sp->role.level != PG_LEVEL_4K) {
5194 ++vcpu->kvm->stat.mmu_pde_zapped;
5198 ++vcpu->kvm->stat.mmu_pte_updated;
5199 vcpu->arch.mmu->update_pte(vcpu, sp, spte, new);
5202 static bool need_remote_flush(u64 old, u64 new)
5204 if (!is_shadow_present_pte(old))
5206 if (!is_shadow_present_pte(new))
5208 if ((old ^ new) & PT64_BASE_ADDR_MASK)
5210 old ^= shadow_nx_mask;
5211 new ^= shadow_nx_mask;
5212 return (old & ~new & PT64_PERM_MASK) != 0;
5215 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
5222 * Assume that the pte write on a page table of the same type
5223 * as the current vcpu paging mode since we update the sptes only
5224 * when they have the same mode.
5226 if (is_pae(vcpu) && *bytes == 4) {
5227 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5232 if (*bytes == 4 || *bytes == 8) {
5233 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5242 * If we're seeing too many writes to a page, it may no longer be a page table,
5243 * or we may be forking, in which case it is better to unmap the page.
5245 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5248 * Skip write-flooding detected for the sp whose level is 1, because
5249 * it can become unsync, then the guest page is not write-protected.
5251 if (sp->role.level == PG_LEVEL_4K)
5254 atomic_inc(&sp->write_flooding_count);
5255 return atomic_read(&sp->write_flooding_count) >= 3;
5259 * Misaligned accesses are too much trouble to fix up; also, they usually
5260 * indicate a page is not used as a page table.
5262 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5265 unsigned offset, pte_size, misaligned;
5267 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5268 gpa, bytes, sp->role.word);
5270 offset = offset_in_page(gpa);
5271 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5274 * Sometimes, the OS only writes the last one bytes to update status
5275 * bits, for example, in linux, andb instruction is used in clear_bit().
5277 if (!(offset & (pte_size - 1)) && bytes == 1)
5280 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5281 misaligned |= bytes < 4;
5286 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5288 unsigned page_offset, quadrant;
5292 page_offset = offset_in_page(gpa);
5293 level = sp->role.level;
5295 if (!sp->role.gpte_is_8_bytes) {
5296 page_offset <<= 1; /* 32->64 */
5298 * A 32-bit pde maps 4MB while the shadow pdes map
5299 * only 2MB. So we need to double the offset again
5300 * and zap two pdes instead of one.
5302 if (level == PT32_ROOT_LEVEL) {
5303 page_offset &= ~7; /* kill rounding error */
5307 quadrant = page_offset >> PAGE_SHIFT;
5308 page_offset &= ~PAGE_MASK;
5309 if (quadrant != sp->role.quadrant)
5313 spte = &sp->spt[page_offset / sizeof(*spte)];
5318 * Ignore various flags when determining if a SPTE can be immediately
5319 * overwritten for the current MMU.
5320 * - level: explicitly checked in mmu_pte_write_new_pte(), and will never
5321 * match the current MMU role, as MMU's level tracks the root level.
5322 * - access: updated based on the new guest PTE
5323 * - quadrant: handled by get_written_sptes()
5324 * - invalid: always false (loop only walks valid shadow pages)
5326 static const union kvm_mmu_page_role role_ign = {
5333 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5334 const u8 *new, int bytes,
5335 struct kvm_page_track_notifier_node *node)
5337 gfn_t gfn = gpa >> PAGE_SHIFT;
5338 struct kvm_mmu_page *sp;
5339 LIST_HEAD(invalid_list);
5340 u64 entry, gentry, *spte;
5342 bool remote_flush, local_flush;
5345 * If we don't have indirect shadow pages, it means no page is
5346 * write-protected, so we can exit simply.
5348 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5351 remote_flush = local_flush = false;
5353 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5356 * No need to care whether allocation memory is successful
5357 * or not since pte prefetch is skiped if it does not have
5358 * enough objects in the cache.
5360 mmu_topup_memory_caches(vcpu);
5362 spin_lock(&vcpu->kvm->mmu_lock);
5364 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5366 ++vcpu->kvm->stat.mmu_pte_write;
5367 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5369 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5370 if (detect_write_misaligned(sp, gpa, bytes) ||
5371 detect_write_flooding(sp)) {
5372 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5373 ++vcpu->kvm->stat.mmu_flooded;
5377 spte = get_written_sptes(sp, gpa, &npte);
5383 u32 base_role = vcpu->arch.mmu->mmu_role.base.word;
5386 mmu_page_zap_pte(vcpu->kvm, sp, spte);
5388 !((sp->role.word ^ base_role) & ~role_ign.word) &&
5390 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
5391 if (need_remote_flush(entry, *spte))
5392 remote_flush = true;
5396 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5397 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5398 spin_unlock(&vcpu->kvm->mmu_lock);
5401 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
5406 if (vcpu->arch.mmu->direct_map)
5409 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
5411 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
5415 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
5417 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5418 void *insn, int insn_len)
5420 int r, emulation_type = EMULTYPE_PF;
5421 bool direct = vcpu->arch.mmu->direct_map;
5423 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5424 return RET_PF_RETRY;
5427 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5428 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5429 if (r == RET_PF_EMULATE)
5433 if (r == RET_PF_INVALID) {
5434 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5435 lower_32_bits(error_code), false);
5436 WARN_ON(r == RET_PF_INVALID);
5439 if (r == RET_PF_RETRY)
5445 * Before emulating the instruction, check if the error code
5446 * was due to a RO violation while translating the guest page.
5447 * This can occur when using nested virtualization with nested
5448 * paging in both guests. If true, we simply unprotect the page
5449 * and resume the guest.
5451 if (vcpu->arch.mmu->direct_map &&
5452 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5453 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5458 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5459 * optimistically try to just unprotect the page and let the processor
5460 * re-execute the instruction that caused the page fault. Do not allow
5461 * retrying MMIO emulation, as it's not only pointless but could also
5462 * cause us to enter an infinite loop because the processor will keep
5463 * faulting on the non-existent MMIO address. Retrying an instruction
5464 * from a nested guest is also pointless and dangerous as we are only
5465 * explicitly shadowing L1's page tables, i.e. unprotecting something
5466 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5468 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5469 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5472 * On AMD platforms, under certain conditions insn_len may be zero on #NPF.
5473 * This can happen if a guest gets a page-fault on data access but the HW
5474 * table walker is not able to read the instruction page (e.g instruction
5475 * page is not present in memory). In those cases we simply restart the
5476 * guest, with the exception of AMD Erratum 1096 which is unrecoverable.
5478 if (unlikely(insn && !insn_len)) {
5479 if (!kvm_x86_ops.need_emulation_on_page_fault(vcpu))
5483 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5486 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5488 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5489 gva_t gva, hpa_t root_hpa)
5493 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5494 if (mmu != &vcpu->arch.guest_mmu) {
5495 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5496 if (is_noncanonical_address(gva, vcpu))
5499 kvm_x86_ops.tlb_flush_gva(vcpu, gva);
5505 if (root_hpa == INVALID_PAGE) {
5506 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5509 * INVLPG is required to invalidate any global mappings for the VA,
5510 * irrespective of PCID. Since it would take us roughly similar amount
5511 * of work to determine whether any of the prev_root mappings of the VA
5512 * is marked global, or to just sync it blindly, so we might as well
5513 * just always sync it.
5515 * Mappings not reachable via the current cr3 or the prev_roots will be
5516 * synced when switching to that cr3, so nothing needs to be done here
5519 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5520 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5521 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5523 mmu->invlpg(vcpu, gva, root_hpa);
5526 EXPORT_SYMBOL_GPL(kvm_mmu_invalidate_gva);
5528 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5530 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
5531 ++vcpu->stat.invlpg;
5533 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5536 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5538 struct kvm_mmu *mmu = vcpu->arch.mmu;
5539 bool tlb_flush = false;
5542 if (pcid == kvm_get_active_pcid(vcpu)) {
5543 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5547 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5548 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5549 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5550 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5556 kvm_x86_ops.tlb_flush_gva(vcpu, gva);
5558 ++vcpu->stat.invlpg;
5561 * Mappings not reachable via the current cr3 or the prev_roots will be
5562 * synced when switching to that cr3, so nothing needs to be done here
5566 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva);
5568 void kvm_configure_mmu(bool enable_tdp, int tdp_page_level)
5570 tdp_enabled = enable_tdp;
5573 * max_page_level reflects the capabilities of KVM's MMU irrespective
5574 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5575 * the kernel is not. But, KVM never creates a page size greater than
5576 * what is used by the kernel for any given HVA, i.e. the kernel's
5577 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5580 max_page_level = tdp_page_level;
5581 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5582 max_page_level = PG_LEVEL_1G;
5584 max_page_level = PG_LEVEL_2M;
5586 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5588 /* The return value indicates if tlb flush on all vcpus is needed. */
5589 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5591 /* The caller should hold mmu-lock before calling this function. */
5592 static __always_inline bool
5593 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5594 slot_level_handler fn, int start_level, int end_level,
5595 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5597 struct slot_rmap_walk_iterator iterator;
5600 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5601 end_gfn, &iterator) {
5603 flush |= fn(kvm, iterator.rmap);
5605 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5606 if (flush && lock_flush_tlb) {
5607 kvm_flush_remote_tlbs_with_address(kvm,
5609 iterator.gfn - start_gfn + 1);
5612 cond_resched_lock(&kvm->mmu_lock);
5616 if (flush && lock_flush_tlb) {
5617 kvm_flush_remote_tlbs_with_address(kvm, start_gfn,
5618 end_gfn - start_gfn + 1);
5625 static __always_inline bool
5626 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5627 slot_level_handler fn, int start_level, int end_level,
5628 bool lock_flush_tlb)
5630 return slot_handle_level_range(kvm, memslot, fn, start_level,
5631 end_level, memslot->base_gfn,
5632 memslot->base_gfn + memslot->npages - 1,
5636 static __always_inline bool
5637 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5638 slot_level_handler fn, bool lock_flush_tlb)
5640 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5641 KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5644 static __always_inline bool
5645 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5646 slot_level_handler fn, bool lock_flush_tlb)
5648 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K + 1,
5649 KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5652 static __always_inline bool
5653 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5654 slot_level_handler fn, bool lock_flush_tlb)
5656 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5657 PG_LEVEL_4K, lock_flush_tlb);
5660 static void free_mmu_pages(struct kvm_mmu *mmu)
5662 free_page((unsigned long)mmu->pae_root);
5663 free_page((unsigned long)mmu->lm_root);
5666 static int alloc_mmu_pages(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5672 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5673 * while the PDP table is a per-vCPU construct that's allocated at MMU
5674 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5675 * x86_64. Therefore we need to allocate the PDP table in the first
5676 * 4GB of memory, which happens to fit the DMA32 zone. Except for
5677 * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can
5678 * skip allocating the PDP table.
5680 if (tdp_enabled && vcpu->arch.tdp_level > PT32E_ROOT_LEVEL)
5683 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5687 mmu->pae_root = page_address(page);
5688 for (i = 0; i < 4; ++i)
5689 mmu->pae_root[i] = INVALID_PAGE;
5694 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5699 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5700 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5702 vcpu->arch.root_mmu.root_hpa = INVALID_PAGE;
5703 vcpu->arch.root_mmu.root_pgd = 0;
5704 vcpu->arch.root_mmu.translate_gpa = translate_gpa;
5705 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5706 vcpu->arch.root_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5708 vcpu->arch.guest_mmu.root_hpa = INVALID_PAGE;
5709 vcpu->arch.guest_mmu.root_pgd = 0;
5710 vcpu->arch.guest_mmu.translate_gpa = translate_gpa;
5711 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5712 vcpu->arch.guest_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5714 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5716 ret = alloc_mmu_pages(vcpu, &vcpu->arch.guest_mmu);
5720 ret = alloc_mmu_pages(vcpu, &vcpu->arch.root_mmu);
5722 goto fail_allocate_root;
5726 free_mmu_pages(&vcpu->arch.guest_mmu);
5730 #define BATCH_ZAP_PAGES 10
5731 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5733 struct kvm_mmu_page *sp, *node;
5734 int nr_zapped, batch = 0;
5737 list_for_each_entry_safe_reverse(sp, node,
5738 &kvm->arch.active_mmu_pages, link) {
5740 * No obsolete valid page exists before a newly created page
5741 * since active_mmu_pages is a FIFO list.
5743 if (!is_obsolete_sp(kvm, sp))
5747 * Invalid pages should never land back on the list of active
5748 * pages. Skip the bogus page, otherwise we'll get stuck in an
5749 * infinite loop if the page gets put back on the list (again).
5751 if (WARN_ON(sp->role.invalid))
5755 * No need to flush the TLB since we're only zapping shadow
5756 * pages with an obsolete generation number and all vCPUS have
5757 * loaded a new root, i.e. the shadow pages being zapped cannot
5758 * be in active use by the guest.
5760 if (batch >= BATCH_ZAP_PAGES &&
5761 cond_resched_lock(&kvm->mmu_lock)) {
5766 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5767 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5774 * Trigger a remote TLB flush before freeing the page tables to ensure
5775 * KVM is not in the middle of a lockless shadow page table walk, which
5776 * may reference the pages.
5778 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5782 * Fast invalidate all shadow pages and use lock-break technique
5783 * to zap obsolete pages.
5785 * It's required when memslot is being deleted or VM is being
5786 * destroyed, in these cases, we should ensure that KVM MMU does
5787 * not use any resource of the being-deleted slot or all slots
5788 * after calling the function.
5790 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5792 lockdep_assert_held(&kvm->slots_lock);
5794 spin_lock(&kvm->mmu_lock);
5795 trace_kvm_mmu_zap_all_fast(kvm);
5798 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5799 * held for the entire duration of zapping obsolete pages, it's
5800 * impossible for there to be multiple invalid generations associated
5801 * with *valid* shadow pages at any given time, i.e. there is exactly
5802 * one valid generation and (at most) one invalid generation.
5804 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5807 * Notify all vcpus to reload its shadow page table and flush TLB.
5808 * Then all vcpus will switch to new shadow page table with the new
5811 * Note: we need to do this under the protection of mmu_lock,
5812 * otherwise, vcpu would purge shadow page but miss tlb flush.
5814 kvm_reload_remote_mmus(kvm);
5816 kvm_zap_obsolete_pages(kvm);
5817 spin_unlock(&kvm->mmu_lock);
5820 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5822 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5825 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5826 struct kvm_memory_slot *slot,
5827 struct kvm_page_track_notifier_node *node)
5829 kvm_mmu_zap_all_fast(kvm);
5832 void kvm_mmu_init_vm(struct kvm *kvm)
5834 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5836 node->track_write = kvm_mmu_pte_write;
5837 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5838 kvm_page_track_register_notifier(kvm, node);
5841 void kvm_mmu_uninit_vm(struct kvm *kvm)
5843 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5845 kvm_page_track_unregister_notifier(kvm, node);
5848 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5850 struct kvm_memslots *slots;
5851 struct kvm_memory_slot *memslot;
5854 spin_lock(&kvm->mmu_lock);
5855 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5856 slots = __kvm_memslots(kvm, i);
5857 kvm_for_each_memslot(memslot, slots) {
5860 start = max(gfn_start, memslot->base_gfn);
5861 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5865 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5867 KVM_MAX_HUGEPAGE_LEVEL,
5868 start, end - 1, true);
5872 spin_unlock(&kvm->mmu_lock);
5875 static bool slot_rmap_write_protect(struct kvm *kvm,
5876 struct kvm_rmap_head *rmap_head)
5878 return __rmap_write_protect(kvm, rmap_head, false);
5881 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5882 struct kvm_memory_slot *memslot,
5887 spin_lock(&kvm->mmu_lock);
5888 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5889 start_level, KVM_MAX_HUGEPAGE_LEVEL, false);
5890 spin_unlock(&kvm->mmu_lock);
5893 * We can flush all the TLBs out of the mmu lock without TLB
5894 * corruption since we just change the spte from writable to
5895 * readonly so that we only need to care the case of changing
5896 * spte from present to present (changing the spte from present
5897 * to nonpresent will flush all the TLBs immediately), in other
5898 * words, the only case we care is mmu_spte_update() where we
5899 * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5900 * instead of PT_WRITABLE_MASK, that means it does not depend
5901 * on PT_WRITABLE_MASK anymore.
5904 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5907 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5908 struct kvm_rmap_head *rmap_head)
5911 struct rmap_iterator iter;
5912 int need_tlb_flush = 0;
5914 struct kvm_mmu_page *sp;
5917 for_each_rmap_spte(rmap_head, &iter, sptep) {
5918 sp = page_header(__pa(sptep));
5919 pfn = spte_to_pfn(*sptep);
5922 * We cannot do huge page mapping for indirect shadow pages,
5923 * which are found on the last rmap (level = 1) when not using
5924 * tdp; such shadow pages are synced with the page table in
5925 * the guest, and the guest page table is using 4K page size
5926 * mapping if the indirect sp has level = 1.
5928 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5929 (kvm_is_zone_device_pfn(pfn) ||
5930 PageCompound(pfn_to_page(pfn)))) {
5931 pte_list_remove(rmap_head, sptep);
5933 if (kvm_available_flush_tlb_with_range())
5934 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5935 KVM_PAGES_PER_HPAGE(sp->role.level));
5943 return need_tlb_flush;
5946 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5947 const struct kvm_memory_slot *memslot)
5949 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5950 spin_lock(&kvm->mmu_lock);
5951 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5952 kvm_mmu_zap_collapsible_spte, true);
5953 spin_unlock(&kvm->mmu_lock);
5956 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5957 struct kvm_memory_slot *memslot)
5960 * All current use cases for flushing the TLBs for a specific memslot
5961 * are related to dirty logging, and do the TLB flush out of mmu_lock.
5962 * The interaction between the various operations on memslot must be
5963 * serialized by slots_locks to ensure the TLB flush from one operation
5964 * is observed by any other operation on the same memslot.
5966 lockdep_assert_held(&kvm->slots_lock);
5967 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5971 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5972 struct kvm_memory_slot *memslot)
5976 spin_lock(&kvm->mmu_lock);
5977 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5978 spin_unlock(&kvm->mmu_lock);
5981 * It's also safe to flush TLBs out of mmu lock here as currently this
5982 * function is only used for dirty logging, in which case flushing TLB
5983 * out of mmu lock also guarantees no dirty pages will be lost in
5987 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5989 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5991 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5992 struct kvm_memory_slot *memslot)
5996 spin_lock(&kvm->mmu_lock);
5997 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5999 spin_unlock(&kvm->mmu_lock);
6002 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
6004 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
6006 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
6007 struct kvm_memory_slot *memslot)
6011 spin_lock(&kvm->mmu_lock);
6012 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
6013 spin_unlock(&kvm->mmu_lock);
6016 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
6018 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
6020 void kvm_mmu_zap_all(struct kvm *kvm)
6022 struct kvm_mmu_page *sp, *node;
6023 LIST_HEAD(invalid_list);
6026 spin_lock(&kvm->mmu_lock);
6028 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
6029 if (WARN_ON(sp->role.invalid))
6031 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
6033 if (cond_resched_lock(&kvm->mmu_lock))
6037 kvm_mmu_commit_zap_page(kvm, &invalid_list);
6038 spin_unlock(&kvm->mmu_lock);
6041 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
6043 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
6045 gen &= MMIO_SPTE_GEN_MASK;
6048 * Generation numbers are incremented in multiples of the number of
6049 * address spaces in order to provide unique generations across all
6050 * address spaces. Strip what is effectively the address space
6051 * modifier prior to checking for a wrap of the MMIO generation so
6052 * that a wrap in any address space is detected.
6054 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
6057 * The very rare case: if the MMIO generation number has wrapped,
6058 * zap all shadow pages.
6060 if (unlikely(gen == 0)) {
6061 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
6062 kvm_mmu_zap_all_fast(kvm);
6066 static unsigned long
6067 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
6070 int nr_to_scan = sc->nr_to_scan;
6071 unsigned long freed = 0;
6073 mutex_lock(&kvm_lock);
6075 list_for_each_entry(kvm, &vm_list, vm_list) {
6077 LIST_HEAD(invalid_list);
6080 * Never scan more than sc->nr_to_scan VM instances.
6081 * Will not hit this condition practically since we do not try
6082 * to shrink more than one VM and it is very unlikely to see
6083 * !n_used_mmu_pages so many times.
6088 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
6089 * here. We may skip a VM instance errorneosly, but we do not
6090 * want to shrink a VM that only started to populate its MMU
6093 if (!kvm->arch.n_used_mmu_pages &&
6094 !kvm_has_zapped_obsolete_pages(kvm))
6097 idx = srcu_read_lock(&kvm->srcu);
6098 spin_lock(&kvm->mmu_lock);
6100 if (kvm_has_zapped_obsolete_pages(kvm)) {
6101 kvm_mmu_commit_zap_page(kvm,
6102 &kvm->arch.zapped_obsolete_pages);
6106 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
6109 spin_unlock(&kvm->mmu_lock);
6110 srcu_read_unlock(&kvm->srcu, idx);
6113 * unfair on small ones
6114 * per-vm shrinkers cry out
6115 * sadness comes quickly
6117 list_move_tail(&kvm->vm_list, &vm_list);
6121 mutex_unlock(&kvm_lock);
6125 static unsigned long
6126 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
6128 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
6131 static struct shrinker mmu_shrinker = {
6132 .count_objects = mmu_shrink_count,
6133 .scan_objects = mmu_shrink_scan,
6134 .seeks = DEFAULT_SEEKS * 10,
6137 static void mmu_destroy_caches(void)
6139 kmem_cache_destroy(pte_list_desc_cache);
6140 kmem_cache_destroy(mmu_page_header_cache);
6143 static void kvm_set_mmio_spte_mask(void)
6148 * Set a reserved PA bit in MMIO SPTEs to generate page faults with
6149 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT
6150 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports
6151 * 52-bit physical addresses then there are no reserved PA bits in the
6152 * PTEs and so the reserved PA approach must be disabled.
6154 if (shadow_phys_bits < 52)
6155 mask = BIT_ULL(51) | PT_PRESENT_MASK;
6159 kvm_mmu_set_mmio_spte_mask(mask, ACC_WRITE_MASK | ACC_USER_MASK);
6162 static bool get_nx_auto_mode(void)
6164 /* Return true when CPU has the bug, and mitigations are ON */
6165 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
6168 static void __set_nx_huge_pages(bool val)
6170 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
6173 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
6175 bool old_val = nx_huge_pages;
6178 /* In "auto" mode deploy workaround only if CPU has the bug. */
6179 if (sysfs_streq(val, "off"))
6181 else if (sysfs_streq(val, "force"))
6183 else if (sysfs_streq(val, "auto"))
6184 new_val = get_nx_auto_mode();
6185 else if (strtobool(val, &new_val) < 0)
6188 __set_nx_huge_pages(new_val);
6190 if (new_val != old_val) {
6193 mutex_lock(&kvm_lock);
6195 list_for_each_entry(kvm, &vm_list, vm_list) {
6196 mutex_lock(&kvm->slots_lock);
6197 kvm_mmu_zap_all_fast(kvm);
6198 mutex_unlock(&kvm->slots_lock);
6200 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6202 mutex_unlock(&kvm_lock);
6208 int kvm_mmu_module_init(void)
6212 if (nx_huge_pages == -1)
6213 __set_nx_huge_pages(get_nx_auto_mode());
6216 * MMU roles use union aliasing which is, generally speaking, an
6217 * undefined behavior. However, we supposedly know how compilers behave
6218 * and the current status quo is unlikely to change. Guardians below are
6219 * supposed to let us know if the assumption becomes false.
6221 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
6222 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
6223 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
6225 kvm_mmu_reset_all_pte_masks();
6227 kvm_set_mmio_spte_mask();
6229 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
6230 sizeof(struct pte_list_desc),
6231 0, SLAB_ACCOUNT, NULL);
6232 if (!pte_list_desc_cache)
6235 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
6236 sizeof(struct kvm_mmu_page),
6237 0, SLAB_ACCOUNT, NULL);
6238 if (!mmu_page_header_cache)
6241 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
6244 ret = register_shrinker(&mmu_shrinker);
6251 mmu_destroy_caches();
6256 * Calculate mmu pages needed for kvm.
6258 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
6260 unsigned long nr_mmu_pages;
6261 unsigned long nr_pages = 0;
6262 struct kvm_memslots *slots;
6263 struct kvm_memory_slot *memslot;
6266 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6267 slots = __kvm_memslots(kvm, i);
6269 kvm_for_each_memslot(memslot, slots)
6270 nr_pages += memslot->npages;
6273 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
6274 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
6276 return nr_mmu_pages;
6279 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6281 kvm_mmu_unload(vcpu);
6282 free_mmu_pages(&vcpu->arch.root_mmu);
6283 free_mmu_pages(&vcpu->arch.guest_mmu);
6284 mmu_free_memory_caches(vcpu);
6287 void kvm_mmu_module_exit(void)
6289 mmu_destroy_caches();
6290 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6291 unregister_shrinker(&mmu_shrinker);
6292 mmu_audit_disable();
6295 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
6297 unsigned int old_val;
6300 old_val = nx_huge_pages_recovery_ratio;
6301 err = param_set_uint(val, kp);
6305 if (READ_ONCE(nx_huge_pages) &&
6306 !old_val && nx_huge_pages_recovery_ratio) {
6309 mutex_lock(&kvm_lock);
6311 list_for_each_entry(kvm, &vm_list, vm_list)
6312 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6314 mutex_unlock(&kvm_lock);
6320 static void kvm_recover_nx_lpages(struct kvm *kvm)
6323 struct kvm_mmu_page *sp;
6325 LIST_HEAD(invalid_list);
6328 rcu_idx = srcu_read_lock(&kvm->srcu);
6329 spin_lock(&kvm->mmu_lock);
6331 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6332 to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0;
6333 while (to_zap && !list_empty(&kvm->arch.lpage_disallowed_mmu_pages)) {
6335 * We use a separate list instead of just using active_mmu_pages
6336 * because the number of lpage_disallowed pages is expected to
6337 * be relatively small compared to the total.
6339 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6340 struct kvm_mmu_page,
6341 lpage_disallowed_link);
6342 WARN_ON_ONCE(!sp->lpage_disallowed);
6343 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6344 WARN_ON_ONCE(sp->lpage_disallowed);
6346 if (!--to_zap || need_resched() || spin_needbreak(&kvm->mmu_lock)) {
6347 kvm_mmu_commit_zap_page(kvm, &invalid_list);
6349 cond_resched_lock(&kvm->mmu_lock);
6353 spin_unlock(&kvm->mmu_lock);
6354 srcu_read_unlock(&kvm->srcu, rcu_idx);
6357 static long get_nx_lpage_recovery_timeout(u64 start_time)
6359 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6360 ? start_time + 60 * HZ - get_jiffies_64()
6361 : MAX_SCHEDULE_TIMEOUT;
6364 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6367 long remaining_time;
6370 start_time = get_jiffies_64();
6371 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6373 set_current_state(TASK_INTERRUPTIBLE);
6374 while (!kthread_should_stop() && remaining_time > 0) {
6375 schedule_timeout(remaining_time);
6376 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6377 set_current_state(TASK_INTERRUPTIBLE);
6380 set_current_state(TASK_RUNNING);
6382 if (kthread_should_stop())
6385 kvm_recover_nx_lpages(kvm);
6389 int kvm_mmu_post_init_vm(struct kvm *kvm)
6393 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6394 "kvm-nx-lpage-recovery",
6395 &kvm->arch.nx_lpage_recovery_thread);
6397 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6402 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6404 if (kvm->arch.nx_lpage_recovery_thread)
6405 kthread_stop(kvm->arch.nx_lpage_recovery_thread);