1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
52 #include <asm/kvm_page_track.h>
55 extern bool itlb_multihit_kvm_mitigation;
57 static int __read_mostly nx_huge_pages = -1;
58 #ifdef CONFIG_PREEMPT_RT
59 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
60 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
62 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
65 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
66 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
68 static const struct kernel_param_ops nx_huge_pages_ops = {
69 .set = set_nx_huge_pages,
70 .get = param_get_bool,
73 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
74 .set = set_nx_huge_pages_recovery_ratio,
75 .get = param_get_uint,
78 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
79 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
80 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
81 &nx_huge_pages_recovery_ratio, 0644);
82 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
84 static bool __read_mostly force_flush_and_sync_on_reuse;
85 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
88 * When setting this variable to true it enables Two-Dimensional-Paging
89 * where the hardware walks 2 page tables:
90 * 1. the guest-virtual to guest-physical
91 * 2. while doing 1. it walks guest-physical to host-physical
92 * If the hardware supports that we don't need to do shadow paging.
94 bool tdp_enabled = false;
96 static int max_huge_page_level __read_mostly;
97 static int max_tdp_level __read_mostly;
100 AUDIT_PRE_PAGE_FAULT,
101 AUDIT_POST_PAGE_FAULT,
103 AUDIT_POST_PTE_WRITE,
110 module_param(dbg, bool, 0644);
113 #define PTE_PREFETCH_NUM 8
115 #define PT32_LEVEL_BITS 10
117 #define PT32_LEVEL_SHIFT(level) \
118 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
120 #define PT32_LVL_OFFSET_MASK(level) \
121 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
122 * PT32_LEVEL_BITS))) - 1))
124 #define PT32_INDEX(address, level)\
125 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #include <trace/events/kvm.h>
137 /* make pte_list_desc fit well in cache line */
138 #define PTE_LIST_EXT 3
140 struct pte_list_desc {
141 u64 *sptes[PTE_LIST_EXT];
142 struct pte_list_desc *more;
145 struct kvm_shadow_walk_iterator {
153 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
154 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
156 shadow_walk_okay(&(_walker)); \
157 shadow_walk_next(&(_walker)))
159 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
160 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
161 shadow_walk_okay(&(_walker)); \
162 shadow_walk_next(&(_walker)))
164 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
165 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
166 shadow_walk_okay(&(_walker)) && \
167 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
168 __shadow_walk_next(&(_walker), spte))
170 static struct kmem_cache *pte_list_desc_cache;
171 struct kmem_cache *mmu_page_header_cache;
172 static struct percpu_counter kvm_total_used_mmu_pages;
174 static void mmu_spte_set(u64 *sptep, u64 spte);
175 static union kvm_mmu_page_role
176 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
178 #define CREATE_TRACE_POINTS
179 #include "mmutrace.h"
182 static inline bool kvm_available_flush_tlb_with_range(void)
184 return kvm_x86_ops.tlb_remote_flush_with_range;
187 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
188 struct kvm_tlb_range *range)
192 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
193 ret = kvm_x86_ops.tlb_remote_flush_with_range(kvm, range);
196 kvm_flush_remote_tlbs(kvm);
199 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
200 u64 start_gfn, u64 pages)
202 struct kvm_tlb_range range;
204 range.start_gfn = start_gfn;
207 kvm_flush_remote_tlbs_with_range(kvm, &range);
210 bool is_nx_huge_page_enabled(void)
212 return READ_ONCE(nx_huge_pages);
215 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
218 u64 mask = make_mmio_spte(vcpu, gfn, access);
220 trace_mark_mmio_spte(sptep, gfn, mask);
221 mmu_spte_set(sptep, mask);
224 static gfn_t get_mmio_spte_gfn(u64 spte)
226 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
228 gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len)
229 & shadow_nonpresent_or_rsvd_mask;
231 return gpa >> PAGE_SHIFT;
234 static unsigned get_mmio_spte_access(u64 spte)
236 return spte & shadow_mmio_access_mask;
239 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
240 kvm_pfn_t pfn, unsigned int access)
242 if (unlikely(is_noslot_pfn(pfn))) {
243 mark_mmio_spte(vcpu, sptep, gfn, access);
250 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
252 u64 kvm_gen, spte_gen, gen;
254 gen = kvm_vcpu_memslots(vcpu)->generation;
255 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
258 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
259 spte_gen = get_mmio_spte_generation(spte);
261 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
262 return likely(kvm_gen == spte_gen);
265 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
266 struct x86_exception *exception)
268 /* Check if guest physical address doesn't exceed guest maximum */
269 if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) {
270 exception->error_code |= PFERR_RSVD_MASK;
277 static int is_cpuid_PSE36(void)
282 static int is_nx(struct kvm_vcpu *vcpu)
284 return vcpu->arch.efer & EFER_NX;
287 static gfn_t pse36_gfn_delta(u32 gpte)
289 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
291 return (gpte & PT32_DIR_PSE36_MASK) << shift;
295 static void __set_spte(u64 *sptep, u64 spte)
297 WRITE_ONCE(*sptep, spte);
300 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
302 WRITE_ONCE(*sptep, spte);
305 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
307 return xchg(sptep, spte);
310 static u64 __get_spte_lockless(u64 *sptep)
312 return READ_ONCE(*sptep);
323 static void count_spte_clear(u64 *sptep, u64 spte)
325 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
327 if (is_shadow_present_pte(spte))
330 /* Ensure the spte is completely set before we increase the count */
332 sp->clear_spte_count++;
335 static void __set_spte(u64 *sptep, u64 spte)
337 union split_spte *ssptep, sspte;
339 ssptep = (union split_spte *)sptep;
340 sspte = (union split_spte)spte;
342 ssptep->spte_high = sspte.spte_high;
345 * If we map the spte from nonpresent to present, We should store
346 * the high bits firstly, then set present bit, so cpu can not
347 * fetch this spte while we are setting the spte.
351 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
354 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
356 union split_spte *ssptep, sspte;
358 ssptep = (union split_spte *)sptep;
359 sspte = (union split_spte)spte;
361 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
364 * If we map the spte from present to nonpresent, we should clear
365 * present bit firstly to avoid vcpu fetch the old high bits.
369 ssptep->spte_high = sspte.spte_high;
370 count_spte_clear(sptep, spte);
373 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
375 union split_spte *ssptep, sspte, orig;
377 ssptep = (union split_spte *)sptep;
378 sspte = (union split_spte)spte;
380 /* xchg acts as a barrier before the setting of the high bits */
381 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
382 orig.spte_high = ssptep->spte_high;
383 ssptep->spte_high = sspte.spte_high;
384 count_spte_clear(sptep, spte);
390 * The idea using the light way get the spte on x86_32 guest is from
391 * gup_get_pte (mm/gup.c).
393 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
394 * coalesces them and we are running out of the MMU lock. Therefore
395 * we need to protect against in-progress updates of the spte.
397 * Reading the spte while an update is in progress may get the old value
398 * for the high part of the spte. The race is fine for a present->non-present
399 * change (because the high part of the spte is ignored for non-present spte),
400 * but for a present->present change we must reread the spte.
402 * All such changes are done in two steps (present->non-present and
403 * non-present->present), hence it is enough to count the number of
404 * present->non-present updates: if it changed while reading the spte,
405 * we might have hit the race. This is done using clear_spte_count.
407 static u64 __get_spte_lockless(u64 *sptep)
409 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
410 union split_spte spte, *orig = (union split_spte *)sptep;
414 count = sp->clear_spte_count;
417 spte.spte_low = orig->spte_low;
420 spte.spte_high = orig->spte_high;
423 if (unlikely(spte.spte_low != orig->spte_low ||
424 count != sp->clear_spte_count))
431 static bool spte_has_volatile_bits(u64 spte)
433 if (!is_shadow_present_pte(spte))
437 * Always atomically update spte if it can be updated
438 * out of mmu-lock, it can ensure dirty bit is not lost,
439 * also, it can help us to get a stable is_writable_pte()
440 * to ensure tlb flush is not missed.
442 if (spte_can_locklessly_be_made_writable(spte) ||
443 is_access_track_spte(spte))
446 if (spte_ad_enabled(spte)) {
447 if ((spte & shadow_accessed_mask) == 0 ||
448 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
455 /* Rules for using mmu_spte_set:
456 * Set the sptep from nonpresent to present.
457 * Note: the sptep being assigned *must* be either not present
458 * or in a state where the hardware will not attempt to update
461 static void mmu_spte_set(u64 *sptep, u64 new_spte)
463 WARN_ON(is_shadow_present_pte(*sptep));
464 __set_spte(sptep, new_spte);
468 * Update the SPTE (excluding the PFN), but do not track changes in its
469 * accessed/dirty status.
471 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
473 u64 old_spte = *sptep;
475 WARN_ON(!is_shadow_present_pte(new_spte));
477 if (!is_shadow_present_pte(old_spte)) {
478 mmu_spte_set(sptep, new_spte);
482 if (!spte_has_volatile_bits(old_spte))
483 __update_clear_spte_fast(sptep, new_spte);
485 old_spte = __update_clear_spte_slow(sptep, new_spte);
487 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
492 /* Rules for using mmu_spte_update:
493 * Update the state bits, it means the mapped pfn is not changed.
495 * Whenever we overwrite a writable spte with a read-only one we
496 * should flush remote TLBs. Otherwise rmap_write_protect
497 * will find a read-only spte, even though the writable spte
498 * might be cached on a CPU's TLB, the return value indicates this
501 * Returns true if the TLB needs to be flushed
503 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
506 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
508 if (!is_shadow_present_pte(old_spte))
512 * For the spte updated out of mmu-lock is safe, since
513 * we always atomically update it, see the comments in
514 * spte_has_volatile_bits().
516 if (spte_can_locklessly_be_made_writable(old_spte) &&
517 !is_writable_pte(new_spte))
521 * Flush TLB when accessed/dirty states are changed in the page tables,
522 * to guarantee consistency between TLB and page tables.
525 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
527 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
530 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
532 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
539 * Rules for using mmu_spte_clear_track_bits:
540 * It sets the sptep from present to nonpresent, and track the
541 * state bits, it is used to clear the last level sptep.
542 * Returns non-zero if the PTE was previously valid.
544 static int mmu_spte_clear_track_bits(u64 *sptep)
547 u64 old_spte = *sptep;
549 if (!spte_has_volatile_bits(old_spte))
550 __update_clear_spte_fast(sptep, 0ull);
552 old_spte = __update_clear_spte_slow(sptep, 0ull);
554 if (!is_shadow_present_pte(old_spte))
557 pfn = spte_to_pfn(old_spte);
560 * KVM does not hold the refcount of the page used by
561 * kvm mmu, before reclaiming the page, we should
562 * unmap it from mmu first.
564 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
566 if (is_accessed_spte(old_spte))
567 kvm_set_pfn_accessed(pfn);
569 if (is_dirty_spte(old_spte))
570 kvm_set_pfn_dirty(pfn);
576 * Rules for using mmu_spte_clear_no_track:
577 * Directly clear spte without caring the state bits of sptep,
578 * it is used to set the upper level spte.
580 static void mmu_spte_clear_no_track(u64 *sptep)
582 __update_clear_spte_fast(sptep, 0ull);
585 static u64 mmu_spte_get_lockless(u64 *sptep)
587 return __get_spte_lockless(sptep);
590 /* Restore an acc-track PTE back to a regular PTE */
591 static u64 restore_acc_track_spte(u64 spte)
594 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
595 & shadow_acc_track_saved_bits_mask;
597 WARN_ON_ONCE(spte_ad_enabled(spte));
598 WARN_ON_ONCE(!is_access_track_spte(spte));
600 new_spte &= ~shadow_acc_track_mask;
601 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
602 shadow_acc_track_saved_bits_shift);
603 new_spte |= saved_bits;
608 /* Returns the Accessed status of the PTE and resets it at the same time. */
609 static bool mmu_spte_age(u64 *sptep)
611 u64 spte = mmu_spte_get_lockless(sptep);
613 if (!is_accessed_spte(spte))
616 if (spte_ad_enabled(spte)) {
617 clear_bit((ffs(shadow_accessed_mask) - 1),
618 (unsigned long *)sptep);
621 * Capture the dirty status of the page, so that it doesn't get
622 * lost when the SPTE is marked for access tracking.
624 if (is_writable_pte(spte))
625 kvm_set_pfn_dirty(spte_to_pfn(spte));
627 spte = mark_spte_for_access_track(spte);
628 mmu_spte_update_no_track(sptep, spte);
634 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
637 * Prevent page table teardown by making any free-er wait during
638 * kvm_flush_remote_tlbs() IPI to all active vcpus.
643 * Make sure a following spte read is not reordered ahead of the write
646 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
649 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
652 * Make sure the write to vcpu->mode is not reordered in front of
653 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
654 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
656 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
660 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
664 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
665 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
666 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
669 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
670 PT64_ROOT_MAX_LEVEL);
673 if (maybe_indirect) {
674 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
675 PT64_ROOT_MAX_LEVEL);
679 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
680 PT64_ROOT_MAX_LEVEL);
683 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
685 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
686 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
687 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
688 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
691 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
693 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
696 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
698 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
701 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
703 if (!sp->role.direct)
704 return sp->gfns[index];
706 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
709 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
711 if (!sp->role.direct) {
712 sp->gfns[index] = gfn;
716 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
717 pr_err_ratelimited("gfn mismatch under direct page %llx "
718 "(expected %llx, got %llx)\n",
720 kvm_mmu_page_get_gfn(sp, index), gfn);
724 * Return the pointer to the large page information for a given gfn,
725 * handling slots that are not large page aligned.
727 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
728 struct kvm_memory_slot *slot,
733 idx = gfn_to_index(gfn, slot->base_gfn, level);
734 return &slot->arch.lpage_info[level - 2][idx];
737 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
738 gfn_t gfn, int count)
740 struct kvm_lpage_info *linfo;
743 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
744 linfo = lpage_info_slot(gfn, slot, i);
745 linfo->disallow_lpage += count;
746 WARN_ON(linfo->disallow_lpage < 0);
750 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
752 update_gfn_disallow_lpage_count(slot, gfn, 1);
755 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
757 update_gfn_disallow_lpage_count(slot, gfn, -1);
760 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
762 struct kvm_memslots *slots;
763 struct kvm_memory_slot *slot;
766 kvm->arch.indirect_shadow_pages++;
768 slots = kvm_memslots_for_spte_role(kvm, sp->role);
769 slot = __gfn_to_memslot(slots, gfn);
771 /* the non-leaf shadow pages are keeping readonly. */
772 if (sp->role.level > PG_LEVEL_4K)
773 return kvm_slot_page_track_add_page(kvm, slot, gfn,
774 KVM_PAGE_TRACK_WRITE);
776 kvm_mmu_gfn_disallow_lpage(slot, gfn);
779 static void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
781 if (sp->lpage_disallowed)
784 ++kvm->stat.nx_lpage_splits;
785 list_add_tail(&sp->lpage_disallowed_link,
786 &kvm->arch.lpage_disallowed_mmu_pages);
787 sp->lpage_disallowed = true;
790 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
792 struct kvm_memslots *slots;
793 struct kvm_memory_slot *slot;
796 kvm->arch.indirect_shadow_pages--;
798 slots = kvm_memslots_for_spte_role(kvm, sp->role);
799 slot = __gfn_to_memslot(slots, gfn);
800 if (sp->role.level > PG_LEVEL_4K)
801 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
802 KVM_PAGE_TRACK_WRITE);
804 kvm_mmu_gfn_allow_lpage(slot, gfn);
807 static void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
809 --kvm->stat.nx_lpage_splits;
810 sp->lpage_disallowed = false;
811 list_del(&sp->lpage_disallowed_link);
814 static struct kvm_memory_slot *
815 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
818 struct kvm_memory_slot *slot;
820 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
821 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
823 if (no_dirty_log && slot->dirty_bitmap)
830 * About rmap_head encoding:
832 * If the bit zero of rmap_head->val is clear, then it points to the only spte
833 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
834 * pte_list_desc containing more mappings.
838 * Returns the number of pointers in the rmap chain, not counting the new one.
840 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
841 struct kvm_rmap_head *rmap_head)
843 struct pte_list_desc *desc;
846 if (!rmap_head->val) {
847 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
848 rmap_head->val = (unsigned long)spte;
849 } else if (!(rmap_head->val & 1)) {
850 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
851 desc = mmu_alloc_pte_list_desc(vcpu);
852 desc->sptes[0] = (u64 *)rmap_head->val;
853 desc->sptes[1] = spte;
854 rmap_head->val = (unsigned long)desc | 1;
857 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
858 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
859 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
861 count += PTE_LIST_EXT;
863 if (desc->sptes[PTE_LIST_EXT-1]) {
864 desc->more = mmu_alloc_pte_list_desc(vcpu);
867 for (i = 0; desc->sptes[i]; ++i)
869 desc->sptes[i] = spte;
875 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
876 struct pte_list_desc *desc, int i,
877 struct pte_list_desc *prev_desc)
881 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
883 desc->sptes[i] = desc->sptes[j];
884 desc->sptes[j] = NULL;
887 if (!prev_desc && !desc->more)
891 prev_desc->more = desc->more;
893 rmap_head->val = (unsigned long)desc->more | 1;
894 mmu_free_pte_list_desc(desc);
897 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
899 struct pte_list_desc *desc;
900 struct pte_list_desc *prev_desc;
903 if (!rmap_head->val) {
904 pr_err("%s: %p 0->BUG\n", __func__, spte);
906 } else if (!(rmap_head->val & 1)) {
907 rmap_printk("%s: %p 1->0\n", __func__, spte);
908 if ((u64 *)rmap_head->val != spte) {
909 pr_err("%s: %p 1->BUG\n", __func__, spte);
914 rmap_printk("%s: %p many->many\n", __func__, spte);
915 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
918 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
919 if (desc->sptes[i] == spte) {
920 pte_list_desc_remove_entry(rmap_head,
928 pr_err("%s: %p many->many\n", __func__, spte);
933 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
935 mmu_spte_clear_track_bits(sptep);
936 __pte_list_remove(sptep, rmap_head);
939 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
940 struct kvm_memory_slot *slot)
944 idx = gfn_to_index(gfn, slot->base_gfn, level);
945 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
948 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
949 struct kvm_mmu_page *sp)
951 struct kvm_memslots *slots;
952 struct kvm_memory_slot *slot;
954 slots = kvm_memslots_for_spte_role(kvm, sp->role);
955 slot = __gfn_to_memslot(slots, gfn);
956 return __gfn_to_rmap(gfn, sp->role.level, slot);
959 static bool rmap_can_add(struct kvm_vcpu *vcpu)
961 struct kvm_mmu_memory_cache *mc;
963 mc = &vcpu->arch.mmu_pte_list_desc_cache;
964 return kvm_mmu_memory_cache_nr_free_objects(mc);
967 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
969 struct kvm_mmu_page *sp;
970 struct kvm_rmap_head *rmap_head;
972 sp = sptep_to_sp(spte);
973 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
974 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
975 return pte_list_add(vcpu, spte, rmap_head);
978 static void rmap_remove(struct kvm *kvm, u64 *spte)
980 struct kvm_mmu_page *sp;
982 struct kvm_rmap_head *rmap_head;
984 sp = sptep_to_sp(spte);
985 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
986 rmap_head = gfn_to_rmap(kvm, gfn, sp);
987 __pte_list_remove(spte, rmap_head);
991 * Used by the following functions to iterate through the sptes linked by a
992 * rmap. All fields are private and not assumed to be used outside.
994 struct rmap_iterator {
996 struct pte_list_desc *desc; /* holds the sptep if not NULL */
997 int pos; /* index of the sptep */
1001 * Iteration must be started by this function. This should also be used after
1002 * removing/dropping sptes from the rmap link because in such cases the
1003 * information in the iterator may not be valid.
1005 * Returns sptep if found, NULL otherwise.
1007 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1008 struct rmap_iterator *iter)
1012 if (!rmap_head->val)
1015 if (!(rmap_head->val & 1)) {
1017 sptep = (u64 *)rmap_head->val;
1021 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1023 sptep = iter->desc->sptes[iter->pos];
1025 BUG_ON(!is_shadow_present_pte(*sptep));
1030 * Must be used with a valid iterator: e.g. after rmap_get_first().
1032 * Returns sptep if found, NULL otherwise.
1034 static u64 *rmap_get_next(struct rmap_iterator *iter)
1039 if (iter->pos < PTE_LIST_EXT - 1) {
1041 sptep = iter->desc->sptes[iter->pos];
1046 iter->desc = iter->desc->more;
1050 /* desc->sptes[0] cannot be NULL */
1051 sptep = iter->desc->sptes[iter->pos];
1058 BUG_ON(!is_shadow_present_pte(*sptep));
1062 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1063 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1064 _spte_; _spte_ = rmap_get_next(_iter_))
1066 static void drop_spte(struct kvm *kvm, u64 *sptep)
1068 if (mmu_spte_clear_track_bits(sptep))
1069 rmap_remove(kvm, sptep);
1073 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1075 if (is_large_pte(*sptep)) {
1076 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1077 drop_spte(kvm, sptep);
1085 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1087 if (__drop_large_spte(vcpu->kvm, sptep)) {
1088 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1090 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1091 KVM_PAGES_PER_HPAGE(sp->role.level));
1096 * Write-protect on the specified @sptep, @pt_protect indicates whether
1097 * spte write-protection is caused by protecting shadow page table.
1099 * Note: write protection is difference between dirty logging and spte
1101 * - for dirty logging, the spte can be set to writable at anytime if
1102 * its dirty bitmap is properly set.
1103 * - for spte protection, the spte can be writable only after unsync-ing
1106 * Return true if tlb need be flushed.
1108 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1112 if (!is_writable_pte(spte) &&
1113 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1116 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1119 spte &= ~SPTE_MMU_WRITEABLE;
1120 spte = spte & ~PT_WRITABLE_MASK;
1122 return mmu_spte_update(sptep, spte);
1125 static bool __rmap_write_protect(struct kvm *kvm,
1126 struct kvm_rmap_head *rmap_head,
1130 struct rmap_iterator iter;
1133 for_each_rmap_spte(rmap_head, &iter, sptep)
1134 flush |= spte_write_protect(sptep, pt_protect);
1139 static bool spte_clear_dirty(u64 *sptep)
1143 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1145 MMU_WARN_ON(!spte_ad_enabled(spte));
1146 spte &= ~shadow_dirty_mask;
1147 return mmu_spte_update(sptep, spte);
1150 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1152 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1153 (unsigned long *)sptep);
1154 if (was_writable && !spte_ad_enabled(*sptep))
1155 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1157 return was_writable;
1161 * Gets the GFN ready for another round of dirty logging by clearing the
1162 * - D bit on ad-enabled SPTEs, and
1163 * - W bit on ad-disabled SPTEs.
1164 * Returns true iff any D or W bits were cleared.
1166 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1169 struct rmap_iterator iter;
1172 for_each_rmap_spte(rmap_head, &iter, sptep)
1173 if (spte_ad_need_write_protect(*sptep))
1174 flush |= spte_wrprot_for_clear_dirty(sptep);
1176 flush |= spte_clear_dirty(sptep);
1181 static bool spte_set_dirty(u64 *sptep)
1185 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1188 * Similar to the !kvm_x86_ops.slot_disable_log_dirty case,
1189 * do not bother adding back write access to pages marked
1190 * SPTE_AD_WRPROT_ONLY_MASK.
1192 spte |= shadow_dirty_mask;
1194 return mmu_spte_update(sptep, spte);
1197 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1200 struct rmap_iterator iter;
1203 for_each_rmap_spte(rmap_head, &iter, sptep)
1204 if (spte_ad_enabled(*sptep))
1205 flush |= spte_set_dirty(sptep);
1211 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1212 * @kvm: kvm instance
1213 * @slot: slot to protect
1214 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1215 * @mask: indicates which pages we should protect
1217 * Used when we do not need to care about huge page mappings: e.g. during dirty
1218 * logging we do not have any such mappings.
1220 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1221 struct kvm_memory_slot *slot,
1222 gfn_t gfn_offset, unsigned long mask)
1224 struct kvm_rmap_head *rmap_head;
1226 if (kvm->arch.tdp_mmu_enabled)
1227 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1228 slot->base_gfn + gfn_offset, mask, true);
1230 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1232 __rmap_write_protect(kvm, rmap_head, false);
1234 /* clear the first set bit */
1240 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1241 * protect the page if the D-bit isn't supported.
1242 * @kvm: kvm instance
1243 * @slot: slot to clear D-bit
1244 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1245 * @mask: indicates which pages we should clear D-bit
1247 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1249 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1250 struct kvm_memory_slot *slot,
1251 gfn_t gfn_offset, unsigned long mask)
1253 struct kvm_rmap_head *rmap_head;
1255 if (kvm->arch.tdp_mmu_enabled)
1256 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1257 slot->base_gfn + gfn_offset, mask, false);
1259 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1261 __rmap_clear_dirty(kvm, rmap_head);
1263 /* clear the first set bit */
1267 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1270 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1273 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1274 * enable dirty logging for them.
1276 * Used when we do not need to care about huge page mappings: e.g. during dirty
1277 * logging we do not have any such mappings.
1279 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1280 struct kvm_memory_slot *slot,
1281 gfn_t gfn_offset, unsigned long mask)
1283 if (kvm_x86_ops.enable_log_dirty_pt_masked)
1284 kvm_x86_ops.enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1287 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1290 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1291 struct kvm_memory_slot *slot, u64 gfn)
1293 struct kvm_rmap_head *rmap_head;
1295 bool write_protected = false;
1297 for (i = PG_LEVEL_4K; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1298 rmap_head = __gfn_to_rmap(gfn, i, slot);
1299 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1302 if (kvm->arch.tdp_mmu_enabled)
1304 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn);
1306 return write_protected;
1309 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1311 struct kvm_memory_slot *slot;
1313 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1314 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1317 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1320 struct rmap_iterator iter;
1323 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1324 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1326 pte_list_remove(rmap_head, sptep);
1333 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1334 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1337 return kvm_zap_rmapp(kvm, rmap_head);
1340 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1341 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1345 struct rmap_iterator iter;
1348 pte_t *ptep = (pte_t *)data;
1351 WARN_ON(pte_huge(*ptep));
1352 new_pfn = pte_pfn(*ptep);
1355 for_each_rmap_spte(rmap_head, &iter, sptep) {
1356 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1357 sptep, *sptep, gfn, level);
1361 if (pte_write(*ptep)) {
1362 pte_list_remove(rmap_head, sptep);
1365 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1368 mmu_spte_clear_track_bits(sptep);
1369 mmu_spte_set(sptep, new_spte);
1373 if (need_flush && kvm_available_flush_tlb_with_range()) {
1374 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1381 struct slot_rmap_walk_iterator {
1383 struct kvm_memory_slot *slot;
1389 /* output fields. */
1391 struct kvm_rmap_head *rmap;
1394 /* private field. */
1395 struct kvm_rmap_head *end_rmap;
1399 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1401 iterator->level = level;
1402 iterator->gfn = iterator->start_gfn;
1403 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1404 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1409 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1410 struct kvm_memory_slot *slot, int start_level,
1411 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1413 iterator->slot = slot;
1414 iterator->start_level = start_level;
1415 iterator->end_level = end_level;
1416 iterator->start_gfn = start_gfn;
1417 iterator->end_gfn = end_gfn;
1419 rmap_walk_init_level(iterator, iterator->start_level);
1422 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1424 return !!iterator->rmap;
1427 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1429 if (++iterator->rmap <= iterator->end_rmap) {
1430 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1434 if (++iterator->level > iterator->end_level) {
1435 iterator->rmap = NULL;
1439 rmap_walk_init_level(iterator, iterator->level);
1442 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1443 _start_gfn, _end_gfn, _iter_) \
1444 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1445 _end_level_, _start_gfn, _end_gfn); \
1446 slot_rmap_walk_okay(_iter_); \
1447 slot_rmap_walk_next(_iter_))
1449 static int kvm_handle_hva_range(struct kvm *kvm,
1450 unsigned long start,
1453 int (*handler)(struct kvm *kvm,
1454 struct kvm_rmap_head *rmap_head,
1455 struct kvm_memory_slot *slot,
1458 unsigned long data))
1460 struct kvm_memslots *slots;
1461 struct kvm_memory_slot *memslot;
1462 struct slot_rmap_walk_iterator iterator;
1466 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1467 slots = __kvm_memslots(kvm, i);
1468 kvm_for_each_memslot(memslot, slots) {
1469 unsigned long hva_start, hva_end;
1470 gfn_t gfn_start, gfn_end;
1472 hva_start = max(start, memslot->userspace_addr);
1473 hva_end = min(end, memslot->userspace_addr +
1474 (memslot->npages << PAGE_SHIFT));
1475 if (hva_start >= hva_end)
1478 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1479 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1481 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1482 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1484 for_each_slot_rmap_range(memslot, PG_LEVEL_4K,
1485 KVM_MAX_HUGEPAGE_LEVEL,
1486 gfn_start, gfn_end - 1,
1488 ret |= handler(kvm, iterator.rmap, memslot,
1489 iterator.gfn, iterator.level, data);
1496 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1498 int (*handler)(struct kvm *kvm,
1499 struct kvm_rmap_head *rmap_head,
1500 struct kvm_memory_slot *slot,
1501 gfn_t gfn, int level,
1502 unsigned long data))
1504 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1507 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end,
1512 r = kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1514 if (kvm->arch.tdp_mmu_enabled)
1515 r |= kvm_tdp_mmu_zap_hva_range(kvm, start, end);
1520 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1524 r = kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1526 if (kvm->arch.tdp_mmu_enabled)
1527 r |= kvm_tdp_mmu_set_spte_hva(kvm, hva, &pte);
1532 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1533 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1537 struct rmap_iterator iter;
1540 for_each_rmap_spte(rmap_head, &iter, sptep)
1541 young |= mmu_spte_age(sptep);
1543 trace_kvm_age_page(gfn, level, slot, young);
1547 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1548 struct kvm_memory_slot *slot, gfn_t gfn,
1549 int level, unsigned long data)
1552 struct rmap_iterator iter;
1554 for_each_rmap_spte(rmap_head, &iter, sptep)
1555 if (is_accessed_spte(*sptep))
1560 #define RMAP_RECYCLE_THRESHOLD 1000
1562 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1564 struct kvm_rmap_head *rmap_head;
1565 struct kvm_mmu_page *sp;
1567 sp = sptep_to_sp(spte);
1569 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1571 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1572 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1573 KVM_PAGES_PER_HPAGE(sp->role.level));
1576 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1580 young = kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1581 if (kvm->arch.tdp_mmu_enabled)
1582 young |= kvm_tdp_mmu_age_hva_range(kvm, start, end);
1587 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1591 young = kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1592 if (kvm->arch.tdp_mmu_enabled)
1593 young |= kvm_tdp_mmu_test_age_hva(kvm, hva);
1599 static int is_empty_shadow_page(u64 *spt)
1604 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1605 if (is_shadow_present_pte(*pos)) {
1606 printk(KERN_ERR "%s: %p %llx\n", __func__,
1615 * This value is the sum of all of the kvm instances's
1616 * kvm->arch.n_used_mmu_pages values. We need a global,
1617 * aggregate version in order to make the slab shrinker
1620 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
1622 kvm->arch.n_used_mmu_pages += nr;
1623 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1626 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1628 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1629 hlist_del(&sp->hash_link);
1630 list_del(&sp->link);
1631 free_page((unsigned long)sp->spt);
1632 if (!sp->role.direct)
1633 free_page((unsigned long)sp->gfns);
1634 kmem_cache_free(mmu_page_header_cache, sp);
1637 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1639 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1642 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1643 struct kvm_mmu_page *sp, u64 *parent_pte)
1648 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1651 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1654 __pte_list_remove(parent_pte, &sp->parent_ptes);
1657 static void drop_parent_pte(struct kvm_mmu_page *sp,
1660 mmu_page_remove_parent_pte(sp, parent_pte);
1661 mmu_spte_clear_no_track(parent_pte);
1664 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1666 struct kvm_mmu_page *sp;
1668 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1669 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1671 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1672 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1675 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1676 * depends on valid pages being added to the head of the list. See
1677 * comments in kvm_zap_obsolete_pages().
1679 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1680 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1681 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1685 static void mark_unsync(u64 *spte);
1686 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1689 struct rmap_iterator iter;
1691 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1696 static void mark_unsync(u64 *spte)
1698 struct kvm_mmu_page *sp;
1701 sp = sptep_to_sp(spte);
1702 index = spte - sp->spt;
1703 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1705 if (sp->unsync_children++)
1707 kvm_mmu_mark_parents_unsync(sp);
1710 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1711 struct kvm_mmu_page *sp)
1716 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1717 struct kvm_mmu_page *sp, u64 *spte,
1723 #define KVM_PAGE_ARRAY_NR 16
1725 struct kvm_mmu_pages {
1726 struct mmu_page_and_offset {
1727 struct kvm_mmu_page *sp;
1729 } page[KVM_PAGE_ARRAY_NR];
1733 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1739 for (i=0; i < pvec->nr; i++)
1740 if (pvec->page[i].sp == sp)
1743 pvec->page[pvec->nr].sp = sp;
1744 pvec->page[pvec->nr].idx = idx;
1746 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1749 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1751 --sp->unsync_children;
1752 WARN_ON((int)sp->unsync_children < 0);
1753 __clear_bit(idx, sp->unsync_child_bitmap);
1756 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1757 struct kvm_mmu_pages *pvec)
1759 int i, ret, nr_unsync_leaf = 0;
1761 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1762 struct kvm_mmu_page *child;
1763 u64 ent = sp->spt[i];
1765 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1766 clear_unsync_child_bit(sp, i);
1770 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1772 if (child->unsync_children) {
1773 if (mmu_pages_add(pvec, child, i))
1776 ret = __mmu_unsync_walk(child, pvec);
1778 clear_unsync_child_bit(sp, i);
1780 } else if (ret > 0) {
1781 nr_unsync_leaf += ret;
1784 } else if (child->unsync) {
1786 if (mmu_pages_add(pvec, child, i))
1789 clear_unsync_child_bit(sp, i);
1792 return nr_unsync_leaf;
1795 #define INVALID_INDEX (-1)
1797 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1798 struct kvm_mmu_pages *pvec)
1801 if (!sp->unsync_children)
1804 mmu_pages_add(pvec, sp, INVALID_INDEX);
1805 return __mmu_unsync_walk(sp, pvec);
1808 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1810 WARN_ON(!sp->unsync);
1811 trace_kvm_mmu_sync_page(sp);
1813 --kvm->stat.mmu_unsync;
1816 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1817 struct list_head *invalid_list);
1818 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1819 struct list_head *invalid_list);
1821 #define for_each_valid_sp(_kvm, _sp, _list) \
1822 hlist_for_each_entry(_sp, _list, hash_link) \
1823 if (is_obsolete_sp((_kvm), (_sp))) { \
1826 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1827 for_each_valid_sp(_kvm, _sp, \
1828 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1829 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1831 static inline bool is_ept_sp(struct kvm_mmu_page *sp)
1833 return sp->role.cr0_wp && sp->role.smap_andnot_wp;
1836 /* @sp->gfn should be write-protected at the call site */
1837 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1838 struct list_head *invalid_list)
1840 if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) ||
1841 vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
1842 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1849 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1850 struct list_head *invalid_list,
1853 if (!remote_flush && list_empty(invalid_list))
1856 if (!list_empty(invalid_list))
1857 kvm_mmu_commit_zap_page(kvm, invalid_list);
1859 kvm_flush_remote_tlbs(kvm);
1863 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1864 struct list_head *invalid_list,
1865 bool remote_flush, bool local_flush)
1867 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
1871 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1874 #ifdef CONFIG_KVM_MMU_AUDIT
1875 #include "mmu_audit.c"
1877 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1878 static void mmu_audit_disable(void) { }
1881 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1883 return sp->role.invalid ||
1884 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1887 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1888 struct list_head *invalid_list)
1890 kvm_unlink_unsync_page(vcpu->kvm, sp);
1891 return __kvm_sync_page(vcpu, sp, invalid_list);
1894 /* @gfn should be write-protected at the call site */
1895 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
1896 struct list_head *invalid_list)
1898 struct kvm_mmu_page *s;
1901 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1905 WARN_ON(s->role.level != PG_LEVEL_4K);
1906 ret |= kvm_sync_page(vcpu, s, invalid_list);
1912 struct mmu_page_path {
1913 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1914 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1917 #define for_each_sp(pvec, sp, parents, i) \
1918 for (i = mmu_pages_first(&pvec, &parents); \
1919 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1920 i = mmu_pages_next(&pvec, &parents, i))
1922 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1923 struct mmu_page_path *parents,
1928 for (n = i+1; n < pvec->nr; n++) {
1929 struct kvm_mmu_page *sp = pvec->page[n].sp;
1930 unsigned idx = pvec->page[n].idx;
1931 int level = sp->role.level;
1933 parents->idx[level-1] = idx;
1934 if (level == PG_LEVEL_4K)
1937 parents->parent[level-2] = sp;
1943 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1944 struct mmu_page_path *parents)
1946 struct kvm_mmu_page *sp;
1952 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1954 sp = pvec->page[0].sp;
1955 level = sp->role.level;
1956 WARN_ON(level == PG_LEVEL_4K);
1958 parents->parent[level-2] = sp;
1960 /* Also set up a sentinel. Further entries in pvec are all
1961 * children of sp, so this element is never overwritten.
1963 parents->parent[level-1] = NULL;
1964 return mmu_pages_next(pvec, parents, 0);
1967 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1969 struct kvm_mmu_page *sp;
1970 unsigned int level = 0;
1973 unsigned int idx = parents->idx[level];
1974 sp = parents->parent[level];
1978 WARN_ON(idx == INVALID_INDEX);
1979 clear_unsync_child_bit(sp, idx);
1981 } while (!sp->unsync_children);
1984 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1985 struct kvm_mmu_page *parent)
1988 struct kvm_mmu_page *sp;
1989 struct mmu_page_path parents;
1990 struct kvm_mmu_pages pages;
1991 LIST_HEAD(invalid_list);
1994 while (mmu_unsync_walk(parent, &pages)) {
1995 bool protected = false;
1997 for_each_sp(pages, sp, parents, i)
1998 protected |= rmap_write_protect(vcpu, sp->gfn);
2001 kvm_flush_remote_tlbs(vcpu->kvm);
2005 for_each_sp(pages, sp, parents, i) {
2006 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2007 mmu_pages_clear_parents(&parents);
2009 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2010 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2011 cond_resched_lock(&vcpu->kvm->mmu_lock);
2016 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2019 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2021 atomic_set(&sp->write_flooding_count, 0);
2024 static void clear_sp_write_flooding_count(u64 *spte)
2026 __clear_sp_write_flooding_count(sptep_to_sp(spte));
2029 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2034 unsigned int access)
2036 bool direct_mmu = vcpu->arch.mmu->direct_map;
2037 union kvm_mmu_page_role role;
2038 struct hlist_head *sp_list;
2040 struct kvm_mmu_page *sp;
2041 bool need_sync = false;
2044 LIST_HEAD(invalid_list);
2046 role = vcpu->arch.mmu->mmu_role.base;
2048 role.direct = direct;
2050 role.gpte_is_8_bytes = true;
2051 role.access = access;
2052 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2053 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2054 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2055 role.quadrant = quadrant;
2058 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2059 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2060 if (sp->gfn != gfn) {
2065 if (!need_sync && sp->unsync)
2068 if (sp->role.word != role.word)
2072 goto trace_get_page;
2075 /* The page is good, but __kvm_sync_page might still end
2076 * up zapping it. If so, break in order to rebuild it.
2078 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2081 WARN_ON(!list_empty(&invalid_list));
2082 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2085 if (sp->unsync_children)
2086 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2088 __clear_sp_write_flooding_count(sp);
2091 trace_kvm_mmu_get_page(sp, false);
2095 ++vcpu->kvm->stat.mmu_cache_miss;
2097 sp = kvm_mmu_alloc_page(vcpu, direct);
2101 hlist_add_head(&sp->hash_link, sp_list);
2104 * we should do write protection before syncing pages
2105 * otherwise the content of the synced shadow page may
2106 * be inconsistent with guest page table.
2108 account_shadowed(vcpu->kvm, sp);
2109 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2110 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2112 if (level > PG_LEVEL_4K && need_sync)
2113 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2115 trace_kvm_mmu_get_page(sp, true);
2117 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2119 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2120 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2124 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2125 struct kvm_vcpu *vcpu, hpa_t root,
2128 iterator->addr = addr;
2129 iterator->shadow_addr = root;
2130 iterator->level = vcpu->arch.mmu->shadow_root_level;
2132 if (iterator->level == PT64_ROOT_4LEVEL &&
2133 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2134 !vcpu->arch.mmu->direct_map)
2137 if (iterator->level == PT32E_ROOT_LEVEL) {
2139 * prev_root is currently only used for 64-bit hosts. So only
2140 * the active root_hpa is valid here.
2142 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2144 iterator->shadow_addr
2145 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2146 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2148 if (!iterator->shadow_addr)
2149 iterator->level = 0;
2153 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2154 struct kvm_vcpu *vcpu, u64 addr)
2156 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2160 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2162 if (iterator->level < PG_LEVEL_4K)
2165 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2166 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2170 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2173 if (is_last_spte(spte, iterator->level)) {
2174 iterator->level = 0;
2178 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2182 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2184 __shadow_walk_next(iterator, *iterator->sptep);
2187 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2188 struct kvm_mmu_page *sp)
2192 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2194 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2196 mmu_spte_set(sptep, spte);
2198 mmu_page_add_parent_pte(vcpu, sp, sptep);
2200 if (sp->unsync_children || sp->unsync)
2204 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2205 unsigned direct_access)
2207 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2208 struct kvm_mmu_page *child;
2211 * For the direct sp, if the guest pte's dirty bit
2212 * changed form clean to dirty, it will corrupt the
2213 * sp's access: allow writable in the read-only sp,
2214 * so we should update the spte at this point to get
2215 * a new sp with the correct access.
2217 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2218 if (child->role.access == direct_access)
2221 drop_parent_pte(child, sptep);
2222 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2226 /* Returns the number of zapped non-leaf child shadow pages. */
2227 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2228 u64 *spte, struct list_head *invalid_list)
2231 struct kvm_mmu_page *child;
2234 if (is_shadow_present_pte(pte)) {
2235 if (is_last_spte(pte, sp->role.level)) {
2236 drop_spte(kvm, spte);
2237 if (is_large_pte(pte))
2240 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2241 drop_parent_pte(child, spte);
2244 * Recursively zap nested TDP SPs, parentless SPs are
2245 * unlikely to be used again in the near future. This
2246 * avoids retaining a large number of stale nested SPs.
2248 if (tdp_enabled && invalid_list &&
2249 child->role.guest_mode && !child->parent_ptes.val)
2250 return kvm_mmu_prepare_zap_page(kvm, child,
2253 } else if (is_mmio_spte(pte)) {
2254 mmu_spte_clear_no_track(spte);
2259 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2260 struct kvm_mmu_page *sp,
2261 struct list_head *invalid_list)
2266 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2267 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2272 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2275 struct rmap_iterator iter;
2277 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2278 drop_parent_pte(sp, sptep);
2281 static int mmu_zap_unsync_children(struct kvm *kvm,
2282 struct kvm_mmu_page *parent,
2283 struct list_head *invalid_list)
2286 struct mmu_page_path parents;
2287 struct kvm_mmu_pages pages;
2289 if (parent->role.level == PG_LEVEL_4K)
2292 while (mmu_unsync_walk(parent, &pages)) {
2293 struct kvm_mmu_page *sp;
2295 for_each_sp(pages, sp, parents, i) {
2296 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2297 mmu_pages_clear_parents(&parents);
2305 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2306 struct kvm_mmu_page *sp,
2307 struct list_head *invalid_list,
2312 trace_kvm_mmu_prepare_zap_page(sp);
2313 ++kvm->stat.mmu_shadow_zapped;
2314 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2315 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2316 kvm_mmu_unlink_parents(kvm, sp);
2318 /* Zapping children means active_mmu_pages has become unstable. */
2319 list_unstable = *nr_zapped;
2321 if (!sp->role.invalid && !sp->role.direct)
2322 unaccount_shadowed(kvm, sp);
2325 kvm_unlink_unsync_page(kvm, sp);
2326 if (!sp->root_count) {
2331 * Already invalid pages (previously active roots) are not on
2332 * the active page list. See list_del() in the "else" case of
2335 if (sp->role.invalid)
2336 list_add(&sp->link, invalid_list);
2338 list_move(&sp->link, invalid_list);
2339 kvm_mod_used_mmu_pages(kvm, -1);
2342 * Remove the active root from the active page list, the root
2343 * will be explicitly freed when the root_count hits zero.
2345 list_del(&sp->link);
2348 * Obsolete pages cannot be used on any vCPUs, see the comment
2349 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2350 * treats invalid shadow pages as being obsolete.
2352 if (!is_obsolete_sp(kvm, sp))
2353 kvm_reload_remote_mmus(kvm);
2356 if (sp->lpage_disallowed)
2357 unaccount_huge_nx_page(kvm, sp);
2359 sp->role.invalid = 1;
2360 return list_unstable;
2363 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2364 struct list_head *invalid_list)
2368 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2372 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2373 struct list_head *invalid_list)
2375 struct kvm_mmu_page *sp, *nsp;
2377 if (list_empty(invalid_list))
2381 * We need to make sure everyone sees our modifications to
2382 * the page tables and see changes to vcpu->mode here. The barrier
2383 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2384 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2386 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2387 * guest mode and/or lockless shadow page table walks.
2389 kvm_flush_remote_tlbs(kvm);
2391 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2392 WARN_ON(!sp->role.invalid || sp->root_count);
2393 kvm_mmu_free_page(sp);
2397 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2398 unsigned long nr_to_zap)
2400 unsigned long total_zapped = 0;
2401 struct kvm_mmu_page *sp, *tmp;
2402 LIST_HEAD(invalid_list);
2406 if (list_empty(&kvm->arch.active_mmu_pages))
2410 list_for_each_entry_safe(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2412 * Don't zap active root pages, the page itself can't be freed
2413 * and zapping it will just force vCPUs to realloc and reload.
2418 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2420 total_zapped += nr_zapped;
2421 if (total_zapped >= nr_to_zap)
2428 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2430 kvm->stat.mmu_recycled += total_zapped;
2431 return total_zapped;
2434 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2436 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2437 return kvm->arch.n_max_mmu_pages -
2438 kvm->arch.n_used_mmu_pages;
2443 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2445 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2447 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2450 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2452 if (!kvm_mmu_available_pages(vcpu->kvm))
2458 * Changing the number of mmu pages allocated to the vm
2459 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2461 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2463 spin_lock(&kvm->mmu_lock);
2465 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2466 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2469 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2472 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2474 spin_unlock(&kvm->mmu_lock);
2477 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2479 struct kvm_mmu_page *sp;
2480 LIST_HEAD(invalid_list);
2483 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2485 spin_lock(&kvm->mmu_lock);
2486 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2487 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2490 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2492 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2493 spin_unlock(&kvm->mmu_lock);
2497 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2499 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2501 trace_kvm_mmu_unsync_page(sp);
2502 ++vcpu->kvm->stat.mmu_unsync;
2505 kvm_mmu_mark_parents_unsync(sp);
2508 bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2511 struct kvm_mmu_page *sp;
2513 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2516 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2523 WARN_ON(sp->role.level != PG_LEVEL_4K);
2524 kvm_unsync_page(vcpu, sp);
2528 * We need to ensure that the marking of unsync pages is visible
2529 * before the SPTE is updated to allow writes because
2530 * kvm_mmu_sync_roots() checks the unsync flags without holding
2531 * the MMU lock and so can race with this. If the SPTE was updated
2532 * before the page had been marked as unsync-ed, something like the
2533 * following could happen:
2536 * ---------------------------------------------------------------------
2537 * 1.2 Host updates SPTE
2539 * 2.1 Guest writes a GPTE for GVA X.
2540 * (GPTE being in the guest page table shadowed
2541 * by the SP from CPU 1.)
2542 * This reads SPTE during the page table walk.
2543 * Since SPTE.W is read as 1, there is no
2546 * 2.2 Guest issues TLB flush.
2547 * That causes a VM Exit.
2549 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2550 * Since it is false, so it just returns.
2552 * 2.4 Guest accesses GVA X.
2553 * Since the mapping in the SP was not updated,
2554 * so the old mapping for GVA X incorrectly
2558 * (sp->unsync = true)
2560 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2561 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2562 * pairs with this write barrier.
2569 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2570 unsigned int pte_access, int level,
2571 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2572 bool can_unsync, bool host_writable)
2575 struct kvm_mmu_page *sp;
2578 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2581 sp = sptep_to_sp(sptep);
2583 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2584 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2586 if (spte & PT_WRITABLE_MASK)
2587 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2590 ret |= SET_SPTE_SPURIOUS;
2591 else if (mmu_spte_update(sptep, spte))
2592 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2596 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2597 unsigned int pte_access, bool write_fault, int level,
2598 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2601 int was_rmapped = 0;
2604 int ret = RET_PF_FIXED;
2607 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2608 *sptep, write_fault, gfn);
2610 if (is_shadow_present_pte(*sptep)) {
2612 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2613 * the parent of the now unreachable PTE.
2615 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2616 struct kvm_mmu_page *child;
2619 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2620 drop_parent_pte(child, sptep);
2622 } else if (pfn != spte_to_pfn(*sptep)) {
2623 pgprintk("hfn old %llx new %llx\n",
2624 spte_to_pfn(*sptep), pfn);
2625 drop_spte(vcpu->kvm, sptep);
2631 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2632 speculative, true, host_writable);
2633 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2635 ret = RET_PF_EMULATE;
2636 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2639 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2640 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2641 KVM_PAGES_PER_HPAGE(level));
2643 if (unlikely(is_mmio_spte(*sptep)))
2644 ret = RET_PF_EMULATE;
2647 * The fault is fully spurious if and only if the new SPTE and old SPTE
2648 * are identical, and emulation is not required.
2650 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2651 WARN_ON_ONCE(!was_rmapped);
2652 return RET_PF_SPURIOUS;
2655 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2656 trace_kvm_mmu_set_spte(level, gfn, sptep);
2657 if (!was_rmapped && is_large_pte(*sptep))
2658 ++vcpu->kvm->stat.lpages;
2660 if (is_shadow_present_pte(*sptep)) {
2662 rmap_count = rmap_add(vcpu, sptep, gfn);
2663 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2664 rmap_recycle(vcpu, sptep, gfn);
2671 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2674 struct kvm_memory_slot *slot;
2676 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2678 return KVM_PFN_ERR_FAULT;
2680 return gfn_to_pfn_memslot_atomic(slot, gfn);
2683 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2684 struct kvm_mmu_page *sp,
2685 u64 *start, u64 *end)
2687 struct page *pages[PTE_PREFETCH_NUM];
2688 struct kvm_memory_slot *slot;
2689 unsigned int access = sp->role.access;
2693 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2694 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2698 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2702 for (i = 0; i < ret; i++, gfn++, start++) {
2703 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2704 page_to_pfn(pages[i]), true, true);
2711 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2712 struct kvm_mmu_page *sp, u64 *sptep)
2714 u64 *spte, *start = NULL;
2717 WARN_ON(!sp->role.direct);
2719 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2722 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2723 if (is_shadow_present_pte(*spte) || spte == sptep) {
2726 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2734 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2736 struct kvm_mmu_page *sp;
2738 sp = sptep_to_sp(sptep);
2741 * Without accessed bits, there's no way to distinguish between
2742 * actually accessed translations and prefetched, so disable pte
2743 * prefetch if accessed bits aren't available.
2745 if (sp_ad_disabled(sp))
2748 if (sp->role.level > PG_LEVEL_4K)
2751 __direct_pte_prefetch(vcpu, sp, sptep);
2754 static int host_pfn_mapping_level(struct kvm_vcpu *vcpu, gfn_t gfn,
2755 kvm_pfn_t pfn, struct kvm_memory_slot *slot)
2761 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2765 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2766 * is not solely for performance, it's also necessary to avoid the
2767 * "writable" check in __gfn_to_hva_many(), which will always fail on
2768 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2769 * page fault steps have already verified the guest isn't writing a
2770 * read-only memslot.
2772 hva = __gfn_to_hva_memslot(slot, gfn);
2774 pte = lookup_address_in_mm(vcpu->kvm->mm, hva, &level);
2781 int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2782 int max_level, kvm_pfn_t *pfnp,
2783 bool huge_page_disallowed, int *req_level)
2785 struct kvm_memory_slot *slot;
2786 struct kvm_lpage_info *linfo;
2787 kvm_pfn_t pfn = *pfnp;
2791 *req_level = PG_LEVEL_4K;
2793 if (unlikely(max_level == PG_LEVEL_4K))
2796 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
2799 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2803 max_level = min(max_level, max_huge_page_level);
2804 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2805 linfo = lpage_info_slot(gfn, slot, max_level);
2806 if (!linfo->disallow_lpage)
2810 if (max_level == PG_LEVEL_4K)
2813 level = host_pfn_mapping_level(vcpu, gfn, pfn, slot);
2814 if (level == PG_LEVEL_4K)
2817 *req_level = level = min(level, max_level);
2820 * Enforce the iTLB multihit workaround after capturing the requested
2821 * level, which will be used to do precise, accurate accounting.
2823 if (huge_page_disallowed)
2827 * mmu_notifier_retry() was successful and mmu_lock is held, so
2828 * the pmd can't be split from under us.
2830 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2831 VM_BUG_ON((gfn & mask) != (pfn & mask));
2832 *pfnp = pfn & ~mask;
2837 void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2838 kvm_pfn_t *pfnp, int *goal_levelp)
2840 int level = *goal_levelp;
2842 if (cur_level == level && level > PG_LEVEL_4K &&
2843 is_shadow_present_pte(spte) &&
2844 !is_large_pte(spte)) {
2846 * A small SPTE exists for this pfn, but FNAME(fetch)
2847 * and __direct_map would like to create a large PTE
2848 * instead: just force them to go down another level,
2849 * patching back for them into pfn the next 9 bits of
2852 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2853 KVM_PAGES_PER_HPAGE(level - 1);
2854 *pfnp |= gfn & page_mask;
2859 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
2860 int map_writable, int max_level, kvm_pfn_t pfn,
2861 bool prefault, bool is_tdp)
2863 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2864 bool write = error_code & PFERR_WRITE_MASK;
2865 bool exec = error_code & PFERR_FETCH_MASK;
2866 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
2867 struct kvm_shadow_walk_iterator it;
2868 struct kvm_mmu_page *sp;
2869 int level, req_level, ret;
2870 gfn_t gfn = gpa >> PAGE_SHIFT;
2871 gfn_t base_gfn = gfn;
2873 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
2874 return RET_PF_RETRY;
2876 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2877 huge_page_disallowed, &req_level);
2879 trace_kvm_mmu_spte_requested(gpa, level, pfn);
2880 for_each_shadow_entry(vcpu, gpa, it) {
2882 * We cannot overwrite existing page tables with an NX
2883 * large page, as the leaf could be executable.
2885 if (nx_huge_page_workaround_enabled)
2886 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
2889 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2890 if (it.level == level)
2893 drop_large_spte(vcpu, it.sptep);
2894 if (!is_shadow_present_pte(*it.sptep)) {
2895 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2896 it.level - 1, true, ACC_ALL);
2898 link_shadow_page(vcpu, it.sptep, sp);
2899 if (is_tdp && huge_page_disallowed &&
2900 req_level >= it.level)
2901 account_huge_nx_page(vcpu->kvm, sp);
2905 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2906 write, level, base_gfn, pfn, prefault,
2908 if (ret == RET_PF_SPURIOUS)
2911 direct_pte_prefetch(vcpu, it.sptep);
2912 ++vcpu->stat.pf_fixed;
2916 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2918 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2921 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2924 * Do not cache the mmio info caused by writing the readonly gfn
2925 * into the spte otherwise read access on readonly gfn also can
2926 * caused mmio page fault and treat it as mmio access.
2928 if (pfn == KVM_PFN_ERR_RO_FAULT)
2929 return RET_PF_EMULATE;
2931 if (pfn == KVM_PFN_ERR_HWPOISON) {
2932 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2933 return RET_PF_RETRY;
2939 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2940 kvm_pfn_t pfn, unsigned int access,
2943 /* The pfn is invalid, report the error! */
2944 if (unlikely(is_error_pfn(pfn))) {
2945 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2949 if (unlikely(is_noslot_pfn(pfn)))
2950 vcpu_cache_mmio_info(vcpu, gva, gfn,
2951 access & shadow_mmio_access_mask);
2956 static bool page_fault_can_be_fast(u32 error_code)
2959 * Do not fix the mmio spte with invalid generation number which
2960 * need to be updated by slow page fault path.
2962 if (unlikely(error_code & PFERR_RSVD_MASK))
2965 /* See if the page fault is due to an NX violation */
2966 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
2967 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
2971 * #PF can be fast if:
2972 * 1. The shadow page table entry is not present, which could mean that
2973 * the fault is potentially caused by access tracking (if enabled).
2974 * 2. The shadow page table entry is present and the fault
2975 * is caused by write-protect, that means we just need change the W
2976 * bit of the spte which can be done out of mmu-lock.
2978 * However, if access tracking is disabled we know that a non-present
2979 * page must be a genuine page fault where we have to create a new SPTE.
2980 * So, if access tracking is disabled, we return true only for write
2981 * accesses to a present page.
2984 return shadow_acc_track_mask != 0 ||
2985 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
2986 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
2990 * Returns true if the SPTE was fixed successfully. Otherwise,
2991 * someone else modified the SPTE from its original value.
2994 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2995 u64 *sptep, u64 old_spte, u64 new_spte)
2999 WARN_ON(!sp->role.direct);
3002 * Theoretically we could also set dirty bit (and flush TLB) here in
3003 * order to eliminate unnecessary PML logging. See comments in
3004 * set_spte. But fast_page_fault is very unlikely to happen with PML
3005 * enabled, so we do not do this. This might result in the same GPA
3006 * to be logged in PML buffer again when the write really happens, and
3007 * eventually to be called by mark_page_dirty twice. But it's also no
3008 * harm. This also avoids the TLB flush needed after setting dirty bit
3009 * so non-PML cases won't be impacted.
3011 * Compare with set_spte where instead shadow_dirty_mask is set.
3013 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3016 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3018 * The gfn of direct spte is stable since it is
3019 * calculated by sp->gfn.
3021 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3022 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3028 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3030 if (fault_err_code & PFERR_FETCH_MASK)
3031 return is_executable_pte(spte);
3033 if (fault_err_code & PFERR_WRITE_MASK)
3034 return is_writable_pte(spte);
3036 /* Fault was on Read access */
3037 return spte & PT_PRESENT_MASK;
3041 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3043 static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3046 struct kvm_shadow_walk_iterator iterator;
3047 struct kvm_mmu_page *sp;
3048 int ret = RET_PF_INVALID;
3050 uint retry_count = 0;
3052 if (!page_fault_can_be_fast(error_code))
3055 walk_shadow_page_lockless_begin(vcpu);
3060 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3061 if (!is_shadow_present_pte(spte))
3064 sp = sptep_to_sp(iterator.sptep);
3065 if (!is_last_spte(spte, sp->role.level))
3069 * Check whether the memory access that caused the fault would
3070 * still cause it if it were to be performed right now. If not,
3071 * then this is a spurious fault caused by TLB lazily flushed,
3072 * or some other CPU has already fixed the PTE after the
3073 * current CPU took the fault.
3075 * Need not check the access of upper level table entries since
3076 * they are always ACC_ALL.
3078 if (is_access_allowed(error_code, spte)) {
3079 ret = RET_PF_SPURIOUS;
3085 if (is_access_track_spte(spte))
3086 new_spte = restore_acc_track_spte(new_spte);
3089 * Currently, to simplify the code, write-protection can
3090 * be removed in the fast path only if the SPTE was
3091 * write-protected for dirty-logging or access tracking.
3093 if ((error_code & PFERR_WRITE_MASK) &&
3094 spte_can_locklessly_be_made_writable(spte)) {
3095 new_spte |= PT_WRITABLE_MASK;
3098 * Do not fix write-permission on the large spte. Since
3099 * we only dirty the first page into the dirty-bitmap in
3100 * fast_pf_fix_direct_spte(), other pages are missed
3101 * if its slot has dirty logging enabled.
3103 * Instead, we let the slow page fault path create a
3104 * normal spte to fix the access.
3106 * See the comments in kvm_arch_commit_memory_region().
3108 if (sp->role.level > PG_LEVEL_4K)
3112 /* Verify that the fault can be handled in the fast path */
3113 if (new_spte == spte ||
3114 !is_access_allowed(error_code, new_spte))
3118 * Currently, fast page fault only works for direct mapping
3119 * since the gfn is not stable for indirect shadow page. See
3120 * Documentation/virt/kvm/locking.rst to get more detail.
3122 if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte,
3128 if (++retry_count > 4) {
3129 printk_once(KERN_WARNING
3130 "kvm: Fast #PF retrying more than 4 times.\n");
3136 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3138 walk_shadow_page_lockless_end(vcpu);
3143 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3144 struct list_head *invalid_list)
3146 struct kvm_mmu_page *sp;
3148 if (!VALID_PAGE(*root_hpa))
3151 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3153 if (kvm_mmu_put_root(kvm, sp)) {
3154 if (sp->tdp_mmu_page)
3155 kvm_tdp_mmu_free_root(kvm, sp);
3156 else if (sp->role.invalid)
3157 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3160 *root_hpa = INVALID_PAGE;
3163 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3164 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3165 ulong roots_to_free)
3167 struct kvm *kvm = vcpu->kvm;
3169 LIST_HEAD(invalid_list);
3170 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3172 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3174 /* Before acquiring the MMU lock, see if we need to do any real work. */
3175 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3176 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3177 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3178 VALID_PAGE(mmu->prev_roots[i].hpa))
3181 if (i == KVM_MMU_NUM_PREV_ROOTS)
3185 spin_lock(&kvm->mmu_lock);
3187 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3188 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3189 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3192 if (free_active_root) {
3193 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3194 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3195 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3197 for (i = 0; i < 4; ++i)
3198 if (mmu->pae_root[i] != 0)
3199 mmu_free_root_page(kvm,
3202 mmu->root_hpa = INVALID_PAGE;
3207 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3208 spin_unlock(&kvm->mmu_lock);
3210 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3212 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3216 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3217 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3224 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3225 u8 level, bool direct)
3227 struct kvm_mmu_page *sp;
3229 spin_lock(&vcpu->kvm->mmu_lock);
3231 if (make_mmu_pages_available(vcpu)) {
3232 spin_unlock(&vcpu->kvm->mmu_lock);
3233 return INVALID_PAGE;
3235 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3238 spin_unlock(&vcpu->kvm->mmu_lock);
3239 return __pa(sp->spt);
3242 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3244 u8 shadow_root_level = vcpu->arch.mmu->shadow_root_level;
3248 if (vcpu->kvm->arch.tdp_mmu_enabled) {
3249 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3251 if (!VALID_PAGE(root))
3253 vcpu->arch.mmu->root_hpa = root;
3254 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3255 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level,
3258 if (!VALID_PAGE(root))
3260 vcpu->arch.mmu->root_hpa = root;
3261 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3262 for (i = 0; i < 4; ++i) {
3263 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
3265 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3266 i << 30, PT32_ROOT_LEVEL, true);
3267 if (!VALID_PAGE(root))
3269 vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK;
3271 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3275 /* root_pgd is ignored for direct MMUs. */
3276 vcpu->arch.mmu->root_pgd = 0;
3281 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3284 gfn_t root_gfn, root_pgd;
3288 root_pgd = vcpu->arch.mmu->get_guest_pgd(vcpu);
3289 root_gfn = root_pgd >> PAGE_SHIFT;
3291 if (mmu_check_root(vcpu, root_gfn))
3295 * Do we shadow a long mode page table? If so we need to
3296 * write-protect the guests page table root.
3298 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3299 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->root_hpa));
3301 root = mmu_alloc_root(vcpu, root_gfn, 0,
3302 vcpu->arch.mmu->shadow_root_level, false);
3303 if (!VALID_PAGE(root))
3305 vcpu->arch.mmu->root_hpa = root;
3310 * We shadow a 32 bit page table. This may be a legacy 2-level
3311 * or a PAE 3-level page table. In either case we need to be aware that
3312 * the shadow page table may be a PAE or a long mode page table.
3314 pm_mask = PT_PRESENT_MASK;
3315 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3316 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3318 for (i = 0; i < 4; ++i) {
3319 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
3320 if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) {
3321 pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i);
3322 if (!(pdptr & PT_PRESENT_MASK)) {
3323 vcpu->arch.mmu->pae_root[i] = 0;
3326 root_gfn = pdptr >> PAGE_SHIFT;
3327 if (mmu_check_root(vcpu, root_gfn))
3331 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3332 PT32_ROOT_LEVEL, false);
3333 if (!VALID_PAGE(root))
3335 vcpu->arch.mmu->pae_root[i] = root | pm_mask;
3337 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3340 * If we shadow a 32 bit page table with a long mode page
3341 * table we enter this path.
3343 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3344 if (vcpu->arch.mmu->lm_root == NULL) {
3346 * The additional page necessary for this is only
3347 * allocated on demand.
3352 lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3353 if (lm_root == NULL)
3356 lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask;
3358 vcpu->arch.mmu->lm_root = lm_root;
3361 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root);
3365 vcpu->arch.mmu->root_pgd = root_pgd;
3370 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3372 if (vcpu->arch.mmu->direct_map)
3373 return mmu_alloc_direct_roots(vcpu);
3375 return mmu_alloc_shadow_roots(vcpu);
3378 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3381 struct kvm_mmu_page *sp;
3383 if (vcpu->arch.mmu->direct_map)
3386 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3389 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3391 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3392 hpa_t root = vcpu->arch.mmu->root_hpa;
3393 sp = to_shadow_page(root);
3396 * Even if another CPU was marking the SP as unsync-ed
3397 * simultaneously, any guest page table changes are not
3398 * guaranteed to be visible anyway until this VCPU issues a TLB
3399 * flush strictly after those changes are made. We only need to
3400 * ensure that the other CPU sets these flags before any actual
3401 * changes to the page tables are made. The comments in
3402 * mmu_need_write_protect() describe what could go wrong if this
3403 * requirement isn't satisfied.
3405 if (!smp_load_acquire(&sp->unsync) &&
3406 !smp_load_acquire(&sp->unsync_children))
3409 spin_lock(&vcpu->kvm->mmu_lock);
3410 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3412 mmu_sync_children(vcpu, sp);
3414 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3415 spin_unlock(&vcpu->kvm->mmu_lock);
3419 spin_lock(&vcpu->kvm->mmu_lock);
3420 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3422 for (i = 0; i < 4; ++i) {
3423 hpa_t root = vcpu->arch.mmu->pae_root[i];
3425 if (root && VALID_PAGE(root)) {
3426 root &= PT64_BASE_ADDR_MASK;
3427 sp = to_shadow_page(root);
3428 mmu_sync_children(vcpu, sp);
3432 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3433 spin_unlock(&vcpu->kvm->mmu_lock);
3435 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3437 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3438 u32 access, struct x86_exception *exception)
3441 exception->error_code = 0;
3445 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3447 struct x86_exception *exception)
3450 exception->error_code = 0;
3451 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3455 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3457 int bit7 = (pte >> 7) & 1;
3459 return pte & rsvd_check->rsvd_bits_mask[bit7][level-1];
3462 static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte)
3464 return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
3467 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3470 * A nested guest cannot use the MMIO cache if it is using nested
3471 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3473 if (mmu_is_nested(vcpu))
3477 return vcpu_match_mmio_gpa(vcpu, addr);
3479 return vcpu_match_mmio_gva(vcpu, addr);
3482 /* return true if reserved bit is detected on spte. */
3484 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3486 struct kvm_shadow_walk_iterator iterator;
3487 u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull;
3488 struct rsvd_bits_validate *rsvd_check;
3490 bool reserved = false;
3492 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3494 walk_shadow_page_lockless_begin(vcpu);
3496 for (shadow_walk_init(&iterator, vcpu, addr),
3497 leaf = root = iterator.level;
3498 shadow_walk_okay(&iterator);
3499 __shadow_walk_next(&iterator, spte)) {
3500 spte = mmu_spte_get_lockless(iterator.sptep);
3502 sptes[leaf - 1] = spte;
3505 if (!is_shadow_present_pte(spte))
3509 * Use a bitwise-OR instead of a logical-OR to aggregate the
3510 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3511 * adding a Jcc in the loop.
3513 reserved |= __is_bad_mt_xwr(rsvd_check, spte) |
3514 __is_rsvd_bits_set(rsvd_check, spte, iterator.level);
3517 walk_shadow_page_lockless_end(vcpu);
3520 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3522 while (root > leaf) {
3523 pr_err("------ spte 0x%llx level %d.\n",
3524 sptes[root - 1], root);
3533 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3538 if (mmio_info_in_cache(vcpu, addr, direct))
3539 return RET_PF_EMULATE;
3541 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3542 if (WARN_ON(reserved))
3545 if (is_mmio_spte(spte)) {
3546 gfn_t gfn = get_mmio_spte_gfn(spte);
3547 unsigned int access = get_mmio_spte_access(spte);
3549 if (!check_mmio_spte(vcpu, spte))
3550 return RET_PF_INVALID;
3555 trace_handle_mmio_page_fault(addr, gfn, access);
3556 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3557 return RET_PF_EMULATE;
3561 * If the page table is zapped by other cpus, let CPU fault again on
3564 return RET_PF_RETRY;
3567 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3568 u32 error_code, gfn_t gfn)
3570 if (unlikely(error_code & PFERR_RSVD_MASK))
3573 if (!(error_code & PFERR_PRESENT_MASK) ||
3574 !(error_code & PFERR_WRITE_MASK))
3578 * guest is writing the page which is write tracked which can
3579 * not be fixed by page fault handler.
3581 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3587 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3589 struct kvm_shadow_walk_iterator iterator;
3592 walk_shadow_page_lockless_begin(vcpu);
3593 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3594 clear_sp_write_flooding_count(iterator.sptep);
3595 if (!is_shadow_present_pte(spte))
3598 walk_shadow_page_lockless_end(vcpu);
3601 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3604 struct kvm_arch_async_pf arch;
3606 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3608 arch.direct_map = vcpu->arch.mmu->direct_map;
3609 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3611 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3612 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3615 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3616 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, bool write,
3619 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3622 /* Don't expose private memslots to L2. */
3623 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3624 *pfn = KVM_PFN_NOSLOT;
3630 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3632 return false; /* *pfn has correct page already */
3634 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3635 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
3636 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3637 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
3638 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3640 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
3644 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3648 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3649 bool prefault, int max_level, bool is_tdp)
3651 bool write = error_code & PFERR_WRITE_MASK;
3654 gfn_t gfn = gpa >> PAGE_SHIFT;
3655 unsigned long mmu_seq;
3659 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3660 return RET_PF_EMULATE;
3662 if (!is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) {
3663 r = fast_page_fault(vcpu, gpa, error_code);
3664 if (r != RET_PF_INVALID)
3668 r = mmu_topup_memory_caches(vcpu, false);
3672 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3675 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3676 return RET_PF_RETRY;
3678 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
3682 spin_lock(&vcpu->kvm->mmu_lock);
3683 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3685 r = make_mmu_pages_available(vcpu);
3689 if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
3690 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
3693 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
3697 spin_unlock(&vcpu->kvm->mmu_lock);
3698 kvm_release_pfn_clean(pfn);
3702 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
3703 u32 error_code, bool prefault)
3705 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
3707 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3708 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3709 PG_LEVEL_2M, false);
3712 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3713 u64 fault_address, char *insn, int insn_len)
3716 u32 flags = vcpu->arch.apf.host_apf_flags;
3718 #ifndef CONFIG_X86_64
3719 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3720 if (WARN_ON_ONCE(fault_address >> 32))
3724 vcpu->arch.l1tf_flush_l1d = true;
3726 trace_kvm_page_fault(fault_address, error_code);
3728 if (kvm_event_needs_reinjection(vcpu))
3729 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3730 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3732 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
3733 vcpu->arch.apf.host_apf_flags = 0;
3734 local_irq_disable();
3735 kvm_async_pf_task_wait_schedule(fault_address);
3738 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
3743 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3745 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3750 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3751 max_level > PG_LEVEL_4K;
3753 int page_num = KVM_PAGES_PER_HPAGE(max_level);
3754 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
3756 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
3760 return direct_page_fault(vcpu, gpa, error_code, prefault,
3764 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3765 struct kvm_mmu *context)
3767 context->page_fault = nonpaging_page_fault;
3768 context->gva_to_gpa = nonpaging_gva_to_gpa;
3769 context->sync_page = nonpaging_sync_page;
3770 context->invlpg = NULL;
3771 context->update_pte = nonpaging_update_pte;
3772 context->root_level = 0;
3773 context->shadow_root_level = PT32E_ROOT_LEVEL;
3774 context->direct_map = true;
3775 context->nx = false;
3778 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
3779 union kvm_mmu_page_role role)
3781 return (role.direct || pgd == root->pgd) &&
3782 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
3783 role.word == to_shadow_page(root->hpa)->role.word;
3787 * Find out if a previously cached root matching the new pgd/role is available.
3788 * The current root is also inserted into the cache.
3789 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3791 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3792 * false is returned. This root should now be freed by the caller.
3794 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3795 union kvm_mmu_page_role new_role)
3798 struct kvm_mmu_root_info root;
3799 struct kvm_mmu *mmu = vcpu->arch.mmu;
3801 root.pgd = mmu->root_pgd;
3802 root.hpa = mmu->root_hpa;
3804 if (is_root_usable(&root, new_pgd, new_role))
3807 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3808 swap(root, mmu->prev_roots[i]);
3810 if (is_root_usable(&root, new_pgd, new_role))
3814 mmu->root_hpa = root.hpa;
3815 mmu->root_pgd = root.pgd;
3817 return i < KVM_MMU_NUM_PREV_ROOTS;
3820 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3821 union kvm_mmu_page_role new_role)
3823 struct kvm_mmu *mmu = vcpu->arch.mmu;
3826 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
3827 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
3828 * later if necessary.
3830 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3831 mmu->root_level >= PT64_ROOT_4LEVEL)
3832 return cached_root_available(vcpu, new_pgd, new_role);
3837 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3838 union kvm_mmu_page_role new_role,
3839 bool skip_tlb_flush, bool skip_mmu_sync)
3841 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
3842 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
3847 * It's possible that the cached previous root page is obsolete because
3848 * of a change in the MMU generation number. However, changing the
3849 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
3850 * free the root set here and allocate a new one.
3852 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
3854 if (!skip_mmu_sync || force_flush_and_sync_on_reuse)
3855 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
3856 if (!skip_tlb_flush || force_flush_and_sync_on_reuse)
3857 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3860 * The last MMIO access's GVA and GPA are cached in the VCPU. When
3861 * switching to a new CR3, that GVA->GPA mapping may no longer be
3862 * valid. So clear any cached MMIO info even when we don't need to sync
3863 * the shadow page tables.
3865 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3867 __clear_sp_write_flooding_count(to_shadow_page(vcpu->arch.mmu->root_hpa));
3870 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush,
3873 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu),
3874 skip_tlb_flush, skip_mmu_sync);
3876 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
3878 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3880 return kvm_read_cr3(vcpu);
3883 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3884 unsigned int access, int *nr_present)
3886 if (unlikely(is_mmio_spte(*sptep))) {
3887 if (gfn != get_mmio_spte_gfn(*sptep)) {
3888 mmu_spte_clear_no_track(sptep);
3893 mark_mmio_spte(vcpu, sptep, gfn, access);
3900 static inline bool is_last_gpte(struct kvm_mmu *mmu,
3901 unsigned level, unsigned gpte)
3904 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3905 * If it is clear, there are no large pages at this level, so clear
3906 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3908 gpte &= level - mmu->last_nonleaf_level;
3911 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
3912 * iff level <= PG_LEVEL_4K, which for our purpose means
3913 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
3915 gpte |= level - PG_LEVEL_4K - 1;
3917 return gpte & PT_PAGE_SIZE_MASK;
3920 #define PTTYPE_EPT 18 /* arbitrary */
3921 #define PTTYPE PTTYPE_EPT
3922 #include "paging_tmpl.h"
3926 #include "paging_tmpl.h"
3930 #include "paging_tmpl.h"
3934 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3935 struct rsvd_bits_validate *rsvd_check,
3936 int maxphyaddr, int level, bool nx, bool gbpages,
3939 u64 exb_bit_rsvd = 0;
3940 u64 gbpages_bit_rsvd = 0;
3941 u64 nonleaf_bit8_rsvd = 0;
3943 rsvd_check->bad_mt_xwr = 0;
3946 exb_bit_rsvd = rsvd_bits(63, 63);
3948 gbpages_bit_rsvd = rsvd_bits(7, 7);
3951 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3952 * leaf entries) on AMD CPUs only.
3955 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3958 case PT32_ROOT_LEVEL:
3959 /* no rsvd bits for 2 level 4K page table entries */
3960 rsvd_check->rsvd_bits_mask[0][1] = 0;
3961 rsvd_check->rsvd_bits_mask[0][0] = 0;
3962 rsvd_check->rsvd_bits_mask[1][0] =
3963 rsvd_check->rsvd_bits_mask[0][0];
3966 rsvd_check->rsvd_bits_mask[1][1] = 0;
3970 if (is_cpuid_PSE36())
3971 /* 36bits PSE 4MB page */
3972 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3974 /* 32 bits PSE 4MB page */
3975 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3977 case PT32E_ROOT_LEVEL:
3978 rsvd_check->rsvd_bits_mask[0][2] =
3979 rsvd_bits(maxphyaddr, 63) |
3980 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3981 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3982 rsvd_bits(maxphyaddr, 62); /* PDE */
3983 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3984 rsvd_bits(maxphyaddr, 62); /* PTE */
3985 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3986 rsvd_bits(maxphyaddr, 62) |
3987 rsvd_bits(13, 20); /* large page */
3988 rsvd_check->rsvd_bits_mask[1][0] =
3989 rsvd_check->rsvd_bits_mask[0][0];
3991 case PT64_ROOT_5LEVEL:
3992 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
3993 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3994 rsvd_bits(maxphyaddr, 51);
3995 rsvd_check->rsvd_bits_mask[1][4] =
3996 rsvd_check->rsvd_bits_mask[0][4];
3998 case PT64_ROOT_4LEVEL:
3999 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4000 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4001 rsvd_bits(maxphyaddr, 51);
4002 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
4004 rsvd_bits(maxphyaddr, 51);
4005 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4006 rsvd_bits(maxphyaddr, 51);
4007 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4008 rsvd_bits(maxphyaddr, 51);
4009 rsvd_check->rsvd_bits_mask[1][3] =
4010 rsvd_check->rsvd_bits_mask[0][3];
4011 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
4012 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
4014 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4015 rsvd_bits(maxphyaddr, 51) |
4016 rsvd_bits(13, 20); /* large page */
4017 rsvd_check->rsvd_bits_mask[1][0] =
4018 rsvd_check->rsvd_bits_mask[0][0];
4023 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4024 struct kvm_mmu *context)
4026 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4027 cpuid_maxphyaddr(vcpu), context->root_level,
4029 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4031 guest_cpuid_is_amd_or_hygon(vcpu));
4035 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4036 int maxphyaddr, bool execonly)
4040 rsvd_check->rsvd_bits_mask[0][4] =
4041 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4042 rsvd_check->rsvd_bits_mask[0][3] =
4043 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4044 rsvd_check->rsvd_bits_mask[0][2] =
4045 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4046 rsvd_check->rsvd_bits_mask[0][1] =
4047 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4048 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4051 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4052 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4053 rsvd_check->rsvd_bits_mask[1][2] =
4054 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4055 rsvd_check->rsvd_bits_mask[1][1] =
4056 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4057 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4059 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4060 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4061 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4062 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4063 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4065 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4066 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4068 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4071 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4072 struct kvm_mmu *context, bool execonly)
4074 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4075 cpuid_maxphyaddr(vcpu), execonly);
4079 * the page table on host is the shadow page table for the page
4080 * table in guest or amd nested guest, its mmu features completely
4081 * follow the features in guest.
4084 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4086 bool uses_nx = context->nx ||
4087 context->mmu_role.base.smep_andnot_wp;
4088 struct rsvd_bits_validate *shadow_zero_check;
4092 * Passing "true" to the last argument is okay; it adds a check
4093 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4095 shadow_zero_check = &context->shadow_zero_check;
4096 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4098 context->shadow_root_level, uses_nx,
4099 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4100 is_pse(vcpu), true);
4102 if (!shadow_me_mask)
4105 for (i = context->shadow_root_level; --i >= 0;) {
4106 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4107 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4111 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4113 static inline bool boot_cpu_is_amd(void)
4115 WARN_ON_ONCE(!tdp_enabled);
4116 return shadow_x_mask == 0;
4120 * the direct page table on host, use as much mmu features as
4121 * possible, however, kvm currently does not do execution-protection.
4124 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4125 struct kvm_mmu *context)
4127 struct rsvd_bits_validate *shadow_zero_check;
4130 shadow_zero_check = &context->shadow_zero_check;
4132 if (boot_cpu_is_amd())
4133 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4135 context->shadow_root_level, false,
4136 boot_cpu_has(X86_FEATURE_GBPAGES),
4139 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4143 if (!shadow_me_mask)
4146 for (i = context->shadow_root_level; --i >= 0;) {
4147 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4148 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4153 * as the comments in reset_shadow_zero_bits_mask() except it
4154 * is the shadow page table for intel nested guest.
4157 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4158 struct kvm_mmu *context, bool execonly)
4160 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4161 shadow_phys_bits, execonly);
4164 #define BYTE_MASK(access) \
4165 ((1 & (access) ? 2 : 0) | \
4166 (2 & (access) ? 4 : 0) | \
4167 (3 & (access) ? 8 : 0) | \
4168 (4 & (access) ? 16 : 0) | \
4169 (5 & (access) ? 32 : 0) | \
4170 (6 & (access) ? 64 : 0) | \
4171 (7 & (access) ? 128 : 0))
4174 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4175 struct kvm_mmu *mmu, bool ept)
4179 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4180 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4181 const u8 u = BYTE_MASK(ACC_USER_MASK);
4183 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4184 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4185 bool cr0_wp = is_write_protection(vcpu);
4187 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4188 unsigned pfec = byte << 1;
4191 * Each "*f" variable has a 1 bit for each UWX value
4192 * that causes a fault with the given PFEC.
4195 /* Faults from writes to non-writable pages */
4196 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4197 /* Faults from user mode accesses to supervisor pages */
4198 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4199 /* Faults from fetches of non-executable pages*/
4200 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4201 /* Faults from kernel mode fetches of user pages */
4203 /* Faults from kernel mode accesses of user pages */
4207 /* Faults from kernel mode accesses to user pages */
4208 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4210 /* Not really needed: !nx will cause pte.nx to fault */
4214 /* Allow supervisor writes if !cr0.wp */
4216 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4218 /* Disallow supervisor fetches of user code if cr4.smep */
4220 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4223 * SMAP:kernel-mode data accesses from user-mode
4224 * mappings should fault. A fault is considered
4225 * as a SMAP violation if all of the following
4226 * conditions are true:
4227 * - X86_CR4_SMAP is set in CR4
4228 * - A user page is accessed
4229 * - The access is not a fetch
4230 * - Page fault in kernel mode
4231 * - if CPL = 3 or X86_EFLAGS_AC is clear
4233 * Here, we cover the first three conditions.
4234 * The fourth is computed dynamically in permission_fault();
4235 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4236 * *not* subject to SMAP restrictions.
4239 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4242 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4247 * PKU is an additional mechanism by which the paging controls access to
4248 * user-mode addresses based on the value in the PKRU register. Protection
4249 * key violations are reported through a bit in the page fault error code.
4250 * Unlike other bits of the error code, the PK bit is not known at the
4251 * call site of e.g. gva_to_gpa; it must be computed directly in
4252 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4253 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4255 * In particular the following conditions come from the error code, the
4256 * page tables and the machine state:
4257 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4258 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4259 * - PK is always zero if U=0 in the page tables
4260 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4262 * The PKRU bitmask caches the result of these four conditions. The error
4263 * code (minus the P bit) and the page table's U bit form an index into the
4264 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4265 * with the two bits of the PKRU register corresponding to the protection key.
4266 * For the first three conditions above the bits will be 00, thus masking
4267 * away both AD and WD. For all reads or if the last condition holds, WD
4268 * only will be masked away.
4270 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4281 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4282 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4287 wp = is_write_protection(vcpu);
4289 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4290 unsigned pfec, pkey_bits;
4291 bool check_pkey, check_write, ff, uf, wf, pte_user;
4294 ff = pfec & PFERR_FETCH_MASK;
4295 uf = pfec & PFERR_USER_MASK;
4296 wf = pfec & PFERR_WRITE_MASK;
4298 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4299 pte_user = pfec & PFERR_RSVD_MASK;
4302 * Only need to check the access which is not an
4303 * instruction fetch and is to a user page.
4305 check_pkey = (!ff && pte_user);
4307 * write access is controlled by PKRU if it is a
4308 * user access or CR0.WP = 1.
4310 check_write = check_pkey && wf && (uf || wp);
4312 /* PKRU.AD stops both read and write access. */
4313 pkey_bits = !!check_pkey;
4314 /* PKRU.WD stops write access. */
4315 pkey_bits |= (!!check_write) << 1;
4317 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4321 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4323 unsigned root_level = mmu->root_level;
4325 mmu->last_nonleaf_level = root_level;
4326 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4327 mmu->last_nonleaf_level++;
4330 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4331 struct kvm_mmu *context,
4334 context->nx = is_nx(vcpu);
4335 context->root_level = level;
4337 reset_rsvds_bits_mask(vcpu, context);
4338 update_permission_bitmask(vcpu, context, false);
4339 update_pkru_bitmask(vcpu, context, false);
4340 update_last_nonleaf_level(vcpu, context);
4342 MMU_WARN_ON(!is_pae(vcpu));
4343 context->page_fault = paging64_page_fault;
4344 context->gva_to_gpa = paging64_gva_to_gpa;
4345 context->sync_page = paging64_sync_page;
4346 context->invlpg = paging64_invlpg;
4347 context->update_pte = paging64_update_pte;
4348 context->shadow_root_level = level;
4349 context->direct_map = false;
4352 static void paging64_init_context(struct kvm_vcpu *vcpu,
4353 struct kvm_mmu *context)
4355 int root_level = is_la57_mode(vcpu) ?
4356 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4358 paging64_init_context_common(vcpu, context, root_level);
4361 static void paging32_init_context(struct kvm_vcpu *vcpu,
4362 struct kvm_mmu *context)
4364 context->nx = false;
4365 context->root_level = PT32_ROOT_LEVEL;
4367 reset_rsvds_bits_mask(vcpu, context);
4368 update_permission_bitmask(vcpu, context, false);
4369 update_pkru_bitmask(vcpu, context, false);
4370 update_last_nonleaf_level(vcpu, context);
4372 context->page_fault = paging32_page_fault;
4373 context->gva_to_gpa = paging32_gva_to_gpa;
4374 context->sync_page = paging32_sync_page;
4375 context->invlpg = paging32_invlpg;
4376 context->update_pte = paging32_update_pte;
4377 context->shadow_root_level = PT32E_ROOT_LEVEL;
4378 context->direct_map = false;
4381 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4382 struct kvm_mmu *context)
4384 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4387 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4389 union kvm_mmu_extended_role ext = {0};
4391 ext.cr0_pg = !!is_paging(vcpu);
4392 ext.cr4_pae = !!is_pae(vcpu);
4393 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4394 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4395 ext.cr4_pse = !!is_pse(vcpu);
4396 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4397 ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
4404 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4407 union kvm_mmu_role role = {0};
4409 role.base.access = ACC_ALL;
4410 role.base.nxe = !!is_nx(vcpu);
4411 role.base.cr0_wp = is_write_protection(vcpu);
4412 role.base.smm = is_smm(vcpu);
4413 role.base.guest_mode = is_guest_mode(vcpu);
4418 role.ext = kvm_calc_mmu_role_ext(vcpu);
4423 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4425 /* Use 5-level TDP if and only if it's useful/necessary. */
4426 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4429 return max_tdp_level;
4432 static union kvm_mmu_role
4433 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4435 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4437 role.base.ad_disabled = (shadow_accessed_mask == 0);
4438 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4439 role.base.direct = true;
4440 role.base.gpte_is_8_bytes = true;
4445 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4447 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4448 union kvm_mmu_role new_role =
4449 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
4451 if (new_role.as_u64 == context->mmu_role.as_u64)
4454 context->mmu_role.as_u64 = new_role.as_u64;
4455 context->page_fault = kvm_tdp_page_fault;
4456 context->sync_page = nonpaging_sync_page;
4457 context->invlpg = NULL;
4458 context->update_pte = nonpaging_update_pte;
4459 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4460 context->direct_map = true;
4461 context->get_guest_pgd = get_cr3;
4462 context->get_pdptr = kvm_pdptr_read;
4463 context->inject_page_fault = kvm_inject_page_fault;
4465 if (!is_paging(vcpu)) {
4466 context->nx = false;
4467 context->gva_to_gpa = nonpaging_gva_to_gpa;
4468 context->root_level = 0;
4469 } else if (is_long_mode(vcpu)) {
4470 context->nx = is_nx(vcpu);
4471 context->root_level = is_la57_mode(vcpu) ?
4472 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4473 reset_rsvds_bits_mask(vcpu, context);
4474 context->gva_to_gpa = paging64_gva_to_gpa;
4475 } else if (is_pae(vcpu)) {
4476 context->nx = is_nx(vcpu);
4477 context->root_level = PT32E_ROOT_LEVEL;
4478 reset_rsvds_bits_mask(vcpu, context);
4479 context->gva_to_gpa = paging64_gva_to_gpa;
4481 context->nx = false;
4482 context->root_level = PT32_ROOT_LEVEL;
4483 reset_rsvds_bits_mask(vcpu, context);
4484 context->gva_to_gpa = paging32_gva_to_gpa;
4487 update_permission_bitmask(vcpu, context, false);
4488 update_pkru_bitmask(vcpu, context, false);
4489 update_last_nonleaf_level(vcpu, context);
4490 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4493 static union kvm_mmu_role
4494 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, bool base_only)
4496 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4498 role.base.smep_andnot_wp = role.ext.cr4_smep &&
4499 !is_write_protection(vcpu);
4500 role.base.smap_andnot_wp = role.ext.cr4_smap &&
4501 !is_write_protection(vcpu);
4502 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
4507 static union kvm_mmu_role
4508 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4510 union kvm_mmu_role role =
4511 kvm_calc_shadow_root_page_role_common(vcpu, base_only);
4513 role.base.direct = !is_paging(vcpu);
4515 if (!is_long_mode(vcpu))
4516 role.base.level = PT32E_ROOT_LEVEL;
4517 else if (is_la57_mode(vcpu))
4518 role.base.level = PT64_ROOT_5LEVEL;
4520 role.base.level = PT64_ROOT_4LEVEL;
4525 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4526 u32 cr0, u32 cr4, u32 efer,
4527 union kvm_mmu_role new_role)
4529 if (!(cr0 & X86_CR0_PG))
4530 nonpaging_init_context(vcpu, context);
4531 else if (efer & EFER_LMA)
4532 paging64_init_context(vcpu, context);
4533 else if (cr4 & X86_CR4_PAE)
4534 paging32E_init_context(vcpu, context);
4536 paging32_init_context(vcpu, context);
4538 context->mmu_role.as_u64 = new_role.as_u64;
4539 reset_shadow_zero_bits_mask(vcpu, context);
4542 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer)
4544 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4545 union kvm_mmu_role new_role =
4546 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4548 if (new_role.as_u64 != context->mmu_role.as_u64)
4549 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4552 static union kvm_mmu_role
4553 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu)
4555 union kvm_mmu_role role =
4556 kvm_calc_shadow_root_page_role_common(vcpu, false);
4558 role.base.direct = false;
4559 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4564 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer,
4567 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4568 union kvm_mmu_role new_role = kvm_calc_shadow_npt_root_page_role(vcpu);
4570 context->shadow_root_level = new_role.base.level;
4572 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base, false, false);
4574 if (new_role.as_u64 != context->mmu_role.as_u64)
4575 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4577 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4579 static union kvm_mmu_role
4580 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4581 bool execonly, u8 level)
4583 union kvm_mmu_role role = {0};
4585 /* SMM flag is inherited from root_mmu */
4586 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4588 role.base.level = level;
4589 role.base.gpte_is_8_bytes = true;
4590 role.base.direct = false;
4591 role.base.ad_disabled = !accessed_dirty;
4592 role.base.guest_mode = true;
4593 role.base.access = ACC_ALL;
4596 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
4597 * SMAP variation to denote shadow EPT entries.
4599 role.base.cr0_wp = true;
4600 role.base.smap_andnot_wp = true;
4602 role.ext = kvm_calc_mmu_role_ext(vcpu);
4603 role.ext.execonly = execonly;
4608 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4609 bool accessed_dirty, gpa_t new_eptp)
4611 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4612 u8 level = vmx_eptp_page_walk_level(new_eptp);
4613 union kvm_mmu_role new_role =
4614 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4617 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base, true, true);
4619 if (new_role.as_u64 == context->mmu_role.as_u64)
4622 context->shadow_root_level = level;
4625 context->ept_ad = accessed_dirty;
4626 context->page_fault = ept_page_fault;
4627 context->gva_to_gpa = ept_gva_to_gpa;
4628 context->sync_page = ept_sync_page;
4629 context->invlpg = ept_invlpg;
4630 context->update_pte = ept_update_pte;
4631 context->root_level = level;
4632 context->direct_map = false;
4633 context->mmu_role.as_u64 = new_role.as_u64;
4635 update_permission_bitmask(vcpu, context, true);
4636 update_pkru_bitmask(vcpu, context, true);
4637 update_last_nonleaf_level(vcpu, context);
4638 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4639 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4641 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4643 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4645 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4647 kvm_init_shadow_mmu(vcpu,
4648 kvm_read_cr0_bits(vcpu, X86_CR0_PG),
4649 kvm_read_cr4_bits(vcpu, X86_CR4_PAE),
4652 context->get_guest_pgd = get_cr3;
4653 context->get_pdptr = kvm_pdptr_read;
4654 context->inject_page_fault = kvm_inject_page_fault;
4657 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4659 union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false);
4660 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4662 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4665 g_context->mmu_role.as_u64 = new_role.as_u64;
4666 g_context->get_guest_pgd = get_cr3;
4667 g_context->get_pdptr = kvm_pdptr_read;
4668 g_context->inject_page_fault = kvm_inject_page_fault;
4671 * L2 page tables are never shadowed, so there is no need to sync
4674 g_context->invlpg = NULL;
4677 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4678 * L1's nested page tables (e.g. EPT12). The nested translation
4679 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4680 * L2's page tables as the first level of translation and L1's
4681 * nested page tables as the second level of translation. Basically
4682 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4684 if (!is_paging(vcpu)) {
4685 g_context->nx = false;
4686 g_context->root_level = 0;
4687 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4688 } else if (is_long_mode(vcpu)) {
4689 g_context->nx = is_nx(vcpu);
4690 g_context->root_level = is_la57_mode(vcpu) ?
4691 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4692 reset_rsvds_bits_mask(vcpu, g_context);
4693 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4694 } else if (is_pae(vcpu)) {
4695 g_context->nx = is_nx(vcpu);
4696 g_context->root_level = PT32E_ROOT_LEVEL;
4697 reset_rsvds_bits_mask(vcpu, g_context);
4698 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4700 g_context->nx = false;
4701 g_context->root_level = PT32_ROOT_LEVEL;
4702 reset_rsvds_bits_mask(vcpu, g_context);
4703 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4706 update_permission_bitmask(vcpu, g_context, false);
4707 update_pkru_bitmask(vcpu, g_context, false);
4708 update_last_nonleaf_level(vcpu, g_context);
4711 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
4716 vcpu->arch.mmu->root_hpa = INVALID_PAGE;
4718 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
4719 vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
4722 if (mmu_is_nested(vcpu))
4723 init_kvm_nested_mmu(vcpu);
4724 else if (tdp_enabled)
4725 init_kvm_tdp_mmu(vcpu);
4727 init_kvm_softmmu(vcpu);
4729 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4731 static union kvm_mmu_page_role
4732 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4734 union kvm_mmu_role role;
4737 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
4739 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
4744 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4746 kvm_mmu_unload(vcpu);
4747 kvm_init_mmu(vcpu, true);
4749 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4751 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4755 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
4758 r = mmu_alloc_roots(vcpu);
4759 kvm_mmu_sync_roots(vcpu);
4762 kvm_mmu_load_pgd(vcpu);
4763 kvm_x86_ops.tlb_flush_current(vcpu);
4767 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4769 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4771 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
4772 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
4773 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4774 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
4776 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4778 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4779 struct kvm_mmu_page *sp, u64 *spte,
4782 if (sp->role.level != PG_LEVEL_4K) {
4783 ++vcpu->kvm->stat.mmu_pde_zapped;
4787 ++vcpu->kvm->stat.mmu_pte_updated;
4788 vcpu->arch.mmu->update_pte(vcpu, sp, spte, new);
4791 static bool need_remote_flush(u64 old, u64 new)
4793 if (!is_shadow_present_pte(old))
4795 if (!is_shadow_present_pte(new))
4797 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4799 old ^= shadow_nx_mask;
4800 new ^= shadow_nx_mask;
4801 return (old & ~new & PT64_PERM_MASK) != 0;
4804 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4811 * Assume that the pte write on a page table of the same type
4812 * as the current vcpu paging mode since we update the sptes only
4813 * when they have the same mode.
4815 if (is_pae(vcpu) && *bytes == 4) {
4816 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4821 if (*bytes == 4 || *bytes == 8) {
4822 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
4831 * If we're seeing too many writes to a page, it may no longer be a page table,
4832 * or we may be forking, in which case it is better to unmap the page.
4834 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4837 * Skip write-flooding detected for the sp whose level is 1, because
4838 * it can become unsync, then the guest page is not write-protected.
4840 if (sp->role.level == PG_LEVEL_4K)
4843 atomic_inc(&sp->write_flooding_count);
4844 return atomic_read(&sp->write_flooding_count) >= 3;
4848 * Misaligned accesses are too much trouble to fix up; also, they usually
4849 * indicate a page is not used as a page table.
4851 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4854 unsigned offset, pte_size, misaligned;
4856 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4857 gpa, bytes, sp->role.word);
4859 offset = offset_in_page(gpa);
4860 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
4863 * Sometimes, the OS only writes the last one bytes to update status
4864 * bits, for example, in linux, andb instruction is used in clear_bit().
4866 if (!(offset & (pte_size - 1)) && bytes == 1)
4869 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4870 misaligned |= bytes < 4;
4875 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4877 unsigned page_offset, quadrant;
4881 page_offset = offset_in_page(gpa);
4882 level = sp->role.level;
4884 if (!sp->role.gpte_is_8_bytes) {
4885 page_offset <<= 1; /* 32->64 */
4887 * A 32-bit pde maps 4MB while the shadow pdes map
4888 * only 2MB. So we need to double the offset again
4889 * and zap two pdes instead of one.
4891 if (level == PT32_ROOT_LEVEL) {
4892 page_offset &= ~7; /* kill rounding error */
4896 quadrant = page_offset >> PAGE_SHIFT;
4897 page_offset &= ~PAGE_MASK;
4898 if (quadrant != sp->role.quadrant)
4902 spte = &sp->spt[page_offset / sizeof(*spte)];
4907 * Ignore various flags when determining if a SPTE can be immediately
4908 * overwritten for the current MMU.
4909 * - level: explicitly checked in mmu_pte_write_new_pte(), and will never
4910 * match the current MMU role, as MMU's level tracks the root level.
4911 * - access: updated based on the new guest PTE
4912 * - quadrant: handled by get_written_sptes()
4913 * - invalid: always false (loop only walks valid shadow pages)
4915 static const union kvm_mmu_page_role role_ign = {
4922 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4923 const u8 *new, int bytes,
4924 struct kvm_page_track_notifier_node *node)
4926 gfn_t gfn = gpa >> PAGE_SHIFT;
4927 struct kvm_mmu_page *sp;
4928 LIST_HEAD(invalid_list);
4929 u64 entry, gentry, *spte;
4931 bool remote_flush, local_flush;
4934 * If we don't have indirect shadow pages, it means no page is
4935 * write-protected, so we can exit simply.
4937 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4940 remote_flush = local_flush = false;
4942 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4945 * No need to care whether allocation memory is successful
4946 * or not since pte prefetch is skiped if it does not have
4947 * enough objects in the cache.
4949 mmu_topup_memory_caches(vcpu, true);
4951 spin_lock(&vcpu->kvm->mmu_lock);
4953 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
4955 ++vcpu->kvm->stat.mmu_pte_write;
4956 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4958 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4959 if (detect_write_misaligned(sp, gpa, bytes) ||
4960 detect_write_flooding(sp)) {
4961 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4962 ++vcpu->kvm->stat.mmu_flooded;
4966 spte = get_written_sptes(sp, gpa, &npte);
4972 u32 base_role = vcpu->arch.mmu->mmu_role.base.word;
4975 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
4977 !((sp->role.word ^ base_role) & ~role_ign.word) &&
4979 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4980 if (need_remote_flush(entry, *spte))
4981 remote_flush = true;
4985 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
4986 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4987 spin_unlock(&vcpu->kvm->mmu_lock);
4990 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4995 if (vcpu->arch.mmu->direct_map)
4998 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
5000 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
5004 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
5006 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5007 void *insn, int insn_len)
5009 int r, emulation_type = EMULTYPE_PF;
5010 bool direct = vcpu->arch.mmu->direct_map;
5012 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5013 return RET_PF_RETRY;
5016 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5017 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5018 if (r == RET_PF_EMULATE)
5022 if (r == RET_PF_INVALID) {
5023 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5024 lower_32_bits(error_code), false);
5025 if (WARN_ON_ONCE(r == RET_PF_INVALID))
5031 if (r != RET_PF_EMULATE)
5035 * Before emulating the instruction, check if the error code
5036 * was due to a RO violation while translating the guest page.
5037 * This can occur when using nested virtualization with nested
5038 * paging in both guests. If true, we simply unprotect the page
5039 * and resume the guest.
5041 if (vcpu->arch.mmu->direct_map &&
5042 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5043 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5048 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5049 * optimistically try to just unprotect the page and let the processor
5050 * re-execute the instruction that caused the page fault. Do not allow
5051 * retrying MMIO emulation, as it's not only pointless but could also
5052 * cause us to enter an infinite loop because the processor will keep
5053 * faulting on the non-existent MMIO address. Retrying an instruction
5054 * from a nested guest is also pointless and dangerous as we are only
5055 * explicitly shadowing L1's page tables, i.e. unprotecting something
5056 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5058 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5059 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5061 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5064 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5066 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5067 gva_t gva, hpa_t root_hpa)
5071 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5072 if (mmu != &vcpu->arch.guest_mmu) {
5073 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5074 if (is_noncanonical_address(gva, vcpu))
5077 kvm_x86_ops.tlb_flush_gva(vcpu, gva);
5083 if (root_hpa == INVALID_PAGE) {
5084 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5087 * INVLPG is required to invalidate any global mappings for the VA,
5088 * irrespective of PCID. Since it would take us roughly similar amount
5089 * of work to determine whether any of the prev_root mappings of the VA
5090 * is marked global, or to just sync it blindly, so we might as well
5091 * just always sync it.
5093 * Mappings not reachable via the current cr3 or the prev_roots will be
5094 * synced when switching to that cr3, so nothing needs to be done here
5097 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5098 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5099 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5101 mmu->invlpg(vcpu, gva, root_hpa);
5104 EXPORT_SYMBOL_GPL(kvm_mmu_invalidate_gva);
5106 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5108 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
5109 ++vcpu->stat.invlpg;
5111 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5114 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5116 struct kvm_mmu *mmu = vcpu->arch.mmu;
5117 bool tlb_flush = false;
5120 if (pcid == kvm_get_active_pcid(vcpu)) {
5121 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5125 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5126 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5127 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5128 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5134 kvm_x86_ops.tlb_flush_gva(vcpu, gva);
5136 ++vcpu->stat.invlpg;
5139 * Mappings not reachable via the current cr3 or the prev_roots will be
5140 * synced when switching to that cr3, so nothing needs to be done here
5144 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva);
5146 void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
5147 int tdp_huge_page_level)
5149 tdp_enabled = enable_tdp;
5150 max_tdp_level = tdp_max_root_level;
5153 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5154 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5155 * the kernel is not. But, KVM never creates a page size greater than
5156 * what is used by the kernel for any given HVA, i.e. the kernel's
5157 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5160 max_huge_page_level = tdp_huge_page_level;
5161 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5162 max_huge_page_level = PG_LEVEL_1G;
5164 max_huge_page_level = PG_LEVEL_2M;
5166 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5168 /* The return value indicates if tlb flush on all vcpus is needed. */
5169 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5171 /* The caller should hold mmu-lock before calling this function. */
5172 static __always_inline bool
5173 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5174 slot_level_handler fn, int start_level, int end_level,
5175 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5177 struct slot_rmap_walk_iterator iterator;
5180 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5181 end_gfn, &iterator) {
5183 flush |= fn(kvm, iterator.rmap);
5185 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5186 if (flush && lock_flush_tlb) {
5187 kvm_flush_remote_tlbs_with_address(kvm,
5189 iterator.gfn - start_gfn + 1);
5192 cond_resched_lock(&kvm->mmu_lock);
5196 if (flush && lock_flush_tlb) {
5197 kvm_flush_remote_tlbs_with_address(kvm, start_gfn,
5198 end_gfn - start_gfn + 1);
5205 static __always_inline bool
5206 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5207 slot_level_handler fn, int start_level, int end_level,
5208 bool lock_flush_tlb)
5210 return slot_handle_level_range(kvm, memslot, fn, start_level,
5211 end_level, memslot->base_gfn,
5212 memslot->base_gfn + memslot->npages - 1,
5216 static __always_inline bool
5217 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5218 slot_level_handler fn, bool lock_flush_tlb)
5220 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5221 KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5224 static __always_inline bool
5225 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5226 slot_level_handler fn, bool lock_flush_tlb)
5228 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K + 1,
5229 KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5232 static __always_inline bool
5233 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5234 slot_level_handler fn, bool lock_flush_tlb)
5236 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5237 PG_LEVEL_4K, lock_flush_tlb);
5240 static void free_mmu_pages(struct kvm_mmu *mmu)
5242 free_page((unsigned long)mmu->pae_root);
5243 free_page((unsigned long)mmu->lm_root);
5246 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5251 mmu->root_hpa = INVALID_PAGE;
5253 mmu->translate_gpa = translate_gpa;
5254 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5255 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5258 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5259 * while the PDP table is a per-vCPU construct that's allocated at MMU
5260 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5261 * x86_64. Therefore we need to allocate the PDP table in the first
5262 * 4GB of memory, which happens to fit the DMA32 zone. Except for
5263 * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can
5264 * skip allocating the PDP table.
5266 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5269 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5273 mmu->pae_root = page_address(page);
5274 for (i = 0; i < 4; ++i)
5275 mmu->pae_root[i] = INVALID_PAGE;
5280 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5284 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5285 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5287 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5288 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5290 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5292 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5293 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5295 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5297 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5301 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5303 goto fail_allocate_root;
5307 free_mmu_pages(&vcpu->arch.guest_mmu);
5311 #define BATCH_ZAP_PAGES 10
5312 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5314 struct kvm_mmu_page *sp, *node;
5315 int nr_zapped, batch = 0;
5318 list_for_each_entry_safe_reverse(sp, node,
5319 &kvm->arch.active_mmu_pages, link) {
5321 * No obsolete valid page exists before a newly created page
5322 * since active_mmu_pages is a FIFO list.
5324 if (!is_obsolete_sp(kvm, sp))
5328 * Invalid pages should never land back on the list of active
5329 * pages. Skip the bogus page, otherwise we'll get stuck in an
5330 * infinite loop if the page gets put back on the list (again).
5332 if (WARN_ON(sp->role.invalid))
5336 * No need to flush the TLB since we're only zapping shadow
5337 * pages with an obsolete generation number and all vCPUS have
5338 * loaded a new root, i.e. the shadow pages being zapped cannot
5339 * be in active use by the guest.
5341 if (batch >= BATCH_ZAP_PAGES &&
5342 cond_resched_lock(&kvm->mmu_lock)) {
5347 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5348 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5355 * Trigger a remote TLB flush before freeing the page tables to ensure
5356 * KVM is not in the middle of a lockless shadow page table walk, which
5357 * may reference the pages.
5359 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5363 * Fast invalidate all shadow pages and use lock-break technique
5364 * to zap obsolete pages.
5366 * It's required when memslot is being deleted or VM is being
5367 * destroyed, in these cases, we should ensure that KVM MMU does
5368 * not use any resource of the being-deleted slot or all slots
5369 * after calling the function.
5371 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5373 lockdep_assert_held(&kvm->slots_lock);
5375 spin_lock(&kvm->mmu_lock);
5376 trace_kvm_mmu_zap_all_fast(kvm);
5379 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5380 * held for the entire duration of zapping obsolete pages, it's
5381 * impossible for there to be multiple invalid generations associated
5382 * with *valid* shadow pages at any given time, i.e. there is exactly
5383 * one valid generation and (at most) one invalid generation.
5385 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5388 * Notify all vcpus to reload its shadow page table and flush TLB.
5389 * Then all vcpus will switch to new shadow page table with the new
5392 * Note: we need to do this under the protection of mmu_lock,
5393 * otherwise, vcpu would purge shadow page but miss tlb flush.
5395 kvm_reload_remote_mmus(kvm);
5397 kvm_zap_obsolete_pages(kvm);
5399 if (kvm->arch.tdp_mmu_enabled)
5400 kvm_tdp_mmu_zap_all(kvm);
5402 spin_unlock(&kvm->mmu_lock);
5405 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5407 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5410 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5411 struct kvm_memory_slot *slot,
5412 struct kvm_page_track_notifier_node *node)
5414 kvm_mmu_zap_all_fast(kvm);
5417 void kvm_mmu_init_vm(struct kvm *kvm)
5419 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5421 kvm_mmu_init_tdp_mmu(kvm);
5423 node->track_write = kvm_mmu_pte_write;
5424 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5425 kvm_page_track_register_notifier(kvm, node);
5428 void kvm_mmu_uninit_vm(struct kvm *kvm)
5430 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5432 kvm_page_track_unregister_notifier(kvm, node);
5434 kvm_mmu_uninit_tdp_mmu(kvm);
5437 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5439 struct kvm_memslots *slots;
5440 struct kvm_memory_slot *memslot;
5444 spin_lock(&kvm->mmu_lock);
5445 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5446 slots = __kvm_memslots(kvm, i);
5447 kvm_for_each_memslot(memslot, slots) {
5450 start = max(gfn_start, memslot->base_gfn);
5451 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5455 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5457 KVM_MAX_HUGEPAGE_LEVEL,
5458 start, end - 1, true);
5462 if (kvm->arch.tdp_mmu_enabled) {
5463 flush = kvm_tdp_mmu_zap_gfn_range(kvm, gfn_start, gfn_end);
5465 kvm_flush_remote_tlbs(kvm);
5468 spin_unlock(&kvm->mmu_lock);
5471 static bool slot_rmap_write_protect(struct kvm *kvm,
5472 struct kvm_rmap_head *rmap_head)
5474 return __rmap_write_protect(kvm, rmap_head, false);
5477 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5478 struct kvm_memory_slot *memslot,
5483 spin_lock(&kvm->mmu_lock);
5484 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5485 start_level, KVM_MAX_HUGEPAGE_LEVEL, false);
5486 if (kvm->arch.tdp_mmu_enabled)
5487 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, PG_LEVEL_4K);
5488 spin_unlock(&kvm->mmu_lock);
5491 * We can flush all the TLBs out of the mmu lock without TLB
5492 * corruption since we just change the spte from writable to
5493 * readonly so that we only need to care the case of changing
5494 * spte from present to present (changing the spte from present
5495 * to nonpresent will flush all the TLBs immediately), in other
5496 * words, the only case we care is mmu_spte_update() where we
5497 * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5498 * instead of PT_WRITABLE_MASK, that means it does not depend
5499 * on PT_WRITABLE_MASK anymore.
5502 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5505 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5506 struct kvm_rmap_head *rmap_head)
5509 struct rmap_iterator iter;
5510 int need_tlb_flush = 0;
5512 struct kvm_mmu_page *sp;
5515 for_each_rmap_spte(rmap_head, &iter, sptep) {
5516 sp = sptep_to_sp(sptep);
5517 pfn = spte_to_pfn(*sptep);
5520 * We cannot do huge page mapping for indirect shadow pages,
5521 * which are found on the last rmap (level = 1) when not using
5522 * tdp; such shadow pages are synced with the page table in
5523 * the guest, and the guest page table is using 4K page size
5524 * mapping if the indirect sp has level = 1.
5526 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5527 (kvm_is_zone_device_pfn(pfn) ||
5528 PageCompound(pfn_to_page(pfn)))) {
5529 pte_list_remove(rmap_head, sptep);
5531 if (kvm_available_flush_tlb_with_range())
5532 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5533 KVM_PAGES_PER_HPAGE(sp->role.level));
5541 return need_tlb_flush;
5544 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5545 const struct kvm_memory_slot *memslot)
5547 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5548 spin_lock(&kvm->mmu_lock);
5549 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5550 kvm_mmu_zap_collapsible_spte, true);
5552 if (kvm->arch.tdp_mmu_enabled)
5553 kvm_tdp_mmu_zap_collapsible_sptes(kvm, memslot);
5554 spin_unlock(&kvm->mmu_lock);
5557 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5558 struct kvm_memory_slot *memslot)
5561 * All current use cases for flushing the TLBs for a specific memslot
5562 * are related to dirty logging, and do the TLB flush out of mmu_lock.
5563 * The interaction between the various operations on memslot must be
5564 * serialized by slots_locks to ensure the TLB flush from one operation
5565 * is observed by any other operation on the same memslot.
5567 lockdep_assert_held(&kvm->slots_lock);
5568 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5572 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5573 struct kvm_memory_slot *memslot)
5577 spin_lock(&kvm->mmu_lock);
5578 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5579 if (kvm->arch.tdp_mmu_enabled)
5580 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5581 spin_unlock(&kvm->mmu_lock);
5584 * It's also safe to flush TLBs out of mmu lock here as currently this
5585 * function is only used for dirty logging, in which case flushing TLB
5586 * out of mmu lock also guarantees no dirty pages will be lost in
5590 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5592 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5594 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5595 struct kvm_memory_slot *memslot)
5599 spin_lock(&kvm->mmu_lock);
5600 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5602 if (kvm->arch.tdp_mmu_enabled)
5603 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, PG_LEVEL_2M);
5604 spin_unlock(&kvm->mmu_lock);
5607 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5609 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5611 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5612 struct kvm_memory_slot *memslot)
5616 spin_lock(&kvm->mmu_lock);
5617 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
5618 if (kvm->arch.tdp_mmu_enabled)
5619 flush |= kvm_tdp_mmu_slot_set_dirty(kvm, memslot);
5620 spin_unlock(&kvm->mmu_lock);
5623 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5625 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5627 void kvm_mmu_zap_all(struct kvm *kvm)
5629 struct kvm_mmu_page *sp, *node;
5630 LIST_HEAD(invalid_list);
5633 spin_lock(&kvm->mmu_lock);
5635 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5636 if (WARN_ON(sp->role.invalid))
5638 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5640 if (cond_resched_lock(&kvm->mmu_lock))
5644 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5646 if (kvm->arch.tdp_mmu_enabled)
5647 kvm_tdp_mmu_zap_all(kvm);
5649 spin_unlock(&kvm->mmu_lock);
5652 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5654 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5656 gen &= MMIO_SPTE_GEN_MASK;
5659 * Generation numbers are incremented in multiples of the number of
5660 * address spaces in order to provide unique generations across all
5661 * address spaces. Strip what is effectively the address space
5662 * modifier prior to checking for a wrap of the MMIO generation so
5663 * that a wrap in any address space is detected.
5665 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5668 * The very rare case: if the MMIO generation number has wrapped,
5669 * zap all shadow pages.
5671 if (unlikely(gen == 0)) {
5672 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5673 kvm_mmu_zap_all_fast(kvm);
5677 static unsigned long
5678 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5681 int nr_to_scan = sc->nr_to_scan;
5682 unsigned long freed = 0;
5684 mutex_lock(&kvm_lock);
5686 list_for_each_entry(kvm, &vm_list, vm_list) {
5688 LIST_HEAD(invalid_list);
5691 * Never scan more than sc->nr_to_scan VM instances.
5692 * Will not hit this condition practically since we do not try
5693 * to shrink more than one VM and it is very unlikely to see
5694 * !n_used_mmu_pages so many times.
5699 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5700 * here. We may skip a VM instance errorneosly, but we do not
5701 * want to shrink a VM that only started to populate its MMU
5704 if (!kvm->arch.n_used_mmu_pages &&
5705 !kvm_has_zapped_obsolete_pages(kvm))
5708 idx = srcu_read_lock(&kvm->srcu);
5709 spin_lock(&kvm->mmu_lock);
5711 if (kvm_has_zapped_obsolete_pages(kvm)) {
5712 kvm_mmu_commit_zap_page(kvm,
5713 &kvm->arch.zapped_obsolete_pages);
5717 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
5720 spin_unlock(&kvm->mmu_lock);
5721 srcu_read_unlock(&kvm->srcu, idx);
5724 * unfair on small ones
5725 * per-vm shrinkers cry out
5726 * sadness comes quickly
5728 list_move_tail(&kvm->vm_list, &vm_list);
5732 mutex_unlock(&kvm_lock);
5736 static unsigned long
5737 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5739 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5742 static struct shrinker mmu_shrinker = {
5743 .count_objects = mmu_shrink_count,
5744 .scan_objects = mmu_shrink_scan,
5745 .seeks = DEFAULT_SEEKS * 10,
5748 static void mmu_destroy_caches(void)
5750 kmem_cache_destroy(pte_list_desc_cache);
5751 kmem_cache_destroy(mmu_page_header_cache);
5754 static void kvm_set_mmio_spte_mask(void)
5759 * Set a reserved PA bit in MMIO SPTEs to generate page faults with
5760 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT
5761 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports
5762 * 52-bit physical addresses then there are no reserved PA bits in the
5763 * PTEs and so the reserved PA approach must be disabled.
5765 if (shadow_phys_bits < 52)
5766 mask = BIT_ULL(51) | PT_PRESENT_MASK;
5770 kvm_mmu_set_mmio_spte_mask(mask, ACC_WRITE_MASK | ACC_USER_MASK);
5773 static bool get_nx_auto_mode(void)
5775 /* Return true when CPU has the bug, and mitigations are ON */
5776 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5779 static void __set_nx_huge_pages(bool val)
5781 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5784 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5786 bool old_val = nx_huge_pages;
5789 /* In "auto" mode deploy workaround only if CPU has the bug. */
5790 if (sysfs_streq(val, "off"))
5792 else if (sysfs_streq(val, "force"))
5794 else if (sysfs_streq(val, "auto"))
5795 new_val = get_nx_auto_mode();
5796 else if (strtobool(val, &new_val) < 0)
5799 __set_nx_huge_pages(new_val);
5801 if (new_val != old_val) {
5804 mutex_lock(&kvm_lock);
5806 list_for_each_entry(kvm, &vm_list, vm_list) {
5807 mutex_lock(&kvm->slots_lock);
5808 kvm_mmu_zap_all_fast(kvm);
5809 mutex_unlock(&kvm->slots_lock);
5811 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5813 mutex_unlock(&kvm_lock);
5819 int kvm_mmu_module_init(void)
5823 if (nx_huge_pages == -1)
5824 __set_nx_huge_pages(get_nx_auto_mode());
5827 * MMU roles use union aliasing which is, generally speaking, an
5828 * undefined behavior. However, we supposedly know how compilers behave
5829 * and the current status quo is unlikely to change. Guardians below are
5830 * supposed to let us know if the assumption becomes false.
5832 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
5833 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
5834 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
5836 kvm_mmu_reset_all_pte_masks();
5838 kvm_set_mmio_spte_mask();
5840 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5841 sizeof(struct pte_list_desc),
5842 0, SLAB_ACCOUNT, NULL);
5843 if (!pte_list_desc_cache)
5846 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5847 sizeof(struct kvm_mmu_page),
5848 0, SLAB_ACCOUNT, NULL);
5849 if (!mmu_page_header_cache)
5852 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5855 ret = register_shrinker(&mmu_shrinker);
5862 mmu_destroy_caches();
5867 * Calculate mmu pages needed for kvm.
5869 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
5871 unsigned long nr_mmu_pages;
5872 unsigned long nr_pages = 0;
5873 struct kvm_memslots *slots;
5874 struct kvm_memory_slot *memslot;
5877 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5878 slots = __kvm_memslots(kvm, i);
5880 kvm_for_each_memslot(memslot, slots)
5881 nr_pages += memslot->npages;
5884 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5885 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
5887 return nr_mmu_pages;
5890 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5892 kvm_mmu_unload(vcpu);
5893 free_mmu_pages(&vcpu->arch.root_mmu);
5894 free_mmu_pages(&vcpu->arch.guest_mmu);
5895 mmu_free_memory_caches(vcpu);
5898 void kvm_mmu_module_exit(void)
5900 mmu_destroy_caches();
5901 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5902 unregister_shrinker(&mmu_shrinker);
5903 mmu_audit_disable();
5906 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
5908 unsigned int old_val;
5911 old_val = nx_huge_pages_recovery_ratio;
5912 err = param_set_uint(val, kp);
5916 if (READ_ONCE(nx_huge_pages) &&
5917 !old_val && nx_huge_pages_recovery_ratio) {
5920 mutex_lock(&kvm_lock);
5922 list_for_each_entry(kvm, &vm_list, vm_list)
5923 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5925 mutex_unlock(&kvm_lock);
5931 static void kvm_recover_nx_lpages(struct kvm *kvm)
5934 struct kvm_mmu_page *sp;
5936 LIST_HEAD(invalid_list);
5939 rcu_idx = srcu_read_lock(&kvm->srcu);
5940 spin_lock(&kvm->mmu_lock);
5942 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
5943 to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0;
5944 for ( ; to_zap; --to_zap) {
5945 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
5949 * We use a separate list instead of just using active_mmu_pages
5950 * because the number of lpage_disallowed pages is expected to
5951 * be relatively small compared to the total.
5953 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
5954 struct kvm_mmu_page,
5955 lpage_disallowed_link);
5956 WARN_ON_ONCE(!sp->lpage_disallowed);
5957 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
5958 WARN_ON_ONCE(sp->lpage_disallowed);
5960 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5961 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5962 cond_resched_lock(&kvm->mmu_lock);
5965 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5967 spin_unlock(&kvm->mmu_lock);
5968 srcu_read_unlock(&kvm->srcu, rcu_idx);
5971 static long get_nx_lpage_recovery_timeout(u64 start_time)
5973 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
5974 ? start_time + 60 * HZ - get_jiffies_64()
5975 : MAX_SCHEDULE_TIMEOUT;
5978 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
5981 long remaining_time;
5984 start_time = get_jiffies_64();
5985 remaining_time = get_nx_lpage_recovery_timeout(start_time);
5987 set_current_state(TASK_INTERRUPTIBLE);
5988 while (!kthread_should_stop() && remaining_time > 0) {
5989 schedule_timeout(remaining_time);
5990 remaining_time = get_nx_lpage_recovery_timeout(start_time);
5991 set_current_state(TASK_INTERRUPTIBLE);
5994 set_current_state(TASK_RUNNING);
5996 if (kthread_should_stop())
5999 kvm_recover_nx_lpages(kvm);
6003 int kvm_mmu_post_init_vm(struct kvm *kvm)
6007 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6008 "kvm-nx-lpage-recovery",
6009 &kvm->arch.nx_lpage_recovery_thread);
6011 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6016 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6018 if (kvm->arch.nx_lpage_recovery_thread)
6019 kthread_stop(kvm->arch.nx_lpage_recovery_thread);