1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
51 #include <asm/set_memory.h>
53 #include <asm/kvm_page_track.h>
58 extern bool itlb_multihit_kvm_mitigation;
60 int __read_mostly nx_huge_pages = -1;
61 #ifdef CONFIG_PREEMPT_RT
62 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
63 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
65 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
68 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
69 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
71 static const struct kernel_param_ops nx_huge_pages_ops = {
72 .set = set_nx_huge_pages,
73 .get = param_get_bool,
76 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
77 .set = set_nx_huge_pages_recovery_ratio,
78 .get = param_get_uint,
81 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
82 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
83 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
84 &nx_huge_pages_recovery_ratio, 0644);
85 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
87 static bool __read_mostly force_flush_and_sync_on_reuse;
88 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
91 * When setting this variable to true it enables Two-Dimensional-Paging
92 * where the hardware walks 2 page tables:
93 * 1. the guest-virtual to guest-physical
94 * 2. while doing 1. it walks guest-physical to host-physical
95 * If the hardware supports that we don't need to do shadow paging.
97 bool tdp_enabled = false;
99 static int max_huge_page_level __read_mostly;
100 static int max_tdp_level __read_mostly;
103 AUDIT_PRE_PAGE_FAULT,
104 AUDIT_POST_PAGE_FAULT,
106 AUDIT_POST_PTE_WRITE,
113 module_param(dbg, bool, 0644);
116 #define PTE_PREFETCH_NUM 8
118 #define PT32_LEVEL_BITS 10
120 #define PT32_LEVEL_SHIFT(level) \
121 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
123 #define PT32_LVL_OFFSET_MASK(level) \
124 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
125 * PT32_LEVEL_BITS))) - 1))
127 #define PT32_INDEX(address, level)\
128 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
131 #define PT32_BASE_ADDR_MASK PAGE_MASK
132 #define PT32_DIR_BASE_ADDR_MASK \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
134 #define PT32_LVL_ADDR_MASK(level) \
135 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
136 * PT32_LEVEL_BITS))) - 1))
138 #include <trace/events/kvm.h>
140 /* make pte_list_desc fit well in cache line */
141 #define PTE_LIST_EXT 3
143 struct pte_list_desc {
144 u64 *sptes[PTE_LIST_EXT];
145 struct pte_list_desc *more;
148 struct kvm_shadow_walk_iterator {
156 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
157 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
159 shadow_walk_okay(&(_walker)); \
160 shadow_walk_next(&(_walker)))
162 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
163 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
164 shadow_walk_okay(&(_walker)); \
165 shadow_walk_next(&(_walker)))
167 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
168 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
169 shadow_walk_okay(&(_walker)) && \
170 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
171 __shadow_walk_next(&(_walker), spte))
173 static struct kmem_cache *pte_list_desc_cache;
174 struct kmem_cache *mmu_page_header_cache;
175 static struct percpu_counter kvm_total_used_mmu_pages;
177 static void mmu_spte_set(u64 *sptep, u64 spte);
178 static union kvm_mmu_page_role
179 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
181 struct kvm_mmu_role_regs {
182 const unsigned long cr0;
183 const unsigned long cr4;
187 #define CREATE_TRACE_POINTS
188 #include "mmutrace.h"
191 * Yes, lot's of underscores. They're a hint that you probably shouldn't be
192 * reading from the role_regs. Once the mmu_role is constructed, it becomes
193 * the single source of truth for the MMU's state.
195 #define BUILD_MMU_ROLE_REGS_ACCESSOR(reg, name, flag) \
196 static inline bool ____is_##reg##_##name(struct kvm_mmu_role_regs *regs)\
198 return !!(regs->reg & flag); \
200 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, pg, X86_CR0_PG);
201 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, wp, X86_CR0_WP);
202 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pse, X86_CR4_PSE);
203 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pae, X86_CR4_PAE);
204 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smep, X86_CR4_SMEP);
205 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smap, X86_CR4_SMAP);
206 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pke, X86_CR4_PKE);
207 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, la57, X86_CR4_LA57);
208 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, nx, EFER_NX);
209 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, lma, EFER_LMA);
212 * The MMU itself (with a valid role) is the single source of truth for the
213 * MMU. Do not use the regs used to build the MMU/role, nor the vCPU. The
214 * regs don't account for dependencies, e.g. clearing CR4 bits if CR0.PG=1,
215 * and the vCPU may be incorrect/irrelevant.
217 #define BUILD_MMU_ROLE_ACCESSOR(base_or_ext, reg, name) \
218 static inline bool is_##reg##_##name(struct kvm_mmu *mmu) \
220 return !!(mmu->mmu_role. base_or_ext . reg##_##name); \
222 BUILD_MMU_ROLE_ACCESSOR(ext, cr0, pg);
223 BUILD_MMU_ROLE_ACCESSOR(base, cr0, wp);
224 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pse);
225 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pae);
226 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smep);
227 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smap);
228 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pke);
229 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, la57);
230 BUILD_MMU_ROLE_ACCESSOR(base, efer, nx);
232 static struct kvm_mmu_role_regs vcpu_to_role_regs(struct kvm_vcpu *vcpu)
234 struct kvm_mmu_role_regs regs = {
235 .cr0 = kvm_read_cr0_bits(vcpu, KVM_MMU_CR0_ROLE_BITS),
236 .cr4 = kvm_read_cr4_bits(vcpu, KVM_MMU_CR4_ROLE_BITS),
237 .efer = vcpu->arch.efer,
243 static int role_regs_to_root_level(struct kvm_mmu_role_regs *regs)
245 if (!____is_cr0_pg(regs))
247 else if (____is_efer_lma(regs))
248 return ____is_cr4_la57(regs) ? PT64_ROOT_5LEVEL :
250 else if (____is_cr4_pae(regs))
251 return PT32E_ROOT_LEVEL;
253 return PT32_ROOT_LEVEL;
256 static inline bool kvm_available_flush_tlb_with_range(void)
258 return kvm_x86_ops.tlb_remote_flush_with_range;
261 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
262 struct kvm_tlb_range *range)
266 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
267 ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range);
270 kvm_flush_remote_tlbs(kvm);
273 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
274 u64 start_gfn, u64 pages)
276 struct kvm_tlb_range range;
278 range.start_gfn = start_gfn;
281 kvm_flush_remote_tlbs_with_range(kvm, &range);
284 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
287 u64 spte = make_mmio_spte(vcpu, gfn, access);
289 trace_mark_mmio_spte(sptep, gfn, spte);
290 mmu_spte_set(sptep, spte);
293 static gfn_t get_mmio_spte_gfn(u64 spte)
295 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
297 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)
298 & shadow_nonpresent_or_rsvd_mask;
300 return gpa >> PAGE_SHIFT;
303 static unsigned get_mmio_spte_access(u64 spte)
305 return spte & shadow_mmio_access_mask;
308 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
310 u64 kvm_gen, spte_gen, gen;
312 gen = kvm_vcpu_memslots(vcpu)->generation;
313 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
316 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
317 spte_gen = get_mmio_spte_generation(spte);
319 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
320 return likely(kvm_gen == spte_gen);
323 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
324 struct x86_exception *exception)
326 /* Check if guest physical address doesn't exceed guest maximum */
327 if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) {
328 exception->error_code |= PFERR_RSVD_MASK;
335 static int is_cpuid_PSE36(void)
340 static gfn_t pse36_gfn_delta(u32 gpte)
342 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
344 return (gpte & PT32_DIR_PSE36_MASK) << shift;
348 static void __set_spte(u64 *sptep, u64 spte)
350 WRITE_ONCE(*sptep, spte);
353 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
355 WRITE_ONCE(*sptep, spte);
358 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
360 return xchg(sptep, spte);
363 static u64 __get_spte_lockless(u64 *sptep)
365 return READ_ONCE(*sptep);
376 static void count_spte_clear(u64 *sptep, u64 spte)
378 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
380 if (is_shadow_present_pte(spte))
383 /* Ensure the spte is completely set before we increase the count */
385 sp->clear_spte_count++;
388 static void __set_spte(u64 *sptep, u64 spte)
390 union split_spte *ssptep, sspte;
392 ssptep = (union split_spte *)sptep;
393 sspte = (union split_spte)spte;
395 ssptep->spte_high = sspte.spte_high;
398 * If we map the spte from nonpresent to present, We should store
399 * the high bits firstly, then set present bit, so cpu can not
400 * fetch this spte while we are setting the spte.
404 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
407 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
409 union split_spte *ssptep, sspte;
411 ssptep = (union split_spte *)sptep;
412 sspte = (union split_spte)spte;
414 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
417 * If we map the spte from present to nonpresent, we should clear
418 * present bit firstly to avoid vcpu fetch the old high bits.
422 ssptep->spte_high = sspte.spte_high;
423 count_spte_clear(sptep, spte);
426 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
428 union split_spte *ssptep, sspte, orig;
430 ssptep = (union split_spte *)sptep;
431 sspte = (union split_spte)spte;
433 /* xchg acts as a barrier before the setting of the high bits */
434 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
435 orig.spte_high = ssptep->spte_high;
436 ssptep->spte_high = sspte.spte_high;
437 count_spte_clear(sptep, spte);
443 * The idea using the light way get the spte on x86_32 guest is from
444 * gup_get_pte (mm/gup.c).
446 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
447 * coalesces them and we are running out of the MMU lock. Therefore
448 * we need to protect against in-progress updates of the spte.
450 * Reading the spte while an update is in progress may get the old value
451 * for the high part of the spte. The race is fine for a present->non-present
452 * change (because the high part of the spte is ignored for non-present spte),
453 * but for a present->present change we must reread the spte.
455 * All such changes are done in two steps (present->non-present and
456 * non-present->present), hence it is enough to count the number of
457 * present->non-present updates: if it changed while reading the spte,
458 * we might have hit the race. This is done using clear_spte_count.
460 static u64 __get_spte_lockless(u64 *sptep)
462 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
463 union split_spte spte, *orig = (union split_spte *)sptep;
467 count = sp->clear_spte_count;
470 spte.spte_low = orig->spte_low;
473 spte.spte_high = orig->spte_high;
476 if (unlikely(spte.spte_low != orig->spte_low ||
477 count != sp->clear_spte_count))
484 static bool spte_has_volatile_bits(u64 spte)
486 if (!is_shadow_present_pte(spte))
490 * Always atomically update spte if it can be updated
491 * out of mmu-lock, it can ensure dirty bit is not lost,
492 * also, it can help us to get a stable is_writable_pte()
493 * to ensure tlb flush is not missed.
495 if (spte_can_locklessly_be_made_writable(spte) ||
496 is_access_track_spte(spte))
499 if (spte_ad_enabled(spte)) {
500 if ((spte & shadow_accessed_mask) == 0 ||
501 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
508 /* Rules for using mmu_spte_set:
509 * Set the sptep from nonpresent to present.
510 * Note: the sptep being assigned *must* be either not present
511 * or in a state where the hardware will not attempt to update
514 static void mmu_spte_set(u64 *sptep, u64 new_spte)
516 WARN_ON(is_shadow_present_pte(*sptep));
517 __set_spte(sptep, new_spte);
521 * Update the SPTE (excluding the PFN), but do not track changes in its
522 * accessed/dirty status.
524 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
526 u64 old_spte = *sptep;
528 WARN_ON(!is_shadow_present_pte(new_spte));
530 if (!is_shadow_present_pte(old_spte)) {
531 mmu_spte_set(sptep, new_spte);
535 if (!spte_has_volatile_bits(old_spte))
536 __update_clear_spte_fast(sptep, new_spte);
538 old_spte = __update_clear_spte_slow(sptep, new_spte);
540 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
545 /* Rules for using mmu_spte_update:
546 * Update the state bits, it means the mapped pfn is not changed.
548 * Whenever we overwrite a writable spte with a read-only one we
549 * should flush remote TLBs. Otherwise rmap_write_protect
550 * will find a read-only spte, even though the writable spte
551 * might be cached on a CPU's TLB, the return value indicates this
554 * Returns true if the TLB needs to be flushed
556 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
559 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
561 if (!is_shadow_present_pte(old_spte))
565 * For the spte updated out of mmu-lock is safe, since
566 * we always atomically update it, see the comments in
567 * spte_has_volatile_bits().
569 if (spte_can_locklessly_be_made_writable(old_spte) &&
570 !is_writable_pte(new_spte))
574 * Flush TLB when accessed/dirty states are changed in the page tables,
575 * to guarantee consistency between TLB and page tables.
578 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
580 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
583 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
585 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
592 * Rules for using mmu_spte_clear_track_bits:
593 * It sets the sptep from present to nonpresent, and track the
594 * state bits, it is used to clear the last level sptep.
595 * Returns non-zero if the PTE was previously valid.
597 static int mmu_spte_clear_track_bits(u64 *sptep)
600 u64 old_spte = *sptep;
602 if (!spte_has_volatile_bits(old_spte))
603 __update_clear_spte_fast(sptep, 0ull);
605 old_spte = __update_clear_spte_slow(sptep, 0ull);
607 if (!is_shadow_present_pte(old_spte))
610 pfn = spte_to_pfn(old_spte);
613 * KVM does not hold the refcount of the page used by
614 * kvm mmu, before reclaiming the page, we should
615 * unmap it from mmu first.
617 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
619 if (is_accessed_spte(old_spte))
620 kvm_set_pfn_accessed(pfn);
622 if (is_dirty_spte(old_spte))
623 kvm_set_pfn_dirty(pfn);
629 * Rules for using mmu_spte_clear_no_track:
630 * Directly clear spte without caring the state bits of sptep,
631 * it is used to set the upper level spte.
633 static void mmu_spte_clear_no_track(u64 *sptep)
635 __update_clear_spte_fast(sptep, 0ull);
638 static u64 mmu_spte_get_lockless(u64 *sptep)
640 return __get_spte_lockless(sptep);
643 /* Restore an acc-track PTE back to a regular PTE */
644 static u64 restore_acc_track_spte(u64 spte)
647 u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
648 & SHADOW_ACC_TRACK_SAVED_BITS_MASK;
650 WARN_ON_ONCE(spte_ad_enabled(spte));
651 WARN_ON_ONCE(!is_access_track_spte(spte));
653 new_spte &= ~shadow_acc_track_mask;
654 new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
655 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
656 new_spte |= saved_bits;
661 /* Returns the Accessed status of the PTE and resets it at the same time. */
662 static bool mmu_spte_age(u64 *sptep)
664 u64 spte = mmu_spte_get_lockless(sptep);
666 if (!is_accessed_spte(spte))
669 if (spte_ad_enabled(spte)) {
670 clear_bit((ffs(shadow_accessed_mask) - 1),
671 (unsigned long *)sptep);
674 * Capture the dirty status of the page, so that it doesn't get
675 * lost when the SPTE is marked for access tracking.
677 if (is_writable_pte(spte))
678 kvm_set_pfn_dirty(spte_to_pfn(spte));
680 spte = mark_spte_for_access_track(spte);
681 mmu_spte_update_no_track(sptep, spte);
687 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
690 * Prevent page table teardown by making any free-er wait during
691 * kvm_flush_remote_tlbs() IPI to all active vcpus.
696 * Make sure a following spte read is not reordered ahead of the write
699 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
702 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
705 * Make sure the write to vcpu->mode is not reordered in front of
706 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
707 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
709 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
713 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
717 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
718 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
719 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
722 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
723 PT64_ROOT_MAX_LEVEL);
726 if (maybe_indirect) {
727 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
728 PT64_ROOT_MAX_LEVEL);
732 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
733 PT64_ROOT_MAX_LEVEL);
736 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
738 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
739 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
740 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
741 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
744 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
746 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
749 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
751 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
754 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
756 if (!sp->role.direct)
757 return sp->gfns[index];
759 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
762 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
764 if (!sp->role.direct) {
765 sp->gfns[index] = gfn;
769 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
770 pr_err_ratelimited("gfn mismatch under direct page %llx "
771 "(expected %llx, got %llx)\n",
773 kvm_mmu_page_get_gfn(sp, index), gfn);
777 * Return the pointer to the large page information for a given gfn,
778 * handling slots that are not large page aligned.
780 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
781 const struct kvm_memory_slot *slot, int level)
785 idx = gfn_to_index(gfn, slot->base_gfn, level);
786 return &slot->arch.lpage_info[level - 2][idx];
789 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
790 gfn_t gfn, int count)
792 struct kvm_lpage_info *linfo;
795 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
796 linfo = lpage_info_slot(gfn, slot, i);
797 linfo->disallow_lpage += count;
798 WARN_ON(linfo->disallow_lpage < 0);
802 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
804 update_gfn_disallow_lpage_count(slot, gfn, 1);
807 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
809 update_gfn_disallow_lpage_count(slot, gfn, -1);
812 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
814 struct kvm_memslots *slots;
815 struct kvm_memory_slot *slot;
818 kvm->arch.indirect_shadow_pages++;
820 slots = kvm_memslots_for_spte_role(kvm, sp->role);
821 slot = __gfn_to_memslot(slots, gfn);
823 /* the non-leaf shadow pages are keeping readonly. */
824 if (sp->role.level > PG_LEVEL_4K)
825 return kvm_slot_page_track_add_page(kvm, slot, gfn,
826 KVM_PAGE_TRACK_WRITE);
828 kvm_mmu_gfn_disallow_lpage(slot, gfn);
831 void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
833 if (sp->lpage_disallowed)
836 ++kvm->stat.nx_lpage_splits;
837 list_add_tail(&sp->lpage_disallowed_link,
838 &kvm->arch.lpage_disallowed_mmu_pages);
839 sp->lpage_disallowed = true;
842 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
844 struct kvm_memslots *slots;
845 struct kvm_memory_slot *slot;
848 kvm->arch.indirect_shadow_pages--;
850 slots = kvm_memslots_for_spte_role(kvm, sp->role);
851 slot = __gfn_to_memslot(slots, gfn);
852 if (sp->role.level > PG_LEVEL_4K)
853 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
854 KVM_PAGE_TRACK_WRITE);
856 kvm_mmu_gfn_allow_lpage(slot, gfn);
859 void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
861 --kvm->stat.nx_lpage_splits;
862 sp->lpage_disallowed = false;
863 list_del(&sp->lpage_disallowed_link);
866 static struct kvm_memory_slot *
867 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
870 struct kvm_memory_slot *slot;
872 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
873 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
875 if (no_dirty_log && kvm_slot_dirty_track_enabled(slot))
882 * About rmap_head encoding:
884 * If the bit zero of rmap_head->val is clear, then it points to the only spte
885 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
886 * pte_list_desc containing more mappings.
890 * Returns the number of pointers in the rmap chain, not counting the new one.
892 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
893 struct kvm_rmap_head *rmap_head)
895 struct pte_list_desc *desc;
898 if (!rmap_head->val) {
899 rmap_printk("%p %llx 0->1\n", spte, *spte);
900 rmap_head->val = (unsigned long)spte;
901 } else if (!(rmap_head->val & 1)) {
902 rmap_printk("%p %llx 1->many\n", spte, *spte);
903 desc = mmu_alloc_pte_list_desc(vcpu);
904 desc->sptes[0] = (u64 *)rmap_head->val;
905 desc->sptes[1] = spte;
906 rmap_head->val = (unsigned long)desc | 1;
909 rmap_printk("%p %llx many->many\n", spte, *spte);
910 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
911 while (desc->sptes[PTE_LIST_EXT-1]) {
912 count += PTE_LIST_EXT;
915 desc->more = mmu_alloc_pte_list_desc(vcpu);
921 for (i = 0; desc->sptes[i]; ++i)
923 desc->sptes[i] = spte;
929 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
930 struct pte_list_desc *desc, int i,
931 struct pte_list_desc *prev_desc)
935 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
937 desc->sptes[i] = desc->sptes[j];
938 desc->sptes[j] = NULL;
941 if (!prev_desc && !desc->more)
945 prev_desc->more = desc->more;
947 rmap_head->val = (unsigned long)desc->more | 1;
948 mmu_free_pte_list_desc(desc);
951 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
953 struct pte_list_desc *desc;
954 struct pte_list_desc *prev_desc;
957 if (!rmap_head->val) {
958 pr_err("%s: %p 0->BUG\n", __func__, spte);
960 } else if (!(rmap_head->val & 1)) {
961 rmap_printk("%p 1->0\n", spte);
962 if ((u64 *)rmap_head->val != spte) {
963 pr_err("%s: %p 1->BUG\n", __func__, spte);
968 rmap_printk("%p many->many\n", spte);
969 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
972 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
973 if (desc->sptes[i] == spte) {
974 pte_list_desc_remove_entry(rmap_head,
982 pr_err("%s: %p many->many\n", __func__, spte);
987 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
989 mmu_spte_clear_track_bits(sptep);
990 __pte_list_remove(sptep, rmap_head);
993 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
994 struct kvm_memory_slot *slot)
998 idx = gfn_to_index(gfn, slot->base_gfn, level);
999 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
1002 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1003 struct kvm_mmu_page *sp)
1005 struct kvm_memslots *slots;
1006 struct kvm_memory_slot *slot;
1008 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1009 slot = __gfn_to_memslot(slots, gfn);
1010 return __gfn_to_rmap(gfn, sp->role.level, slot);
1013 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1015 struct kvm_mmu_memory_cache *mc;
1017 mc = &vcpu->arch.mmu_pte_list_desc_cache;
1018 return kvm_mmu_memory_cache_nr_free_objects(mc);
1021 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1023 struct kvm_mmu_page *sp;
1024 struct kvm_rmap_head *rmap_head;
1026 sp = sptep_to_sp(spte);
1027 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1028 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1029 return pte_list_add(vcpu, spte, rmap_head);
1032 static void rmap_remove(struct kvm *kvm, u64 *spte)
1034 struct kvm_mmu_page *sp;
1036 struct kvm_rmap_head *rmap_head;
1038 sp = sptep_to_sp(spte);
1039 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1040 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1041 __pte_list_remove(spte, rmap_head);
1045 * Used by the following functions to iterate through the sptes linked by a
1046 * rmap. All fields are private and not assumed to be used outside.
1048 struct rmap_iterator {
1049 /* private fields */
1050 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1051 int pos; /* index of the sptep */
1055 * Iteration must be started by this function. This should also be used after
1056 * removing/dropping sptes from the rmap link because in such cases the
1057 * information in the iterator may not be valid.
1059 * Returns sptep if found, NULL otherwise.
1061 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1062 struct rmap_iterator *iter)
1066 if (!rmap_head->val)
1069 if (!(rmap_head->val & 1)) {
1071 sptep = (u64 *)rmap_head->val;
1075 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1077 sptep = iter->desc->sptes[iter->pos];
1079 BUG_ON(!is_shadow_present_pte(*sptep));
1084 * Must be used with a valid iterator: e.g. after rmap_get_first().
1086 * Returns sptep if found, NULL otherwise.
1088 static u64 *rmap_get_next(struct rmap_iterator *iter)
1093 if (iter->pos < PTE_LIST_EXT - 1) {
1095 sptep = iter->desc->sptes[iter->pos];
1100 iter->desc = iter->desc->more;
1104 /* desc->sptes[0] cannot be NULL */
1105 sptep = iter->desc->sptes[iter->pos];
1112 BUG_ON(!is_shadow_present_pte(*sptep));
1116 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1117 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1118 _spte_; _spte_ = rmap_get_next(_iter_))
1120 static void drop_spte(struct kvm *kvm, u64 *sptep)
1122 if (mmu_spte_clear_track_bits(sptep))
1123 rmap_remove(kvm, sptep);
1127 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1129 if (is_large_pte(*sptep)) {
1130 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1131 drop_spte(kvm, sptep);
1139 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1141 if (__drop_large_spte(vcpu->kvm, sptep)) {
1142 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1144 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1145 KVM_PAGES_PER_HPAGE(sp->role.level));
1150 * Write-protect on the specified @sptep, @pt_protect indicates whether
1151 * spte write-protection is caused by protecting shadow page table.
1153 * Note: write protection is difference between dirty logging and spte
1155 * - for dirty logging, the spte can be set to writable at anytime if
1156 * its dirty bitmap is properly set.
1157 * - for spte protection, the spte can be writable only after unsync-ing
1160 * Return true if tlb need be flushed.
1162 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1166 if (!is_writable_pte(spte) &&
1167 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1170 rmap_printk("spte %p %llx\n", sptep, *sptep);
1173 spte &= ~shadow_mmu_writable_mask;
1174 spte = spte & ~PT_WRITABLE_MASK;
1176 return mmu_spte_update(sptep, spte);
1179 static bool __rmap_write_protect(struct kvm *kvm,
1180 struct kvm_rmap_head *rmap_head,
1184 struct rmap_iterator iter;
1187 for_each_rmap_spte(rmap_head, &iter, sptep)
1188 flush |= spte_write_protect(sptep, pt_protect);
1193 static bool spte_clear_dirty(u64 *sptep)
1197 rmap_printk("spte %p %llx\n", sptep, *sptep);
1199 MMU_WARN_ON(!spte_ad_enabled(spte));
1200 spte &= ~shadow_dirty_mask;
1201 return mmu_spte_update(sptep, spte);
1204 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1206 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1207 (unsigned long *)sptep);
1208 if (was_writable && !spte_ad_enabled(*sptep))
1209 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1211 return was_writable;
1215 * Gets the GFN ready for another round of dirty logging by clearing the
1216 * - D bit on ad-enabled SPTEs, and
1217 * - W bit on ad-disabled SPTEs.
1218 * Returns true iff any D or W bits were cleared.
1220 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1221 struct kvm_memory_slot *slot)
1224 struct rmap_iterator iter;
1227 for_each_rmap_spte(rmap_head, &iter, sptep)
1228 if (spte_ad_need_write_protect(*sptep))
1229 flush |= spte_wrprot_for_clear_dirty(sptep);
1231 flush |= spte_clear_dirty(sptep);
1237 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1238 * @kvm: kvm instance
1239 * @slot: slot to protect
1240 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1241 * @mask: indicates which pages we should protect
1243 * Used when we do not need to care about huge page mappings.
1245 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1246 struct kvm_memory_slot *slot,
1247 gfn_t gfn_offset, unsigned long mask)
1249 struct kvm_rmap_head *rmap_head;
1251 if (is_tdp_mmu_enabled(kvm))
1252 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1253 slot->base_gfn + gfn_offset, mask, true);
1255 if (!kvm_memslots_have_rmaps(kvm))
1259 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1261 __rmap_write_protect(kvm, rmap_head, false);
1263 /* clear the first set bit */
1269 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1270 * protect the page if the D-bit isn't supported.
1271 * @kvm: kvm instance
1272 * @slot: slot to clear D-bit
1273 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1274 * @mask: indicates which pages we should clear D-bit
1276 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1278 static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1279 struct kvm_memory_slot *slot,
1280 gfn_t gfn_offset, unsigned long mask)
1282 struct kvm_rmap_head *rmap_head;
1284 if (is_tdp_mmu_enabled(kvm))
1285 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1286 slot->base_gfn + gfn_offset, mask, false);
1288 if (!kvm_memslots_have_rmaps(kvm))
1292 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1294 __rmap_clear_dirty(kvm, rmap_head, slot);
1296 /* clear the first set bit */
1302 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1305 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1306 * enable dirty logging for them.
1308 * We need to care about huge page mappings: e.g. during dirty logging we may
1309 * have such mappings.
1311 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1312 struct kvm_memory_slot *slot,
1313 gfn_t gfn_offset, unsigned long mask)
1316 * Huge pages are NOT write protected when we start dirty logging in
1317 * initially-all-set mode; must write protect them here so that they
1318 * are split to 4K on the first write.
1320 * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn
1321 * of memslot has no such restriction, so the range can cross two large
1324 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) {
1325 gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask);
1326 gfn_t end = slot->base_gfn + gfn_offset + __fls(mask);
1328 kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M);
1330 /* Cross two large pages? */
1331 if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) !=
1332 ALIGN(end << PAGE_SHIFT, PMD_SIZE))
1333 kvm_mmu_slot_gfn_write_protect(kvm, slot, end,
1337 /* Now handle 4K PTEs. */
1338 if (kvm_x86_ops.cpu_dirty_log_size)
1339 kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask);
1341 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1344 int kvm_cpu_dirty_log_size(void)
1346 return kvm_x86_ops.cpu_dirty_log_size;
1349 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1350 struct kvm_memory_slot *slot, u64 gfn,
1353 struct kvm_rmap_head *rmap_head;
1355 bool write_protected = false;
1357 if (kvm_memslots_have_rmaps(kvm)) {
1358 for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1359 rmap_head = __gfn_to_rmap(gfn, i, slot);
1360 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1364 if (is_tdp_mmu_enabled(kvm))
1366 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level);
1368 return write_protected;
1371 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1373 struct kvm_memory_slot *slot;
1375 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1376 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K);
1379 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1380 struct kvm_memory_slot *slot)
1383 struct rmap_iterator iter;
1386 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1387 rmap_printk("spte %p %llx.\n", sptep, *sptep);
1389 pte_list_remove(rmap_head, sptep);
1396 static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1397 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1400 return kvm_zap_rmapp(kvm, rmap_head, slot);
1403 static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1404 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1408 struct rmap_iterator iter;
1413 WARN_ON(pte_huge(pte));
1414 new_pfn = pte_pfn(pte);
1417 for_each_rmap_spte(rmap_head, &iter, sptep) {
1418 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1419 sptep, *sptep, gfn, level);
1423 if (pte_write(pte)) {
1424 pte_list_remove(rmap_head, sptep);
1427 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1430 mmu_spte_clear_track_bits(sptep);
1431 mmu_spte_set(sptep, new_spte);
1435 if (need_flush && kvm_available_flush_tlb_with_range()) {
1436 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1443 struct slot_rmap_walk_iterator {
1445 struct kvm_memory_slot *slot;
1451 /* output fields. */
1453 struct kvm_rmap_head *rmap;
1456 /* private field. */
1457 struct kvm_rmap_head *end_rmap;
1461 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1463 iterator->level = level;
1464 iterator->gfn = iterator->start_gfn;
1465 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1466 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1471 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1472 struct kvm_memory_slot *slot, int start_level,
1473 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1475 iterator->slot = slot;
1476 iterator->start_level = start_level;
1477 iterator->end_level = end_level;
1478 iterator->start_gfn = start_gfn;
1479 iterator->end_gfn = end_gfn;
1481 rmap_walk_init_level(iterator, iterator->start_level);
1484 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1486 return !!iterator->rmap;
1489 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1491 if (++iterator->rmap <= iterator->end_rmap) {
1492 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1496 if (++iterator->level > iterator->end_level) {
1497 iterator->rmap = NULL;
1501 rmap_walk_init_level(iterator, iterator->level);
1504 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1505 _start_gfn, _end_gfn, _iter_) \
1506 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1507 _end_level_, _start_gfn, _end_gfn); \
1508 slot_rmap_walk_okay(_iter_); \
1509 slot_rmap_walk_next(_iter_))
1511 typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1512 struct kvm_memory_slot *slot, gfn_t gfn,
1513 int level, pte_t pte);
1515 static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm,
1516 struct kvm_gfn_range *range,
1517 rmap_handler_t handler)
1519 struct slot_rmap_walk_iterator iterator;
1522 for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL,
1523 range->start, range->end - 1, &iterator)
1524 ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn,
1525 iterator.level, range->pte);
1530 bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range)
1534 if (kvm_memslots_have_rmaps(kvm))
1535 flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp);
1537 if (is_tdp_mmu_enabled(kvm))
1538 flush |= kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush);
1543 bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1547 if (kvm_memslots_have_rmaps(kvm))
1548 flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp);
1550 if (is_tdp_mmu_enabled(kvm))
1551 flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range);
1556 static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1557 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1561 struct rmap_iterator iter;
1564 for_each_rmap_spte(rmap_head, &iter, sptep)
1565 young |= mmu_spte_age(sptep);
1570 static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1571 struct kvm_memory_slot *slot, gfn_t gfn,
1572 int level, pte_t unused)
1575 struct rmap_iterator iter;
1577 for_each_rmap_spte(rmap_head, &iter, sptep)
1578 if (is_accessed_spte(*sptep))
1583 #define RMAP_RECYCLE_THRESHOLD 1000
1585 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1587 struct kvm_rmap_head *rmap_head;
1588 struct kvm_mmu_page *sp;
1590 sp = sptep_to_sp(spte);
1592 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1594 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0));
1595 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1596 KVM_PAGES_PER_HPAGE(sp->role.level));
1599 bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1603 if (kvm_memslots_have_rmaps(kvm))
1604 young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp);
1606 if (is_tdp_mmu_enabled(kvm))
1607 young |= kvm_tdp_mmu_age_gfn_range(kvm, range);
1612 bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1616 if (kvm_memslots_have_rmaps(kvm))
1617 young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp);
1619 if (is_tdp_mmu_enabled(kvm))
1620 young |= kvm_tdp_mmu_test_age_gfn(kvm, range);
1626 static int is_empty_shadow_page(u64 *spt)
1631 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1632 if (is_shadow_present_pte(*pos)) {
1633 printk(KERN_ERR "%s: %p %llx\n", __func__,
1642 * This value is the sum of all of the kvm instances's
1643 * kvm->arch.n_used_mmu_pages values. We need a global,
1644 * aggregate version in order to make the slab shrinker
1647 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, long nr)
1649 kvm->arch.n_used_mmu_pages += nr;
1650 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1653 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1655 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1656 hlist_del(&sp->hash_link);
1657 list_del(&sp->link);
1658 free_page((unsigned long)sp->spt);
1659 if (!sp->role.direct)
1660 free_page((unsigned long)sp->gfns);
1661 kmem_cache_free(mmu_page_header_cache, sp);
1664 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1666 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1669 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1670 struct kvm_mmu_page *sp, u64 *parent_pte)
1675 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1678 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1681 __pte_list_remove(parent_pte, &sp->parent_ptes);
1684 static void drop_parent_pte(struct kvm_mmu_page *sp,
1687 mmu_page_remove_parent_pte(sp, parent_pte);
1688 mmu_spte_clear_no_track(parent_pte);
1691 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1693 struct kvm_mmu_page *sp;
1695 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1696 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1698 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1699 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1702 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1703 * depends on valid pages being added to the head of the list. See
1704 * comments in kvm_zap_obsolete_pages().
1706 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1707 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1708 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1712 static void mark_unsync(u64 *spte);
1713 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1716 struct rmap_iterator iter;
1718 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1723 static void mark_unsync(u64 *spte)
1725 struct kvm_mmu_page *sp;
1728 sp = sptep_to_sp(spte);
1729 index = spte - sp->spt;
1730 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1732 if (sp->unsync_children++)
1734 kvm_mmu_mark_parents_unsync(sp);
1737 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1738 struct kvm_mmu_page *sp)
1743 #define KVM_PAGE_ARRAY_NR 16
1745 struct kvm_mmu_pages {
1746 struct mmu_page_and_offset {
1747 struct kvm_mmu_page *sp;
1749 } page[KVM_PAGE_ARRAY_NR];
1753 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1759 for (i=0; i < pvec->nr; i++)
1760 if (pvec->page[i].sp == sp)
1763 pvec->page[pvec->nr].sp = sp;
1764 pvec->page[pvec->nr].idx = idx;
1766 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1769 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1771 --sp->unsync_children;
1772 WARN_ON((int)sp->unsync_children < 0);
1773 __clear_bit(idx, sp->unsync_child_bitmap);
1776 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1777 struct kvm_mmu_pages *pvec)
1779 int i, ret, nr_unsync_leaf = 0;
1781 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1782 struct kvm_mmu_page *child;
1783 u64 ent = sp->spt[i];
1785 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1786 clear_unsync_child_bit(sp, i);
1790 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1792 if (child->unsync_children) {
1793 if (mmu_pages_add(pvec, child, i))
1796 ret = __mmu_unsync_walk(child, pvec);
1798 clear_unsync_child_bit(sp, i);
1800 } else if (ret > 0) {
1801 nr_unsync_leaf += ret;
1804 } else if (child->unsync) {
1806 if (mmu_pages_add(pvec, child, i))
1809 clear_unsync_child_bit(sp, i);
1812 return nr_unsync_leaf;
1815 #define INVALID_INDEX (-1)
1817 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1818 struct kvm_mmu_pages *pvec)
1821 if (!sp->unsync_children)
1824 mmu_pages_add(pvec, sp, INVALID_INDEX);
1825 return __mmu_unsync_walk(sp, pvec);
1828 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1830 WARN_ON(!sp->unsync);
1831 trace_kvm_mmu_sync_page(sp);
1833 --kvm->stat.mmu_unsync;
1836 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1837 struct list_head *invalid_list);
1838 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1839 struct list_head *invalid_list);
1841 #define for_each_valid_sp(_kvm, _sp, _list) \
1842 hlist_for_each_entry(_sp, _list, hash_link) \
1843 if (is_obsolete_sp((_kvm), (_sp))) { \
1846 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1847 for_each_valid_sp(_kvm, _sp, \
1848 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1849 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1851 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1852 struct list_head *invalid_list)
1854 if (vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
1855 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1862 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1863 struct list_head *invalid_list,
1866 if (!remote_flush && list_empty(invalid_list))
1869 if (!list_empty(invalid_list))
1870 kvm_mmu_commit_zap_page(kvm, invalid_list);
1872 kvm_flush_remote_tlbs(kvm);
1876 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1877 struct list_head *invalid_list,
1878 bool remote_flush, bool local_flush)
1880 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
1884 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1887 #ifdef CONFIG_KVM_MMU_AUDIT
1888 #include "mmu_audit.c"
1890 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1891 static void mmu_audit_disable(void) { }
1894 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1896 return sp->role.invalid ||
1897 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1900 struct mmu_page_path {
1901 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1902 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1905 #define for_each_sp(pvec, sp, parents, i) \
1906 for (i = mmu_pages_first(&pvec, &parents); \
1907 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1908 i = mmu_pages_next(&pvec, &parents, i))
1910 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1911 struct mmu_page_path *parents,
1916 for (n = i+1; n < pvec->nr; n++) {
1917 struct kvm_mmu_page *sp = pvec->page[n].sp;
1918 unsigned idx = pvec->page[n].idx;
1919 int level = sp->role.level;
1921 parents->idx[level-1] = idx;
1922 if (level == PG_LEVEL_4K)
1925 parents->parent[level-2] = sp;
1931 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1932 struct mmu_page_path *parents)
1934 struct kvm_mmu_page *sp;
1940 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1942 sp = pvec->page[0].sp;
1943 level = sp->role.level;
1944 WARN_ON(level == PG_LEVEL_4K);
1946 parents->parent[level-2] = sp;
1948 /* Also set up a sentinel. Further entries in pvec are all
1949 * children of sp, so this element is never overwritten.
1951 parents->parent[level-1] = NULL;
1952 return mmu_pages_next(pvec, parents, 0);
1955 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1957 struct kvm_mmu_page *sp;
1958 unsigned int level = 0;
1961 unsigned int idx = parents->idx[level];
1962 sp = parents->parent[level];
1966 WARN_ON(idx == INVALID_INDEX);
1967 clear_unsync_child_bit(sp, idx);
1969 } while (!sp->unsync_children);
1972 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1973 struct kvm_mmu_page *parent)
1976 struct kvm_mmu_page *sp;
1977 struct mmu_page_path parents;
1978 struct kvm_mmu_pages pages;
1979 LIST_HEAD(invalid_list);
1982 while (mmu_unsync_walk(parent, &pages)) {
1983 bool protected = false;
1985 for_each_sp(pages, sp, parents, i)
1986 protected |= rmap_write_protect(vcpu, sp->gfn);
1989 kvm_flush_remote_tlbs(vcpu->kvm);
1993 for_each_sp(pages, sp, parents, i) {
1994 kvm_unlink_unsync_page(vcpu->kvm, sp);
1995 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
1996 mmu_pages_clear_parents(&parents);
1998 if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) {
1999 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2000 cond_resched_rwlock_write(&vcpu->kvm->mmu_lock);
2005 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2008 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2010 atomic_set(&sp->write_flooding_count, 0);
2013 static void clear_sp_write_flooding_count(u64 *spte)
2015 __clear_sp_write_flooding_count(sptep_to_sp(spte));
2018 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2023 unsigned int access)
2025 bool direct_mmu = vcpu->arch.mmu->direct_map;
2026 union kvm_mmu_page_role role;
2027 struct hlist_head *sp_list;
2029 struct kvm_mmu_page *sp;
2031 LIST_HEAD(invalid_list);
2033 role = vcpu->arch.mmu->mmu_role.base;
2035 role.direct = direct;
2037 role.gpte_is_8_bytes = true;
2038 role.access = access;
2039 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2040 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2041 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2042 role.quadrant = quadrant;
2045 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2046 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2047 if (sp->gfn != gfn) {
2052 if (sp->role.word != role.word) {
2054 * If the guest is creating an upper-level page, zap
2055 * unsync pages for the same gfn. While it's possible
2056 * the guest is using recursive page tables, in all
2057 * likelihood the guest has stopped using the unsync
2058 * page and is installing a completely unrelated page.
2059 * Unsync pages must not be left as is, because the new
2060 * upper-level page will be write-protected.
2062 if (level > PG_LEVEL_4K && sp->unsync)
2063 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2069 goto trace_get_page;
2073 * The page is good, but is stale. kvm_sync_page does
2074 * get the latest guest state, but (unlike mmu_unsync_children)
2075 * it doesn't write-protect the page or mark it synchronized!
2076 * This way the validity of the mapping is ensured, but the
2077 * overhead of write protection is not incurred until the
2078 * guest invalidates the TLB mapping. This allows multiple
2079 * SPs for a single gfn to be unsync.
2081 * If the sync fails, the page is zapped. If so, break
2082 * in order to rebuild it.
2084 if (!kvm_sync_page(vcpu, sp, &invalid_list))
2087 WARN_ON(!list_empty(&invalid_list));
2088 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2091 if (sp->unsync_children)
2092 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2094 __clear_sp_write_flooding_count(sp);
2097 trace_kvm_mmu_get_page(sp, false);
2101 ++vcpu->kvm->stat.mmu_cache_miss;
2103 sp = kvm_mmu_alloc_page(vcpu, direct);
2107 hlist_add_head(&sp->hash_link, sp_list);
2109 account_shadowed(vcpu->kvm, sp);
2110 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2111 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2113 trace_kvm_mmu_get_page(sp, true);
2115 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2117 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2118 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2122 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2123 struct kvm_vcpu *vcpu, hpa_t root,
2126 iterator->addr = addr;
2127 iterator->shadow_addr = root;
2128 iterator->level = vcpu->arch.mmu->shadow_root_level;
2130 if (iterator->level == PT64_ROOT_4LEVEL &&
2131 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2132 !vcpu->arch.mmu->direct_map)
2135 if (iterator->level == PT32E_ROOT_LEVEL) {
2137 * prev_root is currently only used for 64-bit hosts. So only
2138 * the active root_hpa is valid here.
2140 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2142 iterator->shadow_addr
2143 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2144 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2146 if (!iterator->shadow_addr)
2147 iterator->level = 0;
2151 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2152 struct kvm_vcpu *vcpu, u64 addr)
2154 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2158 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2160 if (iterator->level < PG_LEVEL_4K)
2163 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2164 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2168 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2171 if (is_last_spte(spte, iterator->level)) {
2172 iterator->level = 0;
2176 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2180 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2182 __shadow_walk_next(iterator, *iterator->sptep);
2185 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2186 struct kvm_mmu_page *sp)
2190 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2192 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2194 mmu_spte_set(sptep, spte);
2196 mmu_page_add_parent_pte(vcpu, sp, sptep);
2198 if (sp->unsync_children || sp->unsync)
2202 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2203 unsigned direct_access)
2205 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2206 struct kvm_mmu_page *child;
2209 * For the direct sp, if the guest pte's dirty bit
2210 * changed form clean to dirty, it will corrupt the
2211 * sp's access: allow writable in the read-only sp,
2212 * so we should update the spte at this point to get
2213 * a new sp with the correct access.
2215 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2216 if (child->role.access == direct_access)
2219 drop_parent_pte(child, sptep);
2220 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2224 /* Returns the number of zapped non-leaf child shadow pages. */
2225 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2226 u64 *spte, struct list_head *invalid_list)
2229 struct kvm_mmu_page *child;
2232 if (is_shadow_present_pte(pte)) {
2233 if (is_last_spte(pte, sp->role.level)) {
2234 drop_spte(kvm, spte);
2235 if (is_large_pte(pte))
2238 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2239 drop_parent_pte(child, spte);
2242 * Recursively zap nested TDP SPs, parentless SPs are
2243 * unlikely to be used again in the near future. This
2244 * avoids retaining a large number of stale nested SPs.
2246 if (tdp_enabled && invalid_list &&
2247 child->role.guest_mode && !child->parent_ptes.val)
2248 return kvm_mmu_prepare_zap_page(kvm, child,
2251 } else if (is_mmio_spte(pte)) {
2252 mmu_spte_clear_no_track(spte);
2257 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2258 struct kvm_mmu_page *sp,
2259 struct list_head *invalid_list)
2264 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2265 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2270 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2273 struct rmap_iterator iter;
2275 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2276 drop_parent_pte(sp, sptep);
2279 static int mmu_zap_unsync_children(struct kvm *kvm,
2280 struct kvm_mmu_page *parent,
2281 struct list_head *invalid_list)
2284 struct mmu_page_path parents;
2285 struct kvm_mmu_pages pages;
2287 if (parent->role.level == PG_LEVEL_4K)
2290 while (mmu_unsync_walk(parent, &pages)) {
2291 struct kvm_mmu_page *sp;
2293 for_each_sp(pages, sp, parents, i) {
2294 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2295 mmu_pages_clear_parents(&parents);
2303 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2304 struct kvm_mmu_page *sp,
2305 struct list_head *invalid_list,
2310 trace_kvm_mmu_prepare_zap_page(sp);
2311 ++kvm->stat.mmu_shadow_zapped;
2312 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2313 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2314 kvm_mmu_unlink_parents(kvm, sp);
2316 /* Zapping children means active_mmu_pages has become unstable. */
2317 list_unstable = *nr_zapped;
2319 if (!sp->role.invalid && !sp->role.direct)
2320 unaccount_shadowed(kvm, sp);
2323 kvm_unlink_unsync_page(kvm, sp);
2324 if (!sp->root_count) {
2329 * Already invalid pages (previously active roots) are not on
2330 * the active page list. See list_del() in the "else" case of
2333 if (sp->role.invalid)
2334 list_add(&sp->link, invalid_list);
2336 list_move(&sp->link, invalid_list);
2337 kvm_mod_used_mmu_pages(kvm, -1);
2340 * Remove the active root from the active page list, the root
2341 * will be explicitly freed when the root_count hits zero.
2343 list_del(&sp->link);
2346 * Obsolete pages cannot be used on any vCPUs, see the comment
2347 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2348 * treats invalid shadow pages as being obsolete.
2350 if (!is_obsolete_sp(kvm, sp))
2351 kvm_reload_remote_mmus(kvm);
2354 if (sp->lpage_disallowed)
2355 unaccount_huge_nx_page(kvm, sp);
2357 sp->role.invalid = 1;
2358 return list_unstable;
2361 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2362 struct list_head *invalid_list)
2366 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2370 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2371 struct list_head *invalid_list)
2373 struct kvm_mmu_page *sp, *nsp;
2375 if (list_empty(invalid_list))
2379 * We need to make sure everyone sees our modifications to
2380 * the page tables and see changes to vcpu->mode here. The barrier
2381 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2382 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2384 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2385 * guest mode and/or lockless shadow page table walks.
2387 kvm_flush_remote_tlbs(kvm);
2389 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2390 WARN_ON(!sp->role.invalid || sp->root_count);
2391 kvm_mmu_free_page(sp);
2395 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2396 unsigned long nr_to_zap)
2398 unsigned long total_zapped = 0;
2399 struct kvm_mmu_page *sp, *tmp;
2400 LIST_HEAD(invalid_list);
2404 if (list_empty(&kvm->arch.active_mmu_pages))
2408 list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2410 * Don't zap active root pages, the page itself can't be freed
2411 * and zapping it will just force vCPUs to realloc and reload.
2416 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2418 total_zapped += nr_zapped;
2419 if (total_zapped >= nr_to_zap)
2426 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2428 kvm->stat.mmu_recycled += total_zapped;
2429 return total_zapped;
2432 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2434 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2435 return kvm->arch.n_max_mmu_pages -
2436 kvm->arch.n_used_mmu_pages;
2441 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2443 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2445 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2448 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2451 * Note, this check is intentionally soft, it only guarantees that one
2452 * page is available, while the caller may end up allocating as many as
2453 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2454 * exceeding the (arbitrary by default) limit will not harm the host,
2455 * being too aggressive may unnecessarily kill the guest, and getting an
2456 * exact count is far more trouble than it's worth, especially in the
2459 if (!kvm_mmu_available_pages(vcpu->kvm))
2465 * Changing the number of mmu pages allocated to the vm
2466 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2468 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2470 write_lock(&kvm->mmu_lock);
2472 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2473 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2476 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2479 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2481 write_unlock(&kvm->mmu_lock);
2484 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2486 struct kvm_mmu_page *sp;
2487 LIST_HEAD(invalid_list);
2490 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2492 write_lock(&kvm->mmu_lock);
2493 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2494 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2497 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2499 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2500 write_unlock(&kvm->mmu_lock);
2505 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2510 if (vcpu->arch.mmu->direct_map)
2513 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2515 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2520 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2522 trace_kvm_mmu_unsync_page(sp);
2523 ++vcpu->kvm->stat.mmu_unsync;
2526 kvm_mmu_mark_parents_unsync(sp);
2530 * Attempt to unsync any shadow pages that can be reached by the specified gfn,
2531 * KVM is creating a writable mapping for said gfn. Returns 0 if all pages
2532 * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must
2533 * be write-protected.
2535 int mmu_try_to_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, bool can_unsync)
2537 struct kvm_mmu_page *sp;
2538 bool locked = false;
2541 * Force write-protection if the page is being tracked. Note, the page
2542 * track machinery is used to write-protect upper-level shadow pages,
2543 * i.e. this guards the role.level == 4K assertion below!
2545 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2549 * The page is not write-tracked, mark existing shadow pages unsync
2550 * unless KVM is synchronizing an unsync SP (can_unsync = false). In
2551 * that case, KVM must complete emulation of the guest TLB flush before
2552 * allowing shadow pages to become unsync (writable by the guest).
2554 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2562 * TDP MMU page faults require an additional spinlock as they
2563 * run with mmu_lock held for read, not write, and the unsync
2564 * logic is not thread safe. Take the spinklock regardless of
2565 * the MMU type to avoid extra conditionals/parameters, there's
2566 * no meaningful penalty if mmu_lock is held for write.
2570 spin_lock(&vcpu->kvm->arch.mmu_unsync_pages_lock);
2573 * Recheck after taking the spinlock, a different vCPU
2574 * may have since marked the page unsync. A false
2575 * positive on the unprotected check above is not
2576 * possible as clearing sp->unsync _must_ hold mmu_lock
2577 * for write, i.e. unsync cannot transition from 0->1
2578 * while this CPU holds mmu_lock for read (or write).
2580 if (READ_ONCE(sp->unsync))
2584 WARN_ON(sp->role.level != PG_LEVEL_4K);
2585 kvm_unsync_page(vcpu, sp);
2588 spin_unlock(&vcpu->kvm->arch.mmu_unsync_pages_lock);
2591 * We need to ensure that the marking of unsync pages is visible
2592 * before the SPTE is updated to allow writes because
2593 * kvm_mmu_sync_roots() checks the unsync flags without holding
2594 * the MMU lock and so can race with this. If the SPTE was updated
2595 * before the page had been marked as unsync-ed, something like the
2596 * following could happen:
2599 * ---------------------------------------------------------------------
2600 * 1.2 Host updates SPTE
2602 * 2.1 Guest writes a GPTE for GVA X.
2603 * (GPTE being in the guest page table shadowed
2604 * by the SP from CPU 1.)
2605 * This reads SPTE during the page table walk.
2606 * Since SPTE.W is read as 1, there is no
2609 * 2.2 Guest issues TLB flush.
2610 * That causes a VM Exit.
2612 * 2.3 Walking of unsync pages sees sp->unsync is
2613 * false and skips the page.
2615 * 2.4 Guest accesses GVA X.
2616 * Since the mapping in the SP was not updated,
2617 * so the old mapping for GVA X incorrectly
2621 * (sp->unsync = true)
2623 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2624 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2625 * pairs with this write barrier.
2632 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2633 unsigned int pte_access, int level,
2634 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2635 bool can_unsync, bool host_writable)
2638 struct kvm_mmu_page *sp;
2641 sp = sptep_to_sp(sptep);
2643 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2644 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2646 if (spte & PT_WRITABLE_MASK)
2647 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2650 ret |= SET_SPTE_SPURIOUS;
2651 else if (mmu_spte_update(sptep, spte))
2652 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2656 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2657 unsigned int pte_access, bool write_fault, int level,
2658 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2661 int was_rmapped = 0;
2664 int ret = RET_PF_FIXED;
2667 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2668 *sptep, write_fault, gfn);
2670 if (unlikely(is_noslot_pfn(pfn))) {
2671 mark_mmio_spte(vcpu, sptep, gfn, pte_access);
2672 return RET_PF_EMULATE;
2675 if (is_shadow_present_pte(*sptep)) {
2677 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2678 * the parent of the now unreachable PTE.
2680 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2681 struct kvm_mmu_page *child;
2684 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2685 drop_parent_pte(child, sptep);
2687 } else if (pfn != spte_to_pfn(*sptep)) {
2688 pgprintk("hfn old %llx new %llx\n",
2689 spte_to_pfn(*sptep), pfn);
2690 drop_spte(vcpu->kvm, sptep);
2696 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2697 speculative, true, host_writable);
2698 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2700 ret = RET_PF_EMULATE;
2701 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2704 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2705 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2706 KVM_PAGES_PER_HPAGE(level));
2709 * The fault is fully spurious if and only if the new SPTE and old SPTE
2710 * are identical, and emulation is not required.
2712 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2713 WARN_ON_ONCE(!was_rmapped);
2714 return RET_PF_SPURIOUS;
2717 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2718 trace_kvm_mmu_set_spte(level, gfn, sptep);
2719 if (!was_rmapped && is_large_pte(*sptep))
2720 ++vcpu->kvm->stat.lpages;
2722 if (is_shadow_present_pte(*sptep)) {
2724 rmap_count = rmap_add(vcpu, sptep, gfn);
2725 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2726 rmap_recycle(vcpu, sptep, gfn);
2733 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2736 struct kvm_memory_slot *slot;
2738 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2740 return KVM_PFN_ERR_FAULT;
2742 return gfn_to_pfn_memslot_atomic(slot, gfn);
2745 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2746 struct kvm_mmu_page *sp,
2747 u64 *start, u64 *end)
2749 struct page *pages[PTE_PREFETCH_NUM];
2750 struct kvm_memory_slot *slot;
2751 unsigned int access = sp->role.access;
2755 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2756 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2760 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2764 for (i = 0; i < ret; i++, gfn++, start++) {
2765 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2766 page_to_pfn(pages[i]), true, true);
2773 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2774 struct kvm_mmu_page *sp, u64 *sptep)
2776 u64 *spte, *start = NULL;
2779 WARN_ON(!sp->role.direct);
2781 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2784 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2785 if (is_shadow_present_pte(*spte) || spte == sptep) {
2788 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2796 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2798 struct kvm_mmu_page *sp;
2800 sp = sptep_to_sp(sptep);
2803 * Without accessed bits, there's no way to distinguish between
2804 * actually accessed translations and prefetched, so disable pte
2805 * prefetch if accessed bits aren't available.
2807 if (sp_ad_disabled(sp))
2810 if (sp->role.level > PG_LEVEL_4K)
2814 * If addresses are being invalidated, skip prefetching to avoid
2815 * accidentally prefetching those addresses.
2817 if (unlikely(vcpu->kvm->mmu_notifier_count))
2820 __direct_pte_prefetch(vcpu, sp, sptep);
2823 static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
2824 const struct kvm_memory_slot *slot)
2830 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2834 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2835 * is not solely for performance, it's also necessary to avoid the
2836 * "writable" check in __gfn_to_hva_many(), which will always fail on
2837 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2838 * page fault steps have already verified the guest isn't writing a
2839 * read-only memslot.
2841 hva = __gfn_to_hva_memslot(slot, gfn);
2843 pte = lookup_address_in_mm(kvm->mm, hva, &level);
2850 int kvm_mmu_max_mapping_level(struct kvm *kvm,
2851 const struct kvm_memory_slot *slot, gfn_t gfn,
2852 kvm_pfn_t pfn, int max_level)
2854 struct kvm_lpage_info *linfo;
2856 max_level = min(max_level, max_huge_page_level);
2857 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2858 linfo = lpage_info_slot(gfn, slot, max_level);
2859 if (!linfo->disallow_lpage)
2863 if (max_level == PG_LEVEL_4K)
2866 return host_pfn_mapping_level(kvm, gfn, pfn, slot);
2869 int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2870 int max_level, kvm_pfn_t *pfnp,
2871 bool huge_page_disallowed, int *req_level)
2873 struct kvm_memory_slot *slot;
2874 kvm_pfn_t pfn = *pfnp;
2878 *req_level = PG_LEVEL_4K;
2880 if (unlikely(max_level == PG_LEVEL_4K))
2883 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
2886 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2890 level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level);
2891 if (level == PG_LEVEL_4K)
2894 *req_level = level = min(level, max_level);
2897 * Enforce the iTLB multihit workaround after capturing the requested
2898 * level, which will be used to do precise, accurate accounting.
2900 if (huge_page_disallowed)
2904 * mmu_notifier_retry() was successful and mmu_lock is held, so
2905 * the pmd can't be split from under us.
2907 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2908 VM_BUG_ON((gfn & mask) != (pfn & mask));
2909 *pfnp = pfn & ~mask;
2914 void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2915 kvm_pfn_t *pfnp, int *goal_levelp)
2917 int level = *goal_levelp;
2919 if (cur_level == level && level > PG_LEVEL_4K &&
2920 is_shadow_present_pte(spte) &&
2921 !is_large_pte(spte)) {
2923 * A small SPTE exists for this pfn, but FNAME(fetch)
2924 * and __direct_map would like to create a large PTE
2925 * instead: just force them to go down another level,
2926 * patching back for them into pfn the next 9 bits of
2929 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2930 KVM_PAGES_PER_HPAGE(level - 1);
2931 *pfnp |= gfn & page_mask;
2936 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
2937 int map_writable, int max_level, kvm_pfn_t pfn,
2938 bool prefault, bool is_tdp)
2940 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2941 bool write = error_code & PFERR_WRITE_MASK;
2942 bool exec = error_code & PFERR_FETCH_MASK;
2943 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
2944 struct kvm_shadow_walk_iterator it;
2945 struct kvm_mmu_page *sp;
2946 int level, req_level, ret;
2947 gfn_t gfn = gpa >> PAGE_SHIFT;
2948 gfn_t base_gfn = gfn;
2950 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2951 huge_page_disallowed, &req_level);
2953 trace_kvm_mmu_spte_requested(gpa, level, pfn);
2954 for_each_shadow_entry(vcpu, gpa, it) {
2956 * We cannot overwrite existing page tables with an NX
2957 * large page, as the leaf could be executable.
2959 if (nx_huge_page_workaround_enabled)
2960 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
2963 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2964 if (it.level == level)
2967 drop_large_spte(vcpu, it.sptep);
2968 if (!is_shadow_present_pte(*it.sptep)) {
2969 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2970 it.level - 1, true, ACC_ALL);
2972 link_shadow_page(vcpu, it.sptep, sp);
2973 if (is_tdp && huge_page_disallowed &&
2974 req_level >= it.level)
2975 account_huge_nx_page(vcpu->kvm, sp);
2979 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2980 write, level, base_gfn, pfn, prefault,
2982 if (ret == RET_PF_SPURIOUS)
2985 direct_pte_prefetch(vcpu, it.sptep);
2986 ++vcpu->stat.pf_fixed;
2990 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2992 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2995 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2998 * Do not cache the mmio info caused by writing the readonly gfn
2999 * into the spte otherwise read access on readonly gfn also can
3000 * caused mmio page fault and treat it as mmio access.
3002 if (pfn == KVM_PFN_ERR_RO_FAULT)
3003 return RET_PF_EMULATE;
3005 if (pfn == KVM_PFN_ERR_HWPOISON) {
3006 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3007 return RET_PF_RETRY;
3013 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
3014 kvm_pfn_t pfn, unsigned int access,
3017 /* The pfn is invalid, report the error! */
3018 if (unlikely(is_error_pfn(pfn))) {
3019 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
3023 if (unlikely(is_noslot_pfn(pfn))) {
3024 vcpu_cache_mmio_info(vcpu, gva, gfn,
3025 access & shadow_mmio_access_mask);
3027 * If MMIO caching is disabled, emulate immediately without
3028 * touching the shadow page tables as attempting to install an
3029 * MMIO SPTE will just be an expensive nop.
3031 if (unlikely(!shadow_mmio_value)) {
3032 *ret_val = RET_PF_EMULATE;
3040 static bool page_fault_can_be_fast(u32 error_code)
3043 * Do not fix the mmio spte with invalid generation number which
3044 * need to be updated by slow page fault path.
3046 if (unlikely(error_code & PFERR_RSVD_MASK))
3049 /* See if the page fault is due to an NX violation */
3050 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3051 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3055 * #PF can be fast if:
3056 * 1. The shadow page table entry is not present, which could mean that
3057 * the fault is potentially caused by access tracking (if enabled).
3058 * 2. The shadow page table entry is present and the fault
3059 * is caused by write-protect, that means we just need change the W
3060 * bit of the spte which can be done out of mmu-lock.
3062 * However, if access tracking is disabled we know that a non-present
3063 * page must be a genuine page fault where we have to create a new SPTE.
3064 * So, if access tracking is disabled, we return true only for write
3065 * accesses to a present page.
3068 return shadow_acc_track_mask != 0 ||
3069 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3070 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3074 * Returns true if the SPTE was fixed successfully. Otherwise,
3075 * someone else modified the SPTE from its original value.
3078 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3079 u64 *sptep, u64 old_spte, u64 new_spte)
3083 WARN_ON(!sp->role.direct);
3086 * Theoretically we could also set dirty bit (and flush TLB) here in
3087 * order to eliminate unnecessary PML logging. See comments in
3088 * set_spte. But fast_page_fault is very unlikely to happen with PML
3089 * enabled, so we do not do this. This might result in the same GPA
3090 * to be logged in PML buffer again when the write really happens, and
3091 * eventually to be called by mark_page_dirty twice. But it's also no
3092 * harm. This also avoids the TLB flush needed after setting dirty bit
3093 * so non-PML cases won't be impacted.
3095 * Compare with set_spte where instead shadow_dirty_mask is set.
3097 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3100 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3102 * The gfn of direct spte is stable since it is
3103 * calculated by sp->gfn.
3105 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3106 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3112 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3114 if (fault_err_code & PFERR_FETCH_MASK)
3115 return is_executable_pte(spte);
3117 if (fault_err_code & PFERR_WRITE_MASK)
3118 return is_writable_pte(spte);
3120 /* Fault was on Read access */
3121 return spte & PT_PRESENT_MASK;
3125 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3127 static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3130 struct kvm_shadow_walk_iterator iterator;
3131 struct kvm_mmu_page *sp;
3132 int ret = RET_PF_INVALID;
3134 uint retry_count = 0;
3136 if (!page_fault_can_be_fast(error_code))
3139 walk_shadow_page_lockless_begin(vcpu);
3144 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3145 if (!is_shadow_present_pte(spte))
3148 if (!is_shadow_present_pte(spte))
3151 sp = sptep_to_sp(iterator.sptep);
3152 if (!is_last_spte(spte, sp->role.level))
3156 * Check whether the memory access that caused the fault would
3157 * still cause it if it were to be performed right now. If not,
3158 * then this is a spurious fault caused by TLB lazily flushed,
3159 * or some other CPU has already fixed the PTE after the
3160 * current CPU took the fault.
3162 * Need not check the access of upper level table entries since
3163 * they are always ACC_ALL.
3165 if (is_access_allowed(error_code, spte)) {
3166 ret = RET_PF_SPURIOUS;
3172 if (is_access_track_spte(spte))
3173 new_spte = restore_acc_track_spte(new_spte);
3176 * Currently, to simplify the code, write-protection can
3177 * be removed in the fast path only if the SPTE was
3178 * write-protected for dirty-logging or access tracking.
3180 if ((error_code & PFERR_WRITE_MASK) &&
3181 spte_can_locklessly_be_made_writable(spte)) {
3182 new_spte |= PT_WRITABLE_MASK;
3185 * Do not fix write-permission on the large spte. Since
3186 * we only dirty the first page into the dirty-bitmap in
3187 * fast_pf_fix_direct_spte(), other pages are missed
3188 * if its slot has dirty logging enabled.
3190 * Instead, we let the slow page fault path create a
3191 * normal spte to fix the access.
3193 * See the comments in kvm_arch_commit_memory_region().
3195 if (sp->role.level > PG_LEVEL_4K)
3199 /* Verify that the fault can be handled in the fast path */
3200 if (new_spte == spte ||
3201 !is_access_allowed(error_code, new_spte))
3205 * Currently, fast page fault only works for direct mapping
3206 * since the gfn is not stable for indirect shadow page. See
3207 * Documentation/virt/kvm/locking.rst to get more detail.
3209 if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte,
3215 if (++retry_count > 4) {
3216 printk_once(KERN_WARNING
3217 "kvm: Fast #PF retrying more than 4 times.\n");
3223 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3225 walk_shadow_page_lockless_end(vcpu);
3230 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3231 struct list_head *invalid_list)
3233 struct kvm_mmu_page *sp;
3235 if (!VALID_PAGE(*root_hpa))
3238 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3240 if (is_tdp_mmu_page(sp))
3241 kvm_tdp_mmu_put_root(kvm, sp, false);
3242 else if (!--sp->root_count && sp->role.invalid)
3243 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3245 *root_hpa = INVALID_PAGE;
3248 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3249 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3250 ulong roots_to_free)
3252 struct kvm *kvm = vcpu->kvm;
3254 LIST_HEAD(invalid_list);
3255 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3257 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3259 /* Before acquiring the MMU lock, see if we need to do any real work. */
3260 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3261 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3262 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3263 VALID_PAGE(mmu->prev_roots[i].hpa))
3266 if (i == KVM_MMU_NUM_PREV_ROOTS)
3270 write_lock(&kvm->mmu_lock);
3272 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3273 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3274 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3277 if (free_active_root) {
3278 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3279 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3280 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3281 } else if (mmu->pae_root) {
3282 for (i = 0; i < 4; ++i) {
3283 if (!IS_VALID_PAE_ROOT(mmu->pae_root[i]))
3286 mmu_free_root_page(kvm, &mmu->pae_root[i],
3288 mmu->pae_root[i] = INVALID_PAE_ROOT;
3291 mmu->root_hpa = INVALID_PAGE;
3295 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3296 write_unlock(&kvm->mmu_lock);
3298 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3300 void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3302 unsigned long roots_to_free = 0;
3307 * This should not be called while L2 is active, L2 can't invalidate
3308 * _only_ its own roots, e.g. INVVPID unconditionally exits.
3310 WARN_ON_ONCE(mmu->mmu_role.base.guest_mode);
3312 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3313 root_hpa = mmu->prev_roots[i].hpa;
3314 if (!VALID_PAGE(root_hpa))
3317 if (!to_shadow_page(root_hpa) ||
3318 to_shadow_page(root_hpa)->role.guest_mode)
3319 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
3322 kvm_mmu_free_roots(vcpu, mmu, roots_to_free);
3324 EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots);
3327 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3331 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3332 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3339 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3340 u8 level, bool direct)
3342 struct kvm_mmu_page *sp;
3344 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3347 return __pa(sp->spt);
3350 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3352 struct kvm_mmu *mmu = vcpu->arch.mmu;
3353 u8 shadow_root_level = mmu->shadow_root_level;
3358 write_lock(&vcpu->kvm->mmu_lock);
3359 r = make_mmu_pages_available(vcpu);
3363 if (is_tdp_mmu_enabled(vcpu->kvm)) {
3364 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3365 mmu->root_hpa = root;
3366 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3367 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true);
3368 mmu->root_hpa = root;
3369 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3370 if (WARN_ON_ONCE(!mmu->pae_root)) {
3375 for (i = 0; i < 4; ++i) {
3376 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3378 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3379 i << 30, PT32_ROOT_LEVEL, true);
3380 mmu->pae_root[i] = root | PT_PRESENT_MASK |
3383 mmu->root_hpa = __pa(mmu->pae_root);
3385 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level);
3390 /* root_pgd is ignored for direct MMUs. */
3393 write_unlock(&vcpu->kvm->mmu_lock);
3397 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3399 struct kvm_mmu *mmu = vcpu->arch.mmu;
3400 u64 pdptrs[4], pm_mask;
3401 gfn_t root_gfn, root_pgd;
3406 root_pgd = mmu->get_guest_pgd(vcpu);
3407 root_gfn = root_pgd >> PAGE_SHIFT;
3409 if (mmu_check_root(vcpu, root_gfn))
3413 * On SVM, reading PDPTRs might access guest memory, which might fault
3414 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3416 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3417 for (i = 0; i < 4; ++i) {
3418 pdptrs[i] = mmu->get_pdptr(vcpu, i);
3419 if (!(pdptrs[i] & PT_PRESENT_MASK))
3422 if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT))
3427 r = alloc_all_memslots_rmaps(vcpu->kvm);
3431 write_lock(&vcpu->kvm->mmu_lock);
3432 r = make_mmu_pages_available(vcpu);
3437 * Do we shadow a long mode page table? If so we need to
3438 * write-protect the guests page table root.
3440 if (mmu->root_level >= PT64_ROOT_4LEVEL) {
3441 root = mmu_alloc_root(vcpu, root_gfn, 0,
3442 mmu->shadow_root_level, false);
3443 mmu->root_hpa = root;
3447 if (WARN_ON_ONCE(!mmu->pae_root)) {
3453 * We shadow a 32 bit page table. This may be a legacy 2-level
3454 * or a PAE 3-level page table. In either case we need to be aware that
3455 * the shadow page table may be a PAE or a long mode page table.
3457 pm_mask = PT_PRESENT_MASK | shadow_me_mask;
3458 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3459 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3461 if (WARN_ON_ONCE(!mmu->pml4_root)) {
3466 mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask;
3469 for (i = 0; i < 4; ++i) {
3470 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3472 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3473 if (!(pdptrs[i] & PT_PRESENT_MASK)) {
3474 mmu->pae_root[i] = INVALID_PAE_ROOT;
3477 root_gfn = pdptrs[i] >> PAGE_SHIFT;
3480 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3481 PT32_ROOT_LEVEL, false);
3482 mmu->pae_root[i] = root | pm_mask;
3485 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3486 mmu->root_hpa = __pa(mmu->pml4_root);
3488 mmu->root_hpa = __pa(mmu->pae_root);
3491 mmu->root_pgd = root_pgd;
3493 write_unlock(&vcpu->kvm->mmu_lock);
3498 static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu)
3500 struct kvm_mmu *mmu = vcpu->arch.mmu;
3501 u64 *pml4_root, *pae_root;
3504 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3505 * tables are allocated and initialized at root creation as there is no
3506 * equivalent level in the guest's NPT to shadow. Allocate the tables
3507 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
3509 if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL ||
3510 mmu->shadow_root_level < PT64_ROOT_4LEVEL)
3514 * This mess only works with 4-level paging and needs to be updated to
3515 * work with 5-level paging.
3517 if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL))
3520 if (mmu->pae_root && mmu->pml4_root)
3524 * The special roots should always be allocated in concert. Yell and
3525 * bail if KVM ends up in a state where only one of the roots is valid.
3527 if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root))
3531 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3532 * doesn't need to be decrypted.
3534 pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3538 pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3540 free_page((unsigned long)pae_root);
3544 mmu->pae_root = pae_root;
3545 mmu->pml4_root = pml4_root;
3550 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3553 struct kvm_mmu_page *sp;
3555 if (vcpu->arch.mmu->direct_map)
3558 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3561 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3563 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3564 hpa_t root = vcpu->arch.mmu->root_hpa;
3565 sp = to_shadow_page(root);
3568 * Even if another CPU was marking the SP as unsync-ed
3569 * simultaneously, any guest page table changes are not
3570 * guaranteed to be visible anyway until this VCPU issues a TLB
3571 * flush strictly after those changes are made. We only need to
3572 * ensure that the other CPU sets these flags before any actual
3573 * changes to the page tables are made. The comments in
3574 * mmu_try_to_unsync_pages() describe what could go wrong if
3575 * this requirement isn't satisfied.
3577 if (!smp_load_acquire(&sp->unsync) &&
3578 !smp_load_acquire(&sp->unsync_children))
3581 write_lock(&vcpu->kvm->mmu_lock);
3582 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3584 mmu_sync_children(vcpu, sp);
3586 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3587 write_unlock(&vcpu->kvm->mmu_lock);
3591 write_lock(&vcpu->kvm->mmu_lock);
3592 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3594 for (i = 0; i < 4; ++i) {
3595 hpa_t root = vcpu->arch.mmu->pae_root[i];
3597 if (IS_VALID_PAE_ROOT(root)) {
3598 root &= PT64_BASE_ADDR_MASK;
3599 sp = to_shadow_page(root);
3600 mmu_sync_children(vcpu, sp);
3604 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3605 write_unlock(&vcpu->kvm->mmu_lock);
3608 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3609 u32 access, struct x86_exception *exception)
3612 exception->error_code = 0;
3616 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3618 struct x86_exception *exception)
3621 exception->error_code = 0;
3622 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3625 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3628 * A nested guest cannot use the MMIO cache if it is using nested
3629 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3631 if (mmu_is_nested(vcpu))
3635 return vcpu_match_mmio_gpa(vcpu, addr);
3637 return vcpu_match_mmio_gva(vcpu, addr);
3641 * Return the level of the lowest level SPTE added to sptes.
3642 * That SPTE may be non-present.
3644 static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
3646 struct kvm_shadow_walk_iterator iterator;
3650 walk_shadow_page_lockless_begin(vcpu);
3652 for (shadow_walk_init(&iterator, vcpu, addr),
3653 *root_level = iterator.level;
3654 shadow_walk_okay(&iterator);
3655 __shadow_walk_next(&iterator, spte)) {
3656 leaf = iterator.level;
3657 spte = mmu_spte_get_lockless(iterator.sptep);
3661 if (!is_shadow_present_pte(spte))
3665 walk_shadow_page_lockless_end(vcpu);
3670 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3671 static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3673 u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
3674 struct rsvd_bits_validate *rsvd_check;
3675 int root, leaf, level;
3676 bool reserved = false;
3678 if (is_tdp_mmu(vcpu->arch.mmu))
3679 leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
3681 leaf = get_walk(vcpu, addr, sptes, &root);
3683 if (unlikely(leaf < 0)) {
3688 *sptep = sptes[leaf];
3691 * Skip reserved bits checks on the terminal leaf if it's not a valid
3692 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3693 * design, always have reserved bits set. The purpose of the checks is
3694 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3696 if (!is_shadow_present_pte(sptes[leaf]))
3699 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3701 for (level = root; level >= leaf; level--)
3702 reserved |= is_rsvd_spte(rsvd_check, sptes[level], level);
3705 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
3707 for (level = root; level >= leaf; level--)
3708 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3709 sptes[level], level,
3710 get_rsvd_bits(rsvd_check, sptes[level], level));
3716 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3721 if (mmio_info_in_cache(vcpu, addr, direct))
3722 return RET_PF_EMULATE;
3724 reserved = get_mmio_spte(vcpu, addr, &spte);
3725 if (WARN_ON(reserved))
3728 if (is_mmio_spte(spte)) {
3729 gfn_t gfn = get_mmio_spte_gfn(spte);
3730 unsigned int access = get_mmio_spte_access(spte);
3732 if (!check_mmio_spte(vcpu, spte))
3733 return RET_PF_INVALID;
3738 trace_handle_mmio_page_fault(addr, gfn, access);
3739 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3740 return RET_PF_EMULATE;
3744 * If the page table is zapped by other cpus, let CPU fault again on
3747 return RET_PF_RETRY;
3750 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3751 u32 error_code, gfn_t gfn)
3753 if (unlikely(error_code & PFERR_RSVD_MASK))
3756 if (!(error_code & PFERR_PRESENT_MASK) ||
3757 !(error_code & PFERR_WRITE_MASK))
3761 * guest is writing the page which is write tracked which can
3762 * not be fixed by page fault handler.
3764 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3770 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3772 struct kvm_shadow_walk_iterator iterator;
3775 walk_shadow_page_lockless_begin(vcpu);
3776 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3777 clear_sp_write_flooding_count(iterator.sptep);
3778 if (!is_shadow_present_pte(spte))
3781 walk_shadow_page_lockless_end(vcpu);
3784 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3787 struct kvm_arch_async_pf arch;
3789 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3791 arch.direct_map = vcpu->arch.mmu->direct_map;
3792 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3794 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3795 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3798 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3799 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva,
3800 bool write, bool *writable)
3802 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3806 * Retry the page fault if the gfn hit a memslot that is being deleted
3807 * or moved. This ensures any existing SPTEs for the old memslot will
3808 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3810 if (slot && (slot->flags & KVM_MEMSLOT_INVALID))
3813 /* Don't expose private memslots to L2. */
3814 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3815 *pfn = KVM_PFN_NOSLOT;
3821 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async,
3822 write, writable, hva);
3824 return false; /* *pfn has correct page already */
3826 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3827 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
3828 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3829 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
3830 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3832 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
3836 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL,
3837 write, writable, hva);
3841 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3842 bool prefault, int max_level, bool is_tdp)
3844 bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu);
3845 bool write = error_code & PFERR_WRITE_MASK;
3848 gfn_t gfn = gpa >> PAGE_SHIFT;
3849 unsigned long mmu_seq;
3854 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3855 return RET_PF_EMULATE;
3857 if (!is_tdp_mmu_fault) {
3858 r = fast_page_fault(vcpu, gpa, error_code);
3859 if (r != RET_PF_INVALID)
3863 r = mmu_topup_memory_caches(vcpu, false);
3867 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3870 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, &hva,
3871 write, &map_writable))
3872 return RET_PF_RETRY;
3874 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
3879 if (is_tdp_mmu_fault)
3880 read_lock(&vcpu->kvm->mmu_lock);
3882 write_lock(&vcpu->kvm->mmu_lock);
3884 if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva))
3886 r = make_mmu_pages_available(vcpu);
3890 if (is_tdp_mmu_fault)
3891 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
3894 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
3898 if (is_tdp_mmu_fault)
3899 read_unlock(&vcpu->kvm->mmu_lock);
3901 write_unlock(&vcpu->kvm->mmu_lock);
3902 kvm_release_pfn_clean(pfn);
3906 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
3907 u32 error_code, bool prefault)
3909 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
3911 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3912 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3913 PG_LEVEL_2M, false);
3916 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3917 u64 fault_address, char *insn, int insn_len)
3920 u32 flags = vcpu->arch.apf.host_apf_flags;
3922 #ifndef CONFIG_X86_64
3923 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3924 if (WARN_ON_ONCE(fault_address >> 32))
3928 vcpu->arch.l1tf_flush_l1d = true;
3930 trace_kvm_page_fault(fault_address, error_code);
3932 if (kvm_event_needs_reinjection(vcpu))
3933 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3934 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3936 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
3937 vcpu->arch.apf.host_apf_flags = 0;
3938 local_irq_disable();
3939 kvm_async_pf_task_wait_schedule(fault_address);
3942 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
3947 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3949 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3954 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3955 max_level > PG_LEVEL_4K;
3957 int page_num = KVM_PAGES_PER_HPAGE(max_level);
3958 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
3960 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
3964 return direct_page_fault(vcpu, gpa, error_code, prefault,
3968 static void nonpaging_init_context(struct kvm_mmu *context)
3970 context->page_fault = nonpaging_page_fault;
3971 context->gva_to_gpa = nonpaging_gva_to_gpa;
3972 context->sync_page = nonpaging_sync_page;
3973 context->invlpg = NULL;
3974 context->direct_map = true;
3977 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
3978 union kvm_mmu_page_role role)
3980 return (role.direct || pgd == root->pgd) &&
3981 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
3982 role.word == to_shadow_page(root->hpa)->role.word;
3986 * Find out if a previously cached root matching the new pgd/role is available.
3987 * The current root is also inserted into the cache.
3988 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3990 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3991 * false is returned. This root should now be freed by the caller.
3993 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3994 union kvm_mmu_page_role new_role)
3997 struct kvm_mmu_root_info root;
3998 struct kvm_mmu *mmu = vcpu->arch.mmu;
4000 root.pgd = mmu->root_pgd;
4001 root.hpa = mmu->root_hpa;
4003 if (is_root_usable(&root, new_pgd, new_role))
4006 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4007 swap(root, mmu->prev_roots[i]);
4009 if (is_root_usable(&root, new_pgd, new_role))
4013 mmu->root_hpa = root.hpa;
4014 mmu->root_pgd = root.pgd;
4016 return i < KVM_MMU_NUM_PREV_ROOTS;
4019 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4020 union kvm_mmu_page_role new_role)
4022 struct kvm_mmu *mmu = vcpu->arch.mmu;
4025 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4026 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4027 * later if necessary.
4029 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4030 mmu->root_level >= PT64_ROOT_4LEVEL)
4031 return cached_root_available(vcpu, new_pgd, new_role);
4036 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4037 union kvm_mmu_page_role new_role)
4039 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
4040 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
4045 * It's possible that the cached previous root page is obsolete because
4046 * of a change in the MMU generation number. However, changing the
4047 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
4048 * free the root set here and allocate a new one.
4050 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
4052 if (force_flush_and_sync_on_reuse) {
4053 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4054 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
4058 * The last MMIO access's GVA and GPA are cached in the VCPU. When
4059 * switching to a new CR3, that GVA->GPA mapping may no longer be
4060 * valid. So clear any cached MMIO info even when we don't need to sync
4061 * the shadow page tables.
4063 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4066 * If this is a direct root page, it doesn't have a write flooding
4067 * count. Otherwise, clear the write flooding count.
4069 if (!new_role.direct)
4070 __clear_sp_write_flooding_count(
4071 to_shadow_page(vcpu->arch.mmu->root_hpa));
4074 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd)
4076 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu));
4078 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
4080 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4082 return kvm_read_cr3(vcpu);
4085 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4086 unsigned int access, int *nr_present)
4088 if (unlikely(is_mmio_spte(*sptep))) {
4089 if (gfn != get_mmio_spte_gfn(*sptep)) {
4090 mmu_spte_clear_no_track(sptep);
4095 mark_mmio_spte(vcpu, sptep, gfn, access);
4102 #define PTTYPE_EPT 18 /* arbitrary */
4103 #define PTTYPE PTTYPE_EPT
4104 #include "paging_tmpl.h"
4108 #include "paging_tmpl.h"
4112 #include "paging_tmpl.h"
4116 __reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check,
4117 u64 pa_bits_rsvd, int level, bool nx, bool gbpages,
4120 u64 gbpages_bit_rsvd = 0;
4121 u64 nonleaf_bit8_rsvd = 0;
4124 rsvd_check->bad_mt_xwr = 0;
4127 gbpages_bit_rsvd = rsvd_bits(7, 7);
4129 if (level == PT32E_ROOT_LEVEL)
4130 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62);
4132 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4134 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4136 high_bits_rsvd |= rsvd_bits(63, 63);
4139 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4140 * leaf entries) on AMD CPUs only.
4143 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4146 case PT32_ROOT_LEVEL:
4147 /* no rsvd bits for 2 level 4K page table entries */
4148 rsvd_check->rsvd_bits_mask[0][1] = 0;
4149 rsvd_check->rsvd_bits_mask[0][0] = 0;
4150 rsvd_check->rsvd_bits_mask[1][0] =
4151 rsvd_check->rsvd_bits_mask[0][0];
4154 rsvd_check->rsvd_bits_mask[1][1] = 0;
4158 if (is_cpuid_PSE36())
4159 /* 36bits PSE 4MB page */
4160 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4162 /* 32 bits PSE 4MB page */
4163 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4165 case PT32E_ROOT_LEVEL:
4166 rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
4169 rsvd_bits(1, 2); /* PDPTE */
4170 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
4171 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
4172 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4173 rsvd_bits(13, 20); /* large page */
4174 rsvd_check->rsvd_bits_mask[1][0] =
4175 rsvd_check->rsvd_bits_mask[0][0];
4177 case PT64_ROOT_5LEVEL:
4178 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd |
4181 rsvd_check->rsvd_bits_mask[1][4] =
4182 rsvd_check->rsvd_bits_mask[0][4];
4184 case PT64_ROOT_4LEVEL:
4185 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd |
4188 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd |
4190 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd;
4191 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4192 rsvd_check->rsvd_bits_mask[1][3] =
4193 rsvd_check->rsvd_bits_mask[0][3];
4194 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd |
4197 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4198 rsvd_bits(13, 20); /* large page */
4199 rsvd_check->rsvd_bits_mask[1][0] =
4200 rsvd_check->rsvd_bits_mask[0][0];
4205 static bool guest_can_use_gbpages(struct kvm_vcpu *vcpu)
4208 * If TDP is enabled, let the guest use GBPAGES if they're supported in
4209 * hardware. The hardware page walker doesn't let KVM disable GBPAGES,
4210 * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA
4211 * walk for performance and complexity reasons. Not to mention KVM
4212 * _can't_ solve the problem because GVA->GPA walks aren't visible to
4213 * KVM once a TDP translation is installed. Mimic hardware behavior so
4214 * that KVM's is at least consistent, i.e. doesn't randomly inject #PF.
4216 return tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) :
4217 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES);
4220 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4221 struct kvm_mmu *context)
4223 __reset_rsvds_bits_mask(&context->guest_rsvd_check,
4224 vcpu->arch.reserved_gpa_bits,
4225 context->root_level, is_efer_nx(context),
4226 guest_can_use_gbpages(vcpu),
4227 is_cr4_pse(context),
4228 guest_cpuid_is_amd_or_hygon(vcpu));
4232 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4233 u64 pa_bits_rsvd, bool execonly)
4235 u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4238 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
4239 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
4240 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6);
4241 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6);
4242 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4245 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4246 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4247 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29);
4248 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20);
4249 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4251 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4252 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4253 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4254 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4255 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4257 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4258 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4260 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4263 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4264 struct kvm_mmu *context, bool execonly)
4266 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4267 vcpu->arch.reserved_gpa_bits, execonly);
4270 static inline u64 reserved_hpa_bits(void)
4272 return rsvd_bits(shadow_phys_bits, 63);
4276 * the page table on host is the shadow page table for the page
4277 * table in guest or amd nested guest, its mmu features completely
4278 * follow the features in guest.
4280 static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4281 struct kvm_mmu *context)
4284 * KVM uses NX when TDP is disabled to handle a variety of scenarios,
4285 * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
4286 * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
4287 * The iTLB multi-hit workaround can be toggled at any time, so assume
4288 * NX can be used by any non-nested shadow MMU to avoid having to reset
4289 * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
4291 bool uses_nx = is_efer_nx(context) || !tdp_enabled;
4293 /* @amd adds a check on bit of SPTEs, which KVM shouldn't use anyways. */
4295 /* KVM doesn't use 2-level page tables for the shadow MMU. */
4296 bool is_pse = false;
4297 struct rsvd_bits_validate *shadow_zero_check;
4300 WARN_ON_ONCE(context->shadow_root_level < PT32E_ROOT_LEVEL);
4302 shadow_zero_check = &context->shadow_zero_check;
4303 __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
4304 context->shadow_root_level, uses_nx,
4305 guest_can_use_gbpages(vcpu), is_pse, is_amd);
4307 if (!shadow_me_mask)
4310 for (i = context->shadow_root_level; --i >= 0;) {
4311 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4312 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4317 static inline bool boot_cpu_is_amd(void)
4319 WARN_ON_ONCE(!tdp_enabled);
4320 return shadow_x_mask == 0;
4324 * the direct page table on host, use as much mmu features as
4325 * possible, however, kvm currently does not do execution-protection.
4328 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4329 struct kvm_mmu *context)
4331 struct rsvd_bits_validate *shadow_zero_check;
4334 shadow_zero_check = &context->shadow_zero_check;
4336 if (boot_cpu_is_amd())
4337 __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
4338 context->shadow_root_level, false,
4339 boot_cpu_has(X86_FEATURE_GBPAGES),
4342 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4343 reserved_hpa_bits(), false);
4345 if (!shadow_me_mask)
4348 for (i = context->shadow_root_level; --i >= 0;) {
4349 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4350 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4355 * as the comments in reset_shadow_zero_bits_mask() except it
4356 * is the shadow page table for intel nested guest.
4359 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4360 struct kvm_mmu *context, bool execonly)
4362 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4363 reserved_hpa_bits(), execonly);
4366 #define BYTE_MASK(access) \
4367 ((1 & (access) ? 2 : 0) | \
4368 (2 & (access) ? 4 : 0) | \
4369 (3 & (access) ? 8 : 0) | \
4370 (4 & (access) ? 16 : 0) | \
4371 (5 & (access) ? 32 : 0) | \
4372 (6 & (access) ? 64 : 0) | \
4373 (7 & (access) ? 128 : 0))
4376 static void update_permission_bitmask(struct kvm_mmu *mmu, bool ept)
4380 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4381 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4382 const u8 u = BYTE_MASK(ACC_USER_MASK);
4384 bool cr4_smep = is_cr4_smep(mmu);
4385 bool cr4_smap = is_cr4_smap(mmu);
4386 bool cr0_wp = is_cr0_wp(mmu);
4387 bool efer_nx = is_efer_nx(mmu);
4389 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4390 unsigned pfec = byte << 1;
4393 * Each "*f" variable has a 1 bit for each UWX value
4394 * that causes a fault with the given PFEC.
4397 /* Faults from writes to non-writable pages */
4398 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4399 /* Faults from user mode accesses to supervisor pages */
4400 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4401 /* Faults from fetches of non-executable pages*/
4402 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4403 /* Faults from kernel mode fetches of user pages */
4405 /* Faults from kernel mode accesses of user pages */
4409 /* Faults from kernel mode accesses to user pages */
4410 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4412 /* Not really needed: !nx will cause pte.nx to fault */
4416 /* Allow supervisor writes if !cr0.wp */
4418 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4420 /* Disallow supervisor fetches of user code if cr4.smep */
4422 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4425 * SMAP:kernel-mode data accesses from user-mode
4426 * mappings should fault. A fault is considered
4427 * as a SMAP violation if all of the following
4428 * conditions are true:
4429 * - X86_CR4_SMAP is set in CR4
4430 * - A user page is accessed
4431 * - The access is not a fetch
4432 * - Page fault in kernel mode
4433 * - if CPL = 3 or X86_EFLAGS_AC is clear
4435 * Here, we cover the first three conditions.
4436 * The fourth is computed dynamically in permission_fault();
4437 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4438 * *not* subject to SMAP restrictions.
4441 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4444 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4449 * PKU is an additional mechanism by which the paging controls access to
4450 * user-mode addresses based on the value in the PKRU register. Protection
4451 * key violations are reported through a bit in the page fault error code.
4452 * Unlike other bits of the error code, the PK bit is not known at the
4453 * call site of e.g. gva_to_gpa; it must be computed directly in
4454 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4455 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4457 * In particular the following conditions come from the error code, the
4458 * page tables and the machine state:
4459 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4460 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4461 * - PK is always zero if U=0 in the page tables
4462 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4464 * The PKRU bitmask caches the result of these four conditions. The error
4465 * code (minus the P bit) and the page table's U bit form an index into the
4466 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4467 * with the two bits of the PKRU register corresponding to the protection key.
4468 * For the first three conditions above the bits will be 00, thus masking
4469 * away both AD and WD. For all reads or if the last condition holds, WD
4470 * only will be masked away.
4472 static void update_pkru_bitmask(struct kvm_mmu *mmu)
4477 if (!is_cr4_pke(mmu)) {
4482 wp = is_cr0_wp(mmu);
4484 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4485 unsigned pfec, pkey_bits;
4486 bool check_pkey, check_write, ff, uf, wf, pte_user;
4489 ff = pfec & PFERR_FETCH_MASK;
4490 uf = pfec & PFERR_USER_MASK;
4491 wf = pfec & PFERR_WRITE_MASK;
4493 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4494 pte_user = pfec & PFERR_RSVD_MASK;
4497 * Only need to check the access which is not an
4498 * instruction fetch and is to a user page.
4500 check_pkey = (!ff && pte_user);
4502 * write access is controlled by PKRU if it is a
4503 * user access or CR0.WP = 1.
4505 check_write = check_pkey && wf && (uf || wp);
4507 /* PKRU.AD stops both read and write access. */
4508 pkey_bits = !!check_pkey;
4509 /* PKRU.WD stops write access. */
4510 pkey_bits |= (!!check_write) << 1;
4512 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4516 static void reset_guest_paging_metadata(struct kvm_vcpu *vcpu,
4517 struct kvm_mmu *mmu)
4519 if (!is_cr0_pg(mmu))
4522 reset_rsvds_bits_mask(vcpu, mmu);
4523 update_permission_bitmask(mmu, false);
4524 update_pkru_bitmask(mmu);
4527 static void paging64_init_context(struct kvm_mmu *context)
4529 context->page_fault = paging64_page_fault;
4530 context->gva_to_gpa = paging64_gva_to_gpa;
4531 context->sync_page = paging64_sync_page;
4532 context->invlpg = paging64_invlpg;
4533 context->direct_map = false;
4536 static void paging32_init_context(struct kvm_mmu *context)
4538 context->page_fault = paging32_page_fault;
4539 context->gva_to_gpa = paging32_gva_to_gpa;
4540 context->sync_page = paging32_sync_page;
4541 context->invlpg = paging32_invlpg;
4542 context->direct_map = false;
4545 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu,
4546 struct kvm_mmu_role_regs *regs)
4548 union kvm_mmu_extended_role ext = {0};
4550 if (____is_cr0_pg(regs)) {
4552 ext.cr4_pae = ____is_cr4_pae(regs);
4553 ext.cr4_smep = ____is_cr4_smep(regs);
4554 ext.cr4_smap = ____is_cr4_smap(regs);
4555 ext.cr4_pse = ____is_cr4_pse(regs);
4557 /* PKEY and LA57 are active iff long mode is active. */
4558 ext.cr4_pke = ____is_efer_lma(regs) && ____is_cr4_pke(regs);
4559 ext.cr4_la57 = ____is_efer_lma(regs) && ____is_cr4_la57(regs);
4567 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4568 struct kvm_mmu_role_regs *regs,
4571 union kvm_mmu_role role = {0};
4573 role.base.access = ACC_ALL;
4574 if (____is_cr0_pg(regs)) {
4575 role.base.efer_nx = ____is_efer_nx(regs);
4576 role.base.cr0_wp = ____is_cr0_wp(regs);
4578 role.base.smm = is_smm(vcpu);
4579 role.base.guest_mode = is_guest_mode(vcpu);
4584 role.ext = kvm_calc_mmu_role_ext(vcpu, regs);
4589 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4591 /* Use 5-level TDP if and only if it's useful/necessary. */
4592 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4595 return max_tdp_level;
4598 static union kvm_mmu_role
4599 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu,
4600 struct kvm_mmu_role_regs *regs, bool base_only)
4602 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
4604 role.base.ad_disabled = (shadow_accessed_mask == 0);
4605 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4606 role.base.direct = true;
4607 role.base.gpte_is_8_bytes = true;
4612 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4614 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4615 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4616 union kvm_mmu_role new_role =
4617 kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, false);
4619 if (new_role.as_u64 == context->mmu_role.as_u64)
4622 context->mmu_role.as_u64 = new_role.as_u64;
4623 context->page_fault = kvm_tdp_page_fault;
4624 context->sync_page = nonpaging_sync_page;
4625 context->invlpg = NULL;
4626 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4627 context->direct_map = true;
4628 context->get_guest_pgd = get_cr3;
4629 context->get_pdptr = kvm_pdptr_read;
4630 context->inject_page_fault = kvm_inject_page_fault;
4631 context->root_level = role_regs_to_root_level(®s);
4633 if (!is_cr0_pg(context))
4634 context->gva_to_gpa = nonpaging_gva_to_gpa;
4635 else if (is_cr4_pae(context))
4636 context->gva_to_gpa = paging64_gva_to_gpa;
4638 context->gva_to_gpa = paging32_gva_to_gpa;
4640 reset_guest_paging_metadata(vcpu, context);
4641 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4644 static union kvm_mmu_role
4645 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu,
4646 struct kvm_mmu_role_regs *regs, bool base_only)
4648 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
4650 role.base.smep_andnot_wp = role.ext.cr4_smep && !____is_cr0_wp(regs);
4651 role.base.smap_andnot_wp = role.ext.cr4_smap && !____is_cr0_wp(regs);
4652 role.base.gpte_is_8_bytes = ____is_cr0_pg(regs) && ____is_cr4_pae(regs);
4657 static union kvm_mmu_role
4658 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu,
4659 struct kvm_mmu_role_regs *regs, bool base_only)
4661 union kvm_mmu_role role =
4662 kvm_calc_shadow_root_page_role_common(vcpu, regs, base_only);
4664 role.base.direct = !____is_cr0_pg(regs);
4666 if (!____is_efer_lma(regs))
4667 role.base.level = PT32E_ROOT_LEVEL;
4668 else if (____is_cr4_la57(regs))
4669 role.base.level = PT64_ROOT_5LEVEL;
4671 role.base.level = PT64_ROOT_4LEVEL;
4676 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4677 struct kvm_mmu_role_regs *regs,
4678 union kvm_mmu_role new_role)
4680 if (new_role.as_u64 == context->mmu_role.as_u64)
4683 context->mmu_role.as_u64 = new_role.as_u64;
4685 if (!is_cr0_pg(context))
4686 nonpaging_init_context(context);
4687 else if (is_cr4_pae(context))
4688 paging64_init_context(context);
4690 paging32_init_context(context);
4691 context->root_level = role_regs_to_root_level(regs);
4693 reset_guest_paging_metadata(vcpu, context);
4694 context->shadow_root_level = new_role.base.level;
4696 reset_shadow_zero_bits_mask(vcpu, context);
4699 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu,
4700 struct kvm_mmu_role_regs *regs)
4702 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4703 union kvm_mmu_role new_role =
4704 kvm_calc_shadow_mmu_root_page_role(vcpu, regs, false);
4706 shadow_mmu_init_context(vcpu, context, regs, new_role);
4709 static union kvm_mmu_role
4710 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu,
4711 struct kvm_mmu_role_regs *regs)
4713 union kvm_mmu_role role =
4714 kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
4716 role.base.direct = false;
4717 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4722 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
4723 unsigned long cr4, u64 efer, gpa_t nested_cr3)
4725 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4726 struct kvm_mmu_role_regs regs = {
4731 union kvm_mmu_role new_role;
4733 new_role = kvm_calc_shadow_npt_root_page_role(vcpu, ®s);
4735 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base);
4737 shadow_mmu_init_context(vcpu, context, ®s, new_role);
4739 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4741 static union kvm_mmu_role
4742 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4743 bool execonly, u8 level)
4745 union kvm_mmu_role role = {0};
4747 /* SMM flag is inherited from root_mmu */
4748 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4750 role.base.level = level;
4751 role.base.gpte_is_8_bytes = true;
4752 role.base.direct = false;
4753 role.base.ad_disabled = !accessed_dirty;
4754 role.base.guest_mode = true;
4755 role.base.access = ACC_ALL;
4757 /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */
4759 role.ext.execonly = execonly;
4765 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4766 bool accessed_dirty, gpa_t new_eptp)
4768 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4769 u8 level = vmx_eptp_page_walk_level(new_eptp);
4770 union kvm_mmu_role new_role =
4771 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4774 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base);
4776 if (new_role.as_u64 == context->mmu_role.as_u64)
4779 context->mmu_role.as_u64 = new_role.as_u64;
4781 context->shadow_root_level = level;
4783 context->ept_ad = accessed_dirty;
4784 context->page_fault = ept_page_fault;
4785 context->gva_to_gpa = ept_gva_to_gpa;
4786 context->sync_page = ept_sync_page;
4787 context->invlpg = ept_invlpg;
4788 context->root_level = level;
4789 context->direct_map = false;
4791 update_permission_bitmask(context, true);
4792 update_pkru_bitmask(context);
4793 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4794 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4796 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4798 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4800 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4801 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4803 kvm_init_shadow_mmu(vcpu, ®s);
4805 context->get_guest_pgd = get_cr3;
4806 context->get_pdptr = kvm_pdptr_read;
4807 context->inject_page_fault = kvm_inject_page_fault;
4810 static union kvm_mmu_role
4811 kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu, struct kvm_mmu_role_regs *regs)
4813 union kvm_mmu_role role;
4815 role = kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
4818 * Nested MMUs are used only for walking L2's gva->gpa, they never have
4819 * shadow pages of their own and so "direct" has no meaning. Set it
4820 * to "true" to try to detect bogus usage of the nested MMU.
4822 role.base.direct = true;
4823 role.base.level = role_regs_to_root_level(regs);
4827 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4829 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4830 union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu, ®s);
4831 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4833 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4836 g_context->mmu_role.as_u64 = new_role.as_u64;
4837 g_context->get_guest_pgd = get_cr3;
4838 g_context->get_pdptr = kvm_pdptr_read;
4839 g_context->inject_page_fault = kvm_inject_page_fault;
4840 g_context->root_level = new_role.base.level;
4843 * L2 page tables are never shadowed, so there is no need to sync
4846 g_context->invlpg = NULL;
4849 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4850 * L1's nested page tables (e.g. EPT12). The nested translation
4851 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4852 * L2's page tables as the first level of translation and L1's
4853 * nested page tables as the second level of translation. Basically
4854 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4856 if (!is_paging(vcpu))
4857 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4858 else if (is_long_mode(vcpu))
4859 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4860 else if (is_pae(vcpu))
4861 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4863 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4865 reset_guest_paging_metadata(vcpu, g_context);
4868 void kvm_init_mmu(struct kvm_vcpu *vcpu)
4870 if (mmu_is_nested(vcpu))
4871 init_kvm_nested_mmu(vcpu);
4872 else if (tdp_enabled)
4873 init_kvm_tdp_mmu(vcpu);
4875 init_kvm_softmmu(vcpu);
4877 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4879 static union kvm_mmu_page_role
4880 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4882 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4883 union kvm_mmu_role role;
4886 role = kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, true);
4888 role = kvm_calc_shadow_mmu_root_page_role(vcpu, ®s, true);
4893 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu)
4896 * Invalidate all MMU roles to force them to reinitialize as CPUID
4897 * information is factored into reserved bit calculations.
4899 vcpu->arch.root_mmu.mmu_role.ext.valid = 0;
4900 vcpu->arch.guest_mmu.mmu_role.ext.valid = 0;
4901 vcpu->arch.nested_mmu.mmu_role.ext.valid = 0;
4902 kvm_mmu_reset_context(vcpu);
4905 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
4906 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
4907 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
4908 * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise
4909 * sweep the problem under the rug.
4911 * KVM's horrific CPUID ABI makes the problem all but impossible to
4912 * solve, as correctly handling multiple vCPU models (with respect to
4913 * paging and physical address properties) in a single VM would require
4914 * tracking all relevant CPUID information in kvm_mmu_page_role. That
4915 * is very undesirable as it would double the memory requirements for
4916 * gfn_track (see struct kvm_mmu_page_role comments), and in practice
4917 * no sane VMM mucks with the core vCPU model on the fly.
4919 if (vcpu->arch.last_vmentry_cpu != -1) {
4920 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n");
4921 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n");
4925 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4927 kvm_mmu_unload(vcpu);
4930 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4932 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4936 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
4939 r = mmu_alloc_special_roots(vcpu);
4942 if (vcpu->arch.mmu->direct_map)
4943 r = mmu_alloc_direct_roots(vcpu);
4945 r = mmu_alloc_shadow_roots(vcpu);
4949 kvm_mmu_sync_roots(vcpu);
4951 kvm_mmu_load_pgd(vcpu);
4952 static_call(kvm_x86_tlb_flush_current)(vcpu);
4957 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4959 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
4960 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
4961 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4962 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
4965 static bool need_remote_flush(u64 old, u64 new)
4967 if (!is_shadow_present_pte(old))
4969 if (!is_shadow_present_pte(new))
4971 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4973 old ^= shadow_nx_mask;
4974 new ^= shadow_nx_mask;
4975 return (old & ~new & PT64_PERM_MASK) != 0;
4978 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4985 * Assume that the pte write on a page table of the same type
4986 * as the current vcpu paging mode since we update the sptes only
4987 * when they have the same mode.
4989 if (is_pae(vcpu) && *bytes == 4) {
4990 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4995 if (*bytes == 4 || *bytes == 8) {
4996 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5005 * If we're seeing too many writes to a page, it may no longer be a page table,
5006 * or we may be forking, in which case it is better to unmap the page.
5008 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5011 * Skip write-flooding detected for the sp whose level is 1, because
5012 * it can become unsync, then the guest page is not write-protected.
5014 if (sp->role.level == PG_LEVEL_4K)
5017 atomic_inc(&sp->write_flooding_count);
5018 return atomic_read(&sp->write_flooding_count) >= 3;
5022 * Misaligned accesses are too much trouble to fix up; also, they usually
5023 * indicate a page is not used as a page table.
5025 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5028 unsigned offset, pte_size, misaligned;
5030 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5031 gpa, bytes, sp->role.word);
5033 offset = offset_in_page(gpa);
5034 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5037 * Sometimes, the OS only writes the last one bytes to update status
5038 * bits, for example, in linux, andb instruction is used in clear_bit().
5040 if (!(offset & (pte_size - 1)) && bytes == 1)
5043 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5044 misaligned |= bytes < 4;
5049 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5051 unsigned page_offset, quadrant;
5055 page_offset = offset_in_page(gpa);
5056 level = sp->role.level;
5058 if (!sp->role.gpte_is_8_bytes) {
5059 page_offset <<= 1; /* 32->64 */
5061 * A 32-bit pde maps 4MB while the shadow pdes map
5062 * only 2MB. So we need to double the offset again
5063 * and zap two pdes instead of one.
5065 if (level == PT32_ROOT_LEVEL) {
5066 page_offset &= ~7; /* kill rounding error */
5070 quadrant = page_offset >> PAGE_SHIFT;
5071 page_offset &= ~PAGE_MASK;
5072 if (quadrant != sp->role.quadrant)
5076 spte = &sp->spt[page_offset / sizeof(*spte)];
5080 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5081 const u8 *new, int bytes,
5082 struct kvm_page_track_notifier_node *node)
5084 gfn_t gfn = gpa >> PAGE_SHIFT;
5085 struct kvm_mmu_page *sp;
5086 LIST_HEAD(invalid_list);
5087 u64 entry, gentry, *spte;
5089 bool remote_flush, local_flush;
5092 * If we don't have indirect shadow pages, it means no page is
5093 * write-protected, so we can exit simply.
5095 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5098 remote_flush = local_flush = false;
5100 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5103 * No need to care whether allocation memory is successful
5104 * or not since pte prefetch is skipped if it does not have
5105 * enough objects in the cache.
5107 mmu_topup_memory_caches(vcpu, true);
5109 write_lock(&vcpu->kvm->mmu_lock);
5111 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5113 ++vcpu->kvm->stat.mmu_pte_write;
5114 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5116 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5117 if (detect_write_misaligned(sp, gpa, bytes) ||
5118 detect_write_flooding(sp)) {
5119 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5120 ++vcpu->kvm->stat.mmu_flooded;
5124 spte = get_written_sptes(sp, gpa, &npte);
5131 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
5132 if (gentry && sp->role.level != PG_LEVEL_4K)
5133 ++vcpu->kvm->stat.mmu_pde_zapped;
5134 if (need_remote_flush(entry, *spte))
5135 remote_flush = true;
5139 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5140 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5141 write_unlock(&vcpu->kvm->mmu_lock);
5144 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5145 void *insn, int insn_len)
5147 int r, emulation_type = EMULTYPE_PF;
5148 bool direct = vcpu->arch.mmu->direct_map;
5150 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5151 return RET_PF_RETRY;
5154 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5155 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5156 if (r == RET_PF_EMULATE)
5160 if (r == RET_PF_INVALID) {
5161 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5162 lower_32_bits(error_code), false);
5163 if (WARN_ON_ONCE(r == RET_PF_INVALID))
5169 if (r != RET_PF_EMULATE)
5173 * Before emulating the instruction, check if the error code
5174 * was due to a RO violation while translating the guest page.
5175 * This can occur when using nested virtualization with nested
5176 * paging in both guests. If true, we simply unprotect the page
5177 * and resume the guest.
5179 if (vcpu->arch.mmu->direct_map &&
5180 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5181 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5186 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5187 * optimistically try to just unprotect the page and let the processor
5188 * re-execute the instruction that caused the page fault. Do not allow
5189 * retrying MMIO emulation, as it's not only pointless but could also
5190 * cause us to enter an infinite loop because the processor will keep
5191 * faulting on the non-existent MMIO address. Retrying an instruction
5192 * from a nested guest is also pointless and dangerous as we are only
5193 * explicitly shadowing L1's page tables, i.e. unprotecting something
5194 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5196 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5197 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5199 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5202 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5204 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5205 gva_t gva, hpa_t root_hpa)
5209 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5210 if (mmu != &vcpu->arch.guest_mmu) {
5211 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5212 if (is_noncanonical_address(gva, vcpu))
5215 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5221 if (root_hpa == INVALID_PAGE) {
5222 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5225 * INVLPG is required to invalidate any global mappings for the VA,
5226 * irrespective of PCID. Since it would take us roughly similar amount
5227 * of work to determine whether any of the prev_root mappings of the VA
5228 * is marked global, or to just sync it blindly, so we might as well
5229 * just always sync it.
5231 * Mappings not reachable via the current cr3 or the prev_roots will be
5232 * synced when switching to that cr3, so nothing needs to be done here
5235 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5236 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5237 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5239 mmu->invlpg(vcpu, gva, root_hpa);
5243 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5245 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
5246 ++vcpu->stat.invlpg;
5248 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5251 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5253 struct kvm_mmu *mmu = vcpu->arch.mmu;
5254 bool tlb_flush = false;
5257 if (pcid == kvm_get_active_pcid(vcpu)) {
5258 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5262 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5263 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5264 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5265 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5271 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5273 ++vcpu->stat.invlpg;
5276 * Mappings not reachable via the current cr3 or the prev_roots will be
5277 * synced when switching to that cr3, so nothing needs to be done here
5282 void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
5283 int tdp_huge_page_level)
5285 tdp_enabled = enable_tdp;
5286 max_tdp_level = tdp_max_root_level;
5289 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5290 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5291 * the kernel is not. But, KVM never creates a page size greater than
5292 * what is used by the kernel for any given HVA, i.e. the kernel's
5293 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5296 max_huge_page_level = tdp_huge_page_level;
5297 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5298 max_huge_page_level = PG_LEVEL_1G;
5300 max_huge_page_level = PG_LEVEL_2M;
5302 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5304 /* The return value indicates if tlb flush on all vcpus is needed. */
5305 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head,
5306 struct kvm_memory_slot *slot);
5308 /* The caller should hold mmu-lock before calling this function. */
5309 static __always_inline bool
5310 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5311 slot_level_handler fn, int start_level, int end_level,
5312 gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield,
5315 struct slot_rmap_walk_iterator iterator;
5317 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5318 end_gfn, &iterator) {
5320 flush |= fn(kvm, iterator.rmap, memslot);
5322 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
5323 if (flush && flush_on_yield) {
5324 kvm_flush_remote_tlbs_with_address(kvm,
5326 iterator.gfn - start_gfn + 1);
5329 cond_resched_rwlock_write(&kvm->mmu_lock);
5336 static __always_inline bool
5337 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5338 slot_level_handler fn, int start_level, int end_level,
5339 bool flush_on_yield)
5341 return slot_handle_level_range(kvm, memslot, fn, start_level,
5342 end_level, memslot->base_gfn,
5343 memslot->base_gfn + memslot->npages - 1,
5344 flush_on_yield, false);
5347 static __always_inline bool
5348 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5349 slot_level_handler fn, bool flush_on_yield)
5351 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5352 PG_LEVEL_4K, flush_on_yield);
5355 static void free_mmu_pages(struct kvm_mmu *mmu)
5357 if (!tdp_enabled && mmu->pae_root)
5358 set_memory_encrypted((unsigned long)mmu->pae_root, 1);
5359 free_page((unsigned long)mmu->pae_root);
5360 free_page((unsigned long)mmu->pml4_root);
5363 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5368 mmu->root_hpa = INVALID_PAGE;
5370 mmu->translate_gpa = translate_gpa;
5371 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5372 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5375 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5376 * while the PDP table is a per-vCPU construct that's allocated at MMU
5377 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5378 * x86_64. Therefore we need to allocate the PDP table in the first
5379 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5380 * generally doesn't use PAE paging and can skip allocating the PDP
5381 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5382 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5383 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
5385 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5388 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5392 mmu->pae_root = page_address(page);
5395 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5396 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5397 * that KVM's writes and the CPU's reads get along. Note, this is
5398 * only necessary when using shadow paging, as 64-bit NPT can get at
5399 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5400 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5403 set_memory_decrypted((unsigned long)mmu->pae_root, 1);
5405 WARN_ON_ONCE(shadow_me_mask);
5407 for (i = 0; i < 4; ++i)
5408 mmu->pae_root[i] = INVALID_PAE_ROOT;
5413 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5417 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5418 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5420 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5421 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5423 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5425 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5426 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5428 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5430 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5434 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5436 goto fail_allocate_root;
5440 free_mmu_pages(&vcpu->arch.guest_mmu);
5444 #define BATCH_ZAP_PAGES 10
5445 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5447 struct kvm_mmu_page *sp, *node;
5448 int nr_zapped, batch = 0;
5451 list_for_each_entry_safe_reverse(sp, node,
5452 &kvm->arch.active_mmu_pages, link) {
5454 * No obsolete valid page exists before a newly created page
5455 * since active_mmu_pages is a FIFO list.
5457 if (!is_obsolete_sp(kvm, sp))
5461 * Invalid pages should never land back on the list of active
5462 * pages. Skip the bogus page, otherwise we'll get stuck in an
5463 * infinite loop if the page gets put back on the list (again).
5465 if (WARN_ON(sp->role.invalid))
5469 * No need to flush the TLB since we're only zapping shadow
5470 * pages with an obsolete generation number and all vCPUS have
5471 * loaded a new root, i.e. the shadow pages being zapped cannot
5472 * be in active use by the guest.
5474 if (batch >= BATCH_ZAP_PAGES &&
5475 cond_resched_rwlock_write(&kvm->mmu_lock)) {
5480 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5481 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5488 * Trigger a remote TLB flush before freeing the page tables to ensure
5489 * KVM is not in the middle of a lockless shadow page table walk, which
5490 * may reference the pages.
5492 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5496 * Fast invalidate all shadow pages and use lock-break technique
5497 * to zap obsolete pages.
5499 * It's required when memslot is being deleted or VM is being
5500 * destroyed, in these cases, we should ensure that KVM MMU does
5501 * not use any resource of the being-deleted slot or all slots
5502 * after calling the function.
5504 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5506 lockdep_assert_held(&kvm->slots_lock);
5508 write_lock(&kvm->mmu_lock);
5509 trace_kvm_mmu_zap_all_fast(kvm);
5512 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5513 * held for the entire duration of zapping obsolete pages, it's
5514 * impossible for there to be multiple invalid generations associated
5515 * with *valid* shadow pages at any given time, i.e. there is exactly
5516 * one valid generation and (at most) one invalid generation.
5518 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5520 /* In order to ensure all threads see this change when
5521 * handling the MMU reload signal, this must happen in the
5522 * same critical section as kvm_reload_remote_mmus, and
5523 * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages
5524 * could drop the MMU lock and yield.
5526 if (is_tdp_mmu_enabled(kvm))
5527 kvm_tdp_mmu_invalidate_all_roots(kvm);
5530 * Notify all vcpus to reload its shadow page table and flush TLB.
5531 * Then all vcpus will switch to new shadow page table with the new
5534 * Note: we need to do this under the protection of mmu_lock,
5535 * otherwise, vcpu would purge shadow page but miss tlb flush.
5537 kvm_reload_remote_mmus(kvm);
5539 kvm_zap_obsolete_pages(kvm);
5541 write_unlock(&kvm->mmu_lock);
5543 if (is_tdp_mmu_enabled(kvm)) {
5544 read_lock(&kvm->mmu_lock);
5545 kvm_tdp_mmu_zap_invalidated_roots(kvm);
5546 read_unlock(&kvm->mmu_lock);
5550 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5552 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5555 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5556 struct kvm_memory_slot *slot,
5557 struct kvm_page_track_notifier_node *node)
5559 kvm_mmu_zap_all_fast(kvm);
5562 void kvm_mmu_init_vm(struct kvm *kvm)
5564 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5566 spin_lock_init(&kvm->arch.mmu_unsync_pages_lock);
5568 if (!kvm_mmu_init_tdp_mmu(kvm))
5570 * No smp_load/store wrappers needed here as we are in
5571 * VM init and there cannot be any memslots / other threads
5572 * accessing this struct kvm yet.
5574 kvm->arch.memslots_have_rmaps = true;
5576 node->track_write = kvm_mmu_pte_write;
5577 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5578 kvm_page_track_register_notifier(kvm, node);
5581 void kvm_mmu_uninit_vm(struct kvm *kvm)
5583 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5585 kvm_page_track_unregister_notifier(kvm, node);
5587 kvm_mmu_uninit_tdp_mmu(kvm);
5590 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5592 struct kvm_memslots *slots;
5593 struct kvm_memory_slot *memslot;
5597 if (kvm_memslots_have_rmaps(kvm)) {
5598 write_lock(&kvm->mmu_lock);
5599 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5600 slots = __kvm_memslots(kvm, i);
5601 kvm_for_each_memslot(memslot, slots) {
5604 start = max(gfn_start, memslot->base_gfn);
5605 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5609 flush = slot_handle_level_range(kvm, memslot,
5610 kvm_zap_rmapp, PG_LEVEL_4K,
5611 KVM_MAX_HUGEPAGE_LEVEL, start,
5612 end - 1, true, flush);
5616 kvm_flush_remote_tlbs_with_address(kvm, gfn_start, gfn_end);
5617 write_unlock(&kvm->mmu_lock);
5620 if (is_tdp_mmu_enabled(kvm)) {
5623 read_lock(&kvm->mmu_lock);
5624 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++)
5625 flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start,
5626 gfn_end, flush, true);
5628 kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
5631 read_unlock(&kvm->mmu_lock);
5635 static bool slot_rmap_write_protect(struct kvm *kvm,
5636 struct kvm_rmap_head *rmap_head,
5637 struct kvm_memory_slot *slot)
5639 return __rmap_write_protect(kvm, rmap_head, false);
5642 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5643 struct kvm_memory_slot *memslot,
5648 if (kvm_memslots_have_rmaps(kvm)) {
5649 write_lock(&kvm->mmu_lock);
5650 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5651 start_level, KVM_MAX_HUGEPAGE_LEVEL,
5653 write_unlock(&kvm->mmu_lock);
5656 if (is_tdp_mmu_enabled(kvm)) {
5657 read_lock(&kvm->mmu_lock);
5658 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level);
5659 read_unlock(&kvm->mmu_lock);
5663 * We can flush all the TLBs out of the mmu lock without TLB
5664 * corruption since we just change the spte from writable to
5665 * readonly so that we only need to care the case of changing
5666 * spte from present to present (changing the spte from present
5667 * to nonpresent will flush all the TLBs immediately), in other
5668 * words, the only case we care is mmu_spte_update() where we
5669 * have checked Host-writable | MMU-writable instead of
5670 * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK
5674 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5677 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5678 struct kvm_rmap_head *rmap_head,
5679 struct kvm_memory_slot *slot)
5682 struct rmap_iterator iter;
5683 int need_tlb_flush = 0;
5685 struct kvm_mmu_page *sp;
5688 for_each_rmap_spte(rmap_head, &iter, sptep) {
5689 sp = sptep_to_sp(sptep);
5690 pfn = spte_to_pfn(*sptep);
5693 * We cannot do huge page mapping for indirect shadow pages,
5694 * which are found on the last rmap (level = 1) when not using
5695 * tdp; such shadow pages are synced with the page table in
5696 * the guest, and the guest page table is using 4K page size
5697 * mapping if the indirect sp has level = 1.
5699 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5700 sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn,
5701 pfn, PG_LEVEL_NUM)) {
5702 pte_list_remove(rmap_head, sptep);
5704 if (kvm_available_flush_tlb_with_range())
5705 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5706 KVM_PAGES_PER_HPAGE(sp->role.level));
5714 return need_tlb_flush;
5717 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5718 const struct kvm_memory_slot *memslot)
5720 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5721 struct kvm_memory_slot *slot = (struct kvm_memory_slot *)memslot;
5724 if (kvm_memslots_have_rmaps(kvm)) {
5725 write_lock(&kvm->mmu_lock);
5726 flush = slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true);
5728 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5729 write_unlock(&kvm->mmu_lock);
5732 if (is_tdp_mmu_enabled(kvm)) {
5733 read_lock(&kvm->mmu_lock);
5734 flush = kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot, flush);
5736 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5737 read_unlock(&kvm->mmu_lock);
5741 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5742 const struct kvm_memory_slot *memslot)
5745 * All current use cases for flushing the TLBs for a specific memslot
5746 * related to dirty logging, and many do the TLB flush out of mmu_lock.
5747 * The interaction between the various operations on memslot must be
5748 * serialized by slots_locks to ensure the TLB flush from one operation
5749 * is observed by any other operation on the same memslot.
5751 lockdep_assert_held(&kvm->slots_lock);
5752 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5756 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5757 struct kvm_memory_slot *memslot)
5761 if (kvm_memslots_have_rmaps(kvm)) {
5762 write_lock(&kvm->mmu_lock);
5763 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty,
5765 write_unlock(&kvm->mmu_lock);
5768 if (is_tdp_mmu_enabled(kvm)) {
5769 read_lock(&kvm->mmu_lock);
5770 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5771 read_unlock(&kvm->mmu_lock);
5775 * It's also safe to flush TLBs out of mmu lock here as currently this
5776 * function is only used for dirty logging, in which case flushing TLB
5777 * out of mmu lock also guarantees no dirty pages will be lost in
5781 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5784 void kvm_mmu_zap_all(struct kvm *kvm)
5786 struct kvm_mmu_page *sp, *node;
5787 LIST_HEAD(invalid_list);
5790 write_lock(&kvm->mmu_lock);
5792 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5793 if (WARN_ON(sp->role.invalid))
5795 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5797 if (cond_resched_rwlock_write(&kvm->mmu_lock))
5801 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5803 if (is_tdp_mmu_enabled(kvm))
5804 kvm_tdp_mmu_zap_all(kvm);
5806 write_unlock(&kvm->mmu_lock);
5809 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5811 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5813 gen &= MMIO_SPTE_GEN_MASK;
5816 * Generation numbers are incremented in multiples of the number of
5817 * address spaces in order to provide unique generations across all
5818 * address spaces. Strip what is effectively the address space
5819 * modifier prior to checking for a wrap of the MMIO generation so
5820 * that a wrap in any address space is detected.
5822 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5825 * The very rare case: if the MMIO generation number has wrapped,
5826 * zap all shadow pages.
5828 if (unlikely(gen == 0)) {
5829 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5830 kvm_mmu_zap_all_fast(kvm);
5834 static unsigned long
5835 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5838 int nr_to_scan = sc->nr_to_scan;
5839 unsigned long freed = 0;
5841 mutex_lock(&kvm_lock);
5843 list_for_each_entry(kvm, &vm_list, vm_list) {
5845 LIST_HEAD(invalid_list);
5848 * Never scan more than sc->nr_to_scan VM instances.
5849 * Will not hit this condition practically since we do not try
5850 * to shrink more than one VM and it is very unlikely to see
5851 * !n_used_mmu_pages so many times.
5856 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5857 * here. We may skip a VM instance errorneosly, but we do not
5858 * want to shrink a VM that only started to populate its MMU
5861 if (!kvm->arch.n_used_mmu_pages &&
5862 !kvm_has_zapped_obsolete_pages(kvm))
5865 idx = srcu_read_lock(&kvm->srcu);
5866 write_lock(&kvm->mmu_lock);
5868 if (kvm_has_zapped_obsolete_pages(kvm)) {
5869 kvm_mmu_commit_zap_page(kvm,
5870 &kvm->arch.zapped_obsolete_pages);
5874 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
5877 write_unlock(&kvm->mmu_lock);
5878 srcu_read_unlock(&kvm->srcu, idx);
5881 * unfair on small ones
5882 * per-vm shrinkers cry out
5883 * sadness comes quickly
5885 list_move_tail(&kvm->vm_list, &vm_list);
5889 mutex_unlock(&kvm_lock);
5893 static unsigned long
5894 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5896 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5899 static struct shrinker mmu_shrinker = {
5900 .count_objects = mmu_shrink_count,
5901 .scan_objects = mmu_shrink_scan,
5902 .seeks = DEFAULT_SEEKS * 10,
5905 static void mmu_destroy_caches(void)
5907 kmem_cache_destroy(pte_list_desc_cache);
5908 kmem_cache_destroy(mmu_page_header_cache);
5911 static bool get_nx_auto_mode(void)
5913 /* Return true when CPU has the bug, and mitigations are ON */
5914 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5917 static void __set_nx_huge_pages(bool val)
5919 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5922 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5924 bool old_val = nx_huge_pages;
5927 /* In "auto" mode deploy workaround only if CPU has the bug. */
5928 if (sysfs_streq(val, "off"))
5930 else if (sysfs_streq(val, "force"))
5932 else if (sysfs_streq(val, "auto"))
5933 new_val = get_nx_auto_mode();
5934 else if (strtobool(val, &new_val) < 0)
5937 __set_nx_huge_pages(new_val);
5939 if (new_val != old_val) {
5942 mutex_lock(&kvm_lock);
5944 list_for_each_entry(kvm, &vm_list, vm_list) {
5945 mutex_lock(&kvm->slots_lock);
5946 kvm_mmu_zap_all_fast(kvm);
5947 mutex_unlock(&kvm->slots_lock);
5949 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5951 mutex_unlock(&kvm_lock);
5957 int kvm_mmu_module_init(void)
5961 if (nx_huge_pages == -1)
5962 __set_nx_huge_pages(get_nx_auto_mode());
5965 * MMU roles use union aliasing which is, generally speaking, an
5966 * undefined behavior. However, we supposedly know how compilers behave
5967 * and the current status quo is unlikely to change. Guardians below are
5968 * supposed to let us know if the assumption becomes false.
5970 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
5971 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
5972 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
5974 kvm_mmu_reset_all_pte_masks();
5976 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5977 sizeof(struct pte_list_desc),
5978 0, SLAB_ACCOUNT, NULL);
5979 if (!pte_list_desc_cache)
5982 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5983 sizeof(struct kvm_mmu_page),
5984 0, SLAB_ACCOUNT, NULL);
5985 if (!mmu_page_header_cache)
5988 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5991 ret = register_shrinker(&mmu_shrinker);
5998 mmu_destroy_caches();
6003 * Calculate mmu pages needed for kvm.
6005 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
6007 unsigned long nr_mmu_pages;
6008 unsigned long nr_pages = 0;
6009 struct kvm_memslots *slots;
6010 struct kvm_memory_slot *memslot;
6013 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6014 slots = __kvm_memslots(kvm, i);
6016 kvm_for_each_memslot(memslot, slots)
6017 nr_pages += memslot->npages;
6020 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
6021 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
6023 return nr_mmu_pages;
6026 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6028 kvm_mmu_unload(vcpu);
6029 free_mmu_pages(&vcpu->arch.root_mmu);
6030 free_mmu_pages(&vcpu->arch.guest_mmu);
6031 mmu_free_memory_caches(vcpu);
6034 void kvm_mmu_module_exit(void)
6036 mmu_destroy_caches();
6037 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6038 unregister_shrinker(&mmu_shrinker);
6039 mmu_audit_disable();
6042 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
6044 unsigned int old_val;
6047 old_val = nx_huge_pages_recovery_ratio;
6048 err = param_set_uint(val, kp);
6052 if (READ_ONCE(nx_huge_pages) &&
6053 !old_val && nx_huge_pages_recovery_ratio) {
6056 mutex_lock(&kvm_lock);
6058 list_for_each_entry(kvm, &vm_list, vm_list)
6059 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6061 mutex_unlock(&kvm_lock);
6067 static void kvm_recover_nx_lpages(struct kvm *kvm)
6069 unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits;
6071 struct kvm_mmu_page *sp;
6073 LIST_HEAD(invalid_list);
6077 rcu_idx = srcu_read_lock(&kvm->srcu);
6078 write_lock(&kvm->mmu_lock);
6080 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6081 to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0;
6082 for ( ; to_zap; --to_zap) {
6083 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
6087 * We use a separate list instead of just using active_mmu_pages
6088 * because the number of lpage_disallowed pages is expected to
6089 * be relatively small compared to the total.
6091 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6092 struct kvm_mmu_page,
6093 lpage_disallowed_link);
6094 WARN_ON_ONCE(!sp->lpage_disallowed);
6095 if (is_tdp_mmu_page(sp)) {
6096 flush |= kvm_tdp_mmu_zap_sp(kvm, sp);
6098 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6099 WARN_ON_ONCE(sp->lpage_disallowed);
6102 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
6103 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6104 cond_resched_rwlock_write(&kvm->mmu_lock);
6108 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6110 write_unlock(&kvm->mmu_lock);
6111 srcu_read_unlock(&kvm->srcu, rcu_idx);
6114 static long get_nx_lpage_recovery_timeout(u64 start_time)
6116 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6117 ? start_time + 60 * HZ - get_jiffies_64()
6118 : MAX_SCHEDULE_TIMEOUT;
6121 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6124 long remaining_time;
6127 start_time = get_jiffies_64();
6128 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6130 set_current_state(TASK_INTERRUPTIBLE);
6131 while (!kthread_should_stop() && remaining_time > 0) {
6132 schedule_timeout(remaining_time);
6133 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6134 set_current_state(TASK_INTERRUPTIBLE);
6137 set_current_state(TASK_RUNNING);
6139 if (kthread_should_stop())
6142 kvm_recover_nx_lpages(kvm);
6146 int kvm_mmu_post_init_vm(struct kvm *kvm)
6150 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6151 "kvm-nx-lpage-recovery",
6152 &kvm->arch.nx_lpage_recovery_thread);
6154 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6159 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6161 if (kvm->arch.nx_lpage_recovery_thread)
6162 kthread_stop(kvm->arch.nx_lpage_recovery_thread);