1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
51 #include <asm/set_memory.h>
53 #include <asm/kvm_page_track.h>
56 extern bool itlb_multihit_kvm_mitigation;
58 int __read_mostly nx_huge_pages = -1;
59 #ifdef CONFIG_PREEMPT_RT
60 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
61 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
63 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
66 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
67 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops nx_huge_pages_ops = {
70 .set = set_nx_huge_pages,
71 .get = param_get_bool,
74 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
75 .set = set_nx_huge_pages_recovery_ratio,
76 .get = param_get_uint,
79 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
80 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
81 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
82 &nx_huge_pages_recovery_ratio, 0644);
83 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
85 static bool __read_mostly force_flush_and_sync_on_reuse;
86 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
89 * When setting this variable to true it enables Two-Dimensional-Paging
90 * where the hardware walks 2 page tables:
91 * 1. the guest-virtual to guest-physical
92 * 2. while doing 1. it walks guest-physical to host-physical
93 * If the hardware supports that we don't need to do shadow paging.
95 bool tdp_enabled = false;
97 static int max_huge_page_level __read_mostly;
98 static int max_tdp_level __read_mostly;
101 AUDIT_PRE_PAGE_FAULT,
102 AUDIT_POST_PAGE_FAULT,
104 AUDIT_POST_PTE_WRITE,
111 module_param(dbg, bool, 0644);
114 #define PTE_PREFETCH_NUM 8
116 #define PT32_LEVEL_BITS 10
118 #define PT32_LEVEL_SHIFT(level) \
119 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
121 #define PT32_LVL_OFFSET_MASK(level) \
122 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT32_LEVEL_BITS))) - 1))
125 #define PT32_INDEX(address, level)\
126 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
129 #define PT32_BASE_ADDR_MASK PAGE_MASK
130 #define PT32_DIR_BASE_ADDR_MASK \
131 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
132 #define PT32_LVL_ADDR_MASK(level) \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
134 * PT32_LEVEL_BITS))) - 1))
136 #include <trace/events/kvm.h>
138 /* make pte_list_desc fit well in cache line */
139 #define PTE_LIST_EXT 3
141 struct pte_list_desc {
142 u64 *sptes[PTE_LIST_EXT];
143 struct pte_list_desc *more;
146 struct kvm_shadow_walk_iterator {
154 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
155 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
157 shadow_walk_okay(&(_walker)); \
158 shadow_walk_next(&(_walker)))
160 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
161 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
162 shadow_walk_okay(&(_walker)); \
163 shadow_walk_next(&(_walker)))
165 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
166 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
167 shadow_walk_okay(&(_walker)) && \
168 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
169 __shadow_walk_next(&(_walker), spte))
171 static struct kmem_cache *pte_list_desc_cache;
172 struct kmem_cache *mmu_page_header_cache;
173 static struct percpu_counter kvm_total_used_mmu_pages;
175 static void mmu_spte_set(u64 *sptep, u64 spte);
176 static union kvm_mmu_page_role
177 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
179 #define CREATE_TRACE_POINTS
180 #include "mmutrace.h"
183 static inline bool kvm_available_flush_tlb_with_range(void)
185 return kvm_x86_ops.tlb_remote_flush_with_range;
188 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
189 struct kvm_tlb_range *range)
193 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
194 ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range);
197 kvm_flush_remote_tlbs(kvm);
200 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
201 u64 start_gfn, u64 pages)
203 struct kvm_tlb_range range;
205 range.start_gfn = start_gfn;
208 kvm_flush_remote_tlbs_with_range(kvm, &range);
211 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
214 u64 spte = make_mmio_spte(vcpu, gfn, access);
216 trace_mark_mmio_spte(sptep, gfn, spte);
217 mmu_spte_set(sptep, spte);
220 static gfn_t get_mmio_spte_gfn(u64 spte)
222 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
224 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)
225 & shadow_nonpresent_or_rsvd_mask;
227 return gpa >> PAGE_SHIFT;
230 static unsigned get_mmio_spte_access(u64 spte)
232 return spte & shadow_mmio_access_mask;
235 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
237 u64 kvm_gen, spte_gen, gen;
239 gen = kvm_vcpu_memslots(vcpu)->generation;
240 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
243 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
244 spte_gen = get_mmio_spte_generation(spte);
246 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
247 return likely(kvm_gen == spte_gen);
250 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
251 struct x86_exception *exception)
253 /* Check if guest physical address doesn't exceed guest maximum */
254 if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) {
255 exception->error_code |= PFERR_RSVD_MASK;
262 static int is_cpuid_PSE36(void)
267 static int is_nx(struct kvm_vcpu *vcpu)
269 return vcpu->arch.efer & EFER_NX;
272 static gfn_t pse36_gfn_delta(u32 gpte)
274 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
276 return (gpte & PT32_DIR_PSE36_MASK) << shift;
280 static void __set_spte(u64 *sptep, u64 spte)
282 WRITE_ONCE(*sptep, spte);
285 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
287 WRITE_ONCE(*sptep, spte);
290 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
292 return xchg(sptep, spte);
295 static u64 __get_spte_lockless(u64 *sptep)
297 return READ_ONCE(*sptep);
308 static void count_spte_clear(u64 *sptep, u64 spte)
310 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
312 if (is_shadow_present_pte(spte))
315 /* Ensure the spte is completely set before we increase the count */
317 sp->clear_spte_count++;
320 static void __set_spte(u64 *sptep, u64 spte)
322 union split_spte *ssptep, sspte;
324 ssptep = (union split_spte *)sptep;
325 sspte = (union split_spte)spte;
327 ssptep->spte_high = sspte.spte_high;
330 * If we map the spte from nonpresent to present, We should store
331 * the high bits firstly, then set present bit, so cpu can not
332 * fetch this spte while we are setting the spte.
336 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
339 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
341 union split_spte *ssptep, sspte;
343 ssptep = (union split_spte *)sptep;
344 sspte = (union split_spte)spte;
346 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
349 * If we map the spte from present to nonpresent, we should clear
350 * present bit firstly to avoid vcpu fetch the old high bits.
354 ssptep->spte_high = sspte.spte_high;
355 count_spte_clear(sptep, spte);
358 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
360 union split_spte *ssptep, sspte, orig;
362 ssptep = (union split_spte *)sptep;
363 sspte = (union split_spte)spte;
365 /* xchg acts as a barrier before the setting of the high bits */
366 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
367 orig.spte_high = ssptep->spte_high;
368 ssptep->spte_high = sspte.spte_high;
369 count_spte_clear(sptep, spte);
375 * The idea using the light way get the spte on x86_32 guest is from
376 * gup_get_pte (mm/gup.c).
378 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
379 * coalesces them and we are running out of the MMU lock. Therefore
380 * we need to protect against in-progress updates of the spte.
382 * Reading the spte while an update is in progress may get the old value
383 * for the high part of the spte. The race is fine for a present->non-present
384 * change (because the high part of the spte is ignored for non-present spte),
385 * but for a present->present change we must reread the spte.
387 * All such changes are done in two steps (present->non-present and
388 * non-present->present), hence it is enough to count the number of
389 * present->non-present updates: if it changed while reading the spte,
390 * we might have hit the race. This is done using clear_spte_count.
392 static u64 __get_spte_lockless(u64 *sptep)
394 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
395 union split_spte spte, *orig = (union split_spte *)sptep;
399 count = sp->clear_spte_count;
402 spte.spte_low = orig->spte_low;
405 spte.spte_high = orig->spte_high;
408 if (unlikely(spte.spte_low != orig->spte_low ||
409 count != sp->clear_spte_count))
416 static bool spte_has_volatile_bits(u64 spte)
418 if (!is_shadow_present_pte(spte))
422 * Always atomically update spte if it can be updated
423 * out of mmu-lock, it can ensure dirty bit is not lost,
424 * also, it can help us to get a stable is_writable_pte()
425 * to ensure tlb flush is not missed.
427 if (spte_can_locklessly_be_made_writable(spte) ||
428 is_access_track_spte(spte))
431 if (spte_ad_enabled(spte)) {
432 if ((spte & shadow_accessed_mask) == 0 ||
433 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
440 /* Rules for using mmu_spte_set:
441 * Set the sptep from nonpresent to present.
442 * Note: the sptep being assigned *must* be either not present
443 * or in a state where the hardware will not attempt to update
446 static void mmu_spte_set(u64 *sptep, u64 new_spte)
448 WARN_ON(is_shadow_present_pte(*sptep));
449 __set_spte(sptep, new_spte);
453 * Update the SPTE (excluding the PFN), but do not track changes in its
454 * accessed/dirty status.
456 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
458 u64 old_spte = *sptep;
460 WARN_ON(!is_shadow_present_pte(new_spte));
462 if (!is_shadow_present_pte(old_spte)) {
463 mmu_spte_set(sptep, new_spte);
467 if (!spte_has_volatile_bits(old_spte))
468 __update_clear_spte_fast(sptep, new_spte);
470 old_spte = __update_clear_spte_slow(sptep, new_spte);
472 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
477 /* Rules for using mmu_spte_update:
478 * Update the state bits, it means the mapped pfn is not changed.
480 * Whenever we overwrite a writable spte with a read-only one we
481 * should flush remote TLBs. Otherwise rmap_write_protect
482 * will find a read-only spte, even though the writable spte
483 * might be cached on a CPU's TLB, the return value indicates this
486 * Returns true if the TLB needs to be flushed
488 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
491 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
493 if (!is_shadow_present_pte(old_spte))
497 * For the spte updated out of mmu-lock is safe, since
498 * we always atomically update it, see the comments in
499 * spte_has_volatile_bits().
501 if (spte_can_locklessly_be_made_writable(old_spte) &&
502 !is_writable_pte(new_spte))
506 * Flush TLB when accessed/dirty states are changed in the page tables,
507 * to guarantee consistency between TLB and page tables.
510 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
512 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
515 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
517 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
524 * Rules for using mmu_spte_clear_track_bits:
525 * It sets the sptep from present to nonpresent, and track the
526 * state bits, it is used to clear the last level sptep.
527 * Returns non-zero if the PTE was previously valid.
529 static int mmu_spte_clear_track_bits(u64 *sptep)
532 u64 old_spte = *sptep;
534 if (!spte_has_volatile_bits(old_spte))
535 __update_clear_spte_fast(sptep, 0ull);
537 old_spte = __update_clear_spte_slow(sptep, 0ull);
539 if (!is_shadow_present_pte(old_spte))
542 pfn = spte_to_pfn(old_spte);
545 * KVM does not hold the refcount of the page used by
546 * kvm mmu, before reclaiming the page, we should
547 * unmap it from mmu first.
549 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
551 if (is_accessed_spte(old_spte))
552 kvm_set_pfn_accessed(pfn);
554 if (is_dirty_spte(old_spte))
555 kvm_set_pfn_dirty(pfn);
561 * Rules for using mmu_spte_clear_no_track:
562 * Directly clear spte without caring the state bits of sptep,
563 * it is used to set the upper level spte.
565 static void mmu_spte_clear_no_track(u64 *sptep)
567 __update_clear_spte_fast(sptep, 0ull);
570 static u64 mmu_spte_get_lockless(u64 *sptep)
572 return __get_spte_lockless(sptep);
575 /* Restore an acc-track PTE back to a regular PTE */
576 static u64 restore_acc_track_spte(u64 spte)
579 u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
580 & SHADOW_ACC_TRACK_SAVED_BITS_MASK;
582 WARN_ON_ONCE(spte_ad_enabled(spte));
583 WARN_ON_ONCE(!is_access_track_spte(spte));
585 new_spte &= ~shadow_acc_track_mask;
586 new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
587 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
588 new_spte |= saved_bits;
593 /* Returns the Accessed status of the PTE and resets it at the same time. */
594 static bool mmu_spte_age(u64 *sptep)
596 u64 spte = mmu_spte_get_lockless(sptep);
598 if (!is_accessed_spte(spte))
601 if (spte_ad_enabled(spte)) {
602 clear_bit((ffs(shadow_accessed_mask) - 1),
603 (unsigned long *)sptep);
606 * Capture the dirty status of the page, so that it doesn't get
607 * lost when the SPTE is marked for access tracking.
609 if (is_writable_pte(spte))
610 kvm_set_pfn_dirty(spte_to_pfn(spte));
612 spte = mark_spte_for_access_track(spte);
613 mmu_spte_update_no_track(sptep, spte);
619 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
622 * Prevent page table teardown by making any free-er wait during
623 * kvm_flush_remote_tlbs() IPI to all active vcpus.
628 * Make sure a following spte read is not reordered ahead of the write
631 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
634 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
637 * Make sure the write to vcpu->mode is not reordered in front of
638 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
639 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
641 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
645 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
649 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
650 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
651 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
654 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
655 PT64_ROOT_MAX_LEVEL);
658 if (maybe_indirect) {
659 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
660 PT64_ROOT_MAX_LEVEL);
664 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
665 PT64_ROOT_MAX_LEVEL);
668 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
670 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
671 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
672 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
673 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
676 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
678 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
681 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
683 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
686 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
688 if (!sp->role.direct)
689 return sp->gfns[index];
691 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
694 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
696 if (!sp->role.direct) {
697 sp->gfns[index] = gfn;
701 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
702 pr_err_ratelimited("gfn mismatch under direct page %llx "
703 "(expected %llx, got %llx)\n",
705 kvm_mmu_page_get_gfn(sp, index), gfn);
709 * Return the pointer to the large page information for a given gfn,
710 * handling slots that are not large page aligned.
712 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
713 const struct kvm_memory_slot *slot, int level)
717 idx = gfn_to_index(gfn, slot->base_gfn, level);
718 return &slot->arch.lpage_info[level - 2][idx];
721 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
722 gfn_t gfn, int count)
724 struct kvm_lpage_info *linfo;
727 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
728 linfo = lpage_info_slot(gfn, slot, i);
729 linfo->disallow_lpage += count;
730 WARN_ON(linfo->disallow_lpage < 0);
734 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
736 update_gfn_disallow_lpage_count(slot, gfn, 1);
739 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
741 update_gfn_disallow_lpage_count(slot, gfn, -1);
744 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
746 struct kvm_memslots *slots;
747 struct kvm_memory_slot *slot;
750 kvm->arch.indirect_shadow_pages++;
752 slots = kvm_memslots_for_spte_role(kvm, sp->role);
753 slot = __gfn_to_memslot(slots, gfn);
755 /* the non-leaf shadow pages are keeping readonly. */
756 if (sp->role.level > PG_LEVEL_4K)
757 return kvm_slot_page_track_add_page(kvm, slot, gfn,
758 KVM_PAGE_TRACK_WRITE);
760 kvm_mmu_gfn_disallow_lpage(slot, gfn);
763 void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
765 if (sp->lpage_disallowed)
768 ++kvm->stat.nx_lpage_splits;
769 list_add_tail(&sp->lpage_disallowed_link,
770 &kvm->arch.lpage_disallowed_mmu_pages);
771 sp->lpage_disallowed = true;
774 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
776 struct kvm_memslots *slots;
777 struct kvm_memory_slot *slot;
780 kvm->arch.indirect_shadow_pages--;
782 slots = kvm_memslots_for_spte_role(kvm, sp->role);
783 slot = __gfn_to_memslot(slots, gfn);
784 if (sp->role.level > PG_LEVEL_4K)
785 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
786 KVM_PAGE_TRACK_WRITE);
788 kvm_mmu_gfn_allow_lpage(slot, gfn);
791 void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
793 --kvm->stat.nx_lpage_splits;
794 sp->lpage_disallowed = false;
795 list_del(&sp->lpage_disallowed_link);
798 static struct kvm_memory_slot *
799 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
802 struct kvm_memory_slot *slot;
804 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
805 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
807 if (no_dirty_log && kvm_slot_dirty_track_enabled(slot))
814 * About rmap_head encoding:
816 * If the bit zero of rmap_head->val is clear, then it points to the only spte
817 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
818 * pte_list_desc containing more mappings.
822 * Returns the number of pointers in the rmap chain, not counting the new one.
824 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
825 struct kvm_rmap_head *rmap_head)
827 struct pte_list_desc *desc;
830 if (!rmap_head->val) {
831 rmap_printk("%p %llx 0->1\n", spte, *spte);
832 rmap_head->val = (unsigned long)spte;
833 } else if (!(rmap_head->val & 1)) {
834 rmap_printk("%p %llx 1->many\n", spte, *spte);
835 desc = mmu_alloc_pte_list_desc(vcpu);
836 desc->sptes[0] = (u64 *)rmap_head->val;
837 desc->sptes[1] = spte;
838 rmap_head->val = (unsigned long)desc | 1;
841 rmap_printk("%p %llx many->many\n", spte, *spte);
842 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
843 while (desc->sptes[PTE_LIST_EXT-1]) {
844 count += PTE_LIST_EXT;
847 desc->more = mmu_alloc_pte_list_desc(vcpu);
853 for (i = 0; desc->sptes[i]; ++i)
855 desc->sptes[i] = spte;
861 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
862 struct pte_list_desc *desc, int i,
863 struct pte_list_desc *prev_desc)
867 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
869 desc->sptes[i] = desc->sptes[j];
870 desc->sptes[j] = NULL;
873 if (!prev_desc && !desc->more)
877 prev_desc->more = desc->more;
879 rmap_head->val = (unsigned long)desc->more | 1;
880 mmu_free_pte_list_desc(desc);
883 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
885 struct pte_list_desc *desc;
886 struct pte_list_desc *prev_desc;
889 if (!rmap_head->val) {
890 pr_err("%s: %p 0->BUG\n", __func__, spte);
892 } else if (!(rmap_head->val & 1)) {
893 rmap_printk("%p 1->0\n", spte);
894 if ((u64 *)rmap_head->val != spte) {
895 pr_err("%s: %p 1->BUG\n", __func__, spte);
900 rmap_printk("%p many->many\n", spte);
901 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
904 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
905 if (desc->sptes[i] == spte) {
906 pte_list_desc_remove_entry(rmap_head,
914 pr_err("%s: %p many->many\n", __func__, spte);
919 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
921 mmu_spte_clear_track_bits(sptep);
922 __pte_list_remove(sptep, rmap_head);
925 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
926 struct kvm_memory_slot *slot)
930 idx = gfn_to_index(gfn, slot->base_gfn, level);
931 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
934 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
935 struct kvm_mmu_page *sp)
937 struct kvm_memslots *slots;
938 struct kvm_memory_slot *slot;
940 slots = kvm_memslots_for_spte_role(kvm, sp->role);
941 slot = __gfn_to_memslot(slots, gfn);
942 return __gfn_to_rmap(gfn, sp->role.level, slot);
945 static bool rmap_can_add(struct kvm_vcpu *vcpu)
947 struct kvm_mmu_memory_cache *mc;
949 mc = &vcpu->arch.mmu_pte_list_desc_cache;
950 return kvm_mmu_memory_cache_nr_free_objects(mc);
953 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
955 struct kvm_mmu_page *sp;
956 struct kvm_rmap_head *rmap_head;
958 sp = sptep_to_sp(spte);
959 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
960 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
961 return pte_list_add(vcpu, spte, rmap_head);
964 static void rmap_remove(struct kvm *kvm, u64 *spte)
966 struct kvm_mmu_page *sp;
968 struct kvm_rmap_head *rmap_head;
970 sp = sptep_to_sp(spte);
971 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
972 rmap_head = gfn_to_rmap(kvm, gfn, sp);
973 __pte_list_remove(spte, rmap_head);
977 * Used by the following functions to iterate through the sptes linked by a
978 * rmap. All fields are private and not assumed to be used outside.
980 struct rmap_iterator {
982 struct pte_list_desc *desc; /* holds the sptep if not NULL */
983 int pos; /* index of the sptep */
987 * Iteration must be started by this function. This should also be used after
988 * removing/dropping sptes from the rmap link because in such cases the
989 * information in the iterator may not be valid.
991 * Returns sptep if found, NULL otherwise.
993 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
994 struct rmap_iterator *iter)
1001 if (!(rmap_head->val & 1)) {
1003 sptep = (u64 *)rmap_head->val;
1007 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1009 sptep = iter->desc->sptes[iter->pos];
1011 BUG_ON(!is_shadow_present_pte(*sptep));
1016 * Must be used with a valid iterator: e.g. after rmap_get_first().
1018 * Returns sptep if found, NULL otherwise.
1020 static u64 *rmap_get_next(struct rmap_iterator *iter)
1025 if (iter->pos < PTE_LIST_EXT - 1) {
1027 sptep = iter->desc->sptes[iter->pos];
1032 iter->desc = iter->desc->more;
1036 /* desc->sptes[0] cannot be NULL */
1037 sptep = iter->desc->sptes[iter->pos];
1044 BUG_ON(!is_shadow_present_pte(*sptep));
1048 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1049 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1050 _spte_; _spte_ = rmap_get_next(_iter_))
1052 static void drop_spte(struct kvm *kvm, u64 *sptep)
1054 if (mmu_spte_clear_track_bits(sptep))
1055 rmap_remove(kvm, sptep);
1059 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1061 if (is_large_pte(*sptep)) {
1062 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1063 drop_spte(kvm, sptep);
1071 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1073 if (__drop_large_spte(vcpu->kvm, sptep)) {
1074 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1076 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1077 KVM_PAGES_PER_HPAGE(sp->role.level));
1082 * Write-protect on the specified @sptep, @pt_protect indicates whether
1083 * spte write-protection is caused by protecting shadow page table.
1085 * Note: write protection is difference between dirty logging and spte
1087 * - for dirty logging, the spte can be set to writable at anytime if
1088 * its dirty bitmap is properly set.
1089 * - for spte protection, the spte can be writable only after unsync-ing
1092 * Return true if tlb need be flushed.
1094 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1098 if (!is_writable_pte(spte) &&
1099 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1102 rmap_printk("spte %p %llx\n", sptep, *sptep);
1105 spte &= ~shadow_mmu_writable_mask;
1106 spte = spte & ~PT_WRITABLE_MASK;
1108 return mmu_spte_update(sptep, spte);
1111 static bool __rmap_write_protect(struct kvm *kvm,
1112 struct kvm_rmap_head *rmap_head,
1116 struct rmap_iterator iter;
1119 for_each_rmap_spte(rmap_head, &iter, sptep)
1120 flush |= spte_write_protect(sptep, pt_protect);
1125 static bool spte_clear_dirty(u64 *sptep)
1129 rmap_printk("spte %p %llx\n", sptep, *sptep);
1131 MMU_WARN_ON(!spte_ad_enabled(spte));
1132 spte &= ~shadow_dirty_mask;
1133 return mmu_spte_update(sptep, spte);
1136 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1138 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1139 (unsigned long *)sptep);
1140 if (was_writable && !spte_ad_enabled(*sptep))
1141 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1143 return was_writable;
1147 * Gets the GFN ready for another round of dirty logging by clearing the
1148 * - D bit on ad-enabled SPTEs, and
1149 * - W bit on ad-disabled SPTEs.
1150 * Returns true iff any D or W bits were cleared.
1152 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1153 struct kvm_memory_slot *slot)
1156 struct rmap_iterator iter;
1159 for_each_rmap_spte(rmap_head, &iter, sptep)
1160 if (spte_ad_need_write_protect(*sptep))
1161 flush |= spte_wrprot_for_clear_dirty(sptep);
1163 flush |= spte_clear_dirty(sptep);
1169 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1170 * @kvm: kvm instance
1171 * @slot: slot to protect
1172 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1173 * @mask: indicates which pages we should protect
1175 * Used when we do not need to care about huge page mappings.
1177 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1178 struct kvm_memory_slot *slot,
1179 gfn_t gfn_offset, unsigned long mask)
1181 struct kvm_rmap_head *rmap_head;
1183 if (is_tdp_mmu_enabled(kvm))
1184 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1185 slot->base_gfn + gfn_offset, mask, true);
1187 if (!kvm_memslots_have_rmaps(kvm))
1191 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1193 __rmap_write_protect(kvm, rmap_head, false);
1195 /* clear the first set bit */
1201 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1202 * protect the page if the D-bit isn't supported.
1203 * @kvm: kvm instance
1204 * @slot: slot to clear D-bit
1205 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1206 * @mask: indicates which pages we should clear D-bit
1208 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1210 static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1211 struct kvm_memory_slot *slot,
1212 gfn_t gfn_offset, unsigned long mask)
1214 struct kvm_rmap_head *rmap_head;
1216 if (is_tdp_mmu_enabled(kvm))
1217 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1218 slot->base_gfn + gfn_offset, mask, false);
1220 if (!kvm_memslots_have_rmaps(kvm))
1224 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1226 __rmap_clear_dirty(kvm, rmap_head, slot);
1228 /* clear the first set bit */
1234 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1237 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1238 * enable dirty logging for them.
1240 * We need to care about huge page mappings: e.g. during dirty logging we may
1241 * have such mappings.
1243 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1244 struct kvm_memory_slot *slot,
1245 gfn_t gfn_offset, unsigned long mask)
1248 * Huge pages are NOT write protected when we start dirty logging in
1249 * initially-all-set mode; must write protect them here so that they
1250 * are split to 4K on the first write.
1252 * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn
1253 * of memslot has no such restriction, so the range can cross two large
1256 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) {
1257 gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask);
1258 gfn_t end = slot->base_gfn + gfn_offset + __fls(mask);
1260 kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M);
1262 /* Cross two large pages? */
1263 if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) !=
1264 ALIGN(end << PAGE_SHIFT, PMD_SIZE))
1265 kvm_mmu_slot_gfn_write_protect(kvm, slot, end,
1269 /* Now handle 4K PTEs. */
1270 if (kvm_x86_ops.cpu_dirty_log_size)
1271 kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask);
1273 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1276 int kvm_cpu_dirty_log_size(void)
1278 return kvm_x86_ops.cpu_dirty_log_size;
1281 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1282 struct kvm_memory_slot *slot, u64 gfn,
1285 struct kvm_rmap_head *rmap_head;
1287 bool write_protected = false;
1289 if (kvm_memslots_have_rmaps(kvm)) {
1290 for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1291 rmap_head = __gfn_to_rmap(gfn, i, slot);
1292 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1296 if (is_tdp_mmu_enabled(kvm))
1298 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level);
1300 return write_protected;
1303 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1305 struct kvm_memory_slot *slot;
1307 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1308 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K);
1311 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1312 struct kvm_memory_slot *slot)
1315 struct rmap_iterator iter;
1318 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1319 rmap_printk("spte %p %llx.\n", sptep, *sptep);
1321 pte_list_remove(rmap_head, sptep);
1328 static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1329 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1332 return kvm_zap_rmapp(kvm, rmap_head, slot);
1335 static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1336 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1340 struct rmap_iterator iter;
1345 WARN_ON(pte_huge(pte));
1346 new_pfn = pte_pfn(pte);
1349 for_each_rmap_spte(rmap_head, &iter, sptep) {
1350 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1351 sptep, *sptep, gfn, level);
1355 if (pte_write(pte)) {
1356 pte_list_remove(rmap_head, sptep);
1359 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1362 mmu_spte_clear_track_bits(sptep);
1363 mmu_spte_set(sptep, new_spte);
1367 if (need_flush && kvm_available_flush_tlb_with_range()) {
1368 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1375 struct slot_rmap_walk_iterator {
1377 struct kvm_memory_slot *slot;
1383 /* output fields. */
1385 struct kvm_rmap_head *rmap;
1388 /* private field. */
1389 struct kvm_rmap_head *end_rmap;
1393 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1395 iterator->level = level;
1396 iterator->gfn = iterator->start_gfn;
1397 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1398 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1403 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1404 struct kvm_memory_slot *slot, int start_level,
1405 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1407 iterator->slot = slot;
1408 iterator->start_level = start_level;
1409 iterator->end_level = end_level;
1410 iterator->start_gfn = start_gfn;
1411 iterator->end_gfn = end_gfn;
1413 rmap_walk_init_level(iterator, iterator->start_level);
1416 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1418 return !!iterator->rmap;
1421 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1423 if (++iterator->rmap <= iterator->end_rmap) {
1424 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1428 if (++iterator->level > iterator->end_level) {
1429 iterator->rmap = NULL;
1433 rmap_walk_init_level(iterator, iterator->level);
1436 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1437 _start_gfn, _end_gfn, _iter_) \
1438 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1439 _end_level_, _start_gfn, _end_gfn); \
1440 slot_rmap_walk_okay(_iter_); \
1441 slot_rmap_walk_next(_iter_))
1443 typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1444 struct kvm_memory_slot *slot, gfn_t gfn,
1445 int level, pte_t pte);
1447 static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm,
1448 struct kvm_gfn_range *range,
1449 rmap_handler_t handler)
1451 struct slot_rmap_walk_iterator iterator;
1454 for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL,
1455 range->start, range->end - 1, &iterator)
1456 ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn,
1457 iterator.level, range->pte);
1462 bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range)
1466 if (kvm_memslots_have_rmaps(kvm))
1467 flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp);
1469 if (is_tdp_mmu_enabled(kvm))
1470 flush |= kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush);
1475 bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1479 if (kvm_memslots_have_rmaps(kvm))
1480 flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp);
1482 if (is_tdp_mmu_enabled(kvm))
1483 flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range);
1488 static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1489 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1493 struct rmap_iterator iter;
1496 for_each_rmap_spte(rmap_head, &iter, sptep)
1497 young |= mmu_spte_age(sptep);
1502 static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1503 struct kvm_memory_slot *slot, gfn_t gfn,
1504 int level, pte_t unused)
1507 struct rmap_iterator iter;
1509 for_each_rmap_spte(rmap_head, &iter, sptep)
1510 if (is_accessed_spte(*sptep))
1515 #define RMAP_RECYCLE_THRESHOLD 1000
1517 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1519 struct kvm_rmap_head *rmap_head;
1520 struct kvm_mmu_page *sp;
1522 sp = sptep_to_sp(spte);
1524 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1526 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0));
1527 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1528 KVM_PAGES_PER_HPAGE(sp->role.level));
1531 bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1535 if (kvm_memslots_have_rmaps(kvm))
1536 young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp);
1538 if (is_tdp_mmu_enabled(kvm))
1539 young |= kvm_tdp_mmu_age_gfn_range(kvm, range);
1544 bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1548 if (kvm_memslots_have_rmaps(kvm))
1549 young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp);
1551 if (is_tdp_mmu_enabled(kvm))
1552 young |= kvm_tdp_mmu_test_age_gfn(kvm, range);
1558 static int is_empty_shadow_page(u64 *spt)
1563 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1564 if (is_shadow_present_pte(*pos)) {
1565 printk(KERN_ERR "%s: %p %llx\n", __func__,
1574 * This value is the sum of all of the kvm instances's
1575 * kvm->arch.n_used_mmu_pages values. We need a global,
1576 * aggregate version in order to make the slab shrinker
1579 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
1581 kvm->arch.n_used_mmu_pages += nr;
1582 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1585 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1587 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1588 hlist_del(&sp->hash_link);
1589 list_del(&sp->link);
1590 free_page((unsigned long)sp->spt);
1591 if (!sp->role.direct)
1592 free_page((unsigned long)sp->gfns);
1593 kmem_cache_free(mmu_page_header_cache, sp);
1596 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1598 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1601 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1602 struct kvm_mmu_page *sp, u64 *parent_pte)
1607 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1610 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1613 __pte_list_remove(parent_pte, &sp->parent_ptes);
1616 static void drop_parent_pte(struct kvm_mmu_page *sp,
1619 mmu_page_remove_parent_pte(sp, parent_pte);
1620 mmu_spte_clear_no_track(parent_pte);
1623 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1625 struct kvm_mmu_page *sp;
1627 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1628 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1630 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1631 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1634 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1635 * depends on valid pages being added to the head of the list. See
1636 * comments in kvm_zap_obsolete_pages().
1638 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1639 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1640 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1644 static void mark_unsync(u64 *spte);
1645 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1648 struct rmap_iterator iter;
1650 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1655 static void mark_unsync(u64 *spte)
1657 struct kvm_mmu_page *sp;
1660 sp = sptep_to_sp(spte);
1661 index = spte - sp->spt;
1662 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1664 if (sp->unsync_children++)
1666 kvm_mmu_mark_parents_unsync(sp);
1669 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1670 struct kvm_mmu_page *sp)
1675 #define KVM_PAGE_ARRAY_NR 16
1677 struct kvm_mmu_pages {
1678 struct mmu_page_and_offset {
1679 struct kvm_mmu_page *sp;
1681 } page[KVM_PAGE_ARRAY_NR];
1685 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1691 for (i=0; i < pvec->nr; i++)
1692 if (pvec->page[i].sp == sp)
1695 pvec->page[pvec->nr].sp = sp;
1696 pvec->page[pvec->nr].idx = idx;
1698 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1701 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1703 --sp->unsync_children;
1704 WARN_ON((int)sp->unsync_children < 0);
1705 __clear_bit(idx, sp->unsync_child_bitmap);
1708 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1709 struct kvm_mmu_pages *pvec)
1711 int i, ret, nr_unsync_leaf = 0;
1713 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1714 struct kvm_mmu_page *child;
1715 u64 ent = sp->spt[i];
1717 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1718 clear_unsync_child_bit(sp, i);
1722 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1724 if (child->unsync_children) {
1725 if (mmu_pages_add(pvec, child, i))
1728 ret = __mmu_unsync_walk(child, pvec);
1730 clear_unsync_child_bit(sp, i);
1732 } else if (ret > 0) {
1733 nr_unsync_leaf += ret;
1736 } else if (child->unsync) {
1738 if (mmu_pages_add(pvec, child, i))
1741 clear_unsync_child_bit(sp, i);
1744 return nr_unsync_leaf;
1747 #define INVALID_INDEX (-1)
1749 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1750 struct kvm_mmu_pages *pvec)
1753 if (!sp->unsync_children)
1756 mmu_pages_add(pvec, sp, INVALID_INDEX);
1757 return __mmu_unsync_walk(sp, pvec);
1760 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1762 WARN_ON(!sp->unsync);
1763 trace_kvm_mmu_sync_page(sp);
1765 --kvm->stat.mmu_unsync;
1768 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1769 struct list_head *invalid_list);
1770 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1771 struct list_head *invalid_list);
1773 #define for_each_valid_sp(_kvm, _sp, _list) \
1774 hlist_for_each_entry(_sp, _list, hash_link) \
1775 if (is_obsolete_sp((_kvm), (_sp))) { \
1778 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1779 for_each_valid_sp(_kvm, _sp, \
1780 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1781 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1783 static inline bool is_ept_sp(struct kvm_mmu_page *sp)
1785 return sp->role.cr0_wp && sp->role.smap_andnot_wp;
1788 /* @sp->gfn should be write-protected at the call site */
1789 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1790 struct list_head *invalid_list)
1792 if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) ||
1793 vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
1794 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1801 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1802 struct list_head *invalid_list,
1805 if (!remote_flush && list_empty(invalid_list))
1808 if (!list_empty(invalid_list))
1809 kvm_mmu_commit_zap_page(kvm, invalid_list);
1811 kvm_flush_remote_tlbs(kvm);
1815 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1816 struct list_head *invalid_list,
1817 bool remote_flush, bool local_flush)
1819 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
1823 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1826 #ifdef CONFIG_KVM_MMU_AUDIT
1827 #include "mmu_audit.c"
1829 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1830 static void mmu_audit_disable(void) { }
1833 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1835 return sp->role.invalid ||
1836 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1839 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1840 struct list_head *invalid_list)
1842 kvm_unlink_unsync_page(vcpu->kvm, sp);
1843 return __kvm_sync_page(vcpu, sp, invalid_list);
1846 /* @gfn should be write-protected at the call site */
1847 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
1848 struct list_head *invalid_list)
1850 struct kvm_mmu_page *s;
1853 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1857 WARN_ON(s->role.level != PG_LEVEL_4K);
1858 ret |= kvm_sync_page(vcpu, s, invalid_list);
1864 struct mmu_page_path {
1865 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1866 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1869 #define for_each_sp(pvec, sp, parents, i) \
1870 for (i = mmu_pages_first(&pvec, &parents); \
1871 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1872 i = mmu_pages_next(&pvec, &parents, i))
1874 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1875 struct mmu_page_path *parents,
1880 for (n = i+1; n < pvec->nr; n++) {
1881 struct kvm_mmu_page *sp = pvec->page[n].sp;
1882 unsigned idx = pvec->page[n].idx;
1883 int level = sp->role.level;
1885 parents->idx[level-1] = idx;
1886 if (level == PG_LEVEL_4K)
1889 parents->parent[level-2] = sp;
1895 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1896 struct mmu_page_path *parents)
1898 struct kvm_mmu_page *sp;
1904 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1906 sp = pvec->page[0].sp;
1907 level = sp->role.level;
1908 WARN_ON(level == PG_LEVEL_4K);
1910 parents->parent[level-2] = sp;
1912 /* Also set up a sentinel. Further entries in pvec are all
1913 * children of sp, so this element is never overwritten.
1915 parents->parent[level-1] = NULL;
1916 return mmu_pages_next(pvec, parents, 0);
1919 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1921 struct kvm_mmu_page *sp;
1922 unsigned int level = 0;
1925 unsigned int idx = parents->idx[level];
1926 sp = parents->parent[level];
1930 WARN_ON(idx == INVALID_INDEX);
1931 clear_unsync_child_bit(sp, idx);
1933 } while (!sp->unsync_children);
1936 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1937 struct kvm_mmu_page *parent)
1940 struct kvm_mmu_page *sp;
1941 struct mmu_page_path parents;
1942 struct kvm_mmu_pages pages;
1943 LIST_HEAD(invalid_list);
1946 while (mmu_unsync_walk(parent, &pages)) {
1947 bool protected = false;
1949 for_each_sp(pages, sp, parents, i)
1950 protected |= rmap_write_protect(vcpu, sp->gfn);
1953 kvm_flush_remote_tlbs(vcpu->kvm);
1957 for_each_sp(pages, sp, parents, i) {
1958 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
1959 mmu_pages_clear_parents(&parents);
1961 if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) {
1962 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1963 cond_resched_rwlock_write(&vcpu->kvm->mmu_lock);
1968 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1971 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1973 atomic_set(&sp->write_flooding_count, 0);
1976 static void clear_sp_write_flooding_count(u64 *spte)
1978 __clear_sp_write_flooding_count(sptep_to_sp(spte));
1981 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1986 unsigned int access)
1988 bool direct_mmu = vcpu->arch.mmu->direct_map;
1989 union kvm_mmu_page_role role;
1990 struct hlist_head *sp_list;
1992 struct kvm_mmu_page *sp;
1993 bool need_sync = false;
1996 LIST_HEAD(invalid_list);
1998 role = vcpu->arch.mmu->mmu_role.base;
2000 role.direct = direct;
2002 role.gpte_is_8_bytes = true;
2003 role.access = access;
2004 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2005 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2006 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2007 role.quadrant = quadrant;
2010 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2011 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2012 if (sp->gfn != gfn) {
2017 if (!need_sync && sp->unsync)
2020 if (sp->role.word != role.word)
2024 goto trace_get_page;
2027 /* The page is good, but __kvm_sync_page might still end
2028 * up zapping it. If so, break in order to rebuild it.
2030 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2033 WARN_ON(!list_empty(&invalid_list));
2034 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2037 if (sp->unsync_children)
2038 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2040 __clear_sp_write_flooding_count(sp);
2043 trace_kvm_mmu_get_page(sp, false);
2047 ++vcpu->kvm->stat.mmu_cache_miss;
2049 sp = kvm_mmu_alloc_page(vcpu, direct);
2053 hlist_add_head(&sp->hash_link, sp_list);
2056 * we should do write protection before syncing pages
2057 * otherwise the content of the synced shadow page may
2058 * be inconsistent with guest page table.
2060 account_shadowed(vcpu->kvm, sp);
2061 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2062 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2064 if (level > PG_LEVEL_4K && need_sync)
2065 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2067 trace_kvm_mmu_get_page(sp, true);
2069 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2071 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2072 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2076 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2077 struct kvm_vcpu *vcpu, hpa_t root,
2080 iterator->addr = addr;
2081 iterator->shadow_addr = root;
2082 iterator->level = vcpu->arch.mmu->shadow_root_level;
2084 if (iterator->level == PT64_ROOT_4LEVEL &&
2085 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2086 !vcpu->arch.mmu->direct_map)
2089 if (iterator->level == PT32E_ROOT_LEVEL) {
2091 * prev_root is currently only used for 64-bit hosts. So only
2092 * the active root_hpa is valid here.
2094 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2096 iterator->shadow_addr
2097 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2098 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2100 if (!iterator->shadow_addr)
2101 iterator->level = 0;
2105 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2106 struct kvm_vcpu *vcpu, u64 addr)
2108 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2112 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2114 if (iterator->level < PG_LEVEL_4K)
2117 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2118 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2122 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2125 if (is_last_spte(spte, iterator->level)) {
2126 iterator->level = 0;
2130 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2134 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2136 __shadow_walk_next(iterator, *iterator->sptep);
2139 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2140 struct kvm_mmu_page *sp)
2144 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2146 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2148 mmu_spte_set(sptep, spte);
2150 mmu_page_add_parent_pte(vcpu, sp, sptep);
2152 if (sp->unsync_children || sp->unsync)
2156 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2157 unsigned direct_access)
2159 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2160 struct kvm_mmu_page *child;
2163 * For the direct sp, if the guest pte's dirty bit
2164 * changed form clean to dirty, it will corrupt the
2165 * sp's access: allow writable in the read-only sp,
2166 * so we should update the spte at this point to get
2167 * a new sp with the correct access.
2169 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2170 if (child->role.access == direct_access)
2173 drop_parent_pte(child, sptep);
2174 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2178 /* Returns the number of zapped non-leaf child shadow pages. */
2179 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2180 u64 *spte, struct list_head *invalid_list)
2183 struct kvm_mmu_page *child;
2186 if (is_shadow_present_pte(pte)) {
2187 if (is_last_spte(pte, sp->role.level)) {
2188 drop_spte(kvm, spte);
2189 if (is_large_pte(pte))
2192 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2193 drop_parent_pte(child, spte);
2196 * Recursively zap nested TDP SPs, parentless SPs are
2197 * unlikely to be used again in the near future. This
2198 * avoids retaining a large number of stale nested SPs.
2200 if (tdp_enabled && invalid_list &&
2201 child->role.guest_mode && !child->parent_ptes.val)
2202 return kvm_mmu_prepare_zap_page(kvm, child,
2205 } else if (is_mmio_spte(pte)) {
2206 mmu_spte_clear_no_track(spte);
2211 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2212 struct kvm_mmu_page *sp,
2213 struct list_head *invalid_list)
2218 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2219 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2224 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2227 struct rmap_iterator iter;
2229 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2230 drop_parent_pte(sp, sptep);
2233 static int mmu_zap_unsync_children(struct kvm *kvm,
2234 struct kvm_mmu_page *parent,
2235 struct list_head *invalid_list)
2238 struct mmu_page_path parents;
2239 struct kvm_mmu_pages pages;
2241 if (parent->role.level == PG_LEVEL_4K)
2244 while (mmu_unsync_walk(parent, &pages)) {
2245 struct kvm_mmu_page *sp;
2247 for_each_sp(pages, sp, parents, i) {
2248 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2249 mmu_pages_clear_parents(&parents);
2257 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2258 struct kvm_mmu_page *sp,
2259 struct list_head *invalid_list,
2264 trace_kvm_mmu_prepare_zap_page(sp);
2265 ++kvm->stat.mmu_shadow_zapped;
2266 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2267 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2268 kvm_mmu_unlink_parents(kvm, sp);
2270 /* Zapping children means active_mmu_pages has become unstable. */
2271 list_unstable = *nr_zapped;
2273 if (!sp->role.invalid && !sp->role.direct)
2274 unaccount_shadowed(kvm, sp);
2277 kvm_unlink_unsync_page(kvm, sp);
2278 if (!sp->root_count) {
2283 * Already invalid pages (previously active roots) are not on
2284 * the active page list. See list_del() in the "else" case of
2287 if (sp->role.invalid)
2288 list_add(&sp->link, invalid_list);
2290 list_move(&sp->link, invalid_list);
2291 kvm_mod_used_mmu_pages(kvm, -1);
2294 * Remove the active root from the active page list, the root
2295 * will be explicitly freed when the root_count hits zero.
2297 list_del(&sp->link);
2300 * Obsolete pages cannot be used on any vCPUs, see the comment
2301 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2302 * treats invalid shadow pages as being obsolete.
2304 if (!is_obsolete_sp(kvm, sp))
2305 kvm_reload_remote_mmus(kvm);
2308 if (sp->lpage_disallowed)
2309 unaccount_huge_nx_page(kvm, sp);
2311 sp->role.invalid = 1;
2312 return list_unstable;
2315 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2316 struct list_head *invalid_list)
2320 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2324 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2325 struct list_head *invalid_list)
2327 struct kvm_mmu_page *sp, *nsp;
2329 if (list_empty(invalid_list))
2333 * We need to make sure everyone sees our modifications to
2334 * the page tables and see changes to vcpu->mode here. The barrier
2335 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2336 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2338 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2339 * guest mode and/or lockless shadow page table walks.
2341 kvm_flush_remote_tlbs(kvm);
2343 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2344 WARN_ON(!sp->role.invalid || sp->root_count);
2345 kvm_mmu_free_page(sp);
2349 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2350 unsigned long nr_to_zap)
2352 unsigned long total_zapped = 0;
2353 struct kvm_mmu_page *sp, *tmp;
2354 LIST_HEAD(invalid_list);
2358 if (list_empty(&kvm->arch.active_mmu_pages))
2362 list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2364 * Don't zap active root pages, the page itself can't be freed
2365 * and zapping it will just force vCPUs to realloc and reload.
2370 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2372 total_zapped += nr_zapped;
2373 if (total_zapped >= nr_to_zap)
2380 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2382 kvm->stat.mmu_recycled += total_zapped;
2383 return total_zapped;
2386 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2388 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2389 return kvm->arch.n_max_mmu_pages -
2390 kvm->arch.n_used_mmu_pages;
2395 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2397 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2399 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2402 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2405 * Note, this check is intentionally soft, it only guarantees that one
2406 * page is available, while the caller may end up allocating as many as
2407 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2408 * exceeding the (arbitrary by default) limit will not harm the host,
2409 * being too agressive may unnecessarily kill the guest, and getting an
2410 * exact count is far more trouble than it's worth, especially in the
2413 if (!kvm_mmu_available_pages(vcpu->kvm))
2419 * Changing the number of mmu pages allocated to the vm
2420 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2422 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2424 write_lock(&kvm->mmu_lock);
2426 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2427 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2430 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2433 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2435 write_unlock(&kvm->mmu_lock);
2438 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2440 struct kvm_mmu_page *sp;
2441 LIST_HEAD(invalid_list);
2444 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2446 write_lock(&kvm->mmu_lock);
2447 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2448 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2451 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2453 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2454 write_unlock(&kvm->mmu_lock);
2459 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2464 if (vcpu->arch.mmu->direct_map)
2467 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2469 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2474 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2476 trace_kvm_mmu_unsync_page(sp);
2477 ++vcpu->kvm->stat.mmu_unsync;
2480 kvm_mmu_mark_parents_unsync(sp);
2483 bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2486 struct kvm_mmu_page *sp;
2488 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2491 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2498 WARN_ON(sp->role.level != PG_LEVEL_4K);
2499 kvm_unsync_page(vcpu, sp);
2503 * We need to ensure that the marking of unsync pages is visible
2504 * before the SPTE is updated to allow writes because
2505 * kvm_mmu_sync_roots() checks the unsync flags without holding
2506 * the MMU lock and so can race with this. If the SPTE was updated
2507 * before the page had been marked as unsync-ed, something like the
2508 * following could happen:
2511 * ---------------------------------------------------------------------
2512 * 1.2 Host updates SPTE
2514 * 2.1 Guest writes a GPTE for GVA X.
2515 * (GPTE being in the guest page table shadowed
2516 * by the SP from CPU 1.)
2517 * This reads SPTE during the page table walk.
2518 * Since SPTE.W is read as 1, there is no
2521 * 2.2 Guest issues TLB flush.
2522 * That causes a VM Exit.
2524 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2525 * Since it is false, so it just returns.
2527 * 2.4 Guest accesses GVA X.
2528 * Since the mapping in the SP was not updated,
2529 * so the old mapping for GVA X incorrectly
2533 * (sp->unsync = true)
2535 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2536 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2537 * pairs with this write barrier.
2544 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2545 unsigned int pte_access, int level,
2546 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2547 bool can_unsync, bool host_writable)
2550 struct kvm_mmu_page *sp;
2553 sp = sptep_to_sp(sptep);
2555 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2556 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2558 if (spte & PT_WRITABLE_MASK)
2559 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2562 ret |= SET_SPTE_SPURIOUS;
2563 else if (mmu_spte_update(sptep, spte))
2564 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2568 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2569 unsigned int pte_access, bool write_fault, int level,
2570 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2573 int was_rmapped = 0;
2576 int ret = RET_PF_FIXED;
2579 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2580 *sptep, write_fault, gfn);
2582 if (unlikely(is_noslot_pfn(pfn))) {
2583 mark_mmio_spte(vcpu, sptep, gfn, pte_access);
2584 return RET_PF_EMULATE;
2587 if (is_shadow_present_pte(*sptep)) {
2589 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2590 * the parent of the now unreachable PTE.
2592 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2593 struct kvm_mmu_page *child;
2596 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2597 drop_parent_pte(child, sptep);
2599 } else if (pfn != spte_to_pfn(*sptep)) {
2600 pgprintk("hfn old %llx new %llx\n",
2601 spte_to_pfn(*sptep), pfn);
2602 drop_spte(vcpu->kvm, sptep);
2608 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2609 speculative, true, host_writable);
2610 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2612 ret = RET_PF_EMULATE;
2613 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2616 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2617 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2618 KVM_PAGES_PER_HPAGE(level));
2621 * The fault is fully spurious if and only if the new SPTE and old SPTE
2622 * are identical, and emulation is not required.
2624 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2625 WARN_ON_ONCE(!was_rmapped);
2626 return RET_PF_SPURIOUS;
2629 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2630 trace_kvm_mmu_set_spte(level, gfn, sptep);
2631 if (!was_rmapped && is_large_pte(*sptep))
2632 ++vcpu->kvm->stat.lpages;
2634 if (is_shadow_present_pte(*sptep)) {
2636 rmap_count = rmap_add(vcpu, sptep, gfn);
2637 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2638 rmap_recycle(vcpu, sptep, gfn);
2645 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2648 struct kvm_memory_slot *slot;
2650 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2652 return KVM_PFN_ERR_FAULT;
2654 return gfn_to_pfn_memslot_atomic(slot, gfn);
2657 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2658 struct kvm_mmu_page *sp,
2659 u64 *start, u64 *end)
2661 struct page *pages[PTE_PREFETCH_NUM];
2662 struct kvm_memory_slot *slot;
2663 unsigned int access = sp->role.access;
2667 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2668 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2672 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2676 for (i = 0; i < ret; i++, gfn++, start++) {
2677 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2678 page_to_pfn(pages[i]), true, true);
2685 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2686 struct kvm_mmu_page *sp, u64 *sptep)
2688 u64 *spte, *start = NULL;
2691 WARN_ON(!sp->role.direct);
2693 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2696 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2697 if (is_shadow_present_pte(*spte) || spte == sptep) {
2700 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2708 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2710 struct kvm_mmu_page *sp;
2712 sp = sptep_to_sp(sptep);
2715 * Without accessed bits, there's no way to distinguish between
2716 * actually accessed translations and prefetched, so disable pte
2717 * prefetch if accessed bits aren't available.
2719 if (sp_ad_disabled(sp))
2722 if (sp->role.level > PG_LEVEL_4K)
2726 * If addresses are being invalidated, skip prefetching to avoid
2727 * accidentally prefetching those addresses.
2729 if (unlikely(vcpu->kvm->mmu_notifier_count))
2732 __direct_pte_prefetch(vcpu, sp, sptep);
2735 static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
2736 const struct kvm_memory_slot *slot)
2742 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2746 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2747 * is not solely for performance, it's also necessary to avoid the
2748 * "writable" check in __gfn_to_hva_many(), which will always fail on
2749 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2750 * page fault steps have already verified the guest isn't writing a
2751 * read-only memslot.
2753 hva = __gfn_to_hva_memslot(slot, gfn);
2755 pte = lookup_address_in_mm(kvm->mm, hva, &level);
2762 int kvm_mmu_max_mapping_level(struct kvm *kvm,
2763 const struct kvm_memory_slot *slot, gfn_t gfn,
2764 kvm_pfn_t pfn, int max_level)
2766 struct kvm_lpage_info *linfo;
2768 max_level = min(max_level, max_huge_page_level);
2769 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2770 linfo = lpage_info_slot(gfn, slot, max_level);
2771 if (!linfo->disallow_lpage)
2775 if (max_level == PG_LEVEL_4K)
2778 return host_pfn_mapping_level(kvm, gfn, pfn, slot);
2781 int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2782 int max_level, kvm_pfn_t *pfnp,
2783 bool huge_page_disallowed, int *req_level)
2785 struct kvm_memory_slot *slot;
2786 kvm_pfn_t pfn = *pfnp;
2790 *req_level = PG_LEVEL_4K;
2792 if (unlikely(max_level == PG_LEVEL_4K))
2795 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
2798 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2802 level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level);
2803 if (level == PG_LEVEL_4K)
2806 *req_level = level = min(level, max_level);
2809 * Enforce the iTLB multihit workaround after capturing the requested
2810 * level, which will be used to do precise, accurate accounting.
2812 if (huge_page_disallowed)
2816 * mmu_notifier_retry() was successful and mmu_lock is held, so
2817 * the pmd can't be split from under us.
2819 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2820 VM_BUG_ON((gfn & mask) != (pfn & mask));
2821 *pfnp = pfn & ~mask;
2826 void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2827 kvm_pfn_t *pfnp, int *goal_levelp)
2829 int level = *goal_levelp;
2831 if (cur_level == level && level > PG_LEVEL_4K &&
2832 is_shadow_present_pte(spte) &&
2833 !is_large_pte(spte)) {
2835 * A small SPTE exists for this pfn, but FNAME(fetch)
2836 * and __direct_map would like to create a large PTE
2837 * instead: just force them to go down another level,
2838 * patching back for them into pfn the next 9 bits of
2841 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2842 KVM_PAGES_PER_HPAGE(level - 1);
2843 *pfnp |= gfn & page_mask;
2848 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
2849 int map_writable, int max_level, kvm_pfn_t pfn,
2850 bool prefault, bool is_tdp)
2852 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2853 bool write = error_code & PFERR_WRITE_MASK;
2854 bool exec = error_code & PFERR_FETCH_MASK;
2855 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
2856 struct kvm_shadow_walk_iterator it;
2857 struct kvm_mmu_page *sp;
2858 int level, req_level, ret;
2859 gfn_t gfn = gpa >> PAGE_SHIFT;
2860 gfn_t base_gfn = gfn;
2862 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2863 huge_page_disallowed, &req_level);
2865 trace_kvm_mmu_spte_requested(gpa, level, pfn);
2866 for_each_shadow_entry(vcpu, gpa, it) {
2868 * We cannot overwrite existing page tables with an NX
2869 * large page, as the leaf could be executable.
2871 if (nx_huge_page_workaround_enabled)
2872 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
2875 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2876 if (it.level == level)
2879 drop_large_spte(vcpu, it.sptep);
2880 if (!is_shadow_present_pte(*it.sptep)) {
2881 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2882 it.level - 1, true, ACC_ALL);
2884 link_shadow_page(vcpu, it.sptep, sp);
2885 if (is_tdp && huge_page_disallowed &&
2886 req_level >= it.level)
2887 account_huge_nx_page(vcpu->kvm, sp);
2891 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2892 write, level, base_gfn, pfn, prefault,
2894 if (ret == RET_PF_SPURIOUS)
2897 direct_pte_prefetch(vcpu, it.sptep);
2898 ++vcpu->stat.pf_fixed;
2902 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2904 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2907 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2910 * Do not cache the mmio info caused by writing the readonly gfn
2911 * into the spte otherwise read access on readonly gfn also can
2912 * caused mmio page fault and treat it as mmio access.
2914 if (pfn == KVM_PFN_ERR_RO_FAULT)
2915 return RET_PF_EMULATE;
2917 if (pfn == KVM_PFN_ERR_HWPOISON) {
2918 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2919 return RET_PF_RETRY;
2925 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2926 kvm_pfn_t pfn, unsigned int access,
2929 /* The pfn is invalid, report the error! */
2930 if (unlikely(is_error_pfn(pfn))) {
2931 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2935 if (unlikely(is_noslot_pfn(pfn))) {
2936 vcpu_cache_mmio_info(vcpu, gva, gfn,
2937 access & shadow_mmio_access_mask);
2939 * If MMIO caching is disabled, emulate immediately without
2940 * touching the shadow page tables as attempting to install an
2941 * MMIO SPTE will just be an expensive nop.
2943 if (unlikely(!shadow_mmio_value)) {
2944 *ret_val = RET_PF_EMULATE;
2952 static bool page_fault_can_be_fast(u32 error_code)
2955 * Do not fix the mmio spte with invalid generation number which
2956 * need to be updated by slow page fault path.
2958 if (unlikely(error_code & PFERR_RSVD_MASK))
2961 /* See if the page fault is due to an NX violation */
2962 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
2963 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
2967 * #PF can be fast if:
2968 * 1. The shadow page table entry is not present, which could mean that
2969 * the fault is potentially caused by access tracking (if enabled).
2970 * 2. The shadow page table entry is present and the fault
2971 * is caused by write-protect, that means we just need change the W
2972 * bit of the spte which can be done out of mmu-lock.
2974 * However, if access tracking is disabled we know that a non-present
2975 * page must be a genuine page fault where we have to create a new SPTE.
2976 * So, if access tracking is disabled, we return true only for write
2977 * accesses to a present page.
2980 return shadow_acc_track_mask != 0 ||
2981 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
2982 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
2986 * Returns true if the SPTE was fixed successfully. Otherwise,
2987 * someone else modified the SPTE from its original value.
2990 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2991 u64 *sptep, u64 old_spte, u64 new_spte)
2995 WARN_ON(!sp->role.direct);
2998 * Theoretically we could also set dirty bit (and flush TLB) here in
2999 * order to eliminate unnecessary PML logging. See comments in
3000 * set_spte. But fast_page_fault is very unlikely to happen with PML
3001 * enabled, so we do not do this. This might result in the same GPA
3002 * to be logged in PML buffer again when the write really happens, and
3003 * eventually to be called by mark_page_dirty twice. But it's also no
3004 * harm. This also avoids the TLB flush needed after setting dirty bit
3005 * so non-PML cases won't be impacted.
3007 * Compare with set_spte where instead shadow_dirty_mask is set.
3009 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3012 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3014 * The gfn of direct spte is stable since it is
3015 * calculated by sp->gfn.
3017 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3018 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3024 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3026 if (fault_err_code & PFERR_FETCH_MASK)
3027 return is_executable_pte(spte);
3029 if (fault_err_code & PFERR_WRITE_MASK)
3030 return is_writable_pte(spte);
3032 /* Fault was on Read access */
3033 return spte & PT_PRESENT_MASK;
3037 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3039 static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3042 struct kvm_shadow_walk_iterator iterator;
3043 struct kvm_mmu_page *sp;
3044 int ret = RET_PF_INVALID;
3046 uint retry_count = 0;
3048 if (!page_fault_can_be_fast(error_code))
3051 walk_shadow_page_lockless_begin(vcpu);
3056 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3057 if (!is_shadow_present_pte(spte))
3060 if (!is_shadow_present_pte(spte))
3063 sp = sptep_to_sp(iterator.sptep);
3064 if (!is_last_spte(spte, sp->role.level))
3068 * Check whether the memory access that caused the fault would
3069 * still cause it if it were to be performed right now. If not,
3070 * then this is a spurious fault caused by TLB lazily flushed,
3071 * or some other CPU has already fixed the PTE after the
3072 * current CPU took the fault.
3074 * Need not check the access of upper level table entries since
3075 * they are always ACC_ALL.
3077 if (is_access_allowed(error_code, spte)) {
3078 ret = RET_PF_SPURIOUS;
3084 if (is_access_track_spte(spte))
3085 new_spte = restore_acc_track_spte(new_spte);
3088 * Currently, to simplify the code, write-protection can
3089 * be removed in the fast path only if the SPTE was
3090 * write-protected for dirty-logging or access tracking.
3092 if ((error_code & PFERR_WRITE_MASK) &&
3093 spte_can_locklessly_be_made_writable(spte)) {
3094 new_spte |= PT_WRITABLE_MASK;
3097 * Do not fix write-permission on the large spte. Since
3098 * we only dirty the first page into the dirty-bitmap in
3099 * fast_pf_fix_direct_spte(), other pages are missed
3100 * if its slot has dirty logging enabled.
3102 * Instead, we let the slow page fault path create a
3103 * normal spte to fix the access.
3105 * See the comments in kvm_arch_commit_memory_region().
3107 if (sp->role.level > PG_LEVEL_4K)
3111 /* Verify that the fault can be handled in the fast path */
3112 if (new_spte == spte ||
3113 !is_access_allowed(error_code, new_spte))
3117 * Currently, fast page fault only works for direct mapping
3118 * since the gfn is not stable for indirect shadow page. See
3119 * Documentation/virt/kvm/locking.rst to get more detail.
3121 if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte,
3127 if (++retry_count > 4) {
3128 printk_once(KERN_WARNING
3129 "kvm: Fast #PF retrying more than 4 times.\n");
3135 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3137 walk_shadow_page_lockless_end(vcpu);
3142 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3143 struct list_head *invalid_list)
3145 struct kvm_mmu_page *sp;
3147 if (!VALID_PAGE(*root_hpa))
3150 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3152 if (is_tdp_mmu_page(sp))
3153 kvm_tdp_mmu_put_root(kvm, sp, false);
3154 else if (!--sp->root_count && sp->role.invalid)
3155 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3157 *root_hpa = INVALID_PAGE;
3160 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3161 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3162 ulong roots_to_free)
3164 struct kvm *kvm = vcpu->kvm;
3166 LIST_HEAD(invalid_list);
3167 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3169 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3171 /* Before acquiring the MMU lock, see if we need to do any real work. */
3172 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3173 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3174 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3175 VALID_PAGE(mmu->prev_roots[i].hpa))
3178 if (i == KVM_MMU_NUM_PREV_ROOTS)
3182 write_lock(&kvm->mmu_lock);
3184 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3185 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3186 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3189 if (free_active_root) {
3190 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3191 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3192 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3193 } else if (mmu->pae_root) {
3194 for (i = 0; i < 4; ++i) {
3195 if (!IS_VALID_PAE_ROOT(mmu->pae_root[i]))
3198 mmu_free_root_page(kvm, &mmu->pae_root[i],
3200 mmu->pae_root[i] = INVALID_PAE_ROOT;
3203 mmu->root_hpa = INVALID_PAGE;
3207 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3208 write_unlock(&kvm->mmu_lock);
3210 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3212 void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3214 unsigned long roots_to_free = 0;
3219 * This should not be called while L2 is active, L2 can't invalidate
3220 * _only_ its own roots, e.g. INVVPID unconditionally exits.
3222 WARN_ON_ONCE(mmu->mmu_role.base.guest_mode);
3224 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3225 root_hpa = mmu->prev_roots[i].hpa;
3226 if (!VALID_PAGE(root_hpa))
3229 if (!to_shadow_page(root_hpa) ||
3230 to_shadow_page(root_hpa)->role.guest_mode)
3231 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
3234 kvm_mmu_free_roots(vcpu, mmu, roots_to_free);
3236 EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots);
3239 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3243 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3244 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3251 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3252 u8 level, bool direct)
3254 struct kvm_mmu_page *sp;
3256 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3259 return __pa(sp->spt);
3262 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3264 struct kvm_mmu *mmu = vcpu->arch.mmu;
3265 u8 shadow_root_level = mmu->shadow_root_level;
3270 write_lock(&vcpu->kvm->mmu_lock);
3271 r = make_mmu_pages_available(vcpu);
3275 if (is_tdp_mmu_enabled(vcpu->kvm)) {
3276 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3277 mmu->root_hpa = root;
3278 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3279 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true);
3280 mmu->root_hpa = root;
3281 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3282 if (WARN_ON_ONCE(!mmu->pae_root)) {
3287 for (i = 0; i < 4; ++i) {
3288 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3290 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3291 i << 30, PT32_ROOT_LEVEL, true);
3292 mmu->pae_root[i] = root | PT_PRESENT_MASK |
3295 mmu->root_hpa = __pa(mmu->pae_root);
3297 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level);
3302 /* root_pgd is ignored for direct MMUs. */
3305 write_unlock(&vcpu->kvm->mmu_lock);
3309 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3311 struct kvm_mmu *mmu = vcpu->arch.mmu;
3312 u64 pdptrs[4], pm_mask;
3313 gfn_t root_gfn, root_pgd;
3318 root_pgd = mmu->get_guest_pgd(vcpu);
3319 root_gfn = root_pgd >> PAGE_SHIFT;
3321 if (mmu_check_root(vcpu, root_gfn))
3325 * On SVM, reading PDPTRs might access guest memory, which might fault
3326 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3328 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3329 for (i = 0; i < 4; ++i) {
3330 pdptrs[i] = mmu->get_pdptr(vcpu, i);
3331 if (!(pdptrs[i] & PT_PRESENT_MASK))
3334 if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT))
3339 r = alloc_all_memslots_rmaps(vcpu->kvm);
3343 write_lock(&vcpu->kvm->mmu_lock);
3344 r = make_mmu_pages_available(vcpu);
3349 * Do we shadow a long mode page table? If so we need to
3350 * write-protect the guests page table root.
3352 if (mmu->root_level >= PT64_ROOT_4LEVEL) {
3353 root = mmu_alloc_root(vcpu, root_gfn, 0,
3354 mmu->shadow_root_level, false);
3355 mmu->root_hpa = root;
3359 if (WARN_ON_ONCE(!mmu->pae_root)) {
3365 * We shadow a 32 bit page table. This may be a legacy 2-level
3366 * or a PAE 3-level page table. In either case we need to be aware that
3367 * the shadow page table may be a PAE or a long mode page table.
3369 pm_mask = PT_PRESENT_MASK | shadow_me_mask;
3370 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3371 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3373 if (WARN_ON_ONCE(!mmu->pml4_root)) {
3378 mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask;
3381 for (i = 0; i < 4; ++i) {
3382 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3384 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3385 if (!(pdptrs[i] & PT_PRESENT_MASK)) {
3386 mmu->pae_root[i] = INVALID_PAE_ROOT;
3389 root_gfn = pdptrs[i] >> PAGE_SHIFT;
3392 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3393 PT32_ROOT_LEVEL, false);
3394 mmu->pae_root[i] = root | pm_mask;
3397 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3398 mmu->root_hpa = __pa(mmu->pml4_root);
3400 mmu->root_hpa = __pa(mmu->pae_root);
3403 mmu->root_pgd = root_pgd;
3405 write_unlock(&vcpu->kvm->mmu_lock);
3410 static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu)
3412 struct kvm_mmu *mmu = vcpu->arch.mmu;
3413 u64 *pml4_root, *pae_root;
3416 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3417 * tables are allocated and initialized at root creation as there is no
3418 * equivalent level in the guest's NPT to shadow. Allocate the tables
3419 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
3421 if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL ||
3422 mmu->shadow_root_level < PT64_ROOT_4LEVEL)
3426 * This mess only works with 4-level paging and needs to be updated to
3427 * work with 5-level paging.
3429 if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL))
3432 if (mmu->pae_root && mmu->pml4_root)
3436 * The special roots should always be allocated in concert. Yell and
3437 * bail if KVM ends up in a state where only one of the roots is valid.
3439 if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root))
3443 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3444 * doesn't need to be decrypted.
3446 pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3450 pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3452 free_page((unsigned long)pae_root);
3456 mmu->pae_root = pae_root;
3457 mmu->pml4_root = pml4_root;
3462 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3465 struct kvm_mmu_page *sp;
3467 if (vcpu->arch.mmu->direct_map)
3470 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3473 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3475 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3476 hpa_t root = vcpu->arch.mmu->root_hpa;
3477 sp = to_shadow_page(root);
3480 * Even if another CPU was marking the SP as unsync-ed
3481 * simultaneously, any guest page table changes are not
3482 * guaranteed to be visible anyway until this VCPU issues a TLB
3483 * flush strictly after those changes are made. We only need to
3484 * ensure that the other CPU sets these flags before any actual
3485 * changes to the page tables are made. The comments in
3486 * mmu_need_write_protect() describe what could go wrong if this
3487 * requirement isn't satisfied.
3489 if (!smp_load_acquire(&sp->unsync) &&
3490 !smp_load_acquire(&sp->unsync_children))
3493 write_lock(&vcpu->kvm->mmu_lock);
3494 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3496 mmu_sync_children(vcpu, sp);
3498 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3499 write_unlock(&vcpu->kvm->mmu_lock);
3503 write_lock(&vcpu->kvm->mmu_lock);
3504 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3506 for (i = 0; i < 4; ++i) {
3507 hpa_t root = vcpu->arch.mmu->pae_root[i];
3509 if (IS_VALID_PAE_ROOT(root)) {
3510 root &= PT64_BASE_ADDR_MASK;
3511 sp = to_shadow_page(root);
3512 mmu_sync_children(vcpu, sp);
3516 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3517 write_unlock(&vcpu->kvm->mmu_lock);
3520 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3521 u32 access, struct x86_exception *exception)
3524 exception->error_code = 0;
3528 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3530 struct x86_exception *exception)
3533 exception->error_code = 0;
3534 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3538 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3540 int bit7 = (pte >> 7) & 1;
3542 return pte & rsvd_check->rsvd_bits_mask[bit7][level-1];
3545 static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte)
3547 return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
3550 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3553 * A nested guest cannot use the MMIO cache if it is using nested
3554 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3556 if (mmu_is_nested(vcpu))
3560 return vcpu_match_mmio_gpa(vcpu, addr);
3562 return vcpu_match_mmio_gva(vcpu, addr);
3566 * Return the level of the lowest level SPTE added to sptes.
3567 * That SPTE may be non-present.
3569 static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
3571 struct kvm_shadow_walk_iterator iterator;
3575 walk_shadow_page_lockless_begin(vcpu);
3577 for (shadow_walk_init(&iterator, vcpu, addr),
3578 *root_level = iterator.level;
3579 shadow_walk_okay(&iterator);
3580 __shadow_walk_next(&iterator, spte)) {
3581 leaf = iterator.level;
3582 spte = mmu_spte_get_lockless(iterator.sptep);
3586 if (!is_shadow_present_pte(spte))
3590 walk_shadow_page_lockless_end(vcpu);
3595 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3596 static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3598 u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
3599 struct rsvd_bits_validate *rsvd_check;
3600 int root, leaf, level;
3601 bool reserved = false;
3603 if (is_tdp_mmu(vcpu->arch.mmu))
3604 leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
3606 leaf = get_walk(vcpu, addr, sptes, &root);
3608 if (unlikely(leaf < 0)) {
3613 *sptep = sptes[leaf];
3616 * Skip reserved bits checks on the terminal leaf if it's not a valid
3617 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3618 * design, always have reserved bits set. The purpose of the checks is
3619 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3621 if (!is_shadow_present_pte(sptes[leaf]))
3624 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3626 for (level = root; level >= leaf; level--)
3628 * Use a bitwise-OR instead of a logical-OR to aggregate the
3629 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3630 * adding a Jcc in the loop.
3632 reserved |= __is_bad_mt_xwr(rsvd_check, sptes[level]) |
3633 __is_rsvd_bits_set(rsvd_check, sptes[level], level);
3636 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
3638 for (level = root; level >= leaf; level--)
3639 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3640 sptes[level], level,
3641 rsvd_check->rsvd_bits_mask[(sptes[level] >> 7) & 1][level-1]);
3647 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3652 if (mmio_info_in_cache(vcpu, addr, direct))
3653 return RET_PF_EMULATE;
3655 reserved = get_mmio_spte(vcpu, addr, &spte);
3656 if (WARN_ON(reserved))
3659 if (is_mmio_spte(spte)) {
3660 gfn_t gfn = get_mmio_spte_gfn(spte);
3661 unsigned int access = get_mmio_spte_access(spte);
3663 if (!check_mmio_spte(vcpu, spte))
3664 return RET_PF_INVALID;
3669 trace_handle_mmio_page_fault(addr, gfn, access);
3670 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3671 return RET_PF_EMULATE;
3675 * If the page table is zapped by other cpus, let CPU fault again on
3678 return RET_PF_RETRY;
3681 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3682 u32 error_code, gfn_t gfn)
3684 if (unlikely(error_code & PFERR_RSVD_MASK))
3687 if (!(error_code & PFERR_PRESENT_MASK) ||
3688 !(error_code & PFERR_WRITE_MASK))
3692 * guest is writing the page which is write tracked which can
3693 * not be fixed by page fault handler.
3695 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3701 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3703 struct kvm_shadow_walk_iterator iterator;
3706 walk_shadow_page_lockless_begin(vcpu);
3707 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3708 clear_sp_write_flooding_count(iterator.sptep);
3709 if (!is_shadow_present_pte(spte))
3712 walk_shadow_page_lockless_end(vcpu);
3715 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3718 struct kvm_arch_async_pf arch;
3720 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3722 arch.direct_map = vcpu->arch.mmu->direct_map;
3723 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3725 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3726 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3729 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3730 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva,
3731 bool write, bool *writable)
3733 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3737 * Retry the page fault if the gfn hit a memslot that is being deleted
3738 * or moved. This ensures any existing SPTEs for the old memslot will
3739 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3741 if (slot && (slot->flags & KVM_MEMSLOT_INVALID))
3744 /* Don't expose private memslots to L2. */
3745 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3746 *pfn = KVM_PFN_NOSLOT;
3752 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async,
3753 write, writable, hva);
3755 return false; /* *pfn has correct page already */
3757 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3758 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
3759 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3760 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
3761 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3763 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
3767 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL,
3768 write, writable, hva);
3772 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3773 bool prefault, int max_level, bool is_tdp)
3775 bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu);
3776 bool write = error_code & PFERR_WRITE_MASK;
3779 gfn_t gfn = gpa >> PAGE_SHIFT;
3780 unsigned long mmu_seq;
3785 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3786 return RET_PF_EMULATE;
3788 if (!is_tdp_mmu_fault) {
3789 r = fast_page_fault(vcpu, gpa, error_code);
3790 if (r != RET_PF_INVALID)
3794 r = mmu_topup_memory_caches(vcpu, false);
3798 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3801 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, &hva,
3802 write, &map_writable))
3803 return RET_PF_RETRY;
3805 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
3810 if (is_tdp_mmu_fault)
3811 read_lock(&vcpu->kvm->mmu_lock);
3813 write_lock(&vcpu->kvm->mmu_lock);
3815 if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva))
3817 r = make_mmu_pages_available(vcpu);
3821 if (is_tdp_mmu_fault)
3822 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
3825 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
3829 if (is_tdp_mmu_fault)
3830 read_unlock(&vcpu->kvm->mmu_lock);
3832 write_unlock(&vcpu->kvm->mmu_lock);
3833 kvm_release_pfn_clean(pfn);
3837 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
3838 u32 error_code, bool prefault)
3840 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
3842 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3843 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3844 PG_LEVEL_2M, false);
3847 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3848 u64 fault_address, char *insn, int insn_len)
3851 u32 flags = vcpu->arch.apf.host_apf_flags;
3853 #ifndef CONFIG_X86_64
3854 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3855 if (WARN_ON_ONCE(fault_address >> 32))
3859 vcpu->arch.l1tf_flush_l1d = true;
3861 trace_kvm_page_fault(fault_address, error_code);
3863 if (kvm_event_needs_reinjection(vcpu))
3864 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3865 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3867 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
3868 vcpu->arch.apf.host_apf_flags = 0;
3869 local_irq_disable();
3870 kvm_async_pf_task_wait_schedule(fault_address);
3873 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
3878 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3880 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3885 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3886 max_level > PG_LEVEL_4K;
3888 int page_num = KVM_PAGES_PER_HPAGE(max_level);
3889 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
3891 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
3895 return direct_page_fault(vcpu, gpa, error_code, prefault,
3899 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3900 struct kvm_mmu *context)
3902 context->page_fault = nonpaging_page_fault;
3903 context->gva_to_gpa = nonpaging_gva_to_gpa;
3904 context->sync_page = nonpaging_sync_page;
3905 context->invlpg = NULL;
3906 context->root_level = 0;
3907 context->shadow_root_level = PT32E_ROOT_LEVEL;
3908 context->direct_map = true;
3909 context->nx = false;
3912 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
3913 union kvm_mmu_page_role role)
3915 return (role.direct || pgd == root->pgd) &&
3916 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
3917 role.word == to_shadow_page(root->hpa)->role.word;
3921 * Find out if a previously cached root matching the new pgd/role is available.
3922 * The current root is also inserted into the cache.
3923 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3925 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3926 * false is returned. This root should now be freed by the caller.
3928 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3929 union kvm_mmu_page_role new_role)
3932 struct kvm_mmu_root_info root;
3933 struct kvm_mmu *mmu = vcpu->arch.mmu;
3935 root.pgd = mmu->root_pgd;
3936 root.hpa = mmu->root_hpa;
3938 if (is_root_usable(&root, new_pgd, new_role))
3941 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3942 swap(root, mmu->prev_roots[i]);
3944 if (is_root_usable(&root, new_pgd, new_role))
3948 mmu->root_hpa = root.hpa;
3949 mmu->root_pgd = root.pgd;
3951 return i < KVM_MMU_NUM_PREV_ROOTS;
3954 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3955 union kvm_mmu_page_role new_role)
3957 struct kvm_mmu *mmu = vcpu->arch.mmu;
3960 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
3961 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
3962 * later if necessary.
3964 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3965 mmu->root_level >= PT64_ROOT_4LEVEL)
3966 return cached_root_available(vcpu, new_pgd, new_role);
3971 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3972 union kvm_mmu_page_role new_role)
3974 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
3975 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
3980 * It's possible that the cached previous root page is obsolete because
3981 * of a change in the MMU generation number. However, changing the
3982 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
3983 * free the root set here and allocate a new one.
3985 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
3987 if (force_flush_and_sync_on_reuse) {
3988 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
3989 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3993 * The last MMIO access's GVA and GPA are cached in the VCPU. When
3994 * switching to a new CR3, that GVA->GPA mapping may no longer be
3995 * valid. So clear any cached MMIO info even when we don't need to sync
3996 * the shadow page tables.
3998 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4001 * If this is a direct root page, it doesn't have a write flooding
4002 * count. Otherwise, clear the write flooding count.
4004 if (!new_role.direct)
4005 __clear_sp_write_flooding_count(
4006 to_shadow_page(vcpu->arch.mmu->root_hpa));
4009 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd)
4011 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu));
4013 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
4015 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4017 return kvm_read_cr3(vcpu);
4020 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4021 unsigned int access, int *nr_present)
4023 if (unlikely(is_mmio_spte(*sptep))) {
4024 if (gfn != get_mmio_spte_gfn(*sptep)) {
4025 mmu_spte_clear_no_track(sptep);
4030 mark_mmio_spte(vcpu, sptep, gfn, access);
4037 static inline bool is_last_gpte(struct kvm_mmu *mmu,
4038 unsigned level, unsigned gpte)
4041 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4042 * If it is clear, there are no large pages at this level, so clear
4043 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4045 gpte &= level - mmu->last_nonleaf_level;
4048 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
4049 * iff level <= PG_LEVEL_4K, which for our purpose means
4050 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
4052 gpte |= level - PG_LEVEL_4K - 1;
4054 return gpte & PT_PAGE_SIZE_MASK;
4057 #define PTTYPE_EPT 18 /* arbitrary */
4058 #define PTTYPE PTTYPE_EPT
4059 #include "paging_tmpl.h"
4063 #include "paging_tmpl.h"
4067 #include "paging_tmpl.h"
4071 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4072 struct rsvd_bits_validate *rsvd_check,
4073 u64 pa_bits_rsvd, int level, bool nx, bool gbpages,
4076 u64 gbpages_bit_rsvd = 0;
4077 u64 nonleaf_bit8_rsvd = 0;
4080 rsvd_check->bad_mt_xwr = 0;
4083 gbpages_bit_rsvd = rsvd_bits(7, 7);
4085 if (level == PT32E_ROOT_LEVEL)
4086 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62);
4088 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4090 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4092 high_bits_rsvd |= rsvd_bits(63, 63);
4095 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4096 * leaf entries) on AMD CPUs only.
4099 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4102 case PT32_ROOT_LEVEL:
4103 /* no rsvd bits for 2 level 4K page table entries */
4104 rsvd_check->rsvd_bits_mask[0][1] = 0;
4105 rsvd_check->rsvd_bits_mask[0][0] = 0;
4106 rsvd_check->rsvd_bits_mask[1][0] =
4107 rsvd_check->rsvd_bits_mask[0][0];
4110 rsvd_check->rsvd_bits_mask[1][1] = 0;
4114 if (is_cpuid_PSE36())
4115 /* 36bits PSE 4MB page */
4116 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4118 /* 32 bits PSE 4MB page */
4119 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4121 case PT32E_ROOT_LEVEL:
4122 rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
4125 rsvd_bits(1, 2); /* PDPTE */
4126 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
4127 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
4128 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4129 rsvd_bits(13, 20); /* large page */
4130 rsvd_check->rsvd_bits_mask[1][0] =
4131 rsvd_check->rsvd_bits_mask[0][0];
4133 case PT64_ROOT_5LEVEL:
4134 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd |
4137 rsvd_check->rsvd_bits_mask[1][4] =
4138 rsvd_check->rsvd_bits_mask[0][4];
4140 case PT64_ROOT_4LEVEL:
4141 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd |
4144 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd |
4146 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd;
4147 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4148 rsvd_check->rsvd_bits_mask[1][3] =
4149 rsvd_check->rsvd_bits_mask[0][3];
4150 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd |
4153 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4154 rsvd_bits(13, 20); /* large page */
4155 rsvd_check->rsvd_bits_mask[1][0] =
4156 rsvd_check->rsvd_bits_mask[0][0];
4161 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4162 struct kvm_mmu *context)
4164 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4165 vcpu->arch.reserved_gpa_bits,
4166 context->root_level, context->nx,
4167 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4169 guest_cpuid_is_amd_or_hygon(vcpu));
4173 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4174 u64 pa_bits_rsvd, bool execonly)
4176 u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4179 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
4180 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
4181 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6);
4182 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6);
4183 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4186 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4187 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4188 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29);
4189 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20);
4190 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4192 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4193 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4194 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4195 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4196 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4198 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4199 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4201 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4204 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4205 struct kvm_mmu *context, bool execonly)
4207 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4208 vcpu->arch.reserved_gpa_bits, execonly);
4211 static inline u64 reserved_hpa_bits(void)
4213 return rsvd_bits(shadow_phys_bits, 63);
4217 * the page table on host is the shadow page table for the page
4218 * table in guest or amd nested guest, its mmu features completely
4219 * follow the features in guest.
4222 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4225 * KVM uses NX when TDP is disabled to handle a variety of scenarios,
4226 * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
4227 * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
4228 * The iTLB multi-hit workaround can be toggled at any time, so assume
4229 * NX can be used by any non-nested shadow MMU to avoid having to reset
4230 * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
4232 bool uses_nx = context->nx || !tdp_enabled ||
4233 context->mmu_role.base.smep_andnot_wp;
4234 struct rsvd_bits_validate *shadow_zero_check;
4238 * Passing "true" to the last argument is okay; it adds a check
4239 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4241 shadow_zero_check = &context->shadow_zero_check;
4242 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4243 reserved_hpa_bits(),
4244 context->shadow_root_level, uses_nx,
4245 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4246 is_pse(vcpu), true);
4248 if (!shadow_me_mask)
4251 for (i = context->shadow_root_level; --i >= 0;) {
4252 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4253 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4257 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4259 static inline bool boot_cpu_is_amd(void)
4261 WARN_ON_ONCE(!tdp_enabled);
4262 return shadow_x_mask == 0;
4266 * the direct page table on host, use as much mmu features as
4267 * possible, however, kvm currently does not do execution-protection.
4270 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4271 struct kvm_mmu *context)
4273 struct rsvd_bits_validate *shadow_zero_check;
4276 shadow_zero_check = &context->shadow_zero_check;
4278 if (boot_cpu_is_amd())
4279 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4280 reserved_hpa_bits(),
4281 context->shadow_root_level, false,
4282 boot_cpu_has(X86_FEATURE_GBPAGES),
4285 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4286 reserved_hpa_bits(), false);
4288 if (!shadow_me_mask)
4291 for (i = context->shadow_root_level; --i >= 0;) {
4292 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4293 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4298 * as the comments in reset_shadow_zero_bits_mask() except it
4299 * is the shadow page table for intel nested guest.
4302 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4303 struct kvm_mmu *context, bool execonly)
4305 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4306 reserved_hpa_bits(), execonly);
4309 #define BYTE_MASK(access) \
4310 ((1 & (access) ? 2 : 0) | \
4311 (2 & (access) ? 4 : 0) | \
4312 (3 & (access) ? 8 : 0) | \
4313 (4 & (access) ? 16 : 0) | \
4314 (5 & (access) ? 32 : 0) | \
4315 (6 & (access) ? 64 : 0) | \
4316 (7 & (access) ? 128 : 0))
4319 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4320 struct kvm_mmu *mmu, bool ept)
4324 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4325 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4326 const u8 u = BYTE_MASK(ACC_USER_MASK);
4328 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4329 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4330 bool cr0_wp = is_write_protection(vcpu);
4332 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4333 unsigned pfec = byte << 1;
4336 * Each "*f" variable has a 1 bit for each UWX value
4337 * that causes a fault with the given PFEC.
4340 /* Faults from writes to non-writable pages */
4341 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4342 /* Faults from user mode accesses to supervisor pages */
4343 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4344 /* Faults from fetches of non-executable pages*/
4345 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4346 /* Faults from kernel mode fetches of user pages */
4348 /* Faults from kernel mode accesses of user pages */
4352 /* Faults from kernel mode accesses to user pages */
4353 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4355 /* Not really needed: !nx will cause pte.nx to fault */
4359 /* Allow supervisor writes if !cr0.wp */
4361 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4363 /* Disallow supervisor fetches of user code if cr4.smep */
4365 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4368 * SMAP:kernel-mode data accesses from user-mode
4369 * mappings should fault. A fault is considered
4370 * as a SMAP violation if all of the following
4371 * conditions are true:
4372 * - X86_CR4_SMAP is set in CR4
4373 * - A user page is accessed
4374 * - The access is not a fetch
4375 * - Page fault in kernel mode
4376 * - if CPL = 3 or X86_EFLAGS_AC is clear
4378 * Here, we cover the first three conditions.
4379 * The fourth is computed dynamically in permission_fault();
4380 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4381 * *not* subject to SMAP restrictions.
4384 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4387 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4392 * PKU is an additional mechanism by which the paging controls access to
4393 * user-mode addresses based on the value in the PKRU register. Protection
4394 * key violations are reported through a bit in the page fault error code.
4395 * Unlike other bits of the error code, the PK bit is not known at the
4396 * call site of e.g. gva_to_gpa; it must be computed directly in
4397 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4398 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4400 * In particular the following conditions come from the error code, the
4401 * page tables and the machine state:
4402 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4403 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4404 * - PK is always zero if U=0 in the page tables
4405 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4407 * The PKRU bitmask caches the result of these four conditions. The error
4408 * code (minus the P bit) and the page table's U bit form an index into the
4409 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4410 * with the two bits of the PKRU register corresponding to the protection key.
4411 * For the first three conditions above the bits will be 00, thus masking
4412 * away both AD and WD. For all reads or if the last condition holds, WD
4413 * only will be masked away.
4415 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4426 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4427 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4432 wp = is_write_protection(vcpu);
4434 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4435 unsigned pfec, pkey_bits;
4436 bool check_pkey, check_write, ff, uf, wf, pte_user;
4439 ff = pfec & PFERR_FETCH_MASK;
4440 uf = pfec & PFERR_USER_MASK;
4441 wf = pfec & PFERR_WRITE_MASK;
4443 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4444 pte_user = pfec & PFERR_RSVD_MASK;
4447 * Only need to check the access which is not an
4448 * instruction fetch and is to a user page.
4450 check_pkey = (!ff && pte_user);
4452 * write access is controlled by PKRU if it is a
4453 * user access or CR0.WP = 1.
4455 check_write = check_pkey && wf && (uf || wp);
4457 /* PKRU.AD stops both read and write access. */
4458 pkey_bits = !!check_pkey;
4459 /* PKRU.WD stops write access. */
4460 pkey_bits |= (!!check_write) << 1;
4462 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4466 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4468 unsigned root_level = mmu->root_level;
4470 mmu->last_nonleaf_level = root_level;
4471 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4472 mmu->last_nonleaf_level++;
4475 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4476 struct kvm_mmu *context,
4479 context->nx = is_nx(vcpu);
4480 context->root_level = level;
4482 reset_rsvds_bits_mask(vcpu, context);
4483 update_permission_bitmask(vcpu, context, false);
4484 update_pkru_bitmask(vcpu, context, false);
4485 update_last_nonleaf_level(vcpu, context);
4487 MMU_WARN_ON(!is_pae(vcpu));
4488 context->page_fault = paging64_page_fault;
4489 context->gva_to_gpa = paging64_gva_to_gpa;
4490 context->sync_page = paging64_sync_page;
4491 context->invlpg = paging64_invlpg;
4492 context->shadow_root_level = level;
4493 context->direct_map = false;
4496 static void paging64_init_context(struct kvm_vcpu *vcpu,
4497 struct kvm_mmu *context)
4499 int root_level = is_la57_mode(vcpu) ?
4500 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4502 paging64_init_context_common(vcpu, context, root_level);
4505 static void paging32_init_context(struct kvm_vcpu *vcpu,
4506 struct kvm_mmu *context)
4508 context->nx = false;
4509 context->root_level = PT32_ROOT_LEVEL;
4511 reset_rsvds_bits_mask(vcpu, context);
4512 update_permission_bitmask(vcpu, context, false);
4513 update_pkru_bitmask(vcpu, context, false);
4514 update_last_nonleaf_level(vcpu, context);
4516 context->page_fault = paging32_page_fault;
4517 context->gva_to_gpa = paging32_gva_to_gpa;
4518 context->sync_page = paging32_sync_page;
4519 context->invlpg = paging32_invlpg;
4520 context->shadow_root_level = PT32E_ROOT_LEVEL;
4521 context->direct_map = false;
4524 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4525 struct kvm_mmu *context)
4527 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4530 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4532 union kvm_mmu_extended_role ext = {0};
4534 ext.cr0_pg = !!is_paging(vcpu);
4535 ext.cr4_pae = !!is_pae(vcpu);
4536 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4537 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4538 ext.cr4_pse = !!is_pse(vcpu);
4539 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4540 ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
4547 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4550 union kvm_mmu_role role = {0};
4552 role.base.access = ACC_ALL;
4553 role.base.nxe = !!is_nx(vcpu);
4554 role.base.cr0_wp = is_write_protection(vcpu);
4555 role.base.smm = is_smm(vcpu);
4556 role.base.guest_mode = is_guest_mode(vcpu);
4561 role.ext = kvm_calc_mmu_role_ext(vcpu);
4566 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4568 /* Use 5-level TDP if and only if it's useful/necessary. */
4569 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4572 return max_tdp_level;
4575 static union kvm_mmu_role
4576 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4578 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4580 role.base.ad_disabled = (shadow_accessed_mask == 0);
4581 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4582 role.base.direct = true;
4583 role.base.gpte_is_8_bytes = true;
4588 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4590 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4591 union kvm_mmu_role new_role =
4592 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
4594 if (new_role.as_u64 == context->mmu_role.as_u64)
4597 context->mmu_role.as_u64 = new_role.as_u64;
4598 context->page_fault = kvm_tdp_page_fault;
4599 context->sync_page = nonpaging_sync_page;
4600 context->invlpg = NULL;
4601 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4602 context->direct_map = true;
4603 context->get_guest_pgd = get_cr3;
4604 context->get_pdptr = kvm_pdptr_read;
4605 context->inject_page_fault = kvm_inject_page_fault;
4607 if (!is_paging(vcpu)) {
4608 context->nx = false;
4609 context->gva_to_gpa = nonpaging_gva_to_gpa;
4610 context->root_level = 0;
4611 } else if (is_long_mode(vcpu)) {
4612 context->nx = is_nx(vcpu);
4613 context->root_level = is_la57_mode(vcpu) ?
4614 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4615 reset_rsvds_bits_mask(vcpu, context);
4616 context->gva_to_gpa = paging64_gva_to_gpa;
4617 } else if (is_pae(vcpu)) {
4618 context->nx = is_nx(vcpu);
4619 context->root_level = PT32E_ROOT_LEVEL;
4620 reset_rsvds_bits_mask(vcpu, context);
4621 context->gva_to_gpa = paging64_gva_to_gpa;
4623 context->nx = false;
4624 context->root_level = PT32_ROOT_LEVEL;
4625 reset_rsvds_bits_mask(vcpu, context);
4626 context->gva_to_gpa = paging32_gva_to_gpa;
4629 update_permission_bitmask(vcpu, context, false);
4630 update_pkru_bitmask(vcpu, context, false);
4631 update_last_nonleaf_level(vcpu, context);
4632 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4635 static union kvm_mmu_role
4636 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, bool base_only)
4638 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4640 role.base.smep_andnot_wp = role.ext.cr4_smep &&
4641 !is_write_protection(vcpu);
4642 role.base.smap_andnot_wp = role.ext.cr4_smap &&
4643 !is_write_protection(vcpu);
4644 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
4649 static union kvm_mmu_role
4650 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4652 union kvm_mmu_role role =
4653 kvm_calc_shadow_root_page_role_common(vcpu, base_only);
4655 role.base.direct = !is_paging(vcpu);
4657 if (!is_long_mode(vcpu))
4658 role.base.level = PT32E_ROOT_LEVEL;
4659 else if (is_la57_mode(vcpu))
4660 role.base.level = PT64_ROOT_5LEVEL;
4662 role.base.level = PT64_ROOT_4LEVEL;
4667 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4668 u32 cr0, u32 cr4, u32 efer,
4669 union kvm_mmu_role new_role)
4671 if (!(cr0 & X86_CR0_PG))
4672 nonpaging_init_context(vcpu, context);
4673 else if (efer & EFER_LMA)
4674 paging64_init_context(vcpu, context);
4675 else if (cr4 & X86_CR4_PAE)
4676 paging32E_init_context(vcpu, context);
4678 paging32_init_context(vcpu, context);
4680 context->mmu_role.as_u64 = new_role.as_u64;
4681 reset_shadow_zero_bits_mask(vcpu, context);
4684 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer)
4686 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4687 union kvm_mmu_role new_role =
4688 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4690 if (new_role.as_u64 != context->mmu_role.as_u64)
4691 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4694 static union kvm_mmu_role
4695 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu)
4697 union kvm_mmu_role role =
4698 kvm_calc_shadow_root_page_role_common(vcpu, false);
4700 role.base.direct = false;
4701 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4706 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer,
4709 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4710 union kvm_mmu_role new_role = kvm_calc_shadow_npt_root_page_role(vcpu);
4712 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base);
4714 if (new_role.as_u64 != context->mmu_role.as_u64) {
4715 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4718 * Override the level set by the common init helper, nested TDP
4719 * always uses the host's TDP configuration.
4721 context->shadow_root_level = new_role.base.level;
4724 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4726 static union kvm_mmu_role
4727 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4728 bool execonly, u8 level)
4730 union kvm_mmu_role role = {0};
4732 /* SMM flag is inherited from root_mmu */
4733 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4735 role.base.level = level;
4736 role.base.gpte_is_8_bytes = true;
4737 role.base.direct = false;
4738 role.base.ad_disabled = !accessed_dirty;
4739 role.base.guest_mode = true;
4740 role.base.access = ACC_ALL;
4743 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
4744 * SMAP variation to denote shadow EPT entries.
4746 role.base.cr0_wp = true;
4747 role.base.smap_andnot_wp = true;
4749 role.ext = kvm_calc_mmu_role_ext(vcpu);
4750 role.ext.execonly = execonly;
4755 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4756 bool accessed_dirty, gpa_t new_eptp)
4758 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4759 u8 level = vmx_eptp_page_walk_level(new_eptp);
4760 union kvm_mmu_role new_role =
4761 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4764 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base);
4766 if (new_role.as_u64 == context->mmu_role.as_u64)
4769 context->shadow_root_level = level;
4772 context->ept_ad = accessed_dirty;
4773 context->page_fault = ept_page_fault;
4774 context->gva_to_gpa = ept_gva_to_gpa;
4775 context->sync_page = ept_sync_page;
4776 context->invlpg = ept_invlpg;
4777 context->root_level = level;
4778 context->direct_map = false;
4779 context->mmu_role.as_u64 = new_role.as_u64;
4781 update_permission_bitmask(vcpu, context, true);
4782 update_pkru_bitmask(vcpu, context, true);
4783 update_last_nonleaf_level(vcpu, context);
4784 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4785 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4787 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4789 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4791 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4793 kvm_init_shadow_mmu(vcpu,
4794 kvm_read_cr0_bits(vcpu, X86_CR0_PG),
4795 kvm_read_cr4_bits(vcpu, X86_CR4_PAE),
4798 context->get_guest_pgd = get_cr3;
4799 context->get_pdptr = kvm_pdptr_read;
4800 context->inject_page_fault = kvm_inject_page_fault;
4803 static union kvm_mmu_role kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu)
4805 union kvm_mmu_role role = kvm_calc_shadow_root_page_role_common(vcpu, false);
4808 * Nested MMUs are used only for walking L2's gva->gpa, they never have
4809 * shadow pages of their own and so "direct" has no meaning. Set it
4810 * to "true" to try to detect bogus usage of the nested MMU.
4812 role.base.direct = true;
4814 if (!is_paging(vcpu))
4815 role.base.level = 0;
4816 else if (is_long_mode(vcpu))
4817 role.base.level = is_la57_mode(vcpu) ? PT64_ROOT_5LEVEL :
4819 else if (is_pae(vcpu))
4820 role.base.level = PT32E_ROOT_LEVEL;
4822 role.base.level = PT32_ROOT_LEVEL;
4827 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4829 union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu);
4830 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4832 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4835 g_context->mmu_role.as_u64 = new_role.as_u64;
4836 g_context->get_guest_pgd = get_cr3;
4837 g_context->get_pdptr = kvm_pdptr_read;
4838 g_context->inject_page_fault = kvm_inject_page_fault;
4841 * L2 page tables are never shadowed, so there is no need to sync
4844 g_context->invlpg = NULL;
4847 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4848 * L1's nested page tables (e.g. EPT12). The nested translation
4849 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4850 * L2's page tables as the first level of translation and L1's
4851 * nested page tables as the second level of translation. Basically
4852 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4854 if (!is_paging(vcpu)) {
4855 g_context->nx = false;
4856 g_context->root_level = 0;
4857 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4858 } else if (is_long_mode(vcpu)) {
4859 g_context->nx = is_nx(vcpu);
4860 g_context->root_level = is_la57_mode(vcpu) ?
4861 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4862 reset_rsvds_bits_mask(vcpu, g_context);
4863 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4864 } else if (is_pae(vcpu)) {
4865 g_context->nx = is_nx(vcpu);
4866 g_context->root_level = PT32E_ROOT_LEVEL;
4867 reset_rsvds_bits_mask(vcpu, g_context);
4868 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4870 g_context->nx = false;
4871 g_context->root_level = PT32_ROOT_LEVEL;
4872 reset_rsvds_bits_mask(vcpu, g_context);
4873 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4876 update_permission_bitmask(vcpu, g_context, false);
4877 update_pkru_bitmask(vcpu, g_context, false);
4878 update_last_nonleaf_level(vcpu, g_context);
4881 void kvm_init_mmu(struct kvm_vcpu *vcpu)
4883 if (mmu_is_nested(vcpu))
4884 init_kvm_nested_mmu(vcpu);
4885 else if (tdp_enabled)
4886 init_kvm_tdp_mmu(vcpu);
4888 init_kvm_softmmu(vcpu);
4890 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4892 static union kvm_mmu_page_role
4893 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4895 union kvm_mmu_role role;
4898 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
4900 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
4905 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4907 kvm_mmu_unload(vcpu);
4910 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4912 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4916 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
4919 r = mmu_alloc_special_roots(vcpu);
4922 if (vcpu->arch.mmu->direct_map)
4923 r = mmu_alloc_direct_roots(vcpu);
4925 r = mmu_alloc_shadow_roots(vcpu);
4929 kvm_mmu_sync_roots(vcpu);
4931 kvm_mmu_load_pgd(vcpu);
4932 static_call(kvm_x86_tlb_flush_current)(vcpu);
4937 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4939 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
4940 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
4941 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4942 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
4945 static bool need_remote_flush(u64 old, u64 new)
4947 if (!is_shadow_present_pte(old))
4949 if (!is_shadow_present_pte(new))
4951 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4953 old ^= shadow_nx_mask;
4954 new ^= shadow_nx_mask;
4955 return (old & ~new & PT64_PERM_MASK) != 0;
4958 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4965 * Assume that the pte write on a page table of the same type
4966 * as the current vcpu paging mode since we update the sptes only
4967 * when they have the same mode.
4969 if (is_pae(vcpu) && *bytes == 4) {
4970 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4975 if (*bytes == 4 || *bytes == 8) {
4976 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
4985 * If we're seeing too many writes to a page, it may no longer be a page table,
4986 * or we may be forking, in which case it is better to unmap the page.
4988 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4991 * Skip write-flooding detected for the sp whose level is 1, because
4992 * it can become unsync, then the guest page is not write-protected.
4994 if (sp->role.level == PG_LEVEL_4K)
4997 atomic_inc(&sp->write_flooding_count);
4998 return atomic_read(&sp->write_flooding_count) >= 3;
5002 * Misaligned accesses are too much trouble to fix up; also, they usually
5003 * indicate a page is not used as a page table.
5005 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5008 unsigned offset, pte_size, misaligned;
5010 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5011 gpa, bytes, sp->role.word);
5013 offset = offset_in_page(gpa);
5014 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5017 * Sometimes, the OS only writes the last one bytes to update status
5018 * bits, for example, in linux, andb instruction is used in clear_bit().
5020 if (!(offset & (pte_size - 1)) && bytes == 1)
5023 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5024 misaligned |= bytes < 4;
5029 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5031 unsigned page_offset, quadrant;
5035 page_offset = offset_in_page(gpa);
5036 level = sp->role.level;
5038 if (!sp->role.gpte_is_8_bytes) {
5039 page_offset <<= 1; /* 32->64 */
5041 * A 32-bit pde maps 4MB while the shadow pdes map
5042 * only 2MB. So we need to double the offset again
5043 * and zap two pdes instead of one.
5045 if (level == PT32_ROOT_LEVEL) {
5046 page_offset &= ~7; /* kill rounding error */
5050 quadrant = page_offset >> PAGE_SHIFT;
5051 page_offset &= ~PAGE_MASK;
5052 if (quadrant != sp->role.quadrant)
5056 spte = &sp->spt[page_offset / sizeof(*spte)];
5060 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5061 const u8 *new, int bytes,
5062 struct kvm_page_track_notifier_node *node)
5064 gfn_t gfn = gpa >> PAGE_SHIFT;
5065 struct kvm_mmu_page *sp;
5066 LIST_HEAD(invalid_list);
5067 u64 entry, gentry, *spte;
5069 bool remote_flush, local_flush;
5072 * If we don't have indirect shadow pages, it means no page is
5073 * write-protected, so we can exit simply.
5075 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5078 remote_flush = local_flush = false;
5080 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5083 * No need to care whether allocation memory is successful
5084 * or not since pte prefetch is skipped if it does not have
5085 * enough objects in the cache.
5087 mmu_topup_memory_caches(vcpu, true);
5089 write_lock(&vcpu->kvm->mmu_lock);
5091 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5093 ++vcpu->kvm->stat.mmu_pte_write;
5094 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5096 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5097 if (detect_write_misaligned(sp, gpa, bytes) ||
5098 detect_write_flooding(sp)) {
5099 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5100 ++vcpu->kvm->stat.mmu_flooded;
5104 spte = get_written_sptes(sp, gpa, &npte);
5111 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
5112 if (gentry && sp->role.level != PG_LEVEL_4K)
5113 ++vcpu->kvm->stat.mmu_pde_zapped;
5114 if (need_remote_flush(entry, *spte))
5115 remote_flush = true;
5119 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5120 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5121 write_unlock(&vcpu->kvm->mmu_lock);
5124 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5125 void *insn, int insn_len)
5127 int r, emulation_type = EMULTYPE_PF;
5128 bool direct = vcpu->arch.mmu->direct_map;
5130 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5131 return RET_PF_RETRY;
5134 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5135 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5136 if (r == RET_PF_EMULATE)
5140 if (r == RET_PF_INVALID) {
5141 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5142 lower_32_bits(error_code), false);
5143 if (WARN_ON_ONCE(r == RET_PF_INVALID))
5149 if (r != RET_PF_EMULATE)
5153 * Before emulating the instruction, check if the error code
5154 * was due to a RO violation while translating the guest page.
5155 * This can occur when using nested virtualization with nested
5156 * paging in both guests. If true, we simply unprotect the page
5157 * and resume the guest.
5159 if (vcpu->arch.mmu->direct_map &&
5160 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5161 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5166 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5167 * optimistically try to just unprotect the page and let the processor
5168 * re-execute the instruction that caused the page fault. Do not allow
5169 * retrying MMIO emulation, as it's not only pointless but could also
5170 * cause us to enter an infinite loop because the processor will keep
5171 * faulting on the non-existent MMIO address. Retrying an instruction
5172 * from a nested guest is also pointless and dangerous as we are only
5173 * explicitly shadowing L1's page tables, i.e. unprotecting something
5174 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5176 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5177 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5179 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5182 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5184 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5185 gva_t gva, hpa_t root_hpa)
5189 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5190 if (mmu != &vcpu->arch.guest_mmu) {
5191 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5192 if (is_noncanonical_address(gva, vcpu))
5195 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5201 if (root_hpa == INVALID_PAGE) {
5202 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5205 * INVLPG is required to invalidate any global mappings for the VA,
5206 * irrespective of PCID. Since it would take us roughly similar amount
5207 * of work to determine whether any of the prev_root mappings of the VA
5208 * is marked global, or to just sync it blindly, so we might as well
5209 * just always sync it.
5211 * Mappings not reachable via the current cr3 or the prev_roots will be
5212 * synced when switching to that cr3, so nothing needs to be done here
5215 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5216 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5217 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5219 mmu->invlpg(vcpu, gva, root_hpa);
5223 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5225 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
5226 ++vcpu->stat.invlpg;
5228 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5231 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5233 struct kvm_mmu *mmu = vcpu->arch.mmu;
5234 bool tlb_flush = false;
5237 if (pcid == kvm_get_active_pcid(vcpu)) {
5238 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5242 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5243 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5244 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5245 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5251 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5253 ++vcpu->stat.invlpg;
5256 * Mappings not reachable via the current cr3 or the prev_roots will be
5257 * synced when switching to that cr3, so nothing needs to be done here
5262 void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
5263 int tdp_huge_page_level)
5265 tdp_enabled = enable_tdp;
5266 max_tdp_level = tdp_max_root_level;
5269 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5270 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5271 * the kernel is not. But, KVM never creates a page size greater than
5272 * what is used by the kernel for any given HVA, i.e. the kernel's
5273 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5276 max_huge_page_level = tdp_huge_page_level;
5277 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5278 max_huge_page_level = PG_LEVEL_1G;
5280 max_huge_page_level = PG_LEVEL_2M;
5282 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5284 /* The return value indicates if tlb flush on all vcpus is needed. */
5285 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head,
5286 struct kvm_memory_slot *slot);
5288 /* The caller should hold mmu-lock before calling this function. */
5289 static __always_inline bool
5290 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5291 slot_level_handler fn, int start_level, int end_level,
5292 gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield,
5295 struct slot_rmap_walk_iterator iterator;
5297 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5298 end_gfn, &iterator) {
5300 flush |= fn(kvm, iterator.rmap, memslot);
5302 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
5303 if (flush && flush_on_yield) {
5304 kvm_flush_remote_tlbs_with_address(kvm,
5306 iterator.gfn - start_gfn + 1);
5309 cond_resched_rwlock_write(&kvm->mmu_lock);
5316 static __always_inline bool
5317 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5318 slot_level_handler fn, int start_level, int end_level,
5319 bool flush_on_yield)
5321 return slot_handle_level_range(kvm, memslot, fn, start_level,
5322 end_level, memslot->base_gfn,
5323 memslot->base_gfn + memslot->npages - 1,
5324 flush_on_yield, false);
5327 static __always_inline bool
5328 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5329 slot_level_handler fn, bool flush_on_yield)
5331 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5332 PG_LEVEL_4K, flush_on_yield);
5335 static void free_mmu_pages(struct kvm_mmu *mmu)
5337 if (!tdp_enabled && mmu->pae_root)
5338 set_memory_encrypted((unsigned long)mmu->pae_root, 1);
5339 free_page((unsigned long)mmu->pae_root);
5340 free_page((unsigned long)mmu->pml4_root);
5343 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5348 mmu->root_hpa = INVALID_PAGE;
5350 mmu->translate_gpa = translate_gpa;
5351 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5352 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5355 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5356 * while the PDP table is a per-vCPU construct that's allocated at MMU
5357 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5358 * x86_64. Therefore we need to allocate the PDP table in the first
5359 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5360 * generally doesn't use PAE paging and can skip allocating the PDP
5361 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5362 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5363 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
5365 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5368 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5372 mmu->pae_root = page_address(page);
5375 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5376 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5377 * that KVM's writes and the CPU's reads get along. Note, this is
5378 * only necessary when using shadow paging, as 64-bit NPT can get at
5379 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5380 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5383 set_memory_decrypted((unsigned long)mmu->pae_root, 1);
5385 WARN_ON_ONCE(shadow_me_mask);
5387 for (i = 0; i < 4; ++i)
5388 mmu->pae_root[i] = INVALID_PAE_ROOT;
5393 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5397 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5398 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5400 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5401 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5403 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5405 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5406 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5408 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5410 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5414 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5416 goto fail_allocate_root;
5420 free_mmu_pages(&vcpu->arch.guest_mmu);
5424 #define BATCH_ZAP_PAGES 10
5425 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5427 struct kvm_mmu_page *sp, *node;
5428 int nr_zapped, batch = 0;
5431 list_for_each_entry_safe_reverse(sp, node,
5432 &kvm->arch.active_mmu_pages, link) {
5434 * No obsolete valid page exists before a newly created page
5435 * since active_mmu_pages is a FIFO list.
5437 if (!is_obsolete_sp(kvm, sp))
5441 * Invalid pages should never land back on the list of active
5442 * pages. Skip the bogus page, otherwise we'll get stuck in an
5443 * infinite loop if the page gets put back on the list (again).
5445 if (WARN_ON(sp->role.invalid))
5449 * No need to flush the TLB since we're only zapping shadow
5450 * pages with an obsolete generation number and all vCPUS have
5451 * loaded a new root, i.e. the shadow pages being zapped cannot
5452 * be in active use by the guest.
5454 if (batch >= BATCH_ZAP_PAGES &&
5455 cond_resched_rwlock_write(&kvm->mmu_lock)) {
5460 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5461 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5468 * Trigger a remote TLB flush before freeing the page tables to ensure
5469 * KVM is not in the middle of a lockless shadow page table walk, which
5470 * may reference the pages.
5472 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5476 * Fast invalidate all shadow pages and use lock-break technique
5477 * to zap obsolete pages.
5479 * It's required when memslot is being deleted or VM is being
5480 * destroyed, in these cases, we should ensure that KVM MMU does
5481 * not use any resource of the being-deleted slot or all slots
5482 * after calling the function.
5484 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5486 lockdep_assert_held(&kvm->slots_lock);
5488 write_lock(&kvm->mmu_lock);
5489 trace_kvm_mmu_zap_all_fast(kvm);
5492 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5493 * held for the entire duration of zapping obsolete pages, it's
5494 * impossible for there to be multiple invalid generations associated
5495 * with *valid* shadow pages at any given time, i.e. there is exactly
5496 * one valid generation and (at most) one invalid generation.
5498 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5500 /* In order to ensure all threads see this change when
5501 * handling the MMU reload signal, this must happen in the
5502 * same critical section as kvm_reload_remote_mmus, and
5503 * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages
5504 * could drop the MMU lock and yield.
5506 if (is_tdp_mmu_enabled(kvm))
5507 kvm_tdp_mmu_invalidate_all_roots(kvm);
5510 * Notify all vcpus to reload its shadow page table and flush TLB.
5511 * Then all vcpus will switch to new shadow page table with the new
5514 * Note: we need to do this under the protection of mmu_lock,
5515 * otherwise, vcpu would purge shadow page but miss tlb flush.
5517 kvm_reload_remote_mmus(kvm);
5519 kvm_zap_obsolete_pages(kvm);
5521 write_unlock(&kvm->mmu_lock);
5523 if (is_tdp_mmu_enabled(kvm)) {
5524 read_lock(&kvm->mmu_lock);
5525 kvm_tdp_mmu_zap_invalidated_roots(kvm);
5526 read_unlock(&kvm->mmu_lock);
5530 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5532 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5535 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5536 struct kvm_memory_slot *slot,
5537 struct kvm_page_track_notifier_node *node)
5539 kvm_mmu_zap_all_fast(kvm);
5542 void kvm_mmu_init_vm(struct kvm *kvm)
5544 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5546 if (!kvm_mmu_init_tdp_mmu(kvm))
5548 * No smp_load/store wrappers needed here as we are in
5549 * VM init and there cannot be any memslots / other threads
5550 * accessing this struct kvm yet.
5552 kvm->arch.memslots_have_rmaps = true;
5554 node->track_write = kvm_mmu_pte_write;
5555 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5556 kvm_page_track_register_notifier(kvm, node);
5559 void kvm_mmu_uninit_vm(struct kvm *kvm)
5561 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5563 kvm_page_track_unregister_notifier(kvm, node);
5565 kvm_mmu_uninit_tdp_mmu(kvm);
5568 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5570 struct kvm_memslots *slots;
5571 struct kvm_memory_slot *memslot;
5575 if (kvm_memslots_have_rmaps(kvm)) {
5576 write_lock(&kvm->mmu_lock);
5577 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5578 slots = __kvm_memslots(kvm, i);
5579 kvm_for_each_memslot(memslot, slots) {
5582 start = max(gfn_start, memslot->base_gfn);
5583 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5587 flush = slot_handle_level_range(kvm, memslot,
5588 kvm_zap_rmapp, PG_LEVEL_4K,
5589 KVM_MAX_HUGEPAGE_LEVEL, start,
5590 end - 1, true, flush);
5594 kvm_flush_remote_tlbs_with_address(kvm, gfn_start, gfn_end);
5595 write_unlock(&kvm->mmu_lock);
5598 if (is_tdp_mmu_enabled(kvm)) {
5601 read_lock(&kvm->mmu_lock);
5602 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++)
5603 flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start,
5604 gfn_end, flush, true);
5606 kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
5609 read_unlock(&kvm->mmu_lock);
5613 static bool slot_rmap_write_protect(struct kvm *kvm,
5614 struct kvm_rmap_head *rmap_head,
5615 struct kvm_memory_slot *slot)
5617 return __rmap_write_protect(kvm, rmap_head, false);
5620 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5621 struct kvm_memory_slot *memslot,
5626 if (kvm_memslots_have_rmaps(kvm)) {
5627 write_lock(&kvm->mmu_lock);
5628 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5629 start_level, KVM_MAX_HUGEPAGE_LEVEL,
5631 write_unlock(&kvm->mmu_lock);
5634 if (is_tdp_mmu_enabled(kvm)) {
5635 read_lock(&kvm->mmu_lock);
5636 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level);
5637 read_unlock(&kvm->mmu_lock);
5641 * We can flush all the TLBs out of the mmu lock without TLB
5642 * corruption since we just change the spte from writable to
5643 * readonly so that we only need to care the case of changing
5644 * spte from present to present (changing the spte from present
5645 * to nonpresent will flush all the TLBs immediately), in other
5646 * words, the only case we care is mmu_spte_update() where we
5647 * have checked Host-writable | MMU-writable instead of
5648 * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK
5652 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5655 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5656 struct kvm_rmap_head *rmap_head,
5657 struct kvm_memory_slot *slot)
5660 struct rmap_iterator iter;
5661 int need_tlb_flush = 0;
5663 struct kvm_mmu_page *sp;
5666 for_each_rmap_spte(rmap_head, &iter, sptep) {
5667 sp = sptep_to_sp(sptep);
5668 pfn = spte_to_pfn(*sptep);
5671 * We cannot do huge page mapping for indirect shadow pages,
5672 * which are found on the last rmap (level = 1) when not using
5673 * tdp; such shadow pages are synced with the page table in
5674 * the guest, and the guest page table is using 4K page size
5675 * mapping if the indirect sp has level = 1.
5677 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5678 sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn,
5679 pfn, PG_LEVEL_NUM)) {
5680 pte_list_remove(rmap_head, sptep);
5682 if (kvm_available_flush_tlb_with_range())
5683 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5684 KVM_PAGES_PER_HPAGE(sp->role.level));
5692 return need_tlb_flush;
5695 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5696 const struct kvm_memory_slot *memslot)
5698 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5699 struct kvm_memory_slot *slot = (struct kvm_memory_slot *)memslot;
5702 if (kvm_memslots_have_rmaps(kvm)) {
5703 write_lock(&kvm->mmu_lock);
5704 flush = slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true);
5706 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5707 write_unlock(&kvm->mmu_lock);
5710 if (is_tdp_mmu_enabled(kvm)) {
5711 read_lock(&kvm->mmu_lock);
5712 flush = kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot, flush);
5714 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5715 read_unlock(&kvm->mmu_lock);
5719 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5720 const struct kvm_memory_slot *memslot)
5723 * All current use cases for flushing the TLBs for a specific memslot
5724 * related to dirty logging, and many do the TLB flush out of mmu_lock.
5725 * The interaction between the various operations on memslot must be
5726 * serialized by slots_locks to ensure the TLB flush from one operation
5727 * is observed by any other operation on the same memslot.
5729 lockdep_assert_held(&kvm->slots_lock);
5730 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5734 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5735 struct kvm_memory_slot *memslot)
5739 if (kvm_memslots_have_rmaps(kvm)) {
5740 write_lock(&kvm->mmu_lock);
5741 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty,
5743 write_unlock(&kvm->mmu_lock);
5746 if (is_tdp_mmu_enabled(kvm)) {
5747 read_lock(&kvm->mmu_lock);
5748 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5749 read_unlock(&kvm->mmu_lock);
5753 * It's also safe to flush TLBs out of mmu lock here as currently this
5754 * function is only used for dirty logging, in which case flushing TLB
5755 * out of mmu lock also guarantees no dirty pages will be lost in
5759 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5762 void kvm_mmu_zap_all(struct kvm *kvm)
5764 struct kvm_mmu_page *sp, *node;
5765 LIST_HEAD(invalid_list);
5768 write_lock(&kvm->mmu_lock);
5770 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5771 if (WARN_ON(sp->role.invalid))
5773 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5775 if (cond_resched_rwlock_write(&kvm->mmu_lock))
5779 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5781 if (is_tdp_mmu_enabled(kvm))
5782 kvm_tdp_mmu_zap_all(kvm);
5784 write_unlock(&kvm->mmu_lock);
5787 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5789 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5791 gen &= MMIO_SPTE_GEN_MASK;
5794 * Generation numbers are incremented in multiples of the number of
5795 * address spaces in order to provide unique generations across all
5796 * address spaces. Strip what is effectively the address space
5797 * modifier prior to checking for a wrap of the MMIO generation so
5798 * that a wrap in any address space is detected.
5800 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5803 * The very rare case: if the MMIO generation number has wrapped,
5804 * zap all shadow pages.
5806 if (unlikely(gen == 0)) {
5807 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5808 kvm_mmu_zap_all_fast(kvm);
5812 static unsigned long
5813 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5816 int nr_to_scan = sc->nr_to_scan;
5817 unsigned long freed = 0;
5819 mutex_lock(&kvm_lock);
5821 list_for_each_entry(kvm, &vm_list, vm_list) {
5823 LIST_HEAD(invalid_list);
5826 * Never scan more than sc->nr_to_scan VM instances.
5827 * Will not hit this condition practically since we do not try
5828 * to shrink more than one VM and it is very unlikely to see
5829 * !n_used_mmu_pages so many times.
5834 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5835 * here. We may skip a VM instance errorneosly, but we do not
5836 * want to shrink a VM that only started to populate its MMU
5839 if (!kvm->arch.n_used_mmu_pages &&
5840 !kvm_has_zapped_obsolete_pages(kvm))
5843 idx = srcu_read_lock(&kvm->srcu);
5844 write_lock(&kvm->mmu_lock);
5846 if (kvm_has_zapped_obsolete_pages(kvm)) {
5847 kvm_mmu_commit_zap_page(kvm,
5848 &kvm->arch.zapped_obsolete_pages);
5852 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
5855 write_unlock(&kvm->mmu_lock);
5856 srcu_read_unlock(&kvm->srcu, idx);
5859 * unfair on small ones
5860 * per-vm shrinkers cry out
5861 * sadness comes quickly
5863 list_move_tail(&kvm->vm_list, &vm_list);
5867 mutex_unlock(&kvm_lock);
5871 static unsigned long
5872 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5874 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5877 static struct shrinker mmu_shrinker = {
5878 .count_objects = mmu_shrink_count,
5879 .scan_objects = mmu_shrink_scan,
5880 .seeks = DEFAULT_SEEKS * 10,
5883 static void mmu_destroy_caches(void)
5885 kmem_cache_destroy(pte_list_desc_cache);
5886 kmem_cache_destroy(mmu_page_header_cache);
5889 static bool get_nx_auto_mode(void)
5891 /* Return true when CPU has the bug, and mitigations are ON */
5892 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5895 static void __set_nx_huge_pages(bool val)
5897 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5900 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5902 bool old_val = nx_huge_pages;
5905 /* In "auto" mode deploy workaround only if CPU has the bug. */
5906 if (sysfs_streq(val, "off"))
5908 else if (sysfs_streq(val, "force"))
5910 else if (sysfs_streq(val, "auto"))
5911 new_val = get_nx_auto_mode();
5912 else if (strtobool(val, &new_val) < 0)
5915 __set_nx_huge_pages(new_val);
5917 if (new_val != old_val) {
5920 mutex_lock(&kvm_lock);
5922 list_for_each_entry(kvm, &vm_list, vm_list) {
5923 mutex_lock(&kvm->slots_lock);
5924 kvm_mmu_zap_all_fast(kvm);
5925 mutex_unlock(&kvm->slots_lock);
5927 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5929 mutex_unlock(&kvm_lock);
5935 int kvm_mmu_module_init(void)
5939 if (nx_huge_pages == -1)
5940 __set_nx_huge_pages(get_nx_auto_mode());
5943 * MMU roles use union aliasing which is, generally speaking, an
5944 * undefined behavior. However, we supposedly know how compilers behave
5945 * and the current status quo is unlikely to change. Guardians below are
5946 * supposed to let us know if the assumption becomes false.
5948 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
5949 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
5950 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
5952 kvm_mmu_reset_all_pte_masks();
5954 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5955 sizeof(struct pte_list_desc),
5956 0, SLAB_ACCOUNT, NULL);
5957 if (!pte_list_desc_cache)
5960 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5961 sizeof(struct kvm_mmu_page),
5962 0, SLAB_ACCOUNT, NULL);
5963 if (!mmu_page_header_cache)
5966 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5969 ret = register_shrinker(&mmu_shrinker);
5976 mmu_destroy_caches();
5981 * Calculate mmu pages needed for kvm.
5983 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
5985 unsigned long nr_mmu_pages;
5986 unsigned long nr_pages = 0;
5987 struct kvm_memslots *slots;
5988 struct kvm_memory_slot *memslot;
5991 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5992 slots = __kvm_memslots(kvm, i);
5994 kvm_for_each_memslot(memslot, slots)
5995 nr_pages += memslot->npages;
5998 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5999 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
6001 return nr_mmu_pages;
6004 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6006 kvm_mmu_unload(vcpu);
6007 free_mmu_pages(&vcpu->arch.root_mmu);
6008 free_mmu_pages(&vcpu->arch.guest_mmu);
6009 mmu_free_memory_caches(vcpu);
6012 void kvm_mmu_module_exit(void)
6014 mmu_destroy_caches();
6015 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6016 unregister_shrinker(&mmu_shrinker);
6017 mmu_audit_disable();
6020 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
6022 unsigned int old_val;
6025 old_val = nx_huge_pages_recovery_ratio;
6026 err = param_set_uint(val, kp);
6030 if (READ_ONCE(nx_huge_pages) &&
6031 !old_val && nx_huge_pages_recovery_ratio) {
6034 mutex_lock(&kvm_lock);
6036 list_for_each_entry(kvm, &vm_list, vm_list)
6037 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6039 mutex_unlock(&kvm_lock);
6045 static void kvm_recover_nx_lpages(struct kvm *kvm)
6047 unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits;
6049 struct kvm_mmu_page *sp;
6051 LIST_HEAD(invalid_list);
6055 rcu_idx = srcu_read_lock(&kvm->srcu);
6056 write_lock(&kvm->mmu_lock);
6058 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6059 to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0;
6060 for ( ; to_zap; --to_zap) {
6061 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
6065 * We use a separate list instead of just using active_mmu_pages
6066 * because the number of lpage_disallowed pages is expected to
6067 * be relatively small compared to the total.
6069 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6070 struct kvm_mmu_page,
6071 lpage_disallowed_link);
6072 WARN_ON_ONCE(!sp->lpage_disallowed);
6073 if (is_tdp_mmu_page(sp)) {
6074 flush |= kvm_tdp_mmu_zap_sp(kvm, sp);
6076 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6077 WARN_ON_ONCE(sp->lpage_disallowed);
6080 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
6081 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6082 cond_resched_rwlock_write(&kvm->mmu_lock);
6086 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6088 write_unlock(&kvm->mmu_lock);
6089 srcu_read_unlock(&kvm->srcu, rcu_idx);
6092 static long get_nx_lpage_recovery_timeout(u64 start_time)
6094 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6095 ? start_time + 60 * HZ - get_jiffies_64()
6096 : MAX_SCHEDULE_TIMEOUT;
6099 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6102 long remaining_time;
6105 start_time = get_jiffies_64();
6106 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6108 set_current_state(TASK_INTERRUPTIBLE);
6109 while (!kthread_should_stop() && remaining_time > 0) {
6110 schedule_timeout(remaining_time);
6111 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6112 set_current_state(TASK_INTERRUPTIBLE);
6115 set_current_state(TASK_RUNNING);
6117 if (kthread_should_stop())
6120 kvm_recover_nx_lpages(kvm);
6124 int kvm_mmu_post_init_vm(struct kvm *kvm)
6128 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6129 "kvm-nx-lpage-recovery",
6130 &kvm->arch.nx_lpage_recovery_thread);
6132 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6137 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6139 if (kvm->arch.nx_lpage_recovery_thread)
6140 kthread_stop(kvm->arch.nx_lpage_recovery_thread);