1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
51 #include <asm/set_memory.h>
53 #include <asm/kvm_page_track.h>
56 extern bool itlb_multihit_kvm_mitigation;
58 int __read_mostly nx_huge_pages = -1;
59 #ifdef CONFIG_PREEMPT_RT
60 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
61 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
63 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
66 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
67 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops nx_huge_pages_ops = {
70 .set = set_nx_huge_pages,
71 .get = param_get_bool,
74 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
75 .set = set_nx_huge_pages_recovery_ratio,
76 .get = param_get_uint,
79 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
80 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
81 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
82 &nx_huge_pages_recovery_ratio, 0644);
83 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
85 static bool __read_mostly force_flush_and_sync_on_reuse;
86 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
89 * When setting this variable to true it enables Two-Dimensional-Paging
90 * where the hardware walks 2 page tables:
91 * 1. the guest-virtual to guest-physical
92 * 2. while doing 1. it walks guest-physical to host-physical
93 * If the hardware supports that we don't need to do shadow paging.
95 bool tdp_enabled = false;
97 static int max_huge_page_level __read_mostly;
98 static int max_tdp_level __read_mostly;
101 AUDIT_PRE_PAGE_FAULT,
102 AUDIT_POST_PAGE_FAULT,
104 AUDIT_POST_PTE_WRITE,
111 module_param(dbg, bool, 0644);
114 #define PTE_PREFETCH_NUM 8
116 #define PT32_LEVEL_BITS 10
118 #define PT32_LEVEL_SHIFT(level) \
119 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
121 #define PT32_LVL_OFFSET_MASK(level) \
122 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT32_LEVEL_BITS))) - 1))
125 #define PT32_INDEX(address, level)\
126 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
129 #define PT32_BASE_ADDR_MASK PAGE_MASK
130 #define PT32_DIR_BASE_ADDR_MASK \
131 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
132 #define PT32_LVL_ADDR_MASK(level) \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
134 * PT32_LEVEL_BITS))) - 1))
136 #include <trace/events/kvm.h>
138 /* make pte_list_desc fit well in cache line */
139 #define PTE_LIST_EXT 3
141 struct pte_list_desc {
142 u64 *sptes[PTE_LIST_EXT];
143 struct pte_list_desc *more;
146 struct kvm_shadow_walk_iterator {
154 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
155 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
157 shadow_walk_okay(&(_walker)); \
158 shadow_walk_next(&(_walker)))
160 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
161 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
162 shadow_walk_okay(&(_walker)); \
163 shadow_walk_next(&(_walker)))
165 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
166 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
167 shadow_walk_okay(&(_walker)) && \
168 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
169 __shadow_walk_next(&(_walker), spte))
171 static struct kmem_cache *pte_list_desc_cache;
172 struct kmem_cache *mmu_page_header_cache;
173 static struct percpu_counter kvm_total_used_mmu_pages;
175 static void mmu_spte_set(u64 *sptep, u64 spte);
176 static union kvm_mmu_page_role
177 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
179 struct kvm_mmu_role_regs {
180 const unsigned long cr0;
181 const unsigned long cr4;
185 #define CREATE_TRACE_POINTS
186 #include "mmutrace.h"
189 * Yes, lot's of underscores. They're a hint that you probably shouldn't be
190 * reading from the role_regs. Once the mmu_role is constructed, it becomes
191 * the single source of truth for the MMU's state.
193 #define BUILD_MMU_ROLE_REGS_ACCESSOR(reg, name, flag) \
194 static inline bool ____is_##reg##_##name(struct kvm_mmu_role_regs *regs)\
196 return !!(regs->reg & flag); \
198 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, pg, X86_CR0_PG);
199 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, wp, X86_CR0_WP);
200 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pse, X86_CR4_PSE);
201 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pae, X86_CR4_PAE);
202 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smep, X86_CR4_SMEP);
203 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smap, X86_CR4_SMAP);
204 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pke, X86_CR4_PKE);
205 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, la57, X86_CR4_LA57);
206 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, nx, EFER_NX);
207 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, lma, EFER_LMA);
210 * The MMU itself (with a valid role) is the single source of truth for the
211 * MMU. Do not use the regs used to build the MMU/role, nor the vCPU. The
212 * regs don't account for dependencies, e.g. clearing CR4 bits if CR0.PG=1,
213 * and the vCPU may be incorrect/irrelevant.
215 #define BUILD_MMU_ROLE_ACCESSOR(base_or_ext, reg, name) \
216 static inline bool is_##reg##_##name(struct kvm_mmu *mmu) \
218 return !!(mmu->mmu_role. base_or_ext . reg##_##name); \
220 BUILD_MMU_ROLE_ACCESSOR(ext, cr0, pg);
221 BUILD_MMU_ROLE_ACCESSOR(base, cr0, wp);
222 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pse);
223 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pae);
224 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smep);
225 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smap);
226 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pke);
227 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, la57);
228 BUILD_MMU_ROLE_ACCESSOR(base, efer, nx);
230 static struct kvm_mmu_role_regs vcpu_to_role_regs(struct kvm_vcpu *vcpu)
232 struct kvm_mmu_role_regs regs = {
233 .cr0 = kvm_read_cr0_bits(vcpu, KVM_MMU_CR0_ROLE_BITS),
234 .cr4 = kvm_read_cr4_bits(vcpu, KVM_MMU_CR4_ROLE_BITS),
235 .efer = vcpu->arch.efer,
241 static int role_regs_to_root_level(struct kvm_mmu_role_regs *regs)
243 if (!____is_cr0_pg(regs))
245 else if (____is_efer_lma(regs))
246 return ____is_cr4_la57(regs) ? PT64_ROOT_5LEVEL :
248 else if (____is_cr4_pae(regs))
249 return PT32E_ROOT_LEVEL;
251 return PT32_ROOT_LEVEL;
254 static inline bool kvm_available_flush_tlb_with_range(void)
256 return kvm_x86_ops.tlb_remote_flush_with_range;
259 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
260 struct kvm_tlb_range *range)
264 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
265 ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range);
268 kvm_flush_remote_tlbs(kvm);
271 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
272 u64 start_gfn, u64 pages)
274 struct kvm_tlb_range range;
276 range.start_gfn = start_gfn;
279 kvm_flush_remote_tlbs_with_range(kvm, &range);
282 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
285 u64 spte = make_mmio_spte(vcpu, gfn, access);
287 trace_mark_mmio_spte(sptep, gfn, spte);
288 mmu_spte_set(sptep, spte);
291 static gfn_t get_mmio_spte_gfn(u64 spte)
293 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
295 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)
296 & shadow_nonpresent_or_rsvd_mask;
298 return gpa >> PAGE_SHIFT;
301 static unsigned get_mmio_spte_access(u64 spte)
303 return spte & shadow_mmio_access_mask;
306 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
308 u64 kvm_gen, spte_gen, gen;
310 gen = kvm_vcpu_memslots(vcpu)->generation;
311 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
314 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
315 spte_gen = get_mmio_spte_generation(spte);
317 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
318 return likely(kvm_gen == spte_gen);
321 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
322 struct x86_exception *exception)
324 /* Check if guest physical address doesn't exceed guest maximum */
325 if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) {
326 exception->error_code |= PFERR_RSVD_MASK;
333 static int is_cpuid_PSE36(void)
338 static gfn_t pse36_gfn_delta(u32 gpte)
340 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
342 return (gpte & PT32_DIR_PSE36_MASK) << shift;
346 static void __set_spte(u64 *sptep, u64 spte)
348 WRITE_ONCE(*sptep, spte);
351 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
353 WRITE_ONCE(*sptep, spte);
356 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
358 return xchg(sptep, spte);
361 static u64 __get_spte_lockless(u64 *sptep)
363 return READ_ONCE(*sptep);
374 static void count_spte_clear(u64 *sptep, u64 spte)
376 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
378 if (is_shadow_present_pte(spte))
381 /* Ensure the spte is completely set before we increase the count */
383 sp->clear_spte_count++;
386 static void __set_spte(u64 *sptep, u64 spte)
388 union split_spte *ssptep, sspte;
390 ssptep = (union split_spte *)sptep;
391 sspte = (union split_spte)spte;
393 ssptep->spte_high = sspte.spte_high;
396 * If we map the spte from nonpresent to present, We should store
397 * the high bits firstly, then set present bit, so cpu can not
398 * fetch this spte while we are setting the spte.
402 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
405 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
407 union split_spte *ssptep, sspte;
409 ssptep = (union split_spte *)sptep;
410 sspte = (union split_spte)spte;
412 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
415 * If we map the spte from present to nonpresent, we should clear
416 * present bit firstly to avoid vcpu fetch the old high bits.
420 ssptep->spte_high = sspte.spte_high;
421 count_spte_clear(sptep, spte);
424 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
426 union split_spte *ssptep, sspte, orig;
428 ssptep = (union split_spte *)sptep;
429 sspte = (union split_spte)spte;
431 /* xchg acts as a barrier before the setting of the high bits */
432 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
433 orig.spte_high = ssptep->spte_high;
434 ssptep->spte_high = sspte.spte_high;
435 count_spte_clear(sptep, spte);
441 * The idea using the light way get the spte on x86_32 guest is from
442 * gup_get_pte (mm/gup.c).
444 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
445 * coalesces them and we are running out of the MMU lock. Therefore
446 * we need to protect against in-progress updates of the spte.
448 * Reading the spte while an update is in progress may get the old value
449 * for the high part of the spte. The race is fine for a present->non-present
450 * change (because the high part of the spte is ignored for non-present spte),
451 * but for a present->present change we must reread the spte.
453 * All such changes are done in two steps (present->non-present and
454 * non-present->present), hence it is enough to count the number of
455 * present->non-present updates: if it changed while reading the spte,
456 * we might have hit the race. This is done using clear_spte_count.
458 static u64 __get_spte_lockless(u64 *sptep)
460 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
461 union split_spte spte, *orig = (union split_spte *)sptep;
465 count = sp->clear_spte_count;
468 spte.spte_low = orig->spte_low;
471 spte.spte_high = orig->spte_high;
474 if (unlikely(spte.spte_low != orig->spte_low ||
475 count != sp->clear_spte_count))
482 static bool spte_has_volatile_bits(u64 spte)
484 if (!is_shadow_present_pte(spte))
488 * Always atomically update spte if it can be updated
489 * out of mmu-lock, it can ensure dirty bit is not lost,
490 * also, it can help us to get a stable is_writable_pte()
491 * to ensure tlb flush is not missed.
493 if (spte_can_locklessly_be_made_writable(spte) ||
494 is_access_track_spte(spte))
497 if (spte_ad_enabled(spte)) {
498 if ((spte & shadow_accessed_mask) == 0 ||
499 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
506 /* Rules for using mmu_spte_set:
507 * Set the sptep from nonpresent to present.
508 * Note: the sptep being assigned *must* be either not present
509 * or in a state where the hardware will not attempt to update
512 static void mmu_spte_set(u64 *sptep, u64 new_spte)
514 WARN_ON(is_shadow_present_pte(*sptep));
515 __set_spte(sptep, new_spte);
519 * Update the SPTE (excluding the PFN), but do not track changes in its
520 * accessed/dirty status.
522 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
524 u64 old_spte = *sptep;
526 WARN_ON(!is_shadow_present_pte(new_spte));
528 if (!is_shadow_present_pte(old_spte)) {
529 mmu_spte_set(sptep, new_spte);
533 if (!spte_has_volatile_bits(old_spte))
534 __update_clear_spte_fast(sptep, new_spte);
536 old_spte = __update_clear_spte_slow(sptep, new_spte);
538 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
543 /* Rules for using mmu_spte_update:
544 * Update the state bits, it means the mapped pfn is not changed.
546 * Whenever we overwrite a writable spte with a read-only one we
547 * should flush remote TLBs. Otherwise rmap_write_protect
548 * will find a read-only spte, even though the writable spte
549 * might be cached on a CPU's TLB, the return value indicates this
552 * Returns true if the TLB needs to be flushed
554 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
557 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
559 if (!is_shadow_present_pte(old_spte))
563 * For the spte updated out of mmu-lock is safe, since
564 * we always atomically update it, see the comments in
565 * spte_has_volatile_bits().
567 if (spte_can_locklessly_be_made_writable(old_spte) &&
568 !is_writable_pte(new_spte))
572 * Flush TLB when accessed/dirty states are changed in the page tables,
573 * to guarantee consistency between TLB and page tables.
576 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
578 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
581 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
583 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
590 * Rules for using mmu_spte_clear_track_bits:
591 * It sets the sptep from present to nonpresent, and track the
592 * state bits, it is used to clear the last level sptep.
593 * Returns non-zero if the PTE was previously valid.
595 static int mmu_spte_clear_track_bits(u64 *sptep)
598 u64 old_spte = *sptep;
600 if (!spte_has_volatile_bits(old_spte))
601 __update_clear_spte_fast(sptep, 0ull);
603 old_spte = __update_clear_spte_slow(sptep, 0ull);
605 if (!is_shadow_present_pte(old_spte))
608 pfn = spte_to_pfn(old_spte);
611 * KVM does not hold the refcount of the page used by
612 * kvm mmu, before reclaiming the page, we should
613 * unmap it from mmu first.
615 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
617 if (is_accessed_spte(old_spte))
618 kvm_set_pfn_accessed(pfn);
620 if (is_dirty_spte(old_spte))
621 kvm_set_pfn_dirty(pfn);
627 * Rules for using mmu_spte_clear_no_track:
628 * Directly clear spte without caring the state bits of sptep,
629 * it is used to set the upper level spte.
631 static void mmu_spte_clear_no_track(u64 *sptep)
633 __update_clear_spte_fast(sptep, 0ull);
636 static u64 mmu_spte_get_lockless(u64 *sptep)
638 return __get_spte_lockless(sptep);
641 /* Restore an acc-track PTE back to a regular PTE */
642 static u64 restore_acc_track_spte(u64 spte)
645 u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
646 & SHADOW_ACC_TRACK_SAVED_BITS_MASK;
648 WARN_ON_ONCE(spte_ad_enabled(spte));
649 WARN_ON_ONCE(!is_access_track_spte(spte));
651 new_spte &= ~shadow_acc_track_mask;
652 new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
653 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
654 new_spte |= saved_bits;
659 /* Returns the Accessed status of the PTE and resets it at the same time. */
660 static bool mmu_spte_age(u64 *sptep)
662 u64 spte = mmu_spte_get_lockless(sptep);
664 if (!is_accessed_spte(spte))
667 if (spte_ad_enabled(spte)) {
668 clear_bit((ffs(shadow_accessed_mask) - 1),
669 (unsigned long *)sptep);
672 * Capture the dirty status of the page, so that it doesn't get
673 * lost when the SPTE is marked for access tracking.
675 if (is_writable_pte(spte))
676 kvm_set_pfn_dirty(spte_to_pfn(spte));
678 spte = mark_spte_for_access_track(spte);
679 mmu_spte_update_no_track(sptep, spte);
685 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
688 * Prevent page table teardown by making any free-er wait during
689 * kvm_flush_remote_tlbs() IPI to all active vcpus.
694 * Make sure a following spte read is not reordered ahead of the write
697 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
700 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
703 * Make sure the write to vcpu->mode is not reordered in front of
704 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
705 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
707 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
711 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
715 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
716 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
717 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
720 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
721 PT64_ROOT_MAX_LEVEL);
724 if (maybe_indirect) {
725 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
726 PT64_ROOT_MAX_LEVEL);
730 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
731 PT64_ROOT_MAX_LEVEL);
734 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
736 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
737 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
738 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
739 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
742 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
744 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
747 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
749 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
752 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
754 if (!sp->role.direct)
755 return sp->gfns[index];
757 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
760 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
762 if (!sp->role.direct) {
763 sp->gfns[index] = gfn;
767 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
768 pr_err_ratelimited("gfn mismatch under direct page %llx "
769 "(expected %llx, got %llx)\n",
771 kvm_mmu_page_get_gfn(sp, index), gfn);
775 * Return the pointer to the large page information for a given gfn,
776 * handling slots that are not large page aligned.
778 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
779 const struct kvm_memory_slot *slot, int level)
783 idx = gfn_to_index(gfn, slot->base_gfn, level);
784 return &slot->arch.lpage_info[level - 2][idx];
787 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
788 gfn_t gfn, int count)
790 struct kvm_lpage_info *linfo;
793 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
794 linfo = lpage_info_slot(gfn, slot, i);
795 linfo->disallow_lpage += count;
796 WARN_ON(linfo->disallow_lpage < 0);
800 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
802 update_gfn_disallow_lpage_count(slot, gfn, 1);
805 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
807 update_gfn_disallow_lpage_count(slot, gfn, -1);
810 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
812 struct kvm_memslots *slots;
813 struct kvm_memory_slot *slot;
816 kvm->arch.indirect_shadow_pages++;
818 slots = kvm_memslots_for_spte_role(kvm, sp->role);
819 slot = __gfn_to_memslot(slots, gfn);
821 /* the non-leaf shadow pages are keeping readonly. */
822 if (sp->role.level > PG_LEVEL_4K)
823 return kvm_slot_page_track_add_page(kvm, slot, gfn,
824 KVM_PAGE_TRACK_WRITE);
826 kvm_mmu_gfn_disallow_lpage(slot, gfn);
829 void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
831 if (sp->lpage_disallowed)
834 ++kvm->stat.nx_lpage_splits;
835 list_add_tail(&sp->lpage_disallowed_link,
836 &kvm->arch.lpage_disallowed_mmu_pages);
837 sp->lpage_disallowed = true;
840 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
842 struct kvm_memslots *slots;
843 struct kvm_memory_slot *slot;
846 kvm->arch.indirect_shadow_pages--;
848 slots = kvm_memslots_for_spte_role(kvm, sp->role);
849 slot = __gfn_to_memslot(slots, gfn);
850 if (sp->role.level > PG_LEVEL_4K)
851 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
852 KVM_PAGE_TRACK_WRITE);
854 kvm_mmu_gfn_allow_lpage(slot, gfn);
857 void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
859 --kvm->stat.nx_lpage_splits;
860 sp->lpage_disallowed = false;
861 list_del(&sp->lpage_disallowed_link);
864 static struct kvm_memory_slot *
865 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
868 struct kvm_memory_slot *slot;
870 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
871 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
873 if (no_dirty_log && kvm_slot_dirty_track_enabled(slot))
880 * About rmap_head encoding:
882 * If the bit zero of rmap_head->val is clear, then it points to the only spte
883 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
884 * pte_list_desc containing more mappings.
888 * Returns the number of pointers in the rmap chain, not counting the new one.
890 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
891 struct kvm_rmap_head *rmap_head)
893 struct pte_list_desc *desc;
896 if (!rmap_head->val) {
897 rmap_printk("%p %llx 0->1\n", spte, *spte);
898 rmap_head->val = (unsigned long)spte;
899 } else if (!(rmap_head->val & 1)) {
900 rmap_printk("%p %llx 1->many\n", spte, *spte);
901 desc = mmu_alloc_pte_list_desc(vcpu);
902 desc->sptes[0] = (u64 *)rmap_head->val;
903 desc->sptes[1] = spte;
904 rmap_head->val = (unsigned long)desc | 1;
907 rmap_printk("%p %llx many->many\n", spte, *spte);
908 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
909 while (desc->sptes[PTE_LIST_EXT-1]) {
910 count += PTE_LIST_EXT;
913 desc->more = mmu_alloc_pte_list_desc(vcpu);
919 for (i = 0; desc->sptes[i]; ++i)
921 desc->sptes[i] = spte;
927 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
928 struct pte_list_desc *desc, int i,
929 struct pte_list_desc *prev_desc)
933 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
935 desc->sptes[i] = desc->sptes[j];
936 desc->sptes[j] = NULL;
939 if (!prev_desc && !desc->more)
943 prev_desc->more = desc->more;
945 rmap_head->val = (unsigned long)desc->more | 1;
946 mmu_free_pte_list_desc(desc);
949 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
951 struct pte_list_desc *desc;
952 struct pte_list_desc *prev_desc;
955 if (!rmap_head->val) {
956 pr_err("%s: %p 0->BUG\n", __func__, spte);
958 } else if (!(rmap_head->val & 1)) {
959 rmap_printk("%p 1->0\n", spte);
960 if ((u64 *)rmap_head->val != spte) {
961 pr_err("%s: %p 1->BUG\n", __func__, spte);
966 rmap_printk("%p many->many\n", spte);
967 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
970 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
971 if (desc->sptes[i] == spte) {
972 pte_list_desc_remove_entry(rmap_head,
980 pr_err("%s: %p many->many\n", __func__, spte);
985 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
987 mmu_spte_clear_track_bits(sptep);
988 __pte_list_remove(sptep, rmap_head);
991 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
992 struct kvm_memory_slot *slot)
996 idx = gfn_to_index(gfn, slot->base_gfn, level);
997 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
1000 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1001 struct kvm_mmu_page *sp)
1003 struct kvm_memslots *slots;
1004 struct kvm_memory_slot *slot;
1006 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1007 slot = __gfn_to_memslot(slots, gfn);
1008 return __gfn_to_rmap(gfn, sp->role.level, slot);
1011 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1013 struct kvm_mmu_memory_cache *mc;
1015 mc = &vcpu->arch.mmu_pte_list_desc_cache;
1016 return kvm_mmu_memory_cache_nr_free_objects(mc);
1019 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1021 struct kvm_mmu_page *sp;
1022 struct kvm_rmap_head *rmap_head;
1024 sp = sptep_to_sp(spte);
1025 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1026 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1027 return pte_list_add(vcpu, spte, rmap_head);
1030 static void rmap_remove(struct kvm *kvm, u64 *spte)
1032 struct kvm_mmu_page *sp;
1034 struct kvm_rmap_head *rmap_head;
1036 sp = sptep_to_sp(spte);
1037 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1038 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1039 __pte_list_remove(spte, rmap_head);
1043 * Used by the following functions to iterate through the sptes linked by a
1044 * rmap. All fields are private and not assumed to be used outside.
1046 struct rmap_iterator {
1047 /* private fields */
1048 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1049 int pos; /* index of the sptep */
1053 * Iteration must be started by this function. This should also be used after
1054 * removing/dropping sptes from the rmap link because in such cases the
1055 * information in the iterator may not be valid.
1057 * Returns sptep if found, NULL otherwise.
1059 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1060 struct rmap_iterator *iter)
1064 if (!rmap_head->val)
1067 if (!(rmap_head->val & 1)) {
1069 sptep = (u64 *)rmap_head->val;
1073 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1075 sptep = iter->desc->sptes[iter->pos];
1077 BUG_ON(!is_shadow_present_pte(*sptep));
1082 * Must be used with a valid iterator: e.g. after rmap_get_first().
1084 * Returns sptep if found, NULL otherwise.
1086 static u64 *rmap_get_next(struct rmap_iterator *iter)
1091 if (iter->pos < PTE_LIST_EXT - 1) {
1093 sptep = iter->desc->sptes[iter->pos];
1098 iter->desc = iter->desc->more;
1102 /* desc->sptes[0] cannot be NULL */
1103 sptep = iter->desc->sptes[iter->pos];
1110 BUG_ON(!is_shadow_present_pte(*sptep));
1114 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1115 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1116 _spte_; _spte_ = rmap_get_next(_iter_))
1118 static void drop_spte(struct kvm *kvm, u64 *sptep)
1120 if (mmu_spte_clear_track_bits(sptep))
1121 rmap_remove(kvm, sptep);
1125 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1127 if (is_large_pte(*sptep)) {
1128 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1129 drop_spte(kvm, sptep);
1137 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1139 if (__drop_large_spte(vcpu->kvm, sptep)) {
1140 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1142 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1143 KVM_PAGES_PER_HPAGE(sp->role.level));
1148 * Write-protect on the specified @sptep, @pt_protect indicates whether
1149 * spte write-protection is caused by protecting shadow page table.
1151 * Note: write protection is difference between dirty logging and spte
1153 * - for dirty logging, the spte can be set to writable at anytime if
1154 * its dirty bitmap is properly set.
1155 * - for spte protection, the spte can be writable only after unsync-ing
1158 * Return true if tlb need be flushed.
1160 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1164 if (!is_writable_pte(spte) &&
1165 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1168 rmap_printk("spte %p %llx\n", sptep, *sptep);
1171 spte &= ~shadow_mmu_writable_mask;
1172 spte = spte & ~PT_WRITABLE_MASK;
1174 return mmu_spte_update(sptep, spte);
1177 static bool __rmap_write_protect(struct kvm *kvm,
1178 struct kvm_rmap_head *rmap_head,
1182 struct rmap_iterator iter;
1185 for_each_rmap_spte(rmap_head, &iter, sptep)
1186 flush |= spte_write_protect(sptep, pt_protect);
1191 static bool spte_clear_dirty(u64 *sptep)
1195 rmap_printk("spte %p %llx\n", sptep, *sptep);
1197 MMU_WARN_ON(!spte_ad_enabled(spte));
1198 spte &= ~shadow_dirty_mask;
1199 return mmu_spte_update(sptep, spte);
1202 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1204 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1205 (unsigned long *)sptep);
1206 if (was_writable && !spte_ad_enabled(*sptep))
1207 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1209 return was_writable;
1213 * Gets the GFN ready for another round of dirty logging by clearing the
1214 * - D bit on ad-enabled SPTEs, and
1215 * - W bit on ad-disabled SPTEs.
1216 * Returns true iff any D or W bits were cleared.
1218 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1219 struct kvm_memory_slot *slot)
1222 struct rmap_iterator iter;
1225 for_each_rmap_spte(rmap_head, &iter, sptep)
1226 if (spte_ad_need_write_protect(*sptep))
1227 flush |= spte_wrprot_for_clear_dirty(sptep);
1229 flush |= spte_clear_dirty(sptep);
1235 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1236 * @kvm: kvm instance
1237 * @slot: slot to protect
1238 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1239 * @mask: indicates which pages we should protect
1241 * Used when we do not need to care about huge page mappings.
1243 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1244 struct kvm_memory_slot *slot,
1245 gfn_t gfn_offset, unsigned long mask)
1247 struct kvm_rmap_head *rmap_head;
1249 if (is_tdp_mmu_enabled(kvm))
1250 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1251 slot->base_gfn + gfn_offset, mask, true);
1253 if (!kvm_memslots_have_rmaps(kvm))
1257 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1259 __rmap_write_protect(kvm, rmap_head, false);
1261 /* clear the first set bit */
1267 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1268 * protect the page if the D-bit isn't supported.
1269 * @kvm: kvm instance
1270 * @slot: slot to clear D-bit
1271 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1272 * @mask: indicates which pages we should clear D-bit
1274 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1276 static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1277 struct kvm_memory_slot *slot,
1278 gfn_t gfn_offset, unsigned long mask)
1280 struct kvm_rmap_head *rmap_head;
1282 if (is_tdp_mmu_enabled(kvm))
1283 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1284 slot->base_gfn + gfn_offset, mask, false);
1286 if (!kvm_memslots_have_rmaps(kvm))
1290 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1292 __rmap_clear_dirty(kvm, rmap_head, slot);
1294 /* clear the first set bit */
1300 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1303 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1304 * enable dirty logging for them.
1306 * We need to care about huge page mappings: e.g. during dirty logging we may
1307 * have such mappings.
1309 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1310 struct kvm_memory_slot *slot,
1311 gfn_t gfn_offset, unsigned long mask)
1314 * Huge pages are NOT write protected when we start dirty logging in
1315 * initially-all-set mode; must write protect them here so that they
1316 * are split to 4K on the first write.
1318 * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn
1319 * of memslot has no such restriction, so the range can cross two large
1322 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) {
1323 gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask);
1324 gfn_t end = slot->base_gfn + gfn_offset + __fls(mask);
1326 kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M);
1328 /* Cross two large pages? */
1329 if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) !=
1330 ALIGN(end << PAGE_SHIFT, PMD_SIZE))
1331 kvm_mmu_slot_gfn_write_protect(kvm, slot, end,
1335 /* Now handle 4K PTEs. */
1336 if (kvm_x86_ops.cpu_dirty_log_size)
1337 kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask);
1339 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1342 int kvm_cpu_dirty_log_size(void)
1344 return kvm_x86_ops.cpu_dirty_log_size;
1347 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1348 struct kvm_memory_slot *slot, u64 gfn,
1351 struct kvm_rmap_head *rmap_head;
1353 bool write_protected = false;
1355 if (kvm_memslots_have_rmaps(kvm)) {
1356 for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1357 rmap_head = __gfn_to_rmap(gfn, i, slot);
1358 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1362 if (is_tdp_mmu_enabled(kvm))
1364 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level);
1366 return write_protected;
1369 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1371 struct kvm_memory_slot *slot;
1373 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1374 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K);
1377 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1378 struct kvm_memory_slot *slot)
1381 struct rmap_iterator iter;
1384 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1385 rmap_printk("spte %p %llx.\n", sptep, *sptep);
1387 pte_list_remove(rmap_head, sptep);
1394 static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1395 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1398 return kvm_zap_rmapp(kvm, rmap_head, slot);
1401 static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1402 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1406 struct rmap_iterator iter;
1411 WARN_ON(pte_huge(pte));
1412 new_pfn = pte_pfn(pte);
1415 for_each_rmap_spte(rmap_head, &iter, sptep) {
1416 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1417 sptep, *sptep, gfn, level);
1421 if (pte_write(pte)) {
1422 pte_list_remove(rmap_head, sptep);
1425 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1428 mmu_spte_clear_track_bits(sptep);
1429 mmu_spte_set(sptep, new_spte);
1433 if (need_flush && kvm_available_flush_tlb_with_range()) {
1434 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1441 struct slot_rmap_walk_iterator {
1443 struct kvm_memory_slot *slot;
1449 /* output fields. */
1451 struct kvm_rmap_head *rmap;
1454 /* private field. */
1455 struct kvm_rmap_head *end_rmap;
1459 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1461 iterator->level = level;
1462 iterator->gfn = iterator->start_gfn;
1463 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1464 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1469 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1470 struct kvm_memory_slot *slot, int start_level,
1471 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1473 iterator->slot = slot;
1474 iterator->start_level = start_level;
1475 iterator->end_level = end_level;
1476 iterator->start_gfn = start_gfn;
1477 iterator->end_gfn = end_gfn;
1479 rmap_walk_init_level(iterator, iterator->start_level);
1482 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1484 return !!iterator->rmap;
1487 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1489 if (++iterator->rmap <= iterator->end_rmap) {
1490 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1494 if (++iterator->level > iterator->end_level) {
1495 iterator->rmap = NULL;
1499 rmap_walk_init_level(iterator, iterator->level);
1502 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1503 _start_gfn, _end_gfn, _iter_) \
1504 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1505 _end_level_, _start_gfn, _end_gfn); \
1506 slot_rmap_walk_okay(_iter_); \
1507 slot_rmap_walk_next(_iter_))
1509 typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1510 struct kvm_memory_slot *slot, gfn_t gfn,
1511 int level, pte_t pte);
1513 static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm,
1514 struct kvm_gfn_range *range,
1515 rmap_handler_t handler)
1517 struct slot_rmap_walk_iterator iterator;
1520 for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL,
1521 range->start, range->end - 1, &iterator)
1522 ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn,
1523 iterator.level, range->pte);
1528 bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range)
1532 if (kvm_memslots_have_rmaps(kvm))
1533 flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp);
1535 if (is_tdp_mmu_enabled(kvm))
1536 flush |= kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush);
1541 bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1545 if (kvm_memslots_have_rmaps(kvm))
1546 flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp);
1548 if (is_tdp_mmu_enabled(kvm))
1549 flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range);
1554 static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1555 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1559 struct rmap_iterator iter;
1562 for_each_rmap_spte(rmap_head, &iter, sptep)
1563 young |= mmu_spte_age(sptep);
1568 static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1569 struct kvm_memory_slot *slot, gfn_t gfn,
1570 int level, pte_t unused)
1573 struct rmap_iterator iter;
1575 for_each_rmap_spte(rmap_head, &iter, sptep)
1576 if (is_accessed_spte(*sptep))
1581 #define RMAP_RECYCLE_THRESHOLD 1000
1583 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1585 struct kvm_rmap_head *rmap_head;
1586 struct kvm_mmu_page *sp;
1588 sp = sptep_to_sp(spte);
1590 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1592 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0));
1593 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1594 KVM_PAGES_PER_HPAGE(sp->role.level));
1597 bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1601 if (kvm_memslots_have_rmaps(kvm))
1602 young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp);
1604 if (is_tdp_mmu_enabled(kvm))
1605 young |= kvm_tdp_mmu_age_gfn_range(kvm, range);
1610 bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1614 if (kvm_memslots_have_rmaps(kvm))
1615 young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp);
1617 if (is_tdp_mmu_enabled(kvm))
1618 young |= kvm_tdp_mmu_test_age_gfn(kvm, range);
1624 static int is_empty_shadow_page(u64 *spt)
1629 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1630 if (is_shadow_present_pte(*pos)) {
1631 printk(KERN_ERR "%s: %p %llx\n", __func__,
1640 * This value is the sum of all of the kvm instances's
1641 * kvm->arch.n_used_mmu_pages values. We need a global,
1642 * aggregate version in order to make the slab shrinker
1645 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
1647 kvm->arch.n_used_mmu_pages += nr;
1648 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1651 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1653 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1654 hlist_del(&sp->hash_link);
1655 list_del(&sp->link);
1656 free_page((unsigned long)sp->spt);
1657 if (!sp->role.direct)
1658 free_page((unsigned long)sp->gfns);
1659 kmem_cache_free(mmu_page_header_cache, sp);
1662 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1664 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1667 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1668 struct kvm_mmu_page *sp, u64 *parent_pte)
1673 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1676 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1679 __pte_list_remove(parent_pte, &sp->parent_ptes);
1682 static void drop_parent_pte(struct kvm_mmu_page *sp,
1685 mmu_page_remove_parent_pte(sp, parent_pte);
1686 mmu_spte_clear_no_track(parent_pte);
1689 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1691 struct kvm_mmu_page *sp;
1693 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1694 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1696 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1697 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1700 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1701 * depends on valid pages being added to the head of the list. See
1702 * comments in kvm_zap_obsolete_pages().
1704 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1705 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1706 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1710 static void mark_unsync(u64 *spte);
1711 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1714 struct rmap_iterator iter;
1716 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1721 static void mark_unsync(u64 *spte)
1723 struct kvm_mmu_page *sp;
1726 sp = sptep_to_sp(spte);
1727 index = spte - sp->spt;
1728 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1730 if (sp->unsync_children++)
1732 kvm_mmu_mark_parents_unsync(sp);
1735 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1736 struct kvm_mmu_page *sp)
1741 #define KVM_PAGE_ARRAY_NR 16
1743 struct kvm_mmu_pages {
1744 struct mmu_page_and_offset {
1745 struct kvm_mmu_page *sp;
1747 } page[KVM_PAGE_ARRAY_NR];
1751 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1757 for (i=0; i < pvec->nr; i++)
1758 if (pvec->page[i].sp == sp)
1761 pvec->page[pvec->nr].sp = sp;
1762 pvec->page[pvec->nr].idx = idx;
1764 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1767 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1769 --sp->unsync_children;
1770 WARN_ON((int)sp->unsync_children < 0);
1771 __clear_bit(idx, sp->unsync_child_bitmap);
1774 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1775 struct kvm_mmu_pages *pvec)
1777 int i, ret, nr_unsync_leaf = 0;
1779 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1780 struct kvm_mmu_page *child;
1781 u64 ent = sp->spt[i];
1783 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1784 clear_unsync_child_bit(sp, i);
1788 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1790 if (child->unsync_children) {
1791 if (mmu_pages_add(pvec, child, i))
1794 ret = __mmu_unsync_walk(child, pvec);
1796 clear_unsync_child_bit(sp, i);
1798 } else if (ret > 0) {
1799 nr_unsync_leaf += ret;
1802 } else if (child->unsync) {
1804 if (mmu_pages_add(pvec, child, i))
1807 clear_unsync_child_bit(sp, i);
1810 return nr_unsync_leaf;
1813 #define INVALID_INDEX (-1)
1815 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1816 struct kvm_mmu_pages *pvec)
1819 if (!sp->unsync_children)
1822 mmu_pages_add(pvec, sp, INVALID_INDEX);
1823 return __mmu_unsync_walk(sp, pvec);
1826 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1828 WARN_ON(!sp->unsync);
1829 trace_kvm_mmu_sync_page(sp);
1831 --kvm->stat.mmu_unsync;
1834 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1835 struct list_head *invalid_list);
1836 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1837 struct list_head *invalid_list);
1839 #define for_each_valid_sp(_kvm, _sp, _list) \
1840 hlist_for_each_entry(_sp, _list, hash_link) \
1841 if (is_obsolete_sp((_kvm), (_sp))) { \
1844 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1845 for_each_valid_sp(_kvm, _sp, \
1846 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1847 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1849 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1850 struct list_head *invalid_list)
1852 if (vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
1853 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1860 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1861 struct list_head *invalid_list,
1864 if (!remote_flush && list_empty(invalid_list))
1867 if (!list_empty(invalid_list))
1868 kvm_mmu_commit_zap_page(kvm, invalid_list);
1870 kvm_flush_remote_tlbs(kvm);
1874 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1875 struct list_head *invalid_list,
1876 bool remote_flush, bool local_flush)
1878 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
1882 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1885 #ifdef CONFIG_KVM_MMU_AUDIT
1886 #include "mmu_audit.c"
1888 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1889 static void mmu_audit_disable(void) { }
1892 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1894 return sp->role.invalid ||
1895 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1898 struct mmu_page_path {
1899 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1900 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1903 #define for_each_sp(pvec, sp, parents, i) \
1904 for (i = mmu_pages_first(&pvec, &parents); \
1905 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1906 i = mmu_pages_next(&pvec, &parents, i))
1908 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1909 struct mmu_page_path *parents,
1914 for (n = i+1; n < pvec->nr; n++) {
1915 struct kvm_mmu_page *sp = pvec->page[n].sp;
1916 unsigned idx = pvec->page[n].idx;
1917 int level = sp->role.level;
1919 parents->idx[level-1] = idx;
1920 if (level == PG_LEVEL_4K)
1923 parents->parent[level-2] = sp;
1929 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1930 struct mmu_page_path *parents)
1932 struct kvm_mmu_page *sp;
1938 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1940 sp = pvec->page[0].sp;
1941 level = sp->role.level;
1942 WARN_ON(level == PG_LEVEL_4K);
1944 parents->parent[level-2] = sp;
1946 /* Also set up a sentinel. Further entries in pvec are all
1947 * children of sp, so this element is never overwritten.
1949 parents->parent[level-1] = NULL;
1950 return mmu_pages_next(pvec, parents, 0);
1953 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1955 struct kvm_mmu_page *sp;
1956 unsigned int level = 0;
1959 unsigned int idx = parents->idx[level];
1960 sp = parents->parent[level];
1964 WARN_ON(idx == INVALID_INDEX);
1965 clear_unsync_child_bit(sp, idx);
1967 } while (!sp->unsync_children);
1970 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1971 struct kvm_mmu_page *parent)
1974 struct kvm_mmu_page *sp;
1975 struct mmu_page_path parents;
1976 struct kvm_mmu_pages pages;
1977 LIST_HEAD(invalid_list);
1980 while (mmu_unsync_walk(parent, &pages)) {
1981 bool protected = false;
1983 for_each_sp(pages, sp, parents, i)
1984 protected |= rmap_write_protect(vcpu, sp->gfn);
1987 kvm_flush_remote_tlbs(vcpu->kvm);
1991 for_each_sp(pages, sp, parents, i) {
1992 kvm_unlink_unsync_page(vcpu->kvm, sp);
1993 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
1994 mmu_pages_clear_parents(&parents);
1996 if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) {
1997 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1998 cond_resched_rwlock_write(&vcpu->kvm->mmu_lock);
2003 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2006 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2008 atomic_set(&sp->write_flooding_count, 0);
2011 static void clear_sp_write_flooding_count(u64 *spte)
2013 __clear_sp_write_flooding_count(sptep_to_sp(spte));
2016 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2021 unsigned int access)
2023 bool direct_mmu = vcpu->arch.mmu->direct_map;
2024 union kvm_mmu_page_role role;
2025 struct hlist_head *sp_list;
2027 struct kvm_mmu_page *sp;
2029 LIST_HEAD(invalid_list);
2031 role = vcpu->arch.mmu->mmu_role.base;
2033 role.direct = direct;
2035 role.gpte_is_8_bytes = true;
2036 role.access = access;
2037 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2038 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2039 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2040 role.quadrant = quadrant;
2043 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2044 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2045 if (sp->gfn != gfn) {
2050 if (sp->role.word != role.word) {
2052 * If the guest is creating an upper-level page, zap
2053 * unsync pages for the same gfn. While it's possible
2054 * the guest is using recursive page tables, in all
2055 * likelihood the guest has stopped using the unsync
2056 * page and is installing a completely unrelated page.
2057 * Unsync pages must not be left as is, because the new
2058 * upper-level page will be write-protected.
2060 if (level > PG_LEVEL_4K && sp->unsync)
2061 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2067 goto trace_get_page;
2071 * The page is good, but is stale. kvm_sync_page does
2072 * get the latest guest state, but (unlike mmu_unsync_children)
2073 * it doesn't write-protect the page or mark it synchronized!
2074 * This way the validity of the mapping is ensured, but the
2075 * overhead of write protection is not incurred until the
2076 * guest invalidates the TLB mapping. This allows multiple
2077 * SPs for a single gfn to be unsync.
2079 * If the sync fails, the page is zapped. If so, break
2080 * in order to rebuild it.
2082 if (!kvm_sync_page(vcpu, sp, &invalid_list))
2085 WARN_ON(!list_empty(&invalid_list));
2086 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2089 if (sp->unsync_children)
2090 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2092 __clear_sp_write_flooding_count(sp);
2095 trace_kvm_mmu_get_page(sp, false);
2099 ++vcpu->kvm->stat.mmu_cache_miss;
2101 sp = kvm_mmu_alloc_page(vcpu, direct);
2105 hlist_add_head(&sp->hash_link, sp_list);
2107 account_shadowed(vcpu->kvm, sp);
2108 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2109 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2111 trace_kvm_mmu_get_page(sp, true);
2113 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2115 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2116 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2120 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2121 struct kvm_vcpu *vcpu, hpa_t root,
2124 iterator->addr = addr;
2125 iterator->shadow_addr = root;
2126 iterator->level = vcpu->arch.mmu->shadow_root_level;
2128 if (iterator->level == PT64_ROOT_4LEVEL &&
2129 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2130 !vcpu->arch.mmu->direct_map)
2133 if (iterator->level == PT32E_ROOT_LEVEL) {
2135 * prev_root is currently only used for 64-bit hosts. So only
2136 * the active root_hpa is valid here.
2138 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2140 iterator->shadow_addr
2141 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2142 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2144 if (!iterator->shadow_addr)
2145 iterator->level = 0;
2149 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2150 struct kvm_vcpu *vcpu, u64 addr)
2152 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2156 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2158 if (iterator->level < PG_LEVEL_4K)
2161 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2162 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2166 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2169 if (is_last_spte(spte, iterator->level)) {
2170 iterator->level = 0;
2174 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2178 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2180 __shadow_walk_next(iterator, *iterator->sptep);
2183 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2184 struct kvm_mmu_page *sp)
2188 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2190 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2192 mmu_spte_set(sptep, spte);
2194 mmu_page_add_parent_pte(vcpu, sp, sptep);
2196 if (sp->unsync_children || sp->unsync)
2200 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2201 unsigned direct_access)
2203 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2204 struct kvm_mmu_page *child;
2207 * For the direct sp, if the guest pte's dirty bit
2208 * changed form clean to dirty, it will corrupt the
2209 * sp's access: allow writable in the read-only sp,
2210 * so we should update the spte at this point to get
2211 * a new sp with the correct access.
2213 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2214 if (child->role.access == direct_access)
2217 drop_parent_pte(child, sptep);
2218 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2222 /* Returns the number of zapped non-leaf child shadow pages. */
2223 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2224 u64 *spte, struct list_head *invalid_list)
2227 struct kvm_mmu_page *child;
2230 if (is_shadow_present_pte(pte)) {
2231 if (is_last_spte(pte, sp->role.level)) {
2232 drop_spte(kvm, spte);
2233 if (is_large_pte(pte))
2236 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2237 drop_parent_pte(child, spte);
2240 * Recursively zap nested TDP SPs, parentless SPs are
2241 * unlikely to be used again in the near future. This
2242 * avoids retaining a large number of stale nested SPs.
2244 if (tdp_enabled && invalid_list &&
2245 child->role.guest_mode && !child->parent_ptes.val)
2246 return kvm_mmu_prepare_zap_page(kvm, child,
2249 } else if (is_mmio_spte(pte)) {
2250 mmu_spte_clear_no_track(spte);
2255 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2256 struct kvm_mmu_page *sp,
2257 struct list_head *invalid_list)
2262 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2263 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2268 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2271 struct rmap_iterator iter;
2273 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2274 drop_parent_pte(sp, sptep);
2277 static int mmu_zap_unsync_children(struct kvm *kvm,
2278 struct kvm_mmu_page *parent,
2279 struct list_head *invalid_list)
2282 struct mmu_page_path parents;
2283 struct kvm_mmu_pages pages;
2285 if (parent->role.level == PG_LEVEL_4K)
2288 while (mmu_unsync_walk(parent, &pages)) {
2289 struct kvm_mmu_page *sp;
2291 for_each_sp(pages, sp, parents, i) {
2292 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2293 mmu_pages_clear_parents(&parents);
2301 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2302 struct kvm_mmu_page *sp,
2303 struct list_head *invalid_list,
2308 trace_kvm_mmu_prepare_zap_page(sp);
2309 ++kvm->stat.mmu_shadow_zapped;
2310 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2311 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2312 kvm_mmu_unlink_parents(kvm, sp);
2314 /* Zapping children means active_mmu_pages has become unstable. */
2315 list_unstable = *nr_zapped;
2317 if (!sp->role.invalid && !sp->role.direct)
2318 unaccount_shadowed(kvm, sp);
2321 kvm_unlink_unsync_page(kvm, sp);
2322 if (!sp->root_count) {
2327 * Already invalid pages (previously active roots) are not on
2328 * the active page list. See list_del() in the "else" case of
2331 if (sp->role.invalid)
2332 list_add(&sp->link, invalid_list);
2334 list_move(&sp->link, invalid_list);
2335 kvm_mod_used_mmu_pages(kvm, -1);
2338 * Remove the active root from the active page list, the root
2339 * will be explicitly freed when the root_count hits zero.
2341 list_del(&sp->link);
2344 * Obsolete pages cannot be used on any vCPUs, see the comment
2345 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2346 * treats invalid shadow pages as being obsolete.
2348 if (!is_obsolete_sp(kvm, sp))
2349 kvm_reload_remote_mmus(kvm);
2352 if (sp->lpage_disallowed)
2353 unaccount_huge_nx_page(kvm, sp);
2355 sp->role.invalid = 1;
2356 return list_unstable;
2359 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2360 struct list_head *invalid_list)
2364 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2368 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2369 struct list_head *invalid_list)
2371 struct kvm_mmu_page *sp, *nsp;
2373 if (list_empty(invalid_list))
2377 * We need to make sure everyone sees our modifications to
2378 * the page tables and see changes to vcpu->mode here. The barrier
2379 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2380 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2382 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2383 * guest mode and/or lockless shadow page table walks.
2385 kvm_flush_remote_tlbs(kvm);
2387 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2388 WARN_ON(!sp->role.invalid || sp->root_count);
2389 kvm_mmu_free_page(sp);
2393 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2394 unsigned long nr_to_zap)
2396 unsigned long total_zapped = 0;
2397 struct kvm_mmu_page *sp, *tmp;
2398 LIST_HEAD(invalid_list);
2402 if (list_empty(&kvm->arch.active_mmu_pages))
2406 list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2408 * Don't zap active root pages, the page itself can't be freed
2409 * and zapping it will just force vCPUs to realloc and reload.
2414 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2416 total_zapped += nr_zapped;
2417 if (total_zapped >= nr_to_zap)
2424 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2426 kvm->stat.mmu_recycled += total_zapped;
2427 return total_zapped;
2430 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2432 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2433 return kvm->arch.n_max_mmu_pages -
2434 kvm->arch.n_used_mmu_pages;
2439 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2441 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2443 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2446 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2449 * Note, this check is intentionally soft, it only guarantees that one
2450 * page is available, while the caller may end up allocating as many as
2451 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2452 * exceeding the (arbitrary by default) limit will not harm the host,
2453 * being too agressive may unnecessarily kill the guest, and getting an
2454 * exact count is far more trouble than it's worth, especially in the
2457 if (!kvm_mmu_available_pages(vcpu->kvm))
2463 * Changing the number of mmu pages allocated to the vm
2464 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2466 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2468 write_lock(&kvm->mmu_lock);
2470 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2471 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2474 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2477 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2479 write_unlock(&kvm->mmu_lock);
2482 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2484 struct kvm_mmu_page *sp;
2485 LIST_HEAD(invalid_list);
2488 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2490 write_lock(&kvm->mmu_lock);
2491 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2492 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2495 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2497 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2498 write_unlock(&kvm->mmu_lock);
2503 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2508 if (vcpu->arch.mmu->direct_map)
2511 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2513 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2518 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2520 trace_kvm_mmu_unsync_page(sp);
2521 ++vcpu->kvm->stat.mmu_unsync;
2524 kvm_mmu_mark_parents_unsync(sp);
2528 * Attempt to unsync any shadow pages that can be reached by the specified gfn,
2529 * KVM is creating a writable mapping for said gfn. Returns 0 if all pages
2530 * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must
2531 * be write-protected.
2533 int mmu_try_to_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, bool can_unsync)
2535 struct kvm_mmu_page *sp;
2538 * Force write-protection if the page is being tracked. Note, the page
2539 * track machinery is used to write-protect upper-level shadow pages,
2540 * i.e. this guards the role.level == 4K assertion below!
2542 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2546 * The page is not write-tracked, mark existing shadow pages unsync
2547 * unless KVM is synchronizing an unsync SP (can_unsync = false). In
2548 * that case, KVM must complete emulation of the guest TLB flush before
2549 * allowing shadow pages to become unsync (writable by the guest).
2551 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2558 WARN_ON(sp->role.level != PG_LEVEL_4K);
2559 kvm_unsync_page(vcpu, sp);
2563 * We need to ensure that the marking of unsync pages is visible
2564 * before the SPTE is updated to allow writes because
2565 * kvm_mmu_sync_roots() checks the unsync flags without holding
2566 * the MMU lock and so can race with this. If the SPTE was updated
2567 * before the page had been marked as unsync-ed, something like the
2568 * following could happen:
2571 * ---------------------------------------------------------------------
2572 * 1.2 Host updates SPTE
2574 * 2.1 Guest writes a GPTE for GVA X.
2575 * (GPTE being in the guest page table shadowed
2576 * by the SP from CPU 1.)
2577 * This reads SPTE during the page table walk.
2578 * Since SPTE.W is read as 1, there is no
2581 * 2.2 Guest issues TLB flush.
2582 * That causes a VM Exit.
2584 * 2.3 Walking of unsync pages sees sp->unsync is
2585 * false and skips the page.
2587 * 2.4 Guest accesses GVA X.
2588 * Since the mapping in the SP was not updated,
2589 * so the old mapping for GVA X incorrectly
2593 * (sp->unsync = true)
2595 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2596 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2597 * pairs with this write barrier.
2604 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2605 unsigned int pte_access, int level,
2606 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2607 bool can_unsync, bool host_writable)
2610 struct kvm_mmu_page *sp;
2613 sp = sptep_to_sp(sptep);
2615 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2616 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2618 if (spte & PT_WRITABLE_MASK)
2619 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2622 ret |= SET_SPTE_SPURIOUS;
2623 else if (mmu_spte_update(sptep, spte))
2624 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2628 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2629 unsigned int pte_access, bool write_fault, int level,
2630 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2633 int was_rmapped = 0;
2636 int ret = RET_PF_FIXED;
2639 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2640 *sptep, write_fault, gfn);
2642 if (unlikely(is_noslot_pfn(pfn))) {
2643 mark_mmio_spte(vcpu, sptep, gfn, pte_access);
2644 return RET_PF_EMULATE;
2647 if (is_shadow_present_pte(*sptep)) {
2649 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2650 * the parent of the now unreachable PTE.
2652 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2653 struct kvm_mmu_page *child;
2656 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2657 drop_parent_pte(child, sptep);
2659 } else if (pfn != spte_to_pfn(*sptep)) {
2660 pgprintk("hfn old %llx new %llx\n",
2661 spte_to_pfn(*sptep), pfn);
2662 drop_spte(vcpu->kvm, sptep);
2668 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2669 speculative, true, host_writable);
2670 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2672 ret = RET_PF_EMULATE;
2673 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2676 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2677 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2678 KVM_PAGES_PER_HPAGE(level));
2681 * The fault is fully spurious if and only if the new SPTE and old SPTE
2682 * are identical, and emulation is not required.
2684 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2685 WARN_ON_ONCE(!was_rmapped);
2686 return RET_PF_SPURIOUS;
2689 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2690 trace_kvm_mmu_set_spte(level, gfn, sptep);
2691 if (!was_rmapped && is_large_pte(*sptep))
2692 ++vcpu->kvm->stat.lpages;
2694 if (is_shadow_present_pte(*sptep)) {
2696 rmap_count = rmap_add(vcpu, sptep, gfn);
2697 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2698 rmap_recycle(vcpu, sptep, gfn);
2705 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2708 struct kvm_memory_slot *slot;
2710 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2712 return KVM_PFN_ERR_FAULT;
2714 return gfn_to_pfn_memslot_atomic(slot, gfn);
2717 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2718 struct kvm_mmu_page *sp,
2719 u64 *start, u64 *end)
2721 struct page *pages[PTE_PREFETCH_NUM];
2722 struct kvm_memory_slot *slot;
2723 unsigned int access = sp->role.access;
2727 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2728 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2732 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2736 for (i = 0; i < ret; i++, gfn++, start++) {
2737 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2738 page_to_pfn(pages[i]), true, true);
2745 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2746 struct kvm_mmu_page *sp, u64 *sptep)
2748 u64 *spte, *start = NULL;
2751 WARN_ON(!sp->role.direct);
2753 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2756 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2757 if (is_shadow_present_pte(*spte) || spte == sptep) {
2760 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2768 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2770 struct kvm_mmu_page *sp;
2772 sp = sptep_to_sp(sptep);
2775 * Without accessed bits, there's no way to distinguish between
2776 * actually accessed translations and prefetched, so disable pte
2777 * prefetch if accessed bits aren't available.
2779 if (sp_ad_disabled(sp))
2782 if (sp->role.level > PG_LEVEL_4K)
2786 * If addresses are being invalidated, skip prefetching to avoid
2787 * accidentally prefetching those addresses.
2789 if (unlikely(vcpu->kvm->mmu_notifier_count))
2792 __direct_pte_prefetch(vcpu, sp, sptep);
2795 static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
2796 const struct kvm_memory_slot *slot)
2802 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2806 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2807 * is not solely for performance, it's also necessary to avoid the
2808 * "writable" check in __gfn_to_hva_many(), which will always fail on
2809 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2810 * page fault steps have already verified the guest isn't writing a
2811 * read-only memslot.
2813 hva = __gfn_to_hva_memslot(slot, gfn);
2815 pte = lookup_address_in_mm(kvm->mm, hva, &level);
2822 int kvm_mmu_max_mapping_level(struct kvm *kvm,
2823 const struct kvm_memory_slot *slot, gfn_t gfn,
2824 kvm_pfn_t pfn, int max_level)
2826 struct kvm_lpage_info *linfo;
2828 max_level = min(max_level, max_huge_page_level);
2829 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2830 linfo = lpage_info_slot(gfn, slot, max_level);
2831 if (!linfo->disallow_lpage)
2835 if (max_level == PG_LEVEL_4K)
2838 return host_pfn_mapping_level(kvm, gfn, pfn, slot);
2841 int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2842 int max_level, kvm_pfn_t *pfnp,
2843 bool huge_page_disallowed, int *req_level)
2845 struct kvm_memory_slot *slot;
2846 kvm_pfn_t pfn = *pfnp;
2850 *req_level = PG_LEVEL_4K;
2852 if (unlikely(max_level == PG_LEVEL_4K))
2855 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
2858 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2862 level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level);
2863 if (level == PG_LEVEL_4K)
2866 *req_level = level = min(level, max_level);
2869 * Enforce the iTLB multihit workaround after capturing the requested
2870 * level, which will be used to do precise, accurate accounting.
2872 if (huge_page_disallowed)
2876 * mmu_notifier_retry() was successful and mmu_lock is held, so
2877 * the pmd can't be split from under us.
2879 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2880 VM_BUG_ON((gfn & mask) != (pfn & mask));
2881 *pfnp = pfn & ~mask;
2886 void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2887 kvm_pfn_t *pfnp, int *goal_levelp)
2889 int level = *goal_levelp;
2891 if (cur_level == level && level > PG_LEVEL_4K &&
2892 is_shadow_present_pte(spte) &&
2893 !is_large_pte(spte)) {
2895 * A small SPTE exists for this pfn, but FNAME(fetch)
2896 * and __direct_map would like to create a large PTE
2897 * instead: just force them to go down another level,
2898 * patching back for them into pfn the next 9 bits of
2901 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2902 KVM_PAGES_PER_HPAGE(level - 1);
2903 *pfnp |= gfn & page_mask;
2908 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
2909 int map_writable, int max_level, kvm_pfn_t pfn,
2910 bool prefault, bool is_tdp)
2912 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2913 bool write = error_code & PFERR_WRITE_MASK;
2914 bool exec = error_code & PFERR_FETCH_MASK;
2915 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
2916 struct kvm_shadow_walk_iterator it;
2917 struct kvm_mmu_page *sp;
2918 int level, req_level, ret;
2919 gfn_t gfn = gpa >> PAGE_SHIFT;
2920 gfn_t base_gfn = gfn;
2922 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2923 huge_page_disallowed, &req_level);
2925 trace_kvm_mmu_spte_requested(gpa, level, pfn);
2926 for_each_shadow_entry(vcpu, gpa, it) {
2928 * We cannot overwrite existing page tables with an NX
2929 * large page, as the leaf could be executable.
2931 if (nx_huge_page_workaround_enabled)
2932 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
2935 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2936 if (it.level == level)
2939 drop_large_spte(vcpu, it.sptep);
2940 if (!is_shadow_present_pte(*it.sptep)) {
2941 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2942 it.level - 1, true, ACC_ALL);
2944 link_shadow_page(vcpu, it.sptep, sp);
2945 if (is_tdp && huge_page_disallowed &&
2946 req_level >= it.level)
2947 account_huge_nx_page(vcpu->kvm, sp);
2951 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2952 write, level, base_gfn, pfn, prefault,
2954 if (ret == RET_PF_SPURIOUS)
2957 direct_pte_prefetch(vcpu, it.sptep);
2958 ++vcpu->stat.pf_fixed;
2962 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2964 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2967 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2970 * Do not cache the mmio info caused by writing the readonly gfn
2971 * into the spte otherwise read access on readonly gfn also can
2972 * caused mmio page fault and treat it as mmio access.
2974 if (pfn == KVM_PFN_ERR_RO_FAULT)
2975 return RET_PF_EMULATE;
2977 if (pfn == KVM_PFN_ERR_HWPOISON) {
2978 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2979 return RET_PF_RETRY;
2985 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2986 kvm_pfn_t pfn, unsigned int access,
2989 /* The pfn is invalid, report the error! */
2990 if (unlikely(is_error_pfn(pfn))) {
2991 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2995 if (unlikely(is_noslot_pfn(pfn))) {
2996 vcpu_cache_mmio_info(vcpu, gva, gfn,
2997 access & shadow_mmio_access_mask);
2999 * If MMIO caching is disabled, emulate immediately without
3000 * touching the shadow page tables as attempting to install an
3001 * MMIO SPTE will just be an expensive nop.
3003 if (unlikely(!shadow_mmio_value)) {
3004 *ret_val = RET_PF_EMULATE;
3012 static bool page_fault_can_be_fast(u32 error_code)
3015 * Do not fix the mmio spte with invalid generation number which
3016 * need to be updated by slow page fault path.
3018 if (unlikely(error_code & PFERR_RSVD_MASK))
3021 /* See if the page fault is due to an NX violation */
3022 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3023 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3027 * #PF can be fast if:
3028 * 1. The shadow page table entry is not present, which could mean that
3029 * the fault is potentially caused by access tracking (if enabled).
3030 * 2. The shadow page table entry is present and the fault
3031 * is caused by write-protect, that means we just need change the W
3032 * bit of the spte which can be done out of mmu-lock.
3034 * However, if access tracking is disabled we know that a non-present
3035 * page must be a genuine page fault where we have to create a new SPTE.
3036 * So, if access tracking is disabled, we return true only for write
3037 * accesses to a present page.
3040 return shadow_acc_track_mask != 0 ||
3041 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3042 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3046 * Returns true if the SPTE was fixed successfully. Otherwise,
3047 * someone else modified the SPTE from its original value.
3050 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3051 u64 *sptep, u64 old_spte, u64 new_spte)
3055 WARN_ON(!sp->role.direct);
3058 * Theoretically we could also set dirty bit (and flush TLB) here in
3059 * order to eliminate unnecessary PML logging. See comments in
3060 * set_spte. But fast_page_fault is very unlikely to happen with PML
3061 * enabled, so we do not do this. This might result in the same GPA
3062 * to be logged in PML buffer again when the write really happens, and
3063 * eventually to be called by mark_page_dirty twice. But it's also no
3064 * harm. This also avoids the TLB flush needed after setting dirty bit
3065 * so non-PML cases won't be impacted.
3067 * Compare with set_spte where instead shadow_dirty_mask is set.
3069 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3072 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3074 * The gfn of direct spte is stable since it is
3075 * calculated by sp->gfn.
3077 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3078 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3084 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3086 if (fault_err_code & PFERR_FETCH_MASK)
3087 return is_executable_pte(spte);
3089 if (fault_err_code & PFERR_WRITE_MASK)
3090 return is_writable_pte(spte);
3092 /* Fault was on Read access */
3093 return spte & PT_PRESENT_MASK;
3097 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3099 static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3102 struct kvm_shadow_walk_iterator iterator;
3103 struct kvm_mmu_page *sp;
3104 int ret = RET_PF_INVALID;
3106 uint retry_count = 0;
3108 if (!page_fault_can_be_fast(error_code))
3111 walk_shadow_page_lockless_begin(vcpu);
3116 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3117 if (!is_shadow_present_pte(spte))
3120 if (!is_shadow_present_pte(spte))
3123 sp = sptep_to_sp(iterator.sptep);
3124 if (!is_last_spte(spte, sp->role.level))
3128 * Check whether the memory access that caused the fault would
3129 * still cause it if it were to be performed right now. If not,
3130 * then this is a spurious fault caused by TLB lazily flushed,
3131 * or some other CPU has already fixed the PTE after the
3132 * current CPU took the fault.
3134 * Need not check the access of upper level table entries since
3135 * they are always ACC_ALL.
3137 if (is_access_allowed(error_code, spte)) {
3138 ret = RET_PF_SPURIOUS;
3144 if (is_access_track_spte(spte))
3145 new_spte = restore_acc_track_spte(new_spte);
3148 * Currently, to simplify the code, write-protection can
3149 * be removed in the fast path only if the SPTE was
3150 * write-protected for dirty-logging or access tracking.
3152 if ((error_code & PFERR_WRITE_MASK) &&
3153 spte_can_locklessly_be_made_writable(spte)) {
3154 new_spte |= PT_WRITABLE_MASK;
3157 * Do not fix write-permission on the large spte. Since
3158 * we only dirty the first page into the dirty-bitmap in
3159 * fast_pf_fix_direct_spte(), other pages are missed
3160 * if its slot has dirty logging enabled.
3162 * Instead, we let the slow page fault path create a
3163 * normal spte to fix the access.
3165 * See the comments in kvm_arch_commit_memory_region().
3167 if (sp->role.level > PG_LEVEL_4K)
3171 /* Verify that the fault can be handled in the fast path */
3172 if (new_spte == spte ||
3173 !is_access_allowed(error_code, new_spte))
3177 * Currently, fast page fault only works for direct mapping
3178 * since the gfn is not stable for indirect shadow page. See
3179 * Documentation/virt/kvm/locking.rst to get more detail.
3181 if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte,
3187 if (++retry_count > 4) {
3188 printk_once(KERN_WARNING
3189 "kvm: Fast #PF retrying more than 4 times.\n");
3195 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3197 walk_shadow_page_lockless_end(vcpu);
3202 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3203 struct list_head *invalid_list)
3205 struct kvm_mmu_page *sp;
3207 if (!VALID_PAGE(*root_hpa))
3210 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3212 if (is_tdp_mmu_page(sp))
3213 kvm_tdp_mmu_put_root(kvm, sp, false);
3214 else if (!--sp->root_count && sp->role.invalid)
3215 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3217 *root_hpa = INVALID_PAGE;
3220 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3221 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3222 ulong roots_to_free)
3224 struct kvm *kvm = vcpu->kvm;
3226 LIST_HEAD(invalid_list);
3227 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3229 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3231 /* Before acquiring the MMU lock, see if we need to do any real work. */
3232 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3233 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3234 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3235 VALID_PAGE(mmu->prev_roots[i].hpa))
3238 if (i == KVM_MMU_NUM_PREV_ROOTS)
3242 write_lock(&kvm->mmu_lock);
3244 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3245 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3246 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3249 if (free_active_root) {
3250 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3251 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3252 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3253 } else if (mmu->pae_root) {
3254 for (i = 0; i < 4; ++i) {
3255 if (!IS_VALID_PAE_ROOT(mmu->pae_root[i]))
3258 mmu_free_root_page(kvm, &mmu->pae_root[i],
3260 mmu->pae_root[i] = INVALID_PAE_ROOT;
3263 mmu->root_hpa = INVALID_PAGE;
3267 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3268 write_unlock(&kvm->mmu_lock);
3270 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3272 void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3274 unsigned long roots_to_free = 0;
3279 * This should not be called while L2 is active, L2 can't invalidate
3280 * _only_ its own roots, e.g. INVVPID unconditionally exits.
3282 WARN_ON_ONCE(mmu->mmu_role.base.guest_mode);
3284 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3285 root_hpa = mmu->prev_roots[i].hpa;
3286 if (!VALID_PAGE(root_hpa))
3289 if (!to_shadow_page(root_hpa) ||
3290 to_shadow_page(root_hpa)->role.guest_mode)
3291 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
3294 kvm_mmu_free_roots(vcpu, mmu, roots_to_free);
3296 EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots);
3299 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3303 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3304 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3311 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3312 u8 level, bool direct)
3314 struct kvm_mmu_page *sp;
3316 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3319 return __pa(sp->spt);
3322 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3324 struct kvm_mmu *mmu = vcpu->arch.mmu;
3325 u8 shadow_root_level = mmu->shadow_root_level;
3330 write_lock(&vcpu->kvm->mmu_lock);
3331 r = make_mmu_pages_available(vcpu);
3335 if (is_tdp_mmu_enabled(vcpu->kvm)) {
3336 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3337 mmu->root_hpa = root;
3338 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3339 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true);
3340 mmu->root_hpa = root;
3341 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3342 if (WARN_ON_ONCE(!mmu->pae_root)) {
3347 for (i = 0; i < 4; ++i) {
3348 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3350 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3351 i << 30, PT32_ROOT_LEVEL, true);
3352 mmu->pae_root[i] = root | PT_PRESENT_MASK |
3355 mmu->root_hpa = __pa(mmu->pae_root);
3357 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level);
3362 /* root_pgd is ignored for direct MMUs. */
3365 write_unlock(&vcpu->kvm->mmu_lock);
3369 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3371 struct kvm_mmu *mmu = vcpu->arch.mmu;
3372 u64 pdptrs[4], pm_mask;
3373 gfn_t root_gfn, root_pgd;
3378 root_pgd = mmu->get_guest_pgd(vcpu);
3379 root_gfn = root_pgd >> PAGE_SHIFT;
3381 if (mmu_check_root(vcpu, root_gfn))
3385 * On SVM, reading PDPTRs might access guest memory, which might fault
3386 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3388 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3389 for (i = 0; i < 4; ++i) {
3390 pdptrs[i] = mmu->get_pdptr(vcpu, i);
3391 if (!(pdptrs[i] & PT_PRESENT_MASK))
3394 if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT))
3399 r = alloc_all_memslots_rmaps(vcpu->kvm);
3403 write_lock(&vcpu->kvm->mmu_lock);
3404 r = make_mmu_pages_available(vcpu);
3409 * Do we shadow a long mode page table? If so we need to
3410 * write-protect the guests page table root.
3412 if (mmu->root_level >= PT64_ROOT_4LEVEL) {
3413 root = mmu_alloc_root(vcpu, root_gfn, 0,
3414 mmu->shadow_root_level, false);
3415 mmu->root_hpa = root;
3419 if (WARN_ON_ONCE(!mmu->pae_root)) {
3425 * We shadow a 32 bit page table. This may be a legacy 2-level
3426 * or a PAE 3-level page table. In either case we need to be aware that
3427 * the shadow page table may be a PAE or a long mode page table.
3429 pm_mask = PT_PRESENT_MASK | shadow_me_mask;
3430 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3431 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3433 if (WARN_ON_ONCE(!mmu->pml4_root)) {
3438 mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask;
3441 for (i = 0; i < 4; ++i) {
3442 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3444 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3445 if (!(pdptrs[i] & PT_PRESENT_MASK)) {
3446 mmu->pae_root[i] = INVALID_PAE_ROOT;
3449 root_gfn = pdptrs[i] >> PAGE_SHIFT;
3452 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3453 PT32_ROOT_LEVEL, false);
3454 mmu->pae_root[i] = root | pm_mask;
3457 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3458 mmu->root_hpa = __pa(mmu->pml4_root);
3460 mmu->root_hpa = __pa(mmu->pae_root);
3463 mmu->root_pgd = root_pgd;
3465 write_unlock(&vcpu->kvm->mmu_lock);
3470 static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu)
3472 struct kvm_mmu *mmu = vcpu->arch.mmu;
3473 u64 *pml4_root, *pae_root;
3476 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3477 * tables are allocated and initialized at root creation as there is no
3478 * equivalent level in the guest's NPT to shadow. Allocate the tables
3479 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
3481 if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL ||
3482 mmu->shadow_root_level < PT64_ROOT_4LEVEL)
3486 * This mess only works with 4-level paging and needs to be updated to
3487 * work with 5-level paging.
3489 if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL))
3492 if (mmu->pae_root && mmu->pml4_root)
3496 * The special roots should always be allocated in concert. Yell and
3497 * bail if KVM ends up in a state where only one of the roots is valid.
3499 if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root))
3503 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3504 * doesn't need to be decrypted.
3506 pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3510 pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3512 free_page((unsigned long)pae_root);
3516 mmu->pae_root = pae_root;
3517 mmu->pml4_root = pml4_root;
3522 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3525 struct kvm_mmu_page *sp;
3527 if (vcpu->arch.mmu->direct_map)
3530 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3533 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3535 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3536 hpa_t root = vcpu->arch.mmu->root_hpa;
3537 sp = to_shadow_page(root);
3540 * Even if another CPU was marking the SP as unsync-ed
3541 * simultaneously, any guest page table changes are not
3542 * guaranteed to be visible anyway until this VCPU issues a TLB
3543 * flush strictly after those changes are made. We only need to
3544 * ensure that the other CPU sets these flags before any actual
3545 * changes to the page tables are made. The comments in
3546 * mmu_try_to_unsync_pages() describe what could go wrong if
3547 * this requirement isn't satisfied.
3549 if (!smp_load_acquire(&sp->unsync) &&
3550 !smp_load_acquire(&sp->unsync_children))
3553 write_lock(&vcpu->kvm->mmu_lock);
3554 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3556 mmu_sync_children(vcpu, sp);
3558 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3559 write_unlock(&vcpu->kvm->mmu_lock);
3563 write_lock(&vcpu->kvm->mmu_lock);
3564 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3566 for (i = 0; i < 4; ++i) {
3567 hpa_t root = vcpu->arch.mmu->pae_root[i];
3569 if (IS_VALID_PAE_ROOT(root)) {
3570 root &= PT64_BASE_ADDR_MASK;
3571 sp = to_shadow_page(root);
3572 mmu_sync_children(vcpu, sp);
3576 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3577 write_unlock(&vcpu->kvm->mmu_lock);
3580 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3581 u32 access, struct x86_exception *exception)
3584 exception->error_code = 0;
3588 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3590 struct x86_exception *exception)
3593 exception->error_code = 0;
3594 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3597 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3600 * A nested guest cannot use the MMIO cache if it is using nested
3601 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3603 if (mmu_is_nested(vcpu))
3607 return vcpu_match_mmio_gpa(vcpu, addr);
3609 return vcpu_match_mmio_gva(vcpu, addr);
3613 * Return the level of the lowest level SPTE added to sptes.
3614 * That SPTE may be non-present.
3616 static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
3618 struct kvm_shadow_walk_iterator iterator;
3622 walk_shadow_page_lockless_begin(vcpu);
3624 for (shadow_walk_init(&iterator, vcpu, addr),
3625 *root_level = iterator.level;
3626 shadow_walk_okay(&iterator);
3627 __shadow_walk_next(&iterator, spte)) {
3628 leaf = iterator.level;
3629 spte = mmu_spte_get_lockless(iterator.sptep);
3633 if (!is_shadow_present_pte(spte))
3637 walk_shadow_page_lockless_end(vcpu);
3642 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3643 static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3645 u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
3646 struct rsvd_bits_validate *rsvd_check;
3647 int root, leaf, level;
3648 bool reserved = false;
3650 if (is_tdp_mmu(vcpu->arch.mmu))
3651 leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
3653 leaf = get_walk(vcpu, addr, sptes, &root);
3655 if (unlikely(leaf < 0)) {
3660 *sptep = sptes[leaf];
3663 * Skip reserved bits checks on the terminal leaf if it's not a valid
3664 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3665 * design, always have reserved bits set. The purpose of the checks is
3666 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3668 if (!is_shadow_present_pte(sptes[leaf]))
3671 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3673 for (level = root; level >= leaf; level--)
3674 reserved |= is_rsvd_spte(rsvd_check, sptes[level], level);
3677 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
3679 for (level = root; level >= leaf; level--)
3680 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3681 sptes[level], level,
3682 get_rsvd_bits(rsvd_check, sptes[level], level));
3688 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3693 if (mmio_info_in_cache(vcpu, addr, direct))
3694 return RET_PF_EMULATE;
3696 reserved = get_mmio_spte(vcpu, addr, &spte);
3697 if (WARN_ON(reserved))
3700 if (is_mmio_spte(spte)) {
3701 gfn_t gfn = get_mmio_spte_gfn(spte);
3702 unsigned int access = get_mmio_spte_access(spte);
3704 if (!check_mmio_spte(vcpu, spte))
3705 return RET_PF_INVALID;
3710 trace_handle_mmio_page_fault(addr, gfn, access);
3711 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3712 return RET_PF_EMULATE;
3716 * If the page table is zapped by other cpus, let CPU fault again on
3719 return RET_PF_RETRY;
3722 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3723 u32 error_code, gfn_t gfn)
3725 if (unlikely(error_code & PFERR_RSVD_MASK))
3728 if (!(error_code & PFERR_PRESENT_MASK) ||
3729 !(error_code & PFERR_WRITE_MASK))
3733 * guest is writing the page which is write tracked which can
3734 * not be fixed by page fault handler.
3736 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3742 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3744 struct kvm_shadow_walk_iterator iterator;
3747 walk_shadow_page_lockless_begin(vcpu);
3748 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3749 clear_sp_write_flooding_count(iterator.sptep);
3750 if (!is_shadow_present_pte(spte))
3753 walk_shadow_page_lockless_end(vcpu);
3756 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3759 struct kvm_arch_async_pf arch;
3761 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3763 arch.direct_map = vcpu->arch.mmu->direct_map;
3764 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3766 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3767 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3770 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3771 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva,
3772 bool write, bool *writable)
3774 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3778 * Retry the page fault if the gfn hit a memslot that is being deleted
3779 * or moved. This ensures any existing SPTEs for the old memslot will
3780 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3782 if (slot && (slot->flags & KVM_MEMSLOT_INVALID))
3785 /* Don't expose private memslots to L2. */
3786 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3787 *pfn = KVM_PFN_NOSLOT;
3793 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async,
3794 write, writable, hva);
3796 return false; /* *pfn has correct page already */
3798 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3799 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
3800 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3801 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
3802 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3804 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
3808 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL,
3809 write, writable, hva);
3813 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3814 bool prefault, int max_level, bool is_tdp)
3816 bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu);
3817 bool write = error_code & PFERR_WRITE_MASK;
3820 gfn_t gfn = gpa >> PAGE_SHIFT;
3821 unsigned long mmu_seq;
3826 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3827 return RET_PF_EMULATE;
3829 if (!is_tdp_mmu_fault) {
3830 r = fast_page_fault(vcpu, gpa, error_code);
3831 if (r != RET_PF_INVALID)
3835 r = mmu_topup_memory_caches(vcpu, false);
3839 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3842 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, &hva,
3843 write, &map_writable))
3844 return RET_PF_RETRY;
3846 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
3851 if (is_tdp_mmu_fault)
3852 read_lock(&vcpu->kvm->mmu_lock);
3854 write_lock(&vcpu->kvm->mmu_lock);
3856 if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva))
3858 r = make_mmu_pages_available(vcpu);
3862 if (is_tdp_mmu_fault)
3863 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
3866 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
3870 if (is_tdp_mmu_fault)
3871 read_unlock(&vcpu->kvm->mmu_lock);
3873 write_unlock(&vcpu->kvm->mmu_lock);
3874 kvm_release_pfn_clean(pfn);
3878 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
3879 u32 error_code, bool prefault)
3881 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
3883 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3884 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3885 PG_LEVEL_2M, false);
3888 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3889 u64 fault_address, char *insn, int insn_len)
3892 u32 flags = vcpu->arch.apf.host_apf_flags;
3894 #ifndef CONFIG_X86_64
3895 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3896 if (WARN_ON_ONCE(fault_address >> 32))
3900 vcpu->arch.l1tf_flush_l1d = true;
3902 trace_kvm_page_fault(fault_address, error_code);
3904 if (kvm_event_needs_reinjection(vcpu))
3905 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3906 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3908 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
3909 vcpu->arch.apf.host_apf_flags = 0;
3910 local_irq_disable();
3911 kvm_async_pf_task_wait_schedule(fault_address);
3914 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
3919 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3921 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3926 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3927 max_level > PG_LEVEL_4K;
3929 int page_num = KVM_PAGES_PER_HPAGE(max_level);
3930 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
3932 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
3936 return direct_page_fault(vcpu, gpa, error_code, prefault,
3940 static void nonpaging_init_context(struct kvm_mmu *context)
3942 context->page_fault = nonpaging_page_fault;
3943 context->gva_to_gpa = nonpaging_gva_to_gpa;
3944 context->sync_page = nonpaging_sync_page;
3945 context->invlpg = NULL;
3946 context->direct_map = true;
3949 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
3950 union kvm_mmu_page_role role)
3952 return (role.direct || pgd == root->pgd) &&
3953 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
3954 role.word == to_shadow_page(root->hpa)->role.word;
3958 * Find out if a previously cached root matching the new pgd/role is available.
3959 * The current root is also inserted into the cache.
3960 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3962 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3963 * false is returned. This root should now be freed by the caller.
3965 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3966 union kvm_mmu_page_role new_role)
3969 struct kvm_mmu_root_info root;
3970 struct kvm_mmu *mmu = vcpu->arch.mmu;
3972 root.pgd = mmu->root_pgd;
3973 root.hpa = mmu->root_hpa;
3975 if (is_root_usable(&root, new_pgd, new_role))
3978 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3979 swap(root, mmu->prev_roots[i]);
3981 if (is_root_usable(&root, new_pgd, new_role))
3985 mmu->root_hpa = root.hpa;
3986 mmu->root_pgd = root.pgd;
3988 return i < KVM_MMU_NUM_PREV_ROOTS;
3991 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3992 union kvm_mmu_page_role new_role)
3994 struct kvm_mmu *mmu = vcpu->arch.mmu;
3997 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
3998 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
3999 * later if necessary.
4001 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4002 mmu->root_level >= PT64_ROOT_4LEVEL)
4003 return cached_root_available(vcpu, new_pgd, new_role);
4008 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4009 union kvm_mmu_page_role new_role)
4011 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
4012 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
4017 * It's possible that the cached previous root page is obsolete because
4018 * of a change in the MMU generation number. However, changing the
4019 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
4020 * free the root set here and allocate a new one.
4022 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
4024 if (force_flush_and_sync_on_reuse) {
4025 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4026 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
4030 * The last MMIO access's GVA and GPA are cached in the VCPU. When
4031 * switching to a new CR3, that GVA->GPA mapping may no longer be
4032 * valid. So clear any cached MMIO info even when we don't need to sync
4033 * the shadow page tables.
4035 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4038 * If this is a direct root page, it doesn't have a write flooding
4039 * count. Otherwise, clear the write flooding count.
4041 if (!new_role.direct)
4042 __clear_sp_write_flooding_count(
4043 to_shadow_page(vcpu->arch.mmu->root_hpa));
4046 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd)
4048 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu));
4050 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
4052 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4054 return kvm_read_cr3(vcpu);
4057 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4058 unsigned int access, int *nr_present)
4060 if (unlikely(is_mmio_spte(*sptep))) {
4061 if (gfn != get_mmio_spte_gfn(*sptep)) {
4062 mmu_spte_clear_no_track(sptep);
4067 mark_mmio_spte(vcpu, sptep, gfn, access);
4074 #define PTTYPE_EPT 18 /* arbitrary */
4075 #define PTTYPE PTTYPE_EPT
4076 #include "paging_tmpl.h"
4080 #include "paging_tmpl.h"
4084 #include "paging_tmpl.h"
4088 __reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check,
4089 u64 pa_bits_rsvd, int level, bool nx, bool gbpages,
4092 u64 gbpages_bit_rsvd = 0;
4093 u64 nonleaf_bit8_rsvd = 0;
4096 rsvd_check->bad_mt_xwr = 0;
4099 gbpages_bit_rsvd = rsvd_bits(7, 7);
4101 if (level == PT32E_ROOT_LEVEL)
4102 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62);
4104 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4106 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4108 high_bits_rsvd |= rsvd_bits(63, 63);
4111 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4112 * leaf entries) on AMD CPUs only.
4115 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4118 case PT32_ROOT_LEVEL:
4119 /* no rsvd bits for 2 level 4K page table entries */
4120 rsvd_check->rsvd_bits_mask[0][1] = 0;
4121 rsvd_check->rsvd_bits_mask[0][0] = 0;
4122 rsvd_check->rsvd_bits_mask[1][0] =
4123 rsvd_check->rsvd_bits_mask[0][0];
4126 rsvd_check->rsvd_bits_mask[1][1] = 0;
4130 if (is_cpuid_PSE36())
4131 /* 36bits PSE 4MB page */
4132 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4134 /* 32 bits PSE 4MB page */
4135 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4137 case PT32E_ROOT_LEVEL:
4138 rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
4141 rsvd_bits(1, 2); /* PDPTE */
4142 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
4143 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
4144 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4145 rsvd_bits(13, 20); /* large page */
4146 rsvd_check->rsvd_bits_mask[1][0] =
4147 rsvd_check->rsvd_bits_mask[0][0];
4149 case PT64_ROOT_5LEVEL:
4150 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd |
4153 rsvd_check->rsvd_bits_mask[1][4] =
4154 rsvd_check->rsvd_bits_mask[0][4];
4156 case PT64_ROOT_4LEVEL:
4157 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd |
4160 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd |
4162 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd;
4163 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4164 rsvd_check->rsvd_bits_mask[1][3] =
4165 rsvd_check->rsvd_bits_mask[0][3];
4166 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd |
4169 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4170 rsvd_bits(13, 20); /* large page */
4171 rsvd_check->rsvd_bits_mask[1][0] =
4172 rsvd_check->rsvd_bits_mask[0][0];
4177 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4178 struct kvm_mmu *context)
4180 __reset_rsvds_bits_mask(&context->guest_rsvd_check,
4181 vcpu->arch.reserved_gpa_bits,
4182 context->root_level, is_efer_nx(context),
4183 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4184 is_cr4_pse(context),
4185 guest_cpuid_is_amd_or_hygon(vcpu));
4189 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4190 u64 pa_bits_rsvd, bool execonly)
4192 u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4195 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
4196 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
4197 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6);
4198 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6);
4199 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4202 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4203 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4204 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29);
4205 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20);
4206 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4208 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4209 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4210 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4211 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4212 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4214 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4215 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4217 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4220 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4221 struct kvm_mmu *context, bool execonly)
4223 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4224 vcpu->arch.reserved_gpa_bits, execonly);
4227 static inline u64 reserved_hpa_bits(void)
4229 return rsvd_bits(shadow_phys_bits, 63);
4233 * the page table on host is the shadow page table for the page
4234 * table in guest or amd nested guest, its mmu features completely
4235 * follow the features in guest.
4237 static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4238 struct kvm_mmu *context)
4241 * KVM uses NX when TDP is disabled to handle a variety of scenarios,
4242 * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
4243 * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
4244 * The iTLB multi-hit workaround can be toggled at any time, so assume
4245 * NX can be used by any non-nested shadow MMU to avoid having to reset
4246 * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
4248 bool uses_nx = is_efer_nx(context) || !tdp_enabled;
4250 /* @amd adds a check on bit of SPTEs, which KVM shouldn't use anyways. */
4252 /* KVM doesn't use 2-level page tables for the shadow MMU. */
4253 bool is_pse = false;
4254 struct rsvd_bits_validate *shadow_zero_check;
4257 WARN_ON_ONCE(context->shadow_root_level < PT32E_ROOT_LEVEL);
4259 shadow_zero_check = &context->shadow_zero_check;
4260 __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
4261 context->shadow_root_level, uses_nx,
4262 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4265 if (!shadow_me_mask)
4268 for (i = context->shadow_root_level; --i >= 0;) {
4269 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4270 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4275 static inline bool boot_cpu_is_amd(void)
4277 WARN_ON_ONCE(!tdp_enabled);
4278 return shadow_x_mask == 0;
4282 * the direct page table on host, use as much mmu features as
4283 * possible, however, kvm currently does not do execution-protection.
4286 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4287 struct kvm_mmu *context)
4289 struct rsvd_bits_validate *shadow_zero_check;
4292 shadow_zero_check = &context->shadow_zero_check;
4294 if (boot_cpu_is_amd())
4295 __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
4296 context->shadow_root_level, false,
4297 boot_cpu_has(X86_FEATURE_GBPAGES),
4300 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4301 reserved_hpa_bits(), false);
4303 if (!shadow_me_mask)
4306 for (i = context->shadow_root_level; --i >= 0;) {
4307 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4308 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4313 * as the comments in reset_shadow_zero_bits_mask() except it
4314 * is the shadow page table for intel nested guest.
4317 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4318 struct kvm_mmu *context, bool execonly)
4320 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4321 reserved_hpa_bits(), execonly);
4324 #define BYTE_MASK(access) \
4325 ((1 & (access) ? 2 : 0) | \
4326 (2 & (access) ? 4 : 0) | \
4327 (3 & (access) ? 8 : 0) | \
4328 (4 & (access) ? 16 : 0) | \
4329 (5 & (access) ? 32 : 0) | \
4330 (6 & (access) ? 64 : 0) | \
4331 (7 & (access) ? 128 : 0))
4334 static void update_permission_bitmask(struct kvm_mmu *mmu, bool ept)
4338 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4339 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4340 const u8 u = BYTE_MASK(ACC_USER_MASK);
4342 bool cr4_smep = is_cr4_smep(mmu);
4343 bool cr4_smap = is_cr4_smap(mmu);
4344 bool cr0_wp = is_cr0_wp(mmu);
4345 bool efer_nx = is_efer_nx(mmu);
4347 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4348 unsigned pfec = byte << 1;
4351 * Each "*f" variable has a 1 bit for each UWX value
4352 * that causes a fault with the given PFEC.
4355 /* Faults from writes to non-writable pages */
4356 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4357 /* Faults from user mode accesses to supervisor pages */
4358 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4359 /* Faults from fetches of non-executable pages*/
4360 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4361 /* Faults from kernel mode fetches of user pages */
4363 /* Faults from kernel mode accesses of user pages */
4367 /* Faults from kernel mode accesses to user pages */
4368 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4370 /* Not really needed: !nx will cause pte.nx to fault */
4374 /* Allow supervisor writes if !cr0.wp */
4376 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4378 /* Disallow supervisor fetches of user code if cr4.smep */
4380 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4383 * SMAP:kernel-mode data accesses from user-mode
4384 * mappings should fault. A fault is considered
4385 * as a SMAP violation if all of the following
4386 * conditions are true:
4387 * - X86_CR4_SMAP is set in CR4
4388 * - A user page is accessed
4389 * - The access is not a fetch
4390 * - Page fault in kernel mode
4391 * - if CPL = 3 or X86_EFLAGS_AC is clear
4393 * Here, we cover the first three conditions.
4394 * The fourth is computed dynamically in permission_fault();
4395 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4396 * *not* subject to SMAP restrictions.
4399 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4402 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4407 * PKU is an additional mechanism by which the paging controls access to
4408 * user-mode addresses based on the value in the PKRU register. Protection
4409 * key violations are reported through a bit in the page fault error code.
4410 * Unlike other bits of the error code, the PK bit is not known at the
4411 * call site of e.g. gva_to_gpa; it must be computed directly in
4412 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4413 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4415 * In particular the following conditions come from the error code, the
4416 * page tables and the machine state:
4417 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4418 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4419 * - PK is always zero if U=0 in the page tables
4420 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4422 * The PKRU bitmask caches the result of these four conditions. The error
4423 * code (minus the P bit) and the page table's U bit form an index into the
4424 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4425 * with the two bits of the PKRU register corresponding to the protection key.
4426 * For the first three conditions above the bits will be 00, thus masking
4427 * away both AD and WD. For all reads or if the last condition holds, WD
4428 * only will be masked away.
4430 static void update_pkru_bitmask(struct kvm_mmu *mmu)
4435 if (!is_cr4_pke(mmu)) {
4440 wp = is_cr0_wp(mmu);
4442 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4443 unsigned pfec, pkey_bits;
4444 bool check_pkey, check_write, ff, uf, wf, pte_user;
4447 ff = pfec & PFERR_FETCH_MASK;
4448 uf = pfec & PFERR_USER_MASK;
4449 wf = pfec & PFERR_WRITE_MASK;
4451 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4452 pte_user = pfec & PFERR_RSVD_MASK;
4455 * Only need to check the access which is not an
4456 * instruction fetch and is to a user page.
4458 check_pkey = (!ff && pte_user);
4460 * write access is controlled by PKRU if it is a
4461 * user access or CR0.WP = 1.
4463 check_write = check_pkey && wf && (uf || wp);
4465 /* PKRU.AD stops both read and write access. */
4466 pkey_bits = !!check_pkey;
4467 /* PKRU.WD stops write access. */
4468 pkey_bits |= (!!check_write) << 1;
4470 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4474 static void reset_guest_paging_metadata(struct kvm_vcpu *vcpu,
4475 struct kvm_mmu *mmu)
4477 if (!is_cr0_pg(mmu))
4480 reset_rsvds_bits_mask(vcpu, mmu);
4481 update_permission_bitmask(mmu, false);
4482 update_pkru_bitmask(mmu);
4485 static void paging64_init_context(struct kvm_mmu *context)
4487 context->page_fault = paging64_page_fault;
4488 context->gva_to_gpa = paging64_gva_to_gpa;
4489 context->sync_page = paging64_sync_page;
4490 context->invlpg = paging64_invlpg;
4491 context->direct_map = false;
4494 static void paging32_init_context(struct kvm_mmu *context)
4496 context->page_fault = paging32_page_fault;
4497 context->gva_to_gpa = paging32_gva_to_gpa;
4498 context->sync_page = paging32_sync_page;
4499 context->invlpg = paging32_invlpg;
4500 context->direct_map = false;
4503 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu,
4504 struct kvm_mmu_role_regs *regs)
4506 union kvm_mmu_extended_role ext = {0};
4508 if (____is_cr0_pg(regs)) {
4510 ext.cr4_pae = ____is_cr4_pae(regs);
4511 ext.cr4_smep = ____is_cr4_smep(regs);
4512 ext.cr4_smap = ____is_cr4_smap(regs);
4513 ext.cr4_pse = ____is_cr4_pse(regs);
4515 /* PKEY and LA57 are active iff long mode is active. */
4516 ext.cr4_pke = ____is_efer_lma(regs) && ____is_cr4_pke(regs);
4517 ext.cr4_la57 = ____is_efer_lma(regs) && ____is_cr4_la57(regs);
4525 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4526 struct kvm_mmu_role_regs *regs,
4529 union kvm_mmu_role role = {0};
4531 role.base.access = ACC_ALL;
4532 if (____is_cr0_pg(regs)) {
4533 role.base.efer_nx = ____is_efer_nx(regs);
4534 role.base.cr0_wp = ____is_cr0_wp(regs);
4536 role.base.smm = is_smm(vcpu);
4537 role.base.guest_mode = is_guest_mode(vcpu);
4542 role.ext = kvm_calc_mmu_role_ext(vcpu, regs);
4547 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4549 /* Use 5-level TDP if and only if it's useful/necessary. */
4550 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4553 return max_tdp_level;
4556 static union kvm_mmu_role
4557 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu,
4558 struct kvm_mmu_role_regs *regs, bool base_only)
4560 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
4562 role.base.ad_disabled = (shadow_accessed_mask == 0);
4563 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4564 role.base.direct = true;
4565 role.base.gpte_is_8_bytes = true;
4570 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4572 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4573 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4574 union kvm_mmu_role new_role =
4575 kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, false);
4577 if (new_role.as_u64 == context->mmu_role.as_u64)
4580 context->mmu_role.as_u64 = new_role.as_u64;
4581 context->page_fault = kvm_tdp_page_fault;
4582 context->sync_page = nonpaging_sync_page;
4583 context->invlpg = NULL;
4584 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4585 context->direct_map = true;
4586 context->get_guest_pgd = get_cr3;
4587 context->get_pdptr = kvm_pdptr_read;
4588 context->inject_page_fault = kvm_inject_page_fault;
4589 context->root_level = role_regs_to_root_level(®s);
4591 if (!is_cr0_pg(context))
4592 context->gva_to_gpa = nonpaging_gva_to_gpa;
4593 else if (is_cr4_pae(context))
4594 context->gva_to_gpa = paging64_gva_to_gpa;
4596 context->gva_to_gpa = paging32_gva_to_gpa;
4598 reset_guest_paging_metadata(vcpu, context);
4599 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4602 static union kvm_mmu_role
4603 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu,
4604 struct kvm_mmu_role_regs *regs, bool base_only)
4606 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
4608 role.base.smep_andnot_wp = role.ext.cr4_smep && !____is_cr0_wp(regs);
4609 role.base.smap_andnot_wp = role.ext.cr4_smap && !____is_cr0_wp(regs);
4610 role.base.gpte_is_8_bytes = ____is_cr0_pg(regs) && ____is_cr4_pae(regs);
4615 static union kvm_mmu_role
4616 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu,
4617 struct kvm_mmu_role_regs *regs, bool base_only)
4619 union kvm_mmu_role role =
4620 kvm_calc_shadow_root_page_role_common(vcpu, regs, base_only);
4622 role.base.direct = !____is_cr0_pg(regs);
4624 if (!____is_efer_lma(regs))
4625 role.base.level = PT32E_ROOT_LEVEL;
4626 else if (____is_cr4_la57(regs))
4627 role.base.level = PT64_ROOT_5LEVEL;
4629 role.base.level = PT64_ROOT_4LEVEL;
4634 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4635 struct kvm_mmu_role_regs *regs,
4636 union kvm_mmu_role new_role)
4638 if (new_role.as_u64 == context->mmu_role.as_u64)
4641 context->mmu_role.as_u64 = new_role.as_u64;
4643 if (!is_cr0_pg(context))
4644 nonpaging_init_context(context);
4645 else if (is_cr4_pae(context))
4646 paging64_init_context(context);
4648 paging32_init_context(context);
4649 context->root_level = role_regs_to_root_level(regs);
4651 reset_guest_paging_metadata(vcpu, context);
4652 context->shadow_root_level = new_role.base.level;
4654 reset_shadow_zero_bits_mask(vcpu, context);
4657 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu,
4658 struct kvm_mmu_role_regs *regs)
4660 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4661 union kvm_mmu_role new_role =
4662 kvm_calc_shadow_mmu_root_page_role(vcpu, regs, false);
4664 shadow_mmu_init_context(vcpu, context, regs, new_role);
4667 static union kvm_mmu_role
4668 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu,
4669 struct kvm_mmu_role_regs *regs)
4671 union kvm_mmu_role role =
4672 kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
4674 role.base.direct = false;
4675 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4680 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
4681 unsigned long cr4, u64 efer, gpa_t nested_cr3)
4683 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4684 struct kvm_mmu_role_regs regs = {
4689 union kvm_mmu_role new_role;
4691 new_role = kvm_calc_shadow_npt_root_page_role(vcpu, ®s);
4693 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base);
4695 shadow_mmu_init_context(vcpu, context, ®s, new_role);
4698 * Redo the shadow bits, the reset done by shadow_mmu_init_context()
4699 * (above) may use the wrong shadow_root_level.
4701 reset_shadow_zero_bits_mask(vcpu, context);
4703 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4705 static union kvm_mmu_role
4706 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4707 bool execonly, u8 level)
4709 union kvm_mmu_role role = {0};
4711 /* SMM flag is inherited from root_mmu */
4712 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4714 role.base.level = level;
4715 role.base.gpte_is_8_bytes = true;
4716 role.base.direct = false;
4717 role.base.ad_disabled = !accessed_dirty;
4718 role.base.guest_mode = true;
4719 role.base.access = ACC_ALL;
4721 /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */
4723 role.ext.execonly = execonly;
4729 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4730 bool accessed_dirty, gpa_t new_eptp)
4732 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4733 u8 level = vmx_eptp_page_walk_level(new_eptp);
4734 union kvm_mmu_role new_role =
4735 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4738 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base);
4740 if (new_role.as_u64 == context->mmu_role.as_u64)
4743 context->mmu_role.as_u64 = new_role.as_u64;
4745 context->shadow_root_level = level;
4747 context->ept_ad = accessed_dirty;
4748 context->page_fault = ept_page_fault;
4749 context->gva_to_gpa = ept_gva_to_gpa;
4750 context->sync_page = ept_sync_page;
4751 context->invlpg = ept_invlpg;
4752 context->root_level = level;
4753 context->direct_map = false;
4755 update_permission_bitmask(context, true);
4756 update_pkru_bitmask(context);
4757 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4758 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4760 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4762 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4764 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4765 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4767 kvm_init_shadow_mmu(vcpu, ®s);
4769 context->get_guest_pgd = get_cr3;
4770 context->get_pdptr = kvm_pdptr_read;
4771 context->inject_page_fault = kvm_inject_page_fault;
4774 static union kvm_mmu_role
4775 kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu, struct kvm_mmu_role_regs *regs)
4777 union kvm_mmu_role role;
4779 role = kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
4782 * Nested MMUs are used only for walking L2's gva->gpa, they never have
4783 * shadow pages of their own and so "direct" has no meaning. Set it
4784 * to "true" to try to detect bogus usage of the nested MMU.
4786 role.base.direct = true;
4787 role.base.level = role_regs_to_root_level(regs);
4791 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4793 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4794 union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu, ®s);
4795 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4797 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4800 g_context->mmu_role.as_u64 = new_role.as_u64;
4801 g_context->get_guest_pgd = get_cr3;
4802 g_context->get_pdptr = kvm_pdptr_read;
4803 g_context->inject_page_fault = kvm_inject_page_fault;
4804 g_context->root_level = new_role.base.level;
4807 * L2 page tables are never shadowed, so there is no need to sync
4810 g_context->invlpg = NULL;
4813 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4814 * L1's nested page tables (e.g. EPT12). The nested translation
4815 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4816 * L2's page tables as the first level of translation and L1's
4817 * nested page tables as the second level of translation. Basically
4818 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4820 if (!is_paging(vcpu))
4821 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4822 else if (is_long_mode(vcpu))
4823 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4824 else if (is_pae(vcpu))
4825 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4827 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4829 reset_guest_paging_metadata(vcpu, g_context);
4832 void kvm_init_mmu(struct kvm_vcpu *vcpu)
4834 if (mmu_is_nested(vcpu))
4835 init_kvm_nested_mmu(vcpu);
4836 else if (tdp_enabled)
4837 init_kvm_tdp_mmu(vcpu);
4839 init_kvm_softmmu(vcpu);
4841 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4843 static union kvm_mmu_page_role
4844 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4846 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4847 union kvm_mmu_role role;
4850 role = kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, true);
4852 role = kvm_calc_shadow_mmu_root_page_role(vcpu, ®s, true);
4857 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu)
4860 * Invalidate all MMU roles to force them to reinitialize as CPUID
4861 * information is factored into reserved bit calculations.
4863 vcpu->arch.root_mmu.mmu_role.ext.valid = 0;
4864 vcpu->arch.guest_mmu.mmu_role.ext.valid = 0;
4865 vcpu->arch.nested_mmu.mmu_role.ext.valid = 0;
4866 kvm_mmu_reset_context(vcpu);
4869 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
4870 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
4871 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
4872 * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise
4873 * sweep the problem under the rug.
4875 * KVM's horrific CPUID ABI makes the problem all but impossible to
4876 * solve, as correctly handling multiple vCPU models (with respect to
4877 * paging and physical address properties) in a single VM would require
4878 * tracking all relevant CPUID information in kvm_mmu_page_role. That
4879 * is very undesirable as it would double the memory requirements for
4880 * gfn_track (see struct kvm_mmu_page_role comments), and in practice
4881 * no sane VMM mucks with the core vCPU model on the fly.
4883 if (vcpu->arch.last_vmentry_cpu != -1) {
4884 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n");
4885 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n");
4889 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4891 kvm_mmu_unload(vcpu);
4894 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4896 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4900 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
4903 r = mmu_alloc_special_roots(vcpu);
4906 if (vcpu->arch.mmu->direct_map)
4907 r = mmu_alloc_direct_roots(vcpu);
4909 r = mmu_alloc_shadow_roots(vcpu);
4913 kvm_mmu_sync_roots(vcpu);
4915 kvm_mmu_load_pgd(vcpu);
4916 static_call(kvm_x86_tlb_flush_current)(vcpu);
4921 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4923 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
4924 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
4925 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4926 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
4929 static bool need_remote_flush(u64 old, u64 new)
4931 if (!is_shadow_present_pte(old))
4933 if (!is_shadow_present_pte(new))
4935 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4937 old ^= shadow_nx_mask;
4938 new ^= shadow_nx_mask;
4939 return (old & ~new & PT64_PERM_MASK) != 0;
4942 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4949 * Assume that the pte write on a page table of the same type
4950 * as the current vcpu paging mode since we update the sptes only
4951 * when they have the same mode.
4953 if (is_pae(vcpu) && *bytes == 4) {
4954 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4959 if (*bytes == 4 || *bytes == 8) {
4960 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
4969 * If we're seeing too many writes to a page, it may no longer be a page table,
4970 * or we may be forking, in which case it is better to unmap the page.
4972 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4975 * Skip write-flooding detected for the sp whose level is 1, because
4976 * it can become unsync, then the guest page is not write-protected.
4978 if (sp->role.level == PG_LEVEL_4K)
4981 atomic_inc(&sp->write_flooding_count);
4982 return atomic_read(&sp->write_flooding_count) >= 3;
4986 * Misaligned accesses are too much trouble to fix up; also, they usually
4987 * indicate a page is not used as a page table.
4989 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4992 unsigned offset, pte_size, misaligned;
4994 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4995 gpa, bytes, sp->role.word);
4997 offset = offset_in_page(gpa);
4998 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5001 * Sometimes, the OS only writes the last one bytes to update status
5002 * bits, for example, in linux, andb instruction is used in clear_bit().
5004 if (!(offset & (pte_size - 1)) && bytes == 1)
5007 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5008 misaligned |= bytes < 4;
5013 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5015 unsigned page_offset, quadrant;
5019 page_offset = offset_in_page(gpa);
5020 level = sp->role.level;
5022 if (!sp->role.gpte_is_8_bytes) {
5023 page_offset <<= 1; /* 32->64 */
5025 * A 32-bit pde maps 4MB while the shadow pdes map
5026 * only 2MB. So we need to double the offset again
5027 * and zap two pdes instead of one.
5029 if (level == PT32_ROOT_LEVEL) {
5030 page_offset &= ~7; /* kill rounding error */
5034 quadrant = page_offset >> PAGE_SHIFT;
5035 page_offset &= ~PAGE_MASK;
5036 if (quadrant != sp->role.quadrant)
5040 spte = &sp->spt[page_offset / sizeof(*spte)];
5044 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5045 const u8 *new, int bytes,
5046 struct kvm_page_track_notifier_node *node)
5048 gfn_t gfn = gpa >> PAGE_SHIFT;
5049 struct kvm_mmu_page *sp;
5050 LIST_HEAD(invalid_list);
5051 u64 entry, gentry, *spte;
5053 bool remote_flush, local_flush;
5056 * If we don't have indirect shadow pages, it means no page is
5057 * write-protected, so we can exit simply.
5059 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5062 remote_flush = local_flush = false;
5064 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5067 * No need to care whether allocation memory is successful
5068 * or not since pte prefetch is skipped if it does not have
5069 * enough objects in the cache.
5071 mmu_topup_memory_caches(vcpu, true);
5073 write_lock(&vcpu->kvm->mmu_lock);
5075 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5077 ++vcpu->kvm->stat.mmu_pte_write;
5078 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5080 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5081 if (detect_write_misaligned(sp, gpa, bytes) ||
5082 detect_write_flooding(sp)) {
5083 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5084 ++vcpu->kvm->stat.mmu_flooded;
5088 spte = get_written_sptes(sp, gpa, &npte);
5095 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
5096 if (gentry && sp->role.level != PG_LEVEL_4K)
5097 ++vcpu->kvm->stat.mmu_pde_zapped;
5098 if (need_remote_flush(entry, *spte))
5099 remote_flush = true;
5103 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5104 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5105 write_unlock(&vcpu->kvm->mmu_lock);
5108 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5109 void *insn, int insn_len)
5111 int r, emulation_type = EMULTYPE_PF;
5112 bool direct = vcpu->arch.mmu->direct_map;
5114 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5115 return RET_PF_RETRY;
5118 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5119 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5120 if (r == RET_PF_EMULATE)
5124 if (r == RET_PF_INVALID) {
5125 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5126 lower_32_bits(error_code), false);
5127 if (WARN_ON_ONCE(r == RET_PF_INVALID))
5133 if (r != RET_PF_EMULATE)
5137 * Before emulating the instruction, check if the error code
5138 * was due to a RO violation while translating the guest page.
5139 * This can occur when using nested virtualization with nested
5140 * paging in both guests. If true, we simply unprotect the page
5141 * and resume the guest.
5143 if (vcpu->arch.mmu->direct_map &&
5144 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5145 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5150 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5151 * optimistically try to just unprotect the page and let the processor
5152 * re-execute the instruction that caused the page fault. Do not allow
5153 * retrying MMIO emulation, as it's not only pointless but could also
5154 * cause us to enter an infinite loop because the processor will keep
5155 * faulting on the non-existent MMIO address. Retrying an instruction
5156 * from a nested guest is also pointless and dangerous as we are only
5157 * explicitly shadowing L1's page tables, i.e. unprotecting something
5158 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5160 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5161 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5163 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5166 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5168 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5169 gva_t gva, hpa_t root_hpa)
5173 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5174 if (mmu != &vcpu->arch.guest_mmu) {
5175 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5176 if (is_noncanonical_address(gva, vcpu))
5179 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5185 if (root_hpa == INVALID_PAGE) {
5186 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5189 * INVLPG is required to invalidate any global mappings for the VA,
5190 * irrespective of PCID. Since it would take us roughly similar amount
5191 * of work to determine whether any of the prev_root mappings of the VA
5192 * is marked global, or to just sync it blindly, so we might as well
5193 * just always sync it.
5195 * Mappings not reachable via the current cr3 or the prev_roots will be
5196 * synced when switching to that cr3, so nothing needs to be done here
5199 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5200 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5201 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5203 mmu->invlpg(vcpu, gva, root_hpa);
5207 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5209 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
5210 ++vcpu->stat.invlpg;
5212 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5215 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5217 struct kvm_mmu *mmu = vcpu->arch.mmu;
5218 bool tlb_flush = false;
5221 if (pcid == kvm_get_active_pcid(vcpu)) {
5222 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5226 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5227 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5228 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5229 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5235 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5237 ++vcpu->stat.invlpg;
5240 * Mappings not reachable via the current cr3 or the prev_roots will be
5241 * synced when switching to that cr3, so nothing needs to be done here
5246 void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
5247 int tdp_huge_page_level)
5249 tdp_enabled = enable_tdp;
5250 max_tdp_level = tdp_max_root_level;
5253 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5254 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5255 * the kernel is not. But, KVM never creates a page size greater than
5256 * what is used by the kernel for any given HVA, i.e. the kernel's
5257 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5260 max_huge_page_level = tdp_huge_page_level;
5261 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5262 max_huge_page_level = PG_LEVEL_1G;
5264 max_huge_page_level = PG_LEVEL_2M;
5266 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5268 /* The return value indicates if tlb flush on all vcpus is needed. */
5269 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head,
5270 struct kvm_memory_slot *slot);
5272 /* The caller should hold mmu-lock before calling this function. */
5273 static __always_inline bool
5274 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5275 slot_level_handler fn, int start_level, int end_level,
5276 gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield,
5279 struct slot_rmap_walk_iterator iterator;
5281 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5282 end_gfn, &iterator) {
5284 flush |= fn(kvm, iterator.rmap, memslot);
5286 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
5287 if (flush && flush_on_yield) {
5288 kvm_flush_remote_tlbs_with_address(kvm,
5290 iterator.gfn - start_gfn + 1);
5293 cond_resched_rwlock_write(&kvm->mmu_lock);
5300 static __always_inline bool
5301 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5302 slot_level_handler fn, int start_level, int end_level,
5303 bool flush_on_yield)
5305 return slot_handle_level_range(kvm, memslot, fn, start_level,
5306 end_level, memslot->base_gfn,
5307 memslot->base_gfn + memslot->npages - 1,
5308 flush_on_yield, false);
5311 static __always_inline bool
5312 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5313 slot_level_handler fn, bool flush_on_yield)
5315 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5316 PG_LEVEL_4K, flush_on_yield);
5319 static void free_mmu_pages(struct kvm_mmu *mmu)
5321 if (!tdp_enabled && mmu->pae_root)
5322 set_memory_encrypted((unsigned long)mmu->pae_root, 1);
5323 free_page((unsigned long)mmu->pae_root);
5324 free_page((unsigned long)mmu->pml4_root);
5327 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5332 mmu->root_hpa = INVALID_PAGE;
5334 mmu->translate_gpa = translate_gpa;
5335 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5336 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5339 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5340 * while the PDP table is a per-vCPU construct that's allocated at MMU
5341 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5342 * x86_64. Therefore we need to allocate the PDP table in the first
5343 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5344 * generally doesn't use PAE paging and can skip allocating the PDP
5345 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5346 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5347 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
5349 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5352 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5356 mmu->pae_root = page_address(page);
5359 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5360 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5361 * that KVM's writes and the CPU's reads get along. Note, this is
5362 * only necessary when using shadow paging, as 64-bit NPT can get at
5363 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5364 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5367 set_memory_decrypted((unsigned long)mmu->pae_root, 1);
5369 WARN_ON_ONCE(shadow_me_mask);
5371 for (i = 0; i < 4; ++i)
5372 mmu->pae_root[i] = INVALID_PAE_ROOT;
5377 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5381 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5382 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5384 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5385 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5387 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5389 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5390 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5392 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5394 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5398 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5400 goto fail_allocate_root;
5404 free_mmu_pages(&vcpu->arch.guest_mmu);
5408 #define BATCH_ZAP_PAGES 10
5409 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5411 struct kvm_mmu_page *sp, *node;
5412 int nr_zapped, batch = 0;
5415 list_for_each_entry_safe_reverse(sp, node,
5416 &kvm->arch.active_mmu_pages, link) {
5418 * No obsolete valid page exists before a newly created page
5419 * since active_mmu_pages is a FIFO list.
5421 if (!is_obsolete_sp(kvm, sp))
5425 * Invalid pages should never land back on the list of active
5426 * pages. Skip the bogus page, otherwise we'll get stuck in an
5427 * infinite loop if the page gets put back on the list (again).
5429 if (WARN_ON(sp->role.invalid))
5433 * No need to flush the TLB since we're only zapping shadow
5434 * pages with an obsolete generation number and all vCPUS have
5435 * loaded a new root, i.e. the shadow pages being zapped cannot
5436 * be in active use by the guest.
5438 if (batch >= BATCH_ZAP_PAGES &&
5439 cond_resched_rwlock_write(&kvm->mmu_lock)) {
5444 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5445 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5452 * Trigger a remote TLB flush before freeing the page tables to ensure
5453 * KVM is not in the middle of a lockless shadow page table walk, which
5454 * may reference the pages.
5456 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5460 * Fast invalidate all shadow pages and use lock-break technique
5461 * to zap obsolete pages.
5463 * It's required when memslot is being deleted or VM is being
5464 * destroyed, in these cases, we should ensure that KVM MMU does
5465 * not use any resource of the being-deleted slot or all slots
5466 * after calling the function.
5468 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5470 lockdep_assert_held(&kvm->slots_lock);
5472 write_lock(&kvm->mmu_lock);
5473 trace_kvm_mmu_zap_all_fast(kvm);
5476 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5477 * held for the entire duration of zapping obsolete pages, it's
5478 * impossible for there to be multiple invalid generations associated
5479 * with *valid* shadow pages at any given time, i.e. there is exactly
5480 * one valid generation and (at most) one invalid generation.
5482 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5484 /* In order to ensure all threads see this change when
5485 * handling the MMU reload signal, this must happen in the
5486 * same critical section as kvm_reload_remote_mmus, and
5487 * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages
5488 * could drop the MMU lock and yield.
5490 if (is_tdp_mmu_enabled(kvm))
5491 kvm_tdp_mmu_invalidate_all_roots(kvm);
5494 * Notify all vcpus to reload its shadow page table and flush TLB.
5495 * Then all vcpus will switch to new shadow page table with the new
5498 * Note: we need to do this under the protection of mmu_lock,
5499 * otherwise, vcpu would purge shadow page but miss tlb flush.
5501 kvm_reload_remote_mmus(kvm);
5503 kvm_zap_obsolete_pages(kvm);
5505 write_unlock(&kvm->mmu_lock);
5507 if (is_tdp_mmu_enabled(kvm)) {
5508 read_lock(&kvm->mmu_lock);
5509 kvm_tdp_mmu_zap_invalidated_roots(kvm);
5510 read_unlock(&kvm->mmu_lock);
5514 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5516 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5519 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5520 struct kvm_memory_slot *slot,
5521 struct kvm_page_track_notifier_node *node)
5523 kvm_mmu_zap_all_fast(kvm);
5526 void kvm_mmu_init_vm(struct kvm *kvm)
5528 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5530 if (!kvm_mmu_init_tdp_mmu(kvm))
5532 * No smp_load/store wrappers needed here as we are in
5533 * VM init and there cannot be any memslots / other threads
5534 * accessing this struct kvm yet.
5536 kvm->arch.memslots_have_rmaps = true;
5538 node->track_write = kvm_mmu_pte_write;
5539 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5540 kvm_page_track_register_notifier(kvm, node);
5543 void kvm_mmu_uninit_vm(struct kvm *kvm)
5545 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5547 kvm_page_track_unregister_notifier(kvm, node);
5549 kvm_mmu_uninit_tdp_mmu(kvm);
5552 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5554 struct kvm_memslots *slots;
5555 struct kvm_memory_slot *memslot;
5559 if (kvm_memslots_have_rmaps(kvm)) {
5560 write_lock(&kvm->mmu_lock);
5561 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5562 slots = __kvm_memslots(kvm, i);
5563 kvm_for_each_memslot(memslot, slots) {
5566 start = max(gfn_start, memslot->base_gfn);
5567 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5571 flush = slot_handle_level_range(kvm, memslot,
5572 kvm_zap_rmapp, PG_LEVEL_4K,
5573 KVM_MAX_HUGEPAGE_LEVEL, start,
5574 end - 1, true, flush);
5578 kvm_flush_remote_tlbs_with_address(kvm, gfn_start, gfn_end);
5579 write_unlock(&kvm->mmu_lock);
5582 if (is_tdp_mmu_enabled(kvm)) {
5585 read_lock(&kvm->mmu_lock);
5586 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++)
5587 flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start,
5588 gfn_end, flush, true);
5590 kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
5593 read_unlock(&kvm->mmu_lock);
5597 static bool slot_rmap_write_protect(struct kvm *kvm,
5598 struct kvm_rmap_head *rmap_head,
5599 struct kvm_memory_slot *slot)
5601 return __rmap_write_protect(kvm, rmap_head, false);
5604 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5605 struct kvm_memory_slot *memslot,
5610 if (kvm_memslots_have_rmaps(kvm)) {
5611 write_lock(&kvm->mmu_lock);
5612 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5613 start_level, KVM_MAX_HUGEPAGE_LEVEL,
5615 write_unlock(&kvm->mmu_lock);
5618 if (is_tdp_mmu_enabled(kvm)) {
5619 read_lock(&kvm->mmu_lock);
5620 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level);
5621 read_unlock(&kvm->mmu_lock);
5625 * We can flush all the TLBs out of the mmu lock without TLB
5626 * corruption since we just change the spte from writable to
5627 * readonly so that we only need to care the case of changing
5628 * spte from present to present (changing the spte from present
5629 * to nonpresent will flush all the TLBs immediately), in other
5630 * words, the only case we care is mmu_spte_update() where we
5631 * have checked Host-writable | MMU-writable instead of
5632 * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK
5636 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5639 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5640 struct kvm_rmap_head *rmap_head,
5641 struct kvm_memory_slot *slot)
5644 struct rmap_iterator iter;
5645 int need_tlb_flush = 0;
5647 struct kvm_mmu_page *sp;
5650 for_each_rmap_spte(rmap_head, &iter, sptep) {
5651 sp = sptep_to_sp(sptep);
5652 pfn = spte_to_pfn(*sptep);
5655 * We cannot do huge page mapping for indirect shadow pages,
5656 * which are found on the last rmap (level = 1) when not using
5657 * tdp; such shadow pages are synced with the page table in
5658 * the guest, and the guest page table is using 4K page size
5659 * mapping if the indirect sp has level = 1.
5661 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5662 sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn,
5663 pfn, PG_LEVEL_NUM)) {
5664 pte_list_remove(rmap_head, sptep);
5666 if (kvm_available_flush_tlb_with_range())
5667 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5668 KVM_PAGES_PER_HPAGE(sp->role.level));
5676 return need_tlb_flush;
5679 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5680 const struct kvm_memory_slot *memslot)
5682 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5683 struct kvm_memory_slot *slot = (struct kvm_memory_slot *)memslot;
5686 if (kvm_memslots_have_rmaps(kvm)) {
5687 write_lock(&kvm->mmu_lock);
5688 flush = slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true);
5690 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5691 write_unlock(&kvm->mmu_lock);
5694 if (is_tdp_mmu_enabled(kvm)) {
5695 read_lock(&kvm->mmu_lock);
5696 flush = kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot, flush);
5698 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5699 read_unlock(&kvm->mmu_lock);
5703 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5704 const struct kvm_memory_slot *memslot)
5707 * All current use cases for flushing the TLBs for a specific memslot
5708 * related to dirty logging, and many do the TLB flush out of mmu_lock.
5709 * The interaction between the various operations on memslot must be
5710 * serialized by slots_locks to ensure the TLB flush from one operation
5711 * is observed by any other operation on the same memslot.
5713 lockdep_assert_held(&kvm->slots_lock);
5714 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5718 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5719 struct kvm_memory_slot *memslot)
5723 if (kvm_memslots_have_rmaps(kvm)) {
5724 write_lock(&kvm->mmu_lock);
5725 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty,
5727 write_unlock(&kvm->mmu_lock);
5730 if (is_tdp_mmu_enabled(kvm)) {
5731 read_lock(&kvm->mmu_lock);
5732 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5733 read_unlock(&kvm->mmu_lock);
5737 * It's also safe to flush TLBs out of mmu lock here as currently this
5738 * function is only used for dirty logging, in which case flushing TLB
5739 * out of mmu lock also guarantees no dirty pages will be lost in
5743 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5746 void kvm_mmu_zap_all(struct kvm *kvm)
5748 struct kvm_mmu_page *sp, *node;
5749 LIST_HEAD(invalid_list);
5752 write_lock(&kvm->mmu_lock);
5754 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5755 if (WARN_ON(sp->role.invalid))
5757 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5759 if (cond_resched_rwlock_write(&kvm->mmu_lock))
5763 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5765 if (is_tdp_mmu_enabled(kvm))
5766 kvm_tdp_mmu_zap_all(kvm);
5768 write_unlock(&kvm->mmu_lock);
5771 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5773 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5775 gen &= MMIO_SPTE_GEN_MASK;
5778 * Generation numbers are incremented in multiples of the number of
5779 * address spaces in order to provide unique generations across all
5780 * address spaces. Strip what is effectively the address space
5781 * modifier prior to checking for a wrap of the MMIO generation so
5782 * that a wrap in any address space is detected.
5784 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5787 * The very rare case: if the MMIO generation number has wrapped,
5788 * zap all shadow pages.
5790 if (unlikely(gen == 0)) {
5791 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5792 kvm_mmu_zap_all_fast(kvm);
5796 static unsigned long
5797 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5800 int nr_to_scan = sc->nr_to_scan;
5801 unsigned long freed = 0;
5803 mutex_lock(&kvm_lock);
5805 list_for_each_entry(kvm, &vm_list, vm_list) {
5807 LIST_HEAD(invalid_list);
5810 * Never scan more than sc->nr_to_scan VM instances.
5811 * Will not hit this condition practically since we do not try
5812 * to shrink more than one VM and it is very unlikely to see
5813 * !n_used_mmu_pages so many times.
5818 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5819 * here. We may skip a VM instance errorneosly, but we do not
5820 * want to shrink a VM that only started to populate its MMU
5823 if (!kvm->arch.n_used_mmu_pages &&
5824 !kvm_has_zapped_obsolete_pages(kvm))
5827 idx = srcu_read_lock(&kvm->srcu);
5828 write_lock(&kvm->mmu_lock);
5830 if (kvm_has_zapped_obsolete_pages(kvm)) {
5831 kvm_mmu_commit_zap_page(kvm,
5832 &kvm->arch.zapped_obsolete_pages);
5836 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
5839 write_unlock(&kvm->mmu_lock);
5840 srcu_read_unlock(&kvm->srcu, idx);
5843 * unfair on small ones
5844 * per-vm shrinkers cry out
5845 * sadness comes quickly
5847 list_move_tail(&kvm->vm_list, &vm_list);
5851 mutex_unlock(&kvm_lock);
5855 static unsigned long
5856 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5858 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5861 static struct shrinker mmu_shrinker = {
5862 .count_objects = mmu_shrink_count,
5863 .scan_objects = mmu_shrink_scan,
5864 .seeks = DEFAULT_SEEKS * 10,
5867 static void mmu_destroy_caches(void)
5869 kmem_cache_destroy(pte_list_desc_cache);
5870 kmem_cache_destroy(mmu_page_header_cache);
5873 static bool get_nx_auto_mode(void)
5875 /* Return true when CPU has the bug, and mitigations are ON */
5876 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5879 static void __set_nx_huge_pages(bool val)
5881 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5884 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5886 bool old_val = nx_huge_pages;
5889 /* In "auto" mode deploy workaround only if CPU has the bug. */
5890 if (sysfs_streq(val, "off"))
5892 else if (sysfs_streq(val, "force"))
5894 else if (sysfs_streq(val, "auto"))
5895 new_val = get_nx_auto_mode();
5896 else if (strtobool(val, &new_val) < 0)
5899 __set_nx_huge_pages(new_val);
5901 if (new_val != old_val) {
5904 mutex_lock(&kvm_lock);
5906 list_for_each_entry(kvm, &vm_list, vm_list) {
5907 mutex_lock(&kvm->slots_lock);
5908 kvm_mmu_zap_all_fast(kvm);
5909 mutex_unlock(&kvm->slots_lock);
5911 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5913 mutex_unlock(&kvm_lock);
5919 int kvm_mmu_module_init(void)
5923 if (nx_huge_pages == -1)
5924 __set_nx_huge_pages(get_nx_auto_mode());
5927 * MMU roles use union aliasing which is, generally speaking, an
5928 * undefined behavior. However, we supposedly know how compilers behave
5929 * and the current status quo is unlikely to change. Guardians below are
5930 * supposed to let us know if the assumption becomes false.
5932 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
5933 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
5934 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
5936 kvm_mmu_reset_all_pte_masks();
5938 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5939 sizeof(struct pte_list_desc),
5940 0, SLAB_ACCOUNT, NULL);
5941 if (!pte_list_desc_cache)
5944 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5945 sizeof(struct kvm_mmu_page),
5946 0, SLAB_ACCOUNT, NULL);
5947 if (!mmu_page_header_cache)
5950 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5953 ret = register_shrinker(&mmu_shrinker);
5960 mmu_destroy_caches();
5965 * Calculate mmu pages needed for kvm.
5967 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
5969 unsigned long nr_mmu_pages;
5970 unsigned long nr_pages = 0;
5971 struct kvm_memslots *slots;
5972 struct kvm_memory_slot *memslot;
5975 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5976 slots = __kvm_memslots(kvm, i);
5978 kvm_for_each_memslot(memslot, slots)
5979 nr_pages += memslot->npages;
5982 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5983 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
5985 return nr_mmu_pages;
5988 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5990 kvm_mmu_unload(vcpu);
5991 free_mmu_pages(&vcpu->arch.root_mmu);
5992 free_mmu_pages(&vcpu->arch.guest_mmu);
5993 mmu_free_memory_caches(vcpu);
5996 void kvm_mmu_module_exit(void)
5998 mmu_destroy_caches();
5999 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6000 unregister_shrinker(&mmu_shrinker);
6001 mmu_audit_disable();
6004 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
6006 unsigned int old_val;
6009 old_val = nx_huge_pages_recovery_ratio;
6010 err = param_set_uint(val, kp);
6014 if (READ_ONCE(nx_huge_pages) &&
6015 !old_val && nx_huge_pages_recovery_ratio) {
6018 mutex_lock(&kvm_lock);
6020 list_for_each_entry(kvm, &vm_list, vm_list)
6021 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6023 mutex_unlock(&kvm_lock);
6029 static void kvm_recover_nx_lpages(struct kvm *kvm)
6031 unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits;
6033 struct kvm_mmu_page *sp;
6035 LIST_HEAD(invalid_list);
6039 rcu_idx = srcu_read_lock(&kvm->srcu);
6040 write_lock(&kvm->mmu_lock);
6042 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6043 to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0;
6044 for ( ; to_zap; --to_zap) {
6045 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
6049 * We use a separate list instead of just using active_mmu_pages
6050 * because the number of lpage_disallowed pages is expected to
6051 * be relatively small compared to the total.
6053 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6054 struct kvm_mmu_page,
6055 lpage_disallowed_link);
6056 WARN_ON_ONCE(!sp->lpage_disallowed);
6057 if (is_tdp_mmu_page(sp)) {
6058 flush |= kvm_tdp_mmu_zap_sp(kvm, sp);
6060 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6061 WARN_ON_ONCE(sp->lpage_disallowed);
6064 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
6065 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6066 cond_resched_rwlock_write(&kvm->mmu_lock);
6070 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6072 write_unlock(&kvm->mmu_lock);
6073 srcu_read_unlock(&kvm->srcu, rcu_idx);
6076 static long get_nx_lpage_recovery_timeout(u64 start_time)
6078 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6079 ? start_time + 60 * HZ - get_jiffies_64()
6080 : MAX_SCHEDULE_TIMEOUT;
6083 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6086 long remaining_time;
6089 start_time = get_jiffies_64();
6090 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6092 set_current_state(TASK_INTERRUPTIBLE);
6093 while (!kthread_should_stop() && remaining_time > 0) {
6094 schedule_timeout(remaining_time);
6095 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6096 set_current_state(TASK_INTERRUPTIBLE);
6099 set_current_state(TASK_RUNNING);
6101 if (kthread_should_stop())
6104 kvm_recover_nx_lpages(kvm);
6108 int kvm_mmu_post_init_vm(struct kvm *kvm)
6112 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6113 "kvm-nx-lpage-recovery",
6114 &kvm->arch.nx_lpage_recovery_thread);
6116 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6121 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6123 if (kvm->arch.nx_lpage_recovery_thread)
6124 kthread_stop(kvm->arch.nx_lpage_recovery_thread);