1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
52 #include <asm/kvm_page_track.h>
55 extern bool itlb_multihit_kvm_mitigation;
57 static int __read_mostly nx_huge_pages = -1;
58 #ifdef CONFIG_PREEMPT_RT
59 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
60 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
62 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
65 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
66 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
68 static const struct kernel_param_ops nx_huge_pages_ops = {
69 .set = set_nx_huge_pages,
70 .get = param_get_bool,
73 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
74 .set = set_nx_huge_pages_recovery_ratio,
75 .get = param_get_uint,
78 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
79 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
80 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
81 &nx_huge_pages_recovery_ratio, 0644);
82 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
84 static bool __read_mostly force_flush_and_sync_on_reuse;
85 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
88 * When setting this variable to true it enables Two-Dimensional-Paging
89 * where the hardware walks 2 page tables:
90 * 1. the guest-virtual to guest-physical
91 * 2. while doing 1. it walks guest-physical to host-physical
92 * If the hardware supports that we don't need to do shadow paging.
94 bool tdp_enabled = false;
96 static int max_huge_page_level __read_mostly;
97 static int max_tdp_level __read_mostly;
100 AUDIT_PRE_PAGE_FAULT,
101 AUDIT_POST_PAGE_FAULT,
103 AUDIT_POST_PTE_WRITE,
110 module_param(dbg, bool, 0644);
113 #define PTE_PREFETCH_NUM 8
115 #define PT32_LEVEL_BITS 10
117 #define PT32_LEVEL_SHIFT(level) \
118 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
120 #define PT32_LVL_OFFSET_MASK(level) \
121 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
122 * PT32_LEVEL_BITS))) - 1))
124 #define PT32_INDEX(address, level)\
125 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #include <trace/events/kvm.h>
137 /* make pte_list_desc fit well in cache line */
138 #define PTE_LIST_EXT 3
140 struct pte_list_desc {
141 u64 *sptes[PTE_LIST_EXT];
142 struct pte_list_desc *more;
145 struct kvm_shadow_walk_iterator {
153 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
154 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
156 shadow_walk_okay(&(_walker)); \
157 shadow_walk_next(&(_walker)))
159 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
160 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
161 shadow_walk_okay(&(_walker)); \
162 shadow_walk_next(&(_walker)))
164 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
165 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
166 shadow_walk_okay(&(_walker)) && \
167 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
168 __shadow_walk_next(&(_walker), spte))
170 static struct kmem_cache *pte_list_desc_cache;
171 struct kmem_cache *mmu_page_header_cache;
172 static struct percpu_counter kvm_total_used_mmu_pages;
174 static void mmu_spte_set(u64 *sptep, u64 spte);
175 static union kvm_mmu_page_role
176 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
178 #define CREATE_TRACE_POINTS
179 #include "mmutrace.h"
182 static inline bool kvm_available_flush_tlb_with_range(void)
184 return kvm_x86_ops.tlb_remote_flush_with_range;
187 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
188 struct kvm_tlb_range *range)
192 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
193 ret = kvm_x86_ops.tlb_remote_flush_with_range(kvm, range);
196 kvm_flush_remote_tlbs(kvm);
199 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
200 u64 start_gfn, u64 pages)
202 struct kvm_tlb_range range;
204 range.start_gfn = start_gfn;
207 kvm_flush_remote_tlbs_with_range(kvm, &range);
210 bool is_nx_huge_page_enabled(void)
212 return READ_ONCE(nx_huge_pages);
215 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
218 u64 mask = make_mmio_spte(vcpu, gfn, access);
220 trace_mark_mmio_spte(sptep, gfn, mask);
221 mmu_spte_set(sptep, mask);
224 static gfn_t get_mmio_spte_gfn(u64 spte)
226 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
228 gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len)
229 & shadow_nonpresent_or_rsvd_mask;
231 return gpa >> PAGE_SHIFT;
234 static unsigned get_mmio_spte_access(u64 spte)
236 return spte & shadow_mmio_access_mask;
239 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
240 kvm_pfn_t pfn, unsigned int access)
242 if (unlikely(is_noslot_pfn(pfn))) {
243 mark_mmio_spte(vcpu, sptep, gfn, access);
250 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
252 u64 kvm_gen, spte_gen, gen;
254 gen = kvm_vcpu_memslots(vcpu)->generation;
255 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
258 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
259 spte_gen = get_mmio_spte_generation(spte);
261 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
262 return likely(kvm_gen == spte_gen);
265 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
266 struct x86_exception *exception)
268 /* Check if guest physical address doesn't exceed guest maximum */
269 if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) {
270 exception->error_code |= PFERR_RSVD_MASK;
277 static int is_cpuid_PSE36(void)
282 static int is_nx(struct kvm_vcpu *vcpu)
284 return vcpu->arch.efer & EFER_NX;
287 static gfn_t pse36_gfn_delta(u32 gpte)
289 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
291 return (gpte & PT32_DIR_PSE36_MASK) << shift;
295 static void __set_spte(u64 *sptep, u64 spte)
297 WRITE_ONCE(*sptep, spte);
300 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
302 WRITE_ONCE(*sptep, spte);
305 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
307 return xchg(sptep, spte);
310 static u64 __get_spte_lockless(u64 *sptep)
312 return READ_ONCE(*sptep);
323 static void count_spte_clear(u64 *sptep, u64 spte)
325 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
327 if (is_shadow_present_pte(spte))
330 /* Ensure the spte is completely set before we increase the count */
332 sp->clear_spte_count++;
335 static void __set_spte(u64 *sptep, u64 spte)
337 union split_spte *ssptep, sspte;
339 ssptep = (union split_spte *)sptep;
340 sspte = (union split_spte)spte;
342 ssptep->spte_high = sspte.spte_high;
345 * If we map the spte from nonpresent to present, We should store
346 * the high bits firstly, then set present bit, so cpu can not
347 * fetch this spte while we are setting the spte.
351 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
354 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
356 union split_spte *ssptep, sspte;
358 ssptep = (union split_spte *)sptep;
359 sspte = (union split_spte)spte;
361 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
364 * If we map the spte from present to nonpresent, we should clear
365 * present bit firstly to avoid vcpu fetch the old high bits.
369 ssptep->spte_high = sspte.spte_high;
370 count_spte_clear(sptep, spte);
373 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
375 union split_spte *ssptep, sspte, orig;
377 ssptep = (union split_spte *)sptep;
378 sspte = (union split_spte)spte;
380 /* xchg acts as a barrier before the setting of the high bits */
381 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
382 orig.spte_high = ssptep->spte_high;
383 ssptep->spte_high = sspte.spte_high;
384 count_spte_clear(sptep, spte);
390 * The idea using the light way get the spte on x86_32 guest is from
391 * gup_get_pte (mm/gup.c).
393 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
394 * coalesces them and we are running out of the MMU lock. Therefore
395 * we need to protect against in-progress updates of the spte.
397 * Reading the spte while an update is in progress may get the old value
398 * for the high part of the spte. The race is fine for a present->non-present
399 * change (because the high part of the spte is ignored for non-present spte),
400 * but for a present->present change we must reread the spte.
402 * All such changes are done in two steps (present->non-present and
403 * non-present->present), hence it is enough to count the number of
404 * present->non-present updates: if it changed while reading the spte,
405 * we might have hit the race. This is done using clear_spte_count.
407 static u64 __get_spte_lockless(u64 *sptep)
409 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
410 union split_spte spte, *orig = (union split_spte *)sptep;
414 count = sp->clear_spte_count;
417 spte.spte_low = orig->spte_low;
420 spte.spte_high = orig->spte_high;
423 if (unlikely(spte.spte_low != orig->spte_low ||
424 count != sp->clear_spte_count))
431 static bool spte_has_volatile_bits(u64 spte)
433 if (!is_shadow_present_pte(spte))
437 * Always atomically update spte if it can be updated
438 * out of mmu-lock, it can ensure dirty bit is not lost,
439 * also, it can help us to get a stable is_writable_pte()
440 * to ensure tlb flush is not missed.
442 if (spte_can_locklessly_be_made_writable(spte) ||
443 is_access_track_spte(spte))
446 if (spte_ad_enabled(spte)) {
447 if ((spte & shadow_accessed_mask) == 0 ||
448 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
455 /* Rules for using mmu_spte_set:
456 * Set the sptep from nonpresent to present.
457 * Note: the sptep being assigned *must* be either not present
458 * or in a state where the hardware will not attempt to update
461 static void mmu_spte_set(u64 *sptep, u64 new_spte)
463 WARN_ON(is_shadow_present_pte(*sptep));
464 __set_spte(sptep, new_spte);
468 * Update the SPTE (excluding the PFN), but do not track changes in its
469 * accessed/dirty status.
471 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
473 u64 old_spte = *sptep;
475 WARN_ON(!is_shadow_present_pte(new_spte));
477 if (!is_shadow_present_pte(old_spte)) {
478 mmu_spte_set(sptep, new_spte);
482 if (!spte_has_volatile_bits(old_spte))
483 __update_clear_spte_fast(sptep, new_spte);
485 old_spte = __update_clear_spte_slow(sptep, new_spte);
487 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
492 /* Rules for using mmu_spte_update:
493 * Update the state bits, it means the mapped pfn is not changed.
495 * Whenever we overwrite a writable spte with a read-only one we
496 * should flush remote TLBs. Otherwise rmap_write_protect
497 * will find a read-only spte, even though the writable spte
498 * might be cached on a CPU's TLB, the return value indicates this
501 * Returns true if the TLB needs to be flushed
503 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
506 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
508 if (!is_shadow_present_pte(old_spte))
512 * For the spte updated out of mmu-lock is safe, since
513 * we always atomically update it, see the comments in
514 * spte_has_volatile_bits().
516 if (spte_can_locklessly_be_made_writable(old_spte) &&
517 !is_writable_pte(new_spte))
521 * Flush TLB when accessed/dirty states are changed in the page tables,
522 * to guarantee consistency between TLB and page tables.
525 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
527 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
530 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
532 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
539 * Rules for using mmu_spte_clear_track_bits:
540 * It sets the sptep from present to nonpresent, and track the
541 * state bits, it is used to clear the last level sptep.
542 * Returns non-zero if the PTE was previously valid.
544 static int mmu_spte_clear_track_bits(u64 *sptep)
547 u64 old_spte = *sptep;
549 if (!spte_has_volatile_bits(old_spte))
550 __update_clear_spte_fast(sptep, 0ull);
552 old_spte = __update_clear_spte_slow(sptep, 0ull);
554 if (!is_shadow_present_pte(old_spte))
557 pfn = spte_to_pfn(old_spte);
560 * KVM does not hold the refcount of the page used by
561 * kvm mmu, before reclaiming the page, we should
562 * unmap it from mmu first.
564 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
566 if (is_accessed_spte(old_spte))
567 kvm_set_pfn_accessed(pfn);
569 if (is_dirty_spte(old_spte))
570 kvm_set_pfn_dirty(pfn);
576 * Rules for using mmu_spte_clear_no_track:
577 * Directly clear spte without caring the state bits of sptep,
578 * it is used to set the upper level spte.
580 static void mmu_spte_clear_no_track(u64 *sptep)
582 __update_clear_spte_fast(sptep, 0ull);
585 static u64 mmu_spte_get_lockless(u64 *sptep)
587 return __get_spte_lockless(sptep);
590 /* Restore an acc-track PTE back to a regular PTE */
591 static u64 restore_acc_track_spte(u64 spte)
594 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
595 & shadow_acc_track_saved_bits_mask;
597 WARN_ON_ONCE(spte_ad_enabled(spte));
598 WARN_ON_ONCE(!is_access_track_spte(spte));
600 new_spte &= ~shadow_acc_track_mask;
601 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
602 shadow_acc_track_saved_bits_shift);
603 new_spte |= saved_bits;
608 /* Returns the Accessed status of the PTE and resets it at the same time. */
609 static bool mmu_spte_age(u64 *sptep)
611 u64 spte = mmu_spte_get_lockless(sptep);
613 if (!is_accessed_spte(spte))
616 if (spte_ad_enabled(spte)) {
617 clear_bit((ffs(shadow_accessed_mask) - 1),
618 (unsigned long *)sptep);
621 * Capture the dirty status of the page, so that it doesn't get
622 * lost when the SPTE is marked for access tracking.
624 if (is_writable_pte(spte))
625 kvm_set_pfn_dirty(spte_to_pfn(spte));
627 spte = mark_spte_for_access_track(spte);
628 mmu_spte_update_no_track(sptep, spte);
634 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
637 * Prevent page table teardown by making any free-er wait during
638 * kvm_flush_remote_tlbs() IPI to all active vcpus.
643 * Make sure a following spte read is not reordered ahead of the write
646 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
649 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
652 * Make sure the write to vcpu->mode is not reordered in front of
653 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
654 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
656 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
660 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
664 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
665 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
666 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
669 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
670 PT64_ROOT_MAX_LEVEL);
673 if (maybe_indirect) {
674 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
675 PT64_ROOT_MAX_LEVEL);
679 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
680 PT64_ROOT_MAX_LEVEL);
683 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
685 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
686 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
687 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
688 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
691 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
693 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
696 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
698 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
701 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
703 if (!sp->role.direct)
704 return sp->gfns[index];
706 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
709 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
711 if (!sp->role.direct) {
712 sp->gfns[index] = gfn;
716 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
717 pr_err_ratelimited("gfn mismatch under direct page %llx "
718 "(expected %llx, got %llx)\n",
720 kvm_mmu_page_get_gfn(sp, index), gfn);
724 * Return the pointer to the large page information for a given gfn,
725 * handling slots that are not large page aligned.
727 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
728 struct kvm_memory_slot *slot,
733 idx = gfn_to_index(gfn, slot->base_gfn, level);
734 return &slot->arch.lpage_info[level - 2][idx];
737 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
738 gfn_t gfn, int count)
740 struct kvm_lpage_info *linfo;
743 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
744 linfo = lpage_info_slot(gfn, slot, i);
745 linfo->disallow_lpage += count;
746 WARN_ON(linfo->disallow_lpage < 0);
750 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
752 update_gfn_disallow_lpage_count(slot, gfn, 1);
755 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
757 update_gfn_disallow_lpage_count(slot, gfn, -1);
760 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
762 struct kvm_memslots *slots;
763 struct kvm_memory_slot *slot;
766 kvm->arch.indirect_shadow_pages++;
768 slots = kvm_memslots_for_spte_role(kvm, sp->role);
769 slot = __gfn_to_memslot(slots, gfn);
771 /* the non-leaf shadow pages are keeping readonly. */
772 if (sp->role.level > PG_LEVEL_4K)
773 return kvm_slot_page_track_add_page(kvm, slot, gfn,
774 KVM_PAGE_TRACK_WRITE);
776 kvm_mmu_gfn_disallow_lpage(slot, gfn);
779 static void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
781 if (sp->lpage_disallowed)
784 ++kvm->stat.nx_lpage_splits;
785 list_add_tail(&sp->lpage_disallowed_link,
786 &kvm->arch.lpage_disallowed_mmu_pages);
787 sp->lpage_disallowed = true;
790 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
792 struct kvm_memslots *slots;
793 struct kvm_memory_slot *slot;
796 kvm->arch.indirect_shadow_pages--;
798 slots = kvm_memslots_for_spte_role(kvm, sp->role);
799 slot = __gfn_to_memslot(slots, gfn);
800 if (sp->role.level > PG_LEVEL_4K)
801 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
802 KVM_PAGE_TRACK_WRITE);
804 kvm_mmu_gfn_allow_lpage(slot, gfn);
807 static void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
809 --kvm->stat.nx_lpage_splits;
810 sp->lpage_disallowed = false;
811 list_del(&sp->lpage_disallowed_link);
814 static struct kvm_memory_slot *
815 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
818 struct kvm_memory_slot *slot;
820 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
821 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
823 if (no_dirty_log && slot->dirty_bitmap)
830 * About rmap_head encoding:
832 * If the bit zero of rmap_head->val is clear, then it points to the only spte
833 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
834 * pte_list_desc containing more mappings.
838 * Returns the number of pointers in the rmap chain, not counting the new one.
840 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
841 struct kvm_rmap_head *rmap_head)
843 struct pte_list_desc *desc;
846 if (!rmap_head->val) {
847 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
848 rmap_head->val = (unsigned long)spte;
849 } else if (!(rmap_head->val & 1)) {
850 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
851 desc = mmu_alloc_pte_list_desc(vcpu);
852 desc->sptes[0] = (u64 *)rmap_head->val;
853 desc->sptes[1] = spte;
854 rmap_head->val = (unsigned long)desc | 1;
857 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
858 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
859 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
861 count += PTE_LIST_EXT;
863 if (desc->sptes[PTE_LIST_EXT-1]) {
864 desc->more = mmu_alloc_pte_list_desc(vcpu);
867 for (i = 0; desc->sptes[i]; ++i)
869 desc->sptes[i] = spte;
875 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
876 struct pte_list_desc *desc, int i,
877 struct pte_list_desc *prev_desc)
881 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
883 desc->sptes[i] = desc->sptes[j];
884 desc->sptes[j] = NULL;
887 if (!prev_desc && !desc->more)
891 prev_desc->more = desc->more;
893 rmap_head->val = (unsigned long)desc->more | 1;
894 mmu_free_pte_list_desc(desc);
897 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
899 struct pte_list_desc *desc;
900 struct pte_list_desc *prev_desc;
903 if (!rmap_head->val) {
904 pr_err("%s: %p 0->BUG\n", __func__, spte);
906 } else if (!(rmap_head->val & 1)) {
907 rmap_printk("%s: %p 1->0\n", __func__, spte);
908 if ((u64 *)rmap_head->val != spte) {
909 pr_err("%s: %p 1->BUG\n", __func__, spte);
914 rmap_printk("%s: %p many->many\n", __func__, spte);
915 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
918 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
919 if (desc->sptes[i] == spte) {
920 pte_list_desc_remove_entry(rmap_head,
928 pr_err("%s: %p many->many\n", __func__, spte);
933 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
935 mmu_spte_clear_track_bits(sptep);
936 __pte_list_remove(sptep, rmap_head);
939 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
940 struct kvm_memory_slot *slot)
944 idx = gfn_to_index(gfn, slot->base_gfn, level);
945 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
948 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
949 struct kvm_mmu_page *sp)
951 struct kvm_memslots *slots;
952 struct kvm_memory_slot *slot;
954 slots = kvm_memslots_for_spte_role(kvm, sp->role);
955 slot = __gfn_to_memslot(slots, gfn);
956 return __gfn_to_rmap(gfn, sp->role.level, slot);
959 static bool rmap_can_add(struct kvm_vcpu *vcpu)
961 struct kvm_mmu_memory_cache *mc;
963 mc = &vcpu->arch.mmu_pte_list_desc_cache;
964 return kvm_mmu_memory_cache_nr_free_objects(mc);
967 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
969 struct kvm_mmu_page *sp;
970 struct kvm_rmap_head *rmap_head;
972 sp = sptep_to_sp(spte);
973 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
974 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
975 return pte_list_add(vcpu, spte, rmap_head);
978 static void rmap_remove(struct kvm *kvm, u64 *spte)
980 struct kvm_mmu_page *sp;
982 struct kvm_rmap_head *rmap_head;
984 sp = sptep_to_sp(spte);
985 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
986 rmap_head = gfn_to_rmap(kvm, gfn, sp);
987 __pte_list_remove(spte, rmap_head);
991 * Used by the following functions to iterate through the sptes linked by a
992 * rmap. All fields are private and not assumed to be used outside.
994 struct rmap_iterator {
996 struct pte_list_desc *desc; /* holds the sptep if not NULL */
997 int pos; /* index of the sptep */
1001 * Iteration must be started by this function. This should also be used after
1002 * removing/dropping sptes from the rmap link because in such cases the
1003 * information in the iterator may not be valid.
1005 * Returns sptep if found, NULL otherwise.
1007 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1008 struct rmap_iterator *iter)
1012 if (!rmap_head->val)
1015 if (!(rmap_head->val & 1)) {
1017 sptep = (u64 *)rmap_head->val;
1021 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1023 sptep = iter->desc->sptes[iter->pos];
1025 BUG_ON(!is_shadow_present_pte(*sptep));
1030 * Must be used with a valid iterator: e.g. after rmap_get_first().
1032 * Returns sptep if found, NULL otherwise.
1034 static u64 *rmap_get_next(struct rmap_iterator *iter)
1039 if (iter->pos < PTE_LIST_EXT - 1) {
1041 sptep = iter->desc->sptes[iter->pos];
1046 iter->desc = iter->desc->more;
1050 /* desc->sptes[0] cannot be NULL */
1051 sptep = iter->desc->sptes[iter->pos];
1058 BUG_ON(!is_shadow_present_pte(*sptep));
1062 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1063 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1064 _spte_; _spte_ = rmap_get_next(_iter_))
1066 static void drop_spte(struct kvm *kvm, u64 *sptep)
1068 if (mmu_spte_clear_track_bits(sptep))
1069 rmap_remove(kvm, sptep);
1073 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1075 if (is_large_pte(*sptep)) {
1076 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1077 drop_spte(kvm, sptep);
1085 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1087 if (__drop_large_spte(vcpu->kvm, sptep)) {
1088 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1090 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1091 KVM_PAGES_PER_HPAGE(sp->role.level));
1096 * Write-protect on the specified @sptep, @pt_protect indicates whether
1097 * spte write-protection is caused by protecting shadow page table.
1099 * Note: write protection is difference between dirty logging and spte
1101 * - for dirty logging, the spte can be set to writable at anytime if
1102 * its dirty bitmap is properly set.
1103 * - for spte protection, the spte can be writable only after unsync-ing
1106 * Return true if tlb need be flushed.
1108 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1112 if (!is_writable_pte(spte) &&
1113 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1116 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1119 spte &= ~SPTE_MMU_WRITEABLE;
1120 spte = spte & ~PT_WRITABLE_MASK;
1122 return mmu_spte_update(sptep, spte);
1125 static bool __rmap_write_protect(struct kvm *kvm,
1126 struct kvm_rmap_head *rmap_head,
1130 struct rmap_iterator iter;
1133 for_each_rmap_spte(rmap_head, &iter, sptep)
1134 flush |= spte_write_protect(sptep, pt_protect);
1139 static bool spte_clear_dirty(u64 *sptep)
1143 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1145 MMU_WARN_ON(!spte_ad_enabled(spte));
1146 spte &= ~shadow_dirty_mask;
1147 return mmu_spte_update(sptep, spte);
1150 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1152 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1153 (unsigned long *)sptep);
1154 if (was_writable && !spte_ad_enabled(*sptep))
1155 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1157 return was_writable;
1161 * Gets the GFN ready for another round of dirty logging by clearing the
1162 * - D bit on ad-enabled SPTEs, and
1163 * - W bit on ad-disabled SPTEs.
1164 * Returns true iff any D or W bits were cleared.
1166 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1169 struct rmap_iterator iter;
1172 for_each_rmap_spte(rmap_head, &iter, sptep)
1173 if (spte_ad_need_write_protect(*sptep))
1174 flush |= spte_wrprot_for_clear_dirty(sptep);
1176 flush |= spte_clear_dirty(sptep);
1181 static bool spte_set_dirty(u64 *sptep)
1185 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1188 * Similar to the !kvm_x86_ops.slot_disable_log_dirty case,
1189 * do not bother adding back write access to pages marked
1190 * SPTE_AD_WRPROT_ONLY_MASK.
1192 spte |= shadow_dirty_mask;
1194 return mmu_spte_update(sptep, spte);
1197 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1200 struct rmap_iterator iter;
1203 for_each_rmap_spte(rmap_head, &iter, sptep)
1204 if (spte_ad_enabled(*sptep))
1205 flush |= spte_set_dirty(sptep);
1211 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1212 * @kvm: kvm instance
1213 * @slot: slot to protect
1214 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1215 * @mask: indicates which pages we should protect
1217 * Used when we do not need to care about huge page mappings: e.g. during dirty
1218 * logging we do not have any such mappings.
1220 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1221 struct kvm_memory_slot *slot,
1222 gfn_t gfn_offset, unsigned long mask)
1224 struct kvm_rmap_head *rmap_head;
1227 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1229 __rmap_write_protect(kvm, rmap_head, false);
1231 /* clear the first set bit */
1237 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1238 * protect the page if the D-bit isn't supported.
1239 * @kvm: kvm instance
1240 * @slot: slot to clear D-bit
1241 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1242 * @mask: indicates which pages we should clear D-bit
1244 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1246 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1247 struct kvm_memory_slot *slot,
1248 gfn_t gfn_offset, unsigned long mask)
1250 struct kvm_rmap_head *rmap_head;
1253 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1255 __rmap_clear_dirty(kvm, rmap_head);
1257 /* clear the first set bit */
1261 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1264 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1267 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1268 * enable dirty logging for them.
1270 * Used when we do not need to care about huge page mappings: e.g. during dirty
1271 * logging we do not have any such mappings.
1273 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1274 struct kvm_memory_slot *slot,
1275 gfn_t gfn_offset, unsigned long mask)
1277 if (kvm_x86_ops.enable_log_dirty_pt_masked)
1278 kvm_x86_ops.enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1281 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1284 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1285 struct kvm_memory_slot *slot, u64 gfn)
1287 struct kvm_rmap_head *rmap_head;
1289 bool write_protected = false;
1291 for (i = PG_LEVEL_4K; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1292 rmap_head = __gfn_to_rmap(gfn, i, slot);
1293 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1296 return write_protected;
1299 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1301 struct kvm_memory_slot *slot;
1303 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1304 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1307 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1310 struct rmap_iterator iter;
1313 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1314 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1316 pte_list_remove(rmap_head, sptep);
1323 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1324 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1327 return kvm_zap_rmapp(kvm, rmap_head);
1330 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1331 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1335 struct rmap_iterator iter;
1338 pte_t *ptep = (pte_t *)data;
1341 WARN_ON(pte_huge(*ptep));
1342 new_pfn = pte_pfn(*ptep);
1345 for_each_rmap_spte(rmap_head, &iter, sptep) {
1346 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1347 sptep, *sptep, gfn, level);
1351 if (pte_write(*ptep)) {
1352 pte_list_remove(rmap_head, sptep);
1355 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1358 mmu_spte_clear_track_bits(sptep);
1359 mmu_spte_set(sptep, new_spte);
1363 if (need_flush && kvm_available_flush_tlb_with_range()) {
1364 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1371 struct slot_rmap_walk_iterator {
1373 struct kvm_memory_slot *slot;
1379 /* output fields. */
1381 struct kvm_rmap_head *rmap;
1384 /* private field. */
1385 struct kvm_rmap_head *end_rmap;
1389 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1391 iterator->level = level;
1392 iterator->gfn = iterator->start_gfn;
1393 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1394 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1399 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1400 struct kvm_memory_slot *slot, int start_level,
1401 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1403 iterator->slot = slot;
1404 iterator->start_level = start_level;
1405 iterator->end_level = end_level;
1406 iterator->start_gfn = start_gfn;
1407 iterator->end_gfn = end_gfn;
1409 rmap_walk_init_level(iterator, iterator->start_level);
1412 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1414 return !!iterator->rmap;
1417 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1419 if (++iterator->rmap <= iterator->end_rmap) {
1420 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1424 if (++iterator->level > iterator->end_level) {
1425 iterator->rmap = NULL;
1429 rmap_walk_init_level(iterator, iterator->level);
1432 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1433 _start_gfn, _end_gfn, _iter_) \
1434 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1435 _end_level_, _start_gfn, _end_gfn); \
1436 slot_rmap_walk_okay(_iter_); \
1437 slot_rmap_walk_next(_iter_))
1439 static int kvm_handle_hva_range(struct kvm *kvm,
1440 unsigned long start,
1443 int (*handler)(struct kvm *kvm,
1444 struct kvm_rmap_head *rmap_head,
1445 struct kvm_memory_slot *slot,
1448 unsigned long data))
1450 struct kvm_memslots *slots;
1451 struct kvm_memory_slot *memslot;
1452 struct slot_rmap_walk_iterator iterator;
1456 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1457 slots = __kvm_memslots(kvm, i);
1458 kvm_for_each_memslot(memslot, slots) {
1459 unsigned long hva_start, hva_end;
1460 gfn_t gfn_start, gfn_end;
1462 hva_start = max(start, memslot->userspace_addr);
1463 hva_end = min(end, memslot->userspace_addr +
1464 (memslot->npages << PAGE_SHIFT));
1465 if (hva_start >= hva_end)
1468 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1469 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1471 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1472 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1474 for_each_slot_rmap_range(memslot, PG_LEVEL_4K,
1475 KVM_MAX_HUGEPAGE_LEVEL,
1476 gfn_start, gfn_end - 1,
1478 ret |= handler(kvm, iterator.rmap, memslot,
1479 iterator.gfn, iterator.level, data);
1486 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1488 int (*handler)(struct kvm *kvm,
1489 struct kvm_rmap_head *rmap_head,
1490 struct kvm_memory_slot *slot,
1491 gfn_t gfn, int level,
1492 unsigned long data))
1494 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1497 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end,
1500 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1503 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1505 return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1508 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1509 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1513 struct rmap_iterator iter;
1516 for_each_rmap_spte(rmap_head, &iter, sptep)
1517 young |= mmu_spte_age(sptep);
1519 trace_kvm_age_page(gfn, level, slot, young);
1523 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1524 struct kvm_memory_slot *slot, gfn_t gfn,
1525 int level, unsigned long data)
1528 struct rmap_iterator iter;
1530 for_each_rmap_spte(rmap_head, &iter, sptep)
1531 if (is_accessed_spte(*sptep))
1536 #define RMAP_RECYCLE_THRESHOLD 1000
1538 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1540 struct kvm_rmap_head *rmap_head;
1541 struct kvm_mmu_page *sp;
1543 sp = sptep_to_sp(spte);
1545 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1547 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1548 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1549 KVM_PAGES_PER_HPAGE(sp->role.level));
1552 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1554 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1557 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1559 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1563 static int is_empty_shadow_page(u64 *spt)
1568 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1569 if (is_shadow_present_pte(*pos)) {
1570 printk(KERN_ERR "%s: %p %llx\n", __func__,
1579 * This value is the sum of all of the kvm instances's
1580 * kvm->arch.n_used_mmu_pages values. We need a global,
1581 * aggregate version in order to make the slab shrinker
1584 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
1586 kvm->arch.n_used_mmu_pages += nr;
1587 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1590 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1592 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1593 hlist_del(&sp->hash_link);
1594 list_del(&sp->link);
1595 free_page((unsigned long)sp->spt);
1596 if (!sp->role.direct)
1597 free_page((unsigned long)sp->gfns);
1598 kmem_cache_free(mmu_page_header_cache, sp);
1601 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1603 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1606 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1607 struct kvm_mmu_page *sp, u64 *parent_pte)
1612 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1615 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1618 __pte_list_remove(parent_pte, &sp->parent_ptes);
1621 static void drop_parent_pte(struct kvm_mmu_page *sp,
1624 mmu_page_remove_parent_pte(sp, parent_pte);
1625 mmu_spte_clear_no_track(parent_pte);
1628 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1630 struct kvm_mmu_page *sp;
1632 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1633 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1635 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1636 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1639 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1640 * depends on valid pages being added to the head of the list. See
1641 * comments in kvm_zap_obsolete_pages().
1643 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1644 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1645 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1649 static void mark_unsync(u64 *spte);
1650 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1653 struct rmap_iterator iter;
1655 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1660 static void mark_unsync(u64 *spte)
1662 struct kvm_mmu_page *sp;
1665 sp = sptep_to_sp(spte);
1666 index = spte - sp->spt;
1667 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1669 if (sp->unsync_children++)
1671 kvm_mmu_mark_parents_unsync(sp);
1674 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1675 struct kvm_mmu_page *sp)
1680 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1681 struct kvm_mmu_page *sp, u64 *spte,
1687 #define KVM_PAGE_ARRAY_NR 16
1689 struct kvm_mmu_pages {
1690 struct mmu_page_and_offset {
1691 struct kvm_mmu_page *sp;
1693 } page[KVM_PAGE_ARRAY_NR];
1697 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1703 for (i=0; i < pvec->nr; i++)
1704 if (pvec->page[i].sp == sp)
1707 pvec->page[pvec->nr].sp = sp;
1708 pvec->page[pvec->nr].idx = idx;
1710 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1713 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1715 --sp->unsync_children;
1716 WARN_ON((int)sp->unsync_children < 0);
1717 __clear_bit(idx, sp->unsync_child_bitmap);
1720 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1721 struct kvm_mmu_pages *pvec)
1723 int i, ret, nr_unsync_leaf = 0;
1725 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1726 struct kvm_mmu_page *child;
1727 u64 ent = sp->spt[i];
1729 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1730 clear_unsync_child_bit(sp, i);
1734 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1736 if (child->unsync_children) {
1737 if (mmu_pages_add(pvec, child, i))
1740 ret = __mmu_unsync_walk(child, pvec);
1742 clear_unsync_child_bit(sp, i);
1744 } else if (ret > 0) {
1745 nr_unsync_leaf += ret;
1748 } else if (child->unsync) {
1750 if (mmu_pages_add(pvec, child, i))
1753 clear_unsync_child_bit(sp, i);
1756 return nr_unsync_leaf;
1759 #define INVALID_INDEX (-1)
1761 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1762 struct kvm_mmu_pages *pvec)
1765 if (!sp->unsync_children)
1768 mmu_pages_add(pvec, sp, INVALID_INDEX);
1769 return __mmu_unsync_walk(sp, pvec);
1772 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1774 WARN_ON(!sp->unsync);
1775 trace_kvm_mmu_sync_page(sp);
1777 --kvm->stat.mmu_unsync;
1780 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1781 struct list_head *invalid_list);
1782 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1783 struct list_head *invalid_list);
1785 #define for_each_valid_sp(_kvm, _sp, _list) \
1786 hlist_for_each_entry(_sp, _list, hash_link) \
1787 if (is_obsolete_sp((_kvm), (_sp))) { \
1790 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1791 for_each_valid_sp(_kvm, _sp, \
1792 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1793 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1795 static inline bool is_ept_sp(struct kvm_mmu_page *sp)
1797 return sp->role.cr0_wp && sp->role.smap_andnot_wp;
1800 /* @sp->gfn should be write-protected at the call site */
1801 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1802 struct list_head *invalid_list)
1804 if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) ||
1805 vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
1806 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1813 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1814 struct list_head *invalid_list,
1817 if (!remote_flush && list_empty(invalid_list))
1820 if (!list_empty(invalid_list))
1821 kvm_mmu_commit_zap_page(kvm, invalid_list);
1823 kvm_flush_remote_tlbs(kvm);
1827 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1828 struct list_head *invalid_list,
1829 bool remote_flush, bool local_flush)
1831 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
1835 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1838 #ifdef CONFIG_KVM_MMU_AUDIT
1839 #include "mmu_audit.c"
1841 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1842 static void mmu_audit_disable(void) { }
1845 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1847 return sp->role.invalid ||
1848 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1851 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1852 struct list_head *invalid_list)
1854 kvm_unlink_unsync_page(vcpu->kvm, sp);
1855 return __kvm_sync_page(vcpu, sp, invalid_list);
1858 /* @gfn should be write-protected at the call site */
1859 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
1860 struct list_head *invalid_list)
1862 struct kvm_mmu_page *s;
1865 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1869 WARN_ON(s->role.level != PG_LEVEL_4K);
1870 ret |= kvm_sync_page(vcpu, s, invalid_list);
1876 struct mmu_page_path {
1877 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1878 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1881 #define for_each_sp(pvec, sp, parents, i) \
1882 for (i = mmu_pages_first(&pvec, &parents); \
1883 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1884 i = mmu_pages_next(&pvec, &parents, i))
1886 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1887 struct mmu_page_path *parents,
1892 for (n = i+1; n < pvec->nr; n++) {
1893 struct kvm_mmu_page *sp = pvec->page[n].sp;
1894 unsigned idx = pvec->page[n].idx;
1895 int level = sp->role.level;
1897 parents->idx[level-1] = idx;
1898 if (level == PG_LEVEL_4K)
1901 parents->parent[level-2] = sp;
1907 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1908 struct mmu_page_path *parents)
1910 struct kvm_mmu_page *sp;
1916 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1918 sp = pvec->page[0].sp;
1919 level = sp->role.level;
1920 WARN_ON(level == PG_LEVEL_4K);
1922 parents->parent[level-2] = sp;
1924 /* Also set up a sentinel. Further entries in pvec are all
1925 * children of sp, so this element is never overwritten.
1927 parents->parent[level-1] = NULL;
1928 return mmu_pages_next(pvec, parents, 0);
1931 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1933 struct kvm_mmu_page *sp;
1934 unsigned int level = 0;
1937 unsigned int idx = parents->idx[level];
1938 sp = parents->parent[level];
1942 WARN_ON(idx == INVALID_INDEX);
1943 clear_unsync_child_bit(sp, idx);
1945 } while (!sp->unsync_children);
1948 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1949 struct kvm_mmu_page *parent)
1952 struct kvm_mmu_page *sp;
1953 struct mmu_page_path parents;
1954 struct kvm_mmu_pages pages;
1955 LIST_HEAD(invalid_list);
1958 while (mmu_unsync_walk(parent, &pages)) {
1959 bool protected = false;
1961 for_each_sp(pages, sp, parents, i)
1962 protected |= rmap_write_protect(vcpu, sp->gfn);
1965 kvm_flush_remote_tlbs(vcpu->kvm);
1969 for_each_sp(pages, sp, parents, i) {
1970 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
1971 mmu_pages_clear_parents(&parents);
1973 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
1974 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1975 cond_resched_lock(&vcpu->kvm->mmu_lock);
1980 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1983 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1985 atomic_set(&sp->write_flooding_count, 0);
1988 static void clear_sp_write_flooding_count(u64 *spte)
1990 __clear_sp_write_flooding_count(sptep_to_sp(spte));
1993 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1998 unsigned int access)
2000 bool direct_mmu = vcpu->arch.mmu->direct_map;
2001 union kvm_mmu_page_role role;
2002 struct hlist_head *sp_list;
2004 struct kvm_mmu_page *sp;
2005 bool need_sync = false;
2008 LIST_HEAD(invalid_list);
2010 role = vcpu->arch.mmu->mmu_role.base;
2012 role.direct = direct;
2014 role.gpte_is_8_bytes = true;
2015 role.access = access;
2016 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2017 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2018 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2019 role.quadrant = quadrant;
2022 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2023 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2024 if (sp->gfn != gfn) {
2029 if (!need_sync && sp->unsync)
2032 if (sp->role.word != role.word)
2036 goto trace_get_page;
2039 /* The page is good, but __kvm_sync_page might still end
2040 * up zapping it. If so, break in order to rebuild it.
2042 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2045 WARN_ON(!list_empty(&invalid_list));
2046 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2049 if (sp->unsync_children)
2050 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2052 __clear_sp_write_flooding_count(sp);
2055 trace_kvm_mmu_get_page(sp, false);
2059 ++vcpu->kvm->stat.mmu_cache_miss;
2061 sp = kvm_mmu_alloc_page(vcpu, direct);
2065 hlist_add_head(&sp->hash_link, sp_list);
2068 * we should do write protection before syncing pages
2069 * otherwise the content of the synced shadow page may
2070 * be inconsistent with guest page table.
2072 account_shadowed(vcpu->kvm, sp);
2073 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2074 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2076 if (level > PG_LEVEL_4K && need_sync)
2077 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2079 trace_kvm_mmu_get_page(sp, true);
2081 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2083 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2084 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2088 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2089 struct kvm_vcpu *vcpu, hpa_t root,
2092 iterator->addr = addr;
2093 iterator->shadow_addr = root;
2094 iterator->level = vcpu->arch.mmu->shadow_root_level;
2096 if (iterator->level == PT64_ROOT_4LEVEL &&
2097 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2098 !vcpu->arch.mmu->direct_map)
2101 if (iterator->level == PT32E_ROOT_LEVEL) {
2103 * prev_root is currently only used for 64-bit hosts. So only
2104 * the active root_hpa is valid here.
2106 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2108 iterator->shadow_addr
2109 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2110 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2112 if (!iterator->shadow_addr)
2113 iterator->level = 0;
2117 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2118 struct kvm_vcpu *vcpu, u64 addr)
2120 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2124 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2126 if (iterator->level < PG_LEVEL_4K)
2129 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2130 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2134 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2137 if (is_last_spte(spte, iterator->level)) {
2138 iterator->level = 0;
2142 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2146 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2148 __shadow_walk_next(iterator, *iterator->sptep);
2151 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2152 struct kvm_mmu_page *sp)
2156 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2158 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2160 mmu_spte_set(sptep, spte);
2162 mmu_page_add_parent_pte(vcpu, sp, sptep);
2164 if (sp->unsync_children || sp->unsync)
2168 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2169 unsigned direct_access)
2171 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2172 struct kvm_mmu_page *child;
2175 * For the direct sp, if the guest pte's dirty bit
2176 * changed form clean to dirty, it will corrupt the
2177 * sp's access: allow writable in the read-only sp,
2178 * so we should update the spte at this point to get
2179 * a new sp with the correct access.
2181 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2182 if (child->role.access == direct_access)
2185 drop_parent_pte(child, sptep);
2186 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2190 /* Returns the number of zapped non-leaf child shadow pages. */
2191 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2192 u64 *spte, struct list_head *invalid_list)
2195 struct kvm_mmu_page *child;
2198 if (is_shadow_present_pte(pte)) {
2199 if (is_last_spte(pte, sp->role.level)) {
2200 drop_spte(kvm, spte);
2201 if (is_large_pte(pte))
2204 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2205 drop_parent_pte(child, spte);
2208 * Recursively zap nested TDP SPs, parentless SPs are
2209 * unlikely to be used again in the near future. This
2210 * avoids retaining a large number of stale nested SPs.
2212 if (tdp_enabled && invalid_list &&
2213 child->role.guest_mode && !child->parent_ptes.val)
2214 return kvm_mmu_prepare_zap_page(kvm, child,
2217 } else if (is_mmio_spte(pte)) {
2218 mmu_spte_clear_no_track(spte);
2223 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2224 struct kvm_mmu_page *sp,
2225 struct list_head *invalid_list)
2230 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2231 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2236 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2239 struct rmap_iterator iter;
2241 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2242 drop_parent_pte(sp, sptep);
2245 static int mmu_zap_unsync_children(struct kvm *kvm,
2246 struct kvm_mmu_page *parent,
2247 struct list_head *invalid_list)
2250 struct mmu_page_path parents;
2251 struct kvm_mmu_pages pages;
2253 if (parent->role.level == PG_LEVEL_4K)
2256 while (mmu_unsync_walk(parent, &pages)) {
2257 struct kvm_mmu_page *sp;
2259 for_each_sp(pages, sp, parents, i) {
2260 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2261 mmu_pages_clear_parents(&parents);
2269 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2270 struct kvm_mmu_page *sp,
2271 struct list_head *invalid_list,
2276 trace_kvm_mmu_prepare_zap_page(sp);
2277 ++kvm->stat.mmu_shadow_zapped;
2278 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2279 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2280 kvm_mmu_unlink_parents(kvm, sp);
2282 /* Zapping children means active_mmu_pages has become unstable. */
2283 list_unstable = *nr_zapped;
2285 if (!sp->role.invalid && !sp->role.direct)
2286 unaccount_shadowed(kvm, sp);
2289 kvm_unlink_unsync_page(kvm, sp);
2290 if (!sp->root_count) {
2295 * Already invalid pages (previously active roots) are not on
2296 * the active page list. See list_del() in the "else" case of
2299 if (sp->role.invalid)
2300 list_add(&sp->link, invalid_list);
2302 list_move(&sp->link, invalid_list);
2303 kvm_mod_used_mmu_pages(kvm, -1);
2306 * Remove the active root from the active page list, the root
2307 * will be explicitly freed when the root_count hits zero.
2309 list_del(&sp->link);
2312 * Obsolete pages cannot be used on any vCPUs, see the comment
2313 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2314 * treats invalid shadow pages as being obsolete.
2316 if (!is_obsolete_sp(kvm, sp))
2317 kvm_reload_remote_mmus(kvm);
2320 if (sp->lpage_disallowed)
2321 unaccount_huge_nx_page(kvm, sp);
2323 sp->role.invalid = 1;
2324 return list_unstable;
2327 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2328 struct list_head *invalid_list)
2332 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2336 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2337 struct list_head *invalid_list)
2339 struct kvm_mmu_page *sp, *nsp;
2341 if (list_empty(invalid_list))
2345 * We need to make sure everyone sees our modifications to
2346 * the page tables and see changes to vcpu->mode here. The barrier
2347 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2348 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2350 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2351 * guest mode and/or lockless shadow page table walks.
2353 kvm_flush_remote_tlbs(kvm);
2355 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2356 WARN_ON(!sp->role.invalid || sp->root_count);
2357 kvm_mmu_free_page(sp);
2361 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2362 unsigned long nr_to_zap)
2364 unsigned long total_zapped = 0;
2365 struct kvm_mmu_page *sp, *tmp;
2366 LIST_HEAD(invalid_list);
2370 if (list_empty(&kvm->arch.active_mmu_pages))
2374 list_for_each_entry_safe(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2376 * Don't zap active root pages, the page itself can't be freed
2377 * and zapping it will just force vCPUs to realloc and reload.
2382 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2384 total_zapped += nr_zapped;
2385 if (total_zapped >= nr_to_zap)
2392 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2394 kvm->stat.mmu_recycled += total_zapped;
2395 return total_zapped;
2398 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2400 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2401 return kvm->arch.n_max_mmu_pages -
2402 kvm->arch.n_used_mmu_pages;
2407 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2409 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2411 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2414 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2416 if (!kvm_mmu_available_pages(vcpu->kvm))
2422 * Changing the number of mmu pages allocated to the vm
2423 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2425 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2427 spin_lock(&kvm->mmu_lock);
2429 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2430 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2433 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2436 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2438 spin_unlock(&kvm->mmu_lock);
2441 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2443 struct kvm_mmu_page *sp;
2444 LIST_HEAD(invalid_list);
2447 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2449 spin_lock(&kvm->mmu_lock);
2450 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2451 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2454 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2456 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2457 spin_unlock(&kvm->mmu_lock);
2461 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2463 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2465 trace_kvm_mmu_unsync_page(sp);
2466 ++vcpu->kvm->stat.mmu_unsync;
2469 kvm_mmu_mark_parents_unsync(sp);
2472 bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2475 struct kvm_mmu_page *sp;
2477 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2480 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2487 WARN_ON(sp->role.level != PG_LEVEL_4K);
2488 kvm_unsync_page(vcpu, sp);
2492 * We need to ensure that the marking of unsync pages is visible
2493 * before the SPTE is updated to allow writes because
2494 * kvm_mmu_sync_roots() checks the unsync flags without holding
2495 * the MMU lock and so can race with this. If the SPTE was updated
2496 * before the page had been marked as unsync-ed, something like the
2497 * following could happen:
2500 * ---------------------------------------------------------------------
2501 * 1.2 Host updates SPTE
2503 * 2.1 Guest writes a GPTE for GVA X.
2504 * (GPTE being in the guest page table shadowed
2505 * by the SP from CPU 1.)
2506 * This reads SPTE during the page table walk.
2507 * Since SPTE.W is read as 1, there is no
2510 * 2.2 Guest issues TLB flush.
2511 * That causes a VM Exit.
2513 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2514 * Since it is false, so it just returns.
2516 * 2.4 Guest accesses GVA X.
2517 * Since the mapping in the SP was not updated,
2518 * so the old mapping for GVA X incorrectly
2522 * (sp->unsync = true)
2524 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2525 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2526 * pairs with this write barrier.
2533 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2534 unsigned int pte_access, int level,
2535 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2536 bool can_unsync, bool host_writable)
2539 struct kvm_mmu_page *sp;
2542 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2545 sp = sptep_to_sp(sptep);
2547 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2548 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2550 if (spte & PT_WRITABLE_MASK)
2551 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2554 ret |= SET_SPTE_SPURIOUS;
2555 else if (mmu_spte_update(sptep, spte))
2556 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2560 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2561 unsigned int pte_access, bool write_fault, int level,
2562 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2565 int was_rmapped = 0;
2568 int ret = RET_PF_FIXED;
2571 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2572 *sptep, write_fault, gfn);
2574 if (is_shadow_present_pte(*sptep)) {
2576 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2577 * the parent of the now unreachable PTE.
2579 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2580 struct kvm_mmu_page *child;
2583 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2584 drop_parent_pte(child, sptep);
2586 } else if (pfn != spte_to_pfn(*sptep)) {
2587 pgprintk("hfn old %llx new %llx\n",
2588 spte_to_pfn(*sptep), pfn);
2589 drop_spte(vcpu->kvm, sptep);
2595 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2596 speculative, true, host_writable);
2597 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2599 ret = RET_PF_EMULATE;
2600 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2603 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2604 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2605 KVM_PAGES_PER_HPAGE(level));
2607 if (unlikely(is_mmio_spte(*sptep)))
2608 ret = RET_PF_EMULATE;
2611 * The fault is fully spurious if and only if the new SPTE and old SPTE
2612 * are identical, and emulation is not required.
2614 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2615 WARN_ON_ONCE(!was_rmapped);
2616 return RET_PF_SPURIOUS;
2619 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2620 trace_kvm_mmu_set_spte(level, gfn, sptep);
2621 if (!was_rmapped && is_large_pte(*sptep))
2622 ++vcpu->kvm->stat.lpages;
2624 if (is_shadow_present_pte(*sptep)) {
2626 rmap_count = rmap_add(vcpu, sptep, gfn);
2627 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2628 rmap_recycle(vcpu, sptep, gfn);
2635 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2638 struct kvm_memory_slot *slot;
2640 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2642 return KVM_PFN_ERR_FAULT;
2644 return gfn_to_pfn_memslot_atomic(slot, gfn);
2647 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2648 struct kvm_mmu_page *sp,
2649 u64 *start, u64 *end)
2651 struct page *pages[PTE_PREFETCH_NUM];
2652 struct kvm_memory_slot *slot;
2653 unsigned int access = sp->role.access;
2657 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2658 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2662 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2666 for (i = 0; i < ret; i++, gfn++, start++) {
2667 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2668 page_to_pfn(pages[i]), true, true);
2675 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2676 struct kvm_mmu_page *sp, u64 *sptep)
2678 u64 *spte, *start = NULL;
2681 WARN_ON(!sp->role.direct);
2683 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2686 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2687 if (is_shadow_present_pte(*spte) || spte == sptep) {
2690 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2698 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2700 struct kvm_mmu_page *sp;
2702 sp = sptep_to_sp(sptep);
2705 * Without accessed bits, there's no way to distinguish between
2706 * actually accessed translations and prefetched, so disable pte
2707 * prefetch if accessed bits aren't available.
2709 if (sp_ad_disabled(sp))
2712 if (sp->role.level > PG_LEVEL_4K)
2715 __direct_pte_prefetch(vcpu, sp, sptep);
2718 static int host_pfn_mapping_level(struct kvm_vcpu *vcpu, gfn_t gfn,
2719 kvm_pfn_t pfn, struct kvm_memory_slot *slot)
2725 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2729 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2730 * is not solely for performance, it's also necessary to avoid the
2731 * "writable" check in __gfn_to_hva_many(), which will always fail on
2732 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2733 * page fault steps have already verified the guest isn't writing a
2734 * read-only memslot.
2736 hva = __gfn_to_hva_memslot(slot, gfn);
2738 pte = lookup_address_in_mm(vcpu->kvm->mm, hva, &level);
2745 int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2746 int max_level, kvm_pfn_t *pfnp,
2747 bool huge_page_disallowed, int *req_level)
2749 struct kvm_memory_slot *slot;
2750 struct kvm_lpage_info *linfo;
2751 kvm_pfn_t pfn = *pfnp;
2755 *req_level = PG_LEVEL_4K;
2757 if (unlikely(max_level == PG_LEVEL_4K))
2760 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
2763 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2767 max_level = min(max_level, max_huge_page_level);
2768 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2769 linfo = lpage_info_slot(gfn, slot, max_level);
2770 if (!linfo->disallow_lpage)
2774 if (max_level == PG_LEVEL_4K)
2777 level = host_pfn_mapping_level(vcpu, gfn, pfn, slot);
2778 if (level == PG_LEVEL_4K)
2781 *req_level = level = min(level, max_level);
2784 * Enforce the iTLB multihit workaround after capturing the requested
2785 * level, which will be used to do precise, accurate accounting.
2787 if (huge_page_disallowed)
2791 * mmu_notifier_retry() was successful and mmu_lock is held, so
2792 * the pmd can't be split from under us.
2794 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2795 VM_BUG_ON((gfn & mask) != (pfn & mask));
2796 *pfnp = pfn & ~mask;
2801 void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2802 kvm_pfn_t *pfnp, int *goal_levelp)
2804 int level = *goal_levelp;
2806 if (cur_level == level && level > PG_LEVEL_4K &&
2807 is_shadow_present_pte(spte) &&
2808 !is_large_pte(spte)) {
2810 * A small SPTE exists for this pfn, but FNAME(fetch)
2811 * and __direct_map would like to create a large PTE
2812 * instead: just force them to go down another level,
2813 * patching back for them into pfn the next 9 bits of
2816 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2817 KVM_PAGES_PER_HPAGE(level - 1);
2818 *pfnp |= gfn & page_mask;
2823 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
2824 int map_writable, int max_level, kvm_pfn_t pfn,
2825 bool prefault, bool is_tdp)
2827 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2828 bool write = error_code & PFERR_WRITE_MASK;
2829 bool exec = error_code & PFERR_FETCH_MASK;
2830 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
2831 struct kvm_shadow_walk_iterator it;
2832 struct kvm_mmu_page *sp;
2833 int level, req_level, ret;
2834 gfn_t gfn = gpa >> PAGE_SHIFT;
2835 gfn_t base_gfn = gfn;
2837 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
2838 return RET_PF_RETRY;
2840 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2841 huge_page_disallowed, &req_level);
2843 trace_kvm_mmu_spte_requested(gpa, level, pfn);
2844 for_each_shadow_entry(vcpu, gpa, it) {
2846 * We cannot overwrite existing page tables with an NX
2847 * large page, as the leaf could be executable.
2849 if (nx_huge_page_workaround_enabled)
2850 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
2853 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2854 if (it.level == level)
2857 drop_large_spte(vcpu, it.sptep);
2858 if (!is_shadow_present_pte(*it.sptep)) {
2859 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2860 it.level - 1, true, ACC_ALL);
2862 link_shadow_page(vcpu, it.sptep, sp);
2863 if (is_tdp && huge_page_disallowed &&
2864 req_level >= it.level)
2865 account_huge_nx_page(vcpu->kvm, sp);
2869 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2870 write, level, base_gfn, pfn, prefault,
2872 if (ret == RET_PF_SPURIOUS)
2875 direct_pte_prefetch(vcpu, it.sptep);
2876 ++vcpu->stat.pf_fixed;
2880 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2882 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2885 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2888 * Do not cache the mmio info caused by writing the readonly gfn
2889 * into the spte otherwise read access on readonly gfn also can
2890 * caused mmio page fault and treat it as mmio access.
2892 if (pfn == KVM_PFN_ERR_RO_FAULT)
2893 return RET_PF_EMULATE;
2895 if (pfn == KVM_PFN_ERR_HWPOISON) {
2896 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2897 return RET_PF_RETRY;
2903 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2904 kvm_pfn_t pfn, unsigned int access,
2907 /* The pfn is invalid, report the error! */
2908 if (unlikely(is_error_pfn(pfn))) {
2909 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2913 if (unlikely(is_noslot_pfn(pfn)))
2914 vcpu_cache_mmio_info(vcpu, gva, gfn,
2915 access & shadow_mmio_access_mask);
2920 static bool page_fault_can_be_fast(u32 error_code)
2923 * Do not fix the mmio spte with invalid generation number which
2924 * need to be updated by slow page fault path.
2926 if (unlikely(error_code & PFERR_RSVD_MASK))
2929 /* See if the page fault is due to an NX violation */
2930 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
2931 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
2935 * #PF can be fast if:
2936 * 1. The shadow page table entry is not present, which could mean that
2937 * the fault is potentially caused by access tracking (if enabled).
2938 * 2. The shadow page table entry is present and the fault
2939 * is caused by write-protect, that means we just need change the W
2940 * bit of the spte which can be done out of mmu-lock.
2942 * However, if access tracking is disabled we know that a non-present
2943 * page must be a genuine page fault where we have to create a new SPTE.
2944 * So, if access tracking is disabled, we return true only for write
2945 * accesses to a present page.
2948 return shadow_acc_track_mask != 0 ||
2949 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
2950 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
2954 * Returns true if the SPTE was fixed successfully. Otherwise,
2955 * someone else modified the SPTE from its original value.
2958 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2959 u64 *sptep, u64 old_spte, u64 new_spte)
2963 WARN_ON(!sp->role.direct);
2966 * Theoretically we could also set dirty bit (and flush TLB) here in
2967 * order to eliminate unnecessary PML logging. See comments in
2968 * set_spte. But fast_page_fault is very unlikely to happen with PML
2969 * enabled, so we do not do this. This might result in the same GPA
2970 * to be logged in PML buffer again when the write really happens, and
2971 * eventually to be called by mark_page_dirty twice. But it's also no
2972 * harm. This also avoids the TLB flush needed after setting dirty bit
2973 * so non-PML cases won't be impacted.
2975 * Compare with set_spte where instead shadow_dirty_mask is set.
2977 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
2980 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
2982 * The gfn of direct spte is stable since it is
2983 * calculated by sp->gfn.
2985 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2986 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2992 static bool is_access_allowed(u32 fault_err_code, u64 spte)
2994 if (fault_err_code & PFERR_FETCH_MASK)
2995 return is_executable_pte(spte);
2997 if (fault_err_code & PFERR_WRITE_MASK)
2998 return is_writable_pte(spte);
3000 /* Fault was on Read access */
3001 return spte & PT_PRESENT_MASK;
3005 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3007 static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3010 struct kvm_shadow_walk_iterator iterator;
3011 struct kvm_mmu_page *sp;
3012 int ret = RET_PF_INVALID;
3014 uint retry_count = 0;
3016 if (!page_fault_can_be_fast(error_code))
3019 walk_shadow_page_lockless_begin(vcpu);
3024 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3025 if (!is_shadow_present_pte(spte))
3028 sp = sptep_to_sp(iterator.sptep);
3029 if (!is_last_spte(spte, sp->role.level))
3033 * Check whether the memory access that caused the fault would
3034 * still cause it if it were to be performed right now. If not,
3035 * then this is a spurious fault caused by TLB lazily flushed,
3036 * or some other CPU has already fixed the PTE after the
3037 * current CPU took the fault.
3039 * Need not check the access of upper level table entries since
3040 * they are always ACC_ALL.
3042 if (is_access_allowed(error_code, spte)) {
3043 ret = RET_PF_SPURIOUS;
3049 if (is_access_track_spte(spte))
3050 new_spte = restore_acc_track_spte(new_spte);
3053 * Currently, to simplify the code, write-protection can
3054 * be removed in the fast path only if the SPTE was
3055 * write-protected for dirty-logging or access tracking.
3057 if ((error_code & PFERR_WRITE_MASK) &&
3058 spte_can_locklessly_be_made_writable(spte)) {
3059 new_spte |= PT_WRITABLE_MASK;
3062 * Do not fix write-permission on the large spte. Since
3063 * we only dirty the first page into the dirty-bitmap in
3064 * fast_pf_fix_direct_spte(), other pages are missed
3065 * if its slot has dirty logging enabled.
3067 * Instead, we let the slow page fault path create a
3068 * normal spte to fix the access.
3070 * See the comments in kvm_arch_commit_memory_region().
3072 if (sp->role.level > PG_LEVEL_4K)
3076 /* Verify that the fault can be handled in the fast path */
3077 if (new_spte == spte ||
3078 !is_access_allowed(error_code, new_spte))
3082 * Currently, fast page fault only works for direct mapping
3083 * since the gfn is not stable for indirect shadow page. See
3084 * Documentation/virt/kvm/locking.rst to get more detail.
3086 if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte,
3092 if (++retry_count > 4) {
3093 printk_once(KERN_WARNING
3094 "kvm: Fast #PF retrying more than 4 times.\n");
3100 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3102 walk_shadow_page_lockless_end(vcpu);
3107 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3108 struct list_head *invalid_list)
3110 struct kvm_mmu_page *sp;
3112 if (!VALID_PAGE(*root_hpa))
3115 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3117 if (kvm_mmu_put_root(kvm, sp)) {
3118 if (sp->tdp_mmu_page)
3119 kvm_tdp_mmu_free_root(kvm, sp);
3120 else if (sp->role.invalid)
3121 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3124 *root_hpa = INVALID_PAGE;
3127 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3128 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3129 ulong roots_to_free)
3131 struct kvm *kvm = vcpu->kvm;
3133 LIST_HEAD(invalid_list);
3134 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3136 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3138 /* Before acquiring the MMU lock, see if we need to do any real work. */
3139 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3140 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3141 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3142 VALID_PAGE(mmu->prev_roots[i].hpa))
3145 if (i == KVM_MMU_NUM_PREV_ROOTS)
3149 spin_lock(&kvm->mmu_lock);
3151 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3152 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3153 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3156 if (free_active_root) {
3157 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3158 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3159 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3161 for (i = 0; i < 4; ++i)
3162 if (mmu->pae_root[i] != 0)
3163 mmu_free_root_page(kvm,
3166 mmu->root_hpa = INVALID_PAGE;
3171 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3172 spin_unlock(&kvm->mmu_lock);
3174 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3176 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3180 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3181 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3188 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3189 u8 level, bool direct)
3191 struct kvm_mmu_page *sp;
3193 spin_lock(&vcpu->kvm->mmu_lock);
3195 if (make_mmu_pages_available(vcpu)) {
3196 spin_unlock(&vcpu->kvm->mmu_lock);
3197 return INVALID_PAGE;
3199 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3202 spin_unlock(&vcpu->kvm->mmu_lock);
3203 return __pa(sp->spt);
3206 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3208 u8 shadow_root_level = vcpu->arch.mmu->shadow_root_level;
3212 if (vcpu->kvm->arch.tdp_mmu_enabled) {
3213 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3215 if (!VALID_PAGE(root))
3217 vcpu->arch.mmu->root_hpa = root;
3218 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3219 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level,
3222 if (!VALID_PAGE(root))
3224 vcpu->arch.mmu->root_hpa = root;
3225 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3226 for (i = 0; i < 4; ++i) {
3227 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
3229 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3230 i << 30, PT32_ROOT_LEVEL, true);
3231 if (!VALID_PAGE(root))
3233 vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK;
3235 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3239 /* root_pgd is ignored for direct MMUs. */
3240 vcpu->arch.mmu->root_pgd = 0;
3245 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3248 gfn_t root_gfn, root_pgd;
3252 root_pgd = vcpu->arch.mmu->get_guest_pgd(vcpu);
3253 root_gfn = root_pgd >> PAGE_SHIFT;
3255 if (mmu_check_root(vcpu, root_gfn))
3259 * Do we shadow a long mode page table? If so we need to
3260 * write-protect the guests page table root.
3262 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3263 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->root_hpa));
3265 root = mmu_alloc_root(vcpu, root_gfn, 0,
3266 vcpu->arch.mmu->shadow_root_level, false);
3267 if (!VALID_PAGE(root))
3269 vcpu->arch.mmu->root_hpa = root;
3274 * We shadow a 32 bit page table. This may be a legacy 2-level
3275 * or a PAE 3-level page table. In either case we need to be aware that
3276 * the shadow page table may be a PAE or a long mode page table.
3278 pm_mask = PT_PRESENT_MASK;
3279 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3280 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3282 for (i = 0; i < 4; ++i) {
3283 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
3284 if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) {
3285 pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i);
3286 if (!(pdptr & PT_PRESENT_MASK)) {
3287 vcpu->arch.mmu->pae_root[i] = 0;
3290 root_gfn = pdptr >> PAGE_SHIFT;
3291 if (mmu_check_root(vcpu, root_gfn))
3295 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3296 PT32_ROOT_LEVEL, false);
3297 if (!VALID_PAGE(root))
3299 vcpu->arch.mmu->pae_root[i] = root | pm_mask;
3301 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3304 * If we shadow a 32 bit page table with a long mode page
3305 * table we enter this path.
3307 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3308 if (vcpu->arch.mmu->lm_root == NULL) {
3310 * The additional page necessary for this is only
3311 * allocated on demand.
3316 lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3317 if (lm_root == NULL)
3320 lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask;
3322 vcpu->arch.mmu->lm_root = lm_root;
3325 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root);
3329 vcpu->arch.mmu->root_pgd = root_pgd;
3334 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3336 if (vcpu->arch.mmu->direct_map)
3337 return mmu_alloc_direct_roots(vcpu);
3339 return mmu_alloc_shadow_roots(vcpu);
3342 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3345 struct kvm_mmu_page *sp;
3347 if (vcpu->arch.mmu->direct_map)
3350 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3353 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3355 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3356 hpa_t root = vcpu->arch.mmu->root_hpa;
3357 sp = to_shadow_page(root);
3360 * Even if another CPU was marking the SP as unsync-ed
3361 * simultaneously, any guest page table changes are not
3362 * guaranteed to be visible anyway until this VCPU issues a TLB
3363 * flush strictly after those changes are made. We only need to
3364 * ensure that the other CPU sets these flags before any actual
3365 * changes to the page tables are made. The comments in
3366 * mmu_need_write_protect() describe what could go wrong if this
3367 * requirement isn't satisfied.
3369 if (!smp_load_acquire(&sp->unsync) &&
3370 !smp_load_acquire(&sp->unsync_children))
3373 spin_lock(&vcpu->kvm->mmu_lock);
3374 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3376 mmu_sync_children(vcpu, sp);
3378 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3379 spin_unlock(&vcpu->kvm->mmu_lock);
3383 spin_lock(&vcpu->kvm->mmu_lock);
3384 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3386 for (i = 0; i < 4; ++i) {
3387 hpa_t root = vcpu->arch.mmu->pae_root[i];
3389 if (root && VALID_PAGE(root)) {
3390 root &= PT64_BASE_ADDR_MASK;
3391 sp = to_shadow_page(root);
3392 mmu_sync_children(vcpu, sp);
3396 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3397 spin_unlock(&vcpu->kvm->mmu_lock);
3399 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3401 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3402 u32 access, struct x86_exception *exception)
3405 exception->error_code = 0;
3409 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3411 struct x86_exception *exception)
3414 exception->error_code = 0;
3415 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3419 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3421 int bit7 = (pte >> 7) & 1;
3423 return pte & rsvd_check->rsvd_bits_mask[bit7][level-1];
3426 static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte)
3428 return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
3431 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3434 * A nested guest cannot use the MMIO cache if it is using nested
3435 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3437 if (mmu_is_nested(vcpu))
3441 return vcpu_match_mmio_gpa(vcpu, addr);
3443 return vcpu_match_mmio_gva(vcpu, addr);
3446 /* return true if reserved bit is detected on spte. */
3448 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3450 struct kvm_shadow_walk_iterator iterator;
3451 u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull;
3452 struct rsvd_bits_validate *rsvd_check;
3454 bool reserved = false;
3456 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3458 walk_shadow_page_lockless_begin(vcpu);
3460 for (shadow_walk_init(&iterator, vcpu, addr),
3461 leaf = root = iterator.level;
3462 shadow_walk_okay(&iterator);
3463 __shadow_walk_next(&iterator, spte)) {
3464 spte = mmu_spte_get_lockless(iterator.sptep);
3466 sptes[leaf - 1] = spte;
3469 if (!is_shadow_present_pte(spte))
3473 * Use a bitwise-OR instead of a logical-OR to aggregate the
3474 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3475 * adding a Jcc in the loop.
3477 reserved |= __is_bad_mt_xwr(rsvd_check, spte) |
3478 __is_rsvd_bits_set(rsvd_check, spte, iterator.level);
3481 walk_shadow_page_lockless_end(vcpu);
3484 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3486 while (root > leaf) {
3487 pr_err("------ spte 0x%llx level %d.\n",
3488 sptes[root - 1], root);
3497 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3502 if (mmio_info_in_cache(vcpu, addr, direct))
3503 return RET_PF_EMULATE;
3505 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3506 if (WARN_ON(reserved))
3509 if (is_mmio_spte(spte)) {
3510 gfn_t gfn = get_mmio_spte_gfn(spte);
3511 unsigned int access = get_mmio_spte_access(spte);
3513 if (!check_mmio_spte(vcpu, spte))
3514 return RET_PF_INVALID;
3519 trace_handle_mmio_page_fault(addr, gfn, access);
3520 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3521 return RET_PF_EMULATE;
3525 * If the page table is zapped by other cpus, let CPU fault again on
3528 return RET_PF_RETRY;
3531 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3532 u32 error_code, gfn_t gfn)
3534 if (unlikely(error_code & PFERR_RSVD_MASK))
3537 if (!(error_code & PFERR_PRESENT_MASK) ||
3538 !(error_code & PFERR_WRITE_MASK))
3542 * guest is writing the page which is write tracked which can
3543 * not be fixed by page fault handler.
3545 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3551 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3553 struct kvm_shadow_walk_iterator iterator;
3556 walk_shadow_page_lockless_begin(vcpu);
3557 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3558 clear_sp_write_flooding_count(iterator.sptep);
3559 if (!is_shadow_present_pte(spte))
3562 walk_shadow_page_lockless_end(vcpu);
3565 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3568 struct kvm_arch_async_pf arch;
3570 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3572 arch.direct_map = vcpu->arch.mmu->direct_map;
3573 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3575 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3576 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3579 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3580 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, bool write,
3583 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3586 /* Don't expose private memslots to L2. */
3587 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3588 *pfn = KVM_PFN_NOSLOT;
3594 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3596 return false; /* *pfn has correct page already */
3598 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3599 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
3600 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3601 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
3602 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3604 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
3608 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3612 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3613 bool prefault, int max_level, bool is_tdp)
3615 bool write = error_code & PFERR_WRITE_MASK;
3618 gfn_t gfn = gpa >> PAGE_SHIFT;
3619 unsigned long mmu_seq;
3623 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3624 return RET_PF_EMULATE;
3626 if (!is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) {
3627 r = fast_page_fault(vcpu, gpa, error_code);
3628 if (r != RET_PF_INVALID)
3632 r = mmu_topup_memory_caches(vcpu, false);
3636 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3639 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3640 return RET_PF_RETRY;
3642 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
3646 spin_lock(&vcpu->kvm->mmu_lock);
3647 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3649 r = make_mmu_pages_available(vcpu);
3653 if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
3654 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
3657 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
3661 spin_unlock(&vcpu->kvm->mmu_lock);
3662 kvm_release_pfn_clean(pfn);
3666 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
3667 u32 error_code, bool prefault)
3669 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
3671 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3672 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3673 PG_LEVEL_2M, false);
3676 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3677 u64 fault_address, char *insn, int insn_len)
3680 u32 flags = vcpu->arch.apf.host_apf_flags;
3682 #ifndef CONFIG_X86_64
3683 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3684 if (WARN_ON_ONCE(fault_address >> 32))
3688 vcpu->arch.l1tf_flush_l1d = true;
3690 trace_kvm_page_fault(fault_address, error_code);
3692 if (kvm_event_needs_reinjection(vcpu))
3693 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3694 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3696 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
3697 vcpu->arch.apf.host_apf_flags = 0;
3698 local_irq_disable();
3699 kvm_async_pf_task_wait_schedule(fault_address);
3702 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
3707 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3709 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3714 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3715 max_level > PG_LEVEL_4K;
3717 int page_num = KVM_PAGES_PER_HPAGE(max_level);
3718 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
3720 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
3724 return direct_page_fault(vcpu, gpa, error_code, prefault,
3728 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3729 struct kvm_mmu *context)
3731 context->page_fault = nonpaging_page_fault;
3732 context->gva_to_gpa = nonpaging_gva_to_gpa;
3733 context->sync_page = nonpaging_sync_page;
3734 context->invlpg = NULL;
3735 context->update_pte = nonpaging_update_pte;
3736 context->root_level = 0;
3737 context->shadow_root_level = PT32E_ROOT_LEVEL;
3738 context->direct_map = true;
3739 context->nx = false;
3742 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
3743 union kvm_mmu_page_role role)
3745 return (role.direct || pgd == root->pgd) &&
3746 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
3747 role.word == to_shadow_page(root->hpa)->role.word;
3751 * Find out if a previously cached root matching the new pgd/role is available.
3752 * The current root is also inserted into the cache.
3753 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3755 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3756 * false is returned. This root should now be freed by the caller.
3758 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3759 union kvm_mmu_page_role new_role)
3762 struct kvm_mmu_root_info root;
3763 struct kvm_mmu *mmu = vcpu->arch.mmu;
3765 root.pgd = mmu->root_pgd;
3766 root.hpa = mmu->root_hpa;
3768 if (is_root_usable(&root, new_pgd, new_role))
3771 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3772 swap(root, mmu->prev_roots[i]);
3774 if (is_root_usable(&root, new_pgd, new_role))
3778 mmu->root_hpa = root.hpa;
3779 mmu->root_pgd = root.pgd;
3781 return i < KVM_MMU_NUM_PREV_ROOTS;
3784 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3785 union kvm_mmu_page_role new_role)
3787 struct kvm_mmu *mmu = vcpu->arch.mmu;
3790 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
3791 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
3792 * later if necessary.
3794 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3795 mmu->root_level >= PT64_ROOT_4LEVEL)
3796 return cached_root_available(vcpu, new_pgd, new_role);
3801 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3802 union kvm_mmu_page_role new_role,
3803 bool skip_tlb_flush, bool skip_mmu_sync)
3805 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
3806 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
3811 * It's possible that the cached previous root page is obsolete because
3812 * of a change in the MMU generation number. However, changing the
3813 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
3814 * free the root set here and allocate a new one.
3816 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
3818 if (!skip_mmu_sync || force_flush_and_sync_on_reuse)
3819 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
3820 if (!skip_tlb_flush || force_flush_and_sync_on_reuse)
3821 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3824 * The last MMIO access's GVA and GPA are cached in the VCPU. When
3825 * switching to a new CR3, that GVA->GPA mapping may no longer be
3826 * valid. So clear any cached MMIO info even when we don't need to sync
3827 * the shadow page tables.
3829 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3831 __clear_sp_write_flooding_count(to_shadow_page(vcpu->arch.mmu->root_hpa));
3834 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush,
3837 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu),
3838 skip_tlb_flush, skip_mmu_sync);
3840 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
3842 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3844 return kvm_read_cr3(vcpu);
3847 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3848 unsigned int access, int *nr_present)
3850 if (unlikely(is_mmio_spte(*sptep))) {
3851 if (gfn != get_mmio_spte_gfn(*sptep)) {
3852 mmu_spte_clear_no_track(sptep);
3857 mark_mmio_spte(vcpu, sptep, gfn, access);
3864 static inline bool is_last_gpte(struct kvm_mmu *mmu,
3865 unsigned level, unsigned gpte)
3868 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3869 * If it is clear, there are no large pages at this level, so clear
3870 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3872 gpte &= level - mmu->last_nonleaf_level;
3875 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
3876 * iff level <= PG_LEVEL_4K, which for our purpose means
3877 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
3879 gpte |= level - PG_LEVEL_4K - 1;
3881 return gpte & PT_PAGE_SIZE_MASK;
3884 #define PTTYPE_EPT 18 /* arbitrary */
3885 #define PTTYPE PTTYPE_EPT
3886 #include "paging_tmpl.h"
3890 #include "paging_tmpl.h"
3894 #include "paging_tmpl.h"
3898 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3899 struct rsvd_bits_validate *rsvd_check,
3900 int maxphyaddr, int level, bool nx, bool gbpages,
3903 u64 exb_bit_rsvd = 0;
3904 u64 gbpages_bit_rsvd = 0;
3905 u64 nonleaf_bit8_rsvd = 0;
3907 rsvd_check->bad_mt_xwr = 0;
3910 exb_bit_rsvd = rsvd_bits(63, 63);
3912 gbpages_bit_rsvd = rsvd_bits(7, 7);
3915 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3916 * leaf entries) on AMD CPUs only.
3919 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3922 case PT32_ROOT_LEVEL:
3923 /* no rsvd bits for 2 level 4K page table entries */
3924 rsvd_check->rsvd_bits_mask[0][1] = 0;
3925 rsvd_check->rsvd_bits_mask[0][0] = 0;
3926 rsvd_check->rsvd_bits_mask[1][0] =
3927 rsvd_check->rsvd_bits_mask[0][0];
3930 rsvd_check->rsvd_bits_mask[1][1] = 0;
3934 if (is_cpuid_PSE36())
3935 /* 36bits PSE 4MB page */
3936 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3938 /* 32 bits PSE 4MB page */
3939 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3941 case PT32E_ROOT_LEVEL:
3942 rsvd_check->rsvd_bits_mask[0][2] =
3943 rsvd_bits(maxphyaddr, 63) |
3944 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3945 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3946 rsvd_bits(maxphyaddr, 62); /* PDE */
3947 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3948 rsvd_bits(maxphyaddr, 62); /* PTE */
3949 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3950 rsvd_bits(maxphyaddr, 62) |
3951 rsvd_bits(13, 20); /* large page */
3952 rsvd_check->rsvd_bits_mask[1][0] =
3953 rsvd_check->rsvd_bits_mask[0][0];
3955 case PT64_ROOT_5LEVEL:
3956 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
3957 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3958 rsvd_bits(maxphyaddr, 51);
3959 rsvd_check->rsvd_bits_mask[1][4] =
3960 rsvd_check->rsvd_bits_mask[0][4];
3962 case PT64_ROOT_4LEVEL:
3963 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3964 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3965 rsvd_bits(maxphyaddr, 51);
3966 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3968 rsvd_bits(maxphyaddr, 51);
3969 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3970 rsvd_bits(maxphyaddr, 51);
3971 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3972 rsvd_bits(maxphyaddr, 51);
3973 rsvd_check->rsvd_bits_mask[1][3] =
3974 rsvd_check->rsvd_bits_mask[0][3];
3975 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3976 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3978 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3979 rsvd_bits(maxphyaddr, 51) |
3980 rsvd_bits(13, 20); /* large page */
3981 rsvd_check->rsvd_bits_mask[1][0] =
3982 rsvd_check->rsvd_bits_mask[0][0];
3987 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3988 struct kvm_mmu *context)
3990 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
3991 cpuid_maxphyaddr(vcpu), context->root_level,
3993 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
3995 guest_cpuid_is_amd_or_hygon(vcpu));
3999 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4000 int maxphyaddr, bool execonly)
4004 rsvd_check->rsvd_bits_mask[0][4] =
4005 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4006 rsvd_check->rsvd_bits_mask[0][3] =
4007 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4008 rsvd_check->rsvd_bits_mask[0][2] =
4009 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4010 rsvd_check->rsvd_bits_mask[0][1] =
4011 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4012 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4015 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4016 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4017 rsvd_check->rsvd_bits_mask[1][2] =
4018 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4019 rsvd_check->rsvd_bits_mask[1][1] =
4020 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4021 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4023 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4024 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4025 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4026 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4027 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4029 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4030 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4032 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4035 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4036 struct kvm_mmu *context, bool execonly)
4038 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4039 cpuid_maxphyaddr(vcpu), execonly);
4043 * the page table on host is the shadow page table for the page
4044 * table in guest or amd nested guest, its mmu features completely
4045 * follow the features in guest.
4048 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4050 bool uses_nx = context->nx ||
4051 context->mmu_role.base.smep_andnot_wp;
4052 struct rsvd_bits_validate *shadow_zero_check;
4056 * Passing "true" to the last argument is okay; it adds a check
4057 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4059 shadow_zero_check = &context->shadow_zero_check;
4060 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4062 context->shadow_root_level, uses_nx,
4063 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4064 is_pse(vcpu), true);
4066 if (!shadow_me_mask)
4069 for (i = context->shadow_root_level; --i >= 0;) {
4070 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4071 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4075 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4077 static inline bool boot_cpu_is_amd(void)
4079 WARN_ON_ONCE(!tdp_enabled);
4080 return shadow_x_mask == 0;
4084 * the direct page table on host, use as much mmu features as
4085 * possible, however, kvm currently does not do execution-protection.
4088 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4089 struct kvm_mmu *context)
4091 struct rsvd_bits_validate *shadow_zero_check;
4094 shadow_zero_check = &context->shadow_zero_check;
4096 if (boot_cpu_is_amd())
4097 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4099 context->shadow_root_level, false,
4100 boot_cpu_has(X86_FEATURE_GBPAGES),
4103 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4107 if (!shadow_me_mask)
4110 for (i = context->shadow_root_level; --i >= 0;) {
4111 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4112 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4117 * as the comments in reset_shadow_zero_bits_mask() except it
4118 * is the shadow page table for intel nested guest.
4121 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4122 struct kvm_mmu *context, bool execonly)
4124 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4125 shadow_phys_bits, execonly);
4128 #define BYTE_MASK(access) \
4129 ((1 & (access) ? 2 : 0) | \
4130 (2 & (access) ? 4 : 0) | \
4131 (3 & (access) ? 8 : 0) | \
4132 (4 & (access) ? 16 : 0) | \
4133 (5 & (access) ? 32 : 0) | \
4134 (6 & (access) ? 64 : 0) | \
4135 (7 & (access) ? 128 : 0))
4138 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4139 struct kvm_mmu *mmu, bool ept)
4143 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4144 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4145 const u8 u = BYTE_MASK(ACC_USER_MASK);
4147 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4148 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4149 bool cr0_wp = is_write_protection(vcpu);
4151 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4152 unsigned pfec = byte << 1;
4155 * Each "*f" variable has a 1 bit for each UWX value
4156 * that causes a fault with the given PFEC.
4159 /* Faults from writes to non-writable pages */
4160 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4161 /* Faults from user mode accesses to supervisor pages */
4162 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4163 /* Faults from fetches of non-executable pages*/
4164 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4165 /* Faults from kernel mode fetches of user pages */
4167 /* Faults from kernel mode accesses of user pages */
4171 /* Faults from kernel mode accesses to user pages */
4172 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4174 /* Not really needed: !nx will cause pte.nx to fault */
4178 /* Allow supervisor writes if !cr0.wp */
4180 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4182 /* Disallow supervisor fetches of user code if cr4.smep */
4184 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4187 * SMAP:kernel-mode data accesses from user-mode
4188 * mappings should fault. A fault is considered
4189 * as a SMAP violation if all of the following
4190 * conditions are true:
4191 * - X86_CR4_SMAP is set in CR4
4192 * - A user page is accessed
4193 * - The access is not a fetch
4194 * - Page fault in kernel mode
4195 * - if CPL = 3 or X86_EFLAGS_AC is clear
4197 * Here, we cover the first three conditions.
4198 * The fourth is computed dynamically in permission_fault();
4199 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4200 * *not* subject to SMAP restrictions.
4203 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4206 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4211 * PKU is an additional mechanism by which the paging controls access to
4212 * user-mode addresses based on the value in the PKRU register. Protection
4213 * key violations are reported through a bit in the page fault error code.
4214 * Unlike other bits of the error code, the PK bit is not known at the
4215 * call site of e.g. gva_to_gpa; it must be computed directly in
4216 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4217 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4219 * In particular the following conditions come from the error code, the
4220 * page tables and the machine state:
4221 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4222 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4223 * - PK is always zero if U=0 in the page tables
4224 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4226 * The PKRU bitmask caches the result of these four conditions. The error
4227 * code (minus the P bit) and the page table's U bit form an index into the
4228 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4229 * with the two bits of the PKRU register corresponding to the protection key.
4230 * For the first three conditions above the bits will be 00, thus masking
4231 * away both AD and WD. For all reads or if the last condition holds, WD
4232 * only will be masked away.
4234 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4245 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4246 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4251 wp = is_write_protection(vcpu);
4253 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4254 unsigned pfec, pkey_bits;
4255 bool check_pkey, check_write, ff, uf, wf, pte_user;
4258 ff = pfec & PFERR_FETCH_MASK;
4259 uf = pfec & PFERR_USER_MASK;
4260 wf = pfec & PFERR_WRITE_MASK;
4262 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4263 pte_user = pfec & PFERR_RSVD_MASK;
4266 * Only need to check the access which is not an
4267 * instruction fetch and is to a user page.
4269 check_pkey = (!ff && pte_user);
4271 * write access is controlled by PKRU if it is a
4272 * user access or CR0.WP = 1.
4274 check_write = check_pkey && wf && (uf || wp);
4276 /* PKRU.AD stops both read and write access. */
4277 pkey_bits = !!check_pkey;
4278 /* PKRU.WD stops write access. */
4279 pkey_bits |= (!!check_write) << 1;
4281 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4285 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4287 unsigned root_level = mmu->root_level;
4289 mmu->last_nonleaf_level = root_level;
4290 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4291 mmu->last_nonleaf_level++;
4294 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4295 struct kvm_mmu *context,
4298 context->nx = is_nx(vcpu);
4299 context->root_level = level;
4301 reset_rsvds_bits_mask(vcpu, context);
4302 update_permission_bitmask(vcpu, context, false);
4303 update_pkru_bitmask(vcpu, context, false);
4304 update_last_nonleaf_level(vcpu, context);
4306 MMU_WARN_ON(!is_pae(vcpu));
4307 context->page_fault = paging64_page_fault;
4308 context->gva_to_gpa = paging64_gva_to_gpa;
4309 context->sync_page = paging64_sync_page;
4310 context->invlpg = paging64_invlpg;
4311 context->update_pte = paging64_update_pte;
4312 context->shadow_root_level = level;
4313 context->direct_map = false;
4316 static void paging64_init_context(struct kvm_vcpu *vcpu,
4317 struct kvm_mmu *context)
4319 int root_level = is_la57_mode(vcpu) ?
4320 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4322 paging64_init_context_common(vcpu, context, root_level);
4325 static void paging32_init_context(struct kvm_vcpu *vcpu,
4326 struct kvm_mmu *context)
4328 context->nx = false;
4329 context->root_level = PT32_ROOT_LEVEL;
4331 reset_rsvds_bits_mask(vcpu, context);
4332 update_permission_bitmask(vcpu, context, false);
4333 update_pkru_bitmask(vcpu, context, false);
4334 update_last_nonleaf_level(vcpu, context);
4336 context->page_fault = paging32_page_fault;
4337 context->gva_to_gpa = paging32_gva_to_gpa;
4338 context->sync_page = paging32_sync_page;
4339 context->invlpg = paging32_invlpg;
4340 context->update_pte = paging32_update_pte;
4341 context->shadow_root_level = PT32E_ROOT_LEVEL;
4342 context->direct_map = false;
4345 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4346 struct kvm_mmu *context)
4348 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4351 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4353 union kvm_mmu_extended_role ext = {0};
4355 ext.cr0_pg = !!is_paging(vcpu);
4356 ext.cr4_pae = !!is_pae(vcpu);
4357 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4358 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4359 ext.cr4_pse = !!is_pse(vcpu);
4360 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4361 ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
4368 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4371 union kvm_mmu_role role = {0};
4373 role.base.access = ACC_ALL;
4374 role.base.nxe = !!is_nx(vcpu);
4375 role.base.cr0_wp = is_write_protection(vcpu);
4376 role.base.smm = is_smm(vcpu);
4377 role.base.guest_mode = is_guest_mode(vcpu);
4382 role.ext = kvm_calc_mmu_role_ext(vcpu);
4387 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4389 /* Use 5-level TDP if and only if it's useful/necessary. */
4390 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4393 return max_tdp_level;
4396 static union kvm_mmu_role
4397 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4399 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4401 role.base.ad_disabled = (shadow_accessed_mask == 0);
4402 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4403 role.base.direct = true;
4404 role.base.gpte_is_8_bytes = true;
4409 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4411 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4412 union kvm_mmu_role new_role =
4413 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
4415 if (new_role.as_u64 == context->mmu_role.as_u64)
4418 context->mmu_role.as_u64 = new_role.as_u64;
4419 context->page_fault = kvm_tdp_page_fault;
4420 context->sync_page = nonpaging_sync_page;
4421 context->invlpg = NULL;
4422 context->update_pte = nonpaging_update_pte;
4423 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4424 context->direct_map = true;
4425 context->get_guest_pgd = get_cr3;
4426 context->get_pdptr = kvm_pdptr_read;
4427 context->inject_page_fault = kvm_inject_page_fault;
4429 if (!is_paging(vcpu)) {
4430 context->nx = false;
4431 context->gva_to_gpa = nonpaging_gva_to_gpa;
4432 context->root_level = 0;
4433 } else if (is_long_mode(vcpu)) {
4434 context->nx = is_nx(vcpu);
4435 context->root_level = is_la57_mode(vcpu) ?
4436 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4437 reset_rsvds_bits_mask(vcpu, context);
4438 context->gva_to_gpa = paging64_gva_to_gpa;
4439 } else if (is_pae(vcpu)) {
4440 context->nx = is_nx(vcpu);
4441 context->root_level = PT32E_ROOT_LEVEL;
4442 reset_rsvds_bits_mask(vcpu, context);
4443 context->gva_to_gpa = paging64_gva_to_gpa;
4445 context->nx = false;
4446 context->root_level = PT32_ROOT_LEVEL;
4447 reset_rsvds_bits_mask(vcpu, context);
4448 context->gva_to_gpa = paging32_gva_to_gpa;
4451 update_permission_bitmask(vcpu, context, false);
4452 update_pkru_bitmask(vcpu, context, false);
4453 update_last_nonleaf_level(vcpu, context);
4454 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4457 static union kvm_mmu_role
4458 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, bool base_only)
4460 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4462 role.base.smep_andnot_wp = role.ext.cr4_smep &&
4463 !is_write_protection(vcpu);
4464 role.base.smap_andnot_wp = role.ext.cr4_smap &&
4465 !is_write_protection(vcpu);
4466 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
4471 static union kvm_mmu_role
4472 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4474 union kvm_mmu_role role =
4475 kvm_calc_shadow_root_page_role_common(vcpu, base_only);
4477 role.base.direct = !is_paging(vcpu);
4479 if (!is_long_mode(vcpu))
4480 role.base.level = PT32E_ROOT_LEVEL;
4481 else if (is_la57_mode(vcpu))
4482 role.base.level = PT64_ROOT_5LEVEL;
4484 role.base.level = PT64_ROOT_4LEVEL;
4489 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4490 u32 cr0, u32 cr4, u32 efer,
4491 union kvm_mmu_role new_role)
4493 if (!(cr0 & X86_CR0_PG))
4494 nonpaging_init_context(vcpu, context);
4495 else if (efer & EFER_LMA)
4496 paging64_init_context(vcpu, context);
4497 else if (cr4 & X86_CR4_PAE)
4498 paging32E_init_context(vcpu, context);
4500 paging32_init_context(vcpu, context);
4502 context->mmu_role.as_u64 = new_role.as_u64;
4503 reset_shadow_zero_bits_mask(vcpu, context);
4506 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer)
4508 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4509 union kvm_mmu_role new_role =
4510 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4512 if (new_role.as_u64 != context->mmu_role.as_u64)
4513 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4516 static union kvm_mmu_role
4517 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu)
4519 union kvm_mmu_role role =
4520 kvm_calc_shadow_root_page_role_common(vcpu, false);
4522 role.base.direct = false;
4523 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4528 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer,
4531 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4532 union kvm_mmu_role new_role = kvm_calc_shadow_npt_root_page_role(vcpu);
4534 context->shadow_root_level = new_role.base.level;
4536 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base, false, false);
4538 if (new_role.as_u64 != context->mmu_role.as_u64)
4539 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4541 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4543 static union kvm_mmu_role
4544 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4545 bool execonly, u8 level)
4547 union kvm_mmu_role role = {0};
4549 /* SMM flag is inherited from root_mmu */
4550 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4552 role.base.level = level;
4553 role.base.gpte_is_8_bytes = true;
4554 role.base.direct = false;
4555 role.base.ad_disabled = !accessed_dirty;
4556 role.base.guest_mode = true;
4557 role.base.access = ACC_ALL;
4560 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
4561 * SMAP variation to denote shadow EPT entries.
4563 role.base.cr0_wp = true;
4564 role.base.smap_andnot_wp = true;
4566 role.ext = kvm_calc_mmu_role_ext(vcpu);
4567 role.ext.execonly = execonly;
4572 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4573 bool accessed_dirty, gpa_t new_eptp)
4575 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4576 u8 level = vmx_eptp_page_walk_level(new_eptp);
4577 union kvm_mmu_role new_role =
4578 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4581 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base, true, true);
4583 if (new_role.as_u64 == context->mmu_role.as_u64)
4586 context->shadow_root_level = level;
4589 context->ept_ad = accessed_dirty;
4590 context->page_fault = ept_page_fault;
4591 context->gva_to_gpa = ept_gva_to_gpa;
4592 context->sync_page = ept_sync_page;
4593 context->invlpg = ept_invlpg;
4594 context->update_pte = ept_update_pte;
4595 context->root_level = level;
4596 context->direct_map = false;
4597 context->mmu_role.as_u64 = new_role.as_u64;
4599 update_permission_bitmask(vcpu, context, true);
4600 update_pkru_bitmask(vcpu, context, true);
4601 update_last_nonleaf_level(vcpu, context);
4602 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4603 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4605 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4607 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4609 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4611 kvm_init_shadow_mmu(vcpu,
4612 kvm_read_cr0_bits(vcpu, X86_CR0_PG),
4613 kvm_read_cr4_bits(vcpu, X86_CR4_PAE),
4616 context->get_guest_pgd = get_cr3;
4617 context->get_pdptr = kvm_pdptr_read;
4618 context->inject_page_fault = kvm_inject_page_fault;
4621 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4623 union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false);
4624 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4626 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4629 g_context->mmu_role.as_u64 = new_role.as_u64;
4630 g_context->get_guest_pgd = get_cr3;
4631 g_context->get_pdptr = kvm_pdptr_read;
4632 g_context->inject_page_fault = kvm_inject_page_fault;
4635 * L2 page tables are never shadowed, so there is no need to sync
4638 g_context->invlpg = NULL;
4641 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4642 * L1's nested page tables (e.g. EPT12). The nested translation
4643 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4644 * L2's page tables as the first level of translation and L1's
4645 * nested page tables as the second level of translation. Basically
4646 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4648 if (!is_paging(vcpu)) {
4649 g_context->nx = false;
4650 g_context->root_level = 0;
4651 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4652 } else if (is_long_mode(vcpu)) {
4653 g_context->nx = is_nx(vcpu);
4654 g_context->root_level = is_la57_mode(vcpu) ?
4655 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4656 reset_rsvds_bits_mask(vcpu, g_context);
4657 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4658 } else if (is_pae(vcpu)) {
4659 g_context->nx = is_nx(vcpu);
4660 g_context->root_level = PT32E_ROOT_LEVEL;
4661 reset_rsvds_bits_mask(vcpu, g_context);
4662 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4664 g_context->nx = false;
4665 g_context->root_level = PT32_ROOT_LEVEL;
4666 reset_rsvds_bits_mask(vcpu, g_context);
4667 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4670 update_permission_bitmask(vcpu, g_context, false);
4671 update_pkru_bitmask(vcpu, g_context, false);
4672 update_last_nonleaf_level(vcpu, g_context);
4675 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
4680 vcpu->arch.mmu->root_hpa = INVALID_PAGE;
4682 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
4683 vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
4686 if (mmu_is_nested(vcpu))
4687 init_kvm_nested_mmu(vcpu);
4688 else if (tdp_enabled)
4689 init_kvm_tdp_mmu(vcpu);
4691 init_kvm_softmmu(vcpu);
4693 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4695 static union kvm_mmu_page_role
4696 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4698 union kvm_mmu_role role;
4701 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
4703 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
4708 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4710 kvm_mmu_unload(vcpu);
4711 kvm_init_mmu(vcpu, true);
4713 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4715 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4719 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
4722 r = mmu_alloc_roots(vcpu);
4723 kvm_mmu_sync_roots(vcpu);
4726 kvm_mmu_load_pgd(vcpu);
4727 kvm_x86_ops.tlb_flush_current(vcpu);
4731 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4733 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4735 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
4736 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
4737 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4738 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
4740 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4742 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4743 struct kvm_mmu_page *sp, u64 *spte,
4746 if (sp->role.level != PG_LEVEL_4K) {
4747 ++vcpu->kvm->stat.mmu_pde_zapped;
4751 ++vcpu->kvm->stat.mmu_pte_updated;
4752 vcpu->arch.mmu->update_pte(vcpu, sp, spte, new);
4755 static bool need_remote_flush(u64 old, u64 new)
4757 if (!is_shadow_present_pte(old))
4759 if (!is_shadow_present_pte(new))
4761 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4763 old ^= shadow_nx_mask;
4764 new ^= shadow_nx_mask;
4765 return (old & ~new & PT64_PERM_MASK) != 0;
4768 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4775 * Assume that the pte write on a page table of the same type
4776 * as the current vcpu paging mode since we update the sptes only
4777 * when they have the same mode.
4779 if (is_pae(vcpu) && *bytes == 4) {
4780 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4785 if (*bytes == 4 || *bytes == 8) {
4786 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
4795 * If we're seeing too many writes to a page, it may no longer be a page table,
4796 * or we may be forking, in which case it is better to unmap the page.
4798 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4801 * Skip write-flooding detected for the sp whose level is 1, because
4802 * it can become unsync, then the guest page is not write-protected.
4804 if (sp->role.level == PG_LEVEL_4K)
4807 atomic_inc(&sp->write_flooding_count);
4808 return atomic_read(&sp->write_flooding_count) >= 3;
4812 * Misaligned accesses are too much trouble to fix up; also, they usually
4813 * indicate a page is not used as a page table.
4815 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4818 unsigned offset, pte_size, misaligned;
4820 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4821 gpa, bytes, sp->role.word);
4823 offset = offset_in_page(gpa);
4824 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
4827 * Sometimes, the OS only writes the last one bytes to update status
4828 * bits, for example, in linux, andb instruction is used in clear_bit().
4830 if (!(offset & (pte_size - 1)) && bytes == 1)
4833 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4834 misaligned |= bytes < 4;
4839 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4841 unsigned page_offset, quadrant;
4845 page_offset = offset_in_page(gpa);
4846 level = sp->role.level;
4848 if (!sp->role.gpte_is_8_bytes) {
4849 page_offset <<= 1; /* 32->64 */
4851 * A 32-bit pde maps 4MB while the shadow pdes map
4852 * only 2MB. So we need to double the offset again
4853 * and zap two pdes instead of one.
4855 if (level == PT32_ROOT_LEVEL) {
4856 page_offset &= ~7; /* kill rounding error */
4860 quadrant = page_offset >> PAGE_SHIFT;
4861 page_offset &= ~PAGE_MASK;
4862 if (quadrant != sp->role.quadrant)
4866 spte = &sp->spt[page_offset / sizeof(*spte)];
4871 * Ignore various flags when determining if a SPTE can be immediately
4872 * overwritten for the current MMU.
4873 * - level: explicitly checked in mmu_pte_write_new_pte(), and will never
4874 * match the current MMU role, as MMU's level tracks the root level.
4875 * - access: updated based on the new guest PTE
4876 * - quadrant: handled by get_written_sptes()
4877 * - invalid: always false (loop only walks valid shadow pages)
4879 static const union kvm_mmu_page_role role_ign = {
4886 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4887 const u8 *new, int bytes,
4888 struct kvm_page_track_notifier_node *node)
4890 gfn_t gfn = gpa >> PAGE_SHIFT;
4891 struct kvm_mmu_page *sp;
4892 LIST_HEAD(invalid_list);
4893 u64 entry, gentry, *spte;
4895 bool remote_flush, local_flush;
4898 * If we don't have indirect shadow pages, it means no page is
4899 * write-protected, so we can exit simply.
4901 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4904 remote_flush = local_flush = false;
4906 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4909 * No need to care whether allocation memory is successful
4910 * or not since pte prefetch is skiped if it does not have
4911 * enough objects in the cache.
4913 mmu_topup_memory_caches(vcpu, true);
4915 spin_lock(&vcpu->kvm->mmu_lock);
4917 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
4919 ++vcpu->kvm->stat.mmu_pte_write;
4920 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4922 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4923 if (detect_write_misaligned(sp, gpa, bytes) ||
4924 detect_write_flooding(sp)) {
4925 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4926 ++vcpu->kvm->stat.mmu_flooded;
4930 spte = get_written_sptes(sp, gpa, &npte);
4936 u32 base_role = vcpu->arch.mmu->mmu_role.base.word;
4939 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
4941 !((sp->role.word ^ base_role) & ~role_ign.word) &&
4943 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4944 if (need_remote_flush(entry, *spte))
4945 remote_flush = true;
4949 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
4950 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4951 spin_unlock(&vcpu->kvm->mmu_lock);
4954 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4959 if (vcpu->arch.mmu->direct_map)
4962 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4964 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4968 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4970 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
4971 void *insn, int insn_len)
4973 int r, emulation_type = EMULTYPE_PF;
4974 bool direct = vcpu->arch.mmu->direct_map;
4976 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
4977 return RET_PF_RETRY;
4980 if (unlikely(error_code & PFERR_RSVD_MASK)) {
4981 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
4982 if (r == RET_PF_EMULATE)
4986 if (r == RET_PF_INVALID) {
4987 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
4988 lower_32_bits(error_code), false);
4989 if (WARN_ON_ONCE(r == RET_PF_INVALID))
4995 if (r != RET_PF_EMULATE)
4999 * Before emulating the instruction, check if the error code
5000 * was due to a RO violation while translating the guest page.
5001 * This can occur when using nested virtualization with nested
5002 * paging in both guests. If true, we simply unprotect the page
5003 * and resume the guest.
5005 if (vcpu->arch.mmu->direct_map &&
5006 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5007 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5012 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5013 * optimistically try to just unprotect the page and let the processor
5014 * re-execute the instruction that caused the page fault. Do not allow
5015 * retrying MMIO emulation, as it's not only pointless but could also
5016 * cause us to enter an infinite loop because the processor will keep
5017 * faulting on the non-existent MMIO address. Retrying an instruction
5018 * from a nested guest is also pointless and dangerous as we are only
5019 * explicitly shadowing L1's page tables, i.e. unprotecting something
5020 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5022 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5023 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5025 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5028 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5030 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5031 gva_t gva, hpa_t root_hpa)
5035 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5036 if (mmu != &vcpu->arch.guest_mmu) {
5037 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5038 if (is_noncanonical_address(gva, vcpu))
5041 kvm_x86_ops.tlb_flush_gva(vcpu, gva);
5047 if (root_hpa == INVALID_PAGE) {
5048 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5051 * INVLPG is required to invalidate any global mappings for the VA,
5052 * irrespective of PCID. Since it would take us roughly similar amount
5053 * of work to determine whether any of the prev_root mappings of the VA
5054 * is marked global, or to just sync it blindly, so we might as well
5055 * just always sync it.
5057 * Mappings not reachable via the current cr3 or the prev_roots will be
5058 * synced when switching to that cr3, so nothing needs to be done here
5061 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5062 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5063 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5065 mmu->invlpg(vcpu, gva, root_hpa);
5068 EXPORT_SYMBOL_GPL(kvm_mmu_invalidate_gva);
5070 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5072 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
5073 ++vcpu->stat.invlpg;
5075 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5078 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5080 struct kvm_mmu *mmu = vcpu->arch.mmu;
5081 bool tlb_flush = false;
5084 if (pcid == kvm_get_active_pcid(vcpu)) {
5085 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5089 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5090 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5091 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5092 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5098 kvm_x86_ops.tlb_flush_gva(vcpu, gva);
5100 ++vcpu->stat.invlpg;
5103 * Mappings not reachable via the current cr3 or the prev_roots will be
5104 * synced when switching to that cr3, so nothing needs to be done here
5108 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva);
5110 void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
5111 int tdp_huge_page_level)
5113 tdp_enabled = enable_tdp;
5114 max_tdp_level = tdp_max_root_level;
5117 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5118 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5119 * the kernel is not. But, KVM never creates a page size greater than
5120 * what is used by the kernel for any given HVA, i.e. the kernel's
5121 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5124 max_huge_page_level = tdp_huge_page_level;
5125 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5126 max_huge_page_level = PG_LEVEL_1G;
5128 max_huge_page_level = PG_LEVEL_2M;
5130 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5132 /* The return value indicates if tlb flush on all vcpus is needed. */
5133 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5135 /* The caller should hold mmu-lock before calling this function. */
5136 static __always_inline bool
5137 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5138 slot_level_handler fn, int start_level, int end_level,
5139 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5141 struct slot_rmap_walk_iterator iterator;
5144 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5145 end_gfn, &iterator) {
5147 flush |= fn(kvm, iterator.rmap);
5149 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5150 if (flush && lock_flush_tlb) {
5151 kvm_flush_remote_tlbs_with_address(kvm,
5153 iterator.gfn - start_gfn + 1);
5156 cond_resched_lock(&kvm->mmu_lock);
5160 if (flush && lock_flush_tlb) {
5161 kvm_flush_remote_tlbs_with_address(kvm, start_gfn,
5162 end_gfn - start_gfn + 1);
5169 static __always_inline bool
5170 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5171 slot_level_handler fn, int start_level, int end_level,
5172 bool lock_flush_tlb)
5174 return slot_handle_level_range(kvm, memslot, fn, start_level,
5175 end_level, memslot->base_gfn,
5176 memslot->base_gfn + memslot->npages - 1,
5180 static __always_inline bool
5181 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5182 slot_level_handler fn, bool lock_flush_tlb)
5184 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5185 KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5188 static __always_inline bool
5189 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5190 slot_level_handler fn, bool lock_flush_tlb)
5192 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K + 1,
5193 KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5196 static __always_inline bool
5197 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5198 slot_level_handler fn, bool lock_flush_tlb)
5200 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5201 PG_LEVEL_4K, lock_flush_tlb);
5204 static void free_mmu_pages(struct kvm_mmu *mmu)
5206 free_page((unsigned long)mmu->pae_root);
5207 free_page((unsigned long)mmu->lm_root);
5210 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5215 mmu->root_hpa = INVALID_PAGE;
5217 mmu->translate_gpa = translate_gpa;
5218 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5219 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5222 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5223 * while the PDP table is a per-vCPU construct that's allocated at MMU
5224 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5225 * x86_64. Therefore we need to allocate the PDP table in the first
5226 * 4GB of memory, which happens to fit the DMA32 zone. Except for
5227 * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can
5228 * skip allocating the PDP table.
5230 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5233 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5237 mmu->pae_root = page_address(page);
5238 for (i = 0; i < 4; ++i)
5239 mmu->pae_root[i] = INVALID_PAGE;
5244 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5248 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5249 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5251 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5252 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5254 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5256 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5257 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5259 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5261 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5265 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5267 goto fail_allocate_root;
5271 free_mmu_pages(&vcpu->arch.guest_mmu);
5275 #define BATCH_ZAP_PAGES 10
5276 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5278 struct kvm_mmu_page *sp, *node;
5279 int nr_zapped, batch = 0;
5282 list_for_each_entry_safe_reverse(sp, node,
5283 &kvm->arch.active_mmu_pages, link) {
5285 * No obsolete valid page exists before a newly created page
5286 * since active_mmu_pages is a FIFO list.
5288 if (!is_obsolete_sp(kvm, sp))
5292 * Invalid pages should never land back on the list of active
5293 * pages. Skip the bogus page, otherwise we'll get stuck in an
5294 * infinite loop if the page gets put back on the list (again).
5296 if (WARN_ON(sp->role.invalid))
5300 * No need to flush the TLB since we're only zapping shadow
5301 * pages with an obsolete generation number and all vCPUS have
5302 * loaded a new root, i.e. the shadow pages being zapped cannot
5303 * be in active use by the guest.
5305 if (batch >= BATCH_ZAP_PAGES &&
5306 cond_resched_lock(&kvm->mmu_lock)) {
5311 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5312 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5319 * Trigger a remote TLB flush before freeing the page tables to ensure
5320 * KVM is not in the middle of a lockless shadow page table walk, which
5321 * may reference the pages.
5323 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5327 * Fast invalidate all shadow pages and use lock-break technique
5328 * to zap obsolete pages.
5330 * It's required when memslot is being deleted or VM is being
5331 * destroyed, in these cases, we should ensure that KVM MMU does
5332 * not use any resource of the being-deleted slot or all slots
5333 * after calling the function.
5335 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5337 lockdep_assert_held(&kvm->slots_lock);
5339 spin_lock(&kvm->mmu_lock);
5340 trace_kvm_mmu_zap_all_fast(kvm);
5343 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5344 * held for the entire duration of zapping obsolete pages, it's
5345 * impossible for there to be multiple invalid generations associated
5346 * with *valid* shadow pages at any given time, i.e. there is exactly
5347 * one valid generation and (at most) one invalid generation.
5349 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5352 * Notify all vcpus to reload its shadow page table and flush TLB.
5353 * Then all vcpus will switch to new shadow page table with the new
5356 * Note: we need to do this under the protection of mmu_lock,
5357 * otherwise, vcpu would purge shadow page but miss tlb flush.
5359 kvm_reload_remote_mmus(kvm);
5361 kvm_zap_obsolete_pages(kvm);
5363 if (kvm->arch.tdp_mmu_enabled)
5364 kvm_tdp_mmu_zap_all(kvm);
5366 spin_unlock(&kvm->mmu_lock);
5369 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5371 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5374 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5375 struct kvm_memory_slot *slot,
5376 struct kvm_page_track_notifier_node *node)
5378 kvm_mmu_zap_all_fast(kvm);
5381 void kvm_mmu_init_vm(struct kvm *kvm)
5383 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5385 kvm_mmu_init_tdp_mmu(kvm);
5387 node->track_write = kvm_mmu_pte_write;
5388 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5389 kvm_page_track_register_notifier(kvm, node);
5392 void kvm_mmu_uninit_vm(struct kvm *kvm)
5394 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5396 kvm_page_track_unregister_notifier(kvm, node);
5398 kvm_mmu_uninit_tdp_mmu(kvm);
5401 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5403 struct kvm_memslots *slots;
5404 struct kvm_memory_slot *memslot;
5408 spin_lock(&kvm->mmu_lock);
5409 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5410 slots = __kvm_memslots(kvm, i);
5411 kvm_for_each_memslot(memslot, slots) {
5414 start = max(gfn_start, memslot->base_gfn);
5415 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5419 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5421 KVM_MAX_HUGEPAGE_LEVEL,
5422 start, end - 1, true);
5426 if (kvm->arch.tdp_mmu_enabled) {
5427 flush = kvm_tdp_mmu_zap_gfn_range(kvm, gfn_start, gfn_end);
5429 kvm_flush_remote_tlbs(kvm);
5432 spin_unlock(&kvm->mmu_lock);
5435 static bool slot_rmap_write_protect(struct kvm *kvm,
5436 struct kvm_rmap_head *rmap_head)
5438 return __rmap_write_protect(kvm, rmap_head, false);
5441 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5442 struct kvm_memory_slot *memslot,
5447 spin_lock(&kvm->mmu_lock);
5448 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5449 start_level, KVM_MAX_HUGEPAGE_LEVEL, false);
5450 spin_unlock(&kvm->mmu_lock);
5453 * We can flush all the TLBs out of the mmu lock without TLB
5454 * corruption since we just change the spte from writable to
5455 * readonly so that we only need to care the case of changing
5456 * spte from present to present (changing the spte from present
5457 * to nonpresent will flush all the TLBs immediately), in other
5458 * words, the only case we care is mmu_spte_update() where we
5459 * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5460 * instead of PT_WRITABLE_MASK, that means it does not depend
5461 * on PT_WRITABLE_MASK anymore.
5464 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5467 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5468 struct kvm_rmap_head *rmap_head)
5471 struct rmap_iterator iter;
5472 int need_tlb_flush = 0;
5474 struct kvm_mmu_page *sp;
5477 for_each_rmap_spte(rmap_head, &iter, sptep) {
5478 sp = sptep_to_sp(sptep);
5479 pfn = spte_to_pfn(*sptep);
5482 * We cannot do huge page mapping for indirect shadow pages,
5483 * which are found on the last rmap (level = 1) when not using
5484 * tdp; such shadow pages are synced with the page table in
5485 * the guest, and the guest page table is using 4K page size
5486 * mapping if the indirect sp has level = 1.
5488 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5489 (kvm_is_zone_device_pfn(pfn) ||
5490 PageCompound(pfn_to_page(pfn)))) {
5491 pte_list_remove(rmap_head, sptep);
5493 if (kvm_available_flush_tlb_with_range())
5494 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5495 KVM_PAGES_PER_HPAGE(sp->role.level));
5503 return need_tlb_flush;
5506 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5507 const struct kvm_memory_slot *memslot)
5509 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5510 spin_lock(&kvm->mmu_lock);
5511 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5512 kvm_mmu_zap_collapsible_spte, true);
5513 spin_unlock(&kvm->mmu_lock);
5516 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5517 struct kvm_memory_slot *memslot)
5520 * All current use cases for flushing the TLBs for a specific memslot
5521 * are related to dirty logging, and do the TLB flush out of mmu_lock.
5522 * The interaction between the various operations on memslot must be
5523 * serialized by slots_locks to ensure the TLB flush from one operation
5524 * is observed by any other operation on the same memslot.
5526 lockdep_assert_held(&kvm->slots_lock);
5527 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5531 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5532 struct kvm_memory_slot *memslot)
5536 spin_lock(&kvm->mmu_lock);
5537 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5538 spin_unlock(&kvm->mmu_lock);
5541 * It's also safe to flush TLBs out of mmu lock here as currently this
5542 * function is only used for dirty logging, in which case flushing TLB
5543 * out of mmu lock also guarantees no dirty pages will be lost in
5547 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5549 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5551 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5552 struct kvm_memory_slot *memslot)
5556 spin_lock(&kvm->mmu_lock);
5557 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5559 spin_unlock(&kvm->mmu_lock);
5562 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5564 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5566 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5567 struct kvm_memory_slot *memslot)
5571 spin_lock(&kvm->mmu_lock);
5572 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
5573 spin_unlock(&kvm->mmu_lock);
5576 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5578 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5580 void kvm_mmu_zap_all(struct kvm *kvm)
5582 struct kvm_mmu_page *sp, *node;
5583 LIST_HEAD(invalid_list);
5586 spin_lock(&kvm->mmu_lock);
5588 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5589 if (WARN_ON(sp->role.invalid))
5591 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5593 if (cond_resched_lock(&kvm->mmu_lock))
5597 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5599 if (kvm->arch.tdp_mmu_enabled)
5600 kvm_tdp_mmu_zap_all(kvm);
5602 spin_unlock(&kvm->mmu_lock);
5605 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5607 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5609 gen &= MMIO_SPTE_GEN_MASK;
5612 * Generation numbers are incremented in multiples of the number of
5613 * address spaces in order to provide unique generations across all
5614 * address spaces. Strip what is effectively the address space
5615 * modifier prior to checking for a wrap of the MMIO generation so
5616 * that a wrap in any address space is detected.
5618 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5621 * The very rare case: if the MMIO generation number has wrapped,
5622 * zap all shadow pages.
5624 if (unlikely(gen == 0)) {
5625 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5626 kvm_mmu_zap_all_fast(kvm);
5630 static unsigned long
5631 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5634 int nr_to_scan = sc->nr_to_scan;
5635 unsigned long freed = 0;
5637 mutex_lock(&kvm_lock);
5639 list_for_each_entry(kvm, &vm_list, vm_list) {
5641 LIST_HEAD(invalid_list);
5644 * Never scan more than sc->nr_to_scan VM instances.
5645 * Will not hit this condition practically since we do not try
5646 * to shrink more than one VM and it is very unlikely to see
5647 * !n_used_mmu_pages so many times.
5652 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5653 * here. We may skip a VM instance errorneosly, but we do not
5654 * want to shrink a VM that only started to populate its MMU
5657 if (!kvm->arch.n_used_mmu_pages &&
5658 !kvm_has_zapped_obsolete_pages(kvm))
5661 idx = srcu_read_lock(&kvm->srcu);
5662 spin_lock(&kvm->mmu_lock);
5664 if (kvm_has_zapped_obsolete_pages(kvm)) {
5665 kvm_mmu_commit_zap_page(kvm,
5666 &kvm->arch.zapped_obsolete_pages);
5670 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
5673 spin_unlock(&kvm->mmu_lock);
5674 srcu_read_unlock(&kvm->srcu, idx);
5677 * unfair on small ones
5678 * per-vm shrinkers cry out
5679 * sadness comes quickly
5681 list_move_tail(&kvm->vm_list, &vm_list);
5685 mutex_unlock(&kvm_lock);
5689 static unsigned long
5690 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5692 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5695 static struct shrinker mmu_shrinker = {
5696 .count_objects = mmu_shrink_count,
5697 .scan_objects = mmu_shrink_scan,
5698 .seeks = DEFAULT_SEEKS * 10,
5701 static void mmu_destroy_caches(void)
5703 kmem_cache_destroy(pte_list_desc_cache);
5704 kmem_cache_destroy(mmu_page_header_cache);
5707 static void kvm_set_mmio_spte_mask(void)
5712 * Set a reserved PA bit in MMIO SPTEs to generate page faults with
5713 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT
5714 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports
5715 * 52-bit physical addresses then there are no reserved PA bits in the
5716 * PTEs and so the reserved PA approach must be disabled.
5718 if (shadow_phys_bits < 52)
5719 mask = BIT_ULL(51) | PT_PRESENT_MASK;
5723 kvm_mmu_set_mmio_spte_mask(mask, ACC_WRITE_MASK | ACC_USER_MASK);
5726 static bool get_nx_auto_mode(void)
5728 /* Return true when CPU has the bug, and mitigations are ON */
5729 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5732 static void __set_nx_huge_pages(bool val)
5734 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5737 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5739 bool old_val = nx_huge_pages;
5742 /* In "auto" mode deploy workaround only if CPU has the bug. */
5743 if (sysfs_streq(val, "off"))
5745 else if (sysfs_streq(val, "force"))
5747 else if (sysfs_streq(val, "auto"))
5748 new_val = get_nx_auto_mode();
5749 else if (strtobool(val, &new_val) < 0)
5752 __set_nx_huge_pages(new_val);
5754 if (new_val != old_val) {
5757 mutex_lock(&kvm_lock);
5759 list_for_each_entry(kvm, &vm_list, vm_list) {
5760 mutex_lock(&kvm->slots_lock);
5761 kvm_mmu_zap_all_fast(kvm);
5762 mutex_unlock(&kvm->slots_lock);
5764 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5766 mutex_unlock(&kvm_lock);
5772 int kvm_mmu_module_init(void)
5776 if (nx_huge_pages == -1)
5777 __set_nx_huge_pages(get_nx_auto_mode());
5780 * MMU roles use union aliasing which is, generally speaking, an
5781 * undefined behavior. However, we supposedly know how compilers behave
5782 * and the current status quo is unlikely to change. Guardians below are
5783 * supposed to let us know if the assumption becomes false.
5785 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
5786 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
5787 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
5789 kvm_mmu_reset_all_pte_masks();
5791 kvm_set_mmio_spte_mask();
5793 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5794 sizeof(struct pte_list_desc),
5795 0, SLAB_ACCOUNT, NULL);
5796 if (!pte_list_desc_cache)
5799 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5800 sizeof(struct kvm_mmu_page),
5801 0, SLAB_ACCOUNT, NULL);
5802 if (!mmu_page_header_cache)
5805 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5808 ret = register_shrinker(&mmu_shrinker);
5815 mmu_destroy_caches();
5820 * Calculate mmu pages needed for kvm.
5822 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
5824 unsigned long nr_mmu_pages;
5825 unsigned long nr_pages = 0;
5826 struct kvm_memslots *slots;
5827 struct kvm_memory_slot *memslot;
5830 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5831 slots = __kvm_memslots(kvm, i);
5833 kvm_for_each_memslot(memslot, slots)
5834 nr_pages += memslot->npages;
5837 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5838 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
5840 return nr_mmu_pages;
5843 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5845 kvm_mmu_unload(vcpu);
5846 free_mmu_pages(&vcpu->arch.root_mmu);
5847 free_mmu_pages(&vcpu->arch.guest_mmu);
5848 mmu_free_memory_caches(vcpu);
5851 void kvm_mmu_module_exit(void)
5853 mmu_destroy_caches();
5854 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5855 unregister_shrinker(&mmu_shrinker);
5856 mmu_audit_disable();
5859 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
5861 unsigned int old_val;
5864 old_val = nx_huge_pages_recovery_ratio;
5865 err = param_set_uint(val, kp);
5869 if (READ_ONCE(nx_huge_pages) &&
5870 !old_val && nx_huge_pages_recovery_ratio) {
5873 mutex_lock(&kvm_lock);
5875 list_for_each_entry(kvm, &vm_list, vm_list)
5876 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5878 mutex_unlock(&kvm_lock);
5884 static void kvm_recover_nx_lpages(struct kvm *kvm)
5887 struct kvm_mmu_page *sp;
5889 LIST_HEAD(invalid_list);
5892 rcu_idx = srcu_read_lock(&kvm->srcu);
5893 spin_lock(&kvm->mmu_lock);
5895 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
5896 to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0;
5897 for ( ; to_zap; --to_zap) {
5898 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
5902 * We use a separate list instead of just using active_mmu_pages
5903 * because the number of lpage_disallowed pages is expected to
5904 * be relatively small compared to the total.
5906 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
5907 struct kvm_mmu_page,
5908 lpage_disallowed_link);
5909 WARN_ON_ONCE(!sp->lpage_disallowed);
5910 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
5911 WARN_ON_ONCE(sp->lpage_disallowed);
5913 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5914 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5915 cond_resched_lock(&kvm->mmu_lock);
5918 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5920 spin_unlock(&kvm->mmu_lock);
5921 srcu_read_unlock(&kvm->srcu, rcu_idx);
5924 static long get_nx_lpage_recovery_timeout(u64 start_time)
5926 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
5927 ? start_time + 60 * HZ - get_jiffies_64()
5928 : MAX_SCHEDULE_TIMEOUT;
5931 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
5934 long remaining_time;
5937 start_time = get_jiffies_64();
5938 remaining_time = get_nx_lpage_recovery_timeout(start_time);
5940 set_current_state(TASK_INTERRUPTIBLE);
5941 while (!kthread_should_stop() && remaining_time > 0) {
5942 schedule_timeout(remaining_time);
5943 remaining_time = get_nx_lpage_recovery_timeout(start_time);
5944 set_current_state(TASK_INTERRUPTIBLE);
5947 set_current_state(TASK_RUNNING);
5949 if (kthread_should_stop())
5952 kvm_recover_nx_lpages(kvm);
5956 int kvm_mmu_post_init_vm(struct kvm *kvm)
5960 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
5961 "kvm-nx-lpage-recovery",
5962 &kvm->arch.nx_lpage_recovery_thread);
5964 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
5969 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
5971 if (kvm->arch.nx_lpage_recovery_thread)
5972 kthread_stop(kvm->arch.nx_lpage_recovery_thread);