1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
51 #include <asm/set_memory.h>
53 #include <asm/kvm_page_track.h>
56 extern bool itlb_multihit_kvm_mitigation;
58 int __read_mostly nx_huge_pages = -1;
59 #ifdef CONFIG_PREEMPT_RT
60 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
61 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
63 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
66 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
67 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops nx_huge_pages_ops = {
70 .set = set_nx_huge_pages,
71 .get = param_get_bool,
74 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
75 .set = set_nx_huge_pages_recovery_ratio,
76 .get = param_get_uint,
79 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
80 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
81 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
82 &nx_huge_pages_recovery_ratio, 0644);
83 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
85 static bool __read_mostly force_flush_and_sync_on_reuse;
86 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
89 * When setting this variable to true it enables Two-Dimensional-Paging
90 * where the hardware walks 2 page tables:
91 * 1. the guest-virtual to guest-physical
92 * 2. while doing 1. it walks guest-physical to host-physical
93 * If the hardware supports that we don't need to do shadow paging.
95 bool tdp_enabled = false;
97 static int max_huge_page_level __read_mostly;
98 static int max_tdp_level __read_mostly;
101 AUDIT_PRE_PAGE_FAULT,
102 AUDIT_POST_PAGE_FAULT,
104 AUDIT_POST_PTE_WRITE,
111 module_param(dbg, bool, 0644);
114 #define PTE_PREFETCH_NUM 8
116 #define PT32_LEVEL_BITS 10
118 #define PT32_LEVEL_SHIFT(level) \
119 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
121 #define PT32_LVL_OFFSET_MASK(level) \
122 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT32_LEVEL_BITS))) - 1))
125 #define PT32_INDEX(address, level)\
126 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
129 #define PT32_BASE_ADDR_MASK PAGE_MASK
130 #define PT32_DIR_BASE_ADDR_MASK \
131 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
132 #define PT32_LVL_ADDR_MASK(level) \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
134 * PT32_LEVEL_BITS))) - 1))
136 #include <trace/events/kvm.h>
138 /* make pte_list_desc fit well in cache line */
139 #define PTE_LIST_EXT 3
141 struct pte_list_desc {
142 u64 *sptes[PTE_LIST_EXT];
143 struct pte_list_desc *more;
146 struct kvm_shadow_walk_iterator {
154 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
155 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
157 shadow_walk_okay(&(_walker)); \
158 shadow_walk_next(&(_walker)))
160 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
161 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
162 shadow_walk_okay(&(_walker)); \
163 shadow_walk_next(&(_walker)))
165 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
166 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
167 shadow_walk_okay(&(_walker)) && \
168 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
169 __shadow_walk_next(&(_walker), spte))
171 static struct kmem_cache *pte_list_desc_cache;
172 struct kmem_cache *mmu_page_header_cache;
173 static struct percpu_counter kvm_total_used_mmu_pages;
175 static void mmu_spte_set(u64 *sptep, u64 spte);
176 static union kvm_mmu_page_role
177 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
179 struct kvm_mmu_role_regs {
180 const unsigned long cr0;
181 const unsigned long cr4;
185 #define CREATE_TRACE_POINTS
186 #include "mmutrace.h"
189 * Yes, lot's of underscores. They're a hint that you probably shouldn't be
190 * reading from the role_regs. Once the mmu_role is constructed, it becomes
191 * the single source of truth for the MMU's state.
193 #define BUILD_MMU_ROLE_REGS_ACCESSOR(reg, name, flag) \
194 static inline bool ____is_##reg##_##name(struct kvm_mmu_role_regs *regs)\
196 return !!(regs->reg & flag); \
198 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, pg, X86_CR0_PG);
199 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, wp, X86_CR0_WP);
200 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pse, X86_CR4_PSE);
201 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pae, X86_CR4_PAE);
202 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smep, X86_CR4_SMEP);
203 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smap, X86_CR4_SMAP);
204 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pke, X86_CR4_PKE);
205 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, la57, X86_CR4_LA57);
206 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, nx, EFER_NX);
207 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, lma, EFER_LMA);
210 * The MMU itself (with a valid role) is the single source of truth for the
211 * MMU. Do not use the regs used to build the MMU/role, nor the vCPU. The
212 * regs don't account for dependencies, e.g. clearing CR4 bits if CR0.PG=1,
213 * and the vCPU may be incorrect/irrelevant.
215 #define BUILD_MMU_ROLE_ACCESSOR(base_or_ext, reg, name) \
216 static inline bool is_##reg##_##name(struct kvm_mmu *mmu) \
218 return !!(mmu->mmu_role. base_or_ext . reg##_##name); \
220 BUILD_MMU_ROLE_ACCESSOR(ext, cr0, pg);
221 BUILD_MMU_ROLE_ACCESSOR(base, cr0, wp);
222 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pse);
223 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pae);
224 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smep);
225 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smap);
226 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pke);
227 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, la57);
228 BUILD_MMU_ROLE_ACCESSOR(base, efer, nx);
230 static struct kvm_mmu_role_regs vcpu_to_role_regs(struct kvm_vcpu *vcpu)
232 struct kvm_mmu_role_regs regs = {
233 .cr0 = kvm_read_cr0_bits(vcpu, KVM_MMU_CR0_ROLE_BITS),
234 .cr4 = kvm_read_cr4_bits(vcpu, KVM_MMU_CR4_ROLE_BITS),
235 .efer = vcpu->arch.efer,
241 static inline bool kvm_available_flush_tlb_with_range(void)
243 return kvm_x86_ops.tlb_remote_flush_with_range;
246 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
247 struct kvm_tlb_range *range)
251 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
252 ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range);
255 kvm_flush_remote_tlbs(kvm);
258 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
259 u64 start_gfn, u64 pages)
261 struct kvm_tlb_range range;
263 range.start_gfn = start_gfn;
266 kvm_flush_remote_tlbs_with_range(kvm, &range);
269 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
272 u64 spte = make_mmio_spte(vcpu, gfn, access);
274 trace_mark_mmio_spte(sptep, gfn, spte);
275 mmu_spte_set(sptep, spte);
278 static gfn_t get_mmio_spte_gfn(u64 spte)
280 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
282 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)
283 & shadow_nonpresent_or_rsvd_mask;
285 return gpa >> PAGE_SHIFT;
288 static unsigned get_mmio_spte_access(u64 spte)
290 return spte & shadow_mmio_access_mask;
293 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
295 u64 kvm_gen, spte_gen, gen;
297 gen = kvm_vcpu_memslots(vcpu)->generation;
298 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
301 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
302 spte_gen = get_mmio_spte_generation(spte);
304 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
305 return likely(kvm_gen == spte_gen);
308 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
309 struct x86_exception *exception)
311 /* Check if guest physical address doesn't exceed guest maximum */
312 if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) {
313 exception->error_code |= PFERR_RSVD_MASK;
320 static int is_cpuid_PSE36(void)
325 static int is_nx(struct kvm_vcpu *vcpu)
327 return vcpu->arch.efer & EFER_NX;
330 static gfn_t pse36_gfn_delta(u32 gpte)
332 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
334 return (gpte & PT32_DIR_PSE36_MASK) << shift;
338 static void __set_spte(u64 *sptep, u64 spte)
340 WRITE_ONCE(*sptep, spte);
343 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
345 WRITE_ONCE(*sptep, spte);
348 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
350 return xchg(sptep, spte);
353 static u64 __get_spte_lockless(u64 *sptep)
355 return READ_ONCE(*sptep);
366 static void count_spte_clear(u64 *sptep, u64 spte)
368 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
370 if (is_shadow_present_pte(spte))
373 /* Ensure the spte is completely set before we increase the count */
375 sp->clear_spte_count++;
378 static void __set_spte(u64 *sptep, u64 spte)
380 union split_spte *ssptep, sspte;
382 ssptep = (union split_spte *)sptep;
383 sspte = (union split_spte)spte;
385 ssptep->spte_high = sspte.spte_high;
388 * If we map the spte from nonpresent to present, We should store
389 * the high bits firstly, then set present bit, so cpu can not
390 * fetch this spte while we are setting the spte.
394 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
397 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
399 union split_spte *ssptep, sspte;
401 ssptep = (union split_spte *)sptep;
402 sspte = (union split_spte)spte;
404 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
407 * If we map the spte from present to nonpresent, we should clear
408 * present bit firstly to avoid vcpu fetch the old high bits.
412 ssptep->spte_high = sspte.spte_high;
413 count_spte_clear(sptep, spte);
416 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
418 union split_spte *ssptep, sspte, orig;
420 ssptep = (union split_spte *)sptep;
421 sspte = (union split_spte)spte;
423 /* xchg acts as a barrier before the setting of the high bits */
424 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
425 orig.spte_high = ssptep->spte_high;
426 ssptep->spte_high = sspte.spte_high;
427 count_spte_clear(sptep, spte);
433 * The idea using the light way get the spte on x86_32 guest is from
434 * gup_get_pte (mm/gup.c).
436 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
437 * coalesces them and we are running out of the MMU lock. Therefore
438 * we need to protect against in-progress updates of the spte.
440 * Reading the spte while an update is in progress may get the old value
441 * for the high part of the spte. The race is fine for a present->non-present
442 * change (because the high part of the spte is ignored for non-present spte),
443 * but for a present->present change we must reread the spte.
445 * All such changes are done in two steps (present->non-present and
446 * non-present->present), hence it is enough to count the number of
447 * present->non-present updates: if it changed while reading the spte,
448 * we might have hit the race. This is done using clear_spte_count.
450 static u64 __get_spte_lockless(u64 *sptep)
452 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
453 union split_spte spte, *orig = (union split_spte *)sptep;
457 count = sp->clear_spte_count;
460 spte.spte_low = orig->spte_low;
463 spte.spte_high = orig->spte_high;
466 if (unlikely(spte.spte_low != orig->spte_low ||
467 count != sp->clear_spte_count))
474 static bool spte_has_volatile_bits(u64 spte)
476 if (!is_shadow_present_pte(spte))
480 * Always atomically update spte if it can be updated
481 * out of mmu-lock, it can ensure dirty bit is not lost,
482 * also, it can help us to get a stable is_writable_pte()
483 * to ensure tlb flush is not missed.
485 if (spte_can_locklessly_be_made_writable(spte) ||
486 is_access_track_spte(spte))
489 if (spte_ad_enabled(spte)) {
490 if ((spte & shadow_accessed_mask) == 0 ||
491 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
498 /* Rules for using mmu_spte_set:
499 * Set the sptep from nonpresent to present.
500 * Note: the sptep being assigned *must* be either not present
501 * or in a state where the hardware will not attempt to update
504 static void mmu_spte_set(u64 *sptep, u64 new_spte)
506 WARN_ON(is_shadow_present_pte(*sptep));
507 __set_spte(sptep, new_spte);
511 * Update the SPTE (excluding the PFN), but do not track changes in its
512 * accessed/dirty status.
514 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
516 u64 old_spte = *sptep;
518 WARN_ON(!is_shadow_present_pte(new_spte));
520 if (!is_shadow_present_pte(old_spte)) {
521 mmu_spte_set(sptep, new_spte);
525 if (!spte_has_volatile_bits(old_spte))
526 __update_clear_spte_fast(sptep, new_spte);
528 old_spte = __update_clear_spte_slow(sptep, new_spte);
530 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
535 /* Rules for using mmu_spte_update:
536 * Update the state bits, it means the mapped pfn is not changed.
538 * Whenever we overwrite a writable spte with a read-only one we
539 * should flush remote TLBs. Otherwise rmap_write_protect
540 * will find a read-only spte, even though the writable spte
541 * might be cached on a CPU's TLB, the return value indicates this
544 * Returns true if the TLB needs to be flushed
546 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
549 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
551 if (!is_shadow_present_pte(old_spte))
555 * For the spte updated out of mmu-lock is safe, since
556 * we always atomically update it, see the comments in
557 * spte_has_volatile_bits().
559 if (spte_can_locklessly_be_made_writable(old_spte) &&
560 !is_writable_pte(new_spte))
564 * Flush TLB when accessed/dirty states are changed in the page tables,
565 * to guarantee consistency between TLB and page tables.
568 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
570 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
573 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
575 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
582 * Rules for using mmu_spte_clear_track_bits:
583 * It sets the sptep from present to nonpresent, and track the
584 * state bits, it is used to clear the last level sptep.
585 * Returns non-zero if the PTE was previously valid.
587 static int mmu_spte_clear_track_bits(u64 *sptep)
590 u64 old_spte = *sptep;
592 if (!spte_has_volatile_bits(old_spte))
593 __update_clear_spte_fast(sptep, 0ull);
595 old_spte = __update_clear_spte_slow(sptep, 0ull);
597 if (!is_shadow_present_pte(old_spte))
600 pfn = spte_to_pfn(old_spte);
603 * KVM does not hold the refcount of the page used by
604 * kvm mmu, before reclaiming the page, we should
605 * unmap it from mmu first.
607 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
609 if (is_accessed_spte(old_spte))
610 kvm_set_pfn_accessed(pfn);
612 if (is_dirty_spte(old_spte))
613 kvm_set_pfn_dirty(pfn);
619 * Rules for using mmu_spte_clear_no_track:
620 * Directly clear spte without caring the state bits of sptep,
621 * it is used to set the upper level spte.
623 static void mmu_spte_clear_no_track(u64 *sptep)
625 __update_clear_spte_fast(sptep, 0ull);
628 static u64 mmu_spte_get_lockless(u64 *sptep)
630 return __get_spte_lockless(sptep);
633 /* Restore an acc-track PTE back to a regular PTE */
634 static u64 restore_acc_track_spte(u64 spte)
637 u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
638 & SHADOW_ACC_TRACK_SAVED_BITS_MASK;
640 WARN_ON_ONCE(spte_ad_enabled(spte));
641 WARN_ON_ONCE(!is_access_track_spte(spte));
643 new_spte &= ~shadow_acc_track_mask;
644 new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
645 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
646 new_spte |= saved_bits;
651 /* Returns the Accessed status of the PTE and resets it at the same time. */
652 static bool mmu_spte_age(u64 *sptep)
654 u64 spte = mmu_spte_get_lockless(sptep);
656 if (!is_accessed_spte(spte))
659 if (spte_ad_enabled(spte)) {
660 clear_bit((ffs(shadow_accessed_mask) - 1),
661 (unsigned long *)sptep);
664 * Capture the dirty status of the page, so that it doesn't get
665 * lost when the SPTE is marked for access tracking.
667 if (is_writable_pte(spte))
668 kvm_set_pfn_dirty(spte_to_pfn(spte));
670 spte = mark_spte_for_access_track(spte);
671 mmu_spte_update_no_track(sptep, spte);
677 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
680 * Prevent page table teardown by making any free-er wait during
681 * kvm_flush_remote_tlbs() IPI to all active vcpus.
686 * Make sure a following spte read is not reordered ahead of the write
689 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
692 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
695 * Make sure the write to vcpu->mode is not reordered in front of
696 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
697 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
699 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
703 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
707 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
708 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
709 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
712 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
713 PT64_ROOT_MAX_LEVEL);
716 if (maybe_indirect) {
717 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
718 PT64_ROOT_MAX_LEVEL);
722 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
723 PT64_ROOT_MAX_LEVEL);
726 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
728 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
729 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
730 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
731 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
734 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
736 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
739 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
741 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
744 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
746 if (!sp->role.direct)
747 return sp->gfns[index];
749 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
752 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
754 if (!sp->role.direct) {
755 sp->gfns[index] = gfn;
759 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
760 pr_err_ratelimited("gfn mismatch under direct page %llx "
761 "(expected %llx, got %llx)\n",
763 kvm_mmu_page_get_gfn(sp, index), gfn);
767 * Return the pointer to the large page information for a given gfn,
768 * handling slots that are not large page aligned.
770 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
771 const struct kvm_memory_slot *slot, int level)
775 idx = gfn_to_index(gfn, slot->base_gfn, level);
776 return &slot->arch.lpage_info[level - 2][idx];
779 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
780 gfn_t gfn, int count)
782 struct kvm_lpage_info *linfo;
785 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
786 linfo = lpage_info_slot(gfn, slot, i);
787 linfo->disallow_lpage += count;
788 WARN_ON(linfo->disallow_lpage < 0);
792 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
794 update_gfn_disallow_lpage_count(slot, gfn, 1);
797 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
799 update_gfn_disallow_lpage_count(slot, gfn, -1);
802 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
804 struct kvm_memslots *slots;
805 struct kvm_memory_slot *slot;
808 kvm->arch.indirect_shadow_pages++;
810 slots = kvm_memslots_for_spte_role(kvm, sp->role);
811 slot = __gfn_to_memslot(slots, gfn);
813 /* the non-leaf shadow pages are keeping readonly. */
814 if (sp->role.level > PG_LEVEL_4K)
815 return kvm_slot_page_track_add_page(kvm, slot, gfn,
816 KVM_PAGE_TRACK_WRITE);
818 kvm_mmu_gfn_disallow_lpage(slot, gfn);
821 void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
823 if (sp->lpage_disallowed)
826 ++kvm->stat.nx_lpage_splits;
827 list_add_tail(&sp->lpage_disallowed_link,
828 &kvm->arch.lpage_disallowed_mmu_pages);
829 sp->lpage_disallowed = true;
832 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
834 struct kvm_memslots *slots;
835 struct kvm_memory_slot *slot;
838 kvm->arch.indirect_shadow_pages--;
840 slots = kvm_memslots_for_spte_role(kvm, sp->role);
841 slot = __gfn_to_memslot(slots, gfn);
842 if (sp->role.level > PG_LEVEL_4K)
843 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
844 KVM_PAGE_TRACK_WRITE);
846 kvm_mmu_gfn_allow_lpage(slot, gfn);
849 void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
851 --kvm->stat.nx_lpage_splits;
852 sp->lpage_disallowed = false;
853 list_del(&sp->lpage_disallowed_link);
856 static struct kvm_memory_slot *
857 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
860 struct kvm_memory_slot *slot;
862 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
863 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
865 if (no_dirty_log && kvm_slot_dirty_track_enabled(slot))
872 * About rmap_head encoding:
874 * If the bit zero of rmap_head->val is clear, then it points to the only spte
875 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
876 * pte_list_desc containing more mappings.
880 * Returns the number of pointers in the rmap chain, not counting the new one.
882 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
883 struct kvm_rmap_head *rmap_head)
885 struct pte_list_desc *desc;
888 if (!rmap_head->val) {
889 rmap_printk("%p %llx 0->1\n", spte, *spte);
890 rmap_head->val = (unsigned long)spte;
891 } else if (!(rmap_head->val & 1)) {
892 rmap_printk("%p %llx 1->many\n", spte, *spte);
893 desc = mmu_alloc_pte_list_desc(vcpu);
894 desc->sptes[0] = (u64 *)rmap_head->val;
895 desc->sptes[1] = spte;
896 rmap_head->val = (unsigned long)desc | 1;
899 rmap_printk("%p %llx many->many\n", spte, *spte);
900 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
901 while (desc->sptes[PTE_LIST_EXT-1]) {
902 count += PTE_LIST_EXT;
905 desc->more = mmu_alloc_pte_list_desc(vcpu);
911 for (i = 0; desc->sptes[i]; ++i)
913 desc->sptes[i] = spte;
919 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
920 struct pte_list_desc *desc, int i,
921 struct pte_list_desc *prev_desc)
925 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
927 desc->sptes[i] = desc->sptes[j];
928 desc->sptes[j] = NULL;
931 if (!prev_desc && !desc->more)
935 prev_desc->more = desc->more;
937 rmap_head->val = (unsigned long)desc->more | 1;
938 mmu_free_pte_list_desc(desc);
941 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
943 struct pte_list_desc *desc;
944 struct pte_list_desc *prev_desc;
947 if (!rmap_head->val) {
948 pr_err("%s: %p 0->BUG\n", __func__, spte);
950 } else if (!(rmap_head->val & 1)) {
951 rmap_printk("%p 1->0\n", spte);
952 if ((u64 *)rmap_head->val != spte) {
953 pr_err("%s: %p 1->BUG\n", __func__, spte);
958 rmap_printk("%p many->many\n", spte);
959 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
962 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
963 if (desc->sptes[i] == spte) {
964 pte_list_desc_remove_entry(rmap_head,
972 pr_err("%s: %p many->many\n", __func__, spte);
977 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
979 mmu_spte_clear_track_bits(sptep);
980 __pte_list_remove(sptep, rmap_head);
983 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
984 struct kvm_memory_slot *slot)
988 idx = gfn_to_index(gfn, slot->base_gfn, level);
989 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
992 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
993 struct kvm_mmu_page *sp)
995 struct kvm_memslots *slots;
996 struct kvm_memory_slot *slot;
998 slots = kvm_memslots_for_spte_role(kvm, sp->role);
999 slot = __gfn_to_memslot(slots, gfn);
1000 return __gfn_to_rmap(gfn, sp->role.level, slot);
1003 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1005 struct kvm_mmu_memory_cache *mc;
1007 mc = &vcpu->arch.mmu_pte_list_desc_cache;
1008 return kvm_mmu_memory_cache_nr_free_objects(mc);
1011 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1013 struct kvm_mmu_page *sp;
1014 struct kvm_rmap_head *rmap_head;
1016 sp = sptep_to_sp(spte);
1017 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1018 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1019 return pte_list_add(vcpu, spte, rmap_head);
1022 static void rmap_remove(struct kvm *kvm, u64 *spte)
1024 struct kvm_mmu_page *sp;
1026 struct kvm_rmap_head *rmap_head;
1028 sp = sptep_to_sp(spte);
1029 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1030 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1031 __pte_list_remove(spte, rmap_head);
1035 * Used by the following functions to iterate through the sptes linked by a
1036 * rmap. All fields are private and not assumed to be used outside.
1038 struct rmap_iterator {
1039 /* private fields */
1040 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1041 int pos; /* index of the sptep */
1045 * Iteration must be started by this function. This should also be used after
1046 * removing/dropping sptes from the rmap link because in such cases the
1047 * information in the iterator may not be valid.
1049 * Returns sptep if found, NULL otherwise.
1051 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1052 struct rmap_iterator *iter)
1056 if (!rmap_head->val)
1059 if (!(rmap_head->val & 1)) {
1061 sptep = (u64 *)rmap_head->val;
1065 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1067 sptep = iter->desc->sptes[iter->pos];
1069 BUG_ON(!is_shadow_present_pte(*sptep));
1074 * Must be used with a valid iterator: e.g. after rmap_get_first().
1076 * Returns sptep if found, NULL otherwise.
1078 static u64 *rmap_get_next(struct rmap_iterator *iter)
1083 if (iter->pos < PTE_LIST_EXT - 1) {
1085 sptep = iter->desc->sptes[iter->pos];
1090 iter->desc = iter->desc->more;
1094 /* desc->sptes[0] cannot be NULL */
1095 sptep = iter->desc->sptes[iter->pos];
1102 BUG_ON(!is_shadow_present_pte(*sptep));
1106 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1107 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1108 _spte_; _spte_ = rmap_get_next(_iter_))
1110 static void drop_spte(struct kvm *kvm, u64 *sptep)
1112 if (mmu_spte_clear_track_bits(sptep))
1113 rmap_remove(kvm, sptep);
1117 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1119 if (is_large_pte(*sptep)) {
1120 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1121 drop_spte(kvm, sptep);
1129 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1131 if (__drop_large_spte(vcpu->kvm, sptep)) {
1132 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1134 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1135 KVM_PAGES_PER_HPAGE(sp->role.level));
1140 * Write-protect on the specified @sptep, @pt_protect indicates whether
1141 * spte write-protection is caused by protecting shadow page table.
1143 * Note: write protection is difference between dirty logging and spte
1145 * - for dirty logging, the spte can be set to writable at anytime if
1146 * its dirty bitmap is properly set.
1147 * - for spte protection, the spte can be writable only after unsync-ing
1150 * Return true if tlb need be flushed.
1152 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1156 if (!is_writable_pte(spte) &&
1157 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1160 rmap_printk("spte %p %llx\n", sptep, *sptep);
1163 spte &= ~shadow_mmu_writable_mask;
1164 spte = spte & ~PT_WRITABLE_MASK;
1166 return mmu_spte_update(sptep, spte);
1169 static bool __rmap_write_protect(struct kvm *kvm,
1170 struct kvm_rmap_head *rmap_head,
1174 struct rmap_iterator iter;
1177 for_each_rmap_spte(rmap_head, &iter, sptep)
1178 flush |= spte_write_protect(sptep, pt_protect);
1183 static bool spte_clear_dirty(u64 *sptep)
1187 rmap_printk("spte %p %llx\n", sptep, *sptep);
1189 MMU_WARN_ON(!spte_ad_enabled(spte));
1190 spte &= ~shadow_dirty_mask;
1191 return mmu_spte_update(sptep, spte);
1194 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1196 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1197 (unsigned long *)sptep);
1198 if (was_writable && !spte_ad_enabled(*sptep))
1199 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1201 return was_writable;
1205 * Gets the GFN ready for another round of dirty logging by clearing the
1206 * - D bit on ad-enabled SPTEs, and
1207 * - W bit on ad-disabled SPTEs.
1208 * Returns true iff any D or W bits were cleared.
1210 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1211 struct kvm_memory_slot *slot)
1214 struct rmap_iterator iter;
1217 for_each_rmap_spte(rmap_head, &iter, sptep)
1218 if (spte_ad_need_write_protect(*sptep))
1219 flush |= spte_wrprot_for_clear_dirty(sptep);
1221 flush |= spte_clear_dirty(sptep);
1227 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1228 * @kvm: kvm instance
1229 * @slot: slot to protect
1230 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1231 * @mask: indicates which pages we should protect
1233 * Used when we do not need to care about huge page mappings.
1235 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1236 struct kvm_memory_slot *slot,
1237 gfn_t gfn_offset, unsigned long mask)
1239 struct kvm_rmap_head *rmap_head;
1241 if (is_tdp_mmu_enabled(kvm))
1242 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1243 slot->base_gfn + gfn_offset, mask, true);
1245 if (!kvm_memslots_have_rmaps(kvm))
1249 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1251 __rmap_write_protect(kvm, rmap_head, false);
1253 /* clear the first set bit */
1259 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1260 * protect the page if the D-bit isn't supported.
1261 * @kvm: kvm instance
1262 * @slot: slot to clear D-bit
1263 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1264 * @mask: indicates which pages we should clear D-bit
1266 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1268 static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1269 struct kvm_memory_slot *slot,
1270 gfn_t gfn_offset, unsigned long mask)
1272 struct kvm_rmap_head *rmap_head;
1274 if (is_tdp_mmu_enabled(kvm))
1275 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1276 slot->base_gfn + gfn_offset, mask, false);
1278 if (!kvm_memslots_have_rmaps(kvm))
1282 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1284 __rmap_clear_dirty(kvm, rmap_head, slot);
1286 /* clear the first set bit */
1292 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1295 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1296 * enable dirty logging for them.
1298 * We need to care about huge page mappings: e.g. during dirty logging we may
1299 * have such mappings.
1301 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1302 struct kvm_memory_slot *slot,
1303 gfn_t gfn_offset, unsigned long mask)
1306 * Huge pages are NOT write protected when we start dirty logging in
1307 * initially-all-set mode; must write protect them here so that they
1308 * are split to 4K on the first write.
1310 * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn
1311 * of memslot has no such restriction, so the range can cross two large
1314 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) {
1315 gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask);
1316 gfn_t end = slot->base_gfn + gfn_offset + __fls(mask);
1318 kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M);
1320 /* Cross two large pages? */
1321 if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) !=
1322 ALIGN(end << PAGE_SHIFT, PMD_SIZE))
1323 kvm_mmu_slot_gfn_write_protect(kvm, slot, end,
1327 /* Now handle 4K PTEs. */
1328 if (kvm_x86_ops.cpu_dirty_log_size)
1329 kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask);
1331 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1334 int kvm_cpu_dirty_log_size(void)
1336 return kvm_x86_ops.cpu_dirty_log_size;
1339 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1340 struct kvm_memory_slot *slot, u64 gfn,
1343 struct kvm_rmap_head *rmap_head;
1345 bool write_protected = false;
1347 if (kvm_memslots_have_rmaps(kvm)) {
1348 for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1349 rmap_head = __gfn_to_rmap(gfn, i, slot);
1350 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1354 if (is_tdp_mmu_enabled(kvm))
1356 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level);
1358 return write_protected;
1361 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1363 struct kvm_memory_slot *slot;
1365 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1366 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K);
1369 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1370 struct kvm_memory_slot *slot)
1373 struct rmap_iterator iter;
1376 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1377 rmap_printk("spte %p %llx.\n", sptep, *sptep);
1379 pte_list_remove(rmap_head, sptep);
1386 static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1387 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1390 return kvm_zap_rmapp(kvm, rmap_head, slot);
1393 static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1394 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1398 struct rmap_iterator iter;
1403 WARN_ON(pte_huge(pte));
1404 new_pfn = pte_pfn(pte);
1407 for_each_rmap_spte(rmap_head, &iter, sptep) {
1408 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1409 sptep, *sptep, gfn, level);
1413 if (pte_write(pte)) {
1414 pte_list_remove(rmap_head, sptep);
1417 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1420 mmu_spte_clear_track_bits(sptep);
1421 mmu_spte_set(sptep, new_spte);
1425 if (need_flush && kvm_available_flush_tlb_with_range()) {
1426 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1433 struct slot_rmap_walk_iterator {
1435 struct kvm_memory_slot *slot;
1441 /* output fields. */
1443 struct kvm_rmap_head *rmap;
1446 /* private field. */
1447 struct kvm_rmap_head *end_rmap;
1451 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1453 iterator->level = level;
1454 iterator->gfn = iterator->start_gfn;
1455 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1456 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1461 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1462 struct kvm_memory_slot *slot, int start_level,
1463 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1465 iterator->slot = slot;
1466 iterator->start_level = start_level;
1467 iterator->end_level = end_level;
1468 iterator->start_gfn = start_gfn;
1469 iterator->end_gfn = end_gfn;
1471 rmap_walk_init_level(iterator, iterator->start_level);
1474 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1476 return !!iterator->rmap;
1479 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1481 if (++iterator->rmap <= iterator->end_rmap) {
1482 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1486 if (++iterator->level > iterator->end_level) {
1487 iterator->rmap = NULL;
1491 rmap_walk_init_level(iterator, iterator->level);
1494 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1495 _start_gfn, _end_gfn, _iter_) \
1496 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1497 _end_level_, _start_gfn, _end_gfn); \
1498 slot_rmap_walk_okay(_iter_); \
1499 slot_rmap_walk_next(_iter_))
1501 typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1502 struct kvm_memory_slot *slot, gfn_t gfn,
1503 int level, pte_t pte);
1505 static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm,
1506 struct kvm_gfn_range *range,
1507 rmap_handler_t handler)
1509 struct slot_rmap_walk_iterator iterator;
1512 for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL,
1513 range->start, range->end - 1, &iterator)
1514 ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn,
1515 iterator.level, range->pte);
1520 bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range)
1524 if (kvm_memslots_have_rmaps(kvm))
1525 flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp);
1527 if (is_tdp_mmu_enabled(kvm))
1528 flush |= kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush);
1533 bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1537 if (kvm_memslots_have_rmaps(kvm))
1538 flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp);
1540 if (is_tdp_mmu_enabled(kvm))
1541 flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range);
1546 static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1547 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1551 struct rmap_iterator iter;
1554 for_each_rmap_spte(rmap_head, &iter, sptep)
1555 young |= mmu_spte_age(sptep);
1560 static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1561 struct kvm_memory_slot *slot, gfn_t gfn,
1562 int level, pte_t unused)
1565 struct rmap_iterator iter;
1567 for_each_rmap_spte(rmap_head, &iter, sptep)
1568 if (is_accessed_spte(*sptep))
1573 #define RMAP_RECYCLE_THRESHOLD 1000
1575 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1577 struct kvm_rmap_head *rmap_head;
1578 struct kvm_mmu_page *sp;
1580 sp = sptep_to_sp(spte);
1582 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1584 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0));
1585 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1586 KVM_PAGES_PER_HPAGE(sp->role.level));
1589 bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1593 if (kvm_memslots_have_rmaps(kvm))
1594 young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp);
1596 if (is_tdp_mmu_enabled(kvm))
1597 young |= kvm_tdp_mmu_age_gfn_range(kvm, range);
1602 bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1606 if (kvm_memslots_have_rmaps(kvm))
1607 young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp);
1609 if (is_tdp_mmu_enabled(kvm))
1610 young |= kvm_tdp_mmu_test_age_gfn(kvm, range);
1616 static int is_empty_shadow_page(u64 *spt)
1621 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1622 if (is_shadow_present_pte(*pos)) {
1623 printk(KERN_ERR "%s: %p %llx\n", __func__,
1632 * This value is the sum of all of the kvm instances's
1633 * kvm->arch.n_used_mmu_pages values. We need a global,
1634 * aggregate version in order to make the slab shrinker
1637 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
1639 kvm->arch.n_used_mmu_pages += nr;
1640 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1643 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1645 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1646 hlist_del(&sp->hash_link);
1647 list_del(&sp->link);
1648 free_page((unsigned long)sp->spt);
1649 if (!sp->role.direct)
1650 free_page((unsigned long)sp->gfns);
1651 kmem_cache_free(mmu_page_header_cache, sp);
1654 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1656 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1659 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1660 struct kvm_mmu_page *sp, u64 *parent_pte)
1665 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1668 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1671 __pte_list_remove(parent_pte, &sp->parent_ptes);
1674 static void drop_parent_pte(struct kvm_mmu_page *sp,
1677 mmu_page_remove_parent_pte(sp, parent_pte);
1678 mmu_spte_clear_no_track(parent_pte);
1681 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1683 struct kvm_mmu_page *sp;
1685 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1686 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1688 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1689 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1692 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1693 * depends on valid pages being added to the head of the list. See
1694 * comments in kvm_zap_obsolete_pages().
1696 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1697 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1698 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1702 static void mark_unsync(u64 *spte);
1703 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1706 struct rmap_iterator iter;
1708 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1713 static void mark_unsync(u64 *spte)
1715 struct kvm_mmu_page *sp;
1718 sp = sptep_to_sp(spte);
1719 index = spte - sp->spt;
1720 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1722 if (sp->unsync_children++)
1724 kvm_mmu_mark_parents_unsync(sp);
1727 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1728 struct kvm_mmu_page *sp)
1733 #define KVM_PAGE_ARRAY_NR 16
1735 struct kvm_mmu_pages {
1736 struct mmu_page_and_offset {
1737 struct kvm_mmu_page *sp;
1739 } page[KVM_PAGE_ARRAY_NR];
1743 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1749 for (i=0; i < pvec->nr; i++)
1750 if (pvec->page[i].sp == sp)
1753 pvec->page[pvec->nr].sp = sp;
1754 pvec->page[pvec->nr].idx = idx;
1756 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1759 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1761 --sp->unsync_children;
1762 WARN_ON((int)sp->unsync_children < 0);
1763 __clear_bit(idx, sp->unsync_child_bitmap);
1766 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1767 struct kvm_mmu_pages *pvec)
1769 int i, ret, nr_unsync_leaf = 0;
1771 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1772 struct kvm_mmu_page *child;
1773 u64 ent = sp->spt[i];
1775 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1776 clear_unsync_child_bit(sp, i);
1780 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1782 if (child->unsync_children) {
1783 if (mmu_pages_add(pvec, child, i))
1786 ret = __mmu_unsync_walk(child, pvec);
1788 clear_unsync_child_bit(sp, i);
1790 } else if (ret > 0) {
1791 nr_unsync_leaf += ret;
1794 } else if (child->unsync) {
1796 if (mmu_pages_add(pvec, child, i))
1799 clear_unsync_child_bit(sp, i);
1802 return nr_unsync_leaf;
1805 #define INVALID_INDEX (-1)
1807 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1808 struct kvm_mmu_pages *pvec)
1811 if (!sp->unsync_children)
1814 mmu_pages_add(pvec, sp, INVALID_INDEX);
1815 return __mmu_unsync_walk(sp, pvec);
1818 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1820 WARN_ON(!sp->unsync);
1821 trace_kvm_mmu_sync_page(sp);
1823 --kvm->stat.mmu_unsync;
1826 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1827 struct list_head *invalid_list);
1828 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1829 struct list_head *invalid_list);
1831 #define for_each_valid_sp(_kvm, _sp, _list) \
1832 hlist_for_each_entry(_sp, _list, hash_link) \
1833 if (is_obsolete_sp((_kvm), (_sp))) { \
1836 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1837 for_each_valid_sp(_kvm, _sp, \
1838 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1839 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1841 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1842 struct list_head *invalid_list)
1844 if (vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
1845 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1852 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1853 struct list_head *invalid_list,
1856 if (!remote_flush && list_empty(invalid_list))
1859 if (!list_empty(invalid_list))
1860 kvm_mmu_commit_zap_page(kvm, invalid_list);
1862 kvm_flush_remote_tlbs(kvm);
1866 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1867 struct list_head *invalid_list,
1868 bool remote_flush, bool local_flush)
1870 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
1874 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1877 #ifdef CONFIG_KVM_MMU_AUDIT
1878 #include "mmu_audit.c"
1880 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1881 static void mmu_audit_disable(void) { }
1884 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1886 return sp->role.invalid ||
1887 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1890 struct mmu_page_path {
1891 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1892 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1895 #define for_each_sp(pvec, sp, parents, i) \
1896 for (i = mmu_pages_first(&pvec, &parents); \
1897 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1898 i = mmu_pages_next(&pvec, &parents, i))
1900 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1901 struct mmu_page_path *parents,
1906 for (n = i+1; n < pvec->nr; n++) {
1907 struct kvm_mmu_page *sp = pvec->page[n].sp;
1908 unsigned idx = pvec->page[n].idx;
1909 int level = sp->role.level;
1911 parents->idx[level-1] = idx;
1912 if (level == PG_LEVEL_4K)
1915 parents->parent[level-2] = sp;
1921 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1922 struct mmu_page_path *parents)
1924 struct kvm_mmu_page *sp;
1930 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1932 sp = pvec->page[0].sp;
1933 level = sp->role.level;
1934 WARN_ON(level == PG_LEVEL_4K);
1936 parents->parent[level-2] = sp;
1938 /* Also set up a sentinel. Further entries in pvec are all
1939 * children of sp, so this element is never overwritten.
1941 parents->parent[level-1] = NULL;
1942 return mmu_pages_next(pvec, parents, 0);
1945 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1947 struct kvm_mmu_page *sp;
1948 unsigned int level = 0;
1951 unsigned int idx = parents->idx[level];
1952 sp = parents->parent[level];
1956 WARN_ON(idx == INVALID_INDEX);
1957 clear_unsync_child_bit(sp, idx);
1959 } while (!sp->unsync_children);
1962 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1963 struct kvm_mmu_page *parent)
1966 struct kvm_mmu_page *sp;
1967 struct mmu_page_path parents;
1968 struct kvm_mmu_pages pages;
1969 LIST_HEAD(invalid_list);
1972 while (mmu_unsync_walk(parent, &pages)) {
1973 bool protected = false;
1975 for_each_sp(pages, sp, parents, i)
1976 protected |= rmap_write_protect(vcpu, sp->gfn);
1979 kvm_flush_remote_tlbs(vcpu->kvm);
1983 for_each_sp(pages, sp, parents, i) {
1984 kvm_unlink_unsync_page(vcpu->kvm, sp);
1985 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
1986 mmu_pages_clear_parents(&parents);
1988 if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) {
1989 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1990 cond_resched_rwlock_write(&vcpu->kvm->mmu_lock);
1995 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1998 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2000 atomic_set(&sp->write_flooding_count, 0);
2003 static void clear_sp_write_flooding_count(u64 *spte)
2005 __clear_sp_write_flooding_count(sptep_to_sp(spte));
2008 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2013 unsigned int access)
2015 bool direct_mmu = vcpu->arch.mmu->direct_map;
2016 union kvm_mmu_page_role role;
2017 struct hlist_head *sp_list;
2019 struct kvm_mmu_page *sp;
2021 LIST_HEAD(invalid_list);
2023 role = vcpu->arch.mmu->mmu_role.base;
2025 role.direct = direct;
2027 role.gpte_is_8_bytes = true;
2028 role.access = access;
2029 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2030 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2031 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2032 role.quadrant = quadrant;
2035 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2036 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2037 if (sp->gfn != gfn) {
2042 if (sp->role.word != role.word) {
2044 * If the guest is creating an upper-level page, zap
2045 * unsync pages for the same gfn. While it's possible
2046 * the guest is using recursive page tables, in all
2047 * likelihood the guest has stopped using the unsync
2048 * page and is installing a completely unrelated page.
2049 * Unsync pages must not be left as is, because the new
2050 * upper-level page will be write-protected.
2052 if (level > PG_LEVEL_4K && sp->unsync)
2053 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2059 goto trace_get_page;
2063 * The page is good, but is stale. kvm_sync_page does
2064 * get the latest guest state, but (unlike mmu_unsync_children)
2065 * it doesn't write-protect the page or mark it synchronized!
2066 * This way the validity of the mapping is ensured, but the
2067 * overhead of write protection is not incurred until the
2068 * guest invalidates the TLB mapping. This allows multiple
2069 * SPs for a single gfn to be unsync.
2071 * If the sync fails, the page is zapped. If so, break
2072 * in order to rebuild it.
2074 if (!kvm_sync_page(vcpu, sp, &invalid_list))
2077 WARN_ON(!list_empty(&invalid_list));
2078 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2081 if (sp->unsync_children)
2082 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2084 __clear_sp_write_flooding_count(sp);
2087 trace_kvm_mmu_get_page(sp, false);
2091 ++vcpu->kvm->stat.mmu_cache_miss;
2093 sp = kvm_mmu_alloc_page(vcpu, direct);
2097 hlist_add_head(&sp->hash_link, sp_list);
2099 account_shadowed(vcpu->kvm, sp);
2100 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2101 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2103 trace_kvm_mmu_get_page(sp, true);
2105 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2107 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2108 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2112 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2113 struct kvm_vcpu *vcpu, hpa_t root,
2116 iterator->addr = addr;
2117 iterator->shadow_addr = root;
2118 iterator->level = vcpu->arch.mmu->shadow_root_level;
2120 if (iterator->level == PT64_ROOT_4LEVEL &&
2121 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2122 !vcpu->arch.mmu->direct_map)
2125 if (iterator->level == PT32E_ROOT_LEVEL) {
2127 * prev_root is currently only used for 64-bit hosts. So only
2128 * the active root_hpa is valid here.
2130 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2132 iterator->shadow_addr
2133 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2134 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2136 if (!iterator->shadow_addr)
2137 iterator->level = 0;
2141 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2142 struct kvm_vcpu *vcpu, u64 addr)
2144 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2148 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2150 if (iterator->level < PG_LEVEL_4K)
2153 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2154 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2158 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2161 if (is_last_spte(spte, iterator->level)) {
2162 iterator->level = 0;
2166 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2170 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2172 __shadow_walk_next(iterator, *iterator->sptep);
2175 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2176 struct kvm_mmu_page *sp)
2180 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2182 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2184 mmu_spte_set(sptep, spte);
2186 mmu_page_add_parent_pte(vcpu, sp, sptep);
2188 if (sp->unsync_children || sp->unsync)
2192 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2193 unsigned direct_access)
2195 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2196 struct kvm_mmu_page *child;
2199 * For the direct sp, if the guest pte's dirty bit
2200 * changed form clean to dirty, it will corrupt the
2201 * sp's access: allow writable in the read-only sp,
2202 * so we should update the spte at this point to get
2203 * a new sp with the correct access.
2205 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2206 if (child->role.access == direct_access)
2209 drop_parent_pte(child, sptep);
2210 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2214 /* Returns the number of zapped non-leaf child shadow pages. */
2215 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2216 u64 *spte, struct list_head *invalid_list)
2219 struct kvm_mmu_page *child;
2222 if (is_shadow_present_pte(pte)) {
2223 if (is_last_spte(pte, sp->role.level)) {
2224 drop_spte(kvm, spte);
2225 if (is_large_pte(pte))
2228 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2229 drop_parent_pte(child, spte);
2232 * Recursively zap nested TDP SPs, parentless SPs are
2233 * unlikely to be used again in the near future. This
2234 * avoids retaining a large number of stale nested SPs.
2236 if (tdp_enabled && invalid_list &&
2237 child->role.guest_mode && !child->parent_ptes.val)
2238 return kvm_mmu_prepare_zap_page(kvm, child,
2241 } else if (is_mmio_spte(pte)) {
2242 mmu_spte_clear_no_track(spte);
2247 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2248 struct kvm_mmu_page *sp,
2249 struct list_head *invalid_list)
2254 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2255 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2260 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2263 struct rmap_iterator iter;
2265 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2266 drop_parent_pte(sp, sptep);
2269 static int mmu_zap_unsync_children(struct kvm *kvm,
2270 struct kvm_mmu_page *parent,
2271 struct list_head *invalid_list)
2274 struct mmu_page_path parents;
2275 struct kvm_mmu_pages pages;
2277 if (parent->role.level == PG_LEVEL_4K)
2280 while (mmu_unsync_walk(parent, &pages)) {
2281 struct kvm_mmu_page *sp;
2283 for_each_sp(pages, sp, parents, i) {
2284 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2285 mmu_pages_clear_parents(&parents);
2293 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2294 struct kvm_mmu_page *sp,
2295 struct list_head *invalid_list,
2300 trace_kvm_mmu_prepare_zap_page(sp);
2301 ++kvm->stat.mmu_shadow_zapped;
2302 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2303 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2304 kvm_mmu_unlink_parents(kvm, sp);
2306 /* Zapping children means active_mmu_pages has become unstable. */
2307 list_unstable = *nr_zapped;
2309 if (!sp->role.invalid && !sp->role.direct)
2310 unaccount_shadowed(kvm, sp);
2313 kvm_unlink_unsync_page(kvm, sp);
2314 if (!sp->root_count) {
2319 * Already invalid pages (previously active roots) are not on
2320 * the active page list. See list_del() in the "else" case of
2323 if (sp->role.invalid)
2324 list_add(&sp->link, invalid_list);
2326 list_move(&sp->link, invalid_list);
2327 kvm_mod_used_mmu_pages(kvm, -1);
2330 * Remove the active root from the active page list, the root
2331 * will be explicitly freed when the root_count hits zero.
2333 list_del(&sp->link);
2336 * Obsolete pages cannot be used on any vCPUs, see the comment
2337 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2338 * treats invalid shadow pages as being obsolete.
2340 if (!is_obsolete_sp(kvm, sp))
2341 kvm_reload_remote_mmus(kvm);
2344 if (sp->lpage_disallowed)
2345 unaccount_huge_nx_page(kvm, sp);
2347 sp->role.invalid = 1;
2348 return list_unstable;
2351 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2352 struct list_head *invalid_list)
2356 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2360 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2361 struct list_head *invalid_list)
2363 struct kvm_mmu_page *sp, *nsp;
2365 if (list_empty(invalid_list))
2369 * We need to make sure everyone sees our modifications to
2370 * the page tables and see changes to vcpu->mode here. The barrier
2371 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2372 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2374 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2375 * guest mode and/or lockless shadow page table walks.
2377 kvm_flush_remote_tlbs(kvm);
2379 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2380 WARN_ON(!sp->role.invalid || sp->root_count);
2381 kvm_mmu_free_page(sp);
2385 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2386 unsigned long nr_to_zap)
2388 unsigned long total_zapped = 0;
2389 struct kvm_mmu_page *sp, *tmp;
2390 LIST_HEAD(invalid_list);
2394 if (list_empty(&kvm->arch.active_mmu_pages))
2398 list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2400 * Don't zap active root pages, the page itself can't be freed
2401 * and zapping it will just force vCPUs to realloc and reload.
2406 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2408 total_zapped += nr_zapped;
2409 if (total_zapped >= nr_to_zap)
2416 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2418 kvm->stat.mmu_recycled += total_zapped;
2419 return total_zapped;
2422 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2424 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2425 return kvm->arch.n_max_mmu_pages -
2426 kvm->arch.n_used_mmu_pages;
2431 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2433 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2435 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2438 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2441 * Note, this check is intentionally soft, it only guarantees that one
2442 * page is available, while the caller may end up allocating as many as
2443 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2444 * exceeding the (arbitrary by default) limit will not harm the host,
2445 * being too agressive may unnecessarily kill the guest, and getting an
2446 * exact count is far more trouble than it's worth, especially in the
2449 if (!kvm_mmu_available_pages(vcpu->kvm))
2455 * Changing the number of mmu pages allocated to the vm
2456 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2458 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2460 write_lock(&kvm->mmu_lock);
2462 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2463 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2466 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2469 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2471 write_unlock(&kvm->mmu_lock);
2474 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2476 struct kvm_mmu_page *sp;
2477 LIST_HEAD(invalid_list);
2480 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2482 write_lock(&kvm->mmu_lock);
2483 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2484 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2487 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2489 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2490 write_unlock(&kvm->mmu_lock);
2495 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2500 if (vcpu->arch.mmu->direct_map)
2503 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2505 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2510 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2512 trace_kvm_mmu_unsync_page(sp);
2513 ++vcpu->kvm->stat.mmu_unsync;
2516 kvm_mmu_mark_parents_unsync(sp);
2520 * Attempt to unsync any shadow pages that can be reached by the specified gfn,
2521 * KVM is creating a writable mapping for said gfn. Returns 0 if all pages
2522 * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must
2523 * be write-protected.
2525 int mmu_try_to_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, bool can_unsync)
2527 struct kvm_mmu_page *sp;
2530 * Force write-protection if the page is being tracked. Note, the page
2531 * track machinery is used to write-protect upper-level shadow pages,
2532 * i.e. this guards the role.level == 4K assertion below!
2534 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2538 * The page is not write-tracked, mark existing shadow pages unsync
2539 * unless KVM is synchronizing an unsync SP (can_unsync = false). In
2540 * that case, KVM must complete emulation of the guest TLB flush before
2541 * allowing shadow pages to become unsync (writable by the guest).
2543 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2550 WARN_ON(sp->role.level != PG_LEVEL_4K);
2551 kvm_unsync_page(vcpu, sp);
2555 * We need to ensure that the marking of unsync pages is visible
2556 * before the SPTE is updated to allow writes because
2557 * kvm_mmu_sync_roots() checks the unsync flags without holding
2558 * the MMU lock and so can race with this. If the SPTE was updated
2559 * before the page had been marked as unsync-ed, something like the
2560 * following could happen:
2563 * ---------------------------------------------------------------------
2564 * 1.2 Host updates SPTE
2566 * 2.1 Guest writes a GPTE for GVA X.
2567 * (GPTE being in the guest page table shadowed
2568 * by the SP from CPU 1.)
2569 * This reads SPTE during the page table walk.
2570 * Since SPTE.W is read as 1, there is no
2573 * 2.2 Guest issues TLB flush.
2574 * That causes a VM Exit.
2576 * 2.3 Walking of unsync pages sees sp->unsync is
2577 * false and skips the page.
2579 * 2.4 Guest accesses GVA X.
2580 * Since the mapping in the SP was not updated,
2581 * so the old mapping for GVA X incorrectly
2585 * (sp->unsync = true)
2587 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2588 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2589 * pairs with this write barrier.
2596 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2597 unsigned int pte_access, int level,
2598 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2599 bool can_unsync, bool host_writable)
2602 struct kvm_mmu_page *sp;
2605 sp = sptep_to_sp(sptep);
2607 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2608 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2610 if (spte & PT_WRITABLE_MASK)
2611 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2614 ret |= SET_SPTE_SPURIOUS;
2615 else if (mmu_spte_update(sptep, spte))
2616 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2620 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2621 unsigned int pte_access, bool write_fault, int level,
2622 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2625 int was_rmapped = 0;
2628 int ret = RET_PF_FIXED;
2631 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2632 *sptep, write_fault, gfn);
2634 if (unlikely(is_noslot_pfn(pfn))) {
2635 mark_mmio_spte(vcpu, sptep, gfn, pte_access);
2636 return RET_PF_EMULATE;
2639 if (is_shadow_present_pte(*sptep)) {
2641 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2642 * the parent of the now unreachable PTE.
2644 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2645 struct kvm_mmu_page *child;
2648 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2649 drop_parent_pte(child, sptep);
2651 } else if (pfn != spte_to_pfn(*sptep)) {
2652 pgprintk("hfn old %llx new %llx\n",
2653 spte_to_pfn(*sptep), pfn);
2654 drop_spte(vcpu->kvm, sptep);
2660 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2661 speculative, true, host_writable);
2662 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2664 ret = RET_PF_EMULATE;
2665 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2668 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2669 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2670 KVM_PAGES_PER_HPAGE(level));
2673 * The fault is fully spurious if and only if the new SPTE and old SPTE
2674 * are identical, and emulation is not required.
2676 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2677 WARN_ON_ONCE(!was_rmapped);
2678 return RET_PF_SPURIOUS;
2681 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2682 trace_kvm_mmu_set_spte(level, gfn, sptep);
2683 if (!was_rmapped && is_large_pte(*sptep))
2684 ++vcpu->kvm->stat.lpages;
2686 if (is_shadow_present_pte(*sptep)) {
2688 rmap_count = rmap_add(vcpu, sptep, gfn);
2689 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2690 rmap_recycle(vcpu, sptep, gfn);
2697 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2700 struct kvm_memory_slot *slot;
2702 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2704 return KVM_PFN_ERR_FAULT;
2706 return gfn_to_pfn_memslot_atomic(slot, gfn);
2709 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2710 struct kvm_mmu_page *sp,
2711 u64 *start, u64 *end)
2713 struct page *pages[PTE_PREFETCH_NUM];
2714 struct kvm_memory_slot *slot;
2715 unsigned int access = sp->role.access;
2719 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2720 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2724 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2728 for (i = 0; i < ret; i++, gfn++, start++) {
2729 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2730 page_to_pfn(pages[i]), true, true);
2737 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2738 struct kvm_mmu_page *sp, u64 *sptep)
2740 u64 *spte, *start = NULL;
2743 WARN_ON(!sp->role.direct);
2745 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2748 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2749 if (is_shadow_present_pte(*spte) || spte == sptep) {
2752 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2760 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2762 struct kvm_mmu_page *sp;
2764 sp = sptep_to_sp(sptep);
2767 * Without accessed bits, there's no way to distinguish between
2768 * actually accessed translations and prefetched, so disable pte
2769 * prefetch if accessed bits aren't available.
2771 if (sp_ad_disabled(sp))
2774 if (sp->role.level > PG_LEVEL_4K)
2778 * If addresses are being invalidated, skip prefetching to avoid
2779 * accidentally prefetching those addresses.
2781 if (unlikely(vcpu->kvm->mmu_notifier_count))
2784 __direct_pte_prefetch(vcpu, sp, sptep);
2787 static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
2788 const struct kvm_memory_slot *slot)
2794 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2798 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2799 * is not solely for performance, it's also necessary to avoid the
2800 * "writable" check in __gfn_to_hva_many(), which will always fail on
2801 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2802 * page fault steps have already verified the guest isn't writing a
2803 * read-only memslot.
2805 hva = __gfn_to_hva_memslot(slot, gfn);
2807 pte = lookup_address_in_mm(kvm->mm, hva, &level);
2814 int kvm_mmu_max_mapping_level(struct kvm *kvm,
2815 const struct kvm_memory_slot *slot, gfn_t gfn,
2816 kvm_pfn_t pfn, int max_level)
2818 struct kvm_lpage_info *linfo;
2820 max_level = min(max_level, max_huge_page_level);
2821 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2822 linfo = lpage_info_slot(gfn, slot, max_level);
2823 if (!linfo->disallow_lpage)
2827 if (max_level == PG_LEVEL_4K)
2830 return host_pfn_mapping_level(kvm, gfn, pfn, slot);
2833 int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2834 int max_level, kvm_pfn_t *pfnp,
2835 bool huge_page_disallowed, int *req_level)
2837 struct kvm_memory_slot *slot;
2838 kvm_pfn_t pfn = *pfnp;
2842 *req_level = PG_LEVEL_4K;
2844 if (unlikely(max_level == PG_LEVEL_4K))
2847 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
2850 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2854 level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level);
2855 if (level == PG_LEVEL_4K)
2858 *req_level = level = min(level, max_level);
2861 * Enforce the iTLB multihit workaround after capturing the requested
2862 * level, which will be used to do precise, accurate accounting.
2864 if (huge_page_disallowed)
2868 * mmu_notifier_retry() was successful and mmu_lock is held, so
2869 * the pmd can't be split from under us.
2871 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2872 VM_BUG_ON((gfn & mask) != (pfn & mask));
2873 *pfnp = pfn & ~mask;
2878 void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2879 kvm_pfn_t *pfnp, int *goal_levelp)
2881 int level = *goal_levelp;
2883 if (cur_level == level && level > PG_LEVEL_4K &&
2884 is_shadow_present_pte(spte) &&
2885 !is_large_pte(spte)) {
2887 * A small SPTE exists for this pfn, but FNAME(fetch)
2888 * and __direct_map would like to create a large PTE
2889 * instead: just force them to go down another level,
2890 * patching back for them into pfn the next 9 bits of
2893 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2894 KVM_PAGES_PER_HPAGE(level - 1);
2895 *pfnp |= gfn & page_mask;
2900 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
2901 int map_writable, int max_level, kvm_pfn_t pfn,
2902 bool prefault, bool is_tdp)
2904 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2905 bool write = error_code & PFERR_WRITE_MASK;
2906 bool exec = error_code & PFERR_FETCH_MASK;
2907 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
2908 struct kvm_shadow_walk_iterator it;
2909 struct kvm_mmu_page *sp;
2910 int level, req_level, ret;
2911 gfn_t gfn = gpa >> PAGE_SHIFT;
2912 gfn_t base_gfn = gfn;
2914 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2915 huge_page_disallowed, &req_level);
2917 trace_kvm_mmu_spte_requested(gpa, level, pfn);
2918 for_each_shadow_entry(vcpu, gpa, it) {
2920 * We cannot overwrite existing page tables with an NX
2921 * large page, as the leaf could be executable.
2923 if (nx_huge_page_workaround_enabled)
2924 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
2927 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2928 if (it.level == level)
2931 drop_large_spte(vcpu, it.sptep);
2932 if (!is_shadow_present_pte(*it.sptep)) {
2933 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2934 it.level - 1, true, ACC_ALL);
2936 link_shadow_page(vcpu, it.sptep, sp);
2937 if (is_tdp && huge_page_disallowed &&
2938 req_level >= it.level)
2939 account_huge_nx_page(vcpu->kvm, sp);
2943 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2944 write, level, base_gfn, pfn, prefault,
2946 if (ret == RET_PF_SPURIOUS)
2949 direct_pte_prefetch(vcpu, it.sptep);
2950 ++vcpu->stat.pf_fixed;
2954 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2956 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2959 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2962 * Do not cache the mmio info caused by writing the readonly gfn
2963 * into the spte otherwise read access on readonly gfn also can
2964 * caused mmio page fault and treat it as mmio access.
2966 if (pfn == KVM_PFN_ERR_RO_FAULT)
2967 return RET_PF_EMULATE;
2969 if (pfn == KVM_PFN_ERR_HWPOISON) {
2970 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2971 return RET_PF_RETRY;
2977 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2978 kvm_pfn_t pfn, unsigned int access,
2981 /* The pfn is invalid, report the error! */
2982 if (unlikely(is_error_pfn(pfn))) {
2983 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2987 if (unlikely(is_noslot_pfn(pfn))) {
2988 vcpu_cache_mmio_info(vcpu, gva, gfn,
2989 access & shadow_mmio_access_mask);
2991 * If MMIO caching is disabled, emulate immediately without
2992 * touching the shadow page tables as attempting to install an
2993 * MMIO SPTE will just be an expensive nop.
2995 if (unlikely(!shadow_mmio_value)) {
2996 *ret_val = RET_PF_EMULATE;
3004 static bool page_fault_can_be_fast(u32 error_code)
3007 * Do not fix the mmio spte with invalid generation number which
3008 * need to be updated by slow page fault path.
3010 if (unlikely(error_code & PFERR_RSVD_MASK))
3013 /* See if the page fault is due to an NX violation */
3014 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3015 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3019 * #PF can be fast if:
3020 * 1. The shadow page table entry is not present, which could mean that
3021 * the fault is potentially caused by access tracking (if enabled).
3022 * 2. The shadow page table entry is present and the fault
3023 * is caused by write-protect, that means we just need change the W
3024 * bit of the spte which can be done out of mmu-lock.
3026 * However, if access tracking is disabled we know that a non-present
3027 * page must be a genuine page fault where we have to create a new SPTE.
3028 * So, if access tracking is disabled, we return true only for write
3029 * accesses to a present page.
3032 return shadow_acc_track_mask != 0 ||
3033 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3034 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3038 * Returns true if the SPTE was fixed successfully. Otherwise,
3039 * someone else modified the SPTE from its original value.
3042 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3043 u64 *sptep, u64 old_spte, u64 new_spte)
3047 WARN_ON(!sp->role.direct);
3050 * Theoretically we could also set dirty bit (and flush TLB) here in
3051 * order to eliminate unnecessary PML logging. See comments in
3052 * set_spte. But fast_page_fault is very unlikely to happen with PML
3053 * enabled, so we do not do this. This might result in the same GPA
3054 * to be logged in PML buffer again when the write really happens, and
3055 * eventually to be called by mark_page_dirty twice. But it's also no
3056 * harm. This also avoids the TLB flush needed after setting dirty bit
3057 * so non-PML cases won't be impacted.
3059 * Compare with set_spte where instead shadow_dirty_mask is set.
3061 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3064 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3066 * The gfn of direct spte is stable since it is
3067 * calculated by sp->gfn.
3069 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3070 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3076 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3078 if (fault_err_code & PFERR_FETCH_MASK)
3079 return is_executable_pte(spte);
3081 if (fault_err_code & PFERR_WRITE_MASK)
3082 return is_writable_pte(spte);
3084 /* Fault was on Read access */
3085 return spte & PT_PRESENT_MASK;
3089 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3091 static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3094 struct kvm_shadow_walk_iterator iterator;
3095 struct kvm_mmu_page *sp;
3096 int ret = RET_PF_INVALID;
3098 uint retry_count = 0;
3100 if (!page_fault_can_be_fast(error_code))
3103 walk_shadow_page_lockless_begin(vcpu);
3108 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3109 if (!is_shadow_present_pte(spte))
3112 if (!is_shadow_present_pte(spte))
3115 sp = sptep_to_sp(iterator.sptep);
3116 if (!is_last_spte(spte, sp->role.level))
3120 * Check whether the memory access that caused the fault would
3121 * still cause it if it were to be performed right now. If not,
3122 * then this is a spurious fault caused by TLB lazily flushed,
3123 * or some other CPU has already fixed the PTE after the
3124 * current CPU took the fault.
3126 * Need not check the access of upper level table entries since
3127 * they are always ACC_ALL.
3129 if (is_access_allowed(error_code, spte)) {
3130 ret = RET_PF_SPURIOUS;
3136 if (is_access_track_spte(spte))
3137 new_spte = restore_acc_track_spte(new_spte);
3140 * Currently, to simplify the code, write-protection can
3141 * be removed in the fast path only if the SPTE was
3142 * write-protected for dirty-logging or access tracking.
3144 if ((error_code & PFERR_WRITE_MASK) &&
3145 spte_can_locklessly_be_made_writable(spte)) {
3146 new_spte |= PT_WRITABLE_MASK;
3149 * Do not fix write-permission on the large spte. Since
3150 * we only dirty the first page into the dirty-bitmap in
3151 * fast_pf_fix_direct_spte(), other pages are missed
3152 * if its slot has dirty logging enabled.
3154 * Instead, we let the slow page fault path create a
3155 * normal spte to fix the access.
3157 * See the comments in kvm_arch_commit_memory_region().
3159 if (sp->role.level > PG_LEVEL_4K)
3163 /* Verify that the fault can be handled in the fast path */
3164 if (new_spte == spte ||
3165 !is_access_allowed(error_code, new_spte))
3169 * Currently, fast page fault only works for direct mapping
3170 * since the gfn is not stable for indirect shadow page. See
3171 * Documentation/virt/kvm/locking.rst to get more detail.
3173 if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte,
3179 if (++retry_count > 4) {
3180 printk_once(KERN_WARNING
3181 "kvm: Fast #PF retrying more than 4 times.\n");
3187 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3189 walk_shadow_page_lockless_end(vcpu);
3194 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3195 struct list_head *invalid_list)
3197 struct kvm_mmu_page *sp;
3199 if (!VALID_PAGE(*root_hpa))
3202 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3204 if (is_tdp_mmu_page(sp))
3205 kvm_tdp_mmu_put_root(kvm, sp, false);
3206 else if (!--sp->root_count && sp->role.invalid)
3207 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3209 *root_hpa = INVALID_PAGE;
3212 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3213 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3214 ulong roots_to_free)
3216 struct kvm *kvm = vcpu->kvm;
3218 LIST_HEAD(invalid_list);
3219 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3221 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3223 /* Before acquiring the MMU lock, see if we need to do any real work. */
3224 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3225 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3226 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3227 VALID_PAGE(mmu->prev_roots[i].hpa))
3230 if (i == KVM_MMU_NUM_PREV_ROOTS)
3234 write_lock(&kvm->mmu_lock);
3236 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3237 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3238 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3241 if (free_active_root) {
3242 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3243 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3244 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3245 } else if (mmu->pae_root) {
3246 for (i = 0; i < 4; ++i) {
3247 if (!IS_VALID_PAE_ROOT(mmu->pae_root[i]))
3250 mmu_free_root_page(kvm, &mmu->pae_root[i],
3252 mmu->pae_root[i] = INVALID_PAE_ROOT;
3255 mmu->root_hpa = INVALID_PAGE;
3259 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3260 write_unlock(&kvm->mmu_lock);
3262 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3264 void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3266 unsigned long roots_to_free = 0;
3271 * This should not be called while L2 is active, L2 can't invalidate
3272 * _only_ its own roots, e.g. INVVPID unconditionally exits.
3274 WARN_ON_ONCE(mmu->mmu_role.base.guest_mode);
3276 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3277 root_hpa = mmu->prev_roots[i].hpa;
3278 if (!VALID_PAGE(root_hpa))
3281 if (!to_shadow_page(root_hpa) ||
3282 to_shadow_page(root_hpa)->role.guest_mode)
3283 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
3286 kvm_mmu_free_roots(vcpu, mmu, roots_to_free);
3288 EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots);
3291 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3295 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3296 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3303 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3304 u8 level, bool direct)
3306 struct kvm_mmu_page *sp;
3308 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3311 return __pa(sp->spt);
3314 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3316 struct kvm_mmu *mmu = vcpu->arch.mmu;
3317 u8 shadow_root_level = mmu->shadow_root_level;
3322 write_lock(&vcpu->kvm->mmu_lock);
3323 r = make_mmu_pages_available(vcpu);
3327 if (is_tdp_mmu_enabled(vcpu->kvm)) {
3328 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3329 mmu->root_hpa = root;
3330 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3331 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true);
3332 mmu->root_hpa = root;
3333 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3334 if (WARN_ON_ONCE(!mmu->pae_root)) {
3339 for (i = 0; i < 4; ++i) {
3340 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3342 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3343 i << 30, PT32_ROOT_LEVEL, true);
3344 mmu->pae_root[i] = root | PT_PRESENT_MASK |
3347 mmu->root_hpa = __pa(mmu->pae_root);
3349 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level);
3354 /* root_pgd is ignored for direct MMUs. */
3357 write_unlock(&vcpu->kvm->mmu_lock);
3361 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3363 struct kvm_mmu *mmu = vcpu->arch.mmu;
3364 u64 pdptrs[4], pm_mask;
3365 gfn_t root_gfn, root_pgd;
3370 root_pgd = mmu->get_guest_pgd(vcpu);
3371 root_gfn = root_pgd >> PAGE_SHIFT;
3373 if (mmu_check_root(vcpu, root_gfn))
3377 * On SVM, reading PDPTRs might access guest memory, which might fault
3378 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3380 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3381 for (i = 0; i < 4; ++i) {
3382 pdptrs[i] = mmu->get_pdptr(vcpu, i);
3383 if (!(pdptrs[i] & PT_PRESENT_MASK))
3386 if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT))
3391 r = alloc_all_memslots_rmaps(vcpu->kvm);
3395 write_lock(&vcpu->kvm->mmu_lock);
3396 r = make_mmu_pages_available(vcpu);
3401 * Do we shadow a long mode page table? If so we need to
3402 * write-protect the guests page table root.
3404 if (mmu->root_level >= PT64_ROOT_4LEVEL) {
3405 root = mmu_alloc_root(vcpu, root_gfn, 0,
3406 mmu->shadow_root_level, false);
3407 mmu->root_hpa = root;
3411 if (WARN_ON_ONCE(!mmu->pae_root)) {
3417 * We shadow a 32 bit page table. This may be a legacy 2-level
3418 * or a PAE 3-level page table. In either case we need to be aware that
3419 * the shadow page table may be a PAE or a long mode page table.
3421 pm_mask = PT_PRESENT_MASK | shadow_me_mask;
3422 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3423 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3425 if (WARN_ON_ONCE(!mmu->pml4_root)) {
3430 mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask;
3433 for (i = 0; i < 4; ++i) {
3434 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3436 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3437 if (!(pdptrs[i] & PT_PRESENT_MASK)) {
3438 mmu->pae_root[i] = INVALID_PAE_ROOT;
3441 root_gfn = pdptrs[i] >> PAGE_SHIFT;
3444 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3445 PT32_ROOT_LEVEL, false);
3446 mmu->pae_root[i] = root | pm_mask;
3449 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3450 mmu->root_hpa = __pa(mmu->pml4_root);
3452 mmu->root_hpa = __pa(mmu->pae_root);
3455 mmu->root_pgd = root_pgd;
3457 write_unlock(&vcpu->kvm->mmu_lock);
3462 static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu)
3464 struct kvm_mmu *mmu = vcpu->arch.mmu;
3465 u64 *pml4_root, *pae_root;
3468 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3469 * tables are allocated and initialized at root creation as there is no
3470 * equivalent level in the guest's NPT to shadow. Allocate the tables
3471 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
3473 if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL ||
3474 mmu->shadow_root_level < PT64_ROOT_4LEVEL)
3478 * This mess only works with 4-level paging and needs to be updated to
3479 * work with 5-level paging.
3481 if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL))
3484 if (mmu->pae_root && mmu->pml4_root)
3488 * The special roots should always be allocated in concert. Yell and
3489 * bail if KVM ends up in a state where only one of the roots is valid.
3491 if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root))
3495 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3496 * doesn't need to be decrypted.
3498 pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3502 pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3504 free_page((unsigned long)pae_root);
3508 mmu->pae_root = pae_root;
3509 mmu->pml4_root = pml4_root;
3514 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3517 struct kvm_mmu_page *sp;
3519 if (vcpu->arch.mmu->direct_map)
3522 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3525 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3527 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3528 hpa_t root = vcpu->arch.mmu->root_hpa;
3529 sp = to_shadow_page(root);
3532 * Even if another CPU was marking the SP as unsync-ed
3533 * simultaneously, any guest page table changes are not
3534 * guaranteed to be visible anyway until this VCPU issues a TLB
3535 * flush strictly after those changes are made. We only need to
3536 * ensure that the other CPU sets these flags before any actual
3537 * changes to the page tables are made. The comments in
3538 * mmu_try_to_unsync_pages() describe what could go wrong if
3539 * this requirement isn't satisfied.
3541 if (!smp_load_acquire(&sp->unsync) &&
3542 !smp_load_acquire(&sp->unsync_children))
3545 write_lock(&vcpu->kvm->mmu_lock);
3546 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3548 mmu_sync_children(vcpu, sp);
3550 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3551 write_unlock(&vcpu->kvm->mmu_lock);
3555 write_lock(&vcpu->kvm->mmu_lock);
3556 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3558 for (i = 0; i < 4; ++i) {
3559 hpa_t root = vcpu->arch.mmu->pae_root[i];
3561 if (IS_VALID_PAE_ROOT(root)) {
3562 root &= PT64_BASE_ADDR_MASK;
3563 sp = to_shadow_page(root);
3564 mmu_sync_children(vcpu, sp);
3568 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3569 write_unlock(&vcpu->kvm->mmu_lock);
3572 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3573 u32 access, struct x86_exception *exception)
3576 exception->error_code = 0;
3580 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3582 struct x86_exception *exception)
3585 exception->error_code = 0;
3586 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3590 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3592 int bit7 = (pte >> 7) & 1;
3594 return pte & rsvd_check->rsvd_bits_mask[bit7][level-1];
3597 static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte)
3599 return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
3602 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3605 * A nested guest cannot use the MMIO cache if it is using nested
3606 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3608 if (mmu_is_nested(vcpu))
3612 return vcpu_match_mmio_gpa(vcpu, addr);
3614 return vcpu_match_mmio_gva(vcpu, addr);
3618 * Return the level of the lowest level SPTE added to sptes.
3619 * That SPTE may be non-present.
3621 static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
3623 struct kvm_shadow_walk_iterator iterator;
3627 walk_shadow_page_lockless_begin(vcpu);
3629 for (shadow_walk_init(&iterator, vcpu, addr),
3630 *root_level = iterator.level;
3631 shadow_walk_okay(&iterator);
3632 __shadow_walk_next(&iterator, spte)) {
3633 leaf = iterator.level;
3634 spte = mmu_spte_get_lockless(iterator.sptep);
3638 if (!is_shadow_present_pte(spte))
3642 walk_shadow_page_lockless_end(vcpu);
3647 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3648 static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3650 u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
3651 struct rsvd_bits_validate *rsvd_check;
3652 int root, leaf, level;
3653 bool reserved = false;
3655 if (is_tdp_mmu(vcpu->arch.mmu))
3656 leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
3658 leaf = get_walk(vcpu, addr, sptes, &root);
3660 if (unlikely(leaf < 0)) {
3665 *sptep = sptes[leaf];
3668 * Skip reserved bits checks on the terminal leaf if it's not a valid
3669 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3670 * design, always have reserved bits set. The purpose of the checks is
3671 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3673 if (!is_shadow_present_pte(sptes[leaf]))
3676 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3678 for (level = root; level >= leaf; level--)
3680 * Use a bitwise-OR instead of a logical-OR to aggregate the
3681 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3682 * adding a Jcc in the loop.
3684 reserved |= __is_bad_mt_xwr(rsvd_check, sptes[level]) |
3685 __is_rsvd_bits_set(rsvd_check, sptes[level], level);
3688 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
3690 for (level = root; level >= leaf; level--)
3691 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3692 sptes[level], level,
3693 rsvd_check->rsvd_bits_mask[(sptes[level] >> 7) & 1][level-1]);
3699 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3704 if (mmio_info_in_cache(vcpu, addr, direct))
3705 return RET_PF_EMULATE;
3707 reserved = get_mmio_spte(vcpu, addr, &spte);
3708 if (WARN_ON(reserved))
3711 if (is_mmio_spte(spte)) {
3712 gfn_t gfn = get_mmio_spte_gfn(spte);
3713 unsigned int access = get_mmio_spte_access(spte);
3715 if (!check_mmio_spte(vcpu, spte))
3716 return RET_PF_INVALID;
3721 trace_handle_mmio_page_fault(addr, gfn, access);
3722 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3723 return RET_PF_EMULATE;
3727 * If the page table is zapped by other cpus, let CPU fault again on
3730 return RET_PF_RETRY;
3733 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3734 u32 error_code, gfn_t gfn)
3736 if (unlikely(error_code & PFERR_RSVD_MASK))
3739 if (!(error_code & PFERR_PRESENT_MASK) ||
3740 !(error_code & PFERR_WRITE_MASK))
3744 * guest is writing the page which is write tracked which can
3745 * not be fixed by page fault handler.
3747 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3753 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3755 struct kvm_shadow_walk_iterator iterator;
3758 walk_shadow_page_lockless_begin(vcpu);
3759 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3760 clear_sp_write_flooding_count(iterator.sptep);
3761 if (!is_shadow_present_pte(spte))
3764 walk_shadow_page_lockless_end(vcpu);
3767 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3770 struct kvm_arch_async_pf arch;
3772 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3774 arch.direct_map = vcpu->arch.mmu->direct_map;
3775 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3777 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3778 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3781 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3782 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva,
3783 bool write, bool *writable)
3785 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3789 * Retry the page fault if the gfn hit a memslot that is being deleted
3790 * or moved. This ensures any existing SPTEs for the old memslot will
3791 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3793 if (slot && (slot->flags & KVM_MEMSLOT_INVALID))
3796 /* Don't expose private memslots to L2. */
3797 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3798 *pfn = KVM_PFN_NOSLOT;
3804 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async,
3805 write, writable, hva);
3807 return false; /* *pfn has correct page already */
3809 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3810 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
3811 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3812 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
3813 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3815 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
3819 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL,
3820 write, writable, hva);
3824 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3825 bool prefault, int max_level, bool is_tdp)
3827 bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu);
3828 bool write = error_code & PFERR_WRITE_MASK;
3831 gfn_t gfn = gpa >> PAGE_SHIFT;
3832 unsigned long mmu_seq;
3837 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3838 return RET_PF_EMULATE;
3840 if (!is_tdp_mmu_fault) {
3841 r = fast_page_fault(vcpu, gpa, error_code);
3842 if (r != RET_PF_INVALID)
3846 r = mmu_topup_memory_caches(vcpu, false);
3850 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3853 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, &hva,
3854 write, &map_writable))
3855 return RET_PF_RETRY;
3857 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
3862 if (is_tdp_mmu_fault)
3863 read_lock(&vcpu->kvm->mmu_lock);
3865 write_lock(&vcpu->kvm->mmu_lock);
3867 if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva))
3869 r = make_mmu_pages_available(vcpu);
3873 if (is_tdp_mmu_fault)
3874 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
3877 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
3881 if (is_tdp_mmu_fault)
3882 read_unlock(&vcpu->kvm->mmu_lock);
3884 write_unlock(&vcpu->kvm->mmu_lock);
3885 kvm_release_pfn_clean(pfn);
3889 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
3890 u32 error_code, bool prefault)
3892 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
3894 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3895 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3896 PG_LEVEL_2M, false);
3899 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3900 u64 fault_address, char *insn, int insn_len)
3903 u32 flags = vcpu->arch.apf.host_apf_flags;
3905 #ifndef CONFIG_X86_64
3906 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3907 if (WARN_ON_ONCE(fault_address >> 32))
3911 vcpu->arch.l1tf_flush_l1d = true;
3913 trace_kvm_page_fault(fault_address, error_code);
3915 if (kvm_event_needs_reinjection(vcpu))
3916 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3917 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3919 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
3920 vcpu->arch.apf.host_apf_flags = 0;
3921 local_irq_disable();
3922 kvm_async_pf_task_wait_schedule(fault_address);
3925 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
3930 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3932 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3937 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3938 max_level > PG_LEVEL_4K;
3940 int page_num = KVM_PAGES_PER_HPAGE(max_level);
3941 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
3943 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
3947 return direct_page_fault(vcpu, gpa, error_code, prefault,
3951 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3952 struct kvm_mmu *context)
3954 context->page_fault = nonpaging_page_fault;
3955 context->gva_to_gpa = nonpaging_gva_to_gpa;
3956 context->sync_page = nonpaging_sync_page;
3957 context->invlpg = NULL;
3958 context->root_level = 0;
3959 context->direct_map = true;
3960 context->nx = false;
3963 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
3964 union kvm_mmu_page_role role)
3966 return (role.direct || pgd == root->pgd) &&
3967 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
3968 role.word == to_shadow_page(root->hpa)->role.word;
3972 * Find out if a previously cached root matching the new pgd/role is available.
3973 * The current root is also inserted into the cache.
3974 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3976 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3977 * false is returned. This root should now be freed by the caller.
3979 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3980 union kvm_mmu_page_role new_role)
3983 struct kvm_mmu_root_info root;
3984 struct kvm_mmu *mmu = vcpu->arch.mmu;
3986 root.pgd = mmu->root_pgd;
3987 root.hpa = mmu->root_hpa;
3989 if (is_root_usable(&root, new_pgd, new_role))
3992 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3993 swap(root, mmu->prev_roots[i]);
3995 if (is_root_usable(&root, new_pgd, new_role))
3999 mmu->root_hpa = root.hpa;
4000 mmu->root_pgd = root.pgd;
4002 return i < KVM_MMU_NUM_PREV_ROOTS;
4005 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4006 union kvm_mmu_page_role new_role)
4008 struct kvm_mmu *mmu = vcpu->arch.mmu;
4011 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4012 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4013 * later if necessary.
4015 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4016 mmu->root_level >= PT64_ROOT_4LEVEL)
4017 return cached_root_available(vcpu, new_pgd, new_role);
4022 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4023 union kvm_mmu_page_role new_role)
4025 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
4026 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
4031 * It's possible that the cached previous root page is obsolete because
4032 * of a change in the MMU generation number. However, changing the
4033 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
4034 * free the root set here and allocate a new one.
4036 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
4038 if (force_flush_and_sync_on_reuse) {
4039 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4040 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
4044 * The last MMIO access's GVA and GPA are cached in the VCPU. When
4045 * switching to a new CR3, that GVA->GPA mapping may no longer be
4046 * valid. So clear any cached MMIO info even when we don't need to sync
4047 * the shadow page tables.
4049 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4052 * If this is a direct root page, it doesn't have a write flooding
4053 * count. Otherwise, clear the write flooding count.
4055 if (!new_role.direct)
4056 __clear_sp_write_flooding_count(
4057 to_shadow_page(vcpu->arch.mmu->root_hpa));
4060 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd)
4062 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu));
4064 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
4066 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4068 return kvm_read_cr3(vcpu);
4071 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4072 unsigned int access, int *nr_present)
4074 if (unlikely(is_mmio_spte(*sptep))) {
4075 if (gfn != get_mmio_spte_gfn(*sptep)) {
4076 mmu_spte_clear_no_track(sptep);
4081 mark_mmio_spte(vcpu, sptep, gfn, access);
4088 static inline bool is_last_gpte(struct kvm_mmu *mmu,
4089 unsigned level, unsigned gpte)
4092 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4093 * If it is clear, there are no large pages at this level, so clear
4094 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4096 gpte &= level - mmu->last_nonleaf_level;
4099 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
4100 * iff level <= PG_LEVEL_4K, which for our purpose means
4101 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
4103 gpte |= level - PG_LEVEL_4K - 1;
4105 return gpte & PT_PAGE_SIZE_MASK;
4108 #define PTTYPE_EPT 18 /* arbitrary */
4109 #define PTTYPE PTTYPE_EPT
4110 #include "paging_tmpl.h"
4114 #include "paging_tmpl.h"
4118 #include "paging_tmpl.h"
4122 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4123 struct rsvd_bits_validate *rsvd_check,
4124 u64 pa_bits_rsvd, int level, bool nx, bool gbpages,
4127 u64 gbpages_bit_rsvd = 0;
4128 u64 nonleaf_bit8_rsvd = 0;
4131 rsvd_check->bad_mt_xwr = 0;
4134 gbpages_bit_rsvd = rsvd_bits(7, 7);
4136 if (level == PT32E_ROOT_LEVEL)
4137 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62);
4139 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4141 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4143 high_bits_rsvd |= rsvd_bits(63, 63);
4146 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4147 * leaf entries) on AMD CPUs only.
4150 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4153 case PT32_ROOT_LEVEL:
4154 /* no rsvd bits for 2 level 4K page table entries */
4155 rsvd_check->rsvd_bits_mask[0][1] = 0;
4156 rsvd_check->rsvd_bits_mask[0][0] = 0;
4157 rsvd_check->rsvd_bits_mask[1][0] =
4158 rsvd_check->rsvd_bits_mask[0][0];
4161 rsvd_check->rsvd_bits_mask[1][1] = 0;
4165 if (is_cpuid_PSE36())
4166 /* 36bits PSE 4MB page */
4167 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4169 /* 32 bits PSE 4MB page */
4170 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4172 case PT32E_ROOT_LEVEL:
4173 rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
4176 rsvd_bits(1, 2); /* PDPTE */
4177 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
4178 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
4179 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4180 rsvd_bits(13, 20); /* large page */
4181 rsvd_check->rsvd_bits_mask[1][0] =
4182 rsvd_check->rsvd_bits_mask[0][0];
4184 case PT64_ROOT_5LEVEL:
4185 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd |
4188 rsvd_check->rsvd_bits_mask[1][4] =
4189 rsvd_check->rsvd_bits_mask[0][4];
4191 case PT64_ROOT_4LEVEL:
4192 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd |
4195 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd |
4197 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd;
4198 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4199 rsvd_check->rsvd_bits_mask[1][3] =
4200 rsvd_check->rsvd_bits_mask[0][3];
4201 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd |
4204 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4205 rsvd_bits(13, 20); /* large page */
4206 rsvd_check->rsvd_bits_mask[1][0] =
4207 rsvd_check->rsvd_bits_mask[0][0];
4212 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4213 struct kvm_mmu *context)
4215 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4216 vcpu->arch.reserved_gpa_bits,
4217 context->root_level, context->nx,
4218 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4220 guest_cpuid_is_amd_or_hygon(vcpu));
4224 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4225 u64 pa_bits_rsvd, bool execonly)
4227 u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4230 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
4231 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
4232 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6);
4233 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6);
4234 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4237 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4238 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4239 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29);
4240 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20);
4241 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4243 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4244 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4245 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4246 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4247 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4249 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4250 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4252 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4255 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4256 struct kvm_mmu *context, bool execonly)
4258 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4259 vcpu->arch.reserved_gpa_bits, execonly);
4262 static inline u64 reserved_hpa_bits(void)
4264 return rsvd_bits(shadow_phys_bits, 63);
4268 * the page table on host is the shadow page table for the page
4269 * table in guest or amd nested guest, its mmu features completely
4270 * follow the features in guest.
4272 static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4273 struct kvm_mmu *context)
4276 * KVM uses NX when TDP is disabled to handle a variety of scenarios,
4277 * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
4278 * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
4279 * The iTLB multi-hit workaround can be toggled at any time, so assume
4280 * NX can be used by any non-nested shadow MMU to avoid having to reset
4281 * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
4283 bool uses_nx = context->nx || !tdp_enabled;
4284 struct rsvd_bits_validate *shadow_zero_check;
4288 * Passing "true" to the last argument is okay; it adds a check
4289 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4291 shadow_zero_check = &context->shadow_zero_check;
4292 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4293 reserved_hpa_bits(),
4294 context->shadow_root_level, uses_nx,
4295 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4296 is_pse(vcpu), true);
4298 if (!shadow_me_mask)
4301 for (i = context->shadow_root_level; --i >= 0;) {
4302 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4303 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4308 static inline bool boot_cpu_is_amd(void)
4310 WARN_ON_ONCE(!tdp_enabled);
4311 return shadow_x_mask == 0;
4315 * the direct page table on host, use as much mmu features as
4316 * possible, however, kvm currently does not do execution-protection.
4319 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4320 struct kvm_mmu *context)
4322 struct rsvd_bits_validate *shadow_zero_check;
4325 shadow_zero_check = &context->shadow_zero_check;
4327 if (boot_cpu_is_amd())
4328 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4329 reserved_hpa_bits(),
4330 context->shadow_root_level, false,
4331 boot_cpu_has(X86_FEATURE_GBPAGES),
4334 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4335 reserved_hpa_bits(), false);
4337 if (!shadow_me_mask)
4340 for (i = context->shadow_root_level; --i >= 0;) {
4341 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4342 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4347 * as the comments in reset_shadow_zero_bits_mask() except it
4348 * is the shadow page table for intel nested guest.
4351 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4352 struct kvm_mmu *context, bool execonly)
4354 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4355 reserved_hpa_bits(), execonly);
4358 #define BYTE_MASK(access) \
4359 ((1 & (access) ? 2 : 0) | \
4360 (2 & (access) ? 4 : 0) | \
4361 (3 & (access) ? 8 : 0) | \
4362 (4 & (access) ? 16 : 0) | \
4363 (5 & (access) ? 32 : 0) | \
4364 (6 & (access) ? 64 : 0) | \
4365 (7 & (access) ? 128 : 0))
4368 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4369 struct kvm_mmu *mmu, bool ept)
4373 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4374 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4375 const u8 u = BYTE_MASK(ACC_USER_MASK);
4377 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4378 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4379 bool cr0_wp = is_write_protection(vcpu);
4381 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4382 unsigned pfec = byte << 1;
4385 * Each "*f" variable has a 1 bit for each UWX value
4386 * that causes a fault with the given PFEC.
4389 /* Faults from writes to non-writable pages */
4390 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4391 /* Faults from user mode accesses to supervisor pages */
4392 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4393 /* Faults from fetches of non-executable pages*/
4394 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4395 /* Faults from kernel mode fetches of user pages */
4397 /* Faults from kernel mode accesses of user pages */
4401 /* Faults from kernel mode accesses to user pages */
4402 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4404 /* Not really needed: !nx will cause pte.nx to fault */
4408 /* Allow supervisor writes if !cr0.wp */
4410 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4412 /* Disallow supervisor fetches of user code if cr4.smep */
4414 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4417 * SMAP:kernel-mode data accesses from user-mode
4418 * mappings should fault. A fault is considered
4419 * as a SMAP violation if all of the following
4420 * conditions are true:
4421 * - X86_CR4_SMAP is set in CR4
4422 * - A user page is accessed
4423 * - The access is not a fetch
4424 * - Page fault in kernel mode
4425 * - if CPL = 3 or X86_EFLAGS_AC is clear
4427 * Here, we cover the first three conditions.
4428 * The fourth is computed dynamically in permission_fault();
4429 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4430 * *not* subject to SMAP restrictions.
4433 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4436 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4441 * PKU is an additional mechanism by which the paging controls access to
4442 * user-mode addresses based on the value in the PKRU register. Protection
4443 * key violations are reported through a bit in the page fault error code.
4444 * Unlike other bits of the error code, the PK bit is not known at the
4445 * call site of e.g. gva_to_gpa; it must be computed directly in
4446 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4447 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4449 * In particular the following conditions come from the error code, the
4450 * page tables and the machine state:
4451 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4452 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4453 * - PK is always zero if U=0 in the page tables
4454 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4456 * The PKRU bitmask caches the result of these four conditions. The error
4457 * code (minus the P bit) and the page table's U bit form an index into the
4458 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4459 * with the two bits of the PKRU register corresponding to the protection key.
4460 * For the first three conditions above the bits will be 00, thus masking
4461 * away both AD and WD. For all reads or if the last condition holds, WD
4462 * only will be masked away.
4464 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4475 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4476 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4481 wp = is_write_protection(vcpu);
4483 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4484 unsigned pfec, pkey_bits;
4485 bool check_pkey, check_write, ff, uf, wf, pte_user;
4488 ff = pfec & PFERR_FETCH_MASK;
4489 uf = pfec & PFERR_USER_MASK;
4490 wf = pfec & PFERR_WRITE_MASK;
4492 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4493 pte_user = pfec & PFERR_RSVD_MASK;
4496 * Only need to check the access which is not an
4497 * instruction fetch and is to a user page.
4499 check_pkey = (!ff && pte_user);
4501 * write access is controlled by PKRU if it is a
4502 * user access or CR0.WP = 1.
4504 check_write = check_pkey && wf && (uf || wp);
4506 /* PKRU.AD stops both read and write access. */
4507 pkey_bits = !!check_pkey;
4508 /* PKRU.WD stops write access. */
4509 pkey_bits |= (!!check_write) << 1;
4511 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4515 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4517 unsigned root_level = mmu->root_level;
4519 mmu->last_nonleaf_level = root_level;
4520 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4521 mmu->last_nonleaf_level++;
4524 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4525 struct kvm_mmu *context,
4528 context->nx = is_nx(vcpu);
4529 context->root_level = root_level;
4531 MMU_WARN_ON(!is_pae(vcpu));
4532 context->page_fault = paging64_page_fault;
4533 context->gva_to_gpa = paging64_gva_to_gpa;
4534 context->sync_page = paging64_sync_page;
4535 context->invlpg = paging64_invlpg;
4536 context->direct_map = false;
4539 static void paging64_init_context(struct kvm_vcpu *vcpu,
4540 struct kvm_mmu *context)
4542 int root_level = is_la57_mode(vcpu) ?
4543 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4545 paging64_init_context_common(vcpu, context, root_level);
4548 static void paging32_init_context(struct kvm_vcpu *vcpu,
4549 struct kvm_mmu *context)
4551 context->nx = false;
4552 context->root_level = PT32_ROOT_LEVEL;
4553 context->page_fault = paging32_page_fault;
4554 context->gva_to_gpa = paging32_gva_to_gpa;
4555 context->sync_page = paging32_sync_page;
4556 context->invlpg = paging32_invlpg;
4557 context->direct_map = false;
4560 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4561 struct kvm_mmu *context)
4563 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4566 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu,
4567 struct kvm_mmu_role_regs *regs)
4569 union kvm_mmu_extended_role ext = {0};
4571 ext.cr0_pg = ____is_cr0_pg(regs);
4572 ext.cr4_pae = ____is_cr4_pae(regs);
4573 ext.cr4_smep = ____is_cr4_smep(regs);
4574 ext.cr4_smap = ____is_cr4_smap(regs);
4575 ext.cr4_pse = ____is_cr4_pse(regs);
4576 ext.cr4_pke = ____is_cr4_pke(regs);
4577 ext.cr4_la57 = ____is_cr4_la57(regs);
4584 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4585 struct kvm_mmu_role_regs *regs,
4588 union kvm_mmu_role role = {0};
4590 role.base.access = ACC_ALL;
4591 role.base.efer_nx = ____is_efer_nx(regs);
4592 role.base.cr0_wp = ____is_cr0_wp(regs);
4593 role.base.smm = is_smm(vcpu);
4594 role.base.guest_mode = is_guest_mode(vcpu);
4599 role.ext = kvm_calc_mmu_role_ext(vcpu, regs);
4604 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4606 /* Use 5-level TDP if and only if it's useful/necessary. */
4607 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4610 return max_tdp_level;
4613 static union kvm_mmu_role
4614 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu,
4615 struct kvm_mmu_role_regs *regs, bool base_only)
4617 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
4619 role.base.ad_disabled = (shadow_accessed_mask == 0);
4620 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4621 role.base.direct = true;
4622 role.base.gpte_is_8_bytes = true;
4627 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4629 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4630 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4631 union kvm_mmu_role new_role =
4632 kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, false);
4634 if (new_role.as_u64 == context->mmu_role.as_u64)
4637 context->mmu_role.as_u64 = new_role.as_u64;
4638 context->page_fault = kvm_tdp_page_fault;
4639 context->sync_page = nonpaging_sync_page;
4640 context->invlpg = NULL;
4641 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4642 context->direct_map = true;
4643 context->get_guest_pgd = get_cr3;
4644 context->get_pdptr = kvm_pdptr_read;
4645 context->inject_page_fault = kvm_inject_page_fault;
4647 if (!is_paging(vcpu)) {
4648 context->nx = false;
4649 context->gva_to_gpa = nonpaging_gva_to_gpa;
4650 context->root_level = 0;
4651 } else if (is_long_mode(vcpu)) {
4652 context->nx = is_nx(vcpu);
4653 context->root_level = is_la57_mode(vcpu) ?
4654 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4655 reset_rsvds_bits_mask(vcpu, context);
4656 context->gva_to_gpa = paging64_gva_to_gpa;
4657 } else if (is_pae(vcpu)) {
4658 context->nx = is_nx(vcpu);
4659 context->root_level = PT32E_ROOT_LEVEL;
4660 reset_rsvds_bits_mask(vcpu, context);
4661 context->gva_to_gpa = paging64_gva_to_gpa;
4663 context->nx = false;
4664 context->root_level = PT32_ROOT_LEVEL;
4665 reset_rsvds_bits_mask(vcpu, context);
4666 context->gva_to_gpa = paging32_gva_to_gpa;
4669 update_permission_bitmask(vcpu, context, false);
4670 update_pkru_bitmask(vcpu, context, false);
4671 update_last_nonleaf_level(vcpu, context);
4672 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4675 static union kvm_mmu_role
4676 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu,
4677 struct kvm_mmu_role_regs *regs, bool base_only)
4679 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
4681 role.base.smep_andnot_wp = role.ext.cr4_smep && !____is_cr0_wp(regs);
4682 role.base.smap_andnot_wp = role.ext.cr4_smap && !____is_cr0_wp(regs);
4683 role.base.gpte_is_8_bytes = ____is_cr4_pae(regs);
4688 static union kvm_mmu_role
4689 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu,
4690 struct kvm_mmu_role_regs *regs, bool base_only)
4692 union kvm_mmu_role role =
4693 kvm_calc_shadow_root_page_role_common(vcpu, regs, base_only);
4695 role.base.direct = !____is_cr0_pg(regs);
4697 if (!____is_efer_lma(regs))
4698 role.base.level = PT32E_ROOT_LEVEL;
4699 else if (____is_cr4_la57(regs))
4700 role.base.level = PT64_ROOT_5LEVEL;
4702 role.base.level = PT64_ROOT_4LEVEL;
4707 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4708 struct kvm_mmu_role_regs *regs,
4709 union kvm_mmu_role new_role)
4711 if (!____is_cr0_pg(regs))
4712 nonpaging_init_context(vcpu, context);
4713 else if (____is_efer_lma(regs))
4714 paging64_init_context(vcpu, context);
4715 else if (____is_cr4_pae(regs))
4716 paging32E_init_context(vcpu, context);
4718 paging32_init_context(vcpu, context);
4720 if (____is_cr0_pg(regs)) {
4721 reset_rsvds_bits_mask(vcpu, context);
4722 update_permission_bitmask(vcpu, context, false);
4723 update_pkru_bitmask(vcpu, context, false);
4724 update_last_nonleaf_level(vcpu, context);
4726 context->shadow_root_level = new_role.base.level;
4728 context->mmu_role.as_u64 = new_role.as_u64;
4729 reset_shadow_zero_bits_mask(vcpu, context);
4732 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu,
4733 struct kvm_mmu_role_regs *regs)
4735 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4736 union kvm_mmu_role new_role =
4737 kvm_calc_shadow_mmu_root_page_role(vcpu, regs, false);
4739 if (new_role.as_u64 != context->mmu_role.as_u64)
4740 shadow_mmu_init_context(vcpu, context, regs, new_role);
4743 static union kvm_mmu_role
4744 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu,
4745 struct kvm_mmu_role_regs *regs)
4747 union kvm_mmu_role role =
4748 kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
4750 role.base.direct = false;
4751 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4756 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
4757 unsigned long cr4, u64 efer, gpa_t nested_cr3)
4759 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4760 struct kvm_mmu_role_regs regs = {
4765 union kvm_mmu_role new_role;
4767 new_role = kvm_calc_shadow_npt_root_page_role(vcpu, ®s);
4769 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base);
4771 if (new_role.as_u64 != context->mmu_role.as_u64)
4772 shadow_mmu_init_context(vcpu, context, ®s, new_role);
4775 * Redo the shadow bits, the reset done by shadow_mmu_init_context()
4776 * (above) may use the wrong shadow_root_level.
4778 reset_shadow_zero_bits_mask(vcpu, context);
4780 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4782 static union kvm_mmu_role
4783 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4784 bool execonly, u8 level)
4786 union kvm_mmu_role role = {0};
4788 /* SMM flag is inherited from root_mmu */
4789 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4791 role.base.level = level;
4792 role.base.gpte_is_8_bytes = true;
4793 role.base.direct = false;
4794 role.base.ad_disabled = !accessed_dirty;
4795 role.base.guest_mode = true;
4796 role.base.access = ACC_ALL;
4798 /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */
4800 role.ext.execonly = execonly;
4806 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4807 bool accessed_dirty, gpa_t new_eptp)
4809 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4810 u8 level = vmx_eptp_page_walk_level(new_eptp);
4811 union kvm_mmu_role new_role =
4812 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4815 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base);
4817 if (new_role.as_u64 == context->mmu_role.as_u64)
4820 context->shadow_root_level = level;
4823 context->ept_ad = accessed_dirty;
4824 context->page_fault = ept_page_fault;
4825 context->gva_to_gpa = ept_gva_to_gpa;
4826 context->sync_page = ept_sync_page;
4827 context->invlpg = ept_invlpg;
4828 context->root_level = level;
4829 context->direct_map = false;
4830 context->mmu_role.as_u64 = new_role.as_u64;
4832 update_permission_bitmask(vcpu, context, true);
4833 update_pkru_bitmask(vcpu, context, true);
4834 update_last_nonleaf_level(vcpu, context);
4835 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4836 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4838 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4840 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4842 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4843 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4845 kvm_init_shadow_mmu(vcpu, ®s);
4847 context->get_guest_pgd = get_cr3;
4848 context->get_pdptr = kvm_pdptr_read;
4849 context->inject_page_fault = kvm_inject_page_fault;
4852 static union kvm_mmu_role
4853 kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu, struct kvm_mmu_role_regs *regs)
4855 union kvm_mmu_role role;
4857 role = kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
4860 * Nested MMUs are used only for walking L2's gva->gpa, they never have
4861 * shadow pages of their own and so "direct" has no meaning. Set it
4862 * to "true" to try to detect bogus usage of the nested MMU.
4864 role.base.direct = true;
4866 if (!____is_cr0_pg(regs))
4867 role.base.level = 0;
4868 else if (____is_efer_lma(regs))
4869 role.base.level = ____is_cr4_la57(regs) ? PT64_ROOT_5LEVEL :
4871 else if (____is_cr4_pae(regs))
4872 role.base.level = PT32E_ROOT_LEVEL;
4874 role.base.level = PT32_ROOT_LEVEL;
4879 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4881 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4882 union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu, ®s);
4883 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4885 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4888 g_context->mmu_role.as_u64 = new_role.as_u64;
4889 g_context->get_guest_pgd = get_cr3;
4890 g_context->get_pdptr = kvm_pdptr_read;
4891 g_context->inject_page_fault = kvm_inject_page_fault;
4894 * L2 page tables are never shadowed, so there is no need to sync
4897 g_context->invlpg = NULL;
4900 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4901 * L1's nested page tables (e.g. EPT12). The nested translation
4902 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4903 * L2's page tables as the first level of translation and L1's
4904 * nested page tables as the second level of translation. Basically
4905 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4907 if (!is_paging(vcpu)) {
4908 g_context->nx = false;
4909 g_context->root_level = 0;
4910 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4911 } else if (is_long_mode(vcpu)) {
4912 g_context->nx = is_nx(vcpu);
4913 g_context->root_level = is_la57_mode(vcpu) ?
4914 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4915 reset_rsvds_bits_mask(vcpu, g_context);
4916 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4917 } else if (is_pae(vcpu)) {
4918 g_context->nx = is_nx(vcpu);
4919 g_context->root_level = PT32E_ROOT_LEVEL;
4920 reset_rsvds_bits_mask(vcpu, g_context);
4921 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4923 g_context->nx = false;
4924 g_context->root_level = PT32_ROOT_LEVEL;
4925 reset_rsvds_bits_mask(vcpu, g_context);
4926 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4929 update_permission_bitmask(vcpu, g_context, false);
4930 update_pkru_bitmask(vcpu, g_context, false);
4931 update_last_nonleaf_level(vcpu, g_context);
4934 void kvm_init_mmu(struct kvm_vcpu *vcpu)
4936 if (mmu_is_nested(vcpu))
4937 init_kvm_nested_mmu(vcpu);
4938 else if (tdp_enabled)
4939 init_kvm_tdp_mmu(vcpu);
4941 init_kvm_softmmu(vcpu);
4943 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4945 static union kvm_mmu_page_role
4946 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4948 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4949 union kvm_mmu_role role;
4952 role = kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, true);
4954 role = kvm_calc_shadow_mmu_root_page_role(vcpu, ®s, true);
4959 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu)
4962 * Invalidate all MMU roles to force them to reinitialize as CPUID
4963 * information is factored into reserved bit calculations.
4965 vcpu->arch.root_mmu.mmu_role.ext.valid = 0;
4966 vcpu->arch.guest_mmu.mmu_role.ext.valid = 0;
4967 vcpu->arch.nested_mmu.mmu_role.ext.valid = 0;
4968 kvm_mmu_reset_context(vcpu);
4971 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
4972 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
4973 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
4974 * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise
4975 * sweep the problem under the rug.
4977 * KVM's horrific CPUID ABI makes the problem all but impossible to
4978 * solve, as correctly handling multiple vCPU models (with respect to
4979 * paging and physical address properties) in a single VM would require
4980 * tracking all relevant CPUID information in kvm_mmu_page_role. That
4981 * is very undesirable as it would double the memory requirements for
4982 * gfn_track (see struct kvm_mmu_page_role comments), and in practice
4983 * no sane VMM mucks with the core vCPU model on the fly.
4985 if (vcpu->arch.last_vmentry_cpu != -1) {
4986 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n");
4987 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n");
4991 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4993 kvm_mmu_unload(vcpu);
4996 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4998 int kvm_mmu_load(struct kvm_vcpu *vcpu)
5002 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
5005 r = mmu_alloc_special_roots(vcpu);
5008 if (vcpu->arch.mmu->direct_map)
5009 r = mmu_alloc_direct_roots(vcpu);
5011 r = mmu_alloc_shadow_roots(vcpu);
5015 kvm_mmu_sync_roots(vcpu);
5017 kvm_mmu_load_pgd(vcpu);
5018 static_call(kvm_x86_tlb_flush_current)(vcpu);
5023 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
5025 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
5026 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
5027 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
5028 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
5031 static bool need_remote_flush(u64 old, u64 new)
5033 if (!is_shadow_present_pte(old))
5035 if (!is_shadow_present_pte(new))
5037 if ((old ^ new) & PT64_BASE_ADDR_MASK)
5039 old ^= shadow_nx_mask;
5040 new ^= shadow_nx_mask;
5041 return (old & ~new & PT64_PERM_MASK) != 0;
5044 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
5051 * Assume that the pte write on a page table of the same type
5052 * as the current vcpu paging mode since we update the sptes only
5053 * when they have the same mode.
5055 if (is_pae(vcpu) && *bytes == 4) {
5056 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5061 if (*bytes == 4 || *bytes == 8) {
5062 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5071 * If we're seeing too many writes to a page, it may no longer be a page table,
5072 * or we may be forking, in which case it is better to unmap the page.
5074 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5077 * Skip write-flooding detected for the sp whose level is 1, because
5078 * it can become unsync, then the guest page is not write-protected.
5080 if (sp->role.level == PG_LEVEL_4K)
5083 atomic_inc(&sp->write_flooding_count);
5084 return atomic_read(&sp->write_flooding_count) >= 3;
5088 * Misaligned accesses are too much trouble to fix up; also, they usually
5089 * indicate a page is not used as a page table.
5091 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5094 unsigned offset, pte_size, misaligned;
5096 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5097 gpa, bytes, sp->role.word);
5099 offset = offset_in_page(gpa);
5100 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5103 * Sometimes, the OS only writes the last one bytes to update status
5104 * bits, for example, in linux, andb instruction is used in clear_bit().
5106 if (!(offset & (pte_size - 1)) && bytes == 1)
5109 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5110 misaligned |= bytes < 4;
5115 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5117 unsigned page_offset, quadrant;
5121 page_offset = offset_in_page(gpa);
5122 level = sp->role.level;
5124 if (!sp->role.gpte_is_8_bytes) {
5125 page_offset <<= 1; /* 32->64 */
5127 * A 32-bit pde maps 4MB while the shadow pdes map
5128 * only 2MB. So we need to double the offset again
5129 * and zap two pdes instead of one.
5131 if (level == PT32_ROOT_LEVEL) {
5132 page_offset &= ~7; /* kill rounding error */
5136 quadrant = page_offset >> PAGE_SHIFT;
5137 page_offset &= ~PAGE_MASK;
5138 if (quadrant != sp->role.quadrant)
5142 spte = &sp->spt[page_offset / sizeof(*spte)];
5146 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5147 const u8 *new, int bytes,
5148 struct kvm_page_track_notifier_node *node)
5150 gfn_t gfn = gpa >> PAGE_SHIFT;
5151 struct kvm_mmu_page *sp;
5152 LIST_HEAD(invalid_list);
5153 u64 entry, gentry, *spte;
5155 bool remote_flush, local_flush;
5158 * If we don't have indirect shadow pages, it means no page is
5159 * write-protected, so we can exit simply.
5161 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5164 remote_flush = local_flush = false;
5166 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5169 * No need to care whether allocation memory is successful
5170 * or not since pte prefetch is skipped if it does not have
5171 * enough objects in the cache.
5173 mmu_topup_memory_caches(vcpu, true);
5175 write_lock(&vcpu->kvm->mmu_lock);
5177 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5179 ++vcpu->kvm->stat.mmu_pte_write;
5180 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5182 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5183 if (detect_write_misaligned(sp, gpa, bytes) ||
5184 detect_write_flooding(sp)) {
5185 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5186 ++vcpu->kvm->stat.mmu_flooded;
5190 spte = get_written_sptes(sp, gpa, &npte);
5197 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
5198 if (gentry && sp->role.level != PG_LEVEL_4K)
5199 ++vcpu->kvm->stat.mmu_pde_zapped;
5200 if (need_remote_flush(entry, *spte))
5201 remote_flush = true;
5205 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5206 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5207 write_unlock(&vcpu->kvm->mmu_lock);
5210 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5211 void *insn, int insn_len)
5213 int r, emulation_type = EMULTYPE_PF;
5214 bool direct = vcpu->arch.mmu->direct_map;
5216 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5217 return RET_PF_RETRY;
5220 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5221 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5222 if (r == RET_PF_EMULATE)
5226 if (r == RET_PF_INVALID) {
5227 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5228 lower_32_bits(error_code), false);
5229 if (WARN_ON_ONCE(r == RET_PF_INVALID))
5235 if (r != RET_PF_EMULATE)
5239 * Before emulating the instruction, check if the error code
5240 * was due to a RO violation while translating the guest page.
5241 * This can occur when using nested virtualization with nested
5242 * paging in both guests. If true, we simply unprotect the page
5243 * and resume the guest.
5245 if (vcpu->arch.mmu->direct_map &&
5246 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5247 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5252 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5253 * optimistically try to just unprotect the page and let the processor
5254 * re-execute the instruction that caused the page fault. Do not allow
5255 * retrying MMIO emulation, as it's not only pointless but could also
5256 * cause us to enter an infinite loop because the processor will keep
5257 * faulting on the non-existent MMIO address. Retrying an instruction
5258 * from a nested guest is also pointless and dangerous as we are only
5259 * explicitly shadowing L1's page tables, i.e. unprotecting something
5260 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5262 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5263 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5265 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5268 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5270 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5271 gva_t gva, hpa_t root_hpa)
5275 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5276 if (mmu != &vcpu->arch.guest_mmu) {
5277 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5278 if (is_noncanonical_address(gva, vcpu))
5281 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5287 if (root_hpa == INVALID_PAGE) {
5288 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5291 * INVLPG is required to invalidate any global mappings for the VA,
5292 * irrespective of PCID. Since it would take us roughly similar amount
5293 * of work to determine whether any of the prev_root mappings of the VA
5294 * is marked global, or to just sync it blindly, so we might as well
5295 * just always sync it.
5297 * Mappings not reachable via the current cr3 or the prev_roots will be
5298 * synced when switching to that cr3, so nothing needs to be done here
5301 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5302 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5303 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5305 mmu->invlpg(vcpu, gva, root_hpa);
5309 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5311 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
5312 ++vcpu->stat.invlpg;
5314 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5317 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5319 struct kvm_mmu *mmu = vcpu->arch.mmu;
5320 bool tlb_flush = false;
5323 if (pcid == kvm_get_active_pcid(vcpu)) {
5324 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5328 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5329 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5330 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5331 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5337 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5339 ++vcpu->stat.invlpg;
5342 * Mappings not reachable via the current cr3 or the prev_roots will be
5343 * synced when switching to that cr3, so nothing needs to be done here
5348 void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
5349 int tdp_huge_page_level)
5351 tdp_enabled = enable_tdp;
5352 max_tdp_level = tdp_max_root_level;
5355 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5356 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5357 * the kernel is not. But, KVM never creates a page size greater than
5358 * what is used by the kernel for any given HVA, i.e. the kernel's
5359 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5362 max_huge_page_level = tdp_huge_page_level;
5363 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5364 max_huge_page_level = PG_LEVEL_1G;
5366 max_huge_page_level = PG_LEVEL_2M;
5368 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5370 /* The return value indicates if tlb flush on all vcpus is needed. */
5371 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head,
5372 struct kvm_memory_slot *slot);
5374 /* The caller should hold mmu-lock before calling this function. */
5375 static __always_inline bool
5376 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5377 slot_level_handler fn, int start_level, int end_level,
5378 gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield,
5381 struct slot_rmap_walk_iterator iterator;
5383 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5384 end_gfn, &iterator) {
5386 flush |= fn(kvm, iterator.rmap, memslot);
5388 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
5389 if (flush && flush_on_yield) {
5390 kvm_flush_remote_tlbs_with_address(kvm,
5392 iterator.gfn - start_gfn + 1);
5395 cond_resched_rwlock_write(&kvm->mmu_lock);
5402 static __always_inline bool
5403 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5404 slot_level_handler fn, int start_level, int end_level,
5405 bool flush_on_yield)
5407 return slot_handle_level_range(kvm, memslot, fn, start_level,
5408 end_level, memslot->base_gfn,
5409 memslot->base_gfn + memslot->npages - 1,
5410 flush_on_yield, false);
5413 static __always_inline bool
5414 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5415 slot_level_handler fn, bool flush_on_yield)
5417 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5418 PG_LEVEL_4K, flush_on_yield);
5421 static void free_mmu_pages(struct kvm_mmu *mmu)
5423 if (!tdp_enabled && mmu->pae_root)
5424 set_memory_encrypted((unsigned long)mmu->pae_root, 1);
5425 free_page((unsigned long)mmu->pae_root);
5426 free_page((unsigned long)mmu->pml4_root);
5429 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5434 mmu->root_hpa = INVALID_PAGE;
5436 mmu->translate_gpa = translate_gpa;
5437 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5438 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5441 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5442 * while the PDP table is a per-vCPU construct that's allocated at MMU
5443 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5444 * x86_64. Therefore we need to allocate the PDP table in the first
5445 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5446 * generally doesn't use PAE paging and can skip allocating the PDP
5447 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5448 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5449 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
5451 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5454 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5458 mmu->pae_root = page_address(page);
5461 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5462 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5463 * that KVM's writes and the CPU's reads get along. Note, this is
5464 * only necessary when using shadow paging, as 64-bit NPT can get at
5465 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5466 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5469 set_memory_decrypted((unsigned long)mmu->pae_root, 1);
5471 WARN_ON_ONCE(shadow_me_mask);
5473 for (i = 0; i < 4; ++i)
5474 mmu->pae_root[i] = INVALID_PAE_ROOT;
5479 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5483 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5484 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5486 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5487 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5489 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5491 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5492 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5494 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5496 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5500 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5502 goto fail_allocate_root;
5506 free_mmu_pages(&vcpu->arch.guest_mmu);
5510 #define BATCH_ZAP_PAGES 10
5511 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5513 struct kvm_mmu_page *sp, *node;
5514 int nr_zapped, batch = 0;
5517 list_for_each_entry_safe_reverse(sp, node,
5518 &kvm->arch.active_mmu_pages, link) {
5520 * No obsolete valid page exists before a newly created page
5521 * since active_mmu_pages is a FIFO list.
5523 if (!is_obsolete_sp(kvm, sp))
5527 * Invalid pages should never land back on the list of active
5528 * pages. Skip the bogus page, otherwise we'll get stuck in an
5529 * infinite loop if the page gets put back on the list (again).
5531 if (WARN_ON(sp->role.invalid))
5535 * No need to flush the TLB since we're only zapping shadow
5536 * pages with an obsolete generation number and all vCPUS have
5537 * loaded a new root, i.e. the shadow pages being zapped cannot
5538 * be in active use by the guest.
5540 if (batch >= BATCH_ZAP_PAGES &&
5541 cond_resched_rwlock_write(&kvm->mmu_lock)) {
5546 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5547 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5554 * Trigger a remote TLB flush before freeing the page tables to ensure
5555 * KVM is not in the middle of a lockless shadow page table walk, which
5556 * may reference the pages.
5558 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5562 * Fast invalidate all shadow pages and use lock-break technique
5563 * to zap obsolete pages.
5565 * It's required when memslot is being deleted or VM is being
5566 * destroyed, in these cases, we should ensure that KVM MMU does
5567 * not use any resource of the being-deleted slot or all slots
5568 * after calling the function.
5570 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5572 lockdep_assert_held(&kvm->slots_lock);
5574 write_lock(&kvm->mmu_lock);
5575 trace_kvm_mmu_zap_all_fast(kvm);
5578 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5579 * held for the entire duration of zapping obsolete pages, it's
5580 * impossible for there to be multiple invalid generations associated
5581 * with *valid* shadow pages at any given time, i.e. there is exactly
5582 * one valid generation and (at most) one invalid generation.
5584 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5586 /* In order to ensure all threads see this change when
5587 * handling the MMU reload signal, this must happen in the
5588 * same critical section as kvm_reload_remote_mmus, and
5589 * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages
5590 * could drop the MMU lock and yield.
5592 if (is_tdp_mmu_enabled(kvm))
5593 kvm_tdp_mmu_invalidate_all_roots(kvm);
5596 * Notify all vcpus to reload its shadow page table and flush TLB.
5597 * Then all vcpus will switch to new shadow page table with the new
5600 * Note: we need to do this under the protection of mmu_lock,
5601 * otherwise, vcpu would purge shadow page but miss tlb flush.
5603 kvm_reload_remote_mmus(kvm);
5605 kvm_zap_obsolete_pages(kvm);
5607 write_unlock(&kvm->mmu_lock);
5609 if (is_tdp_mmu_enabled(kvm)) {
5610 read_lock(&kvm->mmu_lock);
5611 kvm_tdp_mmu_zap_invalidated_roots(kvm);
5612 read_unlock(&kvm->mmu_lock);
5616 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5618 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5621 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5622 struct kvm_memory_slot *slot,
5623 struct kvm_page_track_notifier_node *node)
5625 kvm_mmu_zap_all_fast(kvm);
5628 void kvm_mmu_init_vm(struct kvm *kvm)
5630 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5632 if (!kvm_mmu_init_tdp_mmu(kvm))
5634 * No smp_load/store wrappers needed here as we are in
5635 * VM init and there cannot be any memslots / other threads
5636 * accessing this struct kvm yet.
5638 kvm->arch.memslots_have_rmaps = true;
5640 node->track_write = kvm_mmu_pte_write;
5641 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5642 kvm_page_track_register_notifier(kvm, node);
5645 void kvm_mmu_uninit_vm(struct kvm *kvm)
5647 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5649 kvm_page_track_unregister_notifier(kvm, node);
5651 kvm_mmu_uninit_tdp_mmu(kvm);
5654 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5656 struct kvm_memslots *slots;
5657 struct kvm_memory_slot *memslot;
5661 if (kvm_memslots_have_rmaps(kvm)) {
5662 write_lock(&kvm->mmu_lock);
5663 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5664 slots = __kvm_memslots(kvm, i);
5665 kvm_for_each_memslot(memslot, slots) {
5668 start = max(gfn_start, memslot->base_gfn);
5669 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5673 flush = slot_handle_level_range(kvm, memslot,
5674 kvm_zap_rmapp, PG_LEVEL_4K,
5675 KVM_MAX_HUGEPAGE_LEVEL, start,
5676 end - 1, true, flush);
5680 kvm_flush_remote_tlbs_with_address(kvm, gfn_start, gfn_end);
5681 write_unlock(&kvm->mmu_lock);
5684 if (is_tdp_mmu_enabled(kvm)) {
5687 read_lock(&kvm->mmu_lock);
5688 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++)
5689 flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start,
5690 gfn_end, flush, true);
5692 kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
5695 read_unlock(&kvm->mmu_lock);
5699 static bool slot_rmap_write_protect(struct kvm *kvm,
5700 struct kvm_rmap_head *rmap_head,
5701 struct kvm_memory_slot *slot)
5703 return __rmap_write_protect(kvm, rmap_head, false);
5706 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5707 struct kvm_memory_slot *memslot,
5712 if (kvm_memslots_have_rmaps(kvm)) {
5713 write_lock(&kvm->mmu_lock);
5714 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5715 start_level, KVM_MAX_HUGEPAGE_LEVEL,
5717 write_unlock(&kvm->mmu_lock);
5720 if (is_tdp_mmu_enabled(kvm)) {
5721 read_lock(&kvm->mmu_lock);
5722 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level);
5723 read_unlock(&kvm->mmu_lock);
5727 * We can flush all the TLBs out of the mmu lock without TLB
5728 * corruption since we just change the spte from writable to
5729 * readonly so that we only need to care the case of changing
5730 * spte from present to present (changing the spte from present
5731 * to nonpresent will flush all the TLBs immediately), in other
5732 * words, the only case we care is mmu_spte_update() where we
5733 * have checked Host-writable | MMU-writable instead of
5734 * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK
5738 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5741 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5742 struct kvm_rmap_head *rmap_head,
5743 struct kvm_memory_slot *slot)
5746 struct rmap_iterator iter;
5747 int need_tlb_flush = 0;
5749 struct kvm_mmu_page *sp;
5752 for_each_rmap_spte(rmap_head, &iter, sptep) {
5753 sp = sptep_to_sp(sptep);
5754 pfn = spte_to_pfn(*sptep);
5757 * We cannot do huge page mapping for indirect shadow pages,
5758 * which are found on the last rmap (level = 1) when not using
5759 * tdp; such shadow pages are synced with the page table in
5760 * the guest, and the guest page table is using 4K page size
5761 * mapping if the indirect sp has level = 1.
5763 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5764 sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn,
5765 pfn, PG_LEVEL_NUM)) {
5766 pte_list_remove(rmap_head, sptep);
5768 if (kvm_available_flush_tlb_with_range())
5769 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5770 KVM_PAGES_PER_HPAGE(sp->role.level));
5778 return need_tlb_flush;
5781 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5782 const struct kvm_memory_slot *memslot)
5784 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5785 struct kvm_memory_slot *slot = (struct kvm_memory_slot *)memslot;
5788 if (kvm_memslots_have_rmaps(kvm)) {
5789 write_lock(&kvm->mmu_lock);
5790 flush = slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true);
5792 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5793 write_unlock(&kvm->mmu_lock);
5796 if (is_tdp_mmu_enabled(kvm)) {
5797 read_lock(&kvm->mmu_lock);
5798 flush = kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot, flush);
5800 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5801 read_unlock(&kvm->mmu_lock);
5805 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5806 const struct kvm_memory_slot *memslot)
5809 * All current use cases for flushing the TLBs for a specific memslot
5810 * related to dirty logging, and many do the TLB flush out of mmu_lock.
5811 * The interaction between the various operations on memslot must be
5812 * serialized by slots_locks to ensure the TLB flush from one operation
5813 * is observed by any other operation on the same memslot.
5815 lockdep_assert_held(&kvm->slots_lock);
5816 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5820 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5821 struct kvm_memory_slot *memslot)
5825 if (kvm_memslots_have_rmaps(kvm)) {
5826 write_lock(&kvm->mmu_lock);
5827 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty,
5829 write_unlock(&kvm->mmu_lock);
5832 if (is_tdp_mmu_enabled(kvm)) {
5833 read_lock(&kvm->mmu_lock);
5834 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5835 read_unlock(&kvm->mmu_lock);
5839 * It's also safe to flush TLBs out of mmu lock here as currently this
5840 * function is only used for dirty logging, in which case flushing TLB
5841 * out of mmu lock also guarantees no dirty pages will be lost in
5845 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5848 void kvm_mmu_zap_all(struct kvm *kvm)
5850 struct kvm_mmu_page *sp, *node;
5851 LIST_HEAD(invalid_list);
5854 write_lock(&kvm->mmu_lock);
5856 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5857 if (WARN_ON(sp->role.invalid))
5859 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5861 if (cond_resched_rwlock_write(&kvm->mmu_lock))
5865 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5867 if (is_tdp_mmu_enabled(kvm))
5868 kvm_tdp_mmu_zap_all(kvm);
5870 write_unlock(&kvm->mmu_lock);
5873 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5875 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5877 gen &= MMIO_SPTE_GEN_MASK;
5880 * Generation numbers are incremented in multiples of the number of
5881 * address spaces in order to provide unique generations across all
5882 * address spaces. Strip what is effectively the address space
5883 * modifier prior to checking for a wrap of the MMIO generation so
5884 * that a wrap in any address space is detected.
5886 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5889 * The very rare case: if the MMIO generation number has wrapped,
5890 * zap all shadow pages.
5892 if (unlikely(gen == 0)) {
5893 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5894 kvm_mmu_zap_all_fast(kvm);
5898 static unsigned long
5899 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5902 int nr_to_scan = sc->nr_to_scan;
5903 unsigned long freed = 0;
5905 mutex_lock(&kvm_lock);
5907 list_for_each_entry(kvm, &vm_list, vm_list) {
5909 LIST_HEAD(invalid_list);
5912 * Never scan more than sc->nr_to_scan VM instances.
5913 * Will not hit this condition practically since we do not try
5914 * to shrink more than one VM and it is very unlikely to see
5915 * !n_used_mmu_pages so many times.
5920 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5921 * here. We may skip a VM instance errorneosly, but we do not
5922 * want to shrink a VM that only started to populate its MMU
5925 if (!kvm->arch.n_used_mmu_pages &&
5926 !kvm_has_zapped_obsolete_pages(kvm))
5929 idx = srcu_read_lock(&kvm->srcu);
5930 write_lock(&kvm->mmu_lock);
5932 if (kvm_has_zapped_obsolete_pages(kvm)) {
5933 kvm_mmu_commit_zap_page(kvm,
5934 &kvm->arch.zapped_obsolete_pages);
5938 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
5941 write_unlock(&kvm->mmu_lock);
5942 srcu_read_unlock(&kvm->srcu, idx);
5945 * unfair on small ones
5946 * per-vm shrinkers cry out
5947 * sadness comes quickly
5949 list_move_tail(&kvm->vm_list, &vm_list);
5953 mutex_unlock(&kvm_lock);
5957 static unsigned long
5958 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5960 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5963 static struct shrinker mmu_shrinker = {
5964 .count_objects = mmu_shrink_count,
5965 .scan_objects = mmu_shrink_scan,
5966 .seeks = DEFAULT_SEEKS * 10,
5969 static void mmu_destroy_caches(void)
5971 kmem_cache_destroy(pte_list_desc_cache);
5972 kmem_cache_destroy(mmu_page_header_cache);
5975 static bool get_nx_auto_mode(void)
5977 /* Return true when CPU has the bug, and mitigations are ON */
5978 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5981 static void __set_nx_huge_pages(bool val)
5983 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5986 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5988 bool old_val = nx_huge_pages;
5991 /* In "auto" mode deploy workaround only if CPU has the bug. */
5992 if (sysfs_streq(val, "off"))
5994 else if (sysfs_streq(val, "force"))
5996 else if (sysfs_streq(val, "auto"))
5997 new_val = get_nx_auto_mode();
5998 else if (strtobool(val, &new_val) < 0)
6001 __set_nx_huge_pages(new_val);
6003 if (new_val != old_val) {
6006 mutex_lock(&kvm_lock);
6008 list_for_each_entry(kvm, &vm_list, vm_list) {
6009 mutex_lock(&kvm->slots_lock);
6010 kvm_mmu_zap_all_fast(kvm);
6011 mutex_unlock(&kvm->slots_lock);
6013 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6015 mutex_unlock(&kvm_lock);
6021 int kvm_mmu_module_init(void)
6025 if (nx_huge_pages == -1)
6026 __set_nx_huge_pages(get_nx_auto_mode());
6029 * MMU roles use union aliasing which is, generally speaking, an
6030 * undefined behavior. However, we supposedly know how compilers behave
6031 * and the current status quo is unlikely to change. Guardians below are
6032 * supposed to let us know if the assumption becomes false.
6034 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
6035 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
6036 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
6038 kvm_mmu_reset_all_pte_masks();
6040 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
6041 sizeof(struct pte_list_desc),
6042 0, SLAB_ACCOUNT, NULL);
6043 if (!pte_list_desc_cache)
6046 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
6047 sizeof(struct kvm_mmu_page),
6048 0, SLAB_ACCOUNT, NULL);
6049 if (!mmu_page_header_cache)
6052 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
6055 ret = register_shrinker(&mmu_shrinker);
6062 mmu_destroy_caches();
6067 * Calculate mmu pages needed for kvm.
6069 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
6071 unsigned long nr_mmu_pages;
6072 unsigned long nr_pages = 0;
6073 struct kvm_memslots *slots;
6074 struct kvm_memory_slot *memslot;
6077 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6078 slots = __kvm_memslots(kvm, i);
6080 kvm_for_each_memslot(memslot, slots)
6081 nr_pages += memslot->npages;
6084 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
6085 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
6087 return nr_mmu_pages;
6090 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6092 kvm_mmu_unload(vcpu);
6093 free_mmu_pages(&vcpu->arch.root_mmu);
6094 free_mmu_pages(&vcpu->arch.guest_mmu);
6095 mmu_free_memory_caches(vcpu);
6098 void kvm_mmu_module_exit(void)
6100 mmu_destroy_caches();
6101 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6102 unregister_shrinker(&mmu_shrinker);
6103 mmu_audit_disable();
6106 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
6108 unsigned int old_val;
6111 old_val = nx_huge_pages_recovery_ratio;
6112 err = param_set_uint(val, kp);
6116 if (READ_ONCE(nx_huge_pages) &&
6117 !old_val && nx_huge_pages_recovery_ratio) {
6120 mutex_lock(&kvm_lock);
6122 list_for_each_entry(kvm, &vm_list, vm_list)
6123 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6125 mutex_unlock(&kvm_lock);
6131 static void kvm_recover_nx_lpages(struct kvm *kvm)
6133 unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits;
6135 struct kvm_mmu_page *sp;
6137 LIST_HEAD(invalid_list);
6141 rcu_idx = srcu_read_lock(&kvm->srcu);
6142 write_lock(&kvm->mmu_lock);
6144 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6145 to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0;
6146 for ( ; to_zap; --to_zap) {
6147 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
6151 * We use a separate list instead of just using active_mmu_pages
6152 * because the number of lpage_disallowed pages is expected to
6153 * be relatively small compared to the total.
6155 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6156 struct kvm_mmu_page,
6157 lpage_disallowed_link);
6158 WARN_ON_ONCE(!sp->lpage_disallowed);
6159 if (is_tdp_mmu_page(sp)) {
6160 flush |= kvm_tdp_mmu_zap_sp(kvm, sp);
6162 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6163 WARN_ON_ONCE(sp->lpage_disallowed);
6166 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
6167 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6168 cond_resched_rwlock_write(&kvm->mmu_lock);
6172 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6174 write_unlock(&kvm->mmu_lock);
6175 srcu_read_unlock(&kvm->srcu, rcu_idx);
6178 static long get_nx_lpage_recovery_timeout(u64 start_time)
6180 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6181 ? start_time + 60 * HZ - get_jiffies_64()
6182 : MAX_SCHEDULE_TIMEOUT;
6185 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6188 long remaining_time;
6191 start_time = get_jiffies_64();
6192 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6194 set_current_state(TASK_INTERRUPTIBLE);
6195 while (!kthread_should_stop() && remaining_time > 0) {
6196 schedule_timeout(remaining_time);
6197 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6198 set_current_state(TASK_INTERRUPTIBLE);
6201 set_current_state(TASK_RUNNING);
6203 if (kthread_should_stop())
6206 kvm_recover_nx_lpages(kvm);
6210 int kvm_mmu_post_init_vm(struct kvm *kvm)
6214 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6215 "kvm-nx-lpage-recovery",
6216 &kvm->arch.nx_lpage_recovery_thread);
6218 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6223 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6225 if (kvm->arch.nx_lpage_recovery_thread)
6226 kthread_stop(kvm->arch.nx_lpage_recovery_thread);